drivers/usb/host/ehci-fsl.c

   1 /*
   2  * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
   5  *
   6  * Author: Tor Krill tor@excito.com
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <pci.h>
  13 #include <usb.h>
  14 #include <asm/io.h>
  15 #include <usb/ehci-fsl.h>
  16 #include <hwconfig.h>
  17 #include <asm/fsl_errata.h>
  18
  19 #include "ehci.h"
  20
  21 /* Check USB PHY clock valid */
  22 static int usb_phy_clk_valid(struct usb_ehci *ehci)
  23 {
  24         if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
  25                         in_be32(&ehci->prictrl))) {
  26                 printf("USB PHY clock invalid!\n");
  27                 return 0;
  28         } else {
  29                 return 1;
  30         }
  31 }
  32
  33 /*
  34  * Create the appropriate control structures to manage
  35  * a new EHCI host controller.
  36  *
  37  * Excerpts from linux ehci fsl driver.
  38  */
  39 int ehci_hcd_init(int index, enum usb_init_type init,
  40                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  41 {
  42         struct usb_ehci *ehci = NULL;
  43         const char *phy_type = NULL;
  44         size_t len;
  45         char current_usb_controller[5];
  46 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  47         char usb_phy[5];
  48
  49         usb_phy[0] = '\0';
  50 #endif
  51         if (has_erratum_a007075()) {
  52                 /*
  53                  * A 5ms delay is needed after applying soft-reset to the
  54                  * controller to let external ULPI phy come out of reset.
  55                  * This delay needs to be added before re-initializing
  56                  * the controller after soft-resetting completes
  57                  */
  58                 mdelay(5);
  59         }
  60         memset(current_usb_controller, '\0', 5);
  61         snprintf(current_usb_controller, 4, "usb%d", index+1);
  62
  63         switch (index) {
  64         case 0:
  65                 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  66                 break;
  67         case 1:
  68                 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
  69                 break;
  70         default:
  71                 printf("ERROR: wrong controller index!!\n");
  72                 break;
  73         };
  74
  75         *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  76         *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  77                         HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  78
  79         /* Set to Host mode */
  80         setbits_le32(&ehci->usbmode, CM_HOST);
  81
  82         out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
  83         out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
  84
  85         /* Init phy */
  86         if (hwconfig_sub(current_usb_controller, "phy_type"))
  87                 phy_type = hwconfig_subarg(current_usb_controller,
  88                                 "phy_type", &len);
  89         else
  90                 phy_type = getenv("usb_phy_type");
  91
  92         if (!phy_type) {
  93 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  94                 /* if none specified assume internal UTMI */
  95                 strcpy(usb_phy, "utmi");
  96                 phy_type = usb_phy;
  97 #else
  98                 printf("WARNING: USB phy type not defined !!\n");
  99                 return -1;
 100 #endif
 101         }
 102
 103         if (!strncmp(phy_type, "utmi", 4)) {
 104 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
 105                 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
 106                 setbits_be32(&ehci->control, UTMI_PHY_EN);
 107                 udelay(1000); /* delay required for PHY Clk to appear */
 108 #endif
 109                 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
 110                 setbits_be32(&ehci->control, USB_EN);
 111         } else {
 112                 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
 113                 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
 114                 udelay(1000); /* delay required for PHY Clk to appear */
 115                 if (!usb_phy_clk_valid(ehci))
 116                         return -EINVAL;
 117                 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
 118         }
 119
 120         out_be32(&ehci->prictrl, 0x0000000c);
 121         out_be32(&ehci->age_cnt_limit, 0x00000040);
 122         out_be32(&ehci->sictrl, 0x00000001);
 123
 124         in_le32(&ehci->usbmode);
 125
 126         return 0;
 127 }
 128
 129 /*
 130  * Destroy the appropriate control structures corresponding
 131  * the the EHCI host controller.
 132  */
 133 int ehci_hcd_stop(int index)
 134 {
 135         return 0;
 136 }