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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/usb/host/ehci-fsl.c
2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <usb/ehci-fsl.h>
17 #include <asm/fsl_errata.h>
21 static void set_txfifothresh(struct usb_ehci
*, u32
);
23 /* Check USB PHY clock valid */
24 static int usb_phy_clk_valid(struct usb_ehci
*ehci
)
26 if (!((in_be32(&ehci
->control
) & PHY_CLK_VALID
) ||
27 in_be32(&ehci
->prictrl
))) {
28 printf("USB PHY clock invalid!\n");
36 * Create the appropriate control structures to manage
37 * a new EHCI host controller.
39 * Excerpts from linux ehci fsl driver.
41 int ehci_hcd_init(int index
, enum usb_init_type init
,
42 struct ehci_hccr
**hccr
, struct ehci_hcor
**hcor
)
44 struct usb_ehci
*ehci
= NULL
;
45 const char *phy_type
= NULL
;
47 char current_usb_controller
[5];
48 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
53 if (has_erratum_a007075()) {
55 * A 5ms delay is needed after applying soft-reset to the
56 * controller to let external ULPI phy come out of reset.
57 * This delay needs to be added before re-initializing
58 * the controller after soft-resetting completes
62 memset(current_usb_controller
, '\0', 5);
63 snprintf(current_usb_controller
, 4, "usb%d", index
+1);
67 ehci
= (struct usb_ehci
*)CONFIG_SYS_FSL_USB1_ADDR
;
70 ehci
= (struct usb_ehci
*)CONFIG_SYS_FSL_USB2_ADDR
;
73 printf("ERROR: wrong controller index!!\n");
77 *hccr
= (struct ehci_hccr
*)((uint32_t)&ehci
->caplength
);
78 *hcor
= (struct ehci_hcor
*)((uint32_t) *hccr
+
79 HC_LENGTH(ehci_readl(&(*hccr
)->cr_capbase
)));
81 /* Set to Host mode */
82 setbits_le32(&ehci
->usbmode
, CM_HOST
);
84 out_be32(&ehci
->snoop1
, SNOOP_SIZE_2GB
);
85 out_be32(&ehci
->snoop2
, 0x80000000 | SNOOP_SIZE_2GB
);
88 if (hwconfig_sub(current_usb_controller
, "phy_type"))
89 phy_type
= hwconfig_subarg(current_usb_controller
,
92 phy_type
= getenv("usb_phy_type");
95 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
96 /* if none specified assume internal UTMI */
97 strcpy(usb_phy
, "utmi");
100 printf("WARNING: USB phy type not defined !!\n");
105 if (!strncmp(phy_type
, "utmi", 4)) {
106 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
107 setbits_be32(&ehci
->control
, PHY_CLK_SEL_UTMI
);
108 setbits_be32(&ehci
->control
, UTMI_PHY_EN
);
109 udelay(1000); /* delay required for PHY Clk to appear */
111 out_le32(&(*hcor
)->or_portsc
[0], PORT_PTS_UTMI
);
112 setbits_be32(&ehci
->control
, USB_EN
);
114 setbits_be32(&ehci
->control
, PHY_CLK_SEL_ULPI
);
115 clrsetbits_be32(&ehci
->control
, UTMI_PHY_EN
, USB_EN
);
116 udelay(1000); /* delay required for PHY Clk to appear */
117 if (!usb_phy_clk_valid(ehci
))
119 out_le32(&(*hcor
)->or_portsc
[0], PORT_PTS_ULPI
);
122 out_be32(&ehci
->prictrl
, 0x0000000c);
123 out_be32(&ehci
->age_cnt_limit
, 0x00000040);
124 out_be32(&ehci
->sictrl
, 0x00000001);
126 in_le32(&ehci
->usbmode
);
128 if (SVR_SOC_VER(get_svr()) == SVR_T4240
&&
129 IS_SVR_REV(get_svr(), 2, 0))
130 set_txfifothresh(ehci
, TXFIFOTHRESH
);
136 * Destroy the appropriate control structures corresponding
137 * the the EHCI host controller.
139 int ehci_hcd_stop(int index
)
145 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
146 * to counter DDR latencies in writing data into Tx buffer.
147 * This prevents Tx buffer from getting underrun
149 static void set_txfifothresh(struct usb_ehci
*ehci
, u32 txfifo_thresh
)
152 cmd
= ehci_readl(&ehci
->txfilltuning
);
153 cmd
&= ~TXFIFO_THRESH_MASK
;
154 cmd
|= TXFIFO_THRESH(txfifo_thresh
);
155 ehci_writel(&ehci
->txfilltuning
, cmd
);