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1 /*
2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
5 *
6 * Author: Tor Krill tor@excito.com
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <pci.h>
13 #include <usb.h>
14 #include <asm/io.h>
15 #include <usb/ehci-fsl.h>
16 #include <hwconfig.h>
17
18 #include "ehci.h"
19
20 /* Check USB PHY clock valid */
21 static int usb_phy_clk_valid(struct usb_ehci *ehci)
22 {
23 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
24 in_be32(&ehci->prictrl))) {
25 printf("USB PHY clock invalid!\n");
26 return 0;
27 } else {
28 return 1;
29 }
30 }
31
32 /*
33 * Create the appropriate control structures to manage
34 * a new EHCI host controller.
35 *
36 * Excerpts from linux ehci fsl driver.
37 */
38 int ehci_hcd_init(int index, enum usb_init_type init,
39 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
40 {
41 struct usb_ehci *ehci = NULL;
42 const char *phy_type = NULL;
43 size_t len;
44 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
45 char usb_phy[5];
46
47 usb_phy[0] = '\0';
48 #endif
49
50 switch (index) {
51 case 0:
52 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
53 break;
54 case 1:
55 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
56 break;
57 default:
58 printf("ERROR: wrong controller index!!\n");
59 break;
60 };
61
62 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
63 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
64 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
65
66 /* Set to Host mode */
67 setbits_le32(&ehci->usbmode, CM_HOST);
68
69 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
70 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
71
72 /* Init phy */
73 if (hwconfig_sub("usb1", "phy_type"))
74 phy_type = hwconfig_subarg("usb1", "phy_type", &len);
75 else
76 phy_type = getenv("usb_phy_type");
77
78 if (!phy_type) {
79 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
80 /* if none specified assume internal UTMI */
81 strcpy(usb_phy, "utmi");
82 phy_type = usb_phy;
83 #else
84 printf("WARNING: USB phy type not defined !!\n");
85 return -1;
86 #endif
87 }
88
89 if (!strcmp(phy_type, "utmi")) {
90 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
91 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
92 setbits_be32(&ehci->control, UTMI_PHY_EN);
93 udelay(1000); /* delay required for PHY Clk to appear */
94 #endif
95 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
96 setbits_be32(&ehci->control, USB_EN);
97 } else {
98 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
99 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
100 udelay(1000); /* delay required for PHY Clk to appear */
101 if (!usb_phy_clk_valid(ehci))
102 return -EINVAL;
103 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
104 }
105
106 out_be32(&ehci->prictrl, 0x0000000c);
107 out_be32(&ehci->age_cnt_limit, 0x00000040);
108 out_be32(&ehci->sictrl, 0x00000001);
109
110 in_le32(&ehci->usbmode);
111
112 return 0;
113 }
114
115 /*
116 * Destroy the appropriate control structures corresponding
117 * the the EHCI host controller.
118 */
119 int ehci_hcd_stop(int index)
120 {
121 return 0;
122 }