1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* Diagnostics inline function utilities.
166 These are lightweight utilities which should only be called by parse_operands
167 and other parsers. GAS processes each assembly line by parsing it against
168 instruction template(s), in the case of multiple templates (for the same
169 mnemonic name), those templates are tried one by one until one succeeds or
170 all fail. An assembly line may fail a few templates before being
171 successfully parsed; an error saved here in most cases is not a user error
172 but an error indicating the current template is not the right template.
173 Therefore it is very important that errors can be saved at a low cost during
174 the parsing; we don't want to slow down the whole parsing by recording
175 non-user errors in detail.
177 Remember that the objective is to help GAS pick up the most appropriate
178 error message in the case of multiple templates, e.g. FMOV which has 8
184 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
185 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
195 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
197 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
198 inst
.parsing_error
.index
= -1;
199 inst
.parsing_error
.kind
= kind
;
200 inst
.parsing_error
.error
= error
;
204 set_recoverable_error (const char *error
)
206 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
209 /* Use the DESC field of the corresponding aarch64_operand entry to compose
210 the error message. */
212 set_default_error (void)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
218 set_syntax_error (const char *error
)
220 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
224 set_first_syntax_error (const char *error
)
227 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
231 set_fatal_syntax_error (const char *error
)
233 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
236 /* Return value for certain parsers when the parsing fails; those parsers
237 return the information of the parsed result, e.g. register number, on
239 #define PARSE_FAIL -1
241 /* This is an invalid condition code that means no conditional field is
243 #define COND_ALWAYS 0x10
247 const char *template;
254 bfd_reloc_code_real_type reloc
;
257 /* Macros to define the register types and masks for the purpose
260 #undef AARCH64_REG_TYPES
261 #define AARCH64_REG_TYPES \
262 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
263 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
264 BASIC_REG_TYPE(SP_32) /* wsp */ \
265 BASIC_REG_TYPE(SP_64) /* sp */ \
266 BASIC_REG_TYPE(Z_32) /* wzr */ \
267 BASIC_REG_TYPE(Z_64) /* xzr */ \
268 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
269 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
270 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
271 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
272 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
273 BASIC_REG_TYPE(VN) /* v[0-31] */ \
274 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
275 BASIC_REG_TYPE(PN) /* p[0-15] */ \
276 BASIC_REG_TYPE(ZA) /* za */ \
277 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
278 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
279 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
280 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
281 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
282 /* Typecheck: same, plus SVE registers. */ \
283 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
285 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
286 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
288 /* Typecheck: same, plus SVE registers. */ \
289 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
292 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
293 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
295 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Typecheck: any [BHSDQ]P FP. */ \
300 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
301 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
302 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
305 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
306 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
307 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
308 be used for SVE instructions, since Zn and Pn are valid symbols \
309 in other contexts. */ \
310 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
315 | REG_TYPE(ZN) | REG_TYPE(PN)) \
316 /* Any integer register; used for error messages only. */ \
317 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
320 /* The whole of ZA or a single tile. */ \
321 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
322 /* A horizontal or vertical slice of a ZA tile. */ \
323 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
324 /* Pseudo type to mark the end of the enumerator sequence. */ \
327 #undef BASIC_REG_TYPE
328 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
329 #undef MULTI_REG_TYPE
330 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
332 /* Register type enumerators. */
333 typedef enum aarch64_reg_type_
335 /* A list of REG_TYPE_*. */
339 #undef BASIC_REG_TYPE
340 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
342 #define REG_TYPE(T) (1 << REG_TYPE_##T)
343 #undef MULTI_REG_TYPE
344 #define MULTI_REG_TYPE(T,V) V,
346 /* Structure for a hash table entry for a register. */
350 unsigned char number
;
351 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
352 unsigned char builtin
;
355 /* Values indexed by aarch64_reg_type to assist the type checking. */
356 static const unsigned reg_type_masks
[] =
361 #undef BASIC_REG_TYPE
363 #undef MULTI_REG_TYPE
364 #undef AARCH64_REG_TYPES
366 /* Diagnostics used when we don't get a register of the expected type.
367 Note: this has to synchronized with aarch64_reg_type definitions
370 get_reg_expected_msg (aarch64_reg_type reg_type
)
377 msg
= N_("integer 32-bit register expected");
380 msg
= N_("integer 64-bit register expected");
383 msg
= N_("integer register expected");
385 case REG_TYPE_R64_SP
:
386 msg
= N_("64-bit integer or SP register expected");
388 case REG_TYPE_SVE_BASE
:
389 msg
= N_("base register expected");
392 msg
= N_("integer or zero register expected");
394 case REG_TYPE_SVE_OFFSET
:
395 msg
= N_("offset register expected");
398 msg
= N_("integer or SP register expected");
400 case REG_TYPE_R_Z_SP
:
401 msg
= N_("integer, zero or SP register expected");
404 msg
= N_("8-bit SIMD scalar register expected");
407 msg
= N_("16-bit SIMD scalar or floating-point half precision "
408 "register expected");
411 msg
= N_("32-bit SIMD scalar or floating-point single precision "
412 "register expected");
415 msg
= N_("64-bit SIMD scalar or floating-point double precision "
416 "register expected");
419 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
420 "register expected");
422 case REG_TYPE_R_Z_BHSDQ_V
:
423 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
424 msg
= N_("register expected");
426 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
427 msg
= N_("SIMD scalar or floating-point register expected");
429 case REG_TYPE_VN
: /* any V reg */
430 msg
= N_("vector register expected");
433 msg
= N_("SVE vector register expected");
436 msg
= N_("SVE predicate register expected");
439 as_fatal (_("invalid register type %d"), reg_type
);
444 /* Some well known registers that we refer to directly elsewhere. */
448 /* Instructions take 4 bytes in the object file. */
451 static htab_t aarch64_ops_hsh
;
452 static htab_t aarch64_cond_hsh
;
453 static htab_t aarch64_shift_hsh
;
454 static htab_t aarch64_sys_regs_hsh
;
455 static htab_t aarch64_pstatefield_hsh
;
456 static htab_t aarch64_sys_regs_ic_hsh
;
457 static htab_t aarch64_sys_regs_dc_hsh
;
458 static htab_t aarch64_sys_regs_at_hsh
;
459 static htab_t aarch64_sys_regs_tlbi_hsh
;
460 static htab_t aarch64_sys_regs_sr_hsh
;
461 static htab_t aarch64_reg_hsh
;
462 static htab_t aarch64_barrier_opt_hsh
;
463 static htab_t aarch64_nzcv_hsh
;
464 static htab_t aarch64_pldop_hsh
;
465 static htab_t aarch64_hint_opt_hsh
;
467 /* Stuff needed to resolve the label ambiguity
476 static symbolS
*last_label_seen
;
478 /* Literal pool structure. Held on a per-section
479 and per-sub-section basis. */
481 #define MAX_LITERAL_POOL_SIZE 1024
482 typedef struct literal_expression
485 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
486 LITTLENUM_TYPE
* bignum
;
487 } literal_expression
;
489 typedef struct literal_pool
491 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
492 unsigned int next_free_entry
;
498 struct literal_pool
*next
;
501 /* Pointer to a linked list of literal pools. */
502 static literal_pool
*list_of_pools
= NULL
;
506 /* This array holds the chars that always start a comment. If the
507 pre-processor is disabled, these aren't very useful. */
508 const char comment_chars
[] = "";
510 /* This array holds the chars that only start a comment at the beginning of
511 a line. If the line seems to have the form '# 123 filename'
512 .line and .file directives will appear in the pre-processed output. */
513 /* Note that input_file.c hand checks for '#' at the beginning of the
514 first line of the input file. This is because the compiler outputs
515 #NO_APP at the beginning of its output. */
516 /* Also note that comments like this one will always work. */
517 const char line_comment_chars
[] = "#";
519 const char line_separator_chars
[] = ";";
521 /* Chars that can be used to separate mant
522 from exp in floating point numbers. */
523 const char EXP_CHARS
[] = "eE";
525 /* Chars that mean this number is a floating point constant. */
529 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
531 /* Prefix character that indicates the start of an immediate value. */
532 #define is_immediate_prefix(C) ((C) == '#')
534 /* Separator character handling. */
536 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
539 skip_past_char (char **str
, char c
)
550 #define skip_past_comma(str) skip_past_char (str, ',')
552 /* Arithmetic expressions (possibly involving symbols). */
554 static bool in_aarch64_get_expression
= false;
556 /* Third argument to aarch64_get_expression. */
557 #define GE_NO_PREFIX false
558 #define GE_OPT_PREFIX true
560 /* Fourth argument to aarch64_get_expression. */
561 #define ALLOW_ABSENT false
562 #define REJECT_ABSENT true
564 /* Return TRUE if the string pointed by *STR is successfully parsed
565 as an valid expression; *EP will be filled with the information of
566 such an expression. Otherwise return FALSE.
568 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
569 If REJECT_ABSENT is true then trat missing expressions as an error. */
572 aarch64_get_expression (expressionS
* ep
,
574 bool allow_immediate_prefix
,
579 bool prefix_present
= false;
581 if (allow_immediate_prefix
)
583 if (is_immediate_prefix (**str
))
586 prefix_present
= true;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_aarch64_get_expression
= true;
595 seg
= expression (ep
);
596 in_aarch64_get_expression
= false;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
615 && seg
!= undefined_section
)
617 set_syntax_error (_("bad segment"));
618 *str
= input_line_pointer
;
619 input_line_pointer
= save_in
;
626 *str
= input_line_pointer
;
627 input_line_pointer
= save_in
;
631 /* Turn a string in input_line_pointer into a floating point constant
632 of type TYPE, and store the appropriate bytes in *LITP. The number
633 of LITTLENUMS emitted is stored in *SIZEP. An error message is
634 returned, or NULL on OK. */
637 md_atof (int type
, char *litP
, int *sizeP
)
639 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
642 /* We handle all bad expressions here, so that we can report the faulty
643 instruction in the error message. */
645 md_operand (expressionS
* exp
)
647 if (in_aarch64_get_expression
)
648 exp
->X_op
= O_illegal
;
651 /* Immediate values. */
653 /* Errors may be set multiple times during parsing or bit encoding
654 (particularly in the Neon bits), but usually the earliest error which is set
655 will be the most meaningful. Avoid overwriting it with later (cascading)
656 errors by calling this function. */
659 first_error (const char *error
)
662 set_syntax_error (error
);
665 /* Similar to first_error, but this function accepts formatted error
668 first_error_fmt (const char *format
, ...)
673 /* N.B. this single buffer will not cause error messages for different
674 instructions to pollute each other; this is because at the end of
675 processing of each assembly line, error message if any will be
676 collected by as_bad. */
677 static char buffer
[size
];
681 int ret ATTRIBUTE_UNUSED
;
682 va_start (args
, format
);
683 ret
= vsnprintf (buffer
, size
, format
, args
);
684 know (ret
<= size
- 1 && ret
>= 0);
686 set_syntax_error (buffer
);
690 /* Internal helper routine converting a vector_type_el structure *VECTYPE
691 to a corresponding operand qualifier. */
693 static inline aarch64_opnd_qualifier_t
694 vectype_to_qualifier (const struct vector_type_el
*vectype
)
696 /* Element size in bytes indexed by vector_el_type. */
697 const unsigned char ele_size
[5]
699 const unsigned int ele_base
[5] =
701 AARCH64_OPND_QLF_V_4B
,
702 AARCH64_OPND_QLF_V_2H
,
703 AARCH64_OPND_QLF_V_2S
,
704 AARCH64_OPND_QLF_V_1D
,
705 AARCH64_OPND_QLF_V_1Q
708 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
709 goto vectype_conversion_fail
;
711 if (vectype
->type
== NT_zero
)
712 return AARCH64_OPND_QLF_P_Z
;
713 if (vectype
->type
== NT_merge
)
714 return AARCH64_OPND_QLF_P_M
;
716 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
718 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
720 /* Special case S_4B. */
721 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
722 return AARCH64_OPND_QLF_S_4B
;
724 /* Special case S_2H. */
725 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
726 return AARCH64_OPND_QLF_S_2H
;
728 /* Vector element register. */
729 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
733 /* Vector register. */
734 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
737 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
738 goto vectype_conversion_fail
;
740 /* The conversion is by calculating the offset from the base operand
741 qualifier for the vector type. The operand qualifiers are regular
742 enough that the offset can established by shifting the vector width by
743 a vector-type dependent amount. */
745 if (vectype
->type
== NT_b
)
747 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
749 else if (vectype
->type
>= NT_d
)
754 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
755 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
756 && offset
<= AARCH64_OPND_QLF_V_1Q
);
760 vectype_conversion_fail
:
761 first_error (_("bad vector arrangement type"));
762 return AARCH64_OPND_QLF_NIL
;
765 /* Register parsing. */
767 /* Generic register parser which is called by other specialized
769 CCP points to what should be the beginning of a register name.
770 If it is indeed a valid register name, advance CCP over it and
771 return the reg_entry structure; otherwise return NULL.
772 It does not issue diagnostics. */
775 parse_reg (char **ccp
)
781 #ifdef REGISTER_PREFIX
782 if (*start
!= REGISTER_PREFIX
)
788 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
793 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
795 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
804 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
807 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
809 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
812 /* Try to parse a base or offset register. Allow SVE base and offset
813 registers if REG_TYPE includes SVE registers. Return the register
814 entry on success, setting *QUALIFIER to the register qualifier.
815 Return null otherwise.
817 Note that this function does not issue any diagnostics. */
819 static const reg_entry
*
820 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
821 aarch64_opnd_qualifier_t
*qualifier
)
824 const reg_entry
*reg
= parse_reg (&str
);
834 *qualifier
= AARCH64_OPND_QLF_W
;
840 *qualifier
= AARCH64_OPND_QLF_X
;
844 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
847 switch (TOLOWER (str
[1]))
850 *qualifier
= AARCH64_OPND_QLF_S_S
;
853 *qualifier
= AARCH64_OPND_QLF_S_D
;
870 /* Try to parse a base or offset register. Return the register entry
871 on success, setting *QUALIFIER to the register qualifier. Return null
874 Note that this function does not issue any diagnostics. */
876 static const reg_entry
*
877 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
879 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
882 /* Parse the qualifier of a vector register or vector element of type
883 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
884 succeeds; otherwise return FALSE.
886 Accept only one occurrence of:
887 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
890 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
891 struct vector_type_el
*parsed_type
, char **str
)
895 unsigned element_size
;
896 enum vector_el_type type
;
899 gas_assert (*ptr
== '.');
902 if (reg_type
!= REG_TYPE_VN
|| !ISDIGIT (*ptr
))
907 width
= strtoul (ptr
, &ptr
, 10);
908 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
910 first_error_fmt (_("bad size %d in vector width specifier"), width
);
915 switch (TOLOWER (*ptr
))
934 if (reg_type
!= REG_TYPE_VN
|| width
== 1)
943 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
945 first_error (_("missing element size"));
948 if (width
!= 0 && width
* element_size
!= 64
949 && width
* element_size
!= 128
950 && !(width
== 2 && element_size
== 16)
951 && !(width
== 4 && element_size
== 8))
954 ("invalid element size %d and vector size combination %c"),
960 parsed_type
->type
= type
;
961 parsed_type
->width
= width
;
962 parsed_type
->element_size
= element_size
;
969 /* *STR contains an SVE zero/merge predication suffix. Parse it into
970 *PARSED_TYPE and point *STR at the end of the suffix. */
973 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
978 gas_assert (*ptr
== '/');
980 switch (TOLOWER (*ptr
))
983 parsed_type
->type
= NT_zero
;
986 parsed_type
->type
= NT_merge
;
989 if (*ptr
!= '\0' && *ptr
!= ',')
990 first_error_fmt (_("unexpected character `%c' in predication type"),
993 first_error (_("missing predication type"));
996 parsed_type
->width
= 0;
1001 /* Return true if CH is a valid suffix character for registers of
1005 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1018 return ch
== '.' || ch
== '/';
1025 /* Parse a register of the type TYPE.
1027 Return null if the string pointed to by *CCP is not a valid register
1028 name or the parsed register is not of TYPE.
1030 Otherwise return the register, and optionally return the register
1031 shape and element index information in *TYPEINFO.
1033 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1035 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1038 #define PTR_IN_REGLIST (1U << 0)
1039 #define PTR_FULL_REG (1U << 1)
1041 static const reg_entry
*
1042 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1043 struct vector_type_el
*typeinfo
, unsigned int flags
)
1046 const reg_entry
*reg
= parse_reg (&str
);
1047 struct vector_type_el atype
;
1048 struct vector_type_el parsetype
;
1049 bool is_typed_vecreg
= false;
1052 atype
.type
= NT_invtype
;
1054 atype
.element_size
= 0;
1061 set_default_error ();
1065 if (! aarch64_check_reg_type (reg
, type
))
1067 DEBUG_TRACE ("reg type check failed");
1068 set_default_error ();
1073 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1077 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1079 if ((reg
->type
== REG_TYPE_ZAT
1080 || reg
->type
== REG_TYPE_ZATH
1081 || reg
->type
== REG_TYPE_ZATV
)
1082 && reg
->number
* 8 >= parsetype
.element_size
)
1084 set_syntax_error (_("ZA tile number out of range"));
1090 if (!parse_predication_for_operand (&parsetype
, &str
))
1094 /* Register if of the form Vn.[bhsdq]. */
1095 is_typed_vecreg
= true;
1097 if (type
!= REG_TYPE_VN
)
1099 /* The width is always variable; we don't allow an integer width
1101 gas_assert (parsetype
.width
== 0);
1102 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1104 else if (parsetype
.width
== 0)
1105 /* Expect index. In the new scheme we cannot have
1106 Vn.[bhsdq] represent a scalar. Therefore any
1107 Vn.[bhsdq] should have an index following it.
1108 Except in reglists of course. */
1109 atype
.defined
|= NTA_HASINDEX
;
1111 atype
.defined
|= NTA_HASTYPE
;
1113 atype
.type
= parsetype
.type
;
1114 atype
.width
= parsetype
.width
;
1117 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1121 /* Reject Sn[index] syntax. */
1122 if (!is_typed_vecreg
)
1124 first_error (_("this type of register can't be indexed"));
1128 if (flags
& PTR_IN_REGLIST
)
1130 first_error (_("index not allowed inside register list"));
1134 atype
.defined
|= NTA_HASINDEX
;
1136 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1138 if (exp
.X_op
!= O_constant
)
1140 first_error (_("constant expression required"));
1144 if (! skip_past_char (&str
, ']'))
1147 atype
.index
= exp
.X_add_number
;
1149 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1151 /* Indexed vector register expected. */
1152 first_error (_("indexed vector register expected"));
1156 /* A vector reg Vn should be typed or indexed. */
1157 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1159 first_error (_("invalid use of vector register"));
1172 Return the register on success; return null otherwise.
1174 If this is a NEON vector register with additional type information, fill
1175 in the struct pointed to by VECTYPE (if non-NULL).
1177 This parser does not handle register lists. */
1179 static const reg_entry
*
1180 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1181 struct vector_type_el
*vectype
)
1183 return parse_typed_reg (ccp
, type
, vectype
, 0);
1187 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1189 return (e1
.type
== e2
.type
1190 && e1
.defined
== e2
.defined
1191 && e1
.width
== e2
.width
1192 && e1
.element_size
== e2
.element_size
1193 && e1
.index
== e2
.index
);
1196 /* This function parses a list of vector registers of type TYPE.
1197 On success, it returns the parsed register list information in the
1198 following encoded format:
1200 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1201 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1203 The information of the register shape and/or index is returned in
1206 It returns PARSE_FAIL if the register list is invalid.
1208 The list contains one to four registers.
1209 Each register can be one of:
1212 All <T> should be identical.
1213 All <index> should be identical.
1214 There are restrictions on <Vt> numbers which are checked later
1215 (by reg_list_valid_p). */
1218 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1219 struct vector_type_el
*vectype
)
1223 struct vector_type_el typeinfo
, typeinfo_first
;
1229 bool expect_index
= false;
1233 set_syntax_error (_("expecting {"));
1239 typeinfo_first
.defined
= 0;
1240 typeinfo_first
.type
= NT_invtype
;
1241 typeinfo_first
.width
= -1;
1242 typeinfo_first
.element_size
= 0;
1243 typeinfo_first
.index
= 0;
1252 str
++; /* skip over '-' */
1255 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1259 set_first_syntax_error (_("invalid vector register in list"));
1264 /* reject [bhsd]n */
1265 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1267 set_first_syntax_error (_("invalid scalar register in list"));
1272 if (typeinfo
.defined
& NTA_HASINDEX
)
1273 expect_index
= true;
1277 if (val
< val_range
)
1279 set_first_syntax_error
1280 (_("invalid range in vector register list"));
1289 typeinfo_first
= typeinfo
;
1290 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1292 set_first_syntax_error
1293 (_("type mismatch in vector register list"));
1298 for (i
= val_range
; i
<= val
; i
++)
1300 ret_val
|= i
<< (5 * nb_regs
);
1305 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1307 skip_whitespace (str
);
1310 set_first_syntax_error (_("end of vector register list not found"));
1315 skip_whitespace (str
);
1319 if (skip_past_char (&str
, '['))
1323 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1324 if (exp
.X_op
!= O_constant
)
1326 set_first_syntax_error (_("constant expression required."));
1329 if (! skip_past_char (&str
, ']'))
1332 typeinfo_first
.index
= exp
.X_add_number
;
1336 set_first_syntax_error (_("expected index"));
1343 set_first_syntax_error (_("too many registers in vector register list"));
1346 else if (nb_regs
== 0)
1348 set_first_syntax_error (_("empty vector register list"));
1354 *vectype
= typeinfo_first
;
1356 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1359 /* Directives: register aliases. */
1362 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1367 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1370 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1373 /* Only warn about a redefinition if it's not defined as the
1375 else if (new->number
!= number
|| new->type
!= type
)
1376 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1381 name
= xstrdup (str
);
1382 new = XNEW (reg_entry
);
1385 new->number
= number
;
1387 new->builtin
= false;
1389 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1394 /* Look for the .req directive. This is of the form:
1396 new_register_name .req existing_register_name
1398 If we find one, or if it looks sufficiently like one that we want to
1399 handle any error here, return TRUE. Otherwise return FALSE. */
1402 create_register_alias (char *newname
, char *p
)
1404 const reg_entry
*old
;
1405 char *oldname
, *nbuf
;
1408 /* The input scrubber ensures that whitespace after the mnemonic is
1409 collapsed to single spaces. */
1411 if (!startswith (oldname
, " .req "))
1415 if (*oldname
== '\0')
1418 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1421 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1425 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1426 the desired alias name, and p points to its end. If not, then
1427 the desired alias name is in the global original_case_string. */
1428 #ifdef TC_CASE_SENSITIVE
1431 newname
= original_case_string
;
1432 nlen
= strlen (newname
);
1435 nbuf
= xmemdup0 (newname
, nlen
);
1437 /* Create aliases under the new name as stated; an all-lowercase
1438 version of the new name; and an all-uppercase version of the new
1440 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1442 for (p
= nbuf
; *p
; p
++)
1445 if (strncmp (nbuf
, newname
, nlen
))
1447 /* If this attempt to create an additional alias fails, do not bother
1448 trying to create the all-lower case alias. We will fail and issue
1449 a second, duplicate error message. This situation arises when the
1450 programmer does something like:
1453 The second .req creates the "Foo" alias but then fails to create
1454 the artificial FOO alias because it has already been created by the
1456 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1463 for (p
= nbuf
; *p
; p
++)
1466 if (strncmp (nbuf
, newname
, nlen
))
1467 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1474 /* Should never be called, as .req goes between the alias and the
1475 register name, not at the beginning of the line. */
1477 s_req (int a ATTRIBUTE_UNUSED
)
1479 as_bad (_("invalid syntax for .req directive"));
1482 /* The .unreq directive deletes an alias which was previously defined
1483 by .req. For example:
1489 s_unreq (int a ATTRIBUTE_UNUSED
)
1494 name
= input_line_pointer
;
1495 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1496 saved_char
= *input_line_pointer
;
1497 *input_line_pointer
= 0;
1500 as_bad (_("invalid syntax for .unreq directive"));
1503 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1506 as_bad (_("unknown register alias '%s'"), name
);
1507 else if (reg
->builtin
)
1508 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1515 str_hash_delete (aarch64_reg_hsh
, name
);
1516 free ((char *) reg
->name
);
1519 /* Also locate the all upper case and all lower case versions.
1520 Do not complain if we cannot find one or the other as it
1521 was probably deleted above. */
1523 nbuf
= strdup (name
);
1524 for (p
= nbuf
; *p
; p
++)
1526 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1529 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1530 free ((char *) reg
->name
);
1534 for (p
= nbuf
; *p
; p
++)
1536 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1539 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1540 free ((char *) reg
->name
);
1548 *input_line_pointer
= saved_char
;
1549 demand_empty_rest_of_line ();
1552 /* Directives: Instruction set selection. */
1554 #if defined OBJ_ELF || defined OBJ_COFF
1555 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1556 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1557 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1558 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1560 /* Create a new mapping symbol for the transition to STATE. */
1563 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1566 const char *symname
;
1573 type
= BSF_NO_FLAGS
;
1577 type
= BSF_NO_FLAGS
;
1583 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1584 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1586 /* Save the mapping symbols for future reference. Also check that
1587 we do not place two mapping symbols at the same offset within a
1588 frag. We'll handle overlap between frags in
1589 check_mapping_symbols.
1591 If .fill or other data filling directive generates zero sized data,
1592 the mapping symbol for the following code will have the same value
1593 as the one generated for the data filling directive. In this case,
1594 we replace the old symbol with the new one at the same address. */
1597 if (frag
->tc_frag_data
.first_map
!= NULL
)
1599 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1600 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1603 frag
->tc_frag_data
.first_map
= symbolP
;
1605 if (frag
->tc_frag_data
.last_map
!= NULL
)
1607 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1608 S_GET_VALUE (symbolP
));
1609 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1610 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1613 frag
->tc_frag_data
.last_map
= symbolP
;
1616 /* We must sometimes convert a region marked as code to data during
1617 code alignment, if an odd number of bytes have to be padded. The
1618 code mapping symbol is pushed to an aligned address. */
1621 insert_data_mapping_symbol (enum mstate state
,
1622 valueT value
, fragS
* frag
, offsetT bytes
)
1624 /* If there was already a mapping symbol, remove it. */
1625 if (frag
->tc_frag_data
.last_map
!= NULL
1626 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1627 frag
->fr_address
+ value
)
1629 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1633 know (frag
->tc_frag_data
.first_map
== symp
);
1634 frag
->tc_frag_data
.first_map
= NULL
;
1636 frag
->tc_frag_data
.last_map
= NULL
;
1637 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1640 make_mapping_symbol (MAP_DATA
, value
, frag
);
1641 make_mapping_symbol (state
, value
+ bytes
, frag
);
1644 static void mapping_state_2 (enum mstate state
, int max_chars
);
1646 /* Set the mapping state to STATE. Only call this when about to
1647 emit some STATE bytes to the file. */
1650 mapping_state (enum mstate state
)
1652 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1654 if (state
== MAP_INSN
)
1655 /* AArch64 instructions require 4-byte alignment. When emitting
1656 instructions into any section, record the appropriate section
1658 record_alignment (now_seg
, 2);
1660 if (mapstate
== state
)
1661 /* The mapping symbol has already been emitted.
1662 There is nothing else to do. */
1665 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1666 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1667 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1668 evaluated later in the next else. */
1670 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1672 /* Only add the symbol if the offset is > 0:
1673 if we're at the first frag, check it's size > 0;
1674 if we're not at the first frag, then for sure
1675 the offset is > 0. */
1676 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1677 const int add_symbol
= (frag_now
!= frag_first
)
1678 || (frag_now_fix () > 0);
1681 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1685 mapping_state_2 (state
, 0);
1688 /* Same as mapping_state, but MAX_CHARS bytes have already been
1689 allocated. Put the mapping symbol that far back. */
1692 mapping_state_2 (enum mstate state
, int max_chars
)
1694 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1696 if (!SEG_NORMAL (now_seg
))
1699 if (mapstate
== state
)
1700 /* The mapping symbol has already been emitted.
1701 There is nothing else to do. */
1704 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1705 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1708 #define mapping_state(x) /* nothing */
1709 #define mapping_state_2(x, y) /* nothing */
1712 /* Directives: sectioning and alignment. */
1715 s_bss (int ignore ATTRIBUTE_UNUSED
)
1717 /* We don't support putting frags in the BSS segment, we fake it by
1718 marking in_bss, then looking at s_skip for clues. */
1719 subseg_set (bss_section
, 0);
1720 demand_empty_rest_of_line ();
1721 mapping_state (MAP_DATA
);
1725 s_even (int ignore ATTRIBUTE_UNUSED
)
1727 /* Never make frag if expect extra pass. */
1729 frag_align (1, 0, 0);
1731 record_alignment (now_seg
, 1);
1733 demand_empty_rest_of_line ();
1736 /* Directives: Literal pools. */
1738 static literal_pool
*
1739 find_literal_pool (int size
)
1743 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1745 if (pool
->section
== now_seg
1746 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1753 static literal_pool
*
1754 find_or_make_literal_pool (int size
)
1756 /* Next literal pool ID number. */
1757 static unsigned int latest_pool_num
= 1;
1760 pool
= find_literal_pool (size
);
1764 /* Create a new pool. */
1765 pool
= XNEW (literal_pool
);
1769 /* Currently we always put the literal pool in the current text
1770 section. If we were generating "small" model code where we
1771 knew that all code and initialised data was within 1MB then
1772 we could output literals to mergeable, read-only data
1775 pool
->next_free_entry
= 0;
1776 pool
->section
= now_seg
;
1777 pool
->sub_section
= now_subseg
;
1779 pool
->next
= list_of_pools
;
1780 pool
->symbol
= NULL
;
1782 /* Add it to the list. */
1783 list_of_pools
= pool
;
1786 /* New pools, and emptied pools, will have a NULL symbol. */
1787 if (pool
->symbol
== NULL
)
1789 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1790 &zero_address_frag
, 0);
1791 pool
->id
= latest_pool_num
++;
1798 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1799 Return TRUE on success, otherwise return FALSE. */
1801 add_to_lit_pool (expressionS
*exp
, int size
)
1806 pool
= find_or_make_literal_pool (size
);
1808 /* Check if this literal value is already in the pool. */
1809 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1811 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1813 if ((litexp
->X_op
== exp
->X_op
)
1814 && (exp
->X_op
== O_constant
)
1815 && (litexp
->X_add_number
== exp
->X_add_number
)
1816 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1819 if ((litexp
->X_op
== exp
->X_op
)
1820 && (exp
->X_op
== O_symbol
)
1821 && (litexp
->X_add_number
== exp
->X_add_number
)
1822 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1823 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1827 /* Do we need to create a new entry? */
1828 if (entry
== pool
->next_free_entry
)
1830 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1832 set_syntax_error (_("literal pool overflow"));
1836 pool
->literals
[entry
].exp
= *exp
;
1837 pool
->next_free_entry
+= 1;
1838 if (exp
->X_op
== O_big
)
1840 /* PR 16688: Bignums are held in a single global array. We must
1841 copy and preserve that value now, before it is overwritten. */
1842 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1844 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1845 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1848 pool
->literals
[entry
].bignum
= NULL
;
1851 exp
->X_op
= O_symbol
;
1852 exp
->X_add_number
= ((int) entry
) * size
;
1853 exp
->X_add_symbol
= pool
->symbol
;
1858 /* Can't use symbol_new here, so have to create a symbol and then at
1859 a later date assign it a value. That's what these functions do. */
1862 symbol_locate (symbolS
* symbolP
,
1863 const char *name
,/* It is copied, the caller can modify. */
1864 segT segment
, /* Segment identifier (SEG_<something>). */
1865 valueT valu
, /* Symbol value. */
1866 fragS
* frag
) /* Associated fragment. */
1869 char *preserved_copy_of_name
;
1871 name_length
= strlen (name
) + 1; /* +1 for \0. */
1872 obstack_grow (¬es
, name
, name_length
);
1873 preserved_copy_of_name
= obstack_finish (¬es
);
1875 #ifdef tc_canonicalize_symbol_name
1876 preserved_copy_of_name
=
1877 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1880 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1882 S_SET_SEGMENT (symbolP
, segment
);
1883 S_SET_VALUE (symbolP
, valu
);
1884 symbol_clear_list_pointers (symbolP
);
1886 symbol_set_frag (symbolP
, frag
);
1888 /* Link to end of symbol chain. */
1890 extern int symbol_table_frozen
;
1892 if (symbol_table_frozen
)
1896 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1898 obj_symbol_new_hook (symbolP
);
1900 #ifdef tc_symbol_new_hook
1901 tc_symbol_new_hook (symbolP
);
1905 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1906 #endif /* DEBUG_SYMS */
1911 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1918 for (align
= 2; align
<= 4; align
++)
1920 int size
= 1 << align
;
1922 pool
= find_literal_pool (size
);
1923 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1926 /* Align pool as you have word accesses.
1927 Only make a frag if we have to. */
1929 frag_align (align
, 0, 0);
1931 mapping_state (MAP_DATA
);
1933 record_alignment (now_seg
, align
);
1935 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1937 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1938 (valueT
) frag_now_fix (), frag_now
);
1939 symbol_table_insert (pool
->symbol
);
1941 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1943 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1945 if (exp
->X_op
== O_big
)
1947 /* PR 16688: Restore the global bignum value. */
1948 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1949 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1950 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1953 /* First output the expression in the instruction to the pool. */
1954 emit_expr (exp
, size
); /* .word|.xword */
1956 if (exp
->X_op
== O_big
)
1958 free (pool
->literals
[entry
].bignum
);
1959 pool
->literals
[entry
].bignum
= NULL
;
1963 /* Mark the pool as empty. */
1964 pool
->next_free_entry
= 0;
1965 pool
->symbol
= NULL
;
1969 #if defined(OBJ_ELF) || defined(OBJ_COFF)
1970 /* Forward declarations for functions below, in the MD interface
1972 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1974 /* Directives: Data. */
1975 /* N.B. the support for relocation suffix in this directive needs to be
1976 implemented properly. */
1979 s_aarch64_cons (int nbytes
)
1983 #ifdef md_flush_pending_output
1984 md_flush_pending_output ();
1987 if (is_it_end_of_statement ())
1989 demand_empty_rest_of_line ();
1993 #ifdef md_cons_align
1994 md_cons_align (nbytes
);
1997 mapping_state (MAP_DATA
);
2000 struct reloc_table_entry
*reloc
;
2004 if (exp
.X_op
!= O_symbol
)
2005 emit_expr (&exp
, (unsigned int) nbytes
);
2008 skip_past_char (&input_line_pointer
, '#');
2009 if (skip_past_char (&input_line_pointer
, ':'))
2011 reloc
= find_reloc_table_entry (&input_line_pointer
);
2013 as_bad (_("unrecognized relocation suffix"));
2015 as_bad (_("unimplemented relocation suffix"));
2016 ignore_rest_of_line ();
2020 emit_expr (&exp
, (unsigned int) nbytes
);
2023 while (*input_line_pointer
++ == ',');
2025 /* Put terminator back into stream. */
2026 input_line_pointer
--;
2027 demand_empty_rest_of_line ();
2032 /* Forward declarations for functions below, in the MD interface
2034 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2036 /* Mark symbol that it follows a variant PCS convention. */
2039 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2045 elf_symbol_type
*elfsym
;
2047 c
= get_symbol_name (&name
);
2049 as_bad (_("Missing symbol name in directive"));
2050 sym
= symbol_find_or_make (name
);
2051 restore_line_pointer (c
);
2052 demand_empty_rest_of_line ();
2053 bfdsym
= symbol_get_bfdsym (sym
);
2054 elfsym
= elf_symbol_from (bfdsym
);
2055 gas_assert (elfsym
);
2056 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2058 #endif /* OBJ_ELF */
2060 /* Output a 32-bit word, but mark as an instruction. */
2063 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2068 #ifdef md_flush_pending_output
2069 md_flush_pending_output ();
2072 if (is_it_end_of_statement ())
2074 demand_empty_rest_of_line ();
2078 /* Sections are assumed to start aligned. In executable section, there is no
2079 MAP_DATA symbol pending. So we only align the address during
2080 MAP_DATA --> MAP_INSN transition.
2081 For other sections, this is not guaranteed. */
2082 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2083 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2084 frag_align_code (2, 0);
2087 mapping_state (MAP_INSN
);
2093 if (exp
.X_op
!= O_constant
)
2095 as_bad (_("constant expression required"));
2096 ignore_rest_of_line ();
2100 if (target_big_endian
)
2102 unsigned int val
= exp
.X_add_number
;
2103 exp
.X_add_number
= SWAP_32 (val
);
2105 emit_expr (&exp
, INSN_SIZE
);
2108 while (*input_line_pointer
++ == ',');
2110 dwarf2_emit_insn (n
* INSN_SIZE
);
2112 /* Put terminator back into stream. */
2113 input_line_pointer
--;
2114 demand_empty_rest_of_line ();
2118 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2120 demand_empty_rest_of_line ();
2121 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2122 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2126 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2129 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2135 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2136 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2138 demand_empty_rest_of_line ();
2141 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2144 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2148 /* Since we're just labelling the code, there's no need to define a
2151 /* Make sure there is enough room in this frag for the following
2152 blr. This trick only works if the blr follows immediately after
2153 the .tlsdesc directive. */
2155 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2156 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2158 demand_empty_rest_of_line ();
2161 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2164 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2170 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2171 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2173 demand_empty_rest_of_line ();
2175 #endif /* OBJ_ELF */
2179 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2186 if (exp
.X_op
== O_symbol
)
2187 exp
.X_op
= O_secrel
;
2189 emit_expr (&exp
, 4);
2191 while (*input_line_pointer
++ == ',');
2193 input_line_pointer
--;
2194 demand_empty_rest_of_line ();
2198 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2202 exp
.X_op
= O_secrel
;
2203 exp
.X_add_symbol
= symbol
;
2204 exp
.X_add_number
= 0;
2205 emit_expr (&exp
, size
);
2209 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2216 if (exp
.X_op
== O_symbol
)
2217 exp
.X_op
= O_secidx
;
2219 emit_expr (&exp
, 2);
2221 while (*input_line_pointer
++ == ',');
2223 input_line_pointer
--;
2224 demand_empty_rest_of_line ();
2228 static void s_aarch64_arch (int);
2229 static void s_aarch64_cpu (int);
2230 static void s_aarch64_arch_extension (int);
2232 /* This table describes all the machine specific pseudo-ops the assembler
2233 has to support. The fields are:
2234 pseudo-op name without dot
2235 function to call to execute this pseudo-op
2236 Integer arg to pass to the function. */
2238 const pseudo_typeS md_pseudo_table
[] = {
2239 /* Never called because '.req' does not start a line. */
2241 {"unreq", s_unreq
, 0},
2243 {"even", s_even
, 0},
2244 {"ltorg", s_ltorg
, 0},
2245 {"pool", s_ltorg
, 0},
2246 {"cpu", s_aarch64_cpu
, 0},
2247 {"arch", s_aarch64_arch
, 0},
2248 {"arch_extension", s_aarch64_arch_extension
, 0},
2249 {"inst", s_aarch64_inst
, 0},
2250 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2252 {"tlsdescadd", s_tlsdescadd
, 0},
2253 {"tlsdesccall", s_tlsdesccall
, 0},
2254 {"tlsdescldr", s_tlsdescldr
, 0},
2255 {"variant_pcs", s_variant_pcs
, 0},
2257 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2258 {"word", s_aarch64_cons
, 4},
2259 {"long", s_aarch64_cons
, 4},
2260 {"xword", s_aarch64_cons
, 8},
2261 {"dword", s_aarch64_cons
, 8},
2264 {"secrel32", s_secrel
, 0},
2265 {"secidx", s_secidx
, 0},
2267 {"float16", float_cons
, 'h'},
2268 {"bfloat16", float_cons
, 'b'},
2273 /* Check whether STR points to a register name followed by a comma or the
2274 end of line; REG_TYPE indicates which register types are checked
2275 against. Return TRUE if STR is such a register name; otherwise return
2276 FALSE. The function does not intend to produce any diagnostics, but since
2277 the register parser aarch64_reg_parse, which is called by this function,
2278 does produce diagnostics, we call clear_error to clear any diagnostics
2279 that may be generated by aarch64_reg_parse.
2280 Also, the function returns FALSE directly if there is any user error
2281 present at the function entry. This prevents the existing diagnostics
2282 state from being spoiled.
2283 The function currently serves parse_constant_immediate and
2284 parse_big_immediate only. */
2286 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2288 const reg_entry
*reg
;
2290 /* Prevent the diagnostics state from being spoiled. */
2294 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2296 /* Clear the parsing error that may be set by the reg parser. */
2302 skip_whitespace (str
);
2303 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2309 /* Parser functions used exclusively in instruction operands. */
2311 /* Parse an immediate expression which may not be constant.
2313 To prevent the expression parser from pushing a register name
2314 into the symbol table as an undefined symbol, firstly a check is
2315 done to find out whether STR is a register of type REG_TYPE followed
2316 by a comma or the end of line. Return FALSE if STR is such a string. */
2319 parse_immediate_expression (char **str
, expressionS
*exp
,
2320 aarch64_reg_type reg_type
)
2322 if (reg_name_p (*str
, reg_type
))
2324 set_recoverable_error (_("immediate operand required"));
2328 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2330 if (exp
->X_op
== O_absent
)
2332 set_fatal_syntax_error (_("missing immediate expression"));
2339 /* Constant immediate-value read function for use in insn parsing.
2340 STR points to the beginning of the immediate (with the optional
2341 leading #); *VAL receives the value. REG_TYPE says which register
2342 names should be treated as registers rather than as symbolic immediates.
2344 Return TRUE on success; otherwise return FALSE. */
2347 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2351 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2354 if (exp
.X_op
!= O_constant
)
2356 set_syntax_error (_("constant expression required"));
2360 *val
= exp
.X_add_number
;
2365 encode_imm_float_bits (uint32_t imm
)
2367 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2368 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2371 /* Return TRUE if the single-precision floating-point value encoded in IMM
2372 can be expressed in the AArch64 8-bit signed floating-point format with
2373 3-bit exponent and normalized 4 bits of precision; in other words, the
2374 floating-point value must be expressable as
2375 (+/-) n / 16 * power (2, r)
2376 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2379 aarch64_imm_float_p (uint32_t imm
)
2381 /* If a single-precision floating-point value has the following bit
2382 pattern, it can be expressed in the AArch64 8-bit floating-point
2385 3 32222222 2221111111111
2386 1 09876543 21098765432109876543210
2387 n Eeeeeexx xxxx0000000000000000000
2389 where n, e and each x are either 0 or 1 independently, with
2394 /* Prepare the pattern for 'Eeeeee'. */
2395 if (((imm
>> 30) & 0x1) == 0)
2396 pattern
= 0x3e000000;
2398 pattern
= 0x40000000;
2400 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2401 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2404 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2405 as an IEEE float without any loss of precision. Store the value in
2409 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2411 /* If a double-precision floating-point value has the following bit
2412 pattern, it can be expressed in a float:
2414 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2415 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2416 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2418 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2419 if Eeee_eeee != 1111_1111
2421 where n, e, s and S are either 0 or 1 independently and where ~ is the
2425 uint32_t high32
= imm
>> 32;
2426 uint32_t low32
= imm
;
2428 /* Lower 29 bits need to be 0s. */
2429 if ((imm
& 0x1fffffff) != 0)
2432 /* Prepare the pattern for 'Eeeeeeeee'. */
2433 if (((high32
>> 30) & 0x1) == 0)
2434 pattern
= 0x38000000;
2436 pattern
= 0x40000000;
2439 if ((high32
& 0x78000000) != pattern
)
2442 /* Check Eeee_eeee != 1111_1111. */
2443 if ((high32
& 0x7ff00000) == 0x47f00000)
2446 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2447 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2448 | (low32
>> 29)); /* 3 S bits. */
2452 /* Return true if we should treat OPERAND as a double-precision
2453 floating-point operand rather than a single-precision one. */
2455 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2457 /* Check for unsuffixed SVE registers, which are allowed
2458 for LDR and STR but not in instructions that require an
2459 immediate. We get better error messages if we arbitrarily
2460 pick one size, parse the immediate normally, and then
2461 report the match failure in the normal way. */
2462 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2463 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2466 /* Parse a floating-point immediate. Return TRUE on success and return the
2467 value in *IMMED in the format of IEEE754 single-precision encoding.
2468 *CCP points to the start of the string; DP_P is TRUE when the immediate
2469 is expected to be in double-precision (N.B. this only matters when
2470 hexadecimal representation is involved). REG_TYPE says which register
2471 names should be treated as registers rather than as symbolic immediates.
2473 This routine accepts any IEEE float; it is up to the callers to reject
2477 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2478 aarch64_reg_type reg_type
)
2482 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2484 unsigned fpword
= 0;
2487 skip_past_char (&str
, '#');
2490 skip_whitespace (fpnum
);
2492 if (startswith (fpnum
, "0x"))
2494 /* Support the hexadecimal representation of the IEEE754 encoding.
2495 Double-precision is expected when DP_P is TRUE, otherwise the
2496 representation should be in single-precision. */
2497 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2502 if (!can_convert_double_to_float (val
, &fpword
))
2505 else if ((uint64_t) val
> 0xffffffff)
2512 else if (reg_name_p (str
, reg_type
))
2514 set_recoverable_error (_("immediate operand required"));
2522 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2525 /* Our FP word must be 32 bits (single-precision FP). */
2526 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2528 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2538 set_fatal_syntax_error (_("invalid floating-point constant"));
2542 /* Less-generic immediate-value read function with the possibility of loading
2543 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2546 To prevent the expression parser from pushing a register name into the
2547 symbol table as an undefined symbol, a check is firstly done to find
2548 out whether STR is a register of type REG_TYPE followed by a comma or
2549 the end of line. Return FALSE if STR is such a register. */
2552 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2556 if (reg_name_p (ptr
, reg_type
))
2558 set_syntax_error (_("immediate operand required"));
2562 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2564 if (inst
.reloc
.exp
.X_op
== O_constant
)
2565 *imm
= inst
.reloc
.exp
.X_add_number
;
2572 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2573 if NEED_LIBOPCODES is non-zero, the fixup will need
2574 assistance from the libopcodes. */
2577 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2578 const aarch64_opnd_info
*operand
,
2579 int need_libopcodes_p
)
2581 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2582 reloc
->opnd
= operand
->type
;
2583 if (need_libopcodes_p
)
2584 reloc
->need_libopcodes_p
= 1;
2587 /* Return TRUE if the instruction needs to be fixed up later internally by
2588 the GAS; otherwise return FALSE. */
2591 aarch64_gas_internal_fixup_p (void)
2593 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2596 /* Assign the immediate value to the relevant field in *OPERAND if
2597 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2598 needs an internal fixup in a later stage.
2599 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2600 IMM.VALUE that may get assigned with the constant. */
2602 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2603 aarch64_opnd_info
*operand
,
2605 int need_libopcodes_p
,
2608 if (reloc
->exp
.X_op
== O_constant
)
2611 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2613 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2614 reloc
->type
= BFD_RELOC_UNUSED
;
2618 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2619 /* Tell libopcodes to ignore this operand or not. This is helpful
2620 when one of the operands needs to be fixed up later but we need
2621 libopcodes to check the other operands. */
2622 operand
->skip
= skip_p
;
2626 /* Relocation modifiers. Each entry in the table contains the textual
2627 name for the relocation which may be placed before a symbol used as
2628 a load/store offset, or add immediate. It must be surrounded by a
2629 leading and trailing colon, for example:
2631 ldr x0, [x1, #:rello:varsym]
2632 add x0, x1, #:rello:varsym */
2634 struct reloc_table_entry
2638 bfd_reloc_code_real_type adr_type
;
2639 bfd_reloc_code_real_type adrp_type
;
2640 bfd_reloc_code_real_type movw_type
;
2641 bfd_reloc_code_real_type add_type
;
2642 bfd_reloc_code_real_type ldst_type
;
2643 bfd_reloc_code_real_type ld_literal_type
;
2646 static struct reloc_table_entry reloc_table
[] =
2648 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2653 BFD_RELOC_AARCH64_ADD_LO12
,
2654 BFD_RELOC_AARCH64_LDST_LO12
,
2657 /* Higher 21 bits of pc-relative page offset: ADRP */
2660 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2666 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2669 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2675 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2679 BFD_RELOC_AARCH64_MOVW_G0
,
2684 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2688 BFD_RELOC_AARCH64_MOVW_G0_S
,
2693 /* Less significant bits 0-15 of address/value: MOVK, no check */
2697 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2702 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2706 BFD_RELOC_AARCH64_MOVW_G1
,
2711 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2715 BFD_RELOC_AARCH64_MOVW_G1_S
,
2720 /* Less significant bits 16-31 of address/value: MOVK, no check */
2724 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2729 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2733 BFD_RELOC_AARCH64_MOVW_G2
,
2738 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2742 BFD_RELOC_AARCH64_MOVW_G2_S
,
2747 /* Less significant bits 32-47 of address/value: MOVK, no check */
2751 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2756 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2760 BFD_RELOC_AARCH64_MOVW_G3
,
2765 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2769 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2774 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2778 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2783 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2787 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2792 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2796 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2801 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2805 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2810 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2814 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2819 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2823 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2828 /* Get to the page containing GOT entry for a symbol. */
2831 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2835 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2837 /* 12 bit offset into the page containing GOT entry for that symbol. */
2843 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2846 /* 0-15 bits of address/value: MOVk, no check. */
2850 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2855 /* Most significant bits 16-31 of address/value: MOVZ. */
2859 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2864 /* 15 bit offset into the page containing GOT entry for that symbol. */
2870 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2873 /* Get to the page containing GOT TLS entry for a symbol */
2874 {"gottprel_g0_nc", 0,
2877 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2882 /* Get to the page containing GOT TLS entry for a symbol */
2886 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2891 /* Get to the page containing GOT TLS entry for a symbol */
2893 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2894 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2900 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2905 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2909 /* Lower 16 bits address/value: MOVk. */
2913 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2918 /* Most significant bits 16-31 of address/value: MOVZ. */
2922 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2927 /* Get to the page containing GOT TLS entry for a symbol */
2929 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2930 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2934 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2936 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2941 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2942 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2945 /* Get to the page containing GOT TLS entry for a symbol.
2946 The same as GD, we allocate two consecutive GOT slots
2947 for module index and module offset, the only difference
2948 with GD is the module offset should be initialized to
2949 zero without any outstanding runtime relocation. */
2951 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2952 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2958 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2959 {"tlsldm_lo12_nc", 0,
2963 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2967 /* 12 bit offset into the module TLS base address. */
2972 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2973 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2976 /* Same as dtprel_lo12, no overflow check. */
2977 {"dtprel_lo12_nc", 0,
2981 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2982 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2985 /* bits[23:12] of offset to the module TLS base address. */
2990 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2994 /* bits[15:0] of offset to the module TLS base address. */
2998 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3003 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3007 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3012 /* bits[31:16] of offset to the module TLS base address. */
3016 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3021 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3025 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3030 /* bits[47:32] of offset to the module TLS base address. */
3034 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3039 /* Lower 16 bit offset into GOT entry for a symbol */
3040 {"tlsdesc_off_g0_nc", 0,
3043 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3048 /* Higher 16 bit offset into GOT entry for a symbol */
3049 {"tlsdesc_off_g1", 0,
3052 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3057 /* Get to the page containing GOT TLS entry for a symbol */
3060 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3064 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3066 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3067 {"gottprel_lo12", 0,
3072 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3075 /* Get tp offset for a symbol. */
3080 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3084 /* Get tp offset for a symbol. */
3089 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3090 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3093 /* Get tp offset for a symbol. */
3098 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3102 /* Get tp offset for a symbol. */
3103 {"tprel_lo12_nc", 0,
3107 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3108 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3111 /* Most significant bits 32-47 of address/value: MOVZ. */
3115 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3120 /* Most significant bits 16-31 of address/value: MOVZ. */
3124 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3129 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3133 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3138 /* Most significant bits 0-15 of address/value: MOVZ. */
3142 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3147 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3151 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3156 /* 15bit offset from got entry to base address of GOT table. */
3162 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3165 /* 14bit offset from got entry to base address of GOT table. */
3171 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3175 /* Given the address of a pointer pointing to the textual name of a
3176 relocation as may appear in assembler source, attempt to find its
3177 details in reloc_table. The pointer will be updated to the character
3178 after the trailing colon. On failure, NULL will be returned;
3179 otherwise return the reloc_table_entry. */
3181 static struct reloc_table_entry
*
3182 find_reloc_table_entry (char **str
)
3185 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3187 int length
= strlen (reloc_table
[i
].name
);
3189 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3190 && (*str
)[length
] == ':')
3192 *str
+= (length
+ 1);
3193 return &reloc_table
[i
];
3200 /* Returns 0 if the relocation should never be forced,
3201 1 if the relocation must be forced, and -1 if either
3205 aarch64_force_reloc (unsigned int type
)
3209 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3210 /* Perform these "immediate" internal relocations
3211 even if the symbol is extern or weak. */
3214 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3215 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3216 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3217 /* Pseudo relocs that need to be fixed up according to
3221 case BFD_RELOC_AARCH64_ADD_LO12
:
3222 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3223 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3224 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3225 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3226 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3227 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3228 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3229 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3230 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3231 case BFD_RELOC_AARCH64_LDST128_LO12
:
3232 case BFD_RELOC_AARCH64_LDST16_LO12
:
3233 case BFD_RELOC_AARCH64_LDST32_LO12
:
3234 case BFD_RELOC_AARCH64_LDST64_LO12
:
3235 case BFD_RELOC_AARCH64_LDST8_LO12
:
3236 case BFD_RELOC_AARCH64_LDST_LO12
:
3237 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3238 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3239 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3240 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3241 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3242 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3243 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3244 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3245 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3246 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3247 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3248 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3249 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3250 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3251 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3252 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3253 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3254 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3255 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3256 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3257 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3258 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3259 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3260 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3261 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3262 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3263 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3264 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3265 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3266 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3267 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3268 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3269 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3270 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3271 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3272 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3273 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3274 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3275 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3276 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3277 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3278 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3279 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3280 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3281 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3282 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3283 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3284 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3285 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3286 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3287 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3288 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3289 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3290 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3291 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3292 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3293 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3294 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3295 /* Always leave these relocations for the linker. */
3304 aarch64_force_relocation (struct fix
*fixp
)
3306 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3309 return generic_force_reloc (fixp
);
3313 /* Mode argument to parse_shift and parser_shifter_operand. */
3314 enum parse_shift_mode
3316 SHIFTED_NONE
, /* no shifter allowed */
3317 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3319 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3321 SHIFTED_LSL
, /* bare "lsl #n" */
3322 SHIFTED_MUL
, /* bare "mul #n" */
3323 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3324 SHIFTED_MUL_VL
, /* "mul vl" */
3325 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3328 /* Parse a <shift> operator on an AArch64 data processing instruction.
3329 Return TRUE on success; otherwise return FALSE. */
3331 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3333 const struct aarch64_name_value_pair
*shift_op
;
3334 enum aarch64_modifier_kind kind
;
3340 for (p
= *str
; ISALPHA (*p
); p
++)
3345 set_syntax_error (_("shift expression expected"));
3349 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3351 if (shift_op
== NULL
)
3353 set_syntax_error (_("shift operator expected"));
3357 kind
= aarch64_get_operand_modifier (shift_op
);
3359 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3361 set_syntax_error (_("invalid use of 'MSL'"));
3365 if (kind
== AARCH64_MOD_MUL
3366 && mode
!= SHIFTED_MUL
3367 && mode
!= SHIFTED_MUL_VL
)
3369 set_syntax_error (_("invalid use of 'MUL'"));
3375 case SHIFTED_LOGIC_IMM
:
3376 if (aarch64_extend_operator_p (kind
))
3378 set_syntax_error (_("extending shift is not permitted"));
3383 case SHIFTED_ARITH_IMM
:
3384 if (kind
== AARCH64_MOD_ROR
)
3386 set_syntax_error (_("'ROR' shift is not permitted"));
3392 if (kind
!= AARCH64_MOD_LSL
)
3394 set_syntax_error (_("only 'LSL' shift is permitted"));
3400 if (kind
!= AARCH64_MOD_MUL
)
3402 set_syntax_error (_("only 'MUL' is permitted"));
3407 case SHIFTED_MUL_VL
:
3408 /* "MUL VL" consists of two separate tokens. Require the first
3409 token to be "MUL" and look for a following "VL". */
3410 if (kind
== AARCH64_MOD_MUL
)
3412 skip_whitespace (p
);
3413 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3416 kind
= AARCH64_MOD_MUL_VL
;
3420 set_syntax_error (_("only 'MUL VL' is permitted"));
3423 case SHIFTED_REG_OFFSET
:
3424 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3425 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3427 set_fatal_syntax_error
3428 (_("invalid shift for the register offset addressing mode"));
3433 case SHIFTED_LSL_MSL
:
3434 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3436 set_syntax_error (_("invalid shift operator"));
3445 /* Whitespace can appear here if the next thing is a bare digit. */
3446 skip_whitespace (p
);
3448 /* Parse shift amount. */
3450 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3451 exp
.X_op
= O_absent
;
3454 if (is_immediate_prefix (*p
))
3459 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3461 if (kind
== AARCH64_MOD_MUL_VL
)
3462 /* For consistency, give MUL VL the same shift amount as an implicit
3464 operand
->shifter
.amount
= 1;
3465 else if (exp
.X_op
== O_absent
)
3467 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3469 set_syntax_error (_("missing shift amount"));
3472 operand
->shifter
.amount
= 0;
3474 else if (exp
.X_op
!= O_constant
)
3476 set_syntax_error (_("constant shift amount required"));
3479 /* For parsing purposes, MUL #n has no inherent range. The range
3480 depends on the operand and will be checked by operand-specific
3482 else if (kind
!= AARCH64_MOD_MUL
3483 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3485 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3490 operand
->shifter
.amount
= exp
.X_add_number
;
3491 operand
->shifter
.amount_present
= 1;
3494 operand
->shifter
.operator_present
= 1;
3495 operand
->shifter
.kind
= kind
;
3501 /* Parse a <shifter_operand> for a data processing instruction:
3504 #<immediate>, LSL #imm
3506 Validation of immediate operands is deferred to md_apply_fix.
3508 Return TRUE on success; otherwise return FALSE. */
3511 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3512 enum parse_shift_mode mode
)
3516 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3521 /* Accept an immediate expression. */
3522 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3526 /* Accept optional LSL for arithmetic immediate values. */
3527 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3528 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3531 /* Not accept any shifter for logical immediate values. */
3532 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3533 && parse_shift (&p
, operand
, mode
))
3535 set_syntax_error (_("unexpected shift operator"));
3543 /* Parse a <shifter_operand> for a data processing instruction:
3548 #<immediate>, LSL #imm
3550 where <shift> is handled by parse_shift above, and the last two
3551 cases are handled by the function above.
3553 Validation of immediate operands is deferred to md_apply_fix.
3555 Return TRUE on success; otherwise return FALSE. */
3558 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3559 enum parse_shift_mode mode
)
3561 const reg_entry
*reg
;
3562 aarch64_opnd_qualifier_t qualifier
;
3563 enum aarch64_operand_class opd_class
3564 = aarch64_get_operand_class (operand
->type
);
3566 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3569 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3571 set_syntax_error (_("unexpected register in the immediate operand"));
3575 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3577 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3581 operand
->reg
.regno
= reg
->number
;
3582 operand
->qualifier
= qualifier
;
3584 /* Accept optional shift operation on register. */
3585 if (! skip_past_comma (str
))
3588 if (! parse_shift (str
, operand
, mode
))
3593 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3596 (_("integer register expected in the extended/shifted operand "
3601 /* We have a shifted immediate variable. */
3602 return parse_shifter_operand_imm (str
, operand
, mode
);
3605 /* Return TRUE on success; return FALSE otherwise. */
3608 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3609 enum parse_shift_mode mode
)
3613 /* Determine if we have the sequence of characters #: or just :
3614 coming next. If we do, then we check for a :rello: relocation
3615 modifier. If we don't, punt the whole lot to
3616 parse_shifter_operand. */
3618 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3620 struct reloc_table_entry
*entry
;
3628 /* Try to parse a relocation. Anything else is an error. */
3629 if (!(entry
= find_reloc_table_entry (str
)))
3631 set_syntax_error (_("unknown relocation modifier"));
3635 if (entry
->add_type
== 0)
3638 (_("this relocation modifier is not allowed on this instruction"));
3642 /* Save str before we decompose it. */
3645 /* Next, we parse the expression. */
3646 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3650 /* Record the relocation type (use the ADD variant here). */
3651 inst
.reloc
.type
= entry
->add_type
;
3652 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3654 /* If str is empty, we've reached the end, stop here. */
3658 /* Otherwise, we have a shifted reloc modifier, so rewind to
3659 recover the variable name and continue parsing for the shifter. */
3661 return parse_shifter_operand_imm (str
, operand
, mode
);
3664 return parse_shifter_operand (str
, operand
, mode
);
3667 /* Parse all forms of an address expression. Information is written
3668 to *OPERAND and/or inst.reloc.
3670 The A64 instruction set has the following addressing modes:
3673 [base] // in SIMD ld/st structure
3674 [base{,#0}] // in ld/st exclusive
3676 [base,Xm{,LSL #imm}]
3677 [base,Xm,SXTX {#imm}]
3678 [base,Wm,(S|U)XTW {#imm}]
3680 [base]! // in ldraa/ldrab exclusive
3684 [base],Xm // in SIMD ld/st structure
3685 PC-relative (literal)
3689 [base,Zm.D{,LSL #imm}]
3690 [base,Zm.S,(S|U)XTW {#imm}]
3691 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3695 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3696 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3697 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3699 (As a convenience, the notation "=immediate" is permitted in conjunction
3700 with the pc-relative literal load instructions to automatically place an
3701 immediate value or symbolic address in a nearby literal pool and generate
3702 a hidden label which references it.)
3704 Upon a successful parsing, the address structure in *OPERAND will be
3705 filled in the following way:
3707 .base_regno = <base>
3708 .offset.is_reg // 1 if the offset is a register
3710 .offset.regno = <Rm>
3712 For different addressing modes defined in the A64 ISA:
3715 .pcrel=0; .preind=1; .postind=0; .writeback=0
3717 .pcrel=0; .preind=1; .postind=0; .writeback=1
3719 .pcrel=0; .preind=0; .postind=1; .writeback=1
3720 PC-relative (literal)
3721 .pcrel=1; .preind=1; .postind=0; .writeback=0
3723 The shift/extension information, if any, will be stored in .shifter.
3724 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3725 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3726 corresponding register.
3728 BASE_TYPE says which types of base register should be accepted and
3729 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3730 is the type of shifter that is allowed for immediate offsets,
3731 or SHIFTED_NONE if none.
3733 In all other respects, it is the caller's responsibility to check
3734 for addressing modes not supported by the instruction, and to set
3738 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3739 aarch64_opnd_qualifier_t
*base_qualifier
,
3740 aarch64_opnd_qualifier_t
*offset_qualifier
,
3741 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3742 enum parse_shift_mode imm_shift_mode
)
3745 const reg_entry
*reg
;
3746 expressionS
*exp
= &inst
.reloc
.exp
;
3748 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3749 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3750 if (! skip_past_char (&p
, '['))
3752 /* =immediate or label. */
3753 operand
->addr
.pcrel
= 1;
3754 operand
->addr
.preind
= 1;
3756 /* #:<reloc_op>:<symbol> */
3757 skip_past_char (&p
, '#');
3758 if (skip_past_char (&p
, ':'))
3760 bfd_reloc_code_real_type ty
;
3761 struct reloc_table_entry
*entry
;
3763 /* Try to parse a relocation modifier. Anything else is
3765 entry
= find_reloc_table_entry (&p
);
3768 set_syntax_error (_("unknown relocation modifier"));
3772 switch (operand
->type
)
3774 case AARCH64_OPND_ADDR_PCREL21
:
3776 ty
= entry
->adr_type
;
3780 ty
= entry
->ld_literal_type
;
3787 (_("this relocation modifier is not allowed on this "
3793 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3795 set_syntax_error (_("invalid relocation expression"));
3798 /* #:<reloc_op>:<expr> */
3799 /* Record the relocation type. */
3800 inst
.reloc
.type
= ty
;
3801 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3805 if (skip_past_char (&p
, '='))
3806 /* =immediate; need to generate the literal in the literal pool. */
3807 inst
.gen_lit_pool
= 1;
3809 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3811 set_syntax_error (_("invalid address"));
3822 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3823 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3825 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3828 operand
->addr
.base_regno
= reg
->number
;
3831 if (skip_past_comma (&p
))
3834 operand
->addr
.preind
= 1;
3836 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3839 if (!aarch64_check_reg_type (reg
, offset_type
))
3841 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3846 operand
->addr
.offset
.regno
= reg
->number
;
3847 operand
->addr
.offset
.is_reg
= 1;
3848 /* Shifted index. */
3849 if (skip_past_comma (&p
))
3852 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3853 /* Use the diagnostics set in parse_shift, so not set new
3854 error message here. */
3858 [base,Xm] # For vector plus scalar SVE2 indexing.
3859 [base,Xm{,LSL #imm}]
3860 [base,Xm,SXTX {#imm}]
3861 [base,Wm,(S|U)XTW {#imm}] */
3862 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3863 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3864 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3866 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3868 set_syntax_error (_("invalid use of 32-bit register offset"));
3871 if (aarch64_get_qualifier_esize (*base_qualifier
)
3872 != aarch64_get_qualifier_esize (*offset_qualifier
)
3873 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3874 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3875 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3877 set_syntax_error (_("offset has different size from base"));
3881 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3883 set_syntax_error (_("invalid use of 64-bit register offset"));
3889 /* [Xn,#:<reloc_op>:<symbol> */
3890 skip_past_char (&p
, '#');
3891 if (skip_past_char (&p
, ':'))
3893 struct reloc_table_entry
*entry
;
3895 /* Try to parse a relocation modifier. Anything else is
3897 if (!(entry
= find_reloc_table_entry (&p
)))
3899 set_syntax_error (_("unknown relocation modifier"));
3903 if (entry
->ldst_type
== 0)
3906 (_("this relocation modifier is not allowed on this "
3911 /* [Xn,#:<reloc_op>: */
3912 /* We now have the group relocation table entry corresponding to
3913 the name in the assembler source. Next, we parse the
3915 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3917 set_syntax_error (_("invalid relocation expression"));
3921 /* [Xn,#:<reloc_op>:<expr> */
3922 /* Record the load/store relocation type. */
3923 inst
.reloc
.type
= entry
->ldst_type
;
3924 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3928 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3930 set_syntax_error (_("invalid expression in the address"));
3934 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3935 /* [Xn,<expr>,<shifter> */
3936 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3942 if (! skip_past_char (&p
, ']'))
3944 set_syntax_error (_("']' expected"));
3948 if (skip_past_char (&p
, '!'))
3950 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3952 set_syntax_error (_("register offset not allowed in pre-indexed "
3953 "addressing mode"));
3957 operand
->addr
.writeback
= 1;
3959 else if (skip_past_comma (&p
))
3962 operand
->addr
.postind
= 1;
3963 operand
->addr
.writeback
= 1;
3965 if (operand
->addr
.preind
)
3967 set_syntax_error (_("cannot combine pre- and post-indexing"));
3971 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3975 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3977 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3981 operand
->addr
.offset
.regno
= reg
->number
;
3982 operand
->addr
.offset
.is_reg
= 1;
3984 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3987 set_syntax_error (_("invalid expression in the address"));
3992 /* If at this point neither .preind nor .postind is set, we have a
3993 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3994 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3995 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3997 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3999 if (operand
->addr
.writeback
)
4001 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4003 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4004 operand
->addr
.offset
.is_reg
= 0;
4005 operand
->addr
.offset
.imm
= 0;
4006 operand
->addr
.preind
= 1;
4011 set_syntax_error (_("missing offset in the pre-indexed address"));
4017 operand
->addr
.preind
= 1;
4018 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4020 operand
->addr
.offset
.is_reg
= 1;
4021 operand
->addr
.offset
.regno
= REG_ZR
;
4022 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4026 inst
.reloc
.exp
.X_op
= O_constant
;
4027 inst
.reloc
.exp
.X_add_number
= 0;
4036 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4039 parse_address (char **str
, aarch64_opnd_info
*operand
)
4041 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4042 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4043 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4046 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4047 The arguments have the same meaning as for parse_address_main.
4048 Return TRUE on success. */
4050 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4051 aarch64_opnd_qualifier_t
*base_qualifier
,
4052 aarch64_opnd_qualifier_t
*offset_qualifier
)
4054 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4055 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4059 /* Parse a register X0-X30. The register must be 64-bit and register 31
4062 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4064 const reg_entry
*reg
= parse_reg (str
);
4065 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4067 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
4070 operand
->reg
.regno
= reg
->number
;
4071 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4075 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4076 Return TRUE on success; otherwise return FALSE. */
4078 parse_half (char **str
, int *internal_fixup_p
)
4082 skip_past_char (&p
, '#');
4084 gas_assert (internal_fixup_p
);
4085 *internal_fixup_p
= 0;
4089 struct reloc_table_entry
*entry
;
4091 /* Try to parse a relocation. Anything else is an error. */
4094 if (!(entry
= find_reloc_table_entry (&p
)))
4096 set_syntax_error (_("unknown relocation modifier"));
4100 if (entry
->movw_type
== 0)
4103 (_("this relocation modifier is not allowed on this instruction"));
4107 inst
.reloc
.type
= entry
->movw_type
;
4110 *internal_fixup_p
= 1;
4112 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4119 /* Parse an operand for an ADRP instruction:
4121 Return TRUE on success; otherwise return FALSE. */
4124 parse_adrp (char **str
)
4131 struct reloc_table_entry
*entry
;
4133 /* Try to parse a relocation. Anything else is an error. */
4135 if (!(entry
= find_reloc_table_entry (&p
)))
4137 set_syntax_error (_("unknown relocation modifier"));
4141 if (entry
->adrp_type
== 0)
4144 (_("this relocation modifier is not allowed on this instruction"));
4148 inst
.reloc
.type
= entry
->adrp_type
;
4151 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4153 inst
.reloc
.pc_rel
= 1;
4154 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4160 /* Miscellaneous. */
4162 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4163 of SIZE tokens in which index I gives the token for field value I,
4164 or is null if field value I is invalid. REG_TYPE says which register
4165 names should be treated as registers rather than as symbolic immediates.
4167 Return true on success, moving *STR past the operand and storing the
4168 field value in *VAL. */
4171 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4172 size_t size
, aarch64_reg_type reg_type
)
4178 /* Match C-like tokens. */
4180 while (ISALNUM (*q
))
4183 for (i
= 0; i
< size
; ++i
)
4185 && strncasecmp (array
[i
], p
, q
- p
) == 0
4186 && array
[i
][q
- p
] == 0)
4193 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4196 if (exp
.X_op
== O_constant
4197 && (uint64_t) exp
.X_add_number
< size
)
4199 *val
= exp
.X_add_number
;
4204 /* Use the default error for this operand. */
4208 /* Parse an option for a preload instruction. Returns the encoding for the
4209 option, or PARSE_FAIL. */
4212 parse_pldop (char **str
)
4215 const struct aarch64_name_value_pair
*o
;
4218 while (ISALNUM (*q
))
4221 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4229 /* Parse an option for a barrier instruction. Returns the encoding for the
4230 option, or PARSE_FAIL. */
4233 parse_barrier (char **str
)
4236 const struct aarch64_name_value_pair
*o
;
4239 while (ISALPHA (*q
))
4242 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4250 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4251 return 0 if successful. Otherwise return PARSE_FAIL. */
4254 parse_barrier_psb (char **str
,
4255 const struct aarch64_name_value_pair
** hint_opt
)
4258 const struct aarch64_name_value_pair
*o
;
4261 while (ISALPHA (*q
))
4264 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4267 set_fatal_syntax_error
4268 ( _("unknown or missing option to PSB/TSB"));
4272 if (o
->value
!= 0x11)
4274 /* PSB only accepts option name 'CSYNC'. */
4276 (_("the specified option is not accepted for PSB/TSB"));
4285 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4286 return 0 if successful. Otherwise return PARSE_FAIL. */
4289 parse_bti_operand (char **str
,
4290 const struct aarch64_name_value_pair
** hint_opt
)
4293 const struct aarch64_name_value_pair
*o
;
4296 while (ISALPHA (*q
))
4299 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4302 set_fatal_syntax_error
4303 ( _("unknown option to BTI"));
4309 /* Valid BTI operands. */
4317 (_("unknown option to BTI"));
4326 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4327 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4332 Side effect: Update STR with current parse position of success.
4335 static const reg_entry
*
4336 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4337 aarch64_opnd_qualifier_t
*qualifier
)
4339 struct vector_type_el vectype
;
4340 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4345 if (vectype
.type
== NT_invtype
)
4346 *qualifier
= AARCH64_OPND_QLF_NIL
;
4349 *qualifier
= vectype_to_qualifier (&vectype
);
4350 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4357 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4362 Function return TRUE if immediate was found, or FALSE.
4365 parse_sme_immediate (char **str
, int64_t *imm
)
4368 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4375 /* Parse index with vector select register and immediate:
4379 where <Wv> is in W12-W15 range and # is optional for immediate.
4381 Return true on success, populating OPND with the parsed index. */
4384 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4386 const reg_entry
*reg
;
4388 if (!skip_past_char (str
, '['))
4390 set_syntax_error (_("expected '['"));
4394 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4395 reg
= parse_reg (str
);
4396 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4397 || reg
->number
< 12 || reg
->number
> 15)
4399 set_syntax_error (_("expected vector select register W12-W15"));
4402 opnd
->index
.regno
= reg
->number
;
4404 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4406 set_syntax_error (_("expected ','"));
4410 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4412 set_syntax_error (_("index offset immediate expected"));
4416 if (!skip_past_char (str
, ']'))
4418 set_syntax_error (_("expected ']'"));
4425 /* Parse SME ZA horizontal or vertical vector access to tiles.
4426 Return true on success, populating OPND with information about
4427 the indexed tile and QUALIFIER with the qualifier that was applied
4430 Field format examples:
4432 ZA0<HV>.B[<Wv>, #<imm>]
4433 <ZAn><HV>.H[<Wv>, #<imm>]
4434 <ZAn><HV>.S[<Wv>, #<imm>]
4435 <ZAn><HV>.D[<Wv>, #<imm>]
4436 <ZAn><HV>.Q[<Wv>, #<imm>]
4439 parse_sme_za_hv_tiles_operand (char **str
,
4440 struct aarch64_indexed_za
*opnd
,
4441 aarch64_opnd_qualifier_t
*qualifier
)
4444 const reg_entry
*reg
;
4446 reg
= parse_reg_with_qual (str
, REG_TYPE_ZATHV
, qualifier
);
4450 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4451 opnd
->regno
= reg
->number
;
4455 case AARCH64_OPND_QLF_S_B
:
4458 case AARCH64_OPND_QLF_S_H
:
4461 case AARCH64_OPND_QLF_S_S
:
4464 case AARCH64_OPND_QLF_S_D
:
4467 case AARCH64_OPND_QLF_S_Q
:
4471 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4475 if (!parse_sme_za_index (str
, opnd
))
4478 /* Check if optional index offset is in the range for instruction
4480 if (opnd
->index
.imm
< 0 || opnd
->index
.imm
> imm_limit
)
4482 set_syntax_error (_("index offset out of range"));
4489 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4493 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4494 struct aarch64_indexed_za
*opnd
,
4495 aarch64_opnd_qualifier_t
*qualifier
)
4497 if (!skip_past_char (str
, '{'))
4499 set_syntax_error (_("expected '{'"));
4503 if (!parse_sme_za_hv_tiles_operand (str
, opnd
, qualifier
))
4506 if (!skip_past_char (str
, '}'))
4508 set_syntax_error (_("expected '}'"));
4515 /* Parse list of up to eight 64-bit element tile names separated by commas in
4516 SME's ZERO instruction:
4520 Function returns <mask>:
4522 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4525 parse_sme_zero_mask(char **str
)
4529 aarch64_opnd_qualifier_t qualifier
;
4535 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4540 if (reg
->type
== REG_TYPE_ZA
)
4542 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4544 set_syntax_error ("ZA should not have a size suffix");
4547 /* { ZA } is assembled as all-ones immediate. */
4552 int regno
= reg
->number
;
4553 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4555 /* { ZA0.B } is assembled as all-ones immediate. */
4558 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4559 mask
|= 0x55 << regno
;
4560 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4561 mask
|= 0x11 << regno
;
4562 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4563 mask
|= 0x01 << regno
;
4564 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4566 set_syntax_error (_("ZA tile masks do not operate at .Q"
4570 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4572 set_syntax_error (_("missing ZA tile size"));
4577 set_syntax_error (_("invalid ZA tile"));
4582 while (skip_past_char (&q
, ','));
4588 /* Wraps in curly braces <mask> operand ZERO instruction:
4592 Function returns value of <mask> bit-field.
4595 parse_sme_list_of_64bit_tiles (char **str
)
4599 if (!skip_past_char (str
, '{'))
4601 set_syntax_error (_("expected '{'"));
4605 /* Empty <mask> list is an all-zeros immediate. */
4606 if (!skip_past_char (str
, '}'))
4608 regno
= parse_sme_zero_mask (str
);
4609 if (regno
== PARSE_FAIL
)
4612 if (!skip_past_char (str
, '}'))
4614 set_syntax_error (_("expected '}'"));
4624 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4630 Return true on success, populating OPND with information about
4634 parse_sme_za_array (char **str
, struct aarch64_indexed_za
*opnd
)
4639 const reg_entry
*reg
= parse_reg (&q
);
4640 if (!reg
|| reg
->type
!= REG_TYPE_ZA
)
4642 set_syntax_error (_("expected ZA array"));
4647 if (! parse_sme_za_index (&q
, opnd
))
4650 if (opnd
->index
.imm
< 0 || opnd
->index
.imm
> 15)
4652 set_syntax_error (_("offset out of range"));
4660 /* Parse streaming mode operand for SMSTART and SMSTOP.
4664 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4667 parse_sme_sm_za (char **str
)
4672 while (ISALPHA (*q
))
4676 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4678 set_syntax_error (_("expected SM or ZA operand"));
4683 return TOLOWER (p
[0]);
4686 /* Parse the name of the source scalable predicate register, the index base
4687 register W12-W15 and the element index. Function performs element index
4688 limit checks as well as qualifier type checks.
4690 <Pn>.<T>[<Wv>, <imm>]
4691 <Pn>.<T>[<Wv>, #<imm>]
4693 Return true on success, populating OPND with information about the index
4694 and setting QUALIFIER to <T>. */
4697 parse_sme_pred_reg_with_index (char **str
, struct aarch64_indexed_za
*opnd
,
4698 aarch64_opnd_qualifier_t
*qualifier
)
4702 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4706 regno
= reg
->number
;
4710 case AARCH64_OPND_QLF_S_B
:
4713 case AARCH64_OPND_QLF_S_H
:
4716 case AARCH64_OPND_QLF_S_S
:
4719 case AARCH64_OPND_QLF_S_D
:
4723 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4726 opnd
->regno
= regno
;
4728 if (! parse_sme_za_index (str
, opnd
))
4731 if (opnd
->index
.imm
< 0 || opnd
->index
.imm
> imm_limit
)
4733 set_syntax_error (_("element index out of range for given variant"));
4740 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4741 Returns the encoding for the option, or PARSE_FAIL.
4743 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4744 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4746 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4747 field, otherwise as a system register.
4751 parse_sys_reg (char **str
, htab_t sys_regs
,
4752 int imple_defined_p
, int pstatefield_p
,
4756 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4757 const aarch64_sys_reg
*o
;
4761 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4762 if (p
< buf
+ (sizeof (buf
) - 1))
4763 *p
++ = TOLOWER (*q
);
4766 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4767 valid system register. This is enforced by construction of the hash
4769 if (p
- buf
!= q
- *str
)
4772 o
= str_hash_find (sys_regs
, buf
);
4775 if (!imple_defined_p
)
4779 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4780 unsigned int op0
, op1
, cn
, cm
, op2
;
4782 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4785 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4787 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4794 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4795 as_bad (_("selected processor does not support PSTATE field "
4798 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4799 o
->value
, o
->flags
, o
->features
))
4800 as_bad (_("selected processor does not support system register "
4802 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4803 as_warn (_("system register name '%s' is deprecated and may be "
4804 "removed in a future release"), buf
);
4814 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4815 for the option, or NULL. */
4817 static const aarch64_sys_ins_reg
*
4818 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4821 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4822 const aarch64_sys_ins_reg
*o
;
4825 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4826 if (p
< buf
+ (sizeof (buf
) - 1))
4827 *p
++ = TOLOWER (*q
);
4830 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4831 valid system register. This is enforced by construction of the hash
4833 if (p
- buf
!= q
- *str
)
4836 o
= str_hash_find (sys_ins_regs
, buf
);
4840 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4841 o
->name
, o
->value
, o
->flags
, 0))
4842 as_bad (_("selected processor does not support system register "
4844 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4845 as_warn (_("system register name '%s' is deprecated and may be "
4846 "removed in a future release"), buf
);
4852 #define po_char_or_fail(chr) do { \
4853 if (! skip_past_char (&str, chr)) \
4857 #define po_reg_or_fail(regtype) do { \
4858 reg = aarch64_reg_parse (&str, regtype, NULL); \
4861 set_default_error (); \
4866 #define po_int_reg_or_fail(reg_type) do { \
4867 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4868 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4870 set_default_error (); \
4873 info->reg.regno = reg->number; \
4874 info->qualifier = qualifier; \
4877 #define po_imm_nc_or_fail() do { \
4878 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4882 #define po_imm_or_fail(min, max) do { \
4883 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4885 if (val < min || val > max) \
4887 set_fatal_syntax_error (_("immediate value out of range "\
4888 #min " to "#max)); \
4893 #define po_enum_or_fail(array) do { \
4894 if (!parse_enum_string (&str, &val, array, \
4895 ARRAY_SIZE (array), imm_reg_type)) \
4899 #define po_misc_or_fail(expr) do { \
4904 /* encode the 12-bit imm field of Add/sub immediate */
4905 static inline uint32_t
4906 encode_addsub_imm (uint32_t imm
)
4911 /* encode the shift amount field of Add/sub immediate */
4912 static inline uint32_t
4913 encode_addsub_imm_shift_amount (uint32_t cnt
)
4919 /* encode the imm field of Adr instruction */
4920 static inline uint32_t
4921 encode_adr_imm (uint32_t imm
)
4923 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4924 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4927 /* encode the immediate field of Move wide immediate */
4928 static inline uint32_t
4929 encode_movw_imm (uint32_t imm
)
4934 /* encode the 26-bit offset of unconditional branch */
4935 static inline uint32_t
4936 encode_branch_ofs_26 (uint32_t ofs
)
4938 return ofs
& ((1 << 26) - 1);
4941 /* encode the 19-bit offset of conditional branch and compare & branch */
4942 static inline uint32_t
4943 encode_cond_branch_ofs_19 (uint32_t ofs
)
4945 return (ofs
& ((1 << 19) - 1)) << 5;
4948 /* encode the 19-bit offset of ld literal */
4949 static inline uint32_t
4950 encode_ld_lit_ofs_19 (uint32_t ofs
)
4952 return (ofs
& ((1 << 19) - 1)) << 5;
4955 /* Encode the 14-bit offset of test & branch. */
4956 static inline uint32_t
4957 encode_tst_branch_ofs_14 (uint32_t ofs
)
4959 return (ofs
& ((1 << 14) - 1)) << 5;
4962 /* Encode the 16-bit imm field of svc/hvc/smc. */
4963 static inline uint32_t
4964 encode_svc_imm (uint32_t imm
)
4969 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4970 static inline uint32_t
4971 reencode_addsub_switch_add_sub (uint32_t opcode
)
4973 return opcode
^ (1 << 30);
4976 static inline uint32_t
4977 reencode_movzn_to_movz (uint32_t opcode
)
4979 return opcode
| (1 << 30);
4982 static inline uint32_t
4983 reencode_movzn_to_movn (uint32_t opcode
)
4985 return opcode
& ~(1 << 30);
4988 /* Overall per-instruction processing. */
4990 /* We need to be able to fix up arbitrary expressions in some statements.
4991 This is so that we can handle symbols that are an arbitrary distance from
4992 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4993 which returns part of an address in a form which will be valid for
4994 a data instruction. We do this by pushing the expression into a symbol
4995 in the expr_section, and creating a fix for that. */
4998 fix_new_aarch64 (fragS
* frag
,
5013 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5017 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5024 /* Diagnostics on operands errors. */
5026 /* By default, output verbose error message.
5027 Disable the verbose error message by -mno-verbose-error. */
5028 static int verbose_error_p
= 1;
5030 #ifdef DEBUG_AARCH64
5031 /* N.B. this is only for the purpose of debugging. */
5032 const char* operand_mismatch_kind_names
[] =
5035 "AARCH64_OPDE_RECOVERABLE",
5036 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5037 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5038 "AARCH64_OPDE_SYNTAX_ERROR",
5039 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5040 "AARCH64_OPDE_INVALID_VARIANT",
5041 "AARCH64_OPDE_OUT_OF_RANGE",
5042 "AARCH64_OPDE_UNALIGNED",
5043 "AARCH64_OPDE_REG_LIST",
5044 "AARCH64_OPDE_OTHER_ERROR",
5046 #endif /* DEBUG_AARCH64 */
5048 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5050 When multiple errors of different kinds are found in the same assembly
5051 line, only the error of the highest severity will be picked up for
5052 issuing the diagnostics. */
5055 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5056 enum aarch64_operand_error_kind rhs
)
5058 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5059 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5060 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5061 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5062 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5063 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5064 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5065 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5066 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5067 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5068 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5072 /* Helper routine to get the mnemonic name from the assembly instruction
5073 line; should only be called for the diagnosis purpose, as there is
5074 string copy operation involved, which may affect the runtime
5075 performance if used in elsewhere. */
5078 get_mnemonic_name (const char *str
)
5080 static char mnemonic
[32];
5083 /* Get the first 15 bytes and assume that the full name is included. */
5084 strncpy (mnemonic
, str
, 31);
5085 mnemonic
[31] = '\0';
5087 /* Scan up to the end of the mnemonic, which must end in white space,
5088 '.', or end of string. */
5089 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5094 /* Append '...' to the truncated long name. */
5095 if (ptr
- mnemonic
== 31)
5096 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5102 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5104 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5105 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5108 /* Data structures storing one user error in the assembly code related to
5111 struct operand_error_record
5113 const aarch64_opcode
*opcode
;
5114 aarch64_operand_error detail
;
5115 struct operand_error_record
*next
;
5118 typedef struct operand_error_record operand_error_record
;
5120 struct operand_errors
5122 operand_error_record
*head
;
5123 operand_error_record
*tail
;
5126 typedef struct operand_errors operand_errors
;
5128 /* Top-level data structure reporting user errors for the current line of
5130 The way md_assemble works is that all opcodes sharing the same mnemonic
5131 name are iterated to find a match to the assembly line. In this data
5132 structure, each of the such opcodes will have one operand_error_record
5133 allocated and inserted. In other words, excessive errors related with
5134 a single opcode are disregarded. */
5135 operand_errors operand_error_report
;
5137 /* Free record nodes. */
5138 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5140 /* Initialize the data structure that stores the operand mismatch
5141 information on assembling one line of the assembly code. */
5143 init_operand_error_report (void)
5145 if (operand_error_report
.head
!= NULL
)
5147 gas_assert (operand_error_report
.tail
!= NULL
);
5148 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5149 free_opnd_error_record_nodes
= operand_error_report
.head
;
5150 operand_error_report
.head
= NULL
;
5151 operand_error_report
.tail
= NULL
;
5154 gas_assert (operand_error_report
.tail
== NULL
);
5157 /* Return TRUE if some operand error has been recorded during the
5158 parsing of the current assembly line using the opcode *OPCODE;
5159 otherwise return FALSE. */
5161 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5163 operand_error_record
*record
= operand_error_report
.head
;
5164 return record
&& record
->opcode
== opcode
;
5167 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5168 OPCODE field is initialized with OPCODE.
5169 N.B. only one record for each opcode, i.e. the maximum of one error is
5170 recorded for each instruction template. */
5173 add_operand_error_record (const operand_error_record
* new_record
)
5175 const aarch64_opcode
*opcode
= new_record
->opcode
;
5176 operand_error_record
* record
= operand_error_report
.head
;
5178 /* The record may have been created for this opcode. If not, we need
5180 if (! opcode_has_operand_error_p (opcode
))
5182 /* Get one empty record. */
5183 if (free_opnd_error_record_nodes
== NULL
)
5185 record
= XNEW (operand_error_record
);
5189 record
= free_opnd_error_record_nodes
;
5190 free_opnd_error_record_nodes
= record
->next
;
5192 record
->opcode
= opcode
;
5193 /* Insert at the head. */
5194 record
->next
= operand_error_report
.head
;
5195 operand_error_report
.head
= record
;
5196 if (operand_error_report
.tail
== NULL
)
5197 operand_error_report
.tail
= record
;
5199 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5200 && record
->detail
.index
<= new_record
->detail
.index
5201 && operand_error_higher_severity_p (record
->detail
.kind
,
5202 new_record
->detail
.kind
))
5204 /* In the case of multiple errors found on operands related with a
5205 single opcode, only record the error of the leftmost operand and
5206 only if the error is of higher severity. */
5207 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5208 " the existing error %s on operand %d",
5209 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5210 new_record
->detail
.index
,
5211 operand_mismatch_kind_names
[record
->detail
.kind
],
5212 record
->detail
.index
);
5216 record
->detail
= new_record
->detail
;
5220 record_operand_error_info (const aarch64_opcode
*opcode
,
5221 aarch64_operand_error
*error_info
)
5223 operand_error_record record
;
5224 record
.opcode
= opcode
;
5225 record
.detail
= *error_info
;
5226 add_operand_error_record (&record
);
5229 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5230 error message *ERROR, for operand IDX (count from 0). */
5233 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5234 enum aarch64_operand_error_kind kind
,
5237 aarch64_operand_error info
;
5238 memset(&info
, 0, sizeof (info
));
5242 info
.non_fatal
= false;
5243 record_operand_error_info (opcode
, &info
);
5247 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5248 enum aarch64_operand_error_kind kind
,
5249 const char* error
, const int *extra_data
)
5251 aarch64_operand_error info
;
5255 info
.data
[0].i
= extra_data
[0];
5256 info
.data
[1].i
= extra_data
[1];
5257 info
.data
[2].i
= extra_data
[2];
5258 info
.non_fatal
= false;
5259 record_operand_error_info (opcode
, &info
);
5263 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5264 const char* error
, int lower_bound
,
5267 int data
[3] = {lower_bound
, upper_bound
, 0};
5268 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5272 /* Remove the operand error record for *OPCODE. */
5273 static void ATTRIBUTE_UNUSED
5274 remove_operand_error_record (const aarch64_opcode
*opcode
)
5276 if (opcode_has_operand_error_p (opcode
))
5278 operand_error_record
* record
= operand_error_report
.head
;
5279 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5280 operand_error_report
.head
= record
->next
;
5281 record
->next
= free_opnd_error_record_nodes
;
5282 free_opnd_error_record_nodes
= record
;
5283 if (operand_error_report
.head
== NULL
)
5285 gas_assert (operand_error_report
.tail
== record
);
5286 operand_error_report
.tail
= NULL
;
5291 /* Given the instruction in *INSTR, return the index of the best matched
5292 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5294 Return -1 if there is no qualifier sequence; return the first match
5295 if there is multiple matches found. */
5298 find_best_match (const aarch64_inst
*instr
,
5299 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5301 int i
, num_opnds
, max_num_matched
, idx
;
5303 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5306 DEBUG_TRACE ("no operand");
5310 max_num_matched
= 0;
5313 /* For each pattern. */
5314 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5317 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5319 /* Most opcodes has much fewer patterns in the list. */
5320 if (empty_qualifier_sequence_p (qualifiers
))
5322 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5326 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5327 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5330 if (num_matched
> max_num_matched
)
5332 max_num_matched
= num_matched
;
5337 DEBUG_TRACE ("return with %d", idx
);
5341 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5342 corresponding operands in *INSTR. */
5345 assign_qualifier_sequence (aarch64_inst
*instr
,
5346 const aarch64_opnd_qualifier_t
*qualifiers
)
5349 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5350 gas_assert (num_opnds
);
5351 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5352 instr
->operands
[i
].qualifier
= *qualifiers
;
5355 /* Callback used by aarch64_print_operand to apply STYLE to the
5356 disassembler output created from FMT and ARGS. The STYLER object holds
5357 any required state. Must return a pointer to a string (created from FMT
5358 and ARGS) that will continue to be valid until the complete disassembled
5359 instruction has been printed.
5361 We don't currently add any styling to the output of the disassembler as
5362 used within assembler error messages, and so STYLE is ignored here. A
5363 new string is allocated on the obstack help within STYLER and returned
5366 static const char *aarch64_apply_style
5367 (struct aarch64_styler
*styler
,
5368 enum disassembler_style style ATTRIBUTE_UNUSED
,
5369 const char *fmt
, va_list args
)
5373 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5376 /* Calculate the required space. */
5378 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5380 gas_assert (res
>= 0);
5382 /* Allocate space on the obstack and format the result. */
5383 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5384 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5385 gas_assert (res
>= 0);
5390 /* Print operands for the diagnosis purpose. */
5393 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5394 const aarch64_opnd_info
*opnds
)
5397 struct aarch64_styler styler
;
5398 struct obstack content
;
5399 obstack_init (&content
);
5401 styler
.apply_style
= aarch64_apply_style
;
5402 styler
.state
= (void *) &content
;
5404 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5409 /* We regard the opcode operand info more, however we also look into
5410 the inst->operands to support the disassembling of the optional
5412 The two operand code should be the same in all cases, apart from
5413 when the operand can be optional. */
5414 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5415 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5418 /* Generate the operand string in STR. */
5419 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5420 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5424 strcat (buf
, i
== 0 ? " " : ", ");
5426 /* Append the operand string. */
5429 /* Append a comment. This works because only the last operand ever
5430 adds a comment. If that ever changes then we'll need to be
5434 strcat (buf
, "\t// ");
5439 obstack_free (&content
, NULL
);
5442 /* Send to stderr a string as information. */
5445 output_info (const char *format
, ...)
5451 file
= as_where (&line
);
5455 fprintf (stderr
, "%s:%u: ", file
, line
);
5457 fprintf (stderr
, "%s: ", file
);
5459 fprintf (stderr
, _("Info: "));
5460 va_start (args
, format
);
5461 vfprintf (stderr
, format
, args
);
5463 (void) putc ('\n', stderr
);
5466 /* Output one operand error record. */
5469 output_operand_error_record (const operand_error_record
*record
, char *str
)
5471 const aarch64_operand_error
*detail
= &record
->detail
;
5472 int idx
= detail
->index
;
5473 const aarch64_opcode
*opcode
= record
->opcode
;
5474 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5475 : AARCH64_OPND_NIL
);
5477 typedef void (*handler_t
)(const char *format
, ...);
5478 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5480 switch (detail
->kind
)
5482 case AARCH64_OPDE_NIL
:
5486 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5487 handler (_("this `%s' should have an immediately preceding `%s'"
5489 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5492 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5493 handler (_("the preceding `%s' should be followed by `%s` rather"
5494 " than `%s` -- `%s'"),
5495 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5498 case AARCH64_OPDE_SYNTAX_ERROR
:
5499 case AARCH64_OPDE_RECOVERABLE
:
5500 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5501 case AARCH64_OPDE_OTHER_ERROR
:
5502 /* Use the prepared error message if there is, otherwise use the
5503 operand description string to describe the error. */
5504 if (detail
->error
!= NULL
)
5507 handler (_("%s -- `%s'"), detail
->error
, str
);
5509 handler (_("%s at operand %d -- `%s'"),
5510 detail
->error
, idx
+ 1, str
);
5514 gas_assert (idx
>= 0);
5515 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5516 aarch64_get_operand_desc (opd_code
), str
);
5520 case AARCH64_OPDE_INVALID_VARIANT
:
5521 handler (_("operand mismatch -- `%s'"), str
);
5522 if (verbose_error_p
)
5524 /* We will try to correct the erroneous instruction and also provide
5525 more information e.g. all other valid variants.
5527 The string representation of the corrected instruction and other
5528 valid variants are generated by
5530 1) obtaining the intermediate representation of the erroneous
5532 2) manipulating the IR, e.g. replacing the operand qualifier;
5533 3) printing out the instruction by calling the printer functions
5534 shared with the disassembler.
5536 The limitation of this method is that the exact input assembly
5537 line cannot be accurately reproduced in some cases, for example an
5538 optional operand present in the actual assembly line will be
5539 omitted in the output; likewise for the optional syntax rules,
5540 e.g. the # before the immediate. Another limitation is that the
5541 assembly symbols and relocation operations in the assembly line
5542 currently cannot be printed out in the error report. Last but not
5543 least, when there is other error(s) co-exist with this error, the
5544 'corrected' instruction may be still incorrect, e.g. given
5545 'ldnp h0,h1,[x0,#6]!'
5546 this diagnosis will provide the version:
5547 'ldnp s0,s1,[x0,#6]!'
5548 which is still not right. */
5549 size_t len
= strlen (get_mnemonic_name (str
));
5553 aarch64_inst
*inst_base
= &inst
.base
;
5554 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5557 reset_aarch64_instruction (&inst
);
5558 inst_base
->opcode
= opcode
;
5560 /* Reset the error report so that there is no side effect on the
5561 following operand parsing. */
5562 init_operand_error_report ();
5565 result
= parse_operands (str
+ len
, opcode
)
5566 && programmer_friendly_fixup (&inst
);
5567 gas_assert (result
);
5568 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5569 NULL
, NULL
, insn_sequence
);
5570 gas_assert (!result
);
5572 /* Find the most matched qualifier sequence. */
5573 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5574 gas_assert (qlf_idx
> -1);
5576 /* Assign the qualifiers. */
5577 assign_qualifier_sequence (inst_base
,
5578 opcode
->qualifiers_list
[qlf_idx
]);
5580 /* Print the hint. */
5581 output_info (_(" did you mean this?"));
5582 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5583 print_operands (buf
, opcode
, inst_base
->operands
);
5584 output_info (_(" %s"), buf
);
5586 /* Print out other variant(s) if there is any. */
5588 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5589 output_info (_(" other valid variant(s):"));
5591 /* For each pattern. */
5592 qualifiers_list
= opcode
->qualifiers_list
;
5593 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5595 /* Most opcodes has much fewer patterns in the list.
5596 First NIL qualifier indicates the end in the list. */
5597 if (empty_qualifier_sequence_p (*qualifiers_list
))
5602 /* Mnemonics name. */
5603 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5605 /* Assign the qualifiers. */
5606 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5608 /* Print instruction. */
5609 print_operands (buf
, opcode
, inst_base
->operands
);
5611 output_info (_(" %s"), buf
);
5617 case AARCH64_OPDE_UNTIED_IMMS
:
5618 handler (_("operand %d must have the same immediate value "
5619 "as operand 1 -- `%s'"),
5620 detail
->index
+ 1, str
);
5623 case AARCH64_OPDE_UNTIED_OPERAND
:
5624 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5625 detail
->index
+ 1, str
);
5628 case AARCH64_OPDE_OUT_OF_RANGE
:
5629 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5630 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5631 detail
->error
? detail
->error
: _("immediate value"),
5632 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5634 handler (_("%s must be %d at operand %d -- `%s'"),
5635 detail
->error
? detail
->error
: _("immediate value"),
5636 detail
->data
[0].i
, idx
+ 1, str
);
5639 case AARCH64_OPDE_REG_LIST
:
5640 if (detail
->data
[0].i
== 1)
5641 handler (_("invalid number of registers in the list; "
5642 "only 1 register is expected at operand %d -- `%s'"),
5645 handler (_("invalid number of registers in the list; "
5646 "%d registers are expected at operand %d -- `%s'"),
5647 detail
->data
[0].i
, idx
+ 1, str
);
5650 case AARCH64_OPDE_UNALIGNED
:
5651 handler (_("immediate value must be a multiple of "
5652 "%d at operand %d -- `%s'"),
5653 detail
->data
[0].i
, idx
+ 1, str
);
5662 /* Process and output the error message about the operand mismatching.
5664 When this function is called, the operand error information had
5665 been collected for an assembly line and there will be multiple
5666 errors in the case of multiple instruction templates; output the
5667 error message that most closely describes the problem.
5669 The errors to be printed can be filtered on printing all errors
5670 or only non-fatal errors. This distinction has to be made because
5671 the error buffer may already be filled with fatal errors we don't want to
5672 print due to the different instruction templates. */
5675 output_operand_error_report (char *str
, bool non_fatal_only
)
5677 int largest_error_pos
;
5678 const char *msg
= NULL
;
5679 enum aarch64_operand_error_kind kind
;
5680 operand_error_record
*curr
;
5681 operand_error_record
*head
= operand_error_report
.head
;
5682 operand_error_record
*record
= NULL
;
5684 /* No error to report. */
5688 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5690 /* Only one error. */
5691 if (head
== operand_error_report
.tail
)
5693 /* If the only error is a non-fatal one and we don't want to print it,
5695 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5697 DEBUG_TRACE ("single opcode entry with error kind: %s",
5698 operand_mismatch_kind_names
[head
->detail
.kind
]);
5699 output_operand_error_record (head
, str
);
5704 /* Find the error kind of the highest severity. */
5705 DEBUG_TRACE ("multiple opcode entries with error kind");
5706 kind
= AARCH64_OPDE_NIL
;
5707 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5709 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5710 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5711 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5712 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5713 kind
= curr
->detail
.kind
;
5716 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5718 /* Pick up one of errors of KIND to report. */
5719 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5720 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5722 /* If we don't want to print non-fatal errors then don't consider them
5724 if (curr
->detail
.kind
!= kind
5725 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5727 /* If there are multiple errors, pick up the one with the highest
5728 mismatching operand index. In the case of multiple errors with
5729 the equally highest operand index, pick up the first one or the
5730 first one with non-NULL error message. */
5731 if (curr
->detail
.index
> largest_error_pos
5732 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5733 && curr
->detail
.error
!= NULL
))
5735 largest_error_pos
= curr
->detail
.index
;
5737 msg
= record
->detail
.error
;
5741 /* The way errors are collected in the back-end is a bit non-intuitive. But
5742 essentially, because each operand template is tried recursively you may
5743 always have errors collected from the previous tried OPND. These are
5744 usually skipped if there is one successful match. However now with the
5745 non-fatal errors we have to ignore those previously collected hard errors
5746 when we're only interested in printing the non-fatal ones. This condition
5747 prevents us from printing errors that are not appropriate, since we did
5748 match a condition, but it also has warnings that it wants to print. */
5749 if (non_fatal_only
&& !record
)
5752 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5753 DEBUG_TRACE ("Pick up error kind %s to report",
5754 operand_mismatch_kind_names
[record
->detail
.kind
]);
5757 output_operand_error_record (record
, str
);
5760 /* Write an AARCH64 instruction to buf - always little-endian. */
5762 put_aarch64_insn (char *buf
, uint32_t insn
)
5764 unsigned char *where
= (unsigned char *) buf
;
5766 where
[1] = insn
>> 8;
5767 where
[2] = insn
>> 16;
5768 where
[3] = insn
>> 24;
5772 get_aarch64_insn (char *buf
)
5774 unsigned char *where
= (unsigned char *) buf
;
5776 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5777 | ((uint32_t) where
[3] << 24)));
5782 output_inst (struct aarch64_inst
*new_inst
)
5786 to
= frag_more (INSN_SIZE
);
5788 frag_now
->tc_frag_data
.recorded
= 1;
5790 put_aarch64_insn (to
, inst
.base
.value
);
5792 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5794 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5795 INSN_SIZE
, &inst
.reloc
.exp
,
5798 DEBUG_TRACE ("Prepared relocation fix up");
5799 /* Don't check the addend value against the instruction size,
5800 that's the job of our code in md_apply_fix(). */
5801 fixp
->fx_no_overflow
= 1;
5802 if (new_inst
!= NULL
)
5803 fixp
->tc_fix_data
.inst
= new_inst
;
5804 if (aarch64_gas_internal_fixup_p ())
5806 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5807 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5808 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5812 dwarf2_emit_insn (INSN_SIZE
);
5815 /* Link together opcodes of the same name. */
5819 const aarch64_opcode
*opcode
;
5820 struct templates
*next
;
5823 typedef struct templates templates
;
5826 lookup_mnemonic (const char *start
, int len
)
5828 templates
*templ
= NULL
;
5830 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5834 /* Subroutine of md_assemble, responsible for looking up the primary
5835 opcode from the mnemonic the user wrote. BASE points to the beginning
5836 of the mnemonic, DOT points to the first '.' within the mnemonic
5837 (if any) and END points to the end of the mnemonic. */
5840 opcode_lookup (char *base
, char *dot
, char *end
)
5842 const aarch64_cond
*cond
;
5849 inst
.cond
= COND_ALWAYS
;
5851 /* Handle a possible condition. */
5854 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5857 inst
.cond
= cond
->value
;
5863 if (inst
.cond
== COND_ALWAYS
)
5865 /* Look for unaffixed mnemonic. */
5866 return lookup_mnemonic (base
, len
);
5870 /* append ".c" to mnemonic if conditional */
5871 memcpy (condname
, base
, len
);
5872 memcpy (condname
+ len
, ".c", 2);
5875 return lookup_mnemonic (base
, len
);
5881 /* Process an optional operand that is found omitted from the assembly line.
5882 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5883 instruction's opcode entry while IDX is the index of this omitted operand.
5887 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5888 int idx
, aarch64_opnd_info
*operand
)
5890 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5891 gas_assert (optional_operand_p (opcode
, idx
));
5892 gas_assert (!operand
->present
);
5896 case AARCH64_OPND_Rd
:
5897 case AARCH64_OPND_Rn
:
5898 case AARCH64_OPND_Rm
:
5899 case AARCH64_OPND_Rt
:
5900 case AARCH64_OPND_Rt2
:
5901 case AARCH64_OPND_Rt_LS64
:
5902 case AARCH64_OPND_Rt_SP
:
5903 case AARCH64_OPND_Rs
:
5904 case AARCH64_OPND_Ra
:
5905 case AARCH64_OPND_Rt_SYS
:
5906 case AARCH64_OPND_Rd_SP
:
5907 case AARCH64_OPND_Rn_SP
:
5908 case AARCH64_OPND_Rm_SP
:
5909 case AARCH64_OPND_Fd
:
5910 case AARCH64_OPND_Fn
:
5911 case AARCH64_OPND_Fm
:
5912 case AARCH64_OPND_Fa
:
5913 case AARCH64_OPND_Ft
:
5914 case AARCH64_OPND_Ft2
:
5915 case AARCH64_OPND_Sd
:
5916 case AARCH64_OPND_Sn
:
5917 case AARCH64_OPND_Sm
:
5918 case AARCH64_OPND_Va
:
5919 case AARCH64_OPND_Vd
:
5920 case AARCH64_OPND_Vn
:
5921 case AARCH64_OPND_Vm
:
5922 case AARCH64_OPND_VdD1
:
5923 case AARCH64_OPND_VnD1
:
5924 operand
->reg
.regno
= default_value
;
5927 case AARCH64_OPND_Ed
:
5928 case AARCH64_OPND_En
:
5929 case AARCH64_OPND_Em
:
5930 case AARCH64_OPND_Em16
:
5931 case AARCH64_OPND_SM3_IMM2
:
5932 operand
->reglane
.regno
= default_value
;
5935 case AARCH64_OPND_IDX
:
5936 case AARCH64_OPND_BIT_NUM
:
5937 case AARCH64_OPND_IMMR
:
5938 case AARCH64_OPND_IMMS
:
5939 case AARCH64_OPND_SHLL_IMM
:
5940 case AARCH64_OPND_IMM_VLSL
:
5941 case AARCH64_OPND_IMM_VLSR
:
5942 case AARCH64_OPND_CCMP_IMM
:
5943 case AARCH64_OPND_FBITS
:
5944 case AARCH64_OPND_UIMM4
:
5945 case AARCH64_OPND_UIMM3_OP1
:
5946 case AARCH64_OPND_UIMM3_OP2
:
5947 case AARCH64_OPND_IMM
:
5948 case AARCH64_OPND_IMM_2
:
5949 case AARCH64_OPND_WIDTH
:
5950 case AARCH64_OPND_UIMM7
:
5951 case AARCH64_OPND_NZCV
:
5952 case AARCH64_OPND_SVE_PATTERN
:
5953 case AARCH64_OPND_SVE_PRFOP
:
5954 operand
->imm
.value
= default_value
;
5957 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5958 operand
->imm
.value
= default_value
;
5959 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5960 operand
->shifter
.amount
= 1;
5963 case AARCH64_OPND_EXCEPTION
:
5964 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5967 case AARCH64_OPND_BARRIER_ISB
:
5968 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5971 case AARCH64_OPND_BTI_TARGET
:
5972 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5980 /* Process the relocation type for move wide instructions.
5981 Return TRUE on success; otherwise return FALSE. */
5984 process_movw_reloc_info (void)
5989 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5991 if (inst
.base
.opcode
->op
== OP_MOVK
)
5992 switch (inst
.reloc
.type
)
5994 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5995 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5996 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5997 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5998 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5999 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6000 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6001 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6002 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6003 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6004 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6006 (_("the specified relocation type is not allowed for MOVK"));
6012 switch (inst
.reloc
.type
)
6014 case BFD_RELOC_AARCH64_MOVW_G0
:
6015 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6016 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6017 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6018 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6019 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6020 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6021 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6022 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6023 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6024 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6025 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6026 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6029 case BFD_RELOC_AARCH64_MOVW_G1
:
6030 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6031 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6032 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6033 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6034 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6035 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6036 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6037 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6038 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6039 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6040 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6041 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6044 case BFD_RELOC_AARCH64_MOVW_G2
:
6045 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6046 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6047 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6048 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6049 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6050 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6053 set_fatal_syntax_error
6054 (_("the specified relocation type is not allowed for 32-bit "
6060 case BFD_RELOC_AARCH64_MOVW_G3
:
6061 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6064 set_fatal_syntax_error
6065 (_("the specified relocation type is not allowed for 32-bit "
6072 /* More cases should be added when more MOVW-related relocation types
6073 are supported in GAS. */
6074 gas_assert (aarch64_gas_internal_fixup_p ());
6075 /* The shift amount should have already been set by the parser. */
6078 inst
.base
.operands
[1].shifter
.amount
= shift
;
6082 /* A primitive log calculator. */
6084 static inline unsigned int
6085 get_logsz (unsigned int size
)
6087 const unsigned char ls
[16] =
6088 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6094 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6095 return ls
[size
- 1];
6098 /* Determine and return the real reloc type code for an instruction
6099 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6101 static inline bfd_reloc_code_real_type
6102 ldst_lo12_determine_real_reloc_type (void)
6104 unsigned logsz
, max_logsz
;
6105 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6106 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6108 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6110 BFD_RELOC_AARCH64_LDST8_LO12
,
6111 BFD_RELOC_AARCH64_LDST16_LO12
,
6112 BFD_RELOC_AARCH64_LDST32_LO12
,
6113 BFD_RELOC_AARCH64_LDST64_LO12
,
6114 BFD_RELOC_AARCH64_LDST128_LO12
6117 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6118 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6119 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6120 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6121 BFD_RELOC_AARCH64_NONE
6124 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6125 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6126 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6127 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6128 BFD_RELOC_AARCH64_NONE
6131 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6132 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6133 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6134 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6135 BFD_RELOC_AARCH64_NONE
6138 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6139 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6140 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6141 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6142 BFD_RELOC_AARCH64_NONE
6146 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6147 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6149 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6151 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6153 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6154 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6156 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6158 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6160 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6162 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6164 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6165 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6166 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6167 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6172 if (logsz
> max_logsz
)
6174 /* SEE PR 27904 for an example of this. */
6175 set_fatal_syntax_error
6176 (_("relocation qualifier does not match instruction size"));
6177 return BFD_RELOC_AARCH64_NONE
;
6180 /* In reloc.c, these pseudo relocation types should be defined in similar
6181 order as above reloc_ldst_lo12 array. Because the array index calculation
6182 below relies on this. */
6183 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6186 /* Check whether a register list REGINFO is valid. The registers must be
6187 numbered in increasing order (modulo 32), in increments of one or two.
6189 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6192 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6195 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6197 uint32_t i
, nb_regs
, prev_regno
, incr
;
6199 nb_regs
= 1 + (reginfo
& 0x3);
6201 prev_regno
= reginfo
& 0x1f;
6202 incr
= accept_alternate
? 2 : 1;
6204 for (i
= 1; i
< nb_regs
; ++i
)
6206 uint32_t curr_regno
;
6208 curr_regno
= reginfo
& 0x1f;
6209 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6211 prev_regno
= curr_regno
;
6217 /* Generic instruction operand parser. This does no encoding and no
6218 semantic validation; it merely squirrels values away in the inst
6219 structure. Returns TRUE or FALSE depending on whether the
6220 specified grammar matched. */
6223 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6226 char *backtrack_pos
= 0;
6227 const enum aarch64_opnd
*operands
= opcode
->operands
;
6228 aarch64_reg_type imm_reg_type
;
6231 skip_whitespace (str
);
6233 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6235 | AARCH64_FEATURE_SVE2
))
6236 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6238 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6240 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6243 const reg_entry
*reg
;
6244 int comma_skipped_p
= 0;
6245 struct vector_type_el vectype
;
6246 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6247 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6248 aarch64_reg_type reg_type
;
6250 DEBUG_TRACE ("parse operand %d", i
);
6252 /* Assign the operand code. */
6253 info
->type
= operands
[i
];
6255 if (optional_operand_p (opcode
, i
))
6257 /* Remember where we are in case we need to backtrack. */
6258 gas_assert (!backtrack_pos
);
6259 backtrack_pos
= str
;
6262 /* Expect comma between operands; the backtrack mechanism will take
6263 care of cases of omitted optional operand. */
6264 if (i
> 0 && ! skip_past_char (&str
, ','))
6266 set_syntax_error (_("comma expected between operands"));
6270 comma_skipped_p
= 1;
6272 switch (operands
[i
])
6274 case AARCH64_OPND_Rd
:
6275 case AARCH64_OPND_Rn
:
6276 case AARCH64_OPND_Rm
:
6277 case AARCH64_OPND_Rt
:
6278 case AARCH64_OPND_Rt2
:
6279 case AARCH64_OPND_Rs
:
6280 case AARCH64_OPND_Ra
:
6281 case AARCH64_OPND_Rt_LS64
:
6282 case AARCH64_OPND_Rt_SYS
:
6283 case AARCH64_OPND_PAIRREG
:
6284 case AARCH64_OPND_SVE_Rm
:
6285 po_int_reg_or_fail (REG_TYPE_R_Z
);
6287 /* In LS64 load/store instructions Rt register number must be even
6289 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6291 /* We've already checked if this is valid register.
6292 This will check if register number (Rt) is not undefined for LS64
6294 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6295 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6297 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6303 case AARCH64_OPND_Rd_SP
:
6304 case AARCH64_OPND_Rn_SP
:
6305 case AARCH64_OPND_Rt_SP
:
6306 case AARCH64_OPND_SVE_Rn_SP
:
6307 case AARCH64_OPND_Rm_SP
:
6308 po_int_reg_or_fail (REG_TYPE_R_SP
);
6311 case AARCH64_OPND_Rm_EXT
:
6312 case AARCH64_OPND_Rm_SFT
:
6313 po_misc_or_fail (parse_shifter_operand
6314 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6316 : SHIFTED_LOGIC_IMM
)));
6317 if (!info
->shifter
.operator_present
)
6319 /* Default to LSL if not present. Libopcodes prefers shifter
6320 kind to be explicit. */
6321 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6322 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6323 /* For Rm_EXT, libopcodes will carry out further check on whether
6324 or not stack pointer is used in the instruction (Recall that
6325 "the extend operator is not optional unless at least one of
6326 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6330 case AARCH64_OPND_Fd
:
6331 case AARCH64_OPND_Fn
:
6332 case AARCH64_OPND_Fm
:
6333 case AARCH64_OPND_Fa
:
6334 case AARCH64_OPND_Ft
:
6335 case AARCH64_OPND_Ft2
:
6336 case AARCH64_OPND_Sd
:
6337 case AARCH64_OPND_Sn
:
6338 case AARCH64_OPND_Sm
:
6339 case AARCH64_OPND_SVE_VZn
:
6340 case AARCH64_OPND_SVE_Vd
:
6341 case AARCH64_OPND_SVE_Vm
:
6342 case AARCH64_OPND_SVE_Vn
:
6343 reg
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, NULL
);
6346 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6349 gas_assert (reg
->type
>= REG_TYPE_FP_B
6350 && reg
->type
<= REG_TYPE_FP_Q
);
6352 info
->reg
.regno
= reg
->number
;
6353 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
6356 case AARCH64_OPND_SVE_Pd
:
6357 case AARCH64_OPND_SVE_Pg3
:
6358 case AARCH64_OPND_SVE_Pg4_5
:
6359 case AARCH64_OPND_SVE_Pg4_10
:
6360 case AARCH64_OPND_SVE_Pg4_16
:
6361 case AARCH64_OPND_SVE_Pm
:
6362 case AARCH64_OPND_SVE_Pn
:
6363 case AARCH64_OPND_SVE_Pt
:
6364 case AARCH64_OPND_SME_Pm
:
6365 reg_type
= REG_TYPE_PN
;
6368 case AARCH64_OPND_SVE_Za_5
:
6369 case AARCH64_OPND_SVE_Za_16
:
6370 case AARCH64_OPND_SVE_Zd
:
6371 case AARCH64_OPND_SVE_Zm_5
:
6372 case AARCH64_OPND_SVE_Zm_16
:
6373 case AARCH64_OPND_SVE_Zn
:
6374 case AARCH64_OPND_SVE_Zt
:
6375 reg_type
= REG_TYPE_ZN
;
6378 case AARCH64_OPND_Va
:
6379 case AARCH64_OPND_Vd
:
6380 case AARCH64_OPND_Vn
:
6381 case AARCH64_OPND_Vm
:
6382 reg_type
= REG_TYPE_VN
;
6384 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6387 first_error (_(get_reg_expected_msg (reg_type
)));
6390 if (vectype
.defined
& NTA_HASINDEX
)
6393 info
->reg
.regno
= reg
->number
;
6394 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6395 && vectype
.type
== NT_invtype
)
6396 /* Unqualified Pn and Zn registers are allowed in certain
6397 contexts. Rely on F_STRICT qualifier checking to catch
6399 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6402 info
->qualifier
= vectype_to_qualifier (&vectype
);
6403 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6408 case AARCH64_OPND_VdD1
:
6409 case AARCH64_OPND_VnD1
:
6410 reg
= aarch64_reg_parse (&str
, REG_TYPE_VN
, &vectype
);
6413 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6416 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6418 set_fatal_syntax_error
6419 (_("the top half of a 128-bit FP/SIMD register is expected"));
6422 info
->reg
.regno
= reg
->number
;
6423 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6424 here; it is correct for the purpose of encoding/decoding since
6425 only the register number is explicitly encoded in the related
6426 instructions, although this appears a bit hacky. */
6427 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6430 case AARCH64_OPND_SVE_Zm3_INDEX
:
6431 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6432 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6433 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6434 case AARCH64_OPND_SVE_Zm4_INDEX
:
6435 case AARCH64_OPND_SVE_Zn_INDEX
:
6436 reg_type
= REG_TYPE_ZN
;
6437 goto vector_reg_index
;
6439 case AARCH64_OPND_Ed
:
6440 case AARCH64_OPND_En
:
6441 case AARCH64_OPND_Em
:
6442 case AARCH64_OPND_Em16
:
6443 case AARCH64_OPND_SM3_IMM2
:
6444 reg_type
= REG_TYPE_VN
;
6446 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6449 first_error (_(get_reg_expected_msg (reg_type
)));
6452 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6455 info
->reglane
.regno
= reg
->number
;
6456 info
->reglane
.index
= vectype
.index
;
6457 info
->qualifier
= vectype_to_qualifier (&vectype
);
6458 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6462 case AARCH64_OPND_SVE_ZnxN
:
6463 case AARCH64_OPND_SVE_ZtxN
:
6464 reg_type
= REG_TYPE_ZN
;
6465 goto vector_reg_list
;
6467 case AARCH64_OPND_LVn
:
6468 case AARCH64_OPND_LVt
:
6469 case AARCH64_OPND_LVt_AL
:
6470 case AARCH64_OPND_LEt
:
6471 reg_type
= REG_TYPE_VN
;
6473 if (reg_type
== REG_TYPE_ZN
6474 && get_opcode_dependent_value (opcode
) == 1
6477 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6480 first_error (_(get_reg_expected_msg (reg_type
)));
6483 info
->reglist
.first_regno
= reg
->number
;
6484 info
->reglist
.num_regs
= 1;
6488 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6489 if (val
== PARSE_FAIL
)
6492 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6494 set_fatal_syntax_error (_("invalid register list"));
6498 if (vectype
.width
!= 0 && *str
!= ',')
6500 set_fatal_syntax_error
6501 (_("expected element type rather than vector type"));
6505 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6506 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6508 if (operands
[i
] == AARCH64_OPND_LEt
)
6510 if (!(vectype
.defined
& NTA_HASINDEX
))
6512 info
->reglist
.has_index
= 1;
6513 info
->reglist
.index
= vectype
.index
;
6517 if (vectype
.defined
& NTA_HASINDEX
)
6519 if (!(vectype
.defined
& NTA_HASTYPE
))
6521 if (reg_type
== REG_TYPE_ZN
)
6522 set_fatal_syntax_error (_("missing type suffix"));
6526 info
->qualifier
= vectype_to_qualifier (&vectype
);
6527 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6531 case AARCH64_OPND_CRn
:
6532 case AARCH64_OPND_CRm
:
6534 char prefix
= *(str
++);
6535 if (prefix
!= 'c' && prefix
!= 'C')
6538 po_imm_nc_or_fail ();
6541 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6544 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6545 info
->imm
.value
= val
;
6549 case AARCH64_OPND_SHLL_IMM
:
6550 case AARCH64_OPND_IMM_VLSR
:
6551 po_imm_or_fail (1, 64);
6552 info
->imm
.value
= val
;
6555 case AARCH64_OPND_CCMP_IMM
:
6556 case AARCH64_OPND_SIMM5
:
6557 case AARCH64_OPND_FBITS
:
6558 case AARCH64_OPND_TME_UIMM16
:
6559 case AARCH64_OPND_UIMM4
:
6560 case AARCH64_OPND_UIMM4_ADDG
:
6561 case AARCH64_OPND_UIMM10
:
6562 case AARCH64_OPND_UIMM3_OP1
:
6563 case AARCH64_OPND_UIMM3_OP2
:
6564 case AARCH64_OPND_IMM_VLSL
:
6565 case AARCH64_OPND_IMM
:
6566 case AARCH64_OPND_IMM_2
:
6567 case AARCH64_OPND_WIDTH
:
6568 case AARCH64_OPND_SVE_INV_LIMM
:
6569 case AARCH64_OPND_SVE_LIMM
:
6570 case AARCH64_OPND_SVE_LIMM_MOV
:
6571 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6572 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6573 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6574 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6575 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6576 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6577 case AARCH64_OPND_SVE_SIMM5
:
6578 case AARCH64_OPND_SVE_SIMM5B
:
6579 case AARCH64_OPND_SVE_SIMM6
:
6580 case AARCH64_OPND_SVE_SIMM8
:
6581 case AARCH64_OPND_SVE_UIMM3
:
6582 case AARCH64_OPND_SVE_UIMM7
:
6583 case AARCH64_OPND_SVE_UIMM8
:
6584 case AARCH64_OPND_SVE_UIMM8_53
:
6585 case AARCH64_OPND_IMM_ROT1
:
6586 case AARCH64_OPND_IMM_ROT2
:
6587 case AARCH64_OPND_IMM_ROT3
:
6588 case AARCH64_OPND_SVE_IMM_ROT1
:
6589 case AARCH64_OPND_SVE_IMM_ROT2
:
6590 case AARCH64_OPND_SVE_IMM_ROT3
:
6591 case AARCH64_OPND_CSSC_SIMM8
:
6592 case AARCH64_OPND_CSSC_UIMM8
:
6593 po_imm_nc_or_fail ();
6594 info
->imm
.value
= val
;
6597 case AARCH64_OPND_SVE_AIMM
:
6598 case AARCH64_OPND_SVE_ASIMM
:
6599 po_imm_nc_or_fail ();
6600 info
->imm
.value
= val
;
6601 skip_whitespace (str
);
6602 if (skip_past_comma (&str
))
6603 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6605 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6608 case AARCH64_OPND_SVE_PATTERN
:
6609 po_enum_or_fail (aarch64_sve_pattern_array
);
6610 info
->imm
.value
= val
;
6613 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6614 po_enum_or_fail (aarch64_sve_pattern_array
);
6615 info
->imm
.value
= val
;
6616 if (skip_past_comma (&str
)
6617 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6619 if (!info
->shifter
.operator_present
)
6621 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6622 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6623 info
->shifter
.amount
= 1;
6627 case AARCH64_OPND_SVE_PRFOP
:
6628 po_enum_or_fail (aarch64_sve_prfop_array
);
6629 info
->imm
.value
= val
;
6632 case AARCH64_OPND_UIMM7
:
6633 po_imm_or_fail (0, 127);
6634 info
->imm
.value
= val
;
6637 case AARCH64_OPND_IDX
:
6638 case AARCH64_OPND_MASK
:
6639 case AARCH64_OPND_BIT_NUM
:
6640 case AARCH64_OPND_IMMR
:
6641 case AARCH64_OPND_IMMS
:
6642 po_imm_or_fail (0, 63);
6643 info
->imm
.value
= val
;
6646 case AARCH64_OPND_IMM0
:
6647 po_imm_nc_or_fail ();
6650 set_fatal_syntax_error (_("immediate zero expected"));
6653 info
->imm
.value
= 0;
6656 case AARCH64_OPND_FPIMM0
:
6659 bool res1
= false, res2
= false;
6660 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6661 it is probably not worth the effort to support it. */
6662 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6665 || !(res2
= parse_constant_immediate (&str
, &val
,
6668 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6670 info
->imm
.value
= 0;
6671 info
->imm
.is_fp
= 1;
6674 set_fatal_syntax_error (_("immediate zero expected"));
6678 case AARCH64_OPND_IMM_MOV
:
6681 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6682 reg_name_p (str
, REG_TYPE_VN
))
6685 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6686 GE_OPT_PREFIX
, REJECT_ABSENT
));
6687 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6688 later. fix_mov_imm_insn will try to determine a machine
6689 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6690 message if the immediate cannot be moved by a single
6692 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6693 inst
.base
.operands
[i
].skip
= 1;
6697 case AARCH64_OPND_SIMD_IMM
:
6698 case AARCH64_OPND_SIMD_IMM_SFT
:
6699 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6701 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6703 /* need_libopcodes_p */ 1,
6706 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6707 shift, we don't check it here; we leave the checking to
6708 the libopcodes (operand_general_constraint_met_p). By
6709 doing this, we achieve better diagnostics. */
6710 if (skip_past_comma (&str
)
6711 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6713 if (!info
->shifter
.operator_present
6714 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6716 /* Default to LSL if not present. Libopcodes prefers shifter
6717 kind to be explicit. */
6718 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6719 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6723 case AARCH64_OPND_FPIMM
:
6724 case AARCH64_OPND_SIMD_FPIMM
:
6725 case AARCH64_OPND_SVE_FPIMM8
:
6730 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6731 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6732 || !aarch64_imm_float_p (qfloat
))
6735 set_fatal_syntax_error (_("invalid floating-point"
6739 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6740 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6744 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6745 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6746 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6751 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6752 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6755 set_fatal_syntax_error (_("invalid floating-point"
6759 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6760 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6764 case AARCH64_OPND_LIMM
:
6765 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6766 SHIFTED_LOGIC_IMM
));
6767 if (info
->shifter
.operator_present
)
6769 set_fatal_syntax_error
6770 (_("shift not allowed for bitmask immediate"));
6773 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6775 /* need_libopcodes_p */ 1,
6779 case AARCH64_OPND_AIMM
:
6780 if (opcode
->op
== OP_ADD
)
6781 /* ADD may have relocation types. */
6782 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6783 SHIFTED_ARITH_IMM
));
6785 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6786 SHIFTED_ARITH_IMM
));
6787 switch (inst
.reloc
.type
)
6789 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6790 info
->shifter
.amount
= 12;
6792 case BFD_RELOC_UNUSED
:
6793 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6794 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6795 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6796 inst
.reloc
.pc_rel
= 0;
6801 info
->imm
.value
= 0;
6802 if (!info
->shifter
.operator_present
)
6804 /* Default to LSL if not present. Libopcodes prefers shifter
6805 kind to be explicit. */
6806 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6807 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6811 case AARCH64_OPND_HALF
:
6813 /* #<imm16> or relocation. */
6814 int internal_fixup_p
;
6815 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6816 if (internal_fixup_p
)
6817 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6818 skip_whitespace (str
);
6819 if (skip_past_comma (&str
))
6821 /* {, LSL #<shift>} */
6822 if (! aarch64_gas_internal_fixup_p ())
6824 set_fatal_syntax_error (_("can't mix relocation modifier "
6825 "with explicit shift"));
6828 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6831 inst
.base
.operands
[i
].shifter
.amount
= 0;
6832 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6833 inst
.base
.operands
[i
].imm
.value
= 0;
6834 if (! process_movw_reloc_info ())
6839 case AARCH64_OPND_EXCEPTION
:
6840 case AARCH64_OPND_UNDEFINED
:
6841 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6843 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6845 /* need_libopcodes_p */ 0,
6849 case AARCH64_OPND_NZCV
:
6851 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6855 info
->imm
.value
= nzcv
->value
;
6858 po_imm_or_fail (0, 15);
6859 info
->imm
.value
= val
;
6863 case AARCH64_OPND_COND
:
6864 case AARCH64_OPND_COND1
:
6869 while (ISALPHA (*str
));
6870 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6871 if (info
->cond
== NULL
)
6873 set_syntax_error (_("invalid condition"));
6876 else if (operands
[i
] == AARCH64_OPND_COND1
6877 && (info
->cond
->value
& 0xe) == 0xe)
6879 /* Do not allow AL or NV. */
6880 set_default_error ();
6886 case AARCH64_OPND_ADDR_ADRP
:
6887 po_misc_or_fail (parse_adrp (&str
));
6888 /* Clear the value as operand needs to be relocated. */
6889 info
->imm
.value
= 0;
6892 case AARCH64_OPND_ADDR_PCREL14
:
6893 case AARCH64_OPND_ADDR_PCREL19
:
6894 case AARCH64_OPND_ADDR_PCREL21
:
6895 case AARCH64_OPND_ADDR_PCREL26
:
6896 po_misc_or_fail (parse_address (&str
, info
));
6897 if (!info
->addr
.pcrel
)
6899 set_syntax_error (_("invalid pc-relative address"));
6902 if (inst
.gen_lit_pool
6903 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6905 /* Only permit "=value" in the literal load instructions.
6906 The literal will be generated by programmer_friendly_fixup. */
6907 set_syntax_error (_("invalid use of \"=immediate\""));
6910 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6912 set_syntax_error (_("unrecognized relocation suffix"));
6915 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6917 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6918 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6922 info
->imm
.value
= 0;
6923 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6924 switch (opcode
->iclass
)
6928 /* e.g. CBZ or B.COND */
6929 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6930 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6934 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6935 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6939 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6941 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6942 : BFD_RELOC_AARCH64_JUMP26
;
6945 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6946 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6949 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6950 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6956 inst
.reloc
.pc_rel
= 1;
6960 case AARCH64_OPND_ADDR_SIMPLE
:
6961 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6963 /* [<Xn|SP>{, #<simm>}] */
6965 /* First use the normal address-parsing routines, to get
6966 the usual syntax errors. */
6967 po_misc_or_fail (parse_address (&str
, info
));
6968 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6969 || !info
->addr
.preind
|| info
->addr
.postind
6970 || info
->addr
.writeback
)
6972 set_syntax_error (_("invalid addressing mode"));
6976 /* Then retry, matching the specific syntax of these addresses. */
6978 po_char_or_fail ('[');
6979 po_reg_or_fail (REG_TYPE_R64_SP
);
6980 /* Accept optional ", #0". */
6981 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6982 && skip_past_char (&str
, ','))
6984 skip_past_char (&str
, '#');
6985 if (! skip_past_char (&str
, '0'))
6987 set_fatal_syntax_error
6988 (_("the optional immediate offset can only be 0"));
6992 po_char_or_fail (']');
6996 case AARCH64_OPND_ADDR_REGOFF
:
6997 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6998 po_misc_or_fail (parse_address (&str
, info
));
7000 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7001 || !info
->addr
.preind
|| info
->addr
.postind
7002 || info
->addr
.writeback
)
7004 set_syntax_error (_("invalid addressing mode"));
7007 if (!info
->shifter
.operator_present
)
7009 /* Default to LSL if not present. Libopcodes prefers shifter
7010 kind to be explicit. */
7011 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7012 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7014 /* Qualifier to be deduced by libopcodes. */
7017 case AARCH64_OPND_ADDR_SIMM7
:
7018 po_misc_or_fail (parse_address (&str
, info
));
7019 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7020 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7022 set_syntax_error (_("invalid addressing mode"));
7025 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7027 set_syntax_error (_("relocation not allowed"));
7030 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7032 /* need_libopcodes_p */ 1,
7036 case AARCH64_OPND_ADDR_SIMM9
:
7037 case AARCH64_OPND_ADDR_SIMM9_2
:
7038 case AARCH64_OPND_ADDR_SIMM11
:
7039 case AARCH64_OPND_ADDR_SIMM13
:
7040 po_misc_or_fail (parse_address (&str
, info
));
7041 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7042 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7043 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7044 && info
->addr
.writeback
))
7046 set_syntax_error (_("invalid addressing mode"));
7049 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7051 set_syntax_error (_("relocation not allowed"));
7054 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7056 /* need_libopcodes_p */ 1,
7060 case AARCH64_OPND_ADDR_SIMM10
:
7061 case AARCH64_OPND_ADDR_OFFSET
:
7062 po_misc_or_fail (parse_address (&str
, info
));
7063 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7064 || !info
->addr
.preind
|| info
->addr
.postind
)
7066 set_syntax_error (_("invalid addressing mode"));
7069 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7071 set_syntax_error (_("relocation not allowed"));
7074 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7076 /* need_libopcodes_p */ 1,
7080 case AARCH64_OPND_ADDR_UIMM12
:
7081 po_misc_or_fail (parse_address (&str
, info
));
7082 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7083 || !info
->addr
.preind
|| info
->addr
.writeback
)
7085 set_syntax_error (_("invalid addressing mode"));
7088 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7089 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7090 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7092 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7094 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7096 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7098 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7099 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7100 /* Leave qualifier to be determined by libopcodes. */
7103 case AARCH64_OPND_SIMD_ADDR_POST
:
7104 /* [<Xn|SP>], <Xm|#<amount>> */
7105 po_misc_or_fail (parse_address (&str
, info
));
7106 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7108 set_syntax_error (_("invalid addressing mode"));
7111 if (!info
->addr
.offset
.is_reg
)
7113 if (inst
.reloc
.exp
.X_op
== O_constant
)
7114 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7117 set_fatal_syntax_error
7118 (_("writeback value must be an immediate constant"));
7125 case AARCH64_OPND_SME_SM_ZA
:
7127 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7129 set_syntax_error (_("unknown or missing PSTATE field name"));
7132 info
->reg
.regno
= val
;
7135 case AARCH64_OPND_SME_PnT_Wm_imm
:
7136 /* <Pn>.<T>[<Wm>, #<imm>] */
7137 if (!parse_sme_pred_reg_with_index (&str
, &info
->indexed_za
,
7140 info
->qualifier
= qualifier
;
7143 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7144 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7145 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7146 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7147 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7148 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7149 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7150 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7151 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7152 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7153 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7154 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7155 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7156 /* [X<n>{, #imm, MUL VL}]
7158 but recognizing SVE registers. */
7159 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7160 &offset_qualifier
));
7161 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7163 set_syntax_error (_("invalid addressing mode"));
7167 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7168 || !info
->addr
.preind
|| info
->addr
.writeback
)
7170 set_syntax_error (_("invalid addressing mode"));
7173 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7174 || inst
.reloc
.exp
.X_op
!= O_constant
)
7176 /* Make sure this has priority over
7177 "invalid addressing mode". */
7178 set_fatal_syntax_error (_("constant offset required"));
7181 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7184 case AARCH64_OPND_SVE_ADDR_R
:
7185 /* [<Xn|SP>{, <R><m>}]
7186 but recognizing SVE registers. */
7187 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7188 &offset_qualifier
));
7189 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7191 offset_qualifier
= AARCH64_OPND_QLF_X
;
7192 info
->addr
.offset
.is_reg
= 1;
7193 info
->addr
.offset
.regno
= 31;
7195 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7196 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7198 set_syntax_error (_("invalid addressing mode"));
7203 case AARCH64_OPND_SVE_ADDR_RR
:
7204 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7205 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7206 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7207 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7208 case AARCH64_OPND_SVE_ADDR_RX
:
7209 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7210 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7211 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7212 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7213 but recognizing SVE registers. */
7214 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7215 &offset_qualifier
));
7216 if (base_qualifier
!= AARCH64_OPND_QLF_X
7217 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7219 set_syntax_error (_("invalid addressing mode"));
7224 case AARCH64_OPND_SVE_ADDR_RZ
:
7225 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7226 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7227 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7228 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7229 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7230 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7231 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7232 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7233 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7234 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7235 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7236 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7237 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7238 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7239 &offset_qualifier
));
7240 if (base_qualifier
!= AARCH64_OPND_QLF_X
7241 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7242 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7244 set_syntax_error (_("invalid addressing mode"));
7247 info
->qualifier
= offset_qualifier
;
7250 case AARCH64_OPND_SVE_ADDR_ZX
:
7251 /* [Zn.<T>{, <Xm>}]. */
7252 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7253 &offset_qualifier
));
7255 base_qualifier either S_S or S_D
7256 offset_qualifier must be X
7258 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7259 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7260 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7262 set_syntax_error (_("invalid addressing mode"));
7265 info
->qualifier
= base_qualifier
;
7266 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7267 || !info
->addr
.preind
|| info
->addr
.writeback
7268 || info
->shifter
.operator_present
!= 0)
7270 set_syntax_error (_("invalid addressing mode"));
7273 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7277 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7278 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7279 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7280 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7281 /* [Z<n>.<T>{, #imm}] */
7282 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7283 &offset_qualifier
));
7284 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7285 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7287 set_syntax_error (_("invalid addressing mode"));
7290 info
->qualifier
= base_qualifier
;
7293 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7294 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7295 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7296 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7297 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7301 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7303 here since we get better error messages by leaving it to
7304 the qualifier checking routines. */
7305 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7306 &offset_qualifier
));
7307 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7308 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7309 || offset_qualifier
!= base_qualifier
)
7311 set_syntax_error (_("invalid addressing mode"));
7314 info
->qualifier
= base_qualifier
;
7317 case AARCH64_OPND_SYSREG
:
7319 uint32_t sysreg_flags
;
7320 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7321 &sysreg_flags
)) == PARSE_FAIL
)
7323 set_syntax_error (_("unknown or missing system register name"));
7326 inst
.base
.operands
[i
].sysreg
.value
= val
;
7327 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7331 case AARCH64_OPND_PSTATEFIELD
:
7333 uint32_t sysreg_flags
;
7334 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7335 &sysreg_flags
)) == PARSE_FAIL
)
7337 set_syntax_error (_("unknown or missing PSTATE field name"));
7340 inst
.base
.operands
[i
].pstatefield
= val
;
7341 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7345 case AARCH64_OPND_SYSREG_IC
:
7346 inst
.base
.operands
[i
].sysins_op
=
7347 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7350 case AARCH64_OPND_SYSREG_DC
:
7351 inst
.base
.operands
[i
].sysins_op
=
7352 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7355 case AARCH64_OPND_SYSREG_AT
:
7356 inst
.base
.operands
[i
].sysins_op
=
7357 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7360 case AARCH64_OPND_SYSREG_SR
:
7361 inst
.base
.operands
[i
].sysins_op
=
7362 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7365 case AARCH64_OPND_SYSREG_TLBI
:
7366 inst
.base
.operands
[i
].sysins_op
=
7367 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7369 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7371 set_fatal_syntax_error ( _("unknown or missing operation name"));
7376 case AARCH64_OPND_BARRIER
:
7377 case AARCH64_OPND_BARRIER_ISB
:
7378 val
= parse_barrier (&str
);
7379 if (val
!= PARSE_FAIL
7380 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7382 /* ISB only accepts options name 'sy'. */
7384 (_("the specified option is not accepted in ISB"));
7385 /* Turn off backtrack as this optional operand is present. */
7389 if (val
!= PARSE_FAIL
7390 && operands
[i
] == AARCH64_OPND_BARRIER
)
7392 /* Regular barriers accept options CRm (C0-C15).
7393 DSB nXS barrier variant accepts values > 15. */
7394 if (val
< 0 || val
> 15)
7396 set_syntax_error (_("the specified option is not accepted in DSB"));
7400 /* This is an extension to accept a 0..15 immediate. */
7401 if (val
== PARSE_FAIL
)
7402 po_imm_or_fail (0, 15);
7403 info
->barrier
= aarch64_barrier_options
+ val
;
7406 case AARCH64_OPND_BARRIER_DSB_NXS
:
7407 val
= parse_barrier (&str
);
7408 if (val
!= PARSE_FAIL
)
7410 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7411 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7413 set_syntax_error (_("the specified option is not accepted in DSB"));
7414 /* Turn off backtrack as this optional operand is present. */
7421 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7422 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7423 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7425 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7427 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7431 /* Option index is encoded as 2-bit value in val<3:2>. */
7432 val
= (val
>> 2) - 4;
7433 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7436 case AARCH64_OPND_PRFOP
:
7437 val
= parse_pldop (&str
);
7438 /* This is an extension to accept a 0..31 immediate. */
7439 if (val
== PARSE_FAIL
)
7440 po_imm_or_fail (0, 31);
7441 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7444 case AARCH64_OPND_BARRIER_PSB
:
7445 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7446 if (val
== PARSE_FAIL
)
7450 case AARCH64_OPND_BTI_TARGET
:
7451 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7452 if (val
== PARSE_FAIL
)
7456 case AARCH64_OPND_SME_ZAda_2b
:
7457 case AARCH64_OPND_SME_ZAda_3b
:
7458 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
);
7461 info
->reg
.regno
= reg
->number
;
7462 info
->qualifier
= qualifier
;
7465 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7466 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7467 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7468 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7469 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7472 : !parse_sme_za_hv_tiles_operand (&str
, &info
->indexed_za
,
7475 info
->qualifier
= qualifier
;
7478 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7479 val
= parse_sme_list_of_64bit_tiles (&str
);
7480 if (val
== PARSE_FAIL
)
7482 info
->imm
.value
= val
;
7485 case AARCH64_OPND_SME_ZA_array
:
7486 if (!parse_sme_za_array (&str
, &info
->indexed_za
))
7490 case AARCH64_OPND_MOPS_ADDR_Rd
:
7491 case AARCH64_OPND_MOPS_ADDR_Rs
:
7492 po_char_or_fail ('[');
7493 if (!parse_x0_to_x30 (&str
, info
))
7495 po_char_or_fail (']');
7496 po_char_or_fail ('!');
7499 case AARCH64_OPND_MOPS_WB_Rn
:
7500 if (!parse_x0_to_x30 (&str
, info
))
7502 po_char_or_fail ('!');
7506 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7509 /* If we get here, this operand was successfully parsed. */
7510 inst
.base
.operands
[i
].present
= 1;
7514 /* The parse routine should already have set the error, but in case
7515 not, set a default one here. */
7517 set_default_error ();
7519 if (! backtrack_pos
)
7520 goto parse_operands_return
;
7523 /* We reach here because this operand is marked as optional, and
7524 either no operand was supplied or the operand was supplied but it
7525 was syntactically incorrect. In the latter case we report an
7526 error. In the former case we perform a few more checks before
7527 dropping through to the code to insert the default operand. */
7529 char *tmp
= backtrack_pos
;
7530 char endchar
= END_OF_INSN
;
7532 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7534 skip_past_char (&tmp
, ',');
7536 if (*tmp
!= endchar
)
7537 /* The user has supplied an operand in the wrong format. */
7538 goto parse_operands_return
;
7540 /* Make sure there is not a comma before the optional operand.
7541 For example the fifth operand of 'sys' is optional:
7543 sys #0,c0,c0,#0, <--- wrong
7544 sys #0,c0,c0,#0 <--- correct. */
7545 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7547 set_fatal_syntax_error
7548 (_("unexpected comma before the omitted optional operand"));
7549 goto parse_operands_return
;
7553 /* Reaching here means we are dealing with an optional operand that is
7554 omitted from the assembly line. */
7555 gas_assert (optional_operand_p (opcode
, i
));
7557 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7559 /* Try again, skipping the optional operand at backtrack_pos. */
7560 str
= backtrack_pos
;
7563 /* Clear any error record after the omitted optional operand has been
7564 successfully handled. */
7568 /* Check if we have parsed all the operands. */
7569 if (*str
!= '\0' && ! error_p ())
7571 /* Set I to the index of the last present operand; this is
7572 for the purpose of diagnostics. */
7573 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7575 set_fatal_syntax_error
7576 (_("unexpected characters following instruction"));
7579 parse_operands_return
:
7583 inst
.parsing_error
.index
= i
;
7584 DEBUG_TRACE ("parsing FAIL: %s - %s",
7585 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7586 inst
.parsing_error
.error
);
7587 /* Record the operand error properly; this is useful when there
7588 are multiple instruction templates for a mnemonic name, so that
7589 later on, we can select the error that most closely describes
7591 record_operand_error_info (opcode
, &inst
.parsing_error
);
7596 DEBUG_TRACE ("parsing SUCCESS");
7601 /* It does some fix-up to provide some programmer friendly feature while
7602 keeping the libopcodes happy, i.e. libopcodes only accepts
7603 the preferred architectural syntax.
7604 Return FALSE if there is any failure; otherwise return TRUE. */
7607 programmer_friendly_fixup (aarch64_instruction
*instr
)
7609 aarch64_inst
*base
= &instr
->base
;
7610 const aarch64_opcode
*opcode
= base
->opcode
;
7611 enum aarch64_op op
= opcode
->op
;
7612 aarch64_opnd_info
*operands
= base
->operands
;
7614 DEBUG_TRACE ("enter");
7616 switch (opcode
->iclass
)
7619 /* TBNZ Xn|Wn, #uimm6, label
7620 Test and Branch Not Zero: conditionally jumps to label if bit number
7621 uimm6 in register Xn is not zero. The bit number implies the width of
7622 the register, which may be written and should be disassembled as Wn if
7623 uimm is less than 32. */
7624 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7626 if (operands
[1].imm
.value
>= 32)
7628 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7632 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7636 /* LDR Wt, label | =value
7637 As a convenience assemblers will typically permit the notation
7638 "=value" in conjunction with the pc-relative literal load instructions
7639 to automatically place an immediate value or symbolic address in a
7640 nearby literal pool and generate a hidden label which references it.
7641 ISREG has been set to 0 in the case of =value. */
7642 if (instr
->gen_lit_pool
7643 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7645 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7646 if (op
== OP_LDRSW_LIT
)
7648 if (instr
->reloc
.exp
.X_op
!= O_constant
7649 && instr
->reloc
.exp
.X_op
!= O_big
7650 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7652 record_operand_error (opcode
, 1,
7653 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7654 _("constant expression expected"));
7657 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7659 record_operand_error (opcode
, 1,
7660 AARCH64_OPDE_OTHER_ERROR
,
7661 _("literal pool insertion failed"));
7669 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7670 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7671 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7672 A programmer-friendly assembler should accept a destination Xd in
7673 place of Wd, however that is not the preferred form for disassembly.
7675 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7676 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7677 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7678 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7683 /* In the 64-bit form, the final register operand is written as Wm
7684 for all but the (possibly omitted) UXTX/LSL and SXTX
7686 As a programmer-friendly assembler, we accept e.g.
7687 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7688 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7689 int idx
= aarch64_operand_index (opcode
->operands
,
7690 AARCH64_OPND_Rm_EXT
);
7691 gas_assert (idx
== 1 || idx
== 2);
7692 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7693 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7694 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7695 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7696 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7697 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7705 DEBUG_TRACE ("exit with SUCCESS");
7709 /* Check for loads and stores that will cause unpredictable behavior. */
7712 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7714 aarch64_inst
*base
= &instr
->base
;
7715 const aarch64_opcode
*opcode
= base
->opcode
;
7716 const aarch64_opnd_info
*opnds
= base
->operands
;
7717 switch (opcode
->iclass
)
7724 /* Loading/storing the base register is unpredictable if writeback. */
7725 if ((aarch64_get_operand_class (opnds
[0].type
)
7726 == AARCH64_OPND_CLASS_INT_REG
)
7727 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7728 && opnds
[1].addr
.base_regno
!= REG_SP
7729 /* Exempt STG/STZG/ST2G/STZ2G. */
7730 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7731 && opnds
[1].addr
.writeback
)
7732 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7736 case ldstnapair_offs
:
7737 case ldstpair_indexed
:
7738 /* Loading/storing the base register is unpredictable if writeback. */
7739 if ((aarch64_get_operand_class (opnds
[0].type
)
7740 == AARCH64_OPND_CLASS_INT_REG
)
7741 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7742 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7743 && opnds
[2].addr
.base_regno
!= REG_SP
7745 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7746 && opnds
[2].addr
.writeback
)
7747 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7748 /* Load operations must load different registers. */
7749 if ((opcode
->opcode
& (1 << 22))
7750 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7751 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7755 if ((aarch64_get_operand_class (opnds
[0].type
)
7756 == AARCH64_OPND_CLASS_INT_REG
)
7757 && (aarch64_get_operand_class (opnds
[1].type
)
7758 == AARCH64_OPND_CLASS_INT_REG
))
7760 if ((opcode
->opcode
& (1 << 22)))
7762 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7763 if ((opcode
->opcode
& (1 << 21))
7764 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7765 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7769 /* Store-Exclusive is unpredictable if Rt == Rs. */
7770 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7772 (_("unpredictable: identical transfer and status registers"
7775 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7777 if (!(opcode
->opcode
& (1 << 21)))
7778 /* Store-Exclusive is unpredictable if Rn == Rs. */
7780 (_("unpredictable: identical base and status registers"
7783 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7785 (_("unpredictable: "
7786 "identical transfer and status registers"
7790 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7791 if ((opcode
->opcode
& (1 << 21))
7792 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7793 && opnds
[3].reg
.regno
!= REG_SP
)
7794 as_warn (_("unpredictable: identical base and status registers"
7806 force_automatic_sequence_close (void)
7808 struct aarch64_segment_info_type
*tc_seg_info
;
7810 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7811 if (tc_seg_info
->insn_sequence
.instr
)
7813 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7814 _("previous `%s' sequence has not been closed"),
7815 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7816 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7820 /* A wrapper function to interface with libopcodes on encoding and
7821 record the error message if there is any.
7823 Return TRUE on success; otherwise return FALSE. */
7826 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7829 aarch64_operand_error error_info
;
7830 memset (&error_info
, '\0', sizeof (error_info
));
7831 error_info
.kind
= AARCH64_OPDE_NIL
;
7832 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7833 && !error_info
.non_fatal
)
7836 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7837 record_operand_error_info (opcode
, &error_info
);
7838 return error_info
.non_fatal
;
7841 #ifdef DEBUG_AARCH64
7843 dump_opcode_operands (const aarch64_opcode
*opcode
)
7846 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7848 aarch64_verbose ("\t\t opnd%d: %s", i
,
7849 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7850 ? aarch64_get_operand_name (opcode
->operands
[i
])
7851 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7855 #endif /* DEBUG_AARCH64 */
7857 /* This is the guts of the machine-dependent assembler. STR points to a
7858 machine dependent instruction. This function is supposed to emit
7859 the frags/bytes it assembles to. */
7862 md_assemble (char *str
)
7864 templates
*template;
7865 const aarch64_opcode
*opcode
;
7866 struct aarch64_segment_info_type
*tc_seg_info
;
7867 aarch64_inst
*inst_base
;
7868 unsigned saved_cond
;
7870 /* Align the previous label if needed. */
7871 if (last_label_seen
!= NULL
)
7873 symbol_set_frag (last_label_seen
, frag_now
);
7874 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7875 S_SET_SEGMENT (last_label_seen
, now_seg
);
7878 /* Update the current insn_sequence from the segment. */
7879 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7880 insn_sequence
= &tc_seg_info
->insn_sequence
;
7881 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7883 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7885 DEBUG_TRACE ("\n\n");
7886 DEBUG_TRACE ("==============================");
7887 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7889 /* Scan up to the end of the mnemonic, which must end in whitespace,
7890 '.', or end of string. */
7893 for (; is_part_of_name (*p
); p
++)
7894 if (*p
== '.' && !dot
)
7899 as_bad (_("unknown mnemonic -- `%s'"), str
);
7903 if (!dot
&& create_register_alias (str
, p
))
7906 template = opcode_lookup (str
, dot
, p
);
7909 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7914 skip_whitespace (p
);
7917 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7918 get_mnemonic_name (str
), str
);
7922 init_operand_error_report ();
7924 /* Sections are assumed to start aligned. In executable section, there is no
7925 MAP_DATA symbol pending. So we only align the address during
7926 MAP_DATA --> MAP_INSN transition.
7927 For other sections, this is not guaranteed. */
7928 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7929 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7930 frag_align_code (2, 0);
7932 saved_cond
= inst
.cond
;
7933 reset_aarch64_instruction (&inst
);
7934 inst
.cond
= saved_cond
;
7936 /* Iterate through all opcode entries with the same mnemonic name. */
7939 opcode
= template->opcode
;
7941 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7942 #ifdef DEBUG_AARCH64
7944 dump_opcode_operands (opcode
);
7945 #endif /* DEBUG_AARCH64 */
7947 mapping_state (MAP_INSN
);
7949 inst_base
= &inst
.base
;
7950 inst_base
->opcode
= opcode
;
7952 /* Truly conditionally executed instructions, e.g. b.cond. */
7953 if (opcode
->flags
& F_COND
)
7955 gas_assert (inst
.cond
!= COND_ALWAYS
);
7956 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7957 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7959 else if (inst
.cond
!= COND_ALWAYS
)
7961 /* It shouldn't arrive here, where the assembly looks like a
7962 conditional instruction but the found opcode is unconditional. */
7967 if (parse_operands (p
, opcode
)
7968 && programmer_friendly_fixup (&inst
)
7969 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7971 /* Check that this instruction is supported for this CPU. */
7972 if (!opcode
->avariant
7973 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7975 as_bad (_("selected processor does not support `%s'"), str
);
7979 warn_unpredictable_ldst (&inst
, str
);
7981 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7982 || !inst
.reloc
.need_libopcodes_p
)
7986 /* If there is relocation generated for the instruction,
7987 store the instruction information for the future fix-up. */
7988 struct aarch64_inst
*copy
;
7989 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7990 copy
= XNEW (struct aarch64_inst
);
7991 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7995 /* Issue non-fatal messages if any. */
7996 output_operand_error_report (str
, true);
8000 template = template->next
;
8001 if (template != NULL
)
8003 reset_aarch64_instruction (&inst
);
8004 inst
.cond
= saved_cond
;
8007 while (template != NULL
);
8009 /* Issue the error messages if any. */
8010 output_operand_error_report (str
, false);
8013 /* Various frobbings of labels and their addresses. */
8016 aarch64_start_line_hook (void)
8018 last_label_seen
= NULL
;
8022 aarch64_frob_label (symbolS
* sym
)
8024 last_label_seen
= sym
;
8026 dwarf2_emit_label (sym
);
8030 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8032 /* Check to see if we have a block to close. */
8033 force_automatic_sequence_close ();
8037 aarch64_data_in_code (void)
8039 if (startswith (input_line_pointer
+ 1, "data:"))
8041 *input_line_pointer
= '/';
8042 input_line_pointer
+= 5;
8043 *input_line_pointer
= 0;
8051 aarch64_canonicalize_symbol_name (char *name
)
8055 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8056 *(name
+ len
- 5) = 0;
8061 /* Table of all register names defined by default. The user can
8062 define additional names with .req. Note that all register names
8063 should appear in both upper and lowercase variants. Some registers
8064 also have mixed-case names. */
8066 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8067 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8068 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8069 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8070 #define REGSET16(p,t) \
8071 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8072 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8073 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8074 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8075 #define REGSET16S(p,s,t) \
8076 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8077 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8078 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8079 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8080 #define REGSET31(p,t) \
8082 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8083 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8084 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8085 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8086 #define REGSET(p,t) \
8087 REGSET31(p,t), REGNUM(p,31,t)
8089 /* These go into aarch64_reg_hsh hash-table. */
8090 static const reg_entry reg_names
[] = {
8091 /* Integer registers. */
8092 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8093 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8095 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8096 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8097 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8098 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8099 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8100 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8102 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8103 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8105 /* Floating-point single precision registers. */
8106 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8108 /* Floating-point double precision registers. */
8109 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8111 /* Floating-point half precision registers. */
8112 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8114 /* Floating-point byte precision registers. */
8115 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8117 /* Floating-point quad precision registers. */
8118 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8120 /* FP/SIMD registers. */
8121 REGSET (v
, VN
), REGSET (V
, VN
),
8123 /* SVE vector registers. */
8124 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8126 /* SVE predicate registers. */
8127 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8129 /* SME ZA. We model this as a register because it acts syntactically
8130 like ZA0H, supporting qualifier suffixes and indexing. */
8131 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8133 /* SME ZA tile registers. */
8134 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8136 /* SME ZA tile registers (horizontal slice). */
8137 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8139 /* SME ZA tile registers (vertical slice). */
8140 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8158 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8159 static const asm_nzcv nzcv_names
[] = {
8160 {"nzcv", B (n
, z
, c
, v
)},
8161 {"nzcV", B (n
, z
, c
, V
)},
8162 {"nzCv", B (n
, z
, C
, v
)},
8163 {"nzCV", B (n
, z
, C
, V
)},
8164 {"nZcv", B (n
, Z
, c
, v
)},
8165 {"nZcV", B (n
, Z
, c
, V
)},
8166 {"nZCv", B (n
, Z
, C
, v
)},
8167 {"nZCV", B (n
, Z
, C
, V
)},
8168 {"Nzcv", B (N
, z
, c
, v
)},
8169 {"NzcV", B (N
, z
, c
, V
)},
8170 {"NzCv", B (N
, z
, C
, v
)},
8171 {"NzCV", B (N
, z
, C
, V
)},
8172 {"NZcv", B (N
, Z
, c
, v
)},
8173 {"NZcV", B (N
, Z
, c
, V
)},
8174 {"NZCv", B (N
, Z
, C
, v
)},
8175 {"NZCV", B (N
, Z
, C
, V
)}
8188 /* MD interface: bits in the object file. */
8190 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8191 for use in the a.out file, and stores them in the array pointed to by buf.
8192 This knows about the endian-ness of the target machine and does
8193 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8194 2 (short) and 4 (long) Floating numbers are put out as a series of
8195 LITTLENUMS (shorts, here at least). */
8198 md_number_to_chars (char *buf
, valueT val
, int n
)
8200 if (target_big_endian
)
8201 number_to_chars_bigendian (buf
, val
, n
);
8203 number_to_chars_littleendian (buf
, val
, n
);
8206 /* MD interface: Sections. */
8208 /* Estimate the size of a frag before relaxing. Assume everything fits in
8212 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8218 /* Round up a section size to the appropriate boundary. */
8221 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8226 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8227 of an rs_align_code fragment.
8229 Here we fill the frag with the appropriate info for padding the
8230 output stream. The resulting frag will consist of a fixed (fr_fix)
8231 and of a repeating (fr_var) part.
8233 The fixed content is always emitted before the repeating content and
8234 these two parts are used as follows in constructing the output:
8235 - the fixed part will be used to align to a valid instruction word
8236 boundary, in case that we start at a misaligned address; as no
8237 executable instruction can live at the misaligned location, we
8238 simply fill with zeros;
8239 - the variable part will be used to cover the remaining padding and
8240 we fill using the AArch64 NOP instruction.
8242 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8243 enough storage space for up to 3 bytes for padding the back to a valid
8244 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8247 aarch64_handle_align (fragS
* fragP
)
8249 /* NOP = d503201f */
8250 /* AArch64 instructions are always little-endian. */
8251 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8253 int bytes
, fix
, noop_size
;
8256 if (fragP
->fr_type
!= rs_align_code
)
8259 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8260 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8263 gas_assert (fragP
->tc_frag_data
.recorded
);
8266 noop_size
= sizeof (aarch64_noop
);
8268 fix
= bytes
& (noop_size
- 1);
8271 #if defined OBJ_ELF || defined OBJ_COFF
8272 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8276 fragP
->fr_fix
+= fix
;
8280 memcpy (p
, aarch64_noop
, noop_size
);
8281 fragP
->fr_var
= noop_size
;
8284 /* Perform target specific initialisation of a frag.
8285 Note - despite the name this initialisation is not done when the frag
8286 is created, but only when its type is assigned. A frag can be created
8287 and used a long time before its type is set, so beware of assuming that
8288 this initialisation is performed first. */
8292 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8293 int max_chars ATTRIBUTE_UNUSED
)
8297 #else /* OBJ_ELF is defined. */
8299 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8301 /* Record a mapping symbol for alignment frags. We will delete this
8302 later if the alignment ends up empty. */
8303 if (!fragP
->tc_frag_data
.recorded
)
8304 fragP
->tc_frag_data
.recorded
= 1;
8306 /* PR 21809: Do not set a mapping state for debug sections
8307 - it just confuses other tools. */
8308 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8311 switch (fragP
->fr_type
)
8315 mapping_state_2 (MAP_DATA
, max_chars
);
8318 /* PR 20364: We can get alignment frags in code sections,
8319 so do not just assume that we should use the MAP_DATA state. */
8320 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8323 mapping_state_2 (MAP_INSN
, max_chars
);
8330 /* Whether SFrame stack trace info is supported. */
8333 aarch64_support_sframe_p (void)
8335 /* At this time, SFrame is supported for aarch64 only. */
8336 return (aarch64_abi
== AARCH64_ABI_LP64
);
8339 /* Specify if RA tracking is needed. */
8342 aarch64_sframe_ra_tracking_p (void)
8347 /* Specify the fixed offset to recover RA from CFA.
8348 (useful only when RA tracking is not needed). */
8351 aarch64_sframe_cfa_ra_offset (void)
8353 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8356 /* Get the abi/arch indentifier for SFrame. */
8359 aarch64_sframe_get_abi_arch (void)
8361 unsigned char sframe_abi_arch
= 0;
8363 if (aarch64_support_sframe_p ())
8365 sframe_abi_arch
= target_big_endian
8366 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8367 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8370 return sframe_abi_arch
;
8373 #endif /* OBJ_ELF */
8375 /* Initialize the DWARF-2 unwind information for this procedure. */
8378 tc_aarch64_frame_initial_instructions (void)
8380 cfi_add_CFA_def_cfa (REG_SP
, 0);
8383 /* Convert REGNAME to a DWARF-2 register number. */
8386 tc_aarch64_regname_to_dw2regnum (char *regname
)
8388 const reg_entry
*reg
= parse_reg (®name
);
8394 case REG_TYPE_SP_32
:
8395 case REG_TYPE_SP_64
:
8405 return reg
->number
+ 64;
8413 /* Implement DWARF2_ADDR_SIZE. */
8416 aarch64_dwarf2_addr_size (void)
8422 return bfd_arch_bits_per_address (stdoutput
) / 8;
8425 /* MD interface: Symbol and relocation handling. */
8427 /* Return the address within the segment that a PC-relative fixup is
8428 relative to. For AArch64 PC-relative fixups applied to instructions
8429 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8432 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8434 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8436 /* If this is pc-relative and we are going to emit a relocation
8437 then we just want to put out any pipeline compensation that the linker
8438 will need. Otherwise we want to use the calculated base. */
8440 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8441 || aarch64_force_relocation (fixP
)))
8444 /* AArch64 should be consistent for all pc-relative relocations. */
8445 return base
+ AARCH64_PCREL_OFFSET
;
8448 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8449 Otherwise we have no need to default values of symbols. */
8452 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8455 if (name
[0] == '_' && name
[1] == 'G'
8456 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8460 if (symbol_find (name
))
8461 as_bad (_("GOT already in the symbol table"));
8463 GOT_symbol
= symbol_new (name
, undefined_section
,
8464 &zero_address_frag
, 0);
8474 /* Return non-zero if the indicated VALUE has overflowed the maximum
8475 range expressible by a unsigned number with the indicated number of
8479 unsigned_overflow (valueT value
, unsigned bits
)
8482 if (bits
>= sizeof (valueT
) * 8)
8484 lim
= (valueT
) 1 << bits
;
8485 return (value
>= lim
);
8489 /* Return non-zero if the indicated VALUE has overflowed the maximum
8490 range expressible by an signed number with the indicated number of
8494 signed_overflow (offsetT value
, unsigned bits
)
8497 if (bits
>= sizeof (offsetT
) * 8)
8499 lim
= (offsetT
) 1 << (bits
- 1);
8500 return (value
< -lim
|| value
>= lim
);
8503 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8504 unsigned immediate offset load/store instruction, try to encode it as
8505 an unscaled, 9-bit, signed immediate offset load/store instruction.
8506 Return TRUE if it is successful; otherwise return FALSE.
8508 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8509 in response to the standard LDR/STR mnemonics when the immediate offset is
8510 unambiguous, i.e. when it is negative or unaligned. */
8513 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8516 enum aarch64_op new_op
;
8517 const aarch64_opcode
*new_opcode
;
8519 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8521 switch (instr
->opcode
->op
)
8523 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8524 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8525 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8526 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8527 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8528 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8529 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8530 case OP_STR_POS
: new_op
= OP_STUR
; break;
8531 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8532 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8533 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8534 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8535 default: new_op
= OP_NIL
; break;
8538 if (new_op
== OP_NIL
)
8541 new_opcode
= aarch64_get_opcode (new_op
);
8542 gas_assert (new_opcode
!= NULL
);
8544 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8545 instr
->opcode
->op
, new_opcode
->op
);
8547 aarch64_replace_opcode (instr
, new_opcode
);
8549 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8550 qualifier matching may fail because the out-of-date qualifier will
8551 prevent the operand being updated with a new and correct qualifier. */
8552 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8553 AARCH64_OPND_ADDR_SIMM9
);
8554 gas_assert (idx
== 1);
8555 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8557 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8559 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8566 /* Called by fix_insn to fix a MOV immediate alias instruction.
8568 Operand for a generic move immediate instruction, which is an alias
8569 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8570 a 32-bit/64-bit immediate value into general register. An assembler error
8571 shall result if the immediate cannot be created by a single one of these
8572 instructions. If there is a choice, then to ensure reversability an
8573 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8576 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8578 const aarch64_opcode
*opcode
;
8580 /* Need to check if the destination is SP/ZR. The check has to be done
8581 before any aarch64_replace_opcode. */
8582 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8583 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8585 instr
->operands
[1].imm
.value
= value
;
8586 instr
->operands
[1].skip
= 0;
8590 /* Try the MOVZ alias. */
8591 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8592 aarch64_replace_opcode (instr
, opcode
);
8593 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8594 &instr
->value
, NULL
, NULL
, insn_sequence
))
8596 put_aarch64_insn (buf
, instr
->value
);
8599 /* Try the MOVK alias. */
8600 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8601 aarch64_replace_opcode (instr
, opcode
);
8602 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8603 &instr
->value
, NULL
, NULL
, insn_sequence
))
8605 put_aarch64_insn (buf
, instr
->value
);
8610 if (try_mov_bitmask_p
)
8612 /* Try the ORR alias. */
8613 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8614 aarch64_replace_opcode (instr
, opcode
);
8615 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8616 &instr
->value
, NULL
, NULL
, insn_sequence
))
8618 put_aarch64_insn (buf
, instr
->value
);
8623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8624 _("immediate cannot be moved by a single instruction"));
8627 /* An instruction operand which is immediate related may have symbol used
8628 in the assembly, e.g.
8631 .set u32, 0x00ffff00
8633 At the time when the assembly instruction is parsed, a referenced symbol,
8634 like 'u32' in the above example may not have been seen; a fixS is created
8635 in such a case and is handled here after symbols have been resolved.
8636 Instruction is fixed up with VALUE using the information in *FIXP plus
8637 extra information in FLAGS.
8639 This function is called by md_apply_fix to fix up instructions that need
8640 a fix-up described above but does not involve any linker-time relocation. */
8643 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8647 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8648 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8649 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8653 /* Now the instruction is about to be fixed-up, so the operand that
8654 was previously marked as 'ignored' needs to be unmarked in order
8655 to get the encoding done properly. */
8656 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8657 new_inst
->operands
[idx
].skip
= 0;
8660 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8664 case AARCH64_OPND_EXCEPTION
:
8665 case AARCH64_OPND_UNDEFINED
:
8666 if (unsigned_overflow (value
, 16))
8667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8668 _("immediate out of range"));
8669 insn
= get_aarch64_insn (buf
);
8670 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8671 put_aarch64_insn (buf
, insn
);
8674 case AARCH64_OPND_AIMM
:
8675 /* ADD or SUB with immediate.
8676 NOTE this assumes we come here with a add/sub shifted reg encoding
8677 3 322|2222|2 2 2 21111 111111
8678 1 098|7654|3 2 1 09876 543210 98765 43210
8679 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8680 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8681 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8682 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8684 3 322|2222|2 2 221111111111
8685 1 098|7654|3 2 109876543210 98765 43210
8686 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8687 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8688 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8689 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8690 Fields sf Rn Rd are already set. */
8691 insn
= get_aarch64_insn (buf
);
8695 insn
= reencode_addsub_switch_add_sub (insn
);
8699 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8700 && unsigned_overflow (value
, 12))
8702 /* Try to shift the value by 12 to make it fit. */
8703 if (((value
>> 12) << 12) == value
8704 && ! unsigned_overflow (value
, 12 + 12))
8707 insn
|= encode_addsub_imm_shift_amount (1);
8711 if (unsigned_overflow (value
, 12))
8712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8713 _("immediate out of range"));
8715 insn
|= encode_addsub_imm (value
);
8717 put_aarch64_insn (buf
, insn
);
8720 case AARCH64_OPND_SIMD_IMM
:
8721 case AARCH64_OPND_SIMD_IMM_SFT
:
8722 case AARCH64_OPND_LIMM
:
8723 /* Bit mask immediate. */
8724 gas_assert (new_inst
!= NULL
);
8725 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8726 new_inst
->operands
[idx
].imm
.value
= value
;
8727 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8728 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8729 put_aarch64_insn (buf
, new_inst
->value
);
8731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8732 _("invalid immediate"));
8735 case AARCH64_OPND_HALF
:
8736 /* 16-bit unsigned immediate. */
8737 if (unsigned_overflow (value
, 16))
8738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8739 _("immediate out of range"));
8740 insn
= get_aarch64_insn (buf
);
8741 insn
|= encode_movw_imm (value
& 0xffff);
8742 put_aarch64_insn (buf
, insn
);
8745 case AARCH64_OPND_IMM_MOV
:
8746 /* Operand for a generic move immediate instruction, which is
8747 an alias instruction that generates a single MOVZ, MOVN or ORR
8748 instruction to loads a 32-bit/64-bit immediate value into general
8749 register. An assembler error shall result if the immediate cannot be
8750 created by a single one of these instructions. If there is a choice,
8751 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8752 and MOVZ or MOVN to ORR. */
8753 gas_assert (new_inst
!= NULL
);
8754 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8757 case AARCH64_OPND_ADDR_SIMM7
:
8758 case AARCH64_OPND_ADDR_SIMM9
:
8759 case AARCH64_OPND_ADDR_SIMM9_2
:
8760 case AARCH64_OPND_ADDR_SIMM10
:
8761 case AARCH64_OPND_ADDR_UIMM12
:
8762 case AARCH64_OPND_ADDR_SIMM11
:
8763 case AARCH64_OPND_ADDR_SIMM13
:
8764 /* Immediate offset in an address. */
8765 insn
= get_aarch64_insn (buf
);
8767 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8768 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8769 || new_inst
->opcode
->operands
[2] == opnd
);
8771 /* Get the index of the address operand. */
8772 if (new_inst
->opcode
->operands
[1] == opnd
)
8773 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8776 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8779 /* Update the resolved offset value. */
8780 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8782 /* Encode/fix-up. */
8783 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8784 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8786 put_aarch64_insn (buf
, new_inst
->value
);
8789 else if (new_inst
->opcode
->iclass
== ldst_pos
8790 && try_to_encode_as_unscaled_ldst (new_inst
))
8792 put_aarch64_insn (buf
, new_inst
->value
);
8796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8797 _("immediate offset out of range"));
8802 as_fatal (_("unhandled operand code %d"), opnd
);
8806 /* Apply a fixup (fixP) to segment data, once it has been determined
8807 by our caller that we have all the info we need to fix it up.
8809 Parameter valP is the pointer to the value of the bits. */
8812 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8814 offsetT value
= *valP
;
8816 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8818 unsigned flags
= fixP
->fx_addnumber
;
8820 DEBUG_TRACE ("\n\n");
8821 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8822 DEBUG_TRACE ("Enter md_apply_fix");
8824 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8826 /* Note whether this will delete the relocation. */
8828 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8829 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8832 /* Process the relocations. */
8833 switch (fixP
->fx_r_type
)
8835 case BFD_RELOC_NONE
:
8836 /* This will need to go in the object file. */
8841 case BFD_RELOC_8_PCREL
:
8842 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8843 md_number_to_chars (buf
, value
, 1);
8847 case BFD_RELOC_16_PCREL
:
8848 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8849 md_number_to_chars (buf
, value
, 2);
8853 case BFD_RELOC_32_PCREL
:
8854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8855 md_number_to_chars (buf
, value
, 4);
8859 case BFD_RELOC_64_PCREL
:
8860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8861 md_number_to_chars (buf
, value
, 8);
8864 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8865 /* We claim that these fixups have been processed here, even if
8866 in fact we generate an error because we do not have a reloc
8867 for them, so tc_gen_reloc() will reject them. */
8869 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8872 _("undefined symbol %s used as an immediate value"),
8873 S_GET_NAME (fixP
->fx_addsy
));
8874 goto apply_fix_return
;
8876 fix_insn (fixP
, flags
, value
);
8879 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8880 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8884 _("pc-relative load offset not word aligned"));
8885 if (signed_overflow (value
, 21))
8886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8887 _("pc-relative load offset out of range"));
8888 insn
= get_aarch64_insn (buf
);
8889 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8890 put_aarch64_insn (buf
, insn
);
8894 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8895 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8897 if (signed_overflow (value
, 21))
8898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8899 _("pc-relative address offset out of range"));
8900 insn
= get_aarch64_insn (buf
);
8901 insn
|= encode_adr_imm (value
);
8902 put_aarch64_insn (buf
, insn
);
8906 case BFD_RELOC_AARCH64_BRANCH19
:
8907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8911 _("conditional branch target not word aligned"));
8912 if (signed_overflow (value
, 21))
8913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8914 _("conditional branch out of range"));
8915 insn
= get_aarch64_insn (buf
);
8916 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8917 put_aarch64_insn (buf
, insn
);
8921 case BFD_RELOC_AARCH64_TSTBR14
:
8922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8926 _("conditional branch target not word aligned"));
8927 if (signed_overflow (value
, 16))
8928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8929 _("conditional branch out of range"));
8930 insn
= get_aarch64_insn (buf
);
8931 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8932 put_aarch64_insn (buf
, insn
);
8936 case BFD_RELOC_AARCH64_CALL26
:
8937 case BFD_RELOC_AARCH64_JUMP26
:
8938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8942 _("branch target not word aligned"));
8943 if (signed_overflow (value
, 28))
8944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8945 _("branch out of range"));
8946 insn
= get_aarch64_insn (buf
);
8947 insn
|= encode_branch_ofs_26 (value
>> 2);
8948 put_aarch64_insn (buf
, insn
);
8952 case BFD_RELOC_AARCH64_MOVW_G0
:
8953 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8954 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8955 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8956 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8957 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8960 case BFD_RELOC_AARCH64_MOVW_G1
:
8961 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8962 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8963 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8964 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8965 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8968 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8970 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8971 /* Should always be exported to object file, see
8972 aarch64_force_relocation(). */
8973 gas_assert (!fixP
->fx_done
);
8974 gas_assert (seg
->use_rela_p
);
8976 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8978 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8979 /* Should always be exported to object file, see
8980 aarch64_force_relocation(). */
8981 gas_assert (!fixP
->fx_done
);
8982 gas_assert (seg
->use_rela_p
);
8984 case BFD_RELOC_AARCH64_MOVW_G2
:
8985 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8986 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8987 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8988 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8991 case BFD_RELOC_AARCH64_MOVW_G3
:
8992 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8997 insn
= get_aarch64_insn (buf
);
9001 /* REL signed addend must fit in 16 bits */
9002 if (signed_overflow (value
, 16))
9003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9004 _("offset out of range"));
9008 /* Check for overflow and scale. */
9009 switch (fixP
->fx_r_type
)
9011 case BFD_RELOC_AARCH64_MOVW_G0
:
9012 case BFD_RELOC_AARCH64_MOVW_G1
:
9013 case BFD_RELOC_AARCH64_MOVW_G2
:
9014 case BFD_RELOC_AARCH64_MOVW_G3
:
9015 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9016 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9017 if (unsigned_overflow (value
, scale
+ 16))
9018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9019 _("unsigned value out of range"));
9021 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9022 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9023 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9024 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9025 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9026 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9027 /* NOTE: We can only come here with movz or movn. */
9028 if (signed_overflow (value
, scale
+ 16))
9029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9030 _("signed value out of range"));
9033 /* Force use of MOVN. */
9035 insn
= reencode_movzn_to_movn (insn
);
9039 /* Force use of MOVZ. */
9040 insn
= reencode_movzn_to_movz (insn
);
9044 /* Unchecked relocations. */
9050 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9051 insn
|= encode_movw_imm (value
& 0xffff);
9053 put_aarch64_insn (buf
, insn
);
9057 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9058 fixP
->fx_r_type
= (ilp32_p
9059 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9060 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9061 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9062 /* Should always be exported to object file, see
9063 aarch64_force_relocation(). */
9064 gas_assert (!fixP
->fx_done
);
9065 gas_assert (seg
->use_rela_p
);
9068 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9069 fixP
->fx_r_type
= (ilp32_p
9070 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9071 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9072 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9073 /* Should always be exported to object file, see
9074 aarch64_force_relocation(). */
9075 gas_assert (!fixP
->fx_done
);
9076 gas_assert (seg
->use_rela_p
);
9079 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9080 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9081 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9082 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9083 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9084 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9085 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9086 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9087 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9088 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9089 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9090 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9091 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9092 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9093 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9094 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9095 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9096 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9097 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9098 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9099 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9100 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9101 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9102 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9103 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9104 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9105 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9106 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9107 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9108 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9109 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9110 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9111 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9112 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9113 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9114 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9115 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9116 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9117 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9118 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9119 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9120 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9121 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9122 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9123 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9124 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9125 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9126 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9127 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9128 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9129 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9130 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9131 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9132 /* Should always be exported to object file, see
9133 aarch64_force_relocation(). */
9134 gas_assert (!fixP
->fx_done
);
9135 gas_assert (seg
->use_rela_p
);
9138 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9139 /* Should always be exported to object file, see
9140 aarch64_force_relocation(). */
9141 fixP
->fx_r_type
= (ilp32_p
9142 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9143 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9144 gas_assert (!fixP
->fx_done
);
9145 gas_assert (seg
->use_rela_p
);
9148 case BFD_RELOC_AARCH64_ADD_LO12
:
9149 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9150 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9151 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9152 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9153 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9154 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9155 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9156 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9157 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9158 case BFD_RELOC_AARCH64_LDST128_LO12
:
9159 case BFD_RELOC_AARCH64_LDST16_LO12
:
9160 case BFD_RELOC_AARCH64_LDST32_LO12
:
9161 case BFD_RELOC_AARCH64_LDST64_LO12
:
9162 case BFD_RELOC_AARCH64_LDST8_LO12
:
9163 /* Should always be exported to object file, see
9164 aarch64_force_relocation(). */
9165 gas_assert (!fixP
->fx_done
);
9166 gas_assert (seg
->use_rela_p
);
9169 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9170 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9171 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9174 case BFD_RELOC_UNUSED
:
9175 /* An error will already have been reported. */
9179 case BFD_RELOC_32_SECREL
:
9180 case BFD_RELOC_16_SECIDX
:
9184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9185 _("unexpected %s fixup"),
9186 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9191 /* Free the allocated the struct aarch64_inst.
9192 N.B. currently there are very limited number of fix-up types actually use
9193 this field, so the impact on the performance should be minimal . */
9194 free (fixP
->tc_fix_data
.inst
);
9199 /* Translate internal representation of relocation info to BFD target
9203 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9206 bfd_reloc_code_real_type code
;
9208 reloc
= XNEW (arelent
);
9210 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9211 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9212 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9216 if (section
->use_rela_p
)
9217 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9219 fixp
->fx_offset
= reloc
->address
;
9221 reloc
->addend
= fixp
->fx_offset
;
9223 code
= fixp
->fx_r_type
;
9228 code
= BFD_RELOC_16_PCREL
;
9233 code
= BFD_RELOC_32_PCREL
;
9238 code
= BFD_RELOC_64_PCREL
;
9245 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9246 if (reloc
->howto
== NULL
)
9248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9250 ("cannot represent %s relocation in this object file format"),
9251 bfd_get_reloc_code_name (code
));
9258 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9261 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9263 bfd_reloc_code_real_type type
;
9267 if (exp
->X_op
== O_secrel
)
9269 exp
->X_op
= O_symbol
;
9270 type
= BFD_RELOC_32_SECREL
;
9272 else if (exp
->X_op
== O_secidx
)
9274 exp
->X_op
= O_symbol
;
9275 type
= BFD_RELOC_16_SECIDX
;
9281 FIXME: @@ Should look at CPU word size. */
9288 type
= BFD_RELOC_16
;
9291 type
= BFD_RELOC_32
;
9294 type
= BFD_RELOC_64
;
9297 as_bad (_("cannot do %u-byte relocation"), size
);
9298 type
= BFD_RELOC_UNUSED
;
9305 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9308 /* Implement md_after_parse_args. This is the earliest time we need to decide
9309 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9312 aarch64_after_parse_args (void)
9314 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9318 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9319 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9320 aarch64_abi
= AARCH64_ABI_ILP32
;
9322 aarch64_abi
= AARCH64_ABI_LP64
;
9324 aarch64_abi
= AARCH64_ABI_LLP64
;
9330 elf64_aarch64_target_format (void)
9333 /* FIXME: What to do for ilp32_p ? */
9334 if (target_big_endian
)
9335 return "elf64-bigaarch64-cloudabi";
9337 return "elf64-littleaarch64-cloudabi";
9339 if (target_big_endian
)
9340 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9342 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9347 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9349 elf_frob_symbol (symp
, puntp
);
9351 #elif defined OBJ_COFF
9353 coff_aarch64_target_format (void)
9355 return "pe-aarch64-little";
9359 /* MD interface: Finalization. */
9361 /* A good place to do this, although this was probably not intended
9362 for this kind of use. We need to dump the literal pool before
9363 references are made to a null symbol pointer. */
9366 aarch64_cleanup (void)
9370 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9372 /* Put it at the end of the relevant section. */
9373 subseg_set (pool
->section
, pool
->sub_section
);
9379 /* Remove any excess mapping symbols generated for alignment frags in
9380 SEC. We may have created a mapping symbol before a zero byte
9381 alignment; remove it if there's a mapping symbol after the
9384 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9385 void *dummy ATTRIBUTE_UNUSED
)
9387 segment_info_type
*seginfo
= seg_info (sec
);
9390 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9393 for (fragp
= seginfo
->frchainP
->frch_root
;
9394 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9396 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9397 fragS
*next
= fragp
->fr_next
;
9399 /* Variable-sized frags have been converted to fixed size by
9400 this point. But if this was variable-sized to start with,
9401 there will be a fixed-size frag after it. So don't handle
9403 if (sym
== NULL
|| next
== NULL
)
9406 if (S_GET_VALUE (sym
) < next
->fr_address
)
9407 /* Not at the end of this frag. */
9409 know (S_GET_VALUE (sym
) == next
->fr_address
);
9413 if (next
->tc_frag_data
.first_map
!= NULL
)
9415 /* Next frag starts with a mapping symbol. Discard this
9417 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9421 if (next
->fr_next
== NULL
)
9423 /* This mapping symbol is at the end of the section. Discard
9425 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9426 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9430 /* As long as we have empty frags without any mapping symbols,
9432 /* If the next frag is non-empty and does not start with a
9433 mapping symbol, then this mapping symbol is required. */
9434 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9437 next
= next
->fr_next
;
9439 while (next
!= NULL
);
9444 /* Adjust the symbol table. */
9447 aarch64_adjust_symtab (void)
9450 /* Remove any overlapping mapping symbols generated by alignment frags. */
9451 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9452 /* Now do generic ELF adjustments. */
9453 elf_adjust_symtab ();
9458 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9460 str_hash_insert (table
, key
, value
, 0);
9464 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9466 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9467 checked_hash_insert (table
, key
, value
);
9471 fill_instruction_hash_table (void)
9473 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9475 while (opcode
->name
!= NULL
)
9477 templates
*templ
, *new_templ
;
9478 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9480 new_templ
= XNEW (templates
);
9481 new_templ
->opcode
= opcode
;
9482 new_templ
->next
= NULL
;
9485 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9488 new_templ
->next
= templ
->next
;
9489 templ
->next
= new_templ
;
9496 convert_to_upper (char *dst
, const char *src
, size_t num
)
9499 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9500 *dst
= TOUPPER (*src
);
9504 /* Assume STR point to a lower-case string, allocate, convert and return
9505 the corresponding upper-case string. */
9506 static inline const char*
9507 get_upper_str (const char *str
)
9510 size_t len
= strlen (str
);
9511 ret
= XNEWVEC (char, len
+ 1);
9512 convert_to_upper (ret
, str
, len
);
9516 /* MD interface: Initialization. */
9524 aarch64_ops_hsh
= str_htab_create ();
9525 aarch64_cond_hsh
= str_htab_create ();
9526 aarch64_shift_hsh
= str_htab_create ();
9527 aarch64_sys_regs_hsh
= str_htab_create ();
9528 aarch64_pstatefield_hsh
= str_htab_create ();
9529 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9530 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9531 aarch64_sys_regs_at_hsh
= str_htab_create ();
9532 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9533 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9534 aarch64_reg_hsh
= str_htab_create ();
9535 aarch64_barrier_opt_hsh
= str_htab_create ();
9536 aarch64_nzcv_hsh
= str_htab_create ();
9537 aarch64_pldop_hsh
= str_htab_create ();
9538 aarch64_hint_opt_hsh
= str_htab_create ();
9540 fill_instruction_hash_table ();
9542 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9543 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9544 (void *) (aarch64_sys_regs
+ i
));
9546 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9547 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9548 aarch64_pstatefields
[i
].name
,
9549 (void *) (aarch64_pstatefields
+ i
));
9551 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9552 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9553 aarch64_sys_regs_ic
[i
].name
,
9554 (void *) (aarch64_sys_regs_ic
+ i
));
9556 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9557 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9558 aarch64_sys_regs_dc
[i
].name
,
9559 (void *) (aarch64_sys_regs_dc
+ i
));
9561 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9562 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9563 aarch64_sys_regs_at
[i
].name
,
9564 (void *) (aarch64_sys_regs_at
+ i
));
9566 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9567 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9568 aarch64_sys_regs_tlbi
[i
].name
,
9569 (void *) (aarch64_sys_regs_tlbi
+ i
));
9571 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9572 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9573 aarch64_sys_regs_sr
[i
].name
,
9574 (void *) (aarch64_sys_regs_sr
+ i
));
9576 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9577 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9578 (void *) (reg_names
+ i
));
9580 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9581 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9582 (void *) (nzcv_names
+ i
));
9584 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9586 const char *name
= aarch64_operand_modifiers
[i
].name
;
9587 checked_hash_insert (aarch64_shift_hsh
, name
,
9588 (void *) (aarch64_operand_modifiers
+ i
));
9589 /* Also hash the name in the upper case. */
9590 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9591 (void *) (aarch64_operand_modifiers
+ i
));
9594 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9597 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9598 the same condition code. */
9599 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9601 const char *name
= aarch64_conds
[i
].names
[j
];
9604 checked_hash_insert (aarch64_cond_hsh
, name
,
9605 (void *) (aarch64_conds
+ i
));
9606 /* Also hash the name in the upper case. */
9607 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9608 (void *) (aarch64_conds
+ i
));
9612 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9614 const char *name
= aarch64_barrier_options
[i
].name
;
9615 /* Skip xx00 - the unallocated values of option. */
9618 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9619 (void *) (aarch64_barrier_options
+ i
));
9620 /* Also hash the name in the upper case. */
9621 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9622 (void *) (aarch64_barrier_options
+ i
));
9625 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9627 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9628 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9629 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9630 /* Also hash the name in the upper case. */
9631 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9632 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9635 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9637 const char* name
= aarch64_prfops
[i
].name
;
9638 /* Skip the unallocated hint encodings. */
9641 checked_hash_insert (aarch64_pldop_hsh
, name
,
9642 (void *) (aarch64_prfops
+ i
));
9643 /* Also hash the name in the upper case. */
9644 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9645 (void *) (aarch64_prfops
+ i
));
9648 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9650 const char* name
= aarch64_hint_options
[i
].name
;
9651 const char* upper_name
= get_upper_str(name
);
9653 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9654 (void *) (aarch64_hint_options
+ i
));
9656 /* Also hash the name in the upper case if not the same. */
9657 if (strcmp (name
, upper_name
) != 0)
9658 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9659 (void *) (aarch64_hint_options
+ i
));
9662 /* Set the cpu variant based on the command-line options. */
9664 mcpu_cpu_opt
= march_cpu_opt
;
9667 mcpu_cpu_opt
= &cpu_default
;
9669 cpu_variant
= *mcpu_cpu_opt
;
9671 /* Record the CPU type. */
9673 mach
= bfd_mach_aarch64_ilp32
;
9675 mach
= bfd_mach_aarch64_llp64
;
9677 mach
= bfd_mach_aarch64
;
9679 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9681 /* FIXME - is there a better way to do it ? */
9682 aarch64_sframe_cfa_sp_reg
= 31;
9683 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9684 aarch64_sframe_cfa_ra_reg
= 30;
9688 /* Command line processing. */
9690 const char *md_shortopts
= "m:";
9692 #ifdef AARCH64_BI_ENDIAN
9693 #define OPTION_EB (OPTION_MD_BASE + 0)
9694 #define OPTION_EL (OPTION_MD_BASE + 1)
9696 #if TARGET_BYTES_BIG_ENDIAN
9697 #define OPTION_EB (OPTION_MD_BASE + 0)
9699 #define OPTION_EL (OPTION_MD_BASE + 1)
9703 struct option md_longopts
[] = {
9705 {"EB", no_argument
, NULL
, OPTION_EB
},
9708 {"EL", no_argument
, NULL
, OPTION_EL
},
9710 {NULL
, no_argument
, NULL
, 0}
9713 size_t md_longopts_size
= sizeof (md_longopts
);
9715 struct aarch64_option_table
9717 const char *option
; /* Option name to match. */
9718 const char *help
; /* Help information. */
9719 int *var
; /* Variable to change. */
9720 int value
; /* What to change it to. */
9721 char *deprecated
; /* If non-null, print this message. */
9724 static struct aarch64_option_table aarch64_opts
[] = {
9725 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9726 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9728 #ifdef DEBUG_AARCH64
9729 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9730 #endif /* DEBUG_AARCH64 */
9731 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9733 {"mno-verbose-error", N_("do not output verbose error messages"),
9734 &verbose_error_p
, 0, NULL
},
9735 {NULL
, NULL
, NULL
, 0, NULL
}
9738 struct aarch64_cpu_option_table
9741 const aarch64_feature_set value
;
9742 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9744 const char *canonical_name
;
9747 /* This list should, at a minimum, contain all the cpu names
9748 recognized by GCC. */
9749 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9750 {"all", AARCH64_ANY
, NULL
},
9751 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9752 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9753 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9754 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9755 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9756 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9757 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9758 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9759 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9760 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9761 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9762 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9763 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9764 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9766 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9767 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9769 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9770 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9772 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9773 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9774 | AARCH64_FEATURE_DOTPROD
9775 | AARCH64_FEATURE_SSBS
),
9777 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9778 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9779 | AARCH64_FEATURE_DOTPROD
9780 | AARCH64_FEATURE_SSBS
),
9782 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9783 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9784 | AARCH64_FEATURE_DOTPROD
9785 | AARCH64_FEATURE_SSBS
),
9787 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9788 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9789 | AARCH64_FEATURE_DOTPROD
9790 | AARCH64_FEATURE_SSBS
),
9792 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9794 | AARCH64_FEATURE_RCPC
9795 | AARCH64_FEATURE_DOTPROD
9796 | AARCH64_FEATURE_SSBS
9797 | AARCH64_FEATURE_PROFILE
),
9799 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9801 | AARCH64_FEATURE_RCPC
9802 | AARCH64_FEATURE_DOTPROD
9803 | AARCH64_FEATURE_SSBS
9804 | AARCH64_FEATURE_PROFILE
),
9806 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9807 AARCH64_FEATURE_DOTPROD
9808 | AARCH64_FEATURE_F16
9809 | AARCH64_FEATURE_FLAGM
9810 | AARCH64_FEATURE_PAC
9811 | AARCH64_FEATURE_PROFILE
9812 | AARCH64_FEATURE_RCPC
9813 | AARCH64_FEATURE_SSBS
),
9815 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9816 AARCH64_FEATURE_BFLOAT16
9817 | AARCH64_FEATURE_I8MM
9818 | AARCH64_FEATURE_MEMTAG
9819 | AARCH64_FEATURE_SVE2_BITPERM
),
9821 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9822 AARCH64_FEATURE_BFLOAT16
9823 | AARCH64_FEATURE_I8MM
9824 | AARCH64_FEATURE_MEMTAG
9825 | AARCH64_FEATURE_SVE2_BITPERM
),
9827 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9828 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9829 | AARCH64_FEATURE_DOTPROD
9830 | AARCH64_FEATURE_PROFILE
),
9832 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9833 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9834 "Samsung Exynos M1"},
9835 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9836 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9837 | AARCH64_FEATURE_RDMA
),
9839 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9840 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9841 | AARCH64_FEATURE_DOTPROD
9842 | AARCH64_FEATURE_SSBS
),
9844 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9845 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9846 | AARCH64_FEATURE_DOTPROD
9847 | AARCH64_FEATURE_PROFILE
),
9849 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9850 AARCH64_FEATURE_BFLOAT16
9851 | AARCH64_FEATURE_I8MM
9852 | AARCH64_FEATURE_F16
9853 | AARCH64_FEATURE_SVE
9854 | AARCH64_FEATURE_SVE2
9855 | AARCH64_FEATURE_SVE2_BITPERM
9856 | AARCH64_FEATURE_MEMTAG
9857 | AARCH64_FEATURE_RNG
),
9859 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9860 AARCH64_FEATURE_PROFILE
9861 | AARCH64_FEATURE_CVADP
9862 | AARCH64_FEATURE_SVE
9863 | AARCH64_FEATURE_SSBS
9864 | AARCH64_FEATURE_RNG
9865 | AARCH64_FEATURE_F16
9866 | AARCH64_FEATURE_BFLOAT16
9867 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9868 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9869 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9870 | AARCH64_FEATURE_RDMA
),
9871 "Qualcomm QDF24XX"},
9872 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9873 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9874 "Qualcomm Saphira"},
9875 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9876 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9878 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9879 AARCH64_FEATURE_CRYPTO
),
9881 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9882 in earlier releases and is superseded by 'xgene1' in all
9884 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9885 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9886 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9887 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9888 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9889 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9891 | AARCH64_FEATURE_RCPC
9892 | AARCH64_FEATURE_DOTPROD
9893 | AARCH64_FEATURE_SSBS
9894 | AARCH64_FEATURE_PROFILE
),
9896 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9897 AARCH64_FEATURE_BFLOAT16
9898 | AARCH64_FEATURE_I8MM
9899 | AARCH64_FEATURE_MEMTAG
9900 | AARCH64_FEATURE_SVE2_BITPERM
),
9902 {"generic", AARCH64_ARCH_V8
, NULL
},
9904 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9907 struct aarch64_arch_option_table
9910 const aarch64_feature_set value
;
9913 /* This list should, at a minimum, contain all the architecture names
9914 recognized by GCC. */
9915 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9916 {"all", AARCH64_ANY
},
9917 {"armv8-a", AARCH64_ARCH_V8
},
9918 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9919 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9920 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9921 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9922 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9923 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9924 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9925 {"armv8.8-a", AARCH64_ARCH_V8_8
},
9926 {"armv8-r", AARCH64_ARCH_V8_R
},
9927 {"armv9-a", AARCH64_ARCH_V9
},
9928 {"armv9.1-a", AARCH64_ARCH_V9_1
},
9929 {"armv9.2-a", AARCH64_ARCH_V9_2
},
9930 {"armv9.3-a", AARCH64_ARCH_V9_3
},
9931 {NULL
, AARCH64_ARCH_NONE
}
9934 /* ISA extensions. */
9935 struct aarch64_option_cpu_value_table
9938 const aarch64_feature_set value
;
9939 const aarch64_feature_set require
; /* Feature dependencies. */
9942 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9943 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9945 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9946 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9947 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9949 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9951 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9952 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9953 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9955 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9957 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9959 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9960 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9961 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9962 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9963 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9964 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
9965 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9967 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9968 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
9969 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9971 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9972 AARCH64_FEATURE (AARCH64_FEATURE_F16
9973 | AARCH64_FEATURE_SIMD
, 0)},
9974 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9976 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9977 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9978 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9979 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9980 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9982 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9984 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9985 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9986 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9987 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9988 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9989 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9990 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9992 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9994 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9996 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9997 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9998 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9999 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10000 | AARCH64_FEATURE_SM4
, 0)},
10001 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10002 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10003 | AARCH64_FEATURE_AES
, 0)},
10004 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10005 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10006 | AARCH64_FEATURE_SHA3
, 0)},
10007 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10008 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10009 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10010 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10011 | AARCH64_FEATURE_BFLOAT16
, 0)},
10012 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10013 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10014 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10015 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10016 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10017 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10018 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10019 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10020 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10021 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10022 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10023 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10024 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10025 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10026 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10027 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10028 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10029 AARCH64_ARCH_NONE
},
10030 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10031 AARCH64_ARCH_NONE
},
10032 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10033 AARCH64_ARCH_NONE
},
10034 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10035 AARCH64_ARCH_NONE
},
10036 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10037 AARCH64_ARCH_NONE
},
10038 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10039 AARCH64_ARCH_NONE
},
10040 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10043 struct aarch64_long_option_table
10045 const char *option
; /* Substring to match. */
10046 const char *help
; /* Help information. */
10047 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10048 char *deprecated
; /* If non-null, print this message. */
10051 /* Transitive closure of features depending on set. */
10052 static aarch64_feature_set
10053 aarch64_feature_disable_set (aarch64_feature_set set
)
10055 const struct aarch64_option_cpu_value_table
*opt
;
10056 aarch64_feature_set prev
= 0;
10058 while (prev
!= set
) {
10060 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10061 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10062 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10067 /* Transitive closure of dependencies of set. */
10068 static aarch64_feature_set
10069 aarch64_feature_enable_set (aarch64_feature_set set
)
10071 const struct aarch64_option_cpu_value_table
*opt
;
10072 aarch64_feature_set prev
= 0;
10074 while (prev
!= set
) {
10076 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10077 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10078 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10084 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10087 /* We insist on extensions being added before being removed. We achieve
10088 this by using the ADDING_VALUE variable to indicate whether we are
10089 adding an extension (1) or removing it (0) and only allowing it to
10090 change in the order -1 -> 1 -> 0. */
10091 int adding_value
= -1;
10092 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10094 /* Copy the feature set, so that we can modify it. */
10095 *ext_set
= **opt_p
;
10098 while (str
!= NULL
&& *str
!= 0)
10100 const struct aarch64_option_cpu_value_table
*opt
;
10101 const char *ext
= NULL
;
10108 as_bad (_("invalid architectural extension"));
10112 ext
= strchr (++str
, '+');
10116 optlen
= ext
- str
;
10118 optlen
= strlen (str
);
10120 if (optlen
>= 2 && startswith (str
, "no"))
10122 if (adding_value
!= 0)
10127 else if (optlen
> 0)
10129 if (adding_value
== -1)
10131 else if (adding_value
!= 1)
10133 as_bad (_("must specify extensions to add before specifying "
10134 "those to remove"));
10141 as_bad (_("missing architectural extension"));
10145 gas_assert (adding_value
!= -1);
10147 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10148 if (strncmp (opt
->name
, str
, optlen
) == 0)
10150 aarch64_feature_set set
;
10152 /* Add or remove the extension. */
10155 set
= aarch64_feature_enable_set (opt
->value
);
10156 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10160 set
= aarch64_feature_disable_set (opt
->value
);
10161 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10166 if (opt
->name
== NULL
)
10168 as_bad (_("unknown architectural extension `%s'"), str
);
10179 aarch64_parse_cpu (const char *str
)
10181 const struct aarch64_cpu_option_table
*opt
;
10182 const char *ext
= strchr (str
, '+');
10186 optlen
= ext
- str
;
10188 optlen
= strlen (str
);
10192 as_bad (_("missing cpu name `%s'"), str
);
10196 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10197 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10199 mcpu_cpu_opt
= &opt
->value
;
10201 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10206 as_bad (_("unknown cpu `%s'"), str
);
10211 aarch64_parse_arch (const char *str
)
10213 const struct aarch64_arch_option_table
*opt
;
10214 const char *ext
= strchr (str
, '+');
10218 optlen
= ext
- str
;
10220 optlen
= strlen (str
);
10224 as_bad (_("missing architecture name `%s'"), str
);
10228 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10229 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10231 march_cpu_opt
= &opt
->value
;
10233 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10238 as_bad (_("unknown architecture `%s'\n"), str
);
10243 struct aarch64_option_abi_value_table
10246 enum aarch64_abi_type value
;
10249 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10251 {"ilp32", AARCH64_ABI_ILP32
},
10252 {"lp64", AARCH64_ABI_LP64
},
10254 {"llp64", AARCH64_ABI_LLP64
},
10259 aarch64_parse_abi (const char *str
)
10263 if (str
[0] == '\0')
10265 as_bad (_("missing abi name `%s'"), str
);
10269 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10270 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10272 aarch64_abi
= aarch64_abis
[i
].value
;
10276 as_bad (_("unknown abi `%s'\n"), str
);
10280 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10281 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10282 aarch64_parse_abi
, NULL
},
10283 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10284 aarch64_parse_cpu
, NULL
},
10285 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10286 aarch64_parse_arch
, NULL
},
10287 {NULL
, NULL
, 0, NULL
}
10291 md_parse_option (int c
, const char *arg
)
10293 struct aarch64_option_table
*opt
;
10294 struct aarch64_long_option_table
*lopt
;
10300 target_big_endian
= 1;
10306 target_big_endian
= 0;
10311 /* Listing option. Just ignore these, we don't support additional
10316 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10318 if (c
== opt
->option
[0]
10319 && ((arg
== NULL
&& opt
->option
[1] == 0)
10320 || streq (arg
, opt
->option
+ 1)))
10322 /* If the option is deprecated, tell the user. */
10323 if (opt
->deprecated
!= NULL
)
10324 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10325 arg
? arg
: "", _(opt
->deprecated
));
10327 if (opt
->var
!= NULL
)
10328 *opt
->var
= opt
->value
;
10334 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10336 /* These options are expected to have an argument. */
10337 if (c
== lopt
->option
[0]
10339 && startswith (arg
, lopt
->option
+ 1))
10341 /* If the option is deprecated, tell the user. */
10342 if (lopt
->deprecated
!= NULL
)
10343 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10344 _(lopt
->deprecated
));
10346 /* Call the sup-option parser. */
10347 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10358 md_show_usage (FILE * fp
)
10360 struct aarch64_option_table
*opt
;
10361 struct aarch64_long_option_table
*lopt
;
10363 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10365 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10366 if (opt
->help
!= NULL
)
10367 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10369 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10370 if (lopt
->help
!= NULL
)
10371 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10375 -EB assemble code for a big-endian cpu\n"));
10380 -EL assemble code for a little-endian cpu\n"));
10384 /* Parse a .cpu directive. */
10387 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10389 const struct aarch64_cpu_option_table
*opt
;
10395 name
= input_line_pointer
;
10396 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10397 saved_char
= *input_line_pointer
;
10398 *input_line_pointer
= 0;
10400 ext
= strchr (name
, '+');
10403 optlen
= ext
- name
;
10405 optlen
= strlen (name
);
10407 /* Skip the first "all" entry. */
10408 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10409 if (strlen (opt
->name
) == optlen
10410 && strncmp (name
, opt
->name
, optlen
) == 0)
10412 mcpu_cpu_opt
= &opt
->value
;
10414 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10417 cpu_variant
= *mcpu_cpu_opt
;
10419 *input_line_pointer
= saved_char
;
10420 demand_empty_rest_of_line ();
10423 as_bad (_("unknown cpu `%s'"), name
);
10424 *input_line_pointer
= saved_char
;
10425 ignore_rest_of_line ();
10429 /* Parse a .arch directive. */
10432 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10434 const struct aarch64_arch_option_table
*opt
;
10440 name
= input_line_pointer
;
10441 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10442 saved_char
= *input_line_pointer
;
10443 *input_line_pointer
= 0;
10445 ext
= strchr (name
, '+');
10448 optlen
= ext
- name
;
10450 optlen
= strlen (name
);
10452 /* Skip the first "all" entry. */
10453 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10454 if (strlen (opt
->name
) == optlen
10455 && strncmp (name
, opt
->name
, optlen
) == 0)
10457 mcpu_cpu_opt
= &opt
->value
;
10459 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10462 cpu_variant
= *mcpu_cpu_opt
;
10464 *input_line_pointer
= saved_char
;
10465 demand_empty_rest_of_line ();
10469 as_bad (_("unknown architecture `%s'\n"), name
);
10470 *input_line_pointer
= saved_char
;
10471 ignore_rest_of_line ();
10474 /* Parse a .arch_extension directive. */
10477 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10480 char *ext
= input_line_pointer
;
10482 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10483 saved_char
= *input_line_pointer
;
10484 *input_line_pointer
= 0;
10486 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10489 cpu_variant
= *mcpu_cpu_opt
;
10491 *input_line_pointer
= saved_char
;
10492 demand_empty_rest_of_line ();
10495 /* Copy symbol information. */
10498 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10500 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10504 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10505 This is needed so AArch64 specific st_other values can be independently
10506 specified for an IFUNC resolver (that is called by the dynamic linker)
10507 and the symbol it resolves (aliased to the resolver). In particular,
10508 if a function symbol has special st_other value set via directives,
10509 then attaching an IFUNC resolver to that symbol should not override
10510 the st_other setting. Requiring the directive on the IFUNC resolver
10511 symbol would be unexpected and problematic in C code, where the two
10512 symbols appear as two independent function declarations. */
10515 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10517 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10518 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10519 /* If size is unset, copy size from src. Because we don't track whether
10520 .size has been used, we can't differentiate .size dest, 0 from the case
10521 where dest's size is unset. */
10522 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10526 destelf
->size
= XNEW (expressionS
);
10527 *destelf
->size
= *srcelf
->size
;
10529 S_SET_SIZE (dest
, S_GET_SIZE (src
));