1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* SME horizontal or vertical slice indicator, encoded in "V".
113 /* Bits for DEFINED field in vector_type_el. */
114 #define NTA_HASTYPE 1
115 #define NTA_HASINDEX 2
116 #define NTA_HASVARWIDTH 4
118 struct vector_type_el
120 enum vector_el_type type
;
121 unsigned char defined
;
126 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bool parse_operands (char *, const aarch64_opcode
*);
161 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 # define now_instr_sequence seg_info \
165 (now_seg)->tc_segment_info_data.insn_sequence
167 static struct aarch64_instr_sequence now_instr_sequence
;
170 /* Diagnostics inline function utilities.
172 These are lightweight utilities which should only be called by parse_operands
173 and other parsers. GAS processes each assembly line by parsing it against
174 instruction template(s), in the case of multiple templates (for the same
175 mnemonic name), those templates are tried one by one until one succeeds or
176 all fail. An assembly line may fail a few templates before being
177 successfully parsed; an error saved here in most cases is not a user error
178 but an error indicating the current template is not the right template.
179 Therefore it is very important that errors can be saved at a low cost during
180 the parsing; we don't want to slow down the whole parsing by recording
181 non-user errors in detail.
183 Remember that the objective is to help GAS pick up the most appropriate
184 error message in the case of multiple templates, e.g. FMOV which has 8
190 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 inst
.parsing_error
.error
= NULL
;
197 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
200 static inline const char *
201 get_error_message (void)
203 return inst
.parsing_error
.error
;
206 static inline enum aarch64_operand_error_kind
207 get_error_kind (void)
209 return inst
.parsing_error
.kind
;
213 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
215 inst
.parsing_error
.kind
= kind
;
216 inst
.parsing_error
.error
= error
;
220 set_recoverable_error (const char *error
)
222 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
225 /* Use the DESC field of the corresponding aarch64_operand entry to compose
226 the error message. */
228 set_default_error (void)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
234 set_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_first_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
247 set_fatal_syntax_error (const char *error
)
249 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
252 /* Return value for certain parsers when the parsing fails; those parsers
253 return the information of the parsed result, e.g. register number, on
255 #define PARSE_FAIL -1
257 /* This is an invalid condition code that means no conditional field is
259 #define COND_ALWAYS 0x10
263 const char *template;
270 bfd_reloc_code_real_type reloc
;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(VN) /* v[0-31] */ \
290 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
291 BASIC_REG_TYPE(PN) /* p[0-15] */ \
292 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
293 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
294 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
295 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
296 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
297 /* Typecheck: same, plus SVE registers. */ \
298 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
300 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
301 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
303 /* Typecheck: same, plus SVE registers. */ \
304 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
307 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
308 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
309 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
310 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
311 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
314 /* Typecheck: any [BHSDQ]P FP. */ \
315 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
318 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
322 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
323 be used for SVE instructions, since Zn and Pn are valid symbols \
324 in other contexts. */ \
325 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
328 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
329 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
330 | REG_TYPE(ZN) | REG_TYPE(PN)) \
331 /* Any integer register; used for error messages only. */ \
332 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
333 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
334 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
335 /* Pseudo type to mark the end of the enumerator sequence. */ \
338 #undef BASIC_REG_TYPE
339 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
343 /* Register type enumerators. */
344 typedef enum aarch64_reg_type_
346 /* A list of REG_TYPE_*. */
350 #undef BASIC_REG_TYPE
351 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
353 #define REG_TYPE(T) (1 << REG_TYPE_##T)
354 #undef MULTI_REG_TYPE
355 #define MULTI_REG_TYPE(T,V) V,
357 /* Structure for a hash table entry for a register. */
361 unsigned char number
;
362 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
363 unsigned char builtin
;
366 /* Values indexed by aarch64_reg_type to assist the type checking. */
367 static const unsigned reg_type_masks
[] =
372 #undef BASIC_REG_TYPE
374 #undef MULTI_REG_TYPE
375 #undef AARCH64_REG_TYPES
377 /* Diagnostics used when we don't get a register of the expected type.
378 Note: this has to synchronized with aarch64_reg_type definitions
381 get_reg_expected_msg (aarch64_reg_type reg_type
)
388 msg
= N_("integer 32-bit register expected");
391 msg
= N_("integer 64-bit register expected");
394 msg
= N_("integer register expected");
396 case REG_TYPE_R64_SP
:
397 msg
= N_("64-bit integer or SP register expected");
399 case REG_TYPE_SVE_BASE
:
400 msg
= N_("base register expected");
403 msg
= N_("integer or zero register expected");
405 case REG_TYPE_SVE_OFFSET
:
406 msg
= N_("offset register expected");
409 msg
= N_("integer or SP register expected");
411 case REG_TYPE_R_Z_SP
:
412 msg
= N_("integer, zero or SP register expected");
415 msg
= N_("8-bit SIMD scalar register expected");
418 msg
= N_("16-bit SIMD scalar or floating-point half precision "
419 "register expected");
422 msg
= N_("32-bit SIMD scalar or floating-point single precision "
423 "register expected");
426 msg
= N_("64-bit SIMD scalar or floating-point double precision "
427 "register expected");
430 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
431 "register expected");
433 case REG_TYPE_R_Z_BHSDQ_V
:
434 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
435 msg
= N_("register expected");
437 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
438 msg
= N_("SIMD scalar or floating-point register expected");
440 case REG_TYPE_VN
: /* any V reg */
441 msg
= N_("vector register expected");
444 msg
= N_("SVE vector register expected");
447 msg
= N_("SVE predicate register expected");
450 as_fatal (_("invalid register type %d"), reg_type
);
455 /* Some well known registers that we refer to directly elsewhere. */
459 /* Instructions take 4 bytes in the object file. */
462 static htab_t aarch64_ops_hsh
;
463 static htab_t aarch64_cond_hsh
;
464 static htab_t aarch64_shift_hsh
;
465 static htab_t aarch64_sys_regs_hsh
;
466 static htab_t aarch64_pstatefield_hsh
;
467 static htab_t aarch64_sys_regs_ic_hsh
;
468 static htab_t aarch64_sys_regs_dc_hsh
;
469 static htab_t aarch64_sys_regs_at_hsh
;
470 static htab_t aarch64_sys_regs_tlbi_hsh
;
471 static htab_t aarch64_sys_regs_sr_hsh
;
472 static htab_t aarch64_reg_hsh
;
473 static htab_t aarch64_barrier_opt_hsh
;
474 static htab_t aarch64_nzcv_hsh
;
475 static htab_t aarch64_pldop_hsh
;
476 static htab_t aarch64_hint_opt_hsh
;
478 /* Stuff needed to resolve the label ambiguity
487 static symbolS
*last_label_seen
;
489 /* Literal pool structure. Held on a per-section
490 and per-sub-section basis. */
492 #define MAX_LITERAL_POOL_SIZE 1024
493 typedef struct literal_expression
496 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
497 LITTLENUM_TYPE
* bignum
;
498 } literal_expression
;
500 typedef struct literal_pool
502 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
503 unsigned int next_free_entry
;
509 struct literal_pool
*next
;
512 /* Pointer to a linked list of literal pools. */
513 static literal_pool
*list_of_pools
= NULL
;
517 /* This array holds the chars that always start a comment. If the
518 pre-processor is disabled, these aren't very useful. */
519 const char comment_chars
[] = "";
521 /* This array holds the chars that only start a comment at the beginning of
522 a line. If the line seems to have the form '# 123 filename'
523 .line and .file directives will appear in the pre-processed output. */
524 /* Note that input_file.c hand checks for '#' at the beginning of the
525 first line of the input file. This is because the compiler outputs
526 #NO_APP at the beginning of its output. */
527 /* Also note that comments like this one will always work. */
528 const char line_comment_chars
[] = "#";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant
533 from exp in floating point numbers. */
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant. */
540 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
542 /* Prefix character that indicates the start of an immediate value. */
543 #define is_immediate_prefix(C) ((C) == '#')
545 /* Separator character handling. */
547 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
550 skip_past_char (char **str
, char c
)
561 #define skip_past_comma(str) skip_past_char (str, ',')
563 /* Arithmetic expressions (possibly involving symbols). */
565 static bool in_aarch64_get_expression
= false;
567 /* Third argument to aarch64_get_expression. */
568 #define GE_NO_PREFIX false
569 #define GE_OPT_PREFIX true
571 /* Fourth argument to aarch64_get_expression. */
572 #define ALLOW_ABSENT false
573 #define REJECT_ABSENT true
575 /* Fifth argument to aarch64_get_expression. */
576 #define NORMAL_RESOLUTION false
578 /* Return TRUE if the string pointed by *STR is successfully parsed
579 as an valid expression; *EP will be filled with the information of
580 such an expression. Otherwise return FALSE.
582 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
583 If REJECT_ABSENT is true then trat missing expressions as an error.
584 If DEFER_RESOLUTION is true, then do not resolve expressions against
585 constant symbols. Necessary if the expression is part of a fixup
586 that uses a reloc that must be emitted. */
589 aarch64_get_expression (expressionS
* ep
,
591 bool allow_immediate_prefix
,
593 bool defer_resolution
)
597 bool prefix_present
= false;
599 if (allow_immediate_prefix
)
601 if (is_immediate_prefix (**str
))
604 prefix_present
= true;
608 memset (ep
, 0, sizeof (expressionS
));
610 save_in
= input_line_pointer
;
611 input_line_pointer
= *str
;
612 in_aarch64_get_expression
= true;
613 if (defer_resolution
)
614 seg
= deferred_expression (ep
);
616 seg
= expression (ep
);
617 in_aarch64_get_expression
= false;
619 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
621 /* We found a bad expression in md_operand(). */
622 *str
= input_line_pointer
;
623 input_line_pointer
= save_in
;
624 if (prefix_present
&& ! error_p ())
625 set_fatal_syntax_error (_("bad expression"));
627 set_first_syntax_error (_("bad expression"));
632 if (seg
!= absolute_section
633 && seg
!= text_section
634 && seg
!= data_section
635 && seg
!= bss_section
636 && seg
!= undefined_section
)
638 set_syntax_error (_("bad segment"));
639 *str
= input_line_pointer
;
640 input_line_pointer
= save_in
;
647 *str
= input_line_pointer
;
648 input_line_pointer
= save_in
;
652 /* Turn a string in input_line_pointer into a floating point constant
653 of type TYPE, and store the appropriate bytes in *LITP. The number
654 of LITTLENUMS emitted is stored in *SIZEP. An error message is
655 returned, or NULL on OK. */
658 md_atof (int type
, char *litP
, int *sizeP
)
660 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
663 /* We handle all bad expressions here, so that we can report the faulty
664 instruction in the error message. */
666 md_operand (expressionS
* exp
)
668 if (in_aarch64_get_expression
)
669 exp
->X_op
= O_illegal
;
672 /* Immediate values. */
674 /* Errors may be set multiple times during parsing or bit encoding
675 (particularly in the Neon bits), but usually the earliest error which is set
676 will be the most meaningful. Avoid overwriting it with later (cascading)
677 errors by calling this function. */
680 first_error (const char *error
)
683 set_syntax_error (error
);
686 /* Similar to first_error, but this function accepts formatted error
689 first_error_fmt (const char *format
, ...)
694 /* N.B. this single buffer will not cause error messages for different
695 instructions to pollute each other; this is because at the end of
696 processing of each assembly line, error message if any will be
697 collected by as_bad. */
698 static char buffer
[size
];
702 int ret ATTRIBUTE_UNUSED
;
703 va_start (args
, format
);
704 ret
= vsnprintf (buffer
, size
, format
, args
);
705 know (ret
<= size
- 1 && ret
>= 0);
707 set_syntax_error (buffer
);
711 /* Register parsing. */
713 /* Generic register parser which is called by other specialized
715 CCP points to what should be the beginning of a register name.
716 If it is indeed a valid register name, advance CCP over it and
717 return the reg_entry structure; otherwise return NULL.
718 It does not issue diagnostics. */
721 parse_reg (char **ccp
)
727 #ifdef REGISTER_PREFIX
728 if (*start
!= REGISTER_PREFIX
)
734 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
739 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
741 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
750 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
753 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
755 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
758 /* Try to parse a base or offset register. Allow SVE base and offset
759 registers if REG_TYPE includes SVE registers. Return the register
760 entry on success, setting *QUALIFIER to the register qualifier.
761 Return null otherwise.
763 Note that this function does not issue any diagnostics. */
765 static const reg_entry
*
766 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
767 aarch64_opnd_qualifier_t
*qualifier
)
770 const reg_entry
*reg
= parse_reg (&str
);
780 *qualifier
= AARCH64_OPND_QLF_W
;
786 *qualifier
= AARCH64_OPND_QLF_X
;
790 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
793 switch (TOLOWER (str
[1]))
796 *qualifier
= AARCH64_OPND_QLF_S_S
;
799 *qualifier
= AARCH64_OPND_QLF_S_D
;
816 /* Try to parse a base or offset register. Return the register entry
817 on success, setting *QUALIFIER to the register qualifier. Return null
820 Note that this function does not issue any diagnostics. */
822 static const reg_entry
*
823 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
825 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
828 /* Parse the qualifier of a vector register or vector element of type
829 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
830 succeeds; otherwise return FALSE.
832 Accept only one occurrence of:
833 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
836 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
837 struct vector_type_el
*parsed_type
, char **str
)
841 unsigned element_size
;
842 enum vector_el_type type
;
845 gas_assert (*ptr
== '.');
848 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
853 width
= strtoul (ptr
, &ptr
, 10);
854 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
856 first_error_fmt (_("bad size %d in vector width specifier"), width
);
861 switch (TOLOWER (*ptr
))
880 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
889 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
891 first_error (_("missing element size"));
894 if (width
!= 0 && width
* element_size
!= 64
895 && width
* element_size
!= 128
896 && !(width
== 2 && element_size
== 16)
897 && !(width
== 4 && element_size
== 8))
900 ("invalid element size %d and vector size combination %c"),
906 parsed_type
->type
= type
;
907 parsed_type
->width
= width
;
914 /* *STR contains an SVE zero/merge predication suffix. Parse it into
915 *PARSED_TYPE and point *STR at the end of the suffix. */
918 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
923 gas_assert (*ptr
== '/');
925 switch (TOLOWER (*ptr
))
928 parsed_type
->type
= NT_zero
;
931 parsed_type
->type
= NT_merge
;
934 if (*ptr
!= '\0' && *ptr
!= ',')
935 first_error_fmt (_("unexpected character `%c' in predication type"),
938 first_error (_("missing predication type"));
941 parsed_type
->width
= 0;
946 /* Parse a register of the type TYPE.
948 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
949 name or the parsed register is not of TYPE.
951 Otherwise return the register number, and optionally fill in the actual
952 type of the register in *RTYPE when multiple alternatives were given, and
953 return the register shape and element index information in *TYPEINFO.
955 IN_REG_LIST should be set with TRUE if the caller is parsing a register
959 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
960 struct vector_type_el
*typeinfo
, bool in_reg_list
)
963 const reg_entry
*reg
= parse_reg (&str
);
964 struct vector_type_el atype
;
965 struct vector_type_el parsetype
;
966 bool is_typed_vecreg
= false;
969 atype
.type
= NT_invtype
;
977 set_default_error ();
981 if (! aarch64_check_reg_type (reg
, type
))
983 DEBUG_TRACE ("reg type check failed");
984 set_default_error ();
989 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
990 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
994 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
999 if (!parse_predication_for_operand (&parsetype
, &str
))
1003 /* Register if of the form Vn.[bhsdq]. */
1004 is_typed_vecreg
= true;
1006 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1008 /* The width is always variable; we don't allow an integer width
1010 gas_assert (parsetype
.width
== 0);
1011 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1013 else if (parsetype
.width
== 0)
1014 /* Expect index. In the new scheme we cannot have
1015 Vn.[bhsdq] represent a scalar. Therefore any
1016 Vn.[bhsdq] should have an index following it.
1017 Except in reglists of course. */
1018 atype
.defined
|= NTA_HASINDEX
;
1020 atype
.defined
|= NTA_HASTYPE
;
1022 atype
.type
= parsetype
.type
;
1023 atype
.width
= parsetype
.width
;
1026 if (skip_past_char (&str
, '['))
1030 /* Reject Sn[index] syntax. */
1031 if (!is_typed_vecreg
)
1033 first_error (_("this type of register can't be indexed"));
1039 first_error (_("index not allowed inside register list"));
1043 atype
.defined
|= NTA_HASINDEX
;
1045 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1048 if (exp
.X_op
!= O_constant
)
1050 first_error (_("constant expression required"));
1054 if (! skip_past_char (&str
, ']'))
1057 atype
.index
= exp
.X_add_number
;
1059 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1061 /* Indexed vector register expected. */
1062 first_error (_("indexed vector register expected"));
1066 /* A vector reg Vn should be typed or indexed. */
1067 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1069 first_error (_("invalid use of vector register"));
1085 Return the register number on success; return PARSE_FAIL otherwise.
1087 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1088 the register (e.g. NEON double or quad reg when either has been requested).
1090 If this is a NEON vector register with additional type information, fill
1091 in the struct pointed to by VECTYPE (if non-NULL).
1093 This parser does not handle register list. */
1096 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1097 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1099 struct vector_type_el atype
;
1101 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1102 /*in_reg_list= */ false);
1104 if (reg
== PARSE_FAIL
)
1116 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1120 && e1
.defined
== e2
.defined
1121 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1124 /* This function parses a list of vector registers of type TYPE.
1125 On success, it returns the parsed register list information in the
1126 following encoded format:
1128 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1129 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1131 The information of the register shape and/or index is returned in
1134 It returns PARSE_FAIL if the register list is invalid.
1136 The list contains one to four registers.
1137 Each register can be one of:
1140 All <T> should be identical.
1141 All <index> should be identical.
1142 There are restrictions on <Vt> numbers which are checked later
1143 (by reg_list_valid_p). */
1146 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1147 struct vector_type_el
*vectype
)
1151 struct vector_type_el typeinfo
, typeinfo_first
;
1157 bool expect_index
= false;
1161 set_syntax_error (_("expecting {"));
1167 typeinfo_first
.defined
= 0;
1168 typeinfo_first
.type
= NT_invtype
;
1169 typeinfo_first
.width
= -1;
1170 typeinfo_first
.index
= 0;
1179 str
++; /* skip over '-' */
1182 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1183 /*in_reg_list= */ true);
1184 if (val
== PARSE_FAIL
)
1186 set_first_syntax_error (_("invalid vector register in list"));
1190 /* reject [bhsd]n */
1191 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1193 set_first_syntax_error (_("invalid scalar register in list"));
1198 if (typeinfo
.defined
& NTA_HASINDEX
)
1199 expect_index
= true;
1203 if (val
< val_range
)
1205 set_first_syntax_error
1206 (_("invalid range in vector register list"));
1215 typeinfo_first
= typeinfo
;
1216 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1218 set_first_syntax_error
1219 (_("type mismatch in vector register list"));
1224 for (i
= val_range
; i
<= val
; i
++)
1226 ret_val
|= i
<< (5 * nb_regs
);
1231 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1233 skip_whitespace (str
);
1236 set_first_syntax_error (_("end of vector register list not found"));
1241 skip_whitespace (str
);
1245 if (skip_past_char (&str
, '['))
1249 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1251 if (exp
.X_op
!= O_constant
)
1253 set_first_syntax_error (_("constant expression required."));
1256 if (! skip_past_char (&str
, ']'))
1259 typeinfo_first
.index
= exp
.X_add_number
;
1263 set_first_syntax_error (_("expected index"));
1270 set_first_syntax_error (_("too many registers in vector register list"));
1273 else if (nb_regs
== 0)
1275 set_first_syntax_error (_("empty vector register list"));
1281 *vectype
= typeinfo_first
;
1283 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1286 /* Directives: register aliases. */
1289 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1294 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1297 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1300 /* Only warn about a redefinition if it's not defined as the
1302 else if (new->number
!= number
|| new->type
!= type
)
1303 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1308 name
= xstrdup (str
);
1309 new = XNEW (reg_entry
);
1312 new->number
= number
;
1314 new->builtin
= false;
1316 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1321 /* Look for the .req directive. This is of the form:
1323 new_register_name .req existing_register_name
1325 If we find one, or if it looks sufficiently like one that we want to
1326 handle any error here, return TRUE. Otherwise return FALSE. */
1329 create_register_alias (char *newname
, char *p
)
1331 const reg_entry
*old
;
1332 char *oldname
, *nbuf
;
1335 /* The input scrubber ensures that whitespace after the mnemonic is
1336 collapsed to single spaces. */
1338 if (!startswith (oldname
, " .req "))
1342 if (*oldname
== '\0')
1345 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1348 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1352 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1353 the desired alias name, and p points to its end. If not, then
1354 the desired alias name is in the global original_case_string. */
1355 #ifdef TC_CASE_SENSITIVE
1358 newname
= original_case_string
;
1359 nlen
= strlen (newname
);
1362 nbuf
= xmemdup0 (newname
, nlen
);
1364 /* Create aliases under the new name as stated; an all-lowercase
1365 version of the new name; and an all-uppercase version of the new
1367 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1374 /* If this attempt to create an additional alias fails, do not bother
1375 trying to create the all-lower case alias. We will fail and issue
1376 a second, duplicate error message. This situation arises when the
1377 programmer does something like:
1380 The second .req creates the "Foo" alias but then fails to create
1381 the artificial FOO alias because it has already been created by the
1383 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1390 for (p
= nbuf
; *p
; p
++)
1393 if (strncmp (nbuf
, newname
, nlen
))
1394 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1401 /* Should never be called, as .req goes between the alias and the
1402 register name, not at the beginning of the line. */
1404 s_req (int a ATTRIBUTE_UNUSED
)
1406 as_bad (_("invalid syntax for .req directive"));
1409 /* The .unreq directive deletes an alias which was previously defined
1410 by .req. For example:
1416 s_unreq (int a ATTRIBUTE_UNUSED
)
1421 name
= input_line_pointer
;
1423 while (*input_line_pointer
!= 0
1424 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1425 ++input_line_pointer
;
1427 saved_char
= *input_line_pointer
;
1428 *input_line_pointer
= 0;
1431 as_bad (_("invalid syntax for .unreq directive"));
1434 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1437 as_bad (_("unknown register alias '%s'"), name
);
1438 else if (reg
->builtin
)
1439 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1446 str_hash_delete (aarch64_reg_hsh
, name
);
1447 free ((char *) reg
->name
);
1450 /* Also locate the all upper case and all lower case versions.
1451 Do not complain if we cannot find one or the other as it
1452 was probably deleted above. */
1454 nbuf
= strdup (name
);
1455 for (p
= nbuf
; *p
; p
++)
1457 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1460 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1461 free ((char *) reg
->name
);
1465 for (p
= nbuf
; *p
; p
++)
1467 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1470 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1471 free ((char *) reg
->name
);
1479 *input_line_pointer
= saved_char
;
1480 demand_empty_rest_of_line ();
1483 /* Directives: Instruction set selection. */
1486 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1487 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1488 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1489 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1491 /* Create a new mapping symbol for the transition to STATE. */
1494 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1497 const char *symname
;
1504 type
= BSF_NO_FLAGS
;
1508 type
= BSF_NO_FLAGS
;
1514 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1515 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1517 /* Save the mapping symbols for future reference. Also check that
1518 we do not place two mapping symbols at the same offset within a
1519 frag. We'll handle overlap between frags in
1520 check_mapping_symbols.
1522 If .fill or other data filling directive generates zero sized data,
1523 the mapping symbol for the following code will have the same value
1524 as the one generated for the data filling directive. In this case,
1525 we replace the old symbol with the new one at the same address. */
1528 if (frag
->tc_frag_data
.first_map
!= NULL
)
1530 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1531 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1534 frag
->tc_frag_data
.first_map
= symbolP
;
1536 if (frag
->tc_frag_data
.last_map
!= NULL
)
1538 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1539 S_GET_VALUE (symbolP
));
1540 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1541 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1544 frag
->tc_frag_data
.last_map
= symbolP
;
1547 /* We must sometimes convert a region marked as code to data during
1548 code alignment, if an odd number of bytes have to be padded. The
1549 code mapping symbol is pushed to an aligned address. */
1552 insert_data_mapping_symbol (enum mstate state
,
1553 valueT value
, fragS
* frag
, offsetT bytes
)
1555 /* If there was already a mapping symbol, remove it. */
1556 if (frag
->tc_frag_data
.last_map
!= NULL
1557 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1558 frag
->fr_address
+ value
)
1560 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1564 know (frag
->tc_frag_data
.first_map
== symp
);
1565 frag
->tc_frag_data
.first_map
= NULL
;
1567 frag
->tc_frag_data
.last_map
= NULL
;
1568 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1571 make_mapping_symbol (MAP_DATA
, value
, frag
);
1572 make_mapping_symbol (state
, value
+ bytes
, frag
);
1575 static void mapping_state_2 (enum mstate state
, int max_chars
);
1577 /* Set the mapping state to STATE. Only call this when about to
1578 emit some STATE bytes to the file. */
1581 mapping_state (enum mstate state
)
1583 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1585 if (state
== MAP_INSN
)
1586 /* AArch64 instructions require 4-byte alignment. When emitting
1587 instructions into any section, record the appropriate section
1589 record_alignment (now_seg
, 2);
1591 if (mapstate
== state
)
1592 /* The mapping symbol has already been emitted.
1593 There is nothing else to do. */
1596 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1597 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1598 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1599 evaluated later in the next else. */
1601 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1603 /* Only add the symbol if the offset is > 0:
1604 if we're at the first frag, check it's size > 0;
1605 if we're not at the first frag, then for sure
1606 the offset is > 0. */
1607 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1608 const int add_symbol
= (frag_now
!= frag_first
)
1609 || (frag_now_fix () > 0);
1612 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1616 mapping_state_2 (state
, 0);
1619 /* Same as mapping_state, but MAX_CHARS bytes have already been
1620 allocated. Put the mapping symbol that far back. */
1623 mapping_state_2 (enum mstate state
, int max_chars
)
1625 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1627 if (!SEG_NORMAL (now_seg
))
1630 if (mapstate
== state
)
1631 /* The mapping symbol has already been emitted.
1632 There is nothing else to do. */
1635 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1636 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1639 #define mapping_state(x) /* nothing */
1640 #define mapping_state_2(x, y) /* nothing */
1643 /* Directives: sectioning and alignment. */
1646 s_bss (int ignore ATTRIBUTE_UNUSED
)
1648 /* We don't support putting frags in the BSS segment, we fake it by
1649 marking in_bss, then looking at s_skip for clues. */
1650 subseg_set (bss_section
, 0);
1651 demand_empty_rest_of_line ();
1652 mapping_state (MAP_DATA
);
1656 s_even (int ignore ATTRIBUTE_UNUSED
)
1658 /* Never make frag if expect extra pass. */
1660 frag_align (1, 0, 0);
1662 record_alignment (now_seg
, 1);
1664 demand_empty_rest_of_line ();
1667 /* Directives: Literal pools. */
1669 static literal_pool
*
1670 find_literal_pool (int size
)
1674 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1676 if (pool
->section
== now_seg
1677 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1684 static literal_pool
*
1685 find_or_make_literal_pool (int size
)
1687 /* Next literal pool ID number. */
1688 static unsigned int latest_pool_num
= 1;
1691 pool
= find_literal_pool (size
);
1695 /* Create a new pool. */
1696 pool
= XNEW (literal_pool
);
1700 /* Currently we always put the literal pool in the current text
1701 section. If we were generating "small" model code where we
1702 knew that all code and initialised data was within 1MB then
1703 we could output literals to mergeable, read-only data
1706 pool
->next_free_entry
= 0;
1707 pool
->section
= now_seg
;
1708 pool
->sub_section
= now_subseg
;
1710 pool
->next
= list_of_pools
;
1711 pool
->symbol
= NULL
;
1713 /* Add it to the list. */
1714 list_of_pools
= pool
;
1717 /* New pools, and emptied pools, will have a NULL symbol. */
1718 if (pool
->symbol
== NULL
)
1720 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1721 &zero_address_frag
, 0);
1722 pool
->id
= latest_pool_num
++;
1729 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1730 Return TRUE on success, otherwise return FALSE. */
1732 add_to_lit_pool (expressionS
*exp
, int size
)
1737 pool
= find_or_make_literal_pool (size
);
1739 /* Check if this literal value is already in the pool. */
1740 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1742 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1744 if ((litexp
->X_op
== exp
->X_op
)
1745 && (exp
->X_op
== O_constant
)
1746 && (litexp
->X_add_number
== exp
->X_add_number
)
1747 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1750 if ((litexp
->X_op
== exp
->X_op
)
1751 && (exp
->X_op
== O_symbol
)
1752 && (litexp
->X_add_number
== exp
->X_add_number
)
1753 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1754 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1758 /* Do we need to create a new entry? */
1759 if (entry
== pool
->next_free_entry
)
1761 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1763 set_syntax_error (_("literal pool overflow"));
1767 pool
->literals
[entry
].exp
= *exp
;
1768 pool
->next_free_entry
+= 1;
1769 if (exp
->X_op
== O_big
)
1771 /* PR 16688: Bignums are held in a single global array. We must
1772 copy and preserve that value now, before it is overwritten. */
1773 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1775 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1776 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1779 pool
->literals
[entry
].bignum
= NULL
;
1782 exp
->X_op
= O_symbol
;
1783 exp
->X_add_number
= ((int) entry
) * size
;
1784 exp
->X_add_symbol
= pool
->symbol
;
1789 /* Can't use symbol_new here, so have to create a symbol and then at
1790 a later date assign it a value. That's what these functions do. */
1793 symbol_locate (symbolS
* symbolP
,
1794 const char *name
,/* It is copied, the caller can modify. */
1795 segT segment
, /* Segment identifier (SEG_<something>). */
1796 valueT valu
, /* Symbol value. */
1797 fragS
* frag
) /* Associated fragment. */
1800 char *preserved_copy_of_name
;
1802 name_length
= strlen (name
) + 1; /* +1 for \0. */
1803 obstack_grow (¬es
, name
, name_length
);
1804 preserved_copy_of_name
= obstack_finish (¬es
);
1806 #ifdef tc_canonicalize_symbol_name
1807 preserved_copy_of_name
=
1808 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1811 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1813 S_SET_SEGMENT (symbolP
, segment
);
1814 S_SET_VALUE (symbolP
, valu
);
1815 symbol_clear_list_pointers (symbolP
);
1817 symbol_set_frag (symbolP
, frag
);
1819 /* Link to end of symbol chain. */
1821 extern int symbol_table_frozen
;
1823 if (symbol_table_frozen
)
1827 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1829 obj_symbol_new_hook (symbolP
);
1831 #ifdef tc_symbol_new_hook
1832 tc_symbol_new_hook (symbolP
);
1836 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1837 #endif /* DEBUG_SYMS */
1842 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1849 for (align
= 2; align
<= 4; align
++)
1851 int size
= 1 << align
;
1853 pool
= find_literal_pool (size
);
1854 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1857 /* Align pool as you have word accesses.
1858 Only make a frag if we have to. */
1860 frag_align (align
, 0, 0);
1862 mapping_state (MAP_DATA
);
1864 record_alignment (now_seg
, align
);
1866 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1868 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1869 (valueT
) frag_now_fix (), frag_now
);
1870 symbol_table_insert (pool
->symbol
);
1872 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1874 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1876 if (exp
->X_op
== O_big
)
1878 /* PR 16688: Restore the global bignum value. */
1879 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1880 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1881 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1884 /* First output the expression in the instruction to the pool. */
1885 emit_expr (exp
, size
); /* .word|.xword */
1887 if (exp
->X_op
== O_big
)
1889 free (pool
->literals
[entry
].bignum
);
1890 pool
->literals
[entry
].bignum
= NULL
;
1894 /* Mark the pool as empty. */
1895 pool
->next_free_entry
= 0;
1896 pool
->symbol
= NULL
;
1901 /* Forward declarations for functions below, in the MD interface
1903 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1904 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1906 /* Directives: Data. */
1907 /* N.B. the support for relocation suffix in this directive needs to be
1908 implemented properly. */
1911 s_aarch64_elf_cons (int nbytes
)
1915 #ifdef md_flush_pending_output
1916 md_flush_pending_output ();
1919 if (is_it_end_of_statement ())
1921 demand_empty_rest_of_line ();
1925 #ifdef md_cons_align
1926 md_cons_align (nbytes
);
1929 mapping_state (MAP_DATA
);
1932 struct reloc_table_entry
*reloc
;
1936 if (exp
.X_op
!= O_symbol
)
1937 emit_expr (&exp
, (unsigned int) nbytes
);
1940 skip_past_char (&input_line_pointer
, '#');
1941 if (skip_past_char (&input_line_pointer
, ':'))
1943 reloc
= find_reloc_table_entry (&input_line_pointer
);
1945 as_bad (_("unrecognized relocation suffix"));
1947 as_bad (_("unimplemented relocation suffix"));
1948 ignore_rest_of_line ();
1952 emit_expr (&exp
, (unsigned int) nbytes
);
1955 while (*input_line_pointer
++ == ',');
1957 /* Put terminator back into stream. */
1958 input_line_pointer
--;
1959 demand_empty_rest_of_line ();
1962 /* Mark symbol that it follows a variant PCS convention. */
1965 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1971 elf_symbol_type
*elfsym
;
1973 c
= get_symbol_name (&name
);
1975 as_bad (_("Missing symbol name in directive"));
1976 sym
= symbol_find_or_make (name
);
1977 restore_line_pointer (c
);
1978 demand_empty_rest_of_line ();
1979 bfdsym
= symbol_get_bfdsym (sym
);
1980 elfsym
= elf_symbol_from (bfdsym
);
1981 gas_assert (elfsym
);
1982 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1984 #endif /* OBJ_ELF */
1986 /* Output a 32-bit word, but mark as an instruction. */
1989 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1993 #ifdef md_flush_pending_output
1994 md_flush_pending_output ();
1997 if (is_it_end_of_statement ())
1999 demand_empty_rest_of_line ();
2003 /* Sections are assumed to start aligned. In executable section, there is no
2004 MAP_DATA symbol pending. So we only align the address during
2005 MAP_DATA --> MAP_INSN transition.
2006 For other sections, this is not guaranteed. */
2007 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2008 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2009 frag_align_code (2, 0);
2012 mapping_state (MAP_INSN
);
2018 if (exp
.X_op
!= O_constant
)
2020 as_bad (_("constant expression required"));
2021 ignore_rest_of_line ();
2025 if (target_big_endian
)
2027 unsigned int val
= exp
.X_add_number
;
2028 exp
.X_add_number
= SWAP_32 (val
);
2030 emit_expr (&exp
, 4);
2032 while (*input_line_pointer
++ == ',');
2034 /* Put terminator back into stream. */
2035 input_line_pointer
--;
2036 demand_empty_rest_of_line ();
2040 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2042 demand_empty_rest_of_line ();
2043 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2044 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2048 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2051 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2057 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2058 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2060 demand_empty_rest_of_line ();
2063 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2066 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2070 /* Since we're just labelling the code, there's no need to define a
2073 /* Make sure there is enough room in this frag for the following
2074 blr. This trick only works if the blr follows immediately after
2075 the .tlsdesc directive. */
2077 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2078 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2080 demand_empty_rest_of_line ();
2083 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2086 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2092 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2093 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2095 demand_empty_rest_of_line ();
2097 #endif /* OBJ_ELF */
2099 static void s_aarch64_arch (int);
2100 static void s_aarch64_cpu (int);
2101 static void s_aarch64_arch_extension (int);
2103 /* This table describes all the machine specific pseudo-ops the assembler
2104 has to support. The fields are:
2105 pseudo-op name without dot
2106 function to call to execute this pseudo-op
2107 Integer arg to pass to the function. */
2109 const pseudo_typeS md_pseudo_table
[] = {
2110 /* Never called because '.req' does not start a line. */
2112 {"unreq", s_unreq
, 0},
2114 {"even", s_even
, 0},
2115 {"ltorg", s_ltorg
, 0},
2116 {"pool", s_ltorg
, 0},
2117 {"cpu", s_aarch64_cpu
, 0},
2118 {"arch", s_aarch64_arch
, 0},
2119 {"arch_extension", s_aarch64_arch_extension
, 0},
2120 {"inst", s_aarch64_inst
, 0},
2121 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2123 {"tlsdescadd", s_tlsdescadd
, 0},
2124 {"tlsdesccall", s_tlsdesccall
, 0},
2125 {"tlsdescldr", s_tlsdescldr
, 0},
2126 {"word", s_aarch64_elf_cons
, 4},
2127 {"long", s_aarch64_elf_cons
, 4},
2128 {"xword", s_aarch64_elf_cons
, 8},
2129 {"dword", s_aarch64_elf_cons
, 8},
2130 {"variant_pcs", s_variant_pcs
, 0},
2132 {"float16", float_cons
, 'h'},
2133 {"bfloat16", float_cons
, 'b'},
2138 /* Check whether STR points to a register name followed by a comma or the
2139 end of line; REG_TYPE indicates which register types are checked
2140 against. Return TRUE if STR is such a register name; otherwise return
2141 FALSE. The function does not intend to produce any diagnostics, but since
2142 the register parser aarch64_reg_parse, which is called by this function,
2143 does produce diagnostics, we call clear_error to clear any diagnostics
2144 that may be generated by aarch64_reg_parse.
2145 Also, the function returns FALSE directly if there is any user error
2146 present at the function entry. This prevents the existing diagnostics
2147 state from being spoiled.
2148 The function currently serves parse_constant_immediate and
2149 parse_big_immediate only. */
2151 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2155 /* Prevent the diagnostics state from being spoiled. */
2159 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2161 /* Clear the parsing error that may be set by the reg parser. */
2164 if (reg
== PARSE_FAIL
)
2167 skip_whitespace (str
);
2168 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2174 /* Parser functions used exclusively in instruction operands. */
2176 /* Parse an immediate expression which may not be constant.
2178 To prevent the expression parser from pushing a register name
2179 into the symbol table as an undefined symbol, firstly a check is
2180 done to find out whether STR is a register of type REG_TYPE followed
2181 by a comma or the end of line. Return FALSE if STR is such a string. */
2184 parse_immediate_expression (char **str
, expressionS
*exp
,
2185 aarch64_reg_type reg_type
)
2187 if (reg_name_p (*str
, reg_type
))
2189 set_recoverable_error (_("immediate operand required"));
2193 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2196 if (exp
->X_op
== O_absent
)
2198 set_fatal_syntax_error (_("missing immediate expression"));
2205 /* Constant immediate-value read function for use in insn parsing.
2206 STR points to the beginning of the immediate (with the optional
2207 leading #); *VAL receives the value. REG_TYPE says which register
2208 names should be treated as registers rather than as symbolic immediates.
2210 Return TRUE on success; otherwise return FALSE. */
2213 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2217 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2220 if (exp
.X_op
!= O_constant
)
2222 set_syntax_error (_("constant expression required"));
2226 *val
= exp
.X_add_number
;
2231 encode_imm_float_bits (uint32_t imm
)
2233 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2234 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2237 /* Return TRUE if the single-precision floating-point value encoded in IMM
2238 can be expressed in the AArch64 8-bit signed floating-point format with
2239 3-bit exponent and normalized 4 bits of precision; in other words, the
2240 floating-point value must be expressable as
2241 (+/-) n / 16 * power (2, r)
2242 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2245 aarch64_imm_float_p (uint32_t imm
)
2247 /* If a single-precision floating-point value has the following bit
2248 pattern, it can be expressed in the AArch64 8-bit floating-point
2251 3 32222222 2221111111111
2252 1 09876543 21098765432109876543210
2253 n Eeeeeexx xxxx0000000000000000000
2255 where n, e and each x are either 0 or 1 independently, with
2260 /* Prepare the pattern for 'Eeeeee'. */
2261 if (((imm
>> 30) & 0x1) == 0)
2262 pattern
= 0x3e000000;
2264 pattern
= 0x40000000;
2266 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2267 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2270 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2271 as an IEEE float without any loss of precision. Store the value in
2275 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2277 /* If a double-precision floating-point value has the following bit
2278 pattern, it can be expressed in a float:
2280 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2281 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2282 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2284 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2285 if Eeee_eeee != 1111_1111
2287 where n, e, s and S are either 0 or 1 independently and where ~ is the
2291 uint32_t high32
= imm
>> 32;
2292 uint32_t low32
= imm
;
2294 /* Lower 29 bits need to be 0s. */
2295 if ((imm
& 0x1fffffff) != 0)
2298 /* Prepare the pattern for 'Eeeeeeeee'. */
2299 if (((high32
>> 30) & 0x1) == 0)
2300 pattern
= 0x38000000;
2302 pattern
= 0x40000000;
2305 if ((high32
& 0x78000000) != pattern
)
2308 /* Check Eeee_eeee != 1111_1111. */
2309 if ((high32
& 0x7ff00000) == 0x47f00000)
2312 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2313 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2314 | (low32
>> 29)); /* 3 S bits. */
2318 /* Return true if we should treat OPERAND as a double-precision
2319 floating-point operand rather than a single-precision one. */
2321 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2323 /* Check for unsuffixed SVE registers, which are allowed
2324 for LDR and STR but not in instructions that require an
2325 immediate. We get better error messages if we arbitrarily
2326 pick one size, parse the immediate normally, and then
2327 report the match failure in the normal way. */
2328 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2329 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2332 /* Parse a floating-point immediate. Return TRUE on success and return the
2333 value in *IMMED in the format of IEEE754 single-precision encoding.
2334 *CCP points to the start of the string; DP_P is TRUE when the immediate
2335 is expected to be in double-precision (N.B. this only matters when
2336 hexadecimal representation is involved). REG_TYPE says which register
2337 names should be treated as registers rather than as symbolic immediates.
2339 This routine accepts any IEEE float; it is up to the callers to reject
2343 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2344 aarch64_reg_type reg_type
)
2348 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2350 unsigned fpword
= 0;
2353 skip_past_char (&str
, '#');
2356 skip_whitespace (fpnum
);
2358 if (startswith (fpnum
, "0x"))
2360 /* Support the hexadecimal representation of the IEEE754 encoding.
2361 Double-precision is expected when DP_P is TRUE, otherwise the
2362 representation should be in single-precision. */
2363 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2368 if (!can_convert_double_to_float (val
, &fpword
))
2371 else if ((uint64_t) val
> 0xffffffff)
2378 else if (reg_name_p (str
, reg_type
))
2380 set_recoverable_error (_("immediate operand required"));
2388 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2391 /* Our FP word must be 32 bits (single-precision FP). */
2392 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2394 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2404 set_fatal_syntax_error (_("invalid floating-point constant"));
2408 /* Less-generic immediate-value read function with the possibility of loading
2409 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2412 To prevent the expression parser from pushing a register name into the
2413 symbol table as an undefined symbol, a check is firstly done to find
2414 out whether STR is a register of type REG_TYPE followed by a comma or
2415 the end of line. Return FALSE if STR is such a register. */
2418 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2422 if (reg_name_p (ptr
, reg_type
))
2424 set_syntax_error (_("immediate operand required"));
2428 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2431 if (inst
.reloc
.exp
.X_op
== O_constant
)
2432 *imm
= inst
.reloc
.exp
.X_add_number
;
2439 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2440 if NEED_LIBOPCODES is non-zero, the fixup will need
2441 assistance from the libopcodes. */
2444 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2445 const aarch64_opnd_info
*operand
,
2446 int need_libopcodes_p
)
2448 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2449 reloc
->opnd
= operand
->type
;
2450 if (need_libopcodes_p
)
2451 reloc
->need_libopcodes_p
= 1;
2454 /* Return TRUE if the instruction needs to be fixed up later internally by
2455 the GAS; otherwise return FALSE. */
2458 aarch64_gas_internal_fixup_p (void)
2460 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2463 /* Assign the immediate value to the relevant field in *OPERAND if
2464 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2465 needs an internal fixup in a later stage.
2466 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2467 IMM.VALUE that may get assigned with the constant. */
2469 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2470 aarch64_opnd_info
*operand
,
2472 int need_libopcodes_p
,
2475 if (reloc
->exp
.X_op
== O_constant
)
2478 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2480 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2481 reloc
->type
= BFD_RELOC_UNUSED
;
2485 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2486 /* Tell libopcodes to ignore this operand or not. This is helpful
2487 when one of the operands needs to be fixed up later but we need
2488 libopcodes to check the other operands. */
2489 operand
->skip
= skip_p
;
2493 /* Relocation modifiers. Each entry in the table contains the textual
2494 name for the relocation which may be placed before a symbol used as
2495 a load/store offset, or add immediate. It must be surrounded by a
2496 leading and trailing colon, for example:
2498 ldr x0, [x1, #:rello:varsym]
2499 add x0, x1, #:rello:varsym */
2501 struct reloc_table_entry
2505 bfd_reloc_code_real_type adr_type
;
2506 bfd_reloc_code_real_type adrp_type
;
2507 bfd_reloc_code_real_type movw_type
;
2508 bfd_reloc_code_real_type add_type
;
2509 bfd_reloc_code_real_type ldst_type
;
2510 bfd_reloc_code_real_type ld_literal_type
;
2513 static struct reloc_table_entry reloc_table
[] =
2515 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2520 BFD_RELOC_AARCH64_ADD_LO12
,
2521 BFD_RELOC_AARCH64_LDST_LO12
,
2524 /* Higher 21 bits of pc-relative page offset: ADRP */
2527 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2533 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2536 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2542 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2546 BFD_RELOC_AARCH64_MOVW_G0
,
2551 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2555 BFD_RELOC_AARCH64_MOVW_G0_S
,
2560 /* Less significant bits 0-15 of address/value: MOVK, no check */
2564 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2569 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2573 BFD_RELOC_AARCH64_MOVW_G1
,
2578 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2582 BFD_RELOC_AARCH64_MOVW_G1_S
,
2587 /* Less significant bits 16-31 of address/value: MOVK, no check */
2591 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2596 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2600 BFD_RELOC_AARCH64_MOVW_G2
,
2605 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2609 BFD_RELOC_AARCH64_MOVW_G2_S
,
2614 /* Less significant bits 32-47 of address/value: MOVK, no check */
2618 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2623 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2627 BFD_RELOC_AARCH64_MOVW_G3
,
2632 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2636 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2641 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2645 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2650 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2654 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2659 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2663 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2668 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2672 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2677 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2681 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2686 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2690 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2695 /* Get to the page containing GOT entry for a symbol. */
2698 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2702 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2704 /* 12 bit offset into the page containing GOT entry for that symbol. */
2710 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2713 /* 0-15 bits of address/value: MOVk, no check. */
2717 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2722 /* Most significant bits 16-31 of address/value: MOVZ. */
2726 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2731 /* 15 bit offset into the page containing GOT entry for that symbol. */
2737 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2740 /* Get to the page containing GOT TLS entry for a symbol */
2741 {"gottprel_g0_nc", 0,
2744 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2749 /* Get to the page containing GOT TLS entry for a symbol */
2753 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2758 /* Get to the page containing GOT TLS entry for a symbol */
2760 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2761 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2767 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2772 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2776 /* Lower 16 bits address/value: MOVk. */
2780 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2785 /* Most significant bits 16-31 of address/value: MOVZ. */
2789 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2794 /* Get to the page containing GOT TLS entry for a symbol */
2796 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2797 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2801 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2803 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2808 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2809 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2812 /* Get to the page containing GOT TLS entry for a symbol.
2813 The same as GD, we allocate two consecutive GOT slots
2814 for module index and module offset, the only difference
2815 with GD is the module offset should be initialized to
2816 zero without any outstanding runtime relocation. */
2818 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2819 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2825 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2826 {"tlsldm_lo12_nc", 0,
2830 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2834 /* 12 bit offset into the module TLS base address. */
2839 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2840 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2843 /* Same as dtprel_lo12, no overflow check. */
2844 {"dtprel_lo12_nc", 0,
2848 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2849 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2852 /* bits[23:12] of offset to the module TLS base address. */
2857 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2861 /* bits[15:0] of offset to the module TLS base address. */
2865 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2870 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2874 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2879 /* bits[31:16] of offset to the module TLS base address. */
2883 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2888 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2892 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2897 /* bits[47:32] of offset to the module TLS base address. */
2901 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2906 /* Lower 16 bit offset into GOT entry for a symbol */
2907 {"tlsdesc_off_g0_nc", 0,
2910 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2915 /* Higher 16 bit offset into GOT entry for a symbol */
2916 {"tlsdesc_off_g1", 0,
2919 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2924 /* Get to the page containing GOT TLS entry for a symbol */
2927 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2931 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2933 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2934 {"gottprel_lo12", 0,
2939 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2942 /* Get tp offset for a symbol. */
2947 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2951 /* Get tp offset for a symbol. */
2956 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2957 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2960 /* Get tp offset for a symbol. */
2965 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2969 /* Get tp offset for a symbol. */
2970 {"tprel_lo12_nc", 0,
2974 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2975 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2978 /* Most significant bits 32-47 of address/value: MOVZ. */
2982 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2987 /* Most significant bits 16-31 of address/value: MOVZ. */
2991 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2996 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3000 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3005 /* Most significant bits 0-15 of address/value: MOVZ. */
3009 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3014 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3018 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3023 /* 15bit offset from got entry to base address of GOT table. */
3029 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3032 /* 14bit offset from got entry to base address of GOT table. */
3038 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3042 /* Given the address of a pointer pointing to the textual name of a
3043 relocation as may appear in assembler source, attempt to find its
3044 details in reloc_table. The pointer will be updated to the character
3045 after the trailing colon. On failure, NULL will be returned;
3046 otherwise return the reloc_table_entry. */
3048 static struct reloc_table_entry
*
3049 find_reloc_table_entry (char **str
)
3052 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3054 int length
= strlen (reloc_table
[i
].name
);
3056 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3057 && (*str
)[length
] == ':')
3059 *str
+= (length
+ 1);
3060 return &reloc_table
[i
];
3067 /* Returns 0 if the relocation should never be forced,
3068 1 if the relocation must be forced, and -1 if either
3072 aarch64_force_reloc (unsigned int type
)
3076 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3077 /* Perform these "immediate" internal relocations
3078 even if the symbol is extern or weak. */
3081 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3082 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3083 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3084 /* Pseudo relocs that need to be fixed up according to
3088 case BFD_RELOC_AARCH64_ADD_LO12
:
3089 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3090 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3091 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3092 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3093 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3094 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3095 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3096 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3097 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3098 case BFD_RELOC_AARCH64_LDST128_LO12
:
3099 case BFD_RELOC_AARCH64_LDST16_LO12
:
3100 case BFD_RELOC_AARCH64_LDST32_LO12
:
3101 case BFD_RELOC_AARCH64_LDST64_LO12
:
3102 case BFD_RELOC_AARCH64_LDST8_LO12
:
3103 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3104 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3105 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3106 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3107 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3108 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3109 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3110 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3111 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3112 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3113 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3114 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3115 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3116 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3117 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3118 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3119 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3120 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3121 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3122 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3123 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3124 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3125 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3126 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3127 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3128 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3129 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3130 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3131 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3132 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3133 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3134 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3135 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3136 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3137 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3138 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3139 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3140 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3141 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3142 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3143 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3144 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3145 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3146 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3147 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3148 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3149 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3150 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3151 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3154 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3155 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3156 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3157 /* Always leave these relocations for the linker. */
3166 aarch64_force_relocation (struct fix
*fixp
)
3168 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3171 return generic_force_reloc (fixp
);
3175 /* Mode argument to parse_shift and parser_shifter_operand. */
3176 enum parse_shift_mode
3178 SHIFTED_NONE
, /* no shifter allowed */
3179 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3181 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3183 SHIFTED_LSL
, /* bare "lsl #n" */
3184 SHIFTED_MUL
, /* bare "mul #n" */
3185 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3186 SHIFTED_MUL_VL
, /* "mul vl" */
3187 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3190 /* Parse a <shift> operator on an AArch64 data processing instruction.
3191 Return TRUE on success; otherwise return FALSE. */
3193 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3195 const struct aarch64_name_value_pair
*shift_op
;
3196 enum aarch64_modifier_kind kind
;
3202 for (p
= *str
; ISALPHA (*p
); p
++)
3207 set_syntax_error (_("shift expression expected"));
3211 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3213 if (shift_op
== NULL
)
3215 set_syntax_error (_("shift operator expected"));
3219 kind
= aarch64_get_operand_modifier (shift_op
);
3221 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3223 set_syntax_error (_("invalid use of 'MSL'"));
3227 if (kind
== AARCH64_MOD_MUL
3228 && mode
!= SHIFTED_MUL
3229 && mode
!= SHIFTED_MUL_VL
)
3231 set_syntax_error (_("invalid use of 'MUL'"));
3237 case SHIFTED_LOGIC_IMM
:
3238 if (aarch64_extend_operator_p (kind
))
3240 set_syntax_error (_("extending shift is not permitted"));
3245 case SHIFTED_ARITH_IMM
:
3246 if (kind
== AARCH64_MOD_ROR
)
3248 set_syntax_error (_("'ROR' shift is not permitted"));
3254 if (kind
!= AARCH64_MOD_LSL
)
3256 set_syntax_error (_("only 'LSL' shift is permitted"));
3262 if (kind
!= AARCH64_MOD_MUL
)
3264 set_syntax_error (_("only 'MUL' is permitted"));
3269 case SHIFTED_MUL_VL
:
3270 /* "MUL VL" consists of two separate tokens. Require the first
3271 token to be "MUL" and look for a following "VL". */
3272 if (kind
== AARCH64_MOD_MUL
)
3274 skip_whitespace (p
);
3275 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3278 kind
= AARCH64_MOD_MUL_VL
;
3282 set_syntax_error (_("only 'MUL VL' is permitted"));
3285 case SHIFTED_REG_OFFSET
:
3286 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3287 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3289 set_fatal_syntax_error
3290 (_("invalid shift for the register offset addressing mode"));
3295 case SHIFTED_LSL_MSL
:
3296 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3298 set_syntax_error (_("invalid shift operator"));
3307 /* Whitespace can appear here if the next thing is a bare digit. */
3308 skip_whitespace (p
);
3310 /* Parse shift amount. */
3312 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3313 exp
.X_op
= O_absent
;
3316 if (is_immediate_prefix (*p
))
3321 (void) aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
,
3324 if (kind
== AARCH64_MOD_MUL_VL
)
3325 /* For consistency, give MUL VL the same shift amount as an implicit
3327 operand
->shifter
.amount
= 1;
3328 else if (exp
.X_op
== O_absent
)
3330 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3332 set_syntax_error (_("missing shift amount"));
3335 operand
->shifter
.amount
= 0;
3337 else if (exp
.X_op
!= O_constant
)
3339 set_syntax_error (_("constant shift amount required"));
3342 /* For parsing purposes, MUL #n has no inherent range. The range
3343 depends on the operand and will be checked by operand-specific
3345 else if (kind
!= AARCH64_MOD_MUL
3346 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3348 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3353 operand
->shifter
.amount
= exp
.X_add_number
;
3354 operand
->shifter
.amount_present
= 1;
3357 operand
->shifter
.operator_present
= 1;
3358 operand
->shifter
.kind
= kind
;
3364 /* Parse a <shifter_operand> for a data processing instruction:
3367 #<immediate>, LSL #imm
3369 Validation of immediate operands is deferred to md_apply_fix.
3371 Return TRUE on success; otherwise return FALSE. */
3374 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3375 enum parse_shift_mode mode
)
3379 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3384 /* Accept an immediate expression. */
3385 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3386 REJECT_ABSENT
, NORMAL_RESOLUTION
))
3389 /* Accept optional LSL for arithmetic immediate values. */
3390 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3391 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3394 /* Not accept any shifter for logical immediate values. */
3395 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3396 && parse_shift (&p
, operand
, mode
))
3398 set_syntax_error (_("unexpected shift operator"));
3406 /* Parse a <shifter_operand> for a data processing instruction:
3411 #<immediate>, LSL #imm
3413 where <shift> is handled by parse_shift above, and the last two
3414 cases are handled by the function above.
3416 Validation of immediate operands is deferred to md_apply_fix.
3418 Return TRUE on success; otherwise return FALSE. */
3421 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3422 enum parse_shift_mode mode
)
3424 const reg_entry
*reg
;
3425 aarch64_opnd_qualifier_t qualifier
;
3426 enum aarch64_operand_class opd_class
3427 = aarch64_get_operand_class (operand
->type
);
3429 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3432 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3434 set_syntax_error (_("unexpected register in the immediate operand"));
3438 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3440 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3444 operand
->reg
.regno
= reg
->number
;
3445 operand
->qualifier
= qualifier
;
3447 /* Accept optional shift operation on register. */
3448 if (! skip_past_comma (str
))
3451 if (! parse_shift (str
, operand
, mode
))
3456 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3459 (_("integer register expected in the extended/shifted operand "
3464 /* We have a shifted immediate variable. */
3465 return parse_shifter_operand_imm (str
, operand
, mode
);
3468 /* Return TRUE on success; return FALSE otherwise. */
3471 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3472 enum parse_shift_mode mode
)
3476 /* Determine if we have the sequence of characters #: or just :
3477 coming next. If we do, then we check for a :rello: relocation
3478 modifier. If we don't, punt the whole lot to
3479 parse_shifter_operand. */
3481 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3483 struct reloc_table_entry
*entry
;
3491 /* Try to parse a relocation. Anything else is an error. */
3492 if (!(entry
= find_reloc_table_entry (str
)))
3494 set_syntax_error (_("unknown relocation modifier"));
3498 if (entry
->add_type
== 0)
3501 (_("this relocation modifier is not allowed on this instruction"));
3505 /* Save str before we decompose it. */
3508 /* Next, we parse the expression. */
3509 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3511 aarch64_force_reloc (entry
->add_type
) == 1))
3514 /* Record the relocation type (use the ADD variant here). */
3515 inst
.reloc
.type
= entry
->add_type
;
3516 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3518 /* If str is empty, we've reached the end, stop here. */
3522 /* Otherwise, we have a shifted reloc modifier, so rewind to
3523 recover the variable name and continue parsing for the shifter. */
3525 return parse_shifter_operand_imm (str
, operand
, mode
);
3528 return parse_shifter_operand (str
, operand
, mode
);
3531 /* Parse all forms of an address expression. Information is written
3532 to *OPERAND and/or inst.reloc.
3534 The A64 instruction set has the following addressing modes:
3537 [base] // in SIMD ld/st structure
3538 [base{,#0}] // in ld/st exclusive
3540 [base,Xm{,LSL #imm}]
3541 [base,Xm,SXTX {#imm}]
3542 [base,Wm,(S|U)XTW {#imm}]
3544 [base]! // in ldraa/ldrab exclusive
3548 [base],Xm // in SIMD ld/st structure
3549 PC-relative (literal)
3553 [base,Zm.D{,LSL #imm}]
3554 [base,Zm.S,(S|U)XTW {#imm}]
3555 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3559 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3560 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3561 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3563 (As a convenience, the notation "=immediate" is permitted in conjunction
3564 with the pc-relative literal load instructions to automatically place an
3565 immediate value or symbolic address in a nearby literal pool and generate
3566 a hidden label which references it.)
3568 Upon a successful parsing, the address structure in *OPERAND will be
3569 filled in the following way:
3571 .base_regno = <base>
3572 .offset.is_reg // 1 if the offset is a register
3574 .offset.regno = <Rm>
3576 For different addressing modes defined in the A64 ISA:
3579 .pcrel=0; .preind=1; .postind=0; .writeback=0
3581 .pcrel=0; .preind=1; .postind=0; .writeback=1
3583 .pcrel=0; .preind=0; .postind=1; .writeback=1
3584 PC-relative (literal)
3585 .pcrel=1; .preind=1; .postind=0; .writeback=0
3587 The shift/extension information, if any, will be stored in .shifter.
3588 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3589 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3590 corresponding register.
3592 BASE_TYPE says which types of base register should be accepted and
3593 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3594 is the type of shifter that is allowed for immediate offsets,
3595 or SHIFTED_NONE if none.
3597 In all other respects, it is the caller's responsibility to check
3598 for addressing modes not supported by the instruction, and to set
3602 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3603 aarch64_opnd_qualifier_t
*base_qualifier
,
3604 aarch64_opnd_qualifier_t
*offset_qualifier
,
3605 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3606 enum parse_shift_mode imm_shift_mode
)
3609 const reg_entry
*reg
;
3610 expressionS
*exp
= &inst
.reloc
.exp
;
3612 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3613 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3614 if (! skip_past_char (&p
, '['))
3616 /* =immediate or label. */
3617 operand
->addr
.pcrel
= 1;
3618 operand
->addr
.preind
= 1;
3620 /* #:<reloc_op>:<symbol> */
3621 skip_past_char (&p
, '#');
3622 if (skip_past_char (&p
, ':'))
3624 bfd_reloc_code_real_type ty
;
3625 struct reloc_table_entry
*entry
;
3627 /* Try to parse a relocation modifier. Anything else is
3629 entry
= find_reloc_table_entry (&p
);
3632 set_syntax_error (_("unknown relocation modifier"));
3636 switch (operand
->type
)
3638 case AARCH64_OPND_ADDR_PCREL21
:
3640 ty
= entry
->adr_type
;
3644 ty
= entry
->ld_literal_type
;
3651 (_("this relocation modifier is not allowed on this "
3657 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3658 aarch64_force_reloc (entry
->add_type
) == 1))
3660 set_syntax_error (_("invalid relocation expression"));
3663 /* #:<reloc_op>:<expr> */
3664 /* Record the relocation type. */
3665 inst
.reloc
.type
= ty
;
3666 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3670 if (skip_past_char (&p
, '='))
3671 /* =immediate; need to generate the literal in the literal pool. */
3672 inst
.gen_lit_pool
= 1;
3674 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3677 set_syntax_error (_("invalid address"));
3688 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3689 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3691 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3694 operand
->addr
.base_regno
= reg
->number
;
3697 if (skip_past_comma (&p
))
3700 operand
->addr
.preind
= 1;
3702 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3705 if (!aarch64_check_reg_type (reg
, offset_type
))
3707 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3712 operand
->addr
.offset
.regno
= reg
->number
;
3713 operand
->addr
.offset
.is_reg
= 1;
3714 /* Shifted index. */
3715 if (skip_past_comma (&p
))
3718 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3719 /* Use the diagnostics set in parse_shift, so not set new
3720 error message here. */
3724 [base,Xm] # For vector plus scalar SVE2 indexing.
3725 [base,Xm{,LSL #imm}]
3726 [base,Xm,SXTX {#imm}]
3727 [base,Wm,(S|U)XTW {#imm}] */
3728 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3729 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3730 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3732 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3734 set_syntax_error (_("invalid use of 32-bit register offset"));
3737 if (aarch64_get_qualifier_esize (*base_qualifier
)
3738 != aarch64_get_qualifier_esize (*offset_qualifier
)
3739 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3740 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3741 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3743 set_syntax_error (_("offset has different size from base"));
3747 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3749 set_syntax_error (_("invalid use of 64-bit register offset"));
3755 /* [Xn,#:<reloc_op>:<symbol> */
3756 skip_past_char (&p
, '#');
3757 if (skip_past_char (&p
, ':'))
3759 struct reloc_table_entry
*entry
;
3761 /* Try to parse a relocation modifier. Anything else is
3763 if (!(entry
= find_reloc_table_entry (&p
)))
3765 set_syntax_error (_("unknown relocation modifier"));
3769 if (entry
->ldst_type
== 0)
3772 (_("this relocation modifier is not allowed on this "
3777 /* [Xn,#:<reloc_op>: */
3778 /* We now have the group relocation table entry corresponding to
3779 the name in the assembler source. Next, we parse the
3781 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3782 aarch64_force_reloc (entry
->add_type
) == 1))
3784 set_syntax_error (_("invalid relocation expression"));
3788 /* [Xn,#:<reloc_op>:<expr> */
3789 /* Record the load/store relocation type. */
3790 inst
.reloc
.type
= entry
->ldst_type
;
3791 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3795 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3798 set_syntax_error (_("invalid expression in the address"));
3802 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3803 /* [Xn,<expr>,<shifter> */
3804 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3810 if (! skip_past_char (&p
, ']'))
3812 set_syntax_error (_("']' expected"));
3816 if (skip_past_char (&p
, '!'))
3818 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3820 set_syntax_error (_("register offset not allowed in pre-indexed "
3821 "addressing mode"));
3825 operand
->addr
.writeback
= 1;
3827 else if (skip_past_comma (&p
))
3830 operand
->addr
.postind
= 1;
3831 operand
->addr
.writeback
= 1;
3833 if (operand
->addr
.preind
)
3835 set_syntax_error (_("cannot combine pre- and post-indexing"));
3839 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3843 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3845 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3849 operand
->addr
.offset
.regno
= reg
->number
;
3850 operand
->addr
.offset
.is_reg
= 1;
3852 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3856 set_syntax_error (_("invalid expression in the address"));
3861 /* If at this point neither .preind nor .postind is set, we have a
3862 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3863 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3864 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3866 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3868 if (operand
->addr
.writeback
)
3870 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3872 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3873 operand
->addr
.offset
.is_reg
= 0;
3874 operand
->addr
.offset
.imm
= 0;
3875 operand
->addr
.preind
= 1;
3880 set_syntax_error (_("missing offset in the pre-indexed address"));
3886 operand
->addr
.preind
= 1;
3887 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3889 operand
->addr
.offset
.is_reg
= 1;
3890 operand
->addr
.offset
.regno
= REG_ZR
;
3891 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3895 inst
.reloc
.exp
.X_op
= O_constant
;
3896 inst
.reloc
.exp
.X_add_number
= 0;
3905 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3908 parse_address (char **str
, aarch64_opnd_info
*operand
)
3910 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3911 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3912 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3915 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3916 The arguments have the same meaning as for parse_address_main.
3917 Return TRUE on success. */
3919 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3920 aarch64_opnd_qualifier_t
*base_qualifier
,
3921 aarch64_opnd_qualifier_t
*offset_qualifier
)
3923 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3924 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3928 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3929 Return TRUE on success; otherwise return FALSE. */
3931 parse_half (char **str
, int *internal_fixup_p
)
3935 skip_past_char (&p
, '#');
3937 gas_assert (internal_fixup_p
);
3938 *internal_fixup_p
= 0;
3942 struct reloc_table_entry
*entry
;
3944 /* Try to parse a relocation. Anything else is an error. */
3947 if (!(entry
= find_reloc_table_entry (&p
)))
3949 set_syntax_error (_("unknown relocation modifier"));
3953 if (entry
->movw_type
== 0)
3956 (_("this relocation modifier is not allowed on this instruction"));
3960 inst
.reloc
.type
= entry
->movw_type
;
3963 *internal_fixup_p
= 1;
3965 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3966 aarch64_force_reloc (inst
.reloc
.type
) == 1))
3973 /* Parse an operand for an ADRP instruction:
3975 Return TRUE on success; otherwise return FALSE. */
3978 parse_adrp (char **str
)
3985 struct reloc_table_entry
*entry
;
3987 /* Try to parse a relocation. Anything else is an error. */
3989 if (!(entry
= find_reloc_table_entry (&p
)))
3991 set_syntax_error (_("unknown relocation modifier"));
3995 if (entry
->adrp_type
== 0)
3998 (_("this relocation modifier is not allowed on this instruction"));
4002 inst
.reloc
.type
= entry
->adrp_type
;
4005 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4007 inst
.reloc
.pc_rel
= 1;
4008 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
4009 aarch64_force_reloc (inst
.reloc
.type
) == 1))
4015 /* Miscellaneous. */
4017 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4018 of SIZE tokens in which index I gives the token for field value I,
4019 or is null if field value I is invalid. REG_TYPE says which register
4020 names should be treated as registers rather than as symbolic immediates.
4022 Return true on success, moving *STR past the operand and storing the
4023 field value in *VAL. */
4026 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4027 size_t size
, aarch64_reg_type reg_type
)
4033 /* Match C-like tokens. */
4035 while (ISALNUM (*q
))
4038 for (i
= 0; i
< size
; ++i
)
4040 && strncasecmp (array
[i
], p
, q
- p
) == 0
4041 && array
[i
][q
- p
] == 0)
4048 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4051 if (exp
.X_op
== O_constant
4052 && (uint64_t) exp
.X_add_number
< size
)
4054 *val
= exp
.X_add_number
;
4059 /* Use the default error for this operand. */
4063 /* Parse an option for a preload instruction. Returns the encoding for the
4064 option, or PARSE_FAIL. */
4067 parse_pldop (char **str
)
4070 const struct aarch64_name_value_pair
*o
;
4073 while (ISALNUM (*q
))
4076 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4084 /* Parse an option for a barrier instruction. Returns the encoding for the
4085 option, or PARSE_FAIL. */
4088 parse_barrier (char **str
)
4091 const struct aarch64_name_value_pair
*o
;
4094 while (ISALPHA (*q
))
4097 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4105 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4106 return 0 if successful. Otherwise return PARSE_FAIL. */
4109 parse_barrier_psb (char **str
,
4110 const struct aarch64_name_value_pair
** hint_opt
)
4113 const struct aarch64_name_value_pair
*o
;
4116 while (ISALPHA (*q
))
4119 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4122 set_fatal_syntax_error
4123 ( _("unknown or missing option to PSB/TSB"));
4127 if (o
->value
!= 0x11)
4129 /* PSB only accepts option name 'CSYNC'. */
4131 (_("the specified option is not accepted for PSB/TSB"));
4140 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4141 return 0 if successful. Otherwise return PARSE_FAIL. */
4144 parse_bti_operand (char **str
,
4145 const struct aarch64_name_value_pair
** hint_opt
)
4148 const struct aarch64_name_value_pair
*o
;
4151 while (ISALPHA (*q
))
4154 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4157 set_fatal_syntax_error
4158 ( _("unknown option to BTI"));
4164 /* Valid BTI operands. */
4172 (_("unknown option to BTI"));
4181 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4182 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4187 Side effect: Update STR with current parse position of success.
4190 static const reg_entry
*
4191 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4192 aarch64_opnd_qualifier_t
*qualifier
)
4196 reg_entry
*reg
= parse_reg (str
);
4197 if (reg
!= NULL
&& reg
->type
== reg_type
)
4199 if (!skip_past_char (str
, '.'))
4201 set_syntax_error (_("missing ZA tile element size separator"));
4206 switch (TOLOWER (*q
))
4209 *qualifier
= AARCH64_OPND_QLF_S_B
;
4212 *qualifier
= AARCH64_OPND_QLF_S_H
;
4215 *qualifier
= AARCH64_OPND_QLF_S_S
;
4218 *qualifier
= AARCH64_OPND_QLF_S_D
;
4221 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4235 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4236 Function return tile QUALIFIER on success.
4238 Tiles are in example format: za[0-9]\.[bhsd]
4240 Function returns <ZAda> register number or PARSE_FAIL.
4243 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4246 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4250 regno
= reg
->number
;
4254 case AARCH64_OPND_QLF_S_B
:
4257 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4261 case AARCH64_OPND_QLF_S_H
:
4264 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4268 case AARCH64_OPND_QLF_S_S
:
4271 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4272 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4276 case AARCH64_OPND_QLF_S_D
:
4279 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4280 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4285 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4292 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4297 Function return TRUE if immediate was found, or FALSE.
4300 parse_sme_immediate (char **str
, int64_t *imm
)
4303 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4310 /* Parse index with vector select register and immediate:
4314 where <Wv> is in W12-W15 range and # is optional for immediate.
4316 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4319 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4323 parse_sme_za_hv_tiles_operand_index (char **str
,
4324 int *vector_select_register
,
4327 const reg_entry
*reg
;
4329 if (!skip_past_char (str
, '['))
4331 set_syntax_error (_("expected '['"));
4335 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4336 reg
= parse_reg (str
);
4337 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4338 || reg
->number
< 12 || reg
->number
> 15)
4340 set_syntax_error (_("expected vector select register W12-W15"));
4343 *vector_select_register
= reg
->number
;
4345 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4347 set_syntax_error (_("expected ','"));
4351 if (!parse_sme_immediate (str
, imm
))
4353 set_syntax_error (_("index offset immediate expected"));
4357 if (!skip_past_char (str
, ']'))
4359 set_syntax_error (_("expected ']'"));
4366 /* Parse SME ZA horizontal or vertical vector access to tiles.
4367 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4368 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4369 contains <Wv> select register and corresponding optional IMMEDIATE.
4370 In addition QUALIFIER is extracted.
4372 Field format examples:
4374 ZA0<HV>.B[<Wv>, #<imm>]
4375 <ZAn><HV>.H[<Wv>, #<imm>]
4376 <ZAn><HV>.S[<Wv>, #<imm>]
4377 <ZAn><HV>.D[<Wv>, #<imm>]
4378 <ZAn><HV>.Q[<Wv>, #<imm>]
4380 Function returns <ZAda> register number or PARSE_FAIL.
4383 parse_sme_za_hv_tiles_operand (char **str
,
4384 enum sme_hv_slice
*slice_indicator
,
4385 int *vector_select_register
,
4387 aarch64_opnd_qualifier_t
*qualifier
)
4394 const reg_entry
*reg
;
4397 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4399 *slice_indicator
= HV_horizontal
;
4402 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4404 *slice_indicator
= HV_vertical
;
4409 regno
= reg
->number
;
4413 case AARCH64_OPND_QLF_S_B
:
4417 case AARCH64_OPND_QLF_S_H
:
4421 case AARCH64_OPND_QLF_S_S
:
4425 case AARCH64_OPND_QLF_S_D
:
4429 case AARCH64_OPND_QLF_S_Q
:
4434 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4438 /* Check if destination register ZA tile vector is in range for given
4439 instruction variant. */
4440 if (regno
< 0 || regno
> regno_limit
)
4442 set_syntax_error (_("ZA tile vector out of range"));
4446 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4450 /* Check if optional index offset is in the range for instruction
4452 if (imm_value
< 0 || imm_value
> imm_limit
)
4454 set_syntax_error (_("index offset out of range"));
4465 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4466 enum sme_hv_slice
*slice_indicator
,
4467 int *vector_select_register
,
4469 aarch64_opnd_qualifier_t
*qualifier
)
4473 if (!skip_past_char (str
, '{'))
4475 set_syntax_error (_("expected '{'"));
4479 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4480 vector_select_register
, imm
,
4483 if (regno
== PARSE_FAIL
)
4486 if (!skip_past_char (str
, '}'))
4488 set_syntax_error (_("expected '}'"));
4495 /* Parse list of up to eight 64-bit element tile names separated by commas in
4496 SME's ZERO instruction:
4500 Function returns <mask>:
4502 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4505 parse_sme_zero_mask(char **str
)
4509 aarch64_opnd_qualifier_t qualifier
;
4515 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4518 int regno
= reg
->number
;
4519 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4521 /* { ZA0.B } is assembled as all-ones immediate. */
4524 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4525 mask
|= 0x55 << regno
;
4526 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4527 mask
|= 0x11 << regno
;
4528 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4529 mask
|= 0x01 << regno
;
4532 set_syntax_error (_("wrong ZA tile element format"));
4537 else if (strncasecmp (q
, "za", 2) == 0
4540 /* { ZA } is assembled as all-ones immediate. */
4547 set_syntax_error (_("wrong ZA tile element format"));
4551 while (skip_past_char (&q
, ','));
4557 /* Wraps in curly braces <mask> operand ZERO instruction:
4561 Function returns value of <mask> bit-field.
4564 parse_sme_list_of_64bit_tiles (char **str
)
4568 if (!skip_past_char (str
, '{'))
4570 set_syntax_error (_("expected '{'"));
4574 /* Empty <mask> list is an all-zeros immediate. */
4575 if (!skip_past_char (str
, '}'))
4577 regno
= parse_sme_zero_mask (str
);
4578 if (regno
== PARSE_FAIL
)
4581 if (!skip_past_char (str
, '}'))
4583 set_syntax_error (_("expected '}'"));
4593 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4599 Function returns <Wv> or PARSE_FAIL.
4602 parse_sme_za_array (char **str
, int *imm
)
4609 while (ISALPHA (*q
))
4612 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4614 set_syntax_error (_("expected ZA array"));
4618 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4621 if (imm_value
< 0 || imm_value
> 15)
4623 set_syntax_error (_("offset out of range"));
4632 /* Parse streaming mode operand for SMSTART and SMSTOP.
4636 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4639 parse_sme_sm_za (char **str
)
4644 while (ISALPHA (*q
))
4648 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4650 set_syntax_error (_("expected SM or ZA operand"));
4655 return TOLOWER (p
[0]);
4658 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4659 Returns the encoding for the option, or PARSE_FAIL.
4661 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4662 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4664 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4665 field, otherwise as a system register.
4669 parse_sys_reg (char **str
, htab_t sys_regs
,
4670 int imple_defined_p
, int pstatefield_p
,
4674 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4675 const aarch64_sys_reg
*o
;
4679 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4680 if (p
< buf
+ (sizeof (buf
) - 1))
4681 *p
++ = TOLOWER (*q
);
4684 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4685 valid system register. This is enforced by construction of the hash
4687 if (p
- buf
!= q
- *str
)
4690 o
= str_hash_find (sys_regs
, buf
);
4693 if (!imple_defined_p
)
4697 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4698 unsigned int op0
, op1
, cn
, cm
, op2
;
4700 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4703 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4705 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4712 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4713 as_bad (_("selected processor does not support PSTATE field "
4716 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4717 o
->value
, o
->flags
, o
->features
))
4718 as_bad (_("selected processor does not support system register "
4720 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4721 as_warn (_("system register name '%s' is deprecated and may be "
4722 "removed in a future release"), buf
);
4732 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4733 for the option, or NULL. */
4735 static const aarch64_sys_ins_reg
*
4736 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4739 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4740 const aarch64_sys_ins_reg
*o
;
4743 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4744 if (p
< buf
+ (sizeof (buf
) - 1))
4745 *p
++ = TOLOWER (*q
);
4748 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4749 valid system register. This is enforced by construction of the hash
4751 if (p
- buf
!= q
- *str
)
4754 o
= str_hash_find (sys_ins_regs
, buf
);
4758 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4759 o
->name
, o
->value
, o
->flags
, 0))
4760 as_bad (_("selected processor does not support system register "
4762 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4763 as_warn (_("system register name '%s' is deprecated and may be "
4764 "removed in a future release"), buf
);
4770 #define po_char_or_fail(chr) do { \
4771 if (! skip_past_char (&str, chr)) \
4775 #define po_reg_or_fail(regtype) do { \
4776 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4777 if (val == PARSE_FAIL) \
4779 set_default_error (); \
4784 #define po_int_reg_or_fail(reg_type) do { \
4785 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4786 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4788 set_default_error (); \
4791 info->reg.regno = reg->number; \
4792 info->qualifier = qualifier; \
4795 #define po_imm_nc_or_fail() do { \
4796 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4800 #define po_imm_or_fail(min, max) do { \
4801 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4803 if (val < min || val > max) \
4805 set_fatal_syntax_error (_("immediate value out of range "\
4806 #min " to "#max)); \
4811 #define po_enum_or_fail(array) do { \
4812 if (!parse_enum_string (&str, &val, array, \
4813 ARRAY_SIZE (array), imm_reg_type)) \
4817 #define po_misc_or_fail(expr) do { \
4822 /* encode the 12-bit imm field of Add/sub immediate */
4823 static inline uint32_t
4824 encode_addsub_imm (uint32_t imm
)
4829 /* encode the shift amount field of Add/sub immediate */
4830 static inline uint32_t
4831 encode_addsub_imm_shift_amount (uint32_t cnt
)
4837 /* encode the imm field of Adr instruction */
4838 static inline uint32_t
4839 encode_adr_imm (uint32_t imm
)
4841 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4842 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4845 /* encode the immediate field of Move wide immediate */
4846 static inline uint32_t
4847 encode_movw_imm (uint32_t imm
)
4852 /* encode the 26-bit offset of unconditional branch */
4853 static inline uint32_t
4854 encode_branch_ofs_26 (uint32_t ofs
)
4856 return ofs
& ((1 << 26) - 1);
4859 /* encode the 19-bit offset of conditional branch and compare & branch */
4860 static inline uint32_t
4861 encode_cond_branch_ofs_19 (uint32_t ofs
)
4863 return (ofs
& ((1 << 19) - 1)) << 5;
4866 /* encode the 19-bit offset of ld literal */
4867 static inline uint32_t
4868 encode_ld_lit_ofs_19 (uint32_t ofs
)
4870 return (ofs
& ((1 << 19) - 1)) << 5;
4873 /* Encode the 14-bit offset of test & branch. */
4874 static inline uint32_t
4875 encode_tst_branch_ofs_14 (uint32_t ofs
)
4877 return (ofs
& ((1 << 14) - 1)) << 5;
4880 /* Encode the 16-bit imm field of svc/hvc/smc. */
4881 static inline uint32_t
4882 encode_svc_imm (uint32_t imm
)
4887 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4888 static inline uint32_t
4889 reencode_addsub_switch_add_sub (uint32_t opcode
)
4891 return opcode
^ (1 << 30);
4894 static inline uint32_t
4895 reencode_movzn_to_movz (uint32_t opcode
)
4897 return opcode
| (1 << 30);
4900 static inline uint32_t
4901 reencode_movzn_to_movn (uint32_t opcode
)
4903 return opcode
& ~(1 << 30);
4906 /* Overall per-instruction processing. */
4908 /* We need to be able to fix up arbitrary expressions in some statements.
4909 This is so that we can handle symbols that are an arbitrary distance from
4910 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4911 which returns part of an address in a form which will be valid for
4912 a data instruction. We do this by pushing the expression into a symbol
4913 in the expr_section, and creating a fix for that. */
4916 fix_new_aarch64 (fragS
* frag
,
4931 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4935 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4942 /* Diagnostics on operands errors. */
4944 /* By default, output verbose error message.
4945 Disable the verbose error message by -mno-verbose-error. */
4946 static int verbose_error_p
= 1;
4948 #ifdef DEBUG_AARCH64
4949 /* N.B. this is only for the purpose of debugging. */
4950 const char* operand_mismatch_kind_names
[] =
4953 "AARCH64_OPDE_RECOVERABLE",
4954 "AARCH64_OPDE_SYNTAX_ERROR",
4955 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4956 "AARCH64_OPDE_INVALID_VARIANT",
4957 "AARCH64_OPDE_OUT_OF_RANGE",
4958 "AARCH64_OPDE_UNALIGNED",
4959 "AARCH64_OPDE_REG_LIST",
4960 "AARCH64_OPDE_OTHER_ERROR",
4962 #endif /* DEBUG_AARCH64 */
4964 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4966 When multiple errors of different kinds are found in the same assembly
4967 line, only the error of the highest severity will be picked up for
4968 issuing the diagnostics. */
4971 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4972 enum aarch64_operand_error_kind rhs
)
4974 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4975 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4976 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4977 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4978 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4979 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4980 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4981 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4985 /* Helper routine to get the mnemonic name from the assembly instruction
4986 line; should only be called for the diagnosis purpose, as there is
4987 string copy operation involved, which may affect the runtime
4988 performance if used in elsewhere. */
4991 get_mnemonic_name (const char *str
)
4993 static char mnemonic
[32];
4996 /* Get the first 15 bytes and assume that the full name is included. */
4997 strncpy (mnemonic
, str
, 31);
4998 mnemonic
[31] = '\0';
5000 /* Scan up to the end of the mnemonic, which must end in white space,
5001 '.', or end of string. */
5002 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5007 /* Append '...' to the truncated long name. */
5008 if (ptr
- mnemonic
== 31)
5009 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5015 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5017 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5018 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5021 /* Data structures storing one user error in the assembly code related to
5024 struct operand_error_record
5026 const aarch64_opcode
*opcode
;
5027 aarch64_operand_error detail
;
5028 struct operand_error_record
*next
;
5031 typedef struct operand_error_record operand_error_record
;
5033 struct operand_errors
5035 operand_error_record
*head
;
5036 operand_error_record
*tail
;
5039 typedef struct operand_errors operand_errors
;
5041 /* Top-level data structure reporting user errors for the current line of
5043 The way md_assemble works is that all opcodes sharing the same mnemonic
5044 name are iterated to find a match to the assembly line. In this data
5045 structure, each of the such opcodes will have one operand_error_record
5046 allocated and inserted. In other words, excessive errors related with
5047 a single opcode are disregarded. */
5048 operand_errors operand_error_report
;
5050 /* Free record nodes. */
5051 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5053 /* Initialize the data structure that stores the operand mismatch
5054 information on assembling one line of the assembly code. */
5056 init_operand_error_report (void)
5058 if (operand_error_report
.head
!= NULL
)
5060 gas_assert (operand_error_report
.tail
!= NULL
);
5061 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5062 free_opnd_error_record_nodes
= operand_error_report
.head
;
5063 operand_error_report
.head
= NULL
;
5064 operand_error_report
.tail
= NULL
;
5067 gas_assert (operand_error_report
.tail
== NULL
);
5070 /* Return TRUE if some operand error has been recorded during the
5071 parsing of the current assembly line using the opcode *OPCODE;
5072 otherwise return FALSE. */
5074 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5076 operand_error_record
*record
= operand_error_report
.head
;
5077 return record
&& record
->opcode
== opcode
;
5080 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5081 OPCODE field is initialized with OPCODE.
5082 N.B. only one record for each opcode, i.e. the maximum of one error is
5083 recorded for each instruction template. */
5086 add_operand_error_record (const operand_error_record
* new_record
)
5088 const aarch64_opcode
*opcode
= new_record
->opcode
;
5089 operand_error_record
* record
= operand_error_report
.head
;
5091 /* The record may have been created for this opcode. If not, we need
5093 if (! opcode_has_operand_error_p (opcode
))
5095 /* Get one empty record. */
5096 if (free_opnd_error_record_nodes
== NULL
)
5098 record
= XNEW (operand_error_record
);
5102 record
= free_opnd_error_record_nodes
;
5103 free_opnd_error_record_nodes
= record
->next
;
5105 record
->opcode
= opcode
;
5106 /* Insert at the head. */
5107 record
->next
= operand_error_report
.head
;
5108 operand_error_report
.head
= record
;
5109 if (operand_error_report
.tail
== NULL
)
5110 operand_error_report
.tail
= record
;
5112 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5113 && record
->detail
.index
<= new_record
->detail
.index
5114 && operand_error_higher_severity_p (record
->detail
.kind
,
5115 new_record
->detail
.kind
))
5117 /* In the case of multiple errors found on operands related with a
5118 single opcode, only record the error of the leftmost operand and
5119 only if the error is of higher severity. */
5120 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5121 " the existing error %s on operand %d",
5122 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5123 new_record
->detail
.index
,
5124 operand_mismatch_kind_names
[record
->detail
.kind
],
5125 record
->detail
.index
);
5129 record
->detail
= new_record
->detail
;
5133 record_operand_error_info (const aarch64_opcode
*opcode
,
5134 aarch64_operand_error
*error_info
)
5136 operand_error_record record
;
5137 record
.opcode
= opcode
;
5138 record
.detail
= *error_info
;
5139 add_operand_error_record (&record
);
5142 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5143 error message *ERROR, for operand IDX (count from 0). */
5146 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5147 enum aarch64_operand_error_kind kind
,
5150 aarch64_operand_error info
;
5151 memset(&info
, 0, sizeof (info
));
5155 info
.non_fatal
= false;
5156 record_operand_error_info (opcode
, &info
);
5160 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5161 enum aarch64_operand_error_kind kind
,
5162 const char* error
, const int *extra_data
)
5164 aarch64_operand_error info
;
5168 info
.data
[0] = extra_data
[0];
5169 info
.data
[1] = extra_data
[1];
5170 info
.data
[2] = extra_data
[2];
5171 info
.non_fatal
= false;
5172 record_operand_error_info (opcode
, &info
);
5176 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5177 const char* error
, int lower_bound
,
5180 int data
[3] = {lower_bound
, upper_bound
, 0};
5181 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5185 /* Remove the operand error record for *OPCODE. */
5186 static void ATTRIBUTE_UNUSED
5187 remove_operand_error_record (const aarch64_opcode
*opcode
)
5189 if (opcode_has_operand_error_p (opcode
))
5191 operand_error_record
* record
= operand_error_report
.head
;
5192 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5193 operand_error_report
.head
= record
->next
;
5194 record
->next
= free_opnd_error_record_nodes
;
5195 free_opnd_error_record_nodes
= record
;
5196 if (operand_error_report
.head
== NULL
)
5198 gas_assert (operand_error_report
.tail
== record
);
5199 operand_error_report
.tail
= NULL
;
5204 /* Given the instruction in *INSTR, return the index of the best matched
5205 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5207 Return -1 if there is no qualifier sequence; return the first match
5208 if there is multiple matches found. */
5211 find_best_match (const aarch64_inst
*instr
,
5212 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5214 int i
, num_opnds
, max_num_matched
, idx
;
5216 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5219 DEBUG_TRACE ("no operand");
5223 max_num_matched
= 0;
5226 /* For each pattern. */
5227 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5230 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5232 /* Most opcodes has much fewer patterns in the list. */
5233 if (empty_qualifier_sequence_p (qualifiers
))
5235 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5239 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5240 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5243 if (num_matched
> max_num_matched
)
5245 max_num_matched
= num_matched
;
5250 DEBUG_TRACE ("return with %d", idx
);
5254 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5255 corresponding operands in *INSTR. */
5258 assign_qualifier_sequence (aarch64_inst
*instr
,
5259 const aarch64_opnd_qualifier_t
*qualifiers
)
5262 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5263 gas_assert (num_opnds
);
5264 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5265 instr
->operands
[i
].qualifier
= *qualifiers
;
5268 /* Print operands for the diagnosis purpose. */
5271 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5272 const aarch64_opnd_info
*opnds
)
5276 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5280 /* We regard the opcode operand info more, however we also look into
5281 the inst->operands to support the disassembling of the optional
5283 The two operand code should be the same in all cases, apart from
5284 when the operand can be optional. */
5285 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5286 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5289 /* Generate the operand string in STR. */
5290 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5295 strcat (buf
, i
== 0 ? " " : ", ");
5297 /* Append the operand string. */
5302 /* Send to stderr a string as information. */
5305 output_info (const char *format
, ...)
5311 file
= as_where (&line
);
5315 fprintf (stderr
, "%s:%u: ", file
, line
);
5317 fprintf (stderr
, "%s: ", file
);
5319 fprintf (stderr
, _("Info: "));
5320 va_start (args
, format
);
5321 vfprintf (stderr
, format
, args
);
5323 (void) putc ('\n', stderr
);
5326 /* Output one operand error record. */
5329 output_operand_error_record (const operand_error_record
*record
, char *str
)
5331 const aarch64_operand_error
*detail
= &record
->detail
;
5332 int idx
= detail
->index
;
5333 const aarch64_opcode
*opcode
= record
->opcode
;
5334 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5335 : AARCH64_OPND_NIL
);
5337 typedef void (*handler_t
)(const char *format
, ...);
5338 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5340 switch (detail
->kind
)
5342 case AARCH64_OPDE_NIL
:
5345 case AARCH64_OPDE_SYNTAX_ERROR
:
5346 case AARCH64_OPDE_RECOVERABLE
:
5347 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5348 case AARCH64_OPDE_OTHER_ERROR
:
5349 /* Use the prepared error message if there is, otherwise use the
5350 operand description string to describe the error. */
5351 if (detail
->error
!= NULL
)
5354 handler (_("%s -- `%s'"), detail
->error
, str
);
5356 handler (_("%s at operand %d -- `%s'"),
5357 detail
->error
, idx
+ 1, str
);
5361 gas_assert (idx
>= 0);
5362 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5363 aarch64_get_operand_desc (opd_code
), str
);
5367 case AARCH64_OPDE_INVALID_VARIANT
:
5368 handler (_("operand mismatch -- `%s'"), str
);
5369 if (verbose_error_p
)
5371 /* We will try to correct the erroneous instruction and also provide
5372 more information e.g. all other valid variants.
5374 The string representation of the corrected instruction and other
5375 valid variants are generated by
5377 1) obtaining the intermediate representation of the erroneous
5379 2) manipulating the IR, e.g. replacing the operand qualifier;
5380 3) printing out the instruction by calling the printer functions
5381 shared with the disassembler.
5383 The limitation of this method is that the exact input assembly
5384 line cannot be accurately reproduced in some cases, for example an
5385 optional operand present in the actual assembly line will be
5386 omitted in the output; likewise for the optional syntax rules,
5387 e.g. the # before the immediate. Another limitation is that the
5388 assembly symbols and relocation operations in the assembly line
5389 currently cannot be printed out in the error report. Last but not
5390 least, when there is other error(s) co-exist with this error, the
5391 'corrected' instruction may be still incorrect, e.g. given
5392 'ldnp h0,h1,[x0,#6]!'
5393 this diagnosis will provide the version:
5394 'ldnp s0,s1,[x0,#6]!'
5395 which is still not right. */
5396 size_t len
= strlen (get_mnemonic_name (str
));
5400 aarch64_inst
*inst_base
= &inst
.base
;
5401 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5404 reset_aarch64_instruction (&inst
);
5405 inst_base
->opcode
= opcode
;
5407 /* Reset the error report so that there is no side effect on the
5408 following operand parsing. */
5409 init_operand_error_report ();
5412 result
= parse_operands (str
+ len
, opcode
)
5413 && programmer_friendly_fixup (&inst
);
5414 gas_assert (result
);
5415 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5416 NULL
, NULL
, insn_sequence
);
5417 gas_assert (!result
);
5419 /* Find the most matched qualifier sequence. */
5420 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5421 gas_assert (qlf_idx
> -1);
5423 /* Assign the qualifiers. */
5424 assign_qualifier_sequence (inst_base
,
5425 opcode
->qualifiers_list
[qlf_idx
]);
5427 /* Print the hint. */
5428 output_info (_(" did you mean this?"));
5429 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5430 print_operands (buf
, opcode
, inst_base
->operands
);
5431 output_info (_(" %s"), buf
);
5433 /* Print out other variant(s) if there is any. */
5435 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5436 output_info (_(" other valid variant(s):"));
5438 /* For each pattern. */
5439 qualifiers_list
= opcode
->qualifiers_list
;
5440 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5442 /* Most opcodes has much fewer patterns in the list.
5443 First NIL qualifier indicates the end in the list. */
5444 if (empty_qualifier_sequence_p (*qualifiers_list
))
5449 /* Mnemonics name. */
5450 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5452 /* Assign the qualifiers. */
5453 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5455 /* Print instruction. */
5456 print_operands (buf
, opcode
, inst_base
->operands
);
5458 output_info (_(" %s"), buf
);
5464 case AARCH64_OPDE_UNTIED_IMMS
:
5465 handler (_("operand %d must have the same immediate value "
5466 "as operand 1 -- `%s'"),
5467 detail
->index
+ 1, str
);
5470 case AARCH64_OPDE_UNTIED_OPERAND
:
5471 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5472 detail
->index
+ 1, str
);
5475 case AARCH64_OPDE_OUT_OF_RANGE
:
5476 if (detail
->data
[0] != detail
->data
[1])
5477 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5478 detail
->error
? detail
->error
: _("immediate value"),
5479 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
5481 handler (_("%s must be %d at operand %d -- `%s'"),
5482 detail
->error
? detail
->error
: _("immediate value"),
5483 detail
->data
[0], idx
+ 1, str
);
5486 case AARCH64_OPDE_REG_LIST
:
5487 if (detail
->data
[0] == 1)
5488 handler (_("invalid number of registers in the list; "
5489 "only 1 register is expected at operand %d -- `%s'"),
5492 handler (_("invalid number of registers in the list; "
5493 "%d registers are expected at operand %d -- `%s'"),
5494 detail
->data
[0], idx
+ 1, str
);
5497 case AARCH64_OPDE_UNALIGNED
:
5498 handler (_("immediate value must be a multiple of "
5499 "%d at operand %d -- `%s'"),
5500 detail
->data
[0], idx
+ 1, str
);
5509 /* Process and output the error message about the operand mismatching.
5511 When this function is called, the operand error information had
5512 been collected for an assembly line and there will be multiple
5513 errors in the case of multiple instruction templates; output the
5514 error message that most closely describes the problem.
5516 The errors to be printed can be filtered on printing all errors
5517 or only non-fatal errors. This distinction has to be made because
5518 the error buffer may already be filled with fatal errors we don't want to
5519 print due to the different instruction templates. */
5522 output_operand_error_report (char *str
, bool non_fatal_only
)
5524 int largest_error_pos
;
5525 const char *msg
= NULL
;
5526 enum aarch64_operand_error_kind kind
;
5527 operand_error_record
*curr
;
5528 operand_error_record
*head
= operand_error_report
.head
;
5529 operand_error_record
*record
= NULL
;
5531 /* No error to report. */
5535 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5537 /* Only one error. */
5538 if (head
== operand_error_report
.tail
)
5540 /* If the only error is a non-fatal one and we don't want to print it,
5542 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5544 DEBUG_TRACE ("single opcode entry with error kind: %s",
5545 operand_mismatch_kind_names
[head
->detail
.kind
]);
5546 output_operand_error_record (head
, str
);
5551 /* Find the error kind of the highest severity. */
5552 DEBUG_TRACE ("multiple opcode entries with error kind");
5553 kind
= AARCH64_OPDE_NIL
;
5554 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5556 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5557 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5558 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5559 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5560 kind
= curr
->detail
.kind
;
5563 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5565 /* Pick up one of errors of KIND to report. */
5566 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5567 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5569 /* If we don't want to print non-fatal errors then don't consider them
5571 if (curr
->detail
.kind
!= kind
5572 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5574 /* If there are multiple errors, pick up the one with the highest
5575 mismatching operand index. In the case of multiple errors with
5576 the equally highest operand index, pick up the first one or the
5577 first one with non-NULL error message. */
5578 if (curr
->detail
.index
> largest_error_pos
5579 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5580 && curr
->detail
.error
!= NULL
))
5582 largest_error_pos
= curr
->detail
.index
;
5584 msg
= record
->detail
.error
;
5588 /* The way errors are collected in the back-end is a bit non-intuitive. But
5589 essentially, because each operand template is tried recursively you may
5590 always have errors collected from the previous tried OPND. These are
5591 usually skipped if there is one successful match. However now with the
5592 non-fatal errors we have to ignore those previously collected hard errors
5593 when we're only interested in printing the non-fatal ones. This condition
5594 prevents us from printing errors that are not appropriate, since we did
5595 match a condition, but it also has warnings that it wants to print. */
5596 if (non_fatal_only
&& !record
)
5599 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5600 DEBUG_TRACE ("Pick up error kind %s to report",
5601 operand_mismatch_kind_names
[record
->detail
.kind
]);
5604 output_operand_error_record (record
, str
);
5607 /* Write an AARCH64 instruction to buf - always little-endian. */
5609 put_aarch64_insn (char *buf
, uint32_t insn
)
5611 unsigned char *where
= (unsigned char *) buf
;
5613 where
[1] = insn
>> 8;
5614 where
[2] = insn
>> 16;
5615 where
[3] = insn
>> 24;
5619 get_aarch64_insn (char *buf
)
5621 unsigned char *where
= (unsigned char *) buf
;
5623 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5624 | ((uint32_t) where
[3] << 24)));
5629 output_inst (struct aarch64_inst
*new_inst
)
5633 to
= frag_more (INSN_SIZE
);
5635 frag_now
->tc_frag_data
.recorded
= 1;
5637 put_aarch64_insn (to
, inst
.base
.value
);
5639 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5641 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5642 INSN_SIZE
, &inst
.reloc
.exp
,
5645 DEBUG_TRACE ("Prepared relocation fix up");
5646 /* Don't check the addend value against the instruction size,
5647 that's the job of our code in md_apply_fix(). */
5648 fixp
->fx_no_overflow
= 1;
5649 if (new_inst
!= NULL
)
5650 fixp
->tc_fix_data
.inst
= new_inst
;
5651 if (aarch64_gas_internal_fixup_p ())
5653 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5654 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5655 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5659 dwarf2_emit_insn (INSN_SIZE
);
5662 /* Link together opcodes of the same name. */
5666 const aarch64_opcode
*opcode
;
5667 struct templates
*next
;
5670 typedef struct templates templates
;
5673 lookup_mnemonic (const char *start
, int len
)
5675 templates
*templ
= NULL
;
5677 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5681 /* Subroutine of md_assemble, responsible for looking up the primary
5682 opcode from the mnemonic the user wrote. STR points to the
5683 beginning of the mnemonic. */
5686 opcode_lookup (char **str
)
5688 char *end
, *base
, *dot
;
5689 const aarch64_cond
*cond
;
5693 /* Scan up to the end of the mnemonic, which must end in white space,
5694 '.', or end of string. */
5696 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5697 if (*end
== '.' && !dot
)
5700 if (end
== base
|| dot
== base
)
5703 inst
.cond
= COND_ALWAYS
;
5705 /* Handle a possible condition. */
5708 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5711 inst
.cond
= cond
->value
;
5727 if (inst
.cond
== COND_ALWAYS
)
5729 /* Look for unaffixed mnemonic. */
5730 return lookup_mnemonic (base
, len
);
5734 /* append ".c" to mnemonic if conditional */
5735 memcpy (condname
, base
, len
);
5736 memcpy (condname
+ len
, ".c", 2);
5739 return lookup_mnemonic (base
, len
);
5745 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5746 to a corresponding operand qualifier. */
5748 static inline aarch64_opnd_qualifier_t
5749 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5751 /* Element size in bytes indexed by vector_el_type. */
5752 const unsigned char ele_size
[5]
5754 const unsigned int ele_base
[5] =
5756 AARCH64_OPND_QLF_V_4B
,
5757 AARCH64_OPND_QLF_V_2H
,
5758 AARCH64_OPND_QLF_V_2S
,
5759 AARCH64_OPND_QLF_V_1D
,
5760 AARCH64_OPND_QLF_V_1Q
5763 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5764 goto vectype_conversion_fail
;
5766 if (vectype
->type
== NT_zero
)
5767 return AARCH64_OPND_QLF_P_Z
;
5768 if (vectype
->type
== NT_merge
)
5769 return AARCH64_OPND_QLF_P_M
;
5771 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5773 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5775 /* Special case S_4B. */
5776 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5777 return AARCH64_OPND_QLF_S_4B
;
5779 /* Special case S_2H. */
5780 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5781 return AARCH64_OPND_QLF_S_2H
;
5783 /* Vector element register. */
5784 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5788 /* Vector register. */
5789 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5792 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5793 goto vectype_conversion_fail
;
5795 /* The conversion is by calculating the offset from the base operand
5796 qualifier for the vector type. The operand qualifiers are regular
5797 enough that the offset can established by shifting the vector width by
5798 a vector-type dependent amount. */
5800 if (vectype
->type
== NT_b
)
5802 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5804 else if (vectype
->type
>= NT_d
)
5809 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5810 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5811 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5815 vectype_conversion_fail
:
5816 first_error (_("bad vector arrangement type"));
5817 return AARCH64_OPND_QLF_NIL
;
5820 /* Process an optional operand that is found omitted from the assembly line.
5821 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5822 instruction's opcode entry while IDX is the index of this omitted operand.
5826 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5827 int idx
, aarch64_opnd_info
*operand
)
5829 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5830 gas_assert (optional_operand_p (opcode
, idx
));
5831 gas_assert (!operand
->present
);
5835 case AARCH64_OPND_Rd
:
5836 case AARCH64_OPND_Rn
:
5837 case AARCH64_OPND_Rm
:
5838 case AARCH64_OPND_Rt
:
5839 case AARCH64_OPND_Rt2
:
5840 case AARCH64_OPND_Rt_LS64
:
5841 case AARCH64_OPND_Rt_SP
:
5842 case AARCH64_OPND_Rs
:
5843 case AARCH64_OPND_Ra
:
5844 case AARCH64_OPND_Rt_SYS
:
5845 case AARCH64_OPND_Rd_SP
:
5846 case AARCH64_OPND_Rn_SP
:
5847 case AARCH64_OPND_Rm_SP
:
5848 case AARCH64_OPND_Fd
:
5849 case AARCH64_OPND_Fn
:
5850 case AARCH64_OPND_Fm
:
5851 case AARCH64_OPND_Fa
:
5852 case AARCH64_OPND_Ft
:
5853 case AARCH64_OPND_Ft2
:
5854 case AARCH64_OPND_Sd
:
5855 case AARCH64_OPND_Sn
:
5856 case AARCH64_OPND_Sm
:
5857 case AARCH64_OPND_Va
:
5858 case AARCH64_OPND_Vd
:
5859 case AARCH64_OPND_Vn
:
5860 case AARCH64_OPND_Vm
:
5861 case AARCH64_OPND_VdD1
:
5862 case AARCH64_OPND_VnD1
:
5863 operand
->reg
.regno
= default_value
;
5866 case AARCH64_OPND_Ed
:
5867 case AARCH64_OPND_En
:
5868 case AARCH64_OPND_Em
:
5869 case AARCH64_OPND_Em16
:
5870 case AARCH64_OPND_SM3_IMM2
:
5871 operand
->reglane
.regno
= default_value
;
5874 case AARCH64_OPND_IDX
:
5875 case AARCH64_OPND_BIT_NUM
:
5876 case AARCH64_OPND_IMMR
:
5877 case AARCH64_OPND_IMMS
:
5878 case AARCH64_OPND_SHLL_IMM
:
5879 case AARCH64_OPND_IMM_VLSL
:
5880 case AARCH64_OPND_IMM_VLSR
:
5881 case AARCH64_OPND_CCMP_IMM
:
5882 case AARCH64_OPND_FBITS
:
5883 case AARCH64_OPND_UIMM4
:
5884 case AARCH64_OPND_UIMM3_OP1
:
5885 case AARCH64_OPND_UIMM3_OP2
:
5886 case AARCH64_OPND_IMM
:
5887 case AARCH64_OPND_IMM_2
:
5888 case AARCH64_OPND_WIDTH
:
5889 case AARCH64_OPND_UIMM7
:
5890 case AARCH64_OPND_NZCV
:
5891 case AARCH64_OPND_SVE_PATTERN
:
5892 case AARCH64_OPND_SVE_PRFOP
:
5893 operand
->imm
.value
= default_value
;
5896 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5897 operand
->imm
.value
= default_value
;
5898 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5899 operand
->shifter
.amount
= 1;
5902 case AARCH64_OPND_EXCEPTION
:
5903 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5906 case AARCH64_OPND_BARRIER_ISB
:
5907 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5910 case AARCH64_OPND_BTI_TARGET
:
5911 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5919 /* Process the relocation type for move wide instructions.
5920 Return TRUE on success; otherwise return FALSE. */
5923 process_movw_reloc_info (void)
5928 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5930 if (inst
.base
.opcode
->op
== OP_MOVK
)
5931 switch (inst
.reloc
.type
)
5933 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5934 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5935 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5936 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5937 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5938 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5939 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5940 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5941 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5942 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5943 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5945 (_("the specified relocation type is not allowed for MOVK"));
5951 switch (inst
.reloc
.type
)
5953 case BFD_RELOC_AARCH64_MOVW_G0
:
5954 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5955 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5956 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5957 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5958 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5959 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5960 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5961 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5962 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5963 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5964 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5965 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5968 case BFD_RELOC_AARCH64_MOVW_G1
:
5969 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5970 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5971 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5972 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5973 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5974 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5975 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5976 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5977 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5978 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5979 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5980 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5983 case BFD_RELOC_AARCH64_MOVW_G2
:
5984 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5985 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5986 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5987 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5988 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5989 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5992 set_fatal_syntax_error
5993 (_("the specified relocation type is not allowed for 32-bit "
5999 case BFD_RELOC_AARCH64_MOVW_G3
:
6000 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6003 set_fatal_syntax_error
6004 (_("the specified relocation type is not allowed for 32-bit "
6011 /* More cases should be added when more MOVW-related relocation types
6012 are supported in GAS. */
6013 gas_assert (aarch64_gas_internal_fixup_p ());
6014 /* The shift amount should have already been set by the parser. */
6017 inst
.base
.operands
[1].shifter
.amount
= shift
;
6021 /* A primitive log calculator. */
6023 static inline unsigned int
6024 get_logsz (unsigned int size
)
6026 const unsigned char ls
[16] =
6027 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6033 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6034 return ls
[size
- 1];
6037 /* Determine and return the real reloc type code for an instruction
6038 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6040 static inline bfd_reloc_code_real_type
6041 ldst_lo12_determine_real_reloc_type (void)
6043 unsigned logsz
, max_logsz
;
6044 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6045 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6047 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6049 BFD_RELOC_AARCH64_LDST8_LO12
,
6050 BFD_RELOC_AARCH64_LDST16_LO12
,
6051 BFD_RELOC_AARCH64_LDST32_LO12
,
6052 BFD_RELOC_AARCH64_LDST64_LO12
,
6053 BFD_RELOC_AARCH64_LDST128_LO12
6056 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6057 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6058 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6059 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6060 BFD_RELOC_AARCH64_NONE
6063 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6064 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6065 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6066 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6067 BFD_RELOC_AARCH64_NONE
6070 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6071 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6072 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6073 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6074 BFD_RELOC_AARCH64_NONE
6077 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6078 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6079 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6080 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6081 BFD_RELOC_AARCH64_NONE
6085 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6086 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6088 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6090 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6092 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6093 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6095 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6097 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6099 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6101 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6103 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6104 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6105 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6106 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6111 if (logsz
> max_logsz
)
6113 /* SEE PR 27904 for an example of this. */
6114 set_fatal_syntax_error
6115 (_("relocation qualifier does not match instruction size"));
6116 return BFD_RELOC_AARCH64_NONE
;
6119 /* In reloc.c, these pseudo relocation types should be defined in similar
6120 order as above reloc_ldst_lo12 array. Because the array index calculation
6121 below relies on this. */
6122 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6125 /* Check whether a register list REGINFO is valid. The registers must be
6126 numbered in increasing order (modulo 32), in increments of one or two.
6128 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6131 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6134 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6136 uint32_t i
, nb_regs
, prev_regno
, incr
;
6138 nb_regs
= 1 + (reginfo
& 0x3);
6140 prev_regno
= reginfo
& 0x1f;
6141 incr
= accept_alternate
? 2 : 1;
6143 for (i
= 1; i
< nb_regs
; ++i
)
6145 uint32_t curr_regno
;
6147 curr_regno
= reginfo
& 0x1f;
6148 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6150 prev_regno
= curr_regno
;
6156 /* Generic instruction operand parser. This does no encoding and no
6157 semantic validation; it merely squirrels values away in the inst
6158 structure. Returns TRUE or FALSE depending on whether the
6159 specified grammar matched. */
6162 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6165 char *backtrack_pos
= 0;
6166 const enum aarch64_opnd
*operands
= opcode
->operands
;
6167 aarch64_reg_type imm_reg_type
;
6170 skip_whitespace (str
);
6172 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6173 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6175 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6177 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6180 const reg_entry
*reg
;
6181 int comma_skipped_p
= 0;
6182 aarch64_reg_type rtype
;
6183 struct vector_type_el vectype
;
6184 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6185 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6186 aarch64_reg_type reg_type
;
6188 DEBUG_TRACE ("parse operand %d", i
);
6190 /* Assign the operand code. */
6191 info
->type
= operands
[i
];
6193 if (optional_operand_p (opcode
, i
))
6195 /* Remember where we are in case we need to backtrack. */
6196 gas_assert (!backtrack_pos
);
6197 backtrack_pos
= str
;
6200 /* Expect comma between operands; the backtrack mechanism will take
6201 care of cases of omitted optional operand. */
6202 if (i
> 0 && ! skip_past_char (&str
, ','))
6204 set_syntax_error (_("comma expected between operands"));
6208 comma_skipped_p
= 1;
6210 switch (operands
[i
])
6212 case AARCH64_OPND_Rd
:
6213 case AARCH64_OPND_Rn
:
6214 case AARCH64_OPND_Rm
:
6215 case AARCH64_OPND_Rt
:
6216 case AARCH64_OPND_Rt2
:
6217 case AARCH64_OPND_Rs
:
6218 case AARCH64_OPND_Ra
:
6219 case AARCH64_OPND_Rt_LS64
:
6220 case AARCH64_OPND_Rt_SYS
:
6221 case AARCH64_OPND_PAIRREG
:
6222 case AARCH64_OPND_SVE_Rm
:
6223 po_int_reg_or_fail (REG_TYPE_R_Z
);
6225 /* In LS64 load/store instructions Rt register number must be even
6227 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6229 /* We've already checked if this is valid register.
6230 This will check if register number (Rt) is not undefined for LS64
6232 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6233 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6235 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6241 case AARCH64_OPND_Rd_SP
:
6242 case AARCH64_OPND_Rn_SP
:
6243 case AARCH64_OPND_Rt_SP
:
6244 case AARCH64_OPND_SVE_Rn_SP
:
6245 case AARCH64_OPND_Rm_SP
:
6246 po_int_reg_or_fail (REG_TYPE_R_SP
);
6249 case AARCH64_OPND_Rm_EXT
:
6250 case AARCH64_OPND_Rm_SFT
:
6251 po_misc_or_fail (parse_shifter_operand
6252 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6254 : SHIFTED_LOGIC_IMM
)));
6255 if (!info
->shifter
.operator_present
)
6257 /* Default to LSL if not present. Libopcodes prefers shifter
6258 kind to be explicit. */
6259 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6260 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6261 /* For Rm_EXT, libopcodes will carry out further check on whether
6262 or not stack pointer is used in the instruction (Recall that
6263 "the extend operator is not optional unless at least one of
6264 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6268 case AARCH64_OPND_Fd
:
6269 case AARCH64_OPND_Fn
:
6270 case AARCH64_OPND_Fm
:
6271 case AARCH64_OPND_Fa
:
6272 case AARCH64_OPND_Ft
:
6273 case AARCH64_OPND_Ft2
:
6274 case AARCH64_OPND_Sd
:
6275 case AARCH64_OPND_Sn
:
6276 case AARCH64_OPND_Sm
:
6277 case AARCH64_OPND_SVE_VZn
:
6278 case AARCH64_OPND_SVE_Vd
:
6279 case AARCH64_OPND_SVE_Vm
:
6280 case AARCH64_OPND_SVE_Vn
:
6281 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6282 if (val
== PARSE_FAIL
)
6284 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6287 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6289 info
->reg
.regno
= val
;
6290 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6293 case AARCH64_OPND_SVE_Pd
:
6294 case AARCH64_OPND_SVE_Pg3
:
6295 case AARCH64_OPND_SVE_Pg4_5
:
6296 case AARCH64_OPND_SVE_Pg4_10
:
6297 case AARCH64_OPND_SVE_Pg4_16
:
6298 case AARCH64_OPND_SVE_Pm
:
6299 case AARCH64_OPND_SVE_Pn
:
6300 case AARCH64_OPND_SVE_Pt
:
6301 case AARCH64_OPND_SME_Pm
:
6302 reg_type
= REG_TYPE_PN
;
6305 case AARCH64_OPND_SVE_Za_5
:
6306 case AARCH64_OPND_SVE_Za_16
:
6307 case AARCH64_OPND_SVE_Zd
:
6308 case AARCH64_OPND_SVE_Zm_5
:
6309 case AARCH64_OPND_SVE_Zm_16
:
6310 case AARCH64_OPND_SVE_Zn
:
6311 case AARCH64_OPND_SVE_Zt
:
6312 reg_type
= REG_TYPE_ZN
;
6315 case AARCH64_OPND_Va
:
6316 case AARCH64_OPND_Vd
:
6317 case AARCH64_OPND_Vn
:
6318 case AARCH64_OPND_Vm
:
6319 reg_type
= REG_TYPE_VN
;
6321 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6322 if (val
== PARSE_FAIL
)
6324 first_error (_(get_reg_expected_msg (reg_type
)));
6327 if (vectype
.defined
& NTA_HASINDEX
)
6330 info
->reg
.regno
= val
;
6331 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6332 && vectype
.type
== NT_invtype
)
6333 /* Unqualified Pn and Zn registers are allowed in certain
6334 contexts. Rely on F_STRICT qualifier checking to catch
6336 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6339 info
->qualifier
= vectype_to_qualifier (&vectype
);
6340 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6345 case AARCH64_OPND_VdD1
:
6346 case AARCH64_OPND_VnD1
:
6347 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6348 if (val
== PARSE_FAIL
)
6350 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6353 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6355 set_fatal_syntax_error
6356 (_("the top half of a 128-bit FP/SIMD register is expected"));
6359 info
->reg
.regno
= val
;
6360 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6361 here; it is correct for the purpose of encoding/decoding since
6362 only the register number is explicitly encoded in the related
6363 instructions, although this appears a bit hacky. */
6364 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6367 case AARCH64_OPND_SVE_Zm3_INDEX
:
6368 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6369 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6370 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6371 case AARCH64_OPND_SVE_Zm4_INDEX
:
6372 case AARCH64_OPND_SVE_Zn_INDEX
:
6373 reg_type
= REG_TYPE_ZN
;
6374 goto vector_reg_index
;
6376 case AARCH64_OPND_Ed
:
6377 case AARCH64_OPND_En
:
6378 case AARCH64_OPND_Em
:
6379 case AARCH64_OPND_Em16
:
6380 case AARCH64_OPND_SM3_IMM2
:
6381 reg_type
= REG_TYPE_VN
;
6383 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6384 if (val
== PARSE_FAIL
)
6386 first_error (_(get_reg_expected_msg (reg_type
)));
6389 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6392 info
->reglane
.regno
= val
;
6393 info
->reglane
.index
= vectype
.index
;
6394 info
->qualifier
= vectype_to_qualifier (&vectype
);
6395 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6399 case AARCH64_OPND_SVE_ZnxN
:
6400 case AARCH64_OPND_SVE_ZtxN
:
6401 reg_type
= REG_TYPE_ZN
;
6402 goto vector_reg_list
;
6404 case AARCH64_OPND_LVn
:
6405 case AARCH64_OPND_LVt
:
6406 case AARCH64_OPND_LVt_AL
:
6407 case AARCH64_OPND_LEt
:
6408 reg_type
= REG_TYPE_VN
;
6410 if (reg_type
== REG_TYPE_ZN
6411 && get_opcode_dependent_value (opcode
) == 1
6414 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6415 if (val
== PARSE_FAIL
)
6417 first_error (_(get_reg_expected_msg (reg_type
)));
6420 info
->reglist
.first_regno
= val
;
6421 info
->reglist
.num_regs
= 1;
6425 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6426 if (val
== PARSE_FAIL
)
6429 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6431 set_fatal_syntax_error (_("invalid register list"));
6435 if (vectype
.width
!= 0 && *str
!= ',')
6437 set_fatal_syntax_error
6438 (_("expected element type rather than vector type"));
6442 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6443 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6445 if (operands
[i
] == AARCH64_OPND_LEt
)
6447 if (!(vectype
.defined
& NTA_HASINDEX
))
6449 info
->reglist
.has_index
= 1;
6450 info
->reglist
.index
= vectype
.index
;
6454 if (vectype
.defined
& NTA_HASINDEX
)
6456 if (!(vectype
.defined
& NTA_HASTYPE
))
6458 if (reg_type
== REG_TYPE_ZN
)
6459 set_fatal_syntax_error (_("missing type suffix"));
6463 info
->qualifier
= vectype_to_qualifier (&vectype
);
6464 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6468 case AARCH64_OPND_CRn
:
6469 case AARCH64_OPND_CRm
:
6471 char prefix
= *(str
++);
6472 if (prefix
!= 'c' && prefix
!= 'C')
6475 po_imm_nc_or_fail ();
6478 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6481 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6482 info
->imm
.value
= val
;
6486 case AARCH64_OPND_SHLL_IMM
:
6487 case AARCH64_OPND_IMM_VLSR
:
6488 po_imm_or_fail (1, 64);
6489 info
->imm
.value
= val
;
6492 case AARCH64_OPND_CCMP_IMM
:
6493 case AARCH64_OPND_SIMM5
:
6494 case AARCH64_OPND_FBITS
:
6495 case AARCH64_OPND_TME_UIMM16
:
6496 case AARCH64_OPND_UIMM4
:
6497 case AARCH64_OPND_UIMM4_ADDG
:
6498 case AARCH64_OPND_UIMM10
:
6499 case AARCH64_OPND_UIMM3_OP1
:
6500 case AARCH64_OPND_UIMM3_OP2
:
6501 case AARCH64_OPND_IMM_VLSL
:
6502 case AARCH64_OPND_IMM
:
6503 case AARCH64_OPND_IMM_2
:
6504 case AARCH64_OPND_WIDTH
:
6505 case AARCH64_OPND_SVE_INV_LIMM
:
6506 case AARCH64_OPND_SVE_LIMM
:
6507 case AARCH64_OPND_SVE_LIMM_MOV
:
6508 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6509 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6510 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6511 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6512 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6513 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6514 case AARCH64_OPND_SVE_SIMM5
:
6515 case AARCH64_OPND_SVE_SIMM5B
:
6516 case AARCH64_OPND_SVE_SIMM6
:
6517 case AARCH64_OPND_SVE_SIMM8
:
6518 case AARCH64_OPND_SVE_UIMM3
:
6519 case AARCH64_OPND_SVE_UIMM7
:
6520 case AARCH64_OPND_SVE_UIMM8
:
6521 case AARCH64_OPND_SVE_UIMM8_53
:
6522 case AARCH64_OPND_IMM_ROT1
:
6523 case AARCH64_OPND_IMM_ROT2
:
6524 case AARCH64_OPND_IMM_ROT3
:
6525 case AARCH64_OPND_SVE_IMM_ROT1
:
6526 case AARCH64_OPND_SVE_IMM_ROT2
:
6527 case AARCH64_OPND_SVE_IMM_ROT3
:
6528 po_imm_nc_or_fail ();
6529 info
->imm
.value
= val
;
6532 case AARCH64_OPND_SVE_AIMM
:
6533 case AARCH64_OPND_SVE_ASIMM
:
6534 po_imm_nc_or_fail ();
6535 info
->imm
.value
= val
;
6536 skip_whitespace (str
);
6537 if (skip_past_comma (&str
))
6538 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6540 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6543 case AARCH64_OPND_SVE_PATTERN
:
6544 po_enum_or_fail (aarch64_sve_pattern_array
);
6545 info
->imm
.value
= val
;
6548 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6549 po_enum_or_fail (aarch64_sve_pattern_array
);
6550 info
->imm
.value
= val
;
6551 if (skip_past_comma (&str
)
6552 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6554 if (!info
->shifter
.operator_present
)
6556 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6557 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6558 info
->shifter
.amount
= 1;
6562 case AARCH64_OPND_SVE_PRFOP
:
6563 po_enum_or_fail (aarch64_sve_prfop_array
);
6564 info
->imm
.value
= val
;
6567 case AARCH64_OPND_UIMM7
:
6568 po_imm_or_fail (0, 127);
6569 info
->imm
.value
= val
;
6572 case AARCH64_OPND_IDX
:
6573 case AARCH64_OPND_MASK
:
6574 case AARCH64_OPND_BIT_NUM
:
6575 case AARCH64_OPND_IMMR
:
6576 case AARCH64_OPND_IMMS
:
6577 po_imm_or_fail (0, 63);
6578 info
->imm
.value
= val
;
6581 case AARCH64_OPND_IMM0
:
6582 po_imm_nc_or_fail ();
6585 set_fatal_syntax_error (_("immediate zero expected"));
6588 info
->imm
.value
= 0;
6591 case AARCH64_OPND_FPIMM0
:
6594 bool res1
= false, res2
= false;
6595 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6596 it is probably not worth the effort to support it. */
6597 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6600 || !(res2
= parse_constant_immediate (&str
, &val
,
6603 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6605 info
->imm
.value
= 0;
6606 info
->imm
.is_fp
= 1;
6609 set_fatal_syntax_error (_("immediate zero expected"));
6613 case AARCH64_OPND_IMM_MOV
:
6616 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6617 reg_name_p (str
, REG_TYPE_VN
))
6620 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6621 GE_OPT_PREFIX
, REJECT_ABSENT
,
6622 NORMAL_RESOLUTION
));
6623 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6624 later. fix_mov_imm_insn will try to determine a machine
6625 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6626 message if the immediate cannot be moved by a single
6628 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6629 inst
.base
.operands
[i
].skip
= 1;
6633 case AARCH64_OPND_SIMD_IMM
:
6634 case AARCH64_OPND_SIMD_IMM_SFT
:
6635 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6637 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6639 /* need_libopcodes_p */ 1,
6642 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6643 shift, we don't check it here; we leave the checking to
6644 the libopcodes (operand_general_constraint_met_p). By
6645 doing this, we achieve better diagnostics. */
6646 if (skip_past_comma (&str
)
6647 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6649 if (!info
->shifter
.operator_present
6650 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6652 /* Default to LSL if not present. Libopcodes prefers shifter
6653 kind to be explicit. */
6654 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6655 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6659 case AARCH64_OPND_FPIMM
:
6660 case AARCH64_OPND_SIMD_FPIMM
:
6661 case AARCH64_OPND_SVE_FPIMM8
:
6666 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6667 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6668 || !aarch64_imm_float_p (qfloat
))
6671 set_fatal_syntax_error (_("invalid floating-point"
6675 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6676 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6680 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6681 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6682 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6687 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6688 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6691 set_fatal_syntax_error (_("invalid floating-point"
6695 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6696 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6700 case AARCH64_OPND_LIMM
:
6701 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6702 SHIFTED_LOGIC_IMM
));
6703 if (info
->shifter
.operator_present
)
6705 set_fatal_syntax_error
6706 (_("shift not allowed for bitmask immediate"));
6709 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6711 /* need_libopcodes_p */ 1,
6715 case AARCH64_OPND_AIMM
:
6716 if (opcode
->op
== OP_ADD
)
6717 /* ADD may have relocation types. */
6718 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6719 SHIFTED_ARITH_IMM
));
6721 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6722 SHIFTED_ARITH_IMM
));
6723 switch (inst
.reloc
.type
)
6725 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6726 info
->shifter
.amount
= 12;
6728 case BFD_RELOC_UNUSED
:
6729 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6730 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6731 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6732 inst
.reloc
.pc_rel
= 0;
6737 info
->imm
.value
= 0;
6738 if (!info
->shifter
.operator_present
)
6740 /* Default to LSL if not present. Libopcodes prefers shifter
6741 kind to be explicit. */
6742 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6743 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6747 case AARCH64_OPND_HALF
:
6749 /* #<imm16> or relocation. */
6750 int internal_fixup_p
;
6751 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6752 if (internal_fixup_p
)
6753 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6754 skip_whitespace (str
);
6755 if (skip_past_comma (&str
))
6757 /* {, LSL #<shift>} */
6758 if (! aarch64_gas_internal_fixup_p ())
6760 set_fatal_syntax_error (_("can't mix relocation modifier "
6761 "with explicit shift"));
6764 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6767 inst
.base
.operands
[i
].shifter
.amount
= 0;
6768 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6769 inst
.base
.operands
[i
].imm
.value
= 0;
6770 if (! process_movw_reloc_info ())
6775 case AARCH64_OPND_EXCEPTION
:
6776 case AARCH64_OPND_UNDEFINED
:
6777 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6779 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6781 /* need_libopcodes_p */ 0,
6785 case AARCH64_OPND_NZCV
:
6787 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6791 info
->imm
.value
= nzcv
->value
;
6794 po_imm_or_fail (0, 15);
6795 info
->imm
.value
= val
;
6799 case AARCH64_OPND_COND
:
6800 case AARCH64_OPND_COND1
:
6805 while (ISALPHA (*str
));
6806 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6807 if (info
->cond
== NULL
)
6809 set_syntax_error (_("invalid condition"));
6812 else if (operands
[i
] == AARCH64_OPND_COND1
6813 && (info
->cond
->value
& 0xe) == 0xe)
6815 /* Do not allow AL or NV. */
6816 set_default_error ();
6822 case AARCH64_OPND_ADDR_ADRP
:
6823 po_misc_or_fail (parse_adrp (&str
));
6824 /* Clear the value as operand needs to be relocated. */
6825 info
->imm
.value
= 0;
6828 case AARCH64_OPND_ADDR_PCREL14
:
6829 case AARCH64_OPND_ADDR_PCREL19
:
6830 case AARCH64_OPND_ADDR_PCREL21
:
6831 case AARCH64_OPND_ADDR_PCREL26
:
6832 po_misc_or_fail (parse_address (&str
, info
));
6833 if (!info
->addr
.pcrel
)
6835 set_syntax_error (_("invalid pc-relative address"));
6838 if (inst
.gen_lit_pool
6839 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6841 /* Only permit "=value" in the literal load instructions.
6842 The literal will be generated by programmer_friendly_fixup. */
6843 set_syntax_error (_("invalid use of \"=immediate\""));
6846 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6848 set_syntax_error (_("unrecognized relocation suffix"));
6851 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6853 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6854 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6858 info
->imm
.value
= 0;
6859 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6860 switch (opcode
->iclass
)
6864 /* e.g. CBZ or B.COND */
6865 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6866 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6870 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6871 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6875 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6877 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6878 : BFD_RELOC_AARCH64_JUMP26
;
6881 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6882 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6885 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6886 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6892 inst
.reloc
.pc_rel
= 1;
6896 case AARCH64_OPND_ADDR_SIMPLE
:
6897 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6899 /* [<Xn|SP>{, #<simm>}] */
6901 /* First use the normal address-parsing routines, to get
6902 the usual syntax errors. */
6903 po_misc_or_fail (parse_address (&str
, info
));
6904 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6905 || !info
->addr
.preind
|| info
->addr
.postind
6906 || info
->addr
.writeback
)
6908 set_syntax_error (_("invalid addressing mode"));
6912 /* Then retry, matching the specific syntax of these addresses. */
6914 po_char_or_fail ('[');
6915 po_reg_or_fail (REG_TYPE_R64_SP
);
6916 /* Accept optional ", #0". */
6917 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6918 && skip_past_char (&str
, ','))
6920 skip_past_char (&str
, '#');
6921 if (! skip_past_char (&str
, '0'))
6923 set_fatal_syntax_error
6924 (_("the optional immediate offset can only be 0"));
6928 po_char_or_fail (']');
6932 case AARCH64_OPND_ADDR_REGOFF
:
6933 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6934 po_misc_or_fail (parse_address (&str
, info
));
6936 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6937 || !info
->addr
.preind
|| info
->addr
.postind
6938 || info
->addr
.writeback
)
6940 set_syntax_error (_("invalid addressing mode"));
6943 if (!info
->shifter
.operator_present
)
6945 /* Default to LSL if not present. Libopcodes prefers shifter
6946 kind to be explicit. */
6947 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6948 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6950 /* Qualifier to be deduced by libopcodes. */
6953 case AARCH64_OPND_ADDR_SIMM7
:
6954 po_misc_or_fail (parse_address (&str
, info
));
6955 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6956 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6958 set_syntax_error (_("invalid addressing mode"));
6961 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6963 set_syntax_error (_("relocation not allowed"));
6966 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6968 /* need_libopcodes_p */ 1,
6972 case AARCH64_OPND_ADDR_SIMM9
:
6973 case AARCH64_OPND_ADDR_SIMM9_2
:
6974 case AARCH64_OPND_ADDR_SIMM11
:
6975 case AARCH64_OPND_ADDR_SIMM13
:
6976 po_misc_or_fail (parse_address (&str
, info
));
6977 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6978 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6979 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6980 && info
->addr
.writeback
))
6982 set_syntax_error (_("invalid addressing mode"));
6985 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6987 set_syntax_error (_("relocation not allowed"));
6990 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6992 /* need_libopcodes_p */ 1,
6996 case AARCH64_OPND_ADDR_SIMM10
:
6997 case AARCH64_OPND_ADDR_OFFSET
:
6998 po_misc_or_fail (parse_address (&str
, info
));
6999 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7000 || !info
->addr
.preind
|| info
->addr
.postind
)
7002 set_syntax_error (_("invalid addressing mode"));
7005 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7007 set_syntax_error (_("relocation not allowed"));
7010 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7012 /* need_libopcodes_p */ 1,
7016 case AARCH64_OPND_ADDR_UIMM12
:
7017 po_misc_or_fail (parse_address (&str
, info
));
7018 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7019 || !info
->addr
.preind
|| info
->addr
.writeback
)
7021 set_syntax_error (_("invalid addressing mode"));
7024 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7025 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7026 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7028 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7030 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7032 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7034 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7035 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7036 /* Leave qualifier to be determined by libopcodes. */
7039 case AARCH64_OPND_SIMD_ADDR_POST
:
7040 /* [<Xn|SP>], <Xm|#<amount>> */
7041 po_misc_or_fail (parse_address (&str
, info
));
7042 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7044 set_syntax_error (_("invalid addressing mode"));
7047 if (!info
->addr
.offset
.is_reg
)
7049 if (inst
.reloc
.exp
.X_op
== O_constant
)
7050 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7053 set_fatal_syntax_error
7054 (_("writeback value must be an immediate constant"));
7061 case AARCH64_OPND_SME_SM_ZA
:
7063 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7065 set_syntax_error (_("unknown or missing PSTATE field name"));
7068 info
->reg
.regno
= val
;
7071 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7072 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7073 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7074 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7075 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7076 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7077 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7078 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7079 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7080 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7081 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7082 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7083 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7084 /* [X<n>{, #imm, MUL VL}]
7086 but recognizing SVE registers. */
7087 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7088 &offset_qualifier
));
7089 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7091 set_syntax_error (_("invalid addressing mode"));
7095 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7096 || !info
->addr
.preind
|| info
->addr
.writeback
)
7098 set_syntax_error (_("invalid addressing mode"));
7101 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7102 || inst
.reloc
.exp
.X_op
!= O_constant
)
7104 /* Make sure this has priority over
7105 "invalid addressing mode". */
7106 set_fatal_syntax_error (_("constant offset required"));
7109 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7112 case AARCH64_OPND_SVE_ADDR_R
:
7113 /* [<Xn|SP>{, <R><m>}]
7114 but recognizing SVE registers. */
7115 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7116 &offset_qualifier
));
7117 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7119 offset_qualifier
= AARCH64_OPND_QLF_X
;
7120 info
->addr
.offset
.is_reg
= 1;
7121 info
->addr
.offset
.regno
= 31;
7123 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7124 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7126 set_syntax_error (_("invalid addressing mode"));
7131 case AARCH64_OPND_SVE_ADDR_RR
:
7132 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7133 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7134 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7135 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7136 case AARCH64_OPND_SVE_ADDR_RX
:
7137 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7138 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7139 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7140 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7141 but recognizing SVE registers. */
7142 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7143 &offset_qualifier
));
7144 if (base_qualifier
!= AARCH64_OPND_QLF_X
7145 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7147 set_syntax_error (_("invalid addressing mode"));
7152 case AARCH64_OPND_SVE_ADDR_RZ
:
7153 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7154 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7155 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7156 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7157 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7158 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7159 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7160 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7161 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7162 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7163 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7164 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7165 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7166 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7167 &offset_qualifier
));
7168 if (base_qualifier
!= AARCH64_OPND_QLF_X
7169 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7170 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7172 set_syntax_error (_("invalid addressing mode"));
7175 info
->qualifier
= offset_qualifier
;
7178 case AARCH64_OPND_SVE_ADDR_ZX
:
7179 /* [Zn.<T>{, <Xm>}]. */
7180 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7181 &offset_qualifier
));
7183 base_qualifier either S_S or S_D
7184 offset_qualifier must be X
7186 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7187 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7188 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7190 set_syntax_error (_("invalid addressing mode"));
7193 info
->qualifier
= base_qualifier
;
7194 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7195 || !info
->addr
.preind
|| info
->addr
.writeback
7196 || info
->shifter
.operator_present
!= 0)
7198 set_syntax_error (_("invalid addressing mode"));
7201 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7205 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7206 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7207 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7208 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7209 /* [Z<n>.<T>{, #imm}] */
7210 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7211 &offset_qualifier
));
7212 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7213 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7215 set_syntax_error (_("invalid addressing mode"));
7218 info
->qualifier
= base_qualifier
;
7221 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7222 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7223 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7224 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7225 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7229 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7231 here since we get better error messages by leaving it to
7232 the qualifier checking routines. */
7233 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7234 &offset_qualifier
));
7235 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7236 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7237 || offset_qualifier
!= base_qualifier
)
7239 set_syntax_error (_("invalid addressing mode"));
7242 info
->qualifier
= base_qualifier
;
7245 case AARCH64_OPND_SYSREG
:
7247 uint32_t sysreg_flags
;
7248 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7249 &sysreg_flags
)) == PARSE_FAIL
)
7251 set_syntax_error (_("unknown or missing system register name"));
7254 inst
.base
.operands
[i
].sysreg
.value
= val
;
7255 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7259 case AARCH64_OPND_PSTATEFIELD
:
7261 uint32_t sysreg_flags
;
7262 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7263 &sysreg_flags
)) == PARSE_FAIL
)
7265 set_syntax_error (_("unknown or missing PSTATE field name"));
7268 inst
.base
.operands
[i
].pstatefield
= val
;
7269 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7273 case AARCH64_OPND_SYSREG_IC
:
7274 inst
.base
.operands
[i
].sysins_op
=
7275 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7278 case AARCH64_OPND_SYSREG_DC
:
7279 inst
.base
.operands
[i
].sysins_op
=
7280 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7283 case AARCH64_OPND_SYSREG_AT
:
7284 inst
.base
.operands
[i
].sysins_op
=
7285 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7288 case AARCH64_OPND_SYSREG_SR
:
7289 inst
.base
.operands
[i
].sysins_op
=
7290 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7293 case AARCH64_OPND_SYSREG_TLBI
:
7294 inst
.base
.operands
[i
].sysins_op
=
7295 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7297 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7299 set_fatal_syntax_error ( _("unknown or missing operation name"));
7304 case AARCH64_OPND_BARRIER
:
7305 case AARCH64_OPND_BARRIER_ISB
:
7306 val
= parse_barrier (&str
);
7307 if (val
!= PARSE_FAIL
7308 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7310 /* ISB only accepts options name 'sy'. */
7312 (_("the specified option is not accepted in ISB"));
7313 /* Turn off backtrack as this optional operand is present. */
7317 if (val
!= PARSE_FAIL
7318 && operands
[i
] == AARCH64_OPND_BARRIER
)
7320 /* Regular barriers accept options CRm (C0-C15).
7321 DSB nXS barrier variant accepts values > 15. */
7322 if (val
< 0 || val
> 15)
7324 set_syntax_error (_("the specified option is not accepted in DSB"));
7328 /* This is an extension to accept a 0..15 immediate. */
7329 if (val
== PARSE_FAIL
)
7330 po_imm_or_fail (0, 15);
7331 info
->barrier
= aarch64_barrier_options
+ val
;
7334 case AARCH64_OPND_BARRIER_DSB_NXS
:
7335 val
= parse_barrier (&str
);
7336 if (val
!= PARSE_FAIL
)
7338 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7339 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7341 set_syntax_error (_("the specified option is not accepted in DSB"));
7342 /* Turn off backtrack as this optional operand is present. */
7349 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7350 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7351 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7353 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7355 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7359 /* Option index is encoded as 2-bit value in val<3:2>. */
7360 val
= (val
>> 2) - 4;
7361 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7364 case AARCH64_OPND_PRFOP
:
7365 val
= parse_pldop (&str
);
7366 /* This is an extension to accept a 0..31 immediate. */
7367 if (val
== PARSE_FAIL
)
7368 po_imm_or_fail (0, 31);
7369 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7372 case AARCH64_OPND_BARRIER_PSB
:
7373 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7374 if (val
== PARSE_FAIL
)
7378 case AARCH64_OPND_BTI_TARGET
:
7379 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7380 if (val
== PARSE_FAIL
)
7384 case AARCH64_OPND_SME_ZAda_2b
:
7385 case AARCH64_OPND_SME_ZAda_3b
:
7386 val
= parse_sme_zada_operand (&str
, &qualifier
);
7387 if (val
== PARSE_FAIL
)
7389 info
->reg
.regno
= val
;
7390 info
->qualifier
= qualifier
;
7393 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7394 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7395 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7397 enum sme_hv_slice slice_indicator
;
7398 int vector_select_register
;
7401 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7402 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7404 &vector_select_register
,
7408 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7409 &vector_select_register
,
7412 if (val
== PARSE_FAIL
)
7414 info
->za_tile_vector
.regno
= val
;
7415 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7416 info
->za_tile_vector
.index
.imm
= imm
;
7417 info
->za_tile_vector
.v
= slice_indicator
;
7418 info
->qualifier
= qualifier
;
7422 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7423 val
= parse_sme_list_of_64bit_tiles (&str
);
7424 if (val
== PARSE_FAIL
)
7426 info
->imm
.value
= val
;
7429 case AARCH64_OPND_SME_ZA_array
:
7432 val
= parse_sme_za_array (&str
, &imm
);
7433 if (val
== PARSE_FAIL
)
7435 info
->za_tile_vector
.index
.regno
= val
;
7436 info
->za_tile_vector
.index
.imm
= imm
;
7441 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7444 /* If we get here, this operand was successfully parsed. */
7445 inst
.base
.operands
[i
].present
= 1;
7449 /* The parse routine should already have set the error, but in case
7450 not, set a default one here. */
7452 set_default_error ();
7454 if (! backtrack_pos
)
7455 goto parse_operands_return
;
7458 /* We reach here because this operand is marked as optional, and
7459 either no operand was supplied or the operand was supplied but it
7460 was syntactically incorrect. In the latter case we report an
7461 error. In the former case we perform a few more checks before
7462 dropping through to the code to insert the default operand. */
7464 char *tmp
= backtrack_pos
;
7465 char endchar
= END_OF_INSN
;
7467 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7469 skip_past_char (&tmp
, ',');
7471 if (*tmp
!= endchar
)
7472 /* The user has supplied an operand in the wrong format. */
7473 goto parse_operands_return
;
7475 /* Make sure there is not a comma before the optional operand.
7476 For example the fifth operand of 'sys' is optional:
7478 sys #0,c0,c0,#0, <--- wrong
7479 sys #0,c0,c0,#0 <--- correct. */
7480 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7482 set_fatal_syntax_error
7483 (_("unexpected comma before the omitted optional operand"));
7484 goto parse_operands_return
;
7488 /* Reaching here means we are dealing with an optional operand that is
7489 omitted from the assembly line. */
7490 gas_assert (optional_operand_p (opcode
, i
));
7492 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7494 /* Try again, skipping the optional operand at backtrack_pos. */
7495 str
= backtrack_pos
;
7498 /* Clear any error record after the omitted optional operand has been
7499 successfully handled. */
7503 /* Check if we have parsed all the operands. */
7504 if (*str
!= '\0' && ! error_p ())
7506 /* Set I to the index of the last present operand; this is
7507 for the purpose of diagnostics. */
7508 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7510 set_fatal_syntax_error
7511 (_("unexpected characters following instruction"));
7514 parse_operands_return
:
7518 DEBUG_TRACE ("parsing FAIL: %s - %s",
7519 operand_mismatch_kind_names
[get_error_kind ()],
7520 get_error_message ());
7521 /* Record the operand error properly; this is useful when there
7522 are multiple instruction templates for a mnemonic name, so that
7523 later on, we can select the error that most closely describes
7525 record_operand_error (opcode
, i
, get_error_kind (),
7526 get_error_message ());
7531 DEBUG_TRACE ("parsing SUCCESS");
7536 /* It does some fix-up to provide some programmer friendly feature while
7537 keeping the libopcodes happy, i.e. libopcodes only accepts
7538 the preferred architectural syntax.
7539 Return FALSE if there is any failure; otherwise return TRUE. */
7542 programmer_friendly_fixup (aarch64_instruction
*instr
)
7544 aarch64_inst
*base
= &instr
->base
;
7545 const aarch64_opcode
*opcode
= base
->opcode
;
7546 enum aarch64_op op
= opcode
->op
;
7547 aarch64_opnd_info
*operands
= base
->operands
;
7549 DEBUG_TRACE ("enter");
7551 switch (opcode
->iclass
)
7554 /* TBNZ Xn|Wn, #uimm6, label
7555 Test and Branch Not Zero: conditionally jumps to label if bit number
7556 uimm6 in register Xn is not zero. The bit number implies the width of
7557 the register, which may be written and should be disassembled as Wn if
7558 uimm is less than 32. */
7559 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7561 if (operands
[1].imm
.value
>= 32)
7563 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7567 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7571 /* LDR Wt, label | =value
7572 As a convenience assemblers will typically permit the notation
7573 "=value" in conjunction with the pc-relative literal load instructions
7574 to automatically place an immediate value or symbolic address in a
7575 nearby literal pool and generate a hidden label which references it.
7576 ISREG has been set to 0 in the case of =value. */
7577 if (instr
->gen_lit_pool
7578 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7580 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7581 if (op
== OP_LDRSW_LIT
)
7583 if (instr
->reloc
.exp
.X_op
!= O_constant
7584 && instr
->reloc
.exp
.X_op
!= O_big
7585 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7587 record_operand_error (opcode
, 1,
7588 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7589 _("constant expression expected"));
7592 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7594 record_operand_error (opcode
, 1,
7595 AARCH64_OPDE_OTHER_ERROR
,
7596 _("literal pool insertion failed"));
7604 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7605 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7606 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7607 A programmer-friendly assembler should accept a destination Xd in
7608 place of Wd, however that is not the preferred form for disassembly.
7610 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7611 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7612 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7613 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7618 /* In the 64-bit form, the final register operand is written as Wm
7619 for all but the (possibly omitted) UXTX/LSL and SXTX
7621 As a programmer-friendly assembler, we accept e.g.
7622 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7623 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7624 int idx
= aarch64_operand_index (opcode
->operands
,
7625 AARCH64_OPND_Rm_EXT
);
7626 gas_assert (idx
== 1 || idx
== 2);
7627 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7628 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7629 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7630 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7631 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7632 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7640 DEBUG_TRACE ("exit with SUCCESS");
7644 /* Check for loads and stores that will cause unpredictable behavior. */
7647 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7649 aarch64_inst
*base
= &instr
->base
;
7650 const aarch64_opcode
*opcode
= base
->opcode
;
7651 const aarch64_opnd_info
*opnds
= base
->operands
;
7652 switch (opcode
->iclass
)
7659 /* Loading/storing the base register is unpredictable if writeback. */
7660 if ((aarch64_get_operand_class (opnds
[0].type
)
7661 == AARCH64_OPND_CLASS_INT_REG
)
7662 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7663 && opnds
[1].addr
.base_regno
!= REG_SP
7664 /* Exempt STG/STZG/ST2G/STZ2G. */
7665 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7666 && opnds
[1].addr
.writeback
)
7667 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7671 case ldstnapair_offs
:
7672 case ldstpair_indexed
:
7673 /* Loading/storing the base register is unpredictable if writeback. */
7674 if ((aarch64_get_operand_class (opnds
[0].type
)
7675 == AARCH64_OPND_CLASS_INT_REG
)
7676 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7677 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7678 && opnds
[2].addr
.base_regno
!= REG_SP
7680 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7681 && opnds
[2].addr
.writeback
)
7682 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7683 /* Load operations must load different registers. */
7684 if ((opcode
->opcode
& (1 << 22))
7685 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7686 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7690 if ((aarch64_get_operand_class (opnds
[0].type
)
7691 == AARCH64_OPND_CLASS_INT_REG
)
7692 && (aarch64_get_operand_class (opnds
[1].type
)
7693 == AARCH64_OPND_CLASS_INT_REG
))
7695 if ((opcode
->opcode
& (1 << 22)))
7697 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7698 if ((opcode
->opcode
& (1 << 21))
7699 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7700 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7704 /* Store-Exclusive is unpredictable if Rt == Rs. */
7705 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7707 (_("unpredictable: identical transfer and status registers"
7710 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7712 if (!(opcode
->opcode
& (1 << 21)))
7713 /* Store-Exclusive is unpredictable if Rn == Rs. */
7715 (_("unpredictable: identical base and status registers"
7718 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7720 (_("unpredictable: "
7721 "identical transfer and status registers"
7725 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7726 if ((opcode
->opcode
& (1 << 21))
7727 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7728 && opnds
[3].reg
.regno
!= REG_SP
)
7729 as_warn (_("unpredictable: identical base and status registers"
7741 force_automatic_sequence_close (void)
7743 if (now_instr_sequence
.instr
)
7745 as_warn (_("previous `%s' sequence has not been closed"),
7746 now_instr_sequence
.instr
->opcode
->name
);
7747 init_insn_sequence (NULL
, &now_instr_sequence
);
7751 /* A wrapper function to interface with libopcodes on encoding and
7752 record the error message if there is any.
7754 Return TRUE on success; otherwise return FALSE. */
7757 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7760 aarch64_operand_error error_info
;
7761 memset (&error_info
, '\0', sizeof (error_info
));
7762 error_info
.kind
= AARCH64_OPDE_NIL
;
7763 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7764 && !error_info
.non_fatal
)
7767 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7768 record_operand_error_info (opcode
, &error_info
);
7769 return error_info
.non_fatal
;
7772 #ifdef DEBUG_AARCH64
7774 dump_opcode_operands (const aarch64_opcode
*opcode
)
7777 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7779 aarch64_verbose ("\t\t opnd%d: %s", i
,
7780 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7781 ? aarch64_get_operand_name (opcode
->operands
[i
])
7782 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7786 #endif /* DEBUG_AARCH64 */
7788 /* This is the guts of the machine-dependent assembler. STR points to a
7789 machine dependent instruction. This function is supposed to emit
7790 the frags/bytes it assembles to. */
7793 md_assemble (char *str
)
7796 templates
*template;
7797 const aarch64_opcode
*opcode
;
7798 aarch64_inst
*inst_base
;
7799 unsigned saved_cond
;
7801 /* Align the previous label if needed. */
7802 if (last_label_seen
!= NULL
)
7804 symbol_set_frag (last_label_seen
, frag_now
);
7805 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7806 S_SET_SEGMENT (last_label_seen
, now_seg
);
7809 /* Update the current insn_sequence from the segment. */
7810 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7812 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7814 DEBUG_TRACE ("\n\n");
7815 DEBUG_TRACE ("==============================");
7816 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7818 template = opcode_lookup (&p
);
7821 /* It wasn't an instruction, but it might be a register alias of
7822 the form alias .req reg directive. */
7823 if (!create_register_alias (str
, p
))
7824 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7829 skip_whitespace (p
);
7832 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7833 get_mnemonic_name (str
), str
);
7837 init_operand_error_report ();
7839 /* Sections are assumed to start aligned. In executable section, there is no
7840 MAP_DATA symbol pending. So we only align the address during
7841 MAP_DATA --> MAP_INSN transition.
7842 For other sections, this is not guaranteed. */
7843 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7844 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7845 frag_align_code (2, 0);
7847 saved_cond
= inst
.cond
;
7848 reset_aarch64_instruction (&inst
);
7849 inst
.cond
= saved_cond
;
7851 /* Iterate through all opcode entries with the same mnemonic name. */
7854 opcode
= template->opcode
;
7856 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7857 #ifdef DEBUG_AARCH64
7859 dump_opcode_operands (opcode
);
7860 #endif /* DEBUG_AARCH64 */
7862 mapping_state (MAP_INSN
);
7864 inst_base
= &inst
.base
;
7865 inst_base
->opcode
= opcode
;
7867 /* Truly conditionally executed instructions, e.g. b.cond. */
7868 if (opcode
->flags
& F_COND
)
7870 gas_assert (inst
.cond
!= COND_ALWAYS
);
7871 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7872 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7874 else if (inst
.cond
!= COND_ALWAYS
)
7876 /* It shouldn't arrive here, where the assembly looks like a
7877 conditional instruction but the found opcode is unconditional. */
7882 if (parse_operands (p
, opcode
)
7883 && programmer_friendly_fixup (&inst
)
7884 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7886 /* Check that this instruction is supported for this CPU. */
7887 if (!opcode
->avariant
7888 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7890 as_bad (_("selected processor does not support `%s'"), str
);
7894 warn_unpredictable_ldst (&inst
, str
);
7896 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7897 || !inst
.reloc
.need_libopcodes_p
)
7901 /* If there is relocation generated for the instruction,
7902 store the instruction information for the future fix-up. */
7903 struct aarch64_inst
*copy
;
7904 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7905 copy
= XNEW (struct aarch64_inst
);
7906 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7910 /* Issue non-fatal messages if any. */
7911 output_operand_error_report (str
, true);
7915 template = template->next
;
7916 if (template != NULL
)
7918 reset_aarch64_instruction (&inst
);
7919 inst
.cond
= saved_cond
;
7922 while (template != NULL
);
7924 /* Issue the error messages if any. */
7925 output_operand_error_report (str
, false);
7928 /* Various frobbings of labels and their addresses. */
7931 aarch64_start_line_hook (void)
7933 last_label_seen
= NULL
;
7937 aarch64_frob_label (symbolS
* sym
)
7939 last_label_seen
= sym
;
7941 dwarf2_emit_label (sym
);
7945 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7947 /* Check to see if we have a block to close. */
7948 force_automatic_sequence_close ();
7952 aarch64_data_in_code (void)
7954 if (startswith (input_line_pointer
+ 1, "data:"))
7956 *input_line_pointer
= '/';
7957 input_line_pointer
+= 5;
7958 *input_line_pointer
= 0;
7966 aarch64_canonicalize_symbol_name (char *name
)
7970 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7971 *(name
+ len
- 5) = 0;
7976 /* Table of all register names defined by default. The user can
7977 define additional names with .req. Note that all register names
7978 should appear in both upper and lowercase variants. Some registers
7979 also have mixed-case names. */
7981 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
7982 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
7983 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7984 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
7985 #define REGSET16(p,t) \
7986 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7987 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7988 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7989 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7990 #define REGSET16S(p,s,t) \
7991 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
7992 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
7993 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
7994 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
7995 #define REGSET31(p,t) \
7997 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7998 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7999 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8000 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8001 #define REGSET(p,t) \
8002 REGSET31(p,t), REGNUM(p,31,t)
8004 /* These go into aarch64_reg_hsh hash-table. */
8005 static const reg_entry reg_names
[] = {
8006 /* Integer registers. */
8007 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8008 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8010 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8011 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8012 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8013 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8014 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8015 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8017 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8018 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8020 /* Floating-point single precision registers. */
8021 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8023 /* Floating-point double precision registers. */
8024 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8026 /* Floating-point half precision registers. */
8027 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8029 /* Floating-point byte precision registers. */
8030 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8032 /* Floating-point quad precision registers. */
8033 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8035 /* FP/SIMD registers. */
8036 REGSET (v
, VN
), REGSET (V
, VN
),
8038 /* SVE vector registers. */
8039 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8041 /* SVE predicate registers. */
8042 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8044 /* SME ZA tile registers. */
8045 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8047 /* SME ZA tile registers (horizontal slice). */
8048 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8050 /* SME ZA tile registers (vertical slice). */
8051 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8069 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8070 static const asm_nzcv nzcv_names
[] = {
8071 {"nzcv", B (n
, z
, c
, v
)},
8072 {"nzcV", B (n
, z
, c
, V
)},
8073 {"nzCv", B (n
, z
, C
, v
)},
8074 {"nzCV", B (n
, z
, C
, V
)},
8075 {"nZcv", B (n
, Z
, c
, v
)},
8076 {"nZcV", B (n
, Z
, c
, V
)},
8077 {"nZCv", B (n
, Z
, C
, v
)},
8078 {"nZCV", B (n
, Z
, C
, V
)},
8079 {"Nzcv", B (N
, z
, c
, v
)},
8080 {"NzcV", B (N
, z
, c
, V
)},
8081 {"NzCv", B (N
, z
, C
, v
)},
8082 {"NzCV", B (N
, z
, C
, V
)},
8083 {"NZcv", B (N
, Z
, c
, v
)},
8084 {"NZcV", B (N
, Z
, c
, V
)},
8085 {"NZCv", B (N
, Z
, C
, v
)},
8086 {"NZCV", B (N
, Z
, C
, V
)}
8099 /* MD interface: bits in the object file. */
8101 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8102 for use in the a.out file, and stores them in the array pointed to by buf.
8103 This knows about the endian-ness of the target machine and does
8104 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8105 2 (short) and 4 (long) Floating numbers are put out as a series of
8106 LITTLENUMS (shorts, here at least). */
8109 md_number_to_chars (char *buf
, valueT val
, int n
)
8111 if (target_big_endian
)
8112 number_to_chars_bigendian (buf
, val
, n
);
8114 number_to_chars_littleendian (buf
, val
, n
);
8117 /* MD interface: Sections. */
8119 /* Estimate the size of a frag before relaxing. Assume everything fits in
8123 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8129 /* Round up a section size to the appropriate boundary. */
8132 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8137 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8138 of an rs_align_code fragment.
8140 Here we fill the frag with the appropriate info for padding the
8141 output stream. The resulting frag will consist of a fixed (fr_fix)
8142 and of a repeating (fr_var) part.
8144 The fixed content is always emitted before the repeating content and
8145 these two parts are used as follows in constructing the output:
8146 - the fixed part will be used to align to a valid instruction word
8147 boundary, in case that we start at a misaligned address; as no
8148 executable instruction can live at the misaligned location, we
8149 simply fill with zeros;
8150 - the variable part will be used to cover the remaining padding and
8151 we fill using the AArch64 NOP instruction.
8153 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8154 enough storage space for up to 3 bytes for padding the back to a valid
8155 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8158 aarch64_handle_align (fragS
* fragP
)
8160 /* NOP = d503201f */
8161 /* AArch64 instructions are always little-endian. */
8162 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8164 int bytes
, fix
, noop_size
;
8167 if (fragP
->fr_type
!= rs_align_code
)
8170 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8171 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8174 gas_assert (fragP
->tc_frag_data
.recorded
);
8177 noop_size
= sizeof (aarch64_noop
);
8179 fix
= bytes
& (noop_size
- 1);
8183 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8187 fragP
->fr_fix
+= fix
;
8191 memcpy (p
, aarch64_noop
, noop_size
);
8192 fragP
->fr_var
= noop_size
;
8195 /* Perform target specific initialisation of a frag.
8196 Note - despite the name this initialisation is not done when the frag
8197 is created, but only when its type is assigned. A frag can be created
8198 and used a long time before its type is set, so beware of assuming that
8199 this initialisation is performed first. */
8203 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8204 int max_chars ATTRIBUTE_UNUSED
)
8208 #else /* OBJ_ELF is defined. */
8210 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8212 /* Record a mapping symbol for alignment frags. We will delete this
8213 later if the alignment ends up empty. */
8214 if (!fragP
->tc_frag_data
.recorded
)
8215 fragP
->tc_frag_data
.recorded
= 1;
8217 /* PR 21809: Do not set a mapping state for debug sections
8218 - it just confuses other tools. */
8219 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8222 switch (fragP
->fr_type
)
8226 mapping_state_2 (MAP_DATA
, max_chars
);
8229 /* PR 20364: We can get alignment frags in code sections,
8230 so do not just assume that we should use the MAP_DATA state. */
8231 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8234 mapping_state_2 (MAP_INSN
, max_chars
);
8241 /* Initialize the DWARF-2 unwind information for this procedure. */
8244 tc_aarch64_frame_initial_instructions (void)
8246 cfi_add_CFA_def_cfa (REG_SP
, 0);
8248 #endif /* OBJ_ELF */
8250 /* Convert REGNAME to a DWARF-2 register number. */
8253 tc_aarch64_regname_to_dw2regnum (char *regname
)
8255 const reg_entry
*reg
= parse_reg (®name
);
8261 case REG_TYPE_SP_32
:
8262 case REG_TYPE_SP_64
:
8272 return reg
->number
+ 64;
8280 /* Implement DWARF2_ADDR_SIZE. */
8283 aarch64_dwarf2_addr_size (void)
8285 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8289 return bfd_arch_bits_per_address (stdoutput
) / 8;
8292 /* MD interface: Symbol and relocation handling. */
8294 /* Return the address within the segment that a PC-relative fixup is
8295 relative to. For AArch64 PC-relative fixups applied to instructions
8296 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8299 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8301 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8303 /* If this is pc-relative and we are going to emit a relocation
8304 then we just want to put out any pipeline compensation that the linker
8305 will need. Otherwise we want to use the calculated base. */
8307 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8308 || aarch64_force_relocation (fixP
)))
8311 /* AArch64 should be consistent for all pc-relative relocations. */
8312 return base
+ AARCH64_PCREL_OFFSET
;
8315 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8316 Otherwise we have no need to default values of symbols. */
8319 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8322 if (name
[0] == '_' && name
[1] == 'G'
8323 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8327 if (symbol_find (name
))
8328 as_bad (_("GOT already in the symbol table"));
8330 GOT_symbol
= symbol_new (name
, undefined_section
,
8331 &zero_address_frag
, 0);
8341 /* Return non-zero if the indicated VALUE has overflowed the maximum
8342 range expressible by a unsigned number with the indicated number of
8346 unsigned_overflow (valueT value
, unsigned bits
)
8349 if (bits
>= sizeof (valueT
) * 8)
8351 lim
= (valueT
) 1 << bits
;
8352 return (value
>= lim
);
8356 /* Return non-zero if the indicated VALUE has overflowed the maximum
8357 range expressible by an signed number with the indicated number of
8361 signed_overflow (offsetT value
, unsigned bits
)
8364 if (bits
>= sizeof (offsetT
) * 8)
8366 lim
= (offsetT
) 1 << (bits
- 1);
8367 return (value
< -lim
|| value
>= lim
);
8370 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8371 unsigned immediate offset load/store instruction, try to encode it as
8372 an unscaled, 9-bit, signed immediate offset load/store instruction.
8373 Return TRUE if it is successful; otherwise return FALSE.
8375 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8376 in response to the standard LDR/STR mnemonics when the immediate offset is
8377 unambiguous, i.e. when it is negative or unaligned. */
8380 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8383 enum aarch64_op new_op
;
8384 const aarch64_opcode
*new_opcode
;
8386 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8388 switch (instr
->opcode
->op
)
8390 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8391 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8392 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8393 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8394 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8395 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8396 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8397 case OP_STR_POS
: new_op
= OP_STUR
; break;
8398 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8399 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8400 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8401 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8402 default: new_op
= OP_NIL
; break;
8405 if (new_op
== OP_NIL
)
8408 new_opcode
= aarch64_get_opcode (new_op
);
8409 gas_assert (new_opcode
!= NULL
);
8411 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8412 instr
->opcode
->op
, new_opcode
->op
);
8414 aarch64_replace_opcode (instr
, new_opcode
);
8416 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8417 qualifier matching may fail because the out-of-date qualifier will
8418 prevent the operand being updated with a new and correct qualifier. */
8419 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8420 AARCH64_OPND_ADDR_SIMM9
);
8421 gas_assert (idx
== 1);
8422 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8424 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8426 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8433 /* Called by fix_insn to fix a MOV immediate alias instruction.
8435 Operand for a generic move immediate instruction, which is an alias
8436 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8437 a 32-bit/64-bit immediate value into general register. An assembler error
8438 shall result if the immediate cannot be created by a single one of these
8439 instructions. If there is a choice, then to ensure reversability an
8440 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8443 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8445 const aarch64_opcode
*opcode
;
8447 /* Need to check if the destination is SP/ZR. The check has to be done
8448 before any aarch64_replace_opcode. */
8449 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8450 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8452 instr
->operands
[1].imm
.value
= value
;
8453 instr
->operands
[1].skip
= 0;
8457 /* Try the MOVZ alias. */
8458 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8459 aarch64_replace_opcode (instr
, opcode
);
8460 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8461 &instr
->value
, NULL
, NULL
, insn_sequence
))
8463 put_aarch64_insn (buf
, instr
->value
);
8466 /* Try the MOVK alias. */
8467 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8468 aarch64_replace_opcode (instr
, opcode
);
8469 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8470 &instr
->value
, NULL
, NULL
, insn_sequence
))
8472 put_aarch64_insn (buf
, instr
->value
);
8477 if (try_mov_bitmask_p
)
8479 /* Try the ORR alias. */
8480 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8481 aarch64_replace_opcode (instr
, opcode
);
8482 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8483 &instr
->value
, NULL
, NULL
, insn_sequence
))
8485 put_aarch64_insn (buf
, instr
->value
);
8490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8491 _("immediate cannot be moved by a single instruction"));
8494 /* An instruction operand which is immediate related may have symbol used
8495 in the assembly, e.g.
8498 .set u32, 0x00ffff00
8500 At the time when the assembly instruction is parsed, a referenced symbol,
8501 like 'u32' in the above example may not have been seen; a fixS is created
8502 in such a case and is handled here after symbols have been resolved.
8503 Instruction is fixed up with VALUE using the information in *FIXP plus
8504 extra information in FLAGS.
8506 This function is called by md_apply_fix to fix up instructions that need
8507 a fix-up described above but does not involve any linker-time relocation. */
8510 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8514 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8515 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8516 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8520 /* Now the instruction is about to be fixed-up, so the operand that
8521 was previously marked as 'ignored' needs to be unmarked in order
8522 to get the encoding done properly. */
8523 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8524 new_inst
->operands
[idx
].skip
= 0;
8527 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8531 case AARCH64_OPND_EXCEPTION
:
8532 case AARCH64_OPND_UNDEFINED
:
8533 if (unsigned_overflow (value
, 16))
8534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8535 _("immediate out of range"));
8536 insn
= get_aarch64_insn (buf
);
8537 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8538 put_aarch64_insn (buf
, insn
);
8541 case AARCH64_OPND_AIMM
:
8542 /* ADD or SUB with immediate.
8543 NOTE this assumes we come here with a add/sub shifted reg encoding
8544 3 322|2222|2 2 2 21111 111111
8545 1 098|7654|3 2 1 09876 543210 98765 43210
8546 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8547 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8548 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8549 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8551 3 322|2222|2 2 221111111111
8552 1 098|7654|3 2 109876543210 98765 43210
8553 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8554 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8555 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8556 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8557 Fields sf Rn Rd are already set. */
8558 insn
= get_aarch64_insn (buf
);
8562 insn
= reencode_addsub_switch_add_sub (insn
);
8566 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8567 && unsigned_overflow (value
, 12))
8569 /* Try to shift the value by 12 to make it fit. */
8570 if (((value
>> 12) << 12) == value
8571 && ! unsigned_overflow (value
, 12 + 12))
8574 insn
|= encode_addsub_imm_shift_amount (1);
8578 if (unsigned_overflow (value
, 12))
8579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8580 _("immediate out of range"));
8582 insn
|= encode_addsub_imm (value
);
8584 put_aarch64_insn (buf
, insn
);
8587 case AARCH64_OPND_SIMD_IMM
:
8588 case AARCH64_OPND_SIMD_IMM_SFT
:
8589 case AARCH64_OPND_LIMM
:
8590 /* Bit mask immediate. */
8591 gas_assert (new_inst
!= NULL
);
8592 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8593 new_inst
->operands
[idx
].imm
.value
= value
;
8594 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8595 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8596 put_aarch64_insn (buf
, new_inst
->value
);
8598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8599 _("invalid immediate"));
8602 case AARCH64_OPND_HALF
:
8603 /* 16-bit unsigned immediate. */
8604 if (unsigned_overflow (value
, 16))
8605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8606 _("immediate out of range"));
8607 insn
= get_aarch64_insn (buf
);
8608 insn
|= encode_movw_imm (value
& 0xffff);
8609 put_aarch64_insn (buf
, insn
);
8612 case AARCH64_OPND_IMM_MOV
:
8613 /* Operand for a generic move immediate instruction, which is
8614 an alias instruction that generates a single MOVZ, MOVN or ORR
8615 instruction to loads a 32-bit/64-bit immediate value into general
8616 register. An assembler error shall result if the immediate cannot be
8617 created by a single one of these instructions. If there is a choice,
8618 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8619 and MOVZ or MOVN to ORR. */
8620 gas_assert (new_inst
!= NULL
);
8621 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8624 case AARCH64_OPND_ADDR_SIMM7
:
8625 case AARCH64_OPND_ADDR_SIMM9
:
8626 case AARCH64_OPND_ADDR_SIMM9_2
:
8627 case AARCH64_OPND_ADDR_SIMM10
:
8628 case AARCH64_OPND_ADDR_UIMM12
:
8629 case AARCH64_OPND_ADDR_SIMM11
:
8630 case AARCH64_OPND_ADDR_SIMM13
:
8631 /* Immediate offset in an address. */
8632 insn
= get_aarch64_insn (buf
);
8634 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8635 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8636 || new_inst
->opcode
->operands
[2] == opnd
);
8638 /* Get the index of the address operand. */
8639 if (new_inst
->opcode
->operands
[1] == opnd
)
8640 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8643 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8646 /* Update the resolved offset value. */
8647 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8649 /* Encode/fix-up. */
8650 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8651 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8653 put_aarch64_insn (buf
, new_inst
->value
);
8656 else if (new_inst
->opcode
->iclass
== ldst_pos
8657 && try_to_encode_as_unscaled_ldst (new_inst
))
8659 put_aarch64_insn (buf
, new_inst
->value
);
8663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8664 _("immediate offset out of range"));
8669 as_fatal (_("unhandled operand code %d"), opnd
);
8673 /* Apply a fixup (fixP) to segment data, once it has been determined
8674 by our caller that we have all the info we need to fix it up.
8676 Parameter valP is the pointer to the value of the bits. */
8679 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8681 offsetT value
= *valP
;
8683 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8685 unsigned flags
= fixP
->fx_addnumber
;
8687 DEBUG_TRACE ("\n\n");
8688 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8689 DEBUG_TRACE ("Enter md_apply_fix");
8691 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8693 /* Note whether this will delete the relocation. */
8695 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8698 /* Process the relocations. */
8699 switch (fixP
->fx_r_type
)
8701 case BFD_RELOC_NONE
:
8702 /* This will need to go in the object file. */
8707 case BFD_RELOC_8_PCREL
:
8708 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8709 md_number_to_chars (buf
, value
, 1);
8713 case BFD_RELOC_16_PCREL
:
8714 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8715 md_number_to_chars (buf
, value
, 2);
8719 case BFD_RELOC_32_PCREL
:
8720 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8721 md_number_to_chars (buf
, value
, 4);
8725 case BFD_RELOC_64_PCREL
:
8726 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8727 md_number_to_chars (buf
, value
, 8);
8730 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8731 /* We claim that these fixups have been processed here, even if
8732 in fact we generate an error because we do not have a reloc
8733 for them, so tc_gen_reloc() will reject them. */
8735 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8738 _("undefined symbol %s used as an immediate value"),
8739 S_GET_NAME (fixP
->fx_addsy
));
8740 goto apply_fix_return
;
8742 fix_insn (fixP
, flags
, value
);
8745 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8746 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8750 _("pc-relative load offset not word aligned"));
8751 if (signed_overflow (value
, 21))
8752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8753 _("pc-relative load offset out of range"));
8754 insn
= get_aarch64_insn (buf
);
8755 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8756 put_aarch64_insn (buf
, insn
);
8760 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8761 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8763 if (signed_overflow (value
, 21))
8764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8765 _("pc-relative address offset out of range"));
8766 insn
= get_aarch64_insn (buf
);
8767 insn
|= encode_adr_imm (value
);
8768 put_aarch64_insn (buf
, insn
);
8772 case BFD_RELOC_AARCH64_BRANCH19
:
8773 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8777 _("conditional branch target not word aligned"));
8778 if (signed_overflow (value
, 21))
8779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8780 _("conditional branch out of range"));
8781 insn
= get_aarch64_insn (buf
);
8782 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8783 put_aarch64_insn (buf
, insn
);
8787 case BFD_RELOC_AARCH64_TSTBR14
:
8788 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8792 _("conditional branch target not word aligned"));
8793 if (signed_overflow (value
, 16))
8794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8795 _("conditional branch out of range"));
8796 insn
= get_aarch64_insn (buf
);
8797 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8798 put_aarch64_insn (buf
, insn
);
8802 case BFD_RELOC_AARCH64_CALL26
:
8803 case BFD_RELOC_AARCH64_JUMP26
:
8804 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8808 _("branch target not word aligned"));
8809 if (signed_overflow (value
, 28))
8810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8811 _("branch out of range"));
8812 insn
= get_aarch64_insn (buf
);
8813 insn
|= encode_branch_ofs_26 (value
>> 2);
8814 put_aarch64_insn (buf
, insn
);
8818 case BFD_RELOC_AARCH64_MOVW_G0
:
8819 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8820 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8821 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8822 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8823 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8826 case BFD_RELOC_AARCH64_MOVW_G1
:
8827 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8828 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8829 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8830 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8831 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8834 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8836 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8837 /* Should always be exported to object file, see
8838 aarch64_force_relocation(). */
8839 gas_assert (!fixP
->fx_done
);
8840 gas_assert (seg
->use_rela_p
);
8842 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8844 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8845 /* Should always be exported to object file, see
8846 aarch64_force_relocation(). */
8847 gas_assert (!fixP
->fx_done
);
8848 gas_assert (seg
->use_rela_p
);
8850 case BFD_RELOC_AARCH64_MOVW_G2
:
8851 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8852 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8853 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8854 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8857 case BFD_RELOC_AARCH64_MOVW_G3
:
8858 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8861 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8863 insn
= get_aarch64_insn (buf
);
8867 /* REL signed addend must fit in 16 bits */
8868 if (signed_overflow (value
, 16))
8869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8870 _("offset out of range"));
8874 /* Check for overflow and scale. */
8875 switch (fixP
->fx_r_type
)
8877 case BFD_RELOC_AARCH64_MOVW_G0
:
8878 case BFD_RELOC_AARCH64_MOVW_G1
:
8879 case BFD_RELOC_AARCH64_MOVW_G2
:
8880 case BFD_RELOC_AARCH64_MOVW_G3
:
8881 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8882 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8883 if (unsigned_overflow (value
, scale
+ 16))
8884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8885 _("unsigned value out of range"));
8887 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8888 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8889 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8890 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8891 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8892 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8893 /* NOTE: We can only come here with movz or movn. */
8894 if (signed_overflow (value
, scale
+ 16))
8895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8896 _("signed value out of range"));
8899 /* Force use of MOVN. */
8901 insn
= reencode_movzn_to_movn (insn
);
8905 /* Force use of MOVZ. */
8906 insn
= reencode_movzn_to_movz (insn
);
8910 /* Unchecked relocations. */
8916 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8917 insn
|= encode_movw_imm (value
& 0xffff);
8919 put_aarch64_insn (buf
, insn
);
8923 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8924 fixP
->fx_r_type
= (ilp32_p
8925 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8926 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8927 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8928 /* Should always be exported to object file, see
8929 aarch64_force_relocation(). */
8930 gas_assert (!fixP
->fx_done
);
8931 gas_assert (seg
->use_rela_p
);
8934 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8935 fixP
->fx_r_type
= (ilp32_p
8936 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8937 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8938 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8939 /* Should always be exported to object file, see
8940 aarch64_force_relocation(). */
8941 gas_assert (!fixP
->fx_done
);
8942 gas_assert (seg
->use_rela_p
);
8945 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8946 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8947 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8948 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8949 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8950 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8951 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8952 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8953 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8954 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8955 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8956 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8957 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8958 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8959 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8960 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8961 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8962 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8963 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8964 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8965 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8966 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8967 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8968 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8969 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8970 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8971 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8972 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8973 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8974 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8975 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8976 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8977 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8978 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8979 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8980 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8981 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8982 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8983 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8984 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8985 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8986 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8987 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8988 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8989 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8990 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8991 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8992 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8993 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8994 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8995 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8996 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8997 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8998 /* Should always be exported to object file, see
8999 aarch64_force_relocation(). */
9000 gas_assert (!fixP
->fx_done
);
9001 gas_assert (seg
->use_rela_p
);
9004 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9005 /* Should always be exported to object file, see
9006 aarch64_force_relocation(). */
9007 fixP
->fx_r_type
= (ilp32_p
9008 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9009 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9010 gas_assert (!fixP
->fx_done
);
9011 gas_assert (seg
->use_rela_p
);
9014 case BFD_RELOC_AARCH64_ADD_LO12
:
9015 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9016 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9017 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9018 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9019 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9020 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9021 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9022 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9023 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9024 case BFD_RELOC_AARCH64_LDST128_LO12
:
9025 case BFD_RELOC_AARCH64_LDST16_LO12
:
9026 case BFD_RELOC_AARCH64_LDST32_LO12
:
9027 case BFD_RELOC_AARCH64_LDST64_LO12
:
9028 case BFD_RELOC_AARCH64_LDST8_LO12
:
9029 /* Should always be exported to object file, see
9030 aarch64_force_relocation(). */
9031 gas_assert (!fixP
->fx_done
);
9032 gas_assert (seg
->use_rela_p
);
9035 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9036 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9037 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9040 case BFD_RELOC_UNUSED
:
9041 /* An error will already have been reported. */
9045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9046 _("unexpected %s fixup"),
9047 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9052 /* Free the allocated the struct aarch64_inst.
9053 N.B. currently there are very limited number of fix-up types actually use
9054 this field, so the impact on the performance should be minimal . */
9055 free (fixP
->tc_fix_data
.inst
);
9060 /* Translate internal representation of relocation info to BFD target
9064 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9067 bfd_reloc_code_real_type code
;
9069 reloc
= XNEW (arelent
);
9071 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9072 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9073 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9077 if (section
->use_rela_p
)
9078 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9080 fixp
->fx_offset
= reloc
->address
;
9082 reloc
->addend
= fixp
->fx_offset
;
9084 code
= fixp
->fx_r_type
;
9089 code
= BFD_RELOC_16_PCREL
;
9094 code
= BFD_RELOC_32_PCREL
;
9099 code
= BFD_RELOC_64_PCREL
;
9106 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9107 if (reloc
->howto
== NULL
)
9109 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9111 ("cannot represent %s relocation in this object file format"),
9112 bfd_get_reloc_code_name (code
));
9119 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9122 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9124 bfd_reloc_code_real_type type
;
9128 FIXME: @@ Should look at CPU word size. */
9135 type
= BFD_RELOC_16
;
9138 type
= BFD_RELOC_32
;
9141 type
= BFD_RELOC_64
;
9144 as_bad (_("cannot do %u-byte relocation"), size
);
9145 type
= BFD_RELOC_UNUSED
;
9149 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9154 /* Implement md_after_parse_args. This is the earliest time we need to decide
9155 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9158 aarch64_after_parse_args (void)
9160 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9163 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9164 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9165 aarch64_abi
= AARCH64_ABI_ILP32
;
9167 aarch64_abi
= AARCH64_ABI_LP64
;
9171 elf64_aarch64_target_format (void)
9174 /* FIXME: What to do for ilp32_p ? */
9175 if (target_big_endian
)
9176 return "elf64-bigaarch64-cloudabi";
9178 return "elf64-littleaarch64-cloudabi";
9180 if (target_big_endian
)
9181 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9183 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9188 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9190 elf_frob_symbol (symp
, puntp
);
9194 /* MD interface: Finalization. */
9196 /* A good place to do this, although this was probably not intended
9197 for this kind of use. We need to dump the literal pool before
9198 references are made to a null symbol pointer. */
9201 aarch64_cleanup (void)
9205 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9207 /* Put it at the end of the relevant section. */
9208 subseg_set (pool
->section
, pool
->sub_section
);
9214 /* Remove any excess mapping symbols generated for alignment frags in
9215 SEC. We may have created a mapping symbol before a zero byte
9216 alignment; remove it if there's a mapping symbol after the
9219 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9220 void *dummy ATTRIBUTE_UNUSED
)
9222 segment_info_type
*seginfo
= seg_info (sec
);
9225 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9228 for (fragp
= seginfo
->frchainP
->frch_root
;
9229 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9231 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9232 fragS
*next
= fragp
->fr_next
;
9234 /* Variable-sized frags have been converted to fixed size by
9235 this point. But if this was variable-sized to start with,
9236 there will be a fixed-size frag after it. So don't handle
9238 if (sym
== NULL
|| next
== NULL
)
9241 if (S_GET_VALUE (sym
) < next
->fr_address
)
9242 /* Not at the end of this frag. */
9244 know (S_GET_VALUE (sym
) == next
->fr_address
);
9248 if (next
->tc_frag_data
.first_map
!= NULL
)
9250 /* Next frag starts with a mapping symbol. Discard this
9252 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9256 if (next
->fr_next
== NULL
)
9258 /* This mapping symbol is at the end of the section. Discard
9260 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9261 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9265 /* As long as we have empty frags without any mapping symbols,
9267 /* If the next frag is non-empty and does not start with a
9268 mapping symbol, then this mapping symbol is required. */
9269 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9272 next
= next
->fr_next
;
9274 while (next
!= NULL
);
9279 /* Adjust the symbol table. */
9282 aarch64_adjust_symtab (void)
9285 /* Remove any overlapping mapping symbols generated by alignment frags. */
9286 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9287 /* Now do generic ELF adjustments. */
9288 elf_adjust_symtab ();
9293 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9295 str_hash_insert (table
, key
, value
, 0);
9299 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9301 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9302 checked_hash_insert (table
, key
, value
);
9306 fill_instruction_hash_table (void)
9308 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9310 while (opcode
->name
!= NULL
)
9312 templates
*templ
, *new_templ
;
9313 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9315 new_templ
= XNEW (templates
);
9316 new_templ
->opcode
= opcode
;
9317 new_templ
->next
= NULL
;
9320 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9323 new_templ
->next
= templ
->next
;
9324 templ
->next
= new_templ
;
9331 convert_to_upper (char *dst
, const char *src
, size_t num
)
9334 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9335 *dst
= TOUPPER (*src
);
9339 /* Assume STR point to a lower-case string, allocate, convert and return
9340 the corresponding upper-case string. */
9341 static inline const char*
9342 get_upper_str (const char *str
)
9345 size_t len
= strlen (str
);
9346 ret
= XNEWVEC (char, len
+ 1);
9347 convert_to_upper (ret
, str
, len
);
9351 /* MD interface: Initialization. */
9359 aarch64_ops_hsh
= str_htab_create ();
9360 aarch64_cond_hsh
= str_htab_create ();
9361 aarch64_shift_hsh
= str_htab_create ();
9362 aarch64_sys_regs_hsh
= str_htab_create ();
9363 aarch64_pstatefield_hsh
= str_htab_create ();
9364 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9365 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9366 aarch64_sys_regs_at_hsh
= str_htab_create ();
9367 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9368 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9369 aarch64_reg_hsh
= str_htab_create ();
9370 aarch64_barrier_opt_hsh
= str_htab_create ();
9371 aarch64_nzcv_hsh
= str_htab_create ();
9372 aarch64_pldop_hsh
= str_htab_create ();
9373 aarch64_hint_opt_hsh
= str_htab_create ();
9375 fill_instruction_hash_table ();
9377 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9378 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9379 (void *) (aarch64_sys_regs
+ i
));
9381 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9382 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9383 aarch64_pstatefields
[i
].name
,
9384 (void *) (aarch64_pstatefields
+ i
));
9386 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9387 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9388 aarch64_sys_regs_ic
[i
].name
,
9389 (void *) (aarch64_sys_regs_ic
+ i
));
9391 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9392 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9393 aarch64_sys_regs_dc
[i
].name
,
9394 (void *) (aarch64_sys_regs_dc
+ i
));
9396 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9397 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9398 aarch64_sys_regs_at
[i
].name
,
9399 (void *) (aarch64_sys_regs_at
+ i
));
9401 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9402 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9403 aarch64_sys_regs_tlbi
[i
].name
,
9404 (void *) (aarch64_sys_regs_tlbi
+ i
));
9406 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9407 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9408 aarch64_sys_regs_sr
[i
].name
,
9409 (void *) (aarch64_sys_regs_sr
+ i
));
9411 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9412 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9413 (void *) (reg_names
+ i
));
9415 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9416 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9417 (void *) (nzcv_names
+ i
));
9419 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9421 const char *name
= aarch64_operand_modifiers
[i
].name
;
9422 checked_hash_insert (aarch64_shift_hsh
, name
,
9423 (void *) (aarch64_operand_modifiers
+ i
));
9424 /* Also hash the name in the upper case. */
9425 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9426 (void *) (aarch64_operand_modifiers
+ i
));
9429 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9432 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9433 the same condition code. */
9434 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9436 const char *name
= aarch64_conds
[i
].names
[j
];
9439 checked_hash_insert (aarch64_cond_hsh
, name
,
9440 (void *) (aarch64_conds
+ i
));
9441 /* Also hash the name in the upper case. */
9442 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9443 (void *) (aarch64_conds
+ i
));
9447 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9449 const char *name
= aarch64_barrier_options
[i
].name
;
9450 /* Skip xx00 - the unallocated values of option. */
9453 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9454 (void *) (aarch64_barrier_options
+ i
));
9455 /* Also hash the name in the upper case. */
9456 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9457 (void *) (aarch64_barrier_options
+ i
));
9460 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9462 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9463 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9464 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9465 /* Also hash the name in the upper case. */
9466 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9467 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9470 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9472 const char* name
= aarch64_prfops
[i
].name
;
9473 /* Skip the unallocated hint encodings. */
9476 checked_hash_insert (aarch64_pldop_hsh
, name
,
9477 (void *) (aarch64_prfops
+ i
));
9478 /* Also hash the name in the upper case. */
9479 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9480 (void *) (aarch64_prfops
+ i
));
9483 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9485 const char* name
= aarch64_hint_options
[i
].name
;
9486 const char* upper_name
= get_upper_str(name
);
9488 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9489 (void *) (aarch64_hint_options
+ i
));
9491 /* Also hash the name in the upper case if not the same. */
9492 if (strcmp (name
, upper_name
) != 0)
9493 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9494 (void *) (aarch64_hint_options
+ i
));
9497 /* Set the cpu variant based on the command-line options. */
9499 mcpu_cpu_opt
= march_cpu_opt
;
9502 mcpu_cpu_opt
= &cpu_default
;
9504 cpu_variant
= *mcpu_cpu_opt
;
9506 /* Record the CPU type. */
9507 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9509 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9512 /* Command line processing. */
9514 const char *md_shortopts
= "m:";
9516 #ifdef AARCH64_BI_ENDIAN
9517 #define OPTION_EB (OPTION_MD_BASE + 0)
9518 #define OPTION_EL (OPTION_MD_BASE + 1)
9520 #if TARGET_BYTES_BIG_ENDIAN
9521 #define OPTION_EB (OPTION_MD_BASE + 0)
9523 #define OPTION_EL (OPTION_MD_BASE + 1)
9527 struct option md_longopts
[] = {
9529 {"EB", no_argument
, NULL
, OPTION_EB
},
9532 {"EL", no_argument
, NULL
, OPTION_EL
},
9534 {NULL
, no_argument
, NULL
, 0}
9537 size_t md_longopts_size
= sizeof (md_longopts
);
9539 struct aarch64_option_table
9541 const char *option
; /* Option name to match. */
9542 const char *help
; /* Help information. */
9543 int *var
; /* Variable to change. */
9544 int value
; /* What to change it to. */
9545 char *deprecated
; /* If non-null, print this message. */
9548 static struct aarch64_option_table aarch64_opts
[] = {
9549 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9550 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9552 #ifdef DEBUG_AARCH64
9553 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9554 #endif /* DEBUG_AARCH64 */
9555 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9557 {"mno-verbose-error", N_("do not output verbose error messages"),
9558 &verbose_error_p
, 0, NULL
},
9559 {NULL
, NULL
, NULL
, 0, NULL
}
9562 struct aarch64_cpu_option_table
9565 const aarch64_feature_set value
;
9566 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9568 const char *canonical_name
;
9571 /* This list should, at a minimum, contain all the cpu names
9572 recognized by GCC. */
9573 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9574 {"all", AARCH64_ANY
, NULL
},
9575 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9576 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9577 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9578 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9579 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9580 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9581 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9582 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9583 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9584 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9585 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9586 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9587 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9588 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9590 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9591 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9593 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9594 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9596 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9597 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9598 | AARCH64_FEATURE_DOTPROD
9599 | AARCH64_FEATURE_SSBS
),
9601 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9602 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9603 | AARCH64_FEATURE_DOTPROD
9604 | AARCH64_FEATURE_SSBS
),
9606 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9607 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9608 | AARCH64_FEATURE_DOTPROD
9609 | AARCH64_FEATURE_SSBS
),
9611 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9612 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9613 | AARCH64_FEATURE_DOTPROD
9614 | AARCH64_FEATURE_SSBS
),
9616 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9618 | AARCH64_FEATURE_RCPC
9619 | AARCH64_FEATURE_DOTPROD
9620 | AARCH64_FEATURE_SSBS
9621 | AARCH64_FEATURE_PROFILE
),
9623 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9625 | AARCH64_FEATURE_RCPC
9626 | AARCH64_FEATURE_DOTPROD
9627 | AARCH64_FEATURE_SSBS
9628 | AARCH64_FEATURE_PROFILE
),
9630 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9631 AARCH64_FEATURE_DOTPROD
9632 | AARCH64_FEATURE_F16
9633 | AARCH64_FEATURE_FLAGM
9634 | AARCH64_FEATURE_PAC
9635 | AARCH64_FEATURE_PROFILE
9636 | AARCH64_FEATURE_RCPC
9637 | AARCH64_FEATURE_SSBS
),
9639 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9640 AARCH64_FEATURE_BFLOAT16
9641 | AARCH64_FEATURE_I8MM
9642 | AARCH64_FEATURE_MEMTAG
9643 | AARCH64_FEATURE_SVE2_BITPERM
),
9645 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9646 AARCH64_FEATURE_BFLOAT16
9647 | AARCH64_FEATURE_I8MM
9648 | AARCH64_FEATURE_MEMTAG
9649 | AARCH64_FEATURE_SVE2_BITPERM
),
9651 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9652 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9653 | AARCH64_FEATURE_DOTPROD
9654 | AARCH64_FEATURE_PROFILE
),
9656 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9657 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9658 "Samsung Exynos M1"},
9659 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9660 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9661 | AARCH64_FEATURE_RDMA
),
9663 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9664 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9665 | AARCH64_FEATURE_DOTPROD
9666 | AARCH64_FEATURE_SSBS
),
9668 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9669 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9670 | AARCH64_FEATURE_DOTPROD
9671 | AARCH64_FEATURE_PROFILE
),
9673 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9674 AARCH64_FEATURE_BFLOAT16
9675 | AARCH64_FEATURE_I8MM
9676 | AARCH64_FEATURE_F16
9677 | AARCH64_FEATURE_SVE
9678 | AARCH64_FEATURE_SVE2
9679 | AARCH64_FEATURE_SVE2_BITPERM
9680 | AARCH64_FEATURE_MEMTAG
9681 | AARCH64_FEATURE_RNG
),
9683 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9684 AARCH64_FEATURE_PROFILE
9685 | AARCH64_FEATURE_CVADP
9686 | AARCH64_FEATURE_SVE
9687 | AARCH64_FEATURE_SSBS
9688 | AARCH64_FEATURE_RNG
9689 | AARCH64_FEATURE_F16
9690 | AARCH64_FEATURE_BFLOAT16
9691 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9692 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9693 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9694 | AARCH64_FEATURE_RDMA
),
9695 "Qualcomm QDF24XX"},
9696 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9697 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9698 "Qualcomm Saphira"},
9699 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9700 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9702 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9703 AARCH64_FEATURE_CRYPTO
),
9705 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9706 in earlier releases and is superseded by 'xgene1' in all
9708 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9709 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9710 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9711 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9712 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9713 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9715 | AARCH64_FEATURE_RCPC
9716 | AARCH64_FEATURE_DOTPROD
9717 | AARCH64_FEATURE_SSBS
9718 | AARCH64_FEATURE_PROFILE
),
9720 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9721 AARCH64_FEATURE_BFLOAT16
9722 | AARCH64_FEATURE_I8MM
9723 | AARCH64_FEATURE_MEMTAG
9724 | AARCH64_FEATURE_SVE2_BITPERM
),
9726 {"generic", AARCH64_ARCH_V8
, NULL
},
9728 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9731 struct aarch64_arch_option_table
9734 const aarch64_feature_set value
;
9737 /* This list should, at a minimum, contain all the architecture names
9738 recognized by GCC. */
9739 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9740 {"all", AARCH64_ANY
},
9741 {"armv8-a", AARCH64_ARCH_V8
},
9742 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9743 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9744 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9745 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9746 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9747 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9748 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9749 {"armv8-r", AARCH64_ARCH_V8_R
},
9750 {"armv9-a", AARCH64_ARCH_V9
},
9751 {NULL
, AARCH64_ARCH_NONE
}
9754 /* ISA extensions. */
9755 struct aarch64_option_cpu_value_table
9758 const aarch64_feature_set value
;
9759 const aarch64_feature_set require
; /* Feature dependencies. */
9762 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9763 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9765 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9766 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9767 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9769 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9771 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9772 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9773 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9775 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9777 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9779 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9780 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9781 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9782 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9783 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9784 AARCH64_FEATURE (AARCH64_FEATURE_FP
9785 | AARCH64_FEATURE_F16
, 0)},
9786 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9788 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9789 AARCH64_FEATURE (AARCH64_FEATURE_F16
9790 | AARCH64_FEATURE_SIMD
9791 | AARCH64_FEATURE_COMPNUM
, 0)},
9792 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9794 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9795 AARCH64_FEATURE (AARCH64_FEATURE_F16
9796 | AARCH64_FEATURE_SIMD
, 0)},
9797 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9799 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9801 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9803 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9805 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9807 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9809 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9811 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9812 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9813 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9815 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9817 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9819 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9820 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9821 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9822 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9823 | AARCH64_FEATURE_SM4
, 0)},
9824 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9825 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9826 | AARCH64_FEATURE_AES
, 0)},
9827 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9828 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9829 | AARCH64_FEATURE_SHA3
, 0)},
9830 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9831 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9832 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
9833 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9834 | AARCH64_FEATURE_BFLOAT16
, 0)},
9835 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
9836 AARCH64_FEATURE (AARCH64_FEATURE_SME
9837 | AARCH64_FEATURE_SVE2
9838 | AARCH64_FEATURE_BFLOAT16
, 0)},
9839 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
9840 AARCH64_FEATURE (AARCH64_FEATURE_SME
9841 | AARCH64_FEATURE_SVE2
9842 | AARCH64_FEATURE_BFLOAT16
, 0)},
9843 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9845 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9847 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9848 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9849 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9850 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9851 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9853 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9855 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9857 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9860 struct aarch64_long_option_table
9862 const char *option
; /* Substring to match. */
9863 const char *help
; /* Help information. */
9864 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9865 char *deprecated
; /* If non-null, print this message. */
9868 /* Transitive closure of features depending on set. */
9869 static aarch64_feature_set
9870 aarch64_feature_disable_set (aarch64_feature_set set
)
9872 const struct aarch64_option_cpu_value_table
*opt
;
9873 aarch64_feature_set prev
= 0;
9875 while (prev
!= set
) {
9877 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9878 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9879 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9884 /* Transitive closure of dependencies of set. */
9885 static aarch64_feature_set
9886 aarch64_feature_enable_set (aarch64_feature_set set
)
9888 const struct aarch64_option_cpu_value_table
*opt
;
9889 aarch64_feature_set prev
= 0;
9891 while (prev
!= set
) {
9893 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9894 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9895 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9901 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9904 /* We insist on extensions being added before being removed. We achieve
9905 this by using the ADDING_VALUE variable to indicate whether we are
9906 adding an extension (1) or removing it (0) and only allowing it to
9907 change in the order -1 -> 1 -> 0. */
9908 int adding_value
= -1;
9909 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9911 /* Copy the feature set, so that we can modify it. */
9915 while (str
!= NULL
&& *str
!= 0)
9917 const struct aarch64_option_cpu_value_table
*opt
;
9918 const char *ext
= NULL
;
9925 as_bad (_("invalid architectural extension"));
9929 ext
= strchr (++str
, '+');
9935 optlen
= strlen (str
);
9937 if (optlen
>= 2 && startswith (str
, "no"))
9939 if (adding_value
!= 0)
9944 else if (optlen
> 0)
9946 if (adding_value
== -1)
9948 else if (adding_value
!= 1)
9950 as_bad (_("must specify extensions to add before specifying "
9951 "those to remove"));
9958 as_bad (_("missing architectural extension"));
9962 gas_assert (adding_value
!= -1);
9964 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9965 if (strncmp (opt
->name
, str
, optlen
) == 0)
9967 aarch64_feature_set set
;
9969 /* Add or remove the extension. */
9972 set
= aarch64_feature_enable_set (opt
->value
);
9973 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9977 set
= aarch64_feature_disable_set (opt
->value
);
9978 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9983 if (opt
->name
== NULL
)
9985 as_bad (_("unknown architectural extension `%s'"), str
);
9996 aarch64_parse_cpu (const char *str
)
9998 const struct aarch64_cpu_option_table
*opt
;
9999 const char *ext
= strchr (str
, '+');
10003 optlen
= ext
- str
;
10005 optlen
= strlen (str
);
10009 as_bad (_("missing cpu name `%s'"), str
);
10013 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10014 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10016 mcpu_cpu_opt
= &opt
->value
;
10018 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10023 as_bad (_("unknown cpu `%s'"), str
);
10028 aarch64_parse_arch (const char *str
)
10030 const struct aarch64_arch_option_table
*opt
;
10031 const char *ext
= strchr (str
, '+');
10035 optlen
= ext
- str
;
10037 optlen
= strlen (str
);
10041 as_bad (_("missing architecture name `%s'"), str
);
10045 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10046 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10048 march_cpu_opt
= &opt
->value
;
10050 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10055 as_bad (_("unknown architecture `%s'\n"), str
);
10060 struct aarch64_option_abi_value_table
10063 enum aarch64_abi_type value
;
10066 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10067 {"ilp32", AARCH64_ABI_ILP32
},
10068 {"lp64", AARCH64_ABI_LP64
},
10072 aarch64_parse_abi (const char *str
)
10076 if (str
[0] == '\0')
10078 as_bad (_("missing abi name `%s'"), str
);
10082 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10083 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10085 aarch64_abi
= aarch64_abis
[i
].value
;
10089 as_bad (_("unknown abi `%s'\n"), str
);
10093 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10095 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10096 aarch64_parse_abi
, NULL
},
10097 #endif /* OBJ_ELF */
10098 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10099 aarch64_parse_cpu
, NULL
},
10100 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10101 aarch64_parse_arch
, NULL
},
10102 {NULL
, NULL
, 0, NULL
}
10106 md_parse_option (int c
, const char *arg
)
10108 struct aarch64_option_table
*opt
;
10109 struct aarch64_long_option_table
*lopt
;
10115 target_big_endian
= 1;
10121 target_big_endian
= 0;
10126 /* Listing option. Just ignore these, we don't support additional
10131 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10133 if (c
== opt
->option
[0]
10134 && ((arg
== NULL
&& opt
->option
[1] == 0)
10135 || streq (arg
, opt
->option
+ 1)))
10137 /* If the option is deprecated, tell the user. */
10138 if (opt
->deprecated
!= NULL
)
10139 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10140 arg
? arg
: "", _(opt
->deprecated
));
10142 if (opt
->var
!= NULL
)
10143 *opt
->var
= opt
->value
;
10149 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10151 /* These options are expected to have an argument. */
10152 if (c
== lopt
->option
[0]
10154 && startswith (arg
, lopt
->option
+ 1))
10156 /* If the option is deprecated, tell the user. */
10157 if (lopt
->deprecated
!= NULL
)
10158 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10159 _(lopt
->deprecated
));
10161 /* Call the sup-option parser. */
10162 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10173 md_show_usage (FILE * fp
)
10175 struct aarch64_option_table
*opt
;
10176 struct aarch64_long_option_table
*lopt
;
10178 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10180 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10181 if (opt
->help
!= NULL
)
10182 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10184 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10185 if (lopt
->help
!= NULL
)
10186 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10190 -EB assemble code for a big-endian cpu\n"));
10195 -EL assemble code for a little-endian cpu\n"));
10199 /* Parse a .cpu directive. */
10202 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10204 const struct aarch64_cpu_option_table
*opt
;
10210 name
= input_line_pointer
;
10211 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10212 input_line_pointer
++;
10213 saved_char
= *input_line_pointer
;
10214 *input_line_pointer
= 0;
10216 ext
= strchr (name
, '+');
10219 optlen
= ext
- name
;
10221 optlen
= strlen (name
);
10223 /* Skip the first "all" entry. */
10224 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10225 if (strlen (opt
->name
) == optlen
10226 && strncmp (name
, opt
->name
, optlen
) == 0)
10228 mcpu_cpu_opt
= &opt
->value
;
10230 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10233 cpu_variant
= *mcpu_cpu_opt
;
10235 *input_line_pointer
= saved_char
;
10236 demand_empty_rest_of_line ();
10239 as_bad (_("unknown cpu `%s'"), name
);
10240 *input_line_pointer
= saved_char
;
10241 ignore_rest_of_line ();
10245 /* Parse a .arch directive. */
10248 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10250 const struct aarch64_arch_option_table
*opt
;
10256 name
= input_line_pointer
;
10257 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10258 input_line_pointer
++;
10259 saved_char
= *input_line_pointer
;
10260 *input_line_pointer
= 0;
10262 ext
= strchr (name
, '+');
10265 optlen
= ext
- name
;
10267 optlen
= strlen (name
);
10269 /* Skip the first "all" entry. */
10270 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10271 if (strlen (opt
->name
) == optlen
10272 && strncmp (name
, opt
->name
, optlen
) == 0)
10274 mcpu_cpu_opt
= &opt
->value
;
10276 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10279 cpu_variant
= *mcpu_cpu_opt
;
10281 *input_line_pointer
= saved_char
;
10282 demand_empty_rest_of_line ();
10286 as_bad (_("unknown architecture `%s'\n"), name
);
10287 *input_line_pointer
= saved_char
;
10288 ignore_rest_of_line ();
10291 /* Parse a .arch_extension directive. */
10294 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10297 char *ext
= input_line_pointer
;;
10299 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10300 input_line_pointer
++;
10301 saved_char
= *input_line_pointer
;
10302 *input_line_pointer
= 0;
10304 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10307 cpu_variant
= *mcpu_cpu_opt
;
10309 *input_line_pointer
= saved_char
;
10310 demand_empty_rest_of_line ();
10313 /* Copy symbol information. */
10316 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10318 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10322 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10323 This is needed so AArch64 specific st_other values can be independently
10324 specified for an IFUNC resolver (that is called by the dynamic linker)
10325 and the symbol it resolves (aliased to the resolver). In particular,
10326 if a function symbol has special st_other value set via directives,
10327 then attaching an IFUNC resolver to that symbol should not override
10328 the st_other setting. Requiring the directive on the IFUNC resolver
10329 symbol would be unexpected and problematic in C code, where the two
10330 symbols appear as two independent function declarations. */
10333 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10335 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10336 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10339 if (destelf
->size
== NULL
)
10340 destelf
->size
= XNEW (expressionS
);
10341 *destelf
->size
= *srcelf
->size
;
10345 free (destelf
->size
);
10346 destelf
->size
= NULL
;
10348 S_SET_SIZE (dest
, S_GET_SIZE (src
));