1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bool parse_operands (char *, const aarch64_opcode
*);
150 static bool programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
259 bfd_reloc_code_real_type reloc
;
262 /* Macros to define the register types and masks for the purpose
265 #undef AARCH64_REG_TYPES
266 #define AARCH64_REG_TYPES \
267 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
268 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
269 BASIC_REG_TYPE(SP_32) /* wsp */ \
270 BASIC_REG_TYPE(SP_64) /* sp */ \
271 BASIC_REG_TYPE(Z_32) /* wzr */ \
272 BASIC_REG_TYPE(Z_64) /* xzr */ \
273 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
274 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
275 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
276 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
277 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
278 BASIC_REG_TYPE(VN) /* v[0-31] */ \
279 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
280 BASIC_REG_TYPE(PN) /* p[0-15] */ \
281 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
282 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
283 /* Typecheck: same, plus SVE registers. */ \
284 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
286 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
287 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
293 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
294 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
296 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
297 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
299 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
300 /* Typecheck: any [BHSDQ]P FP. */ \
301 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
302 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
303 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
306 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
307 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
308 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
309 be used for SVE instructions, since Zn and Pn are valid symbols \
310 in other contexts. */ \
311 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
314 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
315 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
316 | REG_TYPE(ZN) | REG_TYPE(PN)) \
317 /* Any integer register; used for error messages only. */ \
318 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
321 /* Pseudo type to mark the end of the enumerator sequence. */ \
324 #undef BASIC_REG_TYPE
325 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
326 #undef MULTI_REG_TYPE
327 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
329 /* Register type enumerators. */
330 typedef enum aarch64_reg_type_
332 /* A list of REG_TYPE_*. */
336 #undef BASIC_REG_TYPE
337 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
339 #define REG_TYPE(T) (1 << REG_TYPE_##T)
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) V,
343 /* Structure for a hash table entry for a register. */
347 unsigned char number
;
348 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
349 unsigned char builtin
;
352 /* Values indexed by aarch64_reg_type to assist the type checking. */
353 static const unsigned reg_type_masks
[] =
358 #undef BASIC_REG_TYPE
360 #undef MULTI_REG_TYPE
361 #undef AARCH64_REG_TYPES
363 /* Diagnostics used when we don't get a register of the expected type.
364 Note: this has to synchronized with aarch64_reg_type definitions
367 get_reg_expected_msg (aarch64_reg_type reg_type
)
374 msg
= N_("integer 32-bit register expected");
377 msg
= N_("integer 64-bit register expected");
380 msg
= N_("integer register expected");
382 case REG_TYPE_R64_SP
:
383 msg
= N_("64-bit integer or SP register expected");
385 case REG_TYPE_SVE_BASE
:
386 msg
= N_("base register expected");
389 msg
= N_("integer or zero register expected");
391 case REG_TYPE_SVE_OFFSET
:
392 msg
= N_("offset register expected");
395 msg
= N_("integer or SP register expected");
397 case REG_TYPE_R_Z_SP
:
398 msg
= N_("integer, zero or SP register expected");
401 msg
= N_("8-bit SIMD scalar register expected");
404 msg
= N_("16-bit SIMD scalar or floating-point half precision "
405 "register expected");
408 msg
= N_("32-bit SIMD scalar or floating-point single precision "
409 "register expected");
412 msg
= N_("64-bit SIMD scalar or floating-point double precision "
413 "register expected");
416 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
417 "register expected");
419 case REG_TYPE_R_Z_BHSDQ_V
:
420 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
421 msg
= N_("register expected");
423 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
424 msg
= N_("SIMD scalar or floating-point register expected");
426 case REG_TYPE_VN
: /* any V reg */
427 msg
= N_("vector register expected");
430 msg
= N_("SVE vector register expected");
433 msg
= N_("SVE predicate register expected");
436 as_fatal (_("invalid register type %d"), reg_type
);
441 /* Some well known registers that we refer to directly elsewhere. */
445 /* Instructions take 4 bytes in the object file. */
448 static htab_t aarch64_ops_hsh
;
449 static htab_t aarch64_cond_hsh
;
450 static htab_t aarch64_shift_hsh
;
451 static htab_t aarch64_sys_regs_hsh
;
452 static htab_t aarch64_pstatefield_hsh
;
453 static htab_t aarch64_sys_regs_ic_hsh
;
454 static htab_t aarch64_sys_regs_dc_hsh
;
455 static htab_t aarch64_sys_regs_at_hsh
;
456 static htab_t aarch64_sys_regs_tlbi_hsh
;
457 static htab_t aarch64_sys_regs_sr_hsh
;
458 static htab_t aarch64_reg_hsh
;
459 static htab_t aarch64_barrier_opt_hsh
;
460 static htab_t aarch64_nzcv_hsh
;
461 static htab_t aarch64_pldop_hsh
;
462 static htab_t aarch64_hint_opt_hsh
;
464 /* Stuff needed to resolve the label ambiguity
473 static symbolS
*last_label_seen
;
475 /* Literal pool structure. Held on a per-section
476 and per-sub-section basis. */
478 #define MAX_LITERAL_POOL_SIZE 1024
479 typedef struct literal_expression
482 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
483 LITTLENUM_TYPE
* bignum
;
484 } literal_expression
;
486 typedef struct literal_pool
488 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
489 unsigned int next_free_entry
;
495 struct literal_pool
*next
;
498 /* Pointer to a linked list of literal pools. */
499 static literal_pool
*list_of_pools
= NULL
;
503 /* This array holds the chars that always start a comment. If the
504 pre-processor is disabled, these aren't very useful. */
505 const char comment_chars
[] = "";
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output. */
510 /* Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output. */
513 /* Also note that comments like this one will always work. */
514 const char line_comment_chars
[] = "#";
516 const char line_separator_chars
[] = ";";
518 /* Chars that can be used to separate mant
519 from exp in floating point numbers. */
520 const char EXP_CHARS
[] = "eE";
522 /* Chars that mean this number is a floating point constant. */
526 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
528 /* Prefix character that indicates the start of an immediate value. */
529 #define is_immediate_prefix(C) ((C) == '#')
531 /* Separator character handling. */
533 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
536 skip_past_char (char **str
, char c
)
547 #define skip_past_comma(str) skip_past_char (str, ',')
549 /* Arithmetic expressions (possibly involving symbols). */
551 static bool in_aarch64_get_expression
= false;
553 /* Third argument to aarch64_get_expression. */
554 #define GE_NO_PREFIX false
555 #define GE_OPT_PREFIX true
557 /* Fourth argument to aarch64_get_expression. */
558 #define ALLOW_ABSENT false
559 #define REJECT_ABSENT true
561 /* Fifth argument to aarch64_get_expression. */
562 #define NORMAL_RESOLUTION false
564 /* Return TRUE if the string pointed by *STR is successfully parsed
565 as an valid expression; *EP will be filled with the information of
566 such an expression. Otherwise return FALSE.
568 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
569 If REJECT_ABSENT is true then trat missing expressions as an error.
570 If DEFER_RESOLUTION is true, then do not resolve expressions against
571 constant symbols. Necessary if the expression is part of a fixup
572 that uses a reloc that must be emitted. */
575 aarch64_get_expression (expressionS
* ep
,
577 bool allow_immediate_prefix
,
579 bool defer_resolution
)
583 bool prefix_present
= false;
585 if (allow_immediate_prefix
)
587 if (is_immediate_prefix (**str
))
590 prefix_present
= true;
594 memset (ep
, 0, sizeof (expressionS
));
596 save_in
= input_line_pointer
;
597 input_line_pointer
= *str
;
598 in_aarch64_get_expression
= true;
599 if (defer_resolution
)
600 seg
= deferred_expression (ep
);
602 seg
= expression (ep
);
603 in_aarch64_get_expression
= false;
605 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
607 /* We found a bad expression in md_operand(). */
608 *str
= input_line_pointer
;
609 input_line_pointer
= save_in
;
610 if (prefix_present
&& ! error_p ())
611 set_fatal_syntax_error (_("bad expression"));
613 set_first_syntax_error (_("bad expression"));
618 if (seg
!= absolute_section
619 && seg
!= text_section
620 && seg
!= data_section
621 && seg
!= bss_section
622 && seg
!= undefined_section
)
624 set_syntax_error (_("bad segment"));
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
633 *str
= input_line_pointer
;
634 input_line_pointer
= save_in
;
638 /* Turn a string in input_line_pointer into a floating point constant
639 of type TYPE, and store the appropriate bytes in *LITP. The number
640 of LITTLENUMS emitted is stored in *SIZEP. An error message is
641 returned, or NULL on OK. */
644 md_atof (int type
, char *litP
, int *sizeP
)
646 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
649 /* We handle all bad expressions here, so that we can report the faulty
650 instruction in the error message. */
652 md_operand (expressionS
* exp
)
654 if (in_aarch64_get_expression
)
655 exp
->X_op
= O_illegal
;
658 /* Immediate values. */
660 /* Errors may be set multiple times during parsing or bit encoding
661 (particularly in the Neon bits), but usually the earliest error which is set
662 will be the most meaningful. Avoid overwriting it with later (cascading)
663 errors by calling this function. */
666 first_error (const char *error
)
669 set_syntax_error (error
);
672 /* Similar to first_error, but this function accepts formatted error
675 first_error_fmt (const char *format
, ...)
680 /* N.B. this single buffer will not cause error messages for different
681 instructions to pollute each other; this is because at the end of
682 processing of each assembly line, error message if any will be
683 collected by as_bad. */
684 static char buffer
[size
];
688 int ret ATTRIBUTE_UNUSED
;
689 va_start (args
, format
);
690 ret
= vsnprintf (buffer
, size
, format
, args
);
691 know (ret
<= size
- 1 && ret
>= 0);
693 set_syntax_error (buffer
);
697 /* Register parsing. */
699 /* Generic register parser which is called by other specialized
701 CCP points to what should be the beginning of a register name.
702 If it is indeed a valid register name, advance CCP over it and
703 return the reg_entry structure; otherwise return NULL.
704 It does not issue diagnostics. */
707 parse_reg (char **ccp
)
713 #ifdef REGISTER_PREFIX
714 if (*start
!= REGISTER_PREFIX
)
720 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
725 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
727 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
736 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
739 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
741 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
744 /* Try to parse a base or offset register. Allow SVE base and offset
745 registers if REG_TYPE includes SVE registers. Return the register
746 entry on success, setting *QUALIFIER to the register qualifier.
747 Return null otherwise.
749 Note that this function does not issue any diagnostics. */
751 static const reg_entry
*
752 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
753 aarch64_opnd_qualifier_t
*qualifier
)
756 const reg_entry
*reg
= parse_reg (&str
);
766 *qualifier
= AARCH64_OPND_QLF_W
;
772 *qualifier
= AARCH64_OPND_QLF_X
;
776 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
779 switch (TOLOWER (str
[1]))
782 *qualifier
= AARCH64_OPND_QLF_S_S
;
785 *qualifier
= AARCH64_OPND_QLF_S_D
;
802 /* Try to parse a base or offset register. Return the register entry
803 on success, setting *QUALIFIER to the register qualifier. Return null
806 Note that this function does not issue any diagnostics. */
808 static const reg_entry
*
809 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
811 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
814 /* Parse the qualifier of a vector register or vector element of type
815 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
816 succeeds; otherwise return FALSE.
818 Accept only one occurrence of:
819 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
822 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
823 struct vector_type_el
*parsed_type
, char **str
)
827 unsigned element_size
;
828 enum vector_el_type type
;
831 gas_assert (*ptr
== '.');
834 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
839 width
= strtoul (ptr
, &ptr
, 10);
840 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
842 first_error_fmt (_("bad size %d in vector width specifier"), width
);
847 switch (TOLOWER (*ptr
))
866 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
875 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
877 first_error (_("missing element size"));
880 if (width
!= 0 && width
* element_size
!= 64
881 && width
* element_size
!= 128
882 && !(width
== 2 && element_size
== 16)
883 && !(width
== 4 && element_size
== 8))
886 ("invalid element size %d and vector size combination %c"),
892 parsed_type
->type
= type
;
893 parsed_type
->width
= width
;
900 /* *STR contains an SVE zero/merge predication suffix. Parse it into
901 *PARSED_TYPE and point *STR at the end of the suffix. */
904 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
909 gas_assert (*ptr
== '/');
911 switch (TOLOWER (*ptr
))
914 parsed_type
->type
= NT_zero
;
917 parsed_type
->type
= NT_merge
;
920 if (*ptr
!= '\0' && *ptr
!= ',')
921 first_error_fmt (_("unexpected character `%c' in predication type"),
924 first_error (_("missing predication type"));
927 parsed_type
->width
= 0;
932 /* Parse a register of the type TYPE.
934 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
935 name or the parsed register is not of TYPE.
937 Otherwise return the register number, and optionally fill in the actual
938 type of the register in *RTYPE when multiple alternatives were given, and
939 return the register shape and element index information in *TYPEINFO.
941 IN_REG_LIST should be set with TRUE if the caller is parsing a register
945 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
946 struct vector_type_el
*typeinfo
, bool in_reg_list
)
949 const reg_entry
*reg
= parse_reg (&str
);
950 struct vector_type_el atype
;
951 struct vector_type_el parsetype
;
952 bool is_typed_vecreg
= false;
955 atype
.type
= NT_invtype
;
963 set_default_error ();
967 if (! aarch64_check_reg_type (reg
, type
))
969 DEBUG_TRACE ("reg type check failed");
970 set_default_error ();
975 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
976 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
980 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
985 if (!parse_predication_for_operand (&parsetype
, &str
))
989 /* Register if of the form Vn.[bhsdq]. */
990 is_typed_vecreg
= true;
992 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
994 /* The width is always variable; we don't allow an integer width
996 gas_assert (parsetype
.width
== 0);
997 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
999 else if (parsetype
.width
== 0)
1000 /* Expect index. In the new scheme we cannot have
1001 Vn.[bhsdq] represent a scalar. Therefore any
1002 Vn.[bhsdq] should have an index following it.
1003 Except in reglists of course. */
1004 atype
.defined
|= NTA_HASINDEX
;
1006 atype
.defined
|= NTA_HASTYPE
;
1008 atype
.type
= parsetype
.type
;
1009 atype
.width
= parsetype
.width
;
1012 if (skip_past_char (&str
, '['))
1016 /* Reject Sn[index] syntax. */
1017 if (!is_typed_vecreg
)
1019 first_error (_("this type of register can't be indexed"));
1025 first_error (_("index not allowed inside register list"));
1029 atype
.defined
|= NTA_HASINDEX
;
1031 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1034 if (exp
.X_op
!= O_constant
)
1036 first_error (_("constant expression required"));
1040 if (! skip_past_char (&str
, ']'))
1043 atype
.index
= exp
.X_add_number
;
1045 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1047 /* Indexed vector register expected. */
1048 first_error (_("indexed vector register expected"));
1052 /* A vector reg Vn should be typed or indexed. */
1053 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1055 first_error (_("invalid use of vector register"));
1071 Return the register number on success; return PARSE_FAIL otherwise.
1073 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1074 the register (e.g. NEON double or quad reg when either has been requested).
1076 If this is a NEON vector register with additional type information, fill
1077 in the struct pointed to by VECTYPE (if non-NULL).
1079 This parser does not handle register list. */
1082 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1083 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1085 struct vector_type_el atype
;
1087 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1088 /*in_reg_list= */ false);
1090 if (reg
== PARSE_FAIL
)
1102 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1106 && e1
.defined
== e2
.defined
1107 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1110 /* This function parses a list of vector registers of type TYPE.
1111 On success, it returns the parsed register list information in the
1112 following encoded format:
1114 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1115 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1117 The information of the register shape and/or index is returned in
1120 It returns PARSE_FAIL if the register list is invalid.
1122 The list contains one to four registers.
1123 Each register can be one of:
1126 All <T> should be identical.
1127 All <index> should be identical.
1128 There are restrictions on <Vt> numbers which are checked later
1129 (by reg_list_valid_p). */
1132 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1133 struct vector_type_el
*vectype
)
1137 struct vector_type_el typeinfo
, typeinfo_first
;
1143 bool expect_index
= false;
1147 set_syntax_error (_("expecting {"));
1153 typeinfo_first
.defined
= 0;
1154 typeinfo_first
.type
= NT_invtype
;
1155 typeinfo_first
.width
= -1;
1156 typeinfo_first
.index
= 0;
1165 str
++; /* skip over '-' */
1168 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1169 /*in_reg_list= */ true);
1170 if (val
== PARSE_FAIL
)
1172 set_first_syntax_error (_("invalid vector register in list"));
1176 /* reject [bhsd]n */
1177 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1179 set_first_syntax_error (_("invalid scalar register in list"));
1184 if (typeinfo
.defined
& NTA_HASINDEX
)
1185 expect_index
= true;
1189 if (val
< val_range
)
1191 set_first_syntax_error
1192 (_("invalid range in vector register list"));
1201 typeinfo_first
= typeinfo
;
1202 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1204 set_first_syntax_error
1205 (_("type mismatch in vector register list"));
1210 for (i
= val_range
; i
<= val
; i
++)
1212 ret_val
|= i
<< (5 * nb_regs
);
1217 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1219 skip_whitespace (str
);
1222 set_first_syntax_error (_("end of vector register list not found"));
1227 skip_whitespace (str
);
1231 if (skip_past_char (&str
, '['))
1235 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1237 if (exp
.X_op
!= O_constant
)
1239 set_first_syntax_error (_("constant expression required."));
1242 if (! skip_past_char (&str
, ']'))
1245 typeinfo_first
.index
= exp
.X_add_number
;
1249 set_first_syntax_error (_("expected index"));
1256 set_first_syntax_error (_("too many registers in vector register list"));
1259 else if (nb_regs
== 0)
1261 set_first_syntax_error (_("empty vector register list"));
1267 *vectype
= typeinfo_first
;
1269 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1272 /* Directives: register aliases. */
1275 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1280 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1283 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1286 /* Only warn about a redefinition if it's not defined as the
1288 else if (new->number
!= number
|| new->type
!= type
)
1289 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1294 name
= xstrdup (str
);
1295 new = XNEW (reg_entry
);
1298 new->number
= number
;
1300 new->builtin
= false;
1302 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1307 /* Look for the .req directive. This is of the form:
1309 new_register_name .req existing_register_name
1311 If we find one, or if it looks sufficiently like one that we want to
1312 handle any error here, return TRUE. Otherwise return FALSE. */
1315 create_register_alias (char *newname
, char *p
)
1317 const reg_entry
*old
;
1318 char *oldname
, *nbuf
;
1321 /* The input scrubber ensures that whitespace after the mnemonic is
1322 collapsed to single spaces. */
1324 if (!startswith (oldname
, " .req "))
1328 if (*oldname
== '\0')
1331 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1334 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1338 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1339 the desired alias name, and p points to its end. If not, then
1340 the desired alias name is in the global original_case_string. */
1341 #ifdef TC_CASE_SENSITIVE
1344 newname
= original_case_string
;
1345 nlen
= strlen (newname
);
1348 nbuf
= xmemdup0 (newname
, nlen
);
1350 /* Create aliases under the new name as stated; an all-lowercase
1351 version of the new name; and an all-uppercase version of the new
1353 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1355 for (p
= nbuf
; *p
; p
++)
1358 if (strncmp (nbuf
, newname
, nlen
))
1360 /* If this attempt to create an additional alias fails, do not bother
1361 trying to create the all-lower case alias. We will fail and issue
1362 a second, duplicate error message. This situation arises when the
1363 programmer does something like:
1366 The second .req creates the "Foo" alias but then fails to create
1367 the artificial FOO alias because it has already been created by the
1369 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1376 for (p
= nbuf
; *p
; p
++)
1379 if (strncmp (nbuf
, newname
, nlen
))
1380 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1387 /* Should never be called, as .req goes between the alias and the
1388 register name, not at the beginning of the line. */
1390 s_req (int a ATTRIBUTE_UNUSED
)
1392 as_bad (_("invalid syntax for .req directive"));
1395 /* The .unreq directive deletes an alias which was previously defined
1396 by .req. For example:
1402 s_unreq (int a ATTRIBUTE_UNUSED
)
1407 name
= input_line_pointer
;
1409 while (*input_line_pointer
!= 0
1410 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1411 ++input_line_pointer
;
1413 saved_char
= *input_line_pointer
;
1414 *input_line_pointer
= 0;
1417 as_bad (_("invalid syntax for .unreq directive"));
1420 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1423 as_bad (_("unknown register alias '%s'"), name
);
1424 else if (reg
->builtin
)
1425 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1432 str_hash_delete (aarch64_reg_hsh
, name
);
1433 free ((char *) reg
->name
);
1436 /* Also locate the all upper case and all lower case versions.
1437 Do not complain if we cannot find one or the other as it
1438 was probably deleted above. */
1440 nbuf
= strdup (name
);
1441 for (p
= nbuf
; *p
; p
++)
1443 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1446 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1447 free ((char *) reg
->name
);
1451 for (p
= nbuf
; *p
; p
++)
1453 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1456 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1457 free ((char *) reg
->name
);
1465 *input_line_pointer
= saved_char
;
1466 demand_empty_rest_of_line ();
1469 /* Directives: Instruction set selection. */
1472 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1473 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1474 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1475 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1477 /* Create a new mapping symbol for the transition to STATE. */
1480 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1483 const char *symname
;
1490 type
= BSF_NO_FLAGS
;
1494 type
= BSF_NO_FLAGS
;
1500 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1503 /* Save the mapping symbols for future reference. Also check that
1504 we do not place two mapping symbols at the same offset within a
1505 frag. We'll handle overlap between frags in
1506 check_mapping_symbols.
1508 If .fill or other data filling directive generates zero sized data,
1509 the mapping symbol for the following code will have the same value
1510 as the one generated for the data filling directive. In this case,
1511 we replace the old symbol with the new one at the same address. */
1514 if (frag
->tc_frag_data
.first_map
!= NULL
)
1516 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1517 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1520 frag
->tc_frag_data
.first_map
= symbolP
;
1522 if (frag
->tc_frag_data
.last_map
!= NULL
)
1524 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1525 S_GET_VALUE (symbolP
));
1526 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1527 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1530 frag
->tc_frag_data
.last_map
= symbolP
;
1533 /* We must sometimes convert a region marked as code to data during
1534 code alignment, if an odd number of bytes have to be padded. The
1535 code mapping symbol is pushed to an aligned address. */
1538 insert_data_mapping_symbol (enum mstate state
,
1539 valueT value
, fragS
* frag
, offsetT bytes
)
1541 /* If there was already a mapping symbol, remove it. */
1542 if (frag
->tc_frag_data
.last_map
!= NULL
1543 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1544 frag
->fr_address
+ value
)
1546 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1550 know (frag
->tc_frag_data
.first_map
== symp
);
1551 frag
->tc_frag_data
.first_map
= NULL
;
1553 frag
->tc_frag_data
.last_map
= NULL
;
1554 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1557 make_mapping_symbol (MAP_DATA
, value
, frag
);
1558 make_mapping_symbol (state
, value
+ bytes
, frag
);
1561 static void mapping_state_2 (enum mstate state
, int max_chars
);
1563 /* Set the mapping state to STATE. Only call this when about to
1564 emit some STATE bytes to the file. */
1567 mapping_state (enum mstate state
)
1569 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1571 if (state
== MAP_INSN
)
1572 /* AArch64 instructions require 4-byte alignment. When emitting
1573 instructions into any section, record the appropriate section
1575 record_alignment (now_seg
, 2);
1577 if (mapstate
== state
)
1578 /* The mapping symbol has already been emitted.
1579 There is nothing else to do. */
1582 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1583 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1584 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1585 evaluated later in the next else. */
1587 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1589 /* Only add the symbol if the offset is > 0:
1590 if we're at the first frag, check it's size > 0;
1591 if we're not at the first frag, then for sure
1592 the offset is > 0. */
1593 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1594 const int add_symbol
= (frag_now
!= frag_first
)
1595 || (frag_now_fix () > 0);
1598 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1602 mapping_state_2 (state
, 0);
1605 /* Same as mapping_state, but MAX_CHARS bytes have already been
1606 allocated. Put the mapping symbol that far back. */
1609 mapping_state_2 (enum mstate state
, int max_chars
)
1611 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1613 if (!SEG_NORMAL (now_seg
))
1616 if (mapstate
== state
)
1617 /* The mapping symbol has already been emitted.
1618 There is nothing else to do. */
1621 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1622 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1625 #define mapping_state(x) /* nothing */
1626 #define mapping_state_2(x, y) /* nothing */
1629 /* Directives: sectioning and alignment. */
1632 s_bss (int ignore ATTRIBUTE_UNUSED
)
1634 /* We don't support putting frags in the BSS segment, we fake it by
1635 marking in_bss, then looking at s_skip for clues. */
1636 subseg_set (bss_section
, 0);
1637 demand_empty_rest_of_line ();
1638 mapping_state (MAP_DATA
);
1642 s_even (int ignore ATTRIBUTE_UNUSED
)
1644 /* Never make frag if expect extra pass. */
1646 frag_align (1, 0, 0);
1648 record_alignment (now_seg
, 1);
1650 demand_empty_rest_of_line ();
1653 /* Directives: Literal pools. */
1655 static literal_pool
*
1656 find_literal_pool (int size
)
1660 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1662 if (pool
->section
== now_seg
1663 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1670 static literal_pool
*
1671 find_or_make_literal_pool (int size
)
1673 /* Next literal pool ID number. */
1674 static unsigned int latest_pool_num
= 1;
1677 pool
= find_literal_pool (size
);
1681 /* Create a new pool. */
1682 pool
= XNEW (literal_pool
);
1686 /* Currently we always put the literal pool in the current text
1687 section. If we were generating "small" model code where we
1688 knew that all code and initialised data was within 1MB then
1689 we could output literals to mergeable, read-only data
1692 pool
->next_free_entry
= 0;
1693 pool
->section
= now_seg
;
1694 pool
->sub_section
= now_subseg
;
1696 pool
->next
= list_of_pools
;
1697 pool
->symbol
= NULL
;
1699 /* Add it to the list. */
1700 list_of_pools
= pool
;
1703 /* New pools, and emptied pools, will have a NULL symbol. */
1704 if (pool
->symbol
== NULL
)
1706 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1707 &zero_address_frag
, 0);
1708 pool
->id
= latest_pool_num
++;
1715 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1716 Return TRUE on success, otherwise return FALSE. */
1718 add_to_lit_pool (expressionS
*exp
, int size
)
1723 pool
= find_or_make_literal_pool (size
);
1725 /* Check if this literal value is already in the pool. */
1726 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1728 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1730 if ((litexp
->X_op
== exp
->X_op
)
1731 && (exp
->X_op
== O_constant
)
1732 && (litexp
->X_add_number
== exp
->X_add_number
)
1733 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1736 if ((litexp
->X_op
== exp
->X_op
)
1737 && (exp
->X_op
== O_symbol
)
1738 && (litexp
->X_add_number
== exp
->X_add_number
)
1739 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1740 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1744 /* Do we need to create a new entry? */
1745 if (entry
== pool
->next_free_entry
)
1747 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1749 set_syntax_error (_("literal pool overflow"));
1753 pool
->literals
[entry
].exp
= *exp
;
1754 pool
->next_free_entry
+= 1;
1755 if (exp
->X_op
== O_big
)
1757 /* PR 16688: Bignums are held in a single global array. We must
1758 copy and preserve that value now, before it is overwritten. */
1759 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1761 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1762 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1765 pool
->literals
[entry
].bignum
= NULL
;
1768 exp
->X_op
= O_symbol
;
1769 exp
->X_add_number
= ((int) entry
) * size
;
1770 exp
->X_add_symbol
= pool
->symbol
;
1775 /* Can't use symbol_new here, so have to create a symbol and then at
1776 a later date assign it a value. That's what these functions do. */
1779 symbol_locate (symbolS
* symbolP
,
1780 const char *name
,/* It is copied, the caller can modify. */
1781 segT segment
, /* Segment identifier (SEG_<something>). */
1782 valueT valu
, /* Symbol value. */
1783 fragS
* frag
) /* Associated fragment. */
1786 char *preserved_copy_of_name
;
1788 name_length
= strlen (name
) + 1; /* +1 for \0. */
1789 obstack_grow (¬es
, name
, name_length
);
1790 preserved_copy_of_name
= obstack_finish (¬es
);
1792 #ifdef tc_canonicalize_symbol_name
1793 preserved_copy_of_name
=
1794 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1797 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1799 S_SET_SEGMENT (symbolP
, segment
);
1800 S_SET_VALUE (symbolP
, valu
);
1801 symbol_clear_list_pointers (symbolP
);
1803 symbol_set_frag (symbolP
, frag
);
1805 /* Link to end of symbol chain. */
1807 extern int symbol_table_frozen
;
1809 if (symbol_table_frozen
)
1813 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1815 obj_symbol_new_hook (symbolP
);
1817 #ifdef tc_symbol_new_hook
1818 tc_symbol_new_hook (symbolP
);
1822 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1823 #endif /* DEBUG_SYMS */
1828 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1835 for (align
= 2; align
<= 4; align
++)
1837 int size
= 1 << align
;
1839 pool
= find_literal_pool (size
);
1840 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1843 /* Align pool as you have word accesses.
1844 Only make a frag if we have to. */
1846 frag_align (align
, 0, 0);
1848 mapping_state (MAP_DATA
);
1850 record_alignment (now_seg
, align
);
1852 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1854 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1855 (valueT
) frag_now_fix (), frag_now
);
1856 symbol_table_insert (pool
->symbol
);
1858 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1860 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1862 if (exp
->X_op
== O_big
)
1864 /* PR 16688: Restore the global bignum value. */
1865 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1866 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1867 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1870 /* First output the expression in the instruction to the pool. */
1871 emit_expr (exp
, size
); /* .word|.xword */
1873 if (exp
->X_op
== O_big
)
1875 free (pool
->literals
[entry
].bignum
);
1876 pool
->literals
[entry
].bignum
= NULL
;
1880 /* Mark the pool as empty. */
1881 pool
->next_free_entry
= 0;
1882 pool
->symbol
= NULL
;
1887 /* Forward declarations for functions below, in the MD interface
1889 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1890 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1892 /* Directives: Data. */
1893 /* N.B. the support for relocation suffix in this directive needs to be
1894 implemented properly. */
1897 s_aarch64_elf_cons (int nbytes
)
1901 #ifdef md_flush_pending_output
1902 md_flush_pending_output ();
1905 if (is_it_end_of_statement ())
1907 demand_empty_rest_of_line ();
1911 #ifdef md_cons_align
1912 md_cons_align (nbytes
);
1915 mapping_state (MAP_DATA
);
1918 struct reloc_table_entry
*reloc
;
1922 if (exp
.X_op
!= O_symbol
)
1923 emit_expr (&exp
, (unsigned int) nbytes
);
1926 skip_past_char (&input_line_pointer
, '#');
1927 if (skip_past_char (&input_line_pointer
, ':'))
1929 reloc
= find_reloc_table_entry (&input_line_pointer
);
1931 as_bad (_("unrecognized relocation suffix"));
1933 as_bad (_("unimplemented relocation suffix"));
1934 ignore_rest_of_line ();
1938 emit_expr (&exp
, (unsigned int) nbytes
);
1941 while (*input_line_pointer
++ == ',');
1943 /* Put terminator back into stream. */
1944 input_line_pointer
--;
1945 demand_empty_rest_of_line ();
1948 /* Mark symbol that it follows a variant PCS convention. */
1951 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1957 elf_symbol_type
*elfsym
;
1959 c
= get_symbol_name (&name
);
1961 as_bad (_("Missing symbol name in directive"));
1962 sym
= symbol_find_or_make (name
);
1963 restore_line_pointer (c
);
1964 demand_empty_rest_of_line ();
1965 bfdsym
= symbol_get_bfdsym (sym
);
1966 elfsym
= elf_symbol_from (bfdsym
);
1967 gas_assert (elfsym
);
1968 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1970 #endif /* OBJ_ELF */
1972 /* Output a 32-bit word, but mark as an instruction. */
1975 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1979 #ifdef md_flush_pending_output
1980 md_flush_pending_output ();
1983 if (is_it_end_of_statement ())
1985 demand_empty_rest_of_line ();
1989 /* Sections are assumed to start aligned. In executable section, there is no
1990 MAP_DATA symbol pending. So we only align the address during
1991 MAP_DATA --> MAP_INSN transition.
1992 For other sections, this is not guaranteed. */
1993 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1994 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1995 frag_align_code (2, 0);
1998 mapping_state (MAP_INSN
);
2004 if (exp
.X_op
!= O_constant
)
2006 as_bad (_("constant expression required"));
2007 ignore_rest_of_line ();
2011 if (target_big_endian
)
2013 unsigned int val
= exp
.X_add_number
;
2014 exp
.X_add_number
= SWAP_32 (val
);
2016 emit_expr (&exp
, 4);
2018 while (*input_line_pointer
++ == ',');
2020 /* Put terminator back into stream. */
2021 input_line_pointer
--;
2022 demand_empty_rest_of_line ();
2026 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2028 demand_empty_rest_of_line ();
2029 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2030 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2034 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2037 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2043 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2044 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2046 demand_empty_rest_of_line ();
2049 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2052 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2056 /* Since we're just labelling the code, there's no need to define a
2059 /* Make sure there is enough room in this frag for the following
2060 blr. This trick only works if the blr follows immediately after
2061 the .tlsdesc directive. */
2063 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2064 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2066 demand_empty_rest_of_line ();
2069 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2072 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2078 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2079 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2081 demand_empty_rest_of_line ();
2083 #endif /* OBJ_ELF */
2085 static void s_aarch64_arch (int);
2086 static void s_aarch64_cpu (int);
2087 static void s_aarch64_arch_extension (int);
2089 /* This table describes all the machine specific pseudo-ops the assembler
2090 has to support. The fields are:
2091 pseudo-op name without dot
2092 function to call to execute this pseudo-op
2093 Integer arg to pass to the function. */
2095 const pseudo_typeS md_pseudo_table
[] = {
2096 /* Never called because '.req' does not start a line. */
2098 {"unreq", s_unreq
, 0},
2100 {"even", s_even
, 0},
2101 {"ltorg", s_ltorg
, 0},
2102 {"pool", s_ltorg
, 0},
2103 {"cpu", s_aarch64_cpu
, 0},
2104 {"arch", s_aarch64_arch
, 0},
2105 {"arch_extension", s_aarch64_arch_extension
, 0},
2106 {"inst", s_aarch64_inst
, 0},
2107 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2109 {"tlsdescadd", s_tlsdescadd
, 0},
2110 {"tlsdesccall", s_tlsdesccall
, 0},
2111 {"tlsdescldr", s_tlsdescldr
, 0},
2112 {"word", s_aarch64_elf_cons
, 4},
2113 {"long", s_aarch64_elf_cons
, 4},
2114 {"xword", s_aarch64_elf_cons
, 8},
2115 {"dword", s_aarch64_elf_cons
, 8},
2116 {"variant_pcs", s_variant_pcs
, 0},
2118 {"float16", float_cons
, 'h'},
2119 {"bfloat16", float_cons
, 'b'},
2124 /* Check whether STR points to a register name followed by a comma or the
2125 end of line; REG_TYPE indicates which register types are checked
2126 against. Return TRUE if STR is such a register name; otherwise return
2127 FALSE. The function does not intend to produce any diagnostics, but since
2128 the register parser aarch64_reg_parse, which is called by this function,
2129 does produce diagnostics, we call clear_error to clear any diagnostics
2130 that may be generated by aarch64_reg_parse.
2131 Also, the function returns FALSE directly if there is any user error
2132 present at the function entry. This prevents the existing diagnostics
2133 state from being spoiled.
2134 The function currently serves parse_constant_immediate and
2135 parse_big_immediate only. */
2137 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2141 /* Prevent the diagnostics state from being spoiled. */
2145 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2147 /* Clear the parsing error that may be set by the reg parser. */
2150 if (reg
== PARSE_FAIL
)
2153 skip_whitespace (str
);
2154 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2160 /* Parser functions used exclusively in instruction operands. */
2162 /* Parse an immediate expression which may not be constant.
2164 To prevent the expression parser from pushing a register name
2165 into the symbol table as an undefined symbol, firstly a check is
2166 done to find out whether STR is a register of type REG_TYPE followed
2167 by a comma or the end of line. Return FALSE if STR is such a string. */
2170 parse_immediate_expression (char **str
, expressionS
*exp
,
2171 aarch64_reg_type reg_type
)
2173 if (reg_name_p (*str
, reg_type
))
2175 set_recoverable_error (_("immediate operand required"));
2179 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2182 if (exp
->X_op
== O_absent
)
2184 set_fatal_syntax_error (_("missing immediate expression"));
2191 /* Constant immediate-value read function for use in insn parsing.
2192 STR points to the beginning of the immediate (with the optional
2193 leading #); *VAL receives the value. REG_TYPE says which register
2194 names should be treated as registers rather than as symbolic immediates.
2196 Return TRUE on success; otherwise return FALSE. */
2199 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2203 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2206 if (exp
.X_op
!= O_constant
)
2208 set_syntax_error (_("constant expression required"));
2212 *val
= exp
.X_add_number
;
2217 encode_imm_float_bits (uint32_t imm
)
2219 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2220 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2223 /* Return TRUE if the single-precision floating-point value encoded in IMM
2224 can be expressed in the AArch64 8-bit signed floating-point format with
2225 3-bit exponent and normalized 4 bits of precision; in other words, the
2226 floating-point value must be expressable as
2227 (+/-) n / 16 * power (2, r)
2228 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2231 aarch64_imm_float_p (uint32_t imm
)
2233 /* If a single-precision floating-point value has the following bit
2234 pattern, it can be expressed in the AArch64 8-bit floating-point
2237 3 32222222 2221111111111
2238 1 09876543 21098765432109876543210
2239 n Eeeeeexx xxxx0000000000000000000
2241 where n, e and each x are either 0 or 1 independently, with
2246 /* Prepare the pattern for 'Eeeeee'. */
2247 if (((imm
>> 30) & 0x1) == 0)
2248 pattern
= 0x3e000000;
2250 pattern
= 0x40000000;
2252 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2253 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2256 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2257 as an IEEE float without any loss of precision. Store the value in
2261 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2263 /* If a double-precision floating-point value has the following bit
2264 pattern, it can be expressed in a float:
2266 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2267 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2268 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2270 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2271 if Eeee_eeee != 1111_1111
2273 where n, e, s and S are either 0 or 1 independently and where ~ is the
2277 uint32_t high32
= imm
>> 32;
2278 uint32_t low32
= imm
;
2280 /* Lower 29 bits need to be 0s. */
2281 if ((imm
& 0x1fffffff) != 0)
2284 /* Prepare the pattern for 'Eeeeeeeee'. */
2285 if (((high32
>> 30) & 0x1) == 0)
2286 pattern
= 0x38000000;
2288 pattern
= 0x40000000;
2291 if ((high32
& 0x78000000) != pattern
)
2294 /* Check Eeee_eeee != 1111_1111. */
2295 if ((high32
& 0x7ff00000) == 0x47f00000)
2298 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2299 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2300 | (low32
>> 29)); /* 3 S bits. */
2304 /* Return true if we should treat OPERAND as a double-precision
2305 floating-point operand rather than a single-precision one. */
2307 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2309 /* Check for unsuffixed SVE registers, which are allowed
2310 for LDR and STR but not in instructions that require an
2311 immediate. We get better error messages if we arbitrarily
2312 pick one size, parse the immediate normally, and then
2313 report the match failure in the normal way. */
2314 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2315 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2318 /* Parse a floating-point immediate. Return TRUE on success and return the
2319 value in *IMMED in the format of IEEE754 single-precision encoding.
2320 *CCP points to the start of the string; DP_P is TRUE when the immediate
2321 is expected to be in double-precision (N.B. this only matters when
2322 hexadecimal representation is involved). REG_TYPE says which register
2323 names should be treated as registers rather than as symbolic immediates.
2325 This routine accepts any IEEE float; it is up to the callers to reject
2329 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2330 aarch64_reg_type reg_type
)
2334 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2336 unsigned fpword
= 0;
2339 skip_past_char (&str
, '#');
2342 skip_whitespace (fpnum
);
2344 if (startswith (fpnum
, "0x"))
2346 /* Support the hexadecimal representation of the IEEE754 encoding.
2347 Double-precision is expected when DP_P is TRUE, otherwise the
2348 representation should be in single-precision. */
2349 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2354 if (!can_convert_double_to_float (val
, &fpword
))
2357 else if ((uint64_t) val
> 0xffffffff)
2364 else if (reg_name_p (str
, reg_type
))
2366 set_recoverable_error (_("immediate operand required"));
2374 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2377 /* Our FP word must be 32 bits (single-precision FP). */
2378 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2380 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2390 set_fatal_syntax_error (_("invalid floating-point constant"));
2394 /* Less-generic immediate-value read function with the possibility of loading
2395 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2398 To prevent the expression parser from pushing a register name into the
2399 symbol table as an undefined symbol, a check is firstly done to find
2400 out whether STR is a register of type REG_TYPE followed by a comma or
2401 the end of line. Return FALSE if STR is such a register. */
2404 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2408 if (reg_name_p (ptr
, reg_type
))
2410 set_syntax_error (_("immediate operand required"));
2414 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2417 if (inst
.reloc
.exp
.X_op
== O_constant
)
2418 *imm
= inst
.reloc
.exp
.X_add_number
;
2425 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2426 if NEED_LIBOPCODES is non-zero, the fixup will need
2427 assistance from the libopcodes. */
2430 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2431 const aarch64_opnd_info
*operand
,
2432 int need_libopcodes_p
)
2434 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2435 reloc
->opnd
= operand
->type
;
2436 if (need_libopcodes_p
)
2437 reloc
->need_libopcodes_p
= 1;
2440 /* Return TRUE if the instruction needs to be fixed up later internally by
2441 the GAS; otherwise return FALSE. */
2444 aarch64_gas_internal_fixup_p (void)
2446 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2449 /* Assign the immediate value to the relevant field in *OPERAND if
2450 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2451 needs an internal fixup in a later stage.
2452 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2453 IMM.VALUE that may get assigned with the constant. */
2455 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2456 aarch64_opnd_info
*operand
,
2458 int need_libopcodes_p
,
2461 if (reloc
->exp
.X_op
== O_constant
)
2464 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2466 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2467 reloc
->type
= BFD_RELOC_UNUSED
;
2471 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2472 /* Tell libopcodes to ignore this operand or not. This is helpful
2473 when one of the operands needs to be fixed up later but we need
2474 libopcodes to check the other operands. */
2475 operand
->skip
= skip_p
;
2479 /* Relocation modifiers. Each entry in the table contains the textual
2480 name for the relocation which may be placed before a symbol used as
2481 a load/store offset, or add immediate. It must be surrounded by a
2482 leading and trailing colon, for example:
2484 ldr x0, [x1, #:rello:varsym]
2485 add x0, x1, #:rello:varsym */
2487 struct reloc_table_entry
2491 bfd_reloc_code_real_type adr_type
;
2492 bfd_reloc_code_real_type adrp_type
;
2493 bfd_reloc_code_real_type movw_type
;
2494 bfd_reloc_code_real_type add_type
;
2495 bfd_reloc_code_real_type ldst_type
;
2496 bfd_reloc_code_real_type ld_literal_type
;
2499 static struct reloc_table_entry reloc_table
[] =
2501 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2506 BFD_RELOC_AARCH64_ADD_LO12
,
2507 BFD_RELOC_AARCH64_LDST_LO12
,
2510 /* Higher 21 bits of pc-relative page offset: ADRP */
2513 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2519 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2522 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2528 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2532 BFD_RELOC_AARCH64_MOVW_G0
,
2537 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2541 BFD_RELOC_AARCH64_MOVW_G0_S
,
2546 /* Less significant bits 0-15 of address/value: MOVK, no check */
2550 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2555 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2559 BFD_RELOC_AARCH64_MOVW_G1
,
2564 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2568 BFD_RELOC_AARCH64_MOVW_G1_S
,
2573 /* Less significant bits 16-31 of address/value: MOVK, no check */
2577 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2582 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2586 BFD_RELOC_AARCH64_MOVW_G2
,
2591 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2595 BFD_RELOC_AARCH64_MOVW_G2_S
,
2600 /* Less significant bits 32-47 of address/value: MOVK, no check */
2604 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2609 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2613 BFD_RELOC_AARCH64_MOVW_G3
,
2618 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2622 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2627 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2631 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2636 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2640 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2645 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2649 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2654 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2658 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2663 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2667 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2672 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2676 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2681 /* Get to the page containing GOT entry for a symbol. */
2684 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2688 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2690 /* 12 bit offset into the page containing GOT entry for that symbol. */
2696 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2699 /* 0-15 bits of address/value: MOVk, no check. */
2703 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2708 /* Most significant bits 16-31 of address/value: MOVZ. */
2712 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2717 /* 15 bit offset into the page containing GOT entry for that symbol. */
2723 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2726 /* Get to the page containing GOT TLS entry for a symbol */
2727 {"gottprel_g0_nc", 0,
2730 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2735 /* Get to the page containing GOT TLS entry for a symbol */
2739 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2744 /* Get to the page containing GOT TLS entry for a symbol */
2746 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2747 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2753 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2758 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2762 /* Lower 16 bits address/value: MOVk. */
2766 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2771 /* Most significant bits 16-31 of address/value: MOVZ. */
2775 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2780 /* Get to the page containing GOT TLS entry for a symbol */
2782 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2783 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2787 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2789 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2794 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2795 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2798 /* Get to the page containing GOT TLS entry for a symbol.
2799 The same as GD, we allocate two consecutive GOT slots
2800 for module index and module offset, the only difference
2801 with GD is the module offset should be initialized to
2802 zero without any outstanding runtime relocation. */
2804 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2805 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2811 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2812 {"tlsldm_lo12_nc", 0,
2816 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2820 /* 12 bit offset into the module TLS base address. */
2825 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2826 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2829 /* Same as dtprel_lo12, no overflow check. */
2830 {"dtprel_lo12_nc", 0,
2834 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2835 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2838 /* bits[23:12] of offset to the module TLS base address. */
2843 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2847 /* bits[15:0] of offset to the module TLS base address. */
2851 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2856 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2860 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2865 /* bits[31:16] of offset to the module TLS base address. */
2869 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2874 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2878 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2883 /* bits[47:32] of offset to the module TLS base address. */
2887 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2892 /* Lower 16 bit offset into GOT entry for a symbol */
2893 {"tlsdesc_off_g0_nc", 0,
2896 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2901 /* Higher 16 bit offset into GOT entry for a symbol */
2902 {"tlsdesc_off_g1", 0,
2905 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2910 /* Get to the page containing GOT TLS entry for a symbol */
2913 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2917 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2919 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2920 {"gottprel_lo12", 0,
2925 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2928 /* Get tp offset for a symbol. */
2933 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2937 /* Get tp offset for a symbol. */
2942 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2943 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2946 /* Get tp offset for a symbol. */
2951 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2955 /* Get tp offset for a symbol. */
2956 {"tprel_lo12_nc", 0,
2960 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2961 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2964 /* Most significant bits 32-47 of address/value: MOVZ. */
2968 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2973 /* Most significant bits 16-31 of address/value: MOVZ. */
2977 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2982 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2986 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2991 /* Most significant bits 0-15 of address/value: MOVZ. */
2995 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3000 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3004 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3009 /* 15bit offset from got entry to base address of GOT table. */
3015 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3018 /* 14bit offset from got entry to base address of GOT table. */
3024 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3028 /* Given the address of a pointer pointing to the textual name of a
3029 relocation as may appear in assembler source, attempt to find its
3030 details in reloc_table. The pointer will be updated to the character
3031 after the trailing colon. On failure, NULL will be returned;
3032 otherwise return the reloc_table_entry. */
3034 static struct reloc_table_entry
*
3035 find_reloc_table_entry (char **str
)
3038 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3040 int length
= strlen (reloc_table
[i
].name
);
3042 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3043 && (*str
)[length
] == ':')
3045 *str
+= (length
+ 1);
3046 return &reloc_table
[i
];
3053 /* Returns 0 if the relocation should never be forced,
3054 1 if the relocation must be forced, and -1 if either
3058 aarch64_force_reloc (unsigned int type
)
3062 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3063 /* Perform these "immediate" internal relocations
3064 even if the symbol is extern or weak. */
3067 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3068 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3069 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3070 /* Pseudo relocs that need to be fixed up according to
3074 case BFD_RELOC_AARCH64_ADD_LO12
:
3075 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3076 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3077 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3078 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3079 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3080 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3081 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3082 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3083 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3084 case BFD_RELOC_AARCH64_LDST128_LO12
:
3085 case BFD_RELOC_AARCH64_LDST16_LO12
:
3086 case BFD_RELOC_AARCH64_LDST32_LO12
:
3087 case BFD_RELOC_AARCH64_LDST64_LO12
:
3088 case BFD_RELOC_AARCH64_LDST8_LO12
:
3089 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3090 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3091 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3092 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3093 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3094 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3095 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3096 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3097 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3098 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3099 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3100 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3101 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3102 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3103 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3104 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3105 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3106 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3107 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3108 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3109 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3110 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3111 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3112 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3113 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3114 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3115 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3116 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3117 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3118 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3119 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3120 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3121 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3122 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3123 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3124 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3125 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3126 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3127 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3128 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3129 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3130 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3131 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3132 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3133 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3134 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3135 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3136 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3137 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3138 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3139 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3140 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3141 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3142 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3143 /* Always leave these relocations for the linker. */
3152 aarch64_force_relocation (struct fix
*fixp
)
3154 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3157 return generic_force_reloc (fixp
);
3161 /* Mode argument to parse_shift and parser_shifter_operand. */
3162 enum parse_shift_mode
3164 SHIFTED_NONE
, /* no shifter allowed */
3165 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3167 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3169 SHIFTED_LSL
, /* bare "lsl #n" */
3170 SHIFTED_MUL
, /* bare "mul #n" */
3171 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3172 SHIFTED_MUL_VL
, /* "mul vl" */
3173 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3176 /* Parse a <shift> operator on an AArch64 data processing instruction.
3177 Return TRUE on success; otherwise return FALSE. */
3179 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3181 const struct aarch64_name_value_pair
*shift_op
;
3182 enum aarch64_modifier_kind kind
;
3188 for (p
= *str
; ISALPHA (*p
); p
++)
3193 set_syntax_error (_("shift expression expected"));
3197 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3199 if (shift_op
== NULL
)
3201 set_syntax_error (_("shift operator expected"));
3205 kind
= aarch64_get_operand_modifier (shift_op
);
3207 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3209 set_syntax_error (_("invalid use of 'MSL'"));
3213 if (kind
== AARCH64_MOD_MUL
3214 && mode
!= SHIFTED_MUL
3215 && mode
!= SHIFTED_MUL_VL
)
3217 set_syntax_error (_("invalid use of 'MUL'"));
3223 case SHIFTED_LOGIC_IMM
:
3224 if (aarch64_extend_operator_p (kind
))
3226 set_syntax_error (_("extending shift is not permitted"));
3231 case SHIFTED_ARITH_IMM
:
3232 if (kind
== AARCH64_MOD_ROR
)
3234 set_syntax_error (_("'ROR' shift is not permitted"));
3240 if (kind
!= AARCH64_MOD_LSL
)
3242 set_syntax_error (_("only 'LSL' shift is permitted"));
3248 if (kind
!= AARCH64_MOD_MUL
)
3250 set_syntax_error (_("only 'MUL' is permitted"));
3255 case SHIFTED_MUL_VL
:
3256 /* "MUL VL" consists of two separate tokens. Require the first
3257 token to be "MUL" and look for a following "VL". */
3258 if (kind
== AARCH64_MOD_MUL
)
3260 skip_whitespace (p
);
3261 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3264 kind
= AARCH64_MOD_MUL_VL
;
3268 set_syntax_error (_("only 'MUL VL' is permitted"));
3271 case SHIFTED_REG_OFFSET
:
3272 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3273 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3275 set_fatal_syntax_error
3276 (_("invalid shift for the register offset addressing mode"));
3281 case SHIFTED_LSL_MSL
:
3282 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3284 set_syntax_error (_("invalid shift operator"));
3293 /* Whitespace can appear here if the next thing is a bare digit. */
3294 skip_whitespace (p
);
3296 /* Parse shift amount. */
3298 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3299 exp
.X_op
= O_absent
;
3302 if (is_immediate_prefix (*p
))
3307 (void) aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
,
3310 if (kind
== AARCH64_MOD_MUL_VL
)
3311 /* For consistency, give MUL VL the same shift amount as an implicit
3313 operand
->shifter
.amount
= 1;
3314 else if (exp
.X_op
== O_absent
)
3316 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3318 set_syntax_error (_("missing shift amount"));
3321 operand
->shifter
.amount
= 0;
3323 else if (exp
.X_op
!= O_constant
)
3325 set_syntax_error (_("constant shift amount required"));
3328 /* For parsing purposes, MUL #n has no inherent range. The range
3329 depends on the operand and will be checked by operand-specific
3331 else if (kind
!= AARCH64_MOD_MUL
3332 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3334 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3339 operand
->shifter
.amount
= exp
.X_add_number
;
3340 operand
->shifter
.amount_present
= 1;
3343 operand
->shifter
.operator_present
= 1;
3344 operand
->shifter
.kind
= kind
;
3350 /* Parse a <shifter_operand> for a data processing instruction:
3353 #<immediate>, LSL #imm
3355 Validation of immediate operands is deferred to md_apply_fix.
3357 Return TRUE on success; otherwise return FALSE. */
3360 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3361 enum parse_shift_mode mode
)
3365 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3370 /* Accept an immediate expression. */
3371 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3372 REJECT_ABSENT
, NORMAL_RESOLUTION
))
3375 /* Accept optional LSL for arithmetic immediate values. */
3376 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3377 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3380 /* Not accept any shifter for logical immediate values. */
3381 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3382 && parse_shift (&p
, operand
, mode
))
3384 set_syntax_error (_("unexpected shift operator"));
3392 /* Parse a <shifter_operand> for a data processing instruction:
3397 #<immediate>, LSL #imm
3399 where <shift> is handled by parse_shift above, and the last two
3400 cases are handled by the function above.
3402 Validation of immediate operands is deferred to md_apply_fix.
3404 Return TRUE on success; otherwise return FALSE. */
3407 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3408 enum parse_shift_mode mode
)
3410 const reg_entry
*reg
;
3411 aarch64_opnd_qualifier_t qualifier
;
3412 enum aarch64_operand_class opd_class
3413 = aarch64_get_operand_class (operand
->type
);
3415 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3418 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3420 set_syntax_error (_("unexpected register in the immediate operand"));
3424 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3426 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3430 operand
->reg
.regno
= reg
->number
;
3431 operand
->qualifier
= qualifier
;
3433 /* Accept optional shift operation on register. */
3434 if (! skip_past_comma (str
))
3437 if (! parse_shift (str
, operand
, mode
))
3442 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3445 (_("integer register expected in the extended/shifted operand "
3450 /* We have a shifted immediate variable. */
3451 return parse_shifter_operand_imm (str
, operand
, mode
);
3454 /* Return TRUE on success; return FALSE otherwise. */
3457 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3458 enum parse_shift_mode mode
)
3462 /* Determine if we have the sequence of characters #: or just :
3463 coming next. If we do, then we check for a :rello: relocation
3464 modifier. If we don't, punt the whole lot to
3465 parse_shifter_operand. */
3467 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3469 struct reloc_table_entry
*entry
;
3477 /* Try to parse a relocation. Anything else is an error. */
3478 if (!(entry
= find_reloc_table_entry (str
)))
3480 set_syntax_error (_("unknown relocation modifier"));
3484 if (entry
->add_type
== 0)
3487 (_("this relocation modifier is not allowed on this instruction"));
3491 /* Save str before we decompose it. */
3494 /* Next, we parse the expression. */
3495 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3497 aarch64_force_reloc (entry
->add_type
) == 1))
3500 /* Record the relocation type (use the ADD variant here). */
3501 inst
.reloc
.type
= entry
->add_type
;
3502 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3504 /* If str is empty, we've reached the end, stop here. */
3508 /* Otherwise, we have a shifted reloc modifier, so rewind to
3509 recover the variable name and continue parsing for the shifter. */
3511 return parse_shifter_operand_imm (str
, operand
, mode
);
3514 return parse_shifter_operand (str
, operand
, mode
);
3517 /* Parse all forms of an address expression. Information is written
3518 to *OPERAND and/or inst.reloc.
3520 The A64 instruction set has the following addressing modes:
3523 [base] // in SIMD ld/st structure
3524 [base{,#0}] // in ld/st exclusive
3526 [base,Xm{,LSL #imm}]
3527 [base,Xm,SXTX {#imm}]
3528 [base,Wm,(S|U)XTW {#imm}]
3530 [base]! // in ldraa/ldrab exclusive
3534 [base],Xm // in SIMD ld/st structure
3535 PC-relative (literal)
3539 [base,Zm.D{,LSL #imm}]
3540 [base,Zm.S,(S|U)XTW {#imm}]
3541 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3545 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3546 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3547 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3549 (As a convenience, the notation "=immediate" is permitted in conjunction
3550 with the pc-relative literal load instructions to automatically place an
3551 immediate value or symbolic address in a nearby literal pool and generate
3552 a hidden label which references it.)
3554 Upon a successful parsing, the address structure in *OPERAND will be
3555 filled in the following way:
3557 .base_regno = <base>
3558 .offset.is_reg // 1 if the offset is a register
3560 .offset.regno = <Rm>
3562 For different addressing modes defined in the A64 ISA:
3565 .pcrel=0; .preind=1; .postind=0; .writeback=0
3567 .pcrel=0; .preind=1; .postind=0; .writeback=1
3569 .pcrel=0; .preind=0; .postind=1; .writeback=1
3570 PC-relative (literal)
3571 .pcrel=1; .preind=1; .postind=0; .writeback=0
3573 The shift/extension information, if any, will be stored in .shifter.
3574 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3575 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3576 corresponding register.
3578 BASE_TYPE says which types of base register should be accepted and
3579 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3580 is the type of shifter that is allowed for immediate offsets,
3581 or SHIFTED_NONE if none.
3583 In all other respects, it is the caller's responsibility to check
3584 for addressing modes not supported by the instruction, and to set
3588 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3589 aarch64_opnd_qualifier_t
*base_qualifier
,
3590 aarch64_opnd_qualifier_t
*offset_qualifier
,
3591 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3592 enum parse_shift_mode imm_shift_mode
)
3595 const reg_entry
*reg
;
3596 expressionS
*exp
= &inst
.reloc
.exp
;
3598 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3599 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3600 if (! skip_past_char (&p
, '['))
3602 /* =immediate or label. */
3603 operand
->addr
.pcrel
= 1;
3604 operand
->addr
.preind
= 1;
3606 /* #:<reloc_op>:<symbol> */
3607 skip_past_char (&p
, '#');
3608 if (skip_past_char (&p
, ':'))
3610 bfd_reloc_code_real_type ty
;
3611 struct reloc_table_entry
*entry
;
3613 /* Try to parse a relocation modifier. Anything else is
3615 entry
= find_reloc_table_entry (&p
);
3618 set_syntax_error (_("unknown relocation modifier"));
3622 switch (operand
->type
)
3624 case AARCH64_OPND_ADDR_PCREL21
:
3626 ty
= entry
->adr_type
;
3630 ty
= entry
->ld_literal_type
;
3637 (_("this relocation modifier is not allowed on this "
3643 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3644 aarch64_force_reloc (entry
->add_type
) == 1))
3646 set_syntax_error (_("invalid relocation expression"));
3649 /* #:<reloc_op>:<expr> */
3650 /* Record the relocation type. */
3651 inst
.reloc
.type
= ty
;
3652 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3656 if (skip_past_char (&p
, '='))
3657 /* =immediate; need to generate the literal in the literal pool. */
3658 inst
.gen_lit_pool
= 1;
3660 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3663 set_syntax_error (_("invalid address"));
3674 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3675 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3677 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3680 operand
->addr
.base_regno
= reg
->number
;
3683 if (skip_past_comma (&p
))
3686 operand
->addr
.preind
= 1;
3688 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3691 if (!aarch64_check_reg_type (reg
, offset_type
))
3693 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3698 operand
->addr
.offset
.regno
= reg
->number
;
3699 operand
->addr
.offset
.is_reg
= 1;
3700 /* Shifted index. */
3701 if (skip_past_comma (&p
))
3704 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3705 /* Use the diagnostics set in parse_shift, so not set new
3706 error message here. */
3710 [base,Xm] # For vector plus scalar SVE2 indexing.
3711 [base,Xm{,LSL #imm}]
3712 [base,Xm,SXTX {#imm}]
3713 [base,Wm,(S|U)XTW {#imm}] */
3714 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3715 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3716 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3718 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3720 set_syntax_error (_("invalid use of 32-bit register offset"));
3723 if (aarch64_get_qualifier_esize (*base_qualifier
)
3724 != aarch64_get_qualifier_esize (*offset_qualifier
)
3725 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3726 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3727 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3729 set_syntax_error (_("offset has different size from base"));
3733 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3735 set_syntax_error (_("invalid use of 64-bit register offset"));
3741 /* [Xn,#:<reloc_op>:<symbol> */
3742 skip_past_char (&p
, '#');
3743 if (skip_past_char (&p
, ':'))
3745 struct reloc_table_entry
*entry
;
3747 /* Try to parse a relocation modifier. Anything else is
3749 if (!(entry
= find_reloc_table_entry (&p
)))
3751 set_syntax_error (_("unknown relocation modifier"));
3755 if (entry
->ldst_type
== 0)
3758 (_("this relocation modifier is not allowed on this "
3763 /* [Xn,#:<reloc_op>: */
3764 /* We now have the group relocation table entry corresponding to
3765 the name in the assembler source. Next, we parse the
3767 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3768 aarch64_force_reloc (entry
->add_type
) == 1))
3770 set_syntax_error (_("invalid relocation expression"));
3774 /* [Xn,#:<reloc_op>:<expr> */
3775 /* Record the load/store relocation type. */
3776 inst
.reloc
.type
= entry
->ldst_type
;
3777 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3781 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3784 set_syntax_error (_("invalid expression in the address"));
3788 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3789 /* [Xn,<expr>,<shifter> */
3790 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3796 if (! skip_past_char (&p
, ']'))
3798 set_syntax_error (_("']' expected"));
3802 if (skip_past_char (&p
, '!'))
3804 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3806 set_syntax_error (_("register offset not allowed in pre-indexed "
3807 "addressing mode"));
3811 operand
->addr
.writeback
= 1;
3813 else if (skip_past_comma (&p
))
3816 operand
->addr
.postind
= 1;
3817 operand
->addr
.writeback
= 1;
3819 if (operand
->addr
.preind
)
3821 set_syntax_error (_("cannot combine pre- and post-indexing"));
3825 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3829 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3831 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3835 operand
->addr
.offset
.regno
= reg
->number
;
3836 operand
->addr
.offset
.is_reg
= 1;
3838 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3842 set_syntax_error (_("invalid expression in the address"));
3847 /* If at this point neither .preind nor .postind is set, we have a
3848 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3849 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3850 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3852 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3854 if (operand
->addr
.writeback
)
3856 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3858 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3859 operand
->addr
.offset
.is_reg
= 0;
3860 operand
->addr
.offset
.imm
= 0;
3861 operand
->addr
.preind
= 1;
3866 set_syntax_error (_("missing offset in the pre-indexed address"));
3872 operand
->addr
.preind
= 1;
3873 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3875 operand
->addr
.offset
.is_reg
= 1;
3876 operand
->addr
.offset
.regno
= REG_ZR
;
3877 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3881 inst
.reloc
.exp
.X_op
= O_constant
;
3882 inst
.reloc
.exp
.X_add_number
= 0;
3891 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3894 parse_address (char **str
, aarch64_opnd_info
*operand
)
3896 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3897 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3898 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3901 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3902 The arguments have the same meaning as for parse_address_main.
3903 Return TRUE on success. */
3905 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3906 aarch64_opnd_qualifier_t
*base_qualifier
,
3907 aarch64_opnd_qualifier_t
*offset_qualifier
)
3909 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3910 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3914 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3915 Return TRUE on success; otherwise return FALSE. */
3917 parse_half (char **str
, int *internal_fixup_p
)
3921 skip_past_char (&p
, '#');
3923 gas_assert (internal_fixup_p
);
3924 *internal_fixup_p
= 0;
3928 struct reloc_table_entry
*entry
;
3930 /* Try to parse a relocation. Anything else is an error. */
3933 if (!(entry
= find_reloc_table_entry (&p
)))
3935 set_syntax_error (_("unknown relocation modifier"));
3939 if (entry
->movw_type
== 0)
3942 (_("this relocation modifier is not allowed on this instruction"));
3946 inst
.reloc
.type
= entry
->movw_type
;
3949 *internal_fixup_p
= 1;
3951 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3952 aarch64_force_reloc (inst
.reloc
.type
) == 1))
3959 /* Parse an operand for an ADRP instruction:
3961 Return TRUE on success; otherwise return FALSE. */
3964 parse_adrp (char **str
)
3971 struct reloc_table_entry
*entry
;
3973 /* Try to parse a relocation. Anything else is an error. */
3975 if (!(entry
= find_reloc_table_entry (&p
)))
3977 set_syntax_error (_("unknown relocation modifier"));
3981 if (entry
->adrp_type
== 0)
3984 (_("this relocation modifier is not allowed on this instruction"));
3988 inst
.reloc
.type
= entry
->adrp_type
;
3991 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3993 inst
.reloc
.pc_rel
= 1;
3994 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3995 aarch64_force_reloc (inst
.reloc
.type
) == 1))
4001 /* Miscellaneous. */
4003 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4004 of SIZE tokens in which index I gives the token for field value I,
4005 or is null if field value I is invalid. REG_TYPE says which register
4006 names should be treated as registers rather than as symbolic immediates.
4008 Return true on success, moving *STR past the operand and storing the
4009 field value in *VAL. */
4012 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4013 size_t size
, aarch64_reg_type reg_type
)
4019 /* Match C-like tokens. */
4021 while (ISALNUM (*q
))
4024 for (i
= 0; i
< size
; ++i
)
4026 && strncasecmp (array
[i
], p
, q
- p
) == 0
4027 && array
[i
][q
- p
] == 0)
4034 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4037 if (exp
.X_op
== O_constant
4038 && (uint64_t) exp
.X_add_number
< size
)
4040 *val
= exp
.X_add_number
;
4045 /* Use the default error for this operand. */
4049 /* Parse an option for a preload instruction. Returns the encoding for the
4050 option, or PARSE_FAIL. */
4053 parse_pldop (char **str
)
4056 const struct aarch64_name_value_pair
*o
;
4059 while (ISALNUM (*q
))
4062 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4070 /* Parse an option for a barrier instruction. Returns the encoding for the
4071 option, or PARSE_FAIL. */
4074 parse_barrier (char **str
)
4077 const struct aarch64_name_value_pair
*o
;
4080 while (ISALPHA (*q
))
4083 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4091 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4092 return 0 if successful. Otherwise return PARSE_FAIL. */
4095 parse_barrier_psb (char **str
,
4096 const struct aarch64_name_value_pair
** hint_opt
)
4099 const struct aarch64_name_value_pair
*o
;
4102 while (ISALPHA (*q
))
4105 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4108 set_fatal_syntax_error
4109 ( _("unknown or missing option to PSB/TSB"));
4113 if (o
->value
!= 0x11)
4115 /* PSB only accepts option name 'CSYNC'. */
4117 (_("the specified option is not accepted for PSB/TSB"));
4126 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4127 return 0 if successful. Otherwise return PARSE_FAIL. */
4130 parse_bti_operand (char **str
,
4131 const struct aarch64_name_value_pair
** hint_opt
)
4134 const struct aarch64_name_value_pair
*o
;
4137 while (ISALPHA (*q
))
4140 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4143 set_fatal_syntax_error
4144 ( _("unknown option to BTI"));
4150 /* Valid BTI operands. */
4158 (_("unknown option to BTI"));
4167 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4168 Returns the encoding for the option, or PARSE_FAIL.
4170 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4171 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4173 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4174 field, otherwise as a system register.
4178 parse_sys_reg (char **str
, htab_t sys_regs
,
4179 int imple_defined_p
, int pstatefield_p
,
4183 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4184 const aarch64_sys_reg
*o
;
4188 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4189 if (p
< buf
+ (sizeof (buf
) - 1))
4190 *p
++ = TOLOWER (*q
);
4193 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4194 valid system register. This is enforced by construction of the hash
4196 if (p
- buf
!= q
- *str
)
4199 o
= str_hash_find (sys_regs
, buf
);
4202 if (!imple_defined_p
)
4206 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4207 unsigned int op0
, op1
, cn
, cm
, op2
;
4209 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4212 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4214 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4221 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4222 as_bad (_("selected processor does not support PSTATE field "
4225 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4226 o
->value
, o
->flags
, o
->features
))
4227 as_bad (_("selected processor does not support system register "
4229 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4230 as_warn (_("system register name '%s' is deprecated and may be "
4231 "removed in a future release"), buf
);
4241 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4242 for the option, or NULL. */
4244 static const aarch64_sys_ins_reg
*
4245 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4248 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4249 const aarch64_sys_ins_reg
*o
;
4252 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4253 if (p
< buf
+ (sizeof (buf
) - 1))
4254 *p
++ = TOLOWER (*q
);
4257 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4258 valid system register. This is enforced by construction of the hash
4260 if (p
- buf
!= q
- *str
)
4263 o
= str_hash_find (sys_ins_regs
, buf
);
4267 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4268 o
->name
, o
->value
, o
->flags
, 0))
4269 as_bad (_("selected processor does not support system register "
4271 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4272 as_warn (_("system register name '%s' is deprecated and may be "
4273 "removed in a future release"), buf
);
4279 #define po_char_or_fail(chr) do { \
4280 if (! skip_past_char (&str, chr)) \
4284 #define po_reg_or_fail(regtype) do { \
4285 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4286 if (val == PARSE_FAIL) \
4288 set_default_error (); \
4293 #define po_int_reg_or_fail(reg_type) do { \
4294 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4295 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4297 set_default_error (); \
4300 info->reg.regno = reg->number; \
4301 info->qualifier = qualifier; \
4304 #define po_imm_nc_or_fail() do { \
4305 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4309 #define po_imm_or_fail(min, max) do { \
4310 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4312 if (val < min || val > max) \
4314 set_fatal_syntax_error (_("immediate value out of range "\
4315 #min " to "#max)); \
4320 #define po_enum_or_fail(array) do { \
4321 if (!parse_enum_string (&str, &val, array, \
4322 ARRAY_SIZE (array), imm_reg_type)) \
4326 #define po_misc_or_fail(expr) do { \
4331 /* encode the 12-bit imm field of Add/sub immediate */
4332 static inline uint32_t
4333 encode_addsub_imm (uint32_t imm
)
4338 /* encode the shift amount field of Add/sub immediate */
4339 static inline uint32_t
4340 encode_addsub_imm_shift_amount (uint32_t cnt
)
4346 /* encode the imm field of Adr instruction */
4347 static inline uint32_t
4348 encode_adr_imm (uint32_t imm
)
4350 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4351 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4354 /* encode the immediate field of Move wide immediate */
4355 static inline uint32_t
4356 encode_movw_imm (uint32_t imm
)
4361 /* encode the 26-bit offset of unconditional branch */
4362 static inline uint32_t
4363 encode_branch_ofs_26 (uint32_t ofs
)
4365 return ofs
& ((1 << 26) - 1);
4368 /* encode the 19-bit offset of conditional branch and compare & branch */
4369 static inline uint32_t
4370 encode_cond_branch_ofs_19 (uint32_t ofs
)
4372 return (ofs
& ((1 << 19) - 1)) << 5;
4375 /* encode the 19-bit offset of ld literal */
4376 static inline uint32_t
4377 encode_ld_lit_ofs_19 (uint32_t ofs
)
4379 return (ofs
& ((1 << 19) - 1)) << 5;
4382 /* Encode the 14-bit offset of test & branch. */
4383 static inline uint32_t
4384 encode_tst_branch_ofs_14 (uint32_t ofs
)
4386 return (ofs
& ((1 << 14) - 1)) << 5;
4389 /* Encode the 16-bit imm field of svc/hvc/smc. */
4390 static inline uint32_t
4391 encode_svc_imm (uint32_t imm
)
4396 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4397 static inline uint32_t
4398 reencode_addsub_switch_add_sub (uint32_t opcode
)
4400 return opcode
^ (1 << 30);
4403 static inline uint32_t
4404 reencode_movzn_to_movz (uint32_t opcode
)
4406 return opcode
| (1 << 30);
4409 static inline uint32_t
4410 reencode_movzn_to_movn (uint32_t opcode
)
4412 return opcode
& ~(1 << 30);
4415 /* Overall per-instruction processing. */
4417 /* We need to be able to fix up arbitrary expressions in some statements.
4418 This is so that we can handle symbols that are an arbitrary distance from
4419 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4420 which returns part of an address in a form which will be valid for
4421 a data instruction. We do this by pushing the expression into a symbol
4422 in the expr_section, and creating a fix for that. */
4425 fix_new_aarch64 (fragS
* frag
,
4440 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4444 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4451 /* Diagnostics on operands errors. */
4453 /* By default, output verbose error message.
4454 Disable the verbose error message by -mno-verbose-error. */
4455 static int verbose_error_p
= 1;
4457 #ifdef DEBUG_AARCH64
4458 /* N.B. this is only for the purpose of debugging. */
4459 const char* operand_mismatch_kind_names
[] =
4462 "AARCH64_OPDE_RECOVERABLE",
4463 "AARCH64_OPDE_SYNTAX_ERROR",
4464 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4465 "AARCH64_OPDE_INVALID_VARIANT",
4466 "AARCH64_OPDE_OUT_OF_RANGE",
4467 "AARCH64_OPDE_UNALIGNED",
4468 "AARCH64_OPDE_REG_LIST",
4469 "AARCH64_OPDE_OTHER_ERROR",
4471 #endif /* DEBUG_AARCH64 */
4473 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4475 When multiple errors of different kinds are found in the same assembly
4476 line, only the error of the highest severity will be picked up for
4477 issuing the diagnostics. */
4480 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4481 enum aarch64_operand_error_kind rhs
)
4483 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4484 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4485 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4486 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4487 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4488 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4489 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4490 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4494 /* Helper routine to get the mnemonic name from the assembly instruction
4495 line; should only be called for the diagnosis purpose, as there is
4496 string copy operation involved, which may affect the runtime
4497 performance if used in elsewhere. */
4500 get_mnemonic_name (const char *str
)
4502 static char mnemonic
[32];
4505 /* Get the first 15 bytes and assume that the full name is included. */
4506 strncpy (mnemonic
, str
, 31);
4507 mnemonic
[31] = '\0';
4509 /* Scan up to the end of the mnemonic, which must end in white space,
4510 '.', or end of string. */
4511 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4516 /* Append '...' to the truncated long name. */
4517 if (ptr
- mnemonic
== 31)
4518 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4524 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4526 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4527 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4530 /* Data structures storing one user error in the assembly code related to
4533 struct operand_error_record
4535 const aarch64_opcode
*opcode
;
4536 aarch64_operand_error detail
;
4537 struct operand_error_record
*next
;
4540 typedef struct operand_error_record operand_error_record
;
4542 struct operand_errors
4544 operand_error_record
*head
;
4545 operand_error_record
*tail
;
4548 typedef struct operand_errors operand_errors
;
4550 /* Top-level data structure reporting user errors for the current line of
4552 The way md_assemble works is that all opcodes sharing the same mnemonic
4553 name are iterated to find a match to the assembly line. In this data
4554 structure, each of the such opcodes will have one operand_error_record
4555 allocated and inserted. In other words, excessive errors related with
4556 a single opcode are disregarded. */
4557 operand_errors operand_error_report
;
4559 /* Free record nodes. */
4560 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4562 /* Initialize the data structure that stores the operand mismatch
4563 information on assembling one line of the assembly code. */
4565 init_operand_error_report (void)
4567 if (operand_error_report
.head
!= NULL
)
4569 gas_assert (operand_error_report
.tail
!= NULL
);
4570 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4571 free_opnd_error_record_nodes
= operand_error_report
.head
;
4572 operand_error_report
.head
= NULL
;
4573 operand_error_report
.tail
= NULL
;
4576 gas_assert (operand_error_report
.tail
== NULL
);
4579 /* Return TRUE if some operand error has been recorded during the
4580 parsing of the current assembly line using the opcode *OPCODE;
4581 otherwise return FALSE. */
4583 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4585 operand_error_record
*record
= operand_error_report
.head
;
4586 return record
&& record
->opcode
== opcode
;
4589 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4590 OPCODE field is initialized with OPCODE.
4591 N.B. only one record for each opcode, i.e. the maximum of one error is
4592 recorded for each instruction template. */
4595 add_operand_error_record (const operand_error_record
* new_record
)
4597 const aarch64_opcode
*opcode
= new_record
->opcode
;
4598 operand_error_record
* record
= operand_error_report
.head
;
4600 /* The record may have been created for this opcode. If not, we need
4602 if (! opcode_has_operand_error_p (opcode
))
4604 /* Get one empty record. */
4605 if (free_opnd_error_record_nodes
== NULL
)
4607 record
= XNEW (operand_error_record
);
4611 record
= free_opnd_error_record_nodes
;
4612 free_opnd_error_record_nodes
= record
->next
;
4614 record
->opcode
= opcode
;
4615 /* Insert at the head. */
4616 record
->next
= operand_error_report
.head
;
4617 operand_error_report
.head
= record
;
4618 if (operand_error_report
.tail
== NULL
)
4619 operand_error_report
.tail
= record
;
4621 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4622 && record
->detail
.index
<= new_record
->detail
.index
4623 && operand_error_higher_severity_p (record
->detail
.kind
,
4624 new_record
->detail
.kind
))
4626 /* In the case of multiple errors found on operands related with a
4627 single opcode, only record the error of the leftmost operand and
4628 only if the error is of higher severity. */
4629 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4630 " the existing error %s on operand %d",
4631 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4632 new_record
->detail
.index
,
4633 operand_mismatch_kind_names
[record
->detail
.kind
],
4634 record
->detail
.index
);
4638 record
->detail
= new_record
->detail
;
4642 record_operand_error_info (const aarch64_opcode
*opcode
,
4643 aarch64_operand_error
*error_info
)
4645 operand_error_record record
;
4646 record
.opcode
= opcode
;
4647 record
.detail
= *error_info
;
4648 add_operand_error_record (&record
);
4651 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4652 error message *ERROR, for operand IDX (count from 0). */
4655 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4656 enum aarch64_operand_error_kind kind
,
4659 aarch64_operand_error info
;
4660 memset(&info
, 0, sizeof (info
));
4664 info
.non_fatal
= false;
4665 record_operand_error_info (opcode
, &info
);
4669 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4670 enum aarch64_operand_error_kind kind
,
4671 const char* error
, const int *extra_data
)
4673 aarch64_operand_error info
;
4677 info
.data
[0] = extra_data
[0];
4678 info
.data
[1] = extra_data
[1];
4679 info
.data
[2] = extra_data
[2];
4680 info
.non_fatal
= false;
4681 record_operand_error_info (opcode
, &info
);
4685 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4686 const char* error
, int lower_bound
,
4689 int data
[3] = {lower_bound
, upper_bound
, 0};
4690 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4694 /* Remove the operand error record for *OPCODE. */
4695 static void ATTRIBUTE_UNUSED
4696 remove_operand_error_record (const aarch64_opcode
*opcode
)
4698 if (opcode_has_operand_error_p (opcode
))
4700 operand_error_record
* record
= operand_error_report
.head
;
4701 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4702 operand_error_report
.head
= record
->next
;
4703 record
->next
= free_opnd_error_record_nodes
;
4704 free_opnd_error_record_nodes
= record
;
4705 if (operand_error_report
.head
== NULL
)
4707 gas_assert (operand_error_report
.tail
== record
);
4708 operand_error_report
.tail
= NULL
;
4713 /* Given the instruction in *INSTR, return the index of the best matched
4714 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4716 Return -1 if there is no qualifier sequence; return the first match
4717 if there is multiple matches found. */
4720 find_best_match (const aarch64_inst
*instr
,
4721 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4723 int i
, num_opnds
, max_num_matched
, idx
;
4725 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4728 DEBUG_TRACE ("no operand");
4732 max_num_matched
= 0;
4735 /* For each pattern. */
4736 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4739 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4741 /* Most opcodes has much fewer patterns in the list. */
4742 if (empty_qualifier_sequence_p (qualifiers
))
4744 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4748 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4749 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4752 if (num_matched
> max_num_matched
)
4754 max_num_matched
= num_matched
;
4759 DEBUG_TRACE ("return with %d", idx
);
4763 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4764 corresponding operands in *INSTR. */
4767 assign_qualifier_sequence (aarch64_inst
*instr
,
4768 const aarch64_opnd_qualifier_t
*qualifiers
)
4771 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4772 gas_assert (num_opnds
);
4773 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4774 instr
->operands
[i
].qualifier
= *qualifiers
;
4777 /* Print operands for the diagnosis purpose. */
4780 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4781 const aarch64_opnd_info
*opnds
)
4785 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4789 /* We regard the opcode operand info more, however we also look into
4790 the inst->operands to support the disassembling of the optional
4792 The two operand code should be the same in all cases, apart from
4793 when the operand can be optional. */
4794 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4795 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4798 /* Generate the operand string in STR. */
4799 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4804 strcat (buf
, i
== 0 ? " " : ", ");
4806 /* Append the operand string. */
4811 /* Send to stderr a string as information. */
4814 output_info (const char *format
, ...)
4820 file
= as_where (&line
);
4824 fprintf (stderr
, "%s:%u: ", file
, line
);
4826 fprintf (stderr
, "%s: ", file
);
4828 fprintf (stderr
, _("Info: "));
4829 va_start (args
, format
);
4830 vfprintf (stderr
, format
, args
);
4832 (void) putc ('\n', stderr
);
4835 /* Output one operand error record. */
4838 output_operand_error_record (const operand_error_record
*record
, char *str
)
4840 const aarch64_operand_error
*detail
= &record
->detail
;
4841 int idx
= detail
->index
;
4842 const aarch64_opcode
*opcode
= record
->opcode
;
4843 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4844 : AARCH64_OPND_NIL
);
4846 typedef void (*handler_t
)(const char *format
, ...);
4847 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4849 switch (detail
->kind
)
4851 case AARCH64_OPDE_NIL
:
4854 case AARCH64_OPDE_SYNTAX_ERROR
:
4855 case AARCH64_OPDE_RECOVERABLE
:
4856 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4857 case AARCH64_OPDE_OTHER_ERROR
:
4858 /* Use the prepared error message if there is, otherwise use the
4859 operand description string to describe the error. */
4860 if (detail
->error
!= NULL
)
4863 handler (_("%s -- `%s'"), detail
->error
, str
);
4865 handler (_("%s at operand %d -- `%s'"),
4866 detail
->error
, idx
+ 1, str
);
4870 gas_assert (idx
>= 0);
4871 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4872 aarch64_get_operand_desc (opd_code
), str
);
4876 case AARCH64_OPDE_INVALID_VARIANT
:
4877 handler (_("operand mismatch -- `%s'"), str
);
4878 if (verbose_error_p
)
4880 /* We will try to correct the erroneous instruction and also provide
4881 more information e.g. all other valid variants.
4883 The string representation of the corrected instruction and other
4884 valid variants are generated by
4886 1) obtaining the intermediate representation of the erroneous
4888 2) manipulating the IR, e.g. replacing the operand qualifier;
4889 3) printing out the instruction by calling the printer functions
4890 shared with the disassembler.
4892 The limitation of this method is that the exact input assembly
4893 line cannot be accurately reproduced in some cases, for example an
4894 optional operand present in the actual assembly line will be
4895 omitted in the output; likewise for the optional syntax rules,
4896 e.g. the # before the immediate. Another limitation is that the
4897 assembly symbols and relocation operations in the assembly line
4898 currently cannot be printed out in the error report. Last but not
4899 least, when there is other error(s) co-exist with this error, the
4900 'corrected' instruction may be still incorrect, e.g. given
4901 'ldnp h0,h1,[x0,#6]!'
4902 this diagnosis will provide the version:
4903 'ldnp s0,s1,[x0,#6]!'
4904 which is still not right. */
4905 size_t len
= strlen (get_mnemonic_name (str
));
4909 aarch64_inst
*inst_base
= &inst
.base
;
4910 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4913 reset_aarch64_instruction (&inst
);
4914 inst_base
->opcode
= opcode
;
4916 /* Reset the error report so that there is no side effect on the
4917 following operand parsing. */
4918 init_operand_error_report ();
4921 result
= parse_operands (str
+ len
, opcode
)
4922 && programmer_friendly_fixup (&inst
);
4923 gas_assert (result
);
4924 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4925 NULL
, NULL
, insn_sequence
);
4926 gas_assert (!result
);
4928 /* Find the most matched qualifier sequence. */
4929 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4930 gas_assert (qlf_idx
> -1);
4932 /* Assign the qualifiers. */
4933 assign_qualifier_sequence (inst_base
,
4934 opcode
->qualifiers_list
[qlf_idx
]);
4936 /* Print the hint. */
4937 output_info (_(" did you mean this?"));
4938 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4939 print_operands (buf
, opcode
, inst_base
->operands
);
4940 output_info (_(" %s"), buf
);
4942 /* Print out other variant(s) if there is any. */
4944 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4945 output_info (_(" other valid variant(s):"));
4947 /* For each pattern. */
4948 qualifiers_list
= opcode
->qualifiers_list
;
4949 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4951 /* Most opcodes has much fewer patterns in the list.
4952 First NIL qualifier indicates the end in the list. */
4953 if (empty_qualifier_sequence_p (*qualifiers_list
))
4958 /* Mnemonics name. */
4959 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4961 /* Assign the qualifiers. */
4962 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4964 /* Print instruction. */
4965 print_operands (buf
, opcode
, inst_base
->operands
);
4967 output_info (_(" %s"), buf
);
4973 case AARCH64_OPDE_UNTIED_OPERAND
:
4974 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4975 detail
->index
+ 1, str
);
4978 case AARCH64_OPDE_OUT_OF_RANGE
:
4979 if (detail
->data
[0] != detail
->data
[1])
4980 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4981 detail
->error
? detail
->error
: _("immediate value"),
4982 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4984 handler (_("%s must be %d at operand %d -- `%s'"),
4985 detail
->error
? detail
->error
: _("immediate value"),
4986 detail
->data
[0], idx
+ 1, str
);
4989 case AARCH64_OPDE_REG_LIST
:
4990 if (detail
->data
[0] == 1)
4991 handler (_("invalid number of registers in the list; "
4992 "only 1 register is expected at operand %d -- `%s'"),
4995 handler (_("invalid number of registers in the list; "
4996 "%d registers are expected at operand %d -- `%s'"),
4997 detail
->data
[0], idx
+ 1, str
);
5000 case AARCH64_OPDE_UNALIGNED
:
5001 handler (_("immediate value must be a multiple of "
5002 "%d at operand %d -- `%s'"),
5003 detail
->data
[0], idx
+ 1, str
);
5012 /* Process and output the error message about the operand mismatching.
5014 When this function is called, the operand error information had
5015 been collected for an assembly line and there will be multiple
5016 errors in the case of multiple instruction templates; output the
5017 error message that most closely describes the problem.
5019 The errors to be printed can be filtered on printing all errors
5020 or only non-fatal errors. This distinction has to be made because
5021 the error buffer may already be filled with fatal errors we don't want to
5022 print due to the different instruction templates. */
5025 output_operand_error_report (char *str
, bool non_fatal_only
)
5027 int largest_error_pos
;
5028 const char *msg
= NULL
;
5029 enum aarch64_operand_error_kind kind
;
5030 operand_error_record
*curr
;
5031 operand_error_record
*head
= operand_error_report
.head
;
5032 operand_error_record
*record
= NULL
;
5034 /* No error to report. */
5038 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5040 /* Only one error. */
5041 if (head
== operand_error_report
.tail
)
5043 /* If the only error is a non-fatal one and we don't want to print it,
5045 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5047 DEBUG_TRACE ("single opcode entry with error kind: %s",
5048 operand_mismatch_kind_names
[head
->detail
.kind
]);
5049 output_operand_error_record (head
, str
);
5054 /* Find the error kind of the highest severity. */
5055 DEBUG_TRACE ("multiple opcode entries with error kind");
5056 kind
= AARCH64_OPDE_NIL
;
5057 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5059 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5060 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5061 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5062 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5063 kind
= curr
->detail
.kind
;
5066 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5068 /* Pick up one of errors of KIND to report. */
5069 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5070 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5072 /* If we don't want to print non-fatal errors then don't consider them
5074 if (curr
->detail
.kind
!= kind
5075 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5077 /* If there are multiple errors, pick up the one with the highest
5078 mismatching operand index. In the case of multiple errors with
5079 the equally highest operand index, pick up the first one or the
5080 first one with non-NULL error message. */
5081 if (curr
->detail
.index
> largest_error_pos
5082 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5083 && curr
->detail
.error
!= NULL
))
5085 largest_error_pos
= curr
->detail
.index
;
5087 msg
= record
->detail
.error
;
5091 /* The way errors are collected in the back-end is a bit non-intuitive. But
5092 essentially, because each operand template is tried recursively you may
5093 always have errors collected from the previous tried OPND. These are
5094 usually skipped if there is one successful match. However now with the
5095 non-fatal errors we have to ignore those previously collected hard errors
5096 when we're only interested in printing the non-fatal ones. This condition
5097 prevents us from printing errors that are not appropriate, since we did
5098 match a condition, but it also has warnings that it wants to print. */
5099 if (non_fatal_only
&& !record
)
5102 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5103 DEBUG_TRACE ("Pick up error kind %s to report",
5104 operand_mismatch_kind_names
[record
->detail
.kind
]);
5107 output_operand_error_record (record
, str
);
5110 /* Write an AARCH64 instruction to buf - always little-endian. */
5112 put_aarch64_insn (char *buf
, uint32_t insn
)
5114 unsigned char *where
= (unsigned char *) buf
;
5116 where
[1] = insn
>> 8;
5117 where
[2] = insn
>> 16;
5118 where
[3] = insn
>> 24;
5122 get_aarch64_insn (char *buf
)
5124 unsigned char *where
= (unsigned char *) buf
;
5126 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5127 | ((uint32_t) where
[3] << 24)));
5132 output_inst (struct aarch64_inst
*new_inst
)
5136 to
= frag_more (INSN_SIZE
);
5138 frag_now
->tc_frag_data
.recorded
= 1;
5140 put_aarch64_insn (to
, inst
.base
.value
);
5142 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5144 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5145 INSN_SIZE
, &inst
.reloc
.exp
,
5148 DEBUG_TRACE ("Prepared relocation fix up");
5149 /* Don't check the addend value against the instruction size,
5150 that's the job of our code in md_apply_fix(). */
5151 fixp
->fx_no_overflow
= 1;
5152 if (new_inst
!= NULL
)
5153 fixp
->tc_fix_data
.inst
= new_inst
;
5154 if (aarch64_gas_internal_fixup_p ())
5156 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5157 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5158 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5162 dwarf2_emit_insn (INSN_SIZE
);
5165 /* Link together opcodes of the same name. */
5169 const aarch64_opcode
*opcode
;
5170 struct templates
*next
;
5173 typedef struct templates templates
;
5176 lookup_mnemonic (const char *start
, int len
)
5178 templates
*templ
= NULL
;
5180 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5184 /* Subroutine of md_assemble, responsible for looking up the primary
5185 opcode from the mnemonic the user wrote. STR points to the
5186 beginning of the mnemonic. */
5189 opcode_lookup (char **str
)
5191 char *end
, *base
, *dot
;
5192 const aarch64_cond
*cond
;
5196 /* Scan up to the end of the mnemonic, which must end in white space,
5197 '.', or end of string. */
5199 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5200 if (*end
== '.' && !dot
)
5203 if (end
== base
|| dot
== base
)
5206 inst
.cond
= COND_ALWAYS
;
5208 /* Handle a possible condition. */
5211 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5214 inst
.cond
= cond
->value
;
5230 if (inst
.cond
== COND_ALWAYS
)
5232 /* Look for unaffixed mnemonic. */
5233 return lookup_mnemonic (base
, len
);
5237 /* append ".c" to mnemonic if conditional */
5238 memcpy (condname
, base
, len
);
5239 memcpy (condname
+ len
, ".c", 2);
5242 return lookup_mnemonic (base
, len
);
5248 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5249 to a corresponding operand qualifier. */
5251 static inline aarch64_opnd_qualifier_t
5252 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5254 /* Element size in bytes indexed by vector_el_type. */
5255 const unsigned char ele_size
[5]
5257 const unsigned int ele_base
[5] =
5259 AARCH64_OPND_QLF_V_4B
,
5260 AARCH64_OPND_QLF_V_2H
,
5261 AARCH64_OPND_QLF_V_2S
,
5262 AARCH64_OPND_QLF_V_1D
,
5263 AARCH64_OPND_QLF_V_1Q
5266 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5267 goto vectype_conversion_fail
;
5269 if (vectype
->type
== NT_zero
)
5270 return AARCH64_OPND_QLF_P_Z
;
5271 if (vectype
->type
== NT_merge
)
5272 return AARCH64_OPND_QLF_P_M
;
5274 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5276 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5278 /* Special case S_4B. */
5279 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5280 return AARCH64_OPND_QLF_S_4B
;
5282 /* Special case S_2H. */
5283 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5284 return AARCH64_OPND_QLF_S_2H
;
5286 /* Vector element register. */
5287 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5291 /* Vector register. */
5292 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5295 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5296 goto vectype_conversion_fail
;
5298 /* The conversion is by calculating the offset from the base operand
5299 qualifier for the vector type. The operand qualifiers are regular
5300 enough that the offset can established by shifting the vector width by
5301 a vector-type dependent amount. */
5303 if (vectype
->type
== NT_b
)
5305 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5307 else if (vectype
->type
>= NT_d
)
5312 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5313 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5314 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5318 vectype_conversion_fail
:
5319 first_error (_("bad vector arrangement type"));
5320 return AARCH64_OPND_QLF_NIL
;
5323 /* Process an optional operand that is found omitted from the assembly line.
5324 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5325 instruction's opcode entry while IDX is the index of this omitted operand.
5329 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5330 int idx
, aarch64_opnd_info
*operand
)
5332 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5333 gas_assert (optional_operand_p (opcode
, idx
));
5334 gas_assert (!operand
->present
);
5338 case AARCH64_OPND_Rd
:
5339 case AARCH64_OPND_Rn
:
5340 case AARCH64_OPND_Rm
:
5341 case AARCH64_OPND_Rt
:
5342 case AARCH64_OPND_Rt2
:
5343 case AARCH64_OPND_Rt_LS64
:
5344 case AARCH64_OPND_Rt_SP
:
5345 case AARCH64_OPND_Rs
:
5346 case AARCH64_OPND_Ra
:
5347 case AARCH64_OPND_Rt_SYS
:
5348 case AARCH64_OPND_Rd_SP
:
5349 case AARCH64_OPND_Rn_SP
:
5350 case AARCH64_OPND_Rm_SP
:
5351 case AARCH64_OPND_Fd
:
5352 case AARCH64_OPND_Fn
:
5353 case AARCH64_OPND_Fm
:
5354 case AARCH64_OPND_Fa
:
5355 case AARCH64_OPND_Ft
:
5356 case AARCH64_OPND_Ft2
:
5357 case AARCH64_OPND_Sd
:
5358 case AARCH64_OPND_Sn
:
5359 case AARCH64_OPND_Sm
:
5360 case AARCH64_OPND_Va
:
5361 case AARCH64_OPND_Vd
:
5362 case AARCH64_OPND_Vn
:
5363 case AARCH64_OPND_Vm
:
5364 case AARCH64_OPND_VdD1
:
5365 case AARCH64_OPND_VnD1
:
5366 operand
->reg
.regno
= default_value
;
5369 case AARCH64_OPND_Ed
:
5370 case AARCH64_OPND_En
:
5371 case AARCH64_OPND_Em
:
5372 case AARCH64_OPND_Em16
:
5373 case AARCH64_OPND_SM3_IMM2
:
5374 operand
->reglane
.regno
= default_value
;
5377 case AARCH64_OPND_IDX
:
5378 case AARCH64_OPND_BIT_NUM
:
5379 case AARCH64_OPND_IMMR
:
5380 case AARCH64_OPND_IMMS
:
5381 case AARCH64_OPND_SHLL_IMM
:
5382 case AARCH64_OPND_IMM_VLSL
:
5383 case AARCH64_OPND_IMM_VLSR
:
5384 case AARCH64_OPND_CCMP_IMM
:
5385 case AARCH64_OPND_FBITS
:
5386 case AARCH64_OPND_UIMM4
:
5387 case AARCH64_OPND_UIMM3_OP1
:
5388 case AARCH64_OPND_UIMM3_OP2
:
5389 case AARCH64_OPND_IMM
:
5390 case AARCH64_OPND_IMM_2
:
5391 case AARCH64_OPND_WIDTH
:
5392 case AARCH64_OPND_UIMM7
:
5393 case AARCH64_OPND_NZCV
:
5394 case AARCH64_OPND_SVE_PATTERN
:
5395 case AARCH64_OPND_SVE_PRFOP
:
5396 operand
->imm
.value
= default_value
;
5399 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5400 operand
->imm
.value
= default_value
;
5401 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5402 operand
->shifter
.amount
= 1;
5405 case AARCH64_OPND_EXCEPTION
:
5406 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5409 case AARCH64_OPND_BARRIER_ISB
:
5410 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5413 case AARCH64_OPND_BTI_TARGET
:
5414 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5422 /* Process the relocation type for move wide instructions.
5423 Return TRUE on success; otherwise return FALSE. */
5426 process_movw_reloc_info (void)
5431 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5433 if (inst
.base
.opcode
->op
== OP_MOVK
)
5434 switch (inst
.reloc
.type
)
5436 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5437 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5438 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5439 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5440 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5441 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5442 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5443 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5444 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5445 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5446 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5448 (_("the specified relocation type is not allowed for MOVK"));
5454 switch (inst
.reloc
.type
)
5456 case BFD_RELOC_AARCH64_MOVW_G0
:
5457 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5458 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5459 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5460 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5461 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5462 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5463 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5464 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5465 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5466 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5467 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5468 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5471 case BFD_RELOC_AARCH64_MOVW_G1
:
5472 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5473 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5474 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5475 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5476 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5477 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5478 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5479 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5480 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5481 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5482 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5483 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5486 case BFD_RELOC_AARCH64_MOVW_G2
:
5487 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5488 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5489 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5490 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5491 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5492 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5495 set_fatal_syntax_error
5496 (_("the specified relocation type is not allowed for 32-bit "
5502 case BFD_RELOC_AARCH64_MOVW_G3
:
5503 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5506 set_fatal_syntax_error
5507 (_("the specified relocation type is not allowed for 32-bit "
5514 /* More cases should be added when more MOVW-related relocation types
5515 are supported in GAS. */
5516 gas_assert (aarch64_gas_internal_fixup_p ());
5517 /* The shift amount should have already been set by the parser. */
5520 inst
.base
.operands
[1].shifter
.amount
= shift
;
5524 /* A primitive log calculator. */
5526 static inline unsigned int
5527 get_logsz (unsigned int size
)
5529 const unsigned char ls
[16] =
5530 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5536 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5537 return ls
[size
- 1];
5540 /* Determine and return the real reloc type code for an instruction
5541 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5543 static inline bfd_reloc_code_real_type
5544 ldst_lo12_determine_real_reloc_type (void)
5546 unsigned logsz
, max_logsz
;
5547 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5548 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5550 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5552 BFD_RELOC_AARCH64_LDST8_LO12
,
5553 BFD_RELOC_AARCH64_LDST16_LO12
,
5554 BFD_RELOC_AARCH64_LDST32_LO12
,
5555 BFD_RELOC_AARCH64_LDST64_LO12
,
5556 BFD_RELOC_AARCH64_LDST128_LO12
5559 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5560 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5561 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5562 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5563 BFD_RELOC_AARCH64_NONE
5566 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5567 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5568 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5569 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5570 BFD_RELOC_AARCH64_NONE
5573 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5574 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5575 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5576 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5577 BFD_RELOC_AARCH64_NONE
5580 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5581 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5582 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5583 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5584 BFD_RELOC_AARCH64_NONE
5588 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5589 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5591 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5593 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5595 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5596 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5598 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5600 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5602 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5604 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5606 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5607 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5608 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5609 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5614 if (logsz
> max_logsz
)
5616 /* SEE PR 27904 for an example of this. */
5617 set_fatal_syntax_error
5618 (_("relocation qualifier does not match instruction size"));
5619 return BFD_RELOC_AARCH64_NONE
;
5622 /* In reloc.c, these pseudo relocation types should be defined in similar
5623 order as above reloc_ldst_lo12 array. Because the array index calculation
5624 below relies on this. */
5625 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5628 /* Check whether a register list REGINFO is valid. The registers must be
5629 numbered in increasing order (modulo 32), in increments of one or two.
5631 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5634 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5637 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5639 uint32_t i
, nb_regs
, prev_regno
, incr
;
5641 nb_regs
= 1 + (reginfo
& 0x3);
5643 prev_regno
= reginfo
& 0x1f;
5644 incr
= accept_alternate
? 2 : 1;
5646 for (i
= 1; i
< nb_regs
; ++i
)
5648 uint32_t curr_regno
;
5650 curr_regno
= reginfo
& 0x1f;
5651 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5653 prev_regno
= curr_regno
;
5659 /* Generic instruction operand parser. This does no encoding and no
5660 semantic validation; it merely squirrels values away in the inst
5661 structure. Returns TRUE or FALSE depending on whether the
5662 specified grammar matched. */
5665 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5668 char *backtrack_pos
= 0;
5669 const enum aarch64_opnd
*operands
= opcode
->operands
;
5670 aarch64_reg_type imm_reg_type
;
5673 skip_whitespace (str
);
5675 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5676 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5678 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5680 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5683 const reg_entry
*reg
;
5684 int comma_skipped_p
= 0;
5685 aarch64_reg_type rtype
;
5686 struct vector_type_el vectype
;
5687 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5688 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5689 aarch64_reg_type reg_type
;
5691 DEBUG_TRACE ("parse operand %d", i
);
5693 /* Assign the operand code. */
5694 info
->type
= operands
[i
];
5696 if (optional_operand_p (opcode
, i
))
5698 /* Remember where we are in case we need to backtrack. */
5699 gas_assert (!backtrack_pos
);
5700 backtrack_pos
= str
;
5703 /* Expect comma between operands; the backtrack mechanism will take
5704 care of cases of omitted optional operand. */
5705 if (i
> 0 && ! skip_past_char (&str
, ','))
5707 set_syntax_error (_("comma expected between operands"));
5711 comma_skipped_p
= 1;
5713 switch (operands
[i
])
5715 case AARCH64_OPND_Rd
:
5716 case AARCH64_OPND_Rn
:
5717 case AARCH64_OPND_Rm
:
5718 case AARCH64_OPND_Rt
:
5719 case AARCH64_OPND_Rt2
:
5720 case AARCH64_OPND_Rs
:
5721 case AARCH64_OPND_Ra
:
5722 case AARCH64_OPND_Rt_LS64
:
5723 case AARCH64_OPND_Rt_SYS
:
5724 case AARCH64_OPND_PAIRREG
:
5725 case AARCH64_OPND_SVE_Rm
:
5726 po_int_reg_or_fail (REG_TYPE_R_Z
);
5728 /* In LS64 load/store instructions Rt register number must be even
5730 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
5732 /* We've already checked if this is valid register.
5733 This will check if register number (Rt) is not undefined for LS64
5735 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
5736 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
5738 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
5744 case AARCH64_OPND_Rd_SP
:
5745 case AARCH64_OPND_Rn_SP
:
5746 case AARCH64_OPND_Rt_SP
:
5747 case AARCH64_OPND_SVE_Rn_SP
:
5748 case AARCH64_OPND_Rm_SP
:
5749 po_int_reg_or_fail (REG_TYPE_R_SP
);
5752 case AARCH64_OPND_Rm_EXT
:
5753 case AARCH64_OPND_Rm_SFT
:
5754 po_misc_or_fail (parse_shifter_operand
5755 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5757 : SHIFTED_LOGIC_IMM
)));
5758 if (!info
->shifter
.operator_present
)
5760 /* Default to LSL if not present. Libopcodes prefers shifter
5761 kind to be explicit. */
5762 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5763 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5764 /* For Rm_EXT, libopcodes will carry out further check on whether
5765 or not stack pointer is used in the instruction (Recall that
5766 "the extend operator is not optional unless at least one of
5767 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5771 case AARCH64_OPND_Fd
:
5772 case AARCH64_OPND_Fn
:
5773 case AARCH64_OPND_Fm
:
5774 case AARCH64_OPND_Fa
:
5775 case AARCH64_OPND_Ft
:
5776 case AARCH64_OPND_Ft2
:
5777 case AARCH64_OPND_Sd
:
5778 case AARCH64_OPND_Sn
:
5779 case AARCH64_OPND_Sm
:
5780 case AARCH64_OPND_SVE_VZn
:
5781 case AARCH64_OPND_SVE_Vd
:
5782 case AARCH64_OPND_SVE_Vm
:
5783 case AARCH64_OPND_SVE_Vn
:
5784 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5785 if (val
== PARSE_FAIL
)
5787 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5790 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5792 info
->reg
.regno
= val
;
5793 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5796 case AARCH64_OPND_SVE_Pd
:
5797 case AARCH64_OPND_SVE_Pg3
:
5798 case AARCH64_OPND_SVE_Pg4_5
:
5799 case AARCH64_OPND_SVE_Pg4_10
:
5800 case AARCH64_OPND_SVE_Pg4_16
:
5801 case AARCH64_OPND_SVE_Pm
:
5802 case AARCH64_OPND_SVE_Pn
:
5803 case AARCH64_OPND_SVE_Pt
:
5804 reg_type
= REG_TYPE_PN
;
5807 case AARCH64_OPND_SVE_Za_5
:
5808 case AARCH64_OPND_SVE_Za_16
:
5809 case AARCH64_OPND_SVE_Zd
:
5810 case AARCH64_OPND_SVE_Zm_5
:
5811 case AARCH64_OPND_SVE_Zm_16
:
5812 case AARCH64_OPND_SVE_Zn
:
5813 case AARCH64_OPND_SVE_Zt
:
5814 reg_type
= REG_TYPE_ZN
;
5817 case AARCH64_OPND_Va
:
5818 case AARCH64_OPND_Vd
:
5819 case AARCH64_OPND_Vn
:
5820 case AARCH64_OPND_Vm
:
5821 reg_type
= REG_TYPE_VN
;
5823 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5824 if (val
== PARSE_FAIL
)
5826 first_error (_(get_reg_expected_msg (reg_type
)));
5829 if (vectype
.defined
& NTA_HASINDEX
)
5832 info
->reg
.regno
= val
;
5833 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5834 && vectype
.type
== NT_invtype
)
5835 /* Unqualified Pn and Zn registers are allowed in certain
5836 contexts. Rely on F_STRICT qualifier checking to catch
5838 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5841 info
->qualifier
= vectype_to_qualifier (&vectype
);
5842 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5847 case AARCH64_OPND_VdD1
:
5848 case AARCH64_OPND_VnD1
:
5849 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5850 if (val
== PARSE_FAIL
)
5852 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5855 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5857 set_fatal_syntax_error
5858 (_("the top half of a 128-bit FP/SIMD register is expected"));
5861 info
->reg
.regno
= val
;
5862 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5863 here; it is correct for the purpose of encoding/decoding since
5864 only the register number is explicitly encoded in the related
5865 instructions, although this appears a bit hacky. */
5866 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5869 case AARCH64_OPND_SVE_Zm3_INDEX
:
5870 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5871 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5872 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5873 case AARCH64_OPND_SVE_Zm4_INDEX
:
5874 case AARCH64_OPND_SVE_Zn_INDEX
:
5875 reg_type
= REG_TYPE_ZN
;
5876 goto vector_reg_index
;
5878 case AARCH64_OPND_Ed
:
5879 case AARCH64_OPND_En
:
5880 case AARCH64_OPND_Em
:
5881 case AARCH64_OPND_Em16
:
5882 case AARCH64_OPND_SM3_IMM2
:
5883 reg_type
= REG_TYPE_VN
;
5885 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5886 if (val
== PARSE_FAIL
)
5888 first_error (_(get_reg_expected_msg (reg_type
)));
5891 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5894 info
->reglane
.regno
= val
;
5895 info
->reglane
.index
= vectype
.index
;
5896 info
->qualifier
= vectype_to_qualifier (&vectype
);
5897 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5901 case AARCH64_OPND_SVE_ZnxN
:
5902 case AARCH64_OPND_SVE_ZtxN
:
5903 reg_type
= REG_TYPE_ZN
;
5904 goto vector_reg_list
;
5906 case AARCH64_OPND_LVn
:
5907 case AARCH64_OPND_LVt
:
5908 case AARCH64_OPND_LVt_AL
:
5909 case AARCH64_OPND_LEt
:
5910 reg_type
= REG_TYPE_VN
;
5912 if (reg_type
== REG_TYPE_ZN
5913 && get_opcode_dependent_value (opcode
) == 1
5916 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5917 if (val
== PARSE_FAIL
)
5919 first_error (_(get_reg_expected_msg (reg_type
)));
5922 info
->reglist
.first_regno
= val
;
5923 info
->reglist
.num_regs
= 1;
5927 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5928 if (val
== PARSE_FAIL
)
5931 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5933 set_fatal_syntax_error (_("invalid register list"));
5937 if (vectype
.width
!= 0 && *str
!= ',')
5939 set_fatal_syntax_error
5940 (_("expected element type rather than vector type"));
5944 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5945 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5947 if (operands
[i
] == AARCH64_OPND_LEt
)
5949 if (!(vectype
.defined
& NTA_HASINDEX
))
5951 info
->reglist
.has_index
= 1;
5952 info
->reglist
.index
= vectype
.index
;
5956 if (vectype
.defined
& NTA_HASINDEX
)
5958 if (!(vectype
.defined
& NTA_HASTYPE
))
5960 if (reg_type
== REG_TYPE_ZN
)
5961 set_fatal_syntax_error (_("missing type suffix"));
5965 info
->qualifier
= vectype_to_qualifier (&vectype
);
5966 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5970 case AARCH64_OPND_CRn
:
5971 case AARCH64_OPND_CRm
:
5973 char prefix
= *(str
++);
5974 if (prefix
!= 'c' && prefix
!= 'C')
5977 po_imm_nc_or_fail ();
5980 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5983 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5984 info
->imm
.value
= val
;
5988 case AARCH64_OPND_SHLL_IMM
:
5989 case AARCH64_OPND_IMM_VLSR
:
5990 po_imm_or_fail (1, 64);
5991 info
->imm
.value
= val
;
5994 case AARCH64_OPND_CCMP_IMM
:
5995 case AARCH64_OPND_SIMM5
:
5996 case AARCH64_OPND_FBITS
:
5997 case AARCH64_OPND_TME_UIMM16
:
5998 case AARCH64_OPND_UIMM4
:
5999 case AARCH64_OPND_UIMM4_ADDG
:
6000 case AARCH64_OPND_UIMM10
:
6001 case AARCH64_OPND_UIMM3_OP1
:
6002 case AARCH64_OPND_UIMM3_OP2
:
6003 case AARCH64_OPND_IMM_VLSL
:
6004 case AARCH64_OPND_IMM
:
6005 case AARCH64_OPND_IMM_2
:
6006 case AARCH64_OPND_WIDTH
:
6007 case AARCH64_OPND_SVE_INV_LIMM
:
6008 case AARCH64_OPND_SVE_LIMM
:
6009 case AARCH64_OPND_SVE_LIMM_MOV
:
6010 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6011 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6012 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6013 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6014 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6015 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6016 case AARCH64_OPND_SVE_SIMM5
:
6017 case AARCH64_OPND_SVE_SIMM5B
:
6018 case AARCH64_OPND_SVE_SIMM6
:
6019 case AARCH64_OPND_SVE_SIMM8
:
6020 case AARCH64_OPND_SVE_UIMM3
:
6021 case AARCH64_OPND_SVE_UIMM7
:
6022 case AARCH64_OPND_SVE_UIMM8
:
6023 case AARCH64_OPND_SVE_UIMM8_53
:
6024 case AARCH64_OPND_IMM_ROT1
:
6025 case AARCH64_OPND_IMM_ROT2
:
6026 case AARCH64_OPND_IMM_ROT3
:
6027 case AARCH64_OPND_SVE_IMM_ROT1
:
6028 case AARCH64_OPND_SVE_IMM_ROT2
:
6029 case AARCH64_OPND_SVE_IMM_ROT3
:
6030 po_imm_nc_or_fail ();
6031 info
->imm
.value
= val
;
6034 case AARCH64_OPND_SVE_AIMM
:
6035 case AARCH64_OPND_SVE_ASIMM
:
6036 po_imm_nc_or_fail ();
6037 info
->imm
.value
= val
;
6038 skip_whitespace (str
);
6039 if (skip_past_comma (&str
))
6040 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6042 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6045 case AARCH64_OPND_SVE_PATTERN
:
6046 po_enum_or_fail (aarch64_sve_pattern_array
);
6047 info
->imm
.value
= val
;
6050 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6051 po_enum_or_fail (aarch64_sve_pattern_array
);
6052 info
->imm
.value
= val
;
6053 if (skip_past_comma (&str
)
6054 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6056 if (!info
->shifter
.operator_present
)
6058 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6059 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6060 info
->shifter
.amount
= 1;
6064 case AARCH64_OPND_SVE_PRFOP
:
6065 po_enum_or_fail (aarch64_sve_prfop_array
);
6066 info
->imm
.value
= val
;
6069 case AARCH64_OPND_UIMM7
:
6070 po_imm_or_fail (0, 127);
6071 info
->imm
.value
= val
;
6074 case AARCH64_OPND_IDX
:
6075 case AARCH64_OPND_MASK
:
6076 case AARCH64_OPND_BIT_NUM
:
6077 case AARCH64_OPND_IMMR
:
6078 case AARCH64_OPND_IMMS
:
6079 po_imm_or_fail (0, 63);
6080 info
->imm
.value
= val
;
6083 case AARCH64_OPND_IMM0
:
6084 po_imm_nc_or_fail ();
6087 set_fatal_syntax_error (_("immediate zero expected"));
6090 info
->imm
.value
= 0;
6093 case AARCH64_OPND_FPIMM0
:
6096 bool res1
= false, res2
= false;
6097 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6098 it is probably not worth the effort to support it. */
6099 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6102 || !(res2
= parse_constant_immediate (&str
, &val
,
6105 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6107 info
->imm
.value
= 0;
6108 info
->imm
.is_fp
= 1;
6111 set_fatal_syntax_error (_("immediate zero expected"));
6115 case AARCH64_OPND_IMM_MOV
:
6118 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6119 reg_name_p (str
, REG_TYPE_VN
))
6122 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6123 GE_OPT_PREFIX
, REJECT_ABSENT
,
6124 NORMAL_RESOLUTION
));
6125 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6126 later. fix_mov_imm_insn will try to determine a machine
6127 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6128 message if the immediate cannot be moved by a single
6130 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6131 inst
.base
.operands
[i
].skip
= 1;
6135 case AARCH64_OPND_SIMD_IMM
:
6136 case AARCH64_OPND_SIMD_IMM_SFT
:
6137 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6139 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6141 /* need_libopcodes_p */ 1,
6144 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6145 shift, we don't check it here; we leave the checking to
6146 the libopcodes (operand_general_constraint_met_p). By
6147 doing this, we achieve better diagnostics. */
6148 if (skip_past_comma (&str
)
6149 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6151 if (!info
->shifter
.operator_present
6152 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6154 /* Default to LSL if not present. Libopcodes prefers shifter
6155 kind to be explicit. */
6156 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6157 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6161 case AARCH64_OPND_FPIMM
:
6162 case AARCH64_OPND_SIMD_FPIMM
:
6163 case AARCH64_OPND_SVE_FPIMM8
:
6168 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6169 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6170 || !aarch64_imm_float_p (qfloat
))
6173 set_fatal_syntax_error (_("invalid floating-point"
6177 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6178 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6182 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6183 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6184 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6189 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6190 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6193 set_fatal_syntax_error (_("invalid floating-point"
6197 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6198 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6202 case AARCH64_OPND_LIMM
:
6203 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6204 SHIFTED_LOGIC_IMM
));
6205 if (info
->shifter
.operator_present
)
6207 set_fatal_syntax_error
6208 (_("shift not allowed for bitmask immediate"));
6211 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6213 /* need_libopcodes_p */ 1,
6217 case AARCH64_OPND_AIMM
:
6218 if (opcode
->op
== OP_ADD
)
6219 /* ADD may have relocation types. */
6220 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6221 SHIFTED_ARITH_IMM
));
6223 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6224 SHIFTED_ARITH_IMM
));
6225 switch (inst
.reloc
.type
)
6227 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6228 info
->shifter
.amount
= 12;
6230 case BFD_RELOC_UNUSED
:
6231 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6232 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6233 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6234 inst
.reloc
.pc_rel
= 0;
6239 info
->imm
.value
= 0;
6240 if (!info
->shifter
.operator_present
)
6242 /* Default to LSL if not present. Libopcodes prefers shifter
6243 kind to be explicit. */
6244 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6245 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6249 case AARCH64_OPND_HALF
:
6251 /* #<imm16> or relocation. */
6252 int internal_fixup_p
;
6253 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6254 if (internal_fixup_p
)
6255 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6256 skip_whitespace (str
);
6257 if (skip_past_comma (&str
))
6259 /* {, LSL #<shift>} */
6260 if (! aarch64_gas_internal_fixup_p ())
6262 set_fatal_syntax_error (_("can't mix relocation modifier "
6263 "with explicit shift"));
6266 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6269 inst
.base
.operands
[i
].shifter
.amount
= 0;
6270 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6271 inst
.base
.operands
[i
].imm
.value
= 0;
6272 if (! process_movw_reloc_info ())
6277 case AARCH64_OPND_EXCEPTION
:
6278 case AARCH64_OPND_UNDEFINED
:
6279 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6281 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6283 /* need_libopcodes_p */ 0,
6287 case AARCH64_OPND_NZCV
:
6289 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6293 info
->imm
.value
= nzcv
->value
;
6296 po_imm_or_fail (0, 15);
6297 info
->imm
.value
= val
;
6301 case AARCH64_OPND_COND
:
6302 case AARCH64_OPND_COND1
:
6307 while (ISALPHA (*str
));
6308 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6309 if (info
->cond
== NULL
)
6311 set_syntax_error (_("invalid condition"));
6314 else if (operands
[i
] == AARCH64_OPND_COND1
6315 && (info
->cond
->value
& 0xe) == 0xe)
6317 /* Do not allow AL or NV. */
6318 set_default_error ();
6324 case AARCH64_OPND_ADDR_ADRP
:
6325 po_misc_or_fail (parse_adrp (&str
));
6326 /* Clear the value as operand needs to be relocated. */
6327 info
->imm
.value
= 0;
6330 case AARCH64_OPND_ADDR_PCREL14
:
6331 case AARCH64_OPND_ADDR_PCREL19
:
6332 case AARCH64_OPND_ADDR_PCREL21
:
6333 case AARCH64_OPND_ADDR_PCREL26
:
6334 po_misc_or_fail (parse_address (&str
, info
));
6335 if (!info
->addr
.pcrel
)
6337 set_syntax_error (_("invalid pc-relative address"));
6340 if (inst
.gen_lit_pool
6341 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6343 /* Only permit "=value" in the literal load instructions.
6344 The literal will be generated by programmer_friendly_fixup. */
6345 set_syntax_error (_("invalid use of \"=immediate\""));
6348 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6350 set_syntax_error (_("unrecognized relocation suffix"));
6353 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6355 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6356 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6360 info
->imm
.value
= 0;
6361 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6362 switch (opcode
->iclass
)
6366 /* e.g. CBZ or B.COND */
6367 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6368 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6372 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6373 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6377 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6379 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6380 : BFD_RELOC_AARCH64_JUMP26
;
6383 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6384 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6387 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6388 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6394 inst
.reloc
.pc_rel
= 1;
6398 case AARCH64_OPND_ADDR_SIMPLE
:
6399 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6401 /* [<Xn|SP>{, #<simm>}] */
6403 /* First use the normal address-parsing routines, to get
6404 the usual syntax errors. */
6405 po_misc_or_fail (parse_address (&str
, info
));
6406 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6407 || !info
->addr
.preind
|| info
->addr
.postind
6408 || info
->addr
.writeback
)
6410 set_syntax_error (_("invalid addressing mode"));
6414 /* Then retry, matching the specific syntax of these addresses. */
6416 po_char_or_fail ('[');
6417 po_reg_or_fail (REG_TYPE_R64_SP
);
6418 /* Accept optional ", #0". */
6419 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6420 && skip_past_char (&str
, ','))
6422 skip_past_char (&str
, '#');
6423 if (! skip_past_char (&str
, '0'))
6425 set_fatal_syntax_error
6426 (_("the optional immediate offset can only be 0"));
6430 po_char_or_fail (']');
6434 case AARCH64_OPND_ADDR_REGOFF
:
6435 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6436 po_misc_or_fail (parse_address (&str
, info
));
6438 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6439 || !info
->addr
.preind
|| info
->addr
.postind
6440 || info
->addr
.writeback
)
6442 set_syntax_error (_("invalid addressing mode"));
6445 if (!info
->shifter
.operator_present
)
6447 /* Default to LSL if not present. Libopcodes prefers shifter
6448 kind to be explicit. */
6449 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6450 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6452 /* Qualifier to be deduced by libopcodes. */
6455 case AARCH64_OPND_ADDR_SIMM7
:
6456 po_misc_or_fail (parse_address (&str
, info
));
6457 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6458 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6460 set_syntax_error (_("invalid addressing mode"));
6463 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6465 set_syntax_error (_("relocation not allowed"));
6468 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6470 /* need_libopcodes_p */ 1,
6474 case AARCH64_OPND_ADDR_SIMM9
:
6475 case AARCH64_OPND_ADDR_SIMM9_2
:
6476 case AARCH64_OPND_ADDR_SIMM11
:
6477 case AARCH64_OPND_ADDR_SIMM13
:
6478 po_misc_or_fail (parse_address (&str
, info
));
6479 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6480 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6481 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6482 && info
->addr
.writeback
))
6484 set_syntax_error (_("invalid addressing mode"));
6487 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6489 set_syntax_error (_("relocation not allowed"));
6492 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6494 /* need_libopcodes_p */ 1,
6498 case AARCH64_OPND_ADDR_SIMM10
:
6499 case AARCH64_OPND_ADDR_OFFSET
:
6500 po_misc_or_fail (parse_address (&str
, info
));
6501 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6502 || !info
->addr
.preind
|| info
->addr
.postind
)
6504 set_syntax_error (_("invalid addressing mode"));
6507 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6509 set_syntax_error (_("relocation not allowed"));
6512 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6514 /* need_libopcodes_p */ 1,
6518 case AARCH64_OPND_ADDR_UIMM12
:
6519 po_misc_or_fail (parse_address (&str
, info
));
6520 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6521 || !info
->addr
.preind
|| info
->addr
.writeback
)
6523 set_syntax_error (_("invalid addressing mode"));
6526 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6527 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6528 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6530 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6532 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6534 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6536 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6537 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6538 /* Leave qualifier to be determined by libopcodes. */
6541 case AARCH64_OPND_SIMD_ADDR_POST
:
6542 /* [<Xn|SP>], <Xm|#<amount>> */
6543 po_misc_or_fail (parse_address (&str
, info
));
6544 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6546 set_syntax_error (_("invalid addressing mode"));
6549 if (!info
->addr
.offset
.is_reg
)
6551 if (inst
.reloc
.exp
.X_op
== O_constant
)
6552 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6555 set_fatal_syntax_error
6556 (_("writeback value must be an immediate constant"));
6563 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6564 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6565 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6566 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6567 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6568 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6569 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6570 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6571 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6572 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6573 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6574 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6575 /* [X<n>{, #imm, MUL VL}]
6577 but recognizing SVE registers. */
6578 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6579 &offset_qualifier
));
6580 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6582 set_syntax_error (_("invalid addressing mode"));
6586 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6587 || !info
->addr
.preind
|| info
->addr
.writeback
)
6589 set_syntax_error (_("invalid addressing mode"));
6592 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6593 || inst
.reloc
.exp
.X_op
!= O_constant
)
6595 /* Make sure this has priority over
6596 "invalid addressing mode". */
6597 set_fatal_syntax_error (_("constant offset required"));
6600 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6603 case AARCH64_OPND_SVE_ADDR_R
:
6604 /* [<Xn|SP>{, <R><m>}]
6605 but recognizing SVE registers. */
6606 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6607 &offset_qualifier
));
6608 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6610 offset_qualifier
= AARCH64_OPND_QLF_X
;
6611 info
->addr
.offset
.is_reg
= 1;
6612 info
->addr
.offset
.regno
= 31;
6614 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6615 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6617 set_syntax_error (_("invalid addressing mode"));
6622 case AARCH64_OPND_SVE_ADDR_RR
:
6623 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6624 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6625 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6626 case AARCH64_OPND_SVE_ADDR_RX
:
6627 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6628 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6629 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6630 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6631 but recognizing SVE registers. */
6632 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6633 &offset_qualifier
));
6634 if (base_qualifier
!= AARCH64_OPND_QLF_X
6635 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6637 set_syntax_error (_("invalid addressing mode"));
6642 case AARCH64_OPND_SVE_ADDR_RZ
:
6643 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6644 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6645 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6646 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6647 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6648 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6649 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6650 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6651 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6652 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6653 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6654 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6655 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6656 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6657 &offset_qualifier
));
6658 if (base_qualifier
!= AARCH64_OPND_QLF_X
6659 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6660 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6662 set_syntax_error (_("invalid addressing mode"));
6665 info
->qualifier
= offset_qualifier
;
6668 case AARCH64_OPND_SVE_ADDR_ZX
:
6669 /* [Zn.<T>{, <Xm>}]. */
6670 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6671 &offset_qualifier
));
6673 base_qualifier either S_S or S_D
6674 offset_qualifier must be X
6676 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6677 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6678 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6680 set_syntax_error (_("invalid addressing mode"));
6683 info
->qualifier
= base_qualifier
;
6684 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6685 || !info
->addr
.preind
|| info
->addr
.writeback
6686 || info
->shifter
.operator_present
!= 0)
6688 set_syntax_error (_("invalid addressing mode"));
6691 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6695 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6696 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6697 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6698 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6699 /* [Z<n>.<T>{, #imm}] */
6700 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6701 &offset_qualifier
));
6702 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6703 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6705 set_syntax_error (_("invalid addressing mode"));
6708 info
->qualifier
= base_qualifier
;
6711 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6712 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6713 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6714 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6715 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6719 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6721 here since we get better error messages by leaving it to
6722 the qualifier checking routines. */
6723 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6724 &offset_qualifier
));
6725 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6726 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6727 || offset_qualifier
!= base_qualifier
)
6729 set_syntax_error (_("invalid addressing mode"));
6732 info
->qualifier
= base_qualifier
;
6735 case AARCH64_OPND_SYSREG
:
6737 uint32_t sysreg_flags
;
6738 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6739 &sysreg_flags
)) == PARSE_FAIL
)
6741 set_syntax_error (_("unknown or missing system register name"));
6744 inst
.base
.operands
[i
].sysreg
.value
= val
;
6745 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6749 case AARCH64_OPND_PSTATEFIELD
:
6750 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6753 set_syntax_error (_("unknown or missing PSTATE field name"));
6756 inst
.base
.operands
[i
].pstatefield
= val
;
6759 case AARCH64_OPND_SYSREG_IC
:
6760 inst
.base
.operands
[i
].sysins_op
=
6761 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6764 case AARCH64_OPND_SYSREG_DC
:
6765 inst
.base
.operands
[i
].sysins_op
=
6766 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6769 case AARCH64_OPND_SYSREG_AT
:
6770 inst
.base
.operands
[i
].sysins_op
=
6771 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6774 case AARCH64_OPND_SYSREG_SR
:
6775 inst
.base
.operands
[i
].sysins_op
=
6776 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6779 case AARCH64_OPND_SYSREG_TLBI
:
6780 inst
.base
.operands
[i
].sysins_op
=
6781 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6783 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6785 set_fatal_syntax_error ( _("unknown or missing operation name"));
6790 case AARCH64_OPND_BARRIER
:
6791 case AARCH64_OPND_BARRIER_ISB
:
6792 val
= parse_barrier (&str
);
6793 if (val
!= PARSE_FAIL
6794 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6796 /* ISB only accepts options name 'sy'. */
6798 (_("the specified option is not accepted in ISB"));
6799 /* Turn off backtrack as this optional operand is present. */
6803 if (val
!= PARSE_FAIL
6804 && operands
[i
] == AARCH64_OPND_BARRIER
)
6806 /* Regular barriers accept options CRm (C0-C15).
6807 DSB nXS barrier variant accepts values > 15. */
6808 if (val
< 0 || val
> 15)
6810 set_syntax_error (_("the specified option is not accepted in DSB"));
6814 /* This is an extension to accept a 0..15 immediate. */
6815 if (val
== PARSE_FAIL
)
6816 po_imm_or_fail (0, 15);
6817 info
->barrier
= aarch64_barrier_options
+ val
;
6820 case AARCH64_OPND_BARRIER_DSB_NXS
:
6821 val
= parse_barrier (&str
);
6822 if (val
!= PARSE_FAIL
)
6824 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
6825 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6827 set_syntax_error (_("the specified option is not accepted in DSB"));
6828 /* Turn off backtrack as this optional operand is present. */
6835 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
6836 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
6837 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
6839 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6841 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
6845 /* Option index is encoded as 2-bit value in val<3:2>. */
6846 val
= (val
>> 2) - 4;
6847 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
6850 case AARCH64_OPND_PRFOP
:
6851 val
= parse_pldop (&str
);
6852 /* This is an extension to accept a 0..31 immediate. */
6853 if (val
== PARSE_FAIL
)
6854 po_imm_or_fail (0, 31);
6855 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6858 case AARCH64_OPND_BARRIER_PSB
:
6859 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6860 if (val
== PARSE_FAIL
)
6864 case AARCH64_OPND_BTI_TARGET
:
6865 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6866 if (val
== PARSE_FAIL
)
6871 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6874 /* If we get here, this operand was successfully parsed. */
6875 inst
.base
.operands
[i
].present
= 1;
6879 /* The parse routine should already have set the error, but in case
6880 not, set a default one here. */
6882 set_default_error ();
6884 if (! backtrack_pos
)
6885 goto parse_operands_return
;
6888 /* We reach here because this operand is marked as optional, and
6889 either no operand was supplied or the operand was supplied but it
6890 was syntactically incorrect. In the latter case we report an
6891 error. In the former case we perform a few more checks before
6892 dropping through to the code to insert the default operand. */
6894 char *tmp
= backtrack_pos
;
6895 char endchar
= END_OF_INSN
;
6897 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6899 skip_past_char (&tmp
, ',');
6901 if (*tmp
!= endchar
)
6902 /* The user has supplied an operand in the wrong format. */
6903 goto parse_operands_return
;
6905 /* Make sure there is not a comma before the optional operand.
6906 For example the fifth operand of 'sys' is optional:
6908 sys #0,c0,c0,#0, <--- wrong
6909 sys #0,c0,c0,#0 <--- correct. */
6910 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6912 set_fatal_syntax_error
6913 (_("unexpected comma before the omitted optional operand"));
6914 goto parse_operands_return
;
6918 /* Reaching here means we are dealing with an optional operand that is
6919 omitted from the assembly line. */
6920 gas_assert (optional_operand_p (opcode
, i
));
6922 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6924 /* Try again, skipping the optional operand at backtrack_pos. */
6925 str
= backtrack_pos
;
6928 /* Clear any error record after the omitted optional operand has been
6929 successfully handled. */
6933 /* Check if we have parsed all the operands. */
6934 if (*str
!= '\0' && ! error_p ())
6936 /* Set I to the index of the last present operand; this is
6937 for the purpose of diagnostics. */
6938 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6940 set_fatal_syntax_error
6941 (_("unexpected characters following instruction"));
6944 parse_operands_return
:
6948 DEBUG_TRACE ("parsing FAIL: %s - %s",
6949 operand_mismatch_kind_names
[get_error_kind ()],
6950 get_error_message ());
6951 /* Record the operand error properly; this is useful when there
6952 are multiple instruction templates for a mnemonic name, so that
6953 later on, we can select the error that most closely describes
6955 record_operand_error (opcode
, i
, get_error_kind (),
6956 get_error_message ());
6961 DEBUG_TRACE ("parsing SUCCESS");
6966 /* It does some fix-up to provide some programmer friendly feature while
6967 keeping the libopcodes happy, i.e. libopcodes only accepts
6968 the preferred architectural syntax.
6969 Return FALSE if there is any failure; otherwise return TRUE. */
6972 programmer_friendly_fixup (aarch64_instruction
*instr
)
6974 aarch64_inst
*base
= &instr
->base
;
6975 const aarch64_opcode
*opcode
= base
->opcode
;
6976 enum aarch64_op op
= opcode
->op
;
6977 aarch64_opnd_info
*operands
= base
->operands
;
6979 DEBUG_TRACE ("enter");
6981 switch (opcode
->iclass
)
6984 /* TBNZ Xn|Wn, #uimm6, label
6985 Test and Branch Not Zero: conditionally jumps to label if bit number
6986 uimm6 in register Xn is not zero. The bit number implies the width of
6987 the register, which may be written and should be disassembled as Wn if
6988 uimm is less than 32. */
6989 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6991 if (operands
[1].imm
.value
>= 32)
6993 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6997 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7001 /* LDR Wt, label | =value
7002 As a convenience assemblers will typically permit the notation
7003 "=value" in conjunction with the pc-relative literal load instructions
7004 to automatically place an immediate value or symbolic address in a
7005 nearby literal pool and generate a hidden label which references it.
7006 ISREG has been set to 0 in the case of =value. */
7007 if (instr
->gen_lit_pool
7008 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7010 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7011 if (op
== OP_LDRSW_LIT
)
7013 if (instr
->reloc
.exp
.X_op
!= O_constant
7014 && instr
->reloc
.exp
.X_op
!= O_big
7015 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7017 record_operand_error (opcode
, 1,
7018 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7019 _("constant expression expected"));
7022 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7024 record_operand_error (opcode
, 1,
7025 AARCH64_OPDE_OTHER_ERROR
,
7026 _("literal pool insertion failed"));
7034 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7035 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7036 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7037 A programmer-friendly assembler should accept a destination Xd in
7038 place of Wd, however that is not the preferred form for disassembly.
7040 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7041 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7042 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7043 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7048 /* In the 64-bit form, the final register operand is written as Wm
7049 for all but the (possibly omitted) UXTX/LSL and SXTX
7051 As a programmer-friendly assembler, we accept e.g.
7052 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7053 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7054 int idx
= aarch64_operand_index (opcode
->operands
,
7055 AARCH64_OPND_Rm_EXT
);
7056 gas_assert (idx
== 1 || idx
== 2);
7057 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7058 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7059 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7060 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7061 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7062 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7070 DEBUG_TRACE ("exit with SUCCESS");
7074 /* Check for loads and stores that will cause unpredictable behavior. */
7077 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7079 aarch64_inst
*base
= &instr
->base
;
7080 const aarch64_opcode
*opcode
= base
->opcode
;
7081 const aarch64_opnd_info
*opnds
= base
->operands
;
7082 switch (opcode
->iclass
)
7089 /* Loading/storing the base register is unpredictable if writeback. */
7090 if ((aarch64_get_operand_class (opnds
[0].type
)
7091 == AARCH64_OPND_CLASS_INT_REG
)
7092 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7093 && opnds
[1].addr
.base_regno
!= REG_SP
7094 /* Exempt STG/STZG/ST2G/STZ2G. */
7095 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7096 && opnds
[1].addr
.writeback
)
7097 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7101 case ldstnapair_offs
:
7102 case ldstpair_indexed
:
7103 /* Loading/storing the base register is unpredictable if writeback. */
7104 if ((aarch64_get_operand_class (opnds
[0].type
)
7105 == AARCH64_OPND_CLASS_INT_REG
)
7106 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7107 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7108 && opnds
[2].addr
.base_regno
!= REG_SP
7110 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7111 && opnds
[2].addr
.writeback
)
7112 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7113 /* Load operations must load different registers. */
7114 if ((opcode
->opcode
& (1 << 22))
7115 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7116 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7120 if ((aarch64_get_operand_class (opnds
[0].type
)
7121 == AARCH64_OPND_CLASS_INT_REG
)
7122 && (aarch64_get_operand_class (opnds
[1].type
)
7123 == AARCH64_OPND_CLASS_INT_REG
))
7125 if ((opcode
->opcode
& (1 << 22)))
7127 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7128 if ((opcode
->opcode
& (1 << 21))
7129 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7130 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7134 /* Store-Exclusive is unpredictable if Rt == Rs. */
7135 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7137 (_("unpredictable: identical transfer and status registers"
7140 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7142 if (!(opcode
->opcode
& (1 << 21)))
7143 /* Store-Exclusive is unpredictable if Rn == Rs. */
7145 (_("unpredictable: identical base and status registers"
7148 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7150 (_("unpredictable: "
7151 "identical transfer and status registers"
7155 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7156 if ((opcode
->opcode
& (1 << 21))
7157 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7158 && opnds
[3].reg
.regno
!= REG_SP
)
7159 as_warn (_("unpredictable: identical base and status registers"
7171 force_automatic_sequence_close (void)
7173 if (now_instr_sequence
.instr
)
7175 as_warn (_("previous `%s' sequence has not been closed"),
7176 now_instr_sequence
.instr
->opcode
->name
);
7177 init_insn_sequence (NULL
, &now_instr_sequence
);
7181 /* A wrapper function to interface with libopcodes on encoding and
7182 record the error message if there is any.
7184 Return TRUE on success; otherwise return FALSE. */
7187 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7190 aarch64_operand_error error_info
;
7191 memset (&error_info
, '\0', sizeof (error_info
));
7192 error_info
.kind
= AARCH64_OPDE_NIL
;
7193 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7194 && !error_info
.non_fatal
)
7197 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7198 record_operand_error_info (opcode
, &error_info
);
7199 return error_info
.non_fatal
;
7202 #ifdef DEBUG_AARCH64
7204 dump_opcode_operands (const aarch64_opcode
*opcode
)
7207 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7209 aarch64_verbose ("\t\t opnd%d: %s", i
,
7210 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7211 ? aarch64_get_operand_name (opcode
->operands
[i
])
7212 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7216 #endif /* DEBUG_AARCH64 */
7218 /* This is the guts of the machine-dependent assembler. STR points to a
7219 machine dependent instruction. This function is supposed to emit
7220 the frags/bytes it assembles to. */
7223 md_assemble (char *str
)
7226 templates
*template;
7227 const aarch64_opcode
*opcode
;
7228 aarch64_inst
*inst_base
;
7229 unsigned saved_cond
;
7231 /* Align the previous label if needed. */
7232 if (last_label_seen
!= NULL
)
7234 symbol_set_frag (last_label_seen
, frag_now
);
7235 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7236 S_SET_SEGMENT (last_label_seen
, now_seg
);
7239 /* Update the current insn_sequence from the segment. */
7240 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7242 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7244 DEBUG_TRACE ("\n\n");
7245 DEBUG_TRACE ("==============================");
7246 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7248 template = opcode_lookup (&p
);
7251 /* It wasn't an instruction, but it might be a register alias of
7252 the form alias .req reg directive. */
7253 if (!create_register_alias (str
, p
))
7254 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7259 skip_whitespace (p
);
7262 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7263 get_mnemonic_name (str
), str
);
7267 init_operand_error_report ();
7269 /* Sections are assumed to start aligned. In executable section, there is no
7270 MAP_DATA symbol pending. So we only align the address during
7271 MAP_DATA --> MAP_INSN transition.
7272 For other sections, this is not guaranteed. */
7273 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7274 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7275 frag_align_code (2, 0);
7277 saved_cond
= inst
.cond
;
7278 reset_aarch64_instruction (&inst
);
7279 inst
.cond
= saved_cond
;
7281 /* Iterate through all opcode entries with the same mnemonic name. */
7284 opcode
= template->opcode
;
7286 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7287 #ifdef DEBUG_AARCH64
7289 dump_opcode_operands (opcode
);
7290 #endif /* DEBUG_AARCH64 */
7292 mapping_state (MAP_INSN
);
7294 inst_base
= &inst
.base
;
7295 inst_base
->opcode
= opcode
;
7297 /* Truly conditionally executed instructions, e.g. b.cond. */
7298 if (opcode
->flags
& F_COND
)
7300 gas_assert (inst
.cond
!= COND_ALWAYS
);
7301 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7302 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7304 else if (inst
.cond
!= COND_ALWAYS
)
7306 /* It shouldn't arrive here, where the assembly looks like a
7307 conditional instruction but the found opcode is unconditional. */
7312 if (parse_operands (p
, opcode
)
7313 && programmer_friendly_fixup (&inst
)
7314 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7316 /* Check that this instruction is supported for this CPU. */
7317 if (!opcode
->avariant
7318 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7320 as_bad (_("selected processor does not support `%s'"), str
);
7324 warn_unpredictable_ldst (&inst
, str
);
7326 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7327 || !inst
.reloc
.need_libopcodes_p
)
7331 /* If there is relocation generated for the instruction,
7332 store the instruction information for the future fix-up. */
7333 struct aarch64_inst
*copy
;
7334 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7335 copy
= XNEW (struct aarch64_inst
);
7336 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7340 /* Issue non-fatal messages if any. */
7341 output_operand_error_report (str
, true);
7345 template = template->next
;
7346 if (template != NULL
)
7348 reset_aarch64_instruction (&inst
);
7349 inst
.cond
= saved_cond
;
7352 while (template != NULL
);
7354 /* Issue the error messages if any. */
7355 output_operand_error_report (str
, false);
7358 /* Various frobbings of labels and their addresses. */
7361 aarch64_start_line_hook (void)
7363 last_label_seen
= NULL
;
7367 aarch64_frob_label (symbolS
* sym
)
7369 last_label_seen
= sym
;
7371 dwarf2_emit_label (sym
);
7375 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7377 /* Check to see if we have a block to close. */
7378 force_automatic_sequence_close ();
7382 aarch64_data_in_code (void)
7384 if (startswith (input_line_pointer
+ 1, "data:"))
7386 *input_line_pointer
= '/';
7387 input_line_pointer
+= 5;
7388 *input_line_pointer
= 0;
7396 aarch64_canonicalize_symbol_name (char *name
)
7400 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7401 *(name
+ len
- 5) = 0;
7406 /* Table of all register names defined by default. The user can
7407 define additional names with .req. Note that all register names
7408 should appear in both upper and lowercase variants. Some registers
7409 also have mixed-case names. */
7411 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
7412 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
7413 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7414 #define REGSET16(p,t) \
7415 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7416 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7417 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7418 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7419 #define REGSET31(p,t) \
7421 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7422 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7423 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7424 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7425 #define REGSET(p,t) \
7426 REGSET31(p,t), REGNUM(p,31,t)
7428 /* These go into aarch64_reg_hsh hash-table. */
7429 static const reg_entry reg_names
[] = {
7430 /* Integer registers. */
7431 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7432 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7434 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7435 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7436 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7437 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7438 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7439 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7441 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7442 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7444 /* Floating-point single precision registers. */
7445 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7447 /* Floating-point double precision registers. */
7448 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7450 /* Floating-point half precision registers. */
7451 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7453 /* Floating-point byte precision registers. */
7454 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7456 /* Floating-point quad precision registers. */
7457 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7459 /* FP/SIMD registers. */
7460 REGSET (v
, VN
), REGSET (V
, VN
),
7462 /* SVE vector registers. */
7463 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7465 /* SVE predicate registers. */
7466 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7484 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7485 static const asm_nzcv nzcv_names
[] = {
7486 {"nzcv", B (n
, z
, c
, v
)},
7487 {"nzcV", B (n
, z
, c
, V
)},
7488 {"nzCv", B (n
, z
, C
, v
)},
7489 {"nzCV", B (n
, z
, C
, V
)},
7490 {"nZcv", B (n
, Z
, c
, v
)},
7491 {"nZcV", B (n
, Z
, c
, V
)},
7492 {"nZCv", B (n
, Z
, C
, v
)},
7493 {"nZCV", B (n
, Z
, C
, V
)},
7494 {"Nzcv", B (N
, z
, c
, v
)},
7495 {"NzcV", B (N
, z
, c
, V
)},
7496 {"NzCv", B (N
, z
, C
, v
)},
7497 {"NzCV", B (N
, z
, C
, V
)},
7498 {"NZcv", B (N
, Z
, c
, v
)},
7499 {"NZcV", B (N
, Z
, c
, V
)},
7500 {"NZCv", B (N
, Z
, C
, v
)},
7501 {"NZCV", B (N
, Z
, C
, V
)}
7514 /* MD interface: bits in the object file. */
7516 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7517 for use in the a.out file, and stores them in the array pointed to by buf.
7518 This knows about the endian-ness of the target machine and does
7519 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7520 2 (short) and 4 (long) Floating numbers are put out as a series of
7521 LITTLENUMS (shorts, here at least). */
7524 md_number_to_chars (char *buf
, valueT val
, int n
)
7526 if (target_big_endian
)
7527 number_to_chars_bigendian (buf
, val
, n
);
7529 number_to_chars_littleendian (buf
, val
, n
);
7532 /* MD interface: Sections. */
7534 /* Estimate the size of a frag before relaxing. Assume everything fits in
7538 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7544 /* Round up a section size to the appropriate boundary. */
7547 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7552 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7553 of an rs_align_code fragment.
7555 Here we fill the frag with the appropriate info for padding the
7556 output stream. The resulting frag will consist of a fixed (fr_fix)
7557 and of a repeating (fr_var) part.
7559 The fixed content is always emitted before the repeating content and
7560 these two parts are used as follows in constructing the output:
7561 - the fixed part will be used to align to a valid instruction word
7562 boundary, in case that we start at a misaligned address; as no
7563 executable instruction can live at the misaligned location, we
7564 simply fill with zeros;
7565 - the variable part will be used to cover the remaining padding and
7566 we fill using the AArch64 NOP instruction.
7568 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7569 enough storage space for up to 3 bytes for padding the back to a valid
7570 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7573 aarch64_handle_align (fragS
* fragP
)
7575 /* NOP = d503201f */
7576 /* AArch64 instructions are always little-endian. */
7577 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7579 int bytes
, fix
, noop_size
;
7582 if (fragP
->fr_type
!= rs_align_code
)
7585 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7586 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7589 gas_assert (fragP
->tc_frag_data
.recorded
);
7592 noop_size
= sizeof (aarch64_noop
);
7594 fix
= bytes
& (noop_size
- 1);
7598 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7602 fragP
->fr_fix
+= fix
;
7606 memcpy (p
, aarch64_noop
, noop_size
);
7607 fragP
->fr_var
= noop_size
;
7610 /* Perform target specific initialisation of a frag.
7611 Note - despite the name this initialisation is not done when the frag
7612 is created, but only when its type is assigned. A frag can be created
7613 and used a long time before its type is set, so beware of assuming that
7614 this initialisation is performed first. */
7618 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7619 int max_chars ATTRIBUTE_UNUSED
)
7623 #else /* OBJ_ELF is defined. */
7625 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7627 /* Record a mapping symbol for alignment frags. We will delete this
7628 later if the alignment ends up empty. */
7629 if (!fragP
->tc_frag_data
.recorded
)
7630 fragP
->tc_frag_data
.recorded
= 1;
7632 /* PR 21809: Do not set a mapping state for debug sections
7633 - it just confuses other tools. */
7634 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7637 switch (fragP
->fr_type
)
7641 mapping_state_2 (MAP_DATA
, max_chars
);
7644 /* PR 20364: We can get alignment frags in code sections,
7645 so do not just assume that we should use the MAP_DATA state. */
7646 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7649 mapping_state_2 (MAP_INSN
, max_chars
);
7656 /* Initialize the DWARF-2 unwind information for this procedure. */
7659 tc_aarch64_frame_initial_instructions (void)
7661 cfi_add_CFA_def_cfa (REG_SP
, 0);
7663 #endif /* OBJ_ELF */
7665 /* Convert REGNAME to a DWARF-2 register number. */
7668 tc_aarch64_regname_to_dw2regnum (char *regname
)
7670 const reg_entry
*reg
= parse_reg (®name
);
7676 case REG_TYPE_SP_32
:
7677 case REG_TYPE_SP_64
:
7687 return reg
->number
+ 64;
7695 /* Implement DWARF2_ADDR_SIZE. */
7698 aarch64_dwarf2_addr_size (void)
7700 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7704 return bfd_arch_bits_per_address (stdoutput
) / 8;
7707 /* MD interface: Symbol and relocation handling. */
7709 /* Return the address within the segment that a PC-relative fixup is
7710 relative to. For AArch64 PC-relative fixups applied to instructions
7711 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7714 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7716 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7718 /* If this is pc-relative and we are going to emit a relocation
7719 then we just want to put out any pipeline compensation that the linker
7720 will need. Otherwise we want to use the calculated base. */
7722 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7723 || aarch64_force_relocation (fixP
)))
7726 /* AArch64 should be consistent for all pc-relative relocations. */
7727 return base
+ AARCH64_PCREL_OFFSET
;
7730 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7731 Otherwise we have no need to default values of symbols. */
7734 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7737 if (name
[0] == '_' && name
[1] == 'G'
7738 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7742 if (symbol_find (name
))
7743 as_bad (_("GOT already in the symbol table"));
7745 GOT_symbol
= symbol_new (name
, undefined_section
,
7746 &zero_address_frag
, 0);
7756 /* Return non-zero if the indicated VALUE has overflowed the maximum
7757 range expressible by a unsigned number with the indicated number of
7761 unsigned_overflow (valueT value
, unsigned bits
)
7764 if (bits
>= sizeof (valueT
) * 8)
7766 lim
= (valueT
) 1 << bits
;
7767 return (value
>= lim
);
7771 /* Return non-zero if the indicated VALUE has overflowed the maximum
7772 range expressible by an signed number with the indicated number of
7776 signed_overflow (offsetT value
, unsigned bits
)
7779 if (bits
>= sizeof (offsetT
) * 8)
7781 lim
= (offsetT
) 1 << (bits
- 1);
7782 return (value
< -lim
|| value
>= lim
);
7785 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7786 unsigned immediate offset load/store instruction, try to encode it as
7787 an unscaled, 9-bit, signed immediate offset load/store instruction.
7788 Return TRUE if it is successful; otherwise return FALSE.
7790 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7791 in response to the standard LDR/STR mnemonics when the immediate offset is
7792 unambiguous, i.e. when it is negative or unaligned. */
7795 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7798 enum aarch64_op new_op
;
7799 const aarch64_opcode
*new_opcode
;
7801 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7803 switch (instr
->opcode
->op
)
7805 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7806 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7807 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7808 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7809 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7810 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7811 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7812 case OP_STR_POS
: new_op
= OP_STUR
; break;
7813 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7814 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7815 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7816 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7817 default: new_op
= OP_NIL
; break;
7820 if (new_op
== OP_NIL
)
7823 new_opcode
= aarch64_get_opcode (new_op
);
7824 gas_assert (new_opcode
!= NULL
);
7826 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7827 instr
->opcode
->op
, new_opcode
->op
);
7829 aarch64_replace_opcode (instr
, new_opcode
);
7831 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7832 qualifier matching may fail because the out-of-date qualifier will
7833 prevent the operand being updated with a new and correct qualifier. */
7834 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7835 AARCH64_OPND_ADDR_SIMM9
);
7836 gas_assert (idx
== 1);
7837 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7839 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7841 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7848 /* Called by fix_insn to fix a MOV immediate alias instruction.
7850 Operand for a generic move immediate instruction, which is an alias
7851 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7852 a 32-bit/64-bit immediate value into general register. An assembler error
7853 shall result if the immediate cannot be created by a single one of these
7854 instructions. If there is a choice, then to ensure reversability an
7855 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7858 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7860 const aarch64_opcode
*opcode
;
7862 /* Need to check if the destination is SP/ZR. The check has to be done
7863 before any aarch64_replace_opcode. */
7864 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7865 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7867 instr
->operands
[1].imm
.value
= value
;
7868 instr
->operands
[1].skip
= 0;
7872 /* Try the MOVZ alias. */
7873 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7874 aarch64_replace_opcode (instr
, opcode
);
7875 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7876 &instr
->value
, NULL
, NULL
, insn_sequence
))
7878 put_aarch64_insn (buf
, instr
->value
);
7881 /* Try the MOVK alias. */
7882 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7883 aarch64_replace_opcode (instr
, opcode
);
7884 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7885 &instr
->value
, NULL
, NULL
, insn_sequence
))
7887 put_aarch64_insn (buf
, instr
->value
);
7892 if (try_mov_bitmask_p
)
7894 /* Try the ORR alias. */
7895 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7896 aarch64_replace_opcode (instr
, opcode
);
7897 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7898 &instr
->value
, NULL
, NULL
, insn_sequence
))
7900 put_aarch64_insn (buf
, instr
->value
);
7905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7906 _("immediate cannot be moved by a single instruction"));
7909 /* An instruction operand which is immediate related may have symbol used
7910 in the assembly, e.g.
7913 .set u32, 0x00ffff00
7915 At the time when the assembly instruction is parsed, a referenced symbol,
7916 like 'u32' in the above example may not have been seen; a fixS is created
7917 in such a case and is handled here after symbols have been resolved.
7918 Instruction is fixed up with VALUE using the information in *FIXP plus
7919 extra information in FLAGS.
7921 This function is called by md_apply_fix to fix up instructions that need
7922 a fix-up described above but does not involve any linker-time relocation. */
7925 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7929 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7930 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7931 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7935 /* Now the instruction is about to be fixed-up, so the operand that
7936 was previously marked as 'ignored' needs to be unmarked in order
7937 to get the encoding done properly. */
7938 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7939 new_inst
->operands
[idx
].skip
= 0;
7942 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7946 case AARCH64_OPND_EXCEPTION
:
7947 case AARCH64_OPND_UNDEFINED
:
7948 if (unsigned_overflow (value
, 16))
7949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7950 _("immediate out of range"));
7951 insn
= get_aarch64_insn (buf
);
7952 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
7953 put_aarch64_insn (buf
, insn
);
7956 case AARCH64_OPND_AIMM
:
7957 /* ADD or SUB with immediate.
7958 NOTE this assumes we come here with a add/sub shifted reg encoding
7959 3 322|2222|2 2 2 21111 111111
7960 1 098|7654|3 2 1 09876 543210 98765 43210
7961 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7962 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7963 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7964 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7966 3 322|2222|2 2 221111111111
7967 1 098|7654|3 2 109876543210 98765 43210
7968 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7969 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7970 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7971 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7972 Fields sf Rn Rd are already set. */
7973 insn
= get_aarch64_insn (buf
);
7977 insn
= reencode_addsub_switch_add_sub (insn
);
7981 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7982 && unsigned_overflow (value
, 12))
7984 /* Try to shift the value by 12 to make it fit. */
7985 if (((value
>> 12) << 12) == value
7986 && ! unsigned_overflow (value
, 12 + 12))
7989 insn
|= encode_addsub_imm_shift_amount (1);
7993 if (unsigned_overflow (value
, 12))
7994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7995 _("immediate out of range"));
7997 insn
|= encode_addsub_imm (value
);
7999 put_aarch64_insn (buf
, insn
);
8002 case AARCH64_OPND_SIMD_IMM
:
8003 case AARCH64_OPND_SIMD_IMM_SFT
:
8004 case AARCH64_OPND_LIMM
:
8005 /* Bit mask immediate. */
8006 gas_assert (new_inst
!= NULL
);
8007 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8008 new_inst
->operands
[idx
].imm
.value
= value
;
8009 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8010 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8011 put_aarch64_insn (buf
, new_inst
->value
);
8013 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8014 _("invalid immediate"));
8017 case AARCH64_OPND_HALF
:
8018 /* 16-bit unsigned immediate. */
8019 if (unsigned_overflow (value
, 16))
8020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8021 _("immediate out of range"));
8022 insn
= get_aarch64_insn (buf
);
8023 insn
|= encode_movw_imm (value
& 0xffff);
8024 put_aarch64_insn (buf
, insn
);
8027 case AARCH64_OPND_IMM_MOV
:
8028 /* Operand for a generic move immediate instruction, which is
8029 an alias instruction that generates a single MOVZ, MOVN or ORR
8030 instruction to loads a 32-bit/64-bit immediate value into general
8031 register. An assembler error shall result if the immediate cannot be
8032 created by a single one of these instructions. If there is a choice,
8033 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8034 and MOVZ or MOVN to ORR. */
8035 gas_assert (new_inst
!= NULL
);
8036 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8039 case AARCH64_OPND_ADDR_SIMM7
:
8040 case AARCH64_OPND_ADDR_SIMM9
:
8041 case AARCH64_OPND_ADDR_SIMM9_2
:
8042 case AARCH64_OPND_ADDR_SIMM10
:
8043 case AARCH64_OPND_ADDR_UIMM12
:
8044 case AARCH64_OPND_ADDR_SIMM11
:
8045 case AARCH64_OPND_ADDR_SIMM13
:
8046 /* Immediate offset in an address. */
8047 insn
= get_aarch64_insn (buf
);
8049 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8050 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8051 || new_inst
->opcode
->operands
[2] == opnd
);
8053 /* Get the index of the address operand. */
8054 if (new_inst
->opcode
->operands
[1] == opnd
)
8055 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8058 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8061 /* Update the resolved offset value. */
8062 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8064 /* Encode/fix-up. */
8065 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8066 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8068 put_aarch64_insn (buf
, new_inst
->value
);
8071 else if (new_inst
->opcode
->iclass
== ldst_pos
8072 && try_to_encode_as_unscaled_ldst (new_inst
))
8074 put_aarch64_insn (buf
, new_inst
->value
);
8078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8079 _("immediate offset out of range"));
8084 as_fatal (_("unhandled operand code %d"), opnd
);
8088 /* Apply a fixup (fixP) to segment data, once it has been determined
8089 by our caller that we have all the info we need to fix it up.
8091 Parameter valP is the pointer to the value of the bits. */
8094 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8096 offsetT value
= *valP
;
8098 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8100 unsigned flags
= fixP
->fx_addnumber
;
8102 DEBUG_TRACE ("\n\n");
8103 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8104 DEBUG_TRACE ("Enter md_apply_fix");
8106 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8108 /* Note whether this will delete the relocation. */
8110 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8113 /* Process the relocations. */
8114 switch (fixP
->fx_r_type
)
8116 case BFD_RELOC_NONE
:
8117 /* This will need to go in the object file. */
8122 case BFD_RELOC_8_PCREL
:
8123 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8124 md_number_to_chars (buf
, value
, 1);
8128 case BFD_RELOC_16_PCREL
:
8129 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8130 md_number_to_chars (buf
, value
, 2);
8134 case BFD_RELOC_32_PCREL
:
8135 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8136 md_number_to_chars (buf
, value
, 4);
8140 case BFD_RELOC_64_PCREL
:
8141 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8142 md_number_to_chars (buf
, value
, 8);
8145 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8146 /* We claim that these fixups have been processed here, even if
8147 in fact we generate an error because we do not have a reloc
8148 for them, so tc_gen_reloc() will reject them. */
8150 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8153 _("undefined symbol %s used as an immediate value"),
8154 S_GET_NAME (fixP
->fx_addsy
));
8155 goto apply_fix_return
;
8157 fix_insn (fixP
, flags
, value
);
8160 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8165 _("pc-relative load offset not word aligned"));
8166 if (signed_overflow (value
, 21))
8167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8168 _("pc-relative load offset out of range"));
8169 insn
= get_aarch64_insn (buf
);
8170 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8171 put_aarch64_insn (buf
, insn
);
8175 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8176 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8178 if (signed_overflow (value
, 21))
8179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8180 _("pc-relative address offset out of range"));
8181 insn
= get_aarch64_insn (buf
);
8182 insn
|= encode_adr_imm (value
);
8183 put_aarch64_insn (buf
, insn
);
8187 case BFD_RELOC_AARCH64_BRANCH19
:
8188 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8192 _("conditional branch target not word aligned"));
8193 if (signed_overflow (value
, 21))
8194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8195 _("conditional branch out of range"));
8196 insn
= get_aarch64_insn (buf
);
8197 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8198 put_aarch64_insn (buf
, insn
);
8202 case BFD_RELOC_AARCH64_TSTBR14
:
8203 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8207 _("conditional branch target not word aligned"));
8208 if (signed_overflow (value
, 16))
8209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8210 _("conditional branch out of range"));
8211 insn
= get_aarch64_insn (buf
);
8212 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8213 put_aarch64_insn (buf
, insn
);
8217 case BFD_RELOC_AARCH64_CALL26
:
8218 case BFD_RELOC_AARCH64_JUMP26
:
8219 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8223 _("branch target not word aligned"));
8224 if (signed_overflow (value
, 28))
8225 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8226 _("branch out of range"));
8227 insn
= get_aarch64_insn (buf
);
8228 insn
|= encode_branch_ofs_26 (value
>> 2);
8229 put_aarch64_insn (buf
, insn
);
8233 case BFD_RELOC_AARCH64_MOVW_G0
:
8234 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8235 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8236 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8237 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8238 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8241 case BFD_RELOC_AARCH64_MOVW_G1
:
8242 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8243 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8244 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8245 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8246 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8249 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8251 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8252 /* Should always be exported to object file, see
8253 aarch64_force_relocation(). */
8254 gas_assert (!fixP
->fx_done
);
8255 gas_assert (seg
->use_rela_p
);
8257 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8259 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8260 /* Should always be exported to object file, see
8261 aarch64_force_relocation(). */
8262 gas_assert (!fixP
->fx_done
);
8263 gas_assert (seg
->use_rela_p
);
8265 case BFD_RELOC_AARCH64_MOVW_G2
:
8266 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8267 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8268 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8269 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8272 case BFD_RELOC_AARCH64_MOVW_G3
:
8273 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8276 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8278 insn
= get_aarch64_insn (buf
);
8282 /* REL signed addend must fit in 16 bits */
8283 if (signed_overflow (value
, 16))
8284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8285 _("offset out of range"));
8289 /* Check for overflow and scale. */
8290 switch (fixP
->fx_r_type
)
8292 case BFD_RELOC_AARCH64_MOVW_G0
:
8293 case BFD_RELOC_AARCH64_MOVW_G1
:
8294 case BFD_RELOC_AARCH64_MOVW_G2
:
8295 case BFD_RELOC_AARCH64_MOVW_G3
:
8296 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8297 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8298 if (unsigned_overflow (value
, scale
+ 16))
8299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8300 _("unsigned value out of range"));
8302 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8303 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8304 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8305 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8306 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8307 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8308 /* NOTE: We can only come here with movz or movn. */
8309 if (signed_overflow (value
, scale
+ 16))
8310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8311 _("signed value out of range"));
8314 /* Force use of MOVN. */
8316 insn
= reencode_movzn_to_movn (insn
);
8320 /* Force use of MOVZ. */
8321 insn
= reencode_movzn_to_movz (insn
);
8325 /* Unchecked relocations. */
8331 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8332 insn
|= encode_movw_imm (value
& 0xffff);
8334 put_aarch64_insn (buf
, insn
);
8338 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8339 fixP
->fx_r_type
= (ilp32_p
8340 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8341 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8342 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8343 /* Should always be exported to object file, see
8344 aarch64_force_relocation(). */
8345 gas_assert (!fixP
->fx_done
);
8346 gas_assert (seg
->use_rela_p
);
8349 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8350 fixP
->fx_r_type
= (ilp32_p
8351 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8352 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8353 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8354 /* Should always be exported to object file, see
8355 aarch64_force_relocation(). */
8356 gas_assert (!fixP
->fx_done
);
8357 gas_assert (seg
->use_rela_p
);
8360 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8361 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8362 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8363 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8364 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8365 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8366 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8367 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8368 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8369 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8370 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8371 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8372 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8373 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8374 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8375 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8376 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8377 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8378 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8379 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8380 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8381 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8382 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8383 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8384 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8385 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8386 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8387 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8388 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8389 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8390 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8391 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8392 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8393 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8394 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8395 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8396 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8397 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8398 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8399 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8400 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8401 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8402 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8403 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8404 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8405 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8406 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8407 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8408 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8409 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8410 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8411 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8412 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8413 /* Should always be exported to object file, see
8414 aarch64_force_relocation(). */
8415 gas_assert (!fixP
->fx_done
);
8416 gas_assert (seg
->use_rela_p
);
8419 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8420 /* Should always be exported to object file, see
8421 aarch64_force_relocation(). */
8422 fixP
->fx_r_type
= (ilp32_p
8423 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8424 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8425 gas_assert (!fixP
->fx_done
);
8426 gas_assert (seg
->use_rela_p
);
8429 case BFD_RELOC_AARCH64_ADD_LO12
:
8430 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8431 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8432 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8433 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8434 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8435 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8436 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8437 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8438 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8439 case BFD_RELOC_AARCH64_LDST128_LO12
:
8440 case BFD_RELOC_AARCH64_LDST16_LO12
:
8441 case BFD_RELOC_AARCH64_LDST32_LO12
:
8442 case BFD_RELOC_AARCH64_LDST64_LO12
:
8443 case BFD_RELOC_AARCH64_LDST8_LO12
:
8444 /* Should always be exported to object file, see
8445 aarch64_force_relocation(). */
8446 gas_assert (!fixP
->fx_done
);
8447 gas_assert (seg
->use_rela_p
);
8450 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8451 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8452 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8455 case BFD_RELOC_UNUSED
:
8456 /* An error will already have been reported. */
8460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8461 _("unexpected %s fixup"),
8462 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8467 /* Free the allocated the struct aarch64_inst.
8468 N.B. currently there are very limited number of fix-up types actually use
8469 this field, so the impact on the performance should be minimal . */
8470 free (fixP
->tc_fix_data
.inst
);
8475 /* Translate internal representation of relocation info to BFD target
8479 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8482 bfd_reloc_code_real_type code
;
8484 reloc
= XNEW (arelent
);
8486 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8487 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8488 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8492 if (section
->use_rela_p
)
8493 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8495 fixp
->fx_offset
= reloc
->address
;
8497 reloc
->addend
= fixp
->fx_offset
;
8499 code
= fixp
->fx_r_type
;
8504 code
= BFD_RELOC_16_PCREL
;
8509 code
= BFD_RELOC_32_PCREL
;
8514 code
= BFD_RELOC_64_PCREL
;
8521 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8522 if (reloc
->howto
== NULL
)
8524 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8526 ("cannot represent %s relocation in this object file format"),
8527 bfd_get_reloc_code_name (code
));
8534 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8537 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8539 bfd_reloc_code_real_type type
;
8543 FIXME: @@ Should look at CPU word size. */
8550 type
= BFD_RELOC_16
;
8553 type
= BFD_RELOC_32
;
8556 type
= BFD_RELOC_64
;
8559 as_bad (_("cannot do %u-byte relocation"), size
);
8560 type
= BFD_RELOC_UNUSED
;
8564 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8569 /* Implement md_after_parse_args. This is the earliest time we need to decide
8570 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8573 aarch64_after_parse_args (void)
8575 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8578 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8579 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8580 aarch64_abi
= AARCH64_ABI_ILP32
;
8582 aarch64_abi
= AARCH64_ABI_LP64
;
8586 elf64_aarch64_target_format (void)
8589 /* FIXME: What to do for ilp32_p ? */
8590 if (target_big_endian
)
8591 return "elf64-bigaarch64-cloudabi";
8593 return "elf64-littleaarch64-cloudabi";
8595 if (target_big_endian
)
8596 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8598 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8603 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8605 elf_frob_symbol (symp
, puntp
);
8609 /* MD interface: Finalization. */
8611 /* A good place to do this, although this was probably not intended
8612 for this kind of use. We need to dump the literal pool before
8613 references are made to a null symbol pointer. */
8616 aarch64_cleanup (void)
8620 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8622 /* Put it at the end of the relevant section. */
8623 subseg_set (pool
->section
, pool
->sub_section
);
8629 /* Remove any excess mapping symbols generated for alignment frags in
8630 SEC. We may have created a mapping symbol before a zero byte
8631 alignment; remove it if there's a mapping symbol after the
8634 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8635 void *dummy ATTRIBUTE_UNUSED
)
8637 segment_info_type
*seginfo
= seg_info (sec
);
8640 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8643 for (fragp
= seginfo
->frchainP
->frch_root
;
8644 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8646 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8647 fragS
*next
= fragp
->fr_next
;
8649 /* Variable-sized frags have been converted to fixed size by
8650 this point. But if this was variable-sized to start with,
8651 there will be a fixed-size frag after it. So don't handle
8653 if (sym
== NULL
|| next
== NULL
)
8656 if (S_GET_VALUE (sym
) < next
->fr_address
)
8657 /* Not at the end of this frag. */
8659 know (S_GET_VALUE (sym
) == next
->fr_address
);
8663 if (next
->tc_frag_data
.first_map
!= NULL
)
8665 /* Next frag starts with a mapping symbol. Discard this
8667 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8671 if (next
->fr_next
== NULL
)
8673 /* This mapping symbol is at the end of the section. Discard
8675 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8676 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8680 /* As long as we have empty frags without any mapping symbols,
8682 /* If the next frag is non-empty and does not start with a
8683 mapping symbol, then this mapping symbol is required. */
8684 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8687 next
= next
->fr_next
;
8689 while (next
!= NULL
);
8694 /* Adjust the symbol table. */
8697 aarch64_adjust_symtab (void)
8700 /* Remove any overlapping mapping symbols generated by alignment frags. */
8701 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8702 /* Now do generic ELF adjustments. */
8703 elf_adjust_symtab ();
8708 checked_hash_insert (htab_t table
, const char *key
, void *value
)
8710 str_hash_insert (table
, key
, value
, 0);
8714 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
8716 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
8717 checked_hash_insert (table
, key
, value
);
8721 fill_instruction_hash_table (void)
8723 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
8725 while (opcode
->name
!= NULL
)
8727 templates
*templ
, *new_templ
;
8728 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
8730 new_templ
= XNEW (templates
);
8731 new_templ
->opcode
= opcode
;
8732 new_templ
->next
= NULL
;
8735 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8738 new_templ
->next
= templ
->next
;
8739 templ
->next
= new_templ
;
8746 convert_to_upper (char *dst
, const char *src
, size_t num
)
8749 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8750 *dst
= TOUPPER (*src
);
8754 /* Assume STR point to a lower-case string, allocate, convert and return
8755 the corresponding upper-case string. */
8756 static inline const char*
8757 get_upper_str (const char *str
)
8760 size_t len
= strlen (str
);
8761 ret
= XNEWVEC (char, len
+ 1);
8762 convert_to_upper (ret
, str
, len
);
8766 /* MD interface: Initialization. */
8774 aarch64_ops_hsh
= str_htab_create ();
8775 aarch64_cond_hsh
= str_htab_create ();
8776 aarch64_shift_hsh
= str_htab_create ();
8777 aarch64_sys_regs_hsh
= str_htab_create ();
8778 aarch64_pstatefield_hsh
= str_htab_create ();
8779 aarch64_sys_regs_ic_hsh
= str_htab_create ();
8780 aarch64_sys_regs_dc_hsh
= str_htab_create ();
8781 aarch64_sys_regs_at_hsh
= str_htab_create ();
8782 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
8783 aarch64_sys_regs_sr_hsh
= str_htab_create ();
8784 aarch64_reg_hsh
= str_htab_create ();
8785 aarch64_barrier_opt_hsh
= str_htab_create ();
8786 aarch64_nzcv_hsh
= str_htab_create ();
8787 aarch64_pldop_hsh
= str_htab_create ();
8788 aarch64_hint_opt_hsh
= str_htab_create ();
8790 fill_instruction_hash_table ();
8792 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8793 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8794 (void *) (aarch64_sys_regs
+ i
));
8796 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8797 sysreg_hash_insert (aarch64_pstatefield_hsh
,
8798 aarch64_pstatefields
[i
].name
,
8799 (void *) (aarch64_pstatefields
+ i
));
8801 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8802 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
8803 aarch64_sys_regs_ic
[i
].name
,
8804 (void *) (aarch64_sys_regs_ic
+ i
));
8806 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8807 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
8808 aarch64_sys_regs_dc
[i
].name
,
8809 (void *) (aarch64_sys_regs_dc
+ i
));
8811 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8812 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
8813 aarch64_sys_regs_at
[i
].name
,
8814 (void *) (aarch64_sys_regs_at
+ i
));
8816 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8817 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8818 aarch64_sys_regs_tlbi
[i
].name
,
8819 (void *) (aarch64_sys_regs_tlbi
+ i
));
8821 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8822 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
8823 aarch64_sys_regs_sr
[i
].name
,
8824 (void *) (aarch64_sys_regs_sr
+ i
));
8826 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8827 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8828 (void *) (reg_names
+ i
));
8830 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8831 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8832 (void *) (nzcv_names
+ i
));
8834 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8836 const char *name
= aarch64_operand_modifiers
[i
].name
;
8837 checked_hash_insert (aarch64_shift_hsh
, name
,
8838 (void *) (aarch64_operand_modifiers
+ i
));
8839 /* Also hash the name in the upper case. */
8840 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8841 (void *) (aarch64_operand_modifiers
+ i
));
8844 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8847 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8848 the same condition code. */
8849 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8851 const char *name
= aarch64_conds
[i
].names
[j
];
8854 checked_hash_insert (aarch64_cond_hsh
, name
,
8855 (void *) (aarch64_conds
+ i
));
8856 /* Also hash the name in the upper case. */
8857 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8858 (void *) (aarch64_conds
+ i
));
8862 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8864 const char *name
= aarch64_barrier_options
[i
].name
;
8865 /* Skip xx00 - the unallocated values of option. */
8868 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8869 (void *) (aarch64_barrier_options
+ i
));
8870 /* Also hash the name in the upper case. */
8871 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8872 (void *) (aarch64_barrier_options
+ i
));
8875 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
8877 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
8878 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8879 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8880 /* Also hash the name in the upper case. */
8881 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8882 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8885 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8887 const char* name
= aarch64_prfops
[i
].name
;
8888 /* Skip the unallocated hint encodings. */
8891 checked_hash_insert (aarch64_pldop_hsh
, name
,
8892 (void *) (aarch64_prfops
+ i
));
8893 /* Also hash the name in the upper case. */
8894 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8895 (void *) (aarch64_prfops
+ i
));
8898 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8900 const char* name
= aarch64_hint_options
[i
].name
;
8901 const char* upper_name
= get_upper_str(name
);
8903 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8904 (void *) (aarch64_hint_options
+ i
));
8906 /* Also hash the name in the upper case if not the same. */
8907 if (strcmp (name
, upper_name
) != 0)
8908 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8909 (void *) (aarch64_hint_options
+ i
));
8912 /* Set the cpu variant based on the command-line options. */
8914 mcpu_cpu_opt
= march_cpu_opt
;
8917 mcpu_cpu_opt
= &cpu_default
;
8919 cpu_variant
= *mcpu_cpu_opt
;
8921 /* Record the CPU type. */
8922 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8924 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8927 /* Command line processing. */
8929 const char *md_shortopts
= "m:";
8931 #ifdef AARCH64_BI_ENDIAN
8932 #define OPTION_EB (OPTION_MD_BASE + 0)
8933 #define OPTION_EL (OPTION_MD_BASE + 1)
8935 #if TARGET_BYTES_BIG_ENDIAN
8936 #define OPTION_EB (OPTION_MD_BASE + 0)
8938 #define OPTION_EL (OPTION_MD_BASE + 1)
8942 struct option md_longopts
[] = {
8944 {"EB", no_argument
, NULL
, OPTION_EB
},
8947 {"EL", no_argument
, NULL
, OPTION_EL
},
8949 {NULL
, no_argument
, NULL
, 0}
8952 size_t md_longopts_size
= sizeof (md_longopts
);
8954 struct aarch64_option_table
8956 const char *option
; /* Option name to match. */
8957 const char *help
; /* Help information. */
8958 int *var
; /* Variable to change. */
8959 int value
; /* What to change it to. */
8960 char *deprecated
; /* If non-null, print this message. */
8963 static struct aarch64_option_table aarch64_opts
[] = {
8964 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8965 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8967 #ifdef DEBUG_AARCH64
8968 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8969 #endif /* DEBUG_AARCH64 */
8970 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8972 {"mno-verbose-error", N_("do not output verbose error messages"),
8973 &verbose_error_p
, 0, NULL
},
8974 {NULL
, NULL
, NULL
, 0, NULL
}
8977 struct aarch64_cpu_option_table
8980 const aarch64_feature_set value
;
8981 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8983 const char *canonical_name
;
8986 /* This list should, at a minimum, contain all the cpu names
8987 recognized by GCC. */
8988 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8989 {"all", AARCH64_ANY
, NULL
},
8990 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8991 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8992 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8993 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8994 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8995 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8996 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8997 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8998 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8999 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9000 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9001 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9002 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9003 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9005 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9006 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9008 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9009 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9011 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9012 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9013 | AARCH64_FEATURE_DOTPROD
9014 | AARCH64_FEATURE_SSBS
),
9016 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9017 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9018 | AARCH64_FEATURE_DOTPROD
9019 | AARCH64_FEATURE_SSBS
),
9021 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9022 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9023 | AARCH64_FEATURE_DOTPROD
9024 | AARCH64_FEATURE_SSBS
),
9026 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9027 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9028 | AARCH64_FEATURE_DOTPROD
9029 | AARCH64_FEATURE_SSBS
),
9031 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9033 | AARCH64_FEATURE_RCPC
9034 | AARCH64_FEATURE_DOTPROD
9035 | AARCH64_FEATURE_SSBS
9036 | AARCH64_FEATURE_PROFILE
),
9038 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9040 | AARCH64_FEATURE_RCPC
9041 | AARCH64_FEATURE_DOTPROD
9042 | AARCH64_FEATURE_SSBS
9043 | AARCH64_FEATURE_PROFILE
),
9045 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9046 AARCH64_FEATURE_DOTPROD
9047 | AARCH64_FEATURE_F16
9048 | AARCH64_FEATURE_FLAGM
9049 | AARCH64_FEATURE_PAC
9050 | AARCH64_FEATURE_PROFILE
9051 | AARCH64_FEATURE_RCPC
9052 | AARCH64_FEATURE_SSBS
),
9054 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9055 AARCH64_FEATURE_BFLOAT16
9056 | AARCH64_FEATURE_I8MM
9057 | AARCH64_FEATURE_MEMTAG
9058 | AARCH64_FEATURE_SVE2_BITPERM
),
9060 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9061 AARCH64_FEATURE_BFLOAT16
9062 | AARCH64_FEATURE_I8MM
9063 | AARCH64_FEATURE_MEMTAG
9064 | AARCH64_FEATURE_SVE2_BITPERM
),
9066 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9067 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9068 | AARCH64_FEATURE_DOTPROD
9069 | AARCH64_FEATURE_PROFILE
),
9071 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9072 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9073 "Samsung Exynos M1"},
9074 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9075 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9076 | AARCH64_FEATURE_RDMA
),
9078 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9079 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9080 | AARCH64_FEATURE_DOTPROD
9081 | AARCH64_FEATURE_SSBS
),
9083 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9084 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9085 | AARCH64_FEATURE_DOTPROD
9086 | AARCH64_FEATURE_PROFILE
),
9088 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9089 AARCH64_FEATURE_BFLOAT16
9090 | AARCH64_FEATURE_I8MM
9091 | AARCH64_FEATURE_F16
9092 | AARCH64_FEATURE_SVE
9093 | AARCH64_FEATURE_SVE2
9094 | AARCH64_FEATURE_SVE2_BITPERM
9095 | AARCH64_FEATURE_MEMTAG
9096 | AARCH64_FEATURE_RNG
),
9098 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9099 AARCH64_FEATURE_PROFILE
9100 | AARCH64_FEATURE_CVADP
9101 | AARCH64_FEATURE_SVE
9102 | AARCH64_FEATURE_SSBS
9103 | AARCH64_FEATURE_RNG
9104 | AARCH64_FEATURE_F16
9105 | AARCH64_FEATURE_BFLOAT16
9106 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9107 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9108 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9109 | AARCH64_FEATURE_RDMA
),
9110 "Qualcomm QDF24XX"},
9111 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9112 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9113 "Qualcomm Saphira"},
9114 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9115 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9117 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9118 AARCH64_FEATURE_CRYPTO
),
9120 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9121 in earlier releases and is superseded by 'xgene1' in all
9123 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9124 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9125 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9126 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9127 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9128 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9130 | AARCH64_FEATURE_RCPC
9131 | AARCH64_FEATURE_DOTPROD
9132 | AARCH64_FEATURE_SSBS
9133 | AARCH64_FEATURE_PROFILE
),
9135 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9136 AARCH64_FEATURE_BFLOAT16
9137 | AARCH64_FEATURE_I8MM
9138 | AARCH64_FEATURE_MEMTAG
9139 | AARCH64_FEATURE_SVE2_BITPERM
),
9141 {"generic", AARCH64_ARCH_V8
, NULL
},
9143 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9146 struct aarch64_arch_option_table
9149 const aarch64_feature_set value
;
9152 /* This list should, at a minimum, contain all the architecture names
9153 recognized by GCC. */
9154 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9155 {"all", AARCH64_ANY
},
9156 {"armv8-a", AARCH64_ARCH_V8
},
9157 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9158 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9159 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9160 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9161 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9162 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9163 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9164 {"armv8-r", AARCH64_ARCH_V8_R
},
9165 {"armv9-a", AARCH64_ARCH_V9
},
9166 {NULL
, AARCH64_ARCH_NONE
}
9169 /* ISA extensions. */
9170 struct aarch64_option_cpu_value_table
9173 const aarch64_feature_set value
;
9174 const aarch64_feature_set require
; /* Feature dependencies. */
9177 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9178 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9180 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9181 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9182 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9184 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9186 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9187 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9188 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9190 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9192 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9194 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9195 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9196 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9197 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9198 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9199 AARCH64_FEATURE (AARCH64_FEATURE_FP
9200 | AARCH64_FEATURE_F16
, 0)},
9201 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9203 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9204 AARCH64_FEATURE (AARCH64_FEATURE_F16
9205 | AARCH64_FEATURE_SIMD
9206 | AARCH64_FEATURE_COMPNUM
, 0)},
9207 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9209 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9210 AARCH64_FEATURE (AARCH64_FEATURE_F16
9211 | AARCH64_FEATURE_SIMD
, 0)},
9212 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9214 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9216 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9218 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9220 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9222 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9224 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9226 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9227 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9228 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9230 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9232 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9234 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9235 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9236 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9237 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9238 | AARCH64_FEATURE_SM4
, 0)},
9239 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9240 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9241 | AARCH64_FEATURE_AES
, 0)},
9242 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9243 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9244 | AARCH64_FEATURE_SHA3
, 0)},
9245 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9246 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9247 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
9248 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9249 | AARCH64_FEATURE_BFLOAT16
, 0)},
9250 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
9251 AARCH64_FEATURE (AARCH64_FEATURE_SME
9252 | AARCH64_FEATURE_SVE2
9253 | AARCH64_FEATURE_BFLOAT16
, 0)},
9254 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
9255 AARCH64_FEATURE (AARCH64_FEATURE_SME
9256 | AARCH64_FEATURE_SVE2
9257 | AARCH64_FEATURE_BFLOAT16
, 0)},
9258 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9260 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9262 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9263 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9264 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9265 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9266 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9268 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9270 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9272 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9275 struct aarch64_long_option_table
9277 const char *option
; /* Substring to match. */
9278 const char *help
; /* Help information. */
9279 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9280 char *deprecated
; /* If non-null, print this message. */
9283 /* Transitive closure of features depending on set. */
9284 static aarch64_feature_set
9285 aarch64_feature_disable_set (aarch64_feature_set set
)
9287 const struct aarch64_option_cpu_value_table
*opt
;
9288 aarch64_feature_set prev
= 0;
9290 while (prev
!= set
) {
9292 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9293 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9294 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9299 /* Transitive closure of dependencies of set. */
9300 static aarch64_feature_set
9301 aarch64_feature_enable_set (aarch64_feature_set set
)
9303 const struct aarch64_option_cpu_value_table
*opt
;
9304 aarch64_feature_set prev
= 0;
9306 while (prev
!= set
) {
9308 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9309 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9310 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9316 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9319 /* We insist on extensions being added before being removed. We achieve
9320 this by using the ADDING_VALUE variable to indicate whether we are
9321 adding an extension (1) or removing it (0) and only allowing it to
9322 change in the order -1 -> 1 -> 0. */
9323 int adding_value
= -1;
9324 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9326 /* Copy the feature set, so that we can modify it. */
9330 while (str
!= NULL
&& *str
!= 0)
9332 const struct aarch64_option_cpu_value_table
*opt
;
9333 const char *ext
= NULL
;
9340 as_bad (_("invalid architectural extension"));
9344 ext
= strchr (++str
, '+');
9350 optlen
= strlen (str
);
9352 if (optlen
>= 2 && startswith (str
, "no"))
9354 if (adding_value
!= 0)
9359 else if (optlen
> 0)
9361 if (adding_value
== -1)
9363 else if (adding_value
!= 1)
9365 as_bad (_("must specify extensions to add before specifying "
9366 "those to remove"));
9373 as_bad (_("missing architectural extension"));
9377 gas_assert (adding_value
!= -1);
9379 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9380 if (strncmp (opt
->name
, str
, optlen
) == 0)
9382 aarch64_feature_set set
;
9384 /* Add or remove the extension. */
9387 set
= aarch64_feature_enable_set (opt
->value
);
9388 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9392 set
= aarch64_feature_disable_set (opt
->value
);
9393 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9398 if (opt
->name
== NULL
)
9400 as_bad (_("unknown architectural extension `%s'"), str
);
9411 aarch64_parse_cpu (const char *str
)
9413 const struct aarch64_cpu_option_table
*opt
;
9414 const char *ext
= strchr (str
, '+');
9420 optlen
= strlen (str
);
9424 as_bad (_("missing cpu name `%s'"), str
);
9428 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9429 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9431 mcpu_cpu_opt
= &opt
->value
;
9433 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
9438 as_bad (_("unknown cpu `%s'"), str
);
9443 aarch64_parse_arch (const char *str
)
9445 const struct aarch64_arch_option_table
*opt
;
9446 const char *ext
= strchr (str
, '+');
9452 optlen
= strlen (str
);
9456 as_bad (_("missing architecture name `%s'"), str
);
9460 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9461 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9463 march_cpu_opt
= &opt
->value
;
9465 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
9470 as_bad (_("unknown architecture `%s'\n"), str
);
9475 struct aarch64_option_abi_value_table
9478 enum aarch64_abi_type value
;
9481 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9482 {"ilp32", AARCH64_ABI_ILP32
},
9483 {"lp64", AARCH64_ABI_LP64
},
9487 aarch64_parse_abi (const char *str
)
9493 as_bad (_("missing abi name `%s'"), str
);
9497 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9498 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9500 aarch64_abi
= aarch64_abis
[i
].value
;
9504 as_bad (_("unknown abi `%s'\n"), str
);
9508 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9510 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9511 aarch64_parse_abi
, NULL
},
9512 #endif /* OBJ_ELF */
9513 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9514 aarch64_parse_cpu
, NULL
},
9515 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9516 aarch64_parse_arch
, NULL
},
9517 {NULL
, NULL
, 0, NULL
}
9521 md_parse_option (int c
, const char *arg
)
9523 struct aarch64_option_table
*opt
;
9524 struct aarch64_long_option_table
*lopt
;
9530 target_big_endian
= 1;
9536 target_big_endian
= 0;
9541 /* Listing option. Just ignore these, we don't support additional
9546 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9548 if (c
== opt
->option
[0]
9549 && ((arg
== NULL
&& opt
->option
[1] == 0)
9550 || streq (arg
, opt
->option
+ 1)))
9552 /* If the option is deprecated, tell the user. */
9553 if (opt
->deprecated
!= NULL
)
9554 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9555 arg
? arg
: "", _(opt
->deprecated
));
9557 if (opt
->var
!= NULL
)
9558 *opt
->var
= opt
->value
;
9564 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9566 /* These options are expected to have an argument. */
9567 if (c
== lopt
->option
[0]
9569 && startswith (arg
, lopt
->option
+ 1))
9571 /* If the option is deprecated, tell the user. */
9572 if (lopt
->deprecated
!= NULL
)
9573 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9574 _(lopt
->deprecated
));
9576 /* Call the sup-option parser. */
9577 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9588 md_show_usage (FILE * fp
)
9590 struct aarch64_option_table
*opt
;
9591 struct aarch64_long_option_table
*lopt
;
9593 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9595 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9596 if (opt
->help
!= NULL
)
9597 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9599 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9600 if (lopt
->help
!= NULL
)
9601 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9605 -EB assemble code for a big-endian cpu\n"));
9610 -EL assemble code for a little-endian cpu\n"));
9614 /* Parse a .cpu directive. */
9617 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9619 const struct aarch64_cpu_option_table
*opt
;
9625 name
= input_line_pointer
;
9626 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9627 input_line_pointer
++;
9628 saved_char
= *input_line_pointer
;
9629 *input_line_pointer
= 0;
9631 ext
= strchr (name
, '+');
9634 optlen
= ext
- name
;
9636 optlen
= strlen (name
);
9638 /* Skip the first "all" entry. */
9639 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9640 if (strlen (opt
->name
) == optlen
9641 && strncmp (name
, opt
->name
, optlen
) == 0)
9643 mcpu_cpu_opt
= &opt
->value
;
9645 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
9648 cpu_variant
= *mcpu_cpu_opt
;
9650 *input_line_pointer
= saved_char
;
9651 demand_empty_rest_of_line ();
9654 as_bad (_("unknown cpu `%s'"), name
);
9655 *input_line_pointer
= saved_char
;
9656 ignore_rest_of_line ();
9660 /* Parse a .arch directive. */
9663 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9665 const struct aarch64_arch_option_table
*opt
;
9671 name
= input_line_pointer
;
9672 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9673 input_line_pointer
++;
9674 saved_char
= *input_line_pointer
;
9675 *input_line_pointer
= 0;
9677 ext
= strchr (name
, '+');
9680 optlen
= ext
- name
;
9682 optlen
= strlen (name
);
9684 /* Skip the first "all" entry. */
9685 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9686 if (strlen (opt
->name
) == optlen
9687 && strncmp (name
, opt
->name
, optlen
) == 0)
9689 mcpu_cpu_opt
= &opt
->value
;
9691 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
9694 cpu_variant
= *mcpu_cpu_opt
;
9696 *input_line_pointer
= saved_char
;
9697 demand_empty_rest_of_line ();
9701 as_bad (_("unknown architecture `%s'\n"), name
);
9702 *input_line_pointer
= saved_char
;
9703 ignore_rest_of_line ();
9706 /* Parse a .arch_extension directive. */
9709 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9712 char *ext
= input_line_pointer
;;
9714 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9715 input_line_pointer
++;
9716 saved_char
= *input_line_pointer
;
9717 *input_line_pointer
= 0;
9719 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
9722 cpu_variant
= *mcpu_cpu_opt
;
9724 *input_line_pointer
= saved_char
;
9725 demand_empty_rest_of_line ();
9728 /* Copy symbol information. */
9731 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9733 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9737 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9738 This is needed so AArch64 specific st_other values can be independently
9739 specified for an IFUNC resolver (that is called by the dynamic linker)
9740 and the symbol it resolves (aliased to the resolver). In particular,
9741 if a function symbol has special st_other value set via directives,
9742 then attaching an IFUNC resolver to that symbol should not override
9743 the st_other setting. Requiring the directive on the IFUNC resolver
9744 symbol would be unexpected and problematic in C code, where the two
9745 symbols appear as two independent function declarations. */
9748 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9750 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9751 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9754 if (destelf
->size
== NULL
)
9755 destelf
->size
= XNEW (expressionS
);
9756 *destelf
->size
= *srcelf
->size
;
9760 free (destelf
->size
);
9761 destelf
->size
= NULL
;
9763 S_SET_SIZE (dest
, S_GET_SIZE (src
));