1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame unwind info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* SME horizontal or vertical slice indicator, encoded in "V".
128 /* Bits for DEFINED field in vector_type_el. */
129 #define NTA_HASTYPE 1
130 #define NTA_HASINDEX 2
131 #define NTA_HASVARWIDTH 4
133 struct vector_type_el
135 enum vector_el_type type
;
136 unsigned char defined
;
141 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
145 bfd_reloc_code_real_type type
;
148 enum aarch64_opnd opnd
;
150 unsigned need_libopcodes_p
: 1;
153 struct aarch64_instruction
155 /* libopcodes structure for instruction intermediate representation. */
157 /* Record assembly errors found during the parsing. */
160 enum aarch64_operand_error_kind kind
;
163 /* The condition that appears in the assembly line. */
165 /* Relocation information (including the GAS internal fixup). */
167 /* Need to generate an immediate in the literal pool. */
168 unsigned gen_lit_pool
: 1;
171 typedef struct aarch64_instruction aarch64_instruction
;
173 static aarch64_instruction inst
;
175 static bool parse_operands (char *, const aarch64_opcode
*);
176 static bool programmer_friendly_fixup (aarch64_instruction
*);
178 /* Diagnostics inline function utilities.
180 These are lightweight utilities which should only be called by parse_operands
181 and other parsers. GAS processes each assembly line by parsing it against
182 instruction template(s), in the case of multiple templates (for the same
183 mnemonic name), those templates are tried one by one until one succeeds or
184 all fail. An assembly line may fail a few templates before being
185 successfully parsed; an error saved here in most cases is not a user error
186 but an error indicating the current template is not the right template.
187 Therefore it is very important that errors can be saved at a low cost during
188 the parsing; we don't want to slow down the whole parsing by recording
189 non-user errors in detail.
191 Remember that the objective is to help GAS pick up the most appropriate
192 error message in the case of multiple templates, e.g. FMOV which has 8
198 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
199 inst
.parsing_error
.error
= NULL
;
205 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
208 static inline const char *
209 get_error_message (void)
211 return inst
.parsing_error
.error
;
214 static inline enum aarch64_operand_error_kind
215 get_error_kind (void)
217 return inst
.parsing_error
.kind
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 inst
.parsing_error
.kind
= kind
;
224 inst
.parsing_error
.error
= error
;
228 set_recoverable_error (const char *error
)
230 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
233 /* Use the DESC field of the corresponding aarch64_operand entry to compose
234 the error message. */
236 set_default_error (void)
238 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
242 set_syntax_error (const char *error
)
244 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
248 set_first_syntax_error (const char *error
)
251 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
255 set_fatal_syntax_error (const char *error
)
257 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
260 /* Return value for certain parsers when the parsing fails; those parsers
261 return the information of the parsed result, e.g. register number, on
263 #define PARSE_FAIL -1
265 /* This is an invalid condition code that means no conditional field is
267 #define COND_ALWAYS 0x10
271 const char *template;
278 bfd_reloc_code_real_type reloc
;
281 /* Macros to define the register types and masks for the purpose
284 #undef AARCH64_REG_TYPES
285 #define AARCH64_REG_TYPES \
286 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
287 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
288 BASIC_REG_TYPE(SP_32) /* wsp */ \
289 BASIC_REG_TYPE(SP_64) /* sp */ \
290 BASIC_REG_TYPE(Z_32) /* wzr */ \
291 BASIC_REG_TYPE(Z_64) /* xzr */ \
292 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
293 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
294 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
295 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
296 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
297 BASIC_REG_TYPE(VN) /* v[0-31] */ \
298 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
299 BASIC_REG_TYPE(PN) /* p[0-15] */ \
300 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
301 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
302 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
303 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
304 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
305 /* Typecheck: same, plus SVE registers. */ \
306 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
308 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
309 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
310 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
311 /* Typecheck: same, plus SVE registers. */ \
312 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
315 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
316 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
317 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
318 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
319 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
320 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
321 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
322 /* Typecheck: any [BHSDQ]P FP. */ \
323 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
325 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
326 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
328 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
329 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
330 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
331 be used for SVE instructions, since Zn and Pn are valid symbols \
332 in other contexts. */ \
333 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
334 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
335 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
336 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
337 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
338 | REG_TYPE(ZN) | REG_TYPE(PN)) \
339 /* Any integer register; used for error messages only. */ \
340 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
341 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
342 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
343 /* Pseudo type to mark the end of the enumerator sequence. */ \
346 #undef BASIC_REG_TYPE
347 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
348 #undef MULTI_REG_TYPE
349 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
351 /* Register type enumerators. */
352 typedef enum aarch64_reg_type_
354 /* A list of REG_TYPE_*. */
358 #undef BASIC_REG_TYPE
359 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
361 #define REG_TYPE(T) (1 << REG_TYPE_##T)
362 #undef MULTI_REG_TYPE
363 #define MULTI_REG_TYPE(T,V) V,
365 /* Structure for a hash table entry for a register. */
369 unsigned char number
;
370 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
371 unsigned char builtin
;
374 /* Values indexed by aarch64_reg_type to assist the type checking. */
375 static const unsigned reg_type_masks
[] =
380 #undef BASIC_REG_TYPE
382 #undef MULTI_REG_TYPE
383 #undef AARCH64_REG_TYPES
385 /* Diagnostics used when we don't get a register of the expected type.
386 Note: this has to synchronized with aarch64_reg_type definitions
389 get_reg_expected_msg (aarch64_reg_type reg_type
)
396 msg
= N_("integer 32-bit register expected");
399 msg
= N_("integer 64-bit register expected");
402 msg
= N_("integer register expected");
404 case REG_TYPE_R64_SP
:
405 msg
= N_("64-bit integer or SP register expected");
407 case REG_TYPE_SVE_BASE
:
408 msg
= N_("base register expected");
411 msg
= N_("integer or zero register expected");
413 case REG_TYPE_SVE_OFFSET
:
414 msg
= N_("offset register expected");
417 msg
= N_("integer or SP register expected");
419 case REG_TYPE_R_Z_SP
:
420 msg
= N_("integer, zero or SP register expected");
423 msg
= N_("8-bit SIMD scalar register expected");
426 msg
= N_("16-bit SIMD scalar or floating-point half precision "
427 "register expected");
430 msg
= N_("32-bit SIMD scalar or floating-point single precision "
431 "register expected");
434 msg
= N_("64-bit SIMD scalar or floating-point double precision "
435 "register expected");
438 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
439 "register expected");
441 case REG_TYPE_R_Z_BHSDQ_V
:
442 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
443 msg
= N_("register expected");
445 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
446 msg
= N_("SIMD scalar or floating-point register expected");
448 case REG_TYPE_VN
: /* any V reg */
449 msg
= N_("vector register expected");
452 msg
= N_("SVE vector register expected");
455 msg
= N_("SVE predicate register expected");
458 as_fatal (_("invalid register type %d"), reg_type
);
463 /* Some well known registers that we refer to directly elsewhere. */
467 /* Instructions take 4 bytes in the object file. */
470 static htab_t aarch64_ops_hsh
;
471 static htab_t aarch64_cond_hsh
;
472 static htab_t aarch64_shift_hsh
;
473 static htab_t aarch64_sys_regs_hsh
;
474 static htab_t aarch64_pstatefield_hsh
;
475 static htab_t aarch64_sys_regs_ic_hsh
;
476 static htab_t aarch64_sys_regs_dc_hsh
;
477 static htab_t aarch64_sys_regs_at_hsh
;
478 static htab_t aarch64_sys_regs_tlbi_hsh
;
479 static htab_t aarch64_sys_regs_sr_hsh
;
480 static htab_t aarch64_reg_hsh
;
481 static htab_t aarch64_barrier_opt_hsh
;
482 static htab_t aarch64_nzcv_hsh
;
483 static htab_t aarch64_pldop_hsh
;
484 static htab_t aarch64_hint_opt_hsh
;
486 /* Stuff needed to resolve the label ambiguity
495 static symbolS
*last_label_seen
;
497 /* Literal pool structure. Held on a per-section
498 and per-sub-section basis. */
500 #define MAX_LITERAL_POOL_SIZE 1024
501 typedef struct literal_expression
504 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
505 LITTLENUM_TYPE
* bignum
;
506 } literal_expression
;
508 typedef struct literal_pool
510 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
511 unsigned int next_free_entry
;
517 struct literal_pool
*next
;
520 /* Pointer to a linked list of literal pools. */
521 static literal_pool
*list_of_pools
= NULL
;
525 /* This array holds the chars that always start a comment. If the
526 pre-processor is disabled, these aren't very useful. */
527 const char comment_chars
[] = "";
529 /* This array holds the chars that only start a comment at the beginning of
530 a line. If the line seems to have the form '# 123 filename'
531 .line and .file directives will appear in the pre-processed output. */
532 /* Note that input_file.c hand checks for '#' at the beginning of the
533 first line of the input file. This is because the compiler outputs
534 #NO_APP at the beginning of its output. */
535 /* Also note that comments like this one will always work. */
536 const char line_comment_chars
[] = "#";
538 const char line_separator_chars
[] = ";";
540 /* Chars that can be used to separate mant
541 from exp in floating point numbers. */
542 const char EXP_CHARS
[] = "eE";
544 /* Chars that mean this number is a floating point constant. */
548 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
550 /* Prefix character that indicates the start of an immediate value. */
551 #define is_immediate_prefix(C) ((C) == '#')
553 /* Separator character handling. */
555 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
558 skip_past_char (char **str
, char c
)
569 #define skip_past_comma(str) skip_past_char (str, ',')
571 /* Arithmetic expressions (possibly involving symbols). */
573 static bool in_aarch64_get_expression
= false;
575 /* Third argument to aarch64_get_expression. */
576 #define GE_NO_PREFIX false
577 #define GE_OPT_PREFIX true
579 /* Fourth argument to aarch64_get_expression. */
580 #define ALLOW_ABSENT false
581 #define REJECT_ABSENT true
583 /* Return TRUE if the string pointed by *STR is successfully parsed
584 as an valid expression; *EP will be filled with the information of
585 such an expression. Otherwise return FALSE.
587 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
588 If REJECT_ABSENT is true then trat missing expressions as an error. */
591 aarch64_get_expression (expressionS
* ep
,
593 bool allow_immediate_prefix
,
598 bool prefix_present
= false;
600 if (allow_immediate_prefix
)
602 if (is_immediate_prefix (**str
))
605 prefix_present
= true;
609 memset (ep
, 0, sizeof (expressionS
));
611 save_in
= input_line_pointer
;
612 input_line_pointer
= *str
;
613 in_aarch64_get_expression
= true;
614 seg
= expression (ep
);
615 in_aarch64_get_expression
= false;
617 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
619 /* We found a bad expression in md_operand(). */
620 *str
= input_line_pointer
;
621 input_line_pointer
= save_in
;
622 if (prefix_present
&& ! error_p ())
623 set_fatal_syntax_error (_("bad expression"));
625 set_first_syntax_error (_("bad expression"));
630 if (seg
!= absolute_section
631 && seg
!= text_section
632 && seg
!= data_section
633 && seg
!= bss_section
634 && seg
!= undefined_section
)
636 set_syntax_error (_("bad segment"));
637 *str
= input_line_pointer
;
638 input_line_pointer
= save_in
;
645 *str
= input_line_pointer
;
646 input_line_pointer
= save_in
;
650 /* Turn a string in input_line_pointer into a floating point constant
651 of type TYPE, and store the appropriate bytes in *LITP. The number
652 of LITTLENUMS emitted is stored in *SIZEP. An error message is
653 returned, or NULL on OK. */
656 md_atof (int type
, char *litP
, int *sizeP
)
658 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
661 /* We handle all bad expressions here, so that we can report the faulty
662 instruction in the error message. */
664 md_operand (expressionS
* exp
)
666 if (in_aarch64_get_expression
)
667 exp
->X_op
= O_illegal
;
670 /* Immediate values. */
672 /* Errors may be set multiple times during parsing or bit encoding
673 (particularly in the Neon bits), but usually the earliest error which is set
674 will be the most meaningful. Avoid overwriting it with later (cascading)
675 errors by calling this function. */
678 first_error (const char *error
)
681 set_syntax_error (error
);
684 /* Similar to first_error, but this function accepts formatted error
687 first_error_fmt (const char *format
, ...)
692 /* N.B. this single buffer will not cause error messages for different
693 instructions to pollute each other; this is because at the end of
694 processing of each assembly line, error message if any will be
695 collected by as_bad. */
696 static char buffer
[size
];
700 int ret ATTRIBUTE_UNUSED
;
701 va_start (args
, format
);
702 ret
= vsnprintf (buffer
, size
, format
, args
);
703 know (ret
<= size
- 1 && ret
>= 0);
705 set_syntax_error (buffer
);
709 /* Register parsing. */
711 /* Generic register parser which is called by other specialized
713 CCP points to what should be the beginning of a register name.
714 If it is indeed a valid register name, advance CCP over it and
715 return the reg_entry structure; otherwise return NULL.
716 It does not issue diagnostics. */
719 parse_reg (char **ccp
)
725 #ifdef REGISTER_PREFIX
726 if (*start
!= REGISTER_PREFIX
)
732 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
737 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
739 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
748 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
751 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
753 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
756 /* Try to parse a base or offset register. Allow SVE base and offset
757 registers if REG_TYPE includes SVE registers. Return the register
758 entry on success, setting *QUALIFIER to the register qualifier.
759 Return null otherwise.
761 Note that this function does not issue any diagnostics. */
763 static const reg_entry
*
764 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
765 aarch64_opnd_qualifier_t
*qualifier
)
768 const reg_entry
*reg
= parse_reg (&str
);
778 *qualifier
= AARCH64_OPND_QLF_W
;
784 *qualifier
= AARCH64_OPND_QLF_X
;
788 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
791 switch (TOLOWER (str
[1]))
794 *qualifier
= AARCH64_OPND_QLF_S_S
;
797 *qualifier
= AARCH64_OPND_QLF_S_D
;
814 /* Try to parse a base or offset register. Return the register entry
815 on success, setting *QUALIFIER to the register qualifier. Return null
818 Note that this function does not issue any diagnostics. */
820 static const reg_entry
*
821 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
823 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
826 /* Parse the qualifier of a vector register or vector element of type
827 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
828 succeeds; otherwise return FALSE.
830 Accept only one occurrence of:
831 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
834 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
835 struct vector_type_el
*parsed_type
, char **str
)
839 unsigned element_size
;
840 enum vector_el_type type
;
843 gas_assert (*ptr
== '.');
846 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
851 width
= strtoul (ptr
, &ptr
, 10);
852 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
854 first_error_fmt (_("bad size %d in vector width specifier"), width
);
859 switch (TOLOWER (*ptr
))
878 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
887 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
889 first_error (_("missing element size"));
892 if (width
!= 0 && width
* element_size
!= 64
893 && width
* element_size
!= 128
894 && !(width
== 2 && element_size
== 16)
895 && !(width
== 4 && element_size
== 8))
898 ("invalid element size %d and vector size combination %c"),
904 parsed_type
->type
= type
;
905 parsed_type
->width
= width
;
912 /* *STR contains an SVE zero/merge predication suffix. Parse it into
913 *PARSED_TYPE and point *STR at the end of the suffix. */
916 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
921 gas_assert (*ptr
== '/');
923 switch (TOLOWER (*ptr
))
926 parsed_type
->type
= NT_zero
;
929 parsed_type
->type
= NT_merge
;
932 if (*ptr
!= '\0' && *ptr
!= ',')
933 first_error_fmt (_("unexpected character `%c' in predication type"),
936 first_error (_("missing predication type"));
939 parsed_type
->width
= 0;
944 /* Parse a register of the type TYPE.
946 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
947 name or the parsed register is not of TYPE.
949 Otherwise return the register number, and optionally fill in the actual
950 type of the register in *RTYPE when multiple alternatives were given, and
951 return the register shape and element index information in *TYPEINFO.
953 IN_REG_LIST should be set with TRUE if the caller is parsing a register
957 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
958 struct vector_type_el
*typeinfo
, bool in_reg_list
)
961 const reg_entry
*reg
= parse_reg (&str
);
962 struct vector_type_el atype
;
963 struct vector_type_el parsetype
;
964 bool is_typed_vecreg
= false;
967 atype
.type
= NT_invtype
;
975 set_default_error ();
979 if (! aarch64_check_reg_type (reg
, type
))
981 DEBUG_TRACE ("reg type check failed");
982 set_default_error ();
987 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
988 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
992 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
997 if (!parse_predication_for_operand (&parsetype
, &str
))
1001 /* Register if of the form Vn.[bhsdq]. */
1002 is_typed_vecreg
= true;
1004 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1006 /* The width is always variable; we don't allow an integer width
1008 gas_assert (parsetype
.width
== 0);
1009 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1011 else if (parsetype
.width
== 0)
1012 /* Expect index. In the new scheme we cannot have
1013 Vn.[bhsdq] represent a scalar. Therefore any
1014 Vn.[bhsdq] should have an index following it.
1015 Except in reglists of course. */
1016 atype
.defined
|= NTA_HASINDEX
;
1018 atype
.defined
|= NTA_HASTYPE
;
1020 atype
.type
= parsetype
.type
;
1021 atype
.width
= parsetype
.width
;
1024 if (skip_past_char (&str
, '['))
1028 /* Reject Sn[index] syntax. */
1029 if (!is_typed_vecreg
)
1031 first_error (_("this type of register can't be indexed"));
1037 first_error (_("index not allowed inside register list"));
1041 atype
.defined
|= NTA_HASINDEX
;
1043 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1045 if (exp
.X_op
!= O_constant
)
1047 first_error (_("constant expression required"));
1051 if (! skip_past_char (&str
, ']'))
1054 atype
.index
= exp
.X_add_number
;
1056 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1058 /* Indexed vector register expected. */
1059 first_error (_("indexed vector register expected"));
1063 /* A vector reg Vn should be typed or indexed. */
1064 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1066 first_error (_("invalid use of vector register"));
1082 Return the register number on success; return PARSE_FAIL otherwise.
1084 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1085 the register (e.g. NEON double or quad reg when either has been requested).
1087 If this is a NEON vector register with additional type information, fill
1088 in the struct pointed to by VECTYPE (if non-NULL).
1090 This parser does not handle register list. */
1093 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1094 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1096 struct vector_type_el atype
;
1098 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1099 /*in_reg_list= */ false);
1101 if (reg
== PARSE_FAIL
)
1113 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1117 && e1
.defined
== e2
.defined
1118 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1121 /* This function parses a list of vector registers of type TYPE.
1122 On success, it returns the parsed register list information in the
1123 following encoded format:
1125 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1126 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1128 The information of the register shape and/or index is returned in
1131 It returns PARSE_FAIL if the register list is invalid.
1133 The list contains one to four registers.
1134 Each register can be one of:
1137 All <T> should be identical.
1138 All <index> should be identical.
1139 There are restrictions on <Vt> numbers which are checked later
1140 (by reg_list_valid_p). */
1143 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1144 struct vector_type_el
*vectype
)
1148 struct vector_type_el typeinfo
, typeinfo_first
;
1154 bool expect_index
= false;
1158 set_syntax_error (_("expecting {"));
1164 typeinfo_first
.defined
= 0;
1165 typeinfo_first
.type
= NT_invtype
;
1166 typeinfo_first
.width
= -1;
1167 typeinfo_first
.index
= 0;
1176 str
++; /* skip over '-' */
1179 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1180 /*in_reg_list= */ true);
1181 if (val
== PARSE_FAIL
)
1183 set_first_syntax_error (_("invalid vector register in list"));
1187 /* reject [bhsd]n */
1188 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1190 set_first_syntax_error (_("invalid scalar register in list"));
1195 if (typeinfo
.defined
& NTA_HASINDEX
)
1196 expect_index
= true;
1200 if (val
< val_range
)
1202 set_first_syntax_error
1203 (_("invalid range in vector register list"));
1212 typeinfo_first
= typeinfo
;
1213 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1215 set_first_syntax_error
1216 (_("type mismatch in vector register list"));
1221 for (i
= val_range
; i
<= val
; i
++)
1223 ret_val
|= i
<< (5 * nb_regs
);
1228 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1230 skip_whitespace (str
);
1233 set_first_syntax_error (_("end of vector register list not found"));
1238 skip_whitespace (str
);
1242 if (skip_past_char (&str
, '['))
1246 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1247 if (exp
.X_op
!= O_constant
)
1249 set_first_syntax_error (_("constant expression required."));
1252 if (! skip_past_char (&str
, ']'))
1255 typeinfo_first
.index
= exp
.X_add_number
;
1259 set_first_syntax_error (_("expected index"));
1266 set_first_syntax_error (_("too many registers in vector register list"));
1269 else if (nb_regs
== 0)
1271 set_first_syntax_error (_("empty vector register list"));
1277 *vectype
= typeinfo_first
;
1279 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1282 /* Directives: register aliases. */
1285 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1290 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1293 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1296 /* Only warn about a redefinition if it's not defined as the
1298 else if (new->number
!= number
|| new->type
!= type
)
1299 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1304 name
= xstrdup (str
);
1305 new = XNEW (reg_entry
);
1308 new->number
= number
;
1310 new->builtin
= false;
1312 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1317 /* Look for the .req directive. This is of the form:
1319 new_register_name .req existing_register_name
1321 If we find one, or if it looks sufficiently like one that we want to
1322 handle any error here, return TRUE. Otherwise return FALSE. */
1325 create_register_alias (char *newname
, char *p
)
1327 const reg_entry
*old
;
1328 char *oldname
, *nbuf
;
1331 /* The input scrubber ensures that whitespace after the mnemonic is
1332 collapsed to single spaces. */
1334 if (!startswith (oldname
, " .req "))
1338 if (*oldname
== '\0')
1341 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1344 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1348 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1349 the desired alias name, and p points to its end. If not, then
1350 the desired alias name is in the global original_case_string. */
1351 #ifdef TC_CASE_SENSITIVE
1354 newname
= original_case_string
;
1355 nlen
= strlen (newname
);
1358 nbuf
= xmemdup0 (newname
, nlen
);
1360 /* Create aliases under the new name as stated; an all-lowercase
1361 version of the new name; and an all-uppercase version of the new
1363 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1365 for (p
= nbuf
; *p
; p
++)
1368 if (strncmp (nbuf
, newname
, nlen
))
1370 /* If this attempt to create an additional alias fails, do not bother
1371 trying to create the all-lower case alias. We will fail and issue
1372 a second, duplicate error message. This situation arises when the
1373 programmer does something like:
1376 The second .req creates the "Foo" alias but then fails to create
1377 the artificial FOO alias because it has already been created by the
1379 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1386 for (p
= nbuf
; *p
; p
++)
1389 if (strncmp (nbuf
, newname
, nlen
))
1390 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1397 /* Should never be called, as .req goes between the alias and the
1398 register name, not at the beginning of the line. */
1400 s_req (int a ATTRIBUTE_UNUSED
)
1402 as_bad (_("invalid syntax for .req directive"));
1405 /* The .unreq directive deletes an alias which was previously defined
1406 by .req. For example:
1412 s_unreq (int a ATTRIBUTE_UNUSED
)
1417 name
= input_line_pointer
;
1418 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1419 saved_char
= *input_line_pointer
;
1420 *input_line_pointer
= 0;
1423 as_bad (_("invalid syntax for .unreq directive"));
1426 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1429 as_bad (_("unknown register alias '%s'"), name
);
1430 else if (reg
->builtin
)
1431 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1438 str_hash_delete (aarch64_reg_hsh
, name
);
1439 free ((char *) reg
->name
);
1442 /* Also locate the all upper case and all lower case versions.
1443 Do not complain if we cannot find one or the other as it
1444 was probably deleted above. */
1446 nbuf
= strdup (name
);
1447 for (p
= nbuf
; *p
; p
++)
1449 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1452 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1453 free ((char *) reg
->name
);
1457 for (p
= nbuf
; *p
; p
++)
1459 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1462 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1463 free ((char *) reg
->name
);
1471 *input_line_pointer
= saved_char
;
1472 demand_empty_rest_of_line ();
1475 /* Directives: Instruction set selection. */
1477 #if defined OBJ_ELF || defined OBJ_COFF
1478 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1479 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1480 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1481 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1483 /* Create a new mapping symbol for the transition to STATE. */
1486 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1489 const char *symname
;
1496 type
= BSF_NO_FLAGS
;
1500 type
= BSF_NO_FLAGS
;
1506 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1507 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1509 /* Save the mapping symbols for future reference. Also check that
1510 we do not place two mapping symbols at the same offset within a
1511 frag. We'll handle overlap between frags in
1512 check_mapping_symbols.
1514 If .fill or other data filling directive generates zero sized data,
1515 the mapping symbol for the following code will have the same value
1516 as the one generated for the data filling directive. In this case,
1517 we replace the old symbol with the new one at the same address. */
1520 if (frag
->tc_frag_data
.first_map
!= NULL
)
1522 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1523 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1526 frag
->tc_frag_data
.first_map
= symbolP
;
1528 if (frag
->tc_frag_data
.last_map
!= NULL
)
1530 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1531 S_GET_VALUE (symbolP
));
1532 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1533 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1536 frag
->tc_frag_data
.last_map
= symbolP
;
1539 /* We must sometimes convert a region marked as code to data during
1540 code alignment, if an odd number of bytes have to be padded. The
1541 code mapping symbol is pushed to an aligned address. */
1544 insert_data_mapping_symbol (enum mstate state
,
1545 valueT value
, fragS
* frag
, offsetT bytes
)
1547 /* If there was already a mapping symbol, remove it. */
1548 if (frag
->tc_frag_data
.last_map
!= NULL
1549 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1550 frag
->fr_address
+ value
)
1552 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1556 know (frag
->tc_frag_data
.first_map
== symp
);
1557 frag
->tc_frag_data
.first_map
= NULL
;
1559 frag
->tc_frag_data
.last_map
= NULL
;
1560 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1563 make_mapping_symbol (MAP_DATA
, value
, frag
);
1564 make_mapping_symbol (state
, value
+ bytes
, frag
);
1567 static void mapping_state_2 (enum mstate state
, int max_chars
);
1569 /* Set the mapping state to STATE. Only call this when about to
1570 emit some STATE bytes to the file. */
1573 mapping_state (enum mstate state
)
1575 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1577 if (state
== MAP_INSN
)
1578 /* AArch64 instructions require 4-byte alignment. When emitting
1579 instructions into any section, record the appropriate section
1581 record_alignment (now_seg
, 2);
1583 if (mapstate
== state
)
1584 /* The mapping symbol has already been emitted.
1585 There is nothing else to do. */
1588 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1589 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1590 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1591 evaluated later in the next else. */
1593 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1595 /* Only add the symbol if the offset is > 0:
1596 if we're at the first frag, check it's size > 0;
1597 if we're not at the first frag, then for sure
1598 the offset is > 0. */
1599 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1600 const int add_symbol
= (frag_now
!= frag_first
)
1601 || (frag_now_fix () > 0);
1604 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1608 mapping_state_2 (state
, 0);
1611 /* Same as mapping_state, but MAX_CHARS bytes have already been
1612 allocated. Put the mapping symbol that far back. */
1615 mapping_state_2 (enum mstate state
, int max_chars
)
1617 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1619 if (!SEG_NORMAL (now_seg
))
1622 if (mapstate
== state
)
1623 /* The mapping symbol has already been emitted.
1624 There is nothing else to do. */
1627 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1628 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1631 #define mapping_state(x) /* nothing */
1632 #define mapping_state_2(x, y) /* nothing */
1635 /* Directives: sectioning and alignment. */
1638 s_bss (int ignore ATTRIBUTE_UNUSED
)
1640 /* We don't support putting frags in the BSS segment, we fake it by
1641 marking in_bss, then looking at s_skip for clues. */
1642 subseg_set (bss_section
, 0);
1643 demand_empty_rest_of_line ();
1644 mapping_state (MAP_DATA
);
1648 s_even (int ignore ATTRIBUTE_UNUSED
)
1650 /* Never make frag if expect extra pass. */
1652 frag_align (1, 0, 0);
1654 record_alignment (now_seg
, 1);
1656 demand_empty_rest_of_line ();
1659 /* Directives: Literal pools. */
1661 static literal_pool
*
1662 find_literal_pool (int size
)
1666 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1668 if (pool
->section
== now_seg
1669 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1676 static literal_pool
*
1677 find_or_make_literal_pool (int size
)
1679 /* Next literal pool ID number. */
1680 static unsigned int latest_pool_num
= 1;
1683 pool
= find_literal_pool (size
);
1687 /* Create a new pool. */
1688 pool
= XNEW (literal_pool
);
1692 /* Currently we always put the literal pool in the current text
1693 section. If we were generating "small" model code where we
1694 knew that all code and initialised data was within 1MB then
1695 we could output literals to mergeable, read-only data
1698 pool
->next_free_entry
= 0;
1699 pool
->section
= now_seg
;
1700 pool
->sub_section
= now_subseg
;
1702 pool
->next
= list_of_pools
;
1703 pool
->symbol
= NULL
;
1705 /* Add it to the list. */
1706 list_of_pools
= pool
;
1709 /* New pools, and emptied pools, will have a NULL symbol. */
1710 if (pool
->symbol
== NULL
)
1712 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1713 &zero_address_frag
, 0);
1714 pool
->id
= latest_pool_num
++;
1721 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1722 Return TRUE on success, otherwise return FALSE. */
1724 add_to_lit_pool (expressionS
*exp
, int size
)
1729 pool
= find_or_make_literal_pool (size
);
1731 /* Check if this literal value is already in the pool. */
1732 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1734 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1736 if ((litexp
->X_op
== exp
->X_op
)
1737 && (exp
->X_op
== O_constant
)
1738 && (litexp
->X_add_number
== exp
->X_add_number
)
1739 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1742 if ((litexp
->X_op
== exp
->X_op
)
1743 && (exp
->X_op
== O_symbol
)
1744 && (litexp
->X_add_number
== exp
->X_add_number
)
1745 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1746 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1750 /* Do we need to create a new entry? */
1751 if (entry
== pool
->next_free_entry
)
1753 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1755 set_syntax_error (_("literal pool overflow"));
1759 pool
->literals
[entry
].exp
= *exp
;
1760 pool
->next_free_entry
+= 1;
1761 if (exp
->X_op
== O_big
)
1763 /* PR 16688: Bignums are held in a single global array. We must
1764 copy and preserve that value now, before it is overwritten. */
1765 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1767 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1768 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1771 pool
->literals
[entry
].bignum
= NULL
;
1774 exp
->X_op
= O_symbol
;
1775 exp
->X_add_number
= ((int) entry
) * size
;
1776 exp
->X_add_symbol
= pool
->symbol
;
1781 /* Can't use symbol_new here, so have to create a symbol and then at
1782 a later date assign it a value. That's what these functions do. */
1785 symbol_locate (symbolS
* symbolP
,
1786 const char *name
,/* It is copied, the caller can modify. */
1787 segT segment
, /* Segment identifier (SEG_<something>). */
1788 valueT valu
, /* Symbol value. */
1789 fragS
* frag
) /* Associated fragment. */
1792 char *preserved_copy_of_name
;
1794 name_length
= strlen (name
) + 1; /* +1 for \0. */
1795 obstack_grow (¬es
, name
, name_length
);
1796 preserved_copy_of_name
= obstack_finish (¬es
);
1798 #ifdef tc_canonicalize_symbol_name
1799 preserved_copy_of_name
=
1800 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1803 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1805 S_SET_SEGMENT (symbolP
, segment
);
1806 S_SET_VALUE (symbolP
, valu
);
1807 symbol_clear_list_pointers (symbolP
);
1809 symbol_set_frag (symbolP
, frag
);
1811 /* Link to end of symbol chain. */
1813 extern int symbol_table_frozen
;
1815 if (symbol_table_frozen
)
1819 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1821 obj_symbol_new_hook (symbolP
);
1823 #ifdef tc_symbol_new_hook
1824 tc_symbol_new_hook (symbolP
);
1828 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1829 #endif /* DEBUG_SYMS */
1834 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1841 for (align
= 2; align
<= 4; align
++)
1843 int size
= 1 << align
;
1845 pool
= find_literal_pool (size
);
1846 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1849 /* Align pool as you have word accesses.
1850 Only make a frag if we have to. */
1852 frag_align (align
, 0, 0);
1854 mapping_state (MAP_DATA
);
1856 record_alignment (now_seg
, align
);
1858 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1860 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1861 (valueT
) frag_now_fix (), frag_now
);
1862 symbol_table_insert (pool
->symbol
);
1864 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1866 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1868 if (exp
->X_op
== O_big
)
1870 /* PR 16688: Restore the global bignum value. */
1871 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1872 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1873 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1876 /* First output the expression in the instruction to the pool. */
1877 emit_expr (exp
, size
); /* .word|.xword */
1879 if (exp
->X_op
== O_big
)
1881 free (pool
->literals
[entry
].bignum
);
1882 pool
->literals
[entry
].bignum
= NULL
;
1886 /* Mark the pool as empty. */
1887 pool
->next_free_entry
= 0;
1888 pool
->symbol
= NULL
;
1892 #if defined(OBJ_ELF) || defined(OBJ_COFF)
1893 /* Forward declarations for functions below, in the MD interface
1895 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1897 /* Directives: Data. */
1898 /* N.B. the support for relocation suffix in this directive needs to be
1899 implemented properly. */
1902 s_aarch64_cons (int nbytes
)
1906 #ifdef md_flush_pending_output
1907 md_flush_pending_output ();
1910 if (is_it_end_of_statement ())
1912 demand_empty_rest_of_line ();
1916 #ifdef md_cons_align
1917 md_cons_align (nbytes
);
1920 mapping_state (MAP_DATA
);
1923 struct reloc_table_entry
*reloc
;
1927 if (exp
.X_op
!= O_symbol
)
1928 emit_expr (&exp
, (unsigned int) nbytes
);
1931 skip_past_char (&input_line_pointer
, '#');
1932 if (skip_past_char (&input_line_pointer
, ':'))
1934 reloc
= find_reloc_table_entry (&input_line_pointer
);
1936 as_bad (_("unrecognized relocation suffix"));
1938 as_bad (_("unimplemented relocation suffix"));
1939 ignore_rest_of_line ();
1943 emit_expr (&exp
, (unsigned int) nbytes
);
1946 while (*input_line_pointer
++ == ',');
1948 /* Put terminator back into stream. */
1949 input_line_pointer
--;
1950 demand_empty_rest_of_line ();
1955 /* Forward declarations for functions below, in the MD interface
1957 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1959 /* Mark symbol that it follows a variant PCS convention. */
1962 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1968 elf_symbol_type
*elfsym
;
1970 c
= get_symbol_name (&name
);
1972 as_bad (_("Missing symbol name in directive"));
1973 sym
= symbol_find_or_make (name
);
1974 restore_line_pointer (c
);
1975 demand_empty_rest_of_line ();
1976 bfdsym
= symbol_get_bfdsym (sym
);
1977 elfsym
= elf_symbol_from (bfdsym
);
1978 gas_assert (elfsym
);
1979 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1981 #endif /* OBJ_ELF */
1983 /* Output a 32-bit word, but mark as an instruction. */
1986 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1991 #ifdef md_flush_pending_output
1992 md_flush_pending_output ();
1995 if (is_it_end_of_statement ())
1997 demand_empty_rest_of_line ();
2001 /* Sections are assumed to start aligned. In executable section, there is no
2002 MAP_DATA symbol pending. So we only align the address during
2003 MAP_DATA --> MAP_INSN transition.
2004 For other sections, this is not guaranteed. */
2005 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2006 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2007 frag_align_code (2, 0);
2010 mapping_state (MAP_INSN
);
2016 if (exp
.X_op
!= O_constant
)
2018 as_bad (_("constant expression required"));
2019 ignore_rest_of_line ();
2023 if (target_big_endian
)
2025 unsigned int val
= exp
.X_add_number
;
2026 exp
.X_add_number
= SWAP_32 (val
);
2028 emit_expr (&exp
, INSN_SIZE
);
2031 while (*input_line_pointer
++ == ',');
2033 dwarf2_emit_insn (n
* INSN_SIZE
);
2035 /* Put terminator back into stream. */
2036 input_line_pointer
--;
2037 demand_empty_rest_of_line ();
2041 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2043 demand_empty_rest_of_line ();
2044 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2045 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2049 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2052 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2058 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2059 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2061 demand_empty_rest_of_line ();
2064 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2067 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2071 /* Since we're just labelling the code, there's no need to define a
2074 /* Make sure there is enough room in this frag for the following
2075 blr. This trick only works if the blr follows immediately after
2076 the .tlsdesc directive. */
2078 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2079 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2081 demand_empty_rest_of_line ();
2084 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2087 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2093 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2094 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2096 demand_empty_rest_of_line ();
2098 #endif /* OBJ_ELF */
2102 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2109 if (exp
.X_op
== O_symbol
)
2110 exp
.X_op
= O_secrel
;
2112 emit_expr (&exp
, 4);
2114 while (*input_line_pointer
++ == ',');
2116 input_line_pointer
--;
2117 demand_empty_rest_of_line ();
2121 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2125 exp
.X_op
= O_secrel
;
2126 exp
.X_add_symbol
= symbol
;
2127 exp
.X_add_number
= 0;
2128 emit_expr (&exp
, size
);
2132 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2139 if (exp
.X_op
== O_symbol
)
2140 exp
.X_op
= O_secidx
;
2142 emit_expr (&exp
, 2);
2144 while (*input_line_pointer
++ == ',');
2146 input_line_pointer
--;
2147 demand_empty_rest_of_line ();
2151 static void s_aarch64_arch (int);
2152 static void s_aarch64_cpu (int);
2153 static void s_aarch64_arch_extension (int);
2155 /* This table describes all the machine specific pseudo-ops the assembler
2156 has to support. The fields are:
2157 pseudo-op name without dot
2158 function to call to execute this pseudo-op
2159 Integer arg to pass to the function. */
2161 const pseudo_typeS md_pseudo_table
[] = {
2162 /* Never called because '.req' does not start a line. */
2164 {"unreq", s_unreq
, 0},
2166 {"even", s_even
, 0},
2167 {"ltorg", s_ltorg
, 0},
2168 {"pool", s_ltorg
, 0},
2169 {"cpu", s_aarch64_cpu
, 0},
2170 {"arch", s_aarch64_arch
, 0},
2171 {"arch_extension", s_aarch64_arch_extension
, 0},
2172 {"inst", s_aarch64_inst
, 0},
2173 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2175 {"tlsdescadd", s_tlsdescadd
, 0},
2176 {"tlsdesccall", s_tlsdesccall
, 0},
2177 {"tlsdescldr", s_tlsdescldr
, 0},
2178 {"variant_pcs", s_variant_pcs
, 0},
2180 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2181 {"word", s_aarch64_cons
, 4},
2182 {"long", s_aarch64_cons
, 4},
2183 {"xword", s_aarch64_cons
, 8},
2184 {"dword", s_aarch64_cons
, 8},
2187 {"secrel32", s_secrel
, 0},
2188 {"secidx", s_secidx
, 0},
2190 {"float16", float_cons
, 'h'},
2191 {"bfloat16", float_cons
, 'b'},
2196 /* Check whether STR points to a register name followed by a comma or the
2197 end of line; REG_TYPE indicates which register types are checked
2198 against. Return TRUE if STR is such a register name; otherwise return
2199 FALSE. The function does not intend to produce any diagnostics, but since
2200 the register parser aarch64_reg_parse, which is called by this function,
2201 does produce diagnostics, we call clear_error to clear any diagnostics
2202 that may be generated by aarch64_reg_parse.
2203 Also, the function returns FALSE directly if there is any user error
2204 present at the function entry. This prevents the existing diagnostics
2205 state from being spoiled.
2206 The function currently serves parse_constant_immediate and
2207 parse_big_immediate only. */
2209 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2213 /* Prevent the diagnostics state from being spoiled. */
2217 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2219 /* Clear the parsing error that may be set by the reg parser. */
2222 if (reg
== PARSE_FAIL
)
2225 skip_whitespace (str
);
2226 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2232 /* Parser functions used exclusively in instruction operands. */
2234 /* Parse an immediate expression which may not be constant.
2236 To prevent the expression parser from pushing a register name
2237 into the symbol table as an undefined symbol, firstly a check is
2238 done to find out whether STR is a register of type REG_TYPE followed
2239 by a comma or the end of line. Return FALSE if STR is such a string. */
2242 parse_immediate_expression (char **str
, expressionS
*exp
,
2243 aarch64_reg_type reg_type
)
2245 if (reg_name_p (*str
, reg_type
))
2247 set_recoverable_error (_("immediate operand required"));
2251 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2253 if (exp
->X_op
== O_absent
)
2255 set_fatal_syntax_error (_("missing immediate expression"));
2262 /* Constant immediate-value read function for use in insn parsing.
2263 STR points to the beginning of the immediate (with the optional
2264 leading #); *VAL receives the value. REG_TYPE says which register
2265 names should be treated as registers rather than as symbolic immediates.
2267 Return TRUE on success; otherwise return FALSE. */
2270 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2274 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2277 if (exp
.X_op
!= O_constant
)
2279 set_syntax_error (_("constant expression required"));
2283 *val
= exp
.X_add_number
;
2288 encode_imm_float_bits (uint32_t imm
)
2290 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2291 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2294 /* Return TRUE if the single-precision floating-point value encoded in IMM
2295 can be expressed in the AArch64 8-bit signed floating-point format with
2296 3-bit exponent and normalized 4 bits of precision; in other words, the
2297 floating-point value must be expressable as
2298 (+/-) n / 16 * power (2, r)
2299 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2302 aarch64_imm_float_p (uint32_t imm
)
2304 /* If a single-precision floating-point value has the following bit
2305 pattern, it can be expressed in the AArch64 8-bit floating-point
2308 3 32222222 2221111111111
2309 1 09876543 21098765432109876543210
2310 n Eeeeeexx xxxx0000000000000000000
2312 where n, e and each x are either 0 or 1 independently, with
2317 /* Prepare the pattern for 'Eeeeee'. */
2318 if (((imm
>> 30) & 0x1) == 0)
2319 pattern
= 0x3e000000;
2321 pattern
= 0x40000000;
2323 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2324 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2327 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2328 as an IEEE float without any loss of precision. Store the value in
2332 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2334 /* If a double-precision floating-point value has the following bit
2335 pattern, it can be expressed in a float:
2337 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2338 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2339 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2341 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2342 if Eeee_eeee != 1111_1111
2344 where n, e, s and S are either 0 or 1 independently and where ~ is the
2348 uint32_t high32
= imm
>> 32;
2349 uint32_t low32
= imm
;
2351 /* Lower 29 bits need to be 0s. */
2352 if ((imm
& 0x1fffffff) != 0)
2355 /* Prepare the pattern for 'Eeeeeeeee'. */
2356 if (((high32
>> 30) & 0x1) == 0)
2357 pattern
= 0x38000000;
2359 pattern
= 0x40000000;
2362 if ((high32
& 0x78000000) != pattern
)
2365 /* Check Eeee_eeee != 1111_1111. */
2366 if ((high32
& 0x7ff00000) == 0x47f00000)
2369 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2370 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2371 | (low32
>> 29)); /* 3 S bits. */
2375 /* Return true if we should treat OPERAND as a double-precision
2376 floating-point operand rather than a single-precision one. */
2378 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2380 /* Check for unsuffixed SVE registers, which are allowed
2381 for LDR and STR but not in instructions that require an
2382 immediate. We get better error messages if we arbitrarily
2383 pick one size, parse the immediate normally, and then
2384 report the match failure in the normal way. */
2385 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2386 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2389 /* Parse a floating-point immediate. Return TRUE on success and return the
2390 value in *IMMED in the format of IEEE754 single-precision encoding.
2391 *CCP points to the start of the string; DP_P is TRUE when the immediate
2392 is expected to be in double-precision (N.B. this only matters when
2393 hexadecimal representation is involved). REG_TYPE says which register
2394 names should be treated as registers rather than as symbolic immediates.
2396 This routine accepts any IEEE float; it is up to the callers to reject
2400 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2401 aarch64_reg_type reg_type
)
2405 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2407 unsigned fpword
= 0;
2410 skip_past_char (&str
, '#');
2413 skip_whitespace (fpnum
);
2415 if (startswith (fpnum
, "0x"))
2417 /* Support the hexadecimal representation of the IEEE754 encoding.
2418 Double-precision is expected when DP_P is TRUE, otherwise the
2419 representation should be in single-precision. */
2420 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2425 if (!can_convert_double_to_float (val
, &fpword
))
2428 else if ((uint64_t) val
> 0xffffffff)
2435 else if (reg_name_p (str
, reg_type
))
2437 set_recoverable_error (_("immediate operand required"));
2445 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2448 /* Our FP word must be 32 bits (single-precision FP). */
2449 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2451 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2461 set_fatal_syntax_error (_("invalid floating-point constant"));
2465 /* Less-generic immediate-value read function with the possibility of loading
2466 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2469 To prevent the expression parser from pushing a register name into the
2470 symbol table as an undefined symbol, a check is firstly done to find
2471 out whether STR is a register of type REG_TYPE followed by a comma or
2472 the end of line. Return FALSE if STR is such a register. */
2475 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2479 if (reg_name_p (ptr
, reg_type
))
2481 set_syntax_error (_("immediate operand required"));
2485 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2487 if (inst
.reloc
.exp
.X_op
== O_constant
)
2488 *imm
= inst
.reloc
.exp
.X_add_number
;
2495 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2496 if NEED_LIBOPCODES is non-zero, the fixup will need
2497 assistance from the libopcodes. */
2500 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2501 const aarch64_opnd_info
*operand
,
2502 int need_libopcodes_p
)
2504 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2505 reloc
->opnd
= operand
->type
;
2506 if (need_libopcodes_p
)
2507 reloc
->need_libopcodes_p
= 1;
2510 /* Return TRUE if the instruction needs to be fixed up later internally by
2511 the GAS; otherwise return FALSE. */
2514 aarch64_gas_internal_fixup_p (void)
2516 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2519 /* Assign the immediate value to the relevant field in *OPERAND if
2520 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2521 needs an internal fixup in a later stage.
2522 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2523 IMM.VALUE that may get assigned with the constant. */
2525 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2526 aarch64_opnd_info
*operand
,
2528 int need_libopcodes_p
,
2531 if (reloc
->exp
.X_op
== O_constant
)
2534 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2536 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2537 reloc
->type
= BFD_RELOC_UNUSED
;
2541 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2542 /* Tell libopcodes to ignore this operand or not. This is helpful
2543 when one of the operands needs to be fixed up later but we need
2544 libopcodes to check the other operands. */
2545 operand
->skip
= skip_p
;
2549 /* Relocation modifiers. Each entry in the table contains the textual
2550 name for the relocation which may be placed before a symbol used as
2551 a load/store offset, or add immediate. It must be surrounded by a
2552 leading and trailing colon, for example:
2554 ldr x0, [x1, #:rello:varsym]
2555 add x0, x1, #:rello:varsym */
2557 struct reloc_table_entry
2561 bfd_reloc_code_real_type adr_type
;
2562 bfd_reloc_code_real_type adrp_type
;
2563 bfd_reloc_code_real_type movw_type
;
2564 bfd_reloc_code_real_type add_type
;
2565 bfd_reloc_code_real_type ldst_type
;
2566 bfd_reloc_code_real_type ld_literal_type
;
2569 static struct reloc_table_entry reloc_table
[] =
2571 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2576 BFD_RELOC_AARCH64_ADD_LO12
,
2577 BFD_RELOC_AARCH64_LDST_LO12
,
2580 /* Higher 21 bits of pc-relative page offset: ADRP */
2583 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2589 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2592 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2598 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2602 BFD_RELOC_AARCH64_MOVW_G0
,
2607 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2611 BFD_RELOC_AARCH64_MOVW_G0_S
,
2616 /* Less significant bits 0-15 of address/value: MOVK, no check */
2620 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2625 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2629 BFD_RELOC_AARCH64_MOVW_G1
,
2634 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2638 BFD_RELOC_AARCH64_MOVW_G1_S
,
2643 /* Less significant bits 16-31 of address/value: MOVK, no check */
2647 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2652 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2656 BFD_RELOC_AARCH64_MOVW_G2
,
2661 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2665 BFD_RELOC_AARCH64_MOVW_G2_S
,
2670 /* Less significant bits 32-47 of address/value: MOVK, no check */
2674 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2679 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2683 BFD_RELOC_AARCH64_MOVW_G3
,
2688 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2692 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2697 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2701 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2706 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2710 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2715 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2719 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2724 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2728 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2733 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2737 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2742 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2746 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2751 /* Get to the page containing GOT entry for a symbol. */
2754 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2758 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2760 /* 12 bit offset into the page containing GOT entry for that symbol. */
2766 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2769 /* 0-15 bits of address/value: MOVk, no check. */
2773 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2778 /* Most significant bits 16-31 of address/value: MOVZ. */
2782 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2787 /* 15 bit offset into the page containing GOT entry for that symbol. */
2793 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2796 /* Get to the page containing GOT TLS entry for a symbol */
2797 {"gottprel_g0_nc", 0,
2800 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2805 /* Get to the page containing GOT TLS entry for a symbol */
2809 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2814 /* Get to the page containing GOT TLS entry for a symbol */
2816 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2817 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2823 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2828 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2832 /* Lower 16 bits address/value: MOVk. */
2836 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2841 /* Most significant bits 16-31 of address/value: MOVZ. */
2845 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2850 /* Get to the page containing GOT TLS entry for a symbol */
2852 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2853 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2857 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2859 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2864 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2865 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2868 /* Get to the page containing GOT TLS entry for a symbol.
2869 The same as GD, we allocate two consecutive GOT slots
2870 for module index and module offset, the only difference
2871 with GD is the module offset should be initialized to
2872 zero without any outstanding runtime relocation. */
2874 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2875 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2881 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2882 {"tlsldm_lo12_nc", 0,
2886 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2890 /* 12 bit offset into the module TLS base address. */
2895 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2896 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2899 /* Same as dtprel_lo12, no overflow check. */
2900 {"dtprel_lo12_nc", 0,
2904 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2905 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2908 /* bits[23:12] of offset to the module TLS base address. */
2913 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2917 /* bits[15:0] of offset to the module TLS base address. */
2921 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2926 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2930 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2935 /* bits[31:16] of offset to the module TLS base address. */
2939 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2944 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2948 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2953 /* bits[47:32] of offset to the module TLS base address. */
2957 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2962 /* Lower 16 bit offset into GOT entry for a symbol */
2963 {"tlsdesc_off_g0_nc", 0,
2966 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2971 /* Higher 16 bit offset into GOT entry for a symbol */
2972 {"tlsdesc_off_g1", 0,
2975 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2980 /* Get to the page containing GOT TLS entry for a symbol */
2983 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2987 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2989 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2990 {"gottprel_lo12", 0,
2995 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2998 /* Get tp offset for a symbol. */
3003 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3007 /* Get tp offset for a symbol. */
3012 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3013 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3016 /* Get tp offset for a symbol. */
3021 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3025 /* Get tp offset for a symbol. */
3026 {"tprel_lo12_nc", 0,
3030 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3031 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3034 /* Most significant bits 32-47 of address/value: MOVZ. */
3038 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3043 /* Most significant bits 16-31 of address/value: MOVZ. */
3047 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3052 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3056 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3061 /* Most significant bits 0-15 of address/value: MOVZ. */
3065 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3070 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3074 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3079 /* 15bit offset from got entry to base address of GOT table. */
3085 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3088 /* 14bit offset from got entry to base address of GOT table. */
3094 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3098 /* Given the address of a pointer pointing to the textual name of a
3099 relocation as may appear in assembler source, attempt to find its
3100 details in reloc_table. The pointer will be updated to the character
3101 after the trailing colon. On failure, NULL will be returned;
3102 otherwise return the reloc_table_entry. */
3104 static struct reloc_table_entry
*
3105 find_reloc_table_entry (char **str
)
3108 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3110 int length
= strlen (reloc_table
[i
].name
);
3112 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3113 && (*str
)[length
] == ':')
3115 *str
+= (length
+ 1);
3116 return &reloc_table
[i
];
3123 /* Returns 0 if the relocation should never be forced,
3124 1 if the relocation must be forced, and -1 if either
3128 aarch64_force_reloc (unsigned int type
)
3132 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3133 /* Perform these "immediate" internal relocations
3134 even if the symbol is extern or weak. */
3137 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3138 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3139 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3140 /* Pseudo relocs that need to be fixed up according to
3144 case BFD_RELOC_AARCH64_ADD_LO12
:
3145 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3146 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3147 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3148 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3149 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3150 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3151 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3152 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3153 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3154 case BFD_RELOC_AARCH64_LDST128_LO12
:
3155 case BFD_RELOC_AARCH64_LDST16_LO12
:
3156 case BFD_RELOC_AARCH64_LDST32_LO12
:
3157 case BFD_RELOC_AARCH64_LDST64_LO12
:
3158 case BFD_RELOC_AARCH64_LDST8_LO12
:
3159 case BFD_RELOC_AARCH64_LDST_LO12
:
3160 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3161 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3162 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3163 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3164 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3165 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3166 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3167 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3168 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3169 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3170 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3171 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3172 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3173 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3174 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3175 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3176 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3177 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3178 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3179 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3180 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3181 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3182 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3183 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3184 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3185 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3186 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3187 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3188 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3189 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3190 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3191 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3192 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3193 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3194 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3195 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3196 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3197 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3198 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3199 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3200 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3201 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3202 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3203 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3204 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3205 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3206 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3207 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3208 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3209 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3210 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3211 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3212 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3213 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3214 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3215 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3216 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3217 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3218 /* Always leave these relocations for the linker. */
3227 aarch64_force_relocation (struct fix
*fixp
)
3229 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3232 return generic_force_reloc (fixp
);
3236 /* Mode argument to parse_shift and parser_shifter_operand. */
3237 enum parse_shift_mode
3239 SHIFTED_NONE
, /* no shifter allowed */
3240 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3242 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3244 SHIFTED_LSL
, /* bare "lsl #n" */
3245 SHIFTED_MUL
, /* bare "mul #n" */
3246 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3247 SHIFTED_MUL_VL
, /* "mul vl" */
3248 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3251 /* Parse a <shift> operator on an AArch64 data processing instruction.
3252 Return TRUE on success; otherwise return FALSE. */
3254 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3256 const struct aarch64_name_value_pair
*shift_op
;
3257 enum aarch64_modifier_kind kind
;
3263 for (p
= *str
; ISALPHA (*p
); p
++)
3268 set_syntax_error (_("shift expression expected"));
3272 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3274 if (shift_op
== NULL
)
3276 set_syntax_error (_("shift operator expected"));
3280 kind
= aarch64_get_operand_modifier (shift_op
);
3282 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3284 set_syntax_error (_("invalid use of 'MSL'"));
3288 if (kind
== AARCH64_MOD_MUL
3289 && mode
!= SHIFTED_MUL
3290 && mode
!= SHIFTED_MUL_VL
)
3292 set_syntax_error (_("invalid use of 'MUL'"));
3298 case SHIFTED_LOGIC_IMM
:
3299 if (aarch64_extend_operator_p (kind
))
3301 set_syntax_error (_("extending shift is not permitted"));
3306 case SHIFTED_ARITH_IMM
:
3307 if (kind
== AARCH64_MOD_ROR
)
3309 set_syntax_error (_("'ROR' shift is not permitted"));
3315 if (kind
!= AARCH64_MOD_LSL
)
3317 set_syntax_error (_("only 'LSL' shift is permitted"));
3323 if (kind
!= AARCH64_MOD_MUL
)
3325 set_syntax_error (_("only 'MUL' is permitted"));
3330 case SHIFTED_MUL_VL
:
3331 /* "MUL VL" consists of two separate tokens. Require the first
3332 token to be "MUL" and look for a following "VL". */
3333 if (kind
== AARCH64_MOD_MUL
)
3335 skip_whitespace (p
);
3336 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3339 kind
= AARCH64_MOD_MUL_VL
;
3343 set_syntax_error (_("only 'MUL VL' is permitted"));
3346 case SHIFTED_REG_OFFSET
:
3347 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3348 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3350 set_fatal_syntax_error
3351 (_("invalid shift for the register offset addressing mode"));
3356 case SHIFTED_LSL_MSL
:
3357 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3359 set_syntax_error (_("invalid shift operator"));
3368 /* Whitespace can appear here if the next thing is a bare digit. */
3369 skip_whitespace (p
);
3371 /* Parse shift amount. */
3373 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3374 exp
.X_op
= O_absent
;
3377 if (is_immediate_prefix (*p
))
3382 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3384 if (kind
== AARCH64_MOD_MUL_VL
)
3385 /* For consistency, give MUL VL the same shift amount as an implicit
3387 operand
->shifter
.amount
= 1;
3388 else if (exp
.X_op
== O_absent
)
3390 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3392 set_syntax_error (_("missing shift amount"));
3395 operand
->shifter
.amount
= 0;
3397 else if (exp
.X_op
!= O_constant
)
3399 set_syntax_error (_("constant shift amount required"));
3402 /* For parsing purposes, MUL #n has no inherent range. The range
3403 depends on the operand and will be checked by operand-specific
3405 else if (kind
!= AARCH64_MOD_MUL
3406 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3408 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3413 operand
->shifter
.amount
= exp
.X_add_number
;
3414 operand
->shifter
.amount_present
= 1;
3417 operand
->shifter
.operator_present
= 1;
3418 operand
->shifter
.kind
= kind
;
3424 /* Parse a <shifter_operand> for a data processing instruction:
3427 #<immediate>, LSL #imm
3429 Validation of immediate operands is deferred to md_apply_fix.
3431 Return TRUE on success; otherwise return FALSE. */
3434 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3435 enum parse_shift_mode mode
)
3439 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3444 /* Accept an immediate expression. */
3445 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3449 /* Accept optional LSL for arithmetic immediate values. */
3450 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3451 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3454 /* Not accept any shifter for logical immediate values. */
3455 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3456 && parse_shift (&p
, operand
, mode
))
3458 set_syntax_error (_("unexpected shift operator"));
3466 /* Parse a <shifter_operand> for a data processing instruction:
3471 #<immediate>, LSL #imm
3473 where <shift> is handled by parse_shift above, and the last two
3474 cases are handled by the function above.
3476 Validation of immediate operands is deferred to md_apply_fix.
3478 Return TRUE on success; otherwise return FALSE. */
3481 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3482 enum parse_shift_mode mode
)
3484 const reg_entry
*reg
;
3485 aarch64_opnd_qualifier_t qualifier
;
3486 enum aarch64_operand_class opd_class
3487 = aarch64_get_operand_class (operand
->type
);
3489 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3492 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3494 set_syntax_error (_("unexpected register in the immediate operand"));
3498 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3500 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3504 operand
->reg
.regno
= reg
->number
;
3505 operand
->qualifier
= qualifier
;
3507 /* Accept optional shift operation on register. */
3508 if (! skip_past_comma (str
))
3511 if (! parse_shift (str
, operand
, mode
))
3516 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3519 (_("integer register expected in the extended/shifted operand "
3524 /* We have a shifted immediate variable. */
3525 return parse_shifter_operand_imm (str
, operand
, mode
);
3528 /* Return TRUE on success; return FALSE otherwise. */
3531 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3532 enum parse_shift_mode mode
)
3536 /* Determine if we have the sequence of characters #: or just :
3537 coming next. If we do, then we check for a :rello: relocation
3538 modifier. If we don't, punt the whole lot to
3539 parse_shifter_operand. */
3541 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3543 struct reloc_table_entry
*entry
;
3551 /* Try to parse a relocation. Anything else is an error. */
3552 if (!(entry
= find_reloc_table_entry (str
)))
3554 set_syntax_error (_("unknown relocation modifier"));
3558 if (entry
->add_type
== 0)
3561 (_("this relocation modifier is not allowed on this instruction"));
3565 /* Save str before we decompose it. */
3568 /* Next, we parse the expression. */
3569 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3573 /* Record the relocation type (use the ADD variant here). */
3574 inst
.reloc
.type
= entry
->add_type
;
3575 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3577 /* If str is empty, we've reached the end, stop here. */
3581 /* Otherwise, we have a shifted reloc modifier, so rewind to
3582 recover the variable name and continue parsing for the shifter. */
3584 return parse_shifter_operand_imm (str
, operand
, mode
);
3587 return parse_shifter_operand (str
, operand
, mode
);
3590 /* Parse all forms of an address expression. Information is written
3591 to *OPERAND and/or inst.reloc.
3593 The A64 instruction set has the following addressing modes:
3596 [base] // in SIMD ld/st structure
3597 [base{,#0}] // in ld/st exclusive
3599 [base,Xm{,LSL #imm}]
3600 [base,Xm,SXTX {#imm}]
3601 [base,Wm,(S|U)XTW {#imm}]
3603 [base]! // in ldraa/ldrab exclusive
3607 [base],Xm // in SIMD ld/st structure
3608 PC-relative (literal)
3612 [base,Zm.D{,LSL #imm}]
3613 [base,Zm.S,(S|U)XTW {#imm}]
3614 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3618 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3619 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3620 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3622 (As a convenience, the notation "=immediate" is permitted in conjunction
3623 with the pc-relative literal load instructions to automatically place an
3624 immediate value or symbolic address in a nearby literal pool and generate
3625 a hidden label which references it.)
3627 Upon a successful parsing, the address structure in *OPERAND will be
3628 filled in the following way:
3630 .base_regno = <base>
3631 .offset.is_reg // 1 if the offset is a register
3633 .offset.regno = <Rm>
3635 For different addressing modes defined in the A64 ISA:
3638 .pcrel=0; .preind=1; .postind=0; .writeback=0
3640 .pcrel=0; .preind=1; .postind=0; .writeback=1
3642 .pcrel=0; .preind=0; .postind=1; .writeback=1
3643 PC-relative (literal)
3644 .pcrel=1; .preind=1; .postind=0; .writeback=0
3646 The shift/extension information, if any, will be stored in .shifter.
3647 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3648 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3649 corresponding register.
3651 BASE_TYPE says which types of base register should be accepted and
3652 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3653 is the type of shifter that is allowed for immediate offsets,
3654 or SHIFTED_NONE if none.
3656 In all other respects, it is the caller's responsibility to check
3657 for addressing modes not supported by the instruction, and to set
3661 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3662 aarch64_opnd_qualifier_t
*base_qualifier
,
3663 aarch64_opnd_qualifier_t
*offset_qualifier
,
3664 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3665 enum parse_shift_mode imm_shift_mode
)
3668 const reg_entry
*reg
;
3669 expressionS
*exp
= &inst
.reloc
.exp
;
3671 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3672 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3673 if (! skip_past_char (&p
, '['))
3675 /* =immediate or label. */
3676 operand
->addr
.pcrel
= 1;
3677 operand
->addr
.preind
= 1;
3679 /* #:<reloc_op>:<symbol> */
3680 skip_past_char (&p
, '#');
3681 if (skip_past_char (&p
, ':'))
3683 bfd_reloc_code_real_type ty
;
3684 struct reloc_table_entry
*entry
;
3686 /* Try to parse a relocation modifier. Anything else is
3688 entry
= find_reloc_table_entry (&p
);
3691 set_syntax_error (_("unknown relocation modifier"));
3695 switch (operand
->type
)
3697 case AARCH64_OPND_ADDR_PCREL21
:
3699 ty
= entry
->adr_type
;
3703 ty
= entry
->ld_literal_type
;
3710 (_("this relocation modifier is not allowed on this "
3716 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3718 set_syntax_error (_("invalid relocation expression"));
3721 /* #:<reloc_op>:<expr> */
3722 /* Record the relocation type. */
3723 inst
.reloc
.type
= ty
;
3724 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3728 if (skip_past_char (&p
, '='))
3729 /* =immediate; need to generate the literal in the literal pool. */
3730 inst
.gen_lit_pool
= 1;
3732 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3734 set_syntax_error (_("invalid address"));
3745 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3746 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3748 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3751 operand
->addr
.base_regno
= reg
->number
;
3754 if (skip_past_comma (&p
))
3757 operand
->addr
.preind
= 1;
3759 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3762 if (!aarch64_check_reg_type (reg
, offset_type
))
3764 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3769 operand
->addr
.offset
.regno
= reg
->number
;
3770 operand
->addr
.offset
.is_reg
= 1;
3771 /* Shifted index. */
3772 if (skip_past_comma (&p
))
3775 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3776 /* Use the diagnostics set in parse_shift, so not set new
3777 error message here. */
3781 [base,Xm] # For vector plus scalar SVE2 indexing.
3782 [base,Xm{,LSL #imm}]
3783 [base,Xm,SXTX {#imm}]
3784 [base,Wm,(S|U)XTW {#imm}] */
3785 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3786 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3787 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3789 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3791 set_syntax_error (_("invalid use of 32-bit register offset"));
3794 if (aarch64_get_qualifier_esize (*base_qualifier
)
3795 != aarch64_get_qualifier_esize (*offset_qualifier
)
3796 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3797 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3798 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3800 set_syntax_error (_("offset has different size from base"));
3804 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3806 set_syntax_error (_("invalid use of 64-bit register offset"));
3812 /* [Xn,#:<reloc_op>:<symbol> */
3813 skip_past_char (&p
, '#');
3814 if (skip_past_char (&p
, ':'))
3816 struct reloc_table_entry
*entry
;
3818 /* Try to parse a relocation modifier. Anything else is
3820 if (!(entry
= find_reloc_table_entry (&p
)))
3822 set_syntax_error (_("unknown relocation modifier"));
3826 if (entry
->ldst_type
== 0)
3829 (_("this relocation modifier is not allowed on this "
3834 /* [Xn,#:<reloc_op>: */
3835 /* We now have the group relocation table entry corresponding to
3836 the name in the assembler source. Next, we parse the
3838 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3840 set_syntax_error (_("invalid relocation expression"));
3844 /* [Xn,#:<reloc_op>:<expr> */
3845 /* Record the load/store relocation type. */
3846 inst
.reloc
.type
= entry
->ldst_type
;
3847 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3851 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3853 set_syntax_error (_("invalid expression in the address"));
3857 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3858 /* [Xn,<expr>,<shifter> */
3859 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3865 if (! skip_past_char (&p
, ']'))
3867 set_syntax_error (_("']' expected"));
3871 if (skip_past_char (&p
, '!'))
3873 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3875 set_syntax_error (_("register offset not allowed in pre-indexed "
3876 "addressing mode"));
3880 operand
->addr
.writeback
= 1;
3882 else if (skip_past_comma (&p
))
3885 operand
->addr
.postind
= 1;
3886 operand
->addr
.writeback
= 1;
3888 if (operand
->addr
.preind
)
3890 set_syntax_error (_("cannot combine pre- and post-indexing"));
3894 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3898 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3900 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3904 operand
->addr
.offset
.regno
= reg
->number
;
3905 operand
->addr
.offset
.is_reg
= 1;
3907 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3910 set_syntax_error (_("invalid expression in the address"));
3915 /* If at this point neither .preind nor .postind is set, we have a
3916 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3917 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3918 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3920 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3922 if (operand
->addr
.writeback
)
3924 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3926 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3927 operand
->addr
.offset
.is_reg
= 0;
3928 operand
->addr
.offset
.imm
= 0;
3929 operand
->addr
.preind
= 1;
3934 set_syntax_error (_("missing offset in the pre-indexed address"));
3940 operand
->addr
.preind
= 1;
3941 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3943 operand
->addr
.offset
.is_reg
= 1;
3944 operand
->addr
.offset
.regno
= REG_ZR
;
3945 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3949 inst
.reloc
.exp
.X_op
= O_constant
;
3950 inst
.reloc
.exp
.X_add_number
= 0;
3959 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3962 parse_address (char **str
, aarch64_opnd_info
*operand
)
3964 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3965 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3966 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3969 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3970 The arguments have the same meaning as for parse_address_main.
3971 Return TRUE on success. */
3973 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3974 aarch64_opnd_qualifier_t
*base_qualifier
,
3975 aarch64_opnd_qualifier_t
*offset_qualifier
)
3977 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3978 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3982 /* Parse a register X0-X30. The register must be 64-bit and register 31
3985 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
3987 const reg_entry
*reg
= parse_reg (str
);
3988 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3990 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3993 operand
->reg
.regno
= reg
->number
;
3994 operand
->qualifier
= AARCH64_OPND_QLF_X
;
3998 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3999 Return TRUE on success; otherwise return FALSE. */
4001 parse_half (char **str
, int *internal_fixup_p
)
4005 skip_past_char (&p
, '#');
4007 gas_assert (internal_fixup_p
);
4008 *internal_fixup_p
= 0;
4012 struct reloc_table_entry
*entry
;
4014 /* Try to parse a relocation. Anything else is an error. */
4017 if (!(entry
= find_reloc_table_entry (&p
)))
4019 set_syntax_error (_("unknown relocation modifier"));
4023 if (entry
->movw_type
== 0)
4026 (_("this relocation modifier is not allowed on this instruction"));
4030 inst
.reloc
.type
= entry
->movw_type
;
4033 *internal_fixup_p
= 1;
4035 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4042 /* Parse an operand for an ADRP instruction:
4044 Return TRUE on success; otherwise return FALSE. */
4047 parse_adrp (char **str
)
4054 struct reloc_table_entry
*entry
;
4056 /* Try to parse a relocation. Anything else is an error. */
4058 if (!(entry
= find_reloc_table_entry (&p
)))
4060 set_syntax_error (_("unknown relocation modifier"));
4064 if (entry
->adrp_type
== 0)
4067 (_("this relocation modifier is not allowed on this instruction"));
4071 inst
.reloc
.type
= entry
->adrp_type
;
4074 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4076 inst
.reloc
.pc_rel
= 1;
4077 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4083 /* Miscellaneous. */
4085 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4086 of SIZE tokens in which index I gives the token for field value I,
4087 or is null if field value I is invalid. REG_TYPE says which register
4088 names should be treated as registers rather than as symbolic immediates.
4090 Return true on success, moving *STR past the operand and storing the
4091 field value in *VAL. */
4094 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4095 size_t size
, aarch64_reg_type reg_type
)
4101 /* Match C-like tokens. */
4103 while (ISALNUM (*q
))
4106 for (i
= 0; i
< size
; ++i
)
4108 && strncasecmp (array
[i
], p
, q
- p
) == 0
4109 && array
[i
][q
- p
] == 0)
4116 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4119 if (exp
.X_op
== O_constant
4120 && (uint64_t) exp
.X_add_number
< size
)
4122 *val
= exp
.X_add_number
;
4127 /* Use the default error for this operand. */
4131 /* Parse an option for a preload instruction. Returns the encoding for the
4132 option, or PARSE_FAIL. */
4135 parse_pldop (char **str
)
4138 const struct aarch64_name_value_pair
*o
;
4141 while (ISALNUM (*q
))
4144 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4152 /* Parse an option for a barrier instruction. Returns the encoding for the
4153 option, or PARSE_FAIL. */
4156 parse_barrier (char **str
)
4159 const struct aarch64_name_value_pair
*o
;
4162 while (ISALPHA (*q
))
4165 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4173 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4174 return 0 if successful. Otherwise return PARSE_FAIL. */
4177 parse_barrier_psb (char **str
,
4178 const struct aarch64_name_value_pair
** hint_opt
)
4181 const struct aarch64_name_value_pair
*o
;
4184 while (ISALPHA (*q
))
4187 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4190 set_fatal_syntax_error
4191 ( _("unknown or missing option to PSB/TSB"));
4195 if (o
->value
!= 0x11)
4197 /* PSB only accepts option name 'CSYNC'. */
4199 (_("the specified option is not accepted for PSB/TSB"));
4208 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4209 return 0 if successful. Otherwise return PARSE_FAIL. */
4212 parse_bti_operand (char **str
,
4213 const struct aarch64_name_value_pair
** hint_opt
)
4216 const struct aarch64_name_value_pair
*o
;
4219 while (ISALPHA (*q
))
4222 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4225 set_fatal_syntax_error
4226 ( _("unknown option to BTI"));
4232 /* Valid BTI operands. */
4240 (_("unknown option to BTI"));
4249 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4250 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4255 Side effect: Update STR with current parse position of success.
4258 static const reg_entry
*
4259 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4260 aarch64_opnd_qualifier_t
*qualifier
)
4264 reg_entry
*reg
= parse_reg (str
);
4265 if (reg
!= NULL
&& reg
->type
== reg_type
)
4267 if (!skip_past_char (str
, '.'))
4269 set_syntax_error (_("missing ZA tile element size separator"));
4274 switch (TOLOWER (*q
))
4277 *qualifier
= AARCH64_OPND_QLF_S_B
;
4280 *qualifier
= AARCH64_OPND_QLF_S_H
;
4283 *qualifier
= AARCH64_OPND_QLF_S_S
;
4286 *qualifier
= AARCH64_OPND_QLF_S_D
;
4289 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4303 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4304 Function return tile QUALIFIER on success.
4306 Tiles are in example format: za[0-9]\.[bhsd]
4308 Function returns <ZAda> register number or PARSE_FAIL.
4311 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4314 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4318 regno
= reg
->number
;
4322 case AARCH64_OPND_QLF_S_B
:
4325 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4329 case AARCH64_OPND_QLF_S_H
:
4332 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4336 case AARCH64_OPND_QLF_S_S
:
4339 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4340 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4344 case AARCH64_OPND_QLF_S_D
:
4347 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4348 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4353 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4360 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4365 Function return TRUE if immediate was found, or FALSE.
4368 parse_sme_immediate (char **str
, int64_t *imm
)
4371 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4378 /* Parse index with vector select register and immediate:
4382 where <Wv> is in W12-W15 range and # is optional for immediate.
4384 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4387 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4391 parse_sme_za_hv_tiles_operand_index (char **str
,
4392 int *vector_select_register
,
4395 const reg_entry
*reg
;
4397 if (!skip_past_char (str
, '['))
4399 set_syntax_error (_("expected '['"));
4403 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4404 reg
= parse_reg (str
);
4405 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4406 || reg
->number
< 12 || reg
->number
> 15)
4408 set_syntax_error (_("expected vector select register W12-W15"));
4411 *vector_select_register
= reg
->number
;
4413 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4415 set_syntax_error (_("expected ','"));
4419 if (!parse_sme_immediate (str
, imm
))
4421 set_syntax_error (_("index offset immediate expected"));
4425 if (!skip_past_char (str
, ']'))
4427 set_syntax_error (_("expected ']'"));
4434 /* Parse SME ZA horizontal or vertical vector access to tiles.
4435 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4436 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4437 contains <Wv> select register and corresponding optional IMMEDIATE.
4438 In addition QUALIFIER is extracted.
4440 Field format examples:
4442 ZA0<HV>.B[<Wv>, #<imm>]
4443 <ZAn><HV>.H[<Wv>, #<imm>]
4444 <ZAn><HV>.S[<Wv>, #<imm>]
4445 <ZAn><HV>.D[<Wv>, #<imm>]
4446 <ZAn><HV>.Q[<Wv>, #<imm>]
4448 Function returns <ZAda> register number or PARSE_FAIL.
4451 parse_sme_za_hv_tiles_operand (char **str
,
4452 enum sme_hv_slice
*slice_indicator
,
4453 int *vector_select_register
,
4455 aarch64_opnd_qualifier_t
*qualifier
)
4462 const reg_entry
*reg
;
4465 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4467 *slice_indicator
= HV_horizontal
;
4470 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4472 *slice_indicator
= HV_vertical
;
4477 regno
= reg
->number
;
4481 case AARCH64_OPND_QLF_S_B
:
4485 case AARCH64_OPND_QLF_S_H
:
4489 case AARCH64_OPND_QLF_S_S
:
4493 case AARCH64_OPND_QLF_S_D
:
4497 case AARCH64_OPND_QLF_S_Q
:
4502 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4506 /* Check if destination register ZA tile vector is in range for given
4507 instruction variant. */
4508 if (regno
< 0 || regno
> regno_limit
)
4510 set_syntax_error (_("ZA tile vector out of range"));
4514 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4518 /* Check if optional index offset is in the range for instruction
4520 if (imm_value
< 0 || imm_value
> imm_limit
)
4522 set_syntax_error (_("index offset out of range"));
4533 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4534 enum sme_hv_slice
*slice_indicator
,
4535 int *vector_select_register
,
4537 aarch64_opnd_qualifier_t
*qualifier
)
4541 if (!skip_past_char (str
, '{'))
4543 set_syntax_error (_("expected '{'"));
4547 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4548 vector_select_register
, imm
,
4551 if (regno
== PARSE_FAIL
)
4554 if (!skip_past_char (str
, '}'))
4556 set_syntax_error (_("expected '}'"));
4563 /* Parse list of up to eight 64-bit element tile names separated by commas in
4564 SME's ZERO instruction:
4568 Function returns <mask>:
4570 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4573 parse_sme_zero_mask(char **str
)
4577 aarch64_opnd_qualifier_t qualifier
;
4583 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4586 int regno
= reg
->number
;
4587 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4589 /* { ZA0.B } is assembled as all-ones immediate. */
4592 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4593 mask
|= 0x55 << regno
;
4594 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4595 mask
|= 0x11 << regno
;
4596 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4597 mask
|= 0x01 << regno
;
4600 set_syntax_error (_("wrong ZA tile element format"));
4605 else if (strncasecmp (q
, "za", 2) == 0
4608 /* { ZA } is assembled as all-ones immediate. */
4615 set_syntax_error (_("wrong ZA tile element format"));
4619 while (skip_past_char (&q
, ','));
4625 /* Wraps in curly braces <mask> operand ZERO instruction:
4629 Function returns value of <mask> bit-field.
4632 parse_sme_list_of_64bit_tiles (char **str
)
4636 if (!skip_past_char (str
, '{'))
4638 set_syntax_error (_("expected '{'"));
4642 /* Empty <mask> list is an all-zeros immediate. */
4643 if (!skip_past_char (str
, '}'))
4645 regno
= parse_sme_zero_mask (str
);
4646 if (regno
== PARSE_FAIL
)
4649 if (!skip_past_char (str
, '}'))
4651 set_syntax_error (_("expected '}'"));
4661 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4667 Function returns <Wv> or PARSE_FAIL.
4670 parse_sme_za_array (char **str
, int *imm
)
4677 while (ISALPHA (*q
))
4680 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4682 set_syntax_error (_("expected ZA array"));
4686 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4689 if (imm_value
< 0 || imm_value
> 15)
4691 set_syntax_error (_("offset out of range"));
4700 /* Parse streaming mode operand for SMSTART and SMSTOP.
4704 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4707 parse_sme_sm_za (char **str
)
4712 while (ISALPHA (*q
))
4716 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4718 set_syntax_error (_("expected SM or ZA operand"));
4723 return TOLOWER (p
[0]);
4726 /* Parse the name of the source scalable predicate register, the index base
4727 register W12-W15 and the element index. Function performs element index
4728 limit checks as well as qualifier type checks.
4730 <Pn>.<T>[<Wv>, <imm>]
4731 <Pn>.<T>[<Wv>, #<imm>]
4733 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4735 Function returns <Pn>, or PARSE_FAIL.
4738 parse_sme_pred_reg_with_index(char **str
,
4739 int *index_base_reg
,
4741 aarch64_opnd_qualifier_t
*qualifier
)
4746 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4750 regno
= reg
->number
;
4754 case AARCH64_OPND_QLF_S_B
:
4757 case AARCH64_OPND_QLF_S_H
:
4760 case AARCH64_OPND_QLF_S_S
:
4763 case AARCH64_OPND_QLF_S_D
:
4767 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4771 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4774 if (imm_value
< 0 || imm_value
> imm_limit
)
4776 set_syntax_error (_("element index out of range for given variant"));
4785 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4786 Returns the encoding for the option, or PARSE_FAIL.
4788 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4789 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4791 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4792 field, otherwise as a system register.
4796 parse_sys_reg (char **str
, htab_t sys_regs
,
4797 int imple_defined_p
, int pstatefield_p
,
4801 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4802 const aarch64_sys_reg
*o
;
4806 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4807 if (p
< buf
+ (sizeof (buf
) - 1))
4808 *p
++ = TOLOWER (*q
);
4811 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4812 valid system register. This is enforced by construction of the hash
4814 if (p
- buf
!= q
- *str
)
4817 o
= str_hash_find (sys_regs
, buf
);
4820 if (!imple_defined_p
)
4824 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4825 unsigned int op0
, op1
, cn
, cm
, op2
;
4827 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4830 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4832 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4839 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4840 as_bad (_("selected processor does not support PSTATE field "
4843 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4844 o
->value
, o
->flags
, o
->features
))
4845 as_bad (_("selected processor does not support system register "
4847 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4848 as_warn (_("system register name '%s' is deprecated and may be "
4849 "removed in a future release"), buf
);
4859 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4860 for the option, or NULL. */
4862 static const aarch64_sys_ins_reg
*
4863 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4866 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4867 const aarch64_sys_ins_reg
*o
;
4870 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4871 if (p
< buf
+ (sizeof (buf
) - 1))
4872 *p
++ = TOLOWER (*q
);
4875 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4876 valid system register. This is enforced by construction of the hash
4878 if (p
- buf
!= q
- *str
)
4881 o
= str_hash_find (sys_ins_regs
, buf
);
4885 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4886 o
->name
, o
->value
, o
->flags
, 0))
4887 as_bad (_("selected processor does not support system register "
4889 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4890 as_warn (_("system register name '%s' is deprecated and may be "
4891 "removed in a future release"), buf
);
4897 #define po_char_or_fail(chr) do { \
4898 if (! skip_past_char (&str, chr)) \
4902 #define po_reg_or_fail(regtype) do { \
4903 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4904 if (val == PARSE_FAIL) \
4906 set_default_error (); \
4911 #define po_int_reg_or_fail(reg_type) do { \
4912 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4913 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4915 set_default_error (); \
4918 info->reg.regno = reg->number; \
4919 info->qualifier = qualifier; \
4922 #define po_imm_nc_or_fail() do { \
4923 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4927 #define po_imm_or_fail(min, max) do { \
4928 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4930 if (val < min || val > max) \
4932 set_fatal_syntax_error (_("immediate value out of range "\
4933 #min " to "#max)); \
4938 #define po_enum_or_fail(array) do { \
4939 if (!parse_enum_string (&str, &val, array, \
4940 ARRAY_SIZE (array), imm_reg_type)) \
4944 #define po_misc_or_fail(expr) do { \
4949 /* encode the 12-bit imm field of Add/sub immediate */
4950 static inline uint32_t
4951 encode_addsub_imm (uint32_t imm
)
4956 /* encode the shift amount field of Add/sub immediate */
4957 static inline uint32_t
4958 encode_addsub_imm_shift_amount (uint32_t cnt
)
4964 /* encode the imm field of Adr instruction */
4965 static inline uint32_t
4966 encode_adr_imm (uint32_t imm
)
4968 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4969 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4972 /* encode the immediate field of Move wide immediate */
4973 static inline uint32_t
4974 encode_movw_imm (uint32_t imm
)
4979 /* encode the 26-bit offset of unconditional branch */
4980 static inline uint32_t
4981 encode_branch_ofs_26 (uint32_t ofs
)
4983 return ofs
& ((1 << 26) - 1);
4986 /* encode the 19-bit offset of conditional branch and compare & branch */
4987 static inline uint32_t
4988 encode_cond_branch_ofs_19 (uint32_t ofs
)
4990 return (ofs
& ((1 << 19) - 1)) << 5;
4993 /* encode the 19-bit offset of ld literal */
4994 static inline uint32_t
4995 encode_ld_lit_ofs_19 (uint32_t ofs
)
4997 return (ofs
& ((1 << 19) - 1)) << 5;
5000 /* Encode the 14-bit offset of test & branch. */
5001 static inline uint32_t
5002 encode_tst_branch_ofs_14 (uint32_t ofs
)
5004 return (ofs
& ((1 << 14) - 1)) << 5;
5007 /* Encode the 16-bit imm field of svc/hvc/smc. */
5008 static inline uint32_t
5009 encode_svc_imm (uint32_t imm
)
5014 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5015 static inline uint32_t
5016 reencode_addsub_switch_add_sub (uint32_t opcode
)
5018 return opcode
^ (1 << 30);
5021 static inline uint32_t
5022 reencode_movzn_to_movz (uint32_t opcode
)
5024 return opcode
| (1 << 30);
5027 static inline uint32_t
5028 reencode_movzn_to_movn (uint32_t opcode
)
5030 return opcode
& ~(1 << 30);
5033 /* Overall per-instruction processing. */
5035 /* We need to be able to fix up arbitrary expressions in some statements.
5036 This is so that we can handle symbols that are an arbitrary distance from
5037 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5038 which returns part of an address in a form which will be valid for
5039 a data instruction. We do this by pushing the expression into a symbol
5040 in the expr_section, and creating a fix for that. */
5043 fix_new_aarch64 (fragS
* frag
,
5058 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5062 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5069 /* Diagnostics on operands errors. */
5071 /* By default, output verbose error message.
5072 Disable the verbose error message by -mno-verbose-error. */
5073 static int verbose_error_p
= 1;
5075 #ifdef DEBUG_AARCH64
5076 /* N.B. this is only for the purpose of debugging. */
5077 const char* operand_mismatch_kind_names
[] =
5080 "AARCH64_OPDE_RECOVERABLE",
5081 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5082 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5083 "AARCH64_OPDE_SYNTAX_ERROR",
5084 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5085 "AARCH64_OPDE_INVALID_VARIANT",
5086 "AARCH64_OPDE_OUT_OF_RANGE",
5087 "AARCH64_OPDE_UNALIGNED",
5088 "AARCH64_OPDE_REG_LIST",
5089 "AARCH64_OPDE_OTHER_ERROR",
5091 #endif /* DEBUG_AARCH64 */
5093 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5095 When multiple errors of different kinds are found in the same assembly
5096 line, only the error of the highest severity will be picked up for
5097 issuing the diagnostics. */
5100 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5101 enum aarch64_operand_error_kind rhs
)
5103 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5104 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5105 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5106 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5107 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5108 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5109 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5110 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5111 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5112 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5113 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5117 /* Helper routine to get the mnemonic name from the assembly instruction
5118 line; should only be called for the diagnosis purpose, as there is
5119 string copy operation involved, which may affect the runtime
5120 performance if used in elsewhere. */
5123 get_mnemonic_name (const char *str
)
5125 static char mnemonic
[32];
5128 /* Get the first 15 bytes and assume that the full name is included. */
5129 strncpy (mnemonic
, str
, 31);
5130 mnemonic
[31] = '\0';
5132 /* Scan up to the end of the mnemonic, which must end in white space,
5133 '.', or end of string. */
5134 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5139 /* Append '...' to the truncated long name. */
5140 if (ptr
- mnemonic
== 31)
5141 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5147 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5149 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5150 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5153 /* Data structures storing one user error in the assembly code related to
5156 struct operand_error_record
5158 const aarch64_opcode
*opcode
;
5159 aarch64_operand_error detail
;
5160 struct operand_error_record
*next
;
5163 typedef struct operand_error_record operand_error_record
;
5165 struct operand_errors
5167 operand_error_record
*head
;
5168 operand_error_record
*tail
;
5171 typedef struct operand_errors operand_errors
;
5173 /* Top-level data structure reporting user errors for the current line of
5175 The way md_assemble works is that all opcodes sharing the same mnemonic
5176 name are iterated to find a match to the assembly line. In this data
5177 structure, each of the such opcodes will have one operand_error_record
5178 allocated and inserted. In other words, excessive errors related with
5179 a single opcode are disregarded. */
5180 operand_errors operand_error_report
;
5182 /* Free record nodes. */
5183 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5185 /* Initialize the data structure that stores the operand mismatch
5186 information on assembling one line of the assembly code. */
5188 init_operand_error_report (void)
5190 if (operand_error_report
.head
!= NULL
)
5192 gas_assert (operand_error_report
.tail
!= NULL
);
5193 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5194 free_opnd_error_record_nodes
= operand_error_report
.head
;
5195 operand_error_report
.head
= NULL
;
5196 operand_error_report
.tail
= NULL
;
5199 gas_assert (operand_error_report
.tail
== NULL
);
5202 /* Return TRUE if some operand error has been recorded during the
5203 parsing of the current assembly line using the opcode *OPCODE;
5204 otherwise return FALSE. */
5206 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5208 operand_error_record
*record
= operand_error_report
.head
;
5209 return record
&& record
->opcode
== opcode
;
5212 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5213 OPCODE field is initialized with OPCODE.
5214 N.B. only one record for each opcode, i.e. the maximum of one error is
5215 recorded for each instruction template. */
5218 add_operand_error_record (const operand_error_record
* new_record
)
5220 const aarch64_opcode
*opcode
= new_record
->opcode
;
5221 operand_error_record
* record
= operand_error_report
.head
;
5223 /* The record may have been created for this opcode. If not, we need
5225 if (! opcode_has_operand_error_p (opcode
))
5227 /* Get one empty record. */
5228 if (free_opnd_error_record_nodes
== NULL
)
5230 record
= XNEW (operand_error_record
);
5234 record
= free_opnd_error_record_nodes
;
5235 free_opnd_error_record_nodes
= record
->next
;
5237 record
->opcode
= opcode
;
5238 /* Insert at the head. */
5239 record
->next
= operand_error_report
.head
;
5240 operand_error_report
.head
= record
;
5241 if (operand_error_report
.tail
== NULL
)
5242 operand_error_report
.tail
= record
;
5244 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5245 && record
->detail
.index
<= new_record
->detail
.index
5246 && operand_error_higher_severity_p (record
->detail
.kind
,
5247 new_record
->detail
.kind
))
5249 /* In the case of multiple errors found on operands related with a
5250 single opcode, only record the error of the leftmost operand and
5251 only if the error is of higher severity. */
5252 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5253 " the existing error %s on operand %d",
5254 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5255 new_record
->detail
.index
,
5256 operand_mismatch_kind_names
[record
->detail
.kind
],
5257 record
->detail
.index
);
5261 record
->detail
= new_record
->detail
;
5265 record_operand_error_info (const aarch64_opcode
*opcode
,
5266 aarch64_operand_error
*error_info
)
5268 operand_error_record record
;
5269 record
.opcode
= opcode
;
5270 record
.detail
= *error_info
;
5271 add_operand_error_record (&record
);
5274 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5275 error message *ERROR, for operand IDX (count from 0). */
5278 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5279 enum aarch64_operand_error_kind kind
,
5282 aarch64_operand_error info
;
5283 memset(&info
, 0, sizeof (info
));
5287 info
.non_fatal
= false;
5288 record_operand_error_info (opcode
, &info
);
5292 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5293 enum aarch64_operand_error_kind kind
,
5294 const char* error
, const int *extra_data
)
5296 aarch64_operand_error info
;
5300 info
.data
[0].i
= extra_data
[0];
5301 info
.data
[1].i
= extra_data
[1];
5302 info
.data
[2].i
= extra_data
[2];
5303 info
.non_fatal
= false;
5304 record_operand_error_info (opcode
, &info
);
5308 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5309 const char* error
, int lower_bound
,
5312 int data
[3] = {lower_bound
, upper_bound
, 0};
5313 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5317 /* Remove the operand error record for *OPCODE. */
5318 static void ATTRIBUTE_UNUSED
5319 remove_operand_error_record (const aarch64_opcode
*opcode
)
5321 if (opcode_has_operand_error_p (opcode
))
5323 operand_error_record
* record
= operand_error_report
.head
;
5324 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5325 operand_error_report
.head
= record
->next
;
5326 record
->next
= free_opnd_error_record_nodes
;
5327 free_opnd_error_record_nodes
= record
;
5328 if (operand_error_report
.head
== NULL
)
5330 gas_assert (operand_error_report
.tail
== record
);
5331 operand_error_report
.tail
= NULL
;
5336 /* Given the instruction in *INSTR, return the index of the best matched
5337 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5339 Return -1 if there is no qualifier sequence; return the first match
5340 if there is multiple matches found. */
5343 find_best_match (const aarch64_inst
*instr
,
5344 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5346 int i
, num_opnds
, max_num_matched
, idx
;
5348 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5351 DEBUG_TRACE ("no operand");
5355 max_num_matched
= 0;
5358 /* For each pattern. */
5359 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5362 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5364 /* Most opcodes has much fewer patterns in the list. */
5365 if (empty_qualifier_sequence_p (qualifiers
))
5367 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5371 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5372 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5375 if (num_matched
> max_num_matched
)
5377 max_num_matched
= num_matched
;
5382 DEBUG_TRACE ("return with %d", idx
);
5386 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5387 corresponding operands in *INSTR. */
5390 assign_qualifier_sequence (aarch64_inst
*instr
,
5391 const aarch64_opnd_qualifier_t
*qualifiers
)
5394 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5395 gas_assert (num_opnds
);
5396 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5397 instr
->operands
[i
].qualifier
= *qualifiers
;
5400 /* Callback used by aarch64_print_operand to apply STYLE to the
5401 disassembler output created from FMT and ARGS. The STYLER object holds
5402 any required state. Must return a pointer to a string (created from FMT
5403 and ARGS) that will continue to be valid until the complete disassembled
5404 instruction has been printed.
5406 We don't currently add any styling to the output of the disassembler as
5407 used within assembler error messages, and so STYLE is ignored here. A
5408 new string is allocated on the obstack help within STYLER and returned
5411 static const char *aarch64_apply_style
5412 (struct aarch64_styler
*styler
,
5413 enum disassembler_style style ATTRIBUTE_UNUSED
,
5414 const char *fmt
, va_list args
)
5418 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5421 /* Calculate the required space. */
5423 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5425 gas_assert (res
>= 0);
5427 /* Allocate space on the obstack and format the result. */
5428 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5429 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5430 gas_assert (res
>= 0);
5435 /* Print operands for the diagnosis purpose. */
5438 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5439 const aarch64_opnd_info
*opnds
)
5442 struct aarch64_styler styler
;
5443 struct obstack content
;
5444 obstack_init (&content
);
5446 styler
.apply_style
= aarch64_apply_style
;
5447 styler
.state
= (void *) &content
;
5449 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5454 /* We regard the opcode operand info more, however we also look into
5455 the inst->operands to support the disassembling of the optional
5457 The two operand code should be the same in all cases, apart from
5458 when the operand can be optional. */
5459 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5460 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5463 /* Generate the operand string in STR. */
5464 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5465 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5469 strcat (buf
, i
== 0 ? " " : ", ");
5471 /* Append the operand string. */
5474 /* Append a comment. This works because only the last operand ever
5475 adds a comment. If that ever changes then we'll need to be
5479 strcat (buf
, "\t// ");
5484 obstack_free (&content
, NULL
);
5487 /* Send to stderr a string as information. */
5490 output_info (const char *format
, ...)
5496 file
= as_where (&line
);
5500 fprintf (stderr
, "%s:%u: ", file
, line
);
5502 fprintf (stderr
, "%s: ", file
);
5504 fprintf (stderr
, _("Info: "));
5505 va_start (args
, format
);
5506 vfprintf (stderr
, format
, args
);
5508 (void) putc ('\n', stderr
);
5511 /* Output one operand error record. */
5514 output_operand_error_record (const operand_error_record
*record
, char *str
)
5516 const aarch64_operand_error
*detail
= &record
->detail
;
5517 int idx
= detail
->index
;
5518 const aarch64_opcode
*opcode
= record
->opcode
;
5519 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5520 : AARCH64_OPND_NIL
);
5522 typedef void (*handler_t
)(const char *format
, ...);
5523 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5525 switch (detail
->kind
)
5527 case AARCH64_OPDE_NIL
:
5531 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5532 handler (_("this `%s' should have an immediately preceding `%s'"
5534 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5537 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5538 handler (_("the preceding `%s' should be followed by `%s` rather"
5539 " than `%s` -- `%s'"),
5540 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5543 case AARCH64_OPDE_SYNTAX_ERROR
:
5544 case AARCH64_OPDE_RECOVERABLE
:
5545 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5546 case AARCH64_OPDE_OTHER_ERROR
:
5547 /* Use the prepared error message if there is, otherwise use the
5548 operand description string to describe the error. */
5549 if (detail
->error
!= NULL
)
5552 handler (_("%s -- `%s'"), detail
->error
, str
);
5554 handler (_("%s at operand %d -- `%s'"),
5555 detail
->error
, idx
+ 1, str
);
5559 gas_assert (idx
>= 0);
5560 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5561 aarch64_get_operand_desc (opd_code
), str
);
5565 case AARCH64_OPDE_INVALID_VARIANT
:
5566 handler (_("operand mismatch -- `%s'"), str
);
5567 if (verbose_error_p
)
5569 /* We will try to correct the erroneous instruction and also provide
5570 more information e.g. all other valid variants.
5572 The string representation of the corrected instruction and other
5573 valid variants are generated by
5575 1) obtaining the intermediate representation of the erroneous
5577 2) manipulating the IR, e.g. replacing the operand qualifier;
5578 3) printing out the instruction by calling the printer functions
5579 shared with the disassembler.
5581 The limitation of this method is that the exact input assembly
5582 line cannot be accurately reproduced in some cases, for example an
5583 optional operand present in the actual assembly line will be
5584 omitted in the output; likewise for the optional syntax rules,
5585 e.g. the # before the immediate. Another limitation is that the
5586 assembly symbols and relocation operations in the assembly line
5587 currently cannot be printed out in the error report. Last but not
5588 least, when there is other error(s) co-exist with this error, the
5589 'corrected' instruction may be still incorrect, e.g. given
5590 'ldnp h0,h1,[x0,#6]!'
5591 this diagnosis will provide the version:
5592 'ldnp s0,s1,[x0,#6]!'
5593 which is still not right. */
5594 size_t len
= strlen (get_mnemonic_name (str
));
5598 aarch64_inst
*inst_base
= &inst
.base
;
5599 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5602 reset_aarch64_instruction (&inst
);
5603 inst_base
->opcode
= opcode
;
5605 /* Reset the error report so that there is no side effect on the
5606 following operand parsing. */
5607 init_operand_error_report ();
5610 result
= parse_operands (str
+ len
, opcode
)
5611 && programmer_friendly_fixup (&inst
);
5612 gas_assert (result
);
5613 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5614 NULL
, NULL
, insn_sequence
);
5615 gas_assert (!result
);
5617 /* Find the most matched qualifier sequence. */
5618 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5619 gas_assert (qlf_idx
> -1);
5621 /* Assign the qualifiers. */
5622 assign_qualifier_sequence (inst_base
,
5623 opcode
->qualifiers_list
[qlf_idx
]);
5625 /* Print the hint. */
5626 output_info (_(" did you mean this?"));
5627 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5628 print_operands (buf
, opcode
, inst_base
->operands
);
5629 output_info (_(" %s"), buf
);
5631 /* Print out other variant(s) if there is any. */
5633 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5634 output_info (_(" other valid variant(s):"));
5636 /* For each pattern. */
5637 qualifiers_list
= opcode
->qualifiers_list
;
5638 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5640 /* Most opcodes has much fewer patterns in the list.
5641 First NIL qualifier indicates the end in the list. */
5642 if (empty_qualifier_sequence_p (*qualifiers_list
))
5647 /* Mnemonics name. */
5648 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5650 /* Assign the qualifiers. */
5651 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5653 /* Print instruction. */
5654 print_operands (buf
, opcode
, inst_base
->operands
);
5656 output_info (_(" %s"), buf
);
5662 case AARCH64_OPDE_UNTIED_IMMS
:
5663 handler (_("operand %d must have the same immediate value "
5664 "as operand 1 -- `%s'"),
5665 detail
->index
+ 1, str
);
5668 case AARCH64_OPDE_UNTIED_OPERAND
:
5669 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5670 detail
->index
+ 1, str
);
5673 case AARCH64_OPDE_OUT_OF_RANGE
:
5674 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5675 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5676 detail
->error
? detail
->error
: _("immediate value"),
5677 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5679 handler (_("%s must be %d at operand %d -- `%s'"),
5680 detail
->error
? detail
->error
: _("immediate value"),
5681 detail
->data
[0].i
, idx
+ 1, str
);
5684 case AARCH64_OPDE_REG_LIST
:
5685 if (detail
->data
[0].i
== 1)
5686 handler (_("invalid number of registers in the list; "
5687 "only 1 register is expected at operand %d -- `%s'"),
5690 handler (_("invalid number of registers in the list; "
5691 "%d registers are expected at operand %d -- `%s'"),
5692 detail
->data
[0].i
, idx
+ 1, str
);
5695 case AARCH64_OPDE_UNALIGNED
:
5696 handler (_("immediate value must be a multiple of "
5697 "%d at operand %d -- `%s'"),
5698 detail
->data
[0].i
, idx
+ 1, str
);
5707 /* Process and output the error message about the operand mismatching.
5709 When this function is called, the operand error information had
5710 been collected for an assembly line and there will be multiple
5711 errors in the case of multiple instruction templates; output the
5712 error message that most closely describes the problem.
5714 The errors to be printed can be filtered on printing all errors
5715 or only non-fatal errors. This distinction has to be made because
5716 the error buffer may already be filled with fatal errors we don't want to
5717 print due to the different instruction templates. */
5720 output_operand_error_report (char *str
, bool non_fatal_only
)
5722 int largest_error_pos
;
5723 const char *msg
= NULL
;
5724 enum aarch64_operand_error_kind kind
;
5725 operand_error_record
*curr
;
5726 operand_error_record
*head
= operand_error_report
.head
;
5727 operand_error_record
*record
= NULL
;
5729 /* No error to report. */
5733 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5735 /* Only one error. */
5736 if (head
== operand_error_report
.tail
)
5738 /* If the only error is a non-fatal one and we don't want to print it,
5740 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5742 DEBUG_TRACE ("single opcode entry with error kind: %s",
5743 operand_mismatch_kind_names
[head
->detail
.kind
]);
5744 output_operand_error_record (head
, str
);
5749 /* Find the error kind of the highest severity. */
5750 DEBUG_TRACE ("multiple opcode entries with error kind");
5751 kind
= AARCH64_OPDE_NIL
;
5752 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5754 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5755 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5756 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5757 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5758 kind
= curr
->detail
.kind
;
5761 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5763 /* Pick up one of errors of KIND to report. */
5764 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5765 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5767 /* If we don't want to print non-fatal errors then don't consider them
5769 if (curr
->detail
.kind
!= kind
5770 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5772 /* If there are multiple errors, pick up the one with the highest
5773 mismatching operand index. In the case of multiple errors with
5774 the equally highest operand index, pick up the first one or the
5775 first one with non-NULL error message. */
5776 if (curr
->detail
.index
> largest_error_pos
5777 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5778 && curr
->detail
.error
!= NULL
))
5780 largest_error_pos
= curr
->detail
.index
;
5782 msg
= record
->detail
.error
;
5786 /* The way errors are collected in the back-end is a bit non-intuitive. But
5787 essentially, because each operand template is tried recursively you may
5788 always have errors collected from the previous tried OPND. These are
5789 usually skipped if there is one successful match. However now with the
5790 non-fatal errors we have to ignore those previously collected hard errors
5791 when we're only interested in printing the non-fatal ones. This condition
5792 prevents us from printing errors that are not appropriate, since we did
5793 match a condition, but it also has warnings that it wants to print. */
5794 if (non_fatal_only
&& !record
)
5797 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5798 DEBUG_TRACE ("Pick up error kind %s to report",
5799 operand_mismatch_kind_names
[record
->detail
.kind
]);
5802 output_operand_error_record (record
, str
);
5805 /* Write an AARCH64 instruction to buf - always little-endian. */
5807 put_aarch64_insn (char *buf
, uint32_t insn
)
5809 unsigned char *where
= (unsigned char *) buf
;
5811 where
[1] = insn
>> 8;
5812 where
[2] = insn
>> 16;
5813 where
[3] = insn
>> 24;
5817 get_aarch64_insn (char *buf
)
5819 unsigned char *where
= (unsigned char *) buf
;
5821 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5822 | ((uint32_t) where
[3] << 24)));
5827 output_inst (struct aarch64_inst
*new_inst
)
5831 to
= frag_more (INSN_SIZE
);
5833 frag_now
->tc_frag_data
.recorded
= 1;
5835 put_aarch64_insn (to
, inst
.base
.value
);
5837 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5839 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5840 INSN_SIZE
, &inst
.reloc
.exp
,
5843 DEBUG_TRACE ("Prepared relocation fix up");
5844 /* Don't check the addend value against the instruction size,
5845 that's the job of our code in md_apply_fix(). */
5846 fixp
->fx_no_overflow
= 1;
5847 if (new_inst
!= NULL
)
5848 fixp
->tc_fix_data
.inst
= new_inst
;
5849 if (aarch64_gas_internal_fixup_p ())
5851 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5852 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5853 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5857 dwarf2_emit_insn (INSN_SIZE
);
5860 /* Link together opcodes of the same name. */
5864 const aarch64_opcode
*opcode
;
5865 struct templates
*next
;
5868 typedef struct templates templates
;
5871 lookup_mnemonic (const char *start
, int len
)
5873 templates
*templ
= NULL
;
5875 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5879 /* Subroutine of md_assemble, responsible for looking up the primary
5880 opcode from the mnemonic the user wrote. BASE points to the beginning
5881 of the mnemonic, DOT points to the first '.' within the mnemonic
5882 (if any) and END points to the end of the mnemonic. */
5885 opcode_lookup (char *base
, char *dot
, char *end
)
5887 const aarch64_cond
*cond
;
5894 inst
.cond
= COND_ALWAYS
;
5896 /* Handle a possible condition. */
5899 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5902 inst
.cond
= cond
->value
;
5908 if (inst
.cond
== COND_ALWAYS
)
5910 /* Look for unaffixed mnemonic. */
5911 return lookup_mnemonic (base
, len
);
5915 /* append ".c" to mnemonic if conditional */
5916 memcpy (condname
, base
, len
);
5917 memcpy (condname
+ len
, ".c", 2);
5920 return lookup_mnemonic (base
, len
);
5926 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5927 to a corresponding operand qualifier. */
5929 static inline aarch64_opnd_qualifier_t
5930 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5932 /* Element size in bytes indexed by vector_el_type. */
5933 const unsigned char ele_size
[5]
5935 const unsigned int ele_base
[5] =
5937 AARCH64_OPND_QLF_V_4B
,
5938 AARCH64_OPND_QLF_V_2H
,
5939 AARCH64_OPND_QLF_V_2S
,
5940 AARCH64_OPND_QLF_V_1D
,
5941 AARCH64_OPND_QLF_V_1Q
5944 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5945 goto vectype_conversion_fail
;
5947 if (vectype
->type
== NT_zero
)
5948 return AARCH64_OPND_QLF_P_Z
;
5949 if (vectype
->type
== NT_merge
)
5950 return AARCH64_OPND_QLF_P_M
;
5952 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5954 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5956 /* Special case S_4B. */
5957 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5958 return AARCH64_OPND_QLF_S_4B
;
5960 /* Special case S_2H. */
5961 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5962 return AARCH64_OPND_QLF_S_2H
;
5964 /* Vector element register. */
5965 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5969 /* Vector register. */
5970 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5973 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5974 goto vectype_conversion_fail
;
5976 /* The conversion is by calculating the offset from the base operand
5977 qualifier for the vector type. The operand qualifiers are regular
5978 enough that the offset can established by shifting the vector width by
5979 a vector-type dependent amount. */
5981 if (vectype
->type
== NT_b
)
5983 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5985 else if (vectype
->type
>= NT_d
)
5990 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5991 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5992 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5996 vectype_conversion_fail
:
5997 first_error (_("bad vector arrangement type"));
5998 return AARCH64_OPND_QLF_NIL
;
6001 /* Process an optional operand that is found omitted from the assembly line.
6002 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
6003 instruction's opcode entry while IDX is the index of this omitted operand.
6007 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6008 int idx
, aarch64_opnd_info
*operand
)
6010 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6011 gas_assert (optional_operand_p (opcode
, idx
));
6012 gas_assert (!operand
->present
);
6016 case AARCH64_OPND_Rd
:
6017 case AARCH64_OPND_Rn
:
6018 case AARCH64_OPND_Rm
:
6019 case AARCH64_OPND_Rt
:
6020 case AARCH64_OPND_Rt2
:
6021 case AARCH64_OPND_Rt_LS64
:
6022 case AARCH64_OPND_Rt_SP
:
6023 case AARCH64_OPND_Rs
:
6024 case AARCH64_OPND_Ra
:
6025 case AARCH64_OPND_Rt_SYS
:
6026 case AARCH64_OPND_Rd_SP
:
6027 case AARCH64_OPND_Rn_SP
:
6028 case AARCH64_OPND_Rm_SP
:
6029 case AARCH64_OPND_Fd
:
6030 case AARCH64_OPND_Fn
:
6031 case AARCH64_OPND_Fm
:
6032 case AARCH64_OPND_Fa
:
6033 case AARCH64_OPND_Ft
:
6034 case AARCH64_OPND_Ft2
:
6035 case AARCH64_OPND_Sd
:
6036 case AARCH64_OPND_Sn
:
6037 case AARCH64_OPND_Sm
:
6038 case AARCH64_OPND_Va
:
6039 case AARCH64_OPND_Vd
:
6040 case AARCH64_OPND_Vn
:
6041 case AARCH64_OPND_Vm
:
6042 case AARCH64_OPND_VdD1
:
6043 case AARCH64_OPND_VnD1
:
6044 operand
->reg
.regno
= default_value
;
6047 case AARCH64_OPND_Ed
:
6048 case AARCH64_OPND_En
:
6049 case AARCH64_OPND_Em
:
6050 case AARCH64_OPND_Em16
:
6051 case AARCH64_OPND_SM3_IMM2
:
6052 operand
->reglane
.regno
= default_value
;
6055 case AARCH64_OPND_IDX
:
6056 case AARCH64_OPND_BIT_NUM
:
6057 case AARCH64_OPND_IMMR
:
6058 case AARCH64_OPND_IMMS
:
6059 case AARCH64_OPND_SHLL_IMM
:
6060 case AARCH64_OPND_IMM_VLSL
:
6061 case AARCH64_OPND_IMM_VLSR
:
6062 case AARCH64_OPND_CCMP_IMM
:
6063 case AARCH64_OPND_FBITS
:
6064 case AARCH64_OPND_UIMM4
:
6065 case AARCH64_OPND_UIMM3_OP1
:
6066 case AARCH64_OPND_UIMM3_OP2
:
6067 case AARCH64_OPND_IMM
:
6068 case AARCH64_OPND_IMM_2
:
6069 case AARCH64_OPND_WIDTH
:
6070 case AARCH64_OPND_UIMM7
:
6071 case AARCH64_OPND_NZCV
:
6072 case AARCH64_OPND_SVE_PATTERN
:
6073 case AARCH64_OPND_SVE_PRFOP
:
6074 operand
->imm
.value
= default_value
;
6077 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6078 operand
->imm
.value
= default_value
;
6079 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6080 operand
->shifter
.amount
= 1;
6083 case AARCH64_OPND_EXCEPTION
:
6084 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6087 case AARCH64_OPND_BARRIER_ISB
:
6088 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6091 case AARCH64_OPND_BTI_TARGET
:
6092 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6100 /* Process the relocation type for move wide instructions.
6101 Return TRUE on success; otherwise return FALSE. */
6104 process_movw_reloc_info (void)
6109 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6111 if (inst
.base
.opcode
->op
== OP_MOVK
)
6112 switch (inst
.reloc
.type
)
6114 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6115 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6116 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6117 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6118 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6119 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6120 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6121 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6122 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6123 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6124 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6126 (_("the specified relocation type is not allowed for MOVK"));
6132 switch (inst
.reloc
.type
)
6134 case BFD_RELOC_AARCH64_MOVW_G0
:
6135 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6136 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6137 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6138 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6139 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6140 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6141 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6142 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6143 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6144 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6145 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6146 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6149 case BFD_RELOC_AARCH64_MOVW_G1
:
6150 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6151 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6152 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6153 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6154 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6155 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6156 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6157 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6158 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6159 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6160 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6161 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6164 case BFD_RELOC_AARCH64_MOVW_G2
:
6165 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6166 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6167 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6168 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6169 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6170 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6173 set_fatal_syntax_error
6174 (_("the specified relocation type is not allowed for 32-bit "
6180 case BFD_RELOC_AARCH64_MOVW_G3
:
6181 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6184 set_fatal_syntax_error
6185 (_("the specified relocation type is not allowed for 32-bit "
6192 /* More cases should be added when more MOVW-related relocation types
6193 are supported in GAS. */
6194 gas_assert (aarch64_gas_internal_fixup_p ());
6195 /* The shift amount should have already been set by the parser. */
6198 inst
.base
.operands
[1].shifter
.amount
= shift
;
6202 /* A primitive log calculator. */
6204 static inline unsigned int
6205 get_logsz (unsigned int size
)
6207 const unsigned char ls
[16] =
6208 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6214 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6215 return ls
[size
- 1];
6218 /* Determine and return the real reloc type code for an instruction
6219 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6221 static inline bfd_reloc_code_real_type
6222 ldst_lo12_determine_real_reloc_type (void)
6224 unsigned logsz
, max_logsz
;
6225 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6226 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6228 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6230 BFD_RELOC_AARCH64_LDST8_LO12
,
6231 BFD_RELOC_AARCH64_LDST16_LO12
,
6232 BFD_RELOC_AARCH64_LDST32_LO12
,
6233 BFD_RELOC_AARCH64_LDST64_LO12
,
6234 BFD_RELOC_AARCH64_LDST128_LO12
6237 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6238 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6239 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6240 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6241 BFD_RELOC_AARCH64_NONE
6244 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6245 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6246 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6247 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6248 BFD_RELOC_AARCH64_NONE
6251 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6252 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6253 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6254 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6255 BFD_RELOC_AARCH64_NONE
6258 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6259 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6260 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6261 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6262 BFD_RELOC_AARCH64_NONE
6266 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6267 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6269 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6271 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6273 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6274 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6276 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6278 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6280 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6282 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6284 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6285 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6286 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6287 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6292 if (logsz
> max_logsz
)
6294 /* SEE PR 27904 for an example of this. */
6295 set_fatal_syntax_error
6296 (_("relocation qualifier does not match instruction size"));
6297 return BFD_RELOC_AARCH64_NONE
;
6300 /* In reloc.c, these pseudo relocation types should be defined in similar
6301 order as above reloc_ldst_lo12 array. Because the array index calculation
6302 below relies on this. */
6303 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6306 /* Check whether a register list REGINFO is valid. The registers must be
6307 numbered in increasing order (modulo 32), in increments of one or two.
6309 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6312 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6315 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6317 uint32_t i
, nb_regs
, prev_regno
, incr
;
6319 nb_regs
= 1 + (reginfo
& 0x3);
6321 prev_regno
= reginfo
& 0x1f;
6322 incr
= accept_alternate
? 2 : 1;
6324 for (i
= 1; i
< nb_regs
; ++i
)
6326 uint32_t curr_regno
;
6328 curr_regno
= reginfo
& 0x1f;
6329 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6331 prev_regno
= curr_regno
;
6337 /* Generic instruction operand parser. This does no encoding and no
6338 semantic validation; it merely squirrels values away in the inst
6339 structure. Returns TRUE or FALSE depending on whether the
6340 specified grammar matched. */
6343 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6346 char *backtrack_pos
= 0;
6347 const enum aarch64_opnd
*operands
= opcode
->operands
;
6348 aarch64_reg_type imm_reg_type
;
6351 skip_whitespace (str
);
6353 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6354 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6356 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6358 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6361 const reg_entry
*reg
;
6362 int comma_skipped_p
= 0;
6363 aarch64_reg_type rtype
;
6364 struct vector_type_el vectype
;
6365 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6366 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6367 aarch64_reg_type reg_type
;
6369 DEBUG_TRACE ("parse operand %d", i
);
6371 /* Assign the operand code. */
6372 info
->type
= operands
[i
];
6374 if (optional_operand_p (opcode
, i
))
6376 /* Remember where we are in case we need to backtrack. */
6377 gas_assert (!backtrack_pos
);
6378 backtrack_pos
= str
;
6381 /* Expect comma between operands; the backtrack mechanism will take
6382 care of cases of omitted optional operand. */
6383 if (i
> 0 && ! skip_past_char (&str
, ','))
6385 set_syntax_error (_("comma expected between operands"));
6389 comma_skipped_p
= 1;
6391 switch (operands
[i
])
6393 case AARCH64_OPND_Rd
:
6394 case AARCH64_OPND_Rn
:
6395 case AARCH64_OPND_Rm
:
6396 case AARCH64_OPND_Rt
:
6397 case AARCH64_OPND_Rt2
:
6398 case AARCH64_OPND_Rs
:
6399 case AARCH64_OPND_Ra
:
6400 case AARCH64_OPND_Rt_LS64
:
6401 case AARCH64_OPND_Rt_SYS
:
6402 case AARCH64_OPND_PAIRREG
:
6403 case AARCH64_OPND_SVE_Rm
:
6404 po_int_reg_or_fail (REG_TYPE_R_Z
);
6406 /* In LS64 load/store instructions Rt register number must be even
6408 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6410 /* We've already checked if this is valid register.
6411 This will check if register number (Rt) is not undefined for LS64
6413 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6414 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6416 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6422 case AARCH64_OPND_Rd_SP
:
6423 case AARCH64_OPND_Rn_SP
:
6424 case AARCH64_OPND_Rt_SP
:
6425 case AARCH64_OPND_SVE_Rn_SP
:
6426 case AARCH64_OPND_Rm_SP
:
6427 po_int_reg_or_fail (REG_TYPE_R_SP
);
6430 case AARCH64_OPND_Rm_EXT
:
6431 case AARCH64_OPND_Rm_SFT
:
6432 po_misc_or_fail (parse_shifter_operand
6433 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6435 : SHIFTED_LOGIC_IMM
)));
6436 if (!info
->shifter
.operator_present
)
6438 /* Default to LSL if not present. Libopcodes prefers shifter
6439 kind to be explicit. */
6440 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6441 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6442 /* For Rm_EXT, libopcodes will carry out further check on whether
6443 or not stack pointer is used in the instruction (Recall that
6444 "the extend operator is not optional unless at least one of
6445 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6449 case AARCH64_OPND_Fd
:
6450 case AARCH64_OPND_Fn
:
6451 case AARCH64_OPND_Fm
:
6452 case AARCH64_OPND_Fa
:
6453 case AARCH64_OPND_Ft
:
6454 case AARCH64_OPND_Ft2
:
6455 case AARCH64_OPND_Sd
:
6456 case AARCH64_OPND_Sn
:
6457 case AARCH64_OPND_Sm
:
6458 case AARCH64_OPND_SVE_VZn
:
6459 case AARCH64_OPND_SVE_Vd
:
6460 case AARCH64_OPND_SVE_Vm
:
6461 case AARCH64_OPND_SVE_Vn
:
6462 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6463 if (val
== PARSE_FAIL
)
6465 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6468 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6470 info
->reg
.regno
= val
;
6471 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6474 case AARCH64_OPND_SVE_Pd
:
6475 case AARCH64_OPND_SVE_Pg3
:
6476 case AARCH64_OPND_SVE_Pg4_5
:
6477 case AARCH64_OPND_SVE_Pg4_10
:
6478 case AARCH64_OPND_SVE_Pg4_16
:
6479 case AARCH64_OPND_SVE_Pm
:
6480 case AARCH64_OPND_SVE_Pn
:
6481 case AARCH64_OPND_SVE_Pt
:
6482 case AARCH64_OPND_SME_Pm
:
6483 reg_type
= REG_TYPE_PN
;
6486 case AARCH64_OPND_SVE_Za_5
:
6487 case AARCH64_OPND_SVE_Za_16
:
6488 case AARCH64_OPND_SVE_Zd
:
6489 case AARCH64_OPND_SVE_Zm_5
:
6490 case AARCH64_OPND_SVE_Zm_16
:
6491 case AARCH64_OPND_SVE_Zn
:
6492 case AARCH64_OPND_SVE_Zt
:
6493 reg_type
= REG_TYPE_ZN
;
6496 case AARCH64_OPND_Va
:
6497 case AARCH64_OPND_Vd
:
6498 case AARCH64_OPND_Vn
:
6499 case AARCH64_OPND_Vm
:
6500 reg_type
= REG_TYPE_VN
;
6502 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6503 if (val
== PARSE_FAIL
)
6505 first_error (_(get_reg_expected_msg (reg_type
)));
6508 if (vectype
.defined
& NTA_HASINDEX
)
6511 info
->reg
.regno
= val
;
6512 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6513 && vectype
.type
== NT_invtype
)
6514 /* Unqualified Pn and Zn registers are allowed in certain
6515 contexts. Rely on F_STRICT qualifier checking to catch
6517 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6520 info
->qualifier
= vectype_to_qualifier (&vectype
);
6521 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6526 case AARCH64_OPND_VdD1
:
6527 case AARCH64_OPND_VnD1
:
6528 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6529 if (val
== PARSE_FAIL
)
6531 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6534 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6536 set_fatal_syntax_error
6537 (_("the top half of a 128-bit FP/SIMD register is expected"));
6540 info
->reg
.regno
= val
;
6541 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6542 here; it is correct for the purpose of encoding/decoding since
6543 only the register number is explicitly encoded in the related
6544 instructions, although this appears a bit hacky. */
6545 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6548 case AARCH64_OPND_SVE_Zm3_INDEX
:
6549 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6550 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6551 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6552 case AARCH64_OPND_SVE_Zm4_INDEX
:
6553 case AARCH64_OPND_SVE_Zn_INDEX
:
6554 reg_type
= REG_TYPE_ZN
;
6555 goto vector_reg_index
;
6557 case AARCH64_OPND_Ed
:
6558 case AARCH64_OPND_En
:
6559 case AARCH64_OPND_Em
:
6560 case AARCH64_OPND_Em16
:
6561 case AARCH64_OPND_SM3_IMM2
:
6562 reg_type
= REG_TYPE_VN
;
6564 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6565 if (val
== PARSE_FAIL
)
6567 first_error (_(get_reg_expected_msg (reg_type
)));
6570 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6573 info
->reglane
.regno
= val
;
6574 info
->reglane
.index
= vectype
.index
;
6575 info
->qualifier
= vectype_to_qualifier (&vectype
);
6576 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6580 case AARCH64_OPND_SVE_ZnxN
:
6581 case AARCH64_OPND_SVE_ZtxN
:
6582 reg_type
= REG_TYPE_ZN
;
6583 goto vector_reg_list
;
6585 case AARCH64_OPND_LVn
:
6586 case AARCH64_OPND_LVt
:
6587 case AARCH64_OPND_LVt_AL
:
6588 case AARCH64_OPND_LEt
:
6589 reg_type
= REG_TYPE_VN
;
6591 if (reg_type
== REG_TYPE_ZN
6592 && get_opcode_dependent_value (opcode
) == 1
6595 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6596 if (val
== PARSE_FAIL
)
6598 first_error (_(get_reg_expected_msg (reg_type
)));
6601 info
->reglist
.first_regno
= val
;
6602 info
->reglist
.num_regs
= 1;
6606 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6607 if (val
== PARSE_FAIL
)
6610 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6612 set_fatal_syntax_error (_("invalid register list"));
6616 if (vectype
.width
!= 0 && *str
!= ',')
6618 set_fatal_syntax_error
6619 (_("expected element type rather than vector type"));
6623 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6624 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6626 if (operands
[i
] == AARCH64_OPND_LEt
)
6628 if (!(vectype
.defined
& NTA_HASINDEX
))
6630 info
->reglist
.has_index
= 1;
6631 info
->reglist
.index
= vectype
.index
;
6635 if (vectype
.defined
& NTA_HASINDEX
)
6637 if (!(vectype
.defined
& NTA_HASTYPE
))
6639 if (reg_type
== REG_TYPE_ZN
)
6640 set_fatal_syntax_error (_("missing type suffix"));
6644 info
->qualifier
= vectype_to_qualifier (&vectype
);
6645 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6649 case AARCH64_OPND_CRn
:
6650 case AARCH64_OPND_CRm
:
6652 char prefix
= *(str
++);
6653 if (prefix
!= 'c' && prefix
!= 'C')
6656 po_imm_nc_or_fail ();
6659 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6662 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6663 info
->imm
.value
= val
;
6667 case AARCH64_OPND_SHLL_IMM
:
6668 case AARCH64_OPND_IMM_VLSR
:
6669 po_imm_or_fail (1, 64);
6670 info
->imm
.value
= val
;
6673 case AARCH64_OPND_CCMP_IMM
:
6674 case AARCH64_OPND_SIMM5
:
6675 case AARCH64_OPND_FBITS
:
6676 case AARCH64_OPND_TME_UIMM16
:
6677 case AARCH64_OPND_UIMM4
:
6678 case AARCH64_OPND_UIMM4_ADDG
:
6679 case AARCH64_OPND_UIMM10
:
6680 case AARCH64_OPND_UIMM3_OP1
:
6681 case AARCH64_OPND_UIMM3_OP2
:
6682 case AARCH64_OPND_IMM_VLSL
:
6683 case AARCH64_OPND_IMM
:
6684 case AARCH64_OPND_IMM_2
:
6685 case AARCH64_OPND_WIDTH
:
6686 case AARCH64_OPND_SVE_INV_LIMM
:
6687 case AARCH64_OPND_SVE_LIMM
:
6688 case AARCH64_OPND_SVE_LIMM_MOV
:
6689 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6690 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6691 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6692 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6693 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6694 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6695 case AARCH64_OPND_SVE_SIMM5
:
6696 case AARCH64_OPND_SVE_SIMM5B
:
6697 case AARCH64_OPND_SVE_SIMM6
:
6698 case AARCH64_OPND_SVE_SIMM8
:
6699 case AARCH64_OPND_SVE_UIMM3
:
6700 case AARCH64_OPND_SVE_UIMM7
:
6701 case AARCH64_OPND_SVE_UIMM8
:
6702 case AARCH64_OPND_SVE_UIMM8_53
:
6703 case AARCH64_OPND_IMM_ROT1
:
6704 case AARCH64_OPND_IMM_ROT2
:
6705 case AARCH64_OPND_IMM_ROT3
:
6706 case AARCH64_OPND_SVE_IMM_ROT1
:
6707 case AARCH64_OPND_SVE_IMM_ROT2
:
6708 case AARCH64_OPND_SVE_IMM_ROT3
:
6709 case AARCH64_OPND_CSSC_SIMM8
:
6710 case AARCH64_OPND_CSSC_UIMM8
:
6711 po_imm_nc_or_fail ();
6712 info
->imm
.value
= val
;
6715 case AARCH64_OPND_SVE_AIMM
:
6716 case AARCH64_OPND_SVE_ASIMM
:
6717 po_imm_nc_or_fail ();
6718 info
->imm
.value
= val
;
6719 skip_whitespace (str
);
6720 if (skip_past_comma (&str
))
6721 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6723 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6726 case AARCH64_OPND_SVE_PATTERN
:
6727 po_enum_or_fail (aarch64_sve_pattern_array
);
6728 info
->imm
.value
= val
;
6731 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6732 po_enum_or_fail (aarch64_sve_pattern_array
);
6733 info
->imm
.value
= val
;
6734 if (skip_past_comma (&str
)
6735 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6737 if (!info
->shifter
.operator_present
)
6739 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6740 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6741 info
->shifter
.amount
= 1;
6745 case AARCH64_OPND_SVE_PRFOP
:
6746 po_enum_or_fail (aarch64_sve_prfop_array
);
6747 info
->imm
.value
= val
;
6750 case AARCH64_OPND_UIMM7
:
6751 po_imm_or_fail (0, 127);
6752 info
->imm
.value
= val
;
6755 case AARCH64_OPND_IDX
:
6756 case AARCH64_OPND_MASK
:
6757 case AARCH64_OPND_BIT_NUM
:
6758 case AARCH64_OPND_IMMR
:
6759 case AARCH64_OPND_IMMS
:
6760 po_imm_or_fail (0, 63);
6761 info
->imm
.value
= val
;
6764 case AARCH64_OPND_IMM0
:
6765 po_imm_nc_or_fail ();
6768 set_fatal_syntax_error (_("immediate zero expected"));
6771 info
->imm
.value
= 0;
6774 case AARCH64_OPND_FPIMM0
:
6777 bool res1
= false, res2
= false;
6778 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6779 it is probably not worth the effort to support it. */
6780 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6783 || !(res2
= parse_constant_immediate (&str
, &val
,
6786 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6788 info
->imm
.value
= 0;
6789 info
->imm
.is_fp
= 1;
6792 set_fatal_syntax_error (_("immediate zero expected"));
6796 case AARCH64_OPND_IMM_MOV
:
6799 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6800 reg_name_p (str
, REG_TYPE_VN
))
6803 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6804 GE_OPT_PREFIX
, REJECT_ABSENT
));
6805 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6806 later. fix_mov_imm_insn will try to determine a machine
6807 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6808 message if the immediate cannot be moved by a single
6810 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6811 inst
.base
.operands
[i
].skip
= 1;
6815 case AARCH64_OPND_SIMD_IMM
:
6816 case AARCH64_OPND_SIMD_IMM_SFT
:
6817 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6819 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6821 /* need_libopcodes_p */ 1,
6824 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6825 shift, we don't check it here; we leave the checking to
6826 the libopcodes (operand_general_constraint_met_p). By
6827 doing this, we achieve better diagnostics. */
6828 if (skip_past_comma (&str
)
6829 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6831 if (!info
->shifter
.operator_present
6832 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6834 /* Default to LSL if not present. Libopcodes prefers shifter
6835 kind to be explicit. */
6836 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6837 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6841 case AARCH64_OPND_FPIMM
:
6842 case AARCH64_OPND_SIMD_FPIMM
:
6843 case AARCH64_OPND_SVE_FPIMM8
:
6848 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6849 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6850 || !aarch64_imm_float_p (qfloat
))
6853 set_fatal_syntax_error (_("invalid floating-point"
6857 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6858 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6862 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6863 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6864 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6869 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6870 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6873 set_fatal_syntax_error (_("invalid floating-point"
6877 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6878 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6882 case AARCH64_OPND_LIMM
:
6883 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6884 SHIFTED_LOGIC_IMM
));
6885 if (info
->shifter
.operator_present
)
6887 set_fatal_syntax_error
6888 (_("shift not allowed for bitmask immediate"));
6891 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6893 /* need_libopcodes_p */ 1,
6897 case AARCH64_OPND_AIMM
:
6898 if (opcode
->op
== OP_ADD
)
6899 /* ADD may have relocation types. */
6900 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6901 SHIFTED_ARITH_IMM
));
6903 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6904 SHIFTED_ARITH_IMM
));
6905 switch (inst
.reloc
.type
)
6907 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6908 info
->shifter
.amount
= 12;
6910 case BFD_RELOC_UNUSED
:
6911 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6912 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6913 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6914 inst
.reloc
.pc_rel
= 0;
6919 info
->imm
.value
= 0;
6920 if (!info
->shifter
.operator_present
)
6922 /* Default to LSL if not present. Libopcodes prefers shifter
6923 kind to be explicit. */
6924 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6925 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6929 case AARCH64_OPND_HALF
:
6931 /* #<imm16> or relocation. */
6932 int internal_fixup_p
;
6933 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6934 if (internal_fixup_p
)
6935 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6936 skip_whitespace (str
);
6937 if (skip_past_comma (&str
))
6939 /* {, LSL #<shift>} */
6940 if (! aarch64_gas_internal_fixup_p ())
6942 set_fatal_syntax_error (_("can't mix relocation modifier "
6943 "with explicit shift"));
6946 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6949 inst
.base
.operands
[i
].shifter
.amount
= 0;
6950 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6951 inst
.base
.operands
[i
].imm
.value
= 0;
6952 if (! process_movw_reloc_info ())
6957 case AARCH64_OPND_EXCEPTION
:
6958 case AARCH64_OPND_UNDEFINED
:
6959 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6961 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6963 /* need_libopcodes_p */ 0,
6967 case AARCH64_OPND_NZCV
:
6969 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6973 info
->imm
.value
= nzcv
->value
;
6976 po_imm_or_fail (0, 15);
6977 info
->imm
.value
= val
;
6981 case AARCH64_OPND_COND
:
6982 case AARCH64_OPND_COND1
:
6987 while (ISALPHA (*str
));
6988 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6989 if (info
->cond
== NULL
)
6991 set_syntax_error (_("invalid condition"));
6994 else if (operands
[i
] == AARCH64_OPND_COND1
6995 && (info
->cond
->value
& 0xe) == 0xe)
6997 /* Do not allow AL or NV. */
6998 set_default_error ();
7004 case AARCH64_OPND_ADDR_ADRP
:
7005 po_misc_or_fail (parse_adrp (&str
));
7006 /* Clear the value as operand needs to be relocated. */
7007 info
->imm
.value
= 0;
7010 case AARCH64_OPND_ADDR_PCREL14
:
7011 case AARCH64_OPND_ADDR_PCREL19
:
7012 case AARCH64_OPND_ADDR_PCREL21
:
7013 case AARCH64_OPND_ADDR_PCREL26
:
7014 po_misc_or_fail (parse_address (&str
, info
));
7015 if (!info
->addr
.pcrel
)
7017 set_syntax_error (_("invalid pc-relative address"));
7020 if (inst
.gen_lit_pool
7021 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
7023 /* Only permit "=value" in the literal load instructions.
7024 The literal will be generated by programmer_friendly_fixup. */
7025 set_syntax_error (_("invalid use of \"=immediate\""));
7028 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7030 set_syntax_error (_("unrecognized relocation suffix"));
7033 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7035 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7036 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7040 info
->imm
.value
= 0;
7041 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7042 switch (opcode
->iclass
)
7046 /* e.g. CBZ or B.COND */
7047 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7048 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7052 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7053 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7057 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7059 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7060 : BFD_RELOC_AARCH64_JUMP26
;
7063 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7064 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7067 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7068 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7074 inst
.reloc
.pc_rel
= 1;
7078 case AARCH64_OPND_ADDR_SIMPLE
:
7079 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7081 /* [<Xn|SP>{, #<simm>}] */
7083 /* First use the normal address-parsing routines, to get
7084 the usual syntax errors. */
7085 po_misc_or_fail (parse_address (&str
, info
));
7086 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7087 || !info
->addr
.preind
|| info
->addr
.postind
7088 || info
->addr
.writeback
)
7090 set_syntax_error (_("invalid addressing mode"));
7094 /* Then retry, matching the specific syntax of these addresses. */
7096 po_char_or_fail ('[');
7097 po_reg_or_fail (REG_TYPE_R64_SP
);
7098 /* Accept optional ", #0". */
7099 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7100 && skip_past_char (&str
, ','))
7102 skip_past_char (&str
, '#');
7103 if (! skip_past_char (&str
, '0'))
7105 set_fatal_syntax_error
7106 (_("the optional immediate offset can only be 0"));
7110 po_char_or_fail (']');
7114 case AARCH64_OPND_ADDR_REGOFF
:
7115 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7116 po_misc_or_fail (parse_address (&str
, info
));
7118 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7119 || !info
->addr
.preind
|| info
->addr
.postind
7120 || info
->addr
.writeback
)
7122 set_syntax_error (_("invalid addressing mode"));
7125 if (!info
->shifter
.operator_present
)
7127 /* Default to LSL if not present. Libopcodes prefers shifter
7128 kind to be explicit. */
7129 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7130 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7132 /* Qualifier to be deduced by libopcodes. */
7135 case AARCH64_OPND_ADDR_SIMM7
:
7136 po_misc_or_fail (parse_address (&str
, info
));
7137 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7138 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7140 set_syntax_error (_("invalid addressing mode"));
7143 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7145 set_syntax_error (_("relocation not allowed"));
7148 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7150 /* need_libopcodes_p */ 1,
7154 case AARCH64_OPND_ADDR_SIMM9
:
7155 case AARCH64_OPND_ADDR_SIMM9_2
:
7156 case AARCH64_OPND_ADDR_SIMM11
:
7157 case AARCH64_OPND_ADDR_SIMM13
:
7158 po_misc_or_fail (parse_address (&str
, info
));
7159 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7160 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7161 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7162 && info
->addr
.writeback
))
7164 set_syntax_error (_("invalid addressing mode"));
7167 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7169 set_syntax_error (_("relocation not allowed"));
7172 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7174 /* need_libopcodes_p */ 1,
7178 case AARCH64_OPND_ADDR_SIMM10
:
7179 case AARCH64_OPND_ADDR_OFFSET
:
7180 po_misc_or_fail (parse_address (&str
, info
));
7181 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7182 || !info
->addr
.preind
|| info
->addr
.postind
)
7184 set_syntax_error (_("invalid addressing mode"));
7187 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7189 set_syntax_error (_("relocation not allowed"));
7192 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7194 /* need_libopcodes_p */ 1,
7198 case AARCH64_OPND_ADDR_UIMM12
:
7199 po_misc_or_fail (parse_address (&str
, info
));
7200 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7201 || !info
->addr
.preind
|| info
->addr
.writeback
)
7203 set_syntax_error (_("invalid addressing mode"));
7206 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7207 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7208 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7210 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7212 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7214 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7216 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7217 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7218 /* Leave qualifier to be determined by libopcodes. */
7221 case AARCH64_OPND_SIMD_ADDR_POST
:
7222 /* [<Xn|SP>], <Xm|#<amount>> */
7223 po_misc_or_fail (parse_address (&str
, info
));
7224 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7226 set_syntax_error (_("invalid addressing mode"));
7229 if (!info
->addr
.offset
.is_reg
)
7231 if (inst
.reloc
.exp
.X_op
== O_constant
)
7232 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7235 set_fatal_syntax_error
7236 (_("writeback value must be an immediate constant"));
7243 case AARCH64_OPND_SME_SM_ZA
:
7245 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7247 set_syntax_error (_("unknown or missing PSTATE field name"));
7250 info
->reg
.regno
= val
;
7253 case AARCH64_OPND_SME_PnT_Wm_imm
:
7254 /* <Pn>.<T>[<Wm>, #<imm>] */
7258 val
= parse_sme_pred_reg_with_index (&str
,
7262 if (val
== PARSE_FAIL
)
7265 info
->za_tile_vector
.regno
= val
;
7266 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7267 info
->za_tile_vector
.index
.imm
= imm
;
7268 info
->qualifier
= qualifier
;
7272 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7273 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7274 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7275 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7276 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7277 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7278 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7279 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7280 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7281 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7282 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7283 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7284 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7285 /* [X<n>{, #imm, MUL VL}]
7287 but recognizing SVE registers. */
7288 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7289 &offset_qualifier
));
7290 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7292 set_syntax_error (_("invalid addressing mode"));
7296 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7297 || !info
->addr
.preind
|| info
->addr
.writeback
)
7299 set_syntax_error (_("invalid addressing mode"));
7302 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7303 || inst
.reloc
.exp
.X_op
!= O_constant
)
7305 /* Make sure this has priority over
7306 "invalid addressing mode". */
7307 set_fatal_syntax_error (_("constant offset required"));
7310 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7313 case AARCH64_OPND_SVE_ADDR_R
:
7314 /* [<Xn|SP>{, <R><m>}]
7315 but recognizing SVE registers. */
7316 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7317 &offset_qualifier
));
7318 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7320 offset_qualifier
= AARCH64_OPND_QLF_X
;
7321 info
->addr
.offset
.is_reg
= 1;
7322 info
->addr
.offset
.regno
= 31;
7324 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7325 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7327 set_syntax_error (_("invalid addressing mode"));
7332 case AARCH64_OPND_SVE_ADDR_RR
:
7333 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7334 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7335 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7336 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7337 case AARCH64_OPND_SVE_ADDR_RX
:
7338 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7339 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7340 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7341 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7342 but recognizing SVE registers. */
7343 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7344 &offset_qualifier
));
7345 if (base_qualifier
!= AARCH64_OPND_QLF_X
7346 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7348 set_syntax_error (_("invalid addressing mode"));
7353 case AARCH64_OPND_SVE_ADDR_RZ
:
7354 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7355 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7356 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7357 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7358 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7359 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7360 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7361 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7362 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7363 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7364 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7365 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7366 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7367 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7368 &offset_qualifier
));
7369 if (base_qualifier
!= AARCH64_OPND_QLF_X
7370 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7371 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7373 set_syntax_error (_("invalid addressing mode"));
7376 info
->qualifier
= offset_qualifier
;
7379 case AARCH64_OPND_SVE_ADDR_ZX
:
7380 /* [Zn.<T>{, <Xm>}]. */
7381 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7382 &offset_qualifier
));
7384 base_qualifier either S_S or S_D
7385 offset_qualifier must be X
7387 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7388 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7389 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7391 set_syntax_error (_("invalid addressing mode"));
7394 info
->qualifier
= base_qualifier
;
7395 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7396 || !info
->addr
.preind
|| info
->addr
.writeback
7397 || info
->shifter
.operator_present
!= 0)
7399 set_syntax_error (_("invalid addressing mode"));
7402 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7406 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7407 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7408 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7409 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7410 /* [Z<n>.<T>{, #imm}] */
7411 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7412 &offset_qualifier
));
7413 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7414 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7416 set_syntax_error (_("invalid addressing mode"));
7419 info
->qualifier
= base_qualifier
;
7422 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7423 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7424 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7425 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7426 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7430 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7432 here since we get better error messages by leaving it to
7433 the qualifier checking routines. */
7434 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7435 &offset_qualifier
));
7436 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7437 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7438 || offset_qualifier
!= base_qualifier
)
7440 set_syntax_error (_("invalid addressing mode"));
7443 info
->qualifier
= base_qualifier
;
7446 case AARCH64_OPND_SYSREG
:
7448 uint32_t sysreg_flags
;
7449 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7450 &sysreg_flags
)) == PARSE_FAIL
)
7452 set_syntax_error (_("unknown or missing system register name"));
7455 inst
.base
.operands
[i
].sysreg
.value
= val
;
7456 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7460 case AARCH64_OPND_PSTATEFIELD
:
7462 uint32_t sysreg_flags
;
7463 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7464 &sysreg_flags
)) == PARSE_FAIL
)
7466 set_syntax_error (_("unknown or missing PSTATE field name"));
7469 inst
.base
.operands
[i
].pstatefield
= val
;
7470 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7474 case AARCH64_OPND_SYSREG_IC
:
7475 inst
.base
.operands
[i
].sysins_op
=
7476 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7479 case AARCH64_OPND_SYSREG_DC
:
7480 inst
.base
.operands
[i
].sysins_op
=
7481 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7484 case AARCH64_OPND_SYSREG_AT
:
7485 inst
.base
.operands
[i
].sysins_op
=
7486 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7489 case AARCH64_OPND_SYSREG_SR
:
7490 inst
.base
.operands
[i
].sysins_op
=
7491 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7494 case AARCH64_OPND_SYSREG_TLBI
:
7495 inst
.base
.operands
[i
].sysins_op
=
7496 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7498 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7500 set_fatal_syntax_error ( _("unknown or missing operation name"));
7505 case AARCH64_OPND_BARRIER
:
7506 case AARCH64_OPND_BARRIER_ISB
:
7507 val
= parse_barrier (&str
);
7508 if (val
!= PARSE_FAIL
7509 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7511 /* ISB only accepts options name 'sy'. */
7513 (_("the specified option is not accepted in ISB"));
7514 /* Turn off backtrack as this optional operand is present. */
7518 if (val
!= PARSE_FAIL
7519 && operands
[i
] == AARCH64_OPND_BARRIER
)
7521 /* Regular barriers accept options CRm (C0-C15).
7522 DSB nXS barrier variant accepts values > 15. */
7523 if (val
< 0 || val
> 15)
7525 set_syntax_error (_("the specified option is not accepted in DSB"));
7529 /* This is an extension to accept a 0..15 immediate. */
7530 if (val
== PARSE_FAIL
)
7531 po_imm_or_fail (0, 15);
7532 info
->barrier
= aarch64_barrier_options
+ val
;
7535 case AARCH64_OPND_BARRIER_DSB_NXS
:
7536 val
= parse_barrier (&str
);
7537 if (val
!= PARSE_FAIL
)
7539 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7540 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7542 set_syntax_error (_("the specified option is not accepted in DSB"));
7543 /* Turn off backtrack as this optional operand is present. */
7550 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7551 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7552 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7554 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7556 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7560 /* Option index is encoded as 2-bit value in val<3:2>. */
7561 val
= (val
>> 2) - 4;
7562 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7565 case AARCH64_OPND_PRFOP
:
7566 val
= parse_pldop (&str
);
7567 /* This is an extension to accept a 0..31 immediate. */
7568 if (val
== PARSE_FAIL
)
7569 po_imm_or_fail (0, 31);
7570 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7573 case AARCH64_OPND_BARRIER_PSB
:
7574 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7575 if (val
== PARSE_FAIL
)
7579 case AARCH64_OPND_BTI_TARGET
:
7580 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7581 if (val
== PARSE_FAIL
)
7585 case AARCH64_OPND_SME_ZAda_2b
:
7586 case AARCH64_OPND_SME_ZAda_3b
:
7587 val
= parse_sme_zada_operand (&str
, &qualifier
);
7588 if (val
== PARSE_FAIL
)
7590 info
->reg
.regno
= val
;
7591 info
->qualifier
= qualifier
;
7594 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7595 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7596 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7598 enum sme_hv_slice slice_indicator
;
7599 int vector_select_register
;
7602 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7603 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7605 &vector_select_register
,
7609 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7610 &vector_select_register
,
7613 if (val
== PARSE_FAIL
)
7615 info
->za_tile_vector
.regno
= val
;
7616 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7617 info
->za_tile_vector
.index
.imm
= imm
;
7618 info
->za_tile_vector
.v
= slice_indicator
;
7619 info
->qualifier
= qualifier
;
7623 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7624 val
= parse_sme_list_of_64bit_tiles (&str
);
7625 if (val
== PARSE_FAIL
)
7627 info
->imm
.value
= val
;
7630 case AARCH64_OPND_SME_ZA_array
:
7633 val
= parse_sme_za_array (&str
, &imm
);
7634 if (val
== PARSE_FAIL
)
7636 info
->za_tile_vector
.index
.regno
= val
;
7637 info
->za_tile_vector
.index
.imm
= imm
;
7641 case AARCH64_OPND_MOPS_ADDR_Rd
:
7642 case AARCH64_OPND_MOPS_ADDR_Rs
:
7643 po_char_or_fail ('[');
7644 if (!parse_x0_to_x30 (&str
, info
))
7646 po_char_or_fail (']');
7647 po_char_or_fail ('!');
7650 case AARCH64_OPND_MOPS_WB_Rn
:
7651 if (!parse_x0_to_x30 (&str
, info
))
7653 po_char_or_fail ('!');
7657 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7660 /* If we get here, this operand was successfully parsed. */
7661 inst
.base
.operands
[i
].present
= 1;
7665 /* The parse routine should already have set the error, but in case
7666 not, set a default one here. */
7668 set_default_error ();
7670 if (! backtrack_pos
)
7671 goto parse_operands_return
;
7674 /* We reach here because this operand is marked as optional, and
7675 either no operand was supplied or the operand was supplied but it
7676 was syntactically incorrect. In the latter case we report an
7677 error. In the former case we perform a few more checks before
7678 dropping through to the code to insert the default operand. */
7680 char *tmp
= backtrack_pos
;
7681 char endchar
= END_OF_INSN
;
7683 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7685 skip_past_char (&tmp
, ',');
7687 if (*tmp
!= endchar
)
7688 /* The user has supplied an operand in the wrong format. */
7689 goto parse_operands_return
;
7691 /* Make sure there is not a comma before the optional operand.
7692 For example the fifth operand of 'sys' is optional:
7694 sys #0,c0,c0,#0, <--- wrong
7695 sys #0,c0,c0,#0 <--- correct. */
7696 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7698 set_fatal_syntax_error
7699 (_("unexpected comma before the omitted optional operand"));
7700 goto parse_operands_return
;
7704 /* Reaching here means we are dealing with an optional operand that is
7705 omitted from the assembly line. */
7706 gas_assert (optional_operand_p (opcode
, i
));
7708 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7710 /* Try again, skipping the optional operand at backtrack_pos. */
7711 str
= backtrack_pos
;
7714 /* Clear any error record after the omitted optional operand has been
7715 successfully handled. */
7719 /* Check if we have parsed all the operands. */
7720 if (*str
!= '\0' && ! error_p ())
7722 /* Set I to the index of the last present operand; this is
7723 for the purpose of diagnostics. */
7724 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7726 set_fatal_syntax_error
7727 (_("unexpected characters following instruction"));
7730 parse_operands_return
:
7734 DEBUG_TRACE ("parsing FAIL: %s - %s",
7735 operand_mismatch_kind_names
[get_error_kind ()],
7736 get_error_message ());
7737 /* Record the operand error properly; this is useful when there
7738 are multiple instruction templates for a mnemonic name, so that
7739 later on, we can select the error that most closely describes
7741 record_operand_error (opcode
, i
, get_error_kind (),
7742 get_error_message ());
7747 DEBUG_TRACE ("parsing SUCCESS");
7752 /* It does some fix-up to provide some programmer friendly feature while
7753 keeping the libopcodes happy, i.e. libopcodes only accepts
7754 the preferred architectural syntax.
7755 Return FALSE if there is any failure; otherwise return TRUE. */
7758 programmer_friendly_fixup (aarch64_instruction
*instr
)
7760 aarch64_inst
*base
= &instr
->base
;
7761 const aarch64_opcode
*opcode
= base
->opcode
;
7762 enum aarch64_op op
= opcode
->op
;
7763 aarch64_opnd_info
*operands
= base
->operands
;
7765 DEBUG_TRACE ("enter");
7767 switch (opcode
->iclass
)
7770 /* TBNZ Xn|Wn, #uimm6, label
7771 Test and Branch Not Zero: conditionally jumps to label if bit number
7772 uimm6 in register Xn is not zero. The bit number implies the width of
7773 the register, which may be written and should be disassembled as Wn if
7774 uimm is less than 32. */
7775 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7777 if (operands
[1].imm
.value
>= 32)
7779 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7783 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7787 /* LDR Wt, label | =value
7788 As a convenience assemblers will typically permit the notation
7789 "=value" in conjunction with the pc-relative literal load instructions
7790 to automatically place an immediate value or symbolic address in a
7791 nearby literal pool and generate a hidden label which references it.
7792 ISREG has been set to 0 in the case of =value. */
7793 if (instr
->gen_lit_pool
7794 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7796 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7797 if (op
== OP_LDRSW_LIT
)
7799 if (instr
->reloc
.exp
.X_op
!= O_constant
7800 && instr
->reloc
.exp
.X_op
!= O_big
7801 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7803 record_operand_error (opcode
, 1,
7804 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7805 _("constant expression expected"));
7808 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7810 record_operand_error (opcode
, 1,
7811 AARCH64_OPDE_OTHER_ERROR
,
7812 _("literal pool insertion failed"));
7820 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7821 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7822 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7823 A programmer-friendly assembler should accept a destination Xd in
7824 place of Wd, however that is not the preferred form for disassembly.
7826 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7827 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7828 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7829 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7834 /* In the 64-bit form, the final register operand is written as Wm
7835 for all but the (possibly omitted) UXTX/LSL and SXTX
7837 As a programmer-friendly assembler, we accept e.g.
7838 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7839 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7840 int idx
= aarch64_operand_index (opcode
->operands
,
7841 AARCH64_OPND_Rm_EXT
);
7842 gas_assert (idx
== 1 || idx
== 2);
7843 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7844 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7845 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7846 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7847 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7848 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7856 DEBUG_TRACE ("exit with SUCCESS");
7860 /* Check for loads and stores that will cause unpredictable behavior. */
7863 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7865 aarch64_inst
*base
= &instr
->base
;
7866 const aarch64_opcode
*opcode
= base
->opcode
;
7867 const aarch64_opnd_info
*opnds
= base
->operands
;
7868 switch (opcode
->iclass
)
7875 /* Loading/storing the base register is unpredictable if writeback. */
7876 if ((aarch64_get_operand_class (opnds
[0].type
)
7877 == AARCH64_OPND_CLASS_INT_REG
)
7878 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7879 && opnds
[1].addr
.base_regno
!= REG_SP
7880 /* Exempt STG/STZG/ST2G/STZ2G. */
7881 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7882 && opnds
[1].addr
.writeback
)
7883 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7887 case ldstnapair_offs
:
7888 case ldstpair_indexed
:
7889 /* Loading/storing the base register is unpredictable if writeback. */
7890 if ((aarch64_get_operand_class (opnds
[0].type
)
7891 == AARCH64_OPND_CLASS_INT_REG
)
7892 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7893 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7894 && opnds
[2].addr
.base_regno
!= REG_SP
7896 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7897 && opnds
[2].addr
.writeback
)
7898 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7899 /* Load operations must load different registers. */
7900 if ((opcode
->opcode
& (1 << 22))
7901 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7902 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7906 if ((aarch64_get_operand_class (opnds
[0].type
)
7907 == AARCH64_OPND_CLASS_INT_REG
)
7908 && (aarch64_get_operand_class (opnds
[1].type
)
7909 == AARCH64_OPND_CLASS_INT_REG
))
7911 if ((opcode
->opcode
& (1 << 22)))
7913 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7914 if ((opcode
->opcode
& (1 << 21))
7915 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7916 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7920 /* Store-Exclusive is unpredictable if Rt == Rs. */
7921 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7923 (_("unpredictable: identical transfer and status registers"
7926 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7928 if (!(opcode
->opcode
& (1 << 21)))
7929 /* Store-Exclusive is unpredictable if Rn == Rs. */
7931 (_("unpredictable: identical base and status registers"
7934 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7936 (_("unpredictable: "
7937 "identical transfer and status registers"
7941 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7942 if ((opcode
->opcode
& (1 << 21))
7943 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7944 && opnds
[3].reg
.regno
!= REG_SP
)
7945 as_warn (_("unpredictable: identical base and status registers"
7957 force_automatic_sequence_close (void)
7959 struct aarch64_segment_info_type
*tc_seg_info
;
7961 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7962 if (tc_seg_info
->insn_sequence
.instr
)
7964 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7965 _("previous `%s' sequence has not been closed"),
7966 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7967 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7971 /* A wrapper function to interface with libopcodes on encoding and
7972 record the error message if there is any.
7974 Return TRUE on success; otherwise return FALSE. */
7977 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7980 aarch64_operand_error error_info
;
7981 memset (&error_info
, '\0', sizeof (error_info
));
7982 error_info
.kind
= AARCH64_OPDE_NIL
;
7983 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7984 && !error_info
.non_fatal
)
7987 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7988 record_operand_error_info (opcode
, &error_info
);
7989 return error_info
.non_fatal
;
7992 #ifdef DEBUG_AARCH64
7994 dump_opcode_operands (const aarch64_opcode
*opcode
)
7997 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7999 aarch64_verbose ("\t\t opnd%d: %s", i
,
8000 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
8001 ? aarch64_get_operand_name (opcode
->operands
[i
])
8002 : aarch64_get_operand_desc (opcode
->operands
[i
]));
8006 #endif /* DEBUG_AARCH64 */
8008 /* This is the guts of the machine-dependent assembler. STR points to a
8009 machine dependent instruction. This function is supposed to emit
8010 the frags/bytes it assembles to. */
8013 md_assemble (char *str
)
8015 templates
*template;
8016 const aarch64_opcode
*opcode
;
8017 struct aarch64_segment_info_type
*tc_seg_info
;
8018 aarch64_inst
*inst_base
;
8019 unsigned saved_cond
;
8021 /* Align the previous label if needed. */
8022 if (last_label_seen
!= NULL
)
8024 symbol_set_frag (last_label_seen
, frag_now
);
8025 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8026 S_SET_SEGMENT (last_label_seen
, now_seg
);
8029 /* Update the current insn_sequence from the segment. */
8030 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8031 insn_sequence
= &tc_seg_info
->insn_sequence
;
8032 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8034 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8036 DEBUG_TRACE ("\n\n");
8037 DEBUG_TRACE ("==============================");
8038 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8040 /* Scan up to the end of the mnemonic, which must end in whitespace,
8041 '.', or end of string. */
8044 for (; is_part_of_name (*p
); p
++)
8045 if (*p
== '.' && !dot
)
8050 as_bad (_("unknown mnemonic -- `%s'"), str
);
8054 if (!dot
&& create_register_alias (str
, p
))
8057 template = opcode_lookup (str
, dot
, p
);
8060 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8065 skip_whitespace (p
);
8068 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8069 get_mnemonic_name (str
), str
);
8073 init_operand_error_report ();
8075 /* Sections are assumed to start aligned. In executable section, there is no
8076 MAP_DATA symbol pending. So we only align the address during
8077 MAP_DATA --> MAP_INSN transition.
8078 For other sections, this is not guaranteed. */
8079 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8080 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8081 frag_align_code (2, 0);
8083 saved_cond
= inst
.cond
;
8084 reset_aarch64_instruction (&inst
);
8085 inst
.cond
= saved_cond
;
8087 /* Iterate through all opcode entries with the same mnemonic name. */
8090 opcode
= template->opcode
;
8092 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8093 #ifdef DEBUG_AARCH64
8095 dump_opcode_operands (opcode
);
8096 #endif /* DEBUG_AARCH64 */
8098 mapping_state (MAP_INSN
);
8100 inst_base
= &inst
.base
;
8101 inst_base
->opcode
= opcode
;
8103 /* Truly conditionally executed instructions, e.g. b.cond. */
8104 if (opcode
->flags
& F_COND
)
8106 gas_assert (inst
.cond
!= COND_ALWAYS
);
8107 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8108 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8110 else if (inst
.cond
!= COND_ALWAYS
)
8112 /* It shouldn't arrive here, where the assembly looks like a
8113 conditional instruction but the found opcode is unconditional. */
8118 if (parse_operands (p
, opcode
)
8119 && programmer_friendly_fixup (&inst
)
8120 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8122 /* Check that this instruction is supported for this CPU. */
8123 if (!opcode
->avariant
8124 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8126 as_bad (_("selected processor does not support `%s'"), str
);
8130 warn_unpredictable_ldst (&inst
, str
);
8132 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8133 || !inst
.reloc
.need_libopcodes_p
)
8137 /* If there is relocation generated for the instruction,
8138 store the instruction information for the future fix-up. */
8139 struct aarch64_inst
*copy
;
8140 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8141 copy
= XNEW (struct aarch64_inst
);
8142 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8146 /* Issue non-fatal messages if any. */
8147 output_operand_error_report (str
, true);
8151 template = template->next
;
8152 if (template != NULL
)
8154 reset_aarch64_instruction (&inst
);
8155 inst
.cond
= saved_cond
;
8158 while (template != NULL
);
8160 /* Issue the error messages if any. */
8161 output_operand_error_report (str
, false);
8164 /* Various frobbings of labels and their addresses. */
8167 aarch64_start_line_hook (void)
8169 last_label_seen
= NULL
;
8173 aarch64_frob_label (symbolS
* sym
)
8175 last_label_seen
= sym
;
8177 dwarf2_emit_label (sym
);
8181 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8183 /* Check to see if we have a block to close. */
8184 force_automatic_sequence_close ();
8188 aarch64_data_in_code (void)
8190 if (startswith (input_line_pointer
+ 1, "data:"))
8192 *input_line_pointer
= '/';
8193 input_line_pointer
+= 5;
8194 *input_line_pointer
= 0;
8202 aarch64_canonicalize_symbol_name (char *name
)
8206 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8207 *(name
+ len
- 5) = 0;
8212 /* Table of all register names defined by default. The user can
8213 define additional names with .req. Note that all register names
8214 should appear in both upper and lowercase variants. Some registers
8215 also have mixed-case names. */
8217 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8218 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8219 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8220 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8221 #define REGSET16(p,t) \
8222 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8223 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8224 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8225 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8226 #define REGSET16S(p,s,t) \
8227 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8228 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8229 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8230 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8231 #define REGSET31(p,t) \
8233 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8234 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8235 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8236 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8237 #define REGSET(p,t) \
8238 REGSET31(p,t), REGNUM(p,31,t)
8240 /* These go into aarch64_reg_hsh hash-table. */
8241 static const reg_entry reg_names
[] = {
8242 /* Integer registers. */
8243 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8244 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8246 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8247 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8248 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8249 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8250 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8251 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8253 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8254 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8256 /* Floating-point single precision registers. */
8257 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8259 /* Floating-point double precision registers. */
8260 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8262 /* Floating-point half precision registers. */
8263 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8265 /* Floating-point byte precision registers. */
8266 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8268 /* Floating-point quad precision registers. */
8269 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8271 /* FP/SIMD registers. */
8272 REGSET (v
, VN
), REGSET (V
, VN
),
8274 /* SVE vector registers. */
8275 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8277 /* SVE predicate registers. */
8278 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8280 /* SME ZA tile registers. */
8281 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8283 /* SME ZA tile registers (horizontal slice). */
8284 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8286 /* SME ZA tile registers (vertical slice). */
8287 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8305 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8306 static const asm_nzcv nzcv_names
[] = {
8307 {"nzcv", B (n
, z
, c
, v
)},
8308 {"nzcV", B (n
, z
, c
, V
)},
8309 {"nzCv", B (n
, z
, C
, v
)},
8310 {"nzCV", B (n
, z
, C
, V
)},
8311 {"nZcv", B (n
, Z
, c
, v
)},
8312 {"nZcV", B (n
, Z
, c
, V
)},
8313 {"nZCv", B (n
, Z
, C
, v
)},
8314 {"nZCV", B (n
, Z
, C
, V
)},
8315 {"Nzcv", B (N
, z
, c
, v
)},
8316 {"NzcV", B (N
, z
, c
, V
)},
8317 {"NzCv", B (N
, z
, C
, v
)},
8318 {"NzCV", B (N
, z
, C
, V
)},
8319 {"NZcv", B (N
, Z
, c
, v
)},
8320 {"NZcV", B (N
, Z
, c
, V
)},
8321 {"NZCv", B (N
, Z
, C
, v
)},
8322 {"NZCV", B (N
, Z
, C
, V
)}
8335 /* MD interface: bits in the object file. */
8337 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8338 for use in the a.out file, and stores them in the array pointed to by buf.
8339 This knows about the endian-ness of the target machine and does
8340 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8341 2 (short) and 4 (long) Floating numbers are put out as a series of
8342 LITTLENUMS (shorts, here at least). */
8345 md_number_to_chars (char *buf
, valueT val
, int n
)
8347 if (target_big_endian
)
8348 number_to_chars_bigendian (buf
, val
, n
);
8350 number_to_chars_littleendian (buf
, val
, n
);
8353 /* MD interface: Sections. */
8355 /* Estimate the size of a frag before relaxing. Assume everything fits in
8359 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8365 /* Round up a section size to the appropriate boundary. */
8368 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8373 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8374 of an rs_align_code fragment.
8376 Here we fill the frag with the appropriate info for padding the
8377 output stream. The resulting frag will consist of a fixed (fr_fix)
8378 and of a repeating (fr_var) part.
8380 The fixed content is always emitted before the repeating content and
8381 these two parts are used as follows in constructing the output:
8382 - the fixed part will be used to align to a valid instruction word
8383 boundary, in case that we start at a misaligned address; as no
8384 executable instruction can live at the misaligned location, we
8385 simply fill with zeros;
8386 - the variable part will be used to cover the remaining padding and
8387 we fill using the AArch64 NOP instruction.
8389 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8390 enough storage space for up to 3 bytes for padding the back to a valid
8391 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8394 aarch64_handle_align (fragS
* fragP
)
8396 /* NOP = d503201f */
8397 /* AArch64 instructions are always little-endian. */
8398 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8400 int bytes
, fix
, noop_size
;
8403 if (fragP
->fr_type
!= rs_align_code
)
8406 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8407 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8410 gas_assert (fragP
->tc_frag_data
.recorded
);
8413 noop_size
= sizeof (aarch64_noop
);
8415 fix
= bytes
& (noop_size
- 1);
8418 #if defined OBJ_ELF || defined OBJ_COFF
8419 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8423 fragP
->fr_fix
+= fix
;
8427 memcpy (p
, aarch64_noop
, noop_size
);
8428 fragP
->fr_var
= noop_size
;
8431 /* Perform target specific initialisation of a frag.
8432 Note - despite the name this initialisation is not done when the frag
8433 is created, but only when its type is assigned. A frag can be created
8434 and used a long time before its type is set, so beware of assuming that
8435 this initialisation is performed first. */
8439 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8440 int max_chars ATTRIBUTE_UNUSED
)
8444 #else /* OBJ_ELF is defined. */
8446 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8448 /* Record a mapping symbol for alignment frags. We will delete this
8449 later if the alignment ends up empty. */
8450 if (!fragP
->tc_frag_data
.recorded
)
8451 fragP
->tc_frag_data
.recorded
= 1;
8453 /* PR 21809: Do not set a mapping state for debug sections
8454 - it just confuses other tools. */
8455 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8458 switch (fragP
->fr_type
)
8462 mapping_state_2 (MAP_DATA
, max_chars
);
8465 /* PR 20364: We can get alignment frags in code sections,
8466 so do not just assume that we should use the MAP_DATA state. */
8467 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8470 mapping_state_2 (MAP_INSN
, max_chars
);
8477 /* Whether SFrame unwind info is supported. */
8480 aarch64_support_sframe_p (void)
8482 /* At this time, SFrame is supported for aarch64 only. */
8483 return (aarch64_abi
== AARCH64_ABI_LP64
);
8486 /* Specify if RA tracking is needed. */
8489 aarch64_sframe_ra_tracking_p (void)
8494 /* Specify the fixed offset to recover RA from CFA.
8495 (useful only when RA tracking is not needed). */
8498 aarch64_sframe_cfa_ra_offset (void)
8500 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8503 /* Get the abi/arch indentifier for SFrame. */
8506 aarch64_sframe_get_abi_arch (void)
8508 unsigned char sframe_abi_arch
= 0;
8510 if (aarch64_support_sframe_p ())
8512 sframe_abi_arch
= target_big_endian
8513 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8514 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8517 return sframe_abi_arch
;
8520 #endif /* OBJ_ELF */
8522 /* Initialize the DWARF-2 unwind information for this procedure. */
8525 tc_aarch64_frame_initial_instructions (void)
8527 cfi_add_CFA_def_cfa (REG_SP
, 0);
8530 /* Convert REGNAME to a DWARF-2 register number. */
8533 tc_aarch64_regname_to_dw2regnum (char *regname
)
8535 const reg_entry
*reg
= parse_reg (®name
);
8541 case REG_TYPE_SP_32
:
8542 case REG_TYPE_SP_64
:
8552 return reg
->number
+ 64;
8560 /* Implement DWARF2_ADDR_SIZE. */
8563 aarch64_dwarf2_addr_size (void)
8569 return bfd_arch_bits_per_address (stdoutput
) / 8;
8572 /* MD interface: Symbol and relocation handling. */
8574 /* Return the address within the segment that a PC-relative fixup is
8575 relative to. For AArch64 PC-relative fixups applied to instructions
8576 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8579 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8581 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8583 /* If this is pc-relative and we are going to emit a relocation
8584 then we just want to put out any pipeline compensation that the linker
8585 will need. Otherwise we want to use the calculated base. */
8587 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8588 || aarch64_force_relocation (fixP
)))
8591 /* AArch64 should be consistent for all pc-relative relocations. */
8592 return base
+ AARCH64_PCREL_OFFSET
;
8595 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8596 Otherwise we have no need to default values of symbols. */
8599 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8602 if (name
[0] == '_' && name
[1] == 'G'
8603 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8607 if (symbol_find (name
))
8608 as_bad (_("GOT already in the symbol table"));
8610 GOT_symbol
= symbol_new (name
, undefined_section
,
8611 &zero_address_frag
, 0);
8621 /* Return non-zero if the indicated VALUE has overflowed the maximum
8622 range expressible by a unsigned number with the indicated number of
8626 unsigned_overflow (valueT value
, unsigned bits
)
8629 if (bits
>= sizeof (valueT
) * 8)
8631 lim
= (valueT
) 1 << bits
;
8632 return (value
>= lim
);
8636 /* Return non-zero if the indicated VALUE has overflowed the maximum
8637 range expressible by an signed number with the indicated number of
8641 signed_overflow (offsetT value
, unsigned bits
)
8644 if (bits
>= sizeof (offsetT
) * 8)
8646 lim
= (offsetT
) 1 << (bits
- 1);
8647 return (value
< -lim
|| value
>= lim
);
8650 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8651 unsigned immediate offset load/store instruction, try to encode it as
8652 an unscaled, 9-bit, signed immediate offset load/store instruction.
8653 Return TRUE if it is successful; otherwise return FALSE.
8655 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8656 in response to the standard LDR/STR mnemonics when the immediate offset is
8657 unambiguous, i.e. when it is negative or unaligned. */
8660 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8663 enum aarch64_op new_op
;
8664 const aarch64_opcode
*new_opcode
;
8666 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8668 switch (instr
->opcode
->op
)
8670 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8671 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8672 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8673 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8674 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8675 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8676 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8677 case OP_STR_POS
: new_op
= OP_STUR
; break;
8678 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8679 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8680 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8681 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8682 default: new_op
= OP_NIL
; break;
8685 if (new_op
== OP_NIL
)
8688 new_opcode
= aarch64_get_opcode (new_op
);
8689 gas_assert (new_opcode
!= NULL
);
8691 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8692 instr
->opcode
->op
, new_opcode
->op
);
8694 aarch64_replace_opcode (instr
, new_opcode
);
8696 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8697 qualifier matching may fail because the out-of-date qualifier will
8698 prevent the operand being updated with a new and correct qualifier. */
8699 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8700 AARCH64_OPND_ADDR_SIMM9
);
8701 gas_assert (idx
== 1);
8702 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8704 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8706 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8713 /* Called by fix_insn to fix a MOV immediate alias instruction.
8715 Operand for a generic move immediate instruction, which is an alias
8716 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8717 a 32-bit/64-bit immediate value into general register. An assembler error
8718 shall result if the immediate cannot be created by a single one of these
8719 instructions. If there is a choice, then to ensure reversability an
8720 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8723 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8725 const aarch64_opcode
*opcode
;
8727 /* Need to check if the destination is SP/ZR. The check has to be done
8728 before any aarch64_replace_opcode. */
8729 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8730 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8732 instr
->operands
[1].imm
.value
= value
;
8733 instr
->operands
[1].skip
= 0;
8737 /* Try the MOVZ alias. */
8738 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8739 aarch64_replace_opcode (instr
, opcode
);
8740 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8741 &instr
->value
, NULL
, NULL
, insn_sequence
))
8743 put_aarch64_insn (buf
, instr
->value
);
8746 /* Try the MOVK alias. */
8747 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8748 aarch64_replace_opcode (instr
, opcode
);
8749 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8750 &instr
->value
, NULL
, NULL
, insn_sequence
))
8752 put_aarch64_insn (buf
, instr
->value
);
8757 if (try_mov_bitmask_p
)
8759 /* Try the ORR alias. */
8760 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8761 aarch64_replace_opcode (instr
, opcode
);
8762 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8763 &instr
->value
, NULL
, NULL
, insn_sequence
))
8765 put_aarch64_insn (buf
, instr
->value
);
8770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8771 _("immediate cannot be moved by a single instruction"));
8774 /* An instruction operand which is immediate related may have symbol used
8775 in the assembly, e.g.
8778 .set u32, 0x00ffff00
8780 At the time when the assembly instruction is parsed, a referenced symbol,
8781 like 'u32' in the above example may not have been seen; a fixS is created
8782 in such a case and is handled here after symbols have been resolved.
8783 Instruction is fixed up with VALUE using the information in *FIXP plus
8784 extra information in FLAGS.
8786 This function is called by md_apply_fix to fix up instructions that need
8787 a fix-up described above but does not involve any linker-time relocation. */
8790 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8794 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8795 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8796 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8800 /* Now the instruction is about to be fixed-up, so the operand that
8801 was previously marked as 'ignored' needs to be unmarked in order
8802 to get the encoding done properly. */
8803 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8804 new_inst
->operands
[idx
].skip
= 0;
8807 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8811 case AARCH64_OPND_EXCEPTION
:
8812 case AARCH64_OPND_UNDEFINED
:
8813 if (unsigned_overflow (value
, 16))
8814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8815 _("immediate out of range"));
8816 insn
= get_aarch64_insn (buf
);
8817 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8818 put_aarch64_insn (buf
, insn
);
8821 case AARCH64_OPND_AIMM
:
8822 /* ADD or SUB with immediate.
8823 NOTE this assumes we come here with a add/sub shifted reg encoding
8824 3 322|2222|2 2 2 21111 111111
8825 1 098|7654|3 2 1 09876 543210 98765 43210
8826 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8827 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8828 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8829 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8831 3 322|2222|2 2 221111111111
8832 1 098|7654|3 2 109876543210 98765 43210
8833 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8834 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8835 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8836 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8837 Fields sf Rn Rd are already set. */
8838 insn
= get_aarch64_insn (buf
);
8842 insn
= reencode_addsub_switch_add_sub (insn
);
8846 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8847 && unsigned_overflow (value
, 12))
8849 /* Try to shift the value by 12 to make it fit. */
8850 if (((value
>> 12) << 12) == value
8851 && ! unsigned_overflow (value
, 12 + 12))
8854 insn
|= encode_addsub_imm_shift_amount (1);
8858 if (unsigned_overflow (value
, 12))
8859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8860 _("immediate out of range"));
8862 insn
|= encode_addsub_imm (value
);
8864 put_aarch64_insn (buf
, insn
);
8867 case AARCH64_OPND_SIMD_IMM
:
8868 case AARCH64_OPND_SIMD_IMM_SFT
:
8869 case AARCH64_OPND_LIMM
:
8870 /* Bit mask immediate. */
8871 gas_assert (new_inst
!= NULL
);
8872 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8873 new_inst
->operands
[idx
].imm
.value
= value
;
8874 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8875 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8876 put_aarch64_insn (buf
, new_inst
->value
);
8878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8879 _("invalid immediate"));
8882 case AARCH64_OPND_HALF
:
8883 /* 16-bit unsigned immediate. */
8884 if (unsigned_overflow (value
, 16))
8885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8886 _("immediate out of range"));
8887 insn
= get_aarch64_insn (buf
);
8888 insn
|= encode_movw_imm (value
& 0xffff);
8889 put_aarch64_insn (buf
, insn
);
8892 case AARCH64_OPND_IMM_MOV
:
8893 /* Operand for a generic move immediate instruction, which is
8894 an alias instruction that generates a single MOVZ, MOVN or ORR
8895 instruction to loads a 32-bit/64-bit immediate value into general
8896 register. An assembler error shall result if the immediate cannot be
8897 created by a single one of these instructions. If there is a choice,
8898 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8899 and MOVZ or MOVN to ORR. */
8900 gas_assert (new_inst
!= NULL
);
8901 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8904 case AARCH64_OPND_ADDR_SIMM7
:
8905 case AARCH64_OPND_ADDR_SIMM9
:
8906 case AARCH64_OPND_ADDR_SIMM9_2
:
8907 case AARCH64_OPND_ADDR_SIMM10
:
8908 case AARCH64_OPND_ADDR_UIMM12
:
8909 case AARCH64_OPND_ADDR_SIMM11
:
8910 case AARCH64_OPND_ADDR_SIMM13
:
8911 /* Immediate offset in an address. */
8912 insn
= get_aarch64_insn (buf
);
8914 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8915 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8916 || new_inst
->opcode
->operands
[2] == opnd
);
8918 /* Get the index of the address operand. */
8919 if (new_inst
->opcode
->operands
[1] == opnd
)
8920 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8923 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8926 /* Update the resolved offset value. */
8927 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8929 /* Encode/fix-up. */
8930 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8931 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8933 put_aarch64_insn (buf
, new_inst
->value
);
8936 else if (new_inst
->opcode
->iclass
== ldst_pos
8937 && try_to_encode_as_unscaled_ldst (new_inst
))
8939 put_aarch64_insn (buf
, new_inst
->value
);
8943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8944 _("immediate offset out of range"));
8949 as_fatal (_("unhandled operand code %d"), opnd
);
8953 /* Apply a fixup (fixP) to segment data, once it has been determined
8954 by our caller that we have all the info we need to fix it up.
8956 Parameter valP is the pointer to the value of the bits. */
8959 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8961 offsetT value
= *valP
;
8963 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8965 unsigned flags
= fixP
->fx_addnumber
;
8967 DEBUG_TRACE ("\n\n");
8968 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8969 DEBUG_TRACE ("Enter md_apply_fix");
8971 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8973 /* Note whether this will delete the relocation. */
8975 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8976 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8979 /* Process the relocations. */
8980 switch (fixP
->fx_r_type
)
8982 case BFD_RELOC_NONE
:
8983 /* This will need to go in the object file. */
8988 case BFD_RELOC_8_PCREL
:
8989 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8990 md_number_to_chars (buf
, value
, 1);
8994 case BFD_RELOC_16_PCREL
:
8995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8996 md_number_to_chars (buf
, value
, 2);
9000 case BFD_RELOC_32_PCREL
:
9001 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9002 md_number_to_chars (buf
, value
, 4);
9006 case BFD_RELOC_64_PCREL
:
9007 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9008 md_number_to_chars (buf
, value
, 8);
9011 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9012 /* We claim that these fixups have been processed here, even if
9013 in fact we generate an error because we do not have a reloc
9014 for them, so tc_gen_reloc() will reject them. */
9016 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
9018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9019 _("undefined symbol %s used as an immediate value"),
9020 S_GET_NAME (fixP
->fx_addsy
));
9021 goto apply_fix_return
;
9023 fix_insn (fixP
, flags
, value
);
9026 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
9027 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9031 _("pc-relative load offset not word aligned"));
9032 if (signed_overflow (value
, 21))
9033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9034 _("pc-relative load offset out of range"));
9035 insn
= get_aarch64_insn (buf
);
9036 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9037 put_aarch64_insn (buf
, insn
);
9041 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9042 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9044 if (signed_overflow (value
, 21))
9045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9046 _("pc-relative address offset out of range"));
9047 insn
= get_aarch64_insn (buf
);
9048 insn
|= encode_adr_imm (value
);
9049 put_aarch64_insn (buf
, insn
);
9053 case BFD_RELOC_AARCH64_BRANCH19
:
9054 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9058 _("conditional branch target not word aligned"));
9059 if (signed_overflow (value
, 21))
9060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9061 _("conditional branch out of range"));
9062 insn
= get_aarch64_insn (buf
);
9063 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9064 put_aarch64_insn (buf
, insn
);
9068 case BFD_RELOC_AARCH64_TSTBR14
:
9069 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9073 _("conditional branch target not word aligned"));
9074 if (signed_overflow (value
, 16))
9075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9076 _("conditional branch out of range"));
9077 insn
= get_aarch64_insn (buf
);
9078 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9079 put_aarch64_insn (buf
, insn
);
9083 case BFD_RELOC_AARCH64_CALL26
:
9084 case BFD_RELOC_AARCH64_JUMP26
:
9085 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9089 _("branch target not word aligned"));
9090 if (signed_overflow (value
, 28))
9091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9092 _("branch out of range"));
9093 insn
= get_aarch64_insn (buf
);
9094 insn
|= encode_branch_ofs_26 (value
>> 2);
9095 put_aarch64_insn (buf
, insn
);
9099 case BFD_RELOC_AARCH64_MOVW_G0
:
9100 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9101 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9102 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9103 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9104 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9107 case BFD_RELOC_AARCH64_MOVW_G1
:
9108 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9109 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9110 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9111 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9112 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9115 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9117 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9118 /* Should always be exported to object file, see
9119 aarch64_force_relocation(). */
9120 gas_assert (!fixP
->fx_done
);
9121 gas_assert (seg
->use_rela_p
);
9123 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9125 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9126 /* Should always be exported to object file, see
9127 aarch64_force_relocation(). */
9128 gas_assert (!fixP
->fx_done
);
9129 gas_assert (seg
->use_rela_p
);
9131 case BFD_RELOC_AARCH64_MOVW_G2
:
9132 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9133 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9134 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9135 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9138 case BFD_RELOC_AARCH64_MOVW_G3
:
9139 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9142 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9144 insn
= get_aarch64_insn (buf
);
9148 /* REL signed addend must fit in 16 bits */
9149 if (signed_overflow (value
, 16))
9150 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9151 _("offset out of range"));
9155 /* Check for overflow and scale. */
9156 switch (fixP
->fx_r_type
)
9158 case BFD_RELOC_AARCH64_MOVW_G0
:
9159 case BFD_RELOC_AARCH64_MOVW_G1
:
9160 case BFD_RELOC_AARCH64_MOVW_G2
:
9161 case BFD_RELOC_AARCH64_MOVW_G3
:
9162 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9163 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9164 if (unsigned_overflow (value
, scale
+ 16))
9165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9166 _("unsigned value out of range"));
9168 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9169 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9170 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9171 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9172 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9173 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9174 /* NOTE: We can only come here with movz or movn. */
9175 if (signed_overflow (value
, scale
+ 16))
9176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9177 _("signed value out of range"));
9180 /* Force use of MOVN. */
9182 insn
= reencode_movzn_to_movn (insn
);
9186 /* Force use of MOVZ. */
9187 insn
= reencode_movzn_to_movz (insn
);
9191 /* Unchecked relocations. */
9197 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9198 insn
|= encode_movw_imm (value
& 0xffff);
9200 put_aarch64_insn (buf
, insn
);
9204 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9205 fixP
->fx_r_type
= (ilp32_p
9206 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9207 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9208 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9209 /* Should always be exported to object file, see
9210 aarch64_force_relocation(). */
9211 gas_assert (!fixP
->fx_done
);
9212 gas_assert (seg
->use_rela_p
);
9215 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9216 fixP
->fx_r_type
= (ilp32_p
9217 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9218 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9219 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9220 /* Should always be exported to object file, see
9221 aarch64_force_relocation(). */
9222 gas_assert (!fixP
->fx_done
);
9223 gas_assert (seg
->use_rela_p
);
9226 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9227 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9228 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9229 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9230 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9231 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9232 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9233 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9234 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9235 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9236 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9237 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9238 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9239 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9240 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9241 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9242 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9243 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9244 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9245 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9246 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9247 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9248 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9249 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9250 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9251 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9252 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9253 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9254 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9255 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9256 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9257 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9258 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9259 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9260 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9261 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9262 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9263 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9264 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9265 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9266 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9267 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9268 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9269 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9270 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9271 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9272 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9273 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9274 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9275 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9277 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9278 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9279 /* Should always be exported to object file, see
9280 aarch64_force_relocation(). */
9281 gas_assert (!fixP
->fx_done
);
9282 gas_assert (seg
->use_rela_p
);
9285 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9286 /* Should always be exported to object file, see
9287 aarch64_force_relocation(). */
9288 fixP
->fx_r_type
= (ilp32_p
9289 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9290 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9291 gas_assert (!fixP
->fx_done
);
9292 gas_assert (seg
->use_rela_p
);
9295 case BFD_RELOC_AARCH64_ADD_LO12
:
9296 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9297 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9298 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9299 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9300 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9301 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9302 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9303 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9304 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9305 case BFD_RELOC_AARCH64_LDST128_LO12
:
9306 case BFD_RELOC_AARCH64_LDST16_LO12
:
9307 case BFD_RELOC_AARCH64_LDST32_LO12
:
9308 case BFD_RELOC_AARCH64_LDST64_LO12
:
9309 case BFD_RELOC_AARCH64_LDST8_LO12
:
9310 /* Should always be exported to object file, see
9311 aarch64_force_relocation(). */
9312 gas_assert (!fixP
->fx_done
);
9313 gas_assert (seg
->use_rela_p
);
9316 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9317 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9318 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9321 case BFD_RELOC_UNUSED
:
9322 /* An error will already have been reported. */
9326 case BFD_RELOC_32_SECREL
:
9327 case BFD_RELOC_16_SECIDX
:
9331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9332 _("unexpected %s fixup"),
9333 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9338 /* Free the allocated the struct aarch64_inst.
9339 N.B. currently there are very limited number of fix-up types actually use
9340 this field, so the impact on the performance should be minimal . */
9341 free (fixP
->tc_fix_data
.inst
);
9346 /* Translate internal representation of relocation info to BFD target
9350 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9353 bfd_reloc_code_real_type code
;
9355 reloc
= XNEW (arelent
);
9357 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9358 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9359 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9363 if (section
->use_rela_p
)
9364 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9366 fixp
->fx_offset
= reloc
->address
;
9368 reloc
->addend
= fixp
->fx_offset
;
9370 code
= fixp
->fx_r_type
;
9375 code
= BFD_RELOC_16_PCREL
;
9380 code
= BFD_RELOC_32_PCREL
;
9385 code
= BFD_RELOC_64_PCREL
;
9392 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9393 if (reloc
->howto
== NULL
)
9395 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9397 ("cannot represent %s relocation in this object file format"),
9398 bfd_get_reloc_code_name (code
));
9405 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9408 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9410 bfd_reloc_code_real_type type
;
9414 if (exp
->X_op
== O_secrel
)
9416 exp
->X_op
= O_symbol
;
9417 type
= BFD_RELOC_32_SECREL
;
9419 else if (exp
->X_op
== O_secidx
)
9421 exp
->X_op
= O_symbol
;
9422 type
= BFD_RELOC_16_SECIDX
;
9428 FIXME: @@ Should look at CPU word size. */
9435 type
= BFD_RELOC_16
;
9438 type
= BFD_RELOC_32
;
9441 type
= BFD_RELOC_64
;
9444 as_bad (_("cannot do %u-byte relocation"), size
);
9445 type
= BFD_RELOC_UNUSED
;
9452 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9455 /* Implement md_after_parse_args. This is the earliest time we need to decide
9456 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9459 aarch64_after_parse_args (void)
9461 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9465 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9466 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9467 aarch64_abi
= AARCH64_ABI_ILP32
;
9469 aarch64_abi
= AARCH64_ABI_LP64
;
9471 aarch64_abi
= AARCH64_ABI_LLP64
;
9477 elf64_aarch64_target_format (void)
9480 /* FIXME: What to do for ilp32_p ? */
9481 if (target_big_endian
)
9482 return "elf64-bigaarch64-cloudabi";
9484 return "elf64-littleaarch64-cloudabi";
9486 if (target_big_endian
)
9487 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9489 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9494 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9496 elf_frob_symbol (symp
, puntp
);
9498 #elif defined OBJ_COFF
9500 coff_aarch64_target_format (void)
9502 return "pe-aarch64-little";
9506 /* MD interface: Finalization. */
9508 /* A good place to do this, although this was probably not intended
9509 for this kind of use. We need to dump the literal pool before
9510 references are made to a null symbol pointer. */
9513 aarch64_cleanup (void)
9517 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9519 /* Put it at the end of the relevant section. */
9520 subseg_set (pool
->section
, pool
->sub_section
);
9526 /* Remove any excess mapping symbols generated for alignment frags in
9527 SEC. We may have created a mapping symbol before a zero byte
9528 alignment; remove it if there's a mapping symbol after the
9531 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9532 void *dummy ATTRIBUTE_UNUSED
)
9534 segment_info_type
*seginfo
= seg_info (sec
);
9537 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9540 for (fragp
= seginfo
->frchainP
->frch_root
;
9541 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9543 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9544 fragS
*next
= fragp
->fr_next
;
9546 /* Variable-sized frags have been converted to fixed size by
9547 this point. But if this was variable-sized to start with,
9548 there will be a fixed-size frag after it. So don't handle
9550 if (sym
== NULL
|| next
== NULL
)
9553 if (S_GET_VALUE (sym
) < next
->fr_address
)
9554 /* Not at the end of this frag. */
9556 know (S_GET_VALUE (sym
) == next
->fr_address
);
9560 if (next
->tc_frag_data
.first_map
!= NULL
)
9562 /* Next frag starts with a mapping symbol. Discard this
9564 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9568 if (next
->fr_next
== NULL
)
9570 /* This mapping symbol is at the end of the section. Discard
9572 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9573 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9577 /* As long as we have empty frags without any mapping symbols,
9579 /* If the next frag is non-empty and does not start with a
9580 mapping symbol, then this mapping symbol is required. */
9581 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9584 next
= next
->fr_next
;
9586 while (next
!= NULL
);
9591 /* Adjust the symbol table. */
9594 aarch64_adjust_symtab (void)
9597 /* Remove any overlapping mapping symbols generated by alignment frags. */
9598 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9599 /* Now do generic ELF adjustments. */
9600 elf_adjust_symtab ();
9605 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9607 str_hash_insert (table
, key
, value
, 0);
9611 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9613 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9614 checked_hash_insert (table
, key
, value
);
9618 fill_instruction_hash_table (void)
9620 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9622 while (opcode
->name
!= NULL
)
9624 templates
*templ
, *new_templ
;
9625 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9627 new_templ
= XNEW (templates
);
9628 new_templ
->opcode
= opcode
;
9629 new_templ
->next
= NULL
;
9632 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9635 new_templ
->next
= templ
->next
;
9636 templ
->next
= new_templ
;
9643 convert_to_upper (char *dst
, const char *src
, size_t num
)
9646 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9647 *dst
= TOUPPER (*src
);
9651 /* Assume STR point to a lower-case string, allocate, convert and return
9652 the corresponding upper-case string. */
9653 static inline const char*
9654 get_upper_str (const char *str
)
9657 size_t len
= strlen (str
);
9658 ret
= XNEWVEC (char, len
+ 1);
9659 convert_to_upper (ret
, str
, len
);
9663 /* MD interface: Initialization. */
9671 aarch64_ops_hsh
= str_htab_create ();
9672 aarch64_cond_hsh
= str_htab_create ();
9673 aarch64_shift_hsh
= str_htab_create ();
9674 aarch64_sys_regs_hsh
= str_htab_create ();
9675 aarch64_pstatefield_hsh
= str_htab_create ();
9676 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9677 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9678 aarch64_sys_regs_at_hsh
= str_htab_create ();
9679 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9680 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9681 aarch64_reg_hsh
= str_htab_create ();
9682 aarch64_barrier_opt_hsh
= str_htab_create ();
9683 aarch64_nzcv_hsh
= str_htab_create ();
9684 aarch64_pldop_hsh
= str_htab_create ();
9685 aarch64_hint_opt_hsh
= str_htab_create ();
9687 fill_instruction_hash_table ();
9689 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9690 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9691 (void *) (aarch64_sys_regs
+ i
));
9693 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9694 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9695 aarch64_pstatefields
[i
].name
,
9696 (void *) (aarch64_pstatefields
+ i
));
9698 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9699 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9700 aarch64_sys_regs_ic
[i
].name
,
9701 (void *) (aarch64_sys_regs_ic
+ i
));
9703 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9704 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9705 aarch64_sys_regs_dc
[i
].name
,
9706 (void *) (aarch64_sys_regs_dc
+ i
));
9708 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9709 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9710 aarch64_sys_regs_at
[i
].name
,
9711 (void *) (aarch64_sys_regs_at
+ i
));
9713 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9714 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9715 aarch64_sys_regs_tlbi
[i
].name
,
9716 (void *) (aarch64_sys_regs_tlbi
+ i
));
9718 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9719 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9720 aarch64_sys_regs_sr
[i
].name
,
9721 (void *) (aarch64_sys_regs_sr
+ i
));
9723 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9724 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9725 (void *) (reg_names
+ i
));
9727 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9728 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9729 (void *) (nzcv_names
+ i
));
9731 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9733 const char *name
= aarch64_operand_modifiers
[i
].name
;
9734 checked_hash_insert (aarch64_shift_hsh
, name
,
9735 (void *) (aarch64_operand_modifiers
+ i
));
9736 /* Also hash the name in the upper case. */
9737 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9738 (void *) (aarch64_operand_modifiers
+ i
));
9741 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9744 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9745 the same condition code. */
9746 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9748 const char *name
= aarch64_conds
[i
].names
[j
];
9751 checked_hash_insert (aarch64_cond_hsh
, name
,
9752 (void *) (aarch64_conds
+ i
));
9753 /* Also hash the name in the upper case. */
9754 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9755 (void *) (aarch64_conds
+ i
));
9759 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9761 const char *name
= aarch64_barrier_options
[i
].name
;
9762 /* Skip xx00 - the unallocated values of option. */
9765 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9766 (void *) (aarch64_barrier_options
+ i
));
9767 /* Also hash the name in the upper case. */
9768 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9769 (void *) (aarch64_barrier_options
+ i
));
9772 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9774 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9775 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9776 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9777 /* Also hash the name in the upper case. */
9778 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9779 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9782 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9784 const char* name
= aarch64_prfops
[i
].name
;
9785 /* Skip the unallocated hint encodings. */
9788 checked_hash_insert (aarch64_pldop_hsh
, name
,
9789 (void *) (aarch64_prfops
+ i
));
9790 /* Also hash the name in the upper case. */
9791 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9792 (void *) (aarch64_prfops
+ i
));
9795 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9797 const char* name
= aarch64_hint_options
[i
].name
;
9798 const char* upper_name
= get_upper_str(name
);
9800 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9801 (void *) (aarch64_hint_options
+ i
));
9803 /* Also hash the name in the upper case if not the same. */
9804 if (strcmp (name
, upper_name
) != 0)
9805 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9806 (void *) (aarch64_hint_options
+ i
));
9809 /* Set the cpu variant based on the command-line options. */
9811 mcpu_cpu_opt
= march_cpu_opt
;
9814 mcpu_cpu_opt
= &cpu_default
;
9816 cpu_variant
= *mcpu_cpu_opt
;
9818 /* Record the CPU type. */
9820 mach
= bfd_mach_aarch64_ilp32
;
9822 mach
= bfd_mach_aarch64_llp64
;
9824 mach
= bfd_mach_aarch64
;
9826 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9828 /* FIXME - is there a better way to do it ? */
9829 aarch64_sframe_cfa_sp_reg
= 31;
9830 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9831 aarch64_sframe_cfa_ra_reg
= 30;
9835 /* Command line processing. */
9837 const char *md_shortopts
= "m:";
9839 #ifdef AARCH64_BI_ENDIAN
9840 #define OPTION_EB (OPTION_MD_BASE + 0)
9841 #define OPTION_EL (OPTION_MD_BASE + 1)
9843 #if TARGET_BYTES_BIG_ENDIAN
9844 #define OPTION_EB (OPTION_MD_BASE + 0)
9846 #define OPTION_EL (OPTION_MD_BASE + 1)
9850 struct option md_longopts
[] = {
9852 {"EB", no_argument
, NULL
, OPTION_EB
},
9855 {"EL", no_argument
, NULL
, OPTION_EL
},
9857 {NULL
, no_argument
, NULL
, 0}
9860 size_t md_longopts_size
= sizeof (md_longopts
);
9862 struct aarch64_option_table
9864 const char *option
; /* Option name to match. */
9865 const char *help
; /* Help information. */
9866 int *var
; /* Variable to change. */
9867 int value
; /* What to change it to. */
9868 char *deprecated
; /* If non-null, print this message. */
9871 static struct aarch64_option_table aarch64_opts
[] = {
9872 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9873 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9875 #ifdef DEBUG_AARCH64
9876 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9877 #endif /* DEBUG_AARCH64 */
9878 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9880 {"mno-verbose-error", N_("do not output verbose error messages"),
9881 &verbose_error_p
, 0, NULL
},
9882 {NULL
, NULL
, NULL
, 0, NULL
}
9885 struct aarch64_cpu_option_table
9888 const aarch64_feature_set value
;
9889 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9891 const char *canonical_name
;
9894 /* This list should, at a minimum, contain all the cpu names
9895 recognized by GCC. */
9896 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9897 {"all", AARCH64_ANY
, NULL
},
9898 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9899 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9900 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9901 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9902 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9903 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9904 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9905 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9906 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9907 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9908 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9909 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9910 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9911 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9913 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9914 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9916 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9917 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9919 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9920 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9921 | AARCH64_FEATURE_DOTPROD
9922 | AARCH64_FEATURE_SSBS
),
9924 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9925 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9926 | AARCH64_FEATURE_DOTPROD
9927 | AARCH64_FEATURE_SSBS
),
9929 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9930 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9931 | AARCH64_FEATURE_DOTPROD
9932 | AARCH64_FEATURE_SSBS
),
9934 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9935 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9936 | AARCH64_FEATURE_DOTPROD
9937 | AARCH64_FEATURE_SSBS
),
9939 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9941 | AARCH64_FEATURE_RCPC
9942 | AARCH64_FEATURE_DOTPROD
9943 | AARCH64_FEATURE_SSBS
9944 | AARCH64_FEATURE_PROFILE
),
9946 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9948 | AARCH64_FEATURE_RCPC
9949 | AARCH64_FEATURE_DOTPROD
9950 | AARCH64_FEATURE_SSBS
9951 | AARCH64_FEATURE_PROFILE
),
9953 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9954 AARCH64_FEATURE_DOTPROD
9955 | AARCH64_FEATURE_F16
9956 | AARCH64_FEATURE_FLAGM
9957 | AARCH64_FEATURE_PAC
9958 | AARCH64_FEATURE_PROFILE
9959 | AARCH64_FEATURE_RCPC
9960 | AARCH64_FEATURE_SSBS
),
9962 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9963 AARCH64_FEATURE_BFLOAT16
9964 | AARCH64_FEATURE_I8MM
9965 | AARCH64_FEATURE_MEMTAG
9966 | AARCH64_FEATURE_SVE2_BITPERM
),
9968 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9969 AARCH64_FEATURE_BFLOAT16
9970 | AARCH64_FEATURE_I8MM
9971 | AARCH64_FEATURE_MEMTAG
9972 | AARCH64_FEATURE_SVE2_BITPERM
),
9974 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9975 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9976 | AARCH64_FEATURE_DOTPROD
9977 | AARCH64_FEATURE_PROFILE
),
9979 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9980 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9981 "Samsung Exynos M1"},
9982 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9983 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9984 | AARCH64_FEATURE_RDMA
),
9986 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9987 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9988 | AARCH64_FEATURE_DOTPROD
9989 | AARCH64_FEATURE_SSBS
),
9991 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9992 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9993 | AARCH64_FEATURE_DOTPROD
9994 | AARCH64_FEATURE_PROFILE
),
9996 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9997 AARCH64_FEATURE_BFLOAT16
9998 | AARCH64_FEATURE_I8MM
9999 | AARCH64_FEATURE_F16
10000 | AARCH64_FEATURE_SVE
10001 | AARCH64_FEATURE_SVE2
10002 | AARCH64_FEATURE_SVE2_BITPERM
10003 | AARCH64_FEATURE_MEMTAG
10004 | AARCH64_FEATURE_RNG
),
10006 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10007 AARCH64_FEATURE_PROFILE
10008 | AARCH64_FEATURE_CVADP
10009 | AARCH64_FEATURE_SVE
10010 | AARCH64_FEATURE_SSBS
10011 | AARCH64_FEATURE_RNG
10012 | AARCH64_FEATURE_F16
10013 | AARCH64_FEATURE_BFLOAT16
10014 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
10015 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10016 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10017 | AARCH64_FEATURE_RDMA
),
10018 "Qualcomm QDF24XX"},
10019 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10020 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
10021 "Qualcomm Saphira"},
10022 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10023 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10024 "Cavium ThunderX"},
10025 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
10026 AARCH64_FEATURE_CRYPTO
),
10027 "Broadcom Vulcan"},
10028 /* The 'xgene-1' name is an older name for 'xgene1', which was used
10029 in earlier releases and is superseded by 'xgene1' in all
10031 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10032 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10033 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10034 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10035 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10036 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10037 AARCH64_FEATURE_F16
10038 | AARCH64_FEATURE_RCPC
10039 | AARCH64_FEATURE_DOTPROD
10040 | AARCH64_FEATURE_SSBS
10041 | AARCH64_FEATURE_PROFILE
),
10043 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10044 AARCH64_FEATURE_BFLOAT16
10045 | AARCH64_FEATURE_I8MM
10046 | AARCH64_FEATURE_MEMTAG
10047 | AARCH64_FEATURE_SVE2_BITPERM
),
10049 {"generic", AARCH64_ARCH_V8
, NULL
},
10051 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10054 struct aarch64_arch_option_table
10057 const aarch64_feature_set value
;
10060 /* This list should, at a minimum, contain all the architecture names
10061 recognized by GCC. */
10062 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10063 {"all", AARCH64_ANY
},
10064 {"armv8-a", AARCH64_ARCH_V8
},
10065 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10066 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10067 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10068 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10069 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10070 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10071 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10072 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10073 {"armv8-r", AARCH64_ARCH_V8_R
},
10074 {"armv9-a", AARCH64_ARCH_V9
},
10075 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10076 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10077 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10078 {NULL
, AARCH64_ARCH_NONE
}
10081 /* ISA extensions. */
10082 struct aarch64_option_cpu_value_table
10085 const aarch64_feature_set value
;
10086 const aarch64_feature_set require
; /* Feature dependencies. */
10089 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10090 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10091 AARCH64_ARCH_NONE
},
10092 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10093 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10094 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10095 AARCH64_ARCH_NONE
},
10096 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10097 AARCH64_ARCH_NONE
},
10098 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10099 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10100 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10101 AARCH64_ARCH_NONE
},
10102 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10103 AARCH64_ARCH_NONE
},
10104 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10105 AARCH64_ARCH_NONE
},
10106 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10107 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10108 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10109 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10110 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10111 AARCH64_FEATURE (AARCH64_FEATURE_FP
10112 | AARCH64_FEATURE_F16
, 0)},
10113 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10114 AARCH64_ARCH_NONE
},
10115 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10116 AARCH64_FEATURE (AARCH64_FEATURE_F16
10117 | AARCH64_FEATURE_SIMD
10118 | AARCH64_FEATURE_COMPNUM
, 0)},
10119 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10120 AARCH64_ARCH_NONE
},
10121 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10122 AARCH64_FEATURE (AARCH64_FEATURE_F16
10123 | AARCH64_FEATURE_SIMD
, 0)},
10124 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10125 AARCH64_ARCH_NONE
},
10126 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10127 AARCH64_ARCH_NONE
},
10128 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10129 AARCH64_ARCH_NONE
},
10130 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10131 AARCH64_ARCH_NONE
},
10132 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10133 AARCH64_ARCH_NONE
},
10134 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10135 AARCH64_ARCH_NONE
},
10136 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10137 AARCH64_ARCH_NONE
},
10138 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10139 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10140 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10141 AARCH64_ARCH_NONE
},
10142 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10143 AARCH64_ARCH_NONE
},
10144 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10145 AARCH64_ARCH_NONE
},
10146 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10147 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10148 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10149 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10150 | AARCH64_FEATURE_SM4
, 0)},
10151 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10152 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10153 | AARCH64_FEATURE_AES
, 0)},
10154 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10155 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10156 | AARCH64_FEATURE_SHA3
, 0)},
10157 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10158 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10159 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10160 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10161 | AARCH64_FEATURE_BFLOAT16
, 0)},
10162 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
10163 AARCH64_FEATURE (AARCH64_FEATURE_SME
10164 | AARCH64_FEATURE_SVE2
10165 | AARCH64_FEATURE_BFLOAT16
, 0)},
10166 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
10167 AARCH64_FEATURE (AARCH64_FEATURE_SME
10168 | AARCH64_FEATURE_SVE2
10169 | AARCH64_FEATURE_BFLOAT16
, 0)},
10170 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10171 AARCH64_ARCH_NONE
},
10172 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10173 AARCH64_ARCH_NONE
},
10174 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10175 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10176 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10177 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10178 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10179 AARCH64_ARCH_NONE
},
10180 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10181 AARCH64_ARCH_NONE
},
10182 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10183 AARCH64_ARCH_NONE
},
10184 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10185 AARCH64_ARCH_NONE
},
10186 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10187 AARCH64_ARCH_NONE
},
10188 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10189 AARCH64_ARCH_NONE
},
10190 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10193 struct aarch64_long_option_table
10195 const char *option
; /* Substring to match. */
10196 const char *help
; /* Help information. */
10197 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10198 char *deprecated
; /* If non-null, print this message. */
10201 /* Transitive closure of features depending on set. */
10202 static aarch64_feature_set
10203 aarch64_feature_disable_set (aarch64_feature_set set
)
10205 const struct aarch64_option_cpu_value_table
*opt
;
10206 aarch64_feature_set prev
= 0;
10208 while (prev
!= set
) {
10210 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10211 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10212 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10217 /* Transitive closure of dependencies of set. */
10218 static aarch64_feature_set
10219 aarch64_feature_enable_set (aarch64_feature_set set
)
10221 const struct aarch64_option_cpu_value_table
*opt
;
10222 aarch64_feature_set prev
= 0;
10224 while (prev
!= set
) {
10226 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10227 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10228 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10234 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10237 /* We insist on extensions being added before being removed. We achieve
10238 this by using the ADDING_VALUE variable to indicate whether we are
10239 adding an extension (1) or removing it (0) and only allowing it to
10240 change in the order -1 -> 1 -> 0. */
10241 int adding_value
= -1;
10242 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10244 /* Copy the feature set, so that we can modify it. */
10245 *ext_set
= **opt_p
;
10248 while (str
!= NULL
&& *str
!= 0)
10250 const struct aarch64_option_cpu_value_table
*opt
;
10251 const char *ext
= NULL
;
10258 as_bad (_("invalid architectural extension"));
10262 ext
= strchr (++str
, '+');
10266 optlen
= ext
- str
;
10268 optlen
= strlen (str
);
10270 if (optlen
>= 2 && startswith (str
, "no"))
10272 if (adding_value
!= 0)
10277 else if (optlen
> 0)
10279 if (adding_value
== -1)
10281 else if (adding_value
!= 1)
10283 as_bad (_("must specify extensions to add before specifying "
10284 "those to remove"));
10291 as_bad (_("missing architectural extension"));
10295 gas_assert (adding_value
!= -1);
10297 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10298 if (strncmp (opt
->name
, str
, optlen
) == 0)
10300 aarch64_feature_set set
;
10302 /* Add or remove the extension. */
10305 set
= aarch64_feature_enable_set (opt
->value
);
10306 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10310 set
= aarch64_feature_disable_set (opt
->value
);
10311 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10316 if (opt
->name
== NULL
)
10318 as_bad (_("unknown architectural extension `%s'"), str
);
10329 aarch64_parse_cpu (const char *str
)
10331 const struct aarch64_cpu_option_table
*opt
;
10332 const char *ext
= strchr (str
, '+');
10336 optlen
= ext
- str
;
10338 optlen
= strlen (str
);
10342 as_bad (_("missing cpu name `%s'"), str
);
10346 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10347 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10349 mcpu_cpu_opt
= &opt
->value
;
10351 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10356 as_bad (_("unknown cpu `%s'"), str
);
10361 aarch64_parse_arch (const char *str
)
10363 const struct aarch64_arch_option_table
*opt
;
10364 const char *ext
= strchr (str
, '+');
10368 optlen
= ext
- str
;
10370 optlen
= strlen (str
);
10374 as_bad (_("missing architecture name `%s'"), str
);
10378 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10379 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10381 march_cpu_opt
= &opt
->value
;
10383 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10388 as_bad (_("unknown architecture `%s'\n"), str
);
10393 struct aarch64_option_abi_value_table
10396 enum aarch64_abi_type value
;
10399 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10401 {"ilp32", AARCH64_ABI_ILP32
},
10402 {"lp64", AARCH64_ABI_LP64
},
10404 {"llp64", AARCH64_ABI_LLP64
},
10409 aarch64_parse_abi (const char *str
)
10413 if (str
[0] == '\0')
10415 as_bad (_("missing abi name `%s'"), str
);
10419 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10420 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10422 aarch64_abi
= aarch64_abis
[i
].value
;
10426 as_bad (_("unknown abi `%s'\n"), str
);
10430 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10431 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10432 aarch64_parse_abi
, NULL
},
10433 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10434 aarch64_parse_cpu
, NULL
},
10435 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10436 aarch64_parse_arch
, NULL
},
10437 {NULL
, NULL
, 0, NULL
}
10441 md_parse_option (int c
, const char *arg
)
10443 struct aarch64_option_table
*opt
;
10444 struct aarch64_long_option_table
*lopt
;
10450 target_big_endian
= 1;
10456 target_big_endian
= 0;
10461 /* Listing option. Just ignore these, we don't support additional
10466 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10468 if (c
== opt
->option
[0]
10469 && ((arg
== NULL
&& opt
->option
[1] == 0)
10470 || streq (arg
, opt
->option
+ 1)))
10472 /* If the option is deprecated, tell the user. */
10473 if (opt
->deprecated
!= NULL
)
10474 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10475 arg
? arg
: "", _(opt
->deprecated
));
10477 if (opt
->var
!= NULL
)
10478 *opt
->var
= opt
->value
;
10484 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10486 /* These options are expected to have an argument. */
10487 if (c
== lopt
->option
[0]
10489 && startswith (arg
, lopt
->option
+ 1))
10491 /* If the option is deprecated, tell the user. */
10492 if (lopt
->deprecated
!= NULL
)
10493 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10494 _(lopt
->deprecated
));
10496 /* Call the sup-option parser. */
10497 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10508 md_show_usage (FILE * fp
)
10510 struct aarch64_option_table
*opt
;
10511 struct aarch64_long_option_table
*lopt
;
10513 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10515 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10516 if (opt
->help
!= NULL
)
10517 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10519 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10520 if (lopt
->help
!= NULL
)
10521 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10525 -EB assemble code for a big-endian cpu\n"));
10530 -EL assemble code for a little-endian cpu\n"));
10534 /* Parse a .cpu directive. */
10537 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10539 const struct aarch64_cpu_option_table
*opt
;
10545 name
= input_line_pointer
;
10546 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10547 saved_char
= *input_line_pointer
;
10548 *input_line_pointer
= 0;
10550 ext
= strchr (name
, '+');
10553 optlen
= ext
- name
;
10555 optlen
= strlen (name
);
10557 /* Skip the first "all" entry. */
10558 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10559 if (strlen (opt
->name
) == optlen
10560 && strncmp (name
, opt
->name
, optlen
) == 0)
10562 mcpu_cpu_opt
= &opt
->value
;
10564 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10567 cpu_variant
= *mcpu_cpu_opt
;
10569 *input_line_pointer
= saved_char
;
10570 demand_empty_rest_of_line ();
10573 as_bad (_("unknown cpu `%s'"), name
);
10574 *input_line_pointer
= saved_char
;
10575 ignore_rest_of_line ();
10579 /* Parse a .arch directive. */
10582 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10584 const struct aarch64_arch_option_table
*opt
;
10590 name
= input_line_pointer
;
10591 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10592 saved_char
= *input_line_pointer
;
10593 *input_line_pointer
= 0;
10595 ext
= strchr (name
, '+');
10598 optlen
= ext
- name
;
10600 optlen
= strlen (name
);
10602 /* Skip the first "all" entry. */
10603 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10604 if (strlen (opt
->name
) == optlen
10605 && strncmp (name
, opt
->name
, optlen
) == 0)
10607 mcpu_cpu_opt
= &opt
->value
;
10609 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10612 cpu_variant
= *mcpu_cpu_opt
;
10614 *input_line_pointer
= saved_char
;
10615 demand_empty_rest_of_line ();
10619 as_bad (_("unknown architecture `%s'\n"), name
);
10620 *input_line_pointer
= saved_char
;
10621 ignore_rest_of_line ();
10624 /* Parse a .arch_extension directive. */
10627 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10630 char *ext
= input_line_pointer
;
10632 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10633 saved_char
= *input_line_pointer
;
10634 *input_line_pointer
= 0;
10636 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10639 cpu_variant
= *mcpu_cpu_opt
;
10641 *input_line_pointer
= saved_char
;
10642 demand_empty_rest_of_line ();
10645 /* Copy symbol information. */
10648 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10650 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10654 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10655 This is needed so AArch64 specific st_other values can be independently
10656 specified for an IFUNC resolver (that is called by the dynamic linker)
10657 and the symbol it resolves (aliased to the resolver). In particular,
10658 if a function symbol has special st_other value set via directives,
10659 then attaching an IFUNC resolver to that symbol should not override
10660 the st_other setting. Requiring the directive on the IFUNC resolver
10661 symbol would be unexpected and problematic in C code, where the two
10662 symbols appear as two independent function declarations. */
10665 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10667 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10668 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10669 /* If size is unset, copy size from src. Because we don't track whether
10670 .size has been used, we can't differentiate .size dest, 0 from the case
10671 where dest's size is unset. */
10672 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10676 destelf
->size
= XNEW (expressionS
);
10677 *destelf
->size
= *srcelf
->size
;
10679 S_SET_SIZE (dest
, S_GET_SIZE (src
));