1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
165 data fields contain the following information:
168 A mask of register types that would have been acceptable as bare
169 operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
170 is set if a general parsing error occured for an operand (that is,
171 an error not related to registers, and having no error string).
174 A mask of register types that would have been acceptable inside
175 a register list. In addition, SEF_IN_REGLIST is set if the
176 operand contained a '{' and if we got to the point of trying
177 to parse a register inside a list.
180 The mask associated with the register that was actually seen, or 0
181 if none. A nonzero value describes a register inside a register
182 list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
185 The idea is that stringless errors from multiple opcode templates can
186 be ORed together to give a summary of the available alternatives. */
187 #define SEF_DEFAULT_ERROR (1U << 31)
188 #define SEF_IN_REGLIST (1U << 31)
190 /* Diagnostics inline function utilities.
192 These are lightweight utilities which should only be called by parse_operands
193 and other parsers. GAS processes each assembly line by parsing it against
194 instruction template(s), in the case of multiple templates (for the same
195 mnemonic name), those templates are tried one by one until one succeeds or
196 all fail. An assembly line may fail a few templates before being
197 successfully parsed; an error saved here in most cases is not a user error
198 but an error indicating the current template is not the right template.
199 Therefore it is very important that errors can be saved at a low cost during
200 the parsing; we don't want to slow down the whole parsing by recording
201 non-user errors in detail.
203 Remember that the objective is to help GAS pick up the most appropriate
204 error message in the case of multiple templates, e.g. FMOV which has 8
210 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
211 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
217 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
224 inst
.parsing_error
.index
= -1;
225 inst
.parsing_error
.kind
= kind
;
226 inst
.parsing_error
.error
= error
;
230 set_recoverable_error (const char *error
)
232 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
235 /* Use the DESC field of the corresponding aarch64_operand entry to compose
236 the error message. */
238 set_default_error (void)
240 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
241 inst
.parsing_error
.data
[0].i
= SEF_DEFAULT_ERROR
;
245 set_expected_error (unsigned int flags
)
247 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
248 inst
.parsing_error
.data
[0].i
= flags
;
252 set_syntax_error (const char *error
)
254 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
258 set_first_syntax_error (const char *error
)
261 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
265 set_fatal_syntax_error (const char *error
)
267 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
270 /* Return value for certain parsers when the parsing fails; those parsers
271 return the information of the parsed result, e.g. register number, on
273 #define PARSE_FAIL -1
275 /* This is an invalid condition code that means no conditional field is
277 #define COND_ALWAYS 0x10
281 const char *template;
288 bfd_reloc_code_real_type reloc
;
291 /* Macros to define the register types and masks for the purpose
294 #undef AARCH64_REG_TYPES
295 #define AARCH64_REG_TYPES \
296 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
297 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
298 BASIC_REG_TYPE(SP_32) /* wsp */ \
299 BASIC_REG_TYPE(SP_64) /* sp */ \
300 BASIC_REG_TYPE(ZR_32) /* wzr */ \
301 BASIC_REG_TYPE(ZR_64) /* xzr */ \
302 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
303 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
304 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
305 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
306 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
307 BASIC_REG_TYPE(V) /* v[0-31] */ \
308 BASIC_REG_TYPE(Z) /* z[0-31] */ \
309 BASIC_REG_TYPE(P) /* p[0-15] */ \
310 BASIC_REG_TYPE(PN) /* pn[0-15] */ \
311 BASIC_REG_TYPE(ZA) /* za */ \
312 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
313 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
314 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
315 BASIC_REG_TYPE(ZT0) /* zt0 */ \
316 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
317 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
318 /* Typecheck: same, plus SVE registers. */ \
319 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
321 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
322 MULTI_REG_TYPE(R_ZR, REG_TYPE(R_32) | REG_TYPE(R_64) \
323 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
324 /* Typecheck: same, plus SVE registers. */ \
325 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) \
328 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
329 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
330 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
331 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
332 MULTI_REG_TYPE(R_ZR_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
333 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
334 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
335 /* Typecheck: any [BHSDQ]P FP. */ \
336 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
337 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
338 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
339 MULTI_REG_TYPE(R_ZR_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
340 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
341 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
342 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
343 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
344 be used for SVE instructions, since Zn and Pn are valid symbols \
345 in other contexts. */ \
346 MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
347 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
348 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
349 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
350 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
351 | REG_TYPE(Z) | REG_TYPE(P)) \
352 /* Any integer register; used for error messages only. */ \
353 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
354 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
355 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
356 /* Any vector register. */ \
357 MULTI_REG_TYPE(VZ, REG_TYPE(V) | REG_TYPE(Z)) \
358 /* An SVE vector or predicate register. */ \
359 MULTI_REG_TYPE(ZP, REG_TYPE(Z) | REG_TYPE(P)) \
360 /* Any vector or predicate register. */ \
361 MULTI_REG_TYPE(VZP, REG_TYPE(V) | REG_TYPE(Z) | REG_TYPE(P)) \
362 /* The whole of ZA or a single tile. */ \
363 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
364 /* A horizontal or vertical slice of a ZA tile. */ \
365 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
366 /* Pseudo type to mark the end of the enumerator sequence. */ \
369 #undef BASIC_REG_TYPE
370 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
371 #undef MULTI_REG_TYPE
372 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
374 #define END_REG_TYPE(T) BASIC_REG_TYPE(T)
376 /* Register type enumerators. */
377 typedef enum aarch64_reg_type_
379 /* A list of REG_TYPE_*. */
383 #undef BASIC_REG_TYPE
384 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
386 #define REG_TYPE(T) (1 << REG_TYPE_##T)
387 #undef MULTI_REG_TYPE
388 #define MULTI_REG_TYPE(T,V) V,
390 #define END_REG_TYPE(T) 0
392 /* Structure for a hash table entry for a register. */
396 unsigned char number
;
397 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
398 unsigned char builtin
;
401 /* Values indexed by aarch64_reg_type to assist the type checking. */
402 static const unsigned reg_type_masks
[] =
407 #undef BASIC_REG_TYPE
409 #undef MULTI_REG_TYPE
411 #undef AARCH64_REG_TYPES
413 /* We expected one of the registers in MASK to be specified. If a register
414 of some kind was specified, SEEN is a mask that contains that register,
415 otherwise it is zero.
417 If it is possible to provide a relatively pithy message that describes
418 the error exactly, return a string that does so, reporting the error
419 against "operand %d". Return null otherwise.
421 From a QoI perspective, any REG_TYPE_* that is passed as the first
422 argument to set_expected_reg_error should generally have its own message.
423 Providing messages for combinations of such REG_TYPE_*s can be useful if
424 it is possible to summarize the combination in a relatively natural way.
425 On the other hand, it seems better to avoid long lists of unrelated
429 get_reg_expected_msg (unsigned int mask
, unsigned int seen
)
431 /* First handle messages that use SEEN. */
432 if ((mask
& reg_type_masks
[REG_TYPE_ZAT
])
433 && (seen
& reg_type_masks
[REG_TYPE_ZATHV
]))
434 return N_("expected an unsuffixed ZA tile at operand %d");
436 if ((mask
& reg_type_masks
[REG_TYPE_ZATHV
])
437 && (seen
& reg_type_masks
[REG_TYPE_ZAT
]))
438 return N_("missing horizontal or vertical suffix at operand %d");
440 if ((mask
& reg_type_masks
[REG_TYPE_ZA
])
441 && (seen
& (reg_type_masks
[REG_TYPE_ZAT
]
442 | reg_type_masks
[REG_TYPE_ZATHV
])))
443 return N_("expected 'za' rather than a ZA tile at operand %d");
445 if ((mask
& reg_type_masks
[REG_TYPE_PN
])
446 && (seen
& reg_type_masks
[REG_TYPE_P
]))
447 return N_("expected a predicate-as-counter rather than predicate-as-mask"
448 " register at operand %d");
450 if ((mask
& reg_type_masks
[REG_TYPE_P
])
451 && (seen
& reg_type_masks
[REG_TYPE_PN
]))
452 return N_("expected a predicate-as-mask rather than predicate-as-counter"
453 " register at operand %d");
455 /* Integer, zero and stack registers. */
456 if (mask
== reg_type_masks
[REG_TYPE_R_64
])
457 return N_("expected a 64-bit integer register at operand %d");
458 if (mask
== reg_type_masks
[REG_TYPE_R_ZR
])
459 return N_("expected an integer or zero register at operand %d");
460 if (mask
== reg_type_masks
[REG_TYPE_R_SP
])
461 return N_("expected an integer or stack pointer register at operand %d");
463 /* Floating-point and SIMD registers. */
464 if (mask
== reg_type_masks
[REG_TYPE_BHSDQ
])
465 return N_("expected a scalar SIMD or floating-point register"
467 if (mask
== reg_type_masks
[REG_TYPE_V
])
468 return N_("expected an Advanced SIMD vector register at operand %d");
469 if (mask
== reg_type_masks
[REG_TYPE_Z
])
470 return N_("expected an SVE vector register at operand %d");
471 if (mask
== reg_type_masks
[REG_TYPE_P
]
472 || mask
== (reg_type_masks
[REG_TYPE_P
] | reg_type_masks
[REG_TYPE_PN
]))
473 /* Use this error for "predicate-as-mask only" and "either kind of
474 predicate". We report a more specific error if P is used where
475 PN is expected, and vice versa, so the issue at this point is
476 "predicate-like" vs. "not predicate-like". */
477 return N_("expected an SVE predicate register at operand %d");
478 if (mask
== reg_type_masks
[REG_TYPE_PN
])
479 return N_("expected an SVE predicate-as-counter register at operand %d");
480 if (mask
== reg_type_masks
[REG_TYPE_VZ
])
481 return N_("expected a vector register at operand %d");
482 if (mask
== reg_type_masks
[REG_TYPE_ZP
])
483 return N_("expected an SVE vector or predicate register at operand %d");
484 if (mask
== reg_type_masks
[REG_TYPE_VZP
])
485 return N_("expected a vector or predicate register at operand %d");
487 /* SME-related registers. */
488 if (mask
== reg_type_masks
[REG_TYPE_ZA
])
489 return N_("expected a ZA array vector at operand %d");
490 if (mask
== (reg_type_masks
[REG_TYPE_ZA_ZAT
] | reg_type_masks
[REG_TYPE_ZT0
]))
491 return N_("expected ZT0 or a ZA mask at operand %d");
492 if (mask
== reg_type_masks
[REG_TYPE_ZAT
])
493 return N_("expected a ZA tile at operand %d");
494 if (mask
== reg_type_masks
[REG_TYPE_ZATHV
])
495 return N_("expected a ZA tile slice at operand %d");
497 /* Integer and vector combos. */
498 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_V
]))
499 return N_("expected an integer register or Advanced SIMD vector register"
501 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_Z
]))
502 return N_("expected an integer register or SVE vector register"
504 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZ
]))
505 return N_("expected an integer or vector register at operand %d");
506 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_P
]))
507 return N_("expected an integer or predicate register at operand %d");
508 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZP
]))
509 return N_("expected an integer, vector or predicate register"
512 /* SVE and SME combos. */
513 if (mask
== (reg_type_masks
[REG_TYPE_Z
] | reg_type_masks
[REG_TYPE_ZATHV
]))
514 return N_("expected an SVE vector register or ZA tile slice"
520 /* Record that we expected a register of type TYPE but didn't see one.
521 REG is the register that we actually saw, or null if we didn't see a
522 recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
523 contents of a register list, otherwise it is zero. */
526 set_expected_reg_error (aarch64_reg_type type
, const reg_entry
*reg
,
529 assert (flags
== 0 || flags
== SEF_IN_REGLIST
);
530 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
531 if (flags
& SEF_IN_REGLIST
)
532 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
] | flags
;
534 inst
.parsing_error
.data
[0].i
= reg_type_masks
[type
];
536 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
539 /* Record that we expected a register list containing registers of type TYPE,
540 but didn't see the opening '{'. If we saw a register instead, REG is the
541 register that we saw, otherwise it is null. */
544 set_expected_reglist_error (aarch64_reg_type type
, const reg_entry
*reg
)
546 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
547 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
];
549 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
552 /* Some well known registers that we refer to directly elsewhere. */
556 /* Instructions take 4 bytes in the object file. */
559 static htab_t aarch64_ops_hsh
;
560 static htab_t aarch64_cond_hsh
;
561 static htab_t aarch64_shift_hsh
;
562 static htab_t aarch64_sys_regs_hsh
;
563 static htab_t aarch64_pstatefield_hsh
;
564 static htab_t aarch64_sys_regs_ic_hsh
;
565 static htab_t aarch64_sys_regs_dc_hsh
;
566 static htab_t aarch64_sys_regs_at_hsh
;
567 static htab_t aarch64_sys_regs_tlbi_hsh
;
568 static htab_t aarch64_sys_regs_sr_hsh
;
569 static htab_t aarch64_reg_hsh
;
570 static htab_t aarch64_barrier_opt_hsh
;
571 static htab_t aarch64_nzcv_hsh
;
572 static htab_t aarch64_pldop_hsh
;
573 static htab_t aarch64_hint_opt_hsh
;
575 /* Stuff needed to resolve the label ambiguity
584 static symbolS
*last_label_seen
;
586 /* Literal pool structure. Held on a per-section
587 and per-sub-section basis. */
589 #define MAX_LITERAL_POOL_SIZE 1024
590 typedef struct literal_expression
593 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
594 LITTLENUM_TYPE
* bignum
;
595 } literal_expression
;
597 typedef struct literal_pool
599 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
600 unsigned int next_free_entry
;
606 struct literal_pool
*next
;
609 /* Pointer to a linked list of literal pools. */
610 static literal_pool
*list_of_pools
= NULL
;
614 /* This array holds the chars that always start a comment. If the
615 pre-processor is disabled, these aren't very useful. */
616 const char comment_chars
[] = "";
618 /* This array holds the chars that only start a comment at the beginning of
619 a line. If the line seems to have the form '# 123 filename'
620 .line and .file directives will appear in the pre-processed output. */
621 /* Note that input_file.c hand checks for '#' at the beginning of the
622 first line of the input file. This is because the compiler outputs
623 #NO_APP at the beginning of its output. */
624 /* Also note that comments like this one will always work. */
625 const char line_comment_chars
[] = "#";
627 const char line_separator_chars
[] = ";";
629 /* Chars that can be used to separate mant
630 from exp in floating point numbers. */
631 const char EXP_CHARS
[] = "eE";
633 /* Chars that mean this number is a floating point constant. */
637 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
639 /* Prefix character that indicates the start of an immediate value. */
640 #define is_immediate_prefix(C) ((C) == '#')
642 /* Separator character handling. */
644 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
647 skip_past_char (char **str
, char c
)
658 #define skip_past_comma(str) skip_past_char (str, ',')
660 /* Arithmetic expressions (possibly involving symbols). */
662 static bool in_aarch64_get_expression
= false;
664 /* Third argument to aarch64_get_expression. */
665 #define GE_NO_PREFIX false
666 #define GE_OPT_PREFIX true
668 /* Fourth argument to aarch64_get_expression. */
669 #define ALLOW_ABSENT false
670 #define REJECT_ABSENT true
672 /* Return TRUE if the string pointed by *STR is successfully parsed
673 as an valid expression; *EP will be filled with the information of
674 such an expression. Otherwise return FALSE.
676 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
677 If REJECT_ABSENT is true then trat missing expressions as an error. */
680 aarch64_get_expression (expressionS
* ep
,
682 bool allow_immediate_prefix
,
687 bool prefix_present
= false;
689 if (allow_immediate_prefix
)
691 if (is_immediate_prefix (**str
))
694 prefix_present
= true;
698 memset (ep
, 0, sizeof (expressionS
));
700 save_in
= input_line_pointer
;
701 input_line_pointer
= *str
;
702 in_aarch64_get_expression
= true;
703 seg
= expression (ep
);
704 in_aarch64_get_expression
= false;
706 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
708 /* We found a bad expression in md_operand(). */
709 *str
= input_line_pointer
;
710 input_line_pointer
= save_in
;
711 if (prefix_present
&& ! error_p ())
712 set_fatal_syntax_error (_("bad expression"));
714 set_first_syntax_error (_("bad expression"));
719 if (seg
!= absolute_section
720 && seg
!= text_section
721 && seg
!= data_section
722 && seg
!= bss_section
723 && seg
!= undefined_section
)
725 set_syntax_error (_("bad segment"));
726 *str
= input_line_pointer
;
727 input_line_pointer
= save_in
;
734 *str
= input_line_pointer
;
735 input_line_pointer
= save_in
;
739 /* Turn a string in input_line_pointer into a floating point constant
740 of type TYPE, and store the appropriate bytes in *LITP. The number
741 of LITTLENUMS emitted is stored in *SIZEP. An error message is
742 returned, or NULL on OK. */
745 md_atof (int type
, char *litP
, int *sizeP
)
747 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
750 /* We handle all bad expressions here, so that we can report the faulty
751 instruction in the error message. */
753 md_operand (expressionS
* exp
)
755 if (in_aarch64_get_expression
)
756 exp
->X_op
= O_illegal
;
759 /* Immediate values. */
761 /* Errors may be set multiple times during parsing or bit encoding
762 (particularly in the Neon bits), but usually the earliest error which is set
763 will be the most meaningful. Avoid overwriting it with later (cascading)
764 errors by calling this function. */
767 first_error (const char *error
)
770 set_syntax_error (error
);
773 /* Similar to first_error, but this function accepts formatted error
776 first_error_fmt (const char *format
, ...)
781 /* N.B. this single buffer will not cause error messages for different
782 instructions to pollute each other; this is because at the end of
783 processing of each assembly line, error message if any will be
784 collected by as_bad. */
785 static char buffer
[size
];
789 int ret ATTRIBUTE_UNUSED
;
790 va_start (args
, format
);
791 ret
= vsnprintf (buffer
, size
, format
, args
);
792 know (ret
<= size
- 1 && ret
>= 0);
794 set_syntax_error (buffer
);
798 /* Internal helper routine converting a vector_type_el structure *VECTYPE
799 to a corresponding operand qualifier. */
801 static inline aarch64_opnd_qualifier_t
802 vectype_to_qualifier (const struct vector_type_el
*vectype
)
804 /* Element size in bytes indexed by vector_el_type. */
805 const unsigned char ele_size
[5]
807 const unsigned int ele_base
[5] =
809 AARCH64_OPND_QLF_V_4B
,
810 AARCH64_OPND_QLF_V_2H
,
811 AARCH64_OPND_QLF_V_2S
,
812 AARCH64_OPND_QLF_V_1D
,
813 AARCH64_OPND_QLF_V_1Q
816 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
817 goto vectype_conversion_fail
;
819 if (vectype
->type
== NT_zero
)
820 return AARCH64_OPND_QLF_P_Z
;
821 if (vectype
->type
== NT_merge
)
822 return AARCH64_OPND_QLF_P_M
;
824 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
826 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
828 /* Special case S_4B. */
829 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
830 return AARCH64_OPND_QLF_S_4B
;
832 /* Special case S_2H. */
833 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
834 return AARCH64_OPND_QLF_S_2H
;
836 /* Vector element register. */
837 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
841 /* Vector register. */
842 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
845 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
846 goto vectype_conversion_fail
;
848 /* The conversion is by calculating the offset from the base operand
849 qualifier for the vector type. The operand qualifiers are regular
850 enough that the offset can established by shifting the vector width by
851 a vector-type dependent amount. */
853 if (vectype
->type
== NT_b
)
855 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
857 else if (vectype
->type
>= NT_d
)
862 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
863 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
864 && offset
<= AARCH64_OPND_QLF_V_1Q
);
868 vectype_conversion_fail
:
869 first_error (_("bad vector arrangement type"));
870 return AARCH64_OPND_QLF_NIL
;
873 /* Register parsing. */
875 /* Generic register parser which is called by other specialized
877 CCP points to what should be the beginning of a register name.
878 If it is indeed a valid register name, advance CCP over it and
879 return the reg_entry structure; otherwise return NULL.
880 It does not issue diagnostics. */
883 parse_reg (char **ccp
)
889 #ifdef REGISTER_PREFIX
890 if (*start
!= REGISTER_PREFIX
)
896 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
901 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
903 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
912 /* Return the operand qualifier associated with all uses of REG, or
913 AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
914 that qualifiers don't apply to REG or that qualifiers are added
917 static aarch64_opnd_qualifier_t
918 inherent_reg_qualifier (const reg_entry
*reg
)
925 return AARCH64_OPND_QLF_W
;
930 return AARCH64_OPND_QLF_X
;
937 return AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
940 return AARCH64_OPND_QLF_NIL
;
944 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
947 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
949 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
952 /* Try to parse a base or offset register. Allow SVE base and offset
953 registers if REG_TYPE includes SVE registers. Return the register
954 entry on success, setting *QUALIFIER to the register qualifier.
955 Return null otherwise.
957 Note that this function does not issue any diagnostics. */
959 static const reg_entry
*
960 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
961 aarch64_opnd_qualifier_t
*qualifier
)
964 const reg_entry
*reg
= parse_reg (&str
);
972 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_Z
)) == 0
975 switch (TOLOWER (str
[1]))
978 *qualifier
= AARCH64_OPND_QLF_S_S
;
981 *qualifier
= AARCH64_OPND_QLF_S_D
;
990 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR_SP
))
992 *qualifier
= inherent_reg_qualifier (reg
);
1001 /* Try to parse a base or offset register. Return the register entry
1002 on success, setting *QUALIFIER to the register qualifier. Return null
1005 Note that this function does not issue any diagnostics. */
1007 static const reg_entry
*
1008 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
1010 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_ZR_SP
, qualifier
);
1013 /* Parse the qualifier of a vector register or vector element of type
1014 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
1015 succeeds; otherwise return FALSE.
1017 Accept only one occurrence of:
1018 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
1021 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
1022 struct vector_type_el
*parsed_type
, char **str
)
1026 unsigned element_size
;
1027 enum vector_el_type type
;
1030 gas_assert (*ptr
== '.');
1033 if (reg_type
!= REG_TYPE_V
|| !ISDIGIT (*ptr
))
1038 width
= strtoul (ptr
, &ptr
, 10);
1039 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
1041 first_error_fmt (_("bad size %d in vector width specifier"), width
);
1046 switch (TOLOWER (*ptr
))
1065 if (reg_type
!= REG_TYPE_V
|| width
== 1)
1074 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
1076 first_error (_("missing element size"));
1079 if (width
!= 0 && width
* element_size
!= 64
1080 && width
* element_size
!= 128
1081 && !(width
== 2 && element_size
== 16)
1082 && !(width
== 4 && element_size
== 8))
1085 ("invalid element size %d and vector size combination %c"),
1091 parsed_type
->type
= type
;
1092 parsed_type
->width
= width
;
1093 parsed_type
->element_size
= element_size
;
1100 /* *STR contains an SVE zero/merge predication suffix. Parse it into
1101 *PARSED_TYPE and point *STR at the end of the suffix. */
1104 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
1109 gas_assert (*ptr
== '/');
1111 switch (TOLOWER (*ptr
))
1114 parsed_type
->type
= NT_zero
;
1117 parsed_type
->type
= NT_merge
;
1120 if (*ptr
!= '\0' && *ptr
!= ',')
1121 first_error_fmt (_("unexpected character `%c' in predication type"),
1124 first_error (_("missing predication type"));
1127 parsed_type
->width
= 0;
1132 /* Return true if CH is a valid suffix character for registers of
1136 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1150 return ch
== '.' || ch
== '/';
1157 /* Parse an index expression at *STR, storing it in *IMM on success. */
1160 parse_index_expression (char **str
, int64_t *imm
)
1164 aarch64_get_expression (&exp
, str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1165 if (exp
.X_op
!= O_constant
)
1167 first_error (_("constant expression required"));
1170 *imm
= exp
.X_add_number
;
1174 /* Parse a register of the type TYPE.
1176 Return null if the string pointed to by *CCP is not a valid register
1177 name or the parsed register is not of TYPE.
1179 Otherwise return the register, and optionally return the register
1180 shape and element index information in *TYPEINFO.
1182 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1184 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1187 FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
1188 an operand that we can be confident that it is a good match. */
1190 #define PTR_IN_REGLIST (1U << 0)
1191 #define PTR_FULL_REG (1U << 1)
1192 #define PTR_GOOD_MATCH (1U << 2)
1194 static const reg_entry
*
1195 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1196 struct vector_type_el
*typeinfo
, unsigned int flags
)
1199 bool isalpha
= ISALPHA (*str
);
1200 const reg_entry
*reg
= parse_reg (&str
);
1201 struct vector_type_el atype
;
1202 struct vector_type_el parsetype
;
1203 bool is_typed_vecreg
= false;
1204 unsigned int err_flags
= (flags
& PTR_IN_REGLIST
) ? SEF_IN_REGLIST
: 0;
1207 atype
.type
= NT_invtype
;
1209 atype
.element_size
= 0;
1216 if (!isalpha
&& (flags
& PTR_IN_REGLIST
))
1217 set_fatal_syntax_error (_("syntax error in register list"));
1218 else if (flags
& PTR_GOOD_MATCH
)
1219 set_fatal_syntax_error (NULL
);
1221 set_expected_reg_error (type
, reg
, err_flags
);
1225 if (! aarch64_check_reg_type (reg
, type
))
1227 DEBUG_TRACE ("reg type check failed");
1228 if (flags
& PTR_GOOD_MATCH
)
1229 set_fatal_syntax_error (NULL
);
1231 set_expected_reg_error (type
, reg
, err_flags
);
1236 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1240 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1242 if ((reg
->type
== REG_TYPE_ZAT
1243 || reg
->type
== REG_TYPE_ZATH
1244 || reg
->type
== REG_TYPE_ZATV
)
1245 && reg
->number
* 8 >= parsetype
.element_size
)
1247 set_syntax_error (_("ZA tile number out of range"));
1253 if (!parse_predication_for_operand (&parsetype
, &str
))
1257 /* Register if of the form Vn.[bhsdq]. */
1258 is_typed_vecreg
= true;
1260 if (type
!= REG_TYPE_V
)
1262 /* The width is always variable; we don't allow an integer width
1264 gas_assert (parsetype
.width
== 0);
1265 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1267 else if (parsetype
.width
== 0)
1268 /* Expect index. In the new scheme we cannot have
1269 Vn.[bhsdq] represent a scalar. Therefore any
1270 Vn.[bhsdq] should have an index following it.
1271 Except in reglists of course. */
1272 atype
.defined
|= NTA_HASINDEX
;
1274 atype
.defined
|= NTA_HASTYPE
;
1276 atype
.type
= parsetype
.type
;
1277 atype
.width
= parsetype
.width
;
1280 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1282 /* Reject Sn[index] syntax. */
1283 if (reg
->type
!= REG_TYPE_Z
1284 && reg
->type
!= REG_TYPE_PN
1285 && reg
->type
!= REG_TYPE_ZT0
1286 && !is_typed_vecreg
)
1288 first_error (_("this type of register can't be indexed"));
1292 if (flags
& PTR_IN_REGLIST
)
1294 first_error (_("index not allowed inside register list"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (!parse_index_expression (&str
, &atype
.index
))
1303 if (! skip_past_char (&str
, ']'))
1306 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1308 /* Indexed vector register expected. */
1309 first_error (_("indexed vector register expected"));
1313 /* A vector reg Vn should be typed or indexed. */
1314 if (type
== REG_TYPE_V
&& atype
.defined
== 0)
1316 first_error (_("invalid use of vector register"));
1329 Return the register on success; return null otherwise.
1331 If this is a NEON vector register with additional type information, fill
1332 in the struct pointed to by VECTYPE (if non-NULL).
1334 This parser does not handle register lists. */
1336 static const reg_entry
*
1337 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1338 struct vector_type_el
*vectype
)
1340 return parse_typed_reg (ccp
, type
, vectype
, 0);
1344 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1346 return (e1
.type
== e2
.type
1347 && e1
.defined
== e2
.defined
1348 && e1
.width
== e2
.width
1349 && e1
.element_size
== e2
.element_size
1350 && e1
.index
== e2
.index
);
1353 /* Return the register number mask for registers of type REG_TYPE. */
1356 reg_type_mask (aarch64_reg_type reg_type
)
1358 return reg_type
== REG_TYPE_P
? 15 : 31;
1361 /* This function parses a list of vector registers of type TYPE.
1362 On success, it returns the parsed register list information in the
1363 following encoded format:
1365 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1366 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1368 The information of the register shape and/or index is returned in
1371 It returns PARSE_FAIL if the register list is invalid.
1373 The list contains one to four registers.
1374 Each register can be one of:
1377 All <T> should be identical.
1378 All <index> should be identical.
1379 There are restrictions on <Vt> numbers which are checked later
1380 (by reg_list_valid_p). */
1383 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1384 struct vector_type_el
*vectype
)
1388 struct vector_type_el typeinfo
, typeinfo_first
;
1389 int val
, val_range
, mask
;
1393 bool expect_index
= false;
1394 unsigned int ptr_flags
= PTR_IN_REGLIST
;
1398 set_expected_reglist_error (type
, parse_reg (&str
));
1404 typeinfo_first
.defined
= 0;
1405 typeinfo_first
.type
= NT_invtype
;
1406 typeinfo_first
.width
= -1;
1407 typeinfo_first
.element_size
= 0;
1408 typeinfo_first
.index
= 0;
1413 mask
= reg_type_mask (type
);
1418 str
++; /* skip over '-' */
1421 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1425 set_first_syntax_error (_("invalid vector register in list"));
1430 /* reject [bhsd]n */
1431 if (type
== REG_TYPE_V
&& typeinfo
.defined
== 0)
1433 set_first_syntax_error (_("invalid scalar register in list"));
1438 if (typeinfo
.defined
& NTA_HASINDEX
)
1439 expect_index
= true;
1443 if (val
== val_range
)
1445 set_first_syntax_error
1446 (_("invalid range in vector register list"));
1449 val_range
= (val_range
+ 1) & mask
;
1455 typeinfo_first
= typeinfo
;
1456 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1458 set_first_syntax_error
1459 (_("type mismatch in vector register list"));
1466 ret_val
|= val_range
<< (5 * nb_regs
);
1468 if (val_range
== val
)
1470 val_range
= (val_range
+ 1) & mask
;
1473 ptr_flags
|= PTR_GOOD_MATCH
;
1475 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1477 skip_whitespace (str
);
1480 set_first_syntax_error (_("end of vector register list not found"));
1485 skip_whitespace (str
);
1489 if (skip_past_char (&str
, '['))
1491 if (!parse_index_expression (&str
, &typeinfo_first
.index
))
1493 if (! skip_past_char (&str
, ']'))
1498 set_first_syntax_error (_("expected index"));
1505 set_first_syntax_error (_("too many registers in vector register list"));
1508 else if (nb_regs
== 0)
1510 set_first_syntax_error (_("empty vector register list"));
1516 *vectype
= typeinfo_first
;
1518 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1521 /* Directives: register aliases. */
1524 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1529 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1532 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1535 /* Only warn about a redefinition if it's not defined as the
1537 else if (new->number
!= number
|| new->type
!= type
)
1538 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1543 name
= xstrdup (str
);
1544 new = XNEW (reg_entry
);
1547 new->number
= number
;
1549 new->builtin
= false;
1551 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1556 /* Look for the .req directive. This is of the form:
1558 new_register_name .req existing_register_name
1560 If we find one, or if it looks sufficiently like one that we want to
1561 handle any error here, return TRUE. Otherwise return FALSE. */
1564 create_register_alias (char *newname
, char *p
)
1566 const reg_entry
*old
;
1567 char *oldname
, *nbuf
;
1570 /* The input scrubber ensures that whitespace after the mnemonic is
1571 collapsed to single spaces. */
1573 if (!startswith (oldname
, " .req "))
1577 if (*oldname
== '\0')
1580 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1583 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1587 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1588 the desired alias name, and p points to its end. If not, then
1589 the desired alias name is in the global original_case_string. */
1590 #ifdef TC_CASE_SENSITIVE
1593 newname
= original_case_string
;
1594 nlen
= strlen (newname
);
1597 nbuf
= xmemdup0 (newname
, nlen
);
1599 /* Create aliases under the new name as stated; an all-lowercase
1600 version of the new name; and an all-uppercase version of the new
1602 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1604 for (p
= nbuf
; *p
; p
++)
1607 if (strncmp (nbuf
, newname
, nlen
))
1609 /* If this attempt to create an additional alias fails, do not bother
1610 trying to create the all-lower case alias. We will fail and issue
1611 a second, duplicate error message. This situation arises when the
1612 programmer does something like:
1615 The second .req creates the "Foo" alias but then fails to create
1616 the artificial FOO alias because it has already been created by the
1618 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1625 for (p
= nbuf
; *p
; p
++)
1628 if (strncmp (nbuf
, newname
, nlen
))
1629 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1636 /* Should never be called, as .req goes between the alias and the
1637 register name, not at the beginning of the line. */
1639 s_req (int a ATTRIBUTE_UNUSED
)
1641 as_bad (_("invalid syntax for .req directive"));
1644 /* The .unreq directive deletes an alias which was previously defined
1645 by .req. For example:
1651 s_unreq (int a ATTRIBUTE_UNUSED
)
1656 name
= input_line_pointer
;
1657 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1658 saved_char
= *input_line_pointer
;
1659 *input_line_pointer
= 0;
1662 as_bad (_("invalid syntax for .unreq directive"));
1665 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1668 as_bad (_("unknown register alias '%s'"), name
);
1669 else if (reg
->builtin
)
1670 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1677 str_hash_delete (aarch64_reg_hsh
, name
);
1678 free ((char *) reg
->name
);
1681 /* Also locate the all upper case and all lower case versions.
1682 Do not complain if we cannot find one or the other as it
1683 was probably deleted above. */
1685 nbuf
= strdup (name
);
1686 for (p
= nbuf
; *p
; p
++)
1688 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1691 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1692 free ((char *) reg
->name
);
1696 for (p
= nbuf
; *p
; p
++)
1698 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1701 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1702 free ((char *) reg
->name
);
1710 *input_line_pointer
= saved_char
;
1711 demand_empty_rest_of_line ();
1714 /* Directives: Instruction set selection. */
1716 #if defined OBJ_ELF || defined OBJ_COFF
1717 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1718 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1719 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1720 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1722 /* Create a new mapping symbol for the transition to STATE. */
1725 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1728 const char *symname
;
1735 type
= BSF_NO_FLAGS
;
1739 type
= BSF_NO_FLAGS
;
1745 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1746 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1748 /* Save the mapping symbols for future reference. Also check that
1749 we do not place two mapping symbols at the same offset within a
1750 frag. We'll handle overlap between frags in
1751 check_mapping_symbols.
1753 If .fill or other data filling directive generates zero sized data,
1754 the mapping symbol for the following code will have the same value
1755 as the one generated for the data filling directive. In this case,
1756 we replace the old symbol with the new one at the same address. */
1759 if (frag
->tc_frag_data
.first_map
!= NULL
)
1761 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1762 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1765 frag
->tc_frag_data
.first_map
= symbolP
;
1767 if (frag
->tc_frag_data
.last_map
!= NULL
)
1769 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1770 S_GET_VALUE (symbolP
));
1771 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1772 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1775 frag
->tc_frag_data
.last_map
= symbolP
;
1778 /* We must sometimes convert a region marked as code to data during
1779 code alignment, if an odd number of bytes have to be padded. The
1780 code mapping symbol is pushed to an aligned address. */
1783 insert_data_mapping_symbol (enum mstate state
,
1784 valueT value
, fragS
* frag
, offsetT bytes
)
1786 /* If there was already a mapping symbol, remove it. */
1787 if (frag
->tc_frag_data
.last_map
!= NULL
1788 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1789 frag
->fr_address
+ value
)
1791 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1795 know (frag
->tc_frag_data
.first_map
== symp
);
1796 frag
->tc_frag_data
.first_map
= NULL
;
1798 frag
->tc_frag_data
.last_map
= NULL
;
1799 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1802 make_mapping_symbol (MAP_DATA
, value
, frag
);
1803 make_mapping_symbol (state
, value
+ bytes
, frag
);
1806 static void mapping_state_2 (enum mstate state
, int max_chars
);
1808 /* Set the mapping state to STATE. Only call this when about to
1809 emit some STATE bytes to the file. */
1812 mapping_state (enum mstate state
)
1814 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1816 if (state
== MAP_INSN
)
1817 /* AArch64 instructions require 4-byte alignment. When emitting
1818 instructions into any section, record the appropriate section
1820 record_alignment (now_seg
, 2);
1822 if (mapstate
== state
)
1823 /* The mapping symbol has already been emitted.
1824 There is nothing else to do. */
1827 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1828 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1829 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1830 evaluated later in the next else. */
1832 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1834 /* Only add the symbol if the offset is > 0:
1835 if we're at the first frag, check it's size > 0;
1836 if we're not at the first frag, then for sure
1837 the offset is > 0. */
1838 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1839 const int add_symbol
= (frag_now
!= frag_first
)
1840 || (frag_now_fix () > 0);
1843 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1847 mapping_state_2 (state
, 0);
1850 /* Same as mapping_state, but MAX_CHARS bytes have already been
1851 allocated. Put the mapping symbol that far back. */
1854 mapping_state_2 (enum mstate state
, int max_chars
)
1856 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1858 if (!SEG_NORMAL (now_seg
))
1861 if (mapstate
== state
)
1862 /* The mapping symbol has already been emitted.
1863 There is nothing else to do. */
1866 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1867 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1870 #define mapping_state(x) /* nothing */
1871 #define mapping_state_2(x, y) /* nothing */
1874 /* Directives: sectioning and alignment. */
1877 s_bss (int ignore ATTRIBUTE_UNUSED
)
1879 /* We don't support putting frags in the BSS segment, we fake it by
1880 marking in_bss, then looking at s_skip for clues. */
1881 subseg_set (bss_section
, 0);
1882 demand_empty_rest_of_line ();
1883 mapping_state (MAP_DATA
);
1887 s_even (int ignore ATTRIBUTE_UNUSED
)
1889 /* Never make frag if expect extra pass. */
1891 frag_align (1, 0, 0);
1893 record_alignment (now_seg
, 1);
1895 demand_empty_rest_of_line ();
1898 /* Directives: Literal pools. */
1900 static literal_pool
*
1901 find_literal_pool (int size
)
1905 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1907 if (pool
->section
== now_seg
1908 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1915 static literal_pool
*
1916 find_or_make_literal_pool (int size
)
1918 /* Next literal pool ID number. */
1919 static unsigned int latest_pool_num
= 1;
1922 pool
= find_literal_pool (size
);
1926 /* Create a new pool. */
1927 pool
= XNEW (literal_pool
);
1931 /* Currently we always put the literal pool in the current text
1932 section. If we were generating "small" model code where we
1933 knew that all code and initialised data was within 1MB then
1934 we could output literals to mergeable, read-only data
1937 pool
->next_free_entry
= 0;
1938 pool
->section
= now_seg
;
1939 pool
->sub_section
= now_subseg
;
1941 pool
->next
= list_of_pools
;
1942 pool
->symbol
= NULL
;
1944 /* Add it to the list. */
1945 list_of_pools
= pool
;
1948 /* New pools, and emptied pools, will have a NULL symbol. */
1949 if (pool
->symbol
== NULL
)
1951 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1952 &zero_address_frag
, 0);
1953 pool
->id
= latest_pool_num
++;
1960 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1961 Return TRUE on success, otherwise return FALSE. */
1963 add_to_lit_pool (expressionS
*exp
, int size
)
1968 pool
= find_or_make_literal_pool (size
);
1970 /* Check if this literal value is already in the pool. */
1971 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1973 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1975 if ((litexp
->X_op
== exp
->X_op
)
1976 && (exp
->X_op
== O_constant
)
1977 && (litexp
->X_add_number
== exp
->X_add_number
)
1978 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1981 if ((litexp
->X_op
== exp
->X_op
)
1982 && (exp
->X_op
== O_symbol
)
1983 && (litexp
->X_add_number
== exp
->X_add_number
)
1984 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1985 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1989 /* Do we need to create a new entry? */
1990 if (entry
== pool
->next_free_entry
)
1992 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1994 set_syntax_error (_("literal pool overflow"));
1998 pool
->literals
[entry
].exp
= *exp
;
1999 pool
->next_free_entry
+= 1;
2000 if (exp
->X_op
== O_big
)
2002 /* PR 16688: Bignums are held in a single global array. We must
2003 copy and preserve that value now, before it is overwritten. */
2004 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
2006 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
2007 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2010 pool
->literals
[entry
].bignum
= NULL
;
2013 exp
->X_op
= O_symbol
;
2014 exp
->X_add_number
= ((int) entry
) * size
;
2015 exp
->X_add_symbol
= pool
->symbol
;
2020 /* Can't use symbol_new here, so have to create a symbol and then at
2021 a later date assign it a value. That's what these functions do. */
2024 symbol_locate (symbolS
* symbolP
,
2025 const char *name
,/* It is copied, the caller can modify. */
2026 segT segment
, /* Segment identifier (SEG_<something>). */
2027 valueT valu
, /* Symbol value. */
2028 fragS
* frag
) /* Associated fragment. */
2031 char *preserved_copy_of_name
;
2033 name_length
= strlen (name
) + 1; /* +1 for \0. */
2034 obstack_grow (¬es
, name
, name_length
);
2035 preserved_copy_of_name
= obstack_finish (¬es
);
2037 #ifdef tc_canonicalize_symbol_name
2038 preserved_copy_of_name
=
2039 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2042 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2044 S_SET_SEGMENT (symbolP
, segment
);
2045 S_SET_VALUE (symbolP
, valu
);
2046 symbol_clear_list_pointers (symbolP
);
2048 symbol_set_frag (symbolP
, frag
);
2050 /* Link to end of symbol chain. */
2052 extern int symbol_table_frozen
;
2054 if (symbol_table_frozen
)
2058 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
2060 obj_symbol_new_hook (symbolP
);
2062 #ifdef tc_symbol_new_hook
2063 tc_symbol_new_hook (symbolP
);
2067 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2068 #endif /* DEBUG_SYMS */
2073 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2080 for (align
= 2; align
<= 4; align
++)
2082 int size
= 1 << align
;
2084 pool
= find_literal_pool (size
);
2085 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
2088 /* Align pool as you have word accesses.
2089 Only make a frag if we have to. */
2091 frag_align (align
, 0, 0);
2093 mapping_state (MAP_DATA
);
2095 record_alignment (now_seg
, align
);
2097 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2099 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2100 (valueT
) frag_now_fix (), frag_now
);
2101 symbol_table_insert (pool
->symbol
);
2103 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2105 expressionS
* exp
= & pool
->literals
[entry
].exp
;
2107 if (exp
->X_op
== O_big
)
2109 /* PR 16688: Restore the global bignum value. */
2110 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
2111 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
2112 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2115 /* First output the expression in the instruction to the pool. */
2116 emit_expr (exp
, size
); /* .word|.xword */
2118 if (exp
->X_op
== O_big
)
2120 free (pool
->literals
[entry
].bignum
);
2121 pool
->literals
[entry
].bignum
= NULL
;
2125 /* Mark the pool as empty. */
2126 pool
->next_free_entry
= 0;
2127 pool
->symbol
= NULL
;
2131 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2132 /* Forward declarations for functions below, in the MD interface
2134 static struct reloc_table_entry
* find_reloc_table_entry (char **);
2136 /* Directives: Data. */
2137 /* N.B. the support for relocation suffix in this directive needs to be
2138 implemented properly. */
2141 s_aarch64_cons (int nbytes
)
2145 #ifdef md_flush_pending_output
2146 md_flush_pending_output ();
2149 if (is_it_end_of_statement ())
2151 demand_empty_rest_of_line ();
2155 #ifdef md_cons_align
2156 md_cons_align (nbytes
);
2159 mapping_state (MAP_DATA
);
2162 struct reloc_table_entry
*reloc
;
2166 if (exp
.X_op
!= O_symbol
)
2167 emit_expr (&exp
, (unsigned int) nbytes
);
2170 skip_past_char (&input_line_pointer
, '#');
2171 if (skip_past_char (&input_line_pointer
, ':'))
2173 reloc
= find_reloc_table_entry (&input_line_pointer
);
2175 as_bad (_("unrecognized relocation suffix"));
2177 as_bad (_("unimplemented relocation suffix"));
2178 ignore_rest_of_line ();
2182 emit_expr (&exp
, (unsigned int) nbytes
);
2185 while (*input_line_pointer
++ == ',');
2187 /* Put terminator back into stream. */
2188 input_line_pointer
--;
2189 demand_empty_rest_of_line ();
2194 /* Forward declarations for functions below, in the MD interface
2196 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2198 /* Mark symbol that it follows a variant PCS convention. */
2201 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2207 elf_symbol_type
*elfsym
;
2209 c
= get_symbol_name (&name
);
2211 as_bad (_("Missing symbol name in directive"));
2212 sym
= symbol_find_or_make (name
);
2213 restore_line_pointer (c
);
2214 demand_empty_rest_of_line ();
2215 bfdsym
= symbol_get_bfdsym (sym
);
2216 elfsym
= elf_symbol_from (bfdsym
);
2217 gas_assert (elfsym
);
2218 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2220 #endif /* OBJ_ELF */
2222 /* Output a 32-bit word, but mark as an instruction. */
2225 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2230 #ifdef md_flush_pending_output
2231 md_flush_pending_output ();
2234 if (is_it_end_of_statement ())
2236 demand_empty_rest_of_line ();
2240 /* Sections are assumed to start aligned. In executable section, there is no
2241 MAP_DATA symbol pending. So we only align the address during
2242 MAP_DATA --> MAP_INSN transition.
2243 For other sections, this is not guaranteed. */
2244 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2245 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2246 frag_align_code (2, 0);
2249 mapping_state (MAP_INSN
);
2255 if (exp
.X_op
!= O_constant
)
2257 as_bad (_("constant expression required"));
2258 ignore_rest_of_line ();
2262 if (target_big_endian
)
2264 unsigned int val
= exp
.X_add_number
;
2265 exp
.X_add_number
= SWAP_32 (val
);
2267 emit_expr (&exp
, INSN_SIZE
);
2270 while (*input_line_pointer
++ == ',');
2272 dwarf2_emit_insn (n
* INSN_SIZE
);
2274 /* Put terminator back into stream. */
2275 input_line_pointer
--;
2276 demand_empty_rest_of_line ();
2280 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2282 demand_empty_rest_of_line ();
2283 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2284 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2288 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2291 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2297 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2298 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2300 demand_empty_rest_of_line ();
2303 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2306 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2310 /* Since we're just labelling the code, there's no need to define a
2313 /* Make sure there is enough room in this frag for the following
2314 blr. This trick only works if the blr follows immediately after
2315 the .tlsdesc directive. */
2317 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2318 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2320 demand_empty_rest_of_line ();
2323 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2326 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2332 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2333 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2335 demand_empty_rest_of_line ();
2337 #endif /* OBJ_ELF */
2341 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2348 if (exp
.X_op
== O_symbol
)
2349 exp
.X_op
= O_secrel
;
2351 emit_expr (&exp
, 4);
2353 while (*input_line_pointer
++ == ',');
2355 input_line_pointer
--;
2356 demand_empty_rest_of_line ();
2360 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2364 exp
.X_op
= O_secrel
;
2365 exp
.X_add_symbol
= symbol
;
2366 exp
.X_add_number
= 0;
2367 emit_expr (&exp
, size
);
2371 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2378 if (exp
.X_op
== O_symbol
)
2379 exp
.X_op
= O_secidx
;
2381 emit_expr (&exp
, 2);
2383 while (*input_line_pointer
++ == ',');
2385 input_line_pointer
--;
2386 demand_empty_rest_of_line ();
2390 static void s_aarch64_arch (int);
2391 static void s_aarch64_cpu (int);
2392 static void s_aarch64_arch_extension (int);
2394 /* This table describes all the machine specific pseudo-ops the assembler
2395 has to support. The fields are:
2396 pseudo-op name without dot
2397 function to call to execute this pseudo-op
2398 Integer arg to pass to the function. */
2400 const pseudo_typeS md_pseudo_table
[] = {
2401 /* Never called because '.req' does not start a line. */
2403 {"unreq", s_unreq
, 0},
2405 {"even", s_even
, 0},
2406 {"ltorg", s_ltorg
, 0},
2407 {"pool", s_ltorg
, 0},
2408 {"cpu", s_aarch64_cpu
, 0},
2409 {"arch", s_aarch64_arch
, 0},
2410 {"arch_extension", s_aarch64_arch_extension
, 0},
2411 {"inst", s_aarch64_inst
, 0},
2412 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2414 {"tlsdescadd", s_tlsdescadd
, 0},
2415 {"tlsdesccall", s_tlsdesccall
, 0},
2416 {"tlsdescldr", s_tlsdescldr
, 0},
2417 {"variant_pcs", s_variant_pcs
, 0},
2419 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2420 {"word", s_aarch64_cons
, 4},
2421 {"long", s_aarch64_cons
, 4},
2422 {"xword", s_aarch64_cons
, 8},
2423 {"dword", s_aarch64_cons
, 8},
2426 {"secrel32", s_secrel
, 0},
2427 {"secidx", s_secidx
, 0},
2429 {"float16", float_cons
, 'h'},
2430 {"bfloat16", float_cons
, 'b'},
2435 /* Check whether STR points to a register name followed by a comma or the
2436 end of line; REG_TYPE indicates which register types are checked
2437 against. Return TRUE if STR is such a register name; otherwise return
2438 FALSE. The function does not intend to produce any diagnostics, but since
2439 the register parser aarch64_reg_parse, which is called by this function,
2440 does produce diagnostics, we call clear_error to clear any diagnostics
2441 that may be generated by aarch64_reg_parse.
2442 Also, the function returns FALSE directly if there is any user error
2443 present at the function entry. This prevents the existing diagnostics
2444 state from being spoiled.
2445 The function currently serves parse_constant_immediate and
2446 parse_big_immediate only. */
2448 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2450 const reg_entry
*reg
;
2452 /* Prevent the diagnostics state from being spoiled. */
2456 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2458 /* Clear the parsing error that may be set by the reg parser. */
2464 skip_whitespace (str
);
2465 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2471 /* Parser functions used exclusively in instruction operands. */
2473 /* Parse an immediate expression which may not be constant.
2475 To prevent the expression parser from pushing a register name
2476 into the symbol table as an undefined symbol, firstly a check is
2477 done to find out whether STR is a register of type REG_TYPE followed
2478 by a comma or the end of line. Return FALSE if STR is such a string. */
2481 parse_immediate_expression (char **str
, expressionS
*exp
,
2482 aarch64_reg_type reg_type
)
2484 if (reg_name_p (*str
, reg_type
))
2486 set_recoverable_error (_("immediate operand required"));
2490 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2492 if (exp
->X_op
== O_absent
)
2494 set_fatal_syntax_error (_("missing immediate expression"));
2501 /* Constant immediate-value read function for use in insn parsing.
2502 STR points to the beginning of the immediate (with the optional
2503 leading #); *VAL receives the value. REG_TYPE says which register
2504 names should be treated as registers rather than as symbolic immediates.
2506 Return TRUE on success; otherwise return FALSE. */
2509 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2513 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2516 if (exp
.X_op
!= O_constant
)
2518 set_syntax_error (_("constant expression required"));
2522 *val
= exp
.X_add_number
;
2527 encode_imm_float_bits (uint32_t imm
)
2529 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2530 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2533 /* Return TRUE if the single-precision floating-point value encoded in IMM
2534 can be expressed in the AArch64 8-bit signed floating-point format with
2535 3-bit exponent and normalized 4 bits of precision; in other words, the
2536 floating-point value must be expressable as
2537 (+/-) n / 16 * power (2, r)
2538 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2541 aarch64_imm_float_p (uint32_t imm
)
2543 /* If a single-precision floating-point value has the following bit
2544 pattern, it can be expressed in the AArch64 8-bit floating-point
2547 3 32222222 2221111111111
2548 1 09876543 21098765432109876543210
2549 n Eeeeeexx xxxx0000000000000000000
2551 where n, e and each x are either 0 or 1 independently, with
2556 /* Prepare the pattern for 'Eeeeee'. */
2557 if (((imm
>> 30) & 0x1) == 0)
2558 pattern
= 0x3e000000;
2560 pattern
= 0x40000000;
2562 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2563 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2566 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2567 as an IEEE float without any loss of precision. Store the value in
2571 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2573 /* If a double-precision floating-point value has the following bit
2574 pattern, it can be expressed in a float:
2576 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2577 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2578 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2580 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2581 if Eeee_eeee != 1111_1111
2583 where n, e, s and S are either 0 or 1 independently and where ~ is the
2587 uint32_t high32
= imm
>> 32;
2588 uint32_t low32
= imm
;
2590 /* Lower 29 bits need to be 0s. */
2591 if ((imm
& 0x1fffffff) != 0)
2594 /* Prepare the pattern for 'Eeeeeeeee'. */
2595 if (((high32
>> 30) & 0x1) == 0)
2596 pattern
= 0x38000000;
2598 pattern
= 0x40000000;
2601 if ((high32
& 0x78000000) != pattern
)
2604 /* Check Eeee_eeee != 1111_1111. */
2605 if ((high32
& 0x7ff00000) == 0x47f00000)
2608 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2609 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2610 | (low32
>> 29)); /* 3 S bits. */
2614 /* Return true if we should treat OPERAND as a double-precision
2615 floating-point operand rather than a single-precision one. */
2617 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2619 /* Check for unsuffixed SVE registers, which are allowed
2620 for LDR and STR but not in instructions that require an
2621 immediate. We get better error messages if we arbitrarily
2622 pick one size, parse the immediate normally, and then
2623 report the match failure in the normal way. */
2624 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2625 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2628 /* Parse a floating-point immediate. Return TRUE on success and return the
2629 value in *IMMED in the format of IEEE754 single-precision encoding.
2630 *CCP points to the start of the string; DP_P is TRUE when the immediate
2631 is expected to be in double-precision (N.B. this only matters when
2632 hexadecimal representation is involved). REG_TYPE says which register
2633 names should be treated as registers rather than as symbolic immediates.
2635 This routine accepts any IEEE float; it is up to the callers to reject
2639 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2640 aarch64_reg_type reg_type
)
2644 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2646 unsigned fpword
= 0;
2649 skip_past_char (&str
, '#');
2652 skip_whitespace (fpnum
);
2654 if (startswith (fpnum
, "0x"))
2656 /* Support the hexadecimal representation of the IEEE754 encoding.
2657 Double-precision is expected when DP_P is TRUE, otherwise the
2658 representation should be in single-precision. */
2659 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2664 if (!can_convert_double_to_float (val
, &fpword
))
2667 else if ((uint64_t) val
> 0xffffffff)
2674 else if (reg_name_p (str
, reg_type
))
2676 set_recoverable_error (_("immediate operand required"));
2684 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2687 /* Our FP word must be 32 bits (single-precision FP). */
2688 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2690 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2700 set_fatal_syntax_error (_("invalid floating-point constant"));
2704 /* Less-generic immediate-value read function with the possibility of loading
2705 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2708 To prevent the expression parser from pushing a register name into the
2709 symbol table as an undefined symbol, a check is firstly done to find
2710 out whether STR is a register of type REG_TYPE followed by a comma or
2711 the end of line. Return FALSE if STR is such a register. */
2714 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2718 if (reg_name_p (ptr
, reg_type
))
2720 set_syntax_error (_("immediate operand required"));
2724 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2726 if (inst
.reloc
.exp
.X_op
== O_constant
)
2727 *imm
= inst
.reloc
.exp
.X_add_number
;
2734 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2735 if NEED_LIBOPCODES is non-zero, the fixup will need
2736 assistance from the libopcodes. */
2739 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2740 const aarch64_opnd_info
*operand
,
2741 int need_libopcodes_p
)
2743 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2744 reloc
->opnd
= operand
->type
;
2745 if (need_libopcodes_p
)
2746 reloc
->need_libopcodes_p
= 1;
2749 /* Return TRUE if the instruction needs to be fixed up later internally by
2750 the GAS; otherwise return FALSE. */
2753 aarch64_gas_internal_fixup_p (void)
2755 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2758 /* Assign the immediate value to the relevant field in *OPERAND if
2759 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2760 needs an internal fixup in a later stage.
2761 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2762 IMM.VALUE that may get assigned with the constant. */
2764 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2765 aarch64_opnd_info
*operand
,
2767 int need_libopcodes_p
,
2770 if (reloc
->exp
.X_op
== O_constant
)
2773 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2775 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2776 reloc
->type
= BFD_RELOC_UNUSED
;
2780 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2781 /* Tell libopcodes to ignore this operand or not. This is helpful
2782 when one of the operands needs to be fixed up later but we need
2783 libopcodes to check the other operands. */
2784 operand
->skip
= skip_p
;
2788 /* Relocation modifiers. Each entry in the table contains the textual
2789 name for the relocation which may be placed before a symbol used as
2790 a load/store offset, or add immediate. It must be surrounded by a
2791 leading and trailing colon, for example:
2793 ldr x0, [x1, #:rello:varsym]
2794 add x0, x1, #:rello:varsym */
2796 struct reloc_table_entry
2800 bfd_reloc_code_real_type adr_type
;
2801 bfd_reloc_code_real_type adrp_type
;
2802 bfd_reloc_code_real_type movw_type
;
2803 bfd_reloc_code_real_type add_type
;
2804 bfd_reloc_code_real_type ldst_type
;
2805 bfd_reloc_code_real_type ld_literal_type
;
2808 static struct reloc_table_entry reloc_table
[] =
2810 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2815 BFD_RELOC_AARCH64_ADD_LO12
,
2816 BFD_RELOC_AARCH64_LDST_LO12
,
2819 /* Higher 21 bits of pc-relative page offset: ADRP */
2822 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2828 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2831 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2837 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2841 BFD_RELOC_AARCH64_MOVW_G0
,
2846 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2850 BFD_RELOC_AARCH64_MOVW_G0_S
,
2855 /* Less significant bits 0-15 of address/value: MOVK, no check */
2859 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2864 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2868 BFD_RELOC_AARCH64_MOVW_G1
,
2873 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2877 BFD_RELOC_AARCH64_MOVW_G1_S
,
2882 /* Less significant bits 16-31 of address/value: MOVK, no check */
2886 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2891 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2895 BFD_RELOC_AARCH64_MOVW_G2
,
2900 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2904 BFD_RELOC_AARCH64_MOVW_G2_S
,
2909 /* Less significant bits 32-47 of address/value: MOVK, no check */
2913 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2918 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2922 BFD_RELOC_AARCH64_MOVW_G3
,
2927 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2931 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2936 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2940 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2945 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2949 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2954 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2958 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2963 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2967 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2972 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2976 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2981 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2985 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2990 /* Get to the page containing GOT entry for a symbol. */
2993 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2997 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2999 /* 12 bit offset into the page containing GOT entry for that symbol. */
3005 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
3008 /* 0-15 bits of address/value: MOVk, no check. */
3012 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
3017 /* Most significant bits 16-31 of address/value: MOVZ. */
3021 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
3026 /* 15 bit offset into the page containing GOT entry for that symbol. */
3032 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
3035 /* Get to the page containing GOT TLS entry for a symbol */
3036 {"gottprel_g0_nc", 0,
3039 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
3044 /* Get to the page containing GOT TLS entry for a symbol */
3048 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
3053 /* Get to the page containing GOT TLS entry for a symbol */
3055 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
3056 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
3062 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3067 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
3071 /* Lower 16 bits address/value: MOVk. */
3075 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
3080 /* Most significant bits 16-31 of address/value: MOVZ. */
3084 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
3089 /* Get to the page containing GOT TLS entry for a symbol */
3091 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
3092 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
3096 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
3098 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3103 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
3104 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
3107 /* Get to the page containing GOT TLS entry for a symbol.
3108 The same as GD, we allocate two consecutive GOT slots
3109 for module index and module offset, the only difference
3110 with GD is the module offset should be initialized to
3111 zero without any outstanding runtime relocation. */
3113 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
3114 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
3120 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3121 {"tlsldm_lo12_nc", 0,
3125 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
3129 /* 12 bit offset into the module TLS base address. */
3134 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
3135 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
3138 /* Same as dtprel_lo12, no overflow check. */
3139 {"dtprel_lo12_nc", 0,
3143 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
3144 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3147 /* bits[23:12] of offset to the module TLS base address. */
3152 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3156 /* bits[15:0] of offset to the module TLS base address. */
3160 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3165 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3169 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3174 /* bits[31:16] of offset to the module TLS base address. */
3178 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3183 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3187 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3192 /* bits[47:32] of offset to the module TLS base address. */
3196 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3201 /* Lower 16 bit offset into GOT entry for a symbol */
3202 {"tlsdesc_off_g0_nc", 0,
3205 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3210 /* Higher 16 bit offset into GOT entry for a symbol */
3211 {"tlsdesc_off_g1", 0,
3214 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3219 /* Get to the page containing GOT TLS entry for a symbol */
3222 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3226 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3228 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3229 {"gottprel_lo12", 0,
3234 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3237 /* Get tp offset for a symbol. */
3242 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3246 /* Get tp offset for a symbol. */
3251 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3252 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3255 /* Get tp offset for a symbol. */
3260 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3264 /* Get tp offset for a symbol. */
3265 {"tprel_lo12_nc", 0,
3269 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3270 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3273 /* Most significant bits 32-47 of address/value: MOVZ. */
3277 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3282 /* Most significant bits 16-31 of address/value: MOVZ. */
3286 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3291 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3295 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3300 /* Most significant bits 0-15 of address/value: MOVZ. */
3304 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3309 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3313 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3318 /* 15bit offset from got entry to base address of GOT table. */
3324 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3327 /* 14bit offset from got entry to base address of GOT table. */
3333 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3337 /* Given the address of a pointer pointing to the textual name of a
3338 relocation as may appear in assembler source, attempt to find its
3339 details in reloc_table. The pointer will be updated to the character
3340 after the trailing colon. On failure, NULL will be returned;
3341 otherwise return the reloc_table_entry. */
3343 static struct reloc_table_entry
*
3344 find_reloc_table_entry (char **str
)
3347 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3349 int length
= strlen (reloc_table
[i
].name
);
3351 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3352 && (*str
)[length
] == ':')
3354 *str
+= (length
+ 1);
3355 return &reloc_table
[i
];
3362 /* Returns 0 if the relocation should never be forced,
3363 1 if the relocation must be forced, and -1 if either
3367 aarch64_force_reloc (unsigned int type
)
3371 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3372 /* Perform these "immediate" internal relocations
3373 even if the symbol is extern or weak. */
3376 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3377 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3378 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3379 /* Pseudo relocs that need to be fixed up according to
3383 case BFD_RELOC_AARCH64_ADD_LO12
:
3384 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3385 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3386 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3387 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3388 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3389 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3390 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3391 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3392 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3393 case BFD_RELOC_AARCH64_LDST128_LO12
:
3394 case BFD_RELOC_AARCH64_LDST16_LO12
:
3395 case BFD_RELOC_AARCH64_LDST32_LO12
:
3396 case BFD_RELOC_AARCH64_LDST64_LO12
:
3397 case BFD_RELOC_AARCH64_LDST8_LO12
:
3398 case BFD_RELOC_AARCH64_LDST_LO12
:
3399 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3400 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3401 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3402 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3403 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3404 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3405 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3406 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3407 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3408 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3409 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3410 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3411 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3412 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3413 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3414 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3415 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3416 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3417 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3418 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3419 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3420 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3421 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3422 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3423 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3424 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3425 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3426 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3427 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3428 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3429 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3430 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3431 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3432 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3433 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3434 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3435 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3436 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3437 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3438 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3439 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3440 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3441 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3442 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3443 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3444 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3445 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3446 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3447 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3448 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3449 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3450 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3451 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3452 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3453 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3454 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3455 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3456 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3457 /* Always leave these relocations for the linker. */
3466 aarch64_force_relocation (struct fix
*fixp
)
3468 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3471 return generic_force_reloc (fixp
);
3475 /* Mode argument to parse_shift and parser_shifter_operand. */
3476 enum parse_shift_mode
3478 SHIFTED_NONE
, /* no shifter allowed */
3479 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3481 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3483 SHIFTED_LSL
, /* bare "lsl #n" */
3484 SHIFTED_MUL
, /* bare "mul #n" */
3485 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3486 SHIFTED_MUL_VL
, /* "mul vl" */
3487 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3490 /* Parse a <shift> operator on an AArch64 data processing instruction.
3491 Return TRUE on success; otherwise return FALSE. */
3493 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3495 const struct aarch64_name_value_pair
*shift_op
;
3496 enum aarch64_modifier_kind kind
;
3502 for (p
= *str
; ISALPHA (*p
); p
++)
3507 set_syntax_error (_("shift expression expected"));
3511 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3513 if (shift_op
== NULL
)
3515 set_syntax_error (_("shift operator expected"));
3519 kind
= aarch64_get_operand_modifier (shift_op
);
3521 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3523 set_syntax_error (_("invalid use of 'MSL'"));
3527 if (kind
== AARCH64_MOD_MUL
3528 && mode
!= SHIFTED_MUL
3529 && mode
!= SHIFTED_MUL_VL
)
3531 set_syntax_error (_("invalid use of 'MUL'"));
3537 case SHIFTED_LOGIC_IMM
:
3538 if (aarch64_extend_operator_p (kind
))
3540 set_syntax_error (_("extending shift is not permitted"));
3545 case SHIFTED_ARITH_IMM
:
3546 if (kind
== AARCH64_MOD_ROR
)
3548 set_syntax_error (_("'ROR' shift is not permitted"));
3554 if (kind
!= AARCH64_MOD_LSL
)
3556 set_syntax_error (_("only 'LSL' shift is permitted"));
3562 if (kind
!= AARCH64_MOD_MUL
)
3564 set_syntax_error (_("only 'MUL' is permitted"));
3569 case SHIFTED_MUL_VL
:
3570 /* "MUL VL" consists of two separate tokens. Require the first
3571 token to be "MUL" and look for a following "VL". */
3572 if (kind
== AARCH64_MOD_MUL
)
3574 skip_whitespace (p
);
3575 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3578 kind
= AARCH64_MOD_MUL_VL
;
3582 set_syntax_error (_("only 'MUL VL' is permitted"));
3585 case SHIFTED_REG_OFFSET
:
3586 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3587 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3589 set_fatal_syntax_error
3590 (_("invalid shift for the register offset addressing mode"));
3595 case SHIFTED_LSL_MSL
:
3596 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3598 set_syntax_error (_("invalid shift operator"));
3607 /* Whitespace can appear here if the next thing is a bare digit. */
3608 skip_whitespace (p
);
3610 /* Parse shift amount. */
3612 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3613 exp
.X_op
= O_absent
;
3616 if (is_immediate_prefix (*p
))
3621 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3623 if (kind
== AARCH64_MOD_MUL_VL
)
3624 /* For consistency, give MUL VL the same shift amount as an implicit
3626 operand
->shifter
.amount
= 1;
3627 else if (exp
.X_op
== O_absent
)
3629 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3631 set_syntax_error (_("missing shift amount"));
3634 operand
->shifter
.amount
= 0;
3636 else if (exp
.X_op
!= O_constant
)
3638 set_syntax_error (_("constant shift amount required"));
3641 /* For parsing purposes, MUL #n has no inherent range. The range
3642 depends on the operand and will be checked by operand-specific
3644 else if (kind
!= AARCH64_MOD_MUL
3645 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3647 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3652 operand
->shifter
.amount
= exp
.X_add_number
;
3653 operand
->shifter
.amount_present
= 1;
3656 operand
->shifter
.operator_present
= 1;
3657 operand
->shifter
.kind
= kind
;
3663 /* Parse a <shifter_operand> for a data processing instruction:
3666 #<immediate>, LSL #imm
3668 Validation of immediate operands is deferred to md_apply_fix.
3670 Return TRUE on success; otherwise return FALSE. */
3673 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3674 enum parse_shift_mode mode
)
3678 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3683 /* Accept an immediate expression. */
3684 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3688 /* Accept optional LSL for arithmetic immediate values. */
3689 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3690 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3693 /* Not accept any shifter for logical immediate values. */
3694 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3695 && parse_shift (&p
, operand
, mode
))
3697 set_syntax_error (_("unexpected shift operator"));
3705 /* Parse a <shifter_operand> for a data processing instruction:
3710 #<immediate>, LSL #imm
3712 where <shift> is handled by parse_shift above, and the last two
3713 cases are handled by the function above.
3715 Validation of immediate operands is deferred to md_apply_fix.
3717 Return TRUE on success; otherwise return FALSE. */
3720 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3721 enum parse_shift_mode mode
)
3723 const reg_entry
*reg
;
3724 aarch64_opnd_qualifier_t qualifier
;
3725 enum aarch64_operand_class opd_class
3726 = aarch64_get_operand_class (operand
->type
);
3728 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3731 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3733 set_syntax_error (_("unexpected register in the immediate operand"));
3737 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR
))
3739 set_expected_reg_error (REG_TYPE_R_ZR
, reg
, 0);
3743 operand
->reg
.regno
= reg
->number
;
3744 operand
->qualifier
= qualifier
;
3746 /* Accept optional shift operation on register. */
3747 if (! skip_past_comma (str
))
3750 if (! parse_shift (str
, operand
, mode
))
3755 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3758 (_("integer register expected in the extended/shifted operand "
3763 /* We have a shifted immediate variable. */
3764 return parse_shifter_operand_imm (str
, operand
, mode
);
3767 /* Return TRUE on success; return FALSE otherwise. */
3770 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3771 enum parse_shift_mode mode
)
3775 /* Determine if we have the sequence of characters #: or just :
3776 coming next. If we do, then we check for a :rello: relocation
3777 modifier. If we don't, punt the whole lot to
3778 parse_shifter_operand. */
3780 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3782 struct reloc_table_entry
*entry
;
3790 /* Try to parse a relocation. Anything else is an error. */
3791 if (!(entry
= find_reloc_table_entry (str
)))
3793 set_syntax_error (_("unknown relocation modifier"));
3797 if (entry
->add_type
== 0)
3800 (_("this relocation modifier is not allowed on this instruction"));
3804 /* Save str before we decompose it. */
3807 /* Next, we parse the expression. */
3808 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3812 /* Record the relocation type (use the ADD variant here). */
3813 inst
.reloc
.type
= entry
->add_type
;
3814 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3816 /* If str is empty, we've reached the end, stop here. */
3820 /* Otherwise, we have a shifted reloc modifier, so rewind to
3821 recover the variable name and continue parsing for the shifter. */
3823 return parse_shifter_operand_imm (str
, operand
, mode
);
3826 return parse_shifter_operand (str
, operand
, mode
);
3829 /* Parse all forms of an address expression. Information is written
3830 to *OPERAND and/or inst.reloc.
3832 The A64 instruction set has the following addressing modes:
3835 [base] // in SIMD ld/st structure
3836 [base{,#0}] // in ld/st exclusive
3838 [base,Xm{,LSL #imm}]
3839 [base,Xm,SXTX {#imm}]
3840 [base,Wm,(S|U)XTW {#imm}]
3842 [base]! // in ldraa/ldrab exclusive
3846 [base],Xm // in SIMD ld/st structure
3847 PC-relative (literal)
3851 [base,Zm.D{,LSL #imm}]
3852 [base,Zm.S,(S|U)XTW {#imm}]
3853 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3857 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3858 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3859 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3861 (As a convenience, the notation "=immediate" is permitted in conjunction
3862 with the pc-relative literal load instructions to automatically place an
3863 immediate value or symbolic address in a nearby literal pool and generate
3864 a hidden label which references it.)
3866 Upon a successful parsing, the address structure in *OPERAND will be
3867 filled in the following way:
3869 .base_regno = <base>
3870 .offset.is_reg // 1 if the offset is a register
3872 .offset.regno = <Rm>
3874 For different addressing modes defined in the A64 ISA:
3877 .pcrel=0; .preind=1; .postind=0; .writeback=0
3879 .pcrel=0; .preind=1; .postind=0; .writeback=1
3881 .pcrel=0; .preind=0; .postind=1; .writeback=1
3882 PC-relative (literal)
3883 .pcrel=1; .preind=1; .postind=0; .writeback=0
3885 The shift/extension information, if any, will be stored in .shifter.
3886 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3887 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3888 corresponding register.
3890 BASE_TYPE says which types of base register should be accepted and
3891 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3892 is the type of shifter that is allowed for immediate offsets,
3893 or SHIFTED_NONE if none.
3895 In all other respects, it is the caller's responsibility to check
3896 for addressing modes not supported by the instruction, and to set
3900 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3901 aarch64_opnd_qualifier_t
*base_qualifier
,
3902 aarch64_opnd_qualifier_t
*offset_qualifier
,
3903 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3904 enum parse_shift_mode imm_shift_mode
)
3907 const reg_entry
*reg
;
3908 expressionS
*exp
= &inst
.reloc
.exp
;
3910 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3911 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3912 if (! skip_past_char (&p
, '['))
3914 /* =immediate or label. */
3915 operand
->addr
.pcrel
= 1;
3916 operand
->addr
.preind
= 1;
3918 /* #:<reloc_op>:<symbol> */
3919 skip_past_char (&p
, '#');
3920 if (skip_past_char (&p
, ':'))
3922 bfd_reloc_code_real_type ty
;
3923 struct reloc_table_entry
*entry
;
3925 /* Try to parse a relocation modifier. Anything else is
3927 entry
= find_reloc_table_entry (&p
);
3930 set_syntax_error (_("unknown relocation modifier"));
3934 switch (operand
->type
)
3936 case AARCH64_OPND_ADDR_PCREL21
:
3938 ty
= entry
->adr_type
;
3942 ty
= entry
->ld_literal_type
;
3949 (_("this relocation modifier is not allowed on this "
3955 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3957 set_syntax_error (_("invalid relocation expression"));
3960 /* #:<reloc_op>:<expr> */
3961 /* Record the relocation type. */
3962 inst
.reloc
.type
= ty
;
3963 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3967 if (skip_past_char (&p
, '='))
3968 /* =immediate; need to generate the literal in the literal pool. */
3969 inst
.gen_lit_pool
= 1;
3971 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3973 set_syntax_error (_("invalid address"));
3984 bool alpha_base_p
= ISALPHA (*p
);
3985 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3986 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3989 && aarch64_check_reg_type (reg
, REG_TYPE_R_SP
)
3990 && *base_qualifier
== AARCH64_OPND_QLF_W
)
3991 set_syntax_error (_("expected a 64-bit base register"));
3992 else if (alpha_base_p
)
3993 set_syntax_error (_("invalid base register"));
3995 set_syntax_error (_("expected a base register"));
3998 operand
->addr
.base_regno
= reg
->number
;
4001 if (skip_past_comma (&p
))
4004 operand
->addr
.preind
= 1;
4006 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
4009 if (!aarch64_check_reg_type (reg
, offset_type
))
4011 set_syntax_error (_("invalid offset register"));
4016 operand
->addr
.offset
.regno
= reg
->number
;
4017 operand
->addr
.offset
.is_reg
= 1;
4018 /* Shifted index. */
4019 if (skip_past_comma (&p
))
4022 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
4023 /* Use the diagnostics set in parse_shift, so not set new
4024 error message here. */
4028 [base,Xm] # For vector plus scalar SVE2 indexing.
4029 [base,Xm{,LSL #imm}]
4030 [base,Xm,SXTX {#imm}]
4031 [base,Wm,(S|U)XTW {#imm}] */
4032 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
4033 || operand
->shifter
.kind
== AARCH64_MOD_LSL
4034 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
4036 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
4038 set_syntax_error (_("invalid use of 32-bit register offset"));
4041 if (aarch64_get_qualifier_esize (*base_qualifier
)
4042 != aarch64_get_qualifier_esize (*offset_qualifier
)
4043 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
4044 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
4045 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
4047 set_syntax_error (_("offset has different size from base"));
4051 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
4053 set_syntax_error (_("invalid use of 64-bit register offset"));
4059 /* [Xn,#:<reloc_op>:<symbol> */
4060 skip_past_char (&p
, '#');
4061 if (skip_past_char (&p
, ':'))
4063 struct reloc_table_entry
*entry
;
4065 /* Try to parse a relocation modifier. Anything else is
4067 if (!(entry
= find_reloc_table_entry (&p
)))
4069 set_syntax_error (_("unknown relocation modifier"));
4073 if (entry
->ldst_type
== 0)
4076 (_("this relocation modifier is not allowed on this "
4081 /* [Xn,#:<reloc_op>: */
4082 /* We now have the group relocation table entry corresponding to
4083 the name in the assembler source. Next, we parse the
4085 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4087 set_syntax_error (_("invalid relocation expression"));
4091 /* [Xn,#:<reloc_op>:<expr> */
4092 /* Record the load/store relocation type. */
4093 inst
.reloc
.type
= entry
->ldst_type
;
4094 inst
.reloc
.pc_rel
= entry
->pc_rel
;
4098 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4100 set_syntax_error (_("invalid expression in the address"));
4104 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
4105 /* [Xn,<expr>,<shifter> */
4106 if (! parse_shift (&p
, operand
, imm_shift_mode
))
4112 if (! skip_past_char (&p
, ']'))
4114 set_syntax_error (_("']' expected"));
4118 if (skip_past_char (&p
, '!'))
4120 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
4122 set_syntax_error (_("register offset not allowed in pre-indexed "
4123 "addressing mode"));
4127 operand
->addr
.writeback
= 1;
4129 else if (skip_past_comma (&p
))
4132 operand
->addr
.postind
= 1;
4133 operand
->addr
.writeback
= 1;
4135 if (operand
->addr
.preind
)
4137 set_syntax_error (_("cannot combine pre- and post-indexing"));
4141 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
4145 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4147 set_syntax_error (_("invalid offset register"));
4151 operand
->addr
.offset
.regno
= reg
->number
;
4152 operand
->addr
.offset
.is_reg
= 1;
4154 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4157 set_syntax_error (_("invalid expression in the address"));
4162 /* If at this point neither .preind nor .postind is set, we have a
4163 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4164 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4165 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4167 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4169 if (operand
->addr
.writeback
)
4171 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4173 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4174 operand
->addr
.offset
.is_reg
= 0;
4175 operand
->addr
.offset
.imm
= 0;
4176 operand
->addr
.preind
= 1;
4181 set_syntax_error (_("missing offset in the pre-indexed address"));
4187 operand
->addr
.preind
= 1;
4188 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4190 operand
->addr
.offset
.is_reg
= 1;
4191 operand
->addr
.offset
.regno
= REG_ZR
;
4192 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4196 inst
.reloc
.exp
.X_op
= O_constant
;
4197 inst
.reloc
.exp
.X_add_number
= 0;
4206 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4209 parse_address (char **str
, aarch64_opnd_info
*operand
)
4211 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4212 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4213 REG_TYPE_R64_SP
, REG_TYPE_R_ZR
, SHIFTED_NONE
);
4216 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4217 The arguments have the same meaning as for parse_address_main.
4218 Return TRUE on success. */
4220 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4221 aarch64_opnd_qualifier_t
*base_qualifier
,
4222 aarch64_opnd_qualifier_t
*offset_qualifier
)
4224 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4225 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4229 /* Parse a register X0-X30. The register must be 64-bit and register 31
4232 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4234 const reg_entry
*reg
= parse_reg (str
);
4235 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4237 set_expected_reg_error (REG_TYPE_R_64
, reg
, 0);
4240 operand
->reg
.regno
= reg
->number
;
4241 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4245 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4246 Return TRUE on success; otherwise return FALSE. */
4248 parse_half (char **str
, int *internal_fixup_p
)
4252 skip_past_char (&p
, '#');
4254 gas_assert (internal_fixup_p
);
4255 *internal_fixup_p
= 0;
4259 struct reloc_table_entry
*entry
;
4261 /* Try to parse a relocation. Anything else is an error. */
4264 if (!(entry
= find_reloc_table_entry (&p
)))
4266 set_syntax_error (_("unknown relocation modifier"));
4270 if (entry
->movw_type
== 0)
4273 (_("this relocation modifier is not allowed on this instruction"));
4277 inst
.reloc
.type
= entry
->movw_type
;
4280 *internal_fixup_p
= 1;
4282 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4289 /* Parse an operand for an ADRP instruction:
4291 Return TRUE on success; otherwise return FALSE. */
4294 parse_adrp (char **str
)
4301 struct reloc_table_entry
*entry
;
4303 /* Try to parse a relocation. Anything else is an error. */
4305 if (!(entry
= find_reloc_table_entry (&p
)))
4307 set_syntax_error (_("unknown relocation modifier"));
4311 if (entry
->adrp_type
== 0)
4314 (_("this relocation modifier is not allowed on this instruction"));
4318 inst
.reloc
.type
= entry
->adrp_type
;
4321 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4323 inst
.reloc
.pc_rel
= 1;
4324 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4330 /* Miscellaneous. */
4332 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4333 of SIZE tokens in which index I gives the token for field value I,
4334 or is null if field value I is invalid. If the symbolic operand
4335 can also be given as a 0-based integer, REG_TYPE says which register
4336 names should be treated as registers rather than as symbolic immediates
4337 while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise.
4339 Return true on success, moving *STR past the operand and storing the
4340 field value in *VAL. */
4343 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4344 size_t size
, aarch64_reg_type reg_type
)
4350 /* Match C-like tokens. */
4352 while (ISALNUM (*q
))
4355 for (i
= 0; i
< size
; ++i
)
4357 && strncasecmp (array
[i
], p
, q
- p
) == 0
4358 && array
[i
][q
- p
] == 0)
4365 if (reg_type
== REG_TYPE_MAX
)
4368 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4371 if (exp
.X_op
== O_constant
4372 && (uint64_t) exp
.X_add_number
< size
)
4374 *val
= exp
.X_add_number
;
4379 /* Use the default error for this operand. */
4383 /* Parse an option for a preload instruction. Returns the encoding for the
4384 option, or PARSE_FAIL. */
4387 parse_pldop (char **str
)
4390 const struct aarch64_name_value_pair
*o
;
4393 while (ISALNUM (*q
))
4396 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4404 /* Parse an option for a barrier instruction. Returns the encoding for the
4405 option, or PARSE_FAIL. */
4408 parse_barrier (char **str
)
4411 const struct aarch64_name_value_pair
*o
;
4414 while (ISALPHA (*q
))
4417 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4425 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4426 return 0 if successful. Otherwise return PARSE_FAIL. */
4429 parse_barrier_psb (char **str
,
4430 const struct aarch64_name_value_pair
** hint_opt
)
4433 const struct aarch64_name_value_pair
*o
;
4436 while (ISALPHA (*q
))
4439 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4442 set_fatal_syntax_error
4443 ( _("unknown or missing option to PSB/TSB"));
4447 if (o
->value
!= 0x11)
4449 /* PSB only accepts option name 'CSYNC'. */
4451 (_("the specified option is not accepted for PSB/TSB"));
4460 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4461 return 0 if successful. Otherwise return PARSE_FAIL. */
4464 parse_bti_operand (char **str
,
4465 const struct aarch64_name_value_pair
** hint_opt
)
4468 const struct aarch64_name_value_pair
*o
;
4471 while (ISALPHA (*q
))
4474 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4477 set_fatal_syntax_error
4478 ( _("unknown option to BTI"));
4484 /* Valid BTI operands. */
4492 (_("unknown option to BTI"));
4501 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4502 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4507 Side effect: Update STR with current parse position of success.
4509 FLAGS is as for parse_typed_reg. */
4511 static const reg_entry
*
4512 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4513 aarch64_opnd_qualifier_t
*qualifier
, unsigned int flags
)
4515 struct vector_type_el vectype
;
4516 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4517 PTR_FULL_REG
| flags
);
4521 if (vectype
.type
== NT_invtype
)
4522 *qualifier
= AARCH64_OPND_QLF_NIL
;
4525 *qualifier
= vectype_to_qualifier (&vectype
);
4526 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4533 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4538 Function return TRUE if immediate was found, or FALSE.
4541 parse_sme_immediate (char **str
, int64_t *imm
)
4544 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4551 /* Parse index with selection register and immediate offset:
4556 Return true on success, populating OPND with the parsed index. */
4559 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4561 const reg_entry
*reg
;
4563 if (!skip_past_char (str
, '['))
4565 set_syntax_error (_("expected '['"));
4569 /* The selection register, encoded in the 2-bit Rv field. */
4570 reg
= parse_reg (str
);
4571 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
)
4573 set_syntax_error (_("expected a 32-bit selection register"));
4576 opnd
->index
.regno
= reg
->number
;
4578 if (!skip_past_char (str
, ','))
4580 set_syntax_error (_("missing immediate offset"));
4584 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4586 set_syntax_error (_("expected a constant immediate offset"));
4590 if (skip_past_char (str
, ':'))
4593 if (!parse_sme_immediate (str
, &end
))
4595 set_syntax_error (_("expected a constant immediate offset"));
4598 if (end
< opnd
->index
.imm
)
4600 set_syntax_error (_("the last offset is less than the"
4604 if (end
== opnd
->index
.imm
)
4606 set_syntax_error (_("the last offset is equal to the"
4610 opnd
->index
.countm1
= (uint64_t) end
- opnd
->index
.imm
;
4613 opnd
->group_size
= 0;
4614 if (skip_past_char (str
, ','))
4616 if (strncasecmp (*str
, "vgx2", 4) == 0 && !ISALPHA ((*str
)[4]))
4619 opnd
->group_size
= 2;
4621 else if (strncasecmp (*str
, "vgx4", 4) == 0 && !ISALPHA ((*str
)[4]))
4624 opnd
->group_size
= 4;
4628 set_syntax_error (_("invalid vector group size"));
4633 if (!skip_past_char (str
, ']'))
4635 set_syntax_error (_("expected ']'"));
4642 /* Parse a register of type REG_TYPE that might have an element type
4643 qualifier and that is indexed by two values: a 32-bit register,
4644 followed by an immediate. The ranges of the register and the
4645 immediate vary by opcode and are checked in libopcodes.
4647 Return true on success, populating OPND with information about
4648 the operand and setting QUALIFIER to the register qualifier.
4650 Field format examples:
4652 <Pm>.<T>[<Wv>< #<imm>]
4654 <ZAn><HV>.<T>[<Wv>, #<imm>]
4656 FLAGS is as for parse_typed_reg. */
4659 parse_dual_indexed_reg (char **str
, aarch64_reg_type reg_type
,
4660 struct aarch64_indexed_za
*opnd
,
4661 aarch64_opnd_qualifier_t
*qualifier
,
4664 const reg_entry
*reg
= parse_reg_with_qual (str
, reg_type
, qualifier
, flags
);
4668 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4669 opnd
->regno
= reg
->number
;
4671 return parse_sme_za_index (str
, opnd
);
4674 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4678 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4679 struct aarch64_indexed_za
*opnd
,
4680 aarch64_opnd_qualifier_t
*qualifier
)
4682 if (!skip_past_char (str
, '{'))
4684 set_expected_reglist_error (REG_TYPE_ZATHV
, parse_reg (str
));
4688 if (!parse_dual_indexed_reg (str
, REG_TYPE_ZATHV
, opnd
, qualifier
,
4692 if (!skip_past_char (str
, '}'))
4694 set_syntax_error (_("expected '}'"));
4701 /* Parse list of up to eight 64-bit element tile names separated by commas in
4702 SME's ZERO instruction:
4706 Function returns <mask>:
4708 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4711 parse_sme_zero_mask(char **str
)
4715 aarch64_opnd_qualifier_t qualifier
;
4716 unsigned int ptr_flags
= PTR_IN_REGLIST
;
4722 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4723 &qualifier
, ptr_flags
);
4727 if (reg
->type
== REG_TYPE_ZA
)
4729 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4731 set_syntax_error ("ZA should not have a size suffix");
4734 /* { ZA } is assembled as all-ones immediate. */
4739 int regno
= reg
->number
;
4740 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4742 /* { ZA0.B } is assembled as all-ones immediate. */
4745 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4746 mask
|= 0x55 << regno
;
4747 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4748 mask
|= 0x11 << regno
;
4749 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4750 mask
|= 0x01 << regno
;
4751 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4753 set_syntax_error (_("ZA tile masks do not operate at .Q"
4757 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4759 set_syntax_error (_("missing ZA tile size"));
4764 set_syntax_error (_("invalid ZA tile"));
4768 ptr_flags
|= PTR_GOOD_MATCH
;
4770 while (skip_past_char (&q
, ','));
4776 /* Wraps in curly braces <mask> operand ZERO instruction:
4780 Function returns value of <mask> bit-field.
4783 parse_sme_list_of_64bit_tiles (char **str
)
4787 if (!skip_past_char (str
, '{'))
4789 set_syntax_error (_("expected '{'"));
4793 /* Empty <mask> list is an all-zeros immediate. */
4794 if (!skip_past_char (str
, '}'))
4796 regno
= parse_sme_zero_mask (str
);
4797 if (regno
== PARSE_FAIL
)
4800 if (!skip_past_char (str
, '}'))
4802 set_syntax_error (_("expected '}'"));
4812 /* Parse streaming mode operand for SMSTART and SMSTOP.
4816 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4819 parse_sme_sm_za (char **str
)
4824 while (ISALPHA (*q
))
4828 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4830 set_syntax_error (_("expected SM or ZA operand"));
4835 return TOLOWER (p
[0]);
4838 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4839 Returns the encoding for the option, or PARSE_FAIL.
4841 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4842 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4844 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4845 field, otherwise as a system register.
4849 parse_sys_reg (char **str
, htab_t sys_regs
,
4850 int imple_defined_p
, int pstatefield_p
,
4854 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4855 const aarch64_sys_reg
*o
;
4859 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4860 if (p
< buf
+ (sizeof (buf
) - 1))
4861 *p
++ = TOLOWER (*q
);
4864 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4865 valid system register. This is enforced by construction of the hash
4867 if (p
- buf
!= q
- *str
)
4870 o
= str_hash_find (sys_regs
, buf
);
4873 if (!imple_defined_p
)
4877 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4878 unsigned int op0
, op1
, cn
, cm
, op2
;
4880 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4883 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4885 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4892 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4893 as_bad (_("selected processor does not support PSTATE field "
4896 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4897 o
->value
, o
->flags
, o
->features
))
4898 as_bad (_("selected processor does not support system register "
4900 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4901 as_warn (_("system register name '%s' is deprecated and may be "
4902 "removed in a future release"), buf
);
4912 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4913 for the option, or NULL. */
4915 static const aarch64_sys_ins_reg
*
4916 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4919 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4920 const aarch64_sys_ins_reg
*o
;
4923 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4924 if (p
< buf
+ (sizeof (buf
) - 1))
4925 *p
++ = TOLOWER (*q
);
4928 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4929 valid system register. This is enforced by construction of the hash
4931 if (p
- buf
!= q
- *str
)
4934 o
= str_hash_find (sys_ins_regs
, buf
);
4938 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4939 o
->name
, o
->value
, o
->flags
, 0))
4940 as_bad (_("selected processor does not support system register "
4942 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4943 as_warn (_("system register name '%s' is deprecated and may be "
4944 "removed in a future release"), buf
);
4950 #define po_char_or_fail(chr) do { \
4951 if (! skip_past_char (&str, chr)) \
4955 #define po_reg_or_fail(regtype) do { \
4956 reg = aarch64_reg_parse (&str, regtype, NULL); \
4961 #define po_int_fp_reg_or_fail(reg_type) do { \
4962 reg = parse_reg (&str); \
4963 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4965 set_expected_reg_error (reg_type, reg, 0); \
4968 info->reg.regno = reg->number; \
4969 info->qualifier = inherent_reg_qualifier (reg); \
4972 #define po_imm_nc_or_fail() do { \
4973 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4977 #define po_imm_or_fail(min, max) do { \
4978 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4980 if (val < min || val > max) \
4982 set_fatal_syntax_error (_("immediate value out of range "\
4983 #min " to "#max)); \
4988 #define po_enum_or_fail(array) do { \
4989 if (!parse_enum_string (&str, &val, array, \
4990 ARRAY_SIZE (array), imm_reg_type)) \
4994 #define po_strict_enum_or_fail(array) do { \
4995 if (!parse_enum_string (&str, &val, array, \
4996 ARRAY_SIZE (array), REG_TYPE_MAX)) \
5000 #define po_misc_or_fail(expr) do { \
5005 /* A primitive log calculator. */
5007 static inline unsigned int
5008 get_log2 (unsigned int n
)
5010 unsigned int count
= 0;
5019 /* encode the 12-bit imm field of Add/sub immediate */
5020 static inline uint32_t
5021 encode_addsub_imm (uint32_t imm
)
5026 /* encode the shift amount field of Add/sub immediate */
5027 static inline uint32_t
5028 encode_addsub_imm_shift_amount (uint32_t cnt
)
5034 /* encode the imm field of Adr instruction */
5035 static inline uint32_t
5036 encode_adr_imm (uint32_t imm
)
5038 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
5039 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
5042 /* encode the immediate field of Move wide immediate */
5043 static inline uint32_t
5044 encode_movw_imm (uint32_t imm
)
5049 /* encode the 26-bit offset of unconditional branch */
5050 static inline uint32_t
5051 encode_branch_ofs_26 (uint32_t ofs
)
5053 return ofs
& ((1 << 26) - 1);
5056 /* encode the 19-bit offset of conditional branch and compare & branch */
5057 static inline uint32_t
5058 encode_cond_branch_ofs_19 (uint32_t ofs
)
5060 return (ofs
& ((1 << 19) - 1)) << 5;
5063 /* encode the 19-bit offset of ld literal */
5064 static inline uint32_t
5065 encode_ld_lit_ofs_19 (uint32_t ofs
)
5067 return (ofs
& ((1 << 19) - 1)) << 5;
5070 /* Encode the 14-bit offset of test & branch. */
5071 static inline uint32_t
5072 encode_tst_branch_ofs_14 (uint32_t ofs
)
5074 return (ofs
& ((1 << 14) - 1)) << 5;
5077 /* Encode the 16-bit imm field of svc/hvc/smc. */
5078 static inline uint32_t
5079 encode_svc_imm (uint32_t imm
)
5084 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5085 static inline uint32_t
5086 reencode_addsub_switch_add_sub (uint32_t opcode
)
5088 return opcode
^ (1 << 30);
5091 static inline uint32_t
5092 reencode_movzn_to_movz (uint32_t opcode
)
5094 return opcode
| (1 << 30);
5097 static inline uint32_t
5098 reencode_movzn_to_movn (uint32_t opcode
)
5100 return opcode
& ~(1 << 30);
5103 /* Overall per-instruction processing. */
5105 /* We need to be able to fix up arbitrary expressions in some statements.
5106 This is so that we can handle symbols that are an arbitrary distance from
5107 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5108 which returns part of an address in a form which will be valid for
5109 a data instruction. We do this by pushing the expression into a symbol
5110 in the expr_section, and creating a fix for that. */
5113 fix_new_aarch64 (fragS
* frag
,
5128 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5132 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5139 /* Diagnostics on operands errors. */
5141 /* By default, output verbose error message.
5142 Disable the verbose error message by -mno-verbose-error. */
5143 static int verbose_error_p
= 1;
5145 #ifdef DEBUG_AARCH64
5146 /* N.B. this is only for the purpose of debugging. */
5147 const char* operand_mismatch_kind_names
[] =
5150 "AARCH64_OPDE_RECOVERABLE",
5151 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5152 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5153 "AARCH64_OPDE_SYNTAX_ERROR",
5154 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5155 "AARCH64_OPDE_INVALID_VARIANT",
5156 "AARCH64_OPDE_INVALID_VG_SIZE",
5157 "AARCH64_OPDE_REG_LIST_LENGTH",
5158 "AARCH64_OPDE_REG_LIST_STRIDE",
5159 "AARCH64_OPDE_UNTIED_IMMS",
5160 "AARCH64_OPDE_UNTIED_OPERAND",
5161 "AARCH64_OPDE_OUT_OF_RANGE",
5162 "AARCH64_OPDE_UNALIGNED",
5163 "AARCH64_OPDE_OTHER_ERROR",
5164 "AARCH64_OPDE_INVALID_REGNO",
5166 #endif /* DEBUG_AARCH64 */
5168 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5170 When multiple errors of different kinds are found in the same assembly
5171 line, only the error of the highest severity will be picked up for
5172 issuing the diagnostics. */
5175 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5176 enum aarch64_operand_error_kind rhs
)
5178 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5179 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5180 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5181 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5182 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5183 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5184 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5185 gas_assert (AARCH64_OPDE_INVALID_VG_SIZE
> AARCH64_OPDE_INVALID_VARIANT
);
5186 gas_assert (AARCH64_OPDE_REG_LIST_LENGTH
> AARCH64_OPDE_INVALID_VG_SIZE
);
5187 gas_assert (AARCH64_OPDE_REG_LIST_STRIDE
> AARCH64_OPDE_REG_LIST_LENGTH
);
5188 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_REG_LIST_STRIDE
);
5189 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5190 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST_STRIDE
);
5191 gas_assert (AARCH64_OPDE_INVALID_REGNO
> AARCH64_OPDE_OTHER_ERROR
);
5195 /* Helper routine to get the mnemonic name from the assembly instruction
5196 line; should only be called for the diagnosis purpose, as there is
5197 string copy operation involved, which may affect the runtime
5198 performance if used in elsewhere. */
5201 get_mnemonic_name (const char *str
)
5203 static char mnemonic
[32];
5206 /* Get the first 15 bytes and assume that the full name is included. */
5207 strncpy (mnemonic
, str
, 31);
5208 mnemonic
[31] = '\0';
5210 /* Scan up to the end of the mnemonic, which must end in white space,
5211 '.', or end of string. */
5212 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5217 /* Append '...' to the truncated long name. */
5218 if (ptr
- mnemonic
== 31)
5219 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5225 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5227 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5228 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5231 /* Data structures storing one user error in the assembly code related to
5234 struct operand_error_record
5236 const aarch64_opcode
*opcode
;
5237 aarch64_operand_error detail
;
5238 struct operand_error_record
*next
;
5241 typedef struct operand_error_record operand_error_record
;
5243 struct operand_errors
5245 operand_error_record
*head
;
5246 operand_error_record
*tail
;
5249 typedef struct operand_errors operand_errors
;
5251 /* Top-level data structure reporting user errors for the current line of
5253 The way md_assemble works is that all opcodes sharing the same mnemonic
5254 name are iterated to find a match to the assembly line. In this data
5255 structure, each of the such opcodes will have one operand_error_record
5256 allocated and inserted. In other words, excessive errors related with
5257 a single opcode are disregarded. */
5258 operand_errors operand_error_report
;
5260 /* Free record nodes. */
5261 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5263 /* Initialize the data structure that stores the operand mismatch
5264 information on assembling one line of the assembly code. */
5266 init_operand_error_report (void)
5268 if (operand_error_report
.head
!= NULL
)
5270 gas_assert (operand_error_report
.tail
!= NULL
);
5271 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5272 free_opnd_error_record_nodes
= operand_error_report
.head
;
5273 operand_error_report
.head
= NULL
;
5274 operand_error_report
.tail
= NULL
;
5277 gas_assert (operand_error_report
.tail
== NULL
);
5280 /* Return TRUE if some operand error has been recorded during the
5281 parsing of the current assembly line using the opcode *OPCODE;
5282 otherwise return FALSE. */
5284 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5286 operand_error_record
*record
= operand_error_report
.head
;
5287 return record
&& record
->opcode
== opcode
;
5290 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5291 OPCODE field is initialized with OPCODE.
5292 N.B. only one record for each opcode, i.e. the maximum of one error is
5293 recorded for each instruction template. */
5296 add_operand_error_record (const operand_error_record
* new_record
)
5298 const aarch64_opcode
*opcode
= new_record
->opcode
;
5299 operand_error_record
* record
= operand_error_report
.head
;
5301 /* The record may have been created for this opcode. If not, we need
5303 if (! opcode_has_operand_error_p (opcode
))
5305 /* Get one empty record. */
5306 if (free_opnd_error_record_nodes
== NULL
)
5308 record
= XNEW (operand_error_record
);
5312 record
= free_opnd_error_record_nodes
;
5313 free_opnd_error_record_nodes
= record
->next
;
5315 record
->opcode
= opcode
;
5316 /* Insert at the head. */
5317 record
->next
= operand_error_report
.head
;
5318 operand_error_report
.head
= record
;
5319 if (operand_error_report
.tail
== NULL
)
5320 operand_error_report
.tail
= record
;
5322 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5323 && record
->detail
.index
<= new_record
->detail
.index
5324 && operand_error_higher_severity_p (record
->detail
.kind
,
5325 new_record
->detail
.kind
))
5327 /* In the case of multiple errors found on operands related with a
5328 single opcode, only record the error of the leftmost operand and
5329 only if the error is of higher severity. */
5330 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5331 " the existing error %s on operand %d",
5332 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5333 new_record
->detail
.index
,
5334 operand_mismatch_kind_names
[record
->detail
.kind
],
5335 record
->detail
.index
);
5339 record
->detail
= new_record
->detail
;
5343 record_operand_error_info (const aarch64_opcode
*opcode
,
5344 aarch64_operand_error
*error_info
)
5346 operand_error_record record
;
5347 record
.opcode
= opcode
;
5348 record
.detail
= *error_info
;
5349 add_operand_error_record (&record
);
5352 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5353 error message *ERROR, for operand IDX (count from 0). */
5356 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5357 enum aarch64_operand_error_kind kind
,
5360 aarch64_operand_error info
;
5361 memset(&info
, 0, sizeof (info
));
5365 info
.non_fatal
= false;
5366 record_operand_error_info (opcode
, &info
);
5370 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5371 enum aarch64_operand_error_kind kind
,
5372 const char* error
, const int *extra_data
)
5374 aarch64_operand_error info
;
5378 info
.data
[0].i
= extra_data
[0];
5379 info
.data
[1].i
= extra_data
[1];
5380 info
.data
[2].i
= extra_data
[2];
5381 info
.non_fatal
= false;
5382 record_operand_error_info (opcode
, &info
);
5386 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5387 const char* error
, int lower_bound
,
5390 int data
[3] = {lower_bound
, upper_bound
, 0};
5391 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5395 /* Remove the operand error record for *OPCODE. */
5396 static void ATTRIBUTE_UNUSED
5397 remove_operand_error_record (const aarch64_opcode
*opcode
)
5399 if (opcode_has_operand_error_p (opcode
))
5401 operand_error_record
* record
= operand_error_report
.head
;
5402 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5403 operand_error_report
.head
= record
->next
;
5404 record
->next
= free_opnd_error_record_nodes
;
5405 free_opnd_error_record_nodes
= record
;
5406 if (operand_error_report
.head
== NULL
)
5408 gas_assert (operand_error_report
.tail
== record
);
5409 operand_error_report
.tail
= NULL
;
5414 /* Given the instruction in *INSTR, return the index of the best matched
5415 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5417 Return -1 if there is no qualifier sequence; return the first match
5418 if there is multiple matches found. */
5421 find_best_match (const aarch64_inst
*instr
,
5422 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5424 int i
, num_opnds
, max_num_matched
, idx
;
5426 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5429 DEBUG_TRACE ("no operand");
5433 max_num_matched
= 0;
5436 /* For each pattern. */
5437 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5440 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5442 /* Most opcodes has much fewer patterns in the list. */
5443 if (empty_qualifier_sequence_p (qualifiers
))
5445 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5449 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5450 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5453 if (num_matched
> max_num_matched
)
5455 max_num_matched
= num_matched
;
5460 DEBUG_TRACE ("return with %d", idx
);
5464 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5465 corresponding operands in *INSTR. */
5468 assign_qualifier_sequence (aarch64_inst
*instr
,
5469 const aarch64_opnd_qualifier_t
*qualifiers
)
5472 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5473 gas_assert (num_opnds
);
5474 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5475 instr
->operands
[i
].qualifier
= *qualifiers
;
5478 /* Callback used by aarch64_print_operand to apply STYLE to the
5479 disassembler output created from FMT and ARGS. The STYLER object holds
5480 any required state. Must return a pointer to a string (created from FMT
5481 and ARGS) that will continue to be valid until the complete disassembled
5482 instruction has been printed.
5484 We don't currently add any styling to the output of the disassembler as
5485 used within assembler error messages, and so STYLE is ignored here. A
5486 new string is allocated on the obstack help within STYLER and returned
5489 static const char *aarch64_apply_style
5490 (struct aarch64_styler
*styler
,
5491 enum disassembler_style style ATTRIBUTE_UNUSED
,
5492 const char *fmt
, va_list args
)
5496 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5499 /* Calculate the required space. */
5501 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5503 gas_assert (res
>= 0);
5505 /* Allocate space on the obstack and format the result. */
5506 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5507 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5508 gas_assert (res
>= 0);
5513 /* Print operands for the diagnosis purpose. */
5516 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5517 const aarch64_opnd_info
*opnds
)
5520 struct aarch64_styler styler
;
5521 struct obstack content
;
5522 obstack_init (&content
);
5524 styler
.apply_style
= aarch64_apply_style
;
5525 styler
.state
= (void *) &content
;
5527 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5532 /* We regard the opcode operand info more, however we also look into
5533 the inst->operands to support the disassembling of the optional
5535 The two operand code should be the same in all cases, apart from
5536 when the operand can be optional. */
5537 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5538 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5541 /* Generate the operand string in STR. */
5542 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5543 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5547 strcat (buf
, i
== 0 ? " " : ", ");
5549 /* Append the operand string. */
5552 /* Append a comment. This works because only the last operand ever
5553 adds a comment. If that ever changes then we'll need to be
5557 strcat (buf
, "\t// ");
5562 obstack_free (&content
, NULL
);
5565 /* Send to stderr a string as information. */
5568 output_info (const char *format
, ...)
5574 file
= as_where (&line
);
5578 fprintf (stderr
, "%s:%u: ", file
, line
);
5580 fprintf (stderr
, "%s: ", file
);
5582 fprintf (stderr
, _("Info: "));
5583 va_start (args
, format
);
5584 vfprintf (stderr
, format
, args
);
5586 (void) putc ('\n', stderr
);
5589 /* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
5590 relates to registers or register lists. If so, return a string that
5591 reports the error against "operand %d", otherwise return null. */
5594 get_reg_error_message (const aarch64_operand_error
*detail
)
5596 /* Handle the case where we found a register that was expected
5597 to be in a register list outside of a register list. */
5598 if ((detail
->data
[1].i
& detail
->data
[2].i
) != 0
5599 && (detail
->data
[1].i
& SEF_IN_REGLIST
) == 0)
5600 return _("missing braces at operand %d");
5602 /* If some opcodes expected a register, and we found a register,
5603 complain about the difference. */
5604 if (detail
->data
[2].i
)
5606 unsigned int expected
= (detail
->data
[1].i
& SEF_IN_REGLIST
5607 ? detail
->data
[1].i
& ~SEF_IN_REGLIST
5608 : detail
->data
[0].i
& ~SEF_DEFAULT_ERROR
);
5609 const char *msg
= get_reg_expected_msg (expected
, detail
->data
[2].i
);
5611 msg
= N_("unexpected register type at operand %d");
5615 /* Handle the case where we got to the point of trying to parse a
5616 register within a register list, but didn't find a known register. */
5617 if (detail
->data
[1].i
& SEF_IN_REGLIST
)
5619 unsigned int expected
= detail
->data
[1].i
& ~SEF_IN_REGLIST
;
5620 const char *msg
= get_reg_expected_msg (expected
, 0);
5622 msg
= _("invalid register list at operand %d");
5626 /* Punt if register-related problems weren't the only errors. */
5627 if (detail
->data
[0].i
& SEF_DEFAULT_ERROR
)
5630 /* Handle the case where the only acceptable things are registers. */
5631 if (detail
->data
[1].i
== 0)
5633 const char *msg
= get_reg_expected_msg (detail
->data
[0].i
, 0);
5635 msg
= _("expected a register at operand %d");
5639 /* Handle the case where the only acceptable things are register lists,
5640 and there was no opening '{'. */
5641 if (detail
->data
[0].i
== 0)
5642 return _("expected '{' at operand %d");
5644 return _("expected a register or register list at operand %d");
5647 /* Output one operand error record. */
5650 output_operand_error_record (const operand_error_record
*record
, char *str
)
5652 const aarch64_operand_error
*detail
= &record
->detail
;
5653 int idx
= detail
->index
;
5654 const aarch64_opcode
*opcode
= record
->opcode
;
5655 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5656 : AARCH64_OPND_NIL
);
5658 typedef void (*handler_t
)(const char *format
, ...);
5659 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5660 const char *msg
= detail
->error
;
5662 switch (detail
->kind
)
5664 case AARCH64_OPDE_NIL
:
5668 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5669 handler (_("this `%s' should have an immediately preceding `%s'"
5671 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5674 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5675 handler (_("the preceding `%s' should be followed by `%s` rather"
5676 " than `%s` -- `%s'"),
5677 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5680 case AARCH64_OPDE_SYNTAX_ERROR
:
5681 if (!msg
&& idx
>= 0)
5683 msg
= get_reg_error_message (detail
);
5686 char *full_msg
= xasprintf (msg
, idx
+ 1);
5687 handler (_("%s -- `%s'"), full_msg
, str
);
5694 case AARCH64_OPDE_RECOVERABLE
:
5695 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5696 case AARCH64_OPDE_OTHER_ERROR
:
5697 /* Use the prepared error message if there is, otherwise use the
5698 operand description string to describe the error. */
5702 handler (_("%s -- `%s'"), msg
, str
);
5704 handler (_("%s at operand %d -- `%s'"),
5709 gas_assert (idx
>= 0);
5710 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5711 aarch64_get_operand_desc (opd_code
), str
);
5715 case AARCH64_OPDE_INVALID_VARIANT
:
5716 handler (_("operand mismatch -- `%s'"), str
);
5717 if (verbose_error_p
)
5719 /* We will try to correct the erroneous instruction and also provide
5720 more information e.g. all other valid variants.
5722 The string representation of the corrected instruction and other
5723 valid variants are generated by
5725 1) obtaining the intermediate representation of the erroneous
5727 2) manipulating the IR, e.g. replacing the operand qualifier;
5728 3) printing out the instruction by calling the printer functions
5729 shared with the disassembler.
5731 The limitation of this method is that the exact input assembly
5732 line cannot be accurately reproduced in some cases, for example an
5733 optional operand present in the actual assembly line will be
5734 omitted in the output; likewise for the optional syntax rules,
5735 e.g. the # before the immediate. Another limitation is that the
5736 assembly symbols and relocation operations in the assembly line
5737 currently cannot be printed out in the error report. Last but not
5738 least, when there is other error(s) co-exist with this error, the
5739 'corrected' instruction may be still incorrect, e.g. given
5740 'ldnp h0,h1,[x0,#6]!'
5741 this diagnosis will provide the version:
5742 'ldnp s0,s1,[x0,#6]!'
5743 which is still not right. */
5744 size_t len
= strlen (get_mnemonic_name (str
));
5748 aarch64_inst
*inst_base
= &inst
.base
;
5749 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5752 reset_aarch64_instruction (&inst
);
5753 inst_base
->opcode
= opcode
;
5755 /* Reset the error report so that there is no side effect on the
5756 following operand parsing. */
5757 init_operand_error_report ();
5760 result
= parse_operands (str
+ len
, opcode
)
5761 && programmer_friendly_fixup (&inst
);
5762 gas_assert (result
);
5763 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5764 NULL
, NULL
, insn_sequence
);
5765 gas_assert (!result
);
5767 /* Find the most matched qualifier sequence. */
5768 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5769 gas_assert (qlf_idx
> -1);
5771 /* Assign the qualifiers. */
5772 assign_qualifier_sequence (inst_base
,
5773 opcode
->qualifiers_list
[qlf_idx
]);
5775 /* Print the hint. */
5776 output_info (_(" did you mean this?"));
5777 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5778 print_operands (buf
, opcode
, inst_base
->operands
);
5779 output_info (_(" %s"), buf
);
5781 /* Print out other variant(s) if there is any. */
5783 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5784 output_info (_(" other valid variant(s):"));
5786 /* For each pattern. */
5787 qualifiers_list
= opcode
->qualifiers_list
;
5788 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5790 /* Most opcodes has much fewer patterns in the list.
5791 First NIL qualifier indicates the end in the list. */
5792 if (empty_qualifier_sequence_p (*qualifiers_list
))
5797 /* Mnemonics name. */
5798 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5800 /* Assign the qualifiers. */
5801 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5803 /* Print instruction. */
5804 print_operands (buf
, opcode
, inst_base
->operands
);
5806 output_info (_(" %s"), buf
);
5812 case AARCH64_OPDE_UNTIED_IMMS
:
5813 handler (_("operand %d must have the same immediate value "
5814 "as operand 1 -- `%s'"),
5815 detail
->index
+ 1, str
);
5818 case AARCH64_OPDE_UNTIED_OPERAND
:
5819 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5820 detail
->index
+ 1, str
);
5823 case AARCH64_OPDE_INVALID_REGNO
:
5824 handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
5825 detail
->data
[0].s
, detail
->data
[1].i
,
5826 detail
->data
[0].s
, detail
->data
[2].i
, idx
+ 1, str
);
5829 case AARCH64_OPDE_OUT_OF_RANGE
:
5830 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5831 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5832 msg
? msg
: _("immediate value"),
5833 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5835 handler (_("%s must be %d at operand %d -- `%s'"),
5836 msg
? msg
: _("immediate value"),
5837 detail
->data
[0].i
, idx
+ 1, str
);
5840 case AARCH64_OPDE_INVALID_VG_SIZE
:
5841 if (detail
->data
[0].i
== 0)
5842 handler (_("unexpected vector group size at operand %d -- `%s'"),
5845 handler (_("operand %d must have a vector group size of %d -- `%s'"),
5846 idx
+ 1, detail
->data
[0].i
, str
);
5849 case AARCH64_OPDE_REG_LIST_LENGTH
:
5850 if (detail
->data
[0].i
== (1 << 1))
5851 handler (_("expected a single-register list at operand %d -- `%s'"),
5853 else if ((detail
->data
[0].i
& -detail
->data
[0].i
) == detail
->data
[0].i
)
5854 handler (_("expected a list of %d registers at operand %d -- `%s'"),
5855 get_log2 (detail
->data
[0].i
), idx
+ 1, str
);
5856 else if (detail
->data
[0].i
== 0x14)
5857 handler (_("expected a list of %d or %d registers at"
5858 " operand %d -- `%s'"),
5859 2, 4, idx
+ 1, str
);
5861 handler (_("invalid number of registers in the list"
5862 " at operand %d -- `%s'"), idx
+ 1, str
);
5865 case AARCH64_OPDE_REG_LIST_STRIDE
:
5866 if (detail
->data
[0].i
== (1 << 1))
5867 handler (_("the register list must have a stride of %d"
5868 " at operand %d -- `%s'"), 1, idx
+ 1, str
);
5869 else if (detail
->data
[0].i
== 0x12 || detail
->data
[0].i
== 0x102)
5870 handler (_("the register list must have a stride of %d or %d"
5871 " at operand %d -- `%s`"), 1,
5872 detail
->data
[0].i
== 0x12 ? 4 : 8, idx
+ 1, str
);
5874 handler (_("invalid register stride at operand %d -- `%s'"),
5878 case AARCH64_OPDE_UNALIGNED
:
5879 handler (_("immediate value must be a multiple of "
5880 "%d at operand %d -- `%s'"),
5881 detail
->data
[0].i
, idx
+ 1, str
);
5890 /* Return true if the presence of error A against an instruction means
5891 that error B should not be reported. This is only used as a first pass,
5892 to pick the kind of error that we should report. */
5895 better_error_p (operand_error_record
*a
, operand_error_record
*b
)
5897 /* For errors reported during parsing, prefer errors that relate to
5898 later operands, since that implies that the earlier operands were
5899 syntactically valid.
5901 For example, if we see a register R instead of an immediate in
5902 operand N, we'll report that as a recoverable "immediate operand
5903 required" error. This is because there is often another opcode
5904 entry that accepts a register operand N, and any errors about R
5905 should be reported against the register forms of the instruction.
5906 But if no such register form exists, the recoverable error should
5907 still win over a syntax error against operand N-1.
5909 For these purposes, count an error reported at the end of the
5910 assembly string as equivalent to an error reported against the
5911 final operand. This means that opcode entries that expect more
5912 operands win over "unexpected characters following instruction". */
5913 if (a
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
5914 && b
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
)
5916 int a_index
= (a
->detail
.index
< 0
5917 ? aarch64_num_of_operands (a
->opcode
) - 1
5919 int b_index
= (b
->detail
.index
< 0
5920 ? aarch64_num_of_operands (b
->opcode
) - 1
5922 if (a_index
!= b_index
)
5923 return a_index
> b_index
;
5925 return operand_error_higher_severity_p (a
->detail
.kind
, b
->detail
.kind
);
5928 /* Process and output the error message about the operand mismatching.
5930 When this function is called, the operand error information had
5931 been collected for an assembly line and there will be multiple
5932 errors in the case of multiple instruction templates; output the
5933 error message that most closely describes the problem.
5935 The errors to be printed can be filtered on printing all errors
5936 or only non-fatal errors. This distinction has to be made because
5937 the error buffer may already be filled with fatal errors we don't want to
5938 print due to the different instruction templates. */
5941 output_operand_error_report (char *str
, bool non_fatal_only
)
5943 enum aarch64_operand_error_kind kind
;
5944 operand_error_record
*curr
;
5945 operand_error_record
*head
= operand_error_report
.head
;
5946 operand_error_record
*record
;
5948 /* No error to report. */
5952 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5954 /* Only one error. */
5955 if (head
== operand_error_report
.tail
)
5957 /* If the only error is a non-fatal one and we don't want to print it,
5959 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5961 DEBUG_TRACE ("single opcode entry with error kind: %s",
5962 operand_mismatch_kind_names
[head
->detail
.kind
]);
5963 output_operand_error_record (head
, str
);
5968 /* Find the error kind of the highest severity. */
5969 DEBUG_TRACE ("multiple opcode entries with error kind");
5971 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5973 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5974 if (curr
->detail
.kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5976 DEBUG_TRACE ("\t%s [%x, %x, %x]",
5977 operand_mismatch_kind_names
[curr
->detail
.kind
],
5978 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5979 curr
->detail
.data
[2].i
);
5981 else if (curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_LENGTH
5982 || curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
5984 DEBUG_TRACE ("\t%s [%x]",
5985 operand_mismatch_kind_names
[curr
->detail
.kind
],
5986 curr
->detail
.data
[0].i
);
5990 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5992 if ((!non_fatal_only
|| curr
->detail
.non_fatal
)
5993 && (!record
|| better_error_p (curr
, record
)))
5997 kind
= (record
? record
->detail
.kind
: AARCH64_OPDE_NIL
);
5998 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
6000 /* Pick up one of errors of KIND to report. */
6002 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
6004 /* If we don't want to print non-fatal errors then don't consider them
6006 if (curr
->detail
.kind
!= kind
6007 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
6009 /* If there are multiple errors, pick up the one with the highest
6010 mismatching operand index. In the case of multiple errors with
6011 the equally highest operand index, pick up the first one or the
6012 first one with non-NULL error message. */
6013 if (!record
|| curr
->detail
.index
> record
->detail
.index
)
6015 else if (curr
->detail
.index
== record
->detail
.index
6016 && !record
->detail
.error
)
6018 if (curr
->detail
.error
)
6020 else if (kind
== AARCH64_OPDE_SYNTAX_ERROR
)
6022 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6023 record
->detail
.data
[1].i
|= curr
->detail
.data
[1].i
;
6024 record
->detail
.data
[2].i
|= curr
->detail
.data
[2].i
;
6025 DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
6026 operand_mismatch_kind_names
[kind
],
6027 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
6028 curr
->detail
.data
[2].i
);
6030 else if (kind
== AARCH64_OPDE_REG_LIST_LENGTH
6031 || kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
6033 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6034 DEBUG_TRACE ("\t--> %s [%x]",
6035 operand_mismatch_kind_names
[kind
],
6036 curr
->detail
.data
[0].i
);
6038 /* Pick the variant with the cloest match. */
6039 else if (kind
== AARCH64_OPDE_INVALID_VARIANT
6040 && record
->detail
.data
[0].i
> curr
->detail
.data
[0].i
)
6045 /* The way errors are collected in the back-end is a bit non-intuitive. But
6046 essentially, because each operand template is tried recursively you may
6047 always have errors collected from the previous tried OPND. These are
6048 usually skipped if there is one successful match. However now with the
6049 non-fatal errors we have to ignore those previously collected hard errors
6050 when we're only interested in printing the non-fatal ones. This condition
6051 prevents us from printing errors that are not appropriate, since we did
6052 match a condition, but it also has warnings that it wants to print. */
6053 if (non_fatal_only
&& !record
)
6056 gas_assert (record
);
6057 DEBUG_TRACE ("Pick up error kind %s to report",
6058 operand_mismatch_kind_names
[kind
]);
6061 output_operand_error_record (record
, str
);
6064 /* Write an AARCH64 instruction to buf - always little-endian. */
6066 put_aarch64_insn (char *buf
, uint32_t insn
)
6068 unsigned char *where
= (unsigned char *) buf
;
6070 where
[1] = insn
>> 8;
6071 where
[2] = insn
>> 16;
6072 where
[3] = insn
>> 24;
6076 get_aarch64_insn (char *buf
)
6078 unsigned char *where
= (unsigned char *) buf
;
6080 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
6081 | ((uint32_t) where
[3] << 24)));
6086 output_inst (struct aarch64_inst
*new_inst
)
6090 to
= frag_more (INSN_SIZE
);
6092 frag_now
->tc_frag_data
.recorded
= 1;
6094 put_aarch64_insn (to
, inst
.base
.value
);
6096 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6098 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
6099 INSN_SIZE
, &inst
.reloc
.exp
,
6102 DEBUG_TRACE ("Prepared relocation fix up");
6103 /* Don't check the addend value against the instruction size,
6104 that's the job of our code in md_apply_fix(). */
6105 fixp
->fx_no_overflow
= 1;
6106 if (new_inst
!= NULL
)
6107 fixp
->tc_fix_data
.inst
= new_inst
;
6108 if (aarch64_gas_internal_fixup_p ())
6110 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
6111 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
6112 fixp
->fx_addnumber
= inst
.reloc
.flags
;
6116 dwarf2_emit_insn (INSN_SIZE
);
6119 /* Link together opcodes of the same name. */
6123 const aarch64_opcode
*opcode
;
6124 struct templates
*next
;
6127 typedef struct templates templates
;
6130 lookup_mnemonic (const char *start
, int len
)
6132 templates
*templ
= NULL
;
6134 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
6138 /* Subroutine of md_assemble, responsible for looking up the primary
6139 opcode from the mnemonic the user wrote. BASE points to the beginning
6140 of the mnemonic, DOT points to the first '.' within the mnemonic
6141 (if any) and END points to the end of the mnemonic. */
6144 opcode_lookup (char *base
, char *dot
, char *end
)
6146 const aarch64_cond
*cond
;
6153 inst
.cond
= COND_ALWAYS
;
6155 /* Handle a possible condition. */
6158 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
6161 inst
.cond
= cond
->value
;
6167 if (inst
.cond
== COND_ALWAYS
)
6169 /* Look for unaffixed mnemonic. */
6170 return lookup_mnemonic (base
, len
);
6174 /* append ".c" to mnemonic if conditional */
6175 memcpy (condname
, base
, len
);
6176 memcpy (condname
+ len
, ".c", 2);
6179 return lookup_mnemonic (base
, len
);
6185 /* Process an optional operand that is found omitted from the assembly line.
6186 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
6187 instruction's opcode entry while IDX is the index of this omitted operand.
6191 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6192 int idx
, aarch64_opnd_info
*operand
)
6194 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6195 gas_assert (optional_operand_p (opcode
, idx
));
6196 gas_assert (!operand
->present
);
6200 case AARCH64_OPND_Rd
:
6201 case AARCH64_OPND_Rn
:
6202 case AARCH64_OPND_Rm
:
6203 case AARCH64_OPND_Rt
:
6204 case AARCH64_OPND_Rt2
:
6205 case AARCH64_OPND_Rt_LS64
:
6206 case AARCH64_OPND_Rt_SP
:
6207 case AARCH64_OPND_Rs
:
6208 case AARCH64_OPND_Ra
:
6209 case AARCH64_OPND_Rt_SYS
:
6210 case AARCH64_OPND_Rd_SP
:
6211 case AARCH64_OPND_Rn_SP
:
6212 case AARCH64_OPND_Rm_SP
:
6213 case AARCH64_OPND_Fd
:
6214 case AARCH64_OPND_Fn
:
6215 case AARCH64_OPND_Fm
:
6216 case AARCH64_OPND_Fa
:
6217 case AARCH64_OPND_Ft
:
6218 case AARCH64_OPND_Ft2
:
6219 case AARCH64_OPND_Sd
:
6220 case AARCH64_OPND_Sn
:
6221 case AARCH64_OPND_Sm
:
6222 case AARCH64_OPND_Va
:
6223 case AARCH64_OPND_Vd
:
6224 case AARCH64_OPND_Vn
:
6225 case AARCH64_OPND_Vm
:
6226 case AARCH64_OPND_VdD1
:
6227 case AARCH64_OPND_VnD1
:
6228 operand
->reg
.regno
= default_value
;
6231 case AARCH64_OPND_Ed
:
6232 case AARCH64_OPND_En
:
6233 case AARCH64_OPND_Em
:
6234 case AARCH64_OPND_Em16
:
6235 case AARCH64_OPND_SM3_IMM2
:
6236 operand
->reglane
.regno
= default_value
;
6239 case AARCH64_OPND_IDX
:
6240 case AARCH64_OPND_BIT_NUM
:
6241 case AARCH64_OPND_IMMR
:
6242 case AARCH64_OPND_IMMS
:
6243 case AARCH64_OPND_SHLL_IMM
:
6244 case AARCH64_OPND_IMM_VLSL
:
6245 case AARCH64_OPND_IMM_VLSR
:
6246 case AARCH64_OPND_CCMP_IMM
:
6247 case AARCH64_OPND_FBITS
:
6248 case AARCH64_OPND_UIMM4
:
6249 case AARCH64_OPND_UIMM3_OP1
:
6250 case AARCH64_OPND_UIMM3_OP2
:
6251 case AARCH64_OPND_IMM
:
6252 case AARCH64_OPND_IMM_2
:
6253 case AARCH64_OPND_WIDTH
:
6254 case AARCH64_OPND_UIMM7
:
6255 case AARCH64_OPND_NZCV
:
6256 case AARCH64_OPND_SVE_PATTERN
:
6257 case AARCH64_OPND_SVE_PRFOP
:
6258 operand
->imm
.value
= default_value
;
6261 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6262 operand
->imm
.value
= default_value
;
6263 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6264 operand
->shifter
.amount
= 1;
6267 case AARCH64_OPND_EXCEPTION
:
6268 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6271 case AARCH64_OPND_BARRIER_ISB
:
6272 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6275 case AARCH64_OPND_BTI_TARGET
:
6276 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6284 /* Process the relocation type for move wide instructions.
6285 Return TRUE on success; otherwise return FALSE. */
6288 process_movw_reloc_info (void)
6293 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6295 if (inst
.base
.opcode
->op
== OP_MOVK
)
6296 switch (inst
.reloc
.type
)
6298 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6299 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6300 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6301 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6302 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6303 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6304 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6305 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6306 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6307 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6308 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6310 (_("the specified relocation type is not allowed for MOVK"));
6316 switch (inst
.reloc
.type
)
6318 case BFD_RELOC_AARCH64_MOVW_G0
:
6319 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6320 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6321 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6322 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6323 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6324 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6325 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6326 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6327 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6328 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6329 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6330 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6333 case BFD_RELOC_AARCH64_MOVW_G1
:
6334 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6335 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6336 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6337 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6338 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6339 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6340 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6341 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6342 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6343 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6344 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6345 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6348 case BFD_RELOC_AARCH64_MOVW_G2
:
6349 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6350 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6351 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6352 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6353 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6354 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6357 set_fatal_syntax_error
6358 (_("the specified relocation type is not allowed for 32-bit "
6364 case BFD_RELOC_AARCH64_MOVW_G3
:
6365 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6368 set_fatal_syntax_error
6369 (_("the specified relocation type is not allowed for 32-bit "
6376 /* More cases should be added when more MOVW-related relocation types
6377 are supported in GAS. */
6378 gas_assert (aarch64_gas_internal_fixup_p ());
6379 /* The shift amount should have already been set by the parser. */
6382 inst
.base
.operands
[1].shifter
.amount
= shift
;
6386 /* Determine and return the real reloc type code for an instruction
6387 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6389 static inline bfd_reloc_code_real_type
6390 ldst_lo12_determine_real_reloc_type (void)
6392 unsigned logsz
, max_logsz
;
6393 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6394 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6396 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6398 BFD_RELOC_AARCH64_LDST8_LO12
,
6399 BFD_RELOC_AARCH64_LDST16_LO12
,
6400 BFD_RELOC_AARCH64_LDST32_LO12
,
6401 BFD_RELOC_AARCH64_LDST64_LO12
,
6402 BFD_RELOC_AARCH64_LDST128_LO12
6405 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6406 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6407 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6408 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6409 BFD_RELOC_AARCH64_NONE
6412 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6413 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6414 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6415 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6416 BFD_RELOC_AARCH64_NONE
6419 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6420 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6421 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6422 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6423 BFD_RELOC_AARCH64_NONE
6426 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6427 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6428 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6429 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6430 BFD_RELOC_AARCH64_NONE
6434 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6435 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6437 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6439 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6441 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6442 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6444 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6446 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6448 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6450 logsz
= get_log2 (aarch64_get_qualifier_esize (opd1_qlf
));
6452 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6453 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6454 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6455 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6460 if (logsz
> max_logsz
)
6462 /* SEE PR 27904 for an example of this. */
6463 set_fatal_syntax_error
6464 (_("relocation qualifier does not match instruction size"));
6465 return BFD_RELOC_AARCH64_NONE
;
6468 /* In reloc.c, these pseudo relocation types should be defined in similar
6469 order as above reloc_ldst_lo12 array. Because the array index calculation
6470 below relies on this. */
6471 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6474 /* Check whether a register list REGINFO is valid. The registers have type
6475 REG_TYPE and must be numbered in increasing order (modulo the register
6476 bank size). They must have a consistent stride.
6478 Return true if the list is valid, describing it in LIST if so. */
6481 reg_list_valid_p (uint32_t reginfo
, struct aarch64_reglist
*list
,
6482 aarch64_reg_type reg_type
)
6484 uint32_t i
, nb_regs
, prev_regno
, incr
, mask
;
6485 mask
= reg_type_mask (reg_type
);
6487 nb_regs
= 1 + (reginfo
& 0x3);
6489 prev_regno
= reginfo
& 0x1f;
6492 list
->first_regno
= prev_regno
;
6493 list
->num_regs
= nb_regs
;
6495 for (i
= 1; i
< nb_regs
; ++i
)
6497 uint32_t curr_regno
, curr_incr
;
6499 curr_regno
= reginfo
& 0x1f;
6500 curr_incr
= (curr_regno
- prev_regno
) & mask
;
6505 else if (curr_incr
!= incr
)
6507 prev_regno
= curr_regno
;
6510 list
->stride
= incr
;
6514 /* Generic instruction operand parser. This does no encoding and no
6515 semantic validation; it merely squirrels values away in the inst
6516 structure. Returns TRUE or FALSE depending on whether the
6517 specified grammar matched. */
6520 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6523 char *backtrack_pos
= 0;
6524 const enum aarch64_opnd
*operands
= opcode
->operands
;
6525 aarch64_reg_type imm_reg_type
;
6528 skip_whitespace (str
);
6530 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6532 | AARCH64_FEATURE_SVE2
))
6533 imm_reg_type
= REG_TYPE_R_ZR_SP_BHSDQ_VZP
;
6535 imm_reg_type
= REG_TYPE_R_ZR_BHSDQ_V
;
6537 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6540 const reg_entry
*reg
;
6541 int comma_skipped_p
= 0;
6542 struct vector_type_el vectype
;
6543 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6544 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6545 aarch64_reg_type reg_type
;
6547 DEBUG_TRACE ("parse operand %d", i
);
6549 /* Assign the operand code. */
6550 info
->type
= operands
[i
];
6552 if (optional_operand_p (opcode
, i
))
6554 /* Remember where we are in case we need to backtrack. */
6555 gas_assert (!backtrack_pos
);
6556 backtrack_pos
= str
;
6559 /* Expect comma between operands; the backtrack mechanism will take
6560 care of cases of omitted optional operand. */
6561 if (i
> 0 && ! skip_past_char (&str
, ','))
6563 set_syntax_error (_("comma expected between operands"));
6567 comma_skipped_p
= 1;
6569 switch (operands
[i
])
6571 case AARCH64_OPND_Rd
:
6572 case AARCH64_OPND_Rn
:
6573 case AARCH64_OPND_Rm
:
6574 case AARCH64_OPND_Rt
:
6575 case AARCH64_OPND_Rt2
:
6576 case AARCH64_OPND_Rs
:
6577 case AARCH64_OPND_Ra
:
6578 case AARCH64_OPND_Rt_LS64
:
6579 case AARCH64_OPND_Rt_SYS
:
6580 case AARCH64_OPND_PAIRREG
:
6581 case AARCH64_OPND_SVE_Rm
:
6582 po_int_fp_reg_or_fail (REG_TYPE_R_ZR
);
6584 /* In LS64 load/store instructions Rt register number must be even
6586 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6588 /* We've already checked if this is valid register.
6589 This will check if register number (Rt) is not undefined for LS64
6591 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6592 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6594 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6600 case AARCH64_OPND_Rd_SP
:
6601 case AARCH64_OPND_Rn_SP
:
6602 case AARCH64_OPND_Rt_SP
:
6603 case AARCH64_OPND_SVE_Rn_SP
:
6604 case AARCH64_OPND_Rm_SP
:
6605 po_int_fp_reg_or_fail (REG_TYPE_R_SP
);
6608 case AARCH64_OPND_Rm_EXT
:
6609 case AARCH64_OPND_Rm_SFT
:
6610 po_misc_or_fail (parse_shifter_operand
6611 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6613 : SHIFTED_LOGIC_IMM
)));
6614 if (!info
->shifter
.operator_present
)
6616 /* Default to LSL if not present. Libopcodes prefers shifter
6617 kind to be explicit. */
6618 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6619 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6620 /* For Rm_EXT, libopcodes will carry out further check on whether
6621 or not stack pointer is used in the instruction (Recall that
6622 "the extend operator is not optional unless at least one of
6623 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6627 case AARCH64_OPND_Fd
:
6628 case AARCH64_OPND_Fn
:
6629 case AARCH64_OPND_Fm
:
6630 case AARCH64_OPND_Fa
:
6631 case AARCH64_OPND_Ft
:
6632 case AARCH64_OPND_Ft2
:
6633 case AARCH64_OPND_Sd
:
6634 case AARCH64_OPND_Sn
:
6635 case AARCH64_OPND_Sm
:
6636 case AARCH64_OPND_SVE_VZn
:
6637 case AARCH64_OPND_SVE_Vd
:
6638 case AARCH64_OPND_SVE_Vm
:
6639 case AARCH64_OPND_SVE_Vn
:
6640 po_int_fp_reg_or_fail (REG_TYPE_BHSDQ
);
6643 case AARCH64_OPND_SVE_Pd
:
6644 case AARCH64_OPND_SVE_Pg3
:
6645 case AARCH64_OPND_SVE_Pg4_5
:
6646 case AARCH64_OPND_SVE_Pg4_10
:
6647 case AARCH64_OPND_SVE_Pg4_16
:
6648 case AARCH64_OPND_SVE_Pm
:
6649 case AARCH64_OPND_SVE_Pn
:
6650 case AARCH64_OPND_SVE_Pt
:
6651 case AARCH64_OPND_SME_Pm
:
6652 reg_type
= REG_TYPE_P
;
6655 case AARCH64_OPND_SVE_Za_5
:
6656 case AARCH64_OPND_SVE_Za_16
:
6657 case AARCH64_OPND_SVE_Zd
:
6658 case AARCH64_OPND_SVE_Zm_5
:
6659 case AARCH64_OPND_SVE_Zm_16
:
6660 case AARCH64_OPND_SVE_Zn
:
6661 case AARCH64_OPND_SVE_Zt
:
6662 case AARCH64_OPND_SME_Zm
:
6663 reg_type
= REG_TYPE_Z
;
6666 case AARCH64_OPND_SVE_PNd
:
6667 case AARCH64_OPND_SVE_PNg4_10
:
6668 case AARCH64_OPND_SVE_PNn
:
6669 case AARCH64_OPND_SVE_PNt
:
6670 case AARCH64_OPND_SME_PNd3
:
6671 case AARCH64_OPND_SME_PNg3
:
6672 case AARCH64_OPND_SME_PNn
:
6673 reg_type
= REG_TYPE_PN
;
6676 case AARCH64_OPND_Va
:
6677 case AARCH64_OPND_Vd
:
6678 case AARCH64_OPND_Vn
:
6679 case AARCH64_OPND_Vm
:
6680 reg_type
= REG_TYPE_V
;
6682 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6685 if (vectype
.defined
& NTA_HASINDEX
)
6688 info
->reg
.regno
= reg
->number
;
6689 if ((reg_type
== REG_TYPE_P
6690 || reg_type
== REG_TYPE_PN
6691 || reg_type
== REG_TYPE_Z
)
6692 && vectype
.type
== NT_invtype
)
6693 /* Unqualified P and Z registers are allowed in certain
6694 contexts. Rely on F_STRICT qualifier checking to catch
6696 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6699 info
->qualifier
= vectype_to_qualifier (&vectype
);
6700 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6705 case AARCH64_OPND_VdD1
:
6706 case AARCH64_OPND_VnD1
:
6707 reg
= aarch64_reg_parse (&str
, REG_TYPE_V
, &vectype
);
6710 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6712 set_fatal_syntax_error
6713 (_("the top half of a 128-bit FP/SIMD register is expected"));
6716 info
->reg
.regno
= reg
->number
;
6717 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6718 here; it is correct for the purpose of encoding/decoding since
6719 only the register number is explicitly encoded in the related
6720 instructions, although this appears a bit hacky. */
6721 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6724 case AARCH64_OPND_SVE_Zm3_INDEX
:
6725 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6726 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6727 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6728 case AARCH64_OPND_SVE_Zm4_INDEX
:
6729 case AARCH64_OPND_SVE_Zn_INDEX
:
6730 case AARCH64_OPND_SME_Zm_INDEX1
:
6731 case AARCH64_OPND_SME_Zm_INDEX2
:
6732 case AARCH64_OPND_SME_Zn_INDEX1_16
:
6733 case AARCH64_OPND_SME_Zn_INDEX2_15
:
6734 case AARCH64_OPND_SME_Zn_INDEX2_16
:
6735 case AARCH64_OPND_SME_Zn_INDEX3_14
:
6736 case AARCH64_OPND_SME_Zn_INDEX3_15
:
6737 case AARCH64_OPND_SME_Zn_INDEX4_14
:
6738 reg_type
= REG_TYPE_Z
;
6739 goto vector_reg_index
;
6741 case AARCH64_OPND_Ed
:
6742 case AARCH64_OPND_En
:
6743 case AARCH64_OPND_Em
:
6744 case AARCH64_OPND_Em16
:
6745 case AARCH64_OPND_SM3_IMM2
:
6746 reg_type
= REG_TYPE_V
;
6748 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6751 if (!(vectype
.defined
& NTA_HASINDEX
))
6754 if (reg
->type
== REG_TYPE_Z
&& vectype
.type
== NT_invtype
)
6755 /* Unqualified Zn[index] is allowed in LUTI2 instructions. */
6756 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6759 if (vectype
.type
== NT_invtype
)
6761 info
->qualifier
= vectype_to_qualifier (&vectype
);
6762 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6766 info
->reglane
.regno
= reg
->number
;
6767 info
->reglane
.index
= vectype
.index
;
6770 case AARCH64_OPND_SVE_ZnxN
:
6771 case AARCH64_OPND_SVE_ZtxN
:
6772 case AARCH64_OPND_SME_Zdnx2
:
6773 case AARCH64_OPND_SME_Zdnx4
:
6774 case AARCH64_OPND_SME_Zmx2
:
6775 case AARCH64_OPND_SME_Zmx4
:
6776 case AARCH64_OPND_SME_Znx2
:
6777 case AARCH64_OPND_SME_Znx4
:
6778 case AARCH64_OPND_SME_Ztx2_STRIDED
:
6779 case AARCH64_OPND_SME_Ztx4_STRIDED
:
6780 reg_type
= REG_TYPE_Z
;
6781 goto vector_reg_list
;
6783 case AARCH64_OPND_SME_Pdx2
:
6784 case AARCH64_OPND_SME_PdxN
:
6785 reg_type
= REG_TYPE_P
;
6786 goto vector_reg_list
;
6788 case AARCH64_OPND_LVn
:
6789 case AARCH64_OPND_LVt
:
6790 case AARCH64_OPND_LVt_AL
:
6791 case AARCH64_OPND_LEt
:
6792 reg_type
= REG_TYPE_V
;
6794 if (reg_type
== REG_TYPE_Z
6795 && get_opcode_dependent_value (opcode
) == 1
6798 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6801 info
->reglist
.first_regno
= reg
->number
;
6802 info
->reglist
.num_regs
= 1;
6803 info
->reglist
.stride
= 1;
6807 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6808 if (val
== PARSE_FAIL
)
6811 if (! reg_list_valid_p (val
, &info
->reglist
, reg_type
))
6813 set_fatal_syntax_error (_("invalid register list"));
6817 if ((int) vectype
.width
> 0 && *str
!= ',')
6819 set_fatal_syntax_error
6820 (_("expected element type rather than vector type"));
6824 if (operands
[i
] == AARCH64_OPND_LEt
)
6826 if (!(vectype
.defined
& NTA_HASINDEX
))
6828 info
->reglist
.has_index
= 1;
6829 info
->reglist
.index
= vectype
.index
;
6833 if (vectype
.defined
& NTA_HASINDEX
)
6835 if (!(vectype
.defined
& NTA_HASTYPE
))
6837 if (reg_type
== REG_TYPE_Z
|| reg_type
== REG_TYPE_P
)
6838 set_fatal_syntax_error (_("missing type suffix"));
6842 info
->qualifier
= vectype_to_qualifier (&vectype
);
6843 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6847 case AARCH64_OPND_CRn
:
6848 case AARCH64_OPND_CRm
:
6850 char prefix
= *(str
++);
6851 if (prefix
!= 'c' && prefix
!= 'C')
6854 po_imm_nc_or_fail ();
6857 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6860 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6861 info
->imm
.value
= val
;
6865 case AARCH64_OPND_SHLL_IMM
:
6866 case AARCH64_OPND_IMM_VLSR
:
6867 po_imm_or_fail (1, 64);
6868 info
->imm
.value
= val
;
6871 case AARCH64_OPND_CCMP_IMM
:
6872 case AARCH64_OPND_SIMM5
:
6873 case AARCH64_OPND_FBITS
:
6874 case AARCH64_OPND_TME_UIMM16
:
6875 case AARCH64_OPND_UIMM4
:
6876 case AARCH64_OPND_UIMM4_ADDG
:
6877 case AARCH64_OPND_UIMM10
:
6878 case AARCH64_OPND_UIMM3_OP1
:
6879 case AARCH64_OPND_UIMM3_OP2
:
6880 case AARCH64_OPND_IMM_VLSL
:
6881 case AARCH64_OPND_IMM
:
6882 case AARCH64_OPND_IMM_2
:
6883 case AARCH64_OPND_WIDTH
:
6884 case AARCH64_OPND_SVE_INV_LIMM
:
6885 case AARCH64_OPND_SVE_LIMM
:
6886 case AARCH64_OPND_SVE_LIMM_MOV
:
6887 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6888 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6889 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6890 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6891 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6892 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6893 case AARCH64_OPND_SVE_SIMM5
:
6894 case AARCH64_OPND_SVE_SIMM5B
:
6895 case AARCH64_OPND_SVE_SIMM6
:
6896 case AARCH64_OPND_SVE_SIMM8
:
6897 case AARCH64_OPND_SVE_UIMM3
:
6898 case AARCH64_OPND_SVE_UIMM7
:
6899 case AARCH64_OPND_SVE_UIMM8
:
6900 case AARCH64_OPND_SVE_UIMM8_53
:
6901 case AARCH64_OPND_IMM_ROT1
:
6902 case AARCH64_OPND_IMM_ROT2
:
6903 case AARCH64_OPND_IMM_ROT3
:
6904 case AARCH64_OPND_SVE_IMM_ROT1
:
6905 case AARCH64_OPND_SVE_IMM_ROT2
:
6906 case AARCH64_OPND_SVE_IMM_ROT3
:
6907 case AARCH64_OPND_CSSC_SIMM8
:
6908 case AARCH64_OPND_CSSC_UIMM8
:
6909 po_imm_nc_or_fail ();
6910 info
->imm
.value
= val
;
6913 case AARCH64_OPND_SVE_AIMM
:
6914 case AARCH64_OPND_SVE_ASIMM
:
6915 po_imm_nc_or_fail ();
6916 info
->imm
.value
= val
;
6917 skip_whitespace (str
);
6918 if (skip_past_comma (&str
))
6919 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6921 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6924 case AARCH64_OPND_SVE_PATTERN
:
6925 po_enum_or_fail (aarch64_sve_pattern_array
);
6926 info
->imm
.value
= val
;
6929 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6930 po_enum_or_fail (aarch64_sve_pattern_array
);
6931 info
->imm
.value
= val
;
6932 if (skip_past_comma (&str
)
6933 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6935 if (!info
->shifter
.operator_present
)
6937 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6938 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6939 info
->shifter
.amount
= 1;
6943 case AARCH64_OPND_SVE_PRFOP
:
6944 po_enum_or_fail (aarch64_sve_prfop_array
);
6945 info
->imm
.value
= val
;
6948 case AARCH64_OPND_UIMM7
:
6949 po_imm_or_fail (0, 127);
6950 info
->imm
.value
= val
;
6953 case AARCH64_OPND_IDX
:
6954 case AARCH64_OPND_MASK
:
6955 case AARCH64_OPND_BIT_NUM
:
6956 case AARCH64_OPND_IMMR
:
6957 case AARCH64_OPND_IMMS
:
6958 po_imm_or_fail (0, 63);
6959 info
->imm
.value
= val
;
6962 case AARCH64_OPND_IMM0
:
6963 po_imm_nc_or_fail ();
6966 set_fatal_syntax_error (_("immediate zero expected"));
6969 info
->imm
.value
= 0;
6972 case AARCH64_OPND_FPIMM0
:
6975 bool res1
= false, res2
= false;
6976 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6977 it is probably not worth the effort to support it. */
6978 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6981 || !(res2
= parse_constant_immediate (&str
, &val
,
6984 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6986 info
->imm
.value
= 0;
6987 info
->imm
.is_fp
= 1;
6990 set_fatal_syntax_error (_("immediate zero expected"));
6994 case AARCH64_OPND_IMM_MOV
:
6997 if (reg_name_p (str
, REG_TYPE_R_ZR_SP
)
6998 || reg_name_p (str
, REG_TYPE_V
))
7001 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
7002 GE_OPT_PREFIX
, REJECT_ABSENT
));
7003 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
7004 later. fix_mov_imm_insn will try to determine a machine
7005 instruction (MOVZ, MOVN or ORR) for it and will issue an error
7006 message if the immediate cannot be moved by a single
7008 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7009 inst
.base
.operands
[i
].skip
= 1;
7013 case AARCH64_OPND_SIMD_IMM
:
7014 case AARCH64_OPND_SIMD_IMM_SFT
:
7015 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
7017 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7019 /* need_libopcodes_p */ 1,
7022 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
7023 shift, we don't check it here; we leave the checking to
7024 the libopcodes (operand_general_constraint_met_p). By
7025 doing this, we achieve better diagnostics. */
7026 if (skip_past_comma (&str
)
7027 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
7029 if (!info
->shifter
.operator_present
7030 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
7032 /* Default to LSL if not present. Libopcodes prefers shifter
7033 kind to be explicit. */
7034 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7035 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7039 case AARCH64_OPND_FPIMM
:
7040 case AARCH64_OPND_SIMD_FPIMM
:
7041 case AARCH64_OPND_SVE_FPIMM8
:
7046 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7047 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
7048 || !aarch64_imm_float_p (qfloat
))
7051 set_fatal_syntax_error (_("invalid floating-point"
7055 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
7056 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7060 case AARCH64_OPND_SVE_I1_HALF_ONE
:
7061 case AARCH64_OPND_SVE_I1_HALF_TWO
:
7062 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
7067 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7068 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
7071 set_fatal_syntax_error (_("invalid floating-point"
7075 inst
.base
.operands
[i
].imm
.value
= qfloat
;
7076 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7080 case AARCH64_OPND_LIMM
:
7081 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7082 SHIFTED_LOGIC_IMM
));
7083 if (info
->shifter
.operator_present
)
7085 set_fatal_syntax_error
7086 (_("shift not allowed for bitmask immediate"));
7089 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7091 /* need_libopcodes_p */ 1,
7095 case AARCH64_OPND_AIMM
:
7096 if (opcode
->op
== OP_ADD
)
7097 /* ADD may have relocation types. */
7098 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
7099 SHIFTED_ARITH_IMM
));
7101 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7102 SHIFTED_ARITH_IMM
));
7103 switch (inst
.reloc
.type
)
7105 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7106 info
->shifter
.amount
= 12;
7108 case BFD_RELOC_UNUSED
:
7109 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7110 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
7111 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
7112 inst
.reloc
.pc_rel
= 0;
7117 info
->imm
.value
= 0;
7118 if (!info
->shifter
.operator_present
)
7120 /* Default to LSL if not present. Libopcodes prefers shifter
7121 kind to be explicit. */
7122 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7123 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7127 case AARCH64_OPND_HALF
:
7129 /* #<imm16> or relocation. */
7130 int internal_fixup_p
;
7131 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
7132 if (internal_fixup_p
)
7133 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7134 skip_whitespace (str
);
7135 if (skip_past_comma (&str
))
7137 /* {, LSL #<shift>} */
7138 if (! aarch64_gas_internal_fixup_p ())
7140 set_fatal_syntax_error (_("can't mix relocation modifier "
7141 "with explicit shift"));
7144 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
7147 inst
.base
.operands
[i
].shifter
.amount
= 0;
7148 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
7149 inst
.base
.operands
[i
].imm
.value
= 0;
7150 if (! process_movw_reloc_info ())
7155 case AARCH64_OPND_EXCEPTION
:
7156 case AARCH64_OPND_UNDEFINED
:
7157 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
7159 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7161 /* need_libopcodes_p */ 0,
7165 case AARCH64_OPND_NZCV
:
7167 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
7171 info
->imm
.value
= nzcv
->value
;
7174 po_imm_or_fail (0, 15);
7175 info
->imm
.value
= val
;
7179 case AARCH64_OPND_COND
:
7180 case AARCH64_OPND_COND1
:
7185 while (ISALPHA (*str
));
7186 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
7187 if (info
->cond
== NULL
)
7189 set_syntax_error (_("invalid condition"));
7192 else if (operands
[i
] == AARCH64_OPND_COND1
7193 && (info
->cond
->value
& 0xe) == 0xe)
7195 /* Do not allow AL or NV. */
7196 set_default_error ();
7202 case AARCH64_OPND_ADDR_ADRP
:
7203 po_misc_or_fail (parse_adrp (&str
));
7204 /* Clear the value as operand needs to be relocated. */
7205 info
->imm
.value
= 0;
7208 case AARCH64_OPND_ADDR_PCREL14
:
7209 case AARCH64_OPND_ADDR_PCREL19
:
7210 case AARCH64_OPND_ADDR_PCREL21
:
7211 case AARCH64_OPND_ADDR_PCREL26
:
7212 po_misc_or_fail (parse_address (&str
, info
));
7213 if (!info
->addr
.pcrel
)
7215 set_syntax_error (_("invalid pc-relative address"));
7218 if (inst
.gen_lit_pool
7219 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
7221 /* Only permit "=value" in the literal load instructions.
7222 The literal will be generated by programmer_friendly_fixup. */
7223 set_syntax_error (_("invalid use of \"=immediate\""));
7226 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7228 set_syntax_error (_("unrecognized relocation suffix"));
7231 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7233 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7234 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7238 info
->imm
.value
= 0;
7239 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7240 switch (opcode
->iclass
)
7244 /* e.g. CBZ or B.COND */
7245 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7246 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7250 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7251 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7255 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7257 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7258 : BFD_RELOC_AARCH64_JUMP26
;
7261 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7262 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7265 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7266 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7272 inst
.reloc
.pc_rel
= 1;
7276 case AARCH64_OPND_ADDR_SIMPLE
:
7277 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7279 /* [<Xn|SP>{, #<simm>}] */
7281 /* First use the normal address-parsing routines, to get
7282 the usual syntax errors. */
7283 po_misc_or_fail (parse_address (&str
, info
));
7284 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7285 || !info
->addr
.preind
|| info
->addr
.postind
7286 || info
->addr
.writeback
)
7288 set_syntax_error (_("invalid addressing mode"));
7292 /* Then retry, matching the specific syntax of these addresses. */
7294 po_char_or_fail ('[');
7295 po_reg_or_fail (REG_TYPE_R64_SP
);
7296 /* Accept optional ", #0". */
7297 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7298 && skip_past_char (&str
, ','))
7300 skip_past_char (&str
, '#');
7301 if (! skip_past_char (&str
, '0'))
7303 set_fatal_syntax_error
7304 (_("the optional immediate offset can only be 0"));
7308 po_char_or_fail (']');
7312 case AARCH64_OPND_ADDR_REGOFF
:
7313 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7314 po_misc_or_fail (parse_address (&str
, info
));
7316 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7317 || !info
->addr
.preind
|| info
->addr
.postind
7318 || info
->addr
.writeback
)
7320 set_syntax_error (_("invalid addressing mode"));
7323 if (!info
->shifter
.operator_present
)
7325 /* Default to LSL if not present. Libopcodes prefers shifter
7326 kind to be explicit. */
7327 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7328 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7330 /* Qualifier to be deduced by libopcodes. */
7333 case AARCH64_OPND_ADDR_SIMM7
:
7334 po_misc_or_fail (parse_address (&str
, info
));
7335 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7336 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7338 set_syntax_error (_("invalid addressing mode"));
7341 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7343 set_syntax_error (_("relocation not allowed"));
7346 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7348 /* need_libopcodes_p */ 1,
7352 case AARCH64_OPND_ADDR_SIMM9
:
7353 case AARCH64_OPND_ADDR_SIMM9_2
:
7354 case AARCH64_OPND_ADDR_SIMM11
:
7355 case AARCH64_OPND_ADDR_SIMM13
:
7356 po_misc_or_fail (parse_address (&str
, info
));
7357 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7358 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7359 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7360 && info
->addr
.writeback
))
7362 set_syntax_error (_("invalid addressing mode"));
7365 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7367 set_syntax_error (_("relocation not allowed"));
7370 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7372 /* need_libopcodes_p */ 1,
7376 case AARCH64_OPND_ADDR_SIMM10
:
7377 case AARCH64_OPND_ADDR_OFFSET
:
7378 po_misc_or_fail (parse_address (&str
, info
));
7379 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7380 || !info
->addr
.preind
|| info
->addr
.postind
)
7382 set_syntax_error (_("invalid addressing mode"));
7385 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7387 set_syntax_error (_("relocation not allowed"));
7390 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7392 /* need_libopcodes_p */ 1,
7396 case AARCH64_OPND_ADDR_UIMM12
:
7397 po_misc_or_fail (parse_address (&str
, info
));
7398 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7399 || !info
->addr
.preind
|| info
->addr
.writeback
)
7401 set_syntax_error (_("invalid addressing mode"));
7404 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7405 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7406 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7408 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7410 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7412 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7414 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7415 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7416 /* Leave qualifier to be determined by libopcodes. */
7419 case AARCH64_OPND_SIMD_ADDR_POST
:
7420 /* [<Xn|SP>], <Xm|#<amount>> */
7421 po_misc_or_fail (parse_address (&str
, info
));
7422 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7424 set_syntax_error (_("invalid addressing mode"));
7427 if (!info
->addr
.offset
.is_reg
)
7429 if (inst
.reloc
.exp
.X_op
== O_constant
)
7430 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7433 set_fatal_syntax_error
7434 (_("writeback value must be an immediate constant"));
7441 case AARCH64_OPND_SME_SM_ZA
:
7443 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7445 set_syntax_error (_("unknown or missing PSTATE field name"));
7448 info
->reg
.regno
= val
;
7451 case AARCH64_OPND_SME_PnT_Wm_imm
:
7452 if (!parse_dual_indexed_reg (&str
, REG_TYPE_P
,
7453 &info
->indexed_za
, &qualifier
, 0))
7455 info
->qualifier
= qualifier
;
7458 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7459 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7460 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7461 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7462 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7463 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7464 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7465 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7466 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7467 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7468 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7469 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7470 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7471 /* [X<n>{, #imm, MUL VL}]
7473 but recognizing SVE registers. */
7474 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7475 &offset_qualifier
));
7476 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7478 set_syntax_error (_("invalid addressing mode"));
7482 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7483 || !info
->addr
.preind
|| info
->addr
.writeback
)
7485 set_syntax_error (_("invalid addressing mode"));
7488 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7489 || inst
.reloc
.exp
.X_op
!= O_constant
)
7491 /* Make sure this has priority over
7492 "invalid addressing mode". */
7493 set_fatal_syntax_error (_("constant offset required"));
7496 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7499 case AARCH64_OPND_SVE_ADDR_R
:
7500 /* [<Xn|SP>{, <R><m>}]
7501 but recognizing SVE registers. */
7502 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7503 &offset_qualifier
));
7504 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7506 offset_qualifier
= AARCH64_OPND_QLF_X
;
7507 info
->addr
.offset
.is_reg
= 1;
7508 info
->addr
.offset
.regno
= 31;
7510 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7511 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7513 set_syntax_error (_("invalid addressing mode"));
7518 case AARCH64_OPND_SVE_ADDR_RR
:
7519 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7520 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7521 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7522 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7523 case AARCH64_OPND_SVE_ADDR_RX
:
7524 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7525 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7526 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7527 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7528 but recognizing SVE registers. */
7529 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7530 &offset_qualifier
));
7531 if (base_qualifier
!= AARCH64_OPND_QLF_X
7532 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7534 set_syntax_error (_("invalid addressing mode"));
7539 case AARCH64_OPND_SVE_ADDR_RZ
:
7540 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7541 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7542 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7543 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7544 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7545 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7546 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7547 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7548 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7549 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7550 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7551 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7552 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7553 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7554 &offset_qualifier
));
7555 if (base_qualifier
!= AARCH64_OPND_QLF_X
7556 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7557 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7559 set_syntax_error (_("invalid addressing mode"));
7562 info
->qualifier
= offset_qualifier
;
7565 case AARCH64_OPND_SVE_ADDR_ZX
:
7566 /* [Zn.<T>{, <Xm>}]. */
7567 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7568 &offset_qualifier
));
7570 base_qualifier either S_S or S_D
7571 offset_qualifier must be X
7573 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7574 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7575 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7577 set_syntax_error (_("invalid addressing mode"));
7580 info
->qualifier
= base_qualifier
;
7581 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7582 || !info
->addr
.preind
|| info
->addr
.writeback
7583 || info
->shifter
.operator_present
!= 0)
7585 set_syntax_error (_("invalid addressing mode"));
7588 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7592 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7593 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7594 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7595 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7596 /* [Z<n>.<T>{, #imm}] */
7597 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7598 &offset_qualifier
));
7599 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7600 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7602 set_syntax_error (_("invalid addressing mode"));
7605 info
->qualifier
= base_qualifier
;
7608 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7609 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7610 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7611 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7612 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7616 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7618 here since we get better error messages by leaving it to
7619 the qualifier checking routines. */
7620 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7621 &offset_qualifier
));
7622 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7623 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7624 || offset_qualifier
!= base_qualifier
)
7626 set_syntax_error (_("invalid addressing mode"));
7629 info
->qualifier
= base_qualifier
;
7632 case AARCH64_OPND_SYSREG
:
7634 uint32_t sysreg_flags
;
7635 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7636 &sysreg_flags
)) == PARSE_FAIL
)
7638 set_syntax_error (_("unknown or missing system register name"));
7641 inst
.base
.operands
[i
].sysreg
.value
= val
;
7642 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7646 case AARCH64_OPND_PSTATEFIELD
:
7648 uint32_t sysreg_flags
;
7649 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7650 &sysreg_flags
)) == PARSE_FAIL
)
7652 set_syntax_error (_("unknown or missing PSTATE field name"));
7655 inst
.base
.operands
[i
].pstatefield
= val
;
7656 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7660 case AARCH64_OPND_SYSREG_IC
:
7661 inst
.base
.operands
[i
].sysins_op
=
7662 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7665 case AARCH64_OPND_SYSREG_DC
:
7666 inst
.base
.operands
[i
].sysins_op
=
7667 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7670 case AARCH64_OPND_SYSREG_AT
:
7671 inst
.base
.operands
[i
].sysins_op
=
7672 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7675 case AARCH64_OPND_SYSREG_SR
:
7676 inst
.base
.operands
[i
].sysins_op
=
7677 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7680 case AARCH64_OPND_SYSREG_TLBI
:
7681 inst
.base
.operands
[i
].sysins_op
=
7682 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7684 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7686 set_fatal_syntax_error ( _("unknown or missing operation name"));
7691 case AARCH64_OPND_BARRIER
:
7692 case AARCH64_OPND_BARRIER_ISB
:
7693 val
= parse_barrier (&str
);
7694 if (val
!= PARSE_FAIL
7695 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7697 /* ISB only accepts options name 'sy'. */
7699 (_("the specified option is not accepted in ISB"));
7700 /* Turn off backtrack as this optional operand is present. */
7704 if (val
!= PARSE_FAIL
7705 && operands
[i
] == AARCH64_OPND_BARRIER
)
7707 /* Regular barriers accept options CRm (C0-C15).
7708 DSB nXS barrier variant accepts values > 15. */
7709 if (val
< 0 || val
> 15)
7711 set_syntax_error (_("the specified option is not accepted in DSB"));
7715 /* This is an extension to accept a 0..15 immediate. */
7716 if (val
== PARSE_FAIL
)
7717 po_imm_or_fail (0, 15);
7718 info
->barrier
= aarch64_barrier_options
+ val
;
7721 case AARCH64_OPND_BARRIER_DSB_NXS
:
7722 val
= parse_barrier (&str
);
7723 if (val
!= PARSE_FAIL
)
7725 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7726 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7728 set_syntax_error (_("the specified option is not accepted in DSB"));
7729 /* Turn off backtrack as this optional operand is present. */
7736 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7737 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7738 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7740 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7742 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7746 /* Option index is encoded as 2-bit value in val<3:2>. */
7747 val
= (val
>> 2) - 4;
7748 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7751 case AARCH64_OPND_PRFOP
:
7752 val
= parse_pldop (&str
);
7753 /* This is an extension to accept a 0..31 immediate. */
7754 if (val
== PARSE_FAIL
)
7755 po_imm_or_fail (0, 31);
7756 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7759 case AARCH64_OPND_BARRIER_PSB
:
7760 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7761 if (val
== PARSE_FAIL
)
7765 case AARCH64_OPND_SME_ZT0
:
7766 po_reg_or_fail (REG_TYPE_ZT0
);
7769 case AARCH64_OPND_SME_ZT0_INDEX
:
7770 reg
= aarch64_reg_parse (&str
, REG_TYPE_ZT0
, &vectype
);
7771 if (!reg
|| vectype
.type
!= NT_invtype
)
7773 if (!(vectype
.defined
& NTA_HASINDEX
))
7775 set_syntax_error (_("missing register index"));
7778 info
->imm
.value
= vectype
.index
;
7781 case AARCH64_OPND_SME_ZT0_LIST
:
7784 set_expected_reglist_error (REG_TYPE_ZT0
, parse_reg (&str
));
7788 if (!parse_typed_reg (&str
, REG_TYPE_ZT0
, &vectype
, PTR_IN_REGLIST
))
7792 set_syntax_error (_("expected '}' after ZT0"));
7798 case AARCH64_OPND_SME_PNn3_INDEX1
:
7799 case AARCH64_OPND_SME_PNn3_INDEX2
:
7800 reg
= aarch64_reg_parse (&str
, REG_TYPE_PN
, &vectype
);
7803 if (!(vectype
.defined
& NTA_HASINDEX
))
7805 set_syntax_error (_("missing register index"));
7808 info
->reglane
.regno
= reg
->number
;
7809 info
->reglane
.index
= vectype
.index
;
7810 if (vectype
.type
== NT_invtype
)
7811 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
7813 info
->qualifier
= vectype_to_qualifier (&vectype
);
7816 case AARCH64_OPND_BTI_TARGET
:
7817 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7818 if (val
== PARSE_FAIL
)
7822 case AARCH64_OPND_SME_ZAda_2b
:
7823 case AARCH64_OPND_SME_ZAda_3b
:
7824 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
, 0);
7827 info
->reg
.regno
= reg
->number
;
7828 info
->qualifier
= qualifier
;
7831 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7832 case AARCH64_OPND_SME_ZA_HV_idx_srcxN
:
7833 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7834 case AARCH64_OPND_SME_ZA_HV_idx_destxN
:
7835 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7836 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7837 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7840 : !parse_dual_indexed_reg (&str
, REG_TYPE_ZATHV
,
7841 &info
->indexed_za
, &qualifier
, 0))
7843 info
->qualifier
= qualifier
;
7846 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7847 val
= parse_sme_list_of_64bit_tiles (&str
);
7848 if (val
== PARSE_FAIL
)
7850 info
->imm
.value
= val
;
7853 case AARCH64_OPND_SME_ZA_array_off3_0
:
7854 case AARCH64_OPND_SME_ZA_array_off3_5
:
7855 case AARCH64_OPND_SME_ZA_array_off4
:
7856 if (!parse_dual_indexed_reg (&str
, REG_TYPE_ZA
,
7857 &info
->indexed_za
, &qualifier
, 0))
7859 info
->qualifier
= qualifier
;
7862 case AARCH64_OPND_SME_VLxN_10
:
7863 case AARCH64_OPND_SME_VLxN_13
:
7864 po_strict_enum_or_fail (aarch64_sme_vlxn_array
);
7865 info
->imm
.value
= val
;
7868 case AARCH64_OPND_MOPS_ADDR_Rd
:
7869 case AARCH64_OPND_MOPS_ADDR_Rs
:
7870 po_char_or_fail ('[');
7871 if (!parse_x0_to_x30 (&str
, info
))
7873 po_char_or_fail (']');
7874 po_char_or_fail ('!');
7877 case AARCH64_OPND_MOPS_WB_Rn
:
7878 if (!parse_x0_to_x30 (&str
, info
))
7880 po_char_or_fail ('!');
7884 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7887 /* If we get here, this operand was successfully parsed. */
7888 inst
.base
.operands
[i
].present
= 1;
7892 /* The parse routine should already have set the error, but in case
7893 not, set a default one here. */
7895 set_default_error ();
7897 if (! backtrack_pos
)
7898 goto parse_operands_return
;
7901 /* We reach here because this operand is marked as optional, and
7902 either no operand was supplied or the operand was supplied but it
7903 was syntactically incorrect. In the latter case we report an
7904 error. In the former case we perform a few more checks before
7905 dropping through to the code to insert the default operand. */
7907 char *tmp
= backtrack_pos
;
7908 char endchar
= END_OF_INSN
;
7910 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7912 skip_past_char (&tmp
, ',');
7914 if (*tmp
!= endchar
)
7915 /* The user has supplied an operand in the wrong format. */
7916 goto parse_operands_return
;
7918 /* Make sure there is not a comma before the optional operand.
7919 For example the fifth operand of 'sys' is optional:
7921 sys #0,c0,c0,#0, <--- wrong
7922 sys #0,c0,c0,#0 <--- correct. */
7923 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7925 set_fatal_syntax_error
7926 (_("unexpected comma before the omitted optional operand"));
7927 goto parse_operands_return
;
7931 /* Reaching here means we are dealing with an optional operand that is
7932 omitted from the assembly line. */
7933 gas_assert (optional_operand_p (opcode
, i
));
7935 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7937 /* Try again, skipping the optional operand at backtrack_pos. */
7938 str
= backtrack_pos
;
7941 /* Clear any error record after the omitted optional operand has been
7942 successfully handled. */
7946 /* Check if we have parsed all the operands. */
7947 if (*str
!= '\0' && ! error_p ())
7949 /* Set I to the index of the last present operand; this is
7950 for the purpose of diagnostics. */
7951 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7953 set_fatal_syntax_error
7954 (_("unexpected characters following instruction"));
7957 parse_operands_return
:
7961 inst
.parsing_error
.index
= i
;
7962 DEBUG_TRACE ("parsing FAIL: %s - %s",
7963 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7964 inst
.parsing_error
.error
);
7965 /* Record the operand error properly; this is useful when there
7966 are multiple instruction templates for a mnemonic name, so that
7967 later on, we can select the error that most closely describes
7969 record_operand_error_info (opcode
, &inst
.parsing_error
);
7974 DEBUG_TRACE ("parsing SUCCESS");
7979 /* It does some fix-up to provide some programmer friendly feature while
7980 keeping the libopcodes happy, i.e. libopcodes only accepts
7981 the preferred architectural syntax.
7982 Return FALSE if there is any failure; otherwise return TRUE. */
7985 programmer_friendly_fixup (aarch64_instruction
*instr
)
7987 aarch64_inst
*base
= &instr
->base
;
7988 const aarch64_opcode
*opcode
= base
->opcode
;
7989 enum aarch64_op op
= opcode
->op
;
7990 aarch64_opnd_info
*operands
= base
->operands
;
7992 DEBUG_TRACE ("enter");
7994 switch (opcode
->iclass
)
7997 /* TBNZ Xn|Wn, #uimm6, label
7998 Test and Branch Not Zero: conditionally jumps to label if bit number
7999 uimm6 in register Xn is not zero. The bit number implies the width of
8000 the register, which may be written and should be disassembled as Wn if
8001 uimm is less than 32. */
8002 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
8004 if (operands
[1].imm
.value
>= 32)
8006 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
8010 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
8014 /* LDR Wt, label | =value
8015 As a convenience assemblers will typically permit the notation
8016 "=value" in conjunction with the pc-relative literal load instructions
8017 to automatically place an immediate value or symbolic address in a
8018 nearby literal pool and generate a hidden label which references it.
8019 ISREG has been set to 0 in the case of =value. */
8020 if (instr
->gen_lit_pool
8021 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
8023 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
8024 if (op
== OP_LDRSW_LIT
)
8026 if (instr
->reloc
.exp
.X_op
!= O_constant
8027 && instr
->reloc
.exp
.X_op
!= O_big
8028 && instr
->reloc
.exp
.X_op
!= O_symbol
)
8030 record_operand_error (opcode
, 1,
8031 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
8032 _("constant expression expected"));
8035 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
8037 record_operand_error (opcode
, 1,
8038 AARCH64_OPDE_OTHER_ERROR
,
8039 _("literal pool insertion failed"));
8047 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
8048 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
8049 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
8050 A programmer-friendly assembler should accept a destination Xd in
8051 place of Wd, however that is not the preferred form for disassembly.
8053 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
8054 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
8055 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
8056 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
8061 /* In the 64-bit form, the final register operand is written as Wm
8062 for all but the (possibly omitted) UXTX/LSL and SXTX
8064 As a programmer-friendly assembler, we accept e.g.
8065 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
8066 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
8067 int idx
= aarch64_operand_index (opcode
->operands
,
8068 AARCH64_OPND_Rm_EXT
);
8069 gas_assert (idx
== 1 || idx
== 2);
8070 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
8071 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
8072 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
8073 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
8074 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
8075 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
8083 DEBUG_TRACE ("exit with SUCCESS");
8087 /* Check for loads and stores that will cause unpredictable behavior. */
8090 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
8092 aarch64_inst
*base
= &instr
->base
;
8093 const aarch64_opcode
*opcode
= base
->opcode
;
8094 const aarch64_opnd_info
*opnds
= base
->operands
;
8095 switch (opcode
->iclass
)
8102 /* Loading/storing the base register is unpredictable if writeback. */
8103 if ((aarch64_get_operand_class (opnds
[0].type
)
8104 == AARCH64_OPND_CLASS_INT_REG
)
8105 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
8106 && opnds
[1].addr
.base_regno
!= REG_SP
8107 /* Exempt STG/STZG/ST2G/STZ2G. */
8108 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
8109 && opnds
[1].addr
.writeback
)
8110 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8114 case ldstnapair_offs
:
8115 case ldstpair_indexed
:
8116 /* Loading/storing the base register is unpredictable if writeback. */
8117 if ((aarch64_get_operand_class (opnds
[0].type
)
8118 == AARCH64_OPND_CLASS_INT_REG
)
8119 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
8120 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
8121 && opnds
[2].addr
.base_regno
!= REG_SP
8123 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
8124 && opnds
[2].addr
.writeback
)
8125 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8126 /* Load operations must load different registers. */
8127 if ((opcode
->opcode
& (1 << 22))
8128 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8129 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8133 if ((aarch64_get_operand_class (opnds
[0].type
)
8134 == AARCH64_OPND_CLASS_INT_REG
)
8135 && (aarch64_get_operand_class (opnds
[1].type
)
8136 == AARCH64_OPND_CLASS_INT_REG
))
8138 if ((opcode
->opcode
& (1 << 22)))
8140 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
8141 if ((opcode
->opcode
& (1 << 21))
8142 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8143 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8147 /* Store-Exclusive is unpredictable if Rt == Rs. */
8148 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8150 (_("unpredictable: identical transfer and status registers"
8153 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
8155 if (!(opcode
->opcode
& (1 << 21)))
8156 /* Store-Exclusive is unpredictable if Rn == Rs. */
8158 (_("unpredictable: identical base and status registers"
8161 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
8163 (_("unpredictable: "
8164 "identical transfer and status registers"
8168 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
8169 if ((opcode
->opcode
& (1 << 21))
8170 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
8171 && opnds
[3].reg
.regno
!= REG_SP
)
8172 as_warn (_("unpredictable: identical base and status registers"
8184 force_automatic_sequence_close (void)
8186 struct aarch64_segment_info_type
*tc_seg_info
;
8188 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8189 if (tc_seg_info
->insn_sequence
.instr
)
8191 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
8192 _("previous `%s' sequence has not been closed"),
8193 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
8194 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
8198 /* A wrapper function to interface with libopcodes on encoding and
8199 record the error message if there is any.
8201 Return TRUE on success; otherwise return FALSE. */
8204 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
8207 aarch64_operand_error error_info
;
8208 memset (&error_info
, '\0', sizeof (error_info
));
8209 error_info
.kind
= AARCH64_OPDE_NIL
;
8210 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
8211 && !error_info
.non_fatal
)
8214 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
8215 record_operand_error_info (opcode
, &error_info
);
8216 return error_info
.non_fatal
;
8219 #ifdef DEBUG_AARCH64
8221 dump_opcode_operands (const aarch64_opcode
*opcode
)
8224 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
8226 aarch64_verbose ("\t\t opnd%d: %s", i
,
8227 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
8228 ? aarch64_get_operand_name (opcode
->operands
[i
])
8229 : aarch64_get_operand_desc (opcode
->operands
[i
]));
8233 #endif /* DEBUG_AARCH64 */
8235 /* This is the guts of the machine-dependent assembler. STR points to a
8236 machine dependent instruction. This function is supposed to emit
8237 the frags/bytes it assembles to. */
8240 md_assemble (char *str
)
8242 templates
*template;
8243 const aarch64_opcode
*opcode
;
8244 struct aarch64_segment_info_type
*tc_seg_info
;
8245 aarch64_inst
*inst_base
;
8246 unsigned saved_cond
;
8248 /* Align the previous label if needed. */
8249 if (last_label_seen
!= NULL
)
8251 symbol_set_frag (last_label_seen
, frag_now
);
8252 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8253 S_SET_SEGMENT (last_label_seen
, now_seg
);
8256 /* Update the current insn_sequence from the segment. */
8257 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8258 insn_sequence
= &tc_seg_info
->insn_sequence
;
8259 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8261 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8263 DEBUG_TRACE ("\n\n");
8264 DEBUG_TRACE ("==============================");
8265 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8267 /* Scan up to the end of the mnemonic, which must end in whitespace,
8268 '.', or end of string. */
8271 for (; is_part_of_name (*p
); p
++)
8272 if (*p
== '.' && !dot
)
8277 as_bad (_("unknown mnemonic -- `%s'"), str
);
8281 if (!dot
&& create_register_alias (str
, p
))
8284 template = opcode_lookup (str
, dot
, p
);
8287 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8292 skip_whitespace (p
);
8295 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8296 get_mnemonic_name (str
), str
);
8300 init_operand_error_report ();
8302 /* Sections are assumed to start aligned. In executable section, there is no
8303 MAP_DATA symbol pending. So we only align the address during
8304 MAP_DATA --> MAP_INSN transition.
8305 For other sections, this is not guaranteed. */
8306 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8307 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8308 frag_align_code (2, 0);
8310 saved_cond
= inst
.cond
;
8311 reset_aarch64_instruction (&inst
);
8312 inst
.cond
= saved_cond
;
8314 /* Iterate through all opcode entries with the same mnemonic name. */
8317 opcode
= template->opcode
;
8319 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8320 #ifdef DEBUG_AARCH64
8322 dump_opcode_operands (opcode
);
8323 #endif /* DEBUG_AARCH64 */
8325 mapping_state (MAP_INSN
);
8327 inst_base
= &inst
.base
;
8328 inst_base
->opcode
= opcode
;
8330 /* Truly conditionally executed instructions, e.g. b.cond. */
8331 if (opcode
->flags
& F_COND
)
8333 gas_assert (inst
.cond
!= COND_ALWAYS
);
8334 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8335 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8337 else if (inst
.cond
!= COND_ALWAYS
)
8339 /* It shouldn't arrive here, where the assembly looks like a
8340 conditional instruction but the found opcode is unconditional. */
8345 if (parse_operands (p
, opcode
)
8346 && programmer_friendly_fixup (&inst
)
8347 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8349 /* Check that this instruction is supported for this CPU. */
8350 if (!aarch64_cpu_supports_inst_p (cpu_variant
, inst_base
))
8352 as_bad (_("selected processor does not support `%s'"), str
);
8356 warn_unpredictable_ldst (&inst
, str
);
8358 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8359 || !inst
.reloc
.need_libopcodes_p
)
8363 /* If there is relocation generated for the instruction,
8364 store the instruction information for the future fix-up. */
8365 struct aarch64_inst
*copy
;
8366 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8367 copy
= XNEW (struct aarch64_inst
);
8368 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8372 /* Issue non-fatal messages if any. */
8373 output_operand_error_report (str
, true);
8377 template = template->next
;
8378 if (template != NULL
)
8380 reset_aarch64_instruction (&inst
);
8381 inst
.cond
= saved_cond
;
8384 while (template != NULL
);
8386 /* Issue the error messages if any. */
8387 output_operand_error_report (str
, false);
8390 /* Various frobbings of labels and their addresses. */
8393 aarch64_start_line_hook (void)
8395 last_label_seen
= NULL
;
8399 aarch64_frob_label (symbolS
* sym
)
8401 last_label_seen
= sym
;
8403 dwarf2_emit_label (sym
);
8407 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8409 /* Check to see if we have a block to close. */
8410 force_automatic_sequence_close ();
8414 aarch64_data_in_code (void)
8416 if (startswith (input_line_pointer
+ 1, "data:"))
8418 *input_line_pointer
= '/';
8419 input_line_pointer
+= 5;
8420 *input_line_pointer
= 0;
8428 aarch64_canonicalize_symbol_name (char *name
)
8432 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8433 *(name
+ len
- 5) = 0;
8438 /* Table of all register names defined by default. The user can
8439 define additional names with .req. Note that all register names
8440 should appear in both upper and lowercase variants. Some registers
8441 also have mixed-case names. */
8443 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8444 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8445 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8446 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8447 #define REGSET16(p,t) \
8448 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8449 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8450 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8451 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8452 #define REGSET16S(p,s,t) \
8453 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8454 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8455 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8456 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8457 #define REGSET31(p,t) \
8459 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8460 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8461 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8462 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8463 #define REGSET(p,t) \
8464 REGSET31(p,t), REGNUM(p,31,t)
8466 /* These go into aarch64_reg_hsh hash-table. */
8467 static const reg_entry reg_names
[] = {
8468 /* Integer registers. */
8469 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8470 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8472 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8473 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8474 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8475 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8476 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8477 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8479 REGDEF (wzr
, 31, ZR_32
), REGDEF (WZR
, 31, ZR_32
),
8480 REGDEF (xzr
, 31, ZR_64
), REGDEF (XZR
, 31, ZR_64
),
8482 /* Floating-point single precision registers. */
8483 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8485 /* Floating-point double precision registers. */
8486 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8488 /* Floating-point half precision registers. */
8489 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8491 /* Floating-point byte precision registers. */
8492 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8494 /* Floating-point quad precision registers. */
8495 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8497 /* FP/SIMD registers. */
8498 REGSET (v
, V
), REGSET (V
, V
),
8500 /* SVE vector registers. */
8501 REGSET (z
, Z
), REGSET (Z
, Z
),
8503 /* SVE predicate(-as-mask) registers. */
8504 REGSET16 (p
, P
), REGSET16 (P
, P
),
8506 /* SVE predicate-as-counter registers. */
8507 REGSET16 (pn
, PN
), REGSET16 (PN
, PN
),
8509 /* SME ZA. We model this as a register because it acts syntactically
8510 like ZA0H, supporting qualifier suffixes and indexing. */
8511 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8513 /* SME ZA tile registers. */
8514 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8516 /* SME ZA tile registers (horizontal slice). */
8517 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8519 /* SME ZA tile registers (vertical slice). */
8520 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
),
8523 REGDEF (zt0
, 0, ZT0
), REGDEF (ZT0
, 0, ZT0
)
8541 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8542 static const asm_nzcv nzcv_names
[] = {
8543 {"nzcv", B (n
, z
, c
, v
)},
8544 {"nzcV", B (n
, z
, c
, V
)},
8545 {"nzCv", B (n
, z
, C
, v
)},
8546 {"nzCV", B (n
, z
, C
, V
)},
8547 {"nZcv", B (n
, Z
, c
, v
)},
8548 {"nZcV", B (n
, Z
, c
, V
)},
8549 {"nZCv", B (n
, Z
, C
, v
)},
8550 {"nZCV", B (n
, Z
, C
, V
)},
8551 {"Nzcv", B (N
, z
, c
, v
)},
8552 {"NzcV", B (N
, z
, c
, V
)},
8553 {"NzCv", B (N
, z
, C
, v
)},
8554 {"NzCV", B (N
, z
, C
, V
)},
8555 {"NZcv", B (N
, Z
, c
, v
)},
8556 {"NZcV", B (N
, Z
, c
, V
)},
8557 {"NZCv", B (N
, Z
, C
, v
)},
8558 {"NZCV", B (N
, Z
, C
, V
)}
8571 /* MD interface: bits in the object file. */
8573 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8574 for use in the a.out file, and stores them in the array pointed to by buf.
8575 This knows about the endian-ness of the target machine and does
8576 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8577 2 (short) and 4 (long) Floating numbers are put out as a series of
8578 LITTLENUMS (shorts, here at least). */
8581 md_number_to_chars (char *buf
, valueT val
, int n
)
8583 if (target_big_endian
)
8584 number_to_chars_bigendian (buf
, val
, n
);
8586 number_to_chars_littleendian (buf
, val
, n
);
8589 /* MD interface: Sections. */
8591 /* Estimate the size of a frag before relaxing. Assume everything fits in
8595 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8601 /* Round up a section size to the appropriate boundary. */
8604 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8609 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8610 of an rs_align_code fragment.
8612 Here we fill the frag with the appropriate info for padding the
8613 output stream. The resulting frag will consist of a fixed (fr_fix)
8614 and of a repeating (fr_var) part.
8616 The fixed content is always emitted before the repeating content and
8617 these two parts are used as follows in constructing the output:
8618 - the fixed part will be used to align to a valid instruction word
8619 boundary, in case that we start at a misaligned address; as no
8620 executable instruction can live at the misaligned location, we
8621 simply fill with zeros;
8622 - the variable part will be used to cover the remaining padding and
8623 we fill using the AArch64 NOP instruction.
8625 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8626 enough storage space for up to 3 bytes for padding the back to a valid
8627 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8630 aarch64_handle_align (fragS
* fragP
)
8632 /* NOP = d503201f */
8633 /* AArch64 instructions are always little-endian. */
8634 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8636 int bytes
, fix
, noop_size
;
8639 if (fragP
->fr_type
!= rs_align_code
)
8642 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8643 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8646 gas_assert (fragP
->tc_frag_data
.recorded
);
8649 noop_size
= sizeof (aarch64_noop
);
8651 fix
= bytes
& (noop_size
- 1);
8654 #if defined OBJ_ELF || defined OBJ_COFF
8655 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8659 fragP
->fr_fix
+= fix
;
8663 memcpy (p
, aarch64_noop
, noop_size
);
8664 fragP
->fr_var
= noop_size
;
8667 /* Perform target specific initialisation of a frag.
8668 Note - despite the name this initialisation is not done when the frag
8669 is created, but only when its type is assigned. A frag can be created
8670 and used a long time before its type is set, so beware of assuming that
8671 this initialisation is performed first. */
8675 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8676 int max_chars ATTRIBUTE_UNUSED
)
8680 #else /* OBJ_ELF is defined. */
8682 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8684 /* Record a mapping symbol for alignment frags. We will delete this
8685 later if the alignment ends up empty. */
8686 if (!fragP
->tc_frag_data
.recorded
)
8687 fragP
->tc_frag_data
.recorded
= 1;
8689 /* PR 21809: Do not set a mapping state for debug sections
8690 - it just confuses other tools. */
8691 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8694 switch (fragP
->fr_type
)
8698 mapping_state_2 (MAP_DATA
, max_chars
);
8701 /* PR 20364: We can get alignment frags in code sections,
8702 so do not just assume that we should use the MAP_DATA state. */
8703 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8706 mapping_state_2 (MAP_INSN
, max_chars
);
8713 /* Whether SFrame stack trace info is supported. */
8716 aarch64_support_sframe_p (void)
8718 /* At this time, SFrame is supported for aarch64 only. */
8719 return (aarch64_abi
== AARCH64_ABI_LP64
);
8722 /* Specify if RA tracking is needed. */
8725 aarch64_sframe_ra_tracking_p (void)
8730 /* Specify the fixed offset to recover RA from CFA.
8731 (useful only when RA tracking is not needed). */
8734 aarch64_sframe_cfa_ra_offset (void)
8736 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8739 /* Get the abi/arch indentifier for SFrame. */
8742 aarch64_sframe_get_abi_arch (void)
8744 unsigned char sframe_abi_arch
= 0;
8746 if (aarch64_support_sframe_p ())
8748 sframe_abi_arch
= target_big_endian
8749 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8750 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8753 return sframe_abi_arch
;
8756 #endif /* OBJ_ELF */
8758 /* Initialize the DWARF-2 unwind information for this procedure. */
8761 tc_aarch64_frame_initial_instructions (void)
8763 cfi_add_CFA_def_cfa (REG_SP
, 0);
8766 /* Convert REGNAME to a DWARF-2 register number. */
8769 tc_aarch64_regname_to_dw2regnum (char *regname
)
8771 const reg_entry
*reg
= parse_reg (®name
);
8777 case REG_TYPE_SP_32
:
8778 case REG_TYPE_SP_64
:
8788 return reg
->number
+ 64;
8796 /* Implement DWARF2_ADDR_SIZE. */
8799 aarch64_dwarf2_addr_size (void)
8805 return bfd_arch_bits_per_address (stdoutput
) / 8;
8808 /* MD interface: Symbol and relocation handling. */
8810 /* Return the address within the segment that a PC-relative fixup is
8811 relative to. For AArch64 PC-relative fixups applied to instructions
8812 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8815 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8817 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8819 /* If this is pc-relative and we are going to emit a relocation
8820 then we just want to put out any pipeline compensation that the linker
8821 will need. Otherwise we want to use the calculated base. */
8823 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8824 || aarch64_force_relocation (fixP
)))
8827 /* AArch64 should be consistent for all pc-relative relocations. */
8828 return base
+ AARCH64_PCREL_OFFSET
;
8831 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8832 Otherwise we have no need to default values of symbols. */
8835 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8838 if (name
[0] == '_' && name
[1] == 'G'
8839 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8843 if (symbol_find (name
))
8844 as_bad (_("GOT already in the symbol table"));
8846 GOT_symbol
= symbol_new (name
, undefined_section
,
8847 &zero_address_frag
, 0);
8857 /* Return non-zero if the indicated VALUE has overflowed the maximum
8858 range expressible by a unsigned number with the indicated number of
8862 unsigned_overflow (valueT value
, unsigned bits
)
8865 if (bits
>= sizeof (valueT
) * 8)
8867 lim
= (valueT
) 1 << bits
;
8868 return (value
>= lim
);
8872 /* Return non-zero if the indicated VALUE has overflowed the maximum
8873 range expressible by an signed number with the indicated number of
8877 signed_overflow (offsetT value
, unsigned bits
)
8880 if (bits
>= sizeof (offsetT
) * 8)
8882 lim
= (offsetT
) 1 << (bits
- 1);
8883 return (value
< -lim
|| value
>= lim
);
8886 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8887 unsigned immediate offset load/store instruction, try to encode it as
8888 an unscaled, 9-bit, signed immediate offset load/store instruction.
8889 Return TRUE if it is successful; otherwise return FALSE.
8891 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8892 in response to the standard LDR/STR mnemonics when the immediate offset is
8893 unambiguous, i.e. when it is negative or unaligned. */
8896 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8899 enum aarch64_op new_op
;
8900 const aarch64_opcode
*new_opcode
;
8902 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8904 switch (instr
->opcode
->op
)
8906 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8907 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8908 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8909 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8910 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8911 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8912 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8913 case OP_STR_POS
: new_op
= OP_STUR
; break;
8914 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8915 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8916 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8917 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8918 default: new_op
= OP_NIL
; break;
8921 if (new_op
== OP_NIL
)
8924 new_opcode
= aarch64_get_opcode (new_op
);
8925 gas_assert (new_opcode
!= NULL
);
8927 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8928 instr
->opcode
->op
, new_opcode
->op
);
8930 aarch64_replace_opcode (instr
, new_opcode
);
8932 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8933 qualifier matching may fail because the out-of-date qualifier will
8934 prevent the operand being updated with a new and correct qualifier. */
8935 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8936 AARCH64_OPND_ADDR_SIMM9
);
8937 gas_assert (idx
== 1);
8938 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8940 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8942 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8949 /* Called by fix_insn to fix a MOV immediate alias instruction.
8951 Operand for a generic move immediate instruction, which is an alias
8952 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8953 a 32-bit/64-bit immediate value into general register. An assembler error
8954 shall result if the immediate cannot be created by a single one of these
8955 instructions. If there is a choice, then to ensure reversability an
8956 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8959 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8961 const aarch64_opcode
*opcode
;
8963 /* Need to check if the destination is SP/ZR. The check has to be done
8964 before any aarch64_replace_opcode. */
8965 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8966 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8968 instr
->operands
[1].imm
.value
= value
;
8969 instr
->operands
[1].skip
= 0;
8973 /* Try the MOVZ alias. */
8974 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8975 aarch64_replace_opcode (instr
, opcode
);
8976 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8977 &instr
->value
, NULL
, NULL
, insn_sequence
))
8979 put_aarch64_insn (buf
, instr
->value
);
8982 /* Try the MOVK alias. */
8983 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8984 aarch64_replace_opcode (instr
, opcode
);
8985 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8986 &instr
->value
, NULL
, NULL
, insn_sequence
))
8988 put_aarch64_insn (buf
, instr
->value
);
8993 if (try_mov_bitmask_p
)
8995 /* Try the ORR alias. */
8996 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8997 aarch64_replace_opcode (instr
, opcode
);
8998 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8999 &instr
->value
, NULL
, NULL
, insn_sequence
))
9001 put_aarch64_insn (buf
, instr
->value
);
9006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9007 _("immediate cannot be moved by a single instruction"));
9010 /* An instruction operand which is immediate related may have symbol used
9011 in the assembly, e.g.
9014 .set u32, 0x00ffff00
9016 At the time when the assembly instruction is parsed, a referenced symbol,
9017 like 'u32' in the above example may not have been seen; a fixS is created
9018 in such a case and is handled here after symbols have been resolved.
9019 Instruction is fixed up with VALUE using the information in *FIXP plus
9020 extra information in FLAGS.
9022 This function is called by md_apply_fix to fix up instructions that need
9023 a fix-up described above but does not involve any linker-time relocation. */
9026 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
9030 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9031 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
9032 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
9036 /* Now the instruction is about to be fixed-up, so the operand that
9037 was previously marked as 'ignored' needs to be unmarked in order
9038 to get the encoding done properly. */
9039 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
9040 new_inst
->operands
[idx
].skip
= 0;
9043 gas_assert (opnd
!= AARCH64_OPND_NIL
);
9047 case AARCH64_OPND_EXCEPTION
:
9048 case AARCH64_OPND_UNDEFINED
:
9049 if (unsigned_overflow (value
, 16))
9050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9051 _("immediate out of range"));
9052 insn
= get_aarch64_insn (buf
);
9053 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
9054 put_aarch64_insn (buf
, insn
);
9057 case AARCH64_OPND_AIMM
:
9058 /* ADD or SUB with immediate.
9059 NOTE this assumes we come here with a add/sub shifted reg encoding
9060 3 322|2222|2 2 2 21111 111111
9061 1 098|7654|3 2 1 09876 543210 98765 43210
9062 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
9063 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
9064 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
9065 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
9067 3 322|2222|2 2 221111111111
9068 1 098|7654|3 2 109876543210 98765 43210
9069 11000000 sf 001|0001|shift imm12 Rn Rd ADD
9070 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
9071 51000000 sf 101|0001|shift imm12 Rn Rd SUB
9072 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
9073 Fields sf Rn Rd are already set. */
9074 insn
= get_aarch64_insn (buf
);
9078 insn
= reencode_addsub_switch_add_sub (insn
);
9082 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
9083 && unsigned_overflow (value
, 12))
9085 /* Try to shift the value by 12 to make it fit. */
9086 if (((value
>> 12) << 12) == value
9087 && ! unsigned_overflow (value
, 12 + 12))
9090 insn
|= encode_addsub_imm_shift_amount (1);
9094 if (unsigned_overflow (value
, 12))
9095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9096 _("immediate out of range"));
9098 insn
|= encode_addsub_imm (value
);
9100 put_aarch64_insn (buf
, insn
);
9103 case AARCH64_OPND_SIMD_IMM
:
9104 case AARCH64_OPND_SIMD_IMM_SFT
:
9105 case AARCH64_OPND_LIMM
:
9106 /* Bit mask immediate. */
9107 gas_assert (new_inst
!= NULL
);
9108 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
9109 new_inst
->operands
[idx
].imm
.value
= value
;
9110 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9111 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9112 put_aarch64_insn (buf
, new_inst
->value
);
9114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9115 _("invalid immediate"));
9118 case AARCH64_OPND_HALF
:
9119 /* 16-bit unsigned immediate. */
9120 if (unsigned_overflow (value
, 16))
9121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9122 _("immediate out of range"));
9123 insn
= get_aarch64_insn (buf
);
9124 insn
|= encode_movw_imm (value
& 0xffff);
9125 put_aarch64_insn (buf
, insn
);
9128 case AARCH64_OPND_IMM_MOV
:
9129 /* Operand for a generic move immediate instruction, which is
9130 an alias instruction that generates a single MOVZ, MOVN or ORR
9131 instruction to loads a 32-bit/64-bit immediate value into general
9132 register. An assembler error shall result if the immediate cannot be
9133 created by a single one of these instructions. If there is a choice,
9134 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
9135 and MOVZ or MOVN to ORR. */
9136 gas_assert (new_inst
!= NULL
);
9137 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
9140 case AARCH64_OPND_ADDR_SIMM7
:
9141 case AARCH64_OPND_ADDR_SIMM9
:
9142 case AARCH64_OPND_ADDR_SIMM9_2
:
9143 case AARCH64_OPND_ADDR_SIMM10
:
9144 case AARCH64_OPND_ADDR_UIMM12
:
9145 case AARCH64_OPND_ADDR_SIMM11
:
9146 case AARCH64_OPND_ADDR_SIMM13
:
9147 /* Immediate offset in an address. */
9148 insn
= get_aarch64_insn (buf
);
9150 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
9151 gas_assert (new_inst
->opcode
->operands
[1] == opnd
9152 || new_inst
->opcode
->operands
[2] == opnd
);
9154 /* Get the index of the address operand. */
9155 if (new_inst
->opcode
->operands
[1] == opnd
)
9156 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
9159 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
9162 /* Update the resolved offset value. */
9163 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
9165 /* Encode/fix-up. */
9166 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9167 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9169 put_aarch64_insn (buf
, new_inst
->value
);
9172 else if (new_inst
->opcode
->iclass
== ldst_pos
9173 && try_to_encode_as_unscaled_ldst (new_inst
))
9175 put_aarch64_insn (buf
, new_inst
->value
);
9179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9180 _("immediate offset out of range"));
9185 as_fatal (_("unhandled operand code %d"), opnd
);
9189 /* Apply a fixup (fixP) to segment data, once it has been determined
9190 by our caller that we have all the info we need to fix it up.
9192 Parameter valP is the pointer to the value of the bits. */
9195 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
9197 offsetT value
= *valP
;
9199 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9201 unsigned flags
= fixP
->fx_addnumber
;
9203 DEBUG_TRACE ("\n\n");
9204 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
9205 DEBUG_TRACE ("Enter md_apply_fix");
9207 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
9209 /* Note whether this will delete the relocation. */
9211 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
9212 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
9215 /* Process the relocations. */
9216 switch (fixP
->fx_r_type
)
9218 case BFD_RELOC_NONE
:
9219 /* This will need to go in the object file. */
9224 case BFD_RELOC_8_PCREL
:
9225 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9226 md_number_to_chars (buf
, value
, 1);
9230 case BFD_RELOC_16_PCREL
:
9231 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9232 md_number_to_chars (buf
, value
, 2);
9236 case BFD_RELOC_32_PCREL
:
9237 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9238 md_number_to_chars (buf
, value
, 4);
9242 case BFD_RELOC_64_PCREL
:
9243 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9244 md_number_to_chars (buf
, value
, 8);
9247 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9248 /* We claim that these fixups have been processed here, even if
9249 in fact we generate an error because we do not have a reloc
9250 for them, so tc_gen_reloc() will reject them. */
9252 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
9254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9255 _("undefined symbol %s used as an immediate value"),
9256 S_GET_NAME (fixP
->fx_addsy
));
9257 goto apply_fix_return
;
9259 fix_insn (fixP
, flags
, value
);
9262 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
9263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9267 _("pc-relative load offset not word aligned"));
9268 if (signed_overflow (value
, 21))
9269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9270 _("pc-relative load offset out of range"));
9271 insn
= get_aarch64_insn (buf
);
9272 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9273 put_aarch64_insn (buf
, insn
);
9277 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9278 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9280 if (signed_overflow (value
, 21))
9281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9282 _("pc-relative address offset out of range"));
9283 insn
= get_aarch64_insn (buf
);
9284 insn
|= encode_adr_imm (value
);
9285 put_aarch64_insn (buf
, insn
);
9289 case BFD_RELOC_AARCH64_BRANCH19
:
9290 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9294 _("conditional branch target not word aligned"));
9295 if (signed_overflow (value
, 21))
9296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9297 _("conditional branch out of range"));
9298 insn
= get_aarch64_insn (buf
);
9299 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9300 put_aarch64_insn (buf
, insn
);
9304 case BFD_RELOC_AARCH64_TSTBR14
:
9305 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9309 _("conditional branch target not word aligned"));
9310 if (signed_overflow (value
, 16))
9311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9312 _("conditional branch out of range"));
9313 insn
= get_aarch64_insn (buf
);
9314 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9315 put_aarch64_insn (buf
, insn
);
9319 case BFD_RELOC_AARCH64_CALL26
:
9320 case BFD_RELOC_AARCH64_JUMP26
:
9321 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9325 _("branch target not word aligned"));
9326 if (signed_overflow (value
, 28))
9327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9328 _("branch out of range"));
9329 insn
= get_aarch64_insn (buf
);
9330 insn
|= encode_branch_ofs_26 (value
>> 2);
9331 put_aarch64_insn (buf
, insn
);
9335 case BFD_RELOC_AARCH64_MOVW_G0
:
9336 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9337 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9338 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9339 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9340 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9343 case BFD_RELOC_AARCH64_MOVW_G1
:
9344 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9345 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9346 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9347 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9348 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9351 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9353 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9354 /* Should always be exported to object file, see
9355 aarch64_force_relocation(). */
9356 gas_assert (!fixP
->fx_done
);
9357 gas_assert (seg
->use_rela_p
);
9359 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9361 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9362 /* Should always be exported to object file, see
9363 aarch64_force_relocation(). */
9364 gas_assert (!fixP
->fx_done
);
9365 gas_assert (seg
->use_rela_p
);
9367 case BFD_RELOC_AARCH64_MOVW_G2
:
9368 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9369 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9370 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9371 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9374 case BFD_RELOC_AARCH64_MOVW_G3
:
9375 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9378 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9380 insn
= get_aarch64_insn (buf
);
9384 /* REL signed addend must fit in 16 bits */
9385 if (signed_overflow (value
, 16))
9386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9387 _("offset out of range"));
9391 /* Check for overflow and scale. */
9392 switch (fixP
->fx_r_type
)
9394 case BFD_RELOC_AARCH64_MOVW_G0
:
9395 case BFD_RELOC_AARCH64_MOVW_G1
:
9396 case BFD_RELOC_AARCH64_MOVW_G2
:
9397 case BFD_RELOC_AARCH64_MOVW_G3
:
9398 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9399 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9400 if (unsigned_overflow (value
, scale
+ 16))
9401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9402 _("unsigned value out of range"));
9404 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9405 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9406 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9407 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9408 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9409 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9410 /* NOTE: We can only come here with movz or movn. */
9411 if (signed_overflow (value
, scale
+ 16))
9412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9413 _("signed value out of range"));
9416 /* Force use of MOVN. */
9418 insn
= reencode_movzn_to_movn (insn
);
9422 /* Force use of MOVZ. */
9423 insn
= reencode_movzn_to_movz (insn
);
9427 /* Unchecked relocations. */
9433 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9434 insn
|= encode_movw_imm (value
& 0xffff);
9436 put_aarch64_insn (buf
, insn
);
9440 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9441 fixP
->fx_r_type
= (ilp32_p
9442 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9443 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9444 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9445 /* Should always be exported to object file, see
9446 aarch64_force_relocation(). */
9447 gas_assert (!fixP
->fx_done
);
9448 gas_assert (seg
->use_rela_p
);
9451 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9452 fixP
->fx_r_type
= (ilp32_p
9453 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9454 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9455 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9456 /* Should always be exported to object file, see
9457 aarch64_force_relocation(). */
9458 gas_assert (!fixP
->fx_done
);
9459 gas_assert (seg
->use_rela_p
);
9462 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9463 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9464 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9465 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9466 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9467 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9468 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9469 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9470 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9471 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9472 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9473 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9474 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9475 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9476 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9477 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9478 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9479 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9480 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9481 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9482 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9483 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9484 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9485 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9486 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9487 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9488 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9489 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9490 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9491 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9492 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9493 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9494 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9495 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9496 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9497 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9498 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9499 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9500 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9501 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9502 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9503 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9504 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9505 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9506 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9507 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9508 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9509 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9510 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9511 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9512 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9513 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9514 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9515 /* Should always be exported to object file, see
9516 aarch64_force_relocation(). */
9517 gas_assert (!fixP
->fx_done
);
9518 gas_assert (seg
->use_rela_p
);
9521 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9522 /* Should always be exported to object file, see
9523 aarch64_force_relocation(). */
9524 fixP
->fx_r_type
= (ilp32_p
9525 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9526 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9527 gas_assert (!fixP
->fx_done
);
9528 gas_assert (seg
->use_rela_p
);
9531 case BFD_RELOC_AARCH64_ADD_LO12
:
9532 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9533 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9534 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9535 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9536 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9537 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9538 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9539 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9540 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9541 case BFD_RELOC_AARCH64_LDST128_LO12
:
9542 case BFD_RELOC_AARCH64_LDST16_LO12
:
9543 case BFD_RELOC_AARCH64_LDST32_LO12
:
9544 case BFD_RELOC_AARCH64_LDST64_LO12
:
9545 case BFD_RELOC_AARCH64_LDST8_LO12
:
9546 /* Should always be exported to object file, see
9547 aarch64_force_relocation(). */
9548 gas_assert (!fixP
->fx_done
);
9549 gas_assert (seg
->use_rela_p
);
9552 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9553 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9554 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9557 case BFD_RELOC_UNUSED
:
9558 /* An error will already have been reported. */
9562 case BFD_RELOC_32_SECREL
:
9563 case BFD_RELOC_16_SECIDX
:
9567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9568 _("unexpected %s fixup"),
9569 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9574 /* Free the allocated the struct aarch64_inst.
9575 N.B. currently there are very limited number of fix-up types actually use
9576 this field, so the impact on the performance should be minimal . */
9577 free (fixP
->tc_fix_data
.inst
);
9582 /* Translate internal representation of relocation info to BFD target
9586 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9589 bfd_reloc_code_real_type code
;
9591 reloc
= XNEW (arelent
);
9593 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9594 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9595 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9599 if (section
->use_rela_p
)
9600 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9602 fixp
->fx_offset
= reloc
->address
;
9604 reloc
->addend
= fixp
->fx_offset
;
9606 code
= fixp
->fx_r_type
;
9611 code
= BFD_RELOC_16_PCREL
;
9616 code
= BFD_RELOC_32_PCREL
;
9621 code
= BFD_RELOC_64_PCREL
;
9628 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9629 if (reloc
->howto
== NULL
)
9631 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9633 ("cannot represent %s relocation in this object file format"),
9634 bfd_get_reloc_code_name (code
));
9641 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9644 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9646 bfd_reloc_code_real_type type
;
9650 if (exp
->X_op
== O_secrel
)
9652 exp
->X_op
= O_symbol
;
9653 type
= BFD_RELOC_32_SECREL
;
9655 else if (exp
->X_op
== O_secidx
)
9657 exp
->X_op
= O_symbol
;
9658 type
= BFD_RELOC_16_SECIDX
;
9664 FIXME: @@ Should look at CPU word size. */
9671 type
= BFD_RELOC_16
;
9674 type
= BFD_RELOC_32
;
9677 type
= BFD_RELOC_64
;
9680 as_bad (_("cannot do %u-byte relocation"), size
);
9681 type
= BFD_RELOC_UNUSED
;
9688 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9691 /* Implement md_after_parse_args. This is the earliest time we need to decide
9692 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9695 aarch64_after_parse_args (void)
9697 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9701 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9702 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9703 aarch64_abi
= AARCH64_ABI_ILP32
;
9705 aarch64_abi
= AARCH64_ABI_LP64
;
9707 aarch64_abi
= AARCH64_ABI_LLP64
;
9713 elf64_aarch64_target_format (void)
9716 /* FIXME: What to do for ilp32_p ? */
9717 if (target_big_endian
)
9718 return "elf64-bigaarch64-cloudabi";
9720 return "elf64-littleaarch64-cloudabi";
9722 if (target_big_endian
)
9723 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9725 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9730 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9732 elf_frob_symbol (symp
, puntp
);
9734 #elif defined OBJ_COFF
9736 coff_aarch64_target_format (void)
9738 return "pe-aarch64-little";
9742 /* MD interface: Finalization. */
9744 /* A good place to do this, although this was probably not intended
9745 for this kind of use. We need to dump the literal pool before
9746 references are made to a null symbol pointer. */
9749 aarch64_cleanup (void)
9753 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9755 /* Put it at the end of the relevant section. */
9756 subseg_set (pool
->section
, pool
->sub_section
);
9762 /* Remove any excess mapping symbols generated for alignment frags in
9763 SEC. We may have created a mapping symbol before a zero byte
9764 alignment; remove it if there's a mapping symbol after the
9767 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9768 void *dummy ATTRIBUTE_UNUSED
)
9770 segment_info_type
*seginfo
= seg_info (sec
);
9773 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9776 for (fragp
= seginfo
->frchainP
->frch_root
;
9777 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9779 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9780 fragS
*next
= fragp
->fr_next
;
9782 /* Variable-sized frags have been converted to fixed size by
9783 this point. But if this was variable-sized to start with,
9784 there will be a fixed-size frag after it. So don't handle
9786 if (sym
== NULL
|| next
== NULL
)
9789 if (S_GET_VALUE (sym
) < next
->fr_address
)
9790 /* Not at the end of this frag. */
9792 know (S_GET_VALUE (sym
) == next
->fr_address
);
9796 if (next
->tc_frag_data
.first_map
!= NULL
)
9798 /* Next frag starts with a mapping symbol. Discard this
9800 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9804 if (next
->fr_next
== NULL
)
9806 /* This mapping symbol is at the end of the section. Discard
9808 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9809 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9813 /* As long as we have empty frags without any mapping symbols,
9815 /* If the next frag is non-empty and does not start with a
9816 mapping symbol, then this mapping symbol is required. */
9817 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9820 next
= next
->fr_next
;
9822 while (next
!= NULL
);
9827 /* Adjust the symbol table. */
9830 aarch64_adjust_symtab (void)
9833 /* Remove any overlapping mapping symbols generated by alignment frags. */
9834 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9835 /* Now do generic ELF adjustments. */
9836 elf_adjust_symtab ();
9841 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9843 str_hash_insert (table
, key
, value
, 0);
9847 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9849 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9850 checked_hash_insert (table
, key
, value
);
9854 fill_instruction_hash_table (void)
9856 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9858 while (opcode
->name
!= NULL
)
9860 templates
*templ
, *new_templ
;
9861 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9863 new_templ
= XNEW (templates
);
9864 new_templ
->opcode
= opcode
;
9865 new_templ
->next
= NULL
;
9868 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9871 new_templ
->next
= templ
->next
;
9872 templ
->next
= new_templ
;
9879 convert_to_upper (char *dst
, const char *src
, size_t num
)
9882 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9883 *dst
= TOUPPER (*src
);
9887 /* Assume STR point to a lower-case string, allocate, convert and return
9888 the corresponding upper-case string. */
9889 static inline const char*
9890 get_upper_str (const char *str
)
9893 size_t len
= strlen (str
);
9894 ret
= XNEWVEC (char, len
+ 1);
9895 convert_to_upper (ret
, str
, len
);
9899 /* MD interface: Initialization. */
9907 aarch64_ops_hsh
= str_htab_create ();
9908 aarch64_cond_hsh
= str_htab_create ();
9909 aarch64_shift_hsh
= str_htab_create ();
9910 aarch64_sys_regs_hsh
= str_htab_create ();
9911 aarch64_pstatefield_hsh
= str_htab_create ();
9912 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9913 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9914 aarch64_sys_regs_at_hsh
= str_htab_create ();
9915 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9916 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9917 aarch64_reg_hsh
= str_htab_create ();
9918 aarch64_barrier_opt_hsh
= str_htab_create ();
9919 aarch64_nzcv_hsh
= str_htab_create ();
9920 aarch64_pldop_hsh
= str_htab_create ();
9921 aarch64_hint_opt_hsh
= str_htab_create ();
9923 fill_instruction_hash_table ();
9925 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9926 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9927 (void *) (aarch64_sys_regs
+ i
));
9929 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9930 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9931 aarch64_pstatefields
[i
].name
,
9932 (void *) (aarch64_pstatefields
+ i
));
9934 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9935 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9936 aarch64_sys_regs_ic
[i
].name
,
9937 (void *) (aarch64_sys_regs_ic
+ i
));
9939 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9940 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9941 aarch64_sys_regs_dc
[i
].name
,
9942 (void *) (aarch64_sys_regs_dc
+ i
));
9944 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9945 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9946 aarch64_sys_regs_at
[i
].name
,
9947 (void *) (aarch64_sys_regs_at
+ i
));
9949 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9950 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9951 aarch64_sys_regs_tlbi
[i
].name
,
9952 (void *) (aarch64_sys_regs_tlbi
+ i
));
9954 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9955 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9956 aarch64_sys_regs_sr
[i
].name
,
9957 (void *) (aarch64_sys_regs_sr
+ i
));
9959 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9960 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9961 (void *) (reg_names
+ i
));
9963 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9964 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9965 (void *) (nzcv_names
+ i
));
9967 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9969 const char *name
= aarch64_operand_modifiers
[i
].name
;
9970 checked_hash_insert (aarch64_shift_hsh
, name
,
9971 (void *) (aarch64_operand_modifiers
+ i
));
9972 /* Also hash the name in the upper case. */
9973 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9974 (void *) (aarch64_operand_modifiers
+ i
));
9977 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9980 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9981 the same condition code. */
9982 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9984 const char *name
= aarch64_conds
[i
].names
[j
];
9987 checked_hash_insert (aarch64_cond_hsh
, name
,
9988 (void *) (aarch64_conds
+ i
));
9989 /* Also hash the name in the upper case. */
9990 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9991 (void *) (aarch64_conds
+ i
));
9995 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9997 const char *name
= aarch64_barrier_options
[i
].name
;
9998 /* Skip xx00 - the unallocated values of option. */
10001 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
10002 (void *) (aarch64_barrier_options
+ i
));
10003 /* Also hash the name in the upper case. */
10004 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
10005 (void *) (aarch64_barrier_options
+ i
));
10008 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
10010 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
10011 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
10012 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
10013 /* Also hash the name in the upper case. */
10014 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
10015 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
10018 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
10020 const char* name
= aarch64_prfops
[i
].name
;
10021 /* Skip the unallocated hint encodings. */
10024 checked_hash_insert (aarch64_pldop_hsh
, name
,
10025 (void *) (aarch64_prfops
+ i
));
10026 /* Also hash the name in the upper case. */
10027 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
10028 (void *) (aarch64_prfops
+ i
));
10031 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
10033 const char* name
= aarch64_hint_options
[i
].name
;
10034 const char* upper_name
= get_upper_str(name
);
10036 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
10037 (void *) (aarch64_hint_options
+ i
));
10039 /* Also hash the name in the upper case if not the same. */
10040 if (strcmp (name
, upper_name
) != 0)
10041 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
10042 (void *) (aarch64_hint_options
+ i
));
10045 /* Set the cpu variant based on the command-line options. */
10047 mcpu_cpu_opt
= march_cpu_opt
;
10050 mcpu_cpu_opt
= &cpu_default
;
10052 cpu_variant
= *mcpu_cpu_opt
;
10054 /* Record the CPU type. */
10056 mach
= bfd_mach_aarch64_ilp32
;
10058 mach
= bfd_mach_aarch64_llp64
;
10060 mach
= bfd_mach_aarch64
;
10062 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
10064 /* FIXME - is there a better way to do it ? */
10065 aarch64_sframe_cfa_sp_reg
= 31;
10066 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
10067 aarch64_sframe_cfa_ra_reg
= 30;
10071 /* Command line processing. */
10073 const char *md_shortopts
= "m:";
10075 #ifdef AARCH64_BI_ENDIAN
10076 #define OPTION_EB (OPTION_MD_BASE + 0)
10077 #define OPTION_EL (OPTION_MD_BASE + 1)
10079 #if TARGET_BYTES_BIG_ENDIAN
10080 #define OPTION_EB (OPTION_MD_BASE + 0)
10082 #define OPTION_EL (OPTION_MD_BASE + 1)
10086 struct option md_longopts
[] = {
10088 {"EB", no_argument
, NULL
, OPTION_EB
},
10091 {"EL", no_argument
, NULL
, OPTION_EL
},
10093 {NULL
, no_argument
, NULL
, 0}
10096 size_t md_longopts_size
= sizeof (md_longopts
);
10098 struct aarch64_option_table
10100 const char *option
; /* Option name to match. */
10101 const char *help
; /* Help information. */
10102 int *var
; /* Variable to change. */
10103 int value
; /* What to change it to. */
10104 char *deprecated
; /* If non-null, print this message. */
10107 static struct aarch64_option_table aarch64_opts
[] = {
10108 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
10109 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
10111 #ifdef DEBUG_AARCH64
10112 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
10113 #endif /* DEBUG_AARCH64 */
10114 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
10116 {"mno-verbose-error", N_("do not output verbose error messages"),
10117 &verbose_error_p
, 0, NULL
},
10118 {NULL
, NULL
, NULL
, 0, NULL
}
10121 struct aarch64_cpu_option_table
10124 const aarch64_feature_set value
;
10125 /* The canonical name of the CPU, or NULL to use NAME converted to upper
10127 const char *canonical_name
;
10130 /* This list should, at a minimum, contain all the cpu names
10131 recognized by GCC. */
10132 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
10133 {"all", AARCH64_ANY
, NULL
},
10134 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10135 AARCH64_FEATURE_CRC
), "Cortex-A34"},
10136 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10137 AARCH64_FEATURE_CRC
), "Cortex-A35"},
10138 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10139 AARCH64_FEATURE_CRC
), "Cortex-A53"},
10140 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10141 AARCH64_FEATURE_CRC
), "Cortex-A57"},
10142 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10143 AARCH64_FEATURE_CRC
), "Cortex-A72"},
10144 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10145 AARCH64_FEATURE_CRC
), "Cortex-A73"},
10146 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10147 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10149 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10150 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10152 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10153 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10155 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10156 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10157 | AARCH64_FEATURE_DOTPROD
10158 | AARCH64_FEATURE_SSBS
),
10160 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10161 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10162 | AARCH64_FEATURE_DOTPROD
10163 | AARCH64_FEATURE_SSBS
),
10165 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10166 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10167 | AARCH64_FEATURE_DOTPROD
10168 | AARCH64_FEATURE_SSBS
),
10170 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10171 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10172 | AARCH64_FEATURE_DOTPROD
10173 | AARCH64_FEATURE_SSBS
),
10175 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10176 AARCH64_FEATURE_F16
10177 | AARCH64_FEATURE_RCPC
10178 | AARCH64_FEATURE_DOTPROD
10179 | AARCH64_FEATURE_SSBS
10180 | AARCH64_FEATURE_PROFILE
),
10182 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10183 AARCH64_FEATURE_F16
10184 | AARCH64_FEATURE_RCPC
10185 | AARCH64_FEATURE_DOTPROD
10186 | AARCH64_FEATURE_SSBS
10187 | AARCH64_FEATURE_PROFILE
),
10189 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10190 AARCH64_FEATURE_DOTPROD
10191 | AARCH64_FEATURE_F16
10192 | AARCH64_FEATURE_FLAGM
10193 | AARCH64_FEATURE_PAC
10194 | AARCH64_FEATURE_PROFILE
10195 | AARCH64_FEATURE_RCPC
10196 | AARCH64_FEATURE_SSBS
),
10198 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10199 AARCH64_FEATURE_BFLOAT16
10200 | AARCH64_FEATURE_I8MM
10201 | AARCH64_FEATURE_MEMTAG
10202 | AARCH64_FEATURE_SVE2_BITPERM
),
10204 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10205 AARCH64_FEATURE_BFLOAT16
10206 | AARCH64_FEATURE_I8MM
10207 | AARCH64_FEATURE_MEMTAG
10208 | AARCH64_FEATURE_SVE2_BITPERM
),
10210 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10211 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10212 | AARCH64_FEATURE_DOTPROD
10213 | AARCH64_FEATURE_PROFILE
),
10215 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10216 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10217 "Samsung Exynos M1"},
10218 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10219 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10220 | AARCH64_FEATURE_RDMA
),
10221 "Qualcomm Falkor"},
10222 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10223 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10224 | AARCH64_FEATURE_DOTPROD
10225 | AARCH64_FEATURE_SSBS
),
10227 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10228 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10229 | AARCH64_FEATURE_DOTPROD
10230 | AARCH64_FEATURE_PROFILE
),
10232 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
10233 AARCH64_FEATURE_BFLOAT16
10234 | AARCH64_FEATURE_I8MM
10235 | AARCH64_FEATURE_F16
10236 | AARCH64_FEATURE_SVE
10237 | AARCH64_FEATURE_SVE2
10238 | AARCH64_FEATURE_SVE2_BITPERM
10239 | AARCH64_FEATURE_MEMTAG
10240 | AARCH64_FEATURE_RNG
),
10242 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10243 AARCH64_FEATURE_PROFILE
10244 | AARCH64_FEATURE_CVADP
10245 | AARCH64_FEATURE_SVE
10246 | AARCH64_FEATURE_SSBS
10247 | AARCH64_FEATURE_RNG
10248 | AARCH64_FEATURE_F16
10249 | AARCH64_FEATURE_BFLOAT16
10250 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
10251 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10252 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10253 | AARCH64_FEATURE_RDMA
),
10254 "Qualcomm QDF24XX"},
10255 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10256 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
10257 "Qualcomm Saphira"},
10258 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10259 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10260 "Cavium ThunderX"},
10261 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
10262 AARCH64_FEATURE_CRYPTO
),
10263 "Broadcom Vulcan"},
10264 /* The 'xgene-1' name is an older name for 'xgene1', which was used
10265 in earlier releases and is superseded by 'xgene1' in all
10267 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10268 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10269 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10270 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10271 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10272 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10273 AARCH64_FEATURE_F16
10274 | AARCH64_FEATURE_RCPC
10275 | AARCH64_FEATURE_DOTPROD
10276 | AARCH64_FEATURE_SSBS
10277 | AARCH64_FEATURE_PROFILE
),
10279 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10280 AARCH64_FEATURE_BFLOAT16
10281 | AARCH64_FEATURE_I8MM
10282 | AARCH64_FEATURE_MEMTAG
10283 | AARCH64_FEATURE_SVE2_BITPERM
),
10285 {"generic", AARCH64_ARCH_V8
, NULL
},
10287 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10290 struct aarch64_arch_option_table
10293 const aarch64_feature_set value
;
10296 /* This list should, at a minimum, contain all the architecture names
10297 recognized by GCC. */
10298 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10299 {"all", AARCH64_ANY
},
10300 {"armv8-a", AARCH64_ARCH_V8
},
10301 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10302 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10303 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10304 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10305 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10306 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10307 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10308 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10309 {"armv8-r", AARCH64_ARCH_V8_R
},
10310 {"armv9-a", AARCH64_ARCH_V9
},
10311 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10312 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10313 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10314 {NULL
, AARCH64_ARCH_NONE
}
10317 /* ISA extensions. */
10318 struct aarch64_option_cpu_value_table
10321 const aarch64_feature_set value
;
10322 const aarch64_feature_set require
; /* Feature dependencies. */
10325 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10326 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10327 AARCH64_ARCH_NONE
},
10328 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10329 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10330 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10331 AARCH64_ARCH_NONE
},
10332 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10333 AARCH64_ARCH_NONE
},
10334 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10335 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10336 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10337 AARCH64_ARCH_NONE
},
10338 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10339 AARCH64_ARCH_NONE
},
10340 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10341 AARCH64_ARCH_NONE
},
10342 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10343 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10344 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10345 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10346 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10347 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10348 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10349 AARCH64_ARCH_NONE
},
10350 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10351 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10352 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10353 AARCH64_ARCH_NONE
},
10354 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10355 AARCH64_FEATURE (AARCH64_FEATURE_F16
10356 | AARCH64_FEATURE_SIMD
, 0)},
10357 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10358 AARCH64_ARCH_NONE
},
10359 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10360 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10361 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10362 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10363 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10364 AARCH64_ARCH_NONE
},
10365 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10366 AARCH64_ARCH_NONE
},
10367 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10368 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10369 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10370 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10371 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10372 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10373 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10374 AARCH64_ARCH_NONE
},
10375 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10376 AARCH64_ARCH_NONE
},
10377 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10378 AARCH64_ARCH_NONE
},
10379 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10380 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10381 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10382 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10383 | AARCH64_FEATURE_SM4
, 0)},
10384 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10385 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10386 | AARCH64_FEATURE_AES
, 0)},
10387 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10388 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10389 | AARCH64_FEATURE_SHA3
, 0)},
10390 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10391 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10392 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10393 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10394 | AARCH64_FEATURE_BFLOAT16
, 0)},
10395 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10396 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10397 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10398 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10399 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10400 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10401 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10402 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10403 {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2
, 0),
10404 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10405 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10406 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10407 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10408 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10409 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10410 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10411 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10412 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10413 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10414 AARCH64_ARCH_NONE
},
10415 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10416 AARCH64_ARCH_NONE
},
10417 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10418 AARCH64_ARCH_NONE
},
10419 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10420 AARCH64_ARCH_NONE
},
10421 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10422 AARCH64_ARCH_NONE
},
10423 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10424 AARCH64_ARCH_NONE
},
10425 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10428 struct aarch64_long_option_table
10430 const char *option
; /* Substring to match. */
10431 const char *help
; /* Help information. */
10432 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10433 char *deprecated
; /* If non-null, print this message. */
10436 /* Transitive closure of features depending on set. */
10437 static aarch64_feature_set
10438 aarch64_feature_disable_set (aarch64_feature_set set
)
10440 const struct aarch64_option_cpu_value_table
*opt
;
10441 aarch64_feature_set prev
= 0;
10443 while (prev
!= set
) {
10445 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10446 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10447 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10452 /* Transitive closure of dependencies of set. */
10453 static aarch64_feature_set
10454 aarch64_feature_enable_set (aarch64_feature_set set
)
10456 const struct aarch64_option_cpu_value_table
*opt
;
10457 aarch64_feature_set prev
= 0;
10459 while (prev
!= set
) {
10461 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10462 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10463 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10469 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10472 /* We insist on extensions being added before being removed. We achieve
10473 this by using the ADDING_VALUE variable to indicate whether we are
10474 adding an extension (1) or removing it (0) and only allowing it to
10475 change in the order -1 -> 1 -> 0. */
10476 int adding_value
= -1;
10477 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10479 /* Copy the feature set, so that we can modify it. */
10480 *ext_set
= **opt_p
;
10483 while (str
!= NULL
&& *str
!= 0)
10485 const struct aarch64_option_cpu_value_table
*opt
;
10486 const char *ext
= NULL
;
10493 as_bad (_("invalid architectural extension"));
10497 ext
= strchr (++str
, '+');
10501 optlen
= ext
- str
;
10503 optlen
= strlen (str
);
10505 if (optlen
>= 2 && startswith (str
, "no"))
10507 if (adding_value
!= 0)
10512 else if (optlen
> 0)
10514 if (adding_value
== -1)
10516 else if (adding_value
!= 1)
10518 as_bad (_("must specify extensions to add before specifying "
10519 "those to remove"));
10526 as_bad (_("missing architectural extension"));
10530 gas_assert (adding_value
!= -1);
10532 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10533 if (strncmp (opt
->name
, str
, optlen
) == 0)
10535 aarch64_feature_set set
;
10537 /* Add or remove the extension. */
10540 set
= aarch64_feature_enable_set (opt
->value
);
10541 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10545 set
= aarch64_feature_disable_set (opt
->value
);
10546 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10551 if (opt
->name
== NULL
)
10553 as_bad (_("unknown architectural extension `%s'"), str
);
10564 aarch64_parse_cpu (const char *str
)
10566 const struct aarch64_cpu_option_table
*opt
;
10567 const char *ext
= strchr (str
, '+');
10571 optlen
= ext
- str
;
10573 optlen
= strlen (str
);
10577 as_bad (_("missing cpu name `%s'"), str
);
10581 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10582 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10584 mcpu_cpu_opt
= &opt
->value
;
10586 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10591 as_bad (_("unknown cpu `%s'"), str
);
10596 aarch64_parse_arch (const char *str
)
10598 const struct aarch64_arch_option_table
*opt
;
10599 const char *ext
= strchr (str
, '+');
10603 optlen
= ext
- str
;
10605 optlen
= strlen (str
);
10609 as_bad (_("missing architecture name `%s'"), str
);
10613 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10614 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10616 march_cpu_opt
= &opt
->value
;
10618 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10623 as_bad (_("unknown architecture `%s'\n"), str
);
10628 struct aarch64_option_abi_value_table
10631 enum aarch64_abi_type value
;
10634 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10636 {"ilp32", AARCH64_ABI_ILP32
},
10637 {"lp64", AARCH64_ABI_LP64
},
10639 {"llp64", AARCH64_ABI_LLP64
},
10644 aarch64_parse_abi (const char *str
)
10648 if (str
[0] == '\0')
10650 as_bad (_("missing abi name `%s'"), str
);
10654 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10655 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10657 aarch64_abi
= aarch64_abis
[i
].value
;
10661 as_bad (_("unknown abi `%s'\n"), str
);
10665 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10666 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10667 aarch64_parse_abi
, NULL
},
10668 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10669 aarch64_parse_cpu
, NULL
},
10670 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10671 aarch64_parse_arch
, NULL
},
10672 {NULL
, NULL
, 0, NULL
}
10676 md_parse_option (int c
, const char *arg
)
10678 struct aarch64_option_table
*opt
;
10679 struct aarch64_long_option_table
*lopt
;
10685 target_big_endian
= 1;
10691 target_big_endian
= 0;
10696 /* Listing option. Just ignore these, we don't support additional
10701 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10703 if (c
== opt
->option
[0]
10704 && ((arg
== NULL
&& opt
->option
[1] == 0)
10705 || streq (arg
, opt
->option
+ 1)))
10707 /* If the option is deprecated, tell the user. */
10708 if (opt
->deprecated
!= NULL
)
10709 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10710 arg
? arg
: "", _(opt
->deprecated
));
10712 if (opt
->var
!= NULL
)
10713 *opt
->var
= opt
->value
;
10719 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10721 /* These options are expected to have an argument. */
10722 if (c
== lopt
->option
[0]
10724 && startswith (arg
, lopt
->option
+ 1))
10726 /* If the option is deprecated, tell the user. */
10727 if (lopt
->deprecated
!= NULL
)
10728 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10729 _(lopt
->deprecated
));
10731 /* Call the sup-option parser. */
10732 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10743 md_show_usage (FILE * fp
)
10745 struct aarch64_option_table
*opt
;
10746 struct aarch64_long_option_table
*lopt
;
10748 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10750 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10751 if (opt
->help
!= NULL
)
10752 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10754 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10755 if (lopt
->help
!= NULL
)
10756 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10760 -EB assemble code for a big-endian cpu\n"));
10765 -EL assemble code for a little-endian cpu\n"));
10769 /* Parse a .cpu directive. */
10772 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10774 const struct aarch64_cpu_option_table
*opt
;
10780 name
= input_line_pointer
;
10781 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10782 saved_char
= *input_line_pointer
;
10783 *input_line_pointer
= 0;
10785 ext
= strchr (name
, '+');
10788 optlen
= ext
- name
;
10790 optlen
= strlen (name
);
10792 /* Skip the first "all" entry. */
10793 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10794 if (strlen (opt
->name
) == optlen
10795 && strncmp (name
, opt
->name
, optlen
) == 0)
10797 mcpu_cpu_opt
= &opt
->value
;
10799 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10802 cpu_variant
= *mcpu_cpu_opt
;
10804 *input_line_pointer
= saved_char
;
10805 demand_empty_rest_of_line ();
10808 as_bad (_("unknown cpu `%s'"), name
);
10809 *input_line_pointer
= saved_char
;
10810 ignore_rest_of_line ();
10814 /* Parse a .arch directive. */
10817 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10819 const struct aarch64_arch_option_table
*opt
;
10825 name
= input_line_pointer
;
10826 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10827 saved_char
= *input_line_pointer
;
10828 *input_line_pointer
= 0;
10830 ext
= strchr (name
, '+');
10833 optlen
= ext
- name
;
10835 optlen
= strlen (name
);
10837 /* Skip the first "all" entry. */
10838 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10839 if (strlen (opt
->name
) == optlen
10840 && strncmp (name
, opt
->name
, optlen
) == 0)
10842 mcpu_cpu_opt
= &opt
->value
;
10844 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10847 cpu_variant
= *mcpu_cpu_opt
;
10849 *input_line_pointer
= saved_char
;
10850 demand_empty_rest_of_line ();
10854 as_bad (_("unknown architecture `%s'\n"), name
);
10855 *input_line_pointer
= saved_char
;
10856 ignore_rest_of_line ();
10859 /* Parse a .arch_extension directive. */
10862 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10865 char *ext
= input_line_pointer
;
10867 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10868 saved_char
= *input_line_pointer
;
10869 *input_line_pointer
= 0;
10871 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10874 cpu_variant
= *mcpu_cpu_opt
;
10876 *input_line_pointer
= saved_char
;
10877 demand_empty_rest_of_line ();
10880 /* Copy symbol information. */
10883 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10885 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10889 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10890 This is needed so AArch64 specific st_other values can be independently
10891 specified for an IFUNC resolver (that is called by the dynamic linker)
10892 and the symbol it resolves (aliased to the resolver). In particular,
10893 if a function symbol has special st_other value set via directives,
10894 then attaching an IFUNC resolver to that symbol should not override
10895 the st_other setting. Requiring the directive on the IFUNC resolver
10896 symbol would be unexpected and problematic in C code, where the two
10897 symbols appear as two independent function declarations. */
10900 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10902 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10903 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10904 /* If size is unset, copy size from src. Because we don't track whether
10905 .size has been used, we can't differentiate .size dest, 0 from the case
10906 where dest's size is unset. */
10907 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10911 destelf
->size
= XNEW (expressionS
);
10912 *destelf
->size
= *srcelf
->size
;
10914 S_SET_SIZE (dest
, S_GET_SIZE (src
));