1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
165 data fields contain the following information:
168 A mask of register types that would have been acceptable as bare
169 operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
170 is set if a general parsing error occured for an operand (that is,
171 an error not related to registers, and having no error string).
174 A mask of register types that would have been acceptable inside
175 a register list. In addition, SEF_IN_REGLIST is set if the
176 operand contained a '{' and if we got to the point of trying
177 to parse a register inside a list.
180 The mask associated with the register that was actually seen, or 0
181 if none. A nonzero value describes a register inside a register
182 list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
185 The idea is that stringless errors from multiple opcode templates can
186 be ORed together to give a summary of the available alternatives. */
187 #define SEF_DEFAULT_ERROR (1U << 31)
188 #define SEF_IN_REGLIST (1U << 31)
190 /* Diagnostics inline function utilities.
192 These are lightweight utilities which should only be called by parse_operands
193 and other parsers. GAS processes each assembly line by parsing it against
194 instruction template(s), in the case of multiple templates (for the same
195 mnemonic name), those templates are tried one by one until one succeeds or
196 all fail. An assembly line may fail a few templates before being
197 successfully parsed; an error saved here in most cases is not a user error
198 but an error indicating the current template is not the right template.
199 Therefore it is very important that errors can be saved at a low cost during
200 the parsing; we don't want to slow down the whole parsing by recording
201 non-user errors in detail.
203 Remember that the objective is to help GAS pick up the most appropriate
204 error message in the case of multiple templates, e.g. FMOV which has 8
210 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
211 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
217 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
224 inst
.parsing_error
.index
= -1;
225 inst
.parsing_error
.kind
= kind
;
226 inst
.parsing_error
.error
= error
;
230 set_recoverable_error (const char *error
)
232 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
235 /* Use the DESC field of the corresponding aarch64_operand entry to compose
236 the error message. */
238 set_default_error (void)
240 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
241 inst
.parsing_error
.data
[0].i
= SEF_DEFAULT_ERROR
;
245 set_expected_error (unsigned int flags
)
247 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
248 inst
.parsing_error
.data
[0].i
= flags
;
252 set_syntax_error (const char *error
)
254 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
258 set_first_syntax_error (const char *error
)
261 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
265 set_fatal_syntax_error (const char *error
)
267 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
270 /* Return value for certain parsers when the parsing fails; those parsers
271 return the information of the parsed result, e.g. register number, on
273 #define PARSE_FAIL -1
275 /* This is an invalid condition code that means no conditional field is
277 #define COND_ALWAYS 0x10
281 const char *template;
288 bfd_reloc_code_real_type reloc
;
291 /* Macros to define the register types and masks for the purpose
294 #undef AARCH64_REG_TYPES
295 #define AARCH64_REG_TYPES \
296 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
297 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
298 BASIC_REG_TYPE(SP_32) /* wsp */ \
299 BASIC_REG_TYPE(SP_64) /* sp */ \
300 BASIC_REG_TYPE(Z_32) /* wzr */ \
301 BASIC_REG_TYPE(Z_64) /* xzr */ \
302 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
303 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
304 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
305 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
306 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
307 BASIC_REG_TYPE(VN) /* v[0-31] */ \
308 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
309 BASIC_REG_TYPE(PN) /* p[0-15] */ \
310 BASIC_REG_TYPE(ZA) /* za */ \
311 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
312 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
313 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
314 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
315 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
316 /* Typecheck: same, plus SVE registers. */ \
317 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
319 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
320 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
322 /* Typecheck: same, plus SVE registers. */ \
323 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
324 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
326 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
327 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
329 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
330 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
331 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
332 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
333 /* Typecheck: any [BHSDQ]P FP. */ \
334 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
335 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
336 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
337 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
338 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
339 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
340 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
341 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
342 be used for SVE instructions, since Zn and Pn are valid symbols \
343 in other contexts. */ \
344 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
345 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
346 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
347 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
348 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
349 | REG_TYPE(ZN) | REG_TYPE(PN)) \
350 /* Any integer register; used for error messages only. */ \
351 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
352 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
353 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
354 /* Any vector register. */ \
355 MULTI_REG_TYPE(VZ, REG_TYPE(VN) | REG_TYPE(ZN)) \
356 /* An SVE vector or predicate register. */ \
357 MULTI_REG_TYPE(ZP, REG_TYPE(ZN) | REG_TYPE(PN)) \
358 /* Any vector or predicate register. */ \
359 MULTI_REG_TYPE(VZP, REG_TYPE(VN) | REG_TYPE(ZN) | REG_TYPE(PN)) \
360 /* The whole of ZA or a single tile. */ \
361 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
362 /* A horizontal or vertical slice of a ZA tile. */ \
363 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
364 /* Pseudo type to mark the end of the enumerator sequence. */ \
367 #undef BASIC_REG_TYPE
368 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
369 #undef MULTI_REG_TYPE
370 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
372 #define END_REG_TYPE(T) BASIC_REG_TYPE(T)
374 /* Register type enumerators. */
375 typedef enum aarch64_reg_type_
377 /* A list of REG_TYPE_*. */
381 #undef BASIC_REG_TYPE
382 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
384 #define REG_TYPE(T) (1 << REG_TYPE_##T)
385 #undef MULTI_REG_TYPE
386 #define MULTI_REG_TYPE(T,V) V,
388 #define END_REG_TYPE(T) 0
390 /* Structure for a hash table entry for a register. */
394 unsigned char number
;
395 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
396 unsigned char builtin
;
399 /* Values indexed by aarch64_reg_type to assist the type checking. */
400 static const unsigned reg_type_masks
[] =
405 #undef BASIC_REG_TYPE
407 #undef MULTI_REG_TYPE
409 #undef AARCH64_REG_TYPES
411 /* We expected one of the registers in MASK to be specified. If a register
412 of some kind was specified, SEEN is a mask that contains that register,
413 otherwise it is zero.
415 If it is possible to provide a relatively pithy message that describes
416 the error exactly, return a string that does so, reporting the error
417 against "operand %d". Return null otherwise.
419 From a QoI perspective, any REG_TYPE_* that is passed as the first
420 argument to set_expected_reg_error should generally have its own message.
421 Providing messages for combinations of such REG_TYPE_*s can be useful if
422 it is possible to summarize the combination in a relatively natural way.
423 On the other hand, it seems better to avoid long lists of unrelated
427 get_reg_expected_msg (unsigned int mask
, unsigned int seen
)
429 /* First handle messages that use SEEN. */
430 if ((mask
& reg_type_masks
[REG_TYPE_ZAT
])
431 && (seen
& reg_type_masks
[REG_TYPE_ZATHV
]))
432 return N_("expected an unsuffixed ZA tile at operand %d");
434 if ((mask
& reg_type_masks
[REG_TYPE_ZATHV
])
435 && (seen
& reg_type_masks
[REG_TYPE_ZAT
]))
436 return N_("missing horizontal or vertical suffix at operand %d");
438 if ((mask
& reg_type_masks
[REG_TYPE_ZA
])
439 && (seen
& (reg_type_masks
[REG_TYPE_ZAT
]
440 | reg_type_masks
[REG_TYPE_ZATHV
])))
441 return N_("expected 'za' rather than a ZA tile at operand %d");
443 /* Integer, zero and stack registers. */
444 if (mask
== reg_type_masks
[REG_TYPE_R_64
])
445 return N_("expected a 64-bit integer register at operand %d");
446 if (mask
== reg_type_masks
[REG_TYPE_R_Z
])
447 return N_("expected an integer or zero register at operand %d");
448 if (mask
== reg_type_masks
[REG_TYPE_R_SP
])
449 return N_("expected an integer or stack pointer register at operand %d");
451 /* Floating-point and SIMD registers. */
452 if (mask
== reg_type_masks
[REG_TYPE_BHSDQ
])
453 return N_("expected a scalar SIMD or floating-point register"
455 if (mask
== reg_type_masks
[REG_TYPE_VN
])
456 return N_("expected an Advanced SIMD vector register at operand %d");
457 if (mask
== reg_type_masks
[REG_TYPE_ZN
])
458 return N_("expected an SVE vector register at operand %d");
459 if (mask
== reg_type_masks
[REG_TYPE_PN
])
460 return N_("expected an SVE predicate register at operand %d");
461 if (mask
== reg_type_masks
[REG_TYPE_VZ
])
462 return N_("expected a vector register at operand %d");
463 if (mask
== reg_type_masks
[REG_TYPE_ZP
])
464 return N_("expected an SVE vector or predicate register at operand %d");
465 if (mask
== reg_type_masks
[REG_TYPE_VZP
])
466 return N_("expected a vector or predicate register at operand %d");
468 /* ZA-related registers. */
469 if (mask
== reg_type_masks
[REG_TYPE_ZA
])
470 return N_("expected a ZA array vector at operand %d");
471 if (mask
== reg_type_masks
[REG_TYPE_ZA_ZAT
])
472 return N_("expected 'za' or a ZA tile at operand %d");
473 if (mask
== reg_type_masks
[REG_TYPE_ZAT
])
474 return N_("expected a ZA tile at operand %d");
475 if (mask
== reg_type_masks
[REG_TYPE_ZATHV
])
476 return N_("expected a ZA tile slice at operand %d");
478 /* Integer and vector combos. */
479 if (mask
== (reg_type_masks
[REG_TYPE_R_Z
] | reg_type_masks
[REG_TYPE_VN
]))
480 return N_("expected an integer register or Advanced SIMD vector register"
482 if (mask
== (reg_type_masks
[REG_TYPE_R_Z
] | reg_type_masks
[REG_TYPE_ZN
]))
483 return N_("expected an integer register or SVE vector register"
485 if (mask
== (reg_type_masks
[REG_TYPE_R_Z
] | reg_type_masks
[REG_TYPE_VZ
]))
486 return N_("expected an integer or vector register at operand %d");
487 if (mask
== (reg_type_masks
[REG_TYPE_R_Z
] | reg_type_masks
[REG_TYPE_PN
]))
488 return N_("expected an integer or predicate register at operand %d");
489 if (mask
== (reg_type_masks
[REG_TYPE_R_Z
] | reg_type_masks
[REG_TYPE_VZP
]))
490 return N_("expected an integer, vector or predicate register"
493 /* SVE and SME combos. */
494 if (mask
== (reg_type_masks
[REG_TYPE_ZN
] | reg_type_masks
[REG_TYPE_ZATHV
]))
495 return N_("expected an SVE vector register or ZA tile slice"
501 /* Record that we expected a register of type TYPE but didn't see one.
502 REG is the register that we actually saw, or null if we didn't see a
503 recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
504 contents of a register list, otherwise it is zero. */
507 set_expected_reg_error (aarch64_reg_type type
, const reg_entry
*reg
,
510 assert (flags
== 0 || flags
== SEF_IN_REGLIST
);
511 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
512 if (flags
& SEF_IN_REGLIST
)
513 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
] | flags
;
515 inst
.parsing_error
.data
[0].i
= reg_type_masks
[type
];
517 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
520 /* Record that we expected a register list containing registers of type TYPE,
521 but didn't see the opening '{'. If we saw a register instead, REG is the
522 register that we saw, otherwise it is null. */
525 set_expected_reglist_error (aarch64_reg_type type
, const reg_entry
*reg
)
527 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
528 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
];
530 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
533 /* Some well known registers that we refer to directly elsewhere. */
537 /* Instructions take 4 bytes in the object file. */
540 static htab_t aarch64_ops_hsh
;
541 static htab_t aarch64_cond_hsh
;
542 static htab_t aarch64_shift_hsh
;
543 static htab_t aarch64_sys_regs_hsh
;
544 static htab_t aarch64_pstatefield_hsh
;
545 static htab_t aarch64_sys_regs_ic_hsh
;
546 static htab_t aarch64_sys_regs_dc_hsh
;
547 static htab_t aarch64_sys_regs_at_hsh
;
548 static htab_t aarch64_sys_regs_tlbi_hsh
;
549 static htab_t aarch64_sys_regs_sr_hsh
;
550 static htab_t aarch64_reg_hsh
;
551 static htab_t aarch64_barrier_opt_hsh
;
552 static htab_t aarch64_nzcv_hsh
;
553 static htab_t aarch64_pldop_hsh
;
554 static htab_t aarch64_hint_opt_hsh
;
556 /* Stuff needed to resolve the label ambiguity
565 static symbolS
*last_label_seen
;
567 /* Literal pool structure. Held on a per-section
568 and per-sub-section basis. */
570 #define MAX_LITERAL_POOL_SIZE 1024
571 typedef struct literal_expression
574 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
575 LITTLENUM_TYPE
* bignum
;
576 } literal_expression
;
578 typedef struct literal_pool
580 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
581 unsigned int next_free_entry
;
587 struct literal_pool
*next
;
590 /* Pointer to a linked list of literal pools. */
591 static literal_pool
*list_of_pools
= NULL
;
595 /* This array holds the chars that always start a comment. If the
596 pre-processor is disabled, these aren't very useful. */
597 const char comment_chars
[] = "";
599 /* This array holds the chars that only start a comment at the beginning of
600 a line. If the line seems to have the form '# 123 filename'
601 .line and .file directives will appear in the pre-processed output. */
602 /* Note that input_file.c hand checks for '#' at the beginning of the
603 first line of the input file. This is because the compiler outputs
604 #NO_APP at the beginning of its output. */
605 /* Also note that comments like this one will always work. */
606 const char line_comment_chars
[] = "#";
608 const char line_separator_chars
[] = ";";
610 /* Chars that can be used to separate mant
611 from exp in floating point numbers. */
612 const char EXP_CHARS
[] = "eE";
614 /* Chars that mean this number is a floating point constant. */
618 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
620 /* Prefix character that indicates the start of an immediate value. */
621 #define is_immediate_prefix(C) ((C) == '#')
623 /* Separator character handling. */
625 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
628 skip_past_char (char **str
, char c
)
639 #define skip_past_comma(str) skip_past_char (str, ',')
641 /* Arithmetic expressions (possibly involving symbols). */
643 static bool in_aarch64_get_expression
= false;
645 /* Third argument to aarch64_get_expression. */
646 #define GE_NO_PREFIX false
647 #define GE_OPT_PREFIX true
649 /* Fourth argument to aarch64_get_expression. */
650 #define ALLOW_ABSENT false
651 #define REJECT_ABSENT true
653 /* Return TRUE if the string pointed by *STR is successfully parsed
654 as an valid expression; *EP will be filled with the information of
655 such an expression. Otherwise return FALSE.
657 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
658 If REJECT_ABSENT is true then trat missing expressions as an error. */
661 aarch64_get_expression (expressionS
* ep
,
663 bool allow_immediate_prefix
,
668 bool prefix_present
= false;
670 if (allow_immediate_prefix
)
672 if (is_immediate_prefix (**str
))
675 prefix_present
= true;
679 memset (ep
, 0, sizeof (expressionS
));
681 save_in
= input_line_pointer
;
682 input_line_pointer
= *str
;
683 in_aarch64_get_expression
= true;
684 seg
= expression (ep
);
685 in_aarch64_get_expression
= false;
687 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
689 /* We found a bad expression in md_operand(). */
690 *str
= input_line_pointer
;
691 input_line_pointer
= save_in
;
692 if (prefix_present
&& ! error_p ())
693 set_fatal_syntax_error (_("bad expression"));
695 set_first_syntax_error (_("bad expression"));
700 if (seg
!= absolute_section
701 && seg
!= text_section
702 && seg
!= data_section
703 && seg
!= bss_section
704 && seg
!= undefined_section
)
706 set_syntax_error (_("bad segment"));
707 *str
= input_line_pointer
;
708 input_line_pointer
= save_in
;
715 *str
= input_line_pointer
;
716 input_line_pointer
= save_in
;
720 /* Turn a string in input_line_pointer into a floating point constant
721 of type TYPE, and store the appropriate bytes in *LITP. The number
722 of LITTLENUMS emitted is stored in *SIZEP. An error message is
723 returned, or NULL on OK. */
726 md_atof (int type
, char *litP
, int *sizeP
)
728 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
731 /* We handle all bad expressions here, so that we can report the faulty
732 instruction in the error message. */
734 md_operand (expressionS
* exp
)
736 if (in_aarch64_get_expression
)
737 exp
->X_op
= O_illegal
;
740 /* Immediate values. */
742 /* Errors may be set multiple times during parsing or bit encoding
743 (particularly in the Neon bits), but usually the earliest error which is set
744 will be the most meaningful. Avoid overwriting it with later (cascading)
745 errors by calling this function. */
748 first_error (const char *error
)
751 set_syntax_error (error
);
754 /* Similar to first_error, but this function accepts formatted error
757 first_error_fmt (const char *format
, ...)
762 /* N.B. this single buffer will not cause error messages for different
763 instructions to pollute each other; this is because at the end of
764 processing of each assembly line, error message if any will be
765 collected by as_bad. */
766 static char buffer
[size
];
770 int ret ATTRIBUTE_UNUSED
;
771 va_start (args
, format
);
772 ret
= vsnprintf (buffer
, size
, format
, args
);
773 know (ret
<= size
- 1 && ret
>= 0);
775 set_syntax_error (buffer
);
779 /* Internal helper routine converting a vector_type_el structure *VECTYPE
780 to a corresponding operand qualifier. */
782 static inline aarch64_opnd_qualifier_t
783 vectype_to_qualifier (const struct vector_type_el
*vectype
)
785 /* Element size in bytes indexed by vector_el_type. */
786 const unsigned char ele_size
[5]
788 const unsigned int ele_base
[5] =
790 AARCH64_OPND_QLF_V_4B
,
791 AARCH64_OPND_QLF_V_2H
,
792 AARCH64_OPND_QLF_V_2S
,
793 AARCH64_OPND_QLF_V_1D
,
794 AARCH64_OPND_QLF_V_1Q
797 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
798 goto vectype_conversion_fail
;
800 if (vectype
->type
== NT_zero
)
801 return AARCH64_OPND_QLF_P_Z
;
802 if (vectype
->type
== NT_merge
)
803 return AARCH64_OPND_QLF_P_M
;
805 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
807 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
809 /* Special case S_4B. */
810 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
811 return AARCH64_OPND_QLF_S_4B
;
813 /* Special case S_2H. */
814 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
815 return AARCH64_OPND_QLF_S_2H
;
817 /* Vector element register. */
818 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
822 /* Vector register. */
823 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
826 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
827 goto vectype_conversion_fail
;
829 /* The conversion is by calculating the offset from the base operand
830 qualifier for the vector type. The operand qualifiers are regular
831 enough that the offset can established by shifting the vector width by
832 a vector-type dependent amount. */
834 if (vectype
->type
== NT_b
)
836 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
838 else if (vectype
->type
>= NT_d
)
843 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
844 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
845 && offset
<= AARCH64_OPND_QLF_V_1Q
);
849 vectype_conversion_fail
:
850 first_error (_("bad vector arrangement type"));
851 return AARCH64_OPND_QLF_NIL
;
854 /* Register parsing. */
856 /* Generic register parser which is called by other specialized
858 CCP points to what should be the beginning of a register name.
859 If it is indeed a valid register name, advance CCP over it and
860 return the reg_entry structure; otherwise return NULL.
861 It does not issue diagnostics. */
864 parse_reg (char **ccp
)
870 #ifdef REGISTER_PREFIX
871 if (*start
!= REGISTER_PREFIX
)
877 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
882 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
884 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
893 /* Return the operand qualifier associated with all uses of REG, or
894 AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
895 that qualifiers don't apply to REG or that qualifiers are added
898 static aarch64_opnd_qualifier_t
899 inherent_reg_qualifier (const reg_entry
*reg
)
906 return AARCH64_OPND_QLF_W
;
911 return AARCH64_OPND_QLF_X
;
918 return AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
921 return AARCH64_OPND_QLF_NIL
;
925 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
928 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
930 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
933 /* Try to parse a base or offset register. Allow SVE base and offset
934 registers if REG_TYPE includes SVE registers. Return the register
935 entry on success, setting *QUALIFIER to the register qualifier.
936 Return null otherwise.
938 Note that this function does not issue any diagnostics. */
940 static const reg_entry
*
941 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
942 aarch64_opnd_qualifier_t
*qualifier
)
945 const reg_entry
*reg
= parse_reg (&str
);
953 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
956 switch (TOLOWER (str
[1]))
959 *qualifier
= AARCH64_OPND_QLF_S_S
;
962 *qualifier
= AARCH64_OPND_QLF_S_D
;
971 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
973 *qualifier
= inherent_reg_qualifier (reg
);
982 /* Try to parse a base or offset register. Return the register entry
983 on success, setting *QUALIFIER to the register qualifier. Return null
986 Note that this function does not issue any diagnostics. */
988 static const reg_entry
*
989 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
991 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
994 /* Parse the qualifier of a vector register or vector element of type
995 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
996 succeeds; otherwise return FALSE.
998 Accept only one occurrence of:
999 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
1002 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
1003 struct vector_type_el
*parsed_type
, char **str
)
1007 unsigned element_size
;
1008 enum vector_el_type type
;
1011 gas_assert (*ptr
== '.');
1014 if (reg_type
!= REG_TYPE_VN
|| !ISDIGIT (*ptr
))
1019 width
= strtoul (ptr
, &ptr
, 10);
1020 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
1022 first_error_fmt (_("bad size %d in vector width specifier"), width
);
1027 switch (TOLOWER (*ptr
))
1046 if (reg_type
!= REG_TYPE_VN
|| width
== 1)
1055 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
1057 first_error (_("missing element size"));
1060 if (width
!= 0 && width
* element_size
!= 64
1061 && width
* element_size
!= 128
1062 && !(width
== 2 && element_size
== 16)
1063 && !(width
== 4 && element_size
== 8))
1066 ("invalid element size %d and vector size combination %c"),
1072 parsed_type
->type
= type
;
1073 parsed_type
->width
= width
;
1074 parsed_type
->element_size
= element_size
;
1081 /* *STR contains an SVE zero/merge predication suffix. Parse it into
1082 *PARSED_TYPE and point *STR at the end of the suffix. */
1085 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
1090 gas_assert (*ptr
== '/');
1092 switch (TOLOWER (*ptr
))
1095 parsed_type
->type
= NT_zero
;
1098 parsed_type
->type
= NT_merge
;
1101 if (*ptr
!= '\0' && *ptr
!= ',')
1102 first_error_fmt (_("unexpected character `%c' in predication type"),
1105 first_error (_("missing predication type"));
1108 parsed_type
->width
= 0;
1113 /* Return true if CH is a valid suffix character for registers of
1117 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1130 return ch
== '.' || ch
== '/';
1137 /* Parse an index expression at *STR, storing it in *IMM on success. */
1140 parse_index_expression (char **str
, int64_t *imm
)
1144 aarch64_get_expression (&exp
, str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1145 if (exp
.X_op
!= O_constant
)
1147 first_error (_("constant expression required"));
1150 *imm
= exp
.X_add_number
;
1154 /* Parse a register of the type TYPE.
1156 Return null if the string pointed to by *CCP is not a valid register
1157 name or the parsed register is not of TYPE.
1159 Otherwise return the register, and optionally return the register
1160 shape and element index information in *TYPEINFO.
1162 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1164 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1167 FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
1168 an operand that we can be confident that it is a good match. */
1170 #define PTR_IN_REGLIST (1U << 0)
1171 #define PTR_FULL_REG (1U << 1)
1172 #define PTR_GOOD_MATCH (1U << 2)
1174 static const reg_entry
*
1175 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1176 struct vector_type_el
*typeinfo
, unsigned int flags
)
1179 bool isalpha
= ISALPHA (*str
);
1180 const reg_entry
*reg
= parse_reg (&str
);
1181 struct vector_type_el atype
;
1182 struct vector_type_el parsetype
;
1183 bool is_typed_vecreg
= false;
1184 unsigned int err_flags
= (flags
& PTR_IN_REGLIST
) ? SEF_IN_REGLIST
: 0;
1187 atype
.type
= NT_invtype
;
1189 atype
.element_size
= 0;
1196 if (!isalpha
&& (flags
& PTR_IN_REGLIST
))
1197 set_fatal_syntax_error (_("syntax error in register list"));
1198 else if (flags
& PTR_GOOD_MATCH
)
1199 set_fatal_syntax_error (NULL
);
1201 set_expected_reg_error (type
, reg
, err_flags
);
1205 if (! aarch64_check_reg_type (reg
, type
))
1207 DEBUG_TRACE ("reg type check failed");
1208 if (flags
& PTR_GOOD_MATCH
)
1209 set_fatal_syntax_error (NULL
);
1211 set_expected_reg_error (type
, reg
, err_flags
);
1216 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1220 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1222 if ((reg
->type
== REG_TYPE_ZAT
1223 || reg
->type
== REG_TYPE_ZATH
1224 || reg
->type
== REG_TYPE_ZATV
)
1225 && reg
->number
* 8 >= parsetype
.element_size
)
1227 set_syntax_error (_("ZA tile number out of range"));
1233 if (!parse_predication_for_operand (&parsetype
, &str
))
1237 /* Register if of the form Vn.[bhsdq]. */
1238 is_typed_vecreg
= true;
1240 if (type
!= REG_TYPE_VN
)
1242 /* The width is always variable; we don't allow an integer width
1244 gas_assert (parsetype
.width
== 0);
1245 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1247 else if (parsetype
.width
== 0)
1248 /* Expect index. In the new scheme we cannot have
1249 Vn.[bhsdq] represent a scalar. Therefore any
1250 Vn.[bhsdq] should have an index following it.
1251 Except in reglists of course. */
1252 atype
.defined
|= NTA_HASINDEX
;
1254 atype
.defined
|= NTA_HASTYPE
;
1256 atype
.type
= parsetype
.type
;
1257 atype
.width
= parsetype
.width
;
1260 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1262 /* Reject Sn[index] syntax. */
1263 if (!is_typed_vecreg
)
1265 first_error (_("this type of register can't be indexed"));
1269 if (flags
& PTR_IN_REGLIST
)
1271 first_error (_("index not allowed inside register list"));
1275 atype
.defined
|= NTA_HASINDEX
;
1277 if (!parse_index_expression (&str
, &atype
.index
))
1280 if (! skip_past_char (&str
, ']'))
1283 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1285 /* Indexed vector register expected. */
1286 first_error (_("indexed vector register expected"));
1290 /* A vector reg Vn should be typed or indexed. */
1291 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1293 first_error (_("invalid use of vector register"));
1306 Return the register on success; return null otherwise.
1308 If this is a NEON vector register with additional type information, fill
1309 in the struct pointed to by VECTYPE (if non-NULL).
1311 This parser does not handle register lists. */
1313 static const reg_entry
*
1314 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1315 struct vector_type_el
*vectype
)
1317 return parse_typed_reg (ccp
, type
, vectype
, 0);
1321 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1323 return (e1
.type
== e2
.type
1324 && e1
.defined
== e2
.defined
1325 && e1
.width
== e2
.width
1326 && e1
.element_size
== e2
.element_size
1327 && e1
.index
== e2
.index
);
1330 /* This function parses a list of vector registers of type TYPE.
1331 On success, it returns the parsed register list information in the
1332 following encoded format:
1334 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1335 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1337 The information of the register shape and/or index is returned in
1340 It returns PARSE_FAIL if the register list is invalid.
1342 The list contains one to four registers.
1343 Each register can be one of:
1346 All <T> should be identical.
1347 All <index> should be identical.
1348 There are restrictions on <Vt> numbers which are checked later
1349 (by reg_list_valid_p). */
1352 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1353 struct vector_type_el
*vectype
)
1357 struct vector_type_el typeinfo
, typeinfo_first
;
1363 bool expect_index
= false;
1364 unsigned int ptr_flags
= PTR_IN_REGLIST
;
1368 set_expected_reglist_error (type
, parse_reg (&str
));
1374 typeinfo_first
.defined
= 0;
1375 typeinfo_first
.type
= NT_invtype
;
1376 typeinfo_first
.width
= -1;
1377 typeinfo_first
.element_size
= 0;
1378 typeinfo_first
.index
= 0;
1387 str
++; /* skip over '-' */
1390 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1394 set_first_syntax_error (_("invalid vector register in list"));
1399 /* reject [bhsd]n */
1400 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1402 set_first_syntax_error (_("invalid scalar register in list"));
1407 if (typeinfo
.defined
& NTA_HASINDEX
)
1408 expect_index
= true;
1412 if (val
< val_range
)
1414 set_first_syntax_error
1415 (_("invalid range in vector register list"));
1424 typeinfo_first
= typeinfo
;
1425 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1427 set_first_syntax_error
1428 (_("type mismatch in vector register list"));
1433 for (i
= val_range
; i
<= val
; i
++)
1435 ret_val
|= i
<< (5 * nb_regs
);
1439 ptr_flags
|= PTR_GOOD_MATCH
;
1441 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1443 skip_whitespace (str
);
1446 set_first_syntax_error (_("end of vector register list not found"));
1451 skip_whitespace (str
);
1455 if (skip_past_char (&str
, '['))
1457 if (!parse_index_expression (&str
, &typeinfo_first
.index
))
1459 if (! skip_past_char (&str
, ']'))
1464 set_first_syntax_error (_("expected index"));
1471 set_first_syntax_error (_("too many registers in vector register list"));
1474 else if (nb_regs
== 0)
1476 set_first_syntax_error (_("empty vector register list"));
1482 *vectype
= typeinfo_first
;
1484 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1487 /* Directives: register aliases. */
1490 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1495 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1498 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1501 /* Only warn about a redefinition if it's not defined as the
1503 else if (new->number
!= number
|| new->type
!= type
)
1504 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1509 name
= xstrdup (str
);
1510 new = XNEW (reg_entry
);
1513 new->number
= number
;
1515 new->builtin
= false;
1517 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1522 /* Look for the .req directive. This is of the form:
1524 new_register_name .req existing_register_name
1526 If we find one, or if it looks sufficiently like one that we want to
1527 handle any error here, return TRUE. Otherwise return FALSE. */
1530 create_register_alias (char *newname
, char *p
)
1532 const reg_entry
*old
;
1533 char *oldname
, *nbuf
;
1536 /* The input scrubber ensures that whitespace after the mnemonic is
1537 collapsed to single spaces. */
1539 if (!startswith (oldname
, " .req "))
1543 if (*oldname
== '\0')
1546 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1549 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1553 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1554 the desired alias name, and p points to its end. If not, then
1555 the desired alias name is in the global original_case_string. */
1556 #ifdef TC_CASE_SENSITIVE
1559 newname
= original_case_string
;
1560 nlen
= strlen (newname
);
1563 nbuf
= xmemdup0 (newname
, nlen
);
1565 /* Create aliases under the new name as stated; an all-lowercase
1566 version of the new name; and an all-uppercase version of the new
1568 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1570 for (p
= nbuf
; *p
; p
++)
1573 if (strncmp (nbuf
, newname
, nlen
))
1575 /* If this attempt to create an additional alias fails, do not bother
1576 trying to create the all-lower case alias. We will fail and issue
1577 a second, duplicate error message. This situation arises when the
1578 programmer does something like:
1581 The second .req creates the "Foo" alias but then fails to create
1582 the artificial FOO alias because it has already been created by the
1584 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1591 for (p
= nbuf
; *p
; p
++)
1594 if (strncmp (nbuf
, newname
, nlen
))
1595 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1602 /* Should never be called, as .req goes between the alias and the
1603 register name, not at the beginning of the line. */
1605 s_req (int a ATTRIBUTE_UNUSED
)
1607 as_bad (_("invalid syntax for .req directive"));
1610 /* The .unreq directive deletes an alias which was previously defined
1611 by .req. For example:
1617 s_unreq (int a ATTRIBUTE_UNUSED
)
1622 name
= input_line_pointer
;
1623 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1624 saved_char
= *input_line_pointer
;
1625 *input_line_pointer
= 0;
1628 as_bad (_("invalid syntax for .unreq directive"));
1631 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1634 as_bad (_("unknown register alias '%s'"), name
);
1635 else if (reg
->builtin
)
1636 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1643 str_hash_delete (aarch64_reg_hsh
, name
);
1644 free ((char *) reg
->name
);
1647 /* Also locate the all upper case and all lower case versions.
1648 Do not complain if we cannot find one or the other as it
1649 was probably deleted above. */
1651 nbuf
= strdup (name
);
1652 for (p
= nbuf
; *p
; p
++)
1654 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1657 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1658 free ((char *) reg
->name
);
1662 for (p
= nbuf
; *p
; p
++)
1664 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1667 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1668 free ((char *) reg
->name
);
1676 *input_line_pointer
= saved_char
;
1677 demand_empty_rest_of_line ();
1680 /* Directives: Instruction set selection. */
1682 #if defined OBJ_ELF || defined OBJ_COFF
1683 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1684 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1685 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1686 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1688 /* Create a new mapping symbol for the transition to STATE. */
1691 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1694 const char *symname
;
1701 type
= BSF_NO_FLAGS
;
1705 type
= BSF_NO_FLAGS
;
1711 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1712 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1714 /* Save the mapping symbols for future reference. Also check that
1715 we do not place two mapping symbols at the same offset within a
1716 frag. We'll handle overlap between frags in
1717 check_mapping_symbols.
1719 If .fill or other data filling directive generates zero sized data,
1720 the mapping symbol for the following code will have the same value
1721 as the one generated for the data filling directive. In this case,
1722 we replace the old symbol with the new one at the same address. */
1725 if (frag
->tc_frag_data
.first_map
!= NULL
)
1727 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1728 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1731 frag
->tc_frag_data
.first_map
= symbolP
;
1733 if (frag
->tc_frag_data
.last_map
!= NULL
)
1735 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1736 S_GET_VALUE (symbolP
));
1737 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1738 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1741 frag
->tc_frag_data
.last_map
= symbolP
;
1744 /* We must sometimes convert a region marked as code to data during
1745 code alignment, if an odd number of bytes have to be padded. The
1746 code mapping symbol is pushed to an aligned address. */
1749 insert_data_mapping_symbol (enum mstate state
,
1750 valueT value
, fragS
* frag
, offsetT bytes
)
1752 /* If there was already a mapping symbol, remove it. */
1753 if (frag
->tc_frag_data
.last_map
!= NULL
1754 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1755 frag
->fr_address
+ value
)
1757 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1761 know (frag
->tc_frag_data
.first_map
== symp
);
1762 frag
->tc_frag_data
.first_map
= NULL
;
1764 frag
->tc_frag_data
.last_map
= NULL
;
1765 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1768 make_mapping_symbol (MAP_DATA
, value
, frag
);
1769 make_mapping_symbol (state
, value
+ bytes
, frag
);
1772 static void mapping_state_2 (enum mstate state
, int max_chars
);
1774 /* Set the mapping state to STATE. Only call this when about to
1775 emit some STATE bytes to the file. */
1778 mapping_state (enum mstate state
)
1780 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1782 if (state
== MAP_INSN
)
1783 /* AArch64 instructions require 4-byte alignment. When emitting
1784 instructions into any section, record the appropriate section
1786 record_alignment (now_seg
, 2);
1788 if (mapstate
== state
)
1789 /* The mapping symbol has already been emitted.
1790 There is nothing else to do. */
1793 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1794 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1795 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1796 evaluated later in the next else. */
1798 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1800 /* Only add the symbol if the offset is > 0:
1801 if we're at the first frag, check it's size > 0;
1802 if we're not at the first frag, then for sure
1803 the offset is > 0. */
1804 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1805 const int add_symbol
= (frag_now
!= frag_first
)
1806 || (frag_now_fix () > 0);
1809 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1813 mapping_state_2 (state
, 0);
1816 /* Same as mapping_state, but MAX_CHARS bytes have already been
1817 allocated. Put the mapping symbol that far back. */
1820 mapping_state_2 (enum mstate state
, int max_chars
)
1822 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1824 if (!SEG_NORMAL (now_seg
))
1827 if (mapstate
== state
)
1828 /* The mapping symbol has already been emitted.
1829 There is nothing else to do. */
1832 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1833 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1836 #define mapping_state(x) /* nothing */
1837 #define mapping_state_2(x, y) /* nothing */
1840 /* Directives: sectioning and alignment. */
1843 s_bss (int ignore ATTRIBUTE_UNUSED
)
1845 /* We don't support putting frags in the BSS segment, we fake it by
1846 marking in_bss, then looking at s_skip for clues. */
1847 subseg_set (bss_section
, 0);
1848 demand_empty_rest_of_line ();
1849 mapping_state (MAP_DATA
);
1853 s_even (int ignore ATTRIBUTE_UNUSED
)
1855 /* Never make frag if expect extra pass. */
1857 frag_align (1, 0, 0);
1859 record_alignment (now_seg
, 1);
1861 demand_empty_rest_of_line ();
1864 /* Directives: Literal pools. */
1866 static literal_pool
*
1867 find_literal_pool (int size
)
1871 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1873 if (pool
->section
== now_seg
1874 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1881 static literal_pool
*
1882 find_or_make_literal_pool (int size
)
1884 /* Next literal pool ID number. */
1885 static unsigned int latest_pool_num
= 1;
1888 pool
= find_literal_pool (size
);
1892 /* Create a new pool. */
1893 pool
= XNEW (literal_pool
);
1897 /* Currently we always put the literal pool in the current text
1898 section. If we were generating "small" model code where we
1899 knew that all code and initialised data was within 1MB then
1900 we could output literals to mergeable, read-only data
1903 pool
->next_free_entry
= 0;
1904 pool
->section
= now_seg
;
1905 pool
->sub_section
= now_subseg
;
1907 pool
->next
= list_of_pools
;
1908 pool
->symbol
= NULL
;
1910 /* Add it to the list. */
1911 list_of_pools
= pool
;
1914 /* New pools, and emptied pools, will have a NULL symbol. */
1915 if (pool
->symbol
== NULL
)
1917 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1918 &zero_address_frag
, 0);
1919 pool
->id
= latest_pool_num
++;
1926 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1927 Return TRUE on success, otherwise return FALSE. */
1929 add_to_lit_pool (expressionS
*exp
, int size
)
1934 pool
= find_or_make_literal_pool (size
);
1936 /* Check if this literal value is already in the pool. */
1937 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1939 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1941 if ((litexp
->X_op
== exp
->X_op
)
1942 && (exp
->X_op
== O_constant
)
1943 && (litexp
->X_add_number
== exp
->X_add_number
)
1944 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1947 if ((litexp
->X_op
== exp
->X_op
)
1948 && (exp
->X_op
== O_symbol
)
1949 && (litexp
->X_add_number
== exp
->X_add_number
)
1950 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1951 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1955 /* Do we need to create a new entry? */
1956 if (entry
== pool
->next_free_entry
)
1958 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1960 set_syntax_error (_("literal pool overflow"));
1964 pool
->literals
[entry
].exp
= *exp
;
1965 pool
->next_free_entry
+= 1;
1966 if (exp
->X_op
== O_big
)
1968 /* PR 16688: Bignums are held in a single global array. We must
1969 copy and preserve that value now, before it is overwritten. */
1970 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1972 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1973 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1976 pool
->literals
[entry
].bignum
= NULL
;
1979 exp
->X_op
= O_symbol
;
1980 exp
->X_add_number
= ((int) entry
) * size
;
1981 exp
->X_add_symbol
= pool
->symbol
;
1986 /* Can't use symbol_new here, so have to create a symbol and then at
1987 a later date assign it a value. That's what these functions do. */
1990 symbol_locate (symbolS
* symbolP
,
1991 const char *name
,/* It is copied, the caller can modify. */
1992 segT segment
, /* Segment identifier (SEG_<something>). */
1993 valueT valu
, /* Symbol value. */
1994 fragS
* frag
) /* Associated fragment. */
1997 char *preserved_copy_of_name
;
1999 name_length
= strlen (name
) + 1; /* +1 for \0. */
2000 obstack_grow (¬es
, name
, name_length
);
2001 preserved_copy_of_name
= obstack_finish (¬es
);
2003 #ifdef tc_canonicalize_symbol_name
2004 preserved_copy_of_name
=
2005 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2008 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2010 S_SET_SEGMENT (symbolP
, segment
);
2011 S_SET_VALUE (symbolP
, valu
);
2012 symbol_clear_list_pointers (symbolP
);
2014 symbol_set_frag (symbolP
, frag
);
2016 /* Link to end of symbol chain. */
2018 extern int symbol_table_frozen
;
2020 if (symbol_table_frozen
)
2024 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
2026 obj_symbol_new_hook (symbolP
);
2028 #ifdef tc_symbol_new_hook
2029 tc_symbol_new_hook (symbolP
);
2033 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2034 #endif /* DEBUG_SYMS */
2039 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2046 for (align
= 2; align
<= 4; align
++)
2048 int size
= 1 << align
;
2050 pool
= find_literal_pool (size
);
2051 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
2054 /* Align pool as you have word accesses.
2055 Only make a frag if we have to. */
2057 frag_align (align
, 0, 0);
2059 mapping_state (MAP_DATA
);
2061 record_alignment (now_seg
, align
);
2063 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2065 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2066 (valueT
) frag_now_fix (), frag_now
);
2067 symbol_table_insert (pool
->symbol
);
2069 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2071 expressionS
* exp
= & pool
->literals
[entry
].exp
;
2073 if (exp
->X_op
== O_big
)
2075 /* PR 16688: Restore the global bignum value. */
2076 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
2077 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
2078 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2081 /* First output the expression in the instruction to the pool. */
2082 emit_expr (exp
, size
); /* .word|.xword */
2084 if (exp
->X_op
== O_big
)
2086 free (pool
->literals
[entry
].bignum
);
2087 pool
->literals
[entry
].bignum
= NULL
;
2091 /* Mark the pool as empty. */
2092 pool
->next_free_entry
= 0;
2093 pool
->symbol
= NULL
;
2097 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2098 /* Forward declarations for functions below, in the MD interface
2100 static struct reloc_table_entry
* find_reloc_table_entry (char **);
2102 /* Directives: Data. */
2103 /* N.B. the support for relocation suffix in this directive needs to be
2104 implemented properly. */
2107 s_aarch64_cons (int nbytes
)
2111 #ifdef md_flush_pending_output
2112 md_flush_pending_output ();
2115 if (is_it_end_of_statement ())
2117 demand_empty_rest_of_line ();
2121 #ifdef md_cons_align
2122 md_cons_align (nbytes
);
2125 mapping_state (MAP_DATA
);
2128 struct reloc_table_entry
*reloc
;
2132 if (exp
.X_op
!= O_symbol
)
2133 emit_expr (&exp
, (unsigned int) nbytes
);
2136 skip_past_char (&input_line_pointer
, '#');
2137 if (skip_past_char (&input_line_pointer
, ':'))
2139 reloc
= find_reloc_table_entry (&input_line_pointer
);
2141 as_bad (_("unrecognized relocation suffix"));
2143 as_bad (_("unimplemented relocation suffix"));
2144 ignore_rest_of_line ();
2148 emit_expr (&exp
, (unsigned int) nbytes
);
2151 while (*input_line_pointer
++ == ',');
2153 /* Put terminator back into stream. */
2154 input_line_pointer
--;
2155 demand_empty_rest_of_line ();
2160 /* Forward declarations for functions below, in the MD interface
2162 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2164 /* Mark symbol that it follows a variant PCS convention. */
2167 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2173 elf_symbol_type
*elfsym
;
2175 c
= get_symbol_name (&name
);
2177 as_bad (_("Missing symbol name in directive"));
2178 sym
= symbol_find_or_make (name
);
2179 restore_line_pointer (c
);
2180 demand_empty_rest_of_line ();
2181 bfdsym
= symbol_get_bfdsym (sym
);
2182 elfsym
= elf_symbol_from (bfdsym
);
2183 gas_assert (elfsym
);
2184 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2186 #endif /* OBJ_ELF */
2188 /* Output a 32-bit word, but mark as an instruction. */
2191 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2196 #ifdef md_flush_pending_output
2197 md_flush_pending_output ();
2200 if (is_it_end_of_statement ())
2202 demand_empty_rest_of_line ();
2206 /* Sections are assumed to start aligned. In executable section, there is no
2207 MAP_DATA symbol pending. So we only align the address during
2208 MAP_DATA --> MAP_INSN transition.
2209 For other sections, this is not guaranteed. */
2210 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2211 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2212 frag_align_code (2, 0);
2215 mapping_state (MAP_INSN
);
2221 if (exp
.X_op
!= O_constant
)
2223 as_bad (_("constant expression required"));
2224 ignore_rest_of_line ();
2228 if (target_big_endian
)
2230 unsigned int val
= exp
.X_add_number
;
2231 exp
.X_add_number
= SWAP_32 (val
);
2233 emit_expr (&exp
, INSN_SIZE
);
2236 while (*input_line_pointer
++ == ',');
2238 dwarf2_emit_insn (n
* INSN_SIZE
);
2240 /* Put terminator back into stream. */
2241 input_line_pointer
--;
2242 demand_empty_rest_of_line ();
2246 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2248 demand_empty_rest_of_line ();
2249 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2250 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2254 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2257 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2263 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2264 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2266 demand_empty_rest_of_line ();
2269 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2272 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2276 /* Since we're just labelling the code, there's no need to define a
2279 /* Make sure there is enough room in this frag for the following
2280 blr. This trick only works if the blr follows immediately after
2281 the .tlsdesc directive. */
2283 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2284 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2286 demand_empty_rest_of_line ();
2289 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2292 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2298 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2299 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2301 demand_empty_rest_of_line ();
2303 #endif /* OBJ_ELF */
2307 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2314 if (exp
.X_op
== O_symbol
)
2315 exp
.X_op
= O_secrel
;
2317 emit_expr (&exp
, 4);
2319 while (*input_line_pointer
++ == ',');
2321 input_line_pointer
--;
2322 demand_empty_rest_of_line ();
2326 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2330 exp
.X_op
= O_secrel
;
2331 exp
.X_add_symbol
= symbol
;
2332 exp
.X_add_number
= 0;
2333 emit_expr (&exp
, size
);
2337 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2344 if (exp
.X_op
== O_symbol
)
2345 exp
.X_op
= O_secidx
;
2347 emit_expr (&exp
, 2);
2349 while (*input_line_pointer
++ == ',');
2351 input_line_pointer
--;
2352 demand_empty_rest_of_line ();
2356 static void s_aarch64_arch (int);
2357 static void s_aarch64_cpu (int);
2358 static void s_aarch64_arch_extension (int);
2360 /* This table describes all the machine specific pseudo-ops the assembler
2361 has to support. The fields are:
2362 pseudo-op name without dot
2363 function to call to execute this pseudo-op
2364 Integer arg to pass to the function. */
2366 const pseudo_typeS md_pseudo_table
[] = {
2367 /* Never called because '.req' does not start a line. */
2369 {"unreq", s_unreq
, 0},
2371 {"even", s_even
, 0},
2372 {"ltorg", s_ltorg
, 0},
2373 {"pool", s_ltorg
, 0},
2374 {"cpu", s_aarch64_cpu
, 0},
2375 {"arch", s_aarch64_arch
, 0},
2376 {"arch_extension", s_aarch64_arch_extension
, 0},
2377 {"inst", s_aarch64_inst
, 0},
2378 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2380 {"tlsdescadd", s_tlsdescadd
, 0},
2381 {"tlsdesccall", s_tlsdesccall
, 0},
2382 {"tlsdescldr", s_tlsdescldr
, 0},
2383 {"variant_pcs", s_variant_pcs
, 0},
2385 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2386 {"word", s_aarch64_cons
, 4},
2387 {"long", s_aarch64_cons
, 4},
2388 {"xword", s_aarch64_cons
, 8},
2389 {"dword", s_aarch64_cons
, 8},
2392 {"secrel32", s_secrel
, 0},
2393 {"secidx", s_secidx
, 0},
2395 {"float16", float_cons
, 'h'},
2396 {"bfloat16", float_cons
, 'b'},
2401 /* Check whether STR points to a register name followed by a comma or the
2402 end of line; REG_TYPE indicates which register types are checked
2403 against. Return TRUE if STR is such a register name; otherwise return
2404 FALSE. The function does not intend to produce any diagnostics, but since
2405 the register parser aarch64_reg_parse, which is called by this function,
2406 does produce diagnostics, we call clear_error to clear any diagnostics
2407 that may be generated by aarch64_reg_parse.
2408 Also, the function returns FALSE directly if there is any user error
2409 present at the function entry. This prevents the existing diagnostics
2410 state from being spoiled.
2411 The function currently serves parse_constant_immediate and
2412 parse_big_immediate only. */
2414 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2416 const reg_entry
*reg
;
2418 /* Prevent the diagnostics state from being spoiled. */
2422 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2424 /* Clear the parsing error that may be set by the reg parser. */
2430 skip_whitespace (str
);
2431 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2437 /* Parser functions used exclusively in instruction operands. */
2439 /* Parse an immediate expression which may not be constant.
2441 To prevent the expression parser from pushing a register name
2442 into the symbol table as an undefined symbol, firstly a check is
2443 done to find out whether STR is a register of type REG_TYPE followed
2444 by a comma or the end of line. Return FALSE if STR is such a string. */
2447 parse_immediate_expression (char **str
, expressionS
*exp
,
2448 aarch64_reg_type reg_type
)
2450 if (reg_name_p (*str
, reg_type
))
2452 set_recoverable_error (_("immediate operand required"));
2456 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2458 if (exp
->X_op
== O_absent
)
2460 set_fatal_syntax_error (_("missing immediate expression"));
2467 /* Constant immediate-value read function for use in insn parsing.
2468 STR points to the beginning of the immediate (with the optional
2469 leading #); *VAL receives the value. REG_TYPE says which register
2470 names should be treated as registers rather than as symbolic immediates.
2472 Return TRUE on success; otherwise return FALSE. */
2475 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2479 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2482 if (exp
.X_op
!= O_constant
)
2484 set_syntax_error (_("constant expression required"));
2488 *val
= exp
.X_add_number
;
2493 encode_imm_float_bits (uint32_t imm
)
2495 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2496 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2499 /* Return TRUE if the single-precision floating-point value encoded in IMM
2500 can be expressed in the AArch64 8-bit signed floating-point format with
2501 3-bit exponent and normalized 4 bits of precision; in other words, the
2502 floating-point value must be expressable as
2503 (+/-) n / 16 * power (2, r)
2504 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2507 aarch64_imm_float_p (uint32_t imm
)
2509 /* If a single-precision floating-point value has the following bit
2510 pattern, it can be expressed in the AArch64 8-bit floating-point
2513 3 32222222 2221111111111
2514 1 09876543 21098765432109876543210
2515 n Eeeeeexx xxxx0000000000000000000
2517 where n, e and each x are either 0 or 1 independently, with
2522 /* Prepare the pattern for 'Eeeeee'. */
2523 if (((imm
>> 30) & 0x1) == 0)
2524 pattern
= 0x3e000000;
2526 pattern
= 0x40000000;
2528 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2529 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2532 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2533 as an IEEE float without any loss of precision. Store the value in
2537 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2539 /* If a double-precision floating-point value has the following bit
2540 pattern, it can be expressed in a float:
2542 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2543 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2544 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2546 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2547 if Eeee_eeee != 1111_1111
2549 where n, e, s and S are either 0 or 1 independently and where ~ is the
2553 uint32_t high32
= imm
>> 32;
2554 uint32_t low32
= imm
;
2556 /* Lower 29 bits need to be 0s. */
2557 if ((imm
& 0x1fffffff) != 0)
2560 /* Prepare the pattern for 'Eeeeeeeee'. */
2561 if (((high32
>> 30) & 0x1) == 0)
2562 pattern
= 0x38000000;
2564 pattern
= 0x40000000;
2567 if ((high32
& 0x78000000) != pattern
)
2570 /* Check Eeee_eeee != 1111_1111. */
2571 if ((high32
& 0x7ff00000) == 0x47f00000)
2574 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2575 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2576 | (low32
>> 29)); /* 3 S bits. */
2580 /* Return true if we should treat OPERAND as a double-precision
2581 floating-point operand rather than a single-precision one. */
2583 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2585 /* Check for unsuffixed SVE registers, which are allowed
2586 for LDR and STR but not in instructions that require an
2587 immediate. We get better error messages if we arbitrarily
2588 pick one size, parse the immediate normally, and then
2589 report the match failure in the normal way. */
2590 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2591 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2594 /* Parse a floating-point immediate. Return TRUE on success and return the
2595 value in *IMMED in the format of IEEE754 single-precision encoding.
2596 *CCP points to the start of the string; DP_P is TRUE when the immediate
2597 is expected to be in double-precision (N.B. this only matters when
2598 hexadecimal representation is involved). REG_TYPE says which register
2599 names should be treated as registers rather than as symbolic immediates.
2601 This routine accepts any IEEE float; it is up to the callers to reject
2605 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2606 aarch64_reg_type reg_type
)
2610 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2612 unsigned fpword
= 0;
2615 skip_past_char (&str
, '#');
2618 skip_whitespace (fpnum
);
2620 if (startswith (fpnum
, "0x"))
2622 /* Support the hexadecimal representation of the IEEE754 encoding.
2623 Double-precision is expected when DP_P is TRUE, otherwise the
2624 representation should be in single-precision. */
2625 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2630 if (!can_convert_double_to_float (val
, &fpword
))
2633 else if ((uint64_t) val
> 0xffffffff)
2640 else if (reg_name_p (str
, reg_type
))
2642 set_recoverable_error (_("immediate operand required"));
2650 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2653 /* Our FP word must be 32 bits (single-precision FP). */
2654 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2656 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2666 set_fatal_syntax_error (_("invalid floating-point constant"));
2670 /* Less-generic immediate-value read function with the possibility of loading
2671 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2674 To prevent the expression parser from pushing a register name into the
2675 symbol table as an undefined symbol, a check is firstly done to find
2676 out whether STR is a register of type REG_TYPE followed by a comma or
2677 the end of line. Return FALSE if STR is such a register. */
2680 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2684 if (reg_name_p (ptr
, reg_type
))
2686 set_syntax_error (_("immediate operand required"));
2690 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2692 if (inst
.reloc
.exp
.X_op
== O_constant
)
2693 *imm
= inst
.reloc
.exp
.X_add_number
;
2700 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2701 if NEED_LIBOPCODES is non-zero, the fixup will need
2702 assistance from the libopcodes. */
2705 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2706 const aarch64_opnd_info
*operand
,
2707 int need_libopcodes_p
)
2709 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2710 reloc
->opnd
= operand
->type
;
2711 if (need_libopcodes_p
)
2712 reloc
->need_libopcodes_p
= 1;
2715 /* Return TRUE if the instruction needs to be fixed up later internally by
2716 the GAS; otherwise return FALSE. */
2719 aarch64_gas_internal_fixup_p (void)
2721 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2724 /* Assign the immediate value to the relevant field in *OPERAND if
2725 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2726 needs an internal fixup in a later stage.
2727 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2728 IMM.VALUE that may get assigned with the constant. */
2730 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2731 aarch64_opnd_info
*operand
,
2733 int need_libopcodes_p
,
2736 if (reloc
->exp
.X_op
== O_constant
)
2739 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2741 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2742 reloc
->type
= BFD_RELOC_UNUSED
;
2746 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2747 /* Tell libopcodes to ignore this operand or not. This is helpful
2748 when one of the operands needs to be fixed up later but we need
2749 libopcodes to check the other operands. */
2750 operand
->skip
= skip_p
;
2754 /* Relocation modifiers. Each entry in the table contains the textual
2755 name for the relocation which may be placed before a symbol used as
2756 a load/store offset, or add immediate. It must be surrounded by a
2757 leading and trailing colon, for example:
2759 ldr x0, [x1, #:rello:varsym]
2760 add x0, x1, #:rello:varsym */
2762 struct reloc_table_entry
2766 bfd_reloc_code_real_type adr_type
;
2767 bfd_reloc_code_real_type adrp_type
;
2768 bfd_reloc_code_real_type movw_type
;
2769 bfd_reloc_code_real_type add_type
;
2770 bfd_reloc_code_real_type ldst_type
;
2771 bfd_reloc_code_real_type ld_literal_type
;
2774 static struct reloc_table_entry reloc_table
[] =
2776 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2781 BFD_RELOC_AARCH64_ADD_LO12
,
2782 BFD_RELOC_AARCH64_LDST_LO12
,
2785 /* Higher 21 bits of pc-relative page offset: ADRP */
2788 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2794 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2797 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2803 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2807 BFD_RELOC_AARCH64_MOVW_G0
,
2812 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2816 BFD_RELOC_AARCH64_MOVW_G0_S
,
2821 /* Less significant bits 0-15 of address/value: MOVK, no check */
2825 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2830 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2834 BFD_RELOC_AARCH64_MOVW_G1
,
2839 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2843 BFD_RELOC_AARCH64_MOVW_G1_S
,
2848 /* Less significant bits 16-31 of address/value: MOVK, no check */
2852 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2857 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2861 BFD_RELOC_AARCH64_MOVW_G2
,
2866 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2870 BFD_RELOC_AARCH64_MOVW_G2_S
,
2875 /* Less significant bits 32-47 of address/value: MOVK, no check */
2879 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2884 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2888 BFD_RELOC_AARCH64_MOVW_G3
,
2893 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2897 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2902 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2906 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2911 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2915 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2920 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2924 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2929 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2933 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2938 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2942 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2947 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2951 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2956 /* Get to the page containing GOT entry for a symbol. */
2959 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2963 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2965 /* 12 bit offset into the page containing GOT entry for that symbol. */
2971 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2974 /* 0-15 bits of address/value: MOVk, no check. */
2978 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2983 /* Most significant bits 16-31 of address/value: MOVZ. */
2987 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2992 /* 15 bit offset into the page containing GOT entry for that symbol. */
2998 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
3001 /* Get to the page containing GOT TLS entry for a symbol */
3002 {"gottprel_g0_nc", 0,
3005 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
3010 /* Get to the page containing GOT TLS entry for a symbol */
3014 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
3019 /* Get to the page containing GOT TLS entry for a symbol */
3021 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
3022 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
3028 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3033 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
3037 /* Lower 16 bits address/value: MOVk. */
3041 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
3046 /* Most significant bits 16-31 of address/value: MOVZ. */
3050 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
3055 /* Get to the page containing GOT TLS entry for a symbol */
3057 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
3058 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
3062 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
3064 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3069 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
3070 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
3073 /* Get to the page containing GOT TLS entry for a symbol.
3074 The same as GD, we allocate two consecutive GOT slots
3075 for module index and module offset, the only difference
3076 with GD is the module offset should be initialized to
3077 zero without any outstanding runtime relocation. */
3079 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
3080 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
3086 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3087 {"tlsldm_lo12_nc", 0,
3091 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
3095 /* 12 bit offset into the module TLS base address. */
3100 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
3101 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
3104 /* Same as dtprel_lo12, no overflow check. */
3105 {"dtprel_lo12_nc", 0,
3109 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
3110 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3113 /* bits[23:12] of offset to the module TLS base address. */
3118 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3122 /* bits[15:0] of offset to the module TLS base address. */
3126 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3131 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3135 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3140 /* bits[31:16] of offset to the module TLS base address. */
3144 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3149 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3153 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3158 /* bits[47:32] of offset to the module TLS base address. */
3162 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3167 /* Lower 16 bit offset into GOT entry for a symbol */
3168 {"tlsdesc_off_g0_nc", 0,
3171 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3176 /* Higher 16 bit offset into GOT entry for a symbol */
3177 {"tlsdesc_off_g1", 0,
3180 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3185 /* Get to the page containing GOT TLS entry for a symbol */
3188 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3192 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3194 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3195 {"gottprel_lo12", 0,
3200 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3203 /* Get tp offset for a symbol. */
3208 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3212 /* Get tp offset for a symbol. */
3217 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3218 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3221 /* Get tp offset for a symbol. */
3226 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3230 /* Get tp offset for a symbol. */
3231 {"tprel_lo12_nc", 0,
3235 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3236 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3239 /* Most significant bits 32-47 of address/value: MOVZ. */
3243 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3248 /* Most significant bits 16-31 of address/value: MOVZ. */
3252 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3257 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3261 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3266 /* Most significant bits 0-15 of address/value: MOVZ. */
3270 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3275 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3279 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3284 /* 15bit offset from got entry to base address of GOT table. */
3290 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3293 /* 14bit offset from got entry to base address of GOT table. */
3299 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3303 /* Given the address of a pointer pointing to the textual name of a
3304 relocation as may appear in assembler source, attempt to find its
3305 details in reloc_table. The pointer will be updated to the character
3306 after the trailing colon. On failure, NULL will be returned;
3307 otherwise return the reloc_table_entry. */
3309 static struct reloc_table_entry
*
3310 find_reloc_table_entry (char **str
)
3313 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3315 int length
= strlen (reloc_table
[i
].name
);
3317 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3318 && (*str
)[length
] == ':')
3320 *str
+= (length
+ 1);
3321 return &reloc_table
[i
];
3328 /* Returns 0 if the relocation should never be forced,
3329 1 if the relocation must be forced, and -1 if either
3333 aarch64_force_reloc (unsigned int type
)
3337 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3338 /* Perform these "immediate" internal relocations
3339 even if the symbol is extern or weak. */
3342 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3343 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3344 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3345 /* Pseudo relocs that need to be fixed up according to
3349 case BFD_RELOC_AARCH64_ADD_LO12
:
3350 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3351 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3352 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3353 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3354 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3355 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3356 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3357 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3358 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3359 case BFD_RELOC_AARCH64_LDST128_LO12
:
3360 case BFD_RELOC_AARCH64_LDST16_LO12
:
3361 case BFD_RELOC_AARCH64_LDST32_LO12
:
3362 case BFD_RELOC_AARCH64_LDST64_LO12
:
3363 case BFD_RELOC_AARCH64_LDST8_LO12
:
3364 case BFD_RELOC_AARCH64_LDST_LO12
:
3365 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3366 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3367 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3368 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3369 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3370 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3371 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3372 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3373 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3374 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3375 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3376 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3377 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3378 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3379 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3380 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3381 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3382 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3383 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3384 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3385 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3386 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3387 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3388 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3389 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3390 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3391 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3392 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3393 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3394 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3395 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3396 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3397 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3398 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3399 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3400 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3401 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3402 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3403 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3404 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3405 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3406 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3407 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3408 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3409 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3410 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3411 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3412 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3413 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3414 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3415 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3416 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3417 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3418 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3419 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3420 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3421 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3422 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3423 /* Always leave these relocations for the linker. */
3432 aarch64_force_relocation (struct fix
*fixp
)
3434 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3437 return generic_force_reloc (fixp
);
3441 /* Mode argument to parse_shift and parser_shifter_operand. */
3442 enum parse_shift_mode
3444 SHIFTED_NONE
, /* no shifter allowed */
3445 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3447 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3449 SHIFTED_LSL
, /* bare "lsl #n" */
3450 SHIFTED_MUL
, /* bare "mul #n" */
3451 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3452 SHIFTED_MUL_VL
, /* "mul vl" */
3453 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3456 /* Parse a <shift> operator on an AArch64 data processing instruction.
3457 Return TRUE on success; otherwise return FALSE. */
3459 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3461 const struct aarch64_name_value_pair
*shift_op
;
3462 enum aarch64_modifier_kind kind
;
3468 for (p
= *str
; ISALPHA (*p
); p
++)
3473 set_syntax_error (_("shift expression expected"));
3477 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3479 if (shift_op
== NULL
)
3481 set_syntax_error (_("shift operator expected"));
3485 kind
= aarch64_get_operand_modifier (shift_op
);
3487 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3489 set_syntax_error (_("invalid use of 'MSL'"));
3493 if (kind
== AARCH64_MOD_MUL
3494 && mode
!= SHIFTED_MUL
3495 && mode
!= SHIFTED_MUL_VL
)
3497 set_syntax_error (_("invalid use of 'MUL'"));
3503 case SHIFTED_LOGIC_IMM
:
3504 if (aarch64_extend_operator_p (kind
))
3506 set_syntax_error (_("extending shift is not permitted"));
3511 case SHIFTED_ARITH_IMM
:
3512 if (kind
== AARCH64_MOD_ROR
)
3514 set_syntax_error (_("'ROR' shift is not permitted"));
3520 if (kind
!= AARCH64_MOD_LSL
)
3522 set_syntax_error (_("only 'LSL' shift is permitted"));
3528 if (kind
!= AARCH64_MOD_MUL
)
3530 set_syntax_error (_("only 'MUL' is permitted"));
3535 case SHIFTED_MUL_VL
:
3536 /* "MUL VL" consists of two separate tokens. Require the first
3537 token to be "MUL" and look for a following "VL". */
3538 if (kind
== AARCH64_MOD_MUL
)
3540 skip_whitespace (p
);
3541 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3544 kind
= AARCH64_MOD_MUL_VL
;
3548 set_syntax_error (_("only 'MUL VL' is permitted"));
3551 case SHIFTED_REG_OFFSET
:
3552 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3553 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3555 set_fatal_syntax_error
3556 (_("invalid shift for the register offset addressing mode"));
3561 case SHIFTED_LSL_MSL
:
3562 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3564 set_syntax_error (_("invalid shift operator"));
3573 /* Whitespace can appear here if the next thing is a bare digit. */
3574 skip_whitespace (p
);
3576 /* Parse shift amount. */
3578 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3579 exp
.X_op
= O_absent
;
3582 if (is_immediate_prefix (*p
))
3587 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3589 if (kind
== AARCH64_MOD_MUL_VL
)
3590 /* For consistency, give MUL VL the same shift amount as an implicit
3592 operand
->shifter
.amount
= 1;
3593 else if (exp
.X_op
== O_absent
)
3595 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3597 set_syntax_error (_("missing shift amount"));
3600 operand
->shifter
.amount
= 0;
3602 else if (exp
.X_op
!= O_constant
)
3604 set_syntax_error (_("constant shift amount required"));
3607 /* For parsing purposes, MUL #n has no inherent range. The range
3608 depends on the operand and will be checked by operand-specific
3610 else if (kind
!= AARCH64_MOD_MUL
3611 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3613 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3618 operand
->shifter
.amount
= exp
.X_add_number
;
3619 operand
->shifter
.amount_present
= 1;
3622 operand
->shifter
.operator_present
= 1;
3623 operand
->shifter
.kind
= kind
;
3629 /* Parse a <shifter_operand> for a data processing instruction:
3632 #<immediate>, LSL #imm
3634 Validation of immediate operands is deferred to md_apply_fix.
3636 Return TRUE on success; otherwise return FALSE. */
3639 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3640 enum parse_shift_mode mode
)
3644 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3649 /* Accept an immediate expression. */
3650 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3654 /* Accept optional LSL for arithmetic immediate values. */
3655 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3656 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3659 /* Not accept any shifter for logical immediate values. */
3660 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3661 && parse_shift (&p
, operand
, mode
))
3663 set_syntax_error (_("unexpected shift operator"));
3671 /* Parse a <shifter_operand> for a data processing instruction:
3676 #<immediate>, LSL #imm
3678 where <shift> is handled by parse_shift above, and the last two
3679 cases are handled by the function above.
3681 Validation of immediate operands is deferred to md_apply_fix.
3683 Return TRUE on success; otherwise return FALSE. */
3686 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3687 enum parse_shift_mode mode
)
3689 const reg_entry
*reg
;
3690 aarch64_opnd_qualifier_t qualifier
;
3691 enum aarch64_operand_class opd_class
3692 = aarch64_get_operand_class (operand
->type
);
3694 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3697 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3699 set_syntax_error (_("unexpected register in the immediate operand"));
3703 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3705 set_expected_reg_error (REG_TYPE_R_Z
, reg
, 0);
3709 operand
->reg
.regno
= reg
->number
;
3710 operand
->qualifier
= qualifier
;
3712 /* Accept optional shift operation on register. */
3713 if (! skip_past_comma (str
))
3716 if (! parse_shift (str
, operand
, mode
))
3721 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3724 (_("integer register expected in the extended/shifted operand "
3729 /* We have a shifted immediate variable. */
3730 return parse_shifter_operand_imm (str
, operand
, mode
);
3733 /* Return TRUE on success; return FALSE otherwise. */
3736 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3737 enum parse_shift_mode mode
)
3741 /* Determine if we have the sequence of characters #: or just :
3742 coming next. If we do, then we check for a :rello: relocation
3743 modifier. If we don't, punt the whole lot to
3744 parse_shifter_operand. */
3746 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3748 struct reloc_table_entry
*entry
;
3756 /* Try to parse a relocation. Anything else is an error. */
3757 if (!(entry
= find_reloc_table_entry (str
)))
3759 set_syntax_error (_("unknown relocation modifier"));
3763 if (entry
->add_type
== 0)
3766 (_("this relocation modifier is not allowed on this instruction"));
3770 /* Save str before we decompose it. */
3773 /* Next, we parse the expression. */
3774 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3778 /* Record the relocation type (use the ADD variant here). */
3779 inst
.reloc
.type
= entry
->add_type
;
3780 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3782 /* If str is empty, we've reached the end, stop here. */
3786 /* Otherwise, we have a shifted reloc modifier, so rewind to
3787 recover the variable name and continue parsing for the shifter. */
3789 return parse_shifter_operand_imm (str
, operand
, mode
);
3792 return parse_shifter_operand (str
, operand
, mode
);
3795 /* Parse all forms of an address expression. Information is written
3796 to *OPERAND and/or inst.reloc.
3798 The A64 instruction set has the following addressing modes:
3801 [base] // in SIMD ld/st structure
3802 [base{,#0}] // in ld/st exclusive
3804 [base,Xm{,LSL #imm}]
3805 [base,Xm,SXTX {#imm}]
3806 [base,Wm,(S|U)XTW {#imm}]
3808 [base]! // in ldraa/ldrab exclusive
3812 [base],Xm // in SIMD ld/st structure
3813 PC-relative (literal)
3817 [base,Zm.D{,LSL #imm}]
3818 [base,Zm.S,(S|U)XTW {#imm}]
3819 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3823 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3824 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3825 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3827 (As a convenience, the notation "=immediate" is permitted in conjunction
3828 with the pc-relative literal load instructions to automatically place an
3829 immediate value or symbolic address in a nearby literal pool and generate
3830 a hidden label which references it.)
3832 Upon a successful parsing, the address structure in *OPERAND will be
3833 filled in the following way:
3835 .base_regno = <base>
3836 .offset.is_reg // 1 if the offset is a register
3838 .offset.regno = <Rm>
3840 For different addressing modes defined in the A64 ISA:
3843 .pcrel=0; .preind=1; .postind=0; .writeback=0
3845 .pcrel=0; .preind=1; .postind=0; .writeback=1
3847 .pcrel=0; .preind=0; .postind=1; .writeback=1
3848 PC-relative (literal)
3849 .pcrel=1; .preind=1; .postind=0; .writeback=0
3851 The shift/extension information, if any, will be stored in .shifter.
3852 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3853 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3854 corresponding register.
3856 BASE_TYPE says which types of base register should be accepted and
3857 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3858 is the type of shifter that is allowed for immediate offsets,
3859 or SHIFTED_NONE if none.
3861 In all other respects, it is the caller's responsibility to check
3862 for addressing modes not supported by the instruction, and to set
3866 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3867 aarch64_opnd_qualifier_t
*base_qualifier
,
3868 aarch64_opnd_qualifier_t
*offset_qualifier
,
3869 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3870 enum parse_shift_mode imm_shift_mode
)
3873 const reg_entry
*reg
;
3874 expressionS
*exp
= &inst
.reloc
.exp
;
3876 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3877 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3878 if (! skip_past_char (&p
, '['))
3880 /* =immediate or label. */
3881 operand
->addr
.pcrel
= 1;
3882 operand
->addr
.preind
= 1;
3884 /* #:<reloc_op>:<symbol> */
3885 skip_past_char (&p
, '#');
3886 if (skip_past_char (&p
, ':'))
3888 bfd_reloc_code_real_type ty
;
3889 struct reloc_table_entry
*entry
;
3891 /* Try to parse a relocation modifier. Anything else is
3893 entry
= find_reloc_table_entry (&p
);
3896 set_syntax_error (_("unknown relocation modifier"));
3900 switch (operand
->type
)
3902 case AARCH64_OPND_ADDR_PCREL21
:
3904 ty
= entry
->adr_type
;
3908 ty
= entry
->ld_literal_type
;
3915 (_("this relocation modifier is not allowed on this "
3921 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3923 set_syntax_error (_("invalid relocation expression"));
3926 /* #:<reloc_op>:<expr> */
3927 /* Record the relocation type. */
3928 inst
.reloc
.type
= ty
;
3929 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3933 if (skip_past_char (&p
, '='))
3934 /* =immediate; need to generate the literal in the literal pool. */
3935 inst
.gen_lit_pool
= 1;
3937 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3939 set_syntax_error (_("invalid address"));
3950 bool alpha_base_p
= ISALPHA (*p
);
3951 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3952 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3955 && aarch64_check_reg_type (reg
, REG_TYPE_R_SP
)
3956 && *base_qualifier
== AARCH64_OPND_QLF_W
)
3957 set_syntax_error (_("expected a 64-bit base register"));
3958 else if (alpha_base_p
)
3959 set_syntax_error (_("invalid base register"));
3961 set_syntax_error (_("expected a base register"));
3964 operand
->addr
.base_regno
= reg
->number
;
3967 if (skip_past_comma (&p
))
3970 operand
->addr
.preind
= 1;
3972 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3975 if (!aarch64_check_reg_type (reg
, offset_type
))
3977 set_syntax_error (_("invalid offset register"));
3982 operand
->addr
.offset
.regno
= reg
->number
;
3983 operand
->addr
.offset
.is_reg
= 1;
3984 /* Shifted index. */
3985 if (skip_past_comma (&p
))
3988 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3989 /* Use the diagnostics set in parse_shift, so not set new
3990 error message here. */
3994 [base,Xm] # For vector plus scalar SVE2 indexing.
3995 [base,Xm{,LSL #imm}]
3996 [base,Xm,SXTX {#imm}]
3997 [base,Wm,(S|U)XTW {#imm}] */
3998 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3999 || operand
->shifter
.kind
== AARCH64_MOD_LSL
4000 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
4002 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
4004 set_syntax_error (_("invalid use of 32-bit register offset"));
4007 if (aarch64_get_qualifier_esize (*base_qualifier
)
4008 != aarch64_get_qualifier_esize (*offset_qualifier
)
4009 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
4010 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
4011 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
4013 set_syntax_error (_("offset has different size from base"));
4017 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
4019 set_syntax_error (_("invalid use of 64-bit register offset"));
4025 /* [Xn,#:<reloc_op>:<symbol> */
4026 skip_past_char (&p
, '#');
4027 if (skip_past_char (&p
, ':'))
4029 struct reloc_table_entry
*entry
;
4031 /* Try to parse a relocation modifier. Anything else is
4033 if (!(entry
= find_reloc_table_entry (&p
)))
4035 set_syntax_error (_("unknown relocation modifier"));
4039 if (entry
->ldst_type
== 0)
4042 (_("this relocation modifier is not allowed on this "
4047 /* [Xn,#:<reloc_op>: */
4048 /* We now have the group relocation table entry corresponding to
4049 the name in the assembler source. Next, we parse the
4051 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4053 set_syntax_error (_("invalid relocation expression"));
4057 /* [Xn,#:<reloc_op>:<expr> */
4058 /* Record the load/store relocation type. */
4059 inst
.reloc
.type
= entry
->ldst_type
;
4060 inst
.reloc
.pc_rel
= entry
->pc_rel
;
4064 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4066 set_syntax_error (_("invalid expression in the address"));
4070 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
4071 /* [Xn,<expr>,<shifter> */
4072 if (! parse_shift (&p
, operand
, imm_shift_mode
))
4078 if (! skip_past_char (&p
, ']'))
4080 set_syntax_error (_("']' expected"));
4084 if (skip_past_char (&p
, '!'))
4086 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
4088 set_syntax_error (_("register offset not allowed in pre-indexed "
4089 "addressing mode"));
4093 operand
->addr
.writeback
= 1;
4095 else if (skip_past_comma (&p
))
4098 operand
->addr
.postind
= 1;
4099 operand
->addr
.writeback
= 1;
4101 if (operand
->addr
.preind
)
4103 set_syntax_error (_("cannot combine pre- and post-indexing"));
4107 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
4111 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4113 set_syntax_error (_("invalid offset register"));
4117 operand
->addr
.offset
.regno
= reg
->number
;
4118 operand
->addr
.offset
.is_reg
= 1;
4120 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4123 set_syntax_error (_("invalid expression in the address"));
4128 /* If at this point neither .preind nor .postind is set, we have a
4129 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4130 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4131 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4133 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4135 if (operand
->addr
.writeback
)
4137 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4139 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4140 operand
->addr
.offset
.is_reg
= 0;
4141 operand
->addr
.offset
.imm
= 0;
4142 operand
->addr
.preind
= 1;
4147 set_syntax_error (_("missing offset in the pre-indexed address"));
4153 operand
->addr
.preind
= 1;
4154 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4156 operand
->addr
.offset
.is_reg
= 1;
4157 operand
->addr
.offset
.regno
= REG_ZR
;
4158 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4162 inst
.reloc
.exp
.X_op
= O_constant
;
4163 inst
.reloc
.exp
.X_add_number
= 0;
4172 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4175 parse_address (char **str
, aarch64_opnd_info
*operand
)
4177 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4178 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4179 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4182 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4183 The arguments have the same meaning as for parse_address_main.
4184 Return TRUE on success. */
4186 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4187 aarch64_opnd_qualifier_t
*base_qualifier
,
4188 aarch64_opnd_qualifier_t
*offset_qualifier
)
4190 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4191 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4195 /* Parse a register X0-X30. The register must be 64-bit and register 31
4198 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4200 const reg_entry
*reg
= parse_reg (str
);
4201 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4203 set_expected_reg_error (REG_TYPE_R_64
, reg
, 0);
4206 operand
->reg
.regno
= reg
->number
;
4207 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4211 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4212 Return TRUE on success; otherwise return FALSE. */
4214 parse_half (char **str
, int *internal_fixup_p
)
4218 skip_past_char (&p
, '#');
4220 gas_assert (internal_fixup_p
);
4221 *internal_fixup_p
= 0;
4225 struct reloc_table_entry
*entry
;
4227 /* Try to parse a relocation. Anything else is an error. */
4230 if (!(entry
= find_reloc_table_entry (&p
)))
4232 set_syntax_error (_("unknown relocation modifier"));
4236 if (entry
->movw_type
== 0)
4239 (_("this relocation modifier is not allowed on this instruction"));
4243 inst
.reloc
.type
= entry
->movw_type
;
4246 *internal_fixup_p
= 1;
4248 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4255 /* Parse an operand for an ADRP instruction:
4257 Return TRUE on success; otherwise return FALSE. */
4260 parse_adrp (char **str
)
4267 struct reloc_table_entry
*entry
;
4269 /* Try to parse a relocation. Anything else is an error. */
4271 if (!(entry
= find_reloc_table_entry (&p
)))
4273 set_syntax_error (_("unknown relocation modifier"));
4277 if (entry
->adrp_type
== 0)
4280 (_("this relocation modifier is not allowed on this instruction"));
4284 inst
.reloc
.type
= entry
->adrp_type
;
4287 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4289 inst
.reloc
.pc_rel
= 1;
4290 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4296 /* Miscellaneous. */
4298 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4299 of SIZE tokens in which index I gives the token for field value I,
4300 or is null if field value I is invalid. REG_TYPE says which register
4301 names should be treated as registers rather than as symbolic immediates.
4303 Return true on success, moving *STR past the operand and storing the
4304 field value in *VAL. */
4307 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4308 size_t size
, aarch64_reg_type reg_type
)
4314 /* Match C-like tokens. */
4316 while (ISALNUM (*q
))
4319 for (i
= 0; i
< size
; ++i
)
4321 && strncasecmp (array
[i
], p
, q
- p
) == 0
4322 && array
[i
][q
- p
] == 0)
4329 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4332 if (exp
.X_op
== O_constant
4333 && (uint64_t) exp
.X_add_number
< size
)
4335 *val
= exp
.X_add_number
;
4340 /* Use the default error for this operand. */
4344 /* Parse an option for a preload instruction. Returns the encoding for the
4345 option, or PARSE_FAIL. */
4348 parse_pldop (char **str
)
4351 const struct aarch64_name_value_pair
*o
;
4354 while (ISALNUM (*q
))
4357 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4365 /* Parse an option for a barrier instruction. Returns the encoding for the
4366 option, or PARSE_FAIL. */
4369 parse_barrier (char **str
)
4372 const struct aarch64_name_value_pair
*o
;
4375 while (ISALPHA (*q
))
4378 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4386 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4387 return 0 if successful. Otherwise return PARSE_FAIL. */
4390 parse_barrier_psb (char **str
,
4391 const struct aarch64_name_value_pair
** hint_opt
)
4394 const struct aarch64_name_value_pair
*o
;
4397 while (ISALPHA (*q
))
4400 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4403 set_fatal_syntax_error
4404 ( _("unknown or missing option to PSB/TSB"));
4408 if (o
->value
!= 0x11)
4410 /* PSB only accepts option name 'CSYNC'. */
4412 (_("the specified option is not accepted for PSB/TSB"));
4421 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4422 return 0 if successful. Otherwise return PARSE_FAIL. */
4425 parse_bti_operand (char **str
,
4426 const struct aarch64_name_value_pair
** hint_opt
)
4429 const struct aarch64_name_value_pair
*o
;
4432 while (ISALPHA (*q
))
4435 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4438 set_fatal_syntax_error
4439 ( _("unknown option to BTI"));
4445 /* Valid BTI operands. */
4453 (_("unknown option to BTI"));
4462 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4463 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4468 Side effect: Update STR with current parse position of success.
4470 FLAGS is as for parse_typed_reg. */
4472 static const reg_entry
*
4473 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4474 aarch64_opnd_qualifier_t
*qualifier
, unsigned int flags
)
4476 struct vector_type_el vectype
;
4477 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4478 PTR_FULL_REG
| flags
);
4482 if (vectype
.type
== NT_invtype
)
4483 *qualifier
= AARCH64_OPND_QLF_NIL
;
4486 *qualifier
= vectype_to_qualifier (&vectype
);
4487 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4494 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4499 Function return TRUE if immediate was found, or FALSE.
4502 parse_sme_immediate (char **str
, int64_t *imm
)
4505 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4512 /* Parse index with selection register and immediate offset:
4517 Return true on success, populating OPND with the parsed index. */
4520 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4522 const reg_entry
*reg
;
4524 if (!skip_past_char (str
, '['))
4526 set_syntax_error (_("expected '['"));
4530 /* The selection register, encoded in the 2-bit Rv field. */
4531 reg
= parse_reg (str
);
4532 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
)
4534 set_syntax_error (_("expected a 32-bit selection register"));
4537 opnd
->index
.regno
= reg
->number
;
4539 if (!skip_past_char (str
, ','))
4541 set_syntax_error (_("missing immediate offset"));
4545 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4547 set_syntax_error (_("expected a constant immediate offset"));
4551 if (!skip_past_char (str
, ']'))
4553 set_syntax_error (_("expected ']'"));
4560 /* Parse a register of type REG_TYPE that might have an element type
4561 qualifier and that is indexed by two values: a 32-bit register,
4562 followed by an immediate. The ranges of the register and the
4563 immediate vary by opcode and are checked in libopcodes.
4565 Return true on success, populating OPND with information about
4566 the operand and setting QUALIFIER to the register qualifier.
4568 Field format examples:
4570 <Pm>.<T>[<Wv>< #<imm>]
4572 <ZAn><HV>.<T>[<Wv>, #<imm>]
4574 FLAGS is as for parse_typed_reg. */
4577 parse_dual_indexed_reg (char **str
, aarch64_reg_type reg_type
,
4578 struct aarch64_indexed_za
*opnd
,
4579 aarch64_opnd_qualifier_t
*qualifier
,
4582 const reg_entry
*reg
= parse_reg_with_qual (str
, reg_type
, qualifier
, flags
);
4586 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4587 opnd
->regno
= reg
->number
;
4589 return parse_sme_za_index (str
, opnd
);
4592 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4596 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4597 struct aarch64_indexed_za
*opnd
,
4598 aarch64_opnd_qualifier_t
*qualifier
)
4600 if (!skip_past_char (str
, '{'))
4602 set_expected_reglist_error (REG_TYPE_ZATHV
, parse_reg (str
));
4606 if (!parse_dual_indexed_reg (str
, REG_TYPE_ZATHV
, opnd
, qualifier
,
4610 if (!skip_past_char (str
, '}'))
4612 set_syntax_error (_("expected '}'"));
4619 /* Parse list of up to eight 64-bit element tile names separated by commas in
4620 SME's ZERO instruction:
4624 Function returns <mask>:
4626 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4629 parse_sme_zero_mask(char **str
)
4633 aarch64_opnd_qualifier_t qualifier
;
4634 unsigned int ptr_flags
= PTR_IN_REGLIST
;
4640 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4641 &qualifier
, ptr_flags
);
4645 if (reg
->type
== REG_TYPE_ZA
)
4647 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4649 set_syntax_error ("ZA should not have a size suffix");
4652 /* { ZA } is assembled as all-ones immediate. */
4657 int regno
= reg
->number
;
4658 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4660 /* { ZA0.B } is assembled as all-ones immediate. */
4663 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4664 mask
|= 0x55 << regno
;
4665 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4666 mask
|= 0x11 << regno
;
4667 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4668 mask
|= 0x01 << regno
;
4669 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4671 set_syntax_error (_("ZA tile masks do not operate at .Q"
4675 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4677 set_syntax_error (_("missing ZA tile size"));
4682 set_syntax_error (_("invalid ZA tile"));
4686 ptr_flags
|= PTR_GOOD_MATCH
;
4688 while (skip_past_char (&q
, ','));
4694 /* Wraps in curly braces <mask> operand ZERO instruction:
4698 Function returns value of <mask> bit-field.
4701 parse_sme_list_of_64bit_tiles (char **str
)
4705 if (!skip_past_char (str
, '{'))
4707 set_syntax_error (_("expected '{'"));
4711 /* Empty <mask> list is an all-zeros immediate. */
4712 if (!skip_past_char (str
, '}'))
4714 regno
= parse_sme_zero_mask (str
);
4715 if (regno
== PARSE_FAIL
)
4718 if (!skip_past_char (str
, '}'))
4720 set_syntax_error (_("expected '}'"));
4730 /* Parse streaming mode operand for SMSTART and SMSTOP.
4734 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4737 parse_sme_sm_za (char **str
)
4742 while (ISALPHA (*q
))
4746 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4748 set_syntax_error (_("expected SM or ZA operand"));
4753 return TOLOWER (p
[0]);
4756 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4757 Returns the encoding for the option, or PARSE_FAIL.
4759 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4760 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4762 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4763 field, otherwise as a system register.
4767 parse_sys_reg (char **str
, htab_t sys_regs
,
4768 int imple_defined_p
, int pstatefield_p
,
4772 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4773 const aarch64_sys_reg
*o
;
4777 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4778 if (p
< buf
+ (sizeof (buf
) - 1))
4779 *p
++ = TOLOWER (*q
);
4782 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4783 valid system register. This is enforced by construction of the hash
4785 if (p
- buf
!= q
- *str
)
4788 o
= str_hash_find (sys_regs
, buf
);
4791 if (!imple_defined_p
)
4795 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4796 unsigned int op0
, op1
, cn
, cm
, op2
;
4798 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4801 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4803 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4810 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4811 as_bad (_("selected processor does not support PSTATE field "
4814 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4815 o
->value
, o
->flags
, o
->features
))
4816 as_bad (_("selected processor does not support system register "
4818 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4819 as_warn (_("system register name '%s' is deprecated and may be "
4820 "removed in a future release"), buf
);
4830 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4831 for the option, or NULL. */
4833 static const aarch64_sys_ins_reg
*
4834 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4837 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4838 const aarch64_sys_ins_reg
*o
;
4841 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4842 if (p
< buf
+ (sizeof (buf
) - 1))
4843 *p
++ = TOLOWER (*q
);
4846 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4847 valid system register. This is enforced by construction of the hash
4849 if (p
- buf
!= q
- *str
)
4852 o
= str_hash_find (sys_ins_regs
, buf
);
4856 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4857 o
->name
, o
->value
, o
->flags
, 0))
4858 as_bad (_("selected processor does not support system register "
4860 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4861 as_warn (_("system register name '%s' is deprecated and may be "
4862 "removed in a future release"), buf
);
4868 #define po_char_or_fail(chr) do { \
4869 if (! skip_past_char (&str, chr)) \
4873 #define po_reg_or_fail(regtype) do { \
4874 reg = aarch64_reg_parse (&str, regtype, NULL); \
4879 #define po_int_fp_reg_or_fail(reg_type) do { \
4880 reg = parse_reg (&str); \
4881 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4883 set_expected_reg_error (reg_type, reg, 0); \
4886 info->reg.regno = reg->number; \
4887 info->qualifier = inherent_reg_qualifier (reg); \
4890 #define po_imm_nc_or_fail() do { \
4891 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4895 #define po_imm_or_fail(min, max) do { \
4896 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4898 if (val < min || val > max) \
4900 set_fatal_syntax_error (_("immediate value out of range "\
4901 #min " to "#max)); \
4906 #define po_enum_or_fail(array) do { \
4907 if (!parse_enum_string (&str, &val, array, \
4908 ARRAY_SIZE (array), imm_reg_type)) \
4912 #define po_misc_or_fail(expr) do { \
4917 /* encode the 12-bit imm field of Add/sub immediate */
4918 static inline uint32_t
4919 encode_addsub_imm (uint32_t imm
)
4924 /* encode the shift amount field of Add/sub immediate */
4925 static inline uint32_t
4926 encode_addsub_imm_shift_amount (uint32_t cnt
)
4932 /* encode the imm field of Adr instruction */
4933 static inline uint32_t
4934 encode_adr_imm (uint32_t imm
)
4936 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4937 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4940 /* encode the immediate field of Move wide immediate */
4941 static inline uint32_t
4942 encode_movw_imm (uint32_t imm
)
4947 /* encode the 26-bit offset of unconditional branch */
4948 static inline uint32_t
4949 encode_branch_ofs_26 (uint32_t ofs
)
4951 return ofs
& ((1 << 26) - 1);
4954 /* encode the 19-bit offset of conditional branch and compare & branch */
4955 static inline uint32_t
4956 encode_cond_branch_ofs_19 (uint32_t ofs
)
4958 return (ofs
& ((1 << 19) - 1)) << 5;
4961 /* encode the 19-bit offset of ld literal */
4962 static inline uint32_t
4963 encode_ld_lit_ofs_19 (uint32_t ofs
)
4965 return (ofs
& ((1 << 19) - 1)) << 5;
4968 /* Encode the 14-bit offset of test & branch. */
4969 static inline uint32_t
4970 encode_tst_branch_ofs_14 (uint32_t ofs
)
4972 return (ofs
& ((1 << 14) - 1)) << 5;
4975 /* Encode the 16-bit imm field of svc/hvc/smc. */
4976 static inline uint32_t
4977 encode_svc_imm (uint32_t imm
)
4982 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4983 static inline uint32_t
4984 reencode_addsub_switch_add_sub (uint32_t opcode
)
4986 return opcode
^ (1 << 30);
4989 static inline uint32_t
4990 reencode_movzn_to_movz (uint32_t opcode
)
4992 return opcode
| (1 << 30);
4995 static inline uint32_t
4996 reencode_movzn_to_movn (uint32_t opcode
)
4998 return opcode
& ~(1 << 30);
5001 /* Overall per-instruction processing. */
5003 /* We need to be able to fix up arbitrary expressions in some statements.
5004 This is so that we can handle symbols that are an arbitrary distance from
5005 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5006 which returns part of an address in a form which will be valid for
5007 a data instruction. We do this by pushing the expression into a symbol
5008 in the expr_section, and creating a fix for that. */
5011 fix_new_aarch64 (fragS
* frag
,
5026 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5030 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5037 /* Diagnostics on operands errors. */
5039 /* By default, output verbose error message.
5040 Disable the verbose error message by -mno-verbose-error. */
5041 static int verbose_error_p
= 1;
5043 #ifdef DEBUG_AARCH64
5044 /* N.B. this is only for the purpose of debugging. */
5045 const char* operand_mismatch_kind_names
[] =
5048 "AARCH64_OPDE_RECOVERABLE",
5049 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5050 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5051 "AARCH64_OPDE_SYNTAX_ERROR",
5052 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5053 "AARCH64_OPDE_INVALID_VARIANT",
5054 "AARCH64_OPDE_REG_LIST",
5055 "AARCH64_OPDE_UNTIED_IMMS",
5056 "AARCH64_OPDE_UNTIED_OPERAND",
5057 "AARCH64_OPDE_OUT_OF_RANGE",
5058 "AARCH64_OPDE_UNALIGNED",
5059 "AARCH64_OPDE_OTHER_ERROR",
5060 "AARCH64_OPDE_INVALID_REGNO",
5062 #endif /* DEBUG_AARCH64 */
5064 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5066 When multiple errors of different kinds are found in the same assembly
5067 line, only the error of the highest severity will be picked up for
5068 issuing the diagnostics. */
5071 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5072 enum aarch64_operand_error_kind rhs
)
5074 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5075 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5076 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5077 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5078 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5079 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5080 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5081 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_INVALID_VARIANT
);
5082 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_REG_LIST
);
5083 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5084 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5085 gas_assert (AARCH64_OPDE_INVALID_REGNO
> AARCH64_OPDE_OTHER_ERROR
);
5089 /* Helper routine to get the mnemonic name from the assembly instruction
5090 line; should only be called for the diagnosis purpose, as there is
5091 string copy operation involved, which may affect the runtime
5092 performance if used in elsewhere. */
5095 get_mnemonic_name (const char *str
)
5097 static char mnemonic
[32];
5100 /* Get the first 15 bytes and assume that the full name is included. */
5101 strncpy (mnemonic
, str
, 31);
5102 mnemonic
[31] = '\0';
5104 /* Scan up to the end of the mnemonic, which must end in white space,
5105 '.', or end of string. */
5106 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5111 /* Append '...' to the truncated long name. */
5112 if (ptr
- mnemonic
== 31)
5113 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5119 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5121 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5122 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5125 /* Data structures storing one user error in the assembly code related to
5128 struct operand_error_record
5130 const aarch64_opcode
*opcode
;
5131 aarch64_operand_error detail
;
5132 struct operand_error_record
*next
;
5135 typedef struct operand_error_record operand_error_record
;
5137 struct operand_errors
5139 operand_error_record
*head
;
5140 operand_error_record
*tail
;
5143 typedef struct operand_errors operand_errors
;
5145 /* Top-level data structure reporting user errors for the current line of
5147 The way md_assemble works is that all opcodes sharing the same mnemonic
5148 name are iterated to find a match to the assembly line. In this data
5149 structure, each of the such opcodes will have one operand_error_record
5150 allocated and inserted. In other words, excessive errors related with
5151 a single opcode are disregarded. */
5152 operand_errors operand_error_report
;
5154 /* Free record nodes. */
5155 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5157 /* Initialize the data structure that stores the operand mismatch
5158 information on assembling one line of the assembly code. */
5160 init_operand_error_report (void)
5162 if (operand_error_report
.head
!= NULL
)
5164 gas_assert (operand_error_report
.tail
!= NULL
);
5165 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5166 free_opnd_error_record_nodes
= operand_error_report
.head
;
5167 operand_error_report
.head
= NULL
;
5168 operand_error_report
.tail
= NULL
;
5171 gas_assert (operand_error_report
.tail
== NULL
);
5174 /* Return TRUE if some operand error has been recorded during the
5175 parsing of the current assembly line using the opcode *OPCODE;
5176 otherwise return FALSE. */
5178 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5180 operand_error_record
*record
= operand_error_report
.head
;
5181 return record
&& record
->opcode
== opcode
;
5184 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5185 OPCODE field is initialized with OPCODE.
5186 N.B. only one record for each opcode, i.e. the maximum of one error is
5187 recorded for each instruction template. */
5190 add_operand_error_record (const operand_error_record
* new_record
)
5192 const aarch64_opcode
*opcode
= new_record
->opcode
;
5193 operand_error_record
* record
= operand_error_report
.head
;
5195 /* The record may have been created for this opcode. If not, we need
5197 if (! opcode_has_operand_error_p (opcode
))
5199 /* Get one empty record. */
5200 if (free_opnd_error_record_nodes
== NULL
)
5202 record
= XNEW (operand_error_record
);
5206 record
= free_opnd_error_record_nodes
;
5207 free_opnd_error_record_nodes
= record
->next
;
5209 record
->opcode
= opcode
;
5210 /* Insert at the head. */
5211 record
->next
= operand_error_report
.head
;
5212 operand_error_report
.head
= record
;
5213 if (operand_error_report
.tail
== NULL
)
5214 operand_error_report
.tail
= record
;
5216 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5217 && record
->detail
.index
<= new_record
->detail
.index
5218 && operand_error_higher_severity_p (record
->detail
.kind
,
5219 new_record
->detail
.kind
))
5221 /* In the case of multiple errors found on operands related with a
5222 single opcode, only record the error of the leftmost operand and
5223 only if the error is of higher severity. */
5224 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5225 " the existing error %s on operand %d",
5226 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5227 new_record
->detail
.index
,
5228 operand_mismatch_kind_names
[record
->detail
.kind
],
5229 record
->detail
.index
);
5233 record
->detail
= new_record
->detail
;
5237 record_operand_error_info (const aarch64_opcode
*opcode
,
5238 aarch64_operand_error
*error_info
)
5240 operand_error_record record
;
5241 record
.opcode
= opcode
;
5242 record
.detail
= *error_info
;
5243 add_operand_error_record (&record
);
5246 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5247 error message *ERROR, for operand IDX (count from 0). */
5250 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5251 enum aarch64_operand_error_kind kind
,
5254 aarch64_operand_error info
;
5255 memset(&info
, 0, sizeof (info
));
5259 info
.non_fatal
= false;
5260 record_operand_error_info (opcode
, &info
);
5264 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5265 enum aarch64_operand_error_kind kind
,
5266 const char* error
, const int *extra_data
)
5268 aarch64_operand_error info
;
5272 info
.data
[0].i
= extra_data
[0];
5273 info
.data
[1].i
= extra_data
[1];
5274 info
.data
[2].i
= extra_data
[2];
5275 info
.non_fatal
= false;
5276 record_operand_error_info (opcode
, &info
);
5280 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5281 const char* error
, int lower_bound
,
5284 int data
[3] = {lower_bound
, upper_bound
, 0};
5285 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5289 /* Remove the operand error record for *OPCODE. */
5290 static void ATTRIBUTE_UNUSED
5291 remove_operand_error_record (const aarch64_opcode
*opcode
)
5293 if (opcode_has_operand_error_p (opcode
))
5295 operand_error_record
* record
= operand_error_report
.head
;
5296 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5297 operand_error_report
.head
= record
->next
;
5298 record
->next
= free_opnd_error_record_nodes
;
5299 free_opnd_error_record_nodes
= record
;
5300 if (operand_error_report
.head
== NULL
)
5302 gas_assert (operand_error_report
.tail
== record
);
5303 operand_error_report
.tail
= NULL
;
5308 /* Given the instruction in *INSTR, return the index of the best matched
5309 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5311 Return -1 if there is no qualifier sequence; return the first match
5312 if there is multiple matches found. */
5315 find_best_match (const aarch64_inst
*instr
,
5316 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5318 int i
, num_opnds
, max_num_matched
, idx
;
5320 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5323 DEBUG_TRACE ("no operand");
5327 max_num_matched
= 0;
5330 /* For each pattern. */
5331 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5334 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5336 /* Most opcodes has much fewer patterns in the list. */
5337 if (empty_qualifier_sequence_p (qualifiers
))
5339 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5343 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5344 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5347 if (num_matched
> max_num_matched
)
5349 max_num_matched
= num_matched
;
5354 DEBUG_TRACE ("return with %d", idx
);
5358 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5359 corresponding operands in *INSTR. */
5362 assign_qualifier_sequence (aarch64_inst
*instr
,
5363 const aarch64_opnd_qualifier_t
*qualifiers
)
5366 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5367 gas_assert (num_opnds
);
5368 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5369 instr
->operands
[i
].qualifier
= *qualifiers
;
5372 /* Callback used by aarch64_print_operand to apply STYLE to the
5373 disassembler output created from FMT and ARGS. The STYLER object holds
5374 any required state. Must return a pointer to a string (created from FMT
5375 and ARGS) that will continue to be valid until the complete disassembled
5376 instruction has been printed.
5378 We don't currently add any styling to the output of the disassembler as
5379 used within assembler error messages, and so STYLE is ignored here. A
5380 new string is allocated on the obstack help within STYLER and returned
5383 static const char *aarch64_apply_style
5384 (struct aarch64_styler
*styler
,
5385 enum disassembler_style style ATTRIBUTE_UNUSED
,
5386 const char *fmt
, va_list args
)
5390 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5393 /* Calculate the required space. */
5395 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5397 gas_assert (res
>= 0);
5399 /* Allocate space on the obstack and format the result. */
5400 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5401 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5402 gas_assert (res
>= 0);
5407 /* Print operands for the diagnosis purpose. */
5410 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5411 const aarch64_opnd_info
*opnds
)
5414 struct aarch64_styler styler
;
5415 struct obstack content
;
5416 obstack_init (&content
);
5418 styler
.apply_style
= aarch64_apply_style
;
5419 styler
.state
= (void *) &content
;
5421 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5426 /* We regard the opcode operand info more, however we also look into
5427 the inst->operands to support the disassembling of the optional
5429 The two operand code should be the same in all cases, apart from
5430 when the operand can be optional. */
5431 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5432 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5435 /* Generate the operand string in STR. */
5436 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5437 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5441 strcat (buf
, i
== 0 ? " " : ", ");
5443 /* Append the operand string. */
5446 /* Append a comment. This works because only the last operand ever
5447 adds a comment. If that ever changes then we'll need to be
5451 strcat (buf
, "\t// ");
5456 obstack_free (&content
, NULL
);
5459 /* Send to stderr a string as information. */
5462 output_info (const char *format
, ...)
5468 file
= as_where (&line
);
5472 fprintf (stderr
, "%s:%u: ", file
, line
);
5474 fprintf (stderr
, "%s: ", file
);
5476 fprintf (stderr
, _("Info: "));
5477 va_start (args
, format
);
5478 vfprintf (stderr
, format
, args
);
5480 (void) putc ('\n', stderr
);
5483 /* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
5484 relates to registers or register lists. If so, return a string that
5485 reports the error against "operand %d", otherwise return null. */
5488 get_reg_error_message (const aarch64_operand_error
*detail
)
5490 /* Handle the case where we found a register that was expected
5491 to be in a register list outside of a register list. */
5492 if ((detail
->data
[1].i
& detail
->data
[2].i
) != 0
5493 && (detail
->data
[1].i
& SEF_IN_REGLIST
) == 0)
5494 return _("missing braces at operand %d");
5496 /* If some opcodes expected a register, and we found a register,
5497 complain about the difference. */
5498 if (detail
->data
[2].i
)
5500 unsigned int expected
= (detail
->data
[1].i
& SEF_IN_REGLIST
5501 ? detail
->data
[1].i
& ~SEF_IN_REGLIST
5502 : detail
->data
[0].i
& ~SEF_DEFAULT_ERROR
);
5503 const char *msg
= get_reg_expected_msg (expected
, detail
->data
[2].i
);
5505 msg
= N_("unexpected register type at operand %d");
5509 /* Handle the case where we got to the point of trying to parse a
5510 register within a register list, but didn't find a known register. */
5511 if (detail
->data
[1].i
& SEF_IN_REGLIST
)
5513 unsigned int expected
= detail
->data
[1].i
& ~SEF_IN_REGLIST
;
5514 const char *msg
= get_reg_expected_msg (expected
, 0);
5516 msg
= _("invalid register list at operand %d");
5520 /* Punt if register-related problems weren't the only errors. */
5521 if (detail
->data
[0].i
& SEF_DEFAULT_ERROR
)
5524 /* Handle the case where the only acceptable things are registers. */
5525 if (detail
->data
[1].i
== 0)
5527 const char *msg
= get_reg_expected_msg (detail
->data
[0].i
, 0);
5529 msg
= _("expected a register at operand %d");
5533 /* Handle the case where the only acceptable things are register lists,
5534 and there was no opening '{'. */
5535 if (detail
->data
[0].i
== 0)
5536 return _("expected '{' at operand %d");
5538 return _("expected a register or register list at operand %d");
5541 /* Output one operand error record. */
5544 output_operand_error_record (const operand_error_record
*record
, char *str
)
5546 const aarch64_operand_error
*detail
= &record
->detail
;
5547 int idx
= detail
->index
;
5548 const aarch64_opcode
*opcode
= record
->opcode
;
5549 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5550 : AARCH64_OPND_NIL
);
5552 typedef void (*handler_t
)(const char *format
, ...);
5553 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5554 const char *msg
= detail
->error
;
5556 switch (detail
->kind
)
5558 case AARCH64_OPDE_NIL
:
5562 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5563 handler (_("this `%s' should have an immediately preceding `%s'"
5565 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5568 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5569 handler (_("the preceding `%s' should be followed by `%s` rather"
5570 " than `%s` -- `%s'"),
5571 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5574 case AARCH64_OPDE_SYNTAX_ERROR
:
5575 if (!msg
&& idx
>= 0)
5577 msg
= get_reg_error_message (detail
);
5580 char *full_msg
= xasprintf (msg
, idx
+ 1);
5581 handler (_("%s -- `%s'"), full_msg
, str
);
5588 case AARCH64_OPDE_RECOVERABLE
:
5589 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5590 case AARCH64_OPDE_OTHER_ERROR
:
5591 /* Use the prepared error message if there is, otherwise use the
5592 operand description string to describe the error. */
5596 handler (_("%s -- `%s'"), msg
, str
);
5598 handler (_("%s at operand %d -- `%s'"),
5603 gas_assert (idx
>= 0);
5604 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5605 aarch64_get_operand_desc (opd_code
), str
);
5609 case AARCH64_OPDE_INVALID_VARIANT
:
5610 handler (_("operand mismatch -- `%s'"), str
);
5611 if (verbose_error_p
)
5613 /* We will try to correct the erroneous instruction and also provide
5614 more information e.g. all other valid variants.
5616 The string representation of the corrected instruction and other
5617 valid variants are generated by
5619 1) obtaining the intermediate representation of the erroneous
5621 2) manipulating the IR, e.g. replacing the operand qualifier;
5622 3) printing out the instruction by calling the printer functions
5623 shared with the disassembler.
5625 The limitation of this method is that the exact input assembly
5626 line cannot be accurately reproduced in some cases, for example an
5627 optional operand present in the actual assembly line will be
5628 omitted in the output; likewise for the optional syntax rules,
5629 e.g. the # before the immediate. Another limitation is that the
5630 assembly symbols and relocation operations in the assembly line
5631 currently cannot be printed out in the error report. Last but not
5632 least, when there is other error(s) co-exist with this error, the
5633 'corrected' instruction may be still incorrect, e.g. given
5634 'ldnp h0,h1,[x0,#6]!'
5635 this diagnosis will provide the version:
5636 'ldnp s0,s1,[x0,#6]!'
5637 which is still not right. */
5638 size_t len
= strlen (get_mnemonic_name (str
));
5642 aarch64_inst
*inst_base
= &inst
.base
;
5643 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5646 reset_aarch64_instruction (&inst
);
5647 inst_base
->opcode
= opcode
;
5649 /* Reset the error report so that there is no side effect on the
5650 following operand parsing. */
5651 init_operand_error_report ();
5654 result
= parse_operands (str
+ len
, opcode
)
5655 && programmer_friendly_fixup (&inst
);
5656 gas_assert (result
);
5657 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5658 NULL
, NULL
, insn_sequence
);
5659 gas_assert (!result
);
5661 /* Find the most matched qualifier sequence. */
5662 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5663 gas_assert (qlf_idx
> -1);
5665 /* Assign the qualifiers. */
5666 assign_qualifier_sequence (inst_base
,
5667 opcode
->qualifiers_list
[qlf_idx
]);
5669 /* Print the hint. */
5670 output_info (_(" did you mean this?"));
5671 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5672 print_operands (buf
, opcode
, inst_base
->operands
);
5673 output_info (_(" %s"), buf
);
5675 /* Print out other variant(s) if there is any. */
5677 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5678 output_info (_(" other valid variant(s):"));
5680 /* For each pattern. */
5681 qualifiers_list
= opcode
->qualifiers_list
;
5682 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5684 /* Most opcodes has much fewer patterns in the list.
5685 First NIL qualifier indicates the end in the list. */
5686 if (empty_qualifier_sequence_p (*qualifiers_list
))
5691 /* Mnemonics name. */
5692 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5694 /* Assign the qualifiers. */
5695 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5697 /* Print instruction. */
5698 print_operands (buf
, opcode
, inst_base
->operands
);
5700 output_info (_(" %s"), buf
);
5706 case AARCH64_OPDE_UNTIED_IMMS
:
5707 handler (_("operand %d must have the same immediate value "
5708 "as operand 1 -- `%s'"),
5709 detail
->index
+ 1, str
);
5712 case AARCH64_OPDE_UNTIED_OPERAND
:
5713 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5714 detail
->index
+ 1, str
);
5717 case AARCH64_OPDE_INVALID_REGNO
:
5718 handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
5719 detail
->data
[0].s
, detail
->data
[1].i
,
5720 detail
->data
[0].s
, detail
->data
[2].i
, idx
+ 1, str
);
5723 case AARCH64_OPDE_OUT_OF_RANGE
:
5724 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5725 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5726 msg
? msg
: _("immediate value"),
5727 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5729 handler (_("%s must be %d at operand %d -- `%s'"),
5730 msg
? msg
: _("immediate value"),
5731 detail
->data
[0].i
, idx
+ 1, str
);
5734 case AARCH64_OPDE_REG_LIST
:
5735 if (detail
->data
[0].i
== 1)
5736 handler (_("invalid number of registers in the list; "
5737 "only 1 register is expected at operand %d -- `%s'"),
5740 handler (_("invalid number of registers in the list; "
5741 "%d registers are expected at operand %d -- `%s'"),
5742 detail
->data
[0].i
, idx
+ 1, str
);
5745 case AARCH64_OPDE_UNALIGNED
:
5746 handler (_("immediate value must be a multiple of "
5747 "%d at operand %d -- `%s'"),
5748 detail
->data
[0].i
, idx
+ 1, str
);
5757 /* Process and output the error message about the operand mismatching.
5759 When this function is called, the operand error information had
5760 been collected for an assembly line and there will be multiple
5761 errors in the case of multiple instruction templates; output the
5762 error message that most closely describes the problem.
5764 The errors to be printed can be filtered on printing all errors
5765 or only non-fatal errors. This distinction has to be made because
5766 the error buffer may already be filled with fatal errors we don't want to
5767 print due to the different instruction templates. */
5770 output_operand_error_report (char *str
, bool non_fatal_only
)
5772 enum aarch64_operand_error_kind kind
;
5773 operand_error_record
*curr
;
5774 operand_error_record
*head
= operand_error_report
.head
;
5775 operand_error_record
*record
= NULL
;
5777 /* No error to report. */
5781 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5783 /* Only one error. */
5784 if (head
== operand_error_report
.tail
)
5786 /* If the only error is a non-fatal one and we don't want to print it,
5788 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5790 DEBUG_TRACE ("single opcode entry with error kind: %s",
5791 operand_mismatch_kind_names
[head
->detail
.kind
]);
5792 output_operand_error_record (head
, str
);
5797 /* Find the error kind of the highest severity. */
5798 DEBUG_TRACE ("multiple opcode entries with error kind");
5799 kind
= AARCH64_OPDE_NIL
;
5800 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5802 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5803 if (curr
->detail
.kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5805 DEBUG_TRACE ("\t%s [%x, %x, %x]",
5806 operand_mismatch_kind_names
[curr
->detail
.kind
],
5807 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5808 curr
->detail
.data
[2].i
);
5812 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5814 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5815 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5816 kind
= curr
->detail
.kind
;
5819 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5821 /* Pick up one of errors of KIND to report. */
5822 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5824 /* If we don't want to print non-fatal errors then don't consider them
5826 if (curr
->detail
.kind
!= kind
5827 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5829 /* If there are multiple errors, pick up the one with the highest
5830 mismatching operand index. In the case of multiple errors with
5831 the equally highest operand index, pick up the first one or the
5832 first one with non-NULL error message. */
5833 if (!record
|| curr
->detail
.index
> record
->detail
.index
)
5835 else if (curr
->detail
.index
== record
->detail
.index
5836 && !record
->detail
.error
)
5838 if (curr
->detail
.error
)
5840 else if (kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5842 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
5843 record
->detail
.data
[1].i
|= curr
->detail
.data
[1].i
;
5844 record
->detail
.data
[2].i
|= curr
->detail
.data
[2].i
;
5845 DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
5846 operand_mismatch_kind_names
[kind
],
5847 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5848 curr
->detail
.data
[2].i
);
5853 /* The way errors are collected in the back-end is a bit non-intuitive. But
5854 essentially, because each operand template is tried recursively you may
5855 always have errors collected from the previous tried OPND. These are
5856 usually skipped if there is one successful match. However now with the
5857 non-fatal errors we have to ignore those previously collected hard errors
5858 when we're only interested in printing the non-fatal ones. This condition
5859 prevents us from printing errors that are not appropriate, since we did
5860 match a condition, but it also has warnings that it wants to print. */
5861 if (non_fatal_only
&& !record
)
5864 gas_assert (record
);
5865 DEBUG_TRACE ("Pick up error kind %s to report",
5866 operand_mismatch_kind_names
[kind
]);
5869 output_operand_error_record (record
, str
);
5872 /* Write an AARCH64 instruction to buf - always little-endian. */
5874 put_aarch64_insn (char *buf
, uint32_t insn
)
5876 unsigned char *where
= (unsigned char *) buf
;
5878 where
[1] = insn
>> 8;
5879 where
[2] = insn
>> 16;
5880 where
[3] = insn
>> 24;
5884 get_aarch64_insn (char *buf
)
5886 unsigned char *where
= (unsigned char *) buf
;
5888 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5889 | ((uint32_t) where
[3] << 24)));
5894 output_inst (struct aarch64_inst
*new_inst
)
5898 to
= frag_more (INSN_SIZE
);
5900 frag_now
->tc_frag_data
.recorded
= 1;
5902 put_aarch64_insn (to
, inst
.base
.value
);
5904 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5906 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5907 INSN_SIZE
, &inst
.reloc
.exp
,
5910 DEBUG_TRACE ("Prepared relocation fix up");
5911 /* Don't check the addend value against the instruction size,
5912 that's the job of our code in md_apply_fix(). */
5913 fixp
->fx_no_overflow
= 1;
5914 if (new_inst
!= NULL
)
5915 fixp
->tc_fix_data
.inst
= new_inst
;
5916 if (aarch64_gas_internal_fixup_p ())
5918 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5919 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5920 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5924 dwarf2_emit_insn (INSN_SIZE
);
5927 /* Link together opcodes of the same name. */
5931 const aarch64_opcode
*opcode
;
5932 struct templates
*next
;
5935 typedef struct templates templates
;
5938 lookup_mnemonic (const char *start
, int len
)
5940 templates
*templ
= NULL
;
5942 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5946 /* Subroutine of md_assemble, responsible for looking up the primary
5947 opcode from the mnemonic the user wrote. BASE points to the beginning
5948 of the mnemonic, DOT points to the first '.' within the mnemonic
5949 (if any) and END points to the end of the mnemonic. */
5952 opcode_lookup (char *base
, char *dot
, char *end
)
5954 const aarch64_cond
*cond
;
5961 inst
.cond
= COND_ALWAYS
;
5963 /* Handle a possible condition. */
5966 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5969 inst
.cond
= cond
->value
;
5975 if (inst
.cond
== COND_ALWAYS
)
5977 /* Look for unaffixed mnemonic. */
5978 return lookup_mnemonic (base
, len
);
5982 /* append ".c" to mnemonic if conditional */
5983 memcpy (condname
, base
, len
);
5984 memcpy (condname
+ len
, ".c", 2);
5987 return lookup_mnemonic (base
, len
);
5993 /* Process an optional operand that is found omitted from the assembly line.
5994 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5995 instruction's opcode entry while IDX is the index of this omitted operand.
5999 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6000 int idx
, aarch64_opnd_info
*operand
)
6002 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6003 gas_assert (optional_operand_p (opcode
, idx
));
6004 gas_assert (!operand
->present
);
6008 case AARCH64_OPND_Rd
:
6009 case AARCH64_OPND_Rn
:
6010 case AARCH64_OPND_Rm
:
6011 case AARCH64_OPND_Rt
:
6012 case AARCH64_OPND_Rt2
:
6013 case AARCH64_OPND_Rt_LS64
:
6014 case AARCH64_OPND_Rt_SP
:
6015 case AARCH64_OPND_Rs
:
6016 case AARCH64_OPND_Ra
:
6017 case AARCH64_OPND_Rt_SYS
:
6018 case AARCH64_OPND_Rd_SP
:
6019 case AARCH64_OPND_Rn_SP
:
6020 case AARCH64_OPND_Rm_SP
:
6021 case AARCH64_OPND_Fd
:
6022 case AARCH64_OPND_Fn
:
6023 case AARCH64_OPND_Fm
:
6024 case AARCH64_OPND_Fa
:
6025 case AARCH64_OPND_Ft
:
6026 case AARCH64_OPND_Ft2
:
6027 case AARCH64_OPND_Sd
:
6028 case AARCH64_OPND_Sn
:
6029 case AARCH64_OPND_Sm
:
6030 case AARCH64_OPND_Va
:
6031 case AARCH64_OPND_Vd
:
6032 case AARCH64_OPND_Vn
:
6033 case AARCH64_OPND_Vm
:
6034 case AARCH64_OPND_VdD1
:
6035 case AARCH64_OPND_VnD1
:
6036 operand
->reg
.regno
= default_value
;
6039 case AARCH64_OPND_Ed
:
6040 case AARCH64_OPND_En
:
6041 case AARCH64_OPND_Em
:
6042 case AARCH64_OPND_Em16
:
6043 case AARCH64_OPND_SM3_IMM2
:
6044 operand
->reglane
.regno
= default_value
;
6047 case AARCH64_OPND_IDX
:
6048 case AARCH64_OPND_BIT_NUM
:
6049 case AARCH64_OPND_IMMR
:
6050 case AARCH64_OPND_IMMS
:
6051 case AARCH64_OPND_SHLL_IMM
:
6052 case AARCH64_OPND_IMM_VLSL
:
6053 case AARCH64_OPND_IMM_VLSR
:
6054 case AARCH64_OPND_CCMP_IMM
:
6055 case AARCH64_OPND_FBITS
:
6056 case AARCH64_OPND_UIMM4
:
6057 case AARCH64_OPND_UIMM3_OP1
:
6058 case AARCH64_OPND_UIMM3_OP2
:
6059 case AARCH64_OPND_IMM
:
6060 case AARCH64_OPND_IMM_2
:
6061 case AARCH64_OPND_WIDTH
:
6062 case AARCH64_OPND_UIMM7
:
6063 case AARCH64_OPND_NZCV
:
6064 case AARCH64_OPND_SVE_PATTERN
:
6065 case AARCH64_OPND_SVE_PRFOP
:
6066 operand
->imm
.value
= default_value
;
6069 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6070 operand
->imm
.value
= default_value
;
6071 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6072 operand
->shifter
.amount
= 1;
6075 case AARCH64_OPND_EXCEPTION
:
6076 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6079 case AARCH64_OPND_BARRIER_ISB
:
6080 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6083 case AARCH64_OPND_BTI_TARGET
:
6084 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6092 /* Process the relocation type for move wide instructions.
6093 Return TRUE on success; otherwise return FALSE. */
6096 process_movw_reloc_info (void)
6101 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6103 if (inst
.base
.opcode
->op
== OP_MOVK
)
6104 switch (inst
.reloc
.type
)
6106 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6107 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6108 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6109 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6110 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6111 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6112 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6113 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6114 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6115 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6116 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6118 (_("the specified relocation type is not allowed for MOVK"));
6124 switch (inst
.reloc
.type
)
6126 case BFD_RELOC_AARCH64_MOVW_G0
:
6127 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6128 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6129 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6130 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6131 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6132 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6133 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6134 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6135 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6136 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6137 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6138 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6141 case BFD_RELOC_AARCH64_MOVW_G1
:
6142 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6143 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6144 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6145 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6146 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6147 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6148 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6149 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6150 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6151 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6156 case BFD_RELOC_AARCH64_MOVW_G2
:
6157 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6158 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6159 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6160 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6161 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6162 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6165 set_fatal_syntax_error
6166 (_("the specified relocation type is not allowed for 32-bit "
6172 case BFD_RELOC_AARCH64_MOVW_G3
:
6173 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6176 set_fatal_syntax_error
6177 (_("the specified relocation type is not allowed for 32-bit "
6184 /* More cases should be added when more MOVW-related relocation types
6185 are supported in GAS. */
6186 gas_assert (aarch64_gas_internal_fixup_p ());
6187 /* The shift amount should have already been set by the parser. */
6190 inst
.base
.operands
[1].shifter
.amount
= shift
;
6194 /* A primitive log calculator. */
6196 static inline unsigned int
6197 get_logsz (unsigned int size
)
6199 const unsigned char ls
[16] =
6200 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6206 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6207 return ls
[size
- 1];
6210 /* Determine and return the real reloc type code for an instruction
6211 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6213 static inline bfd_reloc_code_real_type
6214 ldst_lo12_determine_real_reloc_type (void)
6216 unsigned logsz
, max_logsz
;
6217 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6218 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6220 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6222 BFD_RELOC_AARCH64_LDST8_LO12
,
6223 BFD_RELOC_AARCH64_LDST16_LO12
,
6224 BFD_RELOC_AARCH64_LDST32_LO12
,
6225 BFD_RELOC_AARCH64_LDST64_LO12
,
6226 BFD_RELOC_AARCH64_LDST128_LO12
6229 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6230 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6231 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6232 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6233 BFD_RELOC_AARCH64_NONE
6236 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6237 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6238 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6239 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6240 BFD_RELOC_AARCH64_NONE
6243 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6244 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6245 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6246 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6247 BFD_RELOC_AARCH64_NONE
6250 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6251 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6252 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6253 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6254 BFD_RELOC_AARCH64_NONE
6258 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6259 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6261 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6263 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6265 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6266 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6268 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6270 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6272 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6274 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6276 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6277 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6278 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6279 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6284 if (logsz
> max_logsz
)
6286 /* SEE PR 27904 for an example of this. */
6287 set_fatal_syntax_error
6288 (_("relocation qualifier does not match instruction size"));
6289 return BFD_RELOC_AARCH64_NONE
;
6292 /* In reloc.c, these pseudo relocation types should be defined in similar
6293 order as above reloc_ldst_lo12 array. Because the array index calculation
6294 below relies on this. */
6295 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6298 /* Check whether a register list REGINFO is valid. The registers must be
6299 numbered in increasing order (modulo 32), in increments of one or two.
6301 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6304 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6307 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6309 uint32_t i
, nb_regs
, prev_regno
, incr
;
6311 nb_regs
= 1 + (reginfo
& 0x3);
6313 prev_regno
= reginfo
& 0x1f;
6314 incr
= accept_alternate
? 2 : 1;
6316 for (i
= 1; i
< nb_regs
; ++i
)
6318 uint32_t curr_regno
;
6320 curr_regno
= reginfo
& 0x1f;
6321 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6323 prev_regno
= curr_regno
;
6329 /* Generic instruction operand parser. This does no encoding and no
6330 semantic validation; it merely squirrels values away in the inst
6331 structure. Returns TRUE or FALSE depending on whether the
6332 specified grammar matched. */
6335 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6338 char *backtrack_pos
= 0;
6339 const enum aarch64_opnd
*operands
= opcode
->operands
;
6340 aarch64_reg_type imm_reg_type
;
6343 skip_whitespace (str
);
6345 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6347 | AARCH64_FEATURE_SVE2
))
6348 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6350 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6352 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6355 const reg_entry
*reg
;
6356 int comma_skipped_p
= 0;
6357 struct vector_type_el vectype
;
6358 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6359 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6360 aarch64_reg_type reg_type
;
6362 DEBUG_TRACE ("parse operand %d", i
);
6364 /* Assign the operand code. */
6365 info
->type
= operands
[i
];
6367 if (optional_operand_p (opcode
, i
))
6369 /* Remember where we are in case we need to backtrack. */
6370 gas_assert (!backtrack_pos
);
6371 backtrack_pos
= str
;
6374 /* Expect comma between operands; the backtrack mechanism will take
6375 care of cases of omitted optional operand. */
6376 if (i
> 0 && ! skip_past_char (&str
, ','))
6378 set_syntax_error (_("comma expected between operands"));
6382 comma_skipped_p
= 1;
6384 switch (operands
[i
])
6386 case AARCH64_OPND_Rd
:
6387 case AARCH64_OPND_Rn
:
6388 case AARCH64_OPND_Rm
:
6389 case AARCH64_OPND_Rt
:
6390 case AARCH64_OPND_Rt2
:
6391 case AARCH64_OPND_Rs
:
6392 case AARCH64_OPND_Ra
:
6393 case AARCH64_OPND_Rt_LS64
:
6394 case AARCH64_OPND_Rt_SYS
:
6395 case AARCH64_OPND_PAIRREG
:
6396 case AARCH64_OPND_SVE_Rm
:
6397 po_int_fp_reg_or_fail (REG_TYPE_R_Z
);
6399 /* In LS64 load/store instructions Rt register number must be even
6401 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6403 /* We've already checked if this is valid register.
6404 This will check if register number (Rt) is not undefined for LS64
6406 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6407 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6409 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6415 case AARCH64_OPND_Rd_SP
:
6416 case AARCH64_OPND_Rn_SP
:
6417 case AARCH64_OPND_Rt_SP
:
6418 case AARCH64_OPND_SVE_Rn_SP
:
6419 case AARCH64_OPND_Rm_SP
:
6420 po_int_fp_reg_or_fail (REG_TYPE_R_SP
);
6423 case AARCH64_OPND_Rm_EXT
:
6424 case AARCH64_OPND_Rm_SFT
:
6425 po_misc_or_fail (parse_shifter_operand
6426 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6428 : SHIFTED_LOGIC_IMM
)));
6429 if (!info
->shifter
.operator_present
)
6431 /* Default to LSL if not present. Libopcodes prefers shifter
6432 kind to be explicit. */
6433 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6434 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6435 /* For Rm_EXT, libopcodes will carry out further check on whether
6436 or not stack pointer is used in the instruction (Recall that
6437 "the extend operator is not optional unless at least one of
6438 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6442 case AARCH64_OPND_Fd
:
6443 case AARCH64_OPND_Fn
:
6444 case AARCH64_OPND_Fm
:
6445 case AARCH64_OPND_Fa
:
6446 case AARCH64_OPND_Ft
:
6447 case AARCH64_OPND_Ft2
:
6448 case AARCH64_OPND_Sd
:
6449 case AARCH64_OPND_Sn
:
6450 case AARCH64_OPND_Sm
:
6451 case AARCH64_OPND_SVE_VZn
:
6452 case AARCH64_OPND_SVE_Vd
:
6453 case AARCH64_OPND_SVE_Vm
:
6454 case AARCH64_OPND_SVE_Vn
:
6455 po_int_fp_reg_or_fail (REG_TYPE_BHSDQ
);
6458 case AARCH64_OPND_SVE_Pd
:
6459 case AARCH64_OPND_SVE_Pg3
:
6460 case AARCH64_OPND_SVE_Pg4_5
:
6461 case AARCH64_OPND_SVE_Pg4_10
:
6462 case AARCH64_OPND_SVE_Pg4_16
:
6463 case AARCH64_OPND_SVE_Pm
:
6464 case AARCH64_OPND_SVE_Pn
:
6465 case AARCH64_OPND_SVE_Pt
:
6466 case AARCH64_OPND_SME_Pm
:
6467 reg_type
= REG_TYPE_PN
;
6470 case AARCH64_OPND_SVE_Za_5
:
6471 case AARCH64_OPND_SVE_Za_16
:
6472 case AARCH64_OPND_SVE_Zd
:
6473 case AARCH64_OPND_SVE_Zm_5
:
6474 case AARCH64_OPND_SVE_Zm_16
:
6475 case AARCH64_OPND_SVE_Zn
:
6476 case AARCH64_OPND_SVE_Zt
:
6477 reg_type
= REG_TYPE_ZN
;
6480 case AARCH64_OPND_Va
:
6481 case AARCH64_OPND_Vd
:
6482 case AARCH64_OPND_Vn
:
6483 case AARCH64_OPND_Vm
:
6484 reg_type
= REG_TYPE_VN
;
6486 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6489 if (vectype
.defined
& NTA_HASINDEX
)
6492 info
->reg
.regno
= reg
->number
;
6493 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6494 && vectype
.type
== NT_invtype
)
6495 /* Unqualified Pn and Zn registers are allowed in certain
6496 contexts. Rely on F_STRICT qualifier checking to catch
6498 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6501 info
->qualifier
= vectype_to_qualifier (&vectype
);
6502 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6507 case AARCH64_OPND_VdD1
:
6508 case AARCH64_OPND_VnD1
:
6509 reg
= aarch64_reg_parse (&str
, REG_TYPE_VN
, &vectype
);
6512 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6514 set_fatal_syntax_error
6515 (_("the top half of a 128-bit FP/SIMD register is expected"));
6518 info
->reg
.regno
= reg
->number
;
6519 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6520 here; it is correct for the purpose of encoding/decoding since
6521 only the register number is explicitly encoded in the related
6522 instructions, although this appears a bit hacky. */
6523 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6526 case AARCH64_OPND_SVE_Zm3_INDEX
:
6527 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6528 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6529 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6530 case AARCH64_OPND_SVE_Zm4_INDEX
:
6531 case AARCH64_OPND_SVE_Zn_INDEX
:
6532 reg_type
= REG_TYPE_ZN
;
6533 goto vector_reg_index
;
6535 case AARCH64_OPND_Ed
:
6536 case AARCH64_OPND_En
:
6537 case AARCH64_OPND_Em
:
6538 case AARCH64_OPND_Em16
:
6539 case AARCH64_OPND_SM3_IMM2
:
6540 reg_type
= REG_TYPE_VN
;
6542 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6545 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6548 info
->reglane
.regno
= reg
->number
;
6549 info
->reglane
.index
= vectype
.index
;
6550 info
->qualifier
= vectype_to_qualifier (&vectype
);
6551 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6555 case AARCH64_OPND_SVE_ZnxN
:
6556 case AARCH64_OPND_SVE_ZtxN
:
6557 reg_type
= REG_TYPE_ZN
;
6558 goto vector_reg_list
;
6560 case AARCH64_OPND_LVn
:
6561 case AARCH64_OPND_LVt
:
6562 case AARCH64_OPND_LVt_AL
:
6563 case AARCH64_OPND_LEt
:
6564 reg_type
= REG_TYPE_VN
;
6566 if (reg_type
== REG_TYPE_ZN
6567 && get_opcode_dependent_value (opcode
) == 1
6570 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6573 info
->reglist
.first_regno
= reg
->number
;
6574 info
->reglist
.num_regs
= 1;
6578 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6579 if (val
== PARSE_FAIL
)
6582 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6584 set_fatal_syntax_error (_("invalid register list"));
6588 if (vectype
.width
!= 0 && *str
!= ',')
6590 set_fatal_syntax_error
6591 (_("expected element type rather than vector type"));
6595 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6596 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6598 if (operands
[i
] == AARCH64_OPND_LEt
)
6600 if (!(vectype
.defined
& NTA_HASINDEX
))
6602 info
->reglist
.has_index
= 1;
6603 info
->reglist
.index
= vectype
.index
;
6607 if (vectype
.defined
& NTA_HASINDEX
)
6609 if (!(vectype
.defined
& NTA_HASTYPE
))
6611 if (reg_type
== REG_TYPE_ZN
)
6612 set_fatal_syntax_error (_("missing type suffix"));
6616 info
->qualifier
= vectype_to_qualifier (&vectype
);
6617 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6621 case AARCH64_OPND_CRn
:
6622 case AARCH64_OPND_CRm
:
6624 char prefix
= *(str
++);
6625 if (prefix
!= 'c' && prefix
!= 'C')
6628 po_imm_nc_or_fail ();
6631 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6634 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6635 info
->imm
.value
= val
;
6639 case AARCH64_OPND_SHLL_IMM
:
6640 case AARCH64_OPND_IMM_VLSR
:
6641 po_imm_or_fail (1, 64);
6642 info
->imm
.value
= val
;
6645 case AARCH64_OPND_CCMP_IMM
:
6646 case AARCH64_OPND_SIMM5
:
6647 case AARCH64_OPND_FBITS
:
6648 case AARCH64_OPND_TME_UIMM16
:
6649 case AARCH64_OPND_UIMM4
:
6650 case AARCH64_OPND_UIMM4_ADDG
:
6651 case AARCH64_OPND_UIMM10
:
6652 case AARCH64_OPND_UIMM3_OP1
:
6653 case AARCH64_OPND_UIMM3_OP2
:
6654 case AARCH64_OPND_IMM_VLSL
:
6655 case AARCH64_OPND_IMM
:
6656 case AARCH64_OPND_IMM_2
:
6657 case AARCH64_OPND_WIDTH
:
6658 case AARCH64_OPND_SVE_INV_LIMM
:
6659 case AARCH64_OPND_SVE_LIMM
:
6660 case AARCH64_OPND_SVE_LIMM_MOV
:
6661 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6662 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6663 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6664 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6665 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6666 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6667 case AARCH64_OPND_SVE_SIMM5
:
6668 case AARCH64_OPND_SVE_SIMM5B
:
6669 case AARCH64_OPND_SVE_SIMM6
:
6670 case AARCH64_OPND_SVE_SIMM8
:
6671 case AARCH64_OPND_SVE_UIMM3
:
6672 case AARCH64_OPND_SVE_UIMM7
:
6673 case AARCH64_OPND_SVE_UIMM8
:
6674 case AARCH64_OPND_SVE_UIMM8_53
:
6675 case AARCH64_OPND_IMM_ROT1
:
6676 case AARCH64_OPND_IMM_ROT2
:
6677 case AARCH64_OPND_IMM_ROT3
:
6678 case AARCH64_OPND_SVE_IMM_ROT1
:
6679 case AARCH64_OPND_SVE_IMM_ROT2
:
6680 case AARCH64_OPND_SVE_IMM_ROT3
:
6681 case AARCH64_OPND_CSSC_SIMM8
:
6682 case AARCH64_OPND_CSSC_UIMM8
:
6683 po_imm_nc_or_fail ();
6684 info
->imm
.value
= val
;
6687 case AARCH64_OPND_SVE_AIMM
:
6688 case AARCH64_OPND_SVE_ASIMM
:
6689 po_imm_nc_or_fail ();
6690 info
->imm
.value
= val
;
6691 skip_whitespace (str
);
6692 if (skip_past_comma (&str
))
6693 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6695 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6698 case AARCH64_OPND_SVE_PATTERN
:
6699 po_enum_or_fail (aarch64_sve_pattern_array
);
6700 info
->imm
.value
= val
;
6703 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6704 po_enum_or_fail (aarch64_sve_pattern_array
);
6705 info
->imm
.value
= val
;
6706 if (skip_past_comma (&str
)
6707 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6709 if (!info
->shifter
.operator_present
)
6711 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6712 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6713 info
->shifter
.amount
= 1;
6717 case AARCH64_OPND_SVE_PRFOP
:
6718 po_enum_or_fail (aarch64_sve_prfop_array
);
6719 info
->imm
.value
= val
;
6722 case AARCH64_OPND_UIMM7
:
6723 po_imm_or_fail (0, 127);
6724 info
->imm
.value
= val
;
6727 case AARCH64_OPND_IDX
:
6728 case AARCH64_OPND_MASK
:
6729 case AARCH64_OPND_BIT_NUM
:
6730 case AARCH64_OPND_IMMR
:
6731 case AARCH64_OPND_IMMS
:
6732 po_imm_or_fail (0, 63);
6733 info
->imm
.value
= val
;
6736 case AARCH64_OPND_IMM0
:
6737 po_imm_nc_or_fail ();
6740 set_fatal_syntax_error (_("immediate zero expected"));
6743 info
->imm
.value
= 0;
6746 case AARCH64_OPND_FPIMM0
:
6749 bool res1
= false, res2
= false;
6750 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6751 it is probably not worth the effort to support it. */
6752 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6755 || !(res2
= parse_constant_immediate (&str
, &val
,
6758 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6760 info
->imm
.value
= 0;
6761 info
->imm
.is_fp
= 1;
6764 set_fatal_syntax_error (_("immediate zero expected"));
6768 case AARCH64_OPND_IMM_MOV
:
6771 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6772 reg_name_p (str
, REG_TYPE_VN
))
6775 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6776 GE_OPT_PREFIX
, REJECT_ABSENT
));
6777 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6778 later. fix_mov_imm_insn will try to determine a machine
6779 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6780 message if the immediate cannot be moved by a single
6782 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6783 inst
.base
.operands
[i
].skip
= 1;
6787 case AARCH64_OPND_SIMD_IMM
:
6788 case AARCH64_OPND_SIMD_IMM_SFT
:
6789 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6791 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6793 /* need_libopcodes_p */ 1,
6796 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6797 shift, we don't check it here; we leave the checking to
6798 the libopcodes (operand_general_constraint_met_p). By
6799 doing this, we achieve better diagnostics. */
6800 if (skip_past_comma (&str
)
6801 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6803 if (!info
->shifter
.operator_present
6804 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6806 /* Default to LSL if not present. Libopcodes prefers shifter
6807 kind to be explicit. */
6808 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6809 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6813 case AARCH64_OPND_FPIMM
:
6814 case AARCH64_OPND_SIMD_FPIMM
:
6815 case AARCH64_OPND_SVE_FPIMM8
:
6820 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6821 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6822 || !aarch64_imm_float_p (qfloat
))
6825 set_fatal_syntax_error (_("invalid floating-point"
6829 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6830 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6834 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6835 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6836 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6841 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6842 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6845 set_fatal_syntax_error (_("invalid floating-point"
6849 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6850 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6854 case AARCH64_OPND_LIMM
:
6855 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6856 SHIFTED_LOGIC_IMM
));
6857 if (info
->shifter
.operator_present
)
6859 set_fatal_syntax_error
6860 (_("shift not allowed for bitmask immediate"));
6863 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6865 /* need_libopcodes_p */ 1,
6869 case AARCH64_OPND_AIMM
:
6870 if (opcode
->op
== OP_ADD
)
6871 /* ADD may have relocation types. */
6872 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6873 SHIFTED_ARITH_IMM
));
6875 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6876 SHIFTED_ARITH_IMM
));
6877 switch (inst
.reloc
.type
)
6879 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6880 info
->shifter
.amount
= 12;
6882 case BFD_RELOC_UNUSED
:
6883 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6884 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6885 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6886 inst
.reloc
.pc_rel
= 0;
6891 info
->imm
.value
= 0;
6892 if (!info
->shifter
.operator_present
)
6894 /* Default to LSL if not present. Libopcodes prefers shifter
6895 kind to be explicit. */
6896 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6897 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6901 case AARCH64_OPND_HALF
:
6903 /* #<imm16> or relocation. */
6904 int internal_fixup_p
;
6905 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6906 if (internal_fixup_p
)
6907 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6908 skip_whitespace (str
);
6909 if (skip_past_comma (&str
))
6911 /* {, LSL #<shift>} */
6912 if (! aarch64_gas_internal_fixup_p ())
6914 set_fatal_syntax_error (_("can't mix relocation modifier "
6915 "with explicit shift"));
6918 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6921 inst
.base
.operands
[i
].shifter
.amount
= 0;
6922 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6923 inst
.base
.operands
[i
].imm
.value
= 0;
6924 if (! process_movw_reloc_info ())
6929 case AARCH64_OPND_EXCEPTION
:
6930 case AARCH64_OPND_UNDEFINED
:
6931 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6933 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6935 /* need_libopcodes_p */ 0,
6939 case AARCH64_OPND_NZCV
:
6941 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6945 info
->imm
.value
= nzcv
->value
;
6948 po_imm_or_fail (0, 15);
6949 info
->imm
.value
= val
;
6953 case AARCH64_OPND_COND
:
6954 case AARCH64_OPND_COND1
:
6959 while (ISALPHA (*str
));
6960 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6961 if (info
->cond
== NULL
)
6963 set_syntax_error (_("invalid condition"));
6966 else if (operands
[i
] == AARCH64_OPND_COND1
6967 && (info
->cond
->value
& 0xe) == 0xe)
6969 /* Do not allow AL or NV. */
6970 set_default_error ();
6976 case AARCH64_OPND_ADDR_ADRP
:
6977 po_misc_or_fail (parse_adrp (&str
));
6978 /* Clear the value as operand needs to be relocated. */
6979 info
->imm
.value
= 0;
6982 case AARCH64_OPND_ADDR_PCREL14
:
6983 case AARCH64_OPND_ADDR_PCREL19
:
6984 case AARCH64_OPND_ADDR_PCREL21
:
6985 case AARCH64_OPND_ADDR_PCREL26
:
6986 po_misc_or_fail (parse_address (&str
, info
));
6987 if (!info
->addr
.pcrel
)
6989 set_syntax_error (_("invalid pc-relative address"));
6992 if (inst
.gen_lit_pool
6993 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6995 /* Only permit "=value" in the literal load instructions.
6996 The literal will be generated by programmer_friendly_fixup. */
6997 set_syntax_error (_("invalid use of \"=immediate\""));
7000 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7002 set_syntax_error (_("unrecognized relocation suffix"));
7005 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7007 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7008 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7012 info
->imm
.value
= 0;
7013 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7014 switch (opcode
->iclass
)
7018 /* e.g. CBZ or B.COND */
7019 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7020 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7024 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7025 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7029 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7031 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7032 : BFD_RELOC_AARCH64_JUMP26
;
7035 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7036 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7039 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7040 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7046 inst
.reloc
.pc_rel
= 1;
7050 case AARCH64_OPND_ADDR_SIMPLE
:
7051 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7053 /* [<Xn|SP>{, #<simm>}] */
7055 /* First use the normal address-parsing routines, to get
7056 the usual syntax errors. */
7057 po_misc_or_fail (parse_address (&str
, info
));
7058 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7059 || !info
->addr
.preind
|| info
->addr
.postind
7060 || info
->addr
.writeback
)
7062 set_syntax_error (_("invalid addressing mode"));
7066 /* Then retry, matching the specific syntax of these addresses. */
7068 po_char_or_fail ('[');
7069 po_reg_or_fail (REG_TYPE_R64_SP
);
7070 /* Accept optional ", #0". */
7071 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7072 && skip_past_char (&str
, ','))
7074 skip_past_char (&str
, '#');
7075 if (! skip_past_char (&str
, '0'))
7077 set_fatal_syntax_error
7078 (_("the optional immediate offset can only be 0"));
7082 po_char_or_fail (']');
7086 case AARCH64_OPND_ADDR_REGOFF
:
7087 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7088 po_misc_or_fail (parse_address (&str
, info
));
7090 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7091 || !info
->addr
.preind
|| info
->addr
.postind
7092 || info
->addr
.writeback
)
7094 set_syntax_error (_("invalid addressing mode"));
7097 if (!info
->shifter
.operator_present
)
7099 /* Default to LSL if not present. Libopcodes prefers shifter
7100 kind to be explicit. */
7101 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7102 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7104 /* Qualifier to be deduced by libopcodes. */
7107 case AARCH64_OPND_ADDR_SIMM7
:
7108 po_misc_or_fail (parse_address (&str
, info
));
7109 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7110 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7112 set_syntax_error (_("invalid addressing mode"));
7115 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7117 set_syntax_error (_("relocation not allowed"));
7120 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7122 /* need_libopcodes_p */ 1,
7126 case AARCH64_OPND_ADDR_SIMM9
:
7127 case AARCH64_OPND_ADDR_SIMM9_2
:
7128 case AARCH64_OPND_ADDR_SIMM11
:
7129 case AARCH64_OPND_ADDR_SIMM13
:
7130 po_misc_or_fail (parse_address (&str
, info
));
7131 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7132 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7133 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7134 && info
->addr
.writeback
))
7136 set_syntax_error (_("invalid addressing mode"));
7139 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7141 set_syntax_error (_("relocation not allowed"));
7144 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7146 /* need_libopcodes_p */ 1,
7150 case AARCH64_OPND_ADDR_SIMM10
:
7151 case AARCH64_OPND_ADDR_OFFSET
:
7152 po_misc_or_fail (parse_address (&str
, info
));
7153 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7154 || !info
->addr
.preind
|| info
->addr
.postind
)
7156 set_syntax_error (_("invalid addressing mode"));
7159 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7161 set_syntax_error (_("relocation not allowed"));
7164 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7166 /* need_libopcodes_p */ 1,
7170 case AARCH64_OPND_ADDR_UIMM12
:
7171 po_misc_or_fail (parse_address (&str
, info
));
7172 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7173 || !info
->addr
.preind
|| info
->addr
.writeback
)
7175 set_syntax_error (_("invalid addressing mode"));
7178 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7179 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7180 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7182 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7184 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7186 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7188 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7189 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7190 /* Leave qualifier to be determined by libopcodes. */
7193 case AARCH64_OPND_SIMD_ADDR_POST
:
7194 /* [<Xn|SP>], <Xm|#<amount>> */
7195 po_misc_or_fail (parse_address (&str
, info
));
7196 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7198 set_syntax_error (_("invalid addressing mode"));
7201 if (!info
->addr
.offset
.is_reg
)
7203 if (inst
.reloc
.exp
.X_op
== O_constant
)
7204 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7207 set_fatal_syntax_error
7208 (_("writeback value must be an immediate constant"));
7215 case AARCH64_OPND_SME_SM_ZA
:
7217 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7219 set_syntax_error (_("unknown or missing PSTATE field name"));
7222 info
->reg
.regno
= val
;
7225 case AARCH64_OPND_SME_PnT_Wm_imm
:
7226 if (!parse_dual_indexed_reg (&str
, REG_TYPE_PN
,
7227 &info
->indexed_za
, &qualifier
, 0))
7229 info
->qualifier
= qualifier
;
7232 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7233 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7234 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7235 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7236 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7237 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7238 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7239 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7240 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7241 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7242 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7243 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7244 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7245 /* [X<n>{, #imm, MUL VL}]
7247 but recognizing SVE registers. */
7248 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7249 &offset_qualifier
));
7250 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7252 set_syntax_error (_("invalid addressing mode"));
7256 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7257 || !info
->addr
.preind
|| info
->addr
.writeback
)
7259 set_syntax_error (_("invalid addressing mode"));
7262 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7263 || inst
.reloc
.exp
.X_op
!= O_constant
)
7265 /* Make sure this has priority over
7266 "invalid addressing mode". */
7267 set_fatal_syntax_error (_("constant offset required"));
7270 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7273 case AARCH64_OPND_SVE_ADDR_R
:
7274 /* [<Xn|SP>{, <R><m>}]
7275 but recognizing SVE registers. */
7276 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7277 &offset_qualifier
));
7278 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7280 offset_qualifier
= AARCH64_OPND_QLF_X
;
7281 info
->addr
.offset
.is_reg
= 1;
7282 info
->addr
.offset
.regno
= 31;
7284 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7285 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7287 set_syntax_error (_("invalid addressing mode"));
7292 case AARCH64_OPND_SVE_ADDR_RR
:
7293 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7294 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7295 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7296 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7297 case AARCH64_OPND_SVE_ADDR_RX
:
7298 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7299 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7300 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7301 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7302 but recognizing SVE registers. */
7303 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7304 &offset_qualifier
));
7305 if (base_qualifier
!= AARCH64_OPND_QLF_X
7306 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7308 set_syntax_error (_("invalid addressing mode"));
7313 case AARCH64_OPND_SVE_ADDR_RZ
:
7314 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7315 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7316 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7317 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7318 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7319 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7320 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7321 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7322 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7323 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7324 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7325 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7326 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7327 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7328 &offset_qualifier
));
7329 if (base_qualifier
!= AARCH64_OPND_QLF_X
7330 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7331 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7333 set_syntax_error (_("invalid addressing mode"));
7336 info
->qualifier
= offset_qualifier
;
7339 case AARCH64_OPND_SVE_ADDR_ZX
:
7340 /* [Zn.<T>{, <Xm>}]. */
7341 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7342 &offset_qualifier
));
7344 base_qualifier either S_S or S_D
7345 offset_qualifier must be X
7347 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7348 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7349 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7351 set_syntax_error (_("invalid addressing mode"));
7354 info
->qualifier
= base_qualifier
;
7355 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7356 || !info
->addr
.preind
|| info
->addr
.writeback
7357 || info
->shifter
.operator_present
!= 0)
7359 set_syntax_error (_("invalid addressing mode"));
7362 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7366 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7367 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7368 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7369 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7370 /* [Z<n>.<T>{, #imm}] */
7371 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7372 &offset_qualifier
));
7373 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7374 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7376 set_syntax_error (_("invalid addressing mode"));
7379 info
->qualifier
= base_qualifier
;
7382 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7383 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7384 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7385 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7386 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7390 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7392 here since we get better error messages by leaving it to
7393 the qualifier checking routines. */
7394 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7395 &offset_qualifier
));
7396 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7397 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7398 || offset_qualifier
!= base_qualifier
)
7400 set_syntax_error (_("invalid addressing mode"));
7403 info
->qualifier
= base_qualifier
;
7406 case AARCH64_OPND_SYSREG
:
7408 uint32_t sysreg_flags
;
7409 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7410 &sysreg_flags
)) == PARSE_FAIL
)
7412 set_syntax_error (_("unknown or missing system register name"));
7415 inst
.base
.operands
[i
].sysreg
.value
= val
;
7416 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7420 case AARCH64_OPND_PSTATEFIELD
:
7422 uint32_t sysreg_flags
;
7423 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7424 &sysreg_flags
)) == PARSE_FAIL
)
7426 set_syntax_error (_("unknown or missing PSTATE field name"));
7429 inst
.base
.operands
[i
].pstatefield
= val
;
7430 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7434 case AARCH64_OPND_SYSREG_IC
:
7435 inst
.base
.operands
[i
].sysins_op
=
7436 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7439 case AARCH64_OPND_SYSREG_DC
:
7440 inst
.base
.operands
[i
].sysins_op
=
7441 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7444 case AARCH64_OPND_SYSREG_AT
:
7445 inst
.base
.operands
[i
].sysins_op
=
7446 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7449 case AARCH64_OPND_SYSREG_SR
:
7450 inst
.base
.operands
[i
].sysins_op
=
7451 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7454 case AARCH64_OPND_SYSREG_TLBI
:
7455 inst
.base
.operands
[i
].sysins_op
=
7456 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7458 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7460 set_fatal_syntax_error ( _("unknown or missing operation name"));
7465 case AARCH64_OPND_BARRIER
:
7466 case AARCH64_OPND_BARRIER_ISB
:
7467 val
= parse_barrier (&str
);
7468 if (val
!= PARSE_FAIL
7469 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7471 /* ISB only accepts options name 'sy'. */
7473 (_("the specified option is not accepted in ISB"));
7474 /* Turn off backtrack as this optional operand is present. */
7478 if (val
!= PARSE_FAIL
7479 && operands
[i
] == AARCH64_OPND_BARRIER
)
7481 /* Regular barriers accept options CRm (C0-C15).
7482 DSB nXS barrier variant accepts values > 15. */
7483 if (val
< 0 || val
> 15)
7485 set_syntax_error (_("the specified option is not accepted in DSB"));
7489 /* This is an extension to accept a 0..15 immediate. */
7490 if (val
== PARSE_FAIL
)
7491 po_imm_or_fail (0, 15);
7492 info
->barrier
= aarch64_barrier_options
+ val
;
7495 case AARCH64_OPND_BARRIER_DSB_NXS
:
7496 val
= parse_barrier (&str
);
7497 if (val
!= PARSE_FAIL
)
7499 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7500 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7502 set_syntax_error (_("the specified option is not accepted in DSB"));
7503 /* Turn off backtrack as this optional operand is present. */
7510 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7511 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7512 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7514 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7516 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7520 /* Option index is encoded as 2-bit value in val<3:2>. */
7521 val
= (val
>> 2) - 4;
7522 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7525 case AARCH64_OPND_PRFOP
:
7526 val
= parse_pldop (&str
);
7527 /* This is an extension to accept a 0..31 immediate. */
7528 if (val
== PARSE_FAIL
)
7529 po_imm_or_fail (0, 31);
7530 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7533 case AARCH64_OPND_BARRIER_PSB
:
7534 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7535 if (val
== PARSE_FAIL
)
7539 case AARCH64_OPND_BTI_TARGET
:
7540 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7541 if (val
== PARSE_FAIL
)
7545 case AARCH64_OPND_SME_ZAda_2b
:
7546 case AARCH64_OPND_SME_ZAda_3b
:
7547 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
, 0);
7550 info
->reg
.regno
= reg
->number
;
7551 info
->qualifier
= qualifier
;
7554 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7555 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7556 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7557 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7558 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7561 : !parse_dual_indexed_reg (&str
, REG_TYPE_ZATHV
,
7562 &info
->indexed_za
, &qualifier
, 0))
7564 info
->qualifier
= qualifier
;
7567 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7568 val
= parse_sme_list_of_64bit_tiles (&str
);
7569 if (val
== PARSE_FAIL
)
7571 info
->imm
.value
= val
;
7574 case AARCH64_OPND_SME_ZA_array
:
7575 if (!parse_dual_indexed_reg (&str
, REG_TYPE_ZA
,
7576 &info
->indexed_za
, &qualifier
, 0))
7578 info
->qualifier
= qualifier
;
7581 case AARCH64_OPND_MOPS_ADDR_Rd
:
7582 case AARCH64_OPND_MOPS_ADDR_Rs
:
7583 po_char_or_fail ('[');
7584 if (!parse_x0_to_x30 (&str
, info
))
7586 po_char_or_fail (']');
7587 po_char_or_fail ('!');
7590 case AARCH64_OPND_MOPS_WB_Rn
:
7591 if (!parse_x0_to_x30 (&str
, info
))
7593 po_char_or_fail ('!');
7597 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7600 /* If we get here, this operand was successfully parsed. */
7601 inst
.base
.operands
[i
].present
= 1;
7605 /* The parse routine should already have set the error, but in case
7606 not, set a default one here. */
7608 set_default_error ();
7610 if (! backtrack_pos
)
7611 goto parse_operands_return
;
7614 /* We reach here because this operand is marked as optional, and
7615 either no operand was supplied or the operand was supplied but it
7616 was syntactically incorrect. In the latter case we report an
7617 error. In the former case we perform a few more checks before
7618 dropping through to the code to insert the default operand. */
7620 char *tmp
= backtrack_pos
;
7621 char endchar
= END_OF_INSN
;
7623 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7625 skip_past_char (&tmp
, ',');
7627 if (*tmp
!= endchar
)
7628 /* The user has supplied an operand in the wrong format. */
7629 goto parse_operands_return
;
7631 /* Make sure there is not a comma before the optional operand.
7632 For example the fifth operand of 'sys' is optional:
7634 sys #0,c0,c0,#0, <--- wrong
7635 sys #0,c0,c0,#0 <--- correct. */
7636 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7638 set_fatal_syntax_error
7639 (_("unexpected comma before the omitted optional operand"));
7640 goto parse_operands_return
;
7644 /* Reaching here means we are dealing with an optional operand that is
7645 omitted from the assembly line. */
7646 gas_assert (optional_operand_p (opcode
, i
));
7648 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7650 /* Try again, skipping the optional operand at backtrack_pos. */
7651 str
= backtrack_pos
;
7654 /* Clear any error record after the omitted optional operand has been
7655 successfully handled. */
7659 /* Check if we have parsed all the operands. */
7660 if (*str
!= '\0' && ! error_p ())
7662 /* Set I to the index of the last present operand; this is
7663 for the purpose of diagnostics. */
7664 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7666 set_fatal_syntax_error
7667 (_("unexpected characters following instruction"));
7670 parse_operands_return
:
7674 inst
.parsing_error
.index
= i
;
7675 DEBUG_TRACE ("parsing FAIL: %s - %s",
7676 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7677 inst
.parsing_error
.error
);
7678 /* Record the operand error properly; this is useful when there
7679 are multiple instruction templates for a mnemonic name, so that
7680 later on, we can select the error that most closely describes
7682 record_operand_error_info (opcode
, &inst
.parsing_error
);
7687 DEBUG_TRACE ("parsing SUCCESS");
7692 /* It does some fix-up to provide some programmer friendly feature while
7693 keeping the libopcodes happy, i.e. libopcodes only accepts
7694 the preferred architectural syntax.
7695 Return FALSE if there is any failure; otherwise return TRUE. */
7698 programmer_friendly_fixup (aarch64_instruction
*instr
)
7700 aarch64_inst
*base
= &instr
->base
;
7701 const aarch64_opcode
*opcode
= base
->opcode
;
7702 enum aarch64_op op
= opcode
->op
;
7703 aarch64_opnd_info
*operands
= base
->operands
;
7705 DEBUG_TRACE ("enter");
7707 switch (opcode
->iclass
)
7710 /* TBNZ Xn|Wn, #uimm6, label
7711 Test and Branch Not Zero: conditionally jumps to label if bit number
7712 uimm6 in register Xn is not zero. The bit number implies the width of
7713 the register, which may be written and should be disassembled as Wn if
7714 uimm is less than 32. */
7715 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7717 if (operands
[1].imm
.value
>= 32)
7719 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7723 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7727 /* LDR Wt, label | =value
7728 As a convenience assemblers will typically permit the notation
7729 "=value" in conjunction with the pc-relative literal load instructions
7730 to automatically place an immediate value or symbolic address in a
7731 nearby literal pool and generate a hidden label which references it.
7732 ISREG has been set to 0 in the case of =value. */
7733 if (instr
->gen_lit_pool
7734 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7736 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7737 if (op
== OP_LDRSW_LIT
)
7739 if (instr
->reloc
.exp
.X_op
!= O_constant
7740 && instr
->reloc
.exp
.X_op
!= O_big
7741 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7743 record_operand_error (opcode
, 1,
7744 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7745 _("constant expression expected"));
7748 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7750 record_operand_error (opcode
, 1,
7751 AARCH64_OPDE_OTHER_ERROR
,
7752 _("literal pool insertion failed"));
7760 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7761 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7762 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7763 A programmer-friendly assembler should accept a destination Xd in
7764 place of Wd, however that is not the preferred form for disassembly.
7766 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7767 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7768 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7769 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7774 /* In the 64-bit form, the final register operand is written as Wm
7775 for all but the (possibly omitted) UXTX/LSL and SXTX
7777 As a programmer-friendly assembler, we accept e.g.
7778 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7779 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7780 int idx
= aarch64_operand_index (opcode
->operands
,
7781 AARCH64_OPND_Rm_EXT
);
7782 gas_assert (idx
== 1 || idx
== 2);
7783 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7784 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7785 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7786 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7787 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7788 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7796 DEBUG_TRACE ("exit with SUCCESS");
7800 /* Check for loads and stores that will cause unpredictable behavior. */
7803 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7805 aarch64_inst
*base
= &instr
->base
;
7806 const aarch64_opcode
*opcode
= base
->opcode
;
7807 const aarch64_opnd_info
*opnds
= base
->operands
;
7808 switch (opcode
->iclass
)
7815 /* Loading/storing the base register is unpredictable if writeback. */
7816 if ((aarch64_get_operand_class (opnds
[0].type
)
7817 == AARCH64_OPND_CLASS_INT_REG
)
7818 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7819 && opnds
[1].addr
.base_regno
!= REG_SP
7820 /* Exempt STG/STZG/ST2G/STZ2G. */
7821 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7822 && opnds
[1].addr
.writeback
)
7823 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7827 case ldstnapair_offs
:
7828 case ldstpair_indexed
:
7829 /* Loading/storing the base register is unpredictable if writeback. */
7830 if ((aarch64_get_operand_class (opnds
[0].type
)
7831 == AARCH64_OPND_CLASS_INT_REG
)
7832 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7833 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7834 && opnds
[2].addr
.base_regno
!= REG_SP
7836 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7837 && opnds
[2].addr
.writeback
)
7838 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7839 /* Load operations must load different registers. */
7840 if ((opcode
->opcode
& (1 << 22))
7841 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7842 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7846 if ((aarch64_get_operand_class (opnds
[0].type
)
7847 == AARCH64_OPND_CLASS_INT_REG
)
7848 && (aarch64_get_operand_class (opnds
[1].type
)
7849 == AARCH64_OPND_CLASS_INT_REG
))
7851 if ((opcode
->opcode
& (1 << 22)))
7853 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7854 if ((opcode
->opcode
& (1 << 21))
7855 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7856 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7860 /* Store-Exclusive is unpredictable if Rt == Rs. */
7861 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7863 (_("unpredictable: identical transfer and status registers"
7866 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7868 if (!(opcode
->opcode
& (1 << 21)))
7869 /* Store-Exclusive is unpredictable if Rn == Rs. */
7871 (_("unpredictable: identical base and status registers"
7874 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7876 (_("unpredictable: "
7877 "identical transfer and status registers"
7881 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7882 if ((opcode
->opcode
& (1 << 21))
7883 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7884 && opnds
[3].reg
.regno
!= REG_SP
)
7885 as_warn (_("unpredictable: identical base and status registers"
7897 force_automatic_sequence_close (void)
7899 struct aarch64_segment_info_type
*tc_seg_info
;
7901 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7902 if (tc_seg_info
->insn_sequence
.instr
)
7904 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7905 _("previous `%s' sequence has not been closed"),
7906 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7907 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7911 /* A wrapper function to interface with libopcodes on encoding and
7912 record the error message if there is any.
7914 Return TRUE on success; otherwise return FALSE. */
7917 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7920 aarch64_operand_error error_info
;
7921 memset (&error_info
, '\0', sizeof (error_info
));
7922 error_info
.kind
= AARCH64_OPDE_NIL
;
7923 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7924 && !error_info
.non_fatal
)
7927 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7928 record_operand_error_info (opcode
, &error_info
);
7929 return error_info
.non_fatal
;
7932 #ifdef DEBUG_AARCH64
7934 dump_opcode_operands (const aarch64_opcode
*opcode
)
7937 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7939 aarch64_verbose ("\t\t opnd%d: %s", i
,
7940 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7941 ? aarch64_get_operand_name (opcode
->operands
[i
])
7942 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7946 #endif /* DEBUG_AARCH64 */
7948 /* This is the guts of the machine-dependent assembler. STR points to a
7949 machine dependent instruction. This function is supposed to emit
7950 the frags/bytes it assembles to. */
7953 md_assemble (char *str
)
7955 templates
*template;
7956 const aarch64_opcode
*opcode
;
7957 struct aarch64_segment_info_type
*tc_seg_info
;
7958 aarch64_inst
*inst_base
;
7959 unsigned saved_cond
;
7961 /* Align the previous label if needed. */
7962 if (last_label_seen
!= NULL
)
7964 symbol_set_frag (last_label_seen
, frag_now
);
7965 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7966 S_SET_SEGMENT (last_label_seen
, now_seg
);
7969 /* Update the current insn_sequence from the segment. */
7970 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7971 insn_sequence
= &tc_seg_info
->insn_sequence
;
7972 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7974 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7976 DEBUG_TRACE ("\n\n");
7977 DEBUG_TRACE ("==============================");
7978 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7980 /* Scan up to the end of the mnemonic, which must end in whitespace,
7981 '.', or end of string. */
7984 for (; is_part_of_name (*p
); p
++)
7985 if (*p
== '.' && !dot
)
7990 as_bad (_("unknown mnemonic -- `%s'"), str
);
7994 if (!dot
&& create_register_alias (str
, p
))
7997 template = opcode_lookup (str
, dot
, p
);
8000 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8005 skip_whitespace (p
);
8008 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8009 get_mnemonic_name (str
), str
);
8013 init_operand_error_report ();
8015 /* Sections are assumed to start aligned. In executable section, there is no
8016 MAP_DATA symbol pending. So we only align the address during
8017 MAP_DATA --> MAP_INSN transition.
8018 For other sections, this is not guaranteed. */
8019 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8020 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8021 frag_align_code (2, 0);
8023 saved_cond
= inst
.cond
;
8024 reset_aarch64_instruction (&inst
);
8025 inst
.cond
= saved_cond
;
8027 /* Iterate through all opcode entries with the same mnemonic name. */
8030 opcode
= template->opcode
;
8032 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8033 #ifdef DEBUG_AARCH64
8035 dump_opcode_operands (opcode
);
8036 #endif /* DEBUG_AARCH64 */
8038 mapping_state (MAP_INSN
);
8040 inst_base
= &inst
.base
;
8041 inst_base
->opcode
= opcode
;
8043 /* Truly conditionally executed instructions, e.g. b.cond. */
8044 if (opcode
->flags
& F_COND
)
8046 gas_assert (inst
.cond
!= COND_ALWAYS
);
8047 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8048 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8050 else if (inst
.cond
!= COND_ALWAYS
)
8052 /* It shouldn't arrive here, where the assembly looks like a
8053 conditional instruction but the found opcode is unconditional. */
8058 if (parse_operands (p
, opcode
)
8059 && programmer_friendly_fixup (&inst
)
8060 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8062 /* Check that this instruction is supported for this CPU. */
8063 if (!opcode
->avariant
8064 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8066 as_bad (_("selected processor does not support `%s'"), str
);
8070 warn_unpredictable_ldst (&inst
, str
);
8072 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8073 || !inst
.reloc
.need_libopcodes_p
)
8077 /* If there is relocation generated for the instruction,
8078 store the instruction information for the future fix-up. */
8079 struct aarch64_inst
*copy
;
8080 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8081 copy
= XNEW (struct aarch64_inst
);
8082 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8086 /* Issue non-fatal messages if any. */
8087 output_operand_error_report (str
, true);
8091 template = template->next
;
8092 if (template != NULL
)
8094 reset_aarch64_instruction (&inst
);
8095 inst
.cond
= saved_cond
;
8098 while (template != NULL
);
8100 /* Issue the error messages if any. */
8101 output_operand_error_report (str
, false);
8104 /* Various frobbings of labels and their addresses. */
8107 aarch64_start_line_hook (void)
8109 last_label_seen
= NULL
;
8113 aarch64_frob_label (symbolS
* sym
)
8115 last_label_seen
= sym
;
8117 dwarf2_emit_label (sym
);
8121 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8123 /* Check to see if we have a block to close. */
8124 force_automatic_sequence_close ();
8128 aarch64_data_in_code (void)
8130 if (startswith (input_line_pointer
+ 1, "data:"))
8132 *input_line_pointer
= '/';
8133 input_line_pointer
+= 5;
8134 *input_line_pointer
= 0;
8142 aarch64_canonicalize_symbol_name (char *name
)
8146 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8147 *(name
+ len
- 5) = 0;
8152 /* Table of all register names defined by default. The user can
8153 define additional names with .req. Note that all register names
8154 should appear in both upper and lowercase variants. Some registers
8155 also have mixed-case names. */
8157 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8158 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8159 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8160 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8161 #define REGSET16(p,t) \
8162 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8163 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8164 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8165 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8166 #define REGSET16S(p,s,t) \
8167 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8168 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8169 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8170 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8171 #define REGSET31(p,t) \
8173 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8174 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8175 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8176 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8177 #define REGSET(p,t) \
8178 REGSET31(p,t), REGNUM(p,31,t)
8180 /* These go into aarch64_reg_hsh hash-table. */
8181 static const reg_entry reg_names
[] = {
8182 /* Integer registers. */
8183 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8184 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8186 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8187 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8188 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8189 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8190 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8191 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8193 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8194 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8196 /* Floating-point single precision registers. */
8197 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8199 /* Floating-point double precision registers. */
8200 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8202 /* Floating-point half precision registers. */
8203 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8205 /* Floating-point byte precision registers. */
8206 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8208 /* Floating-point quad precision registers. */
8209 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8211 /* FP/SIMD registers. */
8212 REGSET (v
, VN
), REGSET (V
, VN
),
8214 /* SVE vector registers. */
8215 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8217 /* SVE predicate registers. */
8218 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8220 /* SME ZA. We model this as a register because it acts syntactically
8221 like ZA0H, supporting qualifier suffixes and indexing. */
8222 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8224 /* SME ZA tile registers. */
8225 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8227 /* SME ZA tile registers (horizontal slice). */
8228 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8230 /* SME ZA tile registers (vertical slice). */
8231 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8249 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8250 static const asm_nzcv nzcv_names
[] = {
8251 {"nzcv", B (n
, z
, c
, v
)},
8252 {"nzcV", B (n
, z
, c
, V
)},
8253 {"nzCv", B (n
, z
, C
, v
)},
8254 {"nzCV", B (n
, z
, C
, V
)},
8255 {"nZcv", B (n
, Z
, c
, v
)},
8256 {"nZcV", B (n
, Z
, c
, V
)},
8257 {"nZCv", B (n
, Z
, C
, v
)},
8258 {"nZCV", B (n
, Z
, C
, V
)},
8259 {"Nzcv", B (N
, z
, c
, v
)},
8260 {"NzcV", B (N
, z
, c
, V
)},
8261 {"NzCv", B (N
, z
, C
, v
)},
8262 {"NzCV", B (N
, z
, C
, V
)},
8263 {"NZcv", B (N
, Z
, c
, v
)},
8264 {"NZcV", B (N
, Z
, c
, V
)},
8265 {"NZCv", B (N
, Z
, C
, v
)},
8266 {"NZCV", B (N
, Z
, C
, V
)}
8279 /* MD interface: bits in the object file. */
8281 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8282 for use in the a.out file, and stores them in the array pointed to by buf.
8283 This knows about the endian-ness of the target machine and does
8284 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8285 2 (short) and 4 (long) Floating numbers are put out as a series of
8286 LITTLENUMS (shorts, here at least). */
8289 md_number_to_chars (char *buf
, valueT val
, int n
)
8291 if (target_big_endian
)
8292 number_to_chars_bigendian (buf
, val
, n
);
8294 number_to_chars_littleendian (buf
, val
, n
);
8297 /* MD interface: Sections. */
8299 /* Estimate the size of a frag before relaxing. Assume everything fits in
8303 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8309 /* Round up a section size to the appropriate boundary. */
8312 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8317 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8318 of an rs_align_code fragment.
8320 Here we fill the frag with the appropriate info for padding the
8321 output stream. The resulting frag will consist of a fixed (fr_fix)
8322 and of a repeating (fr_var) part.
8324 The fixed content is always emitted before the repeating content and
8325 these two parts are used as follows in constructing the output:
8326 - the fixed part will be used to align to a valid instruction word
8327 boundary, in case that we start at a misaligned address; as no
8328 executable instruction can live at the misaligned location, we
8329 simply fill with zeros;
8330 - the variable part will be used to cover the remaining padding and
8331 we fill using the AArch64 NOP instruction.
8333 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8334 enough storage space for up to 3 bytes for padding the back to a valid
8335 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8338 aarch64_handle_align (fragS
* fragP
)
8340 /* NOP = d503201f */
8341 /* AArch64 instructions are always little-endian. */
8342 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8344 int bytes
, fix
, noop_size
;
8347 if (fragP
->fr_type
!= rs_align_code
)
8350 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8351 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8354 gas_assert (fragP
->tc_frag_data
.recorded
);
8357 noop_size
= sizeof (aarch64_noop
);
8359 fix
= bytes
& (noop_size
- 1);
8362 #if defined OBJ_ELF || defined OBJ_COFF
8363 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8367 fragP
->fr_fix
+= fix
;
8371 memcpy (p
, aarch64_noop
, noop_size
);
8372 fragP
->fr_var
= noop_size
;
8375 /* Perform target specific initialisation of a frag.
8376 Note - despite the name this initialisation is not done when the frag
8377 is created, but only when its type is assigned. A frag can be created
8378 and used a long time before its type is set, so beware of assuming that
8379 this initialisation is performed first. */
8383 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8384 int max_chars ATTRIBUTE_UNUSED
)
8388 #else /* OBJ_ELF is defined. */
8390 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8392 /* Record a mapping symbol for alignment frags. We will delete this
8393 later if the alignment ends up empty. */
8394 if (!fragP
->tc_frag_data
.recorded
)
8395 fragP
->tc_frag_data
.recorded
= 1;
8397 /* PR 21809: Do not set a mapping state for debug sections
8398 - it just confuses other tools. */
8399 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8402 switch (fragP
->fr_type
)
8406 mapping_state_2 (MAP_DATA
, max_chars
);
8409 /* PR 20364: We can get alignment frags in code sections,
8410 so do not just assume that we should use the MAP_DATA state. */
8411 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8414 mapping_state_2 (MAP_INSN
, max_chars
);
8421 /* Whether SFrame stack trace info is supported. */
8424 aarch64_support_sframe_p (void)
8426 /* At this time, SFrame is supported for aarch64 only. */
8427 return (aarch64_abi
== AARCH64_ABI_LP64
);
8430 /* Specify if RA tracking is needed. */
8433 aarch64_sframe_ra_tracking_p (void)
8438 /* Specify the fixed offset to recover RA from CFA.
8439 (useful only when RA tracking is not needed). */
8442 aarch64_sframe_cfa_ra_offset (void)
8444 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8447 /* Get the abi/arch indentifier for SFrame. */
8450 aarch64_sframe_get_abi_arch (void)
8452 unsigned char sframe_abi_arch
= 0;
8454 if (aarch64_support_sframe_p ())
8456 sframe_abi_arch
= target_big_endian
8457 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8458 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8461 return sframe_abi_arch
;
8464 #endif /* OBJ_ELF */
8466 /* Initialize the DWARF-2 unwind information for this procedure. */
8469 tc_aarch64_frame_initial_instructions (void)
8471 cfi_add_CFA_def_cfa (REG_SP
, 0);
8474 /* Convert REGNAME to a DWARF-2 register number. */
8477 tc_aarch64_regname_to_dw2regnum (char *regname
)
8479 const reg_entry
*reg
= parse_reg (®name
);
8485 case REG_TYPE_SP_32
:
8486 case REG_TYPE_SP_64
:
8496 return reg
->number
+ 64;
8504 /* Implement DWARF2_ADDR_SIZE. */
8507 aarch64_dwarf2_addr_size (void)
8513 return bfd_arch_bits_per_address (stdoutput
) / 8;
8516 /* MD interface: Symbol and relocation handling. */
8518 /* Return the address within the segment that a PC-relative fixup is
8519 relative to. For AArch64 PC-relative fixups applied to instructions
8520 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8523 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8525 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8527 /* If this is pc-relative and we are going to emit a relocation
8528 then we just want to put out any pipeline compensation that the linker
8529 will need. Otherwise we want to use the calculated base. */
8531 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8532 || aarch64_force_relocation (fixP
)))
8535 /* AArch64 should be consistent for all pc-relative relocations. */
8536 return base
+ AARCH64_PCREL_OFFSET
;
8539 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8540 Otherwise we have no need to default values of symbols. */
8543 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8546 if (name
[0] == '_' && name
[1] == 'G'
8547 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8551 if (symbol_find (name
))
8552 as_bad (_("GOT already in the symbol table"));
8554 GOT_symbol
= symbol_new (name
, undefined_section
,
8555 &zero_address_frag
, 0);
8565 /* Return non-zero if the indicated VALUE has overflowed the maximum
8566 range expressible by a unsigned number with the indicated number of
8570 unsigned_overflow (valueT value
, unsigned bits
)
8573 if (bits
>= sizeof (valueT
) * 8)
8575 lim
= (valueT
) 1 << bits
;
8576 return (value
>= lim
);
8580 /* Return non-zero if the indicated VALUE has overflowed the maximum
8581 range expressible by an signed number with the indicated number of
8585 signed_overflow (offsetT value
, unsigned bits
)
8588 if (bits
>= sizeof (offsetT
) * 8)
8590 lim
= (offsetT
) 1 << (bits
- 1);
8591 return (value
< -lim
|| value
>= lim
);
8594 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8595 unsigned immediate offset load/store instruction, try to encode it as
8596 an unscaled, 9-bit, signed immediate offset load/store instruction.
8597 Return TRUE if it is successful; otherwise return FALSE.
8599 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8600 in response to the standard LDR/STR mnemonics when the immediate offset is
8601 unambiguous, i.e. when it is negative or unaligned. */
8604 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8607 enum aarch64_op new_op
;
8608 const aarch64_opcode
*new_opcode
;
8610 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8612 switch (instr
->opcode
->op
)
8614 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8615 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8616 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8617 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8618 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8619 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8620 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8621 case OP_STR_POS
: new_op
= OP_STUR
; break;
8622 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8623 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8624 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8625 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8626 default: new_op
= OP_NIL
; break;
8629 if (new_op
== OP_NIL
)
8632 new_opcode
= aarch64_get_opcode (new_op
);
8633 gas_assert (new_opcode
!= NULL
);
8635 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8636 instr
->opcode
->op
, new_opcode
->op
);
8638 aarch64_replace_opcode (instr
, new_opcode
);
8640 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8641 qualifier matching may fail because the out-of-date qualifier will
8642 prevent the operand being updated with a new and correct qualifier. */
8643 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8644 AARCH64_OPND_ADDR_SIMM9
);
8645 gas_assert (idx
== 1);
8646 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8648 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8650 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8657 /* Called by fix_insn to fix a MOV immediate alias instruction.
8659 Operand for a generic move immediate instruction, which is an alias
8660 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8661 a 32-bit/64-bit immediate value into general register. An assembler error
8662 shall result if the immediate cannot be created by a single one of these
8663 instructions. If there is a choice, then to ensure reversability an
8664 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8667 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8669 const aarch64_opcode
*opcode
;
8671 /* Need to check if the destination is SP/ZR. The check has to be done
8672 before any aarch64_replace_opcode. */
8673 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8674 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8676 instr
->operands
[1].imm
.value
= value
;
8677 instr
->operands
[1].skip
= 0;
8681 /* Try the MOVZ alias. */
8682 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8683 aarch64_replace_opcode (instr
, opcode
);
8684 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8685 &instr
->value
, NULL
, NULL
, insn_sequence
))
8687 put_aarch64_insn (buf
, instr
->value
);
8690 /* Try the MOVK alias. */
8691 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8692 aarch64_replace_opcode (instr
, opcode
);
8693 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8694 &instr
->value
, NULL
, NULL
, insn_sequence
))
8696 put_aarch64_insn (buf
, instr
->value
);
8701 if (try_mov_bitmask_p
)
8703 /* Try the ORR alias. */
8704 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8705 aarch64_replace_opcode (instr
, opcode
);
8706 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8707 &instr
->value
, NULL
, NULL
, insn_sequence
))
8709 put_aarch64_insn (buf
, instr
->value
);
8714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8715 _("immediate cannot be moved by a single instruction"));
8718 /* An instruction operand which is immediate related may have symbol used
8719 in the assembly, e.g.
8722 .set u32, 0x00ffff00
8724 At the time when the assembly instruction is parsed, a referenced symbol,
8725 like 'u32' in the above example may not have been seen; a fixS is created
8726 in such a case and is handled here after symbols have been resolved.
8727 Instruction is fixed up with VALUE using the information in *FIXP plus
8728 extra information in FLAGS.
8730 This function is called by md_apply_fix to fix up instructions that need
8731 a fix-up described above but does not involve any linker-time relocation. */
8734 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8738 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8739 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8740 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8744 /* Now the instruction is about to be fixed-up, so the operand that
8745 was previously marked as 'ignored' needs to be unmarked in order
8746 to get the encoding done properly. */
8747 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8748 new_inst
->operands
[idx
].skip
= 0;
8751 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8755 case AARCH64_OPND_EXCEPTION
:
8756 case AARCH64_OPND_UNDEFINED
:
8757 if (unsigned_overflow (value
, 16))
8758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8759 _("immediate out of range"));
8760 insn
= get_aarch64_insn (buf
);
8761 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8762 put_aarch64_insn (buf
, insn
);
8765 case AARCH64_OPND_AIMM
:
8766 /* ADD or SUB with immediate.
8767 NOTE this assumes we come here with a add/sub shifted reg encoding
8768 3 322|2222|2 2 2 21111 111111
8769 1 098|7654|3 2 1 09876 543210 98765 43210
8770 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8771 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8772 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8773 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8775 3 322|2222|2 2 221111111111
8776 1 098|7654|3 2 109876543210 98765 43210
8777 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8778 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8779 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8780 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8781 Fields sf Rn Rd are already set. */
8782 insn
= get_aarch64_insn (buf
);
8786 insn
= reencode_addsub_switch_add_sub (insn
);
8790 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8791 && unsigned_overflow (value
, 12))
8793 /* Try to shift the value by 12 to make it fit. */
8794 if (((value
>> 12) << 12) == value
8795 && ! unsigned_overflow (value
, 12 + 12))
8798 insn
|= encode_addsub_imm_shift_amount (1);
8802 if (unsigned_overflow (value
, 12))
8803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8804 _("immediate out of range"));
8806 insn
|= encode_addsub_imm (value
);
8808 put_aarch64_insn (buf
, insn
);
8811 case AARCH64_OPND_SIMD_IMM
:
8812 case AARCH64_OPND_SIMD_IMM_SFT
:
8813 case AARCH64_OPND_LIMM
:
8814 /* Bit mask immediate. */
8815 gas_assert (new_inst
!= NULL
);
8816 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8817 new_inst
->operands
[idx
].imm
.value
= value
;
8818 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8819 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8820 put_aarch64_insn (buf
, new_inst
->value
);
8822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8823 _("invalid immediate"));
8826 case AARCH64_OPND_HALF
:
8827 /* 16-bit unsigned immediate. */
8828 if (unsigned_overflow (value
, 16))
8829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8830 _("immediate out of range"));
8831 insn
= get_aarch64_insn (buf
);
8832 insn
|= encode_movw_imm (value
& 0xffff);
8833 put_aarch64_insn (buf
, insn
);
8836 case AARCH64_OPND_IMM_MOV
:
8837 /* Operand for a generic move immediate instruction, which is
8838 an alias instruction that generates a single MOVZ, MOVN or ORR
8839 instruction to loads a 32-bit/64-bit immediate value into general
8840 register. An assembler error shall result if the immediate cannot be
8841 created by a single one of these instructions. If there is a choice,
8842 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8843 and MOVZ or MOVN to ORR. */
8844 gas_assert (new_inst
!= NULL
);
8845 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8848 case AARCH64_OPND_ADDR_SIMM7
:
8849 case AARCH64_OPND_ADDR_SIMM9
:
8850 case AARCH64_OPND_ADDR_SIMM9_2
:
8851 case AARCH64_OPND_ADDR_SIMM10
:
8852 case AARCH64_OPND_ADDR_UIMM12
:
8853 case AARCH64_OPND_ADDR_SIMM11
:
8854 case AARCH64_OPND_ADDR_SIMM13
:
8855 /* Immediate offset in an address. */
8856 insn
= get_aarch64_insn (buf
);
8858 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8859 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8860 || new_inst
->opcode
->operands
[2] == opnd
);
8862 /* Get the index of the address operand. */
8863 if (new_inst
->opcode
->operands
[1] == opnd
)
8864 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8867 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8870 /* Update the resolved offset value. */
8871 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8873 /* Encode/fix-up. */
8874 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8875 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8877 put_aarch64_insn (buf
, new_inst
->value
);
8880 else if (new_inst
->opcode
->iclass
== ldst_pos
8881 && try_to_encode_as_unscaled_ldst (new_inst
))
8883 put_aarch64_insn (buf
, new_inst
->value
);
8887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8888 _("immediate offset out of range"));
8893 as_fatal (_("unhandled operand code %d"), opnd
);
8897 /* Apply a fixup (fixP) to segment data, once it has been determined
8898 by our caller that we have all the info we need to fix it up.
8900 Parameter valP is the pointer to the value of the bits. */
8903 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8905 offsetT value
= *valP
;
8907 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8909 unsigned flags
= fixP
->fx_addnumber
;
8911 DEBUG_TRACE ("\n\n");
8912 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8913 DEBUG_TRACE ("Enter md_apply_fix");
8915 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8917 /* Note whether this will delete the relocation. */
8919 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8920 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8923 /* Process the relocations. */
8924 switch (fixP
->fx_r_type
)
8926 case BFD_RELOC_NONE
:
8927 /* This will need to go in the object file. */
8932 case BFD_RELOC_8_PCREL
:
8933 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8934 md_number_to_chars (buf
, value
, 1);
8938 case BFD_RELOC_16_PCREL
:
8939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8940 md_number_to_chars (buf
, value
, 2);
8944 case BFD_RELOC_32_PCREL
:
8945 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8946 md_number_to_chars (buf
, value
, 4);
8950 case BFD_RELOC_64_PCREL
:
8951 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8952 md_number_to_chars (buf
, value
, 8);
8955 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8956 /* We claim that these fixups have been processed here, even if
8957 in fact we generate an error because we do not have a reloc
8958 for them, so tc_gen_reloc() will reject them. */
8960 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8963 _("undefined symbol %s used as an immediate value"),
8964 S_GET_NAME (fixP
->fx_addsy
));
8965 goto apply_fix_return
;
8967 fix_insn (fixP
, flags
, value
);
8970 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8975 _("pc-relative load offset not word aligned"));
8976 if (signed_overflow (value
, 21))
8977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8978 _("pc-relative load offset out of range"));
8979 insn
= get_aarch64_insn (buf
);
8980 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8981 put_aarch64_insn (buf
, insn
);
8985 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8986 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8988 if (signed_overflow (value
, 21))
8989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8990 _("pc-relative address offset out of range"));
8991 insn
= get_aarch64_insn (buf
);
8992 insn
|= encode_adr_imm (value
);
8993 put_aarch64_insn (buf
, insn
);
8997 case BFD_RELOC_AARCH64_BRANCH19
:
8998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9002 _("conditional branch target not word aligned"));
9003 if (signed_overflow (value
, 21))
9004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9005 _("conditional branch out of range"));
9006 insn
= get_aarch64_insn (buf
);
9007 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9008 put_aarch64_insn (buf
, insn
);
9012 case BFD_RELOC_AARCH64_TSTBR14
:
9013 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9017 _("conditional branch target not word aligned"));
9018 if (signed_overflow (value
, 16))
9019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9020 _("conditional branch out of range"));
9021 insn
= get_aarch64_insn (buf
);
9022 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9023 put_aarch64_insn (buf
, insn
);
9027 case BFD_RELOC_AARCH64_CALL26
:
9028 case BFD_RELOC_AARCH64_JUMP26
:
9029 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9033 _("branch target not word aligned"));
9034 if (signed_overflow (value
, 28))
9035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9036 _("branch out of range"));
9037 insn
= get_aarch64_insn (buf
);
9038 insn
|= encode_branch_ofs_26 (value
>> 2);
9039 put_aarch64_insn (buf
, insn
);
9043 case BFD_RELOC_AARCH64_MOVW_G0
:
9044 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9045 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9046 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9047 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9048 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9051 case BFD_RELOC_AARCH64_MOVW_G1
:
9052 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9053 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9054 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9055 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9056 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9059 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9061 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9062 /* Should always be exported to object file, see
9063 aarch64_force_relocation(). */
9064 gas_assert (!fixP
->fx_done
);
9065 gas_assert (seg
->use_rela_p
);
9067 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9069 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9070 /* Should always be exported to object file, see
9071 aarch64_force_relocation(). */
9072 gas_assert (!fixP
->fx_done
);
9073 gas_assert (seg
->use_rela_p
);
9075 case BFD_RELOC_AARCH64_MOVW_G2
:
9076 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9077 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9078 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9079 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9082 case BFD_RELOC_AARCH64_MOVW_G3
:
9083 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9086 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9088 insn
= get_aarch64_insn (buf
);
9092 /* REL signed addend must fit in 16 bits */
9093 if (signed_overflow (value
, 16))
9094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9095 _("offset out of range"));
9099 /* Check for overflow and scale. */
9100 switch (fixP
->fx_r_type
)
9102 case BFD_RELOC_AARCH64_MOVW_G0
:
9103 case BFD_RELOC_AARCH64_MOVW_G1
:
9104 case BFD_RELOC_AARCH64_MOVW_G2
:
9105 case BFD_RELOC_AARCH64_MOVW_G3
:
9106 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9107 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9108 if (unsigned_overflow (value
, scale
+ 16))
9109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9110 _("unsigned value out of range"));
9112 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9113 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9114 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9115 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9116 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9117 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9118 /* NOTE: We can only come here with movz or movn. */
9119 if (signed_overflow (value
, scale
+ 16))
9120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9121 _("signed value out of range"));
9124 /* Force use of MOVN. */
9126 insn
= reencode_movzn_to_movn (insn
);
9130 /* Force use of MOVZ. */
9131 insn
= reencode_movzn_to_movz (insn
);
9135 /* Unchecked relocations. */
9141 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9142 insn
|= encode_movw_imm (value
& 0xffff);
9144 put_aarch64_insn (buf
, insn
);
9148 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9149 fixP
->fx_r_type
= (ilp32_p
9150 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9151 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9152 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9153 /* Should always be exported to object file, see
9154 aarch64_force_relocation(). */
9155 gas_assert (!fixP
->fx_done
);
9156 gas_assert (seg
->use_rela_p
);
9159 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9160 fixP
->fx_r_type
= (ilp32_p
9161 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9162 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9163 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9164 /* Should always be exported to object file, see
9165 aarch64_force_relocation(). */
9166 gas_assert (!fixP
->fx_done
);
9167 gas_assert (seg
->use_rela_p
);
9170 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9171 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9172 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9173 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9174 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9175 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9176 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9177 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9178 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9179 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9180 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9181 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9182 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9183 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9184 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9185 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9186 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9187 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9188 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9189 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9190 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9191 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9192 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9193 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9194 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9195 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9196 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9197 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9198 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9199 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9200 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9201 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9202 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9203 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9204 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9205 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9206 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9207 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9208 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9209 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9210 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9211 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9212 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9213 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9214 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9215 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9216 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9217 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9218 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9219 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9220 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9221 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9222 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9223 /* Should always be exported to object file, see
9224 aarch64_force_relocation(). */
9225 gas_assert (!fixP
->fx_done
);
9226 gas_assert (seg
->use_rela_p
);
9229 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9230 /* Should always be exported to object file, see
9231 aarch64_force_relocation(). */
9232 fixP
->fx_r_type
= (ilp32_p
9233 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9234 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9235 gas_assert (!fixP
->fx_done
);
9236 gas_assert (seg
->use_rela_p
);
9239 case BFD_RELOC_AARCH64_ADD_LO12
:
9240 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9241 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9242 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9243 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9244 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9245 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9246 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9247 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9248 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9249 case BFD_RELOC_AARCH64_LDST128_LO12
:
9250 case BFD_RELOC_AARCH64_LDST16_LO12
:
9251 case BFD_RELOC_AARCH64_LDST32_LO12
:
9252 case BFD_RELOC_AARCH64_LDST64_LO12
:
9253 case BFD_RELOC_AARCH64_LDST8_LO12
:
9254 /* Should always be exported to object file, see
9255 aarch64_force_relocation(). */
9256 gas_assert (!fixP
->fx_done
);
9257 gas_assert (seg
->use_rela_p
);
9260 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9261 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9262 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9265 case BFD_RELOC_UNUSED
:
9266 /* An error will already have been reported. */
9270 case BFD_RELOC_32_SECREL
:
9271 case BFD_RELOC_16_SECIDX
:
9275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9276 _("unexpected %s fixup"),
9277 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9282 /* Free the allocated the struct aarch64_inst.
9283 N.B. currently there are very limited number of fix-up types actually use
9284 this field, so the impact on the performance should be minimal . */
9285 free (fixP
->tc_fix_data
.inst
);
9290 /* Translate internal representation of relocation info to BFD target
9294 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9297 bfd_reloc_code_real_type code
;
9299 reloc
= XNEW (arelent
);
9301 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9302 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9303 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9307 if (section
->use_rela_p
)
9308 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9310 fixp
->fx_offset
= reloc
->address
;
9312 reloc
->addend
= fixp
->fx_offset
;
9314 code
= fixp
->fx_r_type
;
9319 code
= BFD_RELOC_16_PCREL
;
9324 code
= BFD_RELOC_32_PCREL
;
9329 code
= BFD_RELOC_64_PCREL
;
9336 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9337 if (reloc
->howto
== NULL
)
9339 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9341 ("cannot represent %s relocation in this object file format"),
9342 bfd_get_reloc_code_name (code
));
9349 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9352 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9354 bfd_reloc_code_real_type type
;
9358 if (exp
->X_op
== O_secrel
)
9360 exp
->X_op
= O_symbol
;
9361 type
= BFD_RELOC_32_SECREL
;
9363 else if (exp
->X_op
== O_secidx
)
9365 exp
->X_op
= O_symbol
;
9366 type
= BFD_RELOC_16_SECIDX
;
9372 FIXME: @@ Should look at CPU word size. */
9379 type
= BFD_RELOC_16
;
9382 type
= BFD_RELOC_32
;
9385 type
= BFD_RELOC_64
;
9388 as_bad (_("cannot do %u-byte relocation"), size
);
9389 type
= BFD_RELOC_UNUSED
;
9396 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9399 /* Implement md_after_parse_args. This is the earliest time we need to decide
9400 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9403 aarch64_after_parse_args (void)
9405 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9409 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9410 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9411 aarch64_abi
= AARCH64_ABI_ILP32
;
9413 aarch64_abi
= AARCH64_ABI_LP64
;
9415 aarch64_abi
= AARCH64_ABI_LLP64
;
9421 elf64_aarch64_target_format (void)
9424 /* FIXME: What to do for ilp32_p ? */
9425 if (target_big_endian
)
9426 return "elf64-bigaarch64-cloudabi";
9428 return "elf64-littleaarch64-cloudabi";
9430 if (target_big_endian
)
9431 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9433 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9438 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9440 elf_frob_symbol (symp
, puntp
);
9442 #elif defined OBJ_COFF
9444 coff_aarch64_target_format (void)
9446 return "pe-aarch64-little";
9450 /* MD interface: Finalization. */
9452 /* A good place to do this, although this was probably not intended
9453 for this kind of use. We need to dump the literal pool before
9454 references are made to a null symbol pointer. */
9457 aarch64_cleanup (void)
9461 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9463 /* Put it at the end of the relevant section. */
9464 subseg_set (pool
->section
, pool
->sub_section
);
9470 /* Remove any excess mapping symbols generated for alignment frags in
9471 SEC. We may have created a mapping symbol before a zero byte
9472 alignment; remove it if there's a mapping symbol after the
9475 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9476 void *dummy ATTRIBUTE_UNUSED
)
9478 segment_info_type
*seginfo
= seg_info (sec
);
9481 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9484 for (fragp
= seginfo
->frchainP
->frch_root
;
9485 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9487 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9488 fragS
*next
= fragp
->fr_next
;
9490 /* Variable-sized frags have been converted to fixed size by
9491 this point. But if this was variable-sized to start with,
9492 there will be a fixed-size frag after it. So don't handle
9494 if (sym
== NULL
|| next
== NULL
)
9497 if (S_GET_VALUE (sym
) < next
->fr_address
)
9498 /* Not at the end of this frag. */
9500 know (S_GET_VALUE (sym
) == next
->fr_address
);
9504 if (next
->tc_frag_data
.first_map
!= NULL
)
9506 /* Next frag starts with a mapping symbol. Discard this
9508 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9512 if (next
->fr_next
== NULL
)
9514 /* This mapping symbol is at the end of the section. Discard
9516 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9517 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9521 /* As long as we have empty frags without any mapping symbols,
9523 /* If the next frag is non-empty and does not start with a
9524 mapping symbol, then this mapping symbol is required. */
9525 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9528 next
= next
->fr_next
;
9530 while (next
!= NULL
);
9535 /* Adjust the symbol table. */
9538 aarch64_adjust_symtab (void)
9541 /* Remove any overlapping mapping symbols generated by alignment frags. */
9542 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9543 /* Now do generic ELF adjustments. */
9544 elf_adjust_symtab ();
9549 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9551 str_hash_insert (table
, key
, value
, 0);
9555 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9557 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9558 checked_hash_insert (table
, key
, value
);
9562 fill_instruction_hash_table (void)
9564 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9566 while (opcode
->name
!= NULL
)
9568 templates
*templ
, *new_templ
;
9569 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9571 new_templ
= XNEW (templates
);
9572 new_templ
->opcode
= opcode
;
9573 new_templ
->next
= NULL
;
9576 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9579 new_templ
->next
= templ
->next
;
9580 templ
->next
= new_templ
;
9587 convert_to_upper (char *dst
, const char *src
, size_t num
)
9590 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9591 *dst
= TOUPPER (*src
);
9595 /* Assume STR point to a lower-case string, allocate, convert and return
9596 the corresponding upper-case string. */
9597 static inline const char*
9598 get_upper_str (const char *str
)
9601 size_t len
= strlen (str
);
9602 ret
= XNEWVEC (char, len
+ 1);
9603 convert_to_upper (ret
, str
, len
);
9607 /* MD interface: Initialization. */
9615 aarch64_ops_hsh
= str_htab_create ();
9616 aarch64_cond_hsh
= str_htab_create ();
9617 aarch64_shift_hsh
= str_htab_create ();
9618 aarch64_sys_regs_hsh
= str_htab_create ();
9619 aarch64_pstatefield_hsh
= str_htab_create ();
9620 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9621 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9622 aarch64_sys_regs_at_hsh
= str_htab_create ();
9623 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9624 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9625 aarch64_reg_hsh
= str_htab_create ();
9626 aarch64_barrier_opt_hsh
= str_htab_create ();
9627 aarch64_nzcv_hsh
= str_htab_create ();
9628 aarch64_pldop_hsh
= str_htab_create ();
9629 aarch64_hint_opt_hsh
= str_htab_create ();
9631 fill_instruction_hash_table ();
9633 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9634 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9635 (void *) (aarch64_sys_regs
+ i
));
9637 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9638 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9639 aarch64_pstatefields
[i
].name
,
9640 (void *) (aarch64_pstatefields
+ i
));
9642 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9643 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9644 aarch64_sys_regs_ic
[i
].name
,
9645 (void *) (aarch64_sys_regs_ic
+ i
));
9647 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9648 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9649 aarch64_sys_regs_dc
[i
].name
,
9650 (void *) (aarch64_sys_regs_dc
+ i
));
9652 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9653 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9654 aarch64_sys_regs_at
[i
].name
,
9655 (void *) (aarch64_sys_regs_at
+ i
));
9657 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9658 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9659 aarch64_sys_regs_tlbi
[i
].name
,
9660 (void *) (aarch64_sys_regs_tlbi
+ i
));
9662 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9663 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9664 aarch64_sys_regs_sr
[i
].name
,
9665 (void *) (aarch64_sys_regs_sr
+ i
));
9667 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9668 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9669 (void *) (reg_names
+ i
));
9671 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9672 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9673 (void *) (nzcv_names
+ i
));
9675 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9677 const char *name
= aarch64_operand_modifiers
[i
].name
;
9678 checked_hash_insert (aarch64_shift_hsh
, name
,
9679 (void *) (aarch64_operand_modifiers
+ i
));
9680 /* Also hash the name in the upper case. */
9681 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9682 (void *) (aarch64_operand_modifiers
+ i
));
9685 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9688 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9689 the same condition code. */
9690 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9692 const char *name
= aarch64_conds
[i
].names
[j
];
9695 checked_hash_insert (aarch64_cond_hsh
, name
,
9696 (void *) (aarch64_conds
+ i
));
9697 /* Also hash the name in the upper case. */
9698 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9699 (void *) (aarch64_conds
+ i
));
9703 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9705 const char *name
= aarch64_barrier_options
[i
].name
;
9706 /* Skip xx00 - the unallocated values of option. */
9709 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9710 (void *) (aarch64_barrier_options
+ i
));
9711 /* Also hash the name in the upper case. */
9712 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9713 (void *) (aarch64_barrier_options
+ i
));
9716 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9718 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9719 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9720 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9721 /* Also hash the name in the upper case. */
9722 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9723 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9726 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9728 const char* name
= aarch64_prfops
[i
].name
;
9729 /* Skip the unallocated hint encodings. */
9732 checked_hash_insert (aarch64_pldop_hsh
, name
,
9733 (void *) (aarch64_prfops
+ i
));
9734 /* Also hash the name in the upper case. */
9735 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9736 (void *) (aarch64_prfops
+ i
));
9739 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9741 const char* name
= aarch64_hint_options
[i
].name
;
9742 const char* upper_name
= get_upper_str(name
);
9744 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9745 (void *) (aarch64_hint_options
+ i
));
9747 /* Also hash the name in the upper case if not the same. */
9748 if (strcmp (name
, upper_name
) != 0)
9749 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9750 (void *) (aarch64_hint_options
+ i
));
9753 /* Set the cpu variant based on the command-line options. */
9755 mcpu_cpu_opt
= march_cpu_opt
;
9758 mcpu_cpu_opt
= &cpu_default
;
9760 cpu_variant
= *mcpu_cpu_opt
;
9762 /* Record the CPU type. */
9764 mach
= bfd_mach_aarch64_ilp32
;
9766 mach
= bfd_mach_aarch64_llp64
;
9768 mach
= bfd_mach_aarch64
;
9770 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9772 /* FIXME - is there a better way to do it ? */
9773 aarch64_sframe_cfa_sp_reg
= 31;
9774 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9775 aarch64_sframe_cfa_ra_reg
= 30;
9779 /* Command line processing. */
9781 const char *md_shortopts
= "m:";
9783 #ifdef AARCH64_BI_ENDIAN
9784 #define OPTION_EB (OPTION_MD_BASE + 0)
9785 #define OPTION_EL (OPTION_MD_BASE + 1)
9787 #if TARGET_BYTES_BIG_ENDIAN
9788 #define OPTION_EB (OPTION_MD_BASE + 0)
9790 #define OPTION_EL (OPTION_MD_BASE + 1)
9794 struct option md_longopts
[] = {
9796 {"EB", no_argument
, NULL
, OPTION_EB
},
9799 {"EL", no_argument
, NULL
, OPTION_EL
},
9801 {NULL
, no_argument
, NULL
, 0}
9804 size_t md_longopts_size
= sizeof (md_longopts
);
9806 struct aarch64_option_table
9808 const char *option
; /* Option name to match. */
9809 const char *help
; /* Help information. */
9810 int *var
; /* Variable to change. */
9811 int value
; /* What to change it to. */
9812 char *deprecated
; /* If non-null, print this message. */
9815 static struct aarch64_option_table aarch64_opts
[] = {
9816 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9817 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9819 #ifdef DEBUG_AARCH64
9820 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9821 #endif /* DEBUG_AARCH64 */
9822 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9824 {"mno-verbose-error", N_("do not output verbose error messages"),
9825 &verbose_error_p
, 0, NULL
},
9826 {NULL
, NULL
, NULL
, 0, NULL
}
9829 struct aarch64_cpu_option_table
9832 const aarch64_feature_set value
;
9833 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9835 const char *canonical_name
;
9838 /* This list should, at a minimum, contain all the cpu names
9839 recognized by GCC. */
9840 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9841 {"all", AARCH64_ANY
, NULL
},
9842 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9843 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9844 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9845 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9846 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9847 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9848 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9849 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9850 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9851 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9852 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9853 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9854 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9855 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9857 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9858 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9860 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9861 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9863 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9864 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9865 | AARCH64_FEATURE_DOTPROD
9866 | AARCH64_FEATURE_SSBS
),
9868 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9869 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9870 | AARCH64_FEATURE_DOTPROD
9871 | AARCH64_FEATURE_SSBS
),
9873 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9874 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9875 | AARCH64_FEATURE_DOTPROD
9876 | AARCH64_FEATURE_SSBS
),
9878 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9879 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9880 | AARCH64_FEATURE_DOTPROD
9881 | AARCH64_FEATURE_SSBS
),
9883 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9885 | AARCH64_FEATURE_RCPC
9886 | AARCH64_FEATURE_DOTPROD
9887 | AARCH64_FEATURE_SSBS
9888 | AARCH64_FEATURE_PROFILE
),
9890 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9892 | AARCH64_FEATURE_RCPC
9893 | AARCH64_FEATURE_DOTPROD
9894 | AARCH64_FEATURE_SSBS
9895 | AARCH64_FEATURE_PROFILE
),
9897 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9898 AARCH64_FEATURE_DOTPROD
9899 | AARCH64_FEATURE_F16
9900 | AARCH64_FEATURE_FLAGM
9901 | AARCH64_FEATURE_PAC
9902 | AARCH64_FEATURE_PROFILE
9903 | AARCH64_FEATURE_RCPC
9904 | AARCH64_FEATURE_SSBS
),
9906 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9907 AARCH64_FEATURE_BFLOAT16
9908 | AARCH64_FEATURE_I8MM
9909 | AARCH64_FEATURE_MEMTAG
9910 | AARCH64_FEATURE_SVE2_BITPERM
),
9912 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9913 AARCH64_FEATURE_BFLOAT16
9914 | AARCH64_FEATURE_I8MM
9915 | AARCH64_FEATURE_MEMTAG
9916 | AARCH64_FEATURE_SVE2_BITPERM
),
9918 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9919 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9920 | AARCH64_FEATURE_DOTPROD
9921 | AARCH64_FEATURE_PROFILE
),
9923 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9924 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9925 "Samsung Exynos M1"},
9926 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9927 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9928 | AARCH64_FEATURE_RDMA
),
9930 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9931 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9932 | AARCH64_FEATURE_DOTPROD
9933 | AARCH64_FEATURE_SSBS
),
9935 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9936 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9937 | AARCH64_FEATURE_DOTPROD
9938 | AARCH64_FEATURE_PROFILE
),
9940 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9941 AARCH64_FEATURE_BFLOAT16
9942 | AARCH64_FEATURE_I8MM
9943 | AARCH64_FEATURE_F16
9944 | AARCH64_FEATURE_SVE
9945 | AARCH64_FEATURE_SVE2
9946 | AARCH64_FEATURE_SVE2_BITPERM
9947 | AARCH64_FEATURE_MEMTAG
9948 | AARCH64_FEATURE_RNG
),
9950 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9951 AARCH64_FEATURE_PROFILE
9952 | AARCH64_FEATURE_CVADP
9953 | AARCH64_FEATURE_SVE
9954 | AARCH64_FEATURE_SSBS
9955 | AARCH64_FEATURE_RNG
9956 | AARCH64_FEATURE_F16
9957 | AARCH64_FEATURE_BFLOAT16
9958 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9959 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9960 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9961 | AARCH64_FEATURE_RDMA
),
9962 "Qualcomm QDF24XX"},
9963 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9964 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9965 "Qualcomm Saphira"},
9966 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9967 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9969 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9970 AARCH64_FEATURE_CRYPTO
),
9972 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9973 in earlier releases and is superseded by 'xgene1' in all
9975 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9976 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9977 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9978 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9979 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9980 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9982 | AARCH64_FEATURE_RCPC
9983 | AARCH64_FEATURE_DOTPROD
9984 | AARCH64_FEATURE_SSBS
9985 | AARCH64_FEATURE_PROFILE
),
9987 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9988 AARCH64_FEATURE_BFLOAT16
9989 | AARCH64_FEATURE_I8MM
9990 | AARCH64_FEATURE_MEMTAG
9991 | AARCH64_FEATURE_SVE2_BITPERM
),
9993 {"generic", AARCH64_ARCH_V8
, NULL
},
9995 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9998 struct aarch64_arch_option_table
10001 const aarch64_feature_set value
;
10004 /* This list should, at a minimum, contain all the architecture names
10005 recognized by GCC. */
10006 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10007 {"all", AARCH64_ANY
},
10008 {"armv8-a", AARCH64_ARCH_V8
},
10009 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10010 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10011 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10012 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10013 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10014 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10015 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10016 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10017 {"armv8-r", AARCH64_ARCH_V8_R
},
10018 {"armv9-a", AARCH64_ARCH_V9
},
10019 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10020 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10021 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10022 {NULL
, AARCH64_ARCH_NONE
}
10025 /* ISA extensions. */
10026 struct aarch64_option_cpu_value_table
10029 const aarch64_feature_set value
;
10030 const aarch64_feature_set require
; /* Feature dependencies. */
10033 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10034 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10035 AARCH64_ARCH_NONE
},
10036 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10037 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10038 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10039 AARCH64_ARCH_NONE
},
10040 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10041 AARCH64_ARCH_NONE
},
10042 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10043 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10044 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10045 AARCH64_ARCH_NONE
},
10046 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10047 AARCH64_ARCH_NONE
},
10048 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10049 AARCH64_ARCH_NONE
},
10050 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10051 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10052 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10053 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10054 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10055 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10056 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10057 AARCH64_ARCH_NONE
},
10058 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10059 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10060 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10061 AARCH64_ARCH_NONE
},
10062 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10063 AARCH64_FEATURE (AARCH64_FEATURE_F16
10064 | AARCH64_FEATURE_SIMD
, 0)},
10065 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10066 AARCH64_ARCH_NONE
},
10067 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10068 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10069 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10070 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10071 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10072 AARCH64_ARCH_NONE
},
10073 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10074 AARCH64_ARCH_NONE
},
10075 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10076 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10077 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10078 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10079 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10080 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10081 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10082 AARCH64_ARCH_NONE
},
10083 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10084 AARCH64_ARCH_NONE
},
10085 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10086 AARCH64_ARCH_NONE
},
10087 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10088 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10089 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10090 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10091 | AARCH64_FEATURE_SM4
, 0)},
10092 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10093 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10094 | AARCH64_FEATURE_AES
, 0)},
10095 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10096 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10097 | AARCH64_FEATURE_SHA3
, 0)},
10098 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10099 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10100 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10101 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10102 | AARCH64_FEATURE_BFLOAT16
, 0)},
10103 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10104 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10105 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10106 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10107 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10108 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10109 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10110 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10111 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10112 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10113 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10114 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10115 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10116 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10117 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10118 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10119 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10120 AARCH64_ARCH_NONE
},
10121 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10122 AARCH64_ARCH_NONE
},
10123 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10124 AARCH64_ARCH_NONE
},
10125 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10126 AARCH64_ARCH_NONE
},
10127 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10128 AARCH64_ARCH_NONE
},
10129 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10130 AARCH64_ARCH_NONE
},
10131 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10134 struct aarch64_long_option_table
10136 const char *option
; /* Substring to match. */
10137 const char *help
; /* Help information. */
10138 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10139 char *deprecated
; /* If non-null, print this message. */
10142 /* Transitive closure of features depending on set. */
10143 static aarch64_feature_set
10144 aarch64_feature_disable_set (aarch64_feature_set set
)
10146 const struct aarch64_option_cpu_value_table
*opt
;
10147 aarch64_feature_set prev
= 0;
10149 while (prev
!= set
) {
10151 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10152 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10153 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10158 /* Transitive closure of dependencies of set. */
10159 static aarch64_feature_set
10160 aarch64_feature_enable_set (aarch64_feature_set set
)
10162 const struct aarch64_option_cpu_value_table
*opt
;
10163 aarch64_feature_set prev
= 0;
10165 while (prev
!= set
) {
10167 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10168 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10169 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10175 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10178 /* We insist on extensions being added before being removed. We achieve
10179 this by using the ADDING_VALUE variable to indicate whether we are
10180 adding an extension (1) or removing it (0) and only allowing it to
10181 change in the order -1 -> 1 -> 0. */
10182 int adding_value
= -1;
10183 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10185 /* Copy the feature set, so that we can modify it. */
10186 *ext_set
= **opt_p
;
10189 while (str
!= NULL
&& *str
!= 0)
10191 const struct aarch64_option_cpu_value_table
*opt
;
10192 const char *ext
= NULL
;
10199 as_bad (_("invalid architectural extension"));
10203 ext
= strchr (++str
, '+');
10207 optlen
= ext
- str
;
10209 optlen
= strlen (str
);
10211 if (optlen
>= 2 && startswith (str
, "no"))
10213 if (adding_value
!= 0)
10218 else if (optlen
> 0)
10220 if (adding_value
== -1)
10222 else if (adding_value
!= 1)
10224 as_bad (_("must specify extensions to add before specifying "
10225 "those to remove"));
10232 as_bad (_("missing architectural extension"));
10236 gas_assert (adding_value
!= -1);
10238 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10239 if (strncmp (opt
->name
, str
, optlen
) == 0)
10241 aarch64_feature_set set
;
10243 /* Add or remove the extension. */
10246 set
= aarch64_feature_enable_set (opt
->value
);
10247 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10251 set
= aarch64_feature_disable_set (opt
->value
);
10252 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10257 if (opt
->name
== NULL
)
10259 as_bad (_("unknown architectural extension `%s'"), str
);
10270 aarch64_parse_cpu (const char *str
)
10272 const struct aarch64_cpu_option_table
*opt
;
10273 const char *ext
= strchr (str
, '+');
10277 optlen
= ext
- str
;
10279 optlen
= strlen (str
);
10283 as_bad (_("missing cpu name `%s'"), str
);
10287 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10288 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10290 mcpu_cpu_opt
= &opt
->value
;
10292 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10297 as_bad (_("unknown cpu `%s'"), str
);
10302 aarch64_parse_arch (const char *str
)
10304 const struct aarch64_arch_option_table
*opt
;
10305 const char *ext
= strchr (str
, '+');
10309 optlen
= ext
- str
;
10311 optlen
= strlen (str
);
10315 as_bad (_("missing architecture name `%s'"), str
);
10319 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10320 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10322 march_cpu_opt
= &opt
->value
;
10324 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10329 as_bad (_("unknown architecture `%s'\n"), str
);
10334 struct aarch64_option_abi_value_table
10337 enum aarch64_abi_type value
;
10340 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10342 {"ilp32", AARCH64_ABI_ILP32
},
10343 {"lp64", AARCH64_ABI_LP64
},
10345 {"llp64", AARCH64_ABI_LLP64
},
10350 aarch64_parse_abi (const char *str
)
10354 if (str
[0] == '\0')
10356 as_bad (_("missing abi name `%s'"), str
);
10360 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10361 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10363 aarch64_abi
= aarch64_abis
[i
].value
;
10367 as_bad (_("unknown abi `%s'\n"), str
);
10371 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10372 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10373 aarch64_parse_abi
, NULL
},
10374 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10375 aarch64_parse_cpu
, NULL
},
10376 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10377 aarch64_parse_arch
, NULL
},
10378 {NULL
, NULL
, 0, NULL
}
10382 md_parse_option (int c
, const char *arg
)
10384 struct aarch64_option_table
*opt
;
10385 struct aarch64_long_option_table
*lopt
;
10391 target_big_endian
= 1;
10397 target_big_endian
= 0;
10402 /* Listing option. Just ignore these, we don't support additional
10407 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10409 if (c
== opt
->option
[0]
10410 && ((arg
== NULL
&& opt
->option
[1] == 0)
10411 || streq (arg
, opt
->option
+ 1)))
10413 /* If the option is deprecated, tell the user. */
10414 if (opt
->deprecated
!= NULL
)
10415 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10416 arg
? arg
: "", _(opt
->deprecated
));
10418 if (opt
->var
!= NULL
)
10419 *opt
->var
= opt
->value
;
10425 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10427 /* These options are expected to have an argument. */
10428 if (c
== lopt
->option
[0]
10430 && startswith (arg
, lopt
->option
+ 1))
10432 /* If the option is deprecated, tell the user. */
10433 if (lopt
->deprecated
!= NULL
)
10434 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10435 _(lopt
->deprecated
));
10437 /* Call the sup-option parser. */
10438 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10449 md_show_usage (FILE * fp
)
10451 struct aarch64_option_table
*opt
;
10452 struct aarch64_long_option_table
*lopt
;
10454 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10456 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10457 if (opt
->help
!= NULL
)
10458 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10460 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10461 if (lopt
->help
!= NULL
)
10462 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10466 -EB assemble code for a big-endian cpu\n"));
10471 -EL assemble code for a little-endian cpu\n"));
10475 /* Parse a .cpu directive. */
10478 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10480 const struct aarch64_cpu_option_table
*opt
;
10486 name
= input_line_pointer
;
10487 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10488 saved_char
= *input_line_pointer
;
10489 *input_line_pointer
= 0;
10491 ext
= strchr (name
, '+');
10494 optlen
= ext
- name
;
10496 optlen
= strlen (name
);
10498 /* Skip the first "all" entry. */
10499 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10500 if (strlen (opt
->name
) == optlen
10501 && strncmp (name
, opt
->name
, optlen
) == 0)
10503 mcpu_cpu_opt
= &opt
->value
;
10505 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10508 cpu_variant
= *mcpu_cpu_opt
;
10510 *input_line_pointer
= saved_char
;
10511 demand_empty_rest_of_line ();
10514 as_bad (_("unknown cpu `%s'"), name
);
10515 *input_line_pointer
= saved_char
;
10516 ignore_rest_of_line ();
10520 /* Parse a .arch directive. */
10523 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10525 const struct aarch64_arch_option_table
*opt
;
10531 name
= input_line_pointer
;
10532 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10533 saved_char
= *input_line_pointer
;
10534 *input_line_pointer
= 0;
10536 ext
= strchr (name
, '+');
10539 optlen
= ext
- name
;
10541 optlen
= strlen (name
);
10543 /* Skip the first "all" entry. */
10544 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10545 if (strlen (opt
->name
) == optlen
10546 && strncmp (name
, opt
->name
, optlen
) == 0)
10548 mcpu_cpu_opt
= &opt
->value
;
10550 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10553 cpu_variant
= *mcpu_cpu_opt
;
10555 *input_line_pointer
= saved_char
;
10556 demand_empty_rest_of_line ();
10560 as_bad (_("unknown architecture `%s'\n"), name
);
10561 *input_line_pointer
= saved_char
;
10562 ignore_rest_of_line ();
10565 /* Parse a .arch_extension directive. */
10568 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10571 char *ext
= input_line_pointer
;
10573 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10574 saved_char
= *input_line_pointer
;
10575 *input_line_pointer
= 0;
10577 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10580 cpu_variant
= *mcpu_cpu_opt
;
10582 *input_line_pointer
= saved_char
;
10583 demand_empty_rest_of_line ();
10586 /* Copy symbol information. */
10589 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10591 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10595 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10596 This is needed so AArch64 specific st_other values can be independently
10597 specified for an IFUNC resolver (that is called by the dynamic linker)
10598 and the symbol it resolves (aliased to the resolver). In particular,
10599 if a function symbol has special st_other value set via directives,
10600 then attaching an IFUNC resolver to that symbol should not override
10601 the st_other setting. Requiring the directive on the IFUNC resolver
10602 symbol would be unexpected and problematic in C code, where the two
10603 symbols appear as two independent function declarations. */
10606 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10608 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10609 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10610 /* If size is unset, copy size from src. Because we don't track whether
10611 .size has been used, we can't differentiate .size dest, 0 from the case
10612 where dest's size is unset. */
10613 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10617 destelf
->size
= XNEW (expressionS
);
10618 *destelf
->size
= *srcelf
->size
;
10620 S_SET_SIZE (dest
, S_GET_SIZE (src
));