1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* SME horizontal or vertical slice indicator, encoded in "V".
128 /* Bits for DEFINED field in vector_type_el. */
129 #define NTA_HASTYPE 1
130 #define NTA_HASINDEX 2
131 #define NTA_HASVARWIDTH 4
133 struct vector_type_el
135 enum vector_el_type type
;
136 unsigned char defined
;
137 unsigned element_size
;
142 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
146 bfd_reloc_code_real_type type
;
149 enum aarch64_opnd opnd
;
151 unsigned need_libopcodes_p
: 1;
154 struct aarch64_instruction
156 /* libopcodes structure for instruction intermediate representation. */
158 /* Record assembly errors found during the parsing. */
159 aarch64_operand_error parsing_error
;
160 /* The condition that appears in the assembly line. */
162 /* Relocation information (including the GAS internal fixup). */
164 /* Need to generate an immediate in the literal pool. */
165 unsigned gen_lit_pool
: 1;
168 typedef struct aarch64_instruction aarch64_instruction
;
170 static aarch64_instruction inst
;
172 static bool parse_operands (char *, const aarch64_opcode
*);
173 static bool programmer_friendly_fixup (aarch64_instruction
*);
175 /* Diagnostics inline function utilities.
177 These are lightweight utilities which should only be called by parse_operands
178 and other parsers. GAS processes each assembly line by parsing it against
179 instruction template(s), in the case of multiple templates (for the same
180 mnemonic name), those templates are tried one by one until one succeeds or
181 all fail. An assembly line may fail a few templates before being
182 successfully parsed; an error saved here in most cases is not a user error
183 but an error indicating the current template is not the right template.
184 Therefore it is very important that errors can be saved at a low cost during
185 the parsing; we don't want to slow down the whole parsing by recording
186 non-user errors in detail.
188 Remember that the objective is to help GAS pick up the most appropriate
189 error message in the case of multiple templates, e.g. FMOV which has 8
195 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
196 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
202 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
206 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
208 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
209 inst
.parsing_error
.index
= -1;
210 inst
.parsing_error
.kind
= kind
;
211 inst
.parsing_error
.error
= error
;
215 set_recoverable_error (const char *error
)
217 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
220 /* Use the DESC field of the corresponding aarch64_operand entry to compose
221 the error message. */
223 set_default_error (void)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
229 set_syntax_error (const char *error
)
231 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
235 set_first_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
242 set_fatal_syntax_error (const char *error
)
244 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
247 /* Return value for certain parsers when the parsing fails; those parsers
248 return the information of the parsed result, e.g. register number, on
250 #define PARSE_FAIL -1
252 /* This is an invalid condition code that means no conditional field is
254 #define COND_ALWAYS 0x10
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
288 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
289 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
319 in other contexts. */ \
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* A horizontal or vertical slice of a ZA tile. */ \
331 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
332 /* Pseudo type to mark the end of the enumerator sequence. */ \
335 #undef BASIC_REG_TYPE
336 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
337 #undef MULTI_REG_TYPE
338 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
340 /* Register type enumerators. */
341 typedef enum aarch64_reg_type_
343 /* A list of REG_TYPE_*. */
347 #undef BASIC_REG_TYPE
348 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
350 #define REG_TYPE(T) (1 << REG_TYPE_##T)
351 #undef MULTI_REG_TYPE
352 #define MULTI_REG_TYPE(T,V) V,
354 /* Structure for a hash table entry for a register. */
358 unsigned char number
;
359 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
360 unsigned char builtin
;
363 /* Values indexed by aarch64_reg_type to assist the type checking. */
364 static const unsigned reg_type_masks
[] =
369 #undef BASIC_REG_TYPE
371 #undef MULTI_REG_TYPE
372 #undef AARCH64_REG_TYPES
374 /* Diagnostics used when we don't get a register of the expected type.
375 Note: this has to synchronized with aarch64_reg_type definitions
378 get_reg_expected_msg (aarch64_reg_type reg_type
)
385 msg
= N_("integer 32-bit register expected");
388 msg
= N_("integer 64-bit register expected");
391 msg
= N_("integer register expected");
393 case REG_TYPE_R64_SP
:
394 msg
= N_("64-bit integer or SP register expected");
396 case REG_TYPE_SVE_BASE
:
397 msg
= N_("base register expected");
400 msg
= N_("integer or zero register expected");
402 case REG_TYPE_SVE_OFFSET
:
403 msg
= N_("offset register expected");
406 msg
= N_("integer or SP register expected");
408 case REG_TYPE_R_Z_SP
:
409 msg
= N_("integer, zero or SP register expected");
412 msg
= N_("8-bit SIMD scalar register expected");
415 msg
= N_("16-bit SIMD scalar or floating-point half precision "
416 "register expected");
419 msg
= N_("32-bit SIMD scalar or floating-point single precision "
420 "register expected");
423 msg
= N_("64-bit SIMD scalar or floating-point double precision "
424 "register expected");
427 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
428 "register expected");
430 case REG_TYPE_R_Z_BHSDQ_V
:
431 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
432 msg
= N_("register expected");
434 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
435 msg
= N_("SIMD scalar or floating-point register expected");
437 case REG_TYPE_VN
: /* any V reg */
438 msg
= N_("vector register expected");
441 msg
= N_("SVE vector register expected");
444 msg
= N_("SVE predicate register expected");
447 as_fatal (_("invalid register type %d"), reg_type
);
452 /* Some well known registers that we refer to directly elsewhere. */
456 /* Instructions take 4 bytes in the object file. */
459 static htab_t aarch64_ops_hsh
;
460 static htab_t aarch64_cond_hsh
;
461 static htab_t aarch64_shift_hsh
;
462 static htab_t aarch64_sys_regs_hsh
;
463 static htab_t aarch64_pstatefield_hsh
;
464 static htab_t aarch64_sys_regs_ic_hsh
;
465 static htab_t aarch64_sys_regs_dc_hsh
;
466 static htab_t aarch64_sys_regs_at_hsh
;
467 static htab_t aarch64_sys_regs_tlbi_hsh
;
468 static htab_t aarch64_sys_regs_sr_hsh
;
469 static htab_t aarch64_reg_hsh
;
470 static htab_t aarch64_barrier_opt_hsh
;
471 static htab_t aarch64_nzcv_hsh
;
472 static htab_t aarch64_pldop_hsh
;
473 static htab_t aarch64_hint_opt_hsh
;
475 /* Stuff needed to resolve the label ambiguity
484 static symbolS
*last_label_seen
;
486 /* Literal pool structure. Held on a per-section
487 and per-sub-section basis. */
489 #define MAX_LITERAL_POOL_SIZE 1024
490 typedef struct literal_expression
493 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
494 LITTLENUM_TYPE
* bignum
;
495 } literal_expression
;
497 typedef struct literal_pool
499 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
500 unsigned int next_free_entry
;
506 struct literal_pool
*next
;
509 /* Pointer to a linked list of literal pools. */
510 static literal_pool
*list_of_pools
= NULL
;
514 /* This array holds the chars that always start a comment. If the
515 pre-processor is disabled, these aren't very useful. */
516 const char comment_chars
[] = "";
518 /* This array holds the chars that only start a comment at the beginning of
519 a line. If the line seems to have the form '# 123 filename'
520 .line and .file directives will appear in the pre-processed output. */
521 /* Note that input_file.c hand checks for '#' at the beginning of the
522 first line of the input file. This is because the compiler outputs
523 #NO_APP at the beginning of its output. */
524 /* Also note that comments like this one will always work. */
525 const char line_comment_chars
[] = "#";
527 const char line_separator_chars
[] = ";";
529 /* Chars that can be used to separate mant
530 from exp in floating point numbers. */
531 const char EXP_CHARS
[] = "eE";
533 /* Chars that mean this number is a floating point constant. */
537 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
539 /* Prefix character that indicates the start of an immediate value. */
540 #define is_immediate_prefix(C) ((C) == '#')
542 /* Separator character handling. */
544 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
547 skip_past_char (char **str
, char c
)
558 #define skip_past_comma(str) skip_past_char (str, ',')
560 /* Arithmetic expressions (possibly involving symbols). */
562 static bool in_aarch64_get_expression
= false;
564 /* Third argument to aarch64_get_expression. */
565 #define GE_NO_PREFIX false
566 #define GE_OPT_PREFIX true
568 /* Fourth argument to aarch64_get_expression. */
569 #define ALLOW_ABSENT false
570 #define REJECT_ABSENT true
572 /* Return TRUE if the string pointed by *STR is successfully parsed
573 as an valid expression; *EP will be filled with the information of
574 such an expression. Otherwise return FALSE.
576 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
577 If REJECT_ABSENT is true then trat missing expressions as an error. */
580 aarch64_get_expression (expressionS
* ep
,
582 bool allow_immediate_prefix
,
587 bool prefix_present
= false;
589 if (allow_immediate_prefix
)
591 if (is_immediate_prefix (**str
))
594 prefix_present
= true;
598 memset (ep
, 0, sizeof (expressionS
));
600 save_in
= input_line_pointer
;
601 input_line_pointer
= *str
;
602 in_aarch64_get_expression
= true;
603 seg
= expression (ep
);
604 in_aarch64_get_expression
= false;
606 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
608 /* We found a bad expression in md_operand(). */
609 *str
= input_line_pointer
;
610 input_line_pointer
= save_in
;
611 if (prefix_present
&& ! error_p ())
612 set_fatal_syntax_error (_("bad expression"));
614 set_first_syntax_error (_("bad expression"));
619 if (seg
!= absolute_section
620 && seg
!= text_section
621 && seg
!= data_section
622 && seg
!= bss_section
623 && seg
!= undefined_section
)
625 set_syntax_error (_("bad segment"));
626 *str
= input_line_pointer
;
627 input_line_pointer
= save_in
;
634 *str
= input_line_pointer
;
635 input_line_pointer
= save_in
;
639 /* Turn a string in input_line_pointer into a floating point constant
640 of type TYPE, and store the appropriate bytes in *LITP. The number
641 of LITTLENUMS emitted is stored in *SIZEP. An error message is
642 returned, or NULL on OK. */
645 md_atof (int type
, char *litP
, int *sizeP
)
647 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
650 /* We handle all bad expressions here, so that we can report the faulty
651 instruction in the error message. */
653 md_operand (expressionS
* exp
)
655 if (in_aarch64_get_expression
)
656 exp
->X_op
= O_illegal
;
659 /* Immediate values. */
661 /* Errors may be set multiple times during parsing or bit encoding
662 (particularly in the Neon bits), but usually the earliest error which is set
663 will be the most meaningful. Avoid overwriting it with later (cascading)
664 errors by calling this function. */
667 first_error (const char *error
)
670 set_syntax_error (error
);
673 /* Similar to first_error, but this function accepts formatted error
676 first_error_fmt (const char *format
, ...)
681 /* N.B. this single buffer will not cause error messages for different
682 instructions to pollute each other; this is because at the end of
683 processing of each assembly line, error message if any will be
684 collected by as_bad. */
685 static char buffer
[size
];
689 int ret ATTRIBUTE_UNUSED
;
690 va_start (args
, format
);
691 ret
= vsnprintf (buffer
, size
, format
, args
);
692 know (ret
<= size
- 1 && ret
>= 0);
694 set_syntax_error (buffer
);
698 /* Internal helper routine converting a vector_type_el structure *VECTYPE
699 to a corresponding operand qualifier. */
701 static inline aarch64_opnd_qualifier_t
702 vectype_to_qualifier (const struct vector_type_el
*vectype
)
704 /* Element size in bytes indexed by vector_el_type. */
705 const unsigned char ele_size
[5]
707 const unsigned int ele_base
[5] =
709 AARCH64_OPND_QLF_V_4B
,
710 AARCH64_OPND_QLF_V_2H
,
711 AARCH64_OPND_QLF_V_2S
,
712 AARCH64_OPND_QLF_V_1D
,
713 AARCH64_OPND_QLF_V_1Q
716 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
717 goto vectype_conversion_fail
;
719 if (vectype
->type
== NT_zero
)
720 return AARCH64_OPND_QLF_P_Z
;
721 if (vectype
->type
== NT_merge
)
722 return AARCH64_OPND_QLF_P_M
;
724 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
726 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
728 /* Special case S_4B. */
729 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
730 return AARCH64_OPND_QLF_S_4B
;
732 /* Special case S_2H. */
733 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
734 return AARCH64_OPND_QLF_S_2H
;
736 /* Vector element register. */
737 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
741 /* Vector register. */
742 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
745 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
746 goto vectype_conversion_fail
;
748 /* The conversion is by calculating the offset from the base operand
749 qualifier for the vector type. The operand qualifiers are regular
750 enough that the offset can established by shifting the vector width by
751 a vector-type dependent amount. */
753 if (vectype
->type
== NT_b
)
755 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
757 else if (vectype
->type
>= NT_d
)
762 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
763 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
764 && offset
<= AARCH64_OPND_QLF_V_1Q
);
768 vectype_conversion_fail
:
769 first_error (_("bad vector arrangement type"));
770 return AARCH64_OPND_QLF_NIL
;
773 /* Register parsing. */
775 /* Generic register parser which is called by other specialized
777 CCP points to what should be the beginning of a register name.
778 If it is indeed a valid register name, advance CCP over it and
779 return the reg_entry structure; otherwise return NULL.
780 It does not issue diagnostics. */
783 parse_reg (char **ccp
)
789 #ifdef REGISTER_PREFIX
790 if (*start
!= REGISTER_PREFIX
)
796 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
801 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
803 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
812 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
815 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
817 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
820 /* Try to parse a base or offset register. Allow SVE base and offset
821 registers if REG_TYPE includes SVE registers. Return the register
822 entry on success, setting *QUALIFIER to the register qualifier.
823 Return null otherwise.
825 Note that this function does not issue any diagnostics. */
827 static const reg_entry
*
828 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
829 aarch64_opnd_qualifier_t
*qualifier
)
832 const reg_entry
*reg
= parse_reg (&str
);
842 *qualifier
= AARCH64_OPND_QLF_W
;
848 *qualifier
= AARCH64_OPND_QLF_X
;
852 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
855 switch (TOLOWER (str
[1]))
858 *qualifier
= AARCH64_OPND_QLF_S_S
;
861 *qualifier
= AARCH64_OPND_QLF_S_D
;
878 /* Try to parse a base or offset register. Return the register entry
879 on success, setting *QUALIFIER to the register qualifier. Return null
882 Note that this function does not issue any diagnostics. */
884 static const reg_entry
*
885 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
887 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
890 /* Parse the qualifier of a vector register or vector element of type
891 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
892 succeeds; otherwise return FALSE.
894 Accept only one occurrence of:
895 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
898 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
899 struct vector_type_el
*parsed_type
, char **str
)
903 unsigned element_size
;
904 enum vector_el_type type
;
907 gas_assert (*ptr
== '.');
910 if (reg_type
!= REG_TYPE_VN
|| !ISDIGIT (*ptr
))
915 width
= strtoul (ptr
, &ptr
, 10);
916 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
918 first_error_fmt (_("bad size %d in vector width specifier"), width
);
923 switch (TOLOWER (*ptr
))
942 if (reg_type
!= REG_TYPE_VN
|| width
== 1)
951 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
953 first_error (_("missing element size"));
956 if (width
!= 0 && width
* element_size
!= 64
957 && width
* element_size
!= 128
958 && !(width
== 2 && element_size
== 16)
959 && !(width
== 4 && element_size
== 8))
962 ("invalid element size %d and vector size combination %c"),
968 parsed_type
->type
= type
;
969 parsed_type
->width
= width
;
970 parsed_type
->element_size
= element_size
;
977 /* *STR contains an SVE zero/merge predication suffix. Parse it into
978 *PARSED_TYPE and point *STR at the end of the suffix. */
981 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
986 gas_assert (*ptr
== '/');
988 switch (TOLOWER (*ptr
))
991 parsed_type
->type
= NT_zero
;
994 parsed_type
->type
= NT_merge
;
997 if (*ptr
!= '\0' && *ptr
!= ',')
998 first_error_fmt (_("unexpected character `%c' in predication type"),
1001 first_error (_("missing predication type"));
1004 parsed_type
->width
= 0;
1009 /* Return true if CH is a valid suffix character for registers of
1013 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1025 return ch
== '.' || ch
== '/';
1032 /* Parse a register of the type TYPE.
1034 Return null if the string pointed to by *CCP is not a valid register
1035 name or the parsed register is not of TYPE.
1037 Otherwise return the register, and optionally return the register
1038 shape and element index information in *TYPEINFO.
1040 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1042 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1045 #define PTR_IN_REGLIST (1U << 0)
1046 #define PTR_FULL_REG (1U << 1)
1048 static const reg_entry
*
1049 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1050 struct vector_type_el
*typeinfo
, unsigned int flags
)
1053 const reg_entry
*reg
= parse_reg (&str
);
1054 struct vector_type_el atype
;
1055 struct vector_type_el parsetype
;
1056 bool is_typed_vecreg
= false;
1059 atype
.type
= NT_invtype
;
1061 atype
.element_size
= 0;
1068 set_default_error ();
1072 if (! aarch64_check_reg_type (reg
, type
))
1074 DEBUG_TRACE ("reg type check failed");
1075 set_default_error ();
1080 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1084 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1086 if ((reg
->type
== REG_TYPE_ZAT
1087 || reg
->type
== REG_TYPE_ZATH
1088 || reg
->type
== REG_TYPE_ZATV
)
1089 && reg
->number
* 8 >= parsetype
.element_size
)
1091 set_syntax_error (_("ZA tile number out of range"));
1097 if (!parse_predication_for_operand (&parsetype
, &str
))
1101 /* Register if of the form Vn.[bhsdq]. */
1102 is_typed_vecreg
= true;
1104 if (type
!= REG_TYPE_VN
)
1106 /* The width is always variable; we don't allow an integer width
1108 gas_assert (parsetype
.width
== 0);
1109 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1111 else if (parsetype
.width
== 0)
1112 /* Expect index. In the new scheme we cannot have
1113 Vn.[bhsdq] represent a scalar. Therefore any
1114 Vn.[bhsdq] should have an index following it.
1115 Except in reglists of course. */
1116 atype
.defined
|= NTA_HASINDEX
;
1118 atype
.defined
|= NTA_HASTYPE
;
1120 atype
.type
= parsetype
.type
;
1121 atype
.width
= parsetype
.width
;
1124 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1128 /* Reject Sn[index] syntax. */
1129 if (!is_typed_vecreg
)
1131 first_error (_("this type of register can't be indexed"));
1135 if (flags
& PTR_IN_REGLIST
)
1137 first_error (_("index not allowed inside register list"));
1141 atype
.defined
|= NTA_HASINDEX
;
1143 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1145 if (exp
.X_op
!= O_constant
)
1147 first_error (_("constant expression required"));
1151 if (! skip_past_char (&str
, ']'))
1154 atype
.index
= exp
.X_add_number
;
1156 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1158 /* Indexed vector register expected. */
1159 first_error (_("indexed vector register expected"));
1163 /* A vector reg Vn should be typed or indexed. */
1164 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1166 first_error (_("invalid use of vector register"));
1179 Return the register on success; return null otherwise.
1181 If this is a NEON vector register with additional type information, fill
1182 in the struct pointed to by VECTYPE (if non-NULL).
1184 This parser does not handle register lists. */
1186 static const reg_entry
*
1187 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1188 struct vector_type_el
*vectype
)
1190 return parse_typed_reg (ccp
, type
, vectype
, 0);
1194 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1196 return (e1
.type
== e2
.type
1197 && e1
.defined
== e2
.defined
1198 && e1
.width
== e2
.width
1199 && e1
.element_size
== e2
.element_size
1200 && e1
.index
== e2
.index
);
1203 /* This function parses a list of vector registers of type TYPE.
1204 On success, it returns the parsed register list information in the
1205 following encoded format:
1207 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1208 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1210 The information of the register shape and/or index is returned in
1213 It returns PARSE_FAIL if the register list is invalid.
1215 The list contains one to four registers.
1216 Each register can be one of:
1219 All <T> should be identical.
1220 All <index> should be identical.
1221 There are restrictions on <Vt> numbers which are checked later
1222 (by reg_list_valid_p). */
1225 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1226 struct vector_type_el
*vectype
)
1230 struct vector_type_el typeinfo
, typeinfo_first
;
1236 bool expect_index
= false;
1240 set_syntax_error (_("expecting {"));
1246 typeinfo_first
.defined
= 0;
1247 typeinfo_first
.type
= NT_invtype
;
1248 typeinfo_first
.width
= -1;
1249 typeinfo_first
.element_size
= 0;
1250 typeinfo_first
.index
= 0;
1259 str
++; /* skip over '-' */
1262 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1266 set_first_syntax_error (_("invalid vector register in list"));
1271 /* reject [bhsd]n */
1272 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1274 set_first_syntax_error (_("invalid scalar register in list"));
1279 if (typeinfo
.defined
& NTA_HASINDEX
)
1280 expect_index
= true;
1284 if (val
< val_range
)
1286 set_first_syntax_error
1287 (_("invalid range in vector register list"));
1296 typeinfo_first
= typeinfo
;
1297 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1299 set_first_syntax_error
1300 (_("type mismatch in vector register list"));
1305 for (i
= val_range
; i
<= val
; i
++)
1307 ret_val
|= i
<< (5 * nb_regs
);
1312 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1314 skip_whitespace (str
);
1317 set_first_syntax_error (_("end of vector register list not found"));
1322 skip_whitespace (str
);
1326 if (skip_past_char (&str
, '['))
1330 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1331 if (exp
.X_op
!= O_constant
)
1333 set_first_syntax_error (_("constant expression required."));
1336 if (! skip_past_char (&str
, ']'))
1339 typeinfo_first
.index
= exp
.X_add_number
;
1343 set_first_syntax_error (_("expected index"));
1350 set_first_syntax_error (_("too many registers in vector register list"));
1353 else if (nb_regs
== 0)
1355 set_first_syntax_error (_("empty vector register list"));
1361 *vectype
= typeinfo_first
;
1363 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1366 /* Directives: register aliases. */
1369 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1374 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1377 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1380 /* Only warn about a redefinition if it's not defined as the
1382 else if (new->number
!= number
|| new->type
!= type
)
1383 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1388 name
= xstrdup (str
);
1389 new = XNEW (reg_entry
);
1392 new->number
= number
;
1394 new->builtin
= false;
1396 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1401 /* Look for the .req directive. This is of the form:
1403 new_register_name .req existing_register_name
1405 If we find one, or if it looks sufficiently like one that we want to
1406 handle any error here, return TRUE. Otherwise return FALSE. */
1409 create_register_alias (char *newname
, char *p
)
1411 const reg_entry
*old
;
1412 char *oldname
, *nbuf
;
1415 /* The input scrubber ensures that whitespace after the mnemonic is
1416 collapsed to single spaces. */
1418 if (!startswith (oldname
, " .req "))
1422 if (*oldname
== '\0')
1425 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1428 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1432 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1433 the desired alias name, and p points to its end. If not, then
1434 the desired alias name is in the global original_case_string. */
1435 #ifdef TC_CASE_SENSITIVE
1438 newname
= original_case_string
;
1439 nlen
= strlen (newname
);
1442 nbuf
= xmemdup0 (newname
, nlen
);
1444 /* Create aliases under the new name as stated; an all-lowercase
1445 version of the new name; and an all-uppercase version of the new
1447 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1449 for (p
= nbuf
; *p
; p
++)
1452 if (strncmp (nbuf
, newname
, nlen
))
1454 /* If this attempt to create an additional alias fails, do not bother
1455 trying to create the all-lower case alias. We will fail and issue
1456 a second, duplicate error message. This situation arises when the
1457 programmer does something like:
1460 The second .req creates the "Foo" alias but then fails to create
1461 the artificial FOO alias because it has already been created by the
1463 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1470 for (p
= nbuf
; *p
; p
++)
1473 if (strncmp (nbuf
, newname
, nlen
))
1474 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1481 /* Should never be called, as .req goes between the alias and the
1482 register name, not at the beginning of the line. */
1484 s_req (int a ATTRIBUTE_UNUSED
)
1486 as_bad (_("invalid syntax for .req directive"));
1489 /* The .unreq directive deletes an alias which was previously defined
1490 by .req. For example:
1496 s_unreq (int a ATTRIBUTE_UNUSED
)
1501 name
= input_line_pointer
;
1502 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1503 saved_char
= *input_line_pointer
;
1504 *input_line_pointer
= 0;
1507 as_bad (_("invalid syntax for .unreq directive"));
1510 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1513 as_bad (_("unknown register alias '%s'"), name
);
1514 else if (reg
->builtin
)
1515 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1522 str_hash_delete (aarch64_reg_hsh
, name
);
1523 free ((char *) reg
->name
);
1526 /* Also locate the all upper case and all lower case versions.
1527 Do not complain if we cannot find one or the other as it
1528 was probably deleted above. */
1530 nbuf
= strdup (name
);
1531 for (p
= nbuf
; *p
; p
++)
1533 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1536 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1537 free ((char *) reg
->name
);
1541 for (p
= nbuf
; *p
; p
++)
1543 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1546 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1547 free ((char *) reg
->name
);
1555 *input_line_pointer
= saved_char
;
1556 demand_empty_rest_of_line ();
1559 /* Directives: Instruction set selection. */
1561 #if defined OBJ_ELF || defined OBJ_COFF
1562 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1563 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1564 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1565 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1567 /* Create a new mapping symbol for the transition to STATE. */
1570 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1573 const char *symname
;
1580 type
= BSF_NO_FLAGS
;
1584 type
= BSF_NO_FLAGS
;
1590 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1591 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1593 /* Save the mapping symbols for future reference. Also check that
1594 we do not place two mapping symbols at the same offset within a
1595 frag. We'll handle overlap between frags in
1596 check_mapping_symbols.
1598 If .fill or other data filling directive generates zero sized data,
1599 the mapping symbol for the following code will have the same value
1600 as the one generated for the data filling directive. In this case,
1601 we replace the old symbol with the new one at the same address. */
1604 if (frag
->tc_frag_data
.first_map
!= NULL
)
1606 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1607 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1610 frag
->tc_frag_data
.first_map
= symbolP
;
1612 if (frag
->tc_frag_data
.last_map
!= NULL
)
1614 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1615 S_GET_VALUE (symbolP
));
1616 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1617 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1620 frag
->tc_frag_data
.last_map
= symbolP
;
1623 /* We must sometimes convert a region marked as code to data during
1624 code alignment, if an odd number of bytes have to be padded. The
1625 code mapping symbol is pushed to an aligned address. */
1628 insert_data_mapping_symbol (enum mstate state
,
1629 valueT value
, fragS
* frag
, offsetT bytes
)
1631 /* If there was already a mapping symbol, remove it. */
1632 if (frag
->tc_frag_data
.last_map
!= NULL
1633 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1634 frag
->fr_address
+ value
)
1636 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1640 know (frag
->tc_frag_data
.first_map
== symp
);
1641 frag
->tc_frag_data
.first_map
= NULL
;
1643 frag
->tc_frag_data
.last_map
= NULL
;
1644 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1647 make_mapping_symbol (MAP_DATA
, value
, frag
);
1648 make_mapping_symbol (state
, value
+ bytes
, frag
);
1651 static void mapping_state_2 (enum mstate state
, int max_chars
);
1653 /* Set the mapping state to STATE. Only call this when about to
1654 emit some STATE bytes to the file. */
1657 mapping_state (enum mstate state
)
1659 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1661 if (state
== MAP_INSN
)
1662 /* AArch64 instructions require 4-byte alignment. When emitting
1663 instructions into any section, record the appropriate section
1665 record_alignment (now_seg
, 2);
1667 if (mapstate
== state
)
1668 /* The mapping symbol has already been emitted.
1669 There is nothing else to do. */
1672 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1673 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1674 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1675 evaluated later in the next else. */
1677 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1679 /* Only add the symbol if the offset is > 0:
1680 if we're at the first frag, check it's size > 0;
1681 if we're not at the first frag, then for sure
1682 the offset is > 0. */
1683 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1684 const int add_symbol
= (frag_now
!= frag_first
)
1685 || (frag_now_fix () > 0);
1688 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1692 mapping_state_2 (state
, 0);
1695 /* Same as mapping_state, but MAX_CHARS bytes have already been
1696 allocated. Put the mapping symbol that far back. */
1699 mapping_state_2 (enum mstate state
, int max_chars
)
1701 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1703 if (!SEG_NORMAL (now_seg
))
1706 if (mapstate
== state
)
1707 /* The mapping symbol has already been emitted.
1708 There is nothing else to do. */
1711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1715 #define mapping_state(x) /* nothing */
1716 #define mapping_state_2(x, y) /* nothing */
1719 /* Directives: sectioning and alignment. */
1722 s_bss (int ignore ATTRIBUTE_UNUSED
)
1724 /* We don't support putting frags in the BSS segment, we fake it by
1725 marking in_bss, then looking at s_skip for clues. */
1726 subseg_set (bss_section
, 0);
1727 demand_empty_rest_of_line ();
1728 mapping_state (MAP_DATA
);
1732 s_even (int ignore ATTRIBUTE_UNUSED
)
1734 /* Never make frag if expect extra pass. */
1736 frag_align (1, 0, 0);
1738 record_alignment (now_seg
, 1);
1740 demand_empty_rest_of_line ();
1743 /* Directives: Literal pools. */
1745 static literal_pool
*
1746 find_literal_pool (int size
)
1750 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1752 if (pool
->section
== now_seg
1753 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1760 static literal_pool
*
1761 find_or_make_literal_pool (int size
)
1763 /* Next literal pool ID number. */
1764 static unsigned int latest_pool_num
= 1;
1767 pool
= find_literal_pool (size
);
1771 /* Create a new pool. */
1772 pool
= XNEW (literal_pool
);
1776 /* Currently we always put the literal pool in the current text
1777 section. If we were generating "small" model code where we
1778 knew that all code and initialised data was within 1MB then
1779 we could output literals to mergeable, read-only data
1782 pool
->next_free_entry
= 0;
1783 pool
->section
= now_seg
;
1784 pool
->sub_section
= now_subseg
;
1786 pool
->next
= list_of_pools
;
1787 pool
->symbol
= NULL
;
1789 /* Add it to the list. */
1790 list_of_pools
= pool
;
1793 /* New pools, and emptied pools, will have a NULL symbol. */
1794 if (pool
->symbol
== NULL
)
1796 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1797 &zero_address_frag
, 0);
1798 pool
->id
= latest_pool_num
++;
1805 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1806 Return TRUE on success, otherwise return FALSE. */
1808 add_to_lit_pool (expressionS
*exp
, int size
)
1813 pool
= find_or_make_literal_pool (size
);
1815 /* Check if this literal value is already in the pool. */
1816 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1818 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1820 if ((litexp
->X_op
== exp
->X_op
)
1821 && (exp
->X_op
== O_constant
)
1822 && (litexp
->X_add_number
== exp
->X_add_number
)
1823 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1826 if ((litexp
->X_op
== exp
->X_op
)
1827 && (exp
->X_op
== O_symbol
)
1828 && (litexp
->X_add_number
== exp
->X_add_number
)
1829 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1830 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1834 /* Do we need to create a new entry? */
1835 if (entry
== pool
->next_free_entry
)
1837 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1839 set_syntax_error (_("literal pool overflow"));
1843 pool
->literals
[entry
].exp
= *exp
;
1844 pool
->next_free_entry
+= 1;
1845 if (exp
->X_op
== O_big
)
1847 /* PR 16688: Bignums are held in a single global array. We must
1848 copy and preserve that value now, before it is overwritten. */
1849 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1851 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1852 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1855 pool
->literals
[entry
].bignum
= NULL
;
1858 exp
->X_op
= O_symbol
;
1859 exp
->X_add_number
= ((int) entry
) * size
;
1860 exp
->X_add_symbol
= pool
->symbol
;
1865 /* Can't use symbol_new here, so have to create a symbol and then at
1866 a later date assign it a value. That's what these functions do. */
1869 symbol_locate (symbolS
* symbolP
,
1870 const char *name
,/* It is copied, the caller can modify. */
1871 segT segment
, /* Segment identifier (SEG_<something>). */
1872 valueT valu
, /* Symbol value. */
1873 fragS
* frag
) /* Associated fragment. */
1876 char *preserved_copy_of_name
;
1878 name_length
= strlen (name
) + 1; /* +1 for \0. */
1879 obstack_grow (¬es
, name
, name_length
);
1880 preserved_copy_of_name
= obstack_finish (¬es
);
1882 #ifdef tc_canonicalize_symbol_name
1883 preserved_copy_of_name
=
1884 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1887 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1889 S_SET_SEGMENT (symbolP
, segment
);
1890 S_SET_VALUE (symbolP
, valu
);
1891 symbol_clear_list_pointers (symbolP
);
1893 symbol_set_frag (symbolP
, frag
);
1895 /* Link to end of symbol chain. */
1897 extern int symbol_table_frozen
;
1899 if (symbol_table_frozen
)
1903 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1905 obj_symbol_new_hook (symbolP
);
1907 #ifdef tc_symbol_new_hook
1908 tc_symbol_new_hook (symbolP
);
1912 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1913 #endif /* DEBUG_SYMS */
1918 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1925 for (align
= 2; align
<= 4; align
++)
1927 int size
= 1 << align
;
1929 pool
= find_literal_pool (size
);
1930 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1933 /* Align pool as you have word accesses.
1934 Only make a frag if we have to. */
1936 frag_align (align
, 0, 0);
1938 mapping_state (MAP_DATA
);
1940 record_alignment (now_seg
, align
);
1942 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1944 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1945 (valueT
) frag_now_fix (), frag_now
);
1946 symbol_table_insert (pool
->symbol
);
1948 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1950 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1952 if (exp
->X_op
== O_big
)
1954 /* PR 16688: Restore the global bignum value. */
1955 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1956 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1957 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1960 /* First output the expression in the instruction to the pool. */
1961 emit_expr (exp
, size
); /* .word|.xword */
1963 if (exp
->X_op
== O_big
)
1965 free (pool
->literals
[entry
].bignum
);
1966 pool
->literals
[entry
].bignum
= NULL
;
1970 /* Mark the pool as empty. */
1971 pool
->next_free_entry
= 0;
1972 pool
->symbol
= NULL
;
1976 #if defined(OBJ_ELF) || defined(OBJ_COFF)
1977 /* Forward declarations for functions below, in the MD interface
1979 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1981 /* Directives: Data. */
1982 /* N.B. the support for relocation suffix in this directive needs to be
1983 implemented properly. */
1986 s_aarch64_cons (int nbytes
)
1990 #ifdef md_flush_pending_output
1991 md_flush_pending_output ();
1994 if (is_it_end_of_statement ())
1996 demand_empty_rest_of_line ();
2000 #ifdef md_cons_align
2001 md_cons_align (nbytes
);
2004 mapping_state (MAP_DATA
);
2007 struct reloc_table_entry
*reloc
;
2011 if (exp
.X_op
!= O_symbol
)
2012 emit_expr (&exp
, (unsigned int) nbytes
);
2015 skip_past_char (&input_line_pointer
, '#');
2016 if (skip_past_char (&input_line_pointer
, ':'))
2018 reloc
= find_reloc_table_entry (&input_line_pointer
);
2020 as_bad (_("unrecognized relocation suffix"));
2022 as_bad (_("unimplemented relocation suffix"));
2023 ignore_rest_of_line ();
2027 emit_expr (&exp
, (unsigned int) nbytes
);
2030 while (*input_line_pointer
++ == ',');
2032 /* Put terminator back into stream. */
2033 input_line_pointer
--;
2034 demand_empty_rest_of_line ();
2039 /* Forward declarations for functions below, in the MD interface
2041 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2043 /* Mark symbol that it follows a variant PCS convention. */
2046 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2052 elf_symbol_type
*elfsym
;
2054 c
= get_symbol_name (&name
);
2056 as_bad (_("Missing symbol name in directive"));
2057 sym
= symbol_find_or_make (name
);
2058 restore_line_pointer (c
);
2059 demand_empty_rest_of_line ();
2060 bfdsym
= symbol_get_bfdsym (sym
);
2061 elfsym
= elf_symbol_from (bfdsym
);
2062 gas_assert (elfsym
);
2063 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2065 #endif /* OBJ_ELF */
2067 /* Output a 32-bit word, but mark as an instruction. */
2070 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2075 #ifdef md_flush_pending_output
2076 md_flush_pending_output ();
2079 if (is_it_end_of_statement ())
2081 demand_empty_rest_of_line ();
2085 /* Sections are assumed to start aligned. In executable section, there is no
2086 MAP_DATA symbol pending. So we only align the address during
2087 MAP_DATA --> MAP_INSN transition.
2088 For other sections, this is not guaranteed. */
2089 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2090 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2091 frag_align_code (2, 0);
2094 mapping_state (MAP_INSN
);
2100 if (exp
.X_op
!= O_constant
)
2102 as_bad (_("constant expression required"));
2103 ignore_rest_of_line ();
2107 if (target_big_endian
)
2109 unsigned int val
= exp
.X_add_number
;
2110 exp
.X_add_number
= SWAP_32 (val
);
2112 emit_expr (&exp
, INSN_SIZE
);
2115 while (*input_line_pointer
++ == ',');
2117 dwarf2_emit_insn (n
* INSN_SIZE
);
2119 /* Put terminator back into stream. */
2120 input_line_pointer
--;
2121 demand_empty_rest_of_line ();
2125 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2127 demand_empty_rest_of_line ();
2128 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2129 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2133 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2136 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2142 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2143 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2145 demand_empty_rest_of_line ();
2148 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2151 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2155 /* Since we're just labelling the code, there's no need to define a
2158 /* Make sure there is enough room in this frag for the following
2159 blr. This trick only works if the blr follows immediately after
2160 the .tlsdesc directive. */
2162 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2163 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2165 demand_empty_rest_of_line ();
2168 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2171 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2177 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2178 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2180 demand_empty_rest_of_line ();
2182 #endif /* OBJ_ELF */
2186 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2193 if (exp
.X_op
== O_symbol
)
2194 exp
.X_op
= O_secrel
;
2196 emit_expr (&exp
, 4);
2198 while (*input_line_pointer
++ == ',');
2200 input_line_pointer
--;
2201 demand_empty_rest_of_line ();
2205 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2209 exp
.X_op
= O_secrel
;
2210 exp
.X_add_symbol
= symbol
;
2211 exp
.X_add_number
= 0;
2212 emit_expr (&exp
, size
);
2216 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2223 if (exp
.X_op
== O_symbol
)
2224 exp
.X_op
= O_secidx
;
2226 emit_expr (&exp
, 2);
2228 while (*input_line_pointer
++ == ',');
2230 input_line_pointer
--;
2231 demand_empty_rest_of_line ();
2235 static void s_aarch64_arch (int);
2236 static void s_aarch64_cpu (int);
2237 static void s_aarch64_arch_extension (int);
2239 /* This table describes all the machine specific pseudo-ops the assembler
2240 has to support. The fields are:
2241 pseudo-op name without dot
2242 function to call to execute this pseudo-op
2243 Integer arg to pass to the function. */
2245 const pseudo_typeS md_pseudo_table
[] = {
2246 /* Never called because '.req' does not start a line. */
2248 {"unreq", s_unreq
, 0},
2250 {"even", s_even
, 0},
2251 {"ltorg", s_ltorg
, 0},
2252 {"pool", s_ltorg
, 0},
2253 {"cpu", s_aarch64_cpu
, 0},
2254 {"arch", s_aarch64_arch
, 0},
2255 {"arch_extension", s_aarch64_arch_extension
, 0},
2256 {"inst", s_aarch64_inst
, 0},
2257 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2259 {"tlsdescadd", s_tlsdescadd
, 0},
2260 {"tlsdesccall", s_tlsdesccall
, 0},
2261 {"tlsdescldr", s_tlsdescldr
, 0},
2262 {"variant_pcs", s_variant_pcs
, 0},
2264 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2265 {"word", s_aarch64_cons
, 4},
2266 {"long", s_aarch64_cons
, 4},
2267 {"xword", s_aarch64_cons
, 8},
2268 {"dword", s_aarch64_cons
, 8},
2271 {"secrel32", s_secrel
, 0},
2272 {"secidx", s_secidx
, 0},
2274 {"float16", float_cons
, 'h'},
2275 {"bfloat16", float_cons
, 'b'},
2280 /* Check whether STR points to a register name followed by a comma or the
2281 end of line; REG_TYPE indicates which register types are checked
2282 against. Return TRUE if STR is such a register name; otherwise return
2283 FALSE. The function does not intend to produce any diagnostics, but since
2284 the register parser aarch64_reg_parse, which is called by this function,
2285 does produce diagnostics, we call clear_error to clear any diagnostics
2286 that may be generated by aarch64_reg_parse.
2287 Also, the function returns FALSE directly if there is any user error
2288 present at the function entry. This prevents the existing diagnostics
2289 state from being spoiled.
2290 The function currently serves parse_constant_immediate and
2291 parse_big_immediate only. */
2293 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2295 const reg_entry
*reg
;
2297 /* Prevent the diagnostics state from being spoiled. */
2301 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2303 /* Clear the parsing error that may be set by the reg parser. */
2309 skip_whitespace (str
);
2310 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2316 /* Parser functions used exclusively in instruction operands. */
2318 /* Parse an immediate expression which may not be constant.
2320 To prevent the expression parser from pushing a register name
2321 into the symbol table as an undefined symbol, firstly a check is
2322 done to find out whether STR is a register of type REG_TYPE followed
2323 by a comma or the end of line. Return FALSE if STR is such a string. */
2326 parse_immediate_expression (char **str
, expressionS
*exp
,
2327 aarch64_reg_type reg_type
)
2329 if (reg_name_p (*str
, reg_type
))
2331 set_recoverable_error (_("immediate operand required"));
2335 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2337 if (exp
->X_op
== O_absent
)
2339 set_fatal_syntax_error (_("missing immediate expression"));
2346 /* Constant immediate-value read function for use in insn parsing.
2347 STR points to the beginning of the immediate (with the optional
2348 leading #); *VAL receives the value. REG_TYPE says which register
2349 names should be treated as registers rather than as symbolic immediates.
2351 Return TRUE on success; otherwise return FALSE. */
2354 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2358 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2361 if (exp
.X_op
!= O_constant
)
2363 set_syntax_error (_("constant expression required"));
2367 *val
= exp
.X_add_number
;
2372 encode_imm_float_bits (uint32_t imm
)
2374 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2375 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2378 /* Return TRUE if the single-precision floating-point value encoded in IMM
2379 can be expressed in the AArch64 8-bit signed floating-point format with
2380 3-bit exponent and normalized 4 bits of precision; in other words, the
2381 floating-point value must be expressable as
2382 (+/-) n / 16 * power (2, r)
2383 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2386 aarch64_imm_float_p (uint32_t imm
)
2388 /* If a single-precision floating-point value has the following bit
2389 pattern, it can be expressed in the AArch64 8-bit floating-point
2392 3 32222222 2221111111111
2393 1 09876543 21098765432109876543210
2394 n Eeeeeexx xxxx0000000000000000000
2396 where n, e and each x are either 0 or 1 independently, with
2401 /* Prepare the pattern for 'Eeeeee'. */
2402 if (((imm
>> 30) & 0x1) == 0)
2403 pattern
= 0x3e000000;
2405 pattern
= 0x40000000;
2407 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2408 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2411 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2412 as an IEEE float without any loss of precision. Store the value in
2416 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2418 /* If a double-precision floating-point value has the following bit
2419 pattern, it can be expressed in a float:
2421 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2422 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2423 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2425 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2426 if Eeee_eeee != 1111_1111
2428 where n, e, s and S are either 0 or 1 independently and where ~ is the
2432 uint32_t high32
= imm
>> 32;
2433 uint32_t low32
= imm
;
2435 /* Lower 29 bits need to be 0s. */
2436 if ((imm
& 0x1fffffff) != 0)
2439 /* Prepare the pattern for 'Eeeeeeeee'. */
2440 if (((high32
>> 30) & 0x1) == 0)
2441 pattern
= 0x38000000;
2443 pattern
= 0x40000000;
2446 if ((high32
& 0x78000000) != pattern
)
2449 /* Check Eeee_eeee != 1111_1111. */
2450 if ((high32
& 0x7ff00000) == 0x47f00000)
2453 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2454 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2455 | (low32
>> 29)); /* 3 S bits. */
2459 /* Return true if we should treat OPERAND as a double-precision
2460 floating-point operand rather than a single-precision one. */
2462 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2464 /* Check for unsuffixed SVE registers, which are allowed
2465 for LDR and STR but not in instructions that require an
2466 immediate. We get better error messages if we arbitrarily
2467 pick one size, parse the immediate normally, and then
2468 report the match failure in the normal way. */
2469 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2470 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2473 /* Parse a floating-point immediate. Return TRUE on success and return the
2474 value in *IMMED in the format of IEEE754 single-precision encoding.
2475 *CCP points to the start of the string; DP_P is TRUE when the immediate
2476 is expected to be in double-precision (N.B. this only matters when
2477 hexadecimal representation is involved). REG_TYPE says which register
2478 names should be treated as registers rather than as symbolic immediates.
2480 This routine accepts any IEEE float; it is up to the callers to reject
2484 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2485 aarch64_reg_type reg_type
)
2489 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2491 unsigned fpword
= 0;
2494 skip_past_char (&str
, '#');
2497 skip_whitespace (fpnum
);
2499 if (startswith (fpnum
, "0x"))
2501 /* Support the hexadecimal representation of the IEEE754 encoding.
2502 Double-precision is expected when DP_P is TRUE, otherwise the
2503 representation should be in single-precision. */
2504 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2509 if (!can_convert_double_to_float (val
, &fpword
))
2512 else if ((uint64_t) val
> 0xffffffff)
2519 else if (reg_name_p (str
, reg_type
))
2521 set_recoverable_error (_("immediate operand required"));
2529 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2532 /* Our FP word must be 32 bits (single-precision FP). */
2533 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2535 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2545 set_fatal_syntax_error (_("invalid floating-point constant"));
2549 /* Less-generic immediate-value read function with the possibility of loading
2550 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2553 To prevent the expression parser from pushing a register name into the
2554 symbol table as an undefined symbol, a check is firstly done to find
2555 out whether STR is a register of type REG_TYPE followed by a comma or
2556 the end of line. Return FALSE if STR is such a register. */
2559 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2563 if (reg_name_p (ptr
, reg_type
))
2565 set_syntax_error (_("immediate operand required"));
2569 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2571 if (inst
.reloc
.exp
.X_op
== O_constant
)
2572 *imm
= inst
.reloc
.exp
.X_add_number
;
2579 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2580 if NEED_LIBOPCODES is non-zero, the fixup will need
2581 assistance from the libopcodes. */
2584 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2585 const aarch64_opnd_info
*operand
,
2586 int need_libopcodes_p
)
2588 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2589 reloc
->opnd
= operand
->type
;
2590 if (need_libopcodes_p
)
2591 reloc
->need_libopcodes_p
= 1;
2594 /* Return TRUE if the instruction needs to be fixed up later internally by
2595 the GAS; otherwise return FALSE. */
2598 aarch64_gas_internal_fixup_p (void)
2600 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2603 /* Assign the immediate value to the relevant field in *OPERAND if
2604 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2605 needs an internal fixup in a later stage.
2606 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2607 IMM.VALUE that may get assigned with the constant. */
2609 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2610 aarch64_opnd_info
*operand
,
2612 int need_libopcodes_p
,
2615 if (reloc
->exp
.X_op
== O_constant
)
2618 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2620 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2621 reloc
->type
= BFD_RELOC_UNUSED
;
2625 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2626 /* Tell libopcodes to ignore this operand or not. This is helpful
2627 when one of the operands needs to be fixed up later but we need
2628 libopcodes to check the other operands. */
2629 operand
->skip
= skip_p
;
2633 /* Relocation modifiers. Each entry in the table contains the textual
2634 name for the relocation which may be placed before a symbol used as
2635 a load/store offset, or add immediate. It must be surrounded by a
2636 leading and trailing colon, for example:
2638 ldr x0, [x1, #:rello:varsym]
2639 add x0, x1, #:rello:varsym */
2641 struct reloc_table_entry
2645 bfd_reloc_code_real_type adr_type
;
2646 bfd_reloc_code_real_type adrp_type
;
2647 bfd_reloc_code_real_type movw_type
;
2648 bfd_reloc_code_real_type add_type
;
2649 bfd_reloc_code_real_type ldst_type
;
2650 bfd_reloc_code_real_type ld_literal_type
;
2653 static struct reloc_table_entry reloc_table
[] =
2655 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2660 BFD_RELOC_AARCH64_ADD_LO12
,
2661 BFD_RELOC_AARCH64_LDST_LO12
,
2664 /* Higher 21 bits of pc-relative page offset: ADRP */
2667 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2673 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2676 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2682 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2686 BFD_RELOC_AARCH64_MOVW_G0
,
2691 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2695 BFD_RELOC_AARCH64_MOVW_G0_S
,
2700 /* Less significant bits 0-15 of address/value: MOVK, no check */
2704 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2709 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2713 BFD_RELOC_AARCH64_MOVW_G1
,
2718 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2722 BFD_RELOC_AARCH64_MOVW_G1_S
,
2727 /* Less significant bits 16-31 of address/value: MOVK, no check */
2731 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2736 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2740 BFD_RELOC_AARCH64_MOVW_G2
,
2745 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2749 BFD_RELOC_AARCH64_MOVW_G2_S
,
2754 /* Less significant bits 32-47 of address/value: MOVK, no check */
2758 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2763 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2767 BFD_RELOC_AARCH64_MOVW_G3
,
2772 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2776 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2781 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2785 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2790 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2794 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2799 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2803 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2808 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2812 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2817 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2821 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2826 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2830 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2835 /* Get to the page containing GOT entry for a symbol. */
2838 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2842 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2844 /* 12 bit offset into the page containing GOT entry for that symbol. */
2850 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2853 /* 0-15 bits of address/value: MOVk, no check. */
2857 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2862 /* Most significant bits 16-31 of address/value: MOVZ. */
2866 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2871 /* 15 bit offset into the page containing GOT entry for that symbol. */
2877 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2880 /* Get to the page containing GOT TLS entry for a symbol */
2881 {"gottprel_g0_nc", 0,
2884 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2889 /* Get to the page containing GOT TLS entry for a symbol */
2893 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2898 /* Get to the page containing GOT TLS entry for a symbol */
2900 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2901 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2907 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2912 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2916 /* Lower 16 bits address/value: MOVk. */
2920 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2925 /* Most significant bits 16-31 of address/value: MOVZ. */
2929 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2934 /* Get to the page containing GOT TLS entry for a symbol */
2936 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2937 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2941 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2943 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2948 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2949 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2952 /* Get to the page containing GOT TLS entry for a symbol.
2953 The same as GD, we allocate two consecutive GOT slots
2954 for module index and module offset, the only difference
2955 with GD is the module offset should be initialized to
2956 zero without any outstanding runtime relocation. */
2958 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2959 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2965 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2966 {"tlsldm_lo12_nc", 0,
2970 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2974 /* 12 bit offset into the module TLS base address. */
2979 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2980 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2983 /* Same as dtprel_lo12, no overflow check. */
2984 {"dtprel_lo12_nc", 0,
2988 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2989 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2992 /* bits[23:12] of offset to the module TLS base address. */
2997 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3001 /* bits[15:0] of offset to the module TLS base address. */
3005 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3010 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3014 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3019 /* bits[31:16] of offset to the module TLS base address. */
3023 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3028 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3032 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3037 /* bits[47:32] of offset to the module TLS base address. */
3041 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3046 /* Lower 16 bit offset into GOT entry for a symbol */
3047 {"tlsdesc_off_g0_nc", 0,
3050 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3055 /* Higher 16 bit offset into GOT entry for a symbol */
3056 {"tlsdesc_off_g1", 0,
3059 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3064 /* Get to the page containing GOT TLS entry for a symbol */
3067 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3071 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3073 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3074 {"gottprel_lo12", 0,
3079 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3082 /* Get tp offset for a symbol. */
3087 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3091 /* Get tp offset for a symbol. */
3096 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3097 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3100 /* Get tp offset for a symbol. */
3105 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3109 /* Get tp offset for a symbol. */
3110 {"tprel_lo12_nc", 0,
3114 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3115 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3118 /* Most significant bits 32-47 of address/value: MOVZ. */
3122 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3127 /* Most significant bits 16-31 of address/value: MOVZ. */
3131 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3136 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3140 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3145 /* Most significant bits 0-15 of address/value: MOVZ. */
3149 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3154 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3158 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3163 /* 15bit offset from got entry to base address of GOT table. */
3169 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3172 /* 14bit offset from got entry to base address of GOT table. */
3178 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3182 /* Given the address of a pointer pointing to the textual name of a
3183 relocation as may appear in assembler source, attempt to find its
3184 details in reloc_table. The pointer will be updated to the character
3185 after the trailing colon. On failure, NULL will be returned;
3186 otherwise return the reloc_table_entry. */
3188 static struct reloc_table_entry
*
3189 find_reloc_table_entry (char **str
)
3192 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3194 int length
= strlen (reloc_table
[i
].name
);
3196 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3197 && (*str
)[length
] == ':')
3199 *str
+= (length
+ 1);
3200 return &reloc_table
[i
];
3207 /* Returns 0 if the relocation should never be forced,
3208 1 if the relocation must be forced, and -1 if either
3212 aarch64_force_reloc (unsigned int type
)
3216 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3217 /* Perform these "immediate" internal relocations
3218 even if the symbol is extern or weak. */
3221 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3222 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3223 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3224 /* Pseudo relocs that need to be fixed up according to
3228 case BFD_RELOC_AARCH64_ADD_LO12
:
3229 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3230 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3231 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3232 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3233 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3234 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3235 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3236 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3237 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3238 case BFD_RELOC_AARCH64_LDST128_LO12
:
3239 case BFD_RELOC_AARCH64_LDST16_LO12
:
3240 case BFD_RELOC_AARCH64_LDST32_LO12
:
3241 case BFD_RELOC_AARCH64_LDST64_LO12
:
3242 case BFD_RELOC_AARCH64_LDST8_LO12
:
3243 case BFD_RELOC_AARCH64_LDST_LO12
:
3244 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3245 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3246 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3247 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3248 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3249 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3250 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3251 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3252 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3253 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3254 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3255 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3256 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3257 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3258 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3259 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3260 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3261 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3262 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3263 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3264 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3265 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3266 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3267 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3268 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3269 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3270 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3271 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3272 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3273 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3274 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3275 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3276 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3277 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3278 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3279 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3280 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3281 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3282 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3283 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3284 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3285 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3286 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3287 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3288 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3289 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3290 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3291 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3292 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3293 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3294 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3295 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3296 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3297 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3298 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3299 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3300 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3301 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3302 /* Always leave these relocations for the linker. */
3311 aarch64_force_relocation (struct fix
*fixp
)
3313 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3316 return generic_force_reloc (fixp
);
3320 /* Mode argument to parse_shift and parser_shifter_operand. */
3321 enum parse_shift_mode
3323 SHIFTED_NONE
, /* no shifter allowed */
3324 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3326 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3328 SHIFTED_LSL
, /* bare "lsl #n" */
3329 SHIFTED_MUL
, /* bare "mul #n" */
3330 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3331 SHIFTED_MUL_VL
, /* "mul vl" */
3332 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3335 /* Parse a <shift> operator on an AArch64 data processing instruction.
3336 Return TRUE on success; otherwise return FALSE. */
3338 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3340 const struct aarch64_name_value_pair
*shift_op
;
3341 enum aarch64_modifier_kind kind
;
3347 for (p
= *str
; ISALPHA (*p
); p
++)
3352 set_syntax_error (_("shift expression expected"));
3356 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3358 if (shift_op
== NULL
)
3360 set_syntax_error (_("shift operator expected"));
3364 kind
= aarch64_get_operand_modifier (shift_op
);
3366 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3368 set_syntax_error (_("invalid use of 'MSL'"));
3372 if (kind
== AARCH64_MOD_MUL
3373 && mode
!= SHIFTED_MUL
3374 && mode
!= SHIFTED_MUL_VL
)
3376 set_syntax_error (_("invalid use of 'MUL'"));
3382 case SHIFTED_LOGIC_IMM
:
3383 if (aarch64_extend_operator_p (kind
))
3385 set_syntax_error (_("extending shift is not permitted"));
3390 case SHIFTED_ARITH_IMM
:
3391 if (kind
== AARCH64_MOD_ROR
)
3393 set_syntax_error (_("'ROR' shift is not permitted"));
3399 if (kind
!= AARCH64_MOD_LSL
)
3401 set_syntax_error (_("only 'LSL' shift is permitted"));
3407 if (kind
!= AARCH64_MOD_MUL
)
3409 set_syntax_error (_("only 'MUL' is permitted"));
3414 case SHIFTED_MUL_VL
:
3415 /* "MUL VL" consists of two separate tokens. Require the first
3416 token to be "MUL" and look for a following "VL". */
3417 if (kind
== AARCH64_MOD_MUL
)
3419 skip_whitespace (p
);
3420 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3423 kind
= AARCH64_MOD_MUL_VL
;
3427 set_syntax_error (_("only 'MUL VL' is permitted"));
3430 case SHIFTED_REG_OFFSET
:
3431 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3432 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3434 set_fatal_syntax_error
3435 (_("invalid shift for the register offset addressing mode"));
3440 case SHIFTED_LSL_MSL
:
3441 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3443 set_syntax_error (_("invalid shift operator"));
3452 /* Whitespace can appear here if the next thing is a bare digit. */
3453 skip_whitespace (p
);
3455 /* Parse shift amount. */
3457 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3458 exp
.X_op
= O_absent
;
3461 if (is_immediate_prefix (*p
))
3466 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3468 if (kind
== AARCH64_MOD_MUL_VL
)
3469 /* For consistency, give MUL VL the same shift amount as an implicit
3471 operand
->shifter
.amount
= 1;
3472 else if (exp
.X_op
== O_absent
)
3474 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3476 set_syntax_error (_("missing shift amount"));
3479 operand
->shifter
.amount
= 0;
3481 else if (exp
.X_op
!= O_constant
)
3483 set_syntax_error (_("constant shift amount required"));
3486 /* For parsing purposes, MUL #n has no inherent range. The range
3487 depends on the operand and will be checked by operand-specific
3489 else if (kind
!= AARCH64_MOD_MUL
3490 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3492 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3497 operand
->shifter
.amount
= exp
.X_add_number
;
3498 operand
->shifter
.amount_present
= 1;
3501 operand
->shifter
.operator_present
= 1;
3502 operand
->shifter
.kind
= kind
;
3508 /* Parse a <shifter_operand> for a data processing instruction:
3511 #<immediate>, LSL #imm
3513 Validation of immediate operands is deferred to md_apply_fix.
3515 Return TRUE on success; otherwise return FALSE. */
3518 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3519 enum parse_shift_mode mode
)
3523 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3528 /* Accept an immediate expression. */
3529 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3533 /* Accept optional LSL for arithmetic immediate values. */
3534 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3535 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3538 /* Not accept any shifter for logical immediate values. */
3539 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3540 && parse_shift (&p
, operand
, mode
))
3542 set_syntax_error (_("unexpected shift operator"));
3550 /* Parse a <shifter_operand> for a data processing instruction:
3555 #<immediate>, LSL #imm
3557 where <shift> is handled by parse_shift above, and the last two
3558 cases are handled by the function above.
3560 Validation of immediate operands is deferred to md_apply_fix.
3562 Return TRUE on success; otherwise return FALSE. */
3565 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3566 enum parse_shift_mode mode
)
3568 const reg_entry
*reg
;
3569 aarch64_opnd_qualifier_t qualifier
;
3570 enum aarch64_operand_class opd_class
3571 = aarch64_get_operand_class (operand
->type
);
3573 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3576 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3578 set_syntax_error (_("unexpected register in the immediate operand"));
3582 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3584 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3588 operand
->reg
.regno
= reg
->number
;
3589 operand
->qualifier
= qualifier
;
3591 /* Accept optional shift operation on register. */
3592 if (! skip_past_comma (str
))
3595 if (! parse_shift (str
, operand
, mode
))
3600 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3603 (_("integer register expected in the extended/shifted operand "
3608 /* We have a shifted immediate variable. */
3609 return parse_shifter_operand_imm (str
, operand
, mode
);
3612 /* Return TRUE on success; return FALSE otherwise. */
3615 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3616 enum parse_shift_mode mode
)
3620 /* Determine if we have the sequence of characters #: or just :
3621 coming next. If we do, then we check for a :rello: relocation
3622 modifier. If we don't, punt the whole lot to
3623 parse_shifter_operand. */
3625 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3627 struct reloc_table_entry
*entry
;
3635 /* Try to parse a relocation. Anything else is an error. */
3636 if (!(entry
= find_reloc_table_entry (str
)))
3638 set_syntax_error (_("unknown relocation modifier"));
3642 if (entry
->add_type
== 0)
3645 (_("this relocation modifier is not allowed on this instruction"));
3649 /* Save str before we decompose it. */
3652 /* Next, we parse the expression. */
3653 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3657 /* Record the relocation type (use the ADD variant here). */
3658 inst
.reloc
.type
= entry
->add_type
;
3659 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3661 /* If str is empty, we've reached the end, stop here. */
3665 /* Otherwise, we have a shifted reloc modifier, so rewind to
3666 recover the variable name and continue parsing for the shifter. */
3668 return parse_shifter_operand_imm (str
, operand
, mode
);
3671 return parse_shifter_operand (str
, operand
, mode
);
3674 /* Parse all forms of an address expression. Information is written
3675 to *OPERAND and/or inst.reloc.
3677 The A64 instruction set has the following addressing modes:
3680 [base] // in SIMD ld/st structure
3681 [base{,#0}] // in ld/st exclusive
3683 [base,Xm{,LSL #imm}]
3684 [base,Xm,SXTX {#imm}]
3685 [base,Wm,(S|U)XTW {#imm}]
3687 [base]! // in ldraa/ldrab exclusive
3691 [base],Xm // in SIMD ld/st structure
3692 PC-relative (literal)
3696 [base,Zm.D{,LSL #imm}]
3697 [base,Zm.S,(S|U)XTW {#imm}]
3698 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3702 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3703 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3704 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3706 (As a convenience, the notation "=immediate" is permitted in conjunction
3707 with the pc-relative literal load instructions to automatically place an
3708 immediate value or symbolic address in a nearby literal pool and generate
3709 a hidden label which references it.)
3711 Upon a successful parsing, the address structure in *OPERAND will be
3712 filled in the following way:
3714 .base_regno = <base>
3715 .offset.is_reg // 1 if the offset is a register
3717 .offset.regno = <Rm>
3719 For different addressing modes defined in the A64 ISA:
3722 .pcrel=0; .preind=1; .postind=0; .writeback=0
3724 .pcrel=0; .preind=1; .postind=0; .writeback=1
3726 .pcrel=0; .preind=0; .postind=1; .writeback=1
3727 PC-relative (literal)
3728 .pcrel=1; .preind=1; .postind=0; .writeback=0
3730 The shift/extension information, if any, will be stored in .shifter.
3731 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3732 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3733 corresponding register.
3735 BASE_TYPE says which types of base register should be accepted and
3736 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3737 is the type of shifter that is allowed for immediate offsets,
3738 or SHIFTED_NONE if none.
3740 In all other respects, it is the caller's responsibility to check
3741 for addressing modes not supported by the instruction, and to set
3745 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3746 aarch64_opnd_qualifier_t
*base_qualifier
,
3747 aarch64_opnd_qualifier_t
*offset_qualifier
,
3748 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3749 enum parse_shift_mode imm_shift_mode
)
3752 const reg_entry
*reg
;
3753 expressionS
*exp
= &inst
.reloc
.exp
;
3755 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3756 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3757 if (! skip_past_char (&p
, '['))
3759 /* =immediate or label. */
3760 operand
->addr
.pcrel
= 1;
3761 operand
->addr
.preind
= 1;
3763 /* #:<reloc_op>:<symbol> */
3764 skip_past_char (&p
, '#');
3765 if (skip_past_char (&p
, ':'))
3767 bfd_reloc_code_real_type ty
;
3768 struct reloc_table_entry
*entry
;
3770 /* Try to parse a relocation modifier. Anything else is
3772 entry
= find_reloc_table_entry (&p
);
3775 set_syntax_error (_("unknown relocation modifier"));
3779 switch (operand
->type
)
3781 case AARCH64_OPND_ADDR_PCREL21
:
3783 ty
= entry
->adr_type
;
3787 ty
= entry
->ld_literal_type
;
3794 (_("this relocation modifier is not allowed on this "
3800 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3802 set_syntax_error (_("invalid relocation expression"));
3805 /* #:<reloc_op>:<expr> */
3806 /* Record the relocation type. */
3807 inst
.reloc
.type
= ty
;
3808 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3812 if (skip_past_char (&p
, '='))
3813 /* =immediate; need to generate the literal in the literal pool. */
3814 inst
.gen_lit_pool
= 1;
3816 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3818 set_syntax_error (_("invalid address"));
3829 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3830 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3832 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3835 operand
->addr
.base_regno
= reg
->number
;
3838 if (skip_past_comma (&p
))
3841 operand
->addr
.preind
= 1;
3843 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3846 if (!aarch64_check_reg_type (reg
, offset_type
))
3848 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3853 operand
->addr
.offset
.regno
= reg
->number
;
3854 operand
->addr
.offset
.is_reg
= 1;
3855 /* Shifted index. */
3856 if (skip_past_comma (&p
))
3859 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3860 /* Use the diagnostics set in parse_shift, so not set new
3861 error message here. */
3865 [base,Xm] # For vector plus scalar SVE2 indexing.
3866 [base,Xm{,LSL #imm}]
3867 [base,Xm,SXTX {#imm}]
3868 [base,Wm,(S|U)XTW {#imm}] */
3869 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3870 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3871 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3873 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3875 set_syntax_error (_("invalid use of 32-bit register offset"));
3878 if (aarch64_get_qualifier_esize (*base_qualifier
)
3879 != aarch64_get_qualifier_esize (*offset_qualifier
)
3880 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3881 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3882 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3884 set_syntax_error (_("offset has different size from base"));
3888 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3890 set_syntax_error (_("invalid use of 64-bit register offset"));
3896 /* [Xn,#:<reloc_op>:<symbol> */
3897 skip_past_char (&p
, '#');
3898 if (skip_past_char (&p
, ':'))
3900 struct reloc_table_entry
*entry
;
3902 /* Try to parse a relocation modifier. Anything else is
3904 if (!(entry
= find_reloc_table_entry (&p
)))
3906 set_syntax_error (_("unknown relocation modifier"));
3910 if (entry
->ldst_type
== 0)
3913 (_("this relocation modifier is not allowed on this "
3918 /* [Xn,#:<reloc_op>: */
3919 /* We now have the group relocation table entry corresponding to
3920 the name in the assembler source. Next, we parse the
3922 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3924 set_syntax_error (_("invalid relocation expression"));
3928 /* [Xn,#:<reloc_op>:<expr> */
3929 /* Record the load/store relocation type. */
3930 inst
.reloc
.type
= entry
->ldst_type
;
3931 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3935 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3937 set_syntax_error (_("invalid expression in the address"));
3941 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3942 /* [Xn,<expr>,<shifter> */
3943 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3949 if (! skip_past_char (&p
, ']'))
3951 set_syntax_error (_("']' expected"));
3955 if (skip_past_char (&p
, '!'))
3957 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3959 set_syntax_error (_("register offset not allowed in pre-indexed "
3960 "addressing mode"));
3964 operand
->addr
.writeback
= 1;
3966 else if (skip_past_comma (&p
))
3969 operand
->addr
.postind
= 1;
3970 operand
->addr
.writeback
= 1;
3972 if (operand
->addr
.preind
)
3974 set_syntax_error (_("cannot combine pre- and post-indexing"));
3978 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3982 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3984 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3988 operand
->addr
.offset
.regno
= reg
->number
;
3989 operand
->addr
.offset
.is_reg
= 1;
3991 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3994 set_syntax_error (_("invalid expression in the address"));
3999 /* If at this point neither .preind nor .postind is set, we have a
4000 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4001 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4002 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4004 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4006 if (operand
->addr
.writeback
)
4008 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4010 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4011 operand
->addr
.offset
.is_reg
= 0;
4012 operand
->addr
.offset
.imm
= 0;
4013 operand
->addr
.preind
= 1;
4018 set_syntax_error (_("missing offset in the pre-indexed address"));
4024 operand
->addr
.preind
= 1;
4025 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4027 operand
->addr
.offset
.is_reg
= 1;
4028 operand
->addr
.offset
.regno
= REG_ZR
;
4029 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4033 inst
.reloc
.exp
.X_op
= O_constant
;
4034 inst
.reloc
.exp
.X_add_number
= 0;
4043 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4046 parse_address (char **str
, aarch64_opnd_info
*operand
)
4048 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4049 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4050 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4053 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4054 The arguments have the same meaning as for parse_address_main.
4055 Return TRUE on success. */
4057 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4058 aarch64_opnd_qualifier_t
*base_qualifier
,
4059 aarch64_opnd_qualifier_t
*offset_qualifier
)
4061 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4062 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4066 /* Parse a register X0-X30. The register must be 64-bit and register 31
4069 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4071 const reg_entry
*reg
= parse_reg (str
);
4072 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4074 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
4077 operand
->reg
.regno
= reg
->number
;
4078 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4082 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4083 Return TRUE on success; otherwise return FALSE. */
4085 parse_half (char **str
, int *internal_fixup_p
)
4089 skip_past_char (&p
, '#');
4091 gas_assert (internal_fixup_p
);
4092 *internal_fixup_p
= 0;
4096 struct reloc_table_entry
*entry
;
4098 /* Try to parse a relocation. Anything else is an error. */
4101 if (!(entry
= find_reloc_table_entry (&p
)))
4103 set_syntax_error (_("unknown relocation modifier"));
4107 if (entry
->movw_type
== 0)
4110 (_("this relocation modifier is not allowed on this instruction"));
4114 inst
.reloc
.type
= entry
->movw_type
;
4117 *internal_fixup_p
= 1;
4119 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4126 /* Parse an operand for an ADRP instruction:
4128 Return TRUE on success; otherwise return FALSE. */
4131 parse_adrp (char **str
)
4138 struct reloc_table_entry
*entry
;
4140 /* Try to parse a relocation. Anything else is an error. */
4142 if (!(entry
= find_reloc_table_entry (&p
)))
4144 set_syntax_error (_("unknown relocation modifier"));
4148 if (entry
->adrp_type
== 0)
4151 (_("this relocation modifier is not allowed on this instruction"));
4155 inst
.reloc
.type
= entry
->adrp_type
;
4158 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4160 inst
.reloc
.pc_rel
= 1;
4161 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4167 /* Miscellaneous. */
4169 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4170 of SIZE tokens in which index I gives the token for field value I,
4171 or is null if field value I is invalid. REG_TYPE says which register
4172 names should be treated as registers rather than as symbolic immediates.
4174 Return true on success, moving *STR past the operand and storing the
4175 field value in *VAL. */
4178 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4179 size_t size
, aarch64_reg_type reg_type
)
4185 /* Match C-like tokens. */
4187 while (ISALNUM (*q
))
4190 for (i
= 0; i
< size
; ++i
)
4192 && strncasecmp (array
[i
], p
, q
- p
) == 0
4193 && array
[i
][q
- p
] == 0)
4200 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4203 if (exp
.X_op
== O_constant
4204 && (uint64_t) exp
.X_add_number
< size
)
4206 *val
= exp
.X_add_number
;
4211 /* Use the default error for this operand. */
4215 /* Parse an option for a preload instruction. Returns the encoding for the
4216 option, or PARSE_FAIL. */
4219 parse_pldop (char **str
)
4222 const struct aarch64_name_value_pair
*o
;
4225 while (ISALNUM (*q
))
4228 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4236 /* Parse an option for a barrier instruction. Returns the encoding for the
4237 option, or PARSE_FAIL. */
4240 parse_barrier (char **str
)
4243 const struct aarch64_name_value_pair
*o
;
4246 while (ISALPHA (*q
))
4249 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4257 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4258 return 0 if successful. Otherwise return PARSE_FAIL. */
4261 parse_barrier_psb (char **str
,
4262 const struct aarch64_name_value_pair
** hint_opt
)
4265 const struct aarch64_name_value_pair
*o
;
4268 while (ISALPHA (*q
))
4271 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4274 set_fatal_syntax_error
4275 ( _("unknown or missing option to PSB/TSB"));
4279 if (o
->value
!= 0x11)
4281 /* PSB only accepts option name 'CSYNC'. */
4283 (_("the specified option is not accepted for PSB/TSB"));
4292 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4293 return 0 if successful. Otherwise return PARSE_FAIL. */
4296 parse_bti_operand (char **str
,
4297 const struct aarch64_name_value_pair
** hint_opt
)
4300 const struct aarch64_name_value_pair
*o
;
4303 while (ISALPHA (*q
))
4306 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4309 set_fatal_syntax_error
4310 ( _("unknown option to BTI"));
4316 /* Valid BTI operands. */
4324 (_("unknown option to BTI"));
4333 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4334 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4339 Side effect: Update STR with current parse position of success.
4342 static const reg_entry
*
4343 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4344 aarch64_opnd_qualifier_t
*qualifier
)
4346 struct vector_type_el vectype
;
4347 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4352 *qualifier
= vectype_to_qualifier (&vectype
);
4353 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4359 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4364 Function return TRUE if immediate was found, or FALSE.
4367 parse_sme_immediate (char **str
, int64_t *imm
)
4370 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4377 /* Parse index with vector select register and immediate:
4381 where <Wv> is in W12-W15 range and # is optional for immediate.
4383 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4386 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4390 parse_sme_za_hv_tiles_operand_index (char **str
,
4391 int *vector_select_register
,
4394 const reg_entry
*reg
;
4396 if (!skip_past_char (str
, '['))
4398 set_syntax_error (_("expected '['"));
4402 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4403 reg
= parse_reg (str
);
4404 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4405 || reg
->number
< 12 || reg
->number
> 15)
4407 set_syntax_error (_("expected vector select register W12-W15"));
4410 *vector_select_register
= reg
->number
;
4412 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4414 set_syntax_error (_("expected ','"));
4418 if (!parse_sme_immediate (str
, imm
))
4420 set_syntax_error (_("index offset immediate expected"));
4424 if (!skip_past_char (str
, ']'))
4426 set_syntax_error (_("expected ']'"));
4433 /* Parse SME ZA horizontal or vertical vector access to tiles.
4434 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4435 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4436 contains <Wv> select register and corresponding optional IMMEDIATE.
4437 In addition QUALIFIER is extracted.
4439 Field format examples:
4441 ZA0<HV>.B[<Wv>, #<imm>]
4442 <ZAn><HV>.H[<Wv>, #<imm>]
4443 <ZAn><HV>.S[<Wv>, #<imm>]
4444 <ZAn><HV>.D[<Wv>, #<imm>]
4445 <ZAn><HV>.Q[<Wv>, #<imm>]
4447 Function returns <ZAda> register number or PARSE_FAIL.
4450 parse_sme_za_hv_tiles_operand (char **str
,
4451 enum sme_hv_slice
*slice_indicator
,
4452 int *vector_select_register
,
4454 aarch64_opnd_qualifier_t
*qualifier
)
4459 const reg_entry
*reg
;
4461 reg
= parse_reg_with_qual (str
, REG_TYPE_ZATHV
, qualifier
);
4465 *slice_indicator
= (aarch64_check_reg_type (reg
, REG_TYPE_ZATH
)
4468 regno
= reg
->number
;
4472 case AARCH64_OPND_QLF_S_B
:
4475 case AARCH64_OPND_QLF_S_H
:
4478 case AARCH64_OPND_QLF_S_S
:
4481 case AARCH64_OPND_QLF_S_D
:
4484 case AARCH64_OPND_QLF_S_Q
:
4488 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4492 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4496 /* Check if optional index offset is in the range for instruction
4498 if (imm_value
< 0 || imm_value
> imm_limit
)
4500 set_syntax_error (_("index offset out of range"));
4511 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4512 enum sme_hv_slice
*slice_indicator
,
4513 int *vector_select_register
,
4515 aarch64_opnd_qualifier_t
*qualifier
)
4519 if (!skip_past_char (str
, '{'))
4521 set_syntax_error (_("expected '{'"));
4525 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4526 vector_select_register
, imm
,
4529 if (regno
== PARSE_FAIL
)
4532 if (!skip_past_char (str
, '}'))
4534 set_syntax_error (_("expected '}'"));
4541 /* Parse list of up to eight 64-bit element tile names separated by commas in
4542 SME's ZERO instruction:
4546 Function returns <mask>:
4548 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4551 parse_sme_zero_mask(char **str
)
4555 aarch64_opnd_qualifier_t qualifier
;
4561 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZAT
,
4565 int regno
= reg
->number
;
4566 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4568 /* { ZA0.B } is assembled as all-ones immediate. */
4571 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4572 mask
|= 0x55 << regno
;
4573 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4574 mask
|= 0x11 << regno
;
4575 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4576 mask
|= 0x01 << regno
;
4579 set_syntax_error (_("wrong ZA tile element format"));
4585 if (strncasecmp (q
, "za", 2) == 0 && !ISALNUM (q
[2]))
4587 /* { ZA } is assembled as all-ones immediate. */
4593 set_syntax_error (_("wrong ZA tile element format"));
4596 while (skip_past_char (&q
, ','));
4602 /* Wraps in curly braces <mask> operand ZERO instruction:
4606 Function returns value of <mask> bit-field.
4609 parse_sme_list_of_64bit_tiles (char **str
)
4613 if (!skip_past_char (str
, '{'))
4615 set_syntax_error (_("expected '{'"));
4619 /* Empty <mask> list is an all-zeros immediate. */
4620 if (!skip_past_char (str
, '}'))
4622 regno
= parse_sme_zero_mask (str
);
4623 if (regno
== PARSE_FAIL
)
4626 if (!skip_past_char (str
, '}'))
4628 set_syntax_error (_("expected '}'"));
4638 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4644 Function returns <Wv> or PARSE_FAIL.
4647 parse_sme_za_array (char **str
, int *imm
)
4654 while (ISALPHA (*q
))
4657 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4659 set_syntax_error (_("expected ZA array"));
4663 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4666 if (imm_value
< 0 || imm_value
> 15)
4668 set_syntax_error (_("offset out of range"));
4677 /* Parse streaming mode operand for SMSTART and SMSTOP.
4681 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4684 parse_sme_sm_za (char **str
)
4689 while (ISALPHA (*q
))
4693 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4695 set_syntax_error (_("expected SM or ZA operand"));
4700 return TOLOWER (p
[0]);
4703 /* Parse the name of the source scalable predicate register, the index base
4704 register W12-W15 and the element index. Function performs element index
4705 limit checks as well as qualifier type checks.
4707 <Pn>.<T>[<Wv>, <imm>]
4708 <Pn>.<T>[<Wv>, #<imm>]
4710 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4712 Function returns <Pn>, or PARSE_FAIL.
4715 parse_sme_pred_reg_with_index(char **str
,
4716 int *index_base_reg
,
4718 aarch64_opnd_qualifier_t
*qualifier
)
4723 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4727 regno
= reg
->number
;
4731 case AARCH64_OPND_QLF_S_B
:
4734 case AARCH64_OPND_QLF_S_H
:
4737 case AARCH64_OPND_QLF_S_S
:
4740 case AARCH64_OPND_QLF_S_D
:
4744 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4748 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4751 if (imm_value
< 0 || imm_value
> imm_limit
)
4753 set_syntax_error (_("element index out of range for given variant"));
4762 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4763 Returns the encoding for the option, or PARSE_FAIL.
4765 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4766 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4768 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4769 field, otherwise as a system register.
4773 parse_sys_reg (char **str
, htab_t sys_regs
,
4774 int imple_defined_p
, int pstatefield_p
,
4778 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4779 const aarch64_sys_reg
*o
;
4783 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4784 if (p
< buf
+ (sizeof (buf
) - 1))
4785 *p
++ = TOLOWER (*q
);
4788 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4789 valid system register. This is enforced by construction of the hash
4791 if (p
- buf
!= q
- *str
)
4794 o
= str_hash_find (sys_regs
, buf
);
4797 if (!imple_defined_p
)
4801 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4802 unsigned int op0
, op1
, cn
, cm
, op2
;
4804 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4807 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4809 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4816 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4817 as_bad (_("selected processor does not support PSTATE field "
4820 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4821 o
->value
, o
->flags
, o
->features
))
4822 as_bad (_("selected processor does not support system register "
4824 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4825 as_warn (_("system register name '%s' is deprecated and may be "
4826 "removed in a future release"), buf
);
4836 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4837 for the option, or NULL. */
4839 static const aarch64_sys_ins_reg
*
4840 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4843 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4844 const aarch64_sys_ins_reg
*o
;
4847 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4848 if (p
< buf
+ (sizeof (buf
) - 1))
4849 *p
++ = TOLOWER (*q
);
4852 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4853 valid system register. This is enforced by construction of the hash
4855 if (p
- buf
!= q
- *str
)
4858 o
= str_hash_find (sys_ins_regs
, buf
);
4862 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4863 o
->name
, o
->value
, o
->flags
, 0))
4864 as_bad (_("selected processor does not support system register "
4866 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4867 as_warn (_("system register name '%s' is deprecated and may be "
4868 "removed in a future release"), buf
);
4874 #define po_char_or_fail(chr) do { \
4875 if (! skip_past_char (&str, chr)) \
4879 #define po_reg_or_fail(regtype) do { \
4880 reg = aarch64_reg_parse (&str, regtype, NULL); \
4883 set_default_error (); \
4888 #define po_int_reg_or_fail(reg_type) do { \
4889 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4890 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4892 set_default_error (); \
4895 info->reg.regno = reg->number; \
4896 info->qualifier = qualifier; \
4899 #define po_imm_nc_or_fail() do { \
4900 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4904 #define po_imm_or_fail(min, max) do { \
4905 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4907 if (val < min || val > max) \
4909 set_fatal_syntax_error (_("immediate value out of range "\
4910 #min " to "#max)); \
4915 #define po_enum_or_fail(array) do { \
4916 if (!parse_enum_string (&str, &val, array, \
4917 ARRAY_SIZE (array), imm_reg_type)) \
4921 #define po_misc_or_fail(expr) do { \
4926 /* encode the 12-bit imm field of Add/sub immediate */
4927 static inline uint32_t
4928 encode_addsub_imm (uint32_t imm
)
4933 /* encode the shift amount field of Add/sub immediate */
4934 static inline uint32_t
4935 encode_addsub_imm_shift_amount (uint32_t cnt
)
4941 /* encode the imm field of Adr instruction */
4942 static inline uint32_t
4943 encode_adr_imm (uint32_t imm
)
4945 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4946 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4949 /* encode the immediate field of Move wide immediate */
4950 static inline uint32_t
4951 encode_movw_imm (uint32_t imm
)
4956 /* encode the 26-bit offset of unconditional branch */
4957 static inline uint32_t
4958 encode_branch_ofs_26 (uint32_t ofs
)
4960 return ofs
& ((1 << 26) - 1);
4963 /* encode the 19-bit offset of conditional branch and compare & branch */
4964 static inline uint32_t
4965 encode_cond_branch_ofs_19 (uint32_t ofs
)
4967 return (ofs
& ((1 << 19) - 1)) << 5;
4970 /* encode the 19-bit offset of ld literal */
4971 static inline uint32_t
4972 encode_ld_lit_ofs_19 (uint32_t ofs
)
4974 return (ofs
& ((1 << 19) - 1)) << 5;
4977 /* Encode the 14-bit offset of test & branch. */
4978 static inline uint32_t
4979 encode_tst_branch_ofs_14 (uint32_t ofs
)
4981 return (ofs
& ((1 << 14) - 1)) << 5;
4984 /* Encode the 16-bit imm field of svc/hvc/smc. */
4985 static inline uint32_t
4986 encode_svc_imm (uint32_t imm
)
4991 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4992 static inline uint32_t
4993 reencode_addsub_switch_add_sub (uint32_t opcode
)
4995 return opcode
^ (1 << 30);
4998 static inline uint32_t
4999 reencode_movzn_to_movz (uint32_t opcode
)
5001 return opcode
| (1 << 30);
5004 static inline uint32_t
5005 reencode_movzn_to_movn (uint32_t opcode
)
5007 return opcode
& ~(1 << 30);
5010 /* Overall per-instruction processing. */
5012 /* We need to be able to fix up arbitrary expressions in some statements.
5013 This is so that we can handle symbols that are an arbitrary distance from
5014 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5015 which returns part of an address in a form which will be valid for
5016 a data instruction. We do this by pushing the expression into a symbol
5017 in the expr_section, and creating a fix for that. */
5020 fix_new_aarch64 (fragS
* frag
,
5035 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5039 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5046 /* Diagnostics on operands errors. */
5048 /* By default, output verbose error message.
5049 Disable the verbose error message by -mno-verbose-error. */
5050 static int verbose_error_p
= 1;
5052 #ifdef DEBUG_AARCH64
5053 /* N.B. this is only for the purpose of debugging. */
5054 const char* operand_mismatch_kind_names
[] =
5057 "AARCH64_OPDE_RECOVERABLE",
5058 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5059 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5060 "AARCH64_OPDE_SYNTAX_ERROR",
5061 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5062 "AARCH64_OPDE_INVALID_VARIANT",
5063 "AARCH64_OPDE_OUT_OF_RANGE",
5064 "AARCH64_OPDE_UNALIGNED",
5065 "AARCH64_OPDE_REG_LIST",
5066 "AARCH64_OPDE_OTHER_ERROR",
5068 #endif /* DEBUG_AARCH64 */
5070 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5072 When multiple errors of different kinds are found in the same assembly
5073 line, only the error of the highest severity will be picked up for
5074 issuing the diagnostics. */
5077 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5078 enum aarch64_operand_error_kind rhs
)
5080 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5081 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5082 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5083 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5084 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5085 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5086 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5087 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5088 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5089 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5090 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5094 /* Helper routine to get the mnemonic name from the assembly instruction
5095 line; should only be called for the diagnosis purpose, as there is
5096 string copy operation involved, which may affect the runtime
5097 performance if used in elsewhere. */
5100 get_mnemonic_name (const char *str
)
5102 static char mnemonic
[32];
5105 /* Get the first 15 bytes and assume that the full name is included. */
5106 strncpy (mnemonic
, str
, 31);
5107 mnemonic
[31] = '\0';
5109 /* Scan up to the end of the mnemonic, which must end in white space,
5110 '.', or end of string. */
5111 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5116 /* Append '...' to the truncated long name. */
5117 if (ptr
- mnemonic
== 31)
5118 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5124 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5126 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5127 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5130 /* Data structures storing one user error in the assembly code related to
5133 struct operand_error_record
5135 const aarch64_opcode
*opcode
;
5136 aarch64_operand_error detail
;
5137 struct operand_error_record
*next
;
5140 typedef struct operand_error_record operand_error_record
;
5142 struct operand_errors
5144 operand_error_record
*head
;
5145 operand_error_record
*tail
;
5148 typedef struct operand_errors operand_errors
;
5150 /* Top-level data structure reporting user errors for the current line of
5152 The way md_assemble works is that all opcodes sharing the same mnemonic
5153 name are iterated to find a match to the assembly line. In this data
5154 structure, each of the such opcodes will have one operand_error_record
5155 allocated and inserted. In other words, excessive errors related with
5156 a single opcode are disregarded. */
5157 operand_errors operand_error_report
;
5159 /* Free record nodes. */
5160 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5162 /* Initialize the data structure that stores the operand mismatch
5163 information on assembling one line of the assembly code. */
5165 init_operand_error_report (void)
5167 if (operand_error_report
.head
!= NULL
)
5169 gas_assert (operand_error_report
.tail
!= NULL
);
5170 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5171 free_opnd_error_record_nodes
= operand_error_report
.head
;
5172 operand_error_report
.head
= NULL
;
5173 operand_error_report
.tail
= NULL
;
5176 gas_assert (operand_error_report
.tail
== NULL
);
5179 /* Return TRUE if some operand error has been recorded during the
5180 parsing of the current assembly line using the opcode *OPCODE;
5181 otherwise return FALSE. */
5183 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5185 operand_error_record
*record
= operand_error_report
.head
;
5186 return record
&& record
->opcode
== opcode
;
5189 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5190 OPCODE field is initialized with OPCODE.
5191 N.B. only one record for each opcode, i.e. the maximum of one error is
5192 recorded for each instruction template. */
5195 add_operand_error_record (const operand_error_record
* new_record
)
5197 const aarch64_opcode
*opcode
= new_record
->opcode
;
5198 operand_error_record
* record
= operand_error_report
.head
;
5200 /* The record may have been created for this opcode. If not, we need
5202 if (! opcode_has_operand_error_p (opcode
))
5204 /* Get one empty record. */
5205 if (free_opnd_error_record_nodes
== NULL
)
5207 record
= XNEW (operand_error_record
);
5211 record
= free_opnd_error_record_nodes
;
5212 free_opnd_error_record_nodes
= record
->next
;
5214 record
->opcode
= opcode
;
5215 /* Insert at the head. */
5216 record
->next
= operand_error_report
.head
;
5217 operand_error_report
.head
= record
;
5218 if (operand_error_report
.tail
== NULL
)
5219 operand_error_report
.tail
= record
;
5221 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5222 && record
->detail
.index
<= new_record
->detail
.index
5223 && operand_error_higher_severity_p (record
->detail
.kind
,
5224 new_record
->detail
.kind
))
5226 /* In the case of multiple errors found on operands related with a
5227 single opcode, only record the error of the leftmost operand and
5228 only if the error is of higher severity. */
5229 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5230 " the existing error %s on operand %d",
5231 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5232 new_record
->detail
.index
,
5233 operand_mismatch_kind_names
[record
->detail
.kind
],
5234 record
->detail
.index
);
5238 record
->detail
= new_record
->detail
;
5242 record_operand_error_info (const aarch64_opcode
*opcode
,
5243 aarch64_operand_error
*error_info
)
5245 operand_error_record record
;
5246 record
.opcode
= opcode
;
5247 record
.detail
= *error_info
;
5248 add_operand_error_record (&record
);
5251 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5252 error message *ERROR, for operand IDX (count from 0). */
5255 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5256 enum aarch64_operand_error_kind kind
,
5259 aarch64_operand_error info
;
5260 memset(&info
, 0, sizeof (info
));
5264 info
.non_fatal
= false;
5265 record_operand_error_info (opcode
, &info
);
5269 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5270 enum aarch64_operand_error_kind kind
,
5271 const char* error
, const int *extra_data
)
5273 aarch64_operand_error info
;
5277 info
.data
[0].i
= extra_data
[0];
5278 info
.data
[1].i
= extra_data
[1];
5279 info
.data
[2].i
= extra_data
[2];
5280 info
.non_fatal
= false;
5281 record_operand_error_info (opcode
, &info
);
5285 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5286 const char* error
, int lower_bound
,
5289 int data
[3] = {lower_bound
, upper_bound
, 0};
5290 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5294 /* Remove the operand error record for *OPCODE. */
5295 static void ATTRIBUTE_UNUSED
5296 remove_operand_error_record (const aarch64_opcode
*opcode
)
5298 if (opcode_has_operand_error_p (opcode
))
5300 operand_error_record
* record
= operand_error_report
.head
;
5301 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5302 operand_error_report
.head
= record
->next
;
5303 record
->next
= free_opnd_error_record_nodes
;
5304 free_opnd_error_record_nodes
= record
;
5305 if (operand_error_report
.head
== NULL
)
5307 gas_assert (operand_error_report
.tail
== record
);
5308 operand_error_report
.tail
= NULL
;
5313 /* Given the instruction in *INSTR, return the index of the best matched
5314 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5316 Return -1 if there is no qualifier sequence; return the first match
5317 if there is multiple matches found. */
5320 find_best_match (const aarch64_inst
*instr
,
5321 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5323 int i
, num_opnds
, max_num_matched
, idx
;
5325 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5328 DEBUG_TRACE ("no operand");
5332 max_num_matched
= 0;
5335 /* For each pattern. */
5336 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5339 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5341 /* Most opcodes has much fewer patterns in the list. */
5342 if (empty_qualifier_sequence_p (qualifiers
))
5344 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5348 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5349 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5352 if (num_matched
> max_num_matched
)
5354 max_num_matched
= num_matched
;
5359 DEBUG_TRACE ("return with %d", idx
);
5363 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5364 corresponding operands in *INSTR. */
5367 assign_qualifier_sequence (aarch64_inst
*instr
,
5368 const aarch64_opnd_qualifier_t
*qualifiers
)
5371 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5372 gas_assert (num_opnds
);
5373 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5374 instr
->operands
[i
].qualifier
= *qualifiers
;
5377 /* Callback used by aarch64_print_operand to apply STYLE to the
5378 disassembler output created from FMT and ARGS. The STYLER object holds
5379 any required state. Must return a pointer to a string (created from FMT
5380 and ARGS) that will continue to be valid until the complete disassembled
5381 instruction has been printed.
5383 We don't currently add any styling to the output of the disassembler as
5384 used within assembler error messages, and so STYLE is ignored here. A
5385 new string is allocated on the obstack help within STYLER and returned
5388 static const char *aarch64_apply_style
5389 (struct aarch64_styler
*styler
,
5390 enum disassembler_style style ATTRIBUTE_UNUSED
,
5391 const char *fmt
, va_list args
)
5395 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5398 /* Calculate the required space. */
5400 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5402 gas_assert (res
>= 0);
5404 /* Allocate space on the obstack and format the result. */
5405 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5406 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5407 gas_assert (res
>= 0);
5412 /* Print operands for the diagnosis purpose. */
5415 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5416 const aarch64_opnd_info
*opnds
)
5419 struct aarch64_styler styler
;
5420 struct obstack content
;
5421 obstack_init (&content
);
5423 styler
.apply_style
= aarch64_apply_style
;
5424 styler
.state
= (void *) &content
;
5426 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5431 /* We regard the opcode operand info more, however we also look into
5432 the inst->operands to support the disassembling of the optional
5434 The two operand code should be the same in all cases, apart from
5435 when the operand can be optional. */
5436 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5437 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5440 /* Generate the operand string in STR. */
5441 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5442 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5446 strcat (buf
, i
== 0 ? " " : ", ");
5448 /* Append the operand string. */
5451 /* Append a comment. This works because only the last operand ever
5452 adds a comment. If that ever changes then we'll need to be
5456 strcat (buf
, "\t// ");
5461 obstack_free (&content
, NULL
);
5464 /* Send to stderr a string as information. */
5467 output_info (const char *format
, ...)
5473 file
= as_where (&line
);
5477 fprintf (stderr
, "%s:%u: ", file
, line
);
5479 fprintf (stderr
, "%s: ", file
);
5481 fprintf (stderr
, _("Info: "));
5482 va_start (args
, format
);
5483 vfprintf (stderr
, format
, args
);
5485 (void) putc ('\n', stderr
);
5488 /* Output one operand error record. */
5491 output_operand_error_record (const operand_error_record
*record
, char *str
)
5493 const aarch64_operand_error
*detail
= &record
->detail
;
5494 int idx
= detail
->index
;
5495 const aarch64_opcode
*opcode
= record
->opcode
;
5496 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5497 : AARCH64_OPND_NIL
);
5499 typedef void (*handler_t
)(const char *format
, ...);
5500 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5502 switch (detail
->kind
)
5504 case AARCH64_OPDE_NIL
:
5508 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5509 handler (_("this `%s' should have an immediately preceding `%s'"
5511 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5514 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5515 handler (_("the preceding `%s' should be followed by `%s` rather"
5516 " than `%s` -- `%s'"),
5517 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5520 case AARCH64_OPDE_SYNTAX_ERROR
:
5521 case AARCH64_OPDE_RECOVERABLE
:
5522 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5523 case AARCH64_OPDE_OTHER_ERROR
:
5524 /* Use the prepared error message if there is, otherwise use the
5525 operand description string to describe the error. */
5526 if (detail
->error
!= NULL
)
5529 handler (_("%s -- `%s'"), detail
->error
, str
);
5531 handler (_("%s at operand %d -- `%s'"),
5532 detail
->error
, idx
+ 1, str
);
5536 gas_assert (idx
>= 0);
5537 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5538 aarch64_get_operand_desc (opd_code
), str
);
5542 case AARCH64_OPDE_INVALID_VARIANT
:
5543 handler (_("operand mismatch -- `%s'"), str
);
5544 if (verbose_error_p
)
5546 /* We will try to correct the erroneous instruction and also provide
5547 more information e.g. all other valid variants.
5549 The string representation of the corrected instruction and other
5550 valid variants are generated by
5552 1) obtaining the intermediate representation of the erroneous
5554 2) manipulating the IR, e.g. replacing the operand qualifier;
5555 3) printing out the instruction by calling the printer functions
5556 shared with the disassembler.
5558 The limitation of this method is that the exact input assembly
5559 line cannot be accurately reproduced in some cases, for example an
5560 optional operand present in the actual assembly line will be
5561 omitted in the output; likewise for the optional syntax rules,
5562 e.g. the # before the immediate. Another limitation is that the
5563 assembly symbols and relocation operations in the assembly line
5564 currently cannot be printed out in the error report. Last but not
5565 least, when there is other error(s) co-exist with this error, the
5566 'corrected' instruction may be still incorrect, e.g. given
5567 'ldnp h0,h1,[x0,#6]!'
5568 this diagnosis will provide the version:
5569 'ldnp s0,s1,[x0,#6]!'
5570 which is still not right. */
5571 size_t len
= strlen (get_mnemonic_name (str
));
5575 aarch64_inst
*inst_base
= &inst
.base
;
5576 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5579 reset_aarch64_instruction (&inst
);
5580 inst_base
->opcode
= opcode
;
5582 /* Reset the error report so that there is no side effect on the
5583 following operand parsing. */
5584 init_operand_error_report ();
5587 result
= parse_operands (str
+ len
, opcode
)
5588 && programmer_friendly_fixup (&inst
);
5589 gas_assert (result
);
5590 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5591 NULL
, NULL
, insn_sequence
);
5592 gas_assert (!result
);
5594 /* Find the most matched qualifier sequence. */
5595 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5596 gas_assert (qlf_idx
> -1);
5598 /* Assign the qualifiers. */
5599 assign_qualifier_sequence (inst_base
,
5600 opcode
->qualifiers_list
[qlf_idx
]);
5602 /* Print the hint. */
5603 output_info (_(" did you mean this?"));
5604 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5605 print_operands (buf
, opcode
, inst_base
->operands
);
5606 output_info (_(" %s"), buf
);
5608 /* Print out other variant(s) if there is any. */
5610 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5611 output_info (_(" other valid variant(s):"));
5613 /* For each pattern. */
5614 qualifiers_list
= opcode
->qualifiers_list
;
5615 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5617 /* Most opcodes has much fewer patterns in the list.
5618 First NIL qualifier indicates the end in the list. */
5619 if (empty_qualifier_sequence_p (*qualifiers_list
))
5624 /* Mnemonics name. */
5625 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5627 /* Assign the qualifiers. */
5628 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5630 /* Print instruction. */
5631 print_operands (buf
, opcode
, inst_base
->operands
);
5633 output_info (_(" %s"), buf
);
5639 case AARCH64_OPDE_UNTIED_IMMS
:
5640 handler (_("operand %d must have the same immediate value "
5641 "as operand 1 -- `%s'"),
5642 detail
->index
+ 1, str
);
5645 case AARCH64_OPDE_UNTIED_OPERAND
:
5646 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5647 detail
->index
+ 1, str
);
5650 case AARCH64_OPDE_OUT_OF_RANGE
:
5651 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5652 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5653 detail
->error
? detail
->error
: _("immediate value"),
5654 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5656 handler (_("%s must be %d at operand %d -- `%s'"),
5657 detail
->error
? detail
->error
: _("immediate value"),
5658 detail
->data
[0].i
, idx
+ 1, str
);
5661 case AARCH64_OPDE_REG_LIST
:
5662 if (detail
->data
[0].i
== 1)
5663 handler (_("invalid number of registers in the list; "
5664 "only 1 register is expected at operand %d -- `%s'"),
5667 handler (_("invalid number of registers in the list; "
5668 "%d registers are expected at operand %d -- `%s'"),
5669 detail
->data
[0].i
, idx
+ 1, str
);
5672 case AARCH64_OPDE_UNALIGNED
:
5673 handler (_("immediate value must be a multiple of "
5674 "%d at operand %d -- `%s'"),
5675 detail
->data
[0].i
, idx
+ 1, str
);
5684 /* Process and output the error message about the operand mismatching.
5686 When this function is called, the operand error information had
5687 been collected for an assembly line and there will be multiple
5688 errors in the case of multiple instruction templates; output the
5689 error message that most closely describes the problem.
5691 The errors to be printed can be filtered on printing all errors
5692 or only non-fatal errors. This distinction has to be made because
5693 the error buffer may already be filled with fatal errors we don't want to
5694 print due to the different instruction templates. */
5697 output_operand_error_report (char *str
, bool non_fatal_only
)
5699 int largest_error_pos
;
5700 const char *msg
= NULL
;
5701 enum aarch64_operand_error_kind kind
;
5702 operand_error_record
*curr
;
5703 operand_error_record
*head
= operand_error_report
.head
;
5704 operand_error_record
*record
= NULL
;
5706 /* No error to report. */
5710 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5712 /* Only one error. */
5713 if (head
== operand_error_report
.tail
)
5715 /* If the only error is a non-fatal one and we don't want to print it,
5717 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5719 DEBUG_TRACE ("single opcode entry with error kind: %s",
5720 operand_mismatch_kind_names
[head
->detail
.kind
]);
5721 output_operand_error_record (head
, str
);
5726 /* Find the error kind of the highest severity. */
5727 DEBUG_TRACE ("multiple opcode entries with error kind");
5728 kind
= AARCH64_OPDE_NIL
;
5729 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5731 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5732 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5733 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5734 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5735 kind
= curr
->detail
.kind
;
5738 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5740 /* Pick up one of errors of KIND to report. */
5741 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5742 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5744 /* If we don't want to print non-fatal errors then don't consider them
5746 if (curr
->detail
.kind
!= kind
5747 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5749 /* If there are multiple errors, pick up the one with the highest
5750 mismatching operand index. In the case of multiple errors with
5751 the equally highest operand index, pick up the first one or the
5752 first one with non-NULL error message. */
5753 if (curr
->detail
.index
> largest_error_pos
5754 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5755 && curr
->detail
.error
!= NULL
))
5757 largest_error_pos
= curr
->detail
.index
;
5759 msg
= record
->detail
.error
;
5763 /* The way errors are collected in the back-end is a bit non-intuitive. But
5764 essentially, because each operand template is tried recursively you may
5765 always have errors collected from the previous tried OPND. These are
5766 usually skipped if there is one successful match. However now with the
5767 non-fatal errors we have to ignore those previously collected hard errors
5768 when we're only interested in printing the non-fatal ones. This condition
5769 prevents us from printing errors that are not appropriate, since we did
5770 match a condition, but it also has warnings that it wants to print. */
5771 if (non_fatal_only
&& !record
)
5774 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5775 DEBUG_TRACE ("Pick up error kind %s to report",
5776 operand_mismatch_kind_names
[record
->detail
.kind
]);
5779 output_operand_error_record (record
, str
);
5782 /* Write an AARCH64 instruction to buf - always little-endian. */
5784 put_aarch64_insn (char *buf
, uint32_t insn
)
5786 unsigned char *where
= (unsigned char *) buf
;
5788 where
[1] = insn
>> 8;
5789 where
[2] = insn
>> 16;
5790 where
[3] = insn
>> 24;
5794 get_aarch64_insn (char *buf
)
5796 unsigned char *where
= (unsigned char *) buf
;
5798 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5799 | ((uint32_t) where
[3] << 24)));
5804 output_inst (struct aarch64_inst
*new_inst
)
5808 to
= frag_more (INSN_SIZE
);
5810 frag_now
->tc_frag_data
.recorded
= 1;
5812 put_aarch64_insn (to
, inst
.base
.value
);
5814 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5816 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5817 INSN_SIZE
, &inst
.reloc
.exp
,
5820 DEBUG_TRACE ("Prepared relocation fix up");
5821 /* Don't check the addend value against the instruction size,
5822 that's the job of our code in md_apply_fix(). */
5823 fixp
->fx_no_overflow
= 1;
5824 if (new_inst
!= NULL
)
5825 fixp
->tc_fix_data
.inst
= new_inst
;
5826 if (aarch64_gas_internal_fixup_p ())
5828 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5829 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5830 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5834 dwarf2_emit_insn (INSN_SIZE
);
5837 /* Link together opcodes of the same name. */
5841 const aarch64_opcode
*opcode
;
5842 struct templates
*next
;
5845 typedef struct templates templates
;
5848 lookup_mnemonic (const char *start
, int len
)
5850 templates
*templ
= NULL
;
5852 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5856 /* Subroutine of md_assemble, responsible for looking up the primary
5857 opcode from the mnemonic the user wrote. BASE points to the beginning
5858 of the mnemonic, DOT points to the first '.' within the mnemonic
5859 (if any) and END points to the end of the mnemonic. */
5862 opcode_lookup (char *base
, char *dot
, char *end
)
5864 const aarch64_cond
*cond
;
5871 inst
.cond
= COND_ALWAYS
;
5873 /* Handle a possible condition. */
5876 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5879 inst
.cond
= cond
->value
;
5885 if (inst
.cond
== COND_ALWAYS
)
5887 /* Look for unaffixed mnemonic. */
5888 return lookup_mnemonic (base
, len
);
5892 /* append ".c" to mnemonic if conditional */
5893 memcpy (condname
, base
, len
);
5894 memcpy (condname
+ len
, ".c", 2);
5897 return lookup_mnemonic (base
, len
);
5903 /* Process an optional operand that is found omitted from the assembly line.
5904 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5905 instruction's opcode entry while IDX is the index of this omitted operand.
5909 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5910 int idx
, aarch64_opnd_info
*operand
)
5912 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5913 gas_assert (optional_operand_p (opcode
, idx
));
5914 gas_assert (!operand
->present
);
5918 case AARCH64_OPND_Rd
:
5919 case AARCH64_OPND_Rn
:
5920 case AARCH64_OPND_Rm
:
5921 case AARCH64_OPND_Rt
:
5922 case AARCH64_OPND_Rt2
:
5923 case AARCH64_OPND_Rt_LS64
:
5924 case AARCH64_OPND_Rt_SP
:
5925 case AARCH64_OPND_Rs
:
5926 case AARCH64_OPND_Ra
:
5927 case AARCH64_OPND_Rt_SYS
:
5928 case AARCH64_OPND_Rd_SP
:
5929 case AARCH64_OPND_Rn_SP
:
5930 case AARCH64_OPND_Rm_SP
:
5931 case AARCH64_OPND_Fd
:
5932 case AARCH64_OPND_Fn
:
5933 case AARCH64_OPND_Fm
:
5934 case AARCH64_OPND_Fa
:
5935 case AARCH64_OPND_Ft
:
5936 case AARCH64_OPND_Ft2
:
5937 case AARCH64_OPND_Sd
:
5938 case AARCH64_OPND_Sn
:
5939 case AARCH64_OPND_Sm
:
5940 case AARCH64_OPND_Va
:
5941 case AARCH64_OPND_Vd
:
5942 case AARCH64_OPND_Vn
:
5943 case AARCH64_OPND_Vm
:
5944 case AARCH64_OPND_VdD1
:
5945 case AARCH64_OPND_VnD1
:
5946 operand
->reg
.regno
= default_value
;
5949 case AARCH64_OPND_Ed
:
5950 case AARCH64_OPND_En
:
5951 case AARCH64_OPND_Em
:
5952 case AARCH64_OPND_Em16
:
5953 case AARCH64_OPND_SM3_IMM2
:
5954 operand
->reglane
.regno
= default_value
;
5957 case AARCH64_OPND_IDX
:
5958 case AARCH64_OPND_BIT_NUM
:
5959 case AARCH64_OPND_IMMR
:
5960 case AARCH64_OPND_IMMS
:
5961 case AARCH64_OPND_SHLL_IMM
:
5962 case AARCH64_OPND_IMM_VLSL
:
5963 case AARCH64_OPND_IMM_VLSR
:
5964 case AARCH64_OPND_CCMP_IMM
:
5965 case AARCH64_OPND_FBITS
:
5966 case AARCH64_OPND_UIMM4
:
5967 case AARCH64_OPND_UIMM3_OP1
:
5968 case AARCH64_OPND_UIMM3_OP2
:
5969 case AARCH64_OPND_IMM
:
5970 case AARCH64_OPND_IMM_2
:
5971 case AARCH64_OPND_WIDTH
:
5972 case AARCH64_OPND_UIMM7
:
5973 case AARCH64_OPND_NZCV
:
5974 case AARCH64_OPND_SVE_PATTERN
:
5975 case AARCH64_OPND_SVE_PRFOP
:
5976 operand
->imm
.value
= default_value
;
5979 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5980 operand
->imm
.value
= default_value
;
5981 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5982 operand
->shifter
.amount
= 1;
5985 case AARCH64_OPND_EXCEPTION
:
5986 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5989 case AARCH64_OPND_BARRIER_ISB
:
5990 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5993 case AARCH64_OPND_BTI_TARGET
:
5994 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6002 /* Process the relocation type for move wide instructions.
6003 Return TRUE on success; otherwise return FALSE. */
6006 process_movw_reloc_info (void)
6011 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6013 if (inst
.base
.opcode
->op
== OP_MOVK
)
6014 switch (inst
.reloc
.type
)
6016 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6017 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6018 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6019 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6020 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6021 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6022 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6023 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6024 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6025 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6026 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6028 (_("the specified relocation type is not allowed for MOVK"));
6034 switch (inst
.reloc
.type
)
6036 case BFD_RELOC_AARCH64_MOVW_G0
:
6037 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6038 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6039 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6040 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6041 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6042 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6043 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6044 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6045 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6046 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6047 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6048 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6051 case BFD_RELOC_AARCH64_MOVW_G1
:
6052 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6053 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6054 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6055 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6056 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6057 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6058 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6059 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6060 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6061 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6062 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6063 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6066 case BFD_RELOC_AARCH64_MOVW_G2
:
6067 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6068 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6069 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6070 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6071 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6072 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6075 set_fatal_syntax_error
6076 (_("the specified relocation type is not allowed for 32-bit "
6082 case BFD_RELOC_AARCH64_MOVW_G3
:
6083 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6086 set_fatal_syntax_error
6087 (_("the specified relocation type is not allowed for 32-bit "
6094 /* More cases should be added when more MOVW-related relocation types
6095 are supported in GAS. */
6096 gas_assert (aarch64_gas_internal_fixup_p ());
6097 /* The shift amount should have already been set by the parser. */
6100 inst
.base
.operands
[1].shifter
.amount
= shift
;
6104 /* A primitive log calculator. */
6106 static inline unsigned int
6107 get_logsz (unsigned int size
)
6109 const unsigned char ls
[16] =
6110 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6116 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6117 return ls
[size
- 1];
6120 /* Determine and return the real reloc type code for an instruction
6121 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6123 static inline bfd_reloc_code_real_type
6124 ldst_lo12_determine_real_reloc_type (void)
6126 unsigned logsz
, max_logsz
;
6127 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6128 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6130 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6132 BFD_RELOC_AARCH64_LDST8_LO12
,
6133 BFD_RELOC_AARCH64_LDST16_LO12
,
6134 BFD_RELOC_AARCH64_LDST32_LO12
,
6135 BFD_RELOC_AARCH64_LDST64_LO12
,
6136 BFD_RELOC_AARCH64_LDST128_LO12
6139 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6140 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6141 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6142 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6143 BFD_RELOC_AARCH64_NONE
6146 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6147 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6148 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6149 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6150 BFD_RELOC_AARCH64_NONE
6153 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6154 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6155 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6156 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6157 BFD_RELOC_AARCH64_NONE
6160 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6161 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6162 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6163 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6164 BFD_RELOC_AARCH64_NONE
6168 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6169 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6171 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6173 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6175 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6176 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6178 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6180 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6182 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6184 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6186 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6187 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6188 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6189 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6194 if (logsz
> max_logsz
)
6196 /* SEE PR 27904 for an example of this. */
6197 set_fatal_syntax_error
6198 (_("relocation qualifier does not match instruction size"));
6199 return BFD_RELOC_AARCH64_NONE
;
6202 /* In reloc.c, these pseudo relocation types should be defined in similar
6203 order as above reloc_ldst_lo12 array. Because the array index calculation
6204 below relies on this. */
6205 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6208 /* Check whether a register list REGINFO is valid. The registers must be
6209 numbered in increasing order (modulo 32), in increments of one or two.
6211 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6214 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6217 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6219 uint32_t i
, nb_regs
, prev_regno
, incr
;
6221 nb_regs
= 1 + (reginfo
& 0x3);
6223 prev_regno
= reginfo
& 0x1f;
6224 incr
= accept_alternate
? 2 : 1;
6226 for (i
= 1; i
< nb_regs
; ++i
)
6228 uint32_t curr_regno
;
6230 curr_regno
= reginfo
& 0x1f;
6231 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6233 prev_regno
= curr_regno
;
6239 /* Generic instruction operand parser. This does no encoding and no
6240 semantic validation; it merely squirrels values away in the inst
6241 structure. Returns TRUE or FALSE depending on whether the
6242 specified grammar matched. */
6245 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6248 char *backtrack_pos
= 0;
6249 const enum aarch64_opnd
*operands
= opcode
->operands
;
6250 aarch64_reg_type imm_reg_type
;
6253 skip_whitespace (str
);
6255 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6257 | AARCH64_FEATURE_SVE2
))
6258 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6260 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6262 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6265 const reg_entry
*reg
;
6266 int comma_skipped_p
= 0;
6267 struct vector_type_el vectype
;
6268 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6269 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6270 aarch64_reg_type reg_type
;
6272 DEBUG_TRACE ("parse operand %d", i
);
6274 /* Assign the operand code. */
6275 info
->type
= operands
[i
];
6277 if (optional_operand_p (opcode
, i
))
6279 /* Remember where we are in case we need to backtrack. */
6280 gas_assert (!backtrack_pos
);
6281 backtrack_pos
= str
;
6284 /* Expect comma between operands; the backtrack mechanism will take
6285 care of cases of omitted optional operand. */
6286 if (i
> 0 && ! skip_past_char (&str
, ','))
6288 set_syntax_error (_("comma expected between operands"));
6292 comma_skipped_p
= 1;
6294 switch (operands
[i
])
6296 case AARCH64_OPND_Rd
:
6297 case AARCH64_OPND_Rn
:
6298 case AARCH64_OPND_Rm
:
6299 case AARCH64_OPND_Rt
:
6300 case AARCH64_OPND_Rt2
:
6301 case AARCH64_OPND_Rs
:
6302 case AARCH64_OPND_Ra
:
6303 case AARCH64_OPND_Rt_LS64
:
6304 case AARCH64_OPND_Rt_SYS
:
6305 case AARCH64_OPND_PAIRREG
:
6306 case AARCH64_OPND_SVE_Rm
:
6307 po_int_reg_or_fail (REG_TYPE_R_Z
);
6309 /* In LS64 load/store instructions Rt register number must be even
6311 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6313 /* We've already checked if this is valid register.
6314 This will check if register number (Rt) is not undefined for LS64
6316 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6317 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6319 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6325 case AARCH64_OPND_Rd_SP
:
6326 case AARCH64_OPND_Rn_SP
:
6327 case AARCH64_OPND_Rt_SP
:
6328 case AARCH64_OPND_SVE_Rn_SP
:
6329 case AARCH64_OPND_Rm_SP
:
6330 po_int_reg_or_fail (REG_TYPE_R_SP
);
6333 case AARCH64_OPND_Rm_EXT
:
6334 case AARCH64_OPND_Rm_SFT
:
6335 po_misc_or_fail (parse_shifter_operand
6336 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6338 : SHIFTED_LOGIC_IMM
)));
6339 if (!info
->shifter
.operator_present
)
6341 /* Default to LSL if not present. Libopcodes prefers shifter
6342 kind to be explicit. */
6343 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6344 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6345 /* For Rm_EXT, libopcodes will carry out further check on whether
6346 or not stack pointer is used in the instruction (Recall that
6347 "the extend operator is not optional unless at least one of
6348 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6352 case AARCH64_OPND_Fd
:
6353 case AARCH64_OPND_Fn
:
6354 case AARCH64_OPND_Fm
:
6355 case AARCH64_OPND_Fa
:
6356 case AARCH64_OPND_Ft
:
6357 case AARCH64_OPND_Ft2
:
6358 case AARCH64_OPND_Sd
:
6359 case AARCH64_OPND_Sn
:
6360 case AARCH64_OPND_Sm
:
6361 case AARCH64_OPND_SVE_VZn
:
6362 case AARCH64_OPND_SVE_Vd
:
6363 case AARCH64_OPND_SVE_Vm
:
6364 case AARCH64_OPND_SVE_Vn
:
6365 reg
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, NULL
);
6368 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6371 gas_assert (reg
->type
>= REG_TYPE_FP_B
6372 && reg
->type
<= REG_TYPE_FP_Q
);
6374 info
->reg
.regno
= reg
->number
;
6375 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
6378 case AARCH64_OPND_SVE_Pd
:
6379 case AARCH64_OPND_SVE_Pg3
:
6380 case AARCH64_OPND_SVE_Pg4_5
:
6381 case AARCH64_OPND_SVE_Pg4_10
:
6382 case AARCH64_OPND_SVE_Pg4_16
:
6383 case AARCH64_OPND_SVE_Pm
:
6384 case AARCH64_OPND_SVE_Pn
:
6385 case AARCH64_OPND_SVE_Pt
:
6386 case AARCH64_OPND_SME_Pm
:
6387 reg_type
= REG_TYPE_PN
;
6390 case AARCH64_OPND_SVE_Za_5
:
6391 case AARCH64_OPND_SVE_Za_16
:
6392 case AARCH64_OPND_SVE_Zd
:
6393 case AARCH64_OPND_SVE_Zm_5
:
6394 case AARCH64_OPND_SVE_Zm_16
:
6395 case AARCH64_OPND_SVE_Zn
:
6396 case AARCH64_OPND_SVE_Zt
:
6397 reg_type
= REG_TYPE_ZN
;
6400 case AARCH64_OPND_Va
:
6401 case AARCH64_OPND_Vd
:
6402 case AARCH64_OPND_Vn
:
6403 case AARCH64_OPND_Vm
:
6404 reg_type
= REG_TYPE_VN
;
6406 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6409 first_error (_(get_reg_expected_msg (reg_type
)));
6412 if (vectype
.defined
& NTA_HASINDEX
)
6415 info
->reg
.regno
= reg
->number
;
6416 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6417 && vectype
.type
== NT_invtype
)
6418 /* Unqualified Pn and Zn registers are allowed in certain
6419 contexts. Rely on F_STRICT qualifier checking to catch
6421 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6424 info
->qualifier
= vectype_to_qualifier (&vectype
);
6425 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6430 case AARCH64_OPND_VdD1
:
6431 case AARCH64_OPND_VnD1
:
6432 reg
= aarch64_reg_parse (&str
, REG_TYPE_VN
, &vectype
);
6435 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6438 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6440 set_fatal_syntax_error
6441 (_("the top half of a 128-bit FP/SIMD register is expected"));
6444 info
->reg
.regno
= reg
->number
;
6445 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6446 here; it is correct for the purpose of encoding/decoding since
6447 only the register number is explicitly encoded in the related
6448 instructions, although this appears a bit hacky. */
6449 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6452 case AARCH64_OPND_SVE_Zm3_INDEX
:
6453 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6454 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6455 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6456 case AARCH64_OPND_SVE_Zm4_INDEX
:
6457 case AARCH64_OPND_SVE_Zn_INDEX
:
6458 reg_type
= REG_TYPE_ZN
;
6459 goto vector_reg_index
;
6461 case AARCH64_OPND_Ed
:
6462 case AARCH64_OPND_En
:
6463 case AARCH64_OPND_Em
:
6464 case AARCH64_OPND_Em16
:
6465 case AARCH64_OPND_SM3_IMM2
:
6466 reg_type
= REG_TYPE_VN
;
6468 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6471 first_error (_(get_reg_expected_msg (reg_type
)));
6474 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6477 info
->reglane
.regno
= reg
->number
;
6478 info
->reglane
.index
= vectype
.index
;
6479 info
->qualifier
= vectype_to_qualifier (&vectype
);
6480 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6484 case AARCH64_OPND_SVE_ZnxN
:
6485 case AARCH64_OPND_SVE_ZtxN
:
6486 reg_type
= REG_TYPE_ZN
;
6487 goto vector_reg_list
;
6489 case AARCH64_OPND_LVn
:
6490 case AARCH64_OPND_LVt
:
6491 case AARCH64_OPND_LVt_AL
:
6492 case AARCH64_OPND_LEt
:
6493 reg_type
= REG_TYPE_VN
;
6495 if (reg_type
== REG_TYPE_ZN
6496 && get_opcode_dependent_value (opcode
) == 1
6499 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6502 first_error (_(get_reg_expected_msg (reg_type
)));
6505 info
->reglist
.first_regno
= reg
->number
;
6506 info
->reglist
.num_regs
= 1;
6510 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6511 if (val
== PARSE_FAIL
)
6514 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6516 set_fatal_syntax_error (_("invalid register list"));
6520 if (vectype
.width
!= 0 && *str
!= ',')
6522 set_fatal_syntax_error
6523 (_("expected element type rather than vector type"));
6527 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6528 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6530 if (operands
[i
] == AARCH64_OPND_LEt
)
6532 if (!(vectype
.defined
& NTA_HASINDEX
))
6534 info
->reglist
.has_index
= 1;
6535 info
->reglist
.index
= vectype
.index
;
6539 if (vectype
.defined
& NTA_HASINDEX
)
6541 if (!(vectype
.defined
& NTA_HASTYPE
))
6543 if (reg_type
== REG_TYPE_ZN
)
6544 set_fatal_syntax_error (_("missing type suffix"));
6548 info
->qualifier
= vectype_to_qualifier (&vectype
);
6549 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6553 case AARCH64_OPND_CRn
:
6554 case AARCH64_OPND_CRm
:
6556 char prefix
= *(str
++);
6557 if (prefix
!= 'c' && prefix
!= 'C')
6560 po_imm_nc_or_fail ();
6563 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6566 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6567 info
->imm
.value
= val
;
6571 case AARCH64_OPND_SHLL_IMM
:
6572 case AARCH64_OPND_IMM_VLSR
:
6573 po_imm_or_fail (1, 64);
6574 info
->imm
.value
= val
;
6577 case AARCH64_OPND_CCMP_IMM
:
6578 case AARCH64_OPND_SIMM5
:
6579 case AARCH64_OPND_FBITS
:
6580 case AARCH64_OPND_TME_UIMM16
:
6581 case AARCH64_OPND_UIMM4
:
6582 case AARCH64_OPND_UIMM4_ADDG
:
6583 case AARCH64_OPND_UIMM10
:
6584 case AARCH64_OPND_UIMM3_OP1
:
6585 case AARCH64_OPND_UIMM3_OP2
:
6586 case AARCH64_OPND_IMM_VLSL
:
6587 case AARCH64_OPND_IMM
:
6588 case AARCH64_OPND_IMM_2
:
6589 case AARCH64_OPND_WIDTH
:
6590 case AARCH64_OPND_SVE_INV_LIMM
:
6591 case AARCH64_OPND_SVE_LIMM
:
6592 case AARCH64_OPND_SVE_LIMM_MOV
:
6593 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6594 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6595 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6596 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6597 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6598 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6599 case AARCH64_OPND_SVE_SIMM5
:
6600 case AARCH64_OPND_SVE_SIMM5B
:
6601 case AARCH64_OPND_SVE_SIMM6
:
6602 case AARCH64_OPND_SVE_SIMM8
:
6603 case AARCH64_OPND_SVE_UIMM3
:
6604 case AARCH64_OPND_SVE_UIMM7
:
6605 case AARCH64_OPND_SVE_UIMM8
:
6606 case AARCH64_OPND_SVE_UIMM8_53
:
6607 case AARCH64_OPND_IMM_ROT1
:
6608 case AARCH64_OPND_IMM_ROT2
:
6609 case AARCH64_OPND_IMM_ROT3
:
6610 case AARCH64_OPND_SVE_IMM_ROT1
:
6611 case AARCH64_OPND_SVE_IMM_ROT2
:
6612 case AARCH64_OPND_SVE_IMM_ROT3
:
6613 case AARCH64_OPND_CSSC_SIMM8
:
6614 case AARCH64_OPND_CSSC_UIMM8
:
6615 po_imm_nc_or_fail ();
6616 info
->imm
.value
= val
;
6619 case AARCH64_OPND_SVE_AIMM
:
6620 case AARCH64_OPND_SVE_ASIMM
:
6621 po_imm_nc_or_fail ();
6622 info
->imm
.value
= val
;
6623 skip_whitespace (str
);
6624 if (skip_past_comma (&str
))
6625 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6627 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6630 case AARCH64_OPND_SVE_PATTERN
:
6631 po_enum_or_fail (aarch64_sve_pattern_array
);
6632 info
->imm
.value
= val
;
6635 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6636 po_enum_or_fail (aarch64_sve_pattern_array
);
6637 info
->imm
.value
= val
;
6638 if (skip_past_comma (&str
)
6639 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6641 if (!info
->shifter
.operator_present
)
6643 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6644 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6645 info
->shifter
.amount
= 1;
6649 case AARCH64_OPND_SVE_PRFOP
:
6650 po_enum_or_fail (aarch64_sve_prfop_array
);
6651 info
->imm
.value
= val
;
6654 case AARCH64_OPND_UIMM7
:
6655 po_imm_or_fail (0, 127);
6656 info
->imm
.value
= val
;
6659 case AARCH64_OPND_IDX
:
6660 case AARCH64_OPND_MASK
:
6661 case AARCH64_OPND_BIT_NUM
:
6662 case AARCH64_OPND_IMMR
:
6663 case AARCH64_OPND_IMMS
:
6664 po_imm_or_fail (0, 63);
6665 info
->imm
.value
= val
;
6668 case AARCH64_OPND_IMM0
:
6669 po_imm_nc_or_fail ();
6672 set_fatal_syntax_error (_("immediate zero expected"));
6675 info
->imm
.value
= 0;
6678 case AARCH64_OPND_FPIMM0
:
6681 bool res1
= false, res2
= false;
6682 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6683 it is probably not worth the effort to support it. */
6684 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6687 || !(res2
= parse_constant_immediate (&str
, &val
,
6690 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6692 info
->imm
.value
= 0;
6693 info
->imm
.is_fp
= 1;
6696 set_fatal_syntax_error (_("immediate zero expected"));
6700 case AARCH64_OPND_IMM_MOV
:
6703 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6704 reg_name_p (str
, REG_TYPE_VN
))
6707 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6708 GE_OPT_PREFIX
, REJECT_ABSENT
));
6709 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6710 later. fix_mov_imm_insn will try to determine a machine
6711 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6712 message if the immediate cannot be moved by a single
6714 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6715 inst
.base
.operands
[i
].skip
= 1;
6719 case AARCH64_OPND_SIMD_IMM
:
6720 case AARCH64_OPND_SIMD_IMM_SFT
:
6721 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6723 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6725 /* need_libopcodes_p */ 1,
6728 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6729 shift, we don't check it here; we leave the checking to
6730 the libopcodes (operand_general_constraint_met_p). By
6731 doing this, we achieve better diagnostics. */
6732 if (skip_past_comma (&str
)
6733 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6735 if (!info
->shifter
.operator_present
6736 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6738 /* Default to LSL if not present. Libopcodes prefers shifter
6739 kind to be explicit. */
6740 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6741 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6745 case AARCH64_OPND_FPIMM
:
6746 case AARCH64_OPND_SIMD_FPIMM
:
6747 case AARCH64_OPND_SVE_FPIMM8
:
6752 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6753 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6754 || !aarch64_imm_float_p (qfloat
))
6757 set_fatal_syntax_error (_("invalid floating-point"
6761 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6762 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6766 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6767 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6768 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6773 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6774 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6777 set_fatal_syntax_error (_("invalid floating-point"
6781 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6782 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6786 case AARCH64_OPND_LIMM
:
6787 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6788 SHIFTED_LOGIC_IMM
));
6789 if (info
->shifter
.operator_present
)
6791 set_fatal_syntax_error
6792 (_("shift not allowed for bitmask immediate"));
6795 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6797 /* need_libopcodes_p */ 1,
6801 case AARCH64_OPND_AIMM
:
6802 if (opcode
->op
== OP_ADD
)
6803 /* ADD may have relocation types. */
6804 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6805 SHIFTED_ARITH_IMM
));
6807 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6808 SHIFTED_ARITH_IMM
));
6809 switch (inst
.reloc
.type
)
6811 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6812 info
->shifter
.amount
= 12;
6814 case BFD_RELOC_UNUSED
:
6815 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6816 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6817 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6818 inst
.reloc
.pc_rel
= 0;
6823 info
->imm
.value
= 0;
6824 if (!info
->shifter
.operator_present
)
6826 /* Default to LSL if not present. Libopcodes prefers shifter
6827 kind to be explicit. */
6828 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6829 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6833 case AARCH64_OPND_HALF
:
6835 /* #<imm16> or relocation. */
6836 int internal_fixup_p
;
6837 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6838 if (internal_fixup_p
)
6839 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6840 skip_whitespace (str
);
6841 if (skip_past_comma (&str
))
6843 /* {, LSL #<shift>} */
6844 if (! aarch64_gas_internal_fixup_p ())
6846 set_fatal_syntax_error (_("can't mix relocation modifier "
6847 "with explicit shift"));
6850 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6853 inst
.base
.operands
[i
].shifter
.amount
= 0;
6854 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6855 inst
.base
.operands
[i
].imm
.value
= 0;
6856 if (! process_movw_reloc_info ())
6861 case AARCH64_OPND_EXCEPTION
:
6862 case AARCH64_OPND_UNDEFINED
:
6863 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6865 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6867 /* need_libopcodes_p */ 0,
6871 case AARCH64_OPND_NZCV
:
6873 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6877 info
->imm
.value
= nzcv
->value
;
6880 po_imm_or_fail (0, 15);
6881 info
->imm
.value
= val
;
6885 case AARCH64_OPND_COND
:
6886 case AARCH64_OPND_COND1
:
6891 while (ISALPHA (*str
));
6892 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6893 if (info
->cond
== NULL
)
6895 set_syntax_error (_("invalid condition"));
6898 else if (operands
[i
] == AARCH64_OPND_COND1
6899 && (info
->cond
->value
& 0xe) == 0xe)
6901 /* Do not allow AL or NV. */
6902 set_default_error ();
6908 case AARCH64_OPND_ADDR_ADRP
:
6909 po_misc_or_fail (parse_adrp (&str
));
6910 /* Clear the value as operand needs to be relocated. */
6911 info
->imm
.value
= 0;
6914 case AARCH64_OPND_ADDR_PCREL14
:
6915 case AARCH64_OPND_ADDR_PCREL19
:
6916 case AARCH64_OPND_ADDR_PCREL21
:
6917 case AARCH64_OPND_ADDR_PCREL26
:
6918 po_misc_or_fail (parse_address (&str
, info
));
6919 if (!info
->addr
.pcrel
)
6921 set_syntax_error (_("invalid pc-relative address"));
6924 if (inst
.gen_lit_pool
6925 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6927 /* Only permit "=value" in the literal load instructions.
6928 The literal will be generated by programmer_friendly_fixup. */
6929 set_syntax_error (_("invalid use of \"=immediate\""));
6932 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6934 set_syntax_error (_("unrecognized relocation suffix"));
6937 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6939 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6940 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6944 info
->imm
.value
= 0;
6945 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6946 switch (opcode
->iclass
)
6950 /* e.g. CBZ or B.COND */
6951 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6952 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6956 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6957 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6961 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6963 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6964 : BFD_RELOC_AARCH64_JUMP26
;
6967 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6968 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6971 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6972 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6978 inst
.reloc
.pc_rel
= 1;
6982 case AARCH64_OPND_ADDR_SIMPLE
:
6983 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6985 /* [<Xn|SP>{, #<simm>}] */
6987 /* First use the normal address-parsing routines, to get
6988 the usual syntax errors. */
6989 po_misc_or_fail (parse_address (&str
, info
));
6990 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6991 || !info
->addr
.preind
|| info
->addr
.postind
6992 || info
->addr
.writeback
)
6994 set_syntax_error (_("invalid addressing mode"));
6998 /* Then retry, matching the specific syntax of these addresses. */
7000 po_char_or_fail ('[');
7001 po_reg_or_fail (REG_TYPE_R64_SP
);
7002 /* Accept optional ", #0". */
7003 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7004 && skip_past_char (&str
, ','))
7006 skip_past_char (&str
, '#');
7007 if (! skip_past_char (&str
, '0'))
7009 set_fatal_syntax_error
7010 (_("the optional immediate offset can only be 0"));
7014 po_char_or_fail (']');
7018 case AARCH64_OPND_ADDR_REGOFF
:
7019 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7020 po_misc_or_fail (parse_address (&str
, info
));
7022 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7023 || !info
->addr
.preind
|| info
->addr
.postind
7024 || info
->addr
.writeback
)
7026 set_syntax_error (_("invalid addressing mode"));
7029 if (!info
->shifter
.operator_present
)
7031 /* Default to LSL if not present. Libopcodes prefers shifter
7032 kind to be explicit. */
7033 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7034 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7036 /* Qualifier to be deduced by libopcodes. */
7039 case AARCH64_OPND_ADDR_SIMM7
:
7040 po_misc_or_fail (parse_address (&str
, info
));
7041 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7042 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7044 set_syntax_error (_("invalid addressing mode"));
7047 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7049 set_syntax_error (_("relocation not allowed"));
7052 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7054 /* need_libopcodes_p */ 1,
7058 case AARCH64_OPND_ADDR_SIMM9
:
7059 case AARCH64_OPND_ADDR_SIMM9_2
:
7060 case AARCH64_OPND_ADDR_SIMM11
:
7061 case AARCH64_OPND_ADDR_SIMM13
:
7062 po_misc_or_fail (parse_address (&str
, info
));
7063 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7064 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7065 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7066 && info
->addr
.writeback
))
7068 set_syntax_error (_("invalid addressing mode"));
7071 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7073 set_syntax_error (_("relocation not allowed"));
7076 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7078 /* need_libopcodes_p */ 1,
7082 case AARCH64_OPND_ADDR_SIMM10
:
7083 case AARCH64_OPND_ADDR_OFFSET
:
7084 po_misc_or_fail (parse_address (&str
, info
));
7085 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7086 || !info
->addr
.preind
|| info
->addr
.postind
)
7088 set_syntax_error (_("invalid addressing mode"));
7091 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7093 set_syntax_error (_("relocation not allowed"));
7096 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7098 /* need_libopcodes_p */ 1,
7102 case AARCH64_OPND_ADDR_UIMM12
:
7103 po_misc_or_fail (parse_address (&str
, info
));
7104 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7105 || !info
->addr
.preind
|| info
->addr
.writeback
)
7107 set_syntax_error (_("invalid addressing mode"));
7110 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7111 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7112 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7114 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7116 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7118 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7120 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7121 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7122 /* Leave qualifier to be determined by libopcodes. */
7125 case AARCH64_OPND_SIMD_ADDR_POST
:
7126 /* [<Xn|SP>], <Xm|#<amount>> */
7127 po_misc_or_fail (parse_address (&str
, info
));
7128 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7130 set_syntax_error (_("invalid addressing mode"));
7133 if (!info
->addr
.offset
.is_reg
)
7135 if (inst
.reloc
.exp
.X_op
== O_constant
)
7136 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7139 set_fatal_syntax_error
7140 (_("writeback value must be an immediate constant"));
7147 case AARCH64_OPND_SME_SM_ZA
:
7149 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7151 set_syntax_error (_("unknown or missing PSTATE field name"));
7154 info
->reg
.regno
= val
;
7157 case AARCH64_OPND_SME_PnT_Wm_imm
:
7158 /* <Pn>.<T>[<Wm>, #<imm>] */
7162 val
= parse_sme_pred_reg_with_index (&str
,
7166 if (val
== PARSE_FAIL
)
7169 info
->za_tile_vector
.regno
= val
;
7170 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7171 info
->za_tile_vector
.index
.imm
= imm
;
7172 info
->qualifier
= qualifier
;
7176 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7177 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7178 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7179 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7180 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7181 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7182 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7183 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7184 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7185 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7186 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7187 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7188 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7189 /* [X<n>{, #imm, MUL VL}]
7191 but recognizing SVE registers. */
7192 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7193 &offset_qualifier
));
7194 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7196 set_syntax_error (_("invalid addressing mode"));
7200 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7201 || !info
->addr
.preind
|| info
->addr
.writeback
)
7203 set_syntax_error (_("invalid addressing mode"));
7206 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7207 || inst
.reloc
.exp
.X_op
!= O_constant
)
7209 /* Make sure this has priority over
7210 "invalid addressing mode". */
7211 set_fatal_syntax_error (_("constant offset required"));
7214 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7217 case AARCH64_OPND_SVE_ADDR_R
:
7218 /* [<Xn|SP>{, <R><m>}]
7219 but recognizing SVE registers. */
7220 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7221 &offset_qualifier
));
7222 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7224 offset_qualifier
= AARCH64_OPND_QLF_X
;
7225 info
->addr
.offset
.is_reg
= 1;
7226 info
->addr
.offset
.regno
= 31;
7228 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7229 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7231 set_syntax_error (_("invalid addressing mode"));
7236 case AARCH64_OPND_SVE_ADDR_RR
:
7237 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7238 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7239 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7240 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7241 case AARCH64_OPND_SVE_ADDR_RX
:
7242 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7243 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7244 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7245 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7246 but recognizing SVE registers. */
7247 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7248 &offset_qualifier
));
7249 if (base_qualifier
!= AARCH64_OPND_QLF_X
7250 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7252 set_syntax_error (_("invalid addressing mode"));
7257 case AARCH64_OPND_SVE_ADDR_RZ
:
7258 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7259 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7260 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7261 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7262 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7263 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7264 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7265 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7266 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7267 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7268 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7269 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7270 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7271 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7272 &offset_qualifier
));
7273 if (base_qualifier
!= AARCH64_OPND_QLF_X
7274 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7275 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7277 set_syntax_error (_("invalid addressing mode"));
7280 info
->qualifier
= offset_qualifier
;
7283 case AARCH64_OPND_SVE_ADDR_ZX
:
7284 /* [Zn.<T>{, <Xm>}]. */
7285 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7286 &offset_qualifier
));
7288 base_qualifier either S_S or S_D
7289 offset_qualifier must be X
7291 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7292 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7293 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7295 set_syntax_error (_("invalid addressing mode"));
7298 info
->qualifier
= base_qualifier
;
7299 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7300 || !info
->addr
.preind
|| info
->addr
.writeback
7301 || info
->shifter
.operator_present
!= 0)
7303 set_syntax_error (_("invalid addressing mode"));
7306 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7310 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7311 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7312 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7313 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7314 /* [Z<n>.<T>{, #imm}] */
7315 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7316 &offset_qualifier
));
7317 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7318 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7320 set_syntax_error (_("invalid addressing mode"));
7323 info
->qualifier
= base_qualifier
;
7326 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7327 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7328 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7329 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7330 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7334 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7336 here since we get better error messages by leaving it to
7337 the qualifier checking routines. */
7338 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7339 &offset_qualifier
));
7340 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7341 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7342 || offset_qualifier
!= base_qualifier
)
7344 set_syntax_error (_("invalid addressing mode"));
7347 info
->qualifier
= base_qualifier
;
7350 case AARCH64_OPND_SYSREG
:
7352 uint32_t sysreg_flags
;
7353 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7354 &sysreg_flags
)) == PARSE_FAIL
)
7356 set_syntax_error (_("unknown or missing system register name"));
7359 inst
.base
.operands
[i
].sysreg
.value
= val
;
7360 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7364 case AARCH64_OPND_PSTATEFIELD
:
7366 uint32_t sysreg_flags
;
7367 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7368 &sysreg_flags
)) == PARSE_FAIL
)
7370 set_syntax_error (_("unknown or missing PSTATE field name"));
7373 inst
.base
.operands
[i
].pstatefield
= val
;
7374 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7378 case AARCH64_OPND_SYSREG_IC
:
7379 inst
.base
.operands
[i
].sysins_op
=
7380 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7383 case AARCH64_OPND_SYSREG_DC
:
7384 inst
.base
.operands
[i
].sysins_op
=
7385 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7388 case AARCH64_OPND_SYSREG_AT
:
7389 inst
.base
.operands
[i
].sysins_op
=
7390 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7393 case AARCH64_OPND_SYSREG_SR
:
7394 inst
.base
.operands
[i
].sysins_op
=
7395 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7398 case AARCH64_OPND_SYSREG_TLBI
:
7399 inst
.base
.operands
[i
].sysins_op
=
7400 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7402 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7404 set_fatal_syntax_error ( _("unknown or missing operation name"));
7409 case AARCH64_OPND_BARRIER
:
7410 case AARCH64_OPND_BARRIER_ISB
:
7411 val
= parse_barrier (&str
);
7412 if (val
!= PARSE_FAIL
7413 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7415 /* ISB only accepts options name 'sy'. */
7417 (_("the specified option is not accepted in ISB"));
7418 /* Turn off backtrack as this optional operand is present. */
7422 if (val
!= PARSE_FAIL
7423 && operands
[i
] == AARCH64_OPND_BARRIER
)
7425 /* Regular barriers accept options CRm (C0-C15).
7426 DSB nXS barrier variant accepts values > 15. */
7427 if (val
< 0 || val
> 15)
7429 set_syntax_error (_("the specified option is not accepted in DSB"));
7433 /* This is an extension to accept a 0..15 immediate. */
7434 if (val
== PARSE_FAIL
)
7435 po_imm_or_fail (0, 15);
7436 info
->barrier
= aarch64_barrier_options
+ val
;
7439 case AARCH64_OPND_BARRIER_DSB_NXS
:
7440 val
= parse_barrier (&str
);
7441 if (val
!= PARSE_FAIL
)
7443 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7444 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7446 set_syntax_error (_("the specified option is not accepted in DSB"));
7447 /* Turn off backtrack as this optional operand is present. */
7454 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7455 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7456 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7458 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7460 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7464 /* Option index is encoded as 2-bit value in val<3:2>. */
7465 val
= (val
>> 2) - 4;
7466 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7469 case AARCH64_OPND_PRFOP
:
7470 val
= parse_pldop (&str
);
7471 /* This is an extension to accept a 0..31 immediate. */
7472 if (val
== PARSE_FAIL
)
7473 po_imm_or_fail (0, 31);
7474 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7477 case AARCH64_OPND_BARRIER_PSB
:
7478 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7479 if (val
== PARSE_FAIL
)
7483 case AARCH64_OPND_BTI_TARGET
:
7484 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7485 if (val
== PARSE_FAIL
)
7489 case AARCH64_OPND_SME_ZAda_2b
:
7490 case AARCH64_OPND_SME_ZAda_3b
:
7491 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
);
7494 info
->reg
.regno
= reg
->number
;
7495 info
->qualifier
= qualifier
;
7498 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7499 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7500 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7502 enum sme_hv_slice slice_indicator
;
7503 int vector_select_register
;
7506 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7507 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7509 &vector_select_register
,
7513 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7514 &vector_select_register
,
7517 if (val
== PARSE_FAIL
)
7519 info
->za_tile_vector
.regno
= val
;
7520 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7521 info
->za_tile_vector
.index
.imm
= imm
;
7522 info
->za_tile_vector
.v
= slice_indicator
;
7523 info
->qualifier
= qualifier
;
7527 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7528 val
= parse_sme_list_of_64bit_tiles (&str
);
7529 if (val
== PARSE_FAIL
)
7531 info
->imm
.value
= val
;
7534 case AARCH64_OPND_SME_ZA_array
:
7537 val
= parse_sme_za_array (&str
, &imm
);
7538 if (val
== PARSE_FAIL
)
7540 info
->za_tile_vector
.index
.regno
= val
;
7541 info
->za_tile_vector
.index
.imm
= imm
;
7545 case AARCH64_OPND_MOPS_ADDR_Rd
:
7546 case AARCH64_OPND_MOPS_ADDR_Rs
:
7547 po_char_or_fail ('[');
7548 if (!parse_x0_to_x30 (&str
, info
))
7550 po_char_or_fail (']');
7551 po_char_or_fail ('!');
7554 case AARCH64_OPND_MOPS_WB_Rn
:
7555 if (!parse_x0_to_x30 (&str
, info
))
7557 po_char_or_fail ('!');
7561 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7564 /* If we get here, this operand was successfully parsed. */
7565 inst
.base
.operands
[i
].present
= 1;
7569 /* The parse routine should already have set the error, but in case
7570 not, set a default one here. */
7572 set_default_error ();
7574 if (! backtrack_pos
)
7575 goto parse_operands_return
;
7578 /* We reach here because this operand is marked as optional, and
7579 either no operand was supplied or the operand was supplied but it
7580 was syntactically incorrect. In the latter case we report an
7581 error. In the former case we perform a few more checks before
7582 dropping through to the code to insert the default operand. */
7584 char *tmp
= backtrack_pos
;
7585 char endchar
= END_OF_INSN
;
7587 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7589 skip_past_char (&tmp
, ',');
7591 if (*tmp
!= endchar
)
7592 /* The user has supplied an operand in the wrong format. */
7593 goto parse_operands_return
;
7595 /* Make sure there is not a comma before the optional operand.
7596 For example the fifth operand of 'sys' is optional:
7598 sys #0,c0,c0,#0, <--- wrong
7599 sys #0,c0,c0,#0 <--- correct. */
7600 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7602 set_fatal_syntax_error
7603 (_("unexpected comma before the omitted optional operand"));
7604 goto parse_operands_return
;
7608 /* Reaching here means we are dealing with an optional operand that is
7609 omitted from the assembly line. */
7610 gas_assert (optional_operand_p (opcode
, i
));
7612 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7614 /* Try again, skipping the optional operand at backtrack_pos. */
7615 str
= backtrack_pos
;
7618 /* Clear any error record after the omitted optional operand has been
7619 successfully handled. */
7623 /* Check if we have parsed all the operands. */
7624 if (*str
!= '\0' && ! error_p ())
7626 /* Set I to the index of the last present operand; this is
7627 for the purpose of diagnostics. */
7628 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7630 set_fatal_syntax_error
7631 (_("unexpected characters following instruction"));
7634 parse_operands_return
:
7638 inst
.parsing_error
.index
= i
;
7639 DEBUG_TRACE ("parsing FAIL: %s - %s",
7640 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7641 inst
.parsing_error
.error
);
7642 /* Record the operand error properly; this is useful when there
7643 are multiple instruction templates for a mnemonic name, so that
7644 later on, we can select the error that most closely describes
7646 record_operand_error_info (opcode
, &inst
.parsing_error
);
7651 DEBUG_TRACE ("parsing SUCCESS");
7656 /* It does some fix-up to provide some programmer friendly feature while
7657 keeping the libopcodes happy, i.e. libopcodes only accepts
7658 the preferred architectural syntax.
7659 Return FALSE if there is any failure; otherwise return TRUE. */
7662 programmer_friendly_fixup (aarch64_instruction
*instr
)
7664 aarch64_inst
*base
= &instr
->base
;
7665 const aarch64_opcode
*opcode
= base
->opcode
;
7666 enum aarch64_op op
= opcode
->op
;
7667 aarch64_opnd_info
*operands
= base
->operands
;
7669 DEBUG_TRACE ("enter");
7671 switch (opcode
->iclass
)
7674 /* TBNZ Xn|Wn, #uimm6, label
7675 Test and Branch Not Zero: conditionally jumps to label if bit number
7676 uimm6 in register Xn is not zero. The bit number implies the width of
7677 the register, which may be written and should be disassembled as Wn if
7678 uimm is less than 32. */
7679 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7681 if (operands
[1].imm
.value
>= 32)
7683 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7687 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7691 /* LDR Wt, label | =value
7692 As a convenience assemblers will typically permit the notation
7693 "=value" in conjunction with the pc-relative literal load instructions
7694 to automatically place an immediate value or symbolic address in a
7695 nearby literal pool and generate a hidden label which references it.
7696 ISREG has been set to 0 in the case of =value. */
7697 if (instr
->gen_lit_pool
7698 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7700 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7701 if (op
== OP_LDRSW_LIT
)
7703 if (instr
->reloc
.exp
.X_op
!= O_constant
7704 && instr
->reloc
.exp
.X_op
!= O_big
7705 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7707 record_operand_error (opcode
, 1,
7708 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7709 _("constant expression expected"));
7712 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7714 record_operand_error (opcode
, 1,
7715 AARCH64_OPDE_OTHER_ERROR
,
7716 _("literal pool insertion failed"));
7724 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7725 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7726 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7727 A programmer-friendly assembler should accept a destination Xd in
7728 place of Wd, however that is not the preferred form for disassembly.
7730 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7731 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7732 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7733 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7738 /* In the 64-bit form, the final register operand is written as Wm
7739 for all but the (possibly omitted) UXTX/LSL and SXTX
7741 As a programmer-friendly assembler, we accept e.g.
7742 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7743 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7744 int idx
= aarch64_operand_index (opcode
->operands
,
7745 AARCH64_OPND_Rm_EXT
);
7746 gas_assert (idx
== 1 || idx
== 2);
7747 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7748 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7749 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7750 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7751 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7752 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7760 DEBUG_TRACE ("exit with SUCCESS");
7764 /* Check for loads and stores that will cause unpredictable behavior. */
7767 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7769 aarch64_inst
*base
= &instr
->base
;
7770 const aarch64_opcode
*opcode
= base
->opcode
;
7771 const aarch64_opnd_info
*opnds
= base
->operands
;
7772 switch (opcode
->iclass
)
7779 /* Loading/storing the base register is unpredictable if writeback. */
7780 if ((aarch64_get_operand_class (opnds
[0].type
)
7781 == AARCH64_OPND_CLASS_INT_REG
)
7782 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7783 && opnds
[1].addr
.base_regno
!= REG_SP
7784 /* Exempt STG/STZG/ST2G/STZ2G. */
7785 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7786 && opnds
[1].addr
.writeback
)
7787 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7791 case ldstnapair_offs
:
7792 case ldstpair_indexed
:
7793 /* Loading/storing the base register is unpredictable if writeback. */
7794 if ((aarch64_get_operand_class (opnds
[0].type
)
7795 == AARCH64_OPND_CLASS_INT_REG
)
7796 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7797 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7798 && opnds
[2].addr
.base_regno
!= REG_SP
7800 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7801 && opnds
[2].addr
.writeback
)
7802 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7803 /* Load operations must load different registers. */
7804 if ((opcode
->opcode
& (1 << 22))
7805 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7806 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7810 if ((aarch64_get_operand_class (opnds
[0].type
)
7811 == AARCH64_OPND_CLASS_INT_REG
)
7812 && (aarch64_get_operand_class (opnds
[1].type
)
7813 == AARCH64_OPND_CLASS_INT_REG
))
7815 if ((opcode
->opcode
& (1 << 22)))
7817 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7818 if ((opcode
->opcode
& (1 << 21))
7819 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7820 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7824 /* Store-Exclusive is unpredictable if Rt == Rs. */
7825 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7827 (_("unpredictable: identical transfer and status registers"
7830 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7832 if (!(opcode
->opcode
& (1 << 21)))
7833 /* Store-Exclusive is unpredictable if Rn == Rs. */
7835 (_("unpredictable: identical base and status registers"
7838 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7840 (_("unpredictable: "
7841 "identical transfer and status registers"
7845 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7846 if ((opcode
->opcode
& (1 << 21))
7847 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7848 && opnds
[3].reg
.regno
!= REG_SP
)
7849 as_warn (_("unpredictable: identical base and status registers"
7861 force_automatic_sequence_close (void)
7863 struct aarch64_segment_info_type
*tc_seg_info
;
7865 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7866 if (tc_seg_info
->insn_sequence
.instr
)
7868 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7869 _("previous `%s' sequence has not been closed"),
7870 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7871 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7875 /* A wrapper function to interface with libopcodes on encoding and
7876 record the error message if there is any.
7878 Return TRUE on success; otherwise return FALSE. */
7881 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7884 aarch64_operand_error error_info
;
7885 memset (&error_info
, '\0', sizeof (error_info
));
7886 error_info
.kind
= AARCH64_OPDE_NIL
;
7887 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7888 && !error_info
.non_fatal
)
7891 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7892 record_operand_error_info (opcode
, &error_info
);
7893 return error_info
.non_fatal
;
7896 #ifdef DEBUG_AARCH64
7898 dump_opcode_operands (const aarch64_opcode
*opcode
)
7901 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7903 aarch64_verbose ("\t\t opnd%d: %s", i
,
7904 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7905 ? aarch64_get_operand_name (opcode
->operands
[i
])
7906 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7910 #endif /* DEBUG_AARCH64 */
7912 /* This is the guts of the machine-dependent assembler. STR points to a
7913 machine dependent instruction. This function is supposed to emit
7914 the frags/bytes it assembles to. */
7917 md_assemble (char *str
)
7919 templates
*template;
7920 const aarch64_opcode
*opcode
;
7921 struct aarch64_segment_info_type
*tc_seg_info
;
7922 aarch64_inst
*inst_base
;
7923 unsigned saved_cond
;
7925 /* Align the previous label if needed. */
7926 if (last_label_seen
!= NULL
)
7928 symbol_set_frag (last_label_seen
, frag_now
);
7929 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7930 S_SET_SEGMENT (last_label_seen
, now_seg
);
7933 /* Update the current insn_sequence from the segment. */
7934 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7935 insn_sequence
= &tc_seg_info
->insn_sequence
;
7936 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7938 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7940 DEBUG_TRACE ("\n\n");
7941 DEBUG_TRACE ("==============================");
7942 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7944 /* Scan up to the end of the mnemonic, which must end in whitespace,
7945 '.', or end of string. */
7948 for (; is_part_of_name (*p
); p
++)
7949 if (*p
== '.' && !dot
)
7954 as_bad (_("unknown mnemonic -- `%s'"), str
);
7958 if (!dot
&& create_register_alias (str
, p
))
7961 template = opcode_lookup (str
, dot
, p
);
7964 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7969 skip_whitespace (p
);
7972 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7973 get_mnemonic_name (str
), str
);
7977 init_operand_error_report ();
7979 /* Sections are assumed to start aligned. In executable section, there is no
7980 MAP_DATA symbol pending. So we only align the address during
7981 MAP_DATA --> MAP_INSN transition.
7982 For other sections, this is not guaranteed. */
7983 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7984 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7985 frag_align_code (2, 0);
7987 saved_cond
= inst
.cond
;
7988 reset_aarch64_instruction (&inst
);
7989 inst
.cond
= saved_cond
;
7991 /* Iterate through all opcode entries with the same mnemonic name. */
7994 opcode
= template->opcode
;
7996 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7997 #ifdef DEBUG_AARCH64
7999 dump_opcode_operands (opcode
);
8000 #endif /* DEBUG_AARCH64 */
8002 mapping_state (MAP_INSN
);
8004 inst_base
= &inst
.base
;
8005 inst_base
->opcode
= opcode
;
8007 /* Truly conditionally executed instructions, e.g. b.cond. */
8008 if (opcode
->flags
& F_COND
)
8010 gas_assert (inst
.cond
!= COND_ALWAYS
);
8011 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8012 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8014 else if (inst
.cond
!= COND_ALWAYS
)
8016 /* It shouldn't arrive here, where the assembly looks like a
8017 conditional instruction but the found opcode is unconditional. */
8022 if (parse_operands (p
, opcode
)
8023 && programmer_friendly_fixup (&inst
)
8024 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8026 /* Check that this instruction is supported for this CPU. */
8027 if (!opcode
->avariant
8028 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8030 as_bad (_("selected processor does not support `%s'"), str
);
8034 warn_unpredictable_ldst (&inst
, str
);
8036 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8037 || !inst
.reloc
.need_libopcodes_p
)
8041 /* If there is relocation generated for the instruction,
8042 store the instruction information for the future fix-up. */
8043 struct aarch64_inst
*copy
;
8044 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8045 copy
= XNEW (struct aarch64_inst
);
8046 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8050 /* Issue non-fatal messages if any. */
8051 output_operand_error_report (str
, true);
8055 template = template->next
;
8056 if (template != NULL
)
8058 reset_aarch64_instruction (&inst
);
8059 inst
.cond
= saved_cond
;
8062 while (template != NULL
);
8064 /* Issue the error messages if any. */
8065 output_operand_error_report (str
, false);
8068 /* Various frobbings of labels and their addresses. */
8071 aarch64_start_line_hook (void)
8073 last_label_seen
= NULL
;
8077 aarch64_frob_label (symbolS
* sym
)
8079 last_label_seen
= sym
;
8081 dwarf2_emit_label (sym
);
8085 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8087 /* Check to see if we have a block to close. */
8088 force_automatic_sequence_close ();
8092 aarch64_data_in_code (void)
8094 if (startswith (input_line_pointer
+ 1, "data:"))
8096 *input_line_pointer
= '/';
8097 input_line_pointer
+= 5;
8098 *input_line_pointer
= 0;
8106 aarch64_canonicalize_symbol_name (char *name
)
8110 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8111 *(name
+ len
- 5) = 0;
8116 /* Table of all register names defined by default. The user can
8117 define additional names with .req. Note that all register names
8118 should appear in both upper and lowercase variants. Some registers
8119 also have mixed-case names. */
8121 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8122 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8123 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8124 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8125 #define REGSET16(p,t) \
8126 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8127 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8128 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8129 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8130 #define REGSET16S(p,s,t) \
8131 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8132 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8133 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8134 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8135 #define REGSET31(p,t) \
8137 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8138 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8139 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8140 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8141 #define REGSET(p,t) \
8142 REGSET31(p,t), REGNUM(p,31,t)
8144 /* These go into aarch64_reg_hsh hash-table. */
8145 static const reg_entry reg_names
[] = {
8146 /* Integer registers. */
8147 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8148 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8150 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8151 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8152 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8153 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8154 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8155 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8157 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8158 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8160 /* Floating-point single precision registers. */
8161 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8163 /* Floating-point double precision registers. */
8164 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8166 /* Floating-point half precision registers. */
8167 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8169 /* Floating-point byte precision registers. */
8170 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8172 /* Floating-point quad precision registers. */
8173 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8175 /* FP/SIMD registers. */
8176 REGSET (v
, VN
), REGSET (V
, VN
),
8178 /* SVE vector registers. */
8179 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8181 /* SVE predicate registers. */
8182 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8184 /* SME ZA tile registers. */
8185 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8187 /* SME ZA tile registers (horizontal slice). */
8188 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8190 /* SME ZA tile registers (vertical slice). */
8191 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8209 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8210 static const asm_nzcv nzcv_names
[] = {
8211 {"nzcv", B (n
, z
, c
, v
)},
8212 {"nzcV", B (n
, z
, c
, V
)},
8213 {"nzCv", B (n
, z
, C
, v
)},
8214 {"nzCV", B (n
, z
, C
, V
)},
8215 {"nZcv", B (n
, Z
, c
, v
)},
8216 {"nZcV", B (n
, Z
, c
, V
)},
8217 {"nZCv", B (n
, Z
, C
, v
)},
8218 {"nZCV", B (n
, Z
, C
, V
)},
8219 {"Nzcv", B (N
, z
, c
, v
)},
8220 {"NzcV", B (N
, z
, c
, V
)},
8221 {"NzCv", B (N
, z
, C
, v
)},
8222 {"NzCV", B (N
, z
, C
, V
)},
8223 {"NZcv", B (N
, Z
, c
, v
)},
8224 {"NZcV", B (N
, Z
, c
, V
)},
8225 {"NZCv", B (N
, Z
, C
, v
)},
8226 {"NZCV", B (N
, Z
, C
, V
)}
8239 /* MD interface: bits in the object file. */
8241 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8242 for use in the a.out file, and stores them in the array pointed to by buf.
8243 This knows about the endian-ness of the target machine and does
8244 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8245 2 (short) and 4 (long) Floating numbers are put out as a series of
8246 LITTLENUMS (shorts, here at least). */
8249 md_number_to_chars (char *buf
, valueT val
, int n
)
8251 if (target_big_endian
)
8252 number_to_chars_bigendian (buf
, val
, n
);
8254 number_to_chars_littleendian (buf
, val
, n
);
8257 /* MD interface: Sections. */
8259 /* Estimate the size of a frag before relaxing. Assume everything fits in
8263 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8269 /* Round up a section size to the appropriate boundary. */
8272 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8277 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8278 of an rs_align_code fragment.
8280 Here we fill the frag with the appropriate info for padding the
8281 output stream. The resulting frag will consist of a fixed (fr_fix)
8282 and of a repeating (fr_var) part.
8284 The fixed content is always emitted before the repeating content and
8285 these two parts are used as follows in constructing the output:
8286 - the fixed part will be used to align to a valid instruction word
8287 boundary, in case that we start at a misaligned address; as no
8288 executable instruction can live at the misaligned location, we
8289 simply fill with zeros;
8290 - the variable part will be used to cover the remaining padding and
8291 we fill using the AArch64 NOP instruction.
8293 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8294 enough storage space for up to 3 bytes for padding the back to a valid
8295 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8298 aarch64_handle_align (fragS
* fragP
)
8300 /* NOP = d503201f */
8301 /* AArch64 instructions are always little-endian. */
8302 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8304 int bytes
, fix
, noop_size
;
8307 if (fragP
->fr_type
!= rs_align_code
)
8310 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8311 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8314 gas_assert (fragP
->tc_frag_data
.recorded
);
8317 noop_size
= sizeof (aarch64_noop
);
8319 fix
= bytes
& (noop_size
- 1);
8322 #if defined OBJ_ELF || defined OBJ_COFF
8323 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8327 fragP
->fr_fix
+= fix
;
8331 memcpy (p
, aarch64_noop
, noop_size
);
8332 fragP
->fr_var
= noop_size
;
8335 /* Perform target specific initialisation of a frag.
8336 Note - despite the name this initialisation is not done when the frag
8337 is created, but only when its type is assigned. A frag can be created
8338 and used a long time before its type is set, so beware of assuming that
8339 this initialisation is performed first. */
8343 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8344 int max_chars ATTRIBUTE_UNUSED
)
8348 #else /* OBJ_ELF is defined. */
8350 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8352 /* Record a mapping symbol for alignment frags. We will delete this
8353 later if the alignment ends up empty. */
8354 if (!fragP
->tc_frag_data
.recorded
)
8355 fragP
->tc_frag_data
.recorded
= 1;
8357 /* PR 21809: Do not set a mapping state for debug sections
8358 - it just confuses other tools. */
8359 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8362 switch (fragP
->fr_type
)
8366 mapping_state_2 (MAP_DATA
, max_chars
);
8369 /* PR 20364: We can get alignment frags in code sections,
8370 so do not just assume that we should use the MAP_DATA state. */
8371 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8374 mapping_state_2 (MAP_INSN
, max_chars
);
8381 /* Whether SFrame stack trace info is supported. */
8384 aarch64_support_sframe_p (void)
8386 /* At this time, SFrame is supported for aarch64 only. */
8387 return (aarch64_abi
== AARCH64_ABI_LP64
);
8390 /* Specify if RA tracking is needed. */
8393 aarch64_sframe_ra_tracking_p (void)
8398 /* Specify the fixed offset to recover RA from CFA.
8399 (useful only when RA tracking is not needed). */
8402 aarch64_sframe_cfa_ra_offset (void)
8404 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8407 /* Get the abi/arch indentifier for SFrame. */
8410 aarch64_sframe_get_abi_arch (void)
8412 unsigned char sframe_abi_arch
= 0;
8414 if (aarch64_support_sframe_p ())
8416 sframe_abi_arch
= target_big_endian
8417 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8418 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8421 return sframe_abi_arch
;
8424 #endif /* OBJ_ELF */
8426 /* Initialize the DWARF-2 unwind information for this procedure. */
8429 tc_aarch64_frame_initial_instructions (void)
8431 cfi_add_CFA_def_cfa (REG_SP
, 0);
8434 /* Convert REGNAME to a DWARF-2 register number. */
8437 tc_aarch64_regname_to_dw2regnum (char *regname
)
8439 const reg_entry
*reg
= parse_reg (®name
);
8445 case REG_TYPE_SP_32
:
8446 case REG_TYPE_SP_64
:
8456 return reg
->number
+ 64;
8464 /* Implement DWARF2_ADDR_SIZE. */
8467 aarch64_dwarf2_addr_size (void)
8473 return bfd_arch_bits_per_address (stdoutput
) / 8;
8476 /* MD interface: Symbol and relocation handling. */
8478 /* Return the address within the segment that a PC-relative fixup is
8479 relative to. For AArch64 PC-relative fixups applied to instructions
8480 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8483 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8485 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8487 /* If this is pc-relative and we are going to emit a relocation
8488 then we just want to put out any pipeline compensation that the linker
8489 will need. Otherwise we want to use the calculated base. */
8491 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8492 || aarch64_force_relocation (fixP
)))
8495 /* AArch64 should be consistent for all pc-relative relocations. */
8496 return base
+ AARCH64_PCREL_OFFSET
;
8499 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8500 Otherwise we have no need to default values of symbols. */
8503 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8506 if (name
[0] == '_' && name
[1] == 'G'
8507 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8511 if (symbol_find (name
))
8512 as_bad (_("GOT already in the symbol table"));
8514 GOT_symbol
= symbol_new (name
, undefined_section
,
8515 &zero_address_frag
, 0);
8525 /* Return non-zero if the indicated VALUE has overflowed the maximum
8526 range expressible by a unsigned number with the indicated number of
8530 unsigned_overflow (valueT value
, unsigned bits
)
8533 if (bits
>= sizeof (valueT
) * 8)
8535 lim
= (valueT
) 1 << bits
;
8536 return (value
>= lim
);
8540 /* Return non-zero if the indicated VALUE has overflowed the maximum
8541 range expressible by an signed number with the indicated number of
8545 signed_overflow (offsetT value
, unsigned bits
)
8548 if (bits
>= sizeof (offsetT
) * 8)
8550 lim
= (offsetT
) 1 << (bits
- 1);
8551 return (value
< -lim
|| value
>= lim
);
8554 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8555 unsigned immediate offset load/store instruction, try to encode it as
8556 an unscaled, 9-bit, signed immediate offset load/store instruction.
8557 Return TRUE if it is successful; otherwise return FALSE.
8559 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8560 in response to the standard LDR/STR mnemonics when the immediate offset is
8561 unambiguous, i.e. when it is negative or unaligned. */
8564 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8567 enum aarch64_op new_op
;
8568 const aarch64_opcode
*new_opcode
;
8570 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8572 switch (instr
->opcode
->op
)
8574 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8575 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8576 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8577 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8578 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8579 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8580 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8581 case OP_STR_POS
: new_op
= OP_STUR
; break;
8582 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8583 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8584 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8585 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8586 default: new_op
= OP_NIL
; break;
8589 if (new_op
== OP_NIL
)
8592 new_opcode
= aarch64_get_opcode (new_op
);
8593 gas_assert (new_opcode
!= NULL
);
8595 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8596 instr
->opcode
->op
, new_opcode
->op
);
8598 aarch64_replace_opcode (instr
, new_opcode
);
8600 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8601 qualifier matching may fail because the out-of-date qualifier will
8602 prevent the operand being updated with a new and correct qualifier. */
8603 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8604 AARCH64_OPND_ADDR_SIMM9
);
8605 gas_assert (idx
== 1);
8606 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8608 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8610 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8617 /* Called by fix_insn to fix a MOV immediate alias instruction.
8619 Operand for a generic move immediate instruction, which is an alias
8620 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8621 a 32-bit/64-bit immediate value into general register. An assembler error
8622 shall result if the immediate cannot be created by a single one of these
8623 instructions. If there is a choice, then to ensure reversability an
8624 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8627 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8629 const aarch64_opcode
*opcode
;
8631 /* Need to check if the destination is SP/ZR. The check has to be done
8632 before any aarch64_replace_opcode. */
8633 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8634 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8636 instr
->operands
[1].imm
.value
= value
;
8637 instr
->operands
[1].skip
= 0;
8641 /* Try the MOVZ alias. */
8642 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8643 aarch64_replace_opcode (instr
, opcode
);
8644 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8645 &instr
->value
, NULL
, NULL
, insn_sequence
))
8647 put_aarch64_insn (buf
, instr
->value
);
8650 /* Try the MOVK alias. */
8651 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8652 aarch64_replace_opcode (instr
, opcode
);
8653 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8654 &instr
->value
, NULL
, NULL
, insn_sequence
))
8656 put_aarch64_insn (buf
, instr
->value
);
8661 if (try_mov_bitmask_p
)
8663 /* Try the ORR alias. */
8664 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8665 aarch64_replace_opcode (instr
, opcode
);
8666 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8667 &instr
->value
, NULL
, NULL
, insn_sequence
))
8669 put_aarch64_insn (buf
, instr
->value
);
8674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8675 _("immediate cannot be moved by a single instruction"));
8678 /* An instruction operand which is immediate related may have symbol used
8679 in the assembly, e.g.
8682 .set u32, 0x00ffff00
8684 At the time when the assembly instruction is parsed, a referenced symbol,
8685 like 'u32' in the above example may not have been seen; a fixS is created
8686 in such a case and is handled here after symbols have been resolved.
8687 Instruction is fixed up with VALUE using the information in *FIXP plus
8688 extra information in FLAGS.
8690 This function is called by md_apply_fix to fix up instructions that need
8691 a fix-up described above but does not involve any linker-time relocation. */
8694 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8698 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8699 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8700 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8704 /* Now the instruction is about to be fixed-up, so the operand that
8705 was previously marked as 'ignored' needs to be unmarked in order
8706 to get the encoding done properly. */
8707 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8708 new_inst
->operands
[idx
].skip
= 0;
8711 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8715 case AARCH64_OPND_EXCEPTION
:
8716 case AARCH64_OPND_UNDEFINED
:
8717 if (unsigned_overflow (value
, 16))
8718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8719 _("immediate out of range"));
8720 insn
= get_aarch64_insn (buf
);
8721 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8722 put_aarch64_insn (buf
, insn
);
8725 case AARCH64_OPND_AIMM
:
8726 /* ADD or SUB with immediate.
8727 NOTE this assumes we come here with a add/sub shifted reg encoding
8728 3 322|2222|2 2 2 21111 111111
8729 1 098|7654|3 2 1 09876 543210 98765 43210
8730 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8731 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8732 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8733 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8735 3 322|2222|2 2 221111111111
8736 1 098|7654|3 2 109876543210 98765 43210
8737 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8738 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8739 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8740 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8741 Fields sf Rn Rd are already set. */
8742 insn
= get_aarch64_insn (buf
);
8746 insn
= reencode_addsub_switch_add_sub (insn
);
8750 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8751 && unsigned_overflow (value
, 12))
8753 /* Try to shift the value by 12 to make it fit. */
8754 if (((value
>> 12) << 12) == value
8755 && ! unsigned_overflow (value
, 12 + 12))
8758 insn
|= encode_addsub_imm_shift_amount (1);
8762 if (unsigned_overflow (value
, 12))
8763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8764 _("immediate out of range"));
8766 insn
|= encode_addsub_imm (value
);
8768 put_aarch64_insn (buf
, insn
);
8771 case AARCH64_OPND_SIMD_IMM
:
8772 case AARCH64_OPND_SIMD_IMM_SFT
:
8773 case AARCH64_OPND_LIMM
:
8774 /* Bit mask immediate. */
8775 gas_assert (new_inst
!= NULL
);
8776 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8777 new_inst
->operands
[idx
].imm
.value
= value
;
8778 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8779 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8780 put_aarch64_insn (buf
, new_inst
->value
);
8782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8783 _("invalid immediate"));
8786 case AARCH64_OPND_HALF
:
8787 /* 16-bit unsigned immediate. */
8788 if (unsigned_overflow (value
, 16))
8789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8790 _("immediate out of range"));
8791 insn
= get_aarch64_insn (buf
);
8792 insn
|= encode_movw_imm (value
& 0xffff);
8793 put_aarch64_insn (buf
, insn
);
8796 case AARCH64_OPND_IMM_MOV
:
8797 /* Operand for a generic move immediate instruction, which is
8798 an alias instruction that generates a single MOVZ, MOVN or ORR
8799 instruction to loads a 32-bit/64-bit immediate value into general
8800 register. An assembler error shall result if the immediate cannot be
8801 created by a single one of these instructions. If there is a choice,
8802 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8803 and MOVZ or MOVN to ORR. */
8804 gas_assert (new_inst
!= NULL
);
8805 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8808 case AARCH64_OPND_ADDR_SIMM7
:
8809 case AARCH64_OPND_ADDR_SIMM9
:
8810 case AARCH64_OPND_ADDR_SIMM9_2
:
8811 case AARCH64_OPND_ADDR_SIMM10
:
8812 case AARCH64_OPND_ADDR_UIMM12
:
8813 case AARCH64_OPND_ADDR_SIMM11
:
8814 case AARCH64_OPND_ADDR_SIMM13
:
8815 /* Immediate offset in an address. */
8816 insn
= get_aarch64_insn (buf
);
8818 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8819 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8820 || new_inst
->opcode
->operands
[2] == opnd
);
8822 /* Get the index of the address operand. */
8823 if (new_inst
->opcode
->operands
[1] == opnd
)
8824 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8827 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8830 /* Update the resolved offset value. */
8831 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8833 /* Encode/fix-up. */
8834 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8835 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8837 put_aarch64_insn (buf
, new_inst
->value
);
8840 else if (new_inst
->opcode
->iclass
== ldst_pos
8841 && try_to_encode_as_unscaled_ldst (new_inst
))
8843 put_aarch64_insn (buf
, new_inst
->value
);
8847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8848 _("immediate offset out of range"));
8853 as_fatal (_("unhandled operand code %d"), opnd
);
8857 /* Apply a fixup (fixP) to segment data, once it has been determined
8858 by our caller that we have all the info we need to fix it up.
8860 Parameter valP is the pointer to the value of the bits. */
8863 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8865 offsetT value
= *valP
;
8867 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8869 unsigned flags
= fixP
->fx_addnumber
;
8871 DEBUG_TRACE ("\n\n");
8872 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8873 DEBUG_TRACE ("Enter md_apply_fix");
8875 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8877 /* Note whether this will delete the relocation. */
8879 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8880 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8883 /* Process the relocations. */
8884 switch (fixP
->fx_r_type
)
8886 case BFD_RELOC_NONE
:
8887 /* This will need to go in the object file. */
8892 case BFD_RELOC_8_PCREL
:
8893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8894 md_number_to_chars (buf
, value
, 1);
8898 case BFD_RELOC_16_PCREL
:
8899 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8900 md_number_to_chars (buf
, value
, 2);
8904 case BFD_RELOC_32_PCREL
:
8905 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8906 md_number_to_chars (buf
, value
, 4);
8910 case BFD_RELOC_64_PCREL
:
8911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8912 md_number_to_chars (buf
, value
, 8);
8915 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8916 /* We claim that these fixups have been processed here, even if
8917 in fact we generate an error because we do not have a reloc
8918 for them, so tc_gen_reloc() will reject them. */
8920 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8923 _("undefined symbol %s used as an immediate value"),
8924 S_GET_NAME (fixP
->fx_addsy
));
8925 goto apply_fix_return
;
8927 fix_insn (fixP
, flags
, value
);
8930 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8935 _("pc-relative load offset not word aligned"));
8936 if (signed_overflow (value
, 21))
8937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8938 _("pc-relative load offset out of range"));
8939 insn
= get_aarch64_insn (buf
);
8940 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8941 put_aarch64_insn (buf
, insn
);
8945 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8946 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8948 if (signed_overflow (value
, 21))
8949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8950 _("pc-relative address offset out of range"));
8951 insn
= get_aarch64_insn (buf
);
8952 insn
|= encode_adr_imm (value
);
8953 put_aarch64_insn (buf
, insn
);
8957 case BFD_RELOC_AARCH64_BRANCH19
:
8958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8962 _("conditional branch target not word aligned"));
8963 if (signed_overflow (value
, 21))
8964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8965 _("conditional branch out of range"));
8966 insn
= get_aarch64_insn (buf
);
8967 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8968 put_aarch64_insn (buf
, insn
);
8972 case BFD_RELOC_AARCH64_TSTBR14
:
8973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8977 _("conditional branch target not word aligned"));
8978 if (signed_overflow (value
, 16))
8979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8980 _("conditional branch out of range"));
8981 insn
= get_aarch64_insn (buf
);
8982 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8983 put_aarch64_insn (buf
, insn
);
8987 case BFD_RELOC_AARCH64_CALL26
:
8988 case BFD_RELOC_AARCH64_JUMP26
:
8989 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8993 _("branch target not word aligned"));
8994 if (signed_overflow (value
, 28))
8995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8996 _("branch out of range"));
8997 insn
= get_aarch64_insn (buf
);
8998 insn
|= encode_branch_ofs_26 (value
>> 2);
8999 put_aarch64_insn (buf
, insn
);
9003 case BFD_RELOC_AARCH64_MOVW_G0
:
9004 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9005 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9006 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9007 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9008 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9011 case BFD_RELOC_AARCH64_MOVW_G1
:
9012 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9013 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9014 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9015 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9016 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9019 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9021 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9022 /* Should always be exported to object file, see
9023 aarch64_force_relocation(). */
9024 gas_assert (!fixP
->fx_done
);
9025 gas_assert (seg
->use_rela_p
);
9027 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9029 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9030 /* Should always be exported to object file, see
9031 aarch64_force_relocation(). */
9032 gas_assert (!fixP
->fx_done
);
9033 gas_assert (seg
->use_rela_p
);
9035 case BFD_RELOC_AARCH64_MOVW_G2
:
9036 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9037 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9038 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9039 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9042 case BFD_RELOC_AARCH64_MOVW_G3
:
9043 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9046 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9048 insn
= get_aarch64_insn (buf
);
9052 /* REL signed addend must fit in 16 bits */
9053 if (signed_overflow (value
, 16))
9054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9055 _("offset out of range"));
9059 /* Check for overflow and scale. */
9060 switch (fixP
->fx_r_type
)
9062 case BFD_RELOC_AARCH64_MOVW_G0
:
9063 case BFD_RELOC_AARCH64_MOVW_G1
:
9064 case BFD_RELOC_AARCH64_MOVW_G2
:
9065 case BFD_RELOC_AARCH64_MOVW_G3
:
9066 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9067 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9068 if (unsigned_overflow (value
, scale
+ 16))
9069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9070 _("unsigned value out of range"));
9072 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9073 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9074 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9075 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9076 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9077 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9078 /* NOTE: We can only come here with movz or movn. */
9079 if (signed_overflow (value
, scale
+ 16))
9080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9081 _("signed value out of range"));
9084 /* Force use of MOVN. */
9086 insn
= reencode_movzn_to_movn (insn
);
9090 /* Force use of MOVZ. */
9091 insn
= reencode_movzn_to_movz (insn
);
9095 /* Unchecked relocations. */
9101 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9102 insn
|= encode_movw_imm (value
& 0xffff);
9104 put_aarch64_insn (buf
, insn
);
9108 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9109 fixP
->fx_r_type
= (ilp32_p
9110 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9111 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9112 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9113 /* Should always be exported to object file, see
9114 aarch64_force_relocation(). */
9115 gas_assert (!fixP
->fx_done
);
9116 gas_assert (seg
->use_rela_p
);
9119 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9120 fixP
->fx_r_type
= (ilp32_p
9121 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9122 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9123 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9124 /* Should always be exported to object file, see
9125 aarch64_force_relocation(). */
9126 gas_assert (!fixP
->fx_done
);
9127 gas_assert (seg
->use_rela_p
);
9130 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9131 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9132 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9133 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9134 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9135 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9136 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9137 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9138 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9139 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9140 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9141 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9142 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9143 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9144 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9145 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9146 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9147 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9148 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9149 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9150 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9151 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9152 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9153 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9154 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9155 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9156 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9157 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9158 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9159 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9160 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9161 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9162 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9163 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9164 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9165 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9166 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9167 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9168 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9169 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9170 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9171 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9172 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9173 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9174 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9175 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9176 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9177 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9178 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9179 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9180 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9181 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9182 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9183 /* Should always be exported to object file, see
9184 aarch64_force_relocation(). */
9185 gas_assert (!fixP
->fx_done
);
9186 gas_assert (seg
->use_rela_p
);
9189 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9190 /* Should always be exported to object file, see
9191 aarch64_force_relocation(). */
9192 fixP
->fx_r_type
= (ilp32_p
9193 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9194 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9195 gas_assert (!fixP
->fx_done
);
9196 gas_assert (seg
->use_rela_p
);
9199 case BFD_RELOC_AARCH64_ADD_LO12
:
9200 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9201 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9202 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9203 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9204 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9205 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9206 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9207 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9208 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9209 case BFD_RELOC_AARCH64_LDST128_LO12
:
9210 case BFD_RELOC_AARCH64_LDST16_LO12
:
9211 case BFD_RELOC_AARCH64_LDST32_LO12
:
9212 case BFD_RELOC_AARCH64_LDST64_LO12
:
9213 case BFD_RELOC_AARCH64_LDST8_LO12
:
9214 /* Should always be exported to object file, see
9215 aarch64_force_relocation(). */
9216 gas_assert (!fixP
->fx_done
);
9217 gas_assert (seg
->use_rela_p
);
9220 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9221 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9222 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9225 case BFD_RELOC_UNUSED
:
9226 /* An error will already have been reported. */
9230 case BFD_RELOC_32_SECREL
:
9231 case BFD_RELOC_16_SECIDX
:
9235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9236 _("unexpected %s fixup"),
9237 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9242 /* Free the allocated the struct aarch64_inst.
9243 N.B. currently there are very limited number of fix-up types actually use
9244 this field, so the impact on the performance should be minimal . */
9245 free (fixP
->tc_fix_data
.inst
);
9250 /* Translate internal representation of relocation info to BFD target
9254 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9257 bfd_reloc_code_real_type code
;
9259 reloc
= XNEW (arelent
);
9261 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9262 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9263 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9267 if (section
->use_rela_p
)
9268 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9270 fixp
->fx_offset
= reloc
->address
;
9272 reloc
->addend
= fixp
->fx_offset
;
9274 code
= fixp
->fx_r_type
;
9279 code
= BFD_RELOC_16_PCREL
;
9284 code
= BFD_RELOC_32_PCREL
;
9289 code
= BFD_RELOC_64_PCREL
;
9296 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9297 if (reloc
->howto
== NULL
)
9299 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9301 ("cannot represent %s relocation in this object file format"),
9302 bfd_get_reloc_code_name (code
));
9309 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9312 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9314 bfd_reloc_code_real_type type
;
9318 if (exp
->X_op
== O_secrel
)
9320 exp
->X_op
= O_symbol
;
9321 type
= BFD_RELOC_32_SECREL
;
9323 else if (exp
->X_op
== O_secidx
)
9325 exp
->X_op
= O_symbol
;
9326 type
= BFD_RELOC_16_SECIDX
;
9332 FIXME: @@ Should look at CPU word size. */
9339 type
= BFD_RELOC_16
;
9342 type
= BFD_RELOC_32
;
9345 type
= BFD_RELOC_64
;
9348 as_bad (_("cannot do %u-byte relocation"), size
);
9349 type
= BFD_RELOC_UNUSED
;
9356 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9359 /* Implement md_after_parse_args. This is the earliest time we need to decide
9360 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9363 aarch64_after_parse_args (void)
9365 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9369 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9370 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9371 aarch64_abi
= AARCH64_ABI_ILP32
;
9373 aarch64_abi
= AARCH64_ABI_LP64
;
9375 aarch64_abi
= AARCH64_ABI_LLP64
;
9381 elf64_aarch64_target_format (void)
9384 /* FIXME: What to do for ilp32_p ? */
9385 if (target_big_endian
)
9386 return "elf64-bigaarch64-cloudabi";
9388 return "elf64-littleaarch64-cloudabi";
9390 if (target_big_endian
)
9391 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9393 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9398 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9400 elf_frob_symbol (symp
, puntp
);
9402 #elif defined OBJ_COFF
9404 coff_aarch64_target_format (void)
9406 return "pe-aarch64-little";
9410 /* MD interface: Finalization. */
9412 /* A good place to do this, although this was probably not intended
9413 for this kind of use. We need to dump the literal pool before
9414 references are made to a null symbol pointer. */
9417 aarch64_cleanup (void)
9421 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9423 /* Put it at the end of the relevant section. */
9424 subseg_set (pool
->section
, pool
->sub_section
);
9430 /* Remove any excess mapping symbols generated for alignment frags in
9431 SEC. We may have created a mapping symbol before a zero byte
9432 alignment; remove it if there's a mapping symbol after the
9435 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9436 void *dummy ATTRIBUTE_UNUSED
)
9438 segment_info_type
*seginfo
= seg_info (sec
);
9441 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9444 for (fragp
= seginfo
->frchainP
->frch_root
;
9445 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9447 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9448 fragS
*next
= fragp
->fr_next
;
9450 /* Variable-sized frags have been converted to fixed size by
9451 this point. But if this was variable-sized to start with,
9452 there will be a fixed-size frag after it. So don't handle
9454 if (sym
== NULL
|| next
== NULL
)
9457 if (S_GET_VALUE (sym
) < next
->fr_address
)
9458 /* Not at the end of this frag. */
9460 know (S_GET_VALUE (sym
) == next
->fr_address
);
9464 if (next
->tc_frag_data
.first_map
!= NULL
)
9466 /* Next frag starts with a mapping symbol. Discard this
9468 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9472 if (next
->fr_next
== NULL
)
9474 /* This mapping symbol is at the end of the section. Discard
9476 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9477 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9481 /* As long as we have empty frags without any mapping symbols,
9483 /* If the next frag is non-empty and does not start with a
9484 mapping symbol, then this mapping symbol is required. */
9485 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9488 next
= next
->fr_next
;
9490 while (next
!= NULL
);
9495 /* Adjust the symbol table. */
9498 aarch64_adjust_symtab (void)
9501 /* Remove any overlapping mapping symbols generated by alignment frags. */
9502 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9503 /* Now do generic ELF adjustments. */
9504 elf_adjust_symtab ();
9509 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9511 str_hash_insert (table
, key
, value
, 0);
9515 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9517 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9518 checked_hash_insert (table
, key
, value
);
9522 fill_instruction_hash_table (void)
9524 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9526 while (opcode
->name
!= NULL
)
9528 templates
*templ
, *new_templ
;
9529 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9531 new_templ
= XNEW (templates
);
9532 new_templ
->opcode
= opcode
;
9533 new_templ
->next
= NULL
;
9536 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9539 new_templ
->next
= templ
->next
;
9540 templ
->next
= new_templ
;
9547 convert_to_upper (char *dst
, const char *src
, size_t num
)
9550 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9551 *dst
= TOUPPER (*src
);
9555 /* Assume STR point to a lower-case string, allocate, convert and return
9556 the corresponding upper-case string. */
9557 static inline const char*
9558 get_upper_str (const char *str
)
9561 size_t len
= strlen (str
);
9562 ret
= XNEWVEC (char, len
+ 1);
9563 convert_to_upper (ret
, str
, len
);
9567 /* MD interface: Initialization. */
9575 aarch64_ops_hsh
= str_htab_create ();
9576 aarch64_cond_hsh
= str_htab_create ();
9577 aarch64_shift_hsh
= str_htab_create ();
9578 aarch64_sys_regs_hsh
= str_htab_create ();
9579 aarch64_pstatefield_hsh
= str_htab_create ();
9580 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9581 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9582 aarch64_sys_regs_at_hsh
= str_htab_create ();
9583 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9584 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9585 aarch64_reg_hsh
= str_htab_create ();
9586 aarch64_barrier_opt_hsh
= str_htab_create ();
9587 aarch64_nzcv_hsh
= str_htab_create ();
9588 aarch64_pldop_hsh
= str_htab_create ();
9589 aarch64_hint_opt_hsh
= str_htab_create ();
9591 fill_instruction_hash_table ();
9593 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9594 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9595 (void *) (aarch64_sys_regs
+ i
));
9597 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9598 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9599 aarch64_pstatefields
[i
].name
,
9600 (void *) (aarch64_pstatefields
+ i
));
9602 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9603 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9604 aarch64_sys_regs_ic
[i
].name
,
9605 (void *) (aarch64_sys_regs_ic
+ i
));
9607 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9608 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9609 aarch64_sys_regs_dc
[i
].name
,
9610 (void *) (aarch64_sys_regs_dc
+ i
));
9612 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9613 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9614 aarch64_sys_regs_at
[i
].name
,
9615 (void *) (aarch64_sys_regs_at
+ i
));
9617 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9618 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9619 aarch64_sys_regs_tlbi
[i
].name
,
9620 (void *) (aarch64_sys_regs_tlbi
+ i
));
9622 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9623 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9624 aarch64_sys_regs_sr
[i
].name
,
9625 (void *) (aarch64_sys_regs_sr
+ i
));
9627 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9628 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9629 (void *) (reg_names
+ i
));
9631 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9632 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9633 (void *) (nzcv_names
+ i
));
9635 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9637 const char *name
= aarch64_operand_modifiers
[i
].name
;
9638 checked_hash_insert (aarch64_shift_hsh
, name
,
9639 (void *) (aarch64_operand_modifiers
+ i
));
9640 /* Also hash the name in the upper case. */
9641 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9642 (void *) (aarch64_operand_modifiers
+ i
));
9645 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9648 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9649 the same condition code. */
9650 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9652 const char *name
= aarch64_conds
[i
].names
[j
];
9655 checked_hash_insert (aarch64_cond_hsh
, name
,
9656 (void *) (aarch64_conds
+ i
));
9657 /* Also hash the name in the upper case. */
9658 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9659 (void *) (aarch64_conds
+ i
));
9663 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9665 const char *name
= aarch64_barrier_options
[i
].name
;
9666 /* Skip xx00 - the unallocated values of option. */
9669 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9670 (void *) (aarch64_barrier_options
+ i
));
9671 /* Also hash the name in the upper case. */
9672 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9673 (void *) (aarch64_barrier_options
+ i
));
9676 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9678 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9679 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9680 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9681 /* Also hash the name in the upper case. */
9682 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9683 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9686 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9688 const char* name
= aarch64_prfops
[i
].name
;
9689 /* Skip the unallocated hint encodings. */
9692 checked_hash_insert (aarch64_pldop_hsh
, name
,
9693 (void *) (aarch64_prfops
+ i
));
9694 /* Also hash the name in the upper case. */
9695 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9696 (void *) (aarch64_prfops
+ i
));
9699 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9701 const char* name
= aarch64_hint_options
[i
].name
;
9702 const char* upper_name
= get_upper_str(name
);
9704 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9705 (void *) (aarch64_hint_options
+ i
));
9707 /* Also hash the name in the upper case if not the same. */
9708 if (strcmp (name
, upper_name
) != 0)
9709 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9710 (void *) (aarch64_hint_options
+ i
));
9713 /* Set the cpu variant based on the command-line options. */
9715 mcpu_cpu_opt
= march_cpu_opt
;
9718 mcpu_cpu_opt
= &cpu_default
;
9720 cpu_variant
= *mcpu_cpu_opt
;
9722 /* Record the CPU type. */
9724 mach
= bfd_mach_aarch64_ilp32
;
9726 mach
= bfd_mach_aarch64_llp64
;
9728 mach
= bfd_mach_aarch64
;
9730 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9732 /* FIXME - is there a better way to do it ? */
9733 aarch64_sframe_cfa_sp_reg
= 31;
9734 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9735 aarch64_sframe_cfa_ra_reg
= 30;
9739 /* Command line processing. */
9741 const char *md_shortopts
= "m:";
9743 #ifdef AARCH64_BI_ENDIAN
9744 #define OPTION_EB (OPTION_MD_BASE + 0)
9745 #define OPTION_EL (OPTION_MD_BASE + 1)
9747 #if TARGET_BYTES_BIG_ENDIAN
9748 #define OPTION_EB (OPTION_MD_BASE + 0)
9750 #define OPTION_EL (OPTION_MD_BASE + 1)
9754 struct option md_longopts
[] = {
9756 {"EB", no_argument
, NULL
, OPTION_EB
},
9759 {"EL", no_argument
, NULL
, OPTION_EL
},
9761 {NULL
, no_argument
, NULL
, 0}
9764 size_t md_longopts_size
= sizeof (md_longopts
);
9766 struct aarch64_option_table
9768 const char *option
; /* Option name to match. */
9769 const char *help
; /* Help information. */
9770 int *var
; /* Variable to change. */
9771 int value
; /* What to change it to. */
9772 char *deprecated
; /* If non-null, print this message. */
9775 static struct aarch64_option_table aarch64_opts
[] = {
9776 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9777 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9779 #ifdef DEBUG_AARCH64
9780 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9781 #endif /* DEBUG_AARCH64 */
9782 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9784 {"mno-verbose-error", N_("do not output verbose error messages"),
9785 &verbose_error_p
, 0, NULL
},
9786 {NULL
, NULL
, NULL
, 0, NULL
}
9789 struct aarch64_cpu_option_table
9792 const aarch64_feature_set value
;
9793 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9795 const char *canonical_name
;
9798 /* This list should, at a minimum, contain all the cpu names
9799 recognized by GCC. */
9800 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9801 {"all", AARCH64_ANY
, NULL
},
9802 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9803 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9804 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9805 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9806 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9807 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9808 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9809 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9810 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9811 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9812 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9813 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9814 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9815 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9817 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9818 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9820 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9821 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9823 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9824 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9825 | AARCH64_FEATURE_DOTPROD
9826 | AARCH64_FEATURE_SSBS
),
9828 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9829 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9830 | AARCH64_FEATURE_DOTPROD
9831 | AARCH64_FEATURE_SSBS
),
9833 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9834 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9835 | AARCH64_FEATURE_DOTPROD
9836 | AARCH64_FEATURE_SSBS
),
9838 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9839 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9840 | AARCH64_FEATURE_DOTPROD
9841 | AARCH64_FEATURE_SSBS
),
9843 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9845 | AARCH64_FEATURE_RCPC
9846 | AARCH64_FEATURE_DOTPROD
9847 | AARCH64_FEATURE_SSBS
9848 | AARCH64_FEATURE_PROFILE
),
9850 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9852 | AARCH64_FEATURE_RCPC
9853 | AARCH64_FEATURE_DOTPROD
9854 | AARCH64_FEATURE_SSBS
9855 | AARCH64_FEATURE_PROFILE
),
9857 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9858 AARCH64_FEATURE_DOTPROD
9859 | AARCH64_FEATURE_F16
9860 | AARCH64_FEATURE_FLAGM
9861 | AARCH64_FEATURE_PAC
9862 | AARCH64_FEATURE_PROFILE
9863 | AARCH64_FEATURE_RCPC
9864 | AARCH64_FEATURE_SSBS
),
9866 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9867 AARCH64_FEATURE_BFLOAT16
9868 | AARCH64_FEATURE_I8MM
9869 | AARCH64_FEATURE_MEMTAG
9870 | AARCH64_FEATURE_SVE2_BITPERM
),
9872 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9873 AARCH64_FEATURE_BFLOAT16
9874 | AARCH64_FEATURE_I8MM
9875 | AARCH64_FEATURE_MEMTAG
9876 | AARCH64_FEATURE_SVE2_BITPERM
),
9878 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9879 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9880 | AARCH64_FEATURE_DOTPROD
9881 | AARCH64_FEATURE_PROFILE
),
9883 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9884 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9885 "Samsung Exynos M1"},
9886 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9887 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9888 | AARCH64_FEATURE_RDMA
),
9890 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9891 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9892 | AARCH64_FEATURE_DOTPROD
9893 | AARCH64_FEATURE_SSBS
),
9895 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9896 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9897 | AARCH64_FEATURE_DOTPROD
9898 | AARCH64_FEATURE_PROFILE
),
9900 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9901 AARCH64_FEATURE_BFLOAT16
9902 | AARCH64_FEATURE_I8MM
9903 | AARCH64_FEATURE_F16
9904 | AARCH64_FEATURE_SVE
9905 | AARCH64_FEATURE_SVE2
9906 | AARCH64_FEATURE_SVE2_BITPERM
9907 | AARCH64_FEATURE_MEMTAG
9908 | AARCH64_FEATURE_RNG
),
9910 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9911 AARCH64_FEATURE_PROFILE
9912 | AARCH64_FEATURE_CVADP
9913 | AARCH64_FEATURE_SVE
9914 | AARCH64_FEATURE_SSBS
9915 | AARCH64_FEATURE_RNG
9916 | AARCH64_FEATURE_F16
9917 | AARCH64_FEATURE_BFLOAT16
9918 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9919 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9920 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9921 | AARCH64_FEATURE_RDMA
),
9922 "Qualcomm QDF24XX"},
9923 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9924 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9925 "Qualcomm Saphira"},
9926 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9927 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9929 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9930 AARCH64_FEATURE_CRYPTO
),
9932 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9933 in earlier releases and is superseded by 'xgene1' in all
9935 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9936 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9937 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9938 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9939 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9940 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9942 | AARCH64_FEATURE_RCPC
9943 | AARCH64_FEATURE_DOTPROD
9944 | AARCH64_FEATURE_SSBS
9945 | AARCH64_FEATURE_PROFILE
),
9947 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9948 AARCH64_FEATURE_BFLOAT16
9949 | AARCH64_FEATURE_I8MM
9950 | AARCH64_FEATURE_MEMTAG
9951 | AARCH64_FEATURE_SVE2_BITPERM
),
9953 {"generic", AARCH64_ARCH_V8
, NULL
},
9955 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9958 struct aarch64_arch_option_table
9961 const aarch64_feature_set value
;
9964 /* This list should, at a minimum, contain all the architecture names
9965 recognized by GCC. */
9966 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9967 {"all", AARCH64_ANY
},
9968 {"armv8-a", AARCH64_ARCH_V8
},
9969 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9970 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9971 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9972 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9973 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9974 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9975 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9976 {"armv8.8-a", AARCH64_ARCH_V8_8
},
9977 {"armv8-r", AARCH64_ARCH_V8_R
},
9978 {"armv9-a", AARCH64_ARCH_V9
},
9979 {"armv9.1-a", AARCH64_ARCH_V9_1
},
9980 {"armv9.2-a", AARCH64_ARCH_V9_2
},
9981 {"armv9.3-a", AARCH64_ARCH_V9_3
},
9982 {NULL
, AARCH64_ARCH_NONE
}
9985 /* ISA extensions. */
9986 struct aarch64_option_cpu_value_table
9989 const aarch64_feature_set value
;
9990 const aarch64_feature_set require
; /* Feature dependencies. */
9993 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9994 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9996 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9997 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9998 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10000 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10001 AARCH64_ARCH_NONE
},
10002 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10003 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10004 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10005 AARCH64_ARCH_NONE
},
10006 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10007 AARCH64_ARCH_NONE
},
10008 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10009 AARCH64_ARCH_NONE
},
10010 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10011 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10012 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10013 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10014 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10015 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10016 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10017 AARCH64_ARCH_NONE
},
10018 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10019 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10020 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10021 AARCH64_ARCH_NONE
},
10022 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10023 AARCH64_FEATURE (AARCH64_FEATURE_F16
10024 | AARCH64_FEATURE_SIMD
, 0)},
10025 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10026 AARCH64_ARCH_NONE
},
10027 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10028 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10029 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10030 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10031 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10032 AARCH64_ARCH_NONE
},
10033 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10034 AARCH64_ARCH_NONE
},
10035 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10036 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10037 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10038 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10039 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10040 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10041 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10042 AARCH64_ARCH_NONE
},
10043 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10044 AARCH64_ARCH_NONE
},
10045 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10046 AARCH64_ARCH_NONE
},
10047 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10048 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10049 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10050 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10051 | AARCH64_FEATURE_SM4
, 0)},
10052 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10053 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10054 | AARCH64_FEATURE_AES
, 0)},
10055 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10056 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10057 | AARCH64_FEATURE_SHA3
, 0)},
10058 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10059 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10060 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10061 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10062 | AARCH64_FEATURE_BFLOAT16
, 0)},
10063 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10064 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10065 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10066 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10067 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10068 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10069 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10070 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10071 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10072 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10073 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10074 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10075 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10076 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10077 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10078 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10079 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10080 AARCH64_ARCH_NONE
},
10081 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10082 AARCH64_ARCH_NONE
},
10083 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10084 AARCH64_ARCH_NONE
},
10085 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10086 AARCH64_ARCH_NONE
},
10087 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10088 AARCH64_ARCH_NONE
},
10089 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10090 AARCH64_ARCH_NONE
},
10091 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10094 struct aarch64_long_option_table
10096 const char *option
; /* Substring to match. */
10097 const char *help
; /* Help information. */
10098 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10099 char *deprecated
; /* If non-null, print this message. */
10102 /* Transitive closure of features depending on set. */
10103 static aarch64_feature_set
10104 aarch64_feature_disable_set (aarch64_feature_set set
)
10106 const struct aarch64_option_cpu_value_table
*opt
;
10107 aarch64_feature_set prev
= 0;
10109 while (prev
!= set
) {
10111 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10112 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10113 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10118 /* Transitive closure of dependencies of set. */
10119 static aarch64_feature_set
10120 aarch64_feature_enable_set (aarch64_feature_set set
)
10122 const struct aarch64_option_cpu_value_table
*opt
;
10123 aarch64_feature_set prev
= 0;
10125 while (prev
!= set
) {
10127 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10128 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10129 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10135 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10138 /* We insist on extensions being added before being removed. We achieve
10139 this by using the ADDING_VALUE variable to indicate whether we are
10140 adding an extension (1) or removing it (0) and only allowing it to
10141 change in the order -1 -> 1 -> 0. */
10142 int adding_value
= -1;
10143 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10145 /* Copy the feature set, so that we can modify it. */
10146 *ext_set
= **opt_p
;
10149 while (str
!= NULL
&& *str
!= 0)
10151 const struct aarch64_option_cpu_value_table
*opt
;
10152 const char *ext
= NULL
;
10159 as_bad (_("invalid architectural extension"));
10163 ext
= strchr (++str
, '+');
10167 optlen
= ext
- str
;
10169 optlen
= strlen (str
);
10171 if (optlen
>= 2 && startswith (str
, "no"))
10173 if (adding_value
!= 0)
10178 else if (optlen
> 0)
10180 if (adding_value
== -1)
10182 else if (adding_value
!= 1)
10184 as_bad (_("must specify extensions to add before specifying "
10185 "those to remove"));
10192 as_bad (_("missing architectural extension"));
10196 gas_assert (adding_value
!= -1);
10198 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10199 if (strncmp (opt
->name
, str
, optlen
) == 0)
10201 aarch64_feature_set set
;
10203 /* Add or remove the extension. */
10206 set
= aarch64_feature_enable_set (opt
->value
);
10207 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10211 set
= aarch64_feature_disable_set (opt
->value
);
10212 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10217 if (opt
->name
== NULL
)
10219 as_bad (_("unknown architectural extension `%s'"), str
);
10230 aarch64_parse_cpu (const char *str
)
10232 const struct aarch64_cpu_option_table
*opt
;
10233 const char *ext
= strchr (str
, '+');
10237 optlen
= ext
- str
;
10239 optlen
= strlen (str
);
10243 as_bad (_("missing cpu name `%s'"), str
);
10247 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10248 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10250 mcpu_cpu_opt
= &opt
->value
;
10252 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10257 as_bad (_("unknown cpu `%s'"), str
);
10262 aarch64_parse_arch (const char *str
)
10264 const struct aarch64_arch_option_table
*opt
;
10265 const char *ext
= strchr (str
, '+');
10269 optlen
= ext
- str
;
10271 optlen
= strlen (str
);
10275 as_bad (_("missing architecture name `%s'"), str
);
10279 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10280 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10282 march_cpu_opt
= &opt
->value
;
10284 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10289 as_bad (_("unknown architecture `%s'\n"), str
);
10294 struct aarch64_option_abi_value_table
10297 enum aarch64_abi_type value
;
10300 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10302 {"ilp32", AARCH64_ABI_ILP32
},
10303 {"lp64", AARCH64_ABI_LP64
},
10305 {"llp64", AARCH64_ABI_LLP64
},
10310 aarch64_parse_abi (const char *str
)
10314 if (str
[0] == '\0')
10316 as_bad (_("missing abi name `%s'"), str
);
10320 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10321 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10323 aarch64_abi
= aarch64_abis
[i
].value
;
10327 as_bad (_("unknown abi `%s'\n"), str
);
10331 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10332 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10333 aarch64_parse_abi
, NULL
},
10334 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10335 aarch64_parse_cpu
, NULL
},
10336 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10337 aarch64_parse_arch
, NULL
},
10338 {NULL
, NULL
, 0, NULL
}
10342 md_parse_option (int c
, const char *arg
)
10344 struct aarch64_option_table
*opt
;
10345 struct aarch64_long_option_table
*lopt
;
10351 target_big_endian
= 1;
10357 target_big_endian
= 0;
10362 /* Listing option. Just ignore these, we don't support additional
10367 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10369 if (c
== opt
->option
[0]
10370 && ((arg
== NULL
&& opt
->option
[1] == 0)
10371 || streq (arg
, opt
->option
+ 1)))
10373 /* If the option is deprecated, tell the user. */
10374 if (opt
->deprecated
!= NULL
)
10375 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10376 arg
? arg
: "", _(opt
->deprecated
));
10378 if (opt
->var
!= NULL
)
10379 *opt
->var
= opt
->value
;
10385 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10387 /* These options are expected to have an argument. */
10388 if (c
== lopt
->option
[0]
10390 && startswith (arg
, lopt
->option
+ 1))
10392 /* If the option is deprecated, tell the user. */
10393 if (lopt
->deprecated
!= NULL
)
10394 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10395 _(lopt
->deprecated
));
10397 /* Call the sup-option parser. */
10398 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10409 md_show_usage (FILE * fp
)
10411 struct aarch64_option_table
*opt
;
10412 struct aarch64_long_option_table
*lopt
;
10414 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10416 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10417 if (opt
->help
!= NULL
)
10418 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10420 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10421 if (lopt
->help
!= NULL
)
10422 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10426 -EB assemble code for a big-endian cpu\n"));
10431 -EL assemble code for a little-endian cpu\n"));
10435 /* Parse a .cpu directive. */
10438 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10440 const struct aarch64_cpu_option_table
*opt
;
10446 name
= input_line_pointer
;
10447 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10448 saved_char
= *input_line_pointer
;
10449 *input_line_pointer
= 0;
10451 ext
= strchr (name
, '+');
10454 optlen
= ext
- name
;
10456 optlen
= strlen (name
);
10458 /* Skip the first "all" entry. */
10459 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10460 if (strlen (opt
->name
) == optlen
10461 && strncmp (name
, opt
->name
, optlen
) == 0)
10463 mcpu_cpu_opt
= &opt
->value
;
10465 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10468 cpu_variant
= *mcpu_cpu_opt
;
10470 *input_line_pointer
= saved_char
;
10471 demand_empty_rest_of_line ();
10474 as_bad (_("unknown cpu `%s'"), name
);
10475 *input_line_pointer
= saved_char
;
10476 ignore_rest_of_line ();
10480 /* Parse a .arch directive. */
10483 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10485 const struct aarch64_arch_option_table
*opt
;
10491 name
= input_line_pointer
;
10492 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10493 saved_char
= *input_line_pointer
;
10494 *input_line_pointer
= 0;
10496 ext
= strchr (name
, '+');
10499 optlen
= ext
- name
;
10501 optlen
= strlen (name
);
10503 /* Skip the first "all" entry. */
10504 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10505 if (strlen (opt
->name
) == optlen
10506 && strncmp (name
, opt
->name
, optlen
) == 0)
10508 mcpu_cpu_opt
= &opt
->value
;
10510 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10513 cpu_variant
= *mcpu_cpu_opt
;
10515 *input_line_pointer
= saved_char
;
10516 demand_empty_rest_of_line ();
10520 as_bad (_("unknown architecture `%s'\n"), name
);
10521 *input_line_pointer
= saved_char
;
10522 ignore_rest_of_line ();
10525 /* Parse a .arch_extension directive. */
10528 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10531 char *ext
= input_line_pointer
;
10533 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10534 saved_char
= *input_line_pointer
;
10535 *input_line_pointer
= 0;
10537 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10540 cpu_variant
= *mcpu_cpu_opt
;
10542 *input_line_pointer
= saved_char
;
10543 demand_empty_rest_of_line ();
10546 /* Copy symbol information. */
10549 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10551 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10555 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10556 This is needed so AArch64 specific st_other values can be independently
10557 specified for an IFUNC resolver (that is called by the dynamic linker)
10558 and the symbol it resolves (aliased to the resolver). In particular,
10559 if a function symbol has special st_other value set via directives,
10560 then attaching an IFUNC resolver to that symbol should not override
10561 the st_other setting. Requiring the directive on the IFUNC resolver
10562 symbol would be unexpected and problematic in C code, where the two
10563 symbols appear as two independent function declarations. */
10566 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10568 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10569 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10570 /* If size is unset, copy size from src. Because we don't track whether
10571 .size has been used, we can't differentiate .size dest, 0 from the case
10572 where dest's size is unset. */
10573 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10577 destelf
->size
= XNEW (expressionS
);
10578 *destelf
->size
= *srcelf
->size
;
10580 S_SET_SIZE (dest
, S_GET_SIZE (src
));