1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
165 data fields contain the following information:
168 A mask of register types that would have been acceptable as bare
169 operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
170 is set if a general parsing error occured for an operand (that is,
171 an error not related to registers, and having no error string).
174 A mask of register types that would have been acceptable inside
175 a register list. In addition, SEF_IN_REGLIST is set if the
176 operand contained a '{' and if we got to the point of trying
177 to parse a register inside a list.
180 The mask associated with the register that was actually seen, or 0
181 if none. A nonzero value describes a register inside a register
182 list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
185 The idea is that stringless errors from multiple opcode templates can
186 be ORed together to give a summary of the available alternatives. */
187 #define SEF_DEFAULT_ERROR (1U << 31)
188 #define SEF_IN_REGLIST (1U << 31)
190 /* Diagnostics inline function utilities.
192 These are lightweight utilities which should only be called by parse_operands
193 and other parsers. GAS processes each assembly line by parsing it against
194 instruction template(s), in the case of multiple templates (for the same
195 mnemonic name), those templates are tried one by one until one succeeds or
196 all fail. An assembly line may fail a few templates before being
197 successfully parsed; an error saved here in most cases is not a user error
198 but an error indicating the current template is not the right template.
199 Therefore it is very important that errors can be saved at a low cost during
200 the parsing; we don't want to slow down the whole parsing by recording
201 non-user errors in detail.
203 Remember that the objective is to help GAS pick up the most appropriate
204 error message in the case of multiple templates, e.g. FMOV which has 8
210 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
211 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
217 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
224 inst
.parsing_error
.index
= -1;
225 inst
.parsing_error
.kind
= kind
;
226 inst
.parsing_error
.error
= error
;
230 set_recoverable_error (const char *error
)
232 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
235 /* Use the DESC field of the corresponding aarch64_operand entry to compose
236 the error message. */
238 set_default_error (void)
240 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
241 inst
.parsing_error
.data
[0].i
= SEF_DEFAULT_ERROR
;
245 set_expected_error (unsigned int flags
)
247 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
248 inst
.parsing_error
.data
[0].i
= flags
;
252 set_syntax_error (const char *error
)
254 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
258 set_first_syntax_error (const char *error
)
261 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
265 set_fatal_syntax_error (const char *error
)
267 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
270 /* Return value for certain parsers when the parsing fails; those parsers
271 return the information of the parsed result, e.g. register number, on
273 #define PARSE_FAIL -1
275 /* This is an invalid condition code that means no conditional field is
277 #define COND_ALWAYS 0x10
281 const char *template;
288 bfd_reloc_code_real_type reloc
;
291 /* Macros to define the register types and masks for the purpose
294 #undef AARCH64_REG_TYPES
295 #define AARCH64_REG_TYPES \
296 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
297 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
298 BASIC_REG_TYPE(SP_32) /* wsp */ \
299 BASIC_REG_TYPE(SP_64) /* sp */ \
300 BASIC_REG_TYPE(ZR_32) /* wzr */ \
301 BASIC_REG_TYPE(ZR_64) /* xzr */ \
302 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
303 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
304 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
305 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
306 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
307 BASIC_REG_TYPE(V) /* v[0-31] */ \
308 BASIC_REG_TYPE(Z) /* z[0-31] */ \
309 BASIC_REG_TYPE(P) /* p[0-15] */ \
310 BASIC_REG_TYPE(PN) /* pn[0-15] */ \
311 BASIC_REG_TYPE(ZA) /* za */ \
312 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
313 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
314 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
315 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
316 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
317 /* Typecheck: same, plus SVE registers. */ \
318 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
320 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
321 MULTI_REG_TYPE(R_ZR, REG_TYPE(R_32) | REG_TYPE(R_64) \
322 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
323 /* Typecheck: same, plus SVE registers. */ \
324 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) \
327 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
328 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
329 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
330 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
331 MULTI_REG_TYPE(R_ZR_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
332 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
333 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
334 /* Typecheck: any [BHSDQ]P FP. */ \
335 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
336 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
337 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
338 MULTI_REG_TYPE(R_ZR_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
339 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
340 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
341 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
342 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
343 be used for SVE instructions, since Zn and Pn are valid symbols \
344 in other contexts. */ \
345 MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
346 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
347 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
348 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
349 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
350 | REG_TYPE(Z) | REG_TYPE(P)) \
351 /* Any integer register; used for error messages only. */ \
352 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
353 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
354 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
355 /* Any vector register. */ \
356 MULTI_REG_TYPE(VZ, REG_TYPE(V) | REG_TYPE(Z)) \
357 /* An SVE vector or predicate register. */ \
358 MULTI_REG_TYPE(ZP, REG_TYPE(Z) | REG_TYPE(P)) \
359 /* Any vector or predicate register. */ \
360 MULTI_REG_TYPE(VZP, REG_TYPE(V) | REG_TYPE(Z) | REG_TYPE(P)) \
361 /* The whole of ZA or a single tile. */ \
362 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
363 /* A horizontal or vertical slice of a ZA tile. */ \
364 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
365 /* Pseudo type to mark the end of the enumerator sequence. */ \
368 #undef BASIC_REG_TYPE
369 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
370 #undef MULTI_REG_TYPE
371 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
373 #define END_REG_TYPE(T) BASIC_REG_TYPE(T)
375 /* Register type enumerators. */
376 typedef enum aarch64_reg_type_
378 /* A list of REG_TYPE_*. */
382 #undef BASIC_REG_TYPE
383 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
385 #define REG_TYPE(T) (1 << REG_TYPE_##T)
386 #undef MULTI_REG_TYPE
387 #define MULTI_REG_TYPE(T,V) V,
389 #define END_REG_TYPE(T) 0
391 /* Structure for a hash table entry for a register. */
395 unsigned char number
;
396 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
397 unsigned char builtin
;
400 /* Values indexed by aarch64_reg_type to assist the type checking. */
401 static const unsigned reg_type_masks
[] =
406 #undef BASIC_REG_TYPE
408 #undef MULTI_REG_TYPE
410 #undef AARCH64_REG_TYPES
412 /* We expected one of the registers in MASK to be specified. If a register
413 of some kind was specified, SEEN is a mask that contains that register,
414 otherwise it is zero.
416 If it is possible to provide a relatively pithy message that describes
417 the error exactly, return a string that does so, reporting the error
418 against "operand %d". Return null otherwise.
420 From a QoI perspective, any REG_TYPE_* that is passed as the first
421 argument to set_expected_reg_error should generally have its own message.
422 Providing messages for combinations of such REG_TYPE_*s can be useful if
423 it is possible to summarize the combination in a relatively natural way.
424 On the other hand, it seems better to avoid long lists of unrelated
428 get_reg_expected_msg (unsigned int mask
, unsigned int seen
)
430 /* First handle messages that use SEEN. */
431 if ((mask
& reg_type_masks
[REG_TYPE_ZAT
])
432 && (seen
& reg_type_masks
[REG_TYPE_ZATHV
]))
433 return N_("expected an unsuffixed ZA tile at operand %d");
435 if ((mask
& reg_type_masks
[REG_TYPE_ZATHV
])
436 && (seen
& reg_type_masks
[REG_TYPE_ZAT
]))
437 return N_("missing horizontal or vertical suffix at operand %d");
439 if ((mask
& reg_type_masks
[REG_TYPE_ZA
])
440 && (seen
& (reg_type_masks
[REG_TYPE_ZAT
]
441 | reg_type_masks
[REG_TYPE_ZATHV
])))
442 return N_("expected 'za' rather than a ZA tile at operand %d");
444 if ((mask
& reg_type_masks
[REG_TYPE_PN
])
445 && (seen
& reg_type_masks
[REG_TYPE_P
]))
446 return N_("expected a predicate-as-counter rather than predicate-as-mask"
447 " register at operand %d");
449 if ((mask
& reg_type_masks
[REG_TYPE_P
])
450 && (seen
& reg_type_masks
[REG_TYPE_PN
]))
451 return N_("expected a predicate-as-mask rather than predicate-as-counter"
452 " register at operand %d");
454 /* Integer, zero and stack registers. */
455 if (mask
== reg_type_masks
[REG_TYPE_R_64
])
456 return N_("expected a 64-bit integer register at operand %d");
457 if (mask
== reg_type_masks
[REG_TYPE_R_ZR
])
458 return N_("expected an integer or zero register at operand %d");
459 if (mask
== reg_type_masks
[REG_TYPE_R_SP
])
460 return N_("expected an integer or stack pointer register at operand %d");
462 /* Floating-point and SIMD registers. */
463 if (mask
== reg_type_masks
[REG_TYPE_BHSDQ
])
464 return N_("expected a scalar SIMD or floating-point register"
466 if (mask
== reg_type_masks
[REG_TYPE_V
])
467 return N_("expected an Advanced SIMD vector register at operand %d");
468 if (mask
== reg_type_masks
[REG_TYPE_Z
])
469 return N_("expected an SVE vector register at operand %d");
470 if (mask
== reg_type_masks
[REG_TYPE_P
]
471 || mask
== (reg_type_masks
[REG_TYPE_P
] | reg_type_masks
[REG_TYPE_PN
]))
472 /* Use this error for "predicate-as-mask only" and "either kind of
473 predicate". We report a more specific error if P is used where
474 PN is expected, and vice versa, so the issue at this point is
475 "predicate-like" vs. "not predicate-like". */
476 return N_("expected an SVE predicate register at operand %d");
477 if (mask
== reg_type_masks
[REG_TYPE_PN
])
478 return N_("expected an SVE predicate-as-counter register at operand %d");
479 if (mask
== reg_type_masks
[REG_TYPE_VZ
])
480 return N_("expected a vector register at operand %d");
481 if (mask
== reg_type_masks
[REG_TYPE_ZP
])
482 return N_("expected an SVE vector or predicate register at operand %d");
483 if (mask
== reg_type_masks
[REG_TYPE_VZP
])
484 return N_("expected a vector or predicate register at operand %d");
486 /* ZA-related registers. */
487 if (mask
== reg_type_masks
[REG_TYPE_ZA
])
488 return N_("expected a ZA array vector at operand %d");
489 if (mask
== reg_type_masks
[REG_TYPE_ZA_ZAT
])
490 return N_("expected 'za' or a ZA tile at operand %d");
491 if (mask
== reg_type_masks
[REG_TYPE_ZAT
])
492 return N_("expected a ZA tile at operand %d");
493 if (mask
== reg_type_masks
[REG_TYPE_ZATHV
])
494 return N_("expected a ZA tile slice at operand %d");
496 /* Integer and vector combos. */
497 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_V
]))
498 return N_("expected an integer register or Advanced SIMD vector register"
500 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_Z
]))
501 return N_("expected an integer register or SVE vector register"
503 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZ
]))
504 return N_("expected an integer or vector register at operand %d");
505 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_P
]))
506 return N_("expected an integer or predicate register at operand %d");
507 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZP
]))
508 return N_("expected an integer, vector or predicate register"
511 /* SVE and SME combos. */
512 if (mask
== (reg_type_masks
[REG_TYPE_Z
] | reg_type_masks
[REG_TYPE_ZATHV
]))
513 return N_("expected an SVE vector register or ZA tile slice"
519 /* Record that we expected a register of type TYPE but didn't see one.
520 REG is the register that we actually saw, or null if we didn't see a
521 recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
522 contents of a register list, otherwise it is zero. */
525 set_expected_reg_error (aarch64_reg_type type
, const reg_entry
*reg
,
528 assert (flags
== 0 || flags
== SEF_IN_REGLIST
);
529 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
530 if (flags
& SEF_IN_REGLIST
)
531 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
] | flags
;
533 inst
.parsing_error
.data
[0].i
= reg_type_masks
[type
];
535 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
538 /* Record that we expected a register list containing registers of type TYPE,
539 but didn't see the opening '{'. If we saw a register instead, REG is the
540 register that we saw, otherwise it is null. */
543 set_expected_reglist_error (aarch64_reg_type type
, const reg_entry
*reg
)
545 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
546 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
];
548 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
551 /* Some well known registers that we refer to directly elsewhere. */
555 /* Instructions take 4 bytes in the object file. */
558 static htab_t aarch64_ops_hsh
;
559 static htab_t aarch64_cond_hsh
;
560 static htab_t aarch64_shift_hsh
;
561 static htab_t aarch64_sys_regs_hsh
;
562 static htab_t aarch64_pstatefield_hsh
;
563 static htab_t aarch64_sys_regs_ic_hsh
;
564 static htab_t aarch64_sys_regs_dc_hsh
;
565 static htab_t aarch64_sys_regs_at_hsh
;
566 static htab_t aarch64_sys_regs_tlbi_hsh
;
567 static htab_t aarch64_sys_regs_sr_hsh
;
568 static htab_t aarch64_reg_hsh
;
569 static htab_t aarch64_barrier_opt_hsh
;
570 static htab_t aarch64_nzcv_hsh
;
571 static htab_t aarch64_pldop_hsh
;
572 static htab_t aarch64_hint_opt_hsh
;
574 /* Stuff needed to resolve the label ambiguity
583 static symbolS
*last_label_seen
;
585 /* Literal pool structure. Held on a per-section
586 and per-sub-section basis. */
588 #define MAX_LITERAL_POOL_SIZE 1024
589 typedef struct literal_expression
592 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
593 LITTLENUM_TYPE
* bignum
;
594 } literal_expression
;
596 typedef struct literal_pool
598 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
599 unsigned int next_free_entry
;
605 struct literal_pool
*next
;
608 /* Pointer to a linked list of literal pools. */
609 static literal_pool
*list_of_pools
= NULL
;
613 /* This array holds the chars that always start a comment. If the
614 pre-processor is disabled, these aren't very useful. */
615 const char comment_chars
[] = "";
617 /* This array holds the chars that only start a comment at the beginning of
618 a line. If the line seems to have the form '# 123 filename'
619 .line and .file directives will appear in the pre-processed output. */
620 /* Note that input_file.c hand checks for '#' at the beginning of the
621 first line of the input file. This is because the compiler outputs
622 #NO_APP at the beginning of its output. */
623 /* Also note that comments like this one will always work. */
624 const char line_comment_chars
[] = "#";
626 const char line_separator_chars
[] = ";";
628 /* Chars that can be used to separate mant
629 from exp in floating point numbers. */
630 const char EXP_CHARS
[] = "eE";
632 /* Chars that mean this number is a floating point constant. */
636 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
638 /* Prefix character that indicates the start of an immediate value. */
639 #define is_immediate_prefix(C) ((C) == '#')
641 /* Separator character handling. */
643 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
646 skip_past_char (char **str
, char c
)
657 #define skip_past_comma(str) skip_past_char (str, ',')
659 /* Arithmetic expressions (possibly involving symbols). */
661 static bool in_aarch64_get_expression
= false;
663 /* Third argument to aarch64_get_expression. */
664 #define GE_NO_PREFIX false
665 #define GE_OPT_PREFIX true
667 /* Fourth argument to aarch64_get_expression. */
668 #define ALLOW_ABSENT false
669 #define REJECT_ABSENT true
671 /* Return TRUE if the string pointed by *STR is successfully parsed
672 as an valid expression; *EP will be filled with the information of
673 such an expression. Otherwise return FALSE.
675 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
676 If REJECT_ABSENT is true then trat missing expressions as an error. */
679 aarch64_get_expression (expressionS
* ep
,
681 bool allow_immediate_prefix
,
686 bool prefix_present
= false;
688 if (allow_immediate_prefix
)
690 if (is_immediate_prefix (**str
))
693 prefix_present
= true;
697 memset (ep
, 0, sizeof (expressionS
));
699 save_in
= input_line_pointer
;
700 input_line_pointer
= *str
;
701 in_aarch64_get_expression
= true;
702 seg
= expression (ep
);
703 in_aarch64_get_expression
= false;
705 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
707 /* We found a bad expression in md_operand(). */
708 *str
= input_line_pointer
;
709 input_line_pointer
= save_in
;
710 if (prefix_present
&& ! error_p ())
711 set_fatal_syntax_error (_("bad expression"));
713 set_first_syntax_error (_("bad expression"));
718 if (seg
!= absolute_section
719 && seg
!= text_section
720 && seg
!= data_section
721 && seg
!= bss_section
722 && seg
!= undefined_section
)
724 set_syntax_error (_("bad segment"));
725 *str
= input_line_pointer
;
726 input_line_pointer
= save_in
;
733 *str
= input_line_pointer
;
734 input_line_pointer
= save_in
;
738 /* Turn a string in input_line_pointer into a floating point constant
739 of type TYPE, and store the appropriate bytes in *LITP. The number
740 of LITTLENUMS emitted is stored in *SIZEP. An error message is
741 returned, or NULL on OK. */
744 md_atof (int type
, char *litP
, int *sizeP
)
746 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
749 /* We handle all bad expressions here, so that we can report the faulty
750 instruction in the error message. */
752 md_operand (expressionS
* exp
)
754 if (in_aarch64_get_expression
)
755 exp
->X_op
= O_illegal
;
758 /* Immediate values. */
760 /* Errors may be set multiple times during parsing or bit encoding
761 (particularly in the Neon bits), but usually the earliest error which is set
762 will be the most meaningful. Avoid overwriting it with later (cascading)
763 errors by calling this function. */
766 first_error (const char *error
)
769 set_syntax_error (error
);
772 /* Similar to first_error, but this function accepts formatted error
775 first_error_fmt (const char *format
, ...)
780 /* N.B. this single buffer will not cause error messages for different
781 instructions to pollute each other; this is because at the end of
782 processing of each assembly line, error message if any will be
783 collected by as_bad. */
784 static char buffer
[size
];
788 int ret ATTRIBUTE_UNUSED
;
789 va_start (args
, format
);
790 ret
= vsnprintf (buffer
, size
, format
, args
);
791 know (ret
<= size
- 1 && ret
>= 0);
793 set_syntax_error (buffer
);
797 /* Internal helper routine converting a vector_type_el structure *VECTYPE
798 to a corresponding operand qualifier. */
800 static inline aarch64_opnd_qualifier_t
801 vectype_to_qualifier (const struct vector_type_el
*vectype
)
803 /* Element size in bytes indexed by vector_el_type. */
804 const unsigned char ele_size
[5]
806 const unsigned int ele_base
[5] =
808 AARCH64_OPND_QLF_V_4B
,
809 AARCH64_OPND_QLF_V_2H
,
810 AARCH64_OPND_QLF_V_2S
,
811 AARCH64_OPND_QLF_V_1D
,
812 AARCH64_OPND_QLF_V_1Q
815 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
816 goto vectype_conversion_fail
;
818 if (vectype
->type
== NT_zero
)
819 return AARCH64_OPND_QLF_P_Z
;
820 if (vectype
->type
== NT_merge
)
821 return AARCH64_OPND_QLF_P_M
;
823 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
825 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
827 /* Special case S_4B. */
828 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
829 return AARCH64_OPND_QLF_S_4B
;
831 /* Special case S_2H. */
832 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
833 return AARCH64_OPND_QLF_S_2H
;
835 /* Vector element register. */
836 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
840 /* Vector register. */
841 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
844 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
845 goto vectype_conversion_fail
;
847 /* The conversion is by calculating the offset from the base operand
848 qualifier for the vector type. The operand qualifiers are regular
849 enough that the offset can established by shifting the vector width by
850 a vector-type dependent amount. */
852 if (vectype
->type
== NT_b
)
854 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
856 else if (vectype
->type
>= NT_d
)
861 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
862 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
863 && offset
<= AARCH64_OPND_QLF_V_1Q
);
867 vectype_conversion_fail
:
868 first_error (_("bad vector arrangement type"));
869 return AARCH64_OPND_QLF_NIL
;
872 /* Register parsing. */
874 /* Generic register parser which is called by other specialized
876 CCP points to what should be the beginning of a register name.
877 If it is indeed a valid register name, advance CCP over it and
878 return the reg_entry structure; otherwise return NULL.
879 It does not issue diagnostics. */
882 parse_reg (char **ccp
)
888 #ifdef REGISTER_PREFIX
889 if (*start
!= REGISTER_PREFIX
)
895 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
900 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
902 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
911 /* Return the operand qualifier associated with all uses of REG, or
912 AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
913 that qualifiers don't apply to REG or that qualifiers are added
916 static aarch64_opnd_qualifier_t
917 inherent_reg_qualifier (const reg_entry
*reg
)
924 return AARCH64_OPND_QLF_W
;
929 return AARCH64_OPND_QLF_X
;
936 return AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
939 return AARCH64_OPND_QLF_NIL
;
943 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
946 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
948 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
951 /* Try to parse a base or offset register. Allow SVE base and offset
952 registers if REG_TYPE includes SVE registers. Return the register
953 entry on success, setting *QUALIFIER to the register qualifier.
954 Return null otherwise.
956 Note that this function does not issue any diagnostics. */
958 static const reg_entry
*
959 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
960 aarch64_opnd_qualifier_t
*qualifier
)
963 const reg_entry
*reg
= parse_reg (&str
);
971 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_Z
)) == 0
974 switch (TOLOWER (str
[1]))
977 *qualifier
= AARCH64_OPND_QLF_S_S
;
980 *qualifier
= AARCH64_OPND_QLF_S_D
;
989 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR_SP
))
991 *qualifier
= inherent_reg_qualifier (reg
);
1000 /* Try to parse a base or offset register. Return the register entry
1001 on success, setting *QUALIFIER to the register qualifier. Return null
1004 Note that this function does not issue any diagnostics. */
1006 static const reg_entry
*
1007 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
1009 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_ZR_SP
, qualifier
);
1012 /* Parse the qualifier of a vector register or vector element of type
1013 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
1014 succeeds; otherwise return FALSE.
1016 Accept only one occurrence of:
1017 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
1020 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
1021 struct vector_type_el
*parsed_type
, char **str
)
1025 unsigned element_size
;
1026 enum vector_el_type type
;
1029 gas_assert (*ptr
== '.');
1032 if (reg_type
!= REG_TYPE_V
|| !ISDIGIT (*ptr
))
1037 width
= strtoul (ptr
, &ptr
, 10);
1038 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
1040 first_error_fmt (_("bad size %d in vector width specifier"), width
);
1045 switch (TOLOWER (*ptr
))
1064 if (reg_type
!= REG_TYPE_V
|| width
== 1)
1073 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
1075 first_error (_("missing element size"));
1078 if (width
!= 0 && width
* element_size
!= 64
1079 && width
* element_size
!= 128
1080 && !(width
== 2 && element_size
== 16)
1081 && !(width
== 4 && element_size
== 8))
1084 ("invalid element size %d and vector size combination %c"),
1090 parsed_type
->type
= type
;
1091 parsed_type
->width
= width
;
1092 parsed_type
->element_size
= element_size
;
1099 /* *STR contains an SVE zero/merge predication suffix. Parse it into
1100 *PARSED_TYPE and point *STR at the end of the suffix. */
1103 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
1108 gas_assert (*ptr
== '/');
1110 switch (TOLOWER (*ptr
))
1113 parsed_type
->type
= NT_zero
;
1116 parsed_type
->type
= NT_merge
;
1119 if (*ptr
!= '\0' && *ptr
!= ',')
1120 first_error_fmt (_("unexpected character `%c' in predication type"),
1123 first_error (_("missing predication type"));
1126 parsed_type
->width
= 0;
1131 /* Return true if CH is a valid suffix character for registers of
1135 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1149 return ch
== '.' || ch
== '/';
1156 /* Parse an index expression at *STR, storing it in *IMM on success. */
1159 parse_index_expression (char **str
, int64_t *imm
)
1163 aarch64_get_expression (&exp
, str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1164 if (exp
.X_op
!= O_constant
)
1166 first_error (_("constant expression required"));
1169 *imm
= exp
.X_add_number
;
1173 /* Parse a register of the type TYPE.
1175 Return null if the string pointed to by *CCP is not a valid register
1176 name or the parsed register is not of TYPE.
1178 Otherwise return the register, and optionally return the register
1179 shape and element index information in *TYPEINFO.
1181 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1183 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1186 FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
1187 an operand that we can be confident that it is a good match. */
1189 #define PTR_IN_REGLIST (1U << 0)
1190 #define PTR_FULL_REG (1U << 1)
1191 #define PTR_GOOD_MATCH (1U << 2)
1193 static const reg_entry
*
1194 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1195 struct vector_type_el
*typeinfo
, unsigned int flags
)
1198 bool isalpha
= ISALPHA (*str
);
1199 const reg_entry
*reg
= parse_reg (&str
);
1200 struct vector_type_el atype
;
1201 struct vector_type_el parsetype
;
1202 bool is_typed_vecreg
= false;
1203 unsigned int err_flags
= (flags
& PTR_IN_REGLIST
) ? SEF_IN_REGLIST
: 0;
1206 atype
.type
= NT_invtype
;
1208 atype
.element_size
= 0;
1215 if (!isalpha
&& (flags
& PTR_IN_REGLIST
))
1216 set_fatal_syntax_error (_("syntax error in register list"));
1217 else if (flags
& PTR_GOOD_MATCH
)
1218 set_fatal_syntax_error (NULL
);
1220 set_expected_reg_error (type
, reg
, err_flags
);
1224 if (! aarch64_check_reg_type (reg
, type
))
1226 DEBUG_TRACE ("reg type check failed");
1227 if (flags
& PTR_GOOD_MATCH
)
1228 set_fatal_syntax_error (NULL
);
1230 set_expected_reg_error (type
, reg
, err_flags
);
1235 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1239 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1241 if ((reg
->type
== REG_TYPE_ZAT
1242 || reg
->type
== REG_TYPE_ZATH
1243 || reg
->type
== REG_TYPE_ZATV
)
1244 && reg
->number
* 8 >= parsetype
.element_size
)
1246 set_syntax_error (_("ZA tile number out of range"));
1252 if (!parse_predication_for_operand (&parsetype
, &str
))
1256 /* Register if of the form Vn.[bhsdq]. */
1257 is_typed_vecreg
= true;
1259 if (type
!= REG_TYPE_V
)
1261 /* The width is always variable; we don't allow an integer width
1263 gas_assert (parsetype
.width
== 0);
1264 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1266 else if (parsetype
.width
== 0)
1267 /* Expect index. In the new scheme we cannot have
1268 Vn.[bhsdq] represent a scalar. Therefore any
1269 Vn.[bhsdq] should have an index following it.
1270 Except in reglists of course. */
1271 atype
.defined
|= NTA_HASINDEX
;
1273 atype
.defined
|= NTA_HASTYPE
;
1275 atype
.type
= parsetype
.type
;
1276 atype
.width
= parsetype
.width
;
1279 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1281 /* Reject Sn[index] syntax. */
1282 if (reg
->type
!= REG_TYPE_PN
&& !is_typed_vecreg
)
1284 first_error (_("this type of register can't be indexed"));
1288 if (flags
& PTR_IN_REGLIST
)
1290 first_error (_("index not allowed inside register list"));
1294 atype
.defined
|= NTA_HASINDEX
;
1296 if (!parse_index_expression (&str
, &atype
.index
))
1299 if (! skip_past_char (&str
, ']'))
1302 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1304 /* Indexed vector register expected. */
1305 first_error (_("indexed vector register expected"));
1309 /* A vector reg Vn should be typed or indexed. */
1310 if (type
== REG_TYPE_V
&& atype
.defined
== 0)
1312 first_error (_("invalid use of vector register"));
1325 Return the register on success; return null otherwise.
1327 If this is a NEON vector register with additional type information, fill
1328 in the struct pointed to by VECTYPE (if non-NULL).
1330 This parser does not handle register lists. */
1332 static const reg_entry
*
1333 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1334 struct vector_type_el
*vectype
)
1336 return parse_typed_reg (ccp
, type
, vectype
, 0);
1340 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1342 return (e1
.type
== e2
.type
1343 && e1
.defined
== e2
.defined
1344 && e1
.width
== e2
.width
1345 && e1
.element_size
== e2
.element_size
1346 && e1
.index
== e2
.index
);
1349 /* Return the register number mask for registers of type REG_TYPE. */
1352 reg_type_mask (aarch64_reg_type reg_type
)
1354 return reg_type
== REG_TYPE_P
? 15 : 31;
1357 /* This function parses a list of vector registers of type TYPE.
1358 On success, it returns the parsed register list information in the
1359 following encoded format:
1361 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1362 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1364 The information of the register shape and/or index is returned in
1367 It returns PARSE_FAIL if the register list is invalid.
1369 The list contains one to four registers.
1370 Each register can be one of:
1373 All <T> should be identical.
1374 All <index> should be identical.
1375 There are restrictions on <Vt> numbers which are checked later
1376 (by reg_list_valid_p). */
1379 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1380 struct vector_type_el
*vectype
)
1384 struct vector_type_el typeinfo
, typeinfo_first
;
1385 int val
, val_range
, mask
;
1389 bool expect_index
= false;
1390 unsigned int ptr_flags
= PTR_IN_REGLIST
;
1394 set_expected_reglist_error (type
, parse_reg (&str
));
1400 typeinfo_first
.defined
= 0;
1401 typeinfo_first
.type
= NT_invtype
;
1402 typeinfo_first
.width
= -1;
1403 typeinfo_first
.element_size
= 0;
1404 typeinfo_first
.index
= 0;
1409 mask
= reg_type_mask (type
);
1414 str
++; /* skip over '-' */
1417 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1421 set_first_syntax_error (_("invalid vector register in list"));
1426 /* reject [bhsd]n */
1427 if (type
== REG_TYPE_V
&& typeinfo
.defined
== 0)
1429 set_first_syntax_error (_("invalid scalar register in list"));
1434 if (typeinfo
.defined
& NTA_HASINDEX
)
1435 expect_index
= true;
1439 if (val
== val_range
)
1441 set_first_syntax_error
1442 (_("invalid range in vector register list"));
1445 val_range
= (val_range
+ 1) & mask
;
1451 typeinfo_first
= typeinfo
;
1452 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1454 set_first_syntax_error
1455 (_("type mismatch in vector register list"));
1462 ret_val
|= val_range
<< (5 * nb_regs
);
1464 if (val_range
== val
)
1466 val_range
= (val_range
+ 1) & mask
;
1469 ptr_flags
|= PTR_GOOD_MATCH
;
1471 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1473 skip_whitespace (str
);
1476 set_first_syntax_error (_("end of vector register list not found"));
1481 skip_whitespace (str
);
1485 if (skip_past_char (&str
, '['))
1487 if (!parse_index_expression (&str
, &typeinfo_first
.index
))
1489 if (! skip_past_char (&str
, ']'))
1494 set_first_syntax_error (_("expected index"));
1501 set_first_syntax_error (_("too many registers in vector register list"));
1504 else if (nb_regs
== 0)
1506 set_first_syntax_error (_("empty vector register list"));
1512 *vectype
= typeinfo_first
;
1514 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1517 /* Directives: register aliases. */
1520 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1525 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1528 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1531 /* Only warn about a redefinition if it's not defined as the
1533 else if (new->number
!= number
|| new->type
!= type
)
1534 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1539 name
= xstrdup (str
);
1540 new = XNEW (reg_entry
);
1543 new->number
= number
;
1545 new->builtin
= false;
1547 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1552 /* Look for the .req directive. This is of the form:
1554 new_register_name .req existing_register_name
1556 If we find one, or if it looks sufficiently like one that we want to
1557 handle any error here, return TRUE. Otherwise return FALSE. */
1560 create_register_alias (char *newname
, char *p
)
1562 const reg_entry
*old
;
1563 char *oldname
, *nbuf
;
1566 /* The input scrubber ensures that whitespace after the mnemonic is
1567 collapsed to single spaces. */
1569 if (!startswith (oldname
, " .req "))
1573 if (*oldname
== '\0')
1576 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1579 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1583 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1584 the desired alias name, and p points to its end. If not, then
1585 the desired alias name is in the global original_case_string. */
1586 #ifdef TC_CASE_SENSITIVE
1589 newname
= original_case_string
;
1590 nlen
= strlen (newname
);
1593 nbuf
= xmemdup0 (newname
, nlen
);
1595 /* Create aliases under the new name as stated; an all-lowercase
1596 version of the new name; and an all-uppercase version of the new
1598 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1600 for (p
= nbuf
; *p
; p
++)
1603 if (strncmp (nbuf
, newname
, nlen
))
1605 /* If this attempt to create an additional alias fails, do not bother
1606 trying to create the all-lower case alias. We will fail and issue
1607 a second, duplicate error message. This situation arises when the
1608 programmer does something like:
1611 The second .req creates the "Foo" alias but then fails to create
1612 the artificial FOO alias because it has already been created by the
1614 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1621 for (p
= nbuf
; *p
; p
++)
1624 if (strncmp (nbuf
, newname
, nlen
))
1625 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1632 /* Should never be called, as .req goes between the alias and the
1633 register name, not at the beginning of the line. */
1635 s_req (int a ATTRIBUTE_UNUSED
)
1637 as_bad (_("invalid syntax for .req directive"));
1640 /* The .unreq directive deletes an alias which was previously defined
1641 by .req. For example:
1647 s_unreq (int a ATTRIBUTE_UNUSED
)
1652 name
= input_line_pointer
;
1653 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1654 saved_char
= *input_line_pointer
;
1655 *input_line_pointer
= 0;
1658 as_bad (_("invalid syntax for .unreq directive"));
1661 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1664 as_bad (_("unknown register alias '%s'"), name
);
1665 else if (reg
->builtin
)
1666 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1673 str_hash_delete (aarch64_reg_hsh
, name
);
1674 free ((char *) reg
->name
);
1677 /* Also locate the all upper case and all lower case versions.
1678 Do not complain if we cannot find one or the other as it
1679 was probably deleted above. */
1681 nbuf
= strdup (name
);
1682 for (p
= nbuf
; *p
; p
++)
1684 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1687 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1688 free ((char *) reg
->name
);
1692 for (p
= nbuf
; *p
; p
++)
1694 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1697 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1698 free ((char *) reg
->name
);
1706 *input_line_pointer
= saved_char
;
1707 demand_empty_rest_of_line ();
1710 /* Directives: Instruction set selection. */
1712 #if defined OBJ_ELF || defined OBJ_COFF
1713 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1714 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1715 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1716 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1718 /* Create a new mapping symbol for the transition to STATE. */
1721 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1724 const char *symname
;
1731 type
= BSF_NO_FLAGS
;
1735 type
= BSF_NO_FLAGS
;
1741 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1742 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1744 /* Save the mapping symbols for future reference. Also check that
1745 we do not place two mapping symbols at the same offset within a
1746 frag. We'll handle overlap between frags in
1747 check_mapping_symbols.
1749 If .fill or other data filling directive generates zero sized data,
1750 the mapping symbol for the following code will have the same value
1751 as the one generated for the data filling directive. In this case,
1752 we replace the old symbol with the new one at the same address. */
1755 if (frag
->tc_frag_data
.first_map
!= NULL
)
1757 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1758 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1761 frag
->tc_frag_data
.first_map
= symbolP
;
1763 if (frag
->tc_frag_data
.last_map
!= NULL
)
1765 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1766 S_GET_VALUE (symbolP
));
1767 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1768 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1771 frag
->tc_frag_data
.last_map
= symbolP
;
1774 /* We must sometimes convert a region marked as code to data during
1775 code alignment, if an odd number of bytes have to be padded. The
1776 code mapping symbol is pushed to an aligned address. */
1779 insert_data_mapping_symbol (enum mstate state
,
1780 valueT value
, fragS
* frag
, offsetT bytes
)
1782 /* If there was already a mapping symbol, remove it. */
1783 if (frag
->tc_frag_data
.last_map
!= NULL
1784 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1785 frag
->fr_address
+ value
)
1787 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1791 know (frag
->tc_frag_data
.first_map
== symp
);
1792 frag
->tc_frag_data
.first_map
= NULL
;
1794 frag
->tc_frag_data
.last_map
= NULL
;
1795 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1798 make_mapping_symbol (MAP_DATA
, value
, frag
);
1799 make_mapping_symbol (state
, value
+ bytes
, frag
);
1802 static void mapping_state_2 (enum mstate state
, int max_chars
);
1804 /* Set the mapping state to STATE. Only call this when about to
1805 emit some STATE bytes to the file. */
1808 mapping_state (enum mstate state
)
1810 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1812 if (state
== MAP_INSN
)
1813 /* AArch64 instructions require 4-byte alignment. When emitting
1814 instructions into any section, record the appropriate section
1816 record_alignment (now_seg
, 2);
1818 if (mapstate
== state
)
1819 /* The mapping symbol has already been emitted.
1820 There is nothing else to do. */
1823 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1824 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1825 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1826 evaluated later in the next else. */
1828 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1830 /* Only add the symbol if the offset is > 0:
1831 if we're at the first frag, check it's size > 0;
1832 if we're not at the first frag, then for sure
1833 the offset is > 0. */
1834 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1835 const int add_symbol
= (frag_now
!= frag_first
)
1836 || (frag_now_fix () > 0);
1839 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1843 mapping_state_2 (state
, 0);
1846 /* Same as mapping_state, but MAX_CHARS bytes have already been
1847 allocated. Put the mapping symbol that far back. */
1850 mapping_state_2 (enum mstate state
, int max_chars
)
1852 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1854 if (!SEG_NORMAL (now_seg
))
1857 if (mapstate
== state
)
1858 /* The mapping symbol has already been emitted.
1859 There is nothing else to do. */
1862 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1863 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1866 #define mapping_state(x) /* nothing */
1867 #define mapping_state_2(x, y) /* nothing */
1870 /* Directives: sectioning and alignment. */
1873 s_bss (int ignore ATTRIBUTE_UNUSED
)
1875 /* We don't support putting frags in the BSS segment, we fake it by
1876 marking in_bss, then looking at s_skip for clues. */
1877 subseg_set (bss_section
, 0);
1878 demand_empty_rest_of_line ();
1879 mapping_state (MAP_DATA
);
1883 s_even (int ignore ATTRIBUTE_UNUSED
)
1885 /* Never make frag if expect extra pass. */
1887 frag_align (1, 0, 0);
1889 record_alignment (now_seg
, 1);
1891 demand_empty_rest_of_line ();
1894 /* Directives: Literal pools. */
1896 static literal_pool
*
1897 find_literal_pool (int size
)
1901 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1903 if (pool
->section
== now_seg
1904 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1911 static literal_pool
*
1912 find_or_make_literal_pool (int size
)
1914 /* Next literal pool ID number. */
1915 static unsigned int latest_pool_num
= 1;
1918 pool
= find_literal_pool (size
);
1922 /* Create a new pool. */
1923 pool
= XNEW (literal_pool
);
1927 /* Currently we always put the literal pool in the current text
1928 section. If we were generating "small" model code where we
1929 knew that all code and initialised data was within 1MB then
1930 we could output literals to mergeable, read-only data
1933 pool
->next_free_entry
= 0;
1934 pool
->section
= now_seg
;
1935 pool
->sub_section
= now_subseg
;
1937 pool
->next
= list_of_pools
;
1938 pool
->symbol
= NULL
;
1940 /* Add it to the list. */
1941 list_of_pools
= pool
;
1944 /* New pools, and emptied pools, will have a NULL symbol. */
1945 if (pool
->symbol
== NULL
)
1947 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1948 &zero_address_frag
, 0);
1949 pool
->id
= latest_pool_num
++;
1956 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1957 Return TRUE on success, otherwise return FALSE. */
1959 add_to_lit_pool (expressionS
*exp
, int size
)
1964 pool
= find_or_make_literal_pool (size
);
1966 /* Check if this literal value is already in the pool. */
1967 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1969 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1971 if ((litexp
->X_op
== exp
->X_op
)
1972 && (exp
->X_op
== O_constant
)
1973 && (litexp
->X_add_number
== exp
->X_add_number
)
1974 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1977 if ((litexp
->X_op
== exp
->X_op
)
1978 && (exp
->X_op
== O_symbol
)
1979 && (litexp
->X_add_number
== exp
->X_add_number
)
1980 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1981 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1985 /* Do we need to create a new entry? */
1986 if (entry
== pool
->next_free_entry
)
1988 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1990 set_syntax_error (_("literal pool overflow"));
1994 pool
->literals
[entry
].exp
= *exp
;
1995 pool
->next_free_entry
+= 1;
1996 if (exp
->X_op
== O_big
)
1998 /* PR 16688: Bignums are held in a single global array. We must
1999 copy and preserve that value now, before it is overwritten. */
2000 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
2002 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
2003 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2006 pool
->literals
[entry
].bignum
= NULL
;
2009 exp
->X_op
= O_symbol
;
2010 exp
->X_add_number
= ((int) entry
) * size
;
2011 exp
->X_add_symbol
= pool
->symbol
;
2016 /* Can't use symbol_new here, so have to create a symbol and then at
2017 a later date assign it a value. That's what these functions do. */
2020 symbol_locate (symbolS
* symbolP
,
2021 const char *name
,/* It is copied, the caller can modify. */
2022 segT segment
, /* Segment identifier (SEG_<something>). */
2023 valueT valu
, /* Symbol value. */
2024 fragS
* frag
) /* Associated fragment. */
2027 char *preserved_copy_of_name
;
2029 name_length
= strlen (name
) + 1; /* +1 for \0. */
2030 obstack_grow (¬es
, name
, name_length
);
2031 preserved_copy_of_name
= obstack_finish (¬es
);
2033 #ifdef tc_canonicalize_symbol_name
2034 preserved_copy_of_name
=
2035 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2038 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2040 S_SET_SEGMENT (symbolP
, segment
);
2041 S_SET_VALUE (symbolP
, valu
);
2042 symbol_clear_list_pointers (symbolP
);
2044 symbol_set_frag (symbolP
, frag
);
2046 /* Link to end of symbol chain. */
2048 extern int symbol_table_frozen
;
2050 if (symbol_table_frozen
)
2054 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
2056 obj_symbol_new_hook (symbolP
);
2058 #ifdef tc_symbol_new_hook
2059 tc_symbol_new_hook (symbolP
);
2063 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2064 #endif /* DEBUG_SYMS */
2069 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2076 for (align
= 2; align
<= 4; align
++)
2078 int size
= 1 << align
;
2080 pool
= find_literal_pool (size
);
2081 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
2084 /* Align pool as you have word accesses.
2085 Only make a frag if we have to. */
2087 frag_align (align
, 0, 0);
2089 mapping_state (MAP_DATA
);
2091 record_alignment (now_seg
, align
);
2093 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2095 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2096 (valueT
) frag_now_fix (), frag_now
);
2097 symbol_table_insert (pool
->symbol
);
2099 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2101 expressionS
* exp
= & pool
->literals
[entry
].exp
;
2103 if (exp
->X_op
== O_big
)
2105 /* PR 16688: Restore the global bignum value. */
2106 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
2107 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
2108 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2111 /* First output the expression in the instruction to the pool. */
2112 emit_expr (exp
, size
); /* .word|.xword */
2114 if (exp
->X_op
== O_big
)
2116 free (pool
->literals
[entry
].bignum
);
2117 pool
->literals
[entry
].bignum
= NULL
;
2121 /* Mark the pool as empty. */
2122 pool
->next_free_entry
= 0;
2123 pool
->symbol
= NULL
;
2127 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2128 /* Forward declarations for functions below, in the MD interface
2130 static struct reloc_table_entry
* find_reloc_table_entry (char **);
2132 /* Directives: Data. */
2133 /* N.B. the support for relocation suffix in this directive needs to be
2134 implemented properly. */
2137 s_aarch64_cons (int nbytes
)
2141 #ifdef md_flush_pending_output
2142 md_flush_pending_output ();
2145 if (is_it_end_of_statement ())
2147 demand_empty_rest_of_line ();
2151 #ifdef md_cons_align
2152 md_cons_align (nbytes
);
2155 mapping_state (MAP_DATA
);
2158 struct reloc_table_entry
*reloc
;
2162 if (exp
.X_op
!= O_symbol
)
2163 emit_expr (&exp
, (unsigned int) nbytes
);
2166 skip_past_char (&input_line_pointer
, '#');
2167 if (skip_past_char (&input_line_pointer
, ':'))
2169 reloc
= find_reloc_table_entry (&input_line_pointer
);
2171 as_bad (_("unrecognized relocation suffix"));
2173 as_bad (_("unimplemented relocation suffix"));
2174 ignore_rest_of_line ();
2178 emit_expr (&exp
, (unsigned int) nbytes
);
2181 while (*input_line_pointer
++ == ',');
2183 /* Put terminator back into stream. */
2184 input_line_pointer
--;
2185 demand_empty_rest_of_line ();
2190 /* Forward declarations for functions below, in the MD interface
2192 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2194 /* Mark symbol that it follows a variant PCS convention. */
2197 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2203 elf_symbol_type
*elfsym
;
2205 c
= get_symbol_name (&name
);
2207 as_bad (_("Missing symbol name in directive"));
2208 sym
= symbol_find_or_make (name
);
2209 restore_line_pointer (c
);
2210 demand_empty_rest_of_line ();
2211 bfdsym
= symbol_get_bfdsym (sym
);
2212 elfsym
= elf_symbol_from (bfdsym
);
2213 gas_assert (elfsym
);
2214 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2216 #endif /* OBJ_ELF */
2218 /* Output a 32-bit word, but mark as an instruction. */
2221 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2226 #ifdef md_flush_pending_output
2227 md_flush_pending_output ();
2230 if (is_it_end_of_statement ())
2232 demand_empty_rest_of_line ();
2236 /* Sections are assumed to start aligned. In executable section, there is no
2237 MAP_DATA symbol pending. So we only align the address during
2238 MAP_DATA --> MAP_INSN transition.
2239 For other sections, this is not guaranteed. */
2240 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2241 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2242 frag_align_code (2, 0);
2245 mapping_state (MAP_INSN
);
2251 if (exp
.X_op
!= O_constant
)
2253 as_bad (_("constant expression required"));
2254 ignore_rest_of_line ();
2258 if (target_big_endian
)
2260 unsigned int val
= exp
.X_add_number
;
2261 exp
.X_add_number
= SWAP_32 (val
);
2263 emit_expr (&exp
, INSN_SIZE
);
2266 while (*input_line_pointer
++ == ',');
2268 dwarf2_emit_insn (n
* INSN_SIZE
);
2270 /* Put terminator back into stream. */
2271 input_line_pointer
--;
2272 demand_empty_rest_of_line ();
2276 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2278 demand_empty_rest_of_line ();
2279 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2280 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2284 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2287 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2293 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2294 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2296 demand_empty_rest_of_line ();
2299 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2302 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2306 /* Since we're just labelling the code, there's no need to define a
2309 /* Make sure there is enough room in this frag for the following
2310 blr. This trick only works if the blr follows immediately after
2311 the .tlsdesc directive. */
2313 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2314 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2316 demand_empty_rest_of_line ();
2319 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2322 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2328 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2329 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2331 demand_empty_rest_of_line ();
2333 #endif /* OBJ_ELF */
2337 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2344 if (exp
.X_op
== O_symbol
)
2345 exp
.X_op
= O_secrel
;
2347 emit_expr (&exp
, 4);
2349 while (*input_line_pointer
++ == ',');
2351 input_line_pointer
--;
2352 demand_empty_rest_of_line ();
2356 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2360 exp
.X_op
= O_secrel
;
2361 exp
.X_add_symbol
= symbol
;
2362 exp
.X_add_number
= 0;
2363 emit_expr (&exp
, size
);
2367 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2374 if (exp
.X_op
== O_symbol
)
2375 exp
.X_op
= O_secidx
;
2377 emit_expr (&exp
, 2);
2379 while (*input_line_pointer
++ == ',');
2381 input_line_pointer
--;
2382 demand_empty_rest_of_line ();
2386 static void s_aarch64_arch (int);
2387 static void s_aarch64_cpu (int);
2388 static void s_aarch64_arch_extension (int);
2390 /* This table describes all the machine specific pseudo-ops the assembler
2391 has to support. The fields are:
2392 pseudo-op name without dot
2393 function to call to execute this pseudo-op
2394 Integer arg to pass to the function. */
2396 const pseudo_typeS md_pseudo_table
[] = {
2397 /* Never called because '.req' does not start a line. */
2399 {"unreq", s_unreq
, 0},
2401 {"even", s_even
, 0},
2402 {"ltorg", s_ltorg
, 0},
2403 {"pool", s_ltorg
, 0},
2404 {"cpu", s_aarch64_cpu
, 0},
2405 {"arch", s_aarch64_arch
, 0},
2406 {"arch_extension", s_aarch64_arch_extension
, 0},
2407 {"inst", s_aarch64_inst
, 0},
2408 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2410 {"tlsdescadd", s_tlsdescadd
, 0},
2411 {"tlsdesccall", s_tlsdesccall
, 0},
2412 {"tlsdescldr", s_tlsdescldr
, 0},
2413 {"variant_pcs", s_variant_pcs
, 0},
2415 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2416 {"word", s_aarch64_cons
, 4},
2417 {"long", s_aarch64_cons
, 4},
2418 {"xword", s_aarch64_cons
, 8},
2419 {"dword", s_aarch64_cons
, 8},
2422 {"secrel32", s_secrel
, 0},
2423 {"secidx", s_secidx
, 0},
2425 {"float16", float_cons
, 'h'},
2426 {"bfloat16", float_cons
, 'b'},
2431 /* Check whether STR points to a register name followed by a comma or the
2432 end of line; REG_TYPE indicates which register types are checked
2433 against. Return TRUE if STR is such a register name; otherwise return
2434 FALSE. The function does not intend to produce any diagnostics, but since
2435 the register parser aarch64_reg_parse, which is called by this function,
2436 does produce diagnostics, we call clear_error to clear any diagnostics
2437 that may be generated by aarch64_reg_parse.
2438 Also, the function returns FALSE directly if there is any user error
2439 present at the function entry. This prevents the existing diagnostics
2440 state from being spoiled.
2441 The function currently serves parse_constant_immediate and
2442 parse_big_immediate only. */
2444 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2446 const reg_entry
*reg
;
2448 /* Prevent the diagnostics state from being spoiled. */
2452 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2454 /* Clear the parsing error that may be set by the reg parser. */
2460 skip_whitespace (str
);
2461 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2467 /* Parser functions used exclusively in instruction operands. */
2469 /* Parse an immediate expression which may not be constant.
2471 To prevent the expression parser from pushing a register name
2472 into the symbol table as an undefined symbol, firstly a check is
2473 done to find out whether STR is a register of type REG_TYPE followed
2474 by a comma or the end of line. Return FALSE if STR is such a string. */
2477 parse_immediate_expression (char **str
, expressionS
*exp
,
2478 aarch64_reg_type reg_type
)
2480 if (reg_name_p (*str
, reg_type
))
2482 set_recoverable_error (_("immediate operand required"));
2486 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2488 if (exp
->X_op
== O_absent
)
2490 set_fatal_syntax_error (_("missing immediate expression"));
2497 /* Constant immediate-value read function for use in insn parsing.
2498 STR points to the beginning of the immediate (with the optional
2499 leading #); *VAL receives the value. REG_TYPE says which register
2500 names should be treated as registers rather than as symbolic immediates.
2502 Return TRUE on success; otherwise return FALSE. */
2505 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2509 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2512 if (exp
.X_op
!= O_constant
)
2514 set_syntax_error (_("constant expression required"));
2518 *val
= exp
.X_add_number
;
2523 encode_imm_float_bits (uint32_t imm
)
2525 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2526 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2529 /* Return TRUE if the single-precision floating-point value encoded in IMM
2530 can be expressed in the AArch64 8-bit signed floating-point format with
2531 3-bit exponent and normalized 4 bits of precision; in other words, the
2532 floating-point value must be expressable as
2533 (+/-) n / 16 * power (2, r)
2534 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2537 aarch64_imm_float_p (uint32_t imm
)
2539 /* If a single-precision floating-point value has the following bit
2540 pattern, it can be expressed in the AArch64 8-bit floating-point
2543 3 32222222 2221111111111
2544 1 09876543 21098765432109876543210
2545 n Eeeeeexx xxxx0000000000000000000
2547 where n, e and each x are either 0 or 1 independently, with
2552 /* Prepare the pattern for 'Eeeeee'. */
2553 if (((imm
>> 30) & 0x1) == 0)
2554 pattern
= 0x3e000000;
2556 pattern
= 0x40000000;
2558 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2559 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2562 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2563 as an IEEE float without any loss of precision. Store the value in
2567 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2569 /* If a double-precision floating-point value has the following bit
2570 pattern, it can be expressed in a float:
2572 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2573 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2574 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2576 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2577 if Eeee_eeee != 1111_1111
2579 where n, e, s and S are either 0 or 1 independently and where ~ is the
2583 uint32_t high32
= imm
>> 32;
2584 uint32_t low32
= imm
;
2586 /* Lower 29 bits need to be 0s. */
2587 if ((imm
& 0x1fffffff) != 0)
2590 /* Prepare the pattern for 'Eeeeeeeee'. */
2591 if (((high32
>> 30) & 0x1) == 0)
2592 pattern
= 0x38000000;
2594 pattern
= 0x40000000;
2597 if ((high32
& 0x78000000) != pattern
)
2600 /* Check Eeee_eeee != 1111_1111. */
2601 if ((high32
& 0x7ff00000) == 0x47f00000)
2604 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2605 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2606 | (low32
>> 29)); /* 3 S bits. */
2610 /* Return true if we should treat OPERAND as a double-precision
2611 floating-point operand rather than a single-precision one. */
2613 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2615 /* Check for unsuffixed SVE registers, which are allowed
2616 for LDR and STR but not in instructions that require an
2617 immediate. We get better error messages if we arbitrarily
2618 pick one size, parse the immediate normally, and then
2619 report the match failure in the normal way. */
2620 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2621 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2624 /* Parse a floating-point immediate. Return TRUE on success and return the
2625 value in *IMMED in the format of IEEE754 single-precision encoding.
2626 *CCP points to the start of the string; DP_P is TRUE when the immediate
2627 is expected to be in double-precision (N.B. this only matters when
2628 hexadecimal representation is involved). REG_TYPE says which register
2629 names should be treated as registers rather than as symbolic immediates.
2631 This routine accepts any IEEE float; it is up to the callers to reject
2635 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2636 aarch64_reg_type reg_type
)
2640 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2642 unsigned fpword
= 0;
2645 skip_past_char (&str
, '#');
2648 skip_whitespace (fpnum
);
2650 if (startswith (fpnum
, "0x"))
2652 /* Support the hexadecimal representation of the IEEE754 encoding.
2653 Double-precision is expected when DP_P is TRUE, otherwise the
2654 representation should be in single-precision. */
2655 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2660 if (!can_convert_double_to_float (val
, &fpword
))
2663 else if ((uint64_t) val
> 0xffffffff)
2670 else if (reg_name_p (str
, reg_type
))
2672 set_recoverable_error (_("immediate operand required"));
2680 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2683 /* Our FP word must be 32 bits (single-precision FP). */
2684 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2686 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2696 set_fatal_syntax_error (_("invalid floating-point constant"));
2700 /* Less-generic immediate-value read function with the possibility of loading
2701 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2704 To prevent the expression parser from pushing a register name into the
2705 symbol table as an undefined symbol, a check is firstly done to find
2706 out whether STR is a register of type REG_TYPE followed by a comma or
2707 the end of line. Return FALSE if STR is such a register. */
2710 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2714 if (reg_name_p (ptr
, reg_type
))
2716 set_syntax_error (_("immediate operand required"));
2720 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2722 if (inst
.reloc
.exp
.X_op
== O_constant
)
2723 *imm
= inst
.reloc
.exp
.X_add_number
;
2730 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2731 if NEED_LIBOPCODES is non-zero, the fixup will need
2732 assistance from the libopcodes. */
2735 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2736 const aarch64_opnd_info
*operand
,
2737 int need_libopcodes_p
)
2739 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2740 reloc
->opnd
= operand
->type
;
2741 if (need_libopcodes_p
)
2742 reloc
->need_libopcodes_p
= 1;
2745 /* Return TRUE if the instruction needs to be fixed up later internally by
2746 the GAS; otherwise return FALSE. */
2749 aarch64_gas_internal_fixup_p (void)
2751 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2754 /* Assign the immediate value to the relevant field in *OPERAND if
2755 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2756 needs an internal fixup in a later stage.
2757 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2758 IMM.VALUE that may get assigned with the constant. */
2760 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2761 aarch64_opnd_info
*operand
,
2763 int need_libopcodes_p
,
2766 if (reloc
->exp
.X_op
== O_constant
)
2769 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2771 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2772 reloc
->type
= BFD_RELOC_UNUSED
;
2776 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2777 /* Tell libopcodes to ignore this operand or not. This is helpful
2778 when one of the operands needs to be fixed up later but we need
2779 libopcodes to check the other operands. */
2780 operand
->skip
= skip_p
;
2784 /* Relocation modifiers. Each entry in the table contains the textual
2785 name for the relocation which may be placed before a symbol used as
2786 a load/store offset, or add immediate. It must be surrounded by a
2787 leading and trailing colon, for example:
2789 ldr x0, [x1, #:rello:varsym]
2790 add x0, x1, #:rello:varsym */
2792 struct reloc_table_entry
2796 bfd_reloc_code_real_type adr_type
;
2797 bfd_reloc_code_real_type adrp_type
;
2798 bfd_reloc_code_real_type movw_type
;
2799 bfd_reloc_code_real_type add_type
;
2800 bfd_reloc_code_real_type ldst_type
;
2801 bfd_reloc_code_real_type ld_literal_type
;
2804 static struct reloc_table_entry reloc_table
[] =
2806 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2811 BFD_RELOC_AARCH64_ADD_LO12
,
2812 BFD_RELOC_AARCH64_LDST_LO12
,
2815 /* Higher 21 bits of pc-relative page offset: ADRP */
2818 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2824 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2827 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2833 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2837 BFD_RELOC_AARCH64_MOVW_G0
,
2842 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2846 BFD_RELOC_AARCH64_MOVW_G0_S
,
2851 /* Less significant bits 0-15 of address/value: MOVK, no check */
2855 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2860 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2864 BFD_RELOC_AARCH64_MOVW_G1
,
2869 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2873 BFD_RELOC_AARCH64_MOVW_G1_S
,
2878 /* Less significant bits 16-31 of address/value: MOVK, no check */
2882 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2887 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2891 BFD_RELOC_AARCH64_MOVW_G2
,
2896 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2900 BFD_RELOC_AARCH64_MOVW_G2_S
,
2905 /* Less significant bits 32-47 of address/value: MOVK, no check */
2909 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2914 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2918 BFD_RELOC_AARCH64_MOVW_G3
,
2923 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2927 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2932 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2936 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2941 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2945 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2950 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2954 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2959 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2963 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2968 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2972 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2977 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2981 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2986 /* Get to the page containing GOT entry for a symbol. */
2989 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2993 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2995 /* 12 bit offset into the page containing GOT entry for that symbol. */
3001 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
3004 /* 0-15 bits of address/value: MOVk, no check. */
3008 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
3013 /* Most significant bits 16-31 of address/value: MOVZ. */
3017 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
3022 /* 15 bit offset into the page containing GOT entry for that symbol. */
3028 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
3031 /* Get to the page containing GOT TLS entry for a symbol */
3032 {"gottprel_g0_nc", 0,
3035 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
3040 /* Get to the page containing GOT TLS entry for a symbol */
3044 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
3049 /* Get to the page containing GOT TLS entry for a symbol */
3051 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
3052 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
3058 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3063 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
3067 /* Lower 16 bits address/value: MOVk. */
3071 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
3076 /* Most significant bits 16-31 of address/value: MOVZ. */
3080 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
3085 /* Get to the page containing GOT TLS entry for a symbol */
3087 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
3088 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
3092 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
3094 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3099 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
3100 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
3103 /* Get to the page containing GOT TLS entry for a symbol.
3104 The same as GD, we allocate two consecutive GOT slots
3105 for module index and module offset, the only difference
3106 with GD is the module offset should be initialized to
3107 zero without any outstanding runtime relocation. */
3109 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
3110 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
3116 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3117 {"tlsldm_lo12_nc", 0,
3121 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
3125 /* 12 bit offset into the module TLS base address. */
3130 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
3131 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
3134 /* Same as dtprel_lo12, no overflow check. */
3135 {"dtprel_lo12_nc", 0,
3139 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
3140 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3143 /* bits[23:12] of offset to the module TLS base address. */
3148 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3152 /* bits[15:0] of offset to the module TLS base address. */
3156 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3161 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3165 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3170 /* bits[31:16] of offset to the module TLS base address. */
3174 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3179 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3183 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3188 /* bits[47:32] of offset to the module TLS base address. */
3192 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3197 /* Lower 16 bit offset into GOT entry for a symbol */
3198 {"tlsdesc_off_g0_nc", 0,
3201 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3206 /* Higher 16 bit offset into GOT entry for a symbol */
3207 {"tlsdesc_off_g1", 0,
3210 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3215 /* Get to the page containing GOT TLS entry for a symbol */
3218 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3222 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3224 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3225 {"gottprel_lo12", 0,
3230 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3233 /* Get tp offset for a symbol. */
3238 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3242 /* Get tp offset for a symbol. */
3247 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3248 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3251 /* Get tp offset for a symbol. */
3256 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3260 /* Get tp offset for a symbol. */
3261 {"tprel_lo12_nc", 0,
3265 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3266 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3269 /* Most significant bits 32-47 of address/value: MOVZ. */
3273 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3278 /* Most significant bits 16-31 of address/value: MOVZ. */
3282 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3287 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3291 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3296 /* Most significant bits 0-15 of address/value: MOVZ. */
3300 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3305 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3309 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3314 /* 15bit offset from got entry to base address of GOT table. */
3320 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3323 /* 14bit offset from got entry to base address of GOT table. */
3329 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3333 /* Given the address of a pointer pointing to the textual name of a
3334 relocation as may appear in assembler source, attempt to find its
3335 details in reloc_table. The pointer will be updated to the character
3336 after the trailing colon. On failure, NULL will be returned;
3337 otherwise return the reloc_table_entry. */
3339 static struct reloc_table_entry
*
3340 find_reloc_table_entry (char **str
)
3343 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3345 int length
= strlen (reloc_table
[i
].name
);
3347 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3348 && (*str
)[length
] == ':')
3350 *str
+= (length
+ 1);
3351 return &reloc_table
[i
];
3358 /* Returns 0 if the relocation should never be forced,
3359 1 if the relocation must be forced, and -1 if either
3363 aarch64_force_reloc (unsigned int type
)
3367 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3368 /* Perform these "immediate" internal relocations
3369 even if the symbol is extern or weak. */
3372 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3373 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3374 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3375 /* Pseudo relocs that need to be fixed up according to
3379 case BFD_RELOC_AARCH64_ADD_LO12
:
3380 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3381 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3382 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3383 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3384 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3385 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3386 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3387 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3388 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3389 case BFD_RELOC_AARCH64_LDST128_LO12
:
3390 case BFD_RELOC_AARCH64_LDST16_LO12
:
3391 case BFD_RELOC_AARCH64_LDST32_LO12
:
3392 case BFD_RELOC_AARCH64_LDST64_LO12
:
3393 case BFD_RELOC_AARCH64_LDST8_LO12
:
3394 case BFD_RELOC_AARCH64_LDST_LO12
:
3395 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3396 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3397 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3398 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3399 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3400 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3401 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3402 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3403 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3404 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3405 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3406 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3407 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3408 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3409 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3410 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3411 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3412 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3413 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3414 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3415 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3416 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3417 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3418 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3419 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3420 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3421 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3422 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3423 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3424 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3425 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3426 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3427 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3428 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3429 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3430 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3431 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3432 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3433 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3434 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3435 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3436 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3437 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3438 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3439 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3440 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3441 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3442 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3443 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3444 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3445 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3446 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3447 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3448 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3449 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3450 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3451 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3452 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3453 /* Always leave these relocations for the linker. */
3462 aarch64_force_relocation (struct fix
*fixp
)
3464 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3467 return generic_force_reloc (fixp
);
3471 /* Mode argument to parse_shift and parser_shifter_operand. */
3472 enum parse_shift_mode
3474 SHIFTED_NONE
, /* no shifter allowed */
3475 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3477 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3479 SHIFTED_LSL
, /* bare "lsl #n" */
3480 SHIFTED_MUL
, /* bare "mul #n" */
3481 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3482 SHIFTED_MUL_VL
, /* "mul vl" */
3483 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3486 /* Parse a <shift> operator on an AArch64 data processing instruction.
3487 Return TRUE on success; otherwise return FALSE. */
3489 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3491 const struct aarch64_name_value_pair
*shift_op
;
3492 enum aarch64_modifier_kind kind
;
3498 for (p
= *str
; ISALPHA (*p
); p
++)
3503 set_syntax_error (_("shift expression expected"));
3507 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3509 if (shift_op
== NULL
)
3511 set_syntax_error (_("shift operator expected"));
3515 kind
= aarch64_get_operand_modifier (shift_op
);
3517 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3519 set_syntax_error (_("invalid use of 'MSL'"));
3523 if (kind
== AARCH64_MOD_MUL
3524 && mode
!= SHIFTED_MUL
3525 && mode
!= SHIFTED_MUL_VL
)
3527 set_syntax_error (_("invalid use of 'MUL'"));
3533 case SHIFTED_LOGIC_IMM
:
3534 if (aarch64_extend_operator_p (kind
))
3536 set_syntax_error (_("extending shift is not permitted"));
3541 case SHIFTED_ARITH_IMM
:
3542 if (kind
== AARCH64_MOD_ROR
)
3544 set_syntax_error (_("'ROR' shift is not permitted"));
3550 if (kind
!= AARCH64_MOD_LSL
)
3552 set_syntax_error (_("only 'LSL' shift is permitted"));
3558 if (kind
!= AARCH64_MOD_MUL
)
3560 set_syntax_error (_("only 'MUL' is permitted"));
3565 case SHIFTED_MUL_VL
:
3566 /* "MUL VL" consists of two separate tokens. Require the first
3567 token to be "MUL" and look for a following "VL". */
3568 if (kind
== AARCH64_MOD_MUL
)
3570 skip_whitespace (p
);
3571 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3574 kind
= AARCH64_MOD_MUL_VL
;
3578 set_syntax_error (_("only 'MUL VL' is permitted"));
3581 case SHIFTED_REG_OFFSET
:
3582 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3583 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3585 set_fatal_syntax_error
3586 (_("invalid shift for the register offset addressing mode"));
3591 case SHIFTED_LSL_MSL
:
3592 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3594 set_syntax_error (_("invalid shift operator"));
3603 /* Whitespace can appear here if the next thing is a bare digit. */
3604 skip_whitespace (p
);
3606 /* Parse shift amount. */
3608 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3609 exp
.X_op
= O_absent
;
3612 if (is_immediate_prefix (*p
))
3617 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3619 if (kind
== AARCH64_MOD_MUL_VL
)
3620 /* For consistency, give MUL VL the same shift amount as an implicit
3622 operand
->shifter
.amount
= 1;
3623 else if (exp
.X_op
== O_absent
)
3625 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3627 set_syntax_error (_("missing shift amount"));
3630 operand
->shifter
.amount
= 0;
3632 else if (exp
.X_op
!= O_constant
)
3634 set_syntax_error (_("constant shift amount required"));
3637 /* For parsing purposes, MUL #n has no inherent range. The range
3638 depends on the operand and will be checked by operand-specific
3640 else if (kind
!= AARCH64_MOD_MUL
3641 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3643 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3648 operand
->shifter
.amount
= exp
.X_add_number
;
3649 operand
->shifter
.amount_present
= 1;
3652 operand
->shifter
.operator_present
= 1;
3653 operand
->shifter
.kind
= kind
;
3659 /* Parse a <shifter_operand> for a data processing instruction:
3662 #<immediate>, LSL #imm
3664 Validation of immediate operands is deferred to md_apply_fix.
3666 Return TRUE on success; otherwise return FALSE. */
3669 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3670 enum parse_shift_mode mode
)
3674 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3679 /* Accept an immediate expression. */
3680 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3684 /* Accept optional LSL for arithmetic immediate values. */
3685 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3686 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3689 /* Not accept any shifter for logical immediate values. */
3690 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3691 && parse_shift (&p
, operand
, mode
))
3693 set_syntax_error (_("unexpected shift operator"));
3701 /* Parse a <shifter_operand> for a data processing instruction:
3706 #<immediate>, LSL #imm
3708 where <shift> is handled by parse_shift above, and the last two
3709 cases are handled by the function above.
3711 Validation of immediate operands is deferred to md_apply_fix.
3713 Return TRUE on success; otherwise return FALSE. */
3716 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3717 enum parse_shift_mode mode
)
3719 const reg_entry
*reg
;
3720 aarch64_opnd_qualifier_t qualifier
;
3721 enum aarch64_operand_class opd_class
3722 = aarch64_get_operand_class (operand
->type
);
3724 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3727 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3729 set_syntax_error (_("unexpected register in the immediate operand"));
3733 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR
))
3735 set_expected_reg_error (REG_TYPE_R_ZR
, reg
, 0);
3739 operand
->reg
.regno
= reg
->number
;
3740 operand
->qualifier
= qualifier
;
3742 /* Accept optional shift operation on register. */
3743 if (! skip_past_comma (str
))
3746 if (! parse_shift (str
, operand
, mode
))
3751 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3754 (_("integer register expected in the extended/shifted operand "
3759 /* We have a shifted immediate variable. */
3760 return parse_shifter_operand_imm (str
, operand
, mode
);
3763 /* Return TRUE on success; return FALSE otherwise. */
3766 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3767 enum parse_shift_mode mode
)
3771 /* Determine if we have the sequence of characters #: or just :
3772 coming next. If we do, then we check for a :rello: relocation
3773 modifier. If we don't, punt the whole lot to
3774 parse_shifter_operand. */
3776 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3778 struct reloc_table_entry
*entry
;
3786 /* Try to parse a relocation. Anything else is an error. */
3787 if (!(entry
= find_reloc_table_entry (str
)))
3789 set_syntax_error (_("unknown relocation modifier"));
3793 if (entry
->add_type
== 0)
3796 (_("this relocation modifier is not allowed on this instruction"));
3800 /* Save str before we decompose it. */
3803 /* Next, we parse the expression. */
3804 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3808 /* Record the relocation type (use the ADD variant here). */
3809 inst
.reloc
.type
= entry
->add_type
;
3810 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3812 /* If str is empty, we've reached the end, stop here. */
3816 /* Otherwise, we have a shifted reloc modifier, so rewind to
3817 recover the variable name and continue parsing for the shifter. */
3819 return parse_shifter_operand_imm (str
, operand
, mode
);
3822 return parse_shifter_operand (str
, operand
, mode
);
3825 /* Parse all forms of an address expression. Information is written
3826 to *OPERAND and/or inst.reloc.
3828 The A64 instruction set has the following addressing modes:
3831 [base] // in SIMD ld/st structure
3832 [base{,#0}] // in ld/st exclusive
3834 [base,Xm{,LSL #imm}]
3835 [base,Xm,SXTX {#imm}]
3836 [base,Wm,(S|U)XTW {#imm}]
3838 [base]! // in ldraa/ldrab exclusive
3842 [base],Xm // in SIMD ld/st structure
3843 PC-relative (literal)
3847 [base,Zm.D{,LSL #imm}]
3848 [base,Zm.S,(S|U)XTW {#imm}]
3849 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3853 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3854 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3855 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3857 (As a convenience, the notation "=immediate" is permitted in conjunction
3858 with the pc-relative literal load instructions to automatically place an
3859 immediate value or symbolic address in a nearby literal pool and generate
3860 a hidden label which references it.)
3862 Upon a successful parsing, the address structure in *OPERAND will be
3863 filled in the following way:
3865 .base_regno = <base>
3866 .offset.is_reg // 1 if the offset is a register
3868 .offset.regno = <Rm>
3870 For different addressing modes defined in the A64 ISA:
3873 .pcrel=0; .preind=1; .postind=0; .writeback=0
3875 .pcrel=0; .preind=1; .postind=0; .writeback=1
3877 .pcrel=0; .preind=0; .postind=1; .writeback=1
3878 PC-relative (literal)
3879 .pcrel=1; .preind=1; .postind=0; .writeback=0
3881 The shift/extension information, if any, will be stored in .shifter.
3882 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3883 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3884 corresponding register.
3886 BASE_TYPE says which types of base register should be accepted and
3887 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3888 is the type of shifter that is allowed for immediate offsets,
3889 or SHIFTED_NONE if none.
3891 In all other respects, it is the caller's responsibility to check
3892 for addressing modes not supported by the instruction, and to set
3896 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3897 aarch64_opnd_qualifier_t
*base_qualifier
,
3898 aarch64_opnd_qualifier_t
*offset_qualifier
,
3899 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3900 enum parse_shift_mode imm_shift_mode
)
3903 const reg_entry
*reg
;
3904 expressionS
*exp
= &inst
.reloc
.exp
;
3906 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3907 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3908 if (! skip_past_char (&p
, '['))
3910 /* =immediate or label. */
3911 operand
->addr
.pcrel
= 1;
3912 operand
->addr
.preind
= 1;
3914 /* #:<reloc_op>:<symbol> */
3915 skip_past_char (&p
, '#');
3916 if (skip_past_char (&p
, ':'))
3918 bfd_reloc_code_real_type ty
;
3919 struct reloc_table_entry
*entry
;
3921 /* Try to parse a relocation modifier. Anything else is
3923 entry
= find_reloc_table_entry (&p
);
3926 set_syntax_error (_("unknown relocation modifier"));
3930 switch (operand
->type
)
3932 case AARCH64_OPND_ADDR_PCREL21
:
3934 ty
= entry
->adr_type
;
3938 ty
= entry
->ld_literal_type
;
3945 (_("this relocation modifier is not allowed on this "
3951 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3953 set_syntax_error (_("invalid relocation expression"));
3956 /* #:<reloc_op>:<expr> */
3957 /* Record the relocation type. */
3958 inst
.reloc
.type
= ty
;
3959 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3963 if (skip_past_char (&p
, '='))
3964 /* =immediate; need to generate the literal in the literal pool. */
3965 inst
.gen_lit_pool
= 1;
3967 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3969 set_syntax_error (_("invalid address"));
3980 bool alpha_base_p
= ISALPHA (*p
);
3981 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3982 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3985 && aarch64_check_reg_type (reg
, REG_TYPE_R_SP
)
3986 && *base_qualifier
== AARCH64_OPND_QLF_W
)
3987 set_syntax_error (_("expected a 64-bit base register"));
3988 else if (alpha_base_p
)
3989 set_syntax_error (_("invalid base register"));
3991 set_syntax_error (_("expected a base register"));
3994 operand
->addr
.base_regno
= reg
->number
;
3997 if (skip_past_comma (&p
))
4000 operand
->addr
.preind
= 1;
4002 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
4005 if (!aarch64_check_reg_type (reg
, offset_type
))
4007 set_syntax_error (_("invalid offset register"));
4012 operand
->addr
.offset
.regno
= reg
->number
;
4013 operand
->addr
.offset
.is_reg
= 1;
4014 /* Shifted index. */
4015 if (skip_past_comma (&p
))
4018 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
4019 /* Use the diagnostics set in parse_shift, so not set new
4020 error message here. */
4024 [base,Xm] # For vector plus scalar SVE2 indexing.
4025 [base,Xm{,LSL #imm}]
4026 [base,Xm,SXTX {#imm}]
4027 [base,Wm,(S|U)XTW {#imm}] */
4028 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
4029 || operand
->shifter
.kind
== AARCH64_MOD_LSL
4030 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
4032 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
4034 set_syntax_error (_("invalid use of 32-bit register offset"));
4037 if (aarch64_get_qualifier_esize (*base_qualifier
)
4038 != aarch64_get_qualifier_esize (*offset_qualifier
)
4039 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
4040 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
4041 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
4043 set_syntax_error (_("offset has different size from base"));
4047 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
4049 set_syntax_error (_("invalid use of 64-bit register offset"));
4055 /* [Xn,#:<reloc_op>:<symbol> */
4056 skip_past_char (&p
, '#');
4057 if (skip_past_char (&p
, ':'))
4059 struct reloc_table_entry
*entry
;
4061 /* Try to parse a relocation modifier. Anything else is
4063 if (!(entry
= find_reloc_table_entry (&p
)))
4065 set_syntax_error (_("unknown relocation modifier"));
4069 if (entry
->ldst_type
== 0)
4072 (_("this relocation modifier is not allowed on this "
4077 /* [Xn,#:<reloc_op>: */
4078 /* We now have the group relocation table entry corresponding to
4079 the name in the assembler source. Next, we parse the
4081 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4083 set_syntax_error (_("invalid relocation expression"));
4087 /* [Xn,#:<reloc_op>:<expr> */
4088 /* Record the load/store relocation type. */
4089 inst
.reloc
.type
= entry
->ldst_type
;
4090 inst
.reloc
.pc_rel
= entry
->pc_rel
;
4094 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4096 set_syntax_error (_("invalid expression in the address"));
4100 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
4101 /* [Xn,<expr>,<shifter> */
4102 if (! parse_shift (&p
, operand
, imm_shift_mode
))
4108 if (! skip_past_char (&p
, ']'))
4110 set_syntax_error (_("']' expected"));
4114 if (skip_past_char (&p
, '!'))
4116 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
4118 set_syntax_error (_("register offset not allowed in pre-indexed "
4119 "addressing mode"));
4123 operand
->addr
.writeback
= 1;
4125 else if (skip_past_comma (&p
))
4128 operand
->addr
.postind
= 1;
4129 operand
->addr
.writeback
= 1;
4131 if (operand
->addr
.preind
)
4133 set_syntax_error (_("cannot combine pre- and post-indexing"));
4137 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
4141 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4143 set_syntax_error (_("invalid offset register"));
4147 operand
->addr
.offset
.regno
= reg
->number
;
4148 operand
->addr
.offset
.is_reg
= 1;
4150 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4153 set_syntax_error (_("invalid expression in the address"));
4158 /* If at this point neither .preind nor .postind is set, we have a
4159 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4160 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4161 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4163 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4165 if (operand
->addr
.writeback
)
4167 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4169 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4170 operand
->addr
.offset
.is_reg
= 0;
4171 operand
->addr
.offset
.imm
= 0;
4172 operand
->addr
.preind
= 1;
4177 set_syntax_error (_("missing offset in the pre-indexed address"));
4183 operand
->addr
.preind
= 1;
4184 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4186 operand
->addr
.offset
.is_reg
= 1;
4187 operand
->addr
.offset
.regno
= REG_ZR
;
4188 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4192 inst
.reloc
.exp
.X_op
= O_constant
;
4193 inst
.reloc
.exp
.X_add_number
= 0;
4202 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4205 parse_address (char **str
, aarch64_opnd_info
*operand
)
4207 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4208 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4209 REG_TYPE_R64_SP
, REG_TYPE_R_ZR
, SHIFTED_NONE
);
4212 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4213 The arguments have the same meaning as for parse_address_main.
4214 Return TRUE on success. */
4216 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4217 aarch64_opnd_qualifier_t
*base_qualifier
,
4218 aarch64_opnd_qualifier_t
*offset_qualifier
)
4220 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4221 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4225 /* Parse a register X0-X30. The register must be 64-bit and register 31
4228 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4230 const reg_entry
*reg
= parse_reg (str
);
4231 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4233 set_expected_reg_error (REG_TYPE_R_64
, reg
, 0);
4236 operand
->reg
.regno
= reg
->number
;
4237 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4241 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4242 Return TRUE on success; otherwise return FALSE. */
4244 parse_half (char **str
, int *internal_fixup_p
)
4248 skip_past_char (&p
, '#');
4250 gas_assert (internal_fixup_p
);
4251 *internal_fixup_p
= 0;
4255 struct reloc_table_entry
*entry
;
4257 /* Try to parse a relocation. Anything else is an error. */
4260 if (!(entry
= find_reloc_table_entry (&p
)))
4262 set_syntax_error (_("unknown relocation modifier"));
4266 if (entry
->movw_type
== 0)
4269 (_("this relocation modifier is not allowed on this instruction"));
4273 inst
.reloc
.type
= entry
->movw_type
;
4276 *internal_fixup_p
= 1;
4278 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4285 /* Parse an operand for an ADRP instruction:
4287 Return TRUE on success; otherwise return FALSE. */
4290 parse_adrp (char **str
)
4297 struct reloc_table_entry
*entry
;
4299 /* Try to parse a relocation. Anything else is an error. */
4301 if (!(entry
= find_reloc_table_entry (&p
)))
4303 set_syntax_error (_("unknown relocation modifier"));
4307 if (entry
->adrp_type
== 0)
4310 (_("this relocation modifier is not allowed on this instruction"));
4314 inst
.reloc
.type
= entry
->adrp_type
;
4317 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4319 inst
.reloc
.pc_rel
= 1;
4320 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4326 /* Miscellaneous. */
4328 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4329 of SIZE tokens in which index I gives the token for field value I,
4330 or is null if field value I is invalid. If the symbolic operand
4331 can also be given as a 0-based integer, REG_TYPE says which register
4332 names should be treated as registers rather than as symbolic immediates
4333 while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise.
4335 Return true on success, moving *STR past the operand and storing the
4336 field value in *VAL. */
4339 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4340 size_t size
, aarch64_reg_type reg_type
)
4346 /* Match C-like tokens. */
4348 while (ISALNUM (*q
))
4351 for (i
= 0; i
< size
; ++i
)
4353 && strncasecmp (array
[i
], p
, q
- p
) == 0
4354 && array
[i
][q
- p
] == 0)
4361 if (reg_type
== REG_TYPE_MAX
)
4364 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4367 if (exp
.X_op
== O_constant
4368 && (uint64_t) exp
.X_add_number
< size
)
4370 *val
= exp
.X_add_number
;
4375 /* Use the default error for this operand. */
4379 /* Parse an option for a preload instruction. Returns the encoding for the
4380 option, or PARSE_FAIL. */
4383 parse_pldop (char **str
)
4386 const struct aarch64_name_value_pair
*o
;
4389 while (ISALNUM (*q
))
4392 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4400 /* Parse an option for a barrier instruction. Returns the encoding for the
4401 option, or PARSE_FAIL. */
4404 parse_barrier (char **str
)
4407 const struct aarch64_name_value_pair
*o
;
4410 while (ISALPHA (*q
))
4413 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4421 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4422 return 0 if successful. Otherwise return PARSE_FAIL. */
4425 parse_barrier_psb (char **str
,
4426 const struct aarch64_name_value_pair
** hint_opt
)
4429 const struct aarch64_name_value_pair
*o
;
4432 while (ISALPHA (*q
))
4435 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4438 set_fatal_syntax_error
4439 ( _("unknown or missing option to PSB/TSB"));
4443 if (o
->value
!= 0x11)
4445 /* PSB only accepts option name 'CSYNC'. */
4447 (_("the specified option is not accepted for PSB/TSB"));
4456 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4457 return 0 if successful. Otherwise return PARSE_FAIL. */
4460 parse_bti_operand (char **str
,
4461 const struct aarch64_name_value_pair
** hint_opt
)
4464 const struct aarch64_name_value_pair
*o
;
4467 while (ISALPHA (*q
))
4470 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4473 set_fatal_syntax_error
4474 ( _("unknown option to BTI"));
4480 /* Valid BTI operands. */
4488 (_("unknown option to BTI"));
4497 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4498 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4503 Side effect: Update STR with current parse position of success.
4505 FLAGS is as for parse_typed_reg. */
4507 static const reg_entry
*
4508 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4509 aarch64_opnd_qualifier_t
*qualifier
, unsigned int flags
)
4511 struct vector_type_el vectype
;
4512 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4513 PTR_FULL_REG
| flags
);
4517 if (vectype
.type
== NT_invtype
)
4518 *qualifier
= AARCH64_OPND_QLF_NIL
;
4521 *qualifier
= vectype_to_qualifier (&vectype
);
4522 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4529 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4534 Function return TRUE if immediate was found, or FALSE.
4537 parse_sme_immediate (char **str
, int64_t *imm
)
4540 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4547 /* Parse index with selection register and immediate offset:
4552 Return true on success, populating OPND with the parsed index. */
4555 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4557 const reg_entry
*reg
;
4559 if (!skip_past_char (str
, '['))
4561 set_syntax_error (_("expected '['"));
4565 /* The selection register, encoded in the 2-bit Rv field. */
4566 reg
= parse_reg (str
);
4567 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
)
4569 set_syntax_error (_("expected a 32-bit selection register"));
4572 opnd
->index
.regno
= reg
->number
;
4574 if (!skip_past_char (str
, ','))
4576 set_syntax_error (_("missing immediate offset"));
4580 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4582 set_syntax_error (_("expected a constant immediate offset"));
4586 if (skip_past_char (str
, ':'))
4589 if (!parse_sme_immediate (str
, &end
))
4591 set_syntax_error (_("expected a constant immediate offset"));
4594 if (end
< opnd
->index
.imm
)
4596 set_syntax_error (_("the last offset is less than the"
4600 if (end
== opnd
->index
.imm
)
4602 set_syntax_error (_("the last offset is equal to the"
4606 opnd
->index
.countm1
= (uint64_t) end
- opnd
->index
.imm
;
4609 opnd
->group_size
= 0;
4610 if (skip_past_char (str
, ','))
4612 if (strncasecmp (*str
, "vgx2", 4) == 0 && !ISALPHA ((*str
)[4]))
4615 opnd
->group_size
= 2;
4617 else if (strncasecmp (*str
, "vgx4", 4) == 0 && !ISALPHA ((*str
)[4]))
4620 opnd
->group_size
= 4;
4624 set_syntax_error (_("invalid vector group size"));
4629 if (!skip_past_char (str
, ']'))
4631 set_syntax_error (_("expected ']'"));
4638 /* Parse a register of type REG_TYPE that might have an element type
4639 qualifier and that is indexed by two values: a 32-bit register,
4640 followed by an immediate. The ranges of the register and the
4641 immediate vary by opcode and are checked in libopcodes.
4643 Return true on success, populating OPND with information about
4644 the operand and setting QUALIFIER to the register qualifier.
4646 Field format examples:
4648 <Pm>.<T>[<Wv>< #<imm>]
4650 <ZAn><HV>.<T>[<Wv>, #<imm>]
4652 FLAGS is as for parse_typed_reg. */
4655 parse_dual_indexed_reg (char **str
, aarch64_reg_type reg_type
,
4656 struct aarch64_indexed_za
*opnd
,
4657 aarch64_opnd_qualifier_t
*qualifier
,
4660 const reg_entry
*reg
= parse_reg_with_qual (str
, reg_type
, qualifier
, flags
);
4664 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4665 opnd
->regno
= reg
->number
;
4667 return parse_sme_za_index (str
, opnd
);
4670 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4674 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4675 struct aarch64_indexed_za
*opnd
,
4676 aarch64_opnd_qualifier_t
*qualifier
)
4678 if (!skip_past_char (str
, '{'))
4680 set_expected_reglist_error (REG_TYPE_ZATHV
, parse_reg (str
));
4684 if (!parse_dual_indexed_reg (str
, REG_TYPE_ZATHV
, opnd
, qualifier
,
4688 if (!skip_past_char (str
, '}'))
4690 set_syntax_error (_("expected '}'"));
4697 /* Parse list of up to eight 64-bit element tile names separated by commas in
4698 SME's ZERO instruction:
4702 Function returns <mask>:
4704 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4707 parse_sme_zero_mask(char **str
)
4711 aarch64_opnd_qualifier_t qualifier
;
4712 unsigned int ptr_flags
= PTR_IN_REGLIST
;
4718 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4719 &qualifier
, ptr_flags
);
4723 if (reg
->type
== REG_TYPE_ZA
)
4725 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4727 set_syntax_error ("ZA should not have a size suffix");
4730 /* { ZA } is assembled as all-ones immediate. */
4735 int regno
= reg
->number
;
4736 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4738 /* { ZA0.B } is assembled as all-ones immediate. */
4741 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4742 mask
|= 0x55 << regno
;
4743 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4744 mask
|= 0x11 << regno
;
4745 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4746 mask
|= 0x01 << regno
;
4747 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4749 set_syntax_error (_("ZA tile masks do not operate at .Q"
4753 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4755 set_syntax_error (_("missing ZA tile size"));
4760 set_syntax_error (_("invalid ZA tile"));
4764 ptr_flags
|= PTR_GOOD_MATCH
;
4766 while (skip_past_char (&q
, ','));
4772 /* Wraps in curly braces <mask> operand ZERO instruction:
4776 Function returns value of <mask> bit-field.
4779 parse_sme_list_of_64bit_tiles (char **str
)
4783 if (!skip_past_char (str
, '{'))
4785 set_syntax_error (_("expected '{'"));
4789 /* Empty <mask> list is an all-zeros immediate. */
4790 if (!skip_past_char (str
, '}'))
4792 regno
= parse_sme_zero_mask (str
);
4793 if (regno
== PARSE_FAIL
)
4796 if (!skip_past_char (str
, '}'))
4798 set_syntax_error (_("expected '}'"));
4808 /* Parse streaming mode operand for SMSTART and SMSTOP.
4812 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4815 parse_sme_sm_za (char **str
)
4820 while (ISALPHA (*q
))
4824 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4826 set_syntax_error (_("expected SM or ZA operand"));
4831 return TOLOWER (p
[0]);
4834 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4835 Returns the encoding for the option, or PARSE_FAIL.
4837 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4838 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4840 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4841 field, otherwise as a system register.
4845 parse_sys_reg (char **str
, htab_t sys_regs
,
4846 int imple_defined_p
, int pstatefield_p
,
4850 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4851 const aarch64_sys_reg
*o
;
4855 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4856 if (p
< buf
+ (sizeof (buf
) - 1))
4857 *p
++ = TOLOWER (*q
);
4860 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4861 valid system register. This is enforced by construction of the hash
4863 if (p
- buf
!= q
- *str
)
4866 o
= str_hash_find (sys_regs
, buf
);
4869 if (!imple_defined_p
)
4873 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4874 unsigned int op0
, op1
, cn
, cm
, op2
;
4876 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4879 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4881 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4888 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4889 as_bad (_("selected processor does not support PSTATE field "
4892 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4893 o
->value
, o
->flags
, o
->features
))
4894 as_bad (_("selected processor does not support system register "
4896 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4897 as_warn (_("system register name '%s' is deprecated and may be "
4898 "removed in a future release"), buf
);
4908 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4909 for the option, or NULL. */
4911 static const aarch64_sys_ins_reg
*
4912 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4915 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4916 const aarch64_sys_ins_reg
*o
;
4919 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4920 if (p
< buf
+ (sizeof (buf
) - 1))
4921 *p
++ = TOLOWER (*q
);
4924 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4925 valid system register. This is enforced by construction of the hash
4927 if (p
- buf
!= q
- *str
)
4930 o
= str_hash_find (sys_ins_regs
, buf
);
4934 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4935 o
->name
, o
->value
, o
->flags
, 0))
4936 as_bad (_("selected processor does not support system register "
4938 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4939 as_warn (_("system register name '%s' is deprecated and may be "
4940 "removed in a future release"), buf
);
4946 #define po_char_or_fail(chr) do { \
4947 if (! skip_past_char (&str, chr)) \
4951 #define po_reg_or_fail(regtype) do { \
4952 reg = aarch64_reg_parse (&str, regtype, NULL); \
4957 #define po_int_fp_reg_or_fail(reg_type) do { \
4958 reg = parse_reg (&str); \
4959 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4961 set_expected_reg_error (reg_type, reg, 0); \
4964 info->reg.regno = reg->number; \
4965 info->qualifier = inherent_reg_qualifier (reg); \
4968 #define po_imm_nc_or_fail() do { \
4969 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4973 #define po_imm_or_fail(min, max) do { \
4974 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4976 if (val < min || val > max) \
4978 set_fatal_syntax_error (_("immediate value out of range "\
4979 #min " to "#max)); \
4984 #define po_enum_or_fail(array) do { \
4985 if (!parse_enum_string (&str, &val, array, \
4986 ARRAY_SIZE (array), imm_reg_type)) \
4990 #define po_strict_enum_or_fail(array) do { \
4991 if (!parse_enum_string (&str, &val, array, \
4992 ARRAY_SIZE (array), REG_TYPE_MAX)) \
4996 #define po_misc_or_fail(expr) do { \
5001 /* A primitive log calculator. */
5003 static inline unsigned int
5004 get_log2 (unsigned int n
)
5006 unsigned int count
= 0;
5015 /* encode the 12-bit imm field of Add/sub immediate */
5016 static inline uint32_t
5017 encode_addsub_imm (uint32_t imm
)
5022 /* encode the shift amount field of Add/sub immediate */
5023 static inline uint32_t
5024 encode_addsub_imm_shift_amount (uint32_t cnt
)
5030 /* encode the imm field of Adr instruction */
5031 static inline uint32_t
5032 encode_adr_imm (uint32_t imm
)
5034 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
5035 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
5038 /* encode the immediate field of Move wide immediate */
5039 static inline uint32_t
5040 encode_movw_imm (uint32_t imm
)
5045 /* encode the 26-bit offset of unconditional branch */
5046 static inline uint32_t
5047 encode_branch_ofs_26 (uint32_t ofs
)
5049 return ofs
& ((1 << 26) - 1);
5052 /* encode the 19-bit offset of conditional branch and compare & branch */
5053 static inline uint32_t
5054 encode_cond_branch_ofs_19 (uint32_t ofs
)
5056 return (ofs
& ((1 << 19) - 1)) << 5;
5059 /* encode the 19-bit offset of ld literal */
5060 static inline uint32_t
5061 encode_ld_lit_ofs_19 (uint32_t ofs
)
5063 return (ofs
& ((1 << 19) - 1)) << 5;
5066 /* Encode the 14-bit offset of test & branch. */
5067 static inline uint32_t
5068 encode_tst_branch_ofs_14 (uint32_t ofs
)
5070 return (ofs
& ((1 << 14) - 1)) << 5;
5073 /* Encode the 16-bit imm field of svc/hvc/smc. */
5074 static inline uint32_t
5075 encode_svc_imm (uint32_t imm
)
5080 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5081 static inline uint32_t
5082 reencode_addsub_switch_add_sub (uint32_t opcode
)
5084 return opcode
^ (1 << 30);
5087 static inline uint32_t
5088 reencode_movzn_to_movz (uint32_t opcode
)
5090 return opcode
| (1 << 30);
5093 static inline uint32_t
5094 reencode_movzn_to_movn (uint32_t opcode
)
5096 return opcode
& ~(1 << 30);
5099 /* Overall per-instruction processing. */
5101 /* We need to be able to fix up arbitrary expressions in some statements.
5102 This is so that we can handle symbols that are an arbitrary distance from
5103 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5104 which returns part of an address in a form which will be valid for
5105 a data instruction. We do this by pushing the expression into a symbol
5106 in the expr_section, and creating a fix for that. */
5109 fix_new_aarch64 (fragS
* frag
,
5124 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5128 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5135 /* Diagnostics on operands errors. */
5137 /* By default, output verbose error message.
5138 Disable the verbose error message by -mno-verbose-error. */
5139 static int verbose_error_p
= 1;
5141 #ifdef DEBUG_AARCH64
5142 /* N.B. this is only for the purpose of debugging. */
5143 const char* operand_mismatch_kind_names
[] =
5146 "AARCH64_OPDE_RECOVERABLE",
5147 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5148 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5149 "AARCH64_OPDE_SYNTAX_ERROR",
5150 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5151 "AARCH64_OPDE_INVALID_VARIANT",
5152 "AARCH64_OPDE_INVALID_VG_SIZE",
5153 "AARCH64_OPDE_REG_LIST_LENGTH",
5154 "AARCH64_OPDE_REG_LIST_STRIDE",
5155 "AARCH64_OPDE_UNTIED_IMMS",
5156 "AARCH64_OPDE_UNTIED_OPERAND",
5157 "AARCH64_OPDE_OUT_OF_RANGE",
5158 "AARCH64_OPDE_UNALIGNED",
5159 "AARCH64_OPDE_OTHER_ERROR",
5160 "AARCH64_OPDE_INVALID_REGNO",
5162 #endif /* DEBUG_AARCH64 */
5164 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5166 When multiple errors of different kinds are found in the same assembly
5167 line, only the error of the highest severity will be picked up for
5168 issuing the diagnostics. */
5171 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5172 enum aarch64_operand_error_kind rhs
)
5174 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5175 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5176 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5177 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5178 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5179 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5180 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5181 gas_assert (AARCH64_OPDE_INVALID_VG_SIZE
> AARCH64_OPDE_INVALID_VARIANT
);
5182 gas_assert (AARCH64_OPDE_REG_LIST_LENGTH
> AARCH64_OPDE_INVALID_VG_SIZE
);
5183 gas_assert (AARCH64_OPDE_REG_LIST_STRIDE
> AARCH64_OPDE_REG_LIST_LENGTH
);
5184 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_REG_LIST_STRIDE
);
5185 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5186 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST_STRIDE
);
5187 gas_assert (AARCH64_OPDE_INVALID_REGNO
> AARCH64_OPDE_OTHER_ERROR
);
5191 /* Helper routine to get the mnemonic name from the assembly instruction
5192 line; should only be called for the diagnosis purpose, as there is
5193 string copy operation involved, which may affect the runtime
5194 performance if used in elsewhere. */
5197 get_mnemonic_name (const char *str
)
5199 static char mnemonic
[32];
5202 /* Get the first 15 bytes and assume that the full name is included. */
5203 strncpy (mnemonic
, str
, 31);
5204 mnemonic
[31] = '\0';
5206 /* Scan up to the end of the mnemonic, which must end in white space,
5207 '.', or end of string. */
5208 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5213 /* Append '...' to the truncated long name. */
5214 if (ptr
- mnemonic
== 31)
5215 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5221 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5223 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5224 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5227 /* Data structures storing one user error in the assembly code related to
5230 struct operand_error_record
5232 const aarch64_opcode
*opcode
;
5233 aarch64_operand_error detail
;
5234 struct operand_error_record
*next
;
5237 typedef struct operand_error_record operand_error_record
;
5239 struct operand_errors
5241 operand_error_record
*head
;
5242 operand_error_record
*tail
;
5245 typedef struct operand_errors operand_errors
;
5247 /* Top-level data structure reporting user errors for the current line of
5249 The way md_assemble works is that all opcodes sharing the same mnemonic
5250 name are iterated to find a match to the assembly line. In this data
5251 structure, each of the such opcodes will have one operand_error_record
5252 allocated and inserted. In other words, excessive errors related with
5253 a single opcode are disregarded. */
5254 operand_errors operand_error_report
;
5256 /* Free record nodes. */
5257 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5259 /* Initialize the data structure that stores the operand mismatch
5260 information on assembling one line of the assembly code. */
5262 init_operand_error_report (void)
5264 if (operand_error_report
.head
!= NULL
)
5266 gas_assert (operand_error_report
.tail
!= NULL
);
5267 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5268 free_opnd_error_record_nodes
= operand_error_report
.head
;
5269 operand_error_report
.head
= NULL
;
5270 operand_error_report
.tail
= NULL
;
5273 gas_assert (operand_error_report
.tail
== NULL
);
5276 /* Return TRUE if some operand error has been recorded during the
5277 parsing of the current assembly line using the opcode *OPCODE;
5278 otherwise return FALSE. */
5280 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5282 operand_error_record
*record
= operand_error_report
.head
;
5283 return record
&& record
->opcode
== opcode
;
5286 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5287 OPCODE field is initialized with OPCODE.
5288 N.B. only one record for each opcode, i.e. the maximum of one error is
5289 recorded for each instruction template. */
5292 add_operand_error_record (const operand_error_record
* new_record
)
5294 const aarch64_opcode
*opcode
= new_record
->opcode
;
5295 operand_error_record
* record
= operand_error_report
.head
;
5297 /* The record may have been created for this opcode. If not, we need
5299 if (! opcode_has_operand_error_p (opcode
))
5301 /* Get one empty record. */
5302 if (free_opnd_error_record_nodes
== NULL
)
5304 record
= XNEW (operand_error_record
);
5308 record
= free_opnd_error_record_nodes
;
5309 free_opnd_error_record_nodes
= record
->next
;
5311 record
->opcode
= opcode
;
5312 /* Insert at the head. */
5313 record
->next
= operand_error_report
.head
;
5314 operand_error_report
.head
= record
;
5315 if (operand_error_report
.tail
== NULL
)
5316 operand_error_report
.tail
= record
;
5318 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5319 && record
->detail
.index
<= new_record
->detail
.index
5320 && operand_error_higher_severity_p (record
->detail
.kind
,
5321 new_record
->detail
.kind
))
5323 /* In the case of multiple errors found on operands related with a
5324 single opcode, only record the error of the leftmost operand and
5325 only if the error is of higher severity. */
5326 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5327 " the existing error %s on operand %d",
5328 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5329 new_record
->detail
.index
,
5330 operand_mismatch_kind_names
[record
->detail
.kind
],
5331 record
->detail
.index
);
5335 record
->detail
= new_record
->detail
;
5339 record_operand_error_info (const aarch64_opcode
*opcode
,
5340 aarch64_operand_error
*error_info
)
5342 operand_error_record record
;
5343 record
.opcode
= opcode
;
5344 record
.detail
= *error_info
;
5345 add_operand_error_record (&record
);
5348 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5349 error message *ERROR, for operand IDX (count from 0). */
5352 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5353 enum aarch64_operand_error_kind kind
,
5356 aarch64_operand_error info
;
5357 memset(&info
, 0, sizeof (info
));
5361 info
.non_fatal
= false;
5362 record_operand_error_info (opcode
, &info
);
5366 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5367 enum aarch64_operand_error_kind kind
,
5368 const char* error
, const int *extra_data
)
5370 aarch64_operand_error info
;
5374 info
.data
[0].i
= extra_data
[0];
5375 info
.data
[1].i
= extra_data
[1];
5376 info
.data
[2].i
= extra_data
[2];
5377 info
.non_fatal
= false;
5378 record_operand_error_info (opcode
, &info
);
5382 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5383 const char* error
, int lower_bound
,
5386 int data
[3] = {lower_bound
, upper_bound
, 0};
5387 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5391 /* Remove the operand error record for *OPCODE. */
5392 static void ATTRIBUTE_UNUSED
5393 remove_operand_error_record (const aarch64_opcode
*opcode
)
5395 if (opcode_has_operand_error_p (opcode
))
5397 operand_error_record
* record
= operand_error_report
.head
;
5398 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5399 operand_error_report
.head
= record
->next
;
5400 record
->next
= free_opnd_error_record_nodes
;
5401 free_opnd_error_record_nodes
= record
;
5402 if (operand_error_report
.head
== NULL
)
5404 gas_assert (operand_error_report
.tail
== record
);
5405 operand_error_report
.tail
= NULL
;
5410 /* Given the instruction in *INSTR, return the index of the best matched
5411 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5413 Return -1 if there is no qualifier sequence; return the first match
5414 if there is multiple matches found. */
5417 find_best_match (const aarch64_inst
*instr
,
5418 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5420 int i
, num_opnds
, max_num_matched
, idx
;
5422 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5425 DEBUG_TRACE ("no operand");
5429 max_num_matched
= 0;
5432 /* For each pattern. */
5433 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5436 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5438 /* Most opcodes has much fewer patterns in the list. */
5439 if (empty_qualifier_sequence_p (qualifiers
))
5441 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5445 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5446 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5449 if (num_matched
> max_num_matched
)
5451 max_num_matched
= num_matched
;
5456 DEBUG_TRACE ("return with %d", idx
);
5460 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5461 corresponding operands in *INSTR. */
5464 assign_qualifier_sequence (aarch64_inst
*instr
,
5465 const aarch64_opnd_qualifier_t
*qualifiers
)
5468 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5469 gas_assert (num_opnds
);
5470 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5471 instr
->operands
[i
].qualifier
= *qualifiers
;
5474 /* Callback used by aarch64_print_operand to apply STYLE to the
5475 disassembler output created from FMT and ARGS. The STYLER object holds
5476 any required state. Must return a pointer to a string (created from FMT
5477 and ARGS) that will continue to be valid until the complete disassembled
5478 instruction has been printed.
5480 We don't currently add any styling to the output of the disassembler as
5481 used within assembler error messages, and so STYLE is ignored here. A
5482 new string is allocated on the obstack help within STYLER and returned
5485 static const char *aarch64_apply_style
5486 (struct aarch64_styler
*styler
,
5487 enum disassembler_style style ATTRIBUTE_UNUSED
,
5488 const char *fmt
, va_list args
)
5492 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5495 /* Calculate the required space. */
5497 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5499 gas_assert (res
>= 0);
5501 /* Allocate space on the obstack and format the result. */
5502 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5503 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5504 gas_assert (res
>= 0);
5509 /* Print operands for the diagnosis purpose. */
5512 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5513 const aarch64_opnd_info
*opnds
)
5516 struct aarch64_styler styler
;
5517 struct obstack content
;
5518 obstack_init (&content
);
5520 styler
.apply_style
= aarch64_apply_style
;
5521 styler
.state
= (void *) &content
;
5523 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5528 /* We regard the opcode operand info more, however we also look into
5529 the inst->operands to support the disassembling of the optional
5531 The two operand code should be the same in all cases, apart from
5532 when the operand can be optional. */
5533 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5534 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5537 /* Generate the operand string in STR. */
5538 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5539 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5543 strcat (buf
, i
== 0 ? " " : ", ");
5545 /* Append the operand string. */
5548 /* Append a comment. This works because only the last operand ever
5549 adds a comment. If that ever changes then we'll need to be
5553 strcat (buf
, "\t// ");
5558 obstack_free (&content
, NULL
);
5561 /* Send to stderr a string as information. */
5564 output_info (const char *format
, ...)
5570 file
= as_where (&line
);
5574 fprintf (stderr
, "%s:%u: ", file
, line
);
5576 fprintf (stderr
, "%s: ", file
);
5578 fprintf (stderr
, _("Info: "));
5579 va_start (args
, format
);
5580 vfprintf (stderr
, format
, args
);
5582 (void) putc ('\n', stderr
);
5585 /* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
5586 relates to registers or register lists. If so, return a string that
5587 reports the error against "operand %d", otherwise return null. */
5590 get_reg_error_message (const aarch64_operand_error
*detail
)
5592 /* Handle the case where we found a register that was expected
5593 to be in a register list outside of a register list. */
5594 if ((detail
->data
[1].i
& detail
->data
[2].i
) != 0
5595 && (detail
->data
[1].i
& SEF_IN_REGLIST
) == 0)
5596 return _("missing braces at operand %d");
5598 /* If some opcodes expected a register, and we found a register,
5599 complain about the difference. */
5600 if (detail
->data
[2].i
)
5602 unsigned int expected
= (detail
->data
[1].i
& SEF_IN_REGLIST
5603 ? detail
->data
[1].i
& ~SEF_IN_REGLIST
5604 : detail
->data
[0].i
& ~SEF_DEFAULT_ERROR
);
5605 const char *msg
= get_reg_expected_msg (expected
, detail
->data
[2].i
);
5607 msg
= N_("unexpected register type at operand %d");
5611 /* Handle the case where we got to the point of trying to parse a
5612 register within a register list, but didn't find a known register. */
5613 if (detail
->data
[1].i
& SEF_IN_REGLIST
)
5615 unsigned int expected
= detail
->data
[1].i
& ~SEF_IN_REGLIST
;
5616 const char *msg
= get_reg_expected_msg (expected
, 0);
5618 msg
= _("invalid register list at operand %d");
5622 /* Punt if register-related problems weren't the only errors. */
5623 if (detail
->data
[0].i
& SEF_DEFAULT_ERROR
)
5626 /* Handle the case where the only acceptable things are registers. */
5627 if (detail
->data
[1].i
== 0)
5629 const char *msg
= get_reg_expected_msg (detail
->data
[0].i
, 0);
5631 msg
= _("expected a register at operand %d");
5635 /* Handle the case where the only acceptable things are register lists,
5636 and there was no opening '{'. */
5637 if (detail
->data
[0].i
== 0)
5638 return _("expected '{' at operand %d");
5640 return _("expected a register or register list at operand %d");
5643 /* Output one operand error record. */
5646 output_operand_error_record (const operand_error_record
*record
, char *str
)
5648 const aarch64_operand_error
*detail
= &record
->detail
;
5649 int idx
= detail
->index
;
5650 const aarch64_opcode
*opcode
= record
->opcode
;
5651 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5652 : AARCH64_OPND_NIL
);
5654 typedef void (*handler_t
)(const char *format
, ...);
5655 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5656 const char *msg
= detail
->error
;
5658 switch (detail
->kind
)
5660 case AARCH64_OPDE_NIL
:
5664 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5665 handler (_("this `%s' should have an immediately preceding `%s'"
5667 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5670 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5671 handler (_("the preceding `%s' should be followed by `%s` rather"
5672 " than `%s` -- `%s'"),
5673 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5676 case AARCH64_OPDE_SYNTAX_ERROR
:
5677 if (!msg
&& idx
>= 0)
5679 msg
= get_reg_error_message (detail
);
5682 char *full_msg
= xasprintf (msg
, idx
+ 1);
5683 handler (_("%s -- `%s'"), full_msg
, str
);
5690 case AARCH64_OPDE_RECOVERABLE
:
5691 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5692 case AARCH64_OPDE_OTHER_ERROR
:
5693 /* Use the prepared error message if there is, otherwise use the
5694 operand description string to describe the error. */
5698 handler (_("%s -- `%s'"), msg
, str
);
5700 handler (_("%s at operand %d -- `%s'"),
5705 gas_assert (idx
>= 0);
5706 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5707 aarch64_get_operand_desc (opd_code
), str
);
5711 case AARCH64_OPDE_INVALID_VARIANT
:
5712 handler (_("operand mismatch -- `%s'"), str
);
5713 if (verbose_error_p
)
5715 /* We will try to correct the erroneous instruction and also provide
5716 more information e.g. all other valid variants.
5718 The string representation of the corrected instruction and other
5719 valid variants are generated by
5721 1) obtaining the intermediate representation of the erroneous
5723 2) manipulating the IR, e.g. replacing the operand qualifier;
5724 3) printing out the instruction by calling the printer functions
5725 shared with the disassembler.
5727 The limitation of this method is that the exact input assembly
5728 line cannot be accurately reproduced in some cases, for example an
5729 optional operand present in the actual assembly line will be
5730 omitted in the output; likewise for the optional syntax rules,
5731 e.g. the # before the immediate. Another limitation is that the
5732 assembly symbols and relocation operations in the assembly line
5733 currently cannot be printed out in the error report. Last but not
5734 least, when there is other error(s) co-exist with this error, the
5735 'corrected' instruction may be still incorrect, e.g. given
5736 'ldnp h0,h1,[x0,#6]!'
5737 this diagnosis will provide the version:
5738 'ldnp s0,s1,[x0,#6]!'
5739 which is still not right. */
5740 size_t len
= strlen (get_mnemonic_name (str
));
5744 aarch64_inst
*inst_base
= &inst
.base
;
5745 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5748 reset_aarch64_instruction (&inst
);
5749 inst_base
->opcode
= opcode
;
5751 /* Reset the error report so that there is no side effect on the
5752 following operand parsing. */
5753 init_operand_error_report ();
5756 result
= parse_operands (str
+ len
, opcode
)
5757 && programmer_friendly_fixup (&inst
);
5758 gas_assert (result
);
5759 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5760 NULL
, NULL
, insn_sequence
);
5761 gas_assert (!result
);
5763 /* Find the most matched qualifier sequence. */
5764 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5765 gas_assert (qlf_idx
> -1);
5767 /* Assign the qualifiers. */
5768 assign_qualifier_sequence (inst_base
,
5769 opcode
->qualifiers_list
[qlf_idx
]);
5771 /* Print the hint. */
5772 output_info (_(" did you mean this?"));
5773 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5774 print_operands (buf
, opcode
, inst_base
->operands
);
5775 output_info (_(" %s"), buf
);
5777 /* Print out other variant(s) if there is any. */
5779 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5780 output_info (_(" other valid variant(s):"));
5782 /* For each pattern. */
5783 qualifiers_list
= opcode
->qualifiers_list
;
5784 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5786 /* Most opcodes has much fewer patterns in the list.
5787 First NIL qualifier indicates the end in the list. */
5788 if (empty_qualifier_sequence_p (*qualifiers_list
))
5793 /* Mnemonics name. */
5794 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5796 /* Assign the qualifiers. */
5797 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5799 /* Print instruction. */
5800 print_operands (buf
, opcode
, inst_base
->operands
);
5802 output_info (_(" %s"), buf
);
5808 case AARCH64_OPDE_UNTIED_IMMS
:
5809 handler (_("operand %d must have the same immediate value "
5810 "as operand 1 -- `%s'"),
5811 detail
->index
+ 1, str
);
5814 case AARCH64_OPDE_UNTIED_OPERAND
:
5815 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5816 detail
->index
+ 1, str
);
5819 case AARCH64_OPDE_INVALID_REGNO
:
5820 handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
5821 detail
->data
[0].s
, detail
->data
[1].i
,
5822 detail
->data
[0].s
, detail
->data
[2].i
, idx
+ 1, str
);
5825 case AARCH64_OPDE_OUT_OF_RANGE
:
5826 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5827 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5828 msg
? msg
: _("immediate value"),
5829 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5831 handler (_("%s must be %d at operand %d -- `%s'"),
5832 msg
? msg
: _("immediate value"),
5833 detail
->data
[0].i
, idx
+ 1, str
);
5836 case AARCH64_OPDE_INVALID_VG_SIZE
:
5837 if (detail
->data
[0].i
== 0)
5838 handler (_("unexpected vector group size at operand %d -- `%s'"),
5841 handler (_("operand %d must have a vector group size of %d -- `%s'"),
5842 idx
+ 1, detail
->data
[0].i
, str
);
5845 case AARCH64_OPDE_REG_LIST_LENGTH
:
5846 if (detail
->data
[0].i
== (1 << 1))
5847 handler (_("expected a single-register list at operand %d -- `%s'"),
5849 else if ((detail
->data
[0].i
& -detail
->data
[0].i
) == detail
->data
[0].i
)
5850 handler (_("expected a list of %d registers at operand %d -- `%s'"),
5851 get_log2 (detail
->data
[0].i
), idx
+ 1, str
);
5852 else if (detail
->data
[0].i
== 0x14)
5853 handler (_("expected a list of %d or %d registers at"
5854 " operand %d -- `%s'"),
5855 2, 4, idx
+ 1, str
);
5857 handler (_("invalid number of registers in the list"
5858 " at operand %d -- `%s'"), idx
+ 1, str
);
5861 case AARCH64_OPDE_REG_LIST_STRIDE
:
5862 if (detail
->data
[0].i
== (1 << 1))
5863 handler (_("the register list must have a stride of %d"
5864 " at operand %d -- `%s'"), 1, idx
+ 1, str
);
5865 else if (detail
->data
[0].i
== 0x12 || detail
->data
[0].i
== 0x102)
5866 handler (_("the register list must have a stride of %d or %d"
5867 " at operand %d -- `%s`"), 1,
5868 detail
->data
[0].i
== 0x12 ? 4 : 8, idx
+ 1, str
);
5870 handler (_("invalid register stride at operand %d -- `%s'"),
5874 case AARCH64_OPDE_UNALIGNED
:
5875 handler (_("immediate value must be a multiple of "
5876 "%d at operand %d -- `%s'"),
5877 detail
->data
[0].i
, idx
+ 1, str
);
5886 /* Return true if the presence of error A against an instruction means
5887 that error B should not be reported. This is only used as a first pass,
5888 to pick the kind of error that we should report. */
5891 better_error_p (operand_error_record
*a
, operand_error_record
*b
)
5893 /* For errors reported during parsing, prefer errors that relate to
5894 later operands, since that implies that the earlier operands were
5895 syntactically valid.
5897 For example, if we see a register R instead of an immediate in
5898 operand N, we'll report that as a recoverable "immediate operand
5899 required" error. This is because there is often another opcode
5900 entry that accepts a register operand N, and any errors about R
5901 should be reported against the register forms of the instruction.
5902 But if no such register form exists, the recoverable error should
5903 still win over a syntax error against operand N-1.
5905 For these purposes, count an error reported at the end of the
5906 assembly string as equivalent to an error reported against the
5907 final operand. This means that opcode entries that expect more
5908 operands win over "unexpected characters following instruction". */
5909 if (a
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
5910 && b
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
)
5912 int a_index
= (a
->detail
.index
< 0
5913 ? aarch64_num_of_operands (a
->opcode
) - 1
5915 int b_index
= (b
->detail
.index
< 0
5916 ? aarch64_num_of_operands (b
->opcode
) - 1
5918 if (a_index
!= b_index
)
5919 return a_index
> b_index
;
5921 return operand_error_higher_severity_p (a
->detail
.kind
, b
->detail
.kind
);
5924 /* Process and output the error message about the operand mismatching.
5926 When this function is called, the operand error information had
5927 been collected for an assembly line and there will be multiple
5928 errors in the case of multiple instruction templates; output the
5929 error message that most closely describes the problem.
5931 The errors to be printed can be filtered on printing all errors
5932 or only non-fatal errors. This distinction has to be made because
5933 the error buffer may already be filled with fatal errors we don't want to
5934 print due to the different instruction templates. */
5937 output_operand_error_report (char *str
, bool non_fatal_only
)
5939 enum aarch64_operand_error_kind kind
;
5940 operand_error_record
*curr
;
5941 operand_error_record
*head
= operand_error_report
.head
;
5942 operand_error_record
*record
;
5944 /* No error to report. */
5948 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5950 /* Only one error. */
5951 if (head
== operand_error_report
.tail
)
5953 /* If the only error is a non-fatal one and we don't want to print it,
5955 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5957 DEBUG_TRACE ("single opcode entry with error kind: %s",
5958 operand_mismatch_kind_names
[head
->detail
.kind
]);
5959 output_operand_error_record (head
, str
);
5964 /* Find the error kind of the highest severity. */
5965 DEBUG_TRACE ("multiple opcode entries with error kind");
5967 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5969 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5970 if (curr
->detail
.kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5972 DEBUG_TRACE ("\t%s [%x, %x, %x]",
5973 operand_mismatch_kind_names
[curr
->detail
.kind
],
5974 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5975 curr
->detail
.data
[2].i
);
5977 else if (curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_LENGTH
5978 || curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
5980 DEBUG_TRACE ("\t%s [%x]",
5981 operand_mismatch_kind_names
[curr
->detail
.kind
],
5982 curr
->detail
.data
[0].i
);
5986 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5988 if ((!non_fatal_only
|| curr
->detail
.non_fatal
)
5989 && (!record
|| better_error_p (curr
, record
)))
5993 kind
= (record
? record
->detail
.kind
: AARCH64_OPDE_NIL
);
5994 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5996 /* Pick up one of errors of KIND to report. */
5998 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
6000 /* If we don't want to print non-fatal errors then don't consider them
6002 if (curr
->detail
.kind
!= kind
6003 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
6005 /* If there are multiple errors, pick up the one with the highest
6006 mismatching operand index. In the case of multiple errors with
6007 the equally highest operand index, pick up the first one or the
6008 first one with non-NULL error message. */
6009 if (!record
|| curr
->detail
.index
> record
->detail
.index
)
6011 else if (curr
->detail
.index
== record
->detail
.index
6012 && !record
->detail
.error
)
6014 if (curr
->detail
.error
)
6016 else if (kind
== AARCH64_OPDE_SYNTAX_ERROR
)
6018 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6019 record
->detail
.data
[1].i
|= curr
->detail
.data
[1].i
;
6020 record
->detail
.data
[2].i
|= curr
->detail
.data
[2].i
;
6021 DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
6022 operand_mismatch_kind_names
[kind
],
6023 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
6024 curr
->detail
.data
[2].i
);
6026 else if (kind
== AARCH64_OPDE_REG_LIST_LENGTH
6027 || kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
6029 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6030 DEBUG_TRACE ("\t--> %s [%x]",
6031 operand_mismatch_kind_names
[kind
],
6032 curr
->detail
.data
[0].i
);
6034 /* Pick the variant with the cloest match. */
6035 else if (kind
== AARCH64_OPDE_INVALID_VARIANT
6036 && record
->detail
.data
[0].i
> curr
->detail
.data
[0].i
)
6041 /* The way errors are collected in the back-end is a bit non-intuitive. But
6042 essentially, because each operand template is tried recursively you may
6043 always have errors collected from the previous tried OPND. These are
6044 usually skipped if there is one successful match. However now with the
6045 non-fatal errors we have to ignore those previously collected hard errors
6046 when we're only interested in printing the non-fatal ones. This condition
6047 prevents us from printing errors that are not appropriate, since we did
6048 match a condition, but it also has warnings that it wants to print. */
6049 if (non_fatal_only
&& !record
)
6052 gas_assert (record
);
6053 DEBUG_TRACE ("Pick up error kind %s to report",
6054 operand_mismatch_kind_names
[kind
]);
6057 output_operand_error_record (record
, str
);
6060 /* Write an AARCH64 instruction to buf - always little-endian. */
6062 put_aarch64_insn (char *buf
, uint32_t insn
)
6064 unsigned char *where
= (unsigned char *) buf
;
6066 where
[1] = insn
>> 8;
6067 where
[2] = insn
>> 16;
6068 where
[3] = insn
>> 24;
6072 get_aarch64_insn (char *buf
)
6074 unsigned char *where
= (unsigned char *) buf
;
6076 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
6077 | ((uint32_t) where
[3] << 24)));
6082 output_inst (struct aarch64_inst
*new_inst
)
6086 to
= frag_more (INSN_SIZE
);
6088 frag_now
->tc_frag_data
.recorded
= 1;
6090 put_aarch64_insn (to
, inst
.base
.value
);
6092 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6094 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
6095 INSN_SIZE
, &inst
.reloc
.exp
,
6098 DEBUG_TRACE ("Prepared relocation fix up");
6099 /* Don't check the addend value against the instruction size,
6100 that's the job of our code in md_apply_fix(). */
6101 fixp
->fx_no_overflow
= 1;
6102 if (new_inst
!= NULL
)
6103 fixp
->tc_fix_data
.inst
= new_inst
;
6104 if (aarch64_gas_internal_fixup_p ())
6106 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
6107 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
6108 fixp
->fx_addnumber
= inst
.reloc
.flags
;
6112 dwarf2_emit_insn (INSN_SIZE
);
6115 /* Link together opcodes of the same name. */
6119 const aarch64_opcode
*opcode
;
6120 struct templates
*next
;
6123 typedef struct templates templates
;
6126 lookup_mnemonic (const char *start
, int len
)
6128 templates
*templ
= NULL
;
6130 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
6134 /* Subroutine of md_assemble, responsible for looking up the primary
6135 opcode from the mnemonic the user wrote. BASE points to the beginning
6136 of the mnemonic, DOT points to the first '.' within the mnemonic
6137 (if any) and END points to the end of the mnemonic. */
6140 opcode_lookup (char *base
, char *dot
, char *end
)
6142 const aarch64_cond
*cond
;
6149 inst
.cond
= COND_ALWAYS
;
6151 /* Handle a possible condition. */
6154 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
6157 inst
.cond
= cond
->value
;
6163 if (inst
.cond
== COND_ALWAYS
)
6165 /* Look for unaffixed mnemonic. */
6166 return lookup_mnemonic (base
, len
);
6170 /* append ".c" to mnemonic if conditional */
6171 memcpy (condname
, base
, len
);
6172 memcpy (condname
+ len
, ".c", 2);
6175 return lookup_mnemonic (base
, len
);
6181 /* Process an optional operand that is found omitted from the assembly line.
6182 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
6183 instruction's opcode entry while IDX is the index of this omitted operand.
6187 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6188 int idx
, aarch64_opnd_info
*operand
)
6190 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6191 gas_assert (optional_operand_p (opcode
, idx
));
6192 gas_assert (!operand
->present
);
6196 case AARCH64_OPND_Rd
:
6197 case AARCH64_OPND_Rn
:
6198 case AARCH64_OPND_Rm
:
6199 case AARCH64_OPND_Rt
:
6200 case AARCH64_OPND_Rt2
:
6201 case AARCH64_OPND_Rt_LS64
:
6202 case AARCH64_OPND_Rt_SP
:
6203 case AARCH64_OPND_Rs
:
6204 case AARCH64_OPND_Ra
:
6205 case AARCH64_OPND_Rt_SYS
:
6206 case AARCH64_OPND_Rd_SP
:
6207 case AARCH64_OPND_Rn_SP
:
6208 case AARCH64_OPND_Rm_SP
:
6209 case AARCH64_OPND_Fd
:
6210 case AARCH64_OPND_Fn
:
6211 case AARCH64_OPND_Fm
:
6212 case AARCH64_OPND_Fa
:
6213 case AARCH64_OPND_Ft
:
6214 case AARCH64_OPND_Ft2
:
6215 case AARCH64_OPND_Sd
:
6216 case AARCH64_OPND_Sn
:
6217 case AARCH64_OPND_Sm
:
6218 case AARCH64_OPND_Va
:
6219 case AARCH64_OPND_Vd
:
6220 case AARCH64_OPND_Vn
:
6221 case AARCH64_OPND_Vm
:
6222 case AARCH64_OPND_VdD1
:
6223 case AARCH64_OPND_VnD1
:
6224 operand
->reg
.regno
= default_value
;
6227 case AARCH64_OPND_Ed
:
6228 case AARCH64_OPND_En
:
6229 case AARCH64_OPND_Em
:
6230 case AARCH64_OPND_Em16
:
6231 case AARCH64_OPND_SM3_IMM2
:
6232 operand
->reglane
.regno
= default_value
;
6235 case AARCH64_OPND_IDX
:
6236 case AARCH64_OPND_BIT_NUM
:
6237 case AARCH64_OPND_IMMR
:
6238 case AARCH64_OPND_IMMS
:
6239 case AARCH64_OPND_SHLL_IMM
:
6240 case AARCH64_OPND_IMM_VLSL
:
6241 case AARCH64_OPND_IMM_VLSR
:
6242 case AARCH64_OPND_CCMP_IMM
:
6243 case AARCH64_OPND_FBITS
:
6244 case AARCH64_OPND_UIMM4
:
6245 case AARCH64_OPND_UIMM3_OP1
:
6246 case AARCH64_OPND_UIMM3_OP2
:
6247 case AARCH64_OPND_IMM
:
6248 case AARCH64_OPND_IMM_2
:
6249 case AARCH64_OPND_WIDTH
:
6250 case AARCH64_OPND_UIMM7
:
6251 case AARCH64_OPND_NZCV
:
6252 case AARCH64_OPND_SVE_PATTERN
:
6253 case AARCH64_OPND_SVE_PRFOP
:
6254 operand
->imm
.value
= default_value
;
6257 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6258 operand
->imm
.value
= default_value
;
6259 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6260 operand
->shifter
.amount
= 1;
6263 case AARCH64_OPND_EXCEPTION
:
6264 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6267 case AARCH64_OPND_BARRIER_ISB
:
6268 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6271 case AARCH64_OPND_BTI_TARGET
:
6272 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6280 /* Process the relocation type for move wide instructions.
6281 Return TRUE on success; otherwise return FALSE. */
6284 process_movw_reloc_info (void)
6289 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6291 if (inst
.base
.opcode
->op
== OP_MOVK
)
6292 switch (inst
.reloc
.type
)
6294 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6295 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6296 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6297 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6298 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6299 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6300 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6301 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6302 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6303 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6304 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6306 (_("the specified relocation type is not allowed for MOVK"));
6312 switch (inst
.reloc
.type
)
6314 case BFD_RELOC_AARCH64_MOVW_G0
:
6315 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6316 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6317 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6318 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6319 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6320 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6321 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6322 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6323 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6324 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6325 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6326 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6329 case BFD_RELOC_AARCH64_MOVW_G1
:
6330 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6331 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6332 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6333 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6334 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6335 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6336 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6337 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6338 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6339 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6340 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6341 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6344 case BFD_RELOC_AARCH64_MOVW_G2
:
6345 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6346 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6347 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6348 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6349 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6350 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6353 set_fatal_syntax_error
6354 (_("the specified relocation type is not allowed for 32-bit "
6360 case BFD_RELOC_AARCH64_MOVW_G3
:
6361 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6364 set_fatal_syntax_error
6365 (_("the specified relocation type is not allowed for 32-bit "
6372 /* More cases should be added when more MOVW-related relocation types
6373 are supported in GAS. */
6374 gas_assert (aarch64_gas_internal_fixup_p ());
6375 /* The shift amount should have already been set by the parser. */
6378 inst
.base
.operands
[1].shifter
.amount
= shift
;
6382 /* Determine and return the real reloc type code for an instruction
6383 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6385 static inline bfd_reloc_code_real_type
6386 ldst_lo12_determine_real_reloc_type (void)
6388 unsigned logsz
, max_logsz
;
6389 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6390 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6392 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6394 BFD_RELOC_AARCH64_LDST8_LO12
,
6395 BFD_RELOC_AARCH64_LDST16_LO12
,
6396 BFD_RELOC_AARCH64_LDST32_LO12
,
6397 BFD_RELOC_AARCH64_LDST64_LO12
,
6398 BFD_RELOC_AARCH64_LDST128_LO12
6401 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6402 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6403 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6404 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6405 BFD_RELOC_AARCH64_NONE
6408 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6409 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6410 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6411 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6412 BFD_RELOC_AARCH64_NONE
6415 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6416 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6417 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6418 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6419 BFD_RELOC_AARCH64_NONE
6422 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6423 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6424 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6425 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6426 BFD_RELOC_AARCH64_NONE
6430 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6431 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6433 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6435 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6437 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6438 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6440 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6442 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6444 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6446 logsz
= get_log2 (aarch64_get_qualifier_esize (opd1_qlf
));
6448 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6449 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6450 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6451 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6456 if (logsz
> max_logsz
)
6458 /* SEE PR 27904 for an example of this. */
6459 set_fatal_syntax_error
6460 (_("relocation qualifier does not match instruction size"));
6461 return BFD_RELOC_AARCH64_NONE
;
6464 /* In reloc.c, these pseudo relocation types should be defined in similar
6465 order as above reloc_ldst_lo12 array. Because the array index calculation
6466 below relies on this. */
6467 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6470 /* Check whether a register list REGINFO is valid. The registers have type
6471 REG_TYPE and must be numbered in increasing order (modulo the register
6472 bank size). They must have a consistent stride.
6474 Return true if the list is valid, describing it in LIST if so. */
6477 reg_list_valid_p (uint32_t reginfo
, struct aarch64_reglist
*list
,
6478 aarch64_reg_type reg_type
)
6480 uint32_t i
, nb_regs
, prev_regno
, incr
, mask
;
6481 mask
= reg_type_mask (reg_type
);
6483 nb_regs
= 1 + (reginfo
& 0x3);
6485 prev_regno
= reginfo
& 0x1f;
6488 list
->first_regno
= prev_regno
;
6489 list
->num_regs
= nb_regs
;
6491 for (i
= 1; i
< nb_regs
; ++i
)
6493 uint32_t curr_regno
, curr_incr
;
6495 curr_regno
= reginfo
& 0x1f;
6496 curr_incr
= (curr_regno
- prev_regno
) & mask
;
6501 else if (curr_incr
!= incr
)
6503 prev_regno
= curr_regno
;
6506 list
->stride
= incr
;
6510 /* Generic instruction operand parser. This does no encoding and no
6511 semantic validation; it merely squirrels values away in the inst
6512 structure. Returns TRUE or FALSE depending on whether the
6513 specified grammar matched. */
6516 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6519 char *backtrack_pos
= 0;
6520 const enum aarch64_opnd
*operands
= opcode
->operands
;
6521 aarch64_reg_type imm_reg_type
;
6524 skip_whitespace (str
);
6526 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6528 | AARCH64_FEATURE_SVE2
))
6529 imm_reg_type
= REG_TYPE_R_ZR_SP_BHSDQ_VZP
;
6531 imm_reg_type
= REG_TYPE_R_ZR_BHSDQ_V
;
6533 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6536 const reg_entry
*reg
;
6537 int comma_skipped_p
= 0;
6538 struct vector_type_el vectype
;
6539 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6540 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6541 aarch64_reg_type reg_type
;
6543 DEBUG_TRACE ("parse operand %d", i
);
6545 /* Assign the operand code. */
6546 info
->type
= operands
[i
];
6548 if (optional_operand_p (opcode
, i
))
6550 /* Remember where we are in case we need to backtrack. */
6551 gas_assert (!backtrack_pos
);
6552 backtrack_pos
= str
;
6555 /* Expect comma between operands; the backtrack mechanism will take
6556 care of cases of omitted optional operand. */
6557 if (i
> 0 && ! skip_past_char (&str
, ','))
6559 set_syntax_error (_("comma expected between operands"));
6563 comma_skipped_p
= 1;
6565 switch (operands
[i
])
6567 case AARCH64_OPND_Rd
:
6568 case AARCH64_OPND_Rn
:
6569 case AARCH64_OPND_Rm
:
6570 case AARCH64_OPND_Rt
:
6571 case AARCH64_OPND_Rt2
:
6572 case AARCH64_OPND_Rs
:
6573 case AARCH64_OPND_Ra
:
6574 case AARCH64_OPND_Rt_LS64
:
6575 case AARCH64_OPND_Rt_SYS
:
6576 case AARCH64_OPND_PAIRREG
:
6577 case AARCH64_OPND_SVE_Rm
:
6578 po_int_fp_reg_or_fail (REG_TYPE_R_ZR
);
6580 /* In LS64 load/store instructions Rt register number must be even
6582 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6584 /* We've already checked if this is valid register.
6585 This will check if register number (Rt) is not undefined for LS64
6587 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6588 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6590 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6596 case AARCH64_OPND_Rd_SP
:
6597 case AARCH64_OPND_Rn_SP
:
6598 case AARCH64_OPND_Rt_SP
:
6599 case AARCH64_OPND_SVE_Rn_SP
:
6600 case AARCH64_OPND_Rm_SP
:
6601 po_int_fp_reg_or_fail (REG_TYPE_R_SP
);
6604 case AARCH64_OPND_Rm_EXT
:
6605 case AARCH64_OPND_Rm_SFT
:
6606 po_misc_or_fail (parse_shifter_operand
6607 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6609 : SHIFTED_LOGIC_IMM
)));
6610 if (!info
->shifter
.operator_present
)
6612 /* Default to LSL if not present. Libopcodes prefers shifter
6613 kind to be explicit. */
6614 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6615 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6616 /* For Rm_EXT, libopcodes will carry out further check on whether
6617 or not stack pointer is used in the instruction (Recall that
6618 "the extend operator is not optional unless at least one of
6619 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6623 case AARCH64_OPND_Fd
:
6624 case AARCH64_OPND_Fn
:
6625 case AARCH64_OPND_Fm
:
6626 case AARCH64_OPND_Fa
:
6627 case AARCH64_OPND_Ft
:
6628 case AARCH64_OPND_Ft2
:
6629 case AARCH64_OPND_Sd
:
6630 case AARCH64_OPND_Sn
:
6631 case AARCH64_OPND_Sm
:
6632 case AARCH64_OPND_SVE_VZn
:
6633 case AARCH64_OPND_SVE_Vd
:
6634 case AARCH64_OPND_SVE_Vm
:
6635 case AARCH64_OPND_SVE_Vn
:
6636 po_int_fp_reg_or_fail (REG_TYPE_BHSDQ
);
6639 case AARCH64_OPND_SVE_Pd
:
6640 case AARCH64_OPND_SVE_Pg3
:
6641 case AARCH64_OPND_SVE_Pg4_5
:
6642 case AARCH64_OPND_SVE_Pg4_10
:
6643 case AARCH64_OPND_SVE_Pg4_16
:
6644 case AARCH64_OPND_SVE_Pm
:
6645 case AARCH64_OPND_SVE_Pn
:
6646 case AARCH64_OPND_SVE_Pt
:
6647 case AARCH64_OPND_SME_Pm
:
6648 reg_type
= REG_TYPE_P
;
6651 case AARCH64_OPND_SVE_Za_5
:
6652 case AARCH64_OPND_SVE_Za_16
:
6653 case AARCH64_OPND_SVE_Zd
:
6654 case AARCH64_OPND_SVE_Zm_5
:
6655 case AARCH64_OPND_SVE_Zm_16
:
6656 case AARCH64_OPND_SVE_Zn
:
6657 case AARCH64_OPND_SVE_Zt
:
6658 reg_type
= REG_TYPE_Z
;
6661 case AARCH64_OPND_SVE_PNd
:
6662 case AARCH64_OPND_SVE_PNg4_10
:
6663 case AARCH64_OPND_SVE_PNn
:
6664 case AARCH64_OPND_SVE_PNt
:
6665 case AARCH64_OPND_SME_PNd3
:
6666 case AARCH64_OPND_SME_PNg3
:
6667 case AARCH64_OPND_SME_PNn
:
6668 reg_type
= REG_TYPE_PN
;
6671 case AARCH64_OPND_Va
:
6672 case AARCH64_OPND_Vd
:
6673 case AARCH64_OPND_Vn
:
6674 case AARCH64_OPND_Vm
:
6675 reg_type
= REG_TYPE_V
;
6677 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6680 if (vectype
.defined
& NTA_HASINDEX
)
6683 info
->reg
.regno
= reg
->number
;
6684 if ((reg_type
== REG_TYPE_P
6685 || reg_type
== REG_TYPE_PN
6686 || reg_type
== REG_TYPE_Z
)
6687 && vectype
.type
== NT_invtype
)
6688 /* Unqualified P and Z registers are allowed in certain
6689 contexts. Rely on F_STRICT qualifier checking to catch
6691 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6694 info
->qualifier
= vectype_to_qualifier (&vectype
);
6695 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6700 case AARCH64_OPND_VdD1
:
6701 case AARCH64_OPND_VnD1
:
6702 reg
= aarch64_reg_parse (&str
, REG_TYPE_V
, &vectype
);
6705 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6707 set_fatal_syntax_error
6708 (_("the top half of a 128-bit FP/SIMD register is expected"));
6711 info
->reg
.regno
= reg
->number
;
6712 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6713 here; it is correct for the purpose of encoding/decoding since
6714 only the register number is explicitly encoded in the related
6715 instructions, although this appears a bit hacky. */
6716 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6719 case AARCH64_OPND_SVE_Zm3_INDEX
:
6720 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6721 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6722 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6723 case AARCH64_OPND_SVE_Zm4_INDEX
:
6724 case AARCH64_OPND_SVE_Zn_INDEX
:
6725 reg_type
= REG_TYPE_Z
;
6726 goto vector_reg_index
;
6728 case AARCH64_OPND_Ed
:
6729 case AARCH64_OPND_En
:
6730 case AARCH64_OPND_Em
:
6731 case AARCH64_OPND_Em16
:
6732 case AARCH64_OPND_SM3_IMM2
:
6733 reg_type
= REG_TYPE_V
;
6735 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6738 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6741 info
->reglane
.regno
= reg
->number
;
6742 info
->reglane
.index
= vectype
.index
;
6743 info
->qualifier
= vectype_to_qualifier (&vectype
);
6744 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6748 case AARCH64_OPND_SVE_ZnxN
:
6749 case AARCH64_OPND_SVE_ZtxN
:
6750 case AARCH64_OPND_SME_Zdnx2
:
6751 case AARCH64_OPND_SME_Zdnx4
:
6752 case AARCH64_OPND_SME_Zmx2
:
6753 case AARCH64_OPND_SME_Zmx4
:
6754 case AARCH64_OPND_SME_Znx2
:
6755 case AARCH64_OPND_SME_Znx4
:
6756 case AARCH64_OPND_SME_Ztx2_STRIDED
:
6757 case AARCH64_OPND_SME_Ztx4_STRIDED
:
6758 reg_type
= REG_TYPE_Z
;
6759 goto vector_reg_list
;
6761 case AARCH64_OPND_SME_Pdx2
:
6762 case AARCH64_OPND_SME_PdxN
:
6763 reg_type
= REG_TYPE_P
;
6764 goto vector_reg_list
;
6766 case AARCH64_OPND_LVn
:
6767 case AARCH64_OPND_LVt
:
6768 case AARCH64_OPND_LVt_AL
:
6769 case AARCH64_OPND_LEt
:
6770 reg_type
= REG_TYPE_V
;
6772 if (reg_type
== REG_TYPE_Z
6773 && get_opcode_dependent_value (opcode
) == 1
6776 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6779 info
->reglist
.first_regno
= reg
->number
;
6780 info
->reglist
.num_regs
= 1;
6781 info
->reglist
.stride
= 1;
6785 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6786 if (val
== PARSE_FAIL
)
6789 if (! reg_list_valid_p (val
, &info
->reglist
, reg_type
))
6791 set_fatal_syntax_error (_("invalid register list"));
6795 if (vectype
.width
!= 0 && *str
!= ',')
6797 set_fatal_syntax_error
6798 (_("expected element type rather than vector type"));
6802 if (operands
[i
] == AARCH64_OPND_LEt
)
6804 if (!(vectype
.defined
& NTA_HASINDEX
))
6806 info
->reglist
.has_index
= 1;
6807 info
->reglist
.index
= vectype
.index
;
6811 if (vectype
.defined
& NTA_HASINDEX
)
6813 if (!(vectype
.defined
& NTA_HASTYPE
))
6815 if (reg_type
== REG_TYPE_Z
|| reg_type
== REG_TYPE_P
)
6816 set_fatal_syntax_error (_("missing type suffix"));
6820 info
->qualifier
= vectype_to_qualifier (&vectype
);
6821 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6825 case AARCH64_OPND_CRn
:
6826 case AARCH64_OPND_CRm
:
6828 char prefix
= *(str
++);
6829 if (prefix
!= 'c' && prefix
!= 'C')
6832 po_imm_nc_or_fail ();
6835 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6838 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6839 info
->imm
.value
= val
;
6843 case AARCH64_OPND_SHLL_IMM
:
6844 case AARCH64_OPND_IMM_VLSR
:
6845 po_imm_or_fail (1, 64);
6846 info
->imm
.value
= val
;
6849 case AARCH64_OPND_CCMP_IMM
:
6850 case AARCH64_OPND_SIMM5
:
6851 case AARCH64_OPND_FBITS
:
6852 case AARCH64_OPND_TME_UIMM16
:
6853 case AARCH64_OPND_UIMM4
:
6854 case AARCH64_OPND_UIMM4_ADDG
:
6855 case AARCH64_OPND_UIMM10
:
6856 case AARCH64_OPND_UIMM3_OP1
:
6857 case AARCH64_OPND_UIMM3_OP2
:
6858 case AARCH64_OPND_IMM_VLSL
:
6859 case AARCH64_OPND_IMM
:
6860 case AARCH64_OPND_IMM_2
:
6861 case AARCH64_OPND_WIDTH
:
6862 case AARCH64_OPND_SVE_INV_LIMM
:
6863 case AARCH64_OPND_SVE_LIMM
:
6864 case AARCH64_OPND_SVE_LIMM_MOV
:
6865 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6866 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6867 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6868 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6869 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6870 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6871 case AARCH64_OPND_SVE_SIMM5
:
6872 case AARCH64_OPND_SVE_SIMM5B
:
6873 case AARCH64_OPND_SVE_SIMM6
:
6874 case AARCH64_OPND_SVE_SIMM8
:
6875 case AARCH64_OPND_SVE_UIMM3
:
6876 case AARCH64_OPND_SVE_UIMM7
:
6877 case AARCH64_OPND_SVE_UIMM8
:
6878 case AARCH64_OPND_SVE_UIMM8_53
:
6879 case AARCH64_OPND_IMM_ROT1
:
6880 case AARCH64_OPND_IMM_ROT2
:
6881 case AARCH64_OPND_IMM_ROT3
:
6882 case AARCH64_OPND_SVE_IMM_ROT1
:
6883 case AARCH64_OPND_SVE_IMM_ROT2
:
6884 case AARCH64_OPND_SVE_IMM_ROT3
:
6885 case AARCH64_OPND_CSSC_SIMM8
:
6886 case AARCH64_OPND_CSSC_UIMM8
:
6887 po_imm_nc_or_fail ();
6888 info
->imm
.value
= val
;
6891 case AARCH64_OPND_SVE_AIMM
:
6892 case AARCH64_OPND_SVE_ASIMM
:
6893 po_imm_nc_or_fail ();
6894 info
->imm
.value
= val
;
6895 skip_whitespace (str
);
6896 if (skip_past_comma (&str
))
6897 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6899 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6902 case AARCH64_OPND_SVE_PATTERN
:
6903 po_enum_or_fail (aarch64_sve_pattern_array
);
6904 info
->imm
.value
= val
;
6907 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6908 po_enum_or_fail (aarch64_sve_pattern_array
);
6909 info
->imm
.value
= val
;
6910 if (skip_past_comma (&str
)
6911 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6913 if (!info
->shifter
.operator_present
)
6915 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6916 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6917 info
->shifter
.amount
= 1;
6921 case AARCH64_OPND_SVE_PRFOP
:
6922 po_enum_or_fail (aarch64_sve_prfop_array
);
6923 info
->imm
.value
= val
;
6926 case AARCH64_OPND_UIMM7
:
6927 po_imm_or_fail (0, 127);
6928 info
->imm
.value
= val
;
6931 case AARCH64_OPND_IDX
:
6932 case AARCH64_OPND_MASK
:
6933 case AARCH64_OPND_BIT_NUM
:
6934 case AARCH64_OPND_IMMR
:
6935 case AARCH64_OPND_IMMS
:
6936 po_imm_or_fail (0, 63);
6937 info
->imm
.value
= val
;
6940 case AARCH64_OPND_IMM0
:
6941 po_imm_nc_or_fail ();
6944 set_fatal_syntax_error (_("immediate zero expected"));
6947 info
->imm
.value
= 0;
6950 case AARCH64_OPND_FPIMM0
:
6953 bool res1
= false, res2
= false;
6954 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6955 it is probably not worth the effort to support it. */
6956 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6959 || !(res2
= parse_constant_immediate (&str
, &val
,
6962 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6964 info
->imm
.value
= 0;
6965 info
->imm
.is_fp
= 1;
6968 set_fatal_syntax_error (_("immediate zero expected"));
6972 case AARCH64_OPND_IMM_MOV
:
6975 if (reg_name_p (str
, REG_TYPE_R_ZR_SP
)
6976 || reg_name_p (str
, REG_TYPE_V
))
6979 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6980 GE_OPT_PREFIX
, REJECT_ABSENT
));
6981 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6982 later. fix_mov_imm_insn will try to determine a machine
6983 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6984 message if the immediate cannot be moved by a single
6986 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6987 inst
.base
.operands
[i
].skip
= 1;
6991 case AARCH64_OPND_SIMD_IMM
:
6992 case AARCH64_OPND_SIMD_IMM_SFT
:
6993 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6995 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6997 /* need_libopcodes_p */ 1,
7000 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
7001 shift, we don't check it here; we leave the checking to
7002 the libopcodes (operand_general_constraint_met_p). By
7003 doing this, we achieve better diagnostics. */
7004 if (skip_past_comma (&str
)
7005 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
7007 if (!info
->shifter
.operator_present
7008 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
7010 /* Default to LSL if not present. Libopcodes prefers shifter
7011 kind to be explicit. */
7012 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7013 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7017 case AARCH64_OPND_FPIMM
:
7018 case AARCH64_OPND_SIMD_FPIMM
:
7019 case AARCH64_OPND_SVE_FPIMM8
:
7024 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7025 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
7026 || !aarch64_imm_float_p (qfloat
))
7029 set_fatal_syntax_error (_("invalid floating-point"
7033 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
7034 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7038 case AARCH64_OPND_SVE_I1_HALF_ONE
:
7039 case AARCH64_OPND_SVE_I1_HALF_TWO
:
7040 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
7045 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7046 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
7049 set_fatal_syntax_error (_("invalid floating-point"
7053 inst
.base
.operands
[i
].imm
.value
= qfloat
;
7054 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7058 case AARCH64_OPND_LIMM
:
7059 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7060 SHIFTED_LOGIC_IMM
));
7061 if (info
->shifter
.operator_present
)
7063 set_fatal_syntax_error
7064 (_("shift not allowed for bitmask immediate"));
7067 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7069 /* need_libopcodes_p */ 1,
7073 case AARCH64_OPND_AIMM
:
7074 if (opcode
->op
== OP_ADD
)
7075 /* ADD may have relocation types. */
7076 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
7077 SHIFTED_ARITH_IMM
));
7079 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7080 SHIFTED_ARITH_IMM
));
7081 switch (inst
.reloc
.type
)
7083 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7084 info
->shifter
.amount
= 12;
7086 case BFD_RELOC_UNUSED
:
7087 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7088 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
7089 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
7090 inst
.reloc
.pc_rel
= 0;
7095 info
->imm
.value
= 0;
7096 if (!info
->shifter
.operator_present
)
7098 /* Default to LSL if not present. Libopcodes prefers shifter
7099 kind to be explicit. */
7100 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7101 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7105 case AARCH64_OPND_HALF
:
7107 /* #<imm16> or relocation. */
7108 int internal_fixup_p
;
7109 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
7110 if (internal_fixup_p
)
7111 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7112 skip_whitespace (str
);
7113 if (skip_past_comma (&str
))
7115 /* {, LSL #<shift>} */
7116 if (! aarch64_gas_internal_fixup_p ())
7118 set_fatal_syntax_error (_("can't mix relocation modifier "
7119 "with explicit shift"));
7122 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
7125 inst
.base
.operands
[i
].shifter
.amount
= 0;
7126 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
7127 inst
.base
.operands
[i
].imm
.value
= 0;
7128 if (! process_movw_reloc_info ())
7133 case AARCH64_OPND_EXCEPTION
:
7134 case AARCH64_OPND_UNDEFINED
:
7135 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
7137 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7139 /* need_libopcodes_p */ 0,
7143 case AARCH64_OPND_NZCV
:
7145 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
7149 info
->imm
.value
= nzcv
->value
;
7152 po_imm_or_fail (0, 15);
7153 info
->imm
.value
= val
;
7157 case AARCH64_OPND_COND
:
7158 case AARCH64_OPND_COND1
:
7163 while (ISALPHA (*str
));
7164 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
7165 if (info
->cond
== NULL
)
7167 set_syntax_error (_("invalid condition"));
7170 else if (operands
[i
] == AARCH64_OPND_COND1
7171 && (info
->cond
->value
& 0xe) == 0xe)
7173 /* Do not allow AL or NV. */
7174 set_default_error ();
7180 case AARCH64_OPND_ADDR_ADRP
:
7181 po_misc_or_fail (parse_adrp (&str
));
7182 /* Clear the value as operand needs to be relocated. */
7183 info
->imm
.value
= 0;
7186 case AARCH64_OPND_ADDR_PCREL14
:
7187 case AARCH64_OPND_ADDR_PCREL19
:
7188 case AARCH64_OPND_ADDR_PCREL21
:
7189 case AARCH64_OPND_ADDR_PCREL26
:
7190 po_misc_or_fail (parse_address (&str
, info
));
7191 if (!info
->addr
.pcrel
)
7193 set_syntax_error (_("invalid pc-relative address"));
7196 if (inst
.gen_lit_pool
7197 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
7199 /* Only permit "=value" in the literal load instructions.
7200 The literal will be generated by programmer_friendly_fixup. */
7201 set_syntax_error (_("invalid use of \"=immediate\""));
7204 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7206 set_syntax_error (_("unrecognized relocation suffix"));
7209 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7211 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7212 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7216 info
->imm
.value
= 0;
7217 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7218 switch (opcode
->iclass
)
7222 /* e.g. CBZ or B.COND */
7223 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7224 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7228 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7229 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7233 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7235 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7236 : BFD_RELOC_AARCH64_JUMP26
;
7239 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7240 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7243 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7244 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7250 inst
.reloc
.pc_rel
= 1;
7254 case AARCH64_OPND_ADDR_SIMPLE
:
7255 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7257 /* [<Xn|SP>{, #<simm>}] */
7259 /* First use the normal address-parsing routines, to get
7260 the usual syntax errors. */
7261 po_misc_or_fail (parse_address (&str
, info
));
7262 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7263 || !info
->addr
.preind
|| info
->addr
.postind
7264 || info
->addr
.writeback
)
7266 set_syntax_error (_("invalid addressing mode"));
7270 /* Then retry, matching the specific syntax of these addresses. */
7272 po_char_or_fail ('[');
7273 po_reg_or_fail (REG_TYPE_R64_SP
);
7274 /* Accept optional ", #0". */
7275 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7276 && skip_past_char (&str
, ','))
7278 skip_past_char (&str
, '#');
7279 if (! skip_past_char (&str
, '0'))
7281 set_fatal_syntax_error
7282 (_("the optional immediate offset can only be 0"));
7286 po_char_or_fail (']');
7290 case AARCH64_OPND_ADDR_REGOFF
:
7291 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7292 po_misc_or_fail (parse_address (&str
, info
));
7294 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7295 || !info
->addr
.preind
|| info
->addr
.postind
7296 || info
->addr
.writeback
)
7298 set_syntax_error (_("invalid addressing mode"));
7301 if (!info
->shifter
.operator_present
)
7303 /* Default to LSL if not present. Libopcodes prefers shifter
7304 kind to be explicit. */
7305 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7306 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7308 /* Qualifier to be deduced by libopcodes. */
7311 case AARCH64_OPND_ADDR_SIMM7
:
7312 po_misc_or_fail (parse_address (&str
, info
));
7313 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7314 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7316 set_syntax_error (_("invalid addressing mode"));
7319 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7321 set_syntax_error (_("relocation not allowed"));
7324 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7326 /* need_libopcodes_p */ 1,
7330 case AARCH64_OPND_ADDR_SIMM9
:
7331 case AARCH64_OPND_ADDR_SIMM9_2
:
7332 case AARCH64_OPND_ADDR_SIMM11
:
7333 case AARCH64_OPND_ADDR_SIMM13
:
7334 po_misc_or_fail (parse_address (&str
, info
));
7335 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7336 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7337 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7338 && info
->addr
.writeback
))
7340 set_syntax_error (_("invalid addressing mode"));
7343 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7345 set_syntax_error (_("relocation not allowed"));
7348 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7350 /* need_libopcodes_p */ 1,
7354 case AARCH64_OPND_ADDR_SIMM10
:
7355 case AARCH64_OPND_ADDR_OFFSET
:
7356 po_misc_or_fail (parse_address (&str
, info
));
7357 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7358 || !info
->addr
.preind
|| info
->addr
.postind
)
7360 set_syntax_error (_("invalid addressing mode"));
7363 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7365 set_syntax_error (_("relocation not allowed"));
7368 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7370 /* need_libopcodes_p */ 1,
7374 case AARCH64_OPND_ADDR_UIMM12
:
7375 po_misc_or_fail (parse_address (&str
, info
));
7376 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7377 || !info
->addr
.preind
|| info
->addr
.writeback
)
7379 set_syntax_error (_("invalid addressing mode"));
7382 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7383 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7384 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7386 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7388 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7390 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7392 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7393 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7394 /* Leave qualifier to be determined by libopcodes. */
7397 case AARCH64_OPND_SIMD_ADDR_POST
:
7398 /* [<Xn|SP>], <Xm|#<amount>> */
7399 po_misc_or_fail (parse_address (&str
, info
));
7400 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7402 set_syntax_error (_("invalid addressing mode"));
7405 if (!info
->addr
.offset
.is_reg
)
7407 if (inst
.reloc
.exp
.X_op
== O_constant
)
7408 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7411 set_fatal_syntax_error
7412 (_("writeback value must be an immediate constant"));
7419 case AARCH64_OPND_SME_SM_ZA
:
7421 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7423 set_syntax_error (_("unknown or missing PSTATE field name"));
7426 info
->reg
.regno
= val
;
7429 case AARCH64_OPND_SME_PnT_Wm_imm
:
7430 if (!parse_dual_indexed_reg (&str
, REG_TYPE_P
,
7431 &info
->indexed_za
, &qualifier
, 0))
7433 info
->qualifier
= qualifier
;
7436 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7437 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7438 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7439 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7440 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7441 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7442 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7443 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7444 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7445 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7446 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7447 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7448 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7449 /* [X<n>{, #imm, MUL VL}]
7451 but recognizing SVE registers. */
7452 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7453 &offset_qualifier
));
7454 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7456 set_syntax_error (_("invalid addressing mode"));
7460 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7461 || !info
->addr
.preind
|| info
->addr
.writeback
)
7463 set_syntax_error (_("invalid addressing mode"));
7466 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7467 || inst
.reloc
.exp
.X_op
!= O_constant
)
7469 /* Make sure this has priority over
7470 "invalid addressing mode". */
7471 set_fatal_syntax_error (_("constant offset required"));
7474 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7477 case AARCH64_OPND_SVE_ADDR_R
:
7478 /* [<Xn|SP>{, <R><m>}]
7479 but recognizing SVE registers. */
7480 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7481 &offset_qualifier
));
7482 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7484 offset_qualifier
= AARCH64_OPND_QLF_X
;
7485 info
->addr
.offset
.is_reg
= 1;
7486 info
->addr
.offset
.regno
= 31;
7488 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7489 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7491 set_syntax_error (_("invalid addressing mode"));
7496 case AARCH64_OPND_SVE_ADDR_RR
:
7497 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7498 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7499 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7500 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7501 case AARCH64_OPND_SVE_ADDR_RX
:
7502 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7503 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7504 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7505 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7506 but recognizing SVE registers. */
7507 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7508 &offset_qualifier
));
7509 if (base_qualifier
!= AARCH64_OPND_QLF_X
7510 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7512 set_syntax_error (_("invalid addressing mode"));
7517 case AARCH64_OPND_SVE_ADDR_RZ
:
7518 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7519 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7520 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7521 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7522 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7523 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7524 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7525 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7526 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7527 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7528 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7529 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7530 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7531 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7532 &offset_qualifier
));
7533 if (base_qualifier
!= AARCH64_OPND_QLF_X
7534 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7535 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7537 set_syntax_error (_("invalid addressing mode"));
7540 info
->qualifier
= offset_qualifier
;
7543 case AARCH64_OPND_SVE_ADDR_ZX
:
7544 /* [Zn.<T>{, <Xm>}]. */
7545 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7546 &offset_qualifier
));
7548 base_qualifier either S_S or S_D
7549 offset_qualifier must be X
7551 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7552 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7553 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7555 set_syntax_error (_("invalid addressing mode"));
7558 info
->qualifier
= base_qualifier
;
7559 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7560 || !info
->addr
.preind
|| info
->addr
.writeback
7561 || info
->shifter
.operator_present
!= 0)
7563 set_syntax_error (_("invalid addressing mode"));
7566 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7570 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7571 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7572 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7573 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7574 /* [Z<n>.<T>{, #imm}] */
7575 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7576 &offset_qualifier
));
7577 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7578 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7580 set_syntax_error (_("invalid addressing mode"));
7583 info
->qualifier
= base_qualifier
;
7586 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7587 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7588 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7589 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7590 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7594 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7596 here since we get better error messages by leaving it to
7597 the qualifier checking routines. */
7598 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7599 &offset_qualifier
));
7600 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7601 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7602 || offset_qualifier
!= base_qualifier
)
7604 set_syntax_error (_("invalid addressing mode"));
7607 info
->qualifier
= base_qualifier
;
7610 case AARCH64_OPND_SYSREG
:
7612 uint32_t sysreg_flags
;
7613 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7614 &sysreg_flags
)) == PARSE_FAIL
)
7616 set_syntax_error (_("unknown or missing system register name"));
7619 inst
.base
.operands
[i
].sysreg
.value
= val
;
7620 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7624 case AARCH64_OPND_PSTATEFIELD
:
7626 uint32_t sysreg_flags
;
7627 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7628 &sysreg_flags
)) == PARSE_FAIL
)
7630 set_syntax_error (_("unknown or missing PSTATE field name"));
7633 inst
.base
.operands
[i
].pstatefield
= val
;
7634 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7638 case AARCH64_OPND_SYSREG_IC
:
7639 inst
.base
.operands
[i
].sysins_op
=
7640 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7643 case AARCH64_OPND_SYSREG_DC
:
7644 inst
.base
.operands
[i
].sysins_op
=
7645 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7648 case AARCH64_OPND_SYSREG_AT
:
7649 inst
.base
.operands
[i
].sysins_op
=
7650 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7653 case AARCH64_OPND_SYSREG_SR
:
7654 inst
.base
.operands
[i
].sysins_op
=
7655 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7658 case AARCH64_OPND_SYSREG_TLBI
:
7659 inst
.base
.operands
[i
].sysins_op
=
7660 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7662 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7664 set_fatal_syntax_error ( _("unknown or missing operation name"));
7669 case AARCH64_OPND_BARRIER
:
7670 case AARCH64_OPND_BARRIER_ISB
:
7671 val
= parse_barrier (&str
);
7672 if (val
!= PARSE_FAIL
7673 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7675 /* ISB only accepts options name 'sy'. */
7677 (_("the specified option is not accepted in ISB"));
7678 /* Turn off backtrack as this optional operand is present. */
7682 if (val
!= PARSE_FAIL
7683 && operands
[i
] == AARCH64_OPND_BARRIER
)
7685 /* Regular barriers accept options CRm (C0-C15).
7686 DSB nXS barrier variant accepts values > 15. */
7687 if (val
< 0 || val
> 15)
7689 set_syntax_error (_("the specified option is not accepted in DSB"));
7693 /* This is an extension to accept a 0..15 immediate. */
7694 if (val
== PARSE_FAIL
)
7695 po_imm_or_fail (0, 15);
7696 info
->barrier
= aarch64_barrier_options
+ val
;
7699 case AARCH64_OPND_BARRIER_DSB_NXS
:
7700 val
= parse_barrier (&str
);
7701 if (val
!= PARSE_FAIL
)
7703 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7704 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7706 set_syntax_error (_("the specified option is not accepted in DSB"));
7707 /* Turn off backtrack as this optional operand is present. */
7714 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7715 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7716 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7718 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7720 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7724 /* Option index is encoded as 2-bit value in val<3:2>. */
7725 val
= (val
>> 2) - 4;
7726 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7729 case AARCH64_OPND_PRFOP
:
7730 val
= parse_pldop (&str
);
7731 /* This is an extension to accept a 0..31 immediate. */
7732 if (val
== PARSE_FAIL
)
7733 po_imm_or_fail (0, 31);
7734 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7737 case AARCH64_OPND_BARRIER_PSB
:
7738 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7739 if (val
== PARSE_FAIL
)
7743 case AARCH64_OPND_SME_PNn3_INDEX1
:
7744 case AARCH64_OPND_SME_PNn3_INDEX2
:
7745 reg
= aarch64_reg_parse (&str
, REG_TYPE_PN
, &vectype
);
7748 if (!(vectype
.defined
& NTA_HASINDEX
))
7750 set_syntax_error (_("missing register index"));
7753 info
->reglane
.regno
= reg
->number
;
7754 info
->reglane
.index
= vectype
.index
;
7755 if (vectype
.type
== NT_invtype
)
7756 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
7758 info
->qualifier
= vectype_to_qualifier (&vectype
);
7761 case AARCH64_OPND_BTI_TARGET
:
7762 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7763 if (val
== PARSE_FAIL
)
7767 case AARCH64_OPND_SME_ZAda_2b
:
7768 case AARCH64_OPND_SME_ZAda_3b
:
7769 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
, 0);
7772 info
->reg
.regno
= reg
->number
;
7773 info
->qualifier
= qualifier
;
7776 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7777 case AARCH64_OPND_SME_ZA_HV_idx_srcxN
:
7778 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7779 case AARCH64_OPND_SME_ZA_HV_idx_destxN
:
7780 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7781 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7782 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7785 : !parse_dual_indexed_reg (&str
, REG_TYPE_ZATHV
,
7786 &info
->indexed_za
, &qualifier
, 0))
7788 info
->qualifier
= qualifier
;
7791 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7792 val
= parse_sme_list_of_64bit_tiles (&str
);
7793 if (val
== PARSE_FAIL
)
7795 info
->imm
.value
= val
;
7798 case AARCH64_OPND_SME_ZA_array_off3_0
:
7799 case AARCH64_OPND_SME_ZA_array_off3_5
:
7800 case AARCH64_OPND_SME_ZA_array_off4
:
7801 if (!parse_dual_indexed_reg (&str
, REG_TYPE_ZA
,
7802 &info
->indexed_za
, &qualifier
, 0))
7804 info
->qualifier
= qualifier
;
7807 case AARCH64_OPND_SME_VLxN_10
:
7808 case AARCH64_OPND_SME_VLxN_13
:
7809 po_strict_enum_or_fail (aarch64_sme_vlxn_array
);
7810 info
->imm
.value
= val
;
7813 case AARCH64_OPND_MOPS_ADDR_Rd
:
7814 case AARCH64_OPND_MOPS_ADDR_Rs
:
7815 po_char_or_fail ('[');
7816 if (!parse_x0_to_x30 (&str
, info
))
7818 po_char_or_fail (']');
7819 po_char_or_fail ('!');
7822 case AARCH64_OPND_MOPS_WB_Rn
:
7823 if (!parse_x0_to_x30 (&str
, info
))
7825 po_char_or_fail ('!');
7829 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7832 /* If we get here, this operand was successfully parsed. */
7833 inst
.base
.operands
[i
].present
= 1;
7837 /* The parse routine should already have set the error, but in case
7838 not, set a default one here. */
7840 set_default_error ();
7842 if (! backtrack_pos
)
7843 goto parse_operands_return
;
7846 /* We reach here because this operand is marked as optional, and
7847 either no operand was supplied or the operand was supplied but it
7848 was syntactically incorrect. In the latter case we report an
7849 error. In the former case we perform a few more checks before
7850 dropping through to the code to insert the default operand. */
7852 char *tmp
= backtrack_pos
;
7853 char endchar
= END_OF_INSN
;
7855 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7857 skip_past_char (&tmp
, ',');
7859 if (*tmp
!= endchar
)
7860 /* The user has supplied an operand in the wrong format. */
7861 goto parse_operands_return
;
7863 /* Make sure there is not a comma before the optional operand.
7864 For example the fifth operand of 'sys' is optional:
7866 sys #0,c0,c0,#0, <--- wrong
7867 sys #0,c0,c0,#0 <--- correct. */
7868 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7870 set_fatal_syntax_error
7871 (_("unexpected comma before the omitted optional operand"));
7872 goto parse_operands_return
;
7876 /* Reaching here means we are dealing with an optional operand that is
7877 omitted from the assembly line. */
7878 gas_assert (optional_operand_p (opcode
, i
));
7880 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7882 /* Try again, skipping the optional operand at backtrack_pos. */
7883 str
= backtrack_pos
;
7886 /* Clear any error record after the omitted optional operand has been
7887 successfully handled. */
7891 /* Check if we have parsed all the operands. */
7892 if (*str
!= '\0' && ! error_p ())
7894 /* Set I to the index of the last present operand; this is
7895 for the purpose of diagnostics. */
7896 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7898 set_fatal_syntax_error
7899 (_("unexpected characters following instruction"));
7902 parse_operands_return
:
7906 inst
.parsing_error
.index
= i
;
7907 DEBUG_TRACE ("parsing FAIL: %s - %s",
7908 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7909 inst
.parsing_error
.error
);
7910 /* Record the operand error properly; this is useful when there
7911 are multiple instruction templates for a mnemonic name, so that
7912 later on, we can select the error that most closely describes
7914 record_operand_error_info (opcode
, &inst
.parsing_error
);
7919 DEBUG_TRACE ("parsing SUCCESS");
7924 /* It does some fix-up to provide some programmer friendly feature while
7925 keeping the libopcodes happy, i.e. libopcodes only accepts
7926 the preferred architectural syntax.
7927 Return FALSE if there is any failure; otherwise return TRUE. */
7930 programmer_friendly_fixup (aarch64_instruction
*instr
)
7932 aarch64_inst
*base
= &instr
->base
;
7933 const aarch64_opcode
*opcode
= base
->opcode
;
7934 enum aarch64_op op
= opcode
->op
;
7935 aarch64_opnd_info
*operands
= base
->operands
;
7937 DEBUG_TRACE ("enter");
7939 switch (opcode
->iclass
)
7942 /* TBNZ Xn|Wn, #uimm6, label
7943 Test and Branch Not Zero: conditionally jumps to label if bit number
7944 uimm6 in register Xn is not zero. The bit number implies the width of
7945 the register, which may be written and should be disassembled as Wn if
7946 uimm is less than 32. */
7947 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7949 if (operands
[1].imm
.value
>= 32)
7951 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7955 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7959 /* LDR Wt, label | =value
7960 As a convenience assemblers will typically permit the notation
7961 "=value" in conjunction with the pc-relative literal load instructions
7962 to automatically place an immediate value or symbolic address in a
7963 nearby literal pool and generate a hidden label which references it.
7964 ISREG has been set to 0 in the case of =value. */
7965 if (instr
->gen_lit_pool
7966 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7968 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7969 if (op
== OP_LDRSW_LIT
)
7971 if (instr
->reloc
.exp
.X_op
!= O_constant
7972 && instr
->reloc
.exp
.X_op
!= O_big
7973 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7975 record_operand_error (opcode
, 1,
7976 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7977 _("constant expression expected"));
7980 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7982 record_operand_error (opcode
, 1,
7983 AARCH64_OPDE_OTHER_ERROR
,
7984 _("literal pool insertion failed"));
7992 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7993 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7994 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7995 A programmer-friendly assembler should accept a destination Xd in
7996 place of Wd, however that is not the preferred form for disassembly.
7998 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7999 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
8000 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
8001 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
8006 /* In the 64-bit form, the final register operand is written as Wm
8007 for all but the (possibly omitted) UXTX/LSL and SXTX
8009 As a programmer-friendly assembler, we accept e.g.
8010 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
8011 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
8012 int idx
= aarch64_operand_index (opcode
->operands
,
8013 AARCH64_OPND_Rm_EXT
);
8014 gas_assert (idx
== 1 || idx
== 2);
8015 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
8016 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
8017 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
8018 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
8019 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
8020 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
8028 DEBUG_TRACE ("exit with SUCCESS");
8032 /* Check for loads and stores that will cause unpredictable behavior. */
8035 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
8037 aarch64_inst
*base
= &instr
->base
;
8038 const aarch64_opcode
*opcode
= base
->opcode
;
8039 const aarch64_opnd_info
*opnds
= base
->operands
;
8040 switch (opcode
->iclass
)
8047 /* Loading/storing the base register is unpredictable if writeback. */
8048 if ((aarch64_get_operand_class (opnds
[0].type
)
8049 == AARCH64_OPND_CLASS_INT_REG
)
8050 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
8051 && opnds
[1].addr
.base_regno
!= REG_SP
8052 /* Exempt STG/STZG/ST2G/STZ2G. */
8053 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
8054 && opnds
[1].addr
.writeback
)
8055 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8059 case ldstnapair_offs
:
8060 case ldstpair_indexed
:
8061 /* Loading/storing the base register is unpredictable if writeback. */
8062 if ((aarch64_get_operand_class (opnds
[0].type
)
8063 == AARCH64_OPND_CLASS_INT_REG
)
8064 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
8065 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
8066 && opnds
[2].addr
.base_regno
!= REG_SP
8068 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
8069 && opnds
[2].addr
.writeback
)
8070 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8071 /* Load operations must load different registers. */
8072 if ((opcode
->opcode
& (1 << 22))
8073 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8074 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8078 if ((aarch64_get_operand_class (opnds
[0].type
)
8079 == AARCH64_OPND_CLASS_INT_REG
)
8080 && (aarch64_get_operand_class (opnds
[1].type
)
8081 == AARCH64_OPND_CLASS_INT_REG
))
8083 if ((opcode
->opcode
& (1 << 22)))
8085 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
8086 if ((opcode
->opcode
& (1 << 21))
8087 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8088 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8092 /* Store-Exclusive is unpredictable if Rt == Rs. */
8093 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8095 (_("unpredictable: identical transfer and status registers"
8098 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
8100 if (!(opcode
->opcode
& (1 << 21)))
8101 /* Store-Exclusive is unpredictable if Rn == Rs. */
8103 (_("unpredictable: identical base and status registers"
8106 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
8108 (_("unpredictable: "
8109 "identical transfer and status registers"
8113 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
8114 if ((opcode
->opcode
& (1 << 21))
8115 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
8116 && opnds
[3].reg
.regno
!= REG_SP
)
8117 as_warn (_("unpredictable: identical base and status registers"
8129 force_automatic_sequence_close (void)
8131 struct aarch64_segment_info_type
*tc_seg_info
;
8133 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8134 if (tc_seg_info
->insn_sequence
.instr
)
8136 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
8137 _("previous `%s' sequence has not been closed"),
8138 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
8139 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
8143 /* A wrapper function to interface with libopcodes on encoding and
8144 record the error message if there is any.
8146 Return TRUE on success; otherwise return FALSE. */
8149 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
8152 aarch64_operand_error error_info
;
8153 memset (&error_info
, '\0', sizeof (error_info
));
8154 error_info
.kind
= AARCH64_OPDE_NIL
;
8155 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
8156 && !error_info
.non_fatal
)
8159 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
8160 record_operand_error_info (opcode
, &error_info
);
8161 return error_info
.non_fatal
;
8164 #ifdef DEBUG_AARCH64
8166 dump_opcode_operands (const aarch64_opcode
*opcode
)
8169 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
8171 aarch64_verbose ("\t\t opnd%d: %s", i
,
8172 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
8173 ? aarch64_get_operand_name (opcode
->operands
[i
])
8174 : aarch64_get_operand_desc (opcode
->operands
[i
]));
8178 #endif /* DEBUG_AARCH64 */
8180 /* This is the guts of the machine-dependent assembler. STR points to a
8181 machine dependent instruction. This function is supposed to emit
8182 the frags/bytes it assembles to. */
8185 md_assemble (char *str
)
8187 templates
*template;
8188 const aarch64_opcode
*opcode
;
8189 struct aarch64_segment_info_type
*tc_seg_info
;
8190 aarch64_inst
*inst_base
;
8191 unsigned saved_cond
;
8193 /* Align the previous label if needed. */
8194 if (last_label_seen
!= NULL
)
8196 symbol_set_frag (last_label_seen
, frag_now
);
8197 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8198 S_SET_SEGMENT (last_label_seen
, now_seg
);
8201 /* Update the current insn_sequence from the segment. */
8202 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8203 insn_sequence
= &tc_seg_info
->insn_sequence
;
8204 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8206 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8208 DEBUG_TRACE ("\n\n");
8209 DEBUG_TRACE ("==============================");
8210 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8212 /* Scan up to the end of the mnemonic, which must end in whitespace,
8213 '.', or end of string. */
8216 for (; is_part_of_name (*p
); p
++)
8217 if (*p
== '.' && !dot
)
8222 as_bad (_("unknown mnemonic -- `%s'"), str
);
8226 if (!dot
&& create_register_alias (str
, p
))
8229 template = opcode_lookup (str
, dot
, p
);
8232 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8237 skip_whitespace (p
);
8240 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8241 get_mnemonic_name (str
), str
);
8245 init_operand_error_report ();
8247 /* Sections are assumed to start aligned. In executable section, there is no
8248 MAP_DATA symbol pending. So we only align the address during
8249 MAP_DATA --> MAP_INSN transition.
8250 For other sections, this is not guaranteed. */
8251 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8252 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8253 frag_align_code (2, 0);
8255 saved_cond
= inst
.cond
;
8256 reset_aarch64_instruction (&inst
);
8257 inst
.cond
= saved_cond
;
8259 /* Iterate through all opcode entries with the same mnemonic name. */
8262 opcode
= template->opcode
;
8264 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8265 #ifdef DEBUG_AARCH64
8267 dump_opcode_operands (opcode
);
8268 #endif /* DEBUG_AARCH64 */
8270 mapping_state (MAP_INSN
);
8272 inst_base
= &inst
.base
;
8273 inst_base
->opcode
= opcode
;
8275 /* Truly conditionally executed instructions, e.g. b.cond. */
8276 if (opcode
->flags
& F_COND
)
8278 gas_assert (inst
.cond
!= COND_ALWAYS
);
8279 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8280 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8282 else if (inst
.cond
!= COND_ALWAYS
)
8284 /* It shouldn't arrive here, where the assembly looks like a
8285 conditional instruction but the found opcode is unconditional. */
8290 if (parse_operands (p
, opcode
)
8291 && programmer_friendly_fixup (&inst
)
8292 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8294 /* Check that this instruction is supported for this CPU. */
8295 if (!aarch64_cpu_supports_inst_p (cpu_variant
, inst_base
))
8297 as_bad (_("selected processor does not support `%s'"), str
);
8301 warn_unpredictable_ldst (&inst
, str
);
8303 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8304 || !inst
.reloc
.need_libopcodes_p
)
8308 /* If there is relocation generated for the instruction,
8309 store the instruction information for the future fix-up. */
8310 struct aarch64_inst
*copy
;
8311 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8312 copy
= XNEW (struct aarch64_inst
);
8313 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8317 /* Issue non-fatal messages if any. */
8318 output_operand_error_report (str
, true);
8322 template = template->next
;
8323 if (template != NULL
)
8325 reset_aarch64_instruction (&inst
);
8326 inst
.cond
= saved_cond
;
8329 while (template != NULL
);
8331 /* Issue the error messages if any. */
8332 output_operand_error_report (str
, false);
8335 /* Various frobbings of labels and their addresses. */
8338 aarch64_start_line_hook (void)
8340 last_label_seen
= NULL
;
8344 aarch64_frob_label (symbolS
* sym
)
8346 last_label_seen
= sym
;
8348 dwarf2_emit_label (sym
);
8352 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8354 /* Check to see if we have a block to close. */
8355 force_automatic_sequence_close ();
8359 aarch64_data_in_code (void)
8361 if (startswith (input_line_pointer
+ 1, "data:"))
8363 *input_line_pointer
= '/';
8364 input_line_pointer
+= 5;
8365 *input_line_pointer
= 0;
8373 aarch64_canonicalize_symbol_name (char *name
)
8377 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8378 *(name
+ len
- 5) = 0;
8383 /* Table of all register names defined by default. The user can
8384 define additional names with .req. Note that all register names
8385 should appear in both upper and lowercase variants. Some registers
8386 also have mixed-case names. */
8388 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8389 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8390 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8391 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8392 #define REGSET16(p,t) \
8393 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8394 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8395 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8396 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8397 #define REGSET16S(p,s,t) \
8398 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8399 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8400 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8401 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8402 #define REGSET31(p,t) \
8404 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8405 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8406 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8407 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8408 #define REGSET(p,t) \
8409 REGSET31(p,t), REGNUM(p,31,t)
8411 /* These go into aarch64_reg_hsh hash-table. */
8412 static const reg_entry reg_names
[] = {
8413 /* Integer registers. */
8414 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8415 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8417 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8418 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8419 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8420 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8421 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8422 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8424 REGDEF (wzr
, 31, ZR_32
), REGDEF (WZR
, 31, ZR_32
),
8425 REGDEF (xzr
, 31, ZR_64
), REGDEF (XZR
, 31, ZR_64
),
8427 /* Floating-point single precision registers. */
8428 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8430 /* Floating-point double precision registers. */
8431 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8433 /* Floating-point half precision registers. */
8434 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8436 /* Floating-point byte precision registers. */
8437 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8439 /* Floating-point quad precision registers. */
8440 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8442 /* FP/SIMD registers. */
8443 REGSET (v
, V
), REGSET (V
, V
),
8445 /* SVE vector registers. */
8446 REGSET (z
, Z
), REGSET (Z
, Z
),
8448 /* SVE predicate(-as-mask) registers. */
8449 REGSET16 (p
, P
), REGSET16 (P
, P
),
8451 /* SVE predicate-as-counter registers. */
8452 REGSET16 (pn
, PN
), REGSET16 (PN
, PN
),
8454 /* SME ZA. We model this as a register because it acts syntactically
8455 like ZA0H, supporting qualifier suffixes and indexing. */
8456 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8458 /* SME ZA tile registers. */
8459 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8461 /* SME ZA tile registers (horizontal slice). */
8462 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8464 /* SME ZA tile registers (vertical slice). */
8465 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8483 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8484 static const asm_nzcv nzcv_names
[] = {
8485 {"nzcv", B (n
, z
, c
, v
)},
8486 {"nzcV", B (n
, z
, c
, V
)},
8487 {"nzCv", B (n
, z
, C
, v
)},
8488 {"nzCV", B (n
, z
, C
, V
)},
8489 {"nZcv", B (n
, Z
, c
, v
)},
8490 {"nZcV", B (n
, Z
, c
, V
)},
8491 {"nZCv", B (n
, Z
, C
, v
)},
8492 {"nZCV", B (n
, Z
, C
, V
)},
8493 {"Nzcv", B (N
, z
, c
, v
)},
8494 {"NzcV", B (N
, z
, c
, V
)},
8495 {"NzCv", B (N
, z
, C
, v
)},
8496 {"NzCV", B (N
, z
, C
, V
)},
8497 {"NZcv", B (N
, Z
, c
, v
)},
8498 {"NZcV", B (N
, Z
, c
, V
)},
8499 {"NZCv", B (N
, Z
, C
, v
)},
8500 {"NZCV", B (N
, Z
, C
, V
)}
8513 /* MD interface: bits in the object file. */
8515 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8516 for use in the a.out file, and stores them in the array pointed to by buf.
8517 This knows about the endian-ness of the target machine and does
8518 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8519 2 (short) and 4 (long) Floating numbers are put out as a series of
8520 LITTLENUMS (shorts, here at least). */
8523 md_number_to_chars (char *buf
, valueT val
, int n
)
8525 if (target_big_endian
)
8526 number_to_chars_bigendian (buf
, val
, n
);
8528 number_to_chars_littleendian (buf
, val
, n
);
8531 /* MD interface: Sections. */
8533 /* Estimate the size of a frag before relaxing. Assume everything fits in
8537 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8543 /* Round up a section size to the appropriate boundary. */
8546 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8551 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8552 of an rs_align_code fragment.
8554 Here we fill the frag with the appropriate info for padding the
8555 output stream. The resulting frag will consist of a fixed (fr_fix)
8556 and of a repeating (fr_var) part.
8558 The fixed content is always emitted before the repeating content and
8559 these two parts are used as follows in constructing the output:
8560 - the fixed part will be used to align to a valid instruction word
8561 boundary, in case that we start at a misaligned address; as no
8562 executable instruction can live at the misaligned location, we
8563 simply fill with zeros;
8564 - the variable part will be used to cover the remaining padding and
8565 we fill using the AArch64 NOP instruction.
8567 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8568 enough storage space for up to 3 bytes for padding the back to a valid
8569 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8572 aarch64_handle_align (fragS
* fragP
)
8574 /* NOP = d503201f */
8575 /* AArch64 instructions are always little-endian. */
8576 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8578 int bytes
, fix
, noop_size
;
8581 if (fragP
->fr_type
!= rs_align_code
)
8584 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8585 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8588 gas_assert (fragP
->tc_frag_data
.recorded
);
8591 noop_size
= sizeof (aarch64_noop
);
8593 fix
= bytes
& (noop_size
- 1);
8596 #if defined OBJ_ELF || defined OBJ_COFF
8597 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8601 fragP
->fr_fix
+= fix
;
8605 memcpy (p
, aarch64_noop
, noop_size
);
8606 fragP
->fr_var
= noop_size
;
8609 /* Perform target specific initialisation of a frag.
8610 Note - despite the name this initialisation is not done when the frag
8611 is created, but only when its type is assigned. A frag can be created
8612 and used a long time before its type is set, so beware of assuming that
8613 this initialisation is performed first. */
8617 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8618 int max_chars ATTRIBUTE_UNUSED
)
8622 #else /* OBJ_ELF is defined. */
8624 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8626 /* Record a mapping symbol for alignment frags. We will delete this
8627 later if the alignment ends up empty. */
8628 if (!fragP
->tc_frag_data
.recorded
)
8629 fragP
->tc_frag_data
.recorded
= 1;
8631 /* PR 21809: Do not set a mapping state for debug sections
8632 - it just confuses other tools. */
8633 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8636 switch (fragP
->fr_type
)
8640 mapping_state_2 (MAP_DATA
, max_chars
);
8643 /* PR 20364: We can get alignment frags in code sections,
8644 so do not just assume that we should use the MAP_DATA state. */
8645 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8648 mapping_state_2 (MAP_INSN
, max_chars
);
8655 /* Whether SFrame stack trace info is supported. */
8658 aarch64_support_sframe_p (void)
8660 /* At this time, SFrame is supported for aarch64 only. */
8661 return (aarch64_abi
== AARCH64_ABI_LP64
);
8664 /* Specify if RA tracking is needed. */
8667 aarch64_sframe_ra_tracking_p (void)
8672 /* Specify the fixed offset to recover RA from CFA.
8673 (useful only when RA tracking is not needed). */
8676 aarch64_sframe_cfa_ra_offset (void)
8678 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8681 /* Get the abi/arch indentifier for SFrame. */
8684 aarch64_sframe_get_abi_arch (void)
8686 unsigned char sframe_abi_arch
= 0;
8688 if (aarch64_support_sframe_p ())
8690 sframe_abi_arch
= target_big_endian
8691 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8692 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8695 return sframe_abi_arch
;
8698 #endif /* OBJ_ELF */
8700 /* Initialize the DWARF-2 unwind information for this procedure. */
8703 tc_aarch64_frame_initial_instructions (void)
8705 cfi_add_CFA_def_cfa (REG_SP
, 0);
8708 /* Convert REGNAME to a DWARF-2 register number. */
8711 tc_aarch64_regname_to_dw2regnum (char *regname
)
8713 const reg_entry
*reg
= parse_reg (®name
);
8719 case REG_TYPE_SP_32
:
8720 case REG_TYPE_SP_64
:
8730 return reg
->number
+ 64;
8738 /* Implement DWARF2_ADDR_SIZE. */
8741 aarch64_dwarf2_addr_size (void)
8747 return bfd_arch_bits_per_address (stdoutput
) / 8;
8750 /* MD interface: Symbol and relocation handling. */
8752 /* Return the address within the segment that a PC-relative fixup is
8753 relative to. For AArch64 PC-relative fixups applied to instructions
8754 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8757 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8759 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8761 /* If this is pc-relative and we are going to emit a relocation
8762 then we just want to put out any pipeline compensation that the linker
8763 will need. Otherwise we want to use the calculated base. */
8765 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8766 || aarch64_force_relocation (fixP
)))
8769 /* AArch64 should be consistent for all pc-relative relocations. */
8770 return base
+ AARCH64_PCREL_OFFSET
;
8773 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8774 Otherwise we have no need to default values of symbols. */
8777 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8780 if (name
[0] == '_' && name
[1] == 'G'
8781 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8785 if (symbol_find (name
))
8786 as_bad (_("GOT already in the symbol table"));
8788 GOT_symbol
= symbol_new (name
, undefined_section
,
8789 &zero_address_frag
, 0);
8799 /* Return non-zero if the indicated VALUE has overflowed the maximum
8800 range expressible by a unsigned number with the indicated number of
8804 unsigned_overflow (valueT value
, unsigned bits
)
8807 if (bits
>= sizeof (valueT
) * 8)
8809 lim
= (valueT
) 1 << bits
;
8810 return (value
>= lim
);
8814 /* Return non-zero if the indicated VALUE has overflowed the maximum
8815 range expressible by an signed number with the indicated number of
8819 signed_overflow (offsetT value
, unsigned bits
)
8822 if (bits
>= sizeof (offsetT
) * 8)
8824 lim
= (offsetT
) 1 << (bits
- 1);
8825 return (value
< -lim
|| value
>= lim
);
8828 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8829 unsigned immediate offset load/store instruction, try to encode it as
8830 an unscaled, 9-bit, signed immediate offset load/store instruction.
8831 Return TRUE if it is successful; otherwise return FALSE.
8833 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8834 in response to the standard LDR/STR mnemonics when the immediate offset is
8835 unambiguous, i.e. when it is negative or unaligned. */
8838 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8841 enum aarch64_op new_op
;
8842 const aarch64_opcode
*new_opcode
;
8844 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8846 switch (instr
->opcode
->op
)
8848 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8849 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8850 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8851 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8852 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8853 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8854 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8855 case OP_STR_POS
: new_op
= OP_STUR
; break;
8856 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8857 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8858 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8859 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8860 default: new_op
= OP_NIL
; break;
8863 if (new_op
== OP_NIL
)
8866 new_opcode
= aarch64_get_opcode (new_op
);
8867 gas_assert (new_opcode
!= NULL
);
8869 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8870 instr
->opcode
->op
, new_opcode
->op
);
8872 aarch64_replace_opcode (instr
, new_opcode
);
8874 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8875 qualifier matching may fail because the out-of-date qualifier will
8876 prevent the operand being updated with a new and correct qualifier. */
8877 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8878 AARCH64_OPND_ADDR_SIMM9
);
8879 gas_assert (idx
== 1);
8880 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8882 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8884 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8891 /* Called by fix_insn to fix a MOV immediate alias instruction.
8893 Operand for a generic move immediate instruction, which is an alias
8894 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8895 a 32-bit/64-bit immediate value into general register. An assembler error
8896 shall result if the immediate cannot be created by a single one of these
8897 instructions. If there is a choice, then to ensure reversability an
8898 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8901 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8903 const aarch64_opcode
*opcode
;
8905 /* Need to check if the destination is SP/ZR. The check has to be done
8906 before any aarch64_replace_opcode. */
8907 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8908 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8910 instr
->operands
[1].imm
.value
= value
;
8911 instr
->operands
[1].skip
= 0;
8915 /* Try the MOVZ alias. */
8916 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8917 aarch64_replace_opcode (instr
, opcode
);
8918 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8919 &instr
->value
, NULL
, NULL
, insn_sequence
))
8921 put_aarch64_insn (buf
, instr
->value
);
8924 /* Try the MOVK alias. */
8925 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8926 aarch64_replace_opcode (instr
, opcode
);
8927 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8928 &instr
->value
, NULL
, NULL
, insn_sequence
))
8930 put_aarch64_insn (buf
, instr
->value
);
8935 if (try_mov_bitmask_p
)
8937 /* Try the ORR alias. */
8938 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8939 aarch64_replace_opcode (instr
, opcode
);
8940 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8941 &instr
->value
, NULL
, NULL
, insn_sequence
))
8943 put_aarch64_insn (buf
, instr
->value
);
8948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8949 _("immediate cannot be moved by a single instruction"));
8952 /* An instruction operand which is immediate related may have symbol used
8953 in the assembly, e.g.
8956 .set u32, 0x00ffff00
8958 At the time when the assembly instruction is parsed, a referenced symbol,
8959 like 'u32' in the above example may not have been seen; a fixS is created
8960 in such a case and is handled here after symbols have been resolved.
8961 Instruction is fixed up with VALUE using the information in *FIXP plus
8962 extra information in FLAGS.
8964 This function is called by md_apply_fix to fix up instructions that need
8965 a fix-up described above but does not involve any linker-time relocation. */
8968 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8972 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8973 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8974 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8978 /* Now the instruction is about to be fixed-up, so the operand that
8979 was previously marked as 'ignored' needs to be unmarked in order
8980 to get the encoding done properly. */
8981 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8982 new_inst
->operands
[idx
].skip
= 0;
8985 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8989 case AARCH64_OPND_EXCEPTION
:
8990 case AARCH64_OPND_UNDEFINED
:
8991 if (unsigned_overflow (value
, 16))
8992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8993 _("immediate out of range"));
8994 insn
= get_aarch64_insn (buf
);
8995 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8996 put_aarch64_insn (buf
, insn
);
8999 case AARCH64_OPND_AIMM
:
9000 /* ADD or SUB with immediate.
9001 NOTE this assumes we come here with a add/sub shifted reg encoding
9002 3 322|2222|2 2 2 21111 111111
9003 1 098|7654|3 2 1 09876 543210 98765 43210
9004 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
9005 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
9006 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
9007 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
9009 3 322|2222|2 2 221111111111
9010 1 098|7654|3 2 109876543210 98765 43210
9011 11000000 sf 001|0001|shift imm12 Rn Rd ADD
9012 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
9013 51000000 sf 101|0001|shift imm12 Rn Rd SUB
9014 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
9015 Fields sf Rn Rd are already set. */
9016 insn
= get_aarch64_insn (buf
);
9020 insn
= reencode_addsub_switch_add_sub (insn
);
9024 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
9025 && unsigned_overflow (value
, 12))
9027 /* Try to shift the value by 12 to make it fit. */
9028 if (((value
>> 12) << 12) == value
9029 && ! unsigned_overflow (value
, 12 + 12))
9032 insn
|= encode_addsub_imm_shift_amount (1);
9036 if (unsigned_overflow (value
, 12))
9037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9038 _("immediate out of range"));
9040 insn
|= encode_addsub_imm (value
);
9042 put_aarch64_insn (buf
, insn
);
9045 case AARCH64_OPND_SIMD_IMM
:
9046 case AARCH64_OPND_SIMD_IMM_SFT
:
9047 case AARCH64_OPND_LIMM
:
9048 /* Bit mask immediate. */
9049 gas_assert (new_inst
!= NULL
);
9050 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
9051 new_inst
->operands
[idx
].imm
.value
= value
;
9052 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9053 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9054 put_aarch64_insn (buf
, new_inst
->value
);
9056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9057 _("invalid immediate"));
9060 case AARCH64_OPND_HALF
:
9061 /* 16-bit unsigned immediate. */
9062 if (unsigned_overflow (value
, 16))
9063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9064 _("immediate out of range"));
9065 insn
= get_aarch64_insn (buf
);
9066 insn
|= encode_movw_imm (value
& 0xffff);
9067 put_aarch64_insn (buf
, insn
);
9070 case AARCH64_OPND_IMM_MOV
:
9071 /* Operand for a generic move immediate instruction, which is
9072 an alias instruction that generates a single MOVZ, MOVN or ORR
9073 instruction to loads a 32-bit/64-bit immediate value into general
9074 register. An assembler error shall result if the immediate cannot be
9075 created by a single one of these instructions. If there is a choice,
9076 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
9077 and MOVZ or MOVN to ORR. */
9078 gas_assert (new_inst
!= NULL
);
9079 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
9082 case AARCH64_OPND_ADDR_SIMM7
:
9083 case AARCH64_OPND_ADDR_SIMM9
:
9084 case AARCH64_OPND_ADDR_SIMM9_2
:
9085 case AARCH64_OPND_ADDR_SIMM10
:
9086 case AARCH64_OPND_ADDR_UIMM12
:
9087 case AARCH64_OPND_ADDR_SIMM11
:
9088 case AARCH64_OPND_ADDR_SIMM13
:
9089 /* Immediate offset in an address. */
9090 insn
= get_aarch64_insn (buf
);
9092 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
9093 gas_assert (new_inst
->opcode
->operands
[1] == opnd
9094 || new_inst
->opcode
->operands
[2] == opnd
);
9096 /* Get the index of the address operand. */
9097 if (new_inst
->opcode
->operands
[1] == opnd
)
9098 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
9101 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
9104 /* Update the resolved offset value. */
9105 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
9107 /* Encode/fix-up. */
9108 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9109 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9111 put_aarch64_insn (buf
, new_inst
->value
);
9114 else if (new_inst
->opcode
->iclass
== ldst_pos
9115 && try_to_encode_as_unscaled_ldst (new_inst
))
9117 put_aarch64_insn (buf
, new_inst
->value
);
9121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9122 _("immediate offset out of range"));
9127 as_fatal (_("unhandled operand code %d"), opnd
);
9131 /* Apply a fixup (fixP) to segment data, once it has been determined
9132 by our caller that we have all the info we need to fix it up.
9134 Parameter valP is the pointer to the value of the bits. */
9137 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
9139 offsetT value
= *valP
;
9141 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9143 unsigned flags
= fixP
->fx_addnumber
;
9145 DEBUG_TRACE ("\n\n");
9146 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
9147 DEBUG_TRACE ("Enter md_apply_fix");
9149 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
9151 /* Note whether this will delete the relocation. */
9153 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
9154 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
9157 /* Process the relocations. */
9158 switch (fixP
->fx_r_type
)
9160 case BFD_RELOC_NONE
:
9161 /* This will need to go in the object file. */
9166 case BFD_RELOC_8_PCREL
:
9167 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9168 md_number_to_chars (buf
, value
, 1);
9172 case BFD_RELOC_16_PCREL
:
9173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9174 md_number_to_chars (buf
, value
, 2);
9178 case BFD_RELOC_32_PCREL
:
9179 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9180 md_number_to_chars (buf
, value
, 4);
9184 case BFD_RELOC_64_PCREL
:
9185 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9186 md_number_to_chars (buf
, value
, 8);
9189 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9190 /* We claim that these fixups have been processed here, even if
9191 in fact we generate an error because we do not have a reloc
9192 for them, so tc_gen_reloc() will reject them. */
9194 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
9196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9197 _("undefined symbol %s used as an immediate value"),
9198 S_GET_NAME (fixP
->fx_addsy
));
9199 goto apply_fix_return
;
9201 fix_insn (fixP
, flags
, value
);
9204 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
9205 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9209 _("pc-relative load offset not word aligned"));
9210 if (signed_overflow (value
, 21))
9211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9212 _("pc-relative load offset out of range"));
9213 insn
= get_aarch64_insn (buf
);
9214 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9215 put_aarch64_insn (buf
, insn
);
9219 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9220 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9222 if (signed_overflow (value
, 21))
9223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9224 _("pc-relative address offset out of range"));
9225 insn
= get_aarch64_insn (buf
);
9226 insn
|= encode_adr_imm (value
);
9227 put_aarch64_insn (buf
, insn
);
9231 case BFD_RELOC_AARCH64_BRANCH19
:
9232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9236 _("conditional branch target not word aligned"));
9237 if (signed_overflow (value
, 21))
9238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9239 _("conditional branch out of range"));
9240 insn
= get_aarch64_insn (buf
);
9241 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9242 put_aarch64_insn (buf
, insn
);
9246 case BFD_RELOC_AARCH64_TSTBR14
:
9247 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9251 _("conditional branch target not word aligned"));
9252 if (signed_overflow (value
, 16))
9253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9254 _("conditional branch out of range"));
9255 insn
= get_aarch64_insn (buf
);
9256 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9257 put_aarch64_insn (buf
, insn
);
9261 case BFD_RELOC_AARCH64_CALL26
:
9262 case BFD_RELOC_AARCH64_JUMP26
:
9263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9267 _("branch target not word aligned"));
9268 if (signed_overflow (value
, 28))
9269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9270 _("branch out of range"));
9271 insn
= get_aarch64_insn (buf
);
9272 insn
|= encode_branch_ofs_26 (value
>> 2);
9273 put_aarch64_insn (buf
, insn
);
9277 case BFD_RELOC_AARCH64_MOVW_G0
:
9278 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9279 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9280 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9281 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9282 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9285 case BFD_RELOC_AARCH64_MOVW_G1
:
9286 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9287 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9288 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9289 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9290 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9293 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9295 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9296 /* Should always be exported to object file, see
9297 aarch64_force_relocation(). */
9298 gas_assert (!fixP
->fx_done
);
9299 gas_assert (seg
->use_rela_p
);
9301 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9303 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9304 /* Should always be exported to object file, see
9305 aarch64_force_relocation(). */
9306 gas_assert (!fixP
->fx_done
);
9307 gas_assert (seg
->use_rela_p
);
9309 case BFD_RELOC_AARCH64_MOVW_G2
:
9310 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9311 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9312 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9313 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9316 case BFD_RELOC_AARCH64_MOVW_G3
:
9317 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9320 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9322 insn
= get_aarch64_insn (buf
);
9326 /* REL signed addend must fit in 16 bits */
9327 if (signed_overflow (value
, 16))
9328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9329 _("offset out of range"));
9333 /* Check for overflow and scale. */
9334 switch (fixP
->fx_r_type
)
9336 case BFD_RELOC_AARCH64_MOVW_G0
:
9337 case BFD_RELOC_AARCH64_MOVW_G1
:
9338 case BFD_RELOC_AARCH64_MOVW_G2
:
9339 case BFD_RELOC_AARCH64_MOVW_G3
:
9340 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9341 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9342 if (unsigned_overflow (value
, scale
+ 16))
9343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9344 _("unsigned value out of range"));
9346 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9347 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9348 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9349 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9350 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9351 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9352 /* NOTE: We can only come here with movz or movn. */
9353 if (signed_overflow (value
, scale
+ 16))
9354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9355 _("signed value out of range"));
9358 /* Force use of MOVN. */
9360 insn
= reencode_movzn_to_movn (insn
);
9364 /* Force use of MOVZ. */
9365 insn
= reencode_movzn_to_movz (insn
);
9369 /* Unchecked relocations. */
9375 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9376 insn
|= encode_movw_imm (value
& 0xffff);
9378 put_aarch64_insn (buf
, insn
);
9382 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9383 fixP
->fx_r_type
= (ilp32_p
9384 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9385 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9386 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9387 /* Should always be exported to object file, see
9388 aarch64_force_relocation(). */
9389 gas_assert (!fixP
->fx_done
);
9390 gas_assert (seg
->use_rela_p
);
9393 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9394 fixP
->fx_r_type
= (ilp32_p
9395 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9396 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9397 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9398 /* Should always be exported to object file, see
9399 aarch64_force_relocation(). */
9400 gas_assert (!fixP
->fx_done
);
9401 gas_assert (seg
->use_rela_p
);
9404 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9405 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9406 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9407 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9408 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9409 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9410 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9411 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9412 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9413 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9414 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9415 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9416 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9417 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9418 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9419 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9420 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9421 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9422 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9423 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9424 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9425 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9426 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9427 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9428 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9429 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9430 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9431 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9432 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9433 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9434 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9435 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9436 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9437 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9438 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9439 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9440 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9441 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9442 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9443 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9444 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9445 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9446 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9447 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9448 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9449 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9450 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9451 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9452 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9453 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9454 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9455 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9456 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9457 /* Should always be exported to object file, see
9458 aarch64_force_relocation(). */
9459 gas_assert (!fixP
->fx_done
);
9460 gas_assert (seg
->use_rela_p
);
9463 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9464 /* Should always be exported to object file, see
9465 aarch64_force_relocation(). */
9466 fixP
->fx_r_type
= (ilp32_p
9467 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9468 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9469 gas_assert (!fixP
->fx_done
);
9470 gas_assert (seg
->use_rela_p
);
9473 case BFD_RELOC_AARCH64_ADD_LO12
:
9474 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9475 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9476 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9477 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9478 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9479 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9480 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9481 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9482 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9483 case BFD_RELOC_AARCH64_LDST128_LO12
:
9484 case BFD_RELOC_AARCH64_LDST16_LO12
:
9485 case BFD_RELOC_AARCH64_LDST32_LO12
:
9486 case BFD_RELOC_AARCH64_LDST64_LO12
:
9487 case BFD_RELOC_AARCH64_LDST8_LO12
:
9488 /* Should always be exported to object file, see
9489 aarch64_force_relocation(). */
9490 gas_assert (!fixP
->fx_done
);
9491 gas_assert (seg
->use_rela_p
);
9494 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9495 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9496 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9499 case BFD_RELOC_UNUSED
:
9500 /* An error will already have been reported. */
9504 case BFD_RELOC_32_SECREL
:
9505 case BFD_RELOC_16_SECIDX
:
9509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9510 _("unexpected %s fixup"),
9511 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9516 /* Free the allocated the struct aarch64_inst.
9517 N.B. currently there are very limited number of fix-up types actually use
9518 this field, so the impact on the performance should be minimal . */
9519 free (fixP
->tc_fix_data
.inst
);
9524 /* Translate internal representation of relocation info to BFD target
9528 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9531 bfd_reloc_code_real_type code
;
9533 reloc
= XNEW (arelent
);
9535 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9536 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9537 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9541 if (section
->use_rela_p
)
9542 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9544 fixp
->fx_offset
= reloc
->address
;
9546 reloc
->addend
= fixp
->fx_offset
;
9548 code
= fixp
->fx_r_type
;
9553 code
= BFD_RELOC_16_PCREL
;
9558 code
= BFD_RELOC_32_PCREL
;
9563 code
= BFD_RELOC_64_PCREL
;
9570 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9571 if (reloc
->howto
== NULL
)
9573 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9575 ("cannot represent %s relocation in this object file format"),
9576 bfd_get_reloc_code_name (code
));
9583 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9586 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9588 bfd_reloc_code_real_type type
;
9592 if (exp
->X_op
== O_secrel
)
9594 exp
->X_op
= O_symbol
;
9595 type
= BFD_RELOC_32_SECREL
;
9597 else if (exp
->X_op
== O_secidx
)
9599 exp
->X_op
= O_symbol
;
9600 type
= BFD_RELOC_16_SECIDX
;
9606 FIXME: @@ Should look at CPU word size. */
9613 type
= BFD_RELOC_16
;
9616 type
= BFD_RELOC_32
;
9619 type
= BFD_RELOC_64
;
9622 as_bad (_("cannot do %u-byte relocation"), size
);
9623 type
= BFD_RELOC_UNUSED
;
9630 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9633 /* Implement md_after_parse_args. This is the earliest time we need to decide
9634 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9637 aarch64_after_parse_args (void)
9639 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9643 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9644 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9645 aarch64_abi
= AARCH64_ABI_ILP32
;
9647 aarch64_abi
= AARCH64_ABI_LP64
;
9649 aarch64_abi
= AARCH64_ABI_LLP64
;
9655 elf64_aarch64_target_format (void)
9658 /* FIXME: What to do for ilp32_p ? */
9659 if (target_big_endian
)
9660 return "elf64-bigaarch64-cloudabi";
9662 return "elf64-littleaarch64-cloudabi";
9664 if (target_big_endian
)
9665 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9667 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9672 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9674 elf_frob_symbol (symp
, puntp
);
9676 #elif defined OBJ_COFF
9678 coff_aarch64_target_format (void)
9680 return "pe-aarch64-little";
9684 /* MD interface: Finalization. */
9686 /* A good place to do this, although this was probably not intended
9687 for this kind of use. We need to dump the literal pool before
9688 references are made to a null symbol pointer. */
9691 aarch64_cleanup (void)
9695 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9697 /* Put it at the end of the relevant section. */
9698 subseg_set (pool
->section
, pool
->sub_section
);
9704 /* Remove any excess mapping symbols generated for alignment frags in
9705 SEC. We may have created a mapping symbol before a zero byte
9706 alignment; remove it if there's a mapping symbol after the
9709 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9710 void *dummy ATTRIBUTE_UNUSED
)
9712 segment_info_type
*seginfo
= seg_info (sec
);
9715 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9718 for (fragp
= seginfo
->frchainP
->frch_root
;
9719 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9721 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9722 fragS
*next
= fragp
->fr_next
;
9724 /* Variable-sized frags have been converted to fixed size by
9725 this point. But if this was variable-sized to start with,
9726 there will be a fixed-size frag after it. So don't handle
9728 if (sym
== NULL
|| next
== NULL
)
9731 if (S_GET_VALUE (sym
) < next
->fr_address
)
9732 /* Not at the end of this frag. */
9734 know (S_GET_VALUE (sym
) == next
->fr_address
);
9738 if (next
->tc_frag_data
.first_map
!= NULL
)
9740 /* Next frag starts with a mapping symbol. Discard this
9742 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9746 if (next
->fr_next
== NULL
)
9748 /* This mapping symbol is at the end of the section. Discard
9750 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9751 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9755 /* As long as we have empty frags without any mapping symbols,
9757 /* If the next frag is non-empty and does not start with a
9758 mapping symbol, then this mapping symbol is required. */
9759 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9762 next
= next
->fr_next
;
9764 while (next
!= NULL
);
9769 /* Adjust the symbol table. */
9772 aarch64_adjust_symtab (void)
9775 /* Remove any overlapping mapping symbols generated by alignment frags. */
9776 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9777 /* Now do generic ELF adjustments. */
9778 elf_adjust_symtab ();
9783 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9785 str_hash_insert (table
, key
, value
, 0);
9789 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9791 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9792 checked_hash_insert (table
, key
, value
);
9796 fill_instruction_hash_table (void)
9798 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9800 while (opcode
->name
!= NULL
)
9802 templates
*templ
, *new_templ
;
9803 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9805 new_templ
= XNEW (templates
);
9806 new_templ
->opcode
= opcode
;
9807 new_templ
->next
= NULL
;
9810 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9813 new_templ
->next
= templ
->next
;
9814 templ
->next
= new_templ
;
9821 convert_to_upper (char *dst
, const char *src
, size_t num
)
9824 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9825 *dst
= TOUPPER (*src
);
9829 /* Assume STR point to a lower-case string, allocate, convert and return
9830 the corresponding upper-case string. */
9831 static inline const char*
9832 get_upper_str (const char *str
)
9835 size_t len
= strlen (str
);
9836 ret
= XNEWVEC (char, len
+ 1);
9837 convert_to_upper (ret
, str
, len
);
9841 /* MD interface: Initialization. */
9849 aarch64_ops_hsh
= str_htab_create ();
9850 aarch64_cond_hsh
= str_htab_create ();
9851 aarch64_shift_hsh
= str_htab_create ();
9852 aarch64_sys_regs_hsh
= str_htab_create ();
9853 aarch64_pstatefield_hsh
= str_htab_create ();
9854 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9855 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9856 aarch64_sys_regs_at_hsh
= str_htab_create ();
9857 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9858 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9859 aarch64_reg_hsh
= str_htab_create ();
9860 aarch64_barrier_opt_hsh
= str_htab_create ();
9861 aarch64_nzcv_hsh
= str_htab_create ();
9862 aarch64_pldop_hsh
= str_htab_create ();
9863 aarch64_hint_opt_hsh
= str_htab_create ();
9865 fill_instruction_hash_table ();
9867 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9868 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9869 (void *) (aarch64_sys_regs
+ i
));
9871 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9872 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9873 aarch64_pstatefields
[i
].name
,
9874 (void *) (aarch64_pstatefields
+ i
));
9876 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9877 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9878 aarch64_sys_regs_ic
[i
].name
,
9879 (void *) (aarch64_sys_regs_ic
+ i
));
9881 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9882 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9883 aarch64_sys_regs_dc
[i
].name
,
9884 (void *) (aarch64_sys_regs_dc
+ i
));
9886 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9887 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9888 aarch64_sys_regs_at
[i
].name
,
9889 (void *) (aarch64_sys_regs_at
+ i
));
9891 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9892 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9893 aarch64_sys_regs_tlbi
[i
].name
,
9894 (void *) (aarch64_sys_regs_tlbi
+ i
));
9896 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9897 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9898 aarch64_sys_regs_sr
[i
].name
,
9899 (void *) (aarch64_sys_regs_sr
+ i
));
9901 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9902 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9903 (void *) (reg_names
+ i
));
9905 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9906 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9907 (void *) (nzcv_names
+ i
));
9909 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9911 const char *name
= aarch64_operand_modifiers
[i
].name
;
9912 checked_hash_insert (aarch64_shift_hsh
, name
,
9913 (void *) (aarch64_operand_modifiers
+ i
));
9914 /* Also hash the name in the upper case. */
9915 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9916 (void *) (aarch64_operand_modifiers
+ i
));
9919 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9922 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9923 the same condition code. */
9924 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9926 const char *name
= aarch64_conds
[i
].names
[j
];
9929 checked_hash_insert (aarch64_cond_hsh
, name
,
9930 (void *) (aarch64_conds
+ i
));
9931 /* Also hash the name in the upper case. */
9932 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9933 (void *) (aarch64_conds
+ i
));
9937 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9939 const char *name
= aarch64_barrier_options
[i
].name
;
9940 /* Skip xx00 - the unallocated values of option. */
9943 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9944 (void *) (aarch64_barrier_options
+ i
));
9945 /* Also hash the name in the upper case. */
9946 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9947 (void *) (aarch64_barrier_options
+ i
));
9950 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9952 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9953 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9954 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9955 /* Also hash the name in the upper case. */
9956 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9957 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9960 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9962 const char* name
= aarch64_prfops
[i
].name
;
9963 /* Skip the unallocated hint encodings. */
9966 checked_hash_insert (aarch64_pldop_hsh
, name
,
9967 (void *) (aarch64_prfops
+ i
));
9968 /* Also hash the name in the upper case. */
9969 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9970 (void *) (aarch64_prfops
+ i
));
9973 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9975 const char* name
= aarch64_hint_options
[i
].name
;
9976 const char* upper_name
= get_upper_str(name
);
9978 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9979 (void *) (aarch64_hint_options
+ i
));
9981 /* Also hash the name in the upper case if not the same. */
9982 if (strcmp (name
, upper_name
) != 0)
9983 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9984 (void *) (aarch64_hint_options
+ i
));
9987 /* Set the cpu variant based on the command-line options. */
9989 mcpu_cpu_opt
= march_cpu_opt
;
9992 mcpu_cpu_opt
= &cpu_default
;
9994 cpu_variant
= *mcpu_cpu_opt
;
9996 /* Record the CPU type. */
9998 mach
= bfd_mach_aarch64_ilp32
;
10000 mach
= bfd_mach_aarch64_llp64
;
10002 mach
= bfd_mach_aarch64
;
10004 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
10006 /* FIXME - is there a better way to do it ? */
10007 aarch64_sframe_cfa_sp_reg
= 31;
10008 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
10009 aarch64_sframe_cfa_ra_reg
= 30;
10013 /* Command line processing. */
10015 const char *md_shortopts
= "m:";
10017 #ifdef AARCH64_BI_ENDIAN
10018 #define OPTION_EB (OPTION_MD_BASE + 0)
10019 #define OPTION_EL (OPTION_MD_BASE + 1)
10021 #if TARGET_BYTES_BIG_ENDIAN
10022 #define OPTION_EB (OPTION_MD_BASE + 0)
10024 #define OPTION_EL (OPTION_MD_BASE + 1)
10028 struct option md_longopts
[] = {
10030 {"EB", no_argument
, NULL
, OPTION_EB
},
10033 {"EL", no_argument
, NULL
, OPTION_EL
},
10035 {NULL
, no_argument
, NULL
, 0}
10038 size_t md_longopts_size
= sizeof (md_longopts
);
10040 struct aarch64_option_table
10042 const char *option
; /* Option name to match. */
10043 const char *help
; /* Help information. */
10044 int *var
; /* Variable to change. */
10045 int value
; /* What to change it to. */
10046 char *deprecated
; /* If non-null, print this message. */
10049 static struct aarch64_option_table aarch64_opts
[] = {
10050 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
10051 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
10053 #ifdef DEBUG_AARCH64
10054 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
10055 #endif /* DEBUG_AARCH64 */
10056 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
10058 {"mno-verbose-error", N_("do not output verbose error messages"),
10059 &verbose_error_p
, 0, NULL
},
10060 {NULL
, NULL
, NULL
, 0, NULL
}
10063 struct aarch64_cpu_option_table
10066 const aarch64_feature_set value
;
10067 /* The canonical name of the CPU, or NULL to use NAME converted to upper
10069 const char *canonical_name
;
10072 /* This list should, at a minimum, contain all the cpu names
10073 recognized by GCC. */
10074 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
10075 {"all", AARCH64_ANY
, NULL
},
10076 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10077 AARCH64_FEATURE_CRC
), "Cortex-A34"},
10078 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10079 AARCH64_FEATURE_CRC
), "Cortex-A35"},
10080 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10081 AARCH64_FEATURE_CRC
), "Cortex-A53"},
10082 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10083 AARCH64_FEATURE_CRC
), "Cortex-A57"},
10084 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10085 AARCH64_FEATURE_CRC
), "Cortex-A72"},
10086 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10087 AARCH64_FEATURE_CRC
), "Cortex-A73"},
10088 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10089 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10091 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10092 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10094 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10095 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10097 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10098 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10099 | AARCH64_FEATURE_DOTPROD
10100 | AARCH64_FEATURE_SSBS
),
10102 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10103 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10104 | AARCH64_FEATURE_DOTPROD
10105 | AARCH64_FEATURE_SSBS
),
10107 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10108 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10109 | AARCH64_FEATURE_DOTPROD
10110 | AARCH64_FEATURE_SSBS
),
10112 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10113 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10114 | AARCH64_FEATURE_DOTPROD
10115 | AARCH64_FEATURE_SSBS
),
10117 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10118 AARCH64_FEATURE_F16
10119 | AARCH64_FEATURE_RCPC
10120 | AARCH64_FEATURE_DOTPROD
10121 | AARCH64_FEATURE_SSBS
10122 | AARCH64_FEATURE_PROFILE
),
10124 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10125 AARCH64_FEATURE_F16
10126 | AARCH64_FEATURE_RCPC
10127 | AARCH64_FEATURE_DOTPROD
10128 | AARCH64_FEATURE_SSBS
10129 | AARCH64_FEATURE_PROFILE
),
10131 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10132 AARCH64_FEATURE_DOTPROD
10133 | AARCH64_FEATURE_F16
10134 | AARCH64_FEATURE_FLAGM
10135 | AARCH64_FEATURE_PAC
10136 | AARCH64_FEATURE_PROFILE
10137 | AARCH64_FEATURE_RCPC
10138 | AARCH64_FEATURE_SSBS
),
10140 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10141 AARCH64_FEATURE_BFLOAT16
10142 | AARCH64_FEATURE_I8MM
10143 | AARCH64_FEATURE_MEMTAG
10144 | AARCH64_FEATURE_SVE2_BITPERM
),
10146 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10147 AARCH64_FEATURE_BFLOAT16
10148 | AARCH64_FEATURE_I8MM
10149 | AARCH64_FEATURE_MEMTAG
10150 | AARCH64_FEATURE_SVE2_BITPERM
),
10152 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10153 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10154 | AARCH64_FEATURE_DOTPROD
10155 | AARCH64_FEATURE_PROFILE
),
10157 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10158 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10159 "Samsung Exynos M1"},
10160 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10161 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10162 | AARCH64_FEATURE_RDMA
),
10163 "Qualcomm Falkor"},
10164 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10165 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10166 | AARCH64_FEATURE_DOTPROD
10167 | AARCH64_FEATURE_SSBS
),
10169 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10170 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10171 | AARCH64_FEATURE_DOTPROD
10172 | AARCH64_FEATURE_PROFILE
),
10174 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
10175 AARCH64_FEATURE_BFLOAT16
10176 | AARCH64_FEATURE_I8MM
10177 | AARCH64_FEATURE_F16
10178 | AARCH64_FEATURE_SVE
10179 | AARCH64_FEATURE_SVE2
10180 | AARCH64_FEATURE_SVE2_BITPERM
10181 | AARCH64_FEATURE_MEMTAG
10182 | AARCH64_FEATURE_RNG
),
10184 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10185 AARCH64_FEATURE_PROFILE
10186 | AARCH64_FEATURE_CVADP
10187 | AARCH64_FEATURE_SVE
10188 | AARCH64_FEATURE_SSBS
10189 | AARCH64_FEATURE_RNG
10190 | AARCH64_FEATURE_F16
10191 | AARCH64_FEATURE_BFLOAT16
10192 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
10193 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10194 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10195 | AARCH64_FEATURE_RDMA
),
10196 "Qualcomm QDF24XX"},
10197 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10198 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
10199 "Qualcomm Saphira"},
10200 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10201 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10202 "Cavium ThunderX"},
10203 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
10204 AARCH64_FEATURE_CRYPTO
),
10205 "Broadcom Vulcan"},
10206 /* The 'xgene-1' name is an older name for 'xgene1', which was used
10207 in earlier releases and is superseded by 'xgene1' in all
10209 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10210 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10211 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10212 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10213 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10214 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10215 AARCH64_FEATURE_F16
10216 | AARCH64_FEATURE_RCPC
10217 | AARCH64_FEATURE_DOTPROD
10218 | AARCH64_FEATURE_SSBS
10219 | AARCH64_FEATURE_PROFILE
),
10221 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10222 AARCH64_FEATURE_BFLOAT16
10223 | AARCH64_FEATURE_I8MM
10224 | AARCH64_FEATURE_MEMTAG
10225 | AARCH64_FEATURE_SVE2_BITPERM
),
10227 {"generic", AARCH64_ARCH_V8
, NULL
},
10229 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10232 struct aarch64_arch_option_table
10235 const aarch64_feature_set value
;
10238 /* This list should, at a minimum, contain all the architecture names
10239 recognized by GCC. */
10240 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10241 {"all", AARCH64_ANY
},
10242 {"armv8-a", AARCH64_ARCH_V8
},
10243 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10244 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10245 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10246 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10247 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10248 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10249 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10250 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10251 {"armv8-r", AARCH64_ARCH_V8_R
},
10252 {"armv9-a", AARCH64_ARCH_V9
},
10253 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10254 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10255 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10256 {NULL
, AARCH64_ARCH_NONE
}
10259 /* ISA extensions. */
10260 struct aarch64_option_cpu_value_table
10263 const aarch64_feature_set value
;
10264 const aarch64_feature_set require
; /* Feature dependencies. */
10267 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10268 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10269 AARCH64_ARCH_NONE
},
10270 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10271 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10272 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10273 AARCH64_ARCH_NONE
},
10274 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10275 AARCH64_ARCH_NONE
},
10276 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10277 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10278 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10279 AARCH64_ARCH_NONE
},
10280 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10281 AARCH64_ARCH_NONE
},
10282 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10283 AARCH64_ARCH_NONE
},
10284 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10285 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10286 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10287 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10288 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10289 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10290 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10291 AARCH64_ARCH_NONE
},
10292 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10293 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10294 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10295 AARCH64_ARCH_NONE
},
10296 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10297 AARCH64_FEATURE (AARCH64_FEATURE_F16
10298 | AARCH64_FEATURE_SIMD
, 0)},
10299 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10300 AARCH64_ARCH_NONE
},
10301 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10302 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10303 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10304 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10305 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10306 AARCH64_ARCH_NONE
},
10307 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10308 AARCH64_ARCH_NONE
},
10309 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10310 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10311 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10312 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10313 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10314 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10315 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10316 AARCH64_ARCH_NONE
},
10317 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10318 AARCH64_ARCH_NONE
},
10319 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10320 AARCH64_ARCH_NONE
},
10321 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10322 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10323 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10324 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10325 | AARCH64_FEATURE_SM4
, 0)},
10326 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10327 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10328 | AARCH64_FEATURE_AES
, 0)},
10329 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10330 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10331 | AARCH64_FEATURE_SHA3
, 0)},
10332 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10333 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10334 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10335 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10336 | AARCH64_FEATURE_BFLOAT16
, 0)},
10337 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10338 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10339 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10340 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10341 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10342 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10343 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10344 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10345 {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2
, 0),
10346 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10347 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10348 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10349 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10350 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10351 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10352 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10353 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10354 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10355 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10356 AARCH64_ARCH_NONE
},
10357 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10358 AARCH64_ARCH_NONE
},
10359 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10360 AARCH64_ARCH_NONE
},
10361 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10362 AARCH64_ARCH_NONE
},
10363 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10364 AARCH64_ARCH_NONE
},
10365 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10366 AARCH64_ARCH_NONE
},
10367 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10370 struct aarch64_long_option_table
10372 const char *option
; /* Substring to match. */
10373 const char *help
; /* Help information. */
10374 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10375 char *deprecated
; /* If non-null, print this message. */
10378 /* Transitive closure of features depending on set. */
10379 static aarch64_feature_set
10380 aarch64_feature_disable_set (aarch64_feature_set set
)
10382 const struct aarch64_option_cpu_value_table
*opt
;
10383 aarch64_feature_set prev
= 0;
10385 while (prev
!= set
) {
10387 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10388 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10389 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10394 /* Transitive closure of dependencies of set. */
10395 static aarch64_feature_set
10396 aarch64_feature_enable_set (aarch64_feature_set set
)
10398 const struct aarch64_option_cpu_value_table
*opt
;
10399 aarch64_feature_set prev
= 0;
10401 while (prev
!= set
) {
10403 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10404 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10405 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10411 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10414 /* We insist on extensions being added before being removed. We achieve
10415 this by using the ADDING_VALUE variable to indicate whether we are
10416 adding an extension (1) or removing it (0) and only allowing it to
10417 change in the order -1 -> 1 -> 0. */
10418 int adding_value
= -1;
10419 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10421 /* Copy the feature set, so that we can modify it. */
10422 *ext_set
= **opt_p
;
10425 while (str
!= NULL
&& *str
!= 0)
10427 const struct aarch64_option_cpu_value_table
*opt
;
10428 const char *ext
= NULL
;
10435 as_bad (_("invalid architectural extension"));
10439 ext
= strchr (++str
, '+');
10443 optlen
= ext
- str
;
10445 optlen
= strlen (str
);
10447 if (optlen
>= 2 && startswith (str
, "no"))
10449 if (adding_value
!= 0)
10454 else if (optlen
> 0)
10456 if (adding_value
== -1)
10458 else if (adding_value
!= 1)
10460 as_bad (_("must specify extensions to add before specifying "
10461 "those to remove"));
10468 as_bad (_("missing architectural extension"));
10472 gas_assert (adding_value
!= -1);
10474 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10475 if (strncmp (opt
->name
, str
, optlen
) == 0)
10477 aarch64_feature_set set
;
10479 /* Add or remove the extension. */
10482 set
= aarch64_feature_enable_set (opt
->value
);
10483 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10487 set
= aarch64_feature_disable_set (opt
->value
);
10488 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10493 if (opt
->name
== NULL
)
10495 as_bad (_("unknown architectural extension `%s'"), str
);
10506 aarch64_parse_cpu (const char *str
)
10508 const struct aarch64_cpu_option_table
*opt
;
10509 const char *ext
= strchr (str
, '+');
10513 optlen
= ext
- str
;
10515 optlen
= strlen (str
);
10519 as_bad (_("missing cpu name `%s'"), str
);
10523 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10524 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10526 mcpu_cpu_opt
= &opt
->value
;
10528 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10533 as_bad (_("unknown cpu `%s'"), str
);
10538 aarch64_parse_arch (const char *str
)
10540 const struct aarch64_arch_option_table
*opt
;
10541 const char *ext
= strchr (str
, '+');
10545 optlen
= ext
- str
;
10547 optlen
= strlen (str
);
10551 as_bad (_("missing architecture name `%s'"), str
);
10555 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10556 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10558 march_cpu_opt
= &opt
->value
;
10560 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10565 as_bad (_("unknown architecture `%s'\n"), str
);
10570 struct aarch64_option_abi_value_table
10573 enum aarch64_abi_type value
;
10576 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10578 {"ilp32", AARCH64_ABI_ILP32
},
10579 {"lp64", AARCH64_ABI_LP64
},
10581 {"llp64", AARCH64_ABI_LLP64
},
10586 aarch64_parse_abi (const char *str
)
10590 if (str
[0] == '\0')
10592 as_bad (_("missing abi name `%s'"), str
);
10596 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10597 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10599 aarch64_abi
= aarch64_abis
[i
].value
;
10603 as_bad (_("unknown abi `%s'\n"), str
);
10607 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10608 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10609 aarch64_parse_abi
, NULL
},
10610 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10611 aarch64_parse_cpu
, NULL
},
10612 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10613 aarch64_parse_arch
, NULL
},
10614 {NULL
, NULL
, 0, NULL
}
10618 md_parse_option (int c
, const char *arg
)
10620 struct aarch64_option_table
*opt
;
10621 struct aarch64_long_option_table
*lopt
;
10627 target_big_endian
= 1;
10633 target_big_endian
= 0;
10638 /* Listing option. Just ignore these, we don't support additional
10643 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10645 if (c
== opt
->option
[0]
10646 && ((arg
== NULL
&& opt
->option
[1] == 0)
10647 || streq (arg
, opt
->option
+ 1)))
10649 /* If the option is deprecated, tell the user. */
10650 if (opt
->deprecated
!= NULL
)
10651 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10652 arg
? arg
: "", _(opt
->deprecated
));
10654 if (opt
->var
!= NULL
)
10655 *opt
->var
= opt
->value
;
10661 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10663 /* These options are expected to have an argument. */
10664 if (c
== lopt
->option
[0]
10666 && startswith (arg
, lopt
->option
+ 1))
10668 /* If the option is deprecated, tell the user. */
10669 if (lopt
->deprecated
!= NULL
)
10670 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10671 _(lopt
->deprecated
));
10673 /* Call the sup-option parser. */
10674 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10685 md_show_usage (FILE * fp
)
10687 struct aarch64_option_table
*opt
;
10688 struct aarch64_long_option_table
*lopt
;
10690 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10692 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10693 if (opt
->help
!= NULL
)
10694 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10696 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10697 if (lopt
->help
!= NULL
)
10698 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10702 -EB assemble code for a big-endian cpu\n"));
10707 -EL assemble code for a little-endian cpu\n"));
10711 /* Parse a .cpu directive. */
10714 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10716 const struct aarch64_cpu_option_table
*opt
;
10722 name
= input_line_pointer
;
10723 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10724 saved_char
= *input_line_pointer
;
10725 *input_line_pointer
= 0;
10727 ext
= strchr (name
, '+');
10730 optlen
= ext
- name
;
10732 optlen
= strlen (name
);
10734 /* Skip the first "all" entry. */
10735 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10736 if (strlen (opt
->name
) == optlen
10737 && strncmp (name
, opt
->name
, optlen
) == 0)
10739 mcpu_cpu_opt
= &opt
->value
;
10741 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10744 cpu_variant
= *mcpu_cpu_opt
;
10746 *input_line_pointer
= saved_char
;
10747 demand_empty_rest_of_line ();
10750 as_bad (_("unknown cpu `%s'"), name
);
10751 *input_line_pointer
= saved_char
;
10752 ignore_rest_of_line ();
10756 /* Parse a .arch directive. */
10759 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10761 const struct aarch64_arch_option_table
*opt
;
10767 name
= input_line_pointer
;
10768 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10769 saved_char
= *input_line_pointer
;
10770 *input_line_pointer
= 0;
10772 ext
= strchr (name
, '+');
10775 optlen
= ext
- name
;
10777 optlen
= strlen (name
);
10779 /* Skip the first "all" entry. */
10780 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10781 if (strlen (opt
->name
) == optlen
10782 && strncmp (name
, opt
->name
, optlen
) == 0)
10784 mcpu_cpu_opt
= &opt
->value
;
10786 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10789 cpu_variant
= *mcpu_cpu_opt
;
10791 *input_line_pointer
= saved_char
;
10792 demand_empty_rest_of_line ();
10796 as_bad (_("unknown architecture `%s'\n"), name
);
10797 *input_line_pointer
= saved_char
;
10798 ignore_rest_of_line ();
10801 /* Parse a .arch_extension directive. */
10804 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10807 char *ext
= input_line_pointer
;
10809 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10810 saved_char
= *input_line_pointer
;
10811 *input_line_pointer
= 0;
10813 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10816 cpu_variant
= *mcpu_cpu_opt
;
10818 *input_line_pointer
= saved_char
;
10819 demand_empty_rest_of_line ();
10822 /* Copy symbol information. */
10825 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10827 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10831 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10832 This is needed so AArch64 specific st_other values can be independently
10833 specified for an IFUNC resolver (that is called by the dynamic linker)
10834 and the symbol it resolves (aliased to the resolver). In particular,
10835 if a function symbol has special st_other value set via directives,
10836 then attaching an IFUNC resolver to that symbol should not override
10837 the st_other setting. Requiring the directive on the IFUNC resolver
10838 symbol would be unexpected and problematic in C code, where the two
10839 symbols appear as two independent function declarations. */
10842 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10844 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10845 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10846 /* If size is unset, copy size from src. Because we don't track whether
10847 .size has been used, we can't differentiate .size dest, 0 from the case
10848 where dest's size is unset. */
10849 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10853 destelf
->size
= XNEW (expressionS
);
10854 *destelf
->size
= *srcelf
->size
;
10856 S_SET_SIZE (dest
, S_GET_SIZE (src
));