1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2022 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* SME horizontal or vertical slice indicator, encoded in "V".
113 /* Bits for DEFINED field in vector_type_el. */
114 #define NTA_HASTYPE 1
115 #define NTA_HASINDEX 2
116 #define NTA_HASVARWIDTH 4
118 struct vector_type_el
120 enum vector_el_type type
;
121 unsigned char defined
;
126 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bool parse_operands (char *, const aarch64_opcode
*);
161 static bool programmer_friendly_fixup (aarch64_instruction
*);
163 /* Diagnostics inline function utilities.
165 These are lightweight utilities which should only be called by parse_operands
166 and other parsers. GAS processes each assembly line by parsing it against
167 instruction template(s), in the case of multiple templates (for the same
168 mnemonic name), those templates are tried one by one until one succeeds or
169 all fail. An assembly line may fail a few templates before being
170 successfully parsed; an error saved here in most cases is not a user error
171 but an error indicating the current template is not the right template.
172 Therefore it is very important that errors can be saved at a low cost during
173 the parsing; we don't want to slow down the whole parsing by recording
174 non-user errors in detail.
176 Remember that the objective is to help GAS pick up the most appropriate
177 error message in the case of multiple templates, e.g. FMOV which has 8
183 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
184 inst
.parsing_error
.error
= NULL
;
190 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
193 static inline const char *
194 get_error_message (void)
196 return inst
.parsing_error
.error
;
199 static inline enum aarch64_operand_error_kind
200 get_error_kind (void)
202 return inst
.parsing_error
.kind
;
206 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
208 inst
.parsing_error
.kind
= kind
;
209 inst
.parsing_error
.error
= error
;
213 set_recoverable_error (const char *error
)
215 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
218 /* Use the DESC field of the corresponding aarch64_operand entry to compose
219 the error message. */
221 set_default_error (void)
223 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
227 set_syntax_error (const char *error
)
229 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
233 set_first_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_fatal_syntax_error (const char *error
)
242 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
245 /* Return value for certain parsers when the parsing fails; those parsers
246 return the information of the parsed result, e.g. register number, on
248 #define PARSE_FAIL -1
250 /* This is an invalid condition code that means no conditional field is
252 #define COND_ALWAYS 0x10
256 const char *template;
263 bfd_reloc_code_real_type reloc
;
266 /* Macros to define the register types and masks for the purpose
269 #undef AARCH64_REG_TYPES
270 #define AARCH64_REG_TYPES \
271 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
272 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
273 BASIC_REG_TYPE(SP_32) /* wsp */ \
274 BASIC_REG_TYPE(SP_64) /* sp */ \
275 BASIC_REG_TYPE(Z_32) /* wzr */ \
276 BASIC_REG_TYPE(Z_64) /* xzr */ \
277 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
278 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
279 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
280 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
281 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
282 BASIC_REG_TYPE(VN) /* v[0-31] */ \
283 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
284 BASIC_REG_TYPE(PN) /* p[0-15] */ \
285 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
286 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
287 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
288 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
289 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
290 /* Typecheck: same, plus SVE registers. */ \
291 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
293 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
294 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
296 /* Typecheck: same, plus SVE registers. */ \
297 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
300 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
301 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
303 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
306 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
307 /* Typecheck: any [BHSDQ]P FP. */ \
308 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
309 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
310 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
311 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
315 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
316 be used for SVE instructions, since Zn and Pn are valid symbols \
317 in other contexts. */ \
318 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
321 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
322 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
323 | REG_TYPE(ZN) | REG_TYPE(PN)) \
324 /* Any integer register; used for error messages only. */ \
325 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
328 /* Pseudo type to mark the end of the enumerator sequence. */ \
331 #undef BASIC_REG_TYPE
332 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
333 #undef MULTI_REG_TYPE
334 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
336 /* Register type enumerators. */
337 typedef enum aarch64_reg_type_
339 /* A list of REG_TYPE_*. */
343 #undef BASIC_REG_TYPE
344 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
346 #define REG_TYPE(T) (1 << REG_TYPE_##T)
347 #undef MULTI_REG_TYPE
348 #define MULTI_REG_TYPE(T,V) V,
350 /* Structure for a hash table entry for a register. */
354 unsigned char number
;
355 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
356 unsigned char builtin
;
359 /* Values indexed by aarch64_reg_type to assist the type checking. */
360 static const unsigned reg_type_masks
[] =
365 #undef BASIC_REG_TYPE
367 #undef MULTI_REG_TYPE
368 #undef AARCH64_REG_TYPES
370 /* Diagnostics used when we don't get a register of the expected type.
371 Note: this has to synchronized with aarch64_reg_type definitions
374 get_reg_expected_msg (aarch64_reg_type reg_type
)
381 msg
= N_("integer 32-bit register expected");
384 msg
= N_("integer 64-bit register expected");
387 msg
= N_("integer register expected");
389 case REG_TYPE_R64_SP
:
390 msg
= N_("64-bit integer or SP register expected");
392 case REG_TYPE_SVE_BASE
:
393 msg
= N_("base register expected");
396 msg
= N_("integer or zero register expected");
398 case REG_TYPE_SVE_OFFSET
:
399 msg
= N_("offset register expected");
402 msg
= N_("integer or SP register expected");
404 case REG_TYPE_R_Z_SP
:
405 msg
= N_("integer, zero or SP register expected");
408 msg
= N_("8-bit SIMD scalar register expected");
411 msg
= N_("16-bit SIMD scalar or floating-point half precision "
412 "register expected");
415 msg
= N_("32-bit SIMD scalar or floating-point single precision "
416 "register expected");
419 msg
= N_("64-bit SIMD scalar or floating-point double precision "
420 "register expected");
423 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
424 "register expected");
426 case REG_TYPE_R_Z_BHSDQ_V
:
427 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
428 msg
= N_("register expected");
430 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
431 msg
= N_("SIMD scalar or floating-point register expected");
433 case REG_TYPE_VN
: /* any V reg */
434 msg
= N_("vector register expected");
437 msg
= N_("SVE vector register expected");
440 msg
= N_("SVE predicate register expected");
443 as_fatal (_("invalid register type %d"), reg_type
);
448 /* Some well known registers that we refer to directly elsewhere. */
452 /* Instructions take 4 bytes in the object file. */
455 static htab_t aarch64_ops_hsh
;
456 static htab_t aarch64_cond_hsh
;
457 static htab_t aarch64_shift_hsh
;
458 static htab_t aarch64_sys_regs_hsh
;
459 static htab_t aarch64_pstatefield_hsh
;
460 static htab_t aarch64_sys_regs_ic_hsh
;
461 static htab_t aarch64_sys_regs_dc_hsh
;
462 static htab_t aarch64_sys_regs_at_hsh
;
463 static htab_t aarch64_sys_regs_tlbi_hsh
;
464 static htab_t aarch64_sys_regs_sr_hsh
;
465 static htab_t aarch64_reg_hsh
;
466 static htab_t aarch64_barrier_opt_hsh
;
467 static htab_t aarch64_nzcv_hsh
;
468 static htab_t aarch64_pldop_hsh
;
469 static htab_t aarch64_hint_opt_hsh
;
471 /* Stuff needed to resolve the label ambiguity
480 static symbolS
*last_label_seen
;
482 /* Literal pool structure. Held on a per-section
483 and per-sub-section basis. */
485 #define MAX_LITERAL_POOL_SIZE 1024
486 typedef struct literal_expression
489 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
490 LITTLENUM_TYPE
* bignum
;
491 } literal_expression
;
493 typedef struct literal_pool
495 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
496 unsigned int next_free_entry
;
502 struct literal_pool
*next
;
505 /* Pointer to a linked list of literal pools. */
506 static literal_pool
*list_of_pools
= NULL
;
510 /* This array holds the chars that always start a comment. If the
511 pre-processor is disabled, these aren't very useful. */
512 const char comment_chars
[] = "";
514 /* This array holds the chars that only start a comment at the beginning of
515 a line. If the line seems to have the form '# 123 filename'
516 .line and .file directives will appear in the pre-processed output. */
517 /* Note that input_file.c hand checks for '#' at the beginning of the
518 first line of the input file. This is because the compiler outputs
519 #NO_APP at the beginning of its output. */
520 /* Also note that comments like this one will always work. */
521 const char line_comment_chars
[] = "#";
523 const char line_separator_chars
[] = ";";
525 /* Chars that can be used to separate mant
526 from exp in floating point numbers. */
527 const char EXP_CHARS
[] = "eE";
529 /* Chars that mean this number is a floating point constant. */
533 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
535 /* Prefix character that indicates the start of an immediate value. */
536 #define is_immediate_prefix(C) ((C) == '#')
538 /* Separator character handling. */
540 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 skip_past_char (char **str
, char c
)
554 #define skip_past_comma(str) skip_past_char (str, ',')
556 /* Arithmetic expressions (possibly involving symbols). */
558 static bool in_aarch64_get_expression
= false;
560 /* Third argument to aarch64_get_expression. */
561 #define GE_NO_PREFIX false
562 #define GE_OPT_PREFIX true
564 /* Fourth argument to aarch64_get_expression. */
565 #define ALLOW_ABSENT false
566 #define REJECT_ABSENT true
568 /* Fifth argument to aarch64_get_expression. */
569 #define NORMAL_RESOLUTION false
571 /* Return TRUE if the string pointed by *STR is successfully parsed
572 as an valid expression; *EP will be filled with the information of
573 such an expression. Otherwise return FALSE.
575 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
576 If REJECT_ABSENT is true then trat missing expressions as an error.
577 If DEFER_RESOLUTION is true, then do not resolve expressions against
578 constant symbols. Necessary if the expression is part of a fixup
579 that uses a reloc that must be emitted. */
582 aarch64_get_expression (expressionS
* ep
,
584 bool allow_immediate_prefix
,
586 bool defer_resolution
)
590 bool prefix_present
= false;
592 if (allow_immediate_prefix
)
594 if (is_immediate_prefix (**str
))
597 prefix_present
= true;
601 memset (ep
, 0, sizeof (expressionS
));
603 save_in
= input_line_pointer
;
604 input_line_pointer
= *str
;
605 in_aarch64_get_expression
= true;
606 if (defer_resolution
)
607 seg
= deferred_expression (ep
);
609 seg
= expression (ep
);
610 in_aarch64_get_expression
= false;
612 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
614 /* We found a bad expression in md_operand(). */
615 *str
= input_line_pointer
;
616 input_line_pointer
= save_in
;
617 if (prefix_present
&& ! error_p ())
618 set_fatal_syntax_error (_("bad expression"));
620 set_first_syntax_error (_("bad expression"));
625 if (seg
!= absolute_section
626 && seg
!= text_section
627 && seg
!= data_section
628 && seg
!= bss_section
629 && seg
!= undefined_section
)
631 set_syntax_error (_("bad segment"));
632 *str
= input_line_pointer
;
633 input_line_pointer
= save_in
;
640 *str
= input_line_pointer
;
641 input_line_pointer
= save_in
;
645 /* Turn a string in input_line_pointer into a floating point constant
646 of type TYPE, and store the appropriate bytes in *LITP. The number
647 of LITTLENUMS emitted is stored in *SIZEP. An error message is
648 returned, or NULL on OK. */
651 md_atof (int type
, char *litP
, int *sizeP
)
653 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
656 /* We handle all bad expressions here, so that we can report the faulty
657 instruction in the error message. */
659 md_operand (expressionS
* exp
)
661 if (in_aarch64_get_expression
)
662 exp
->X_op
= O_illegal
;
665 /* Immediate values. */
667 /* Errors may be set multiple times during parsing or bit encoding
668 (particularly in the Neon bits), but usually the earliest error which is set
669 will be the most meaningful. Avoid overwriting it with later (cascading)
670 errors by calling this function. */
673 first_error (const char *error
)
676 set_syntax_error (error
);
679 /* Similar to first_error, but this function accepts formatted error
682 first_error_fmt (const char *format
, ...)
687 /* N.B. this single buffer will not cause error messages for different
688 instructions to pollute each other; this is because at the end of
689 processing of each assembly line, error message if any will be
690 collected by as_bad. */
691 static char buffer
[size
];
695 int ret ATTRIBUTE_UNUSED
;
696 va_start (args
, format
);
697 ret
= vsnprintf (buffer
, size
, format
, args
);
698 know (ret
<= size
- 1 && ret
>= 0);
700 set_syntax_error (buffer
);
704 /* Register parsing. */
706 /* Generic register parser which is called by other specialized
708 CCP points to what should be the beginning of a register name.
709 If it is indeed a valid register name, advance CCP over it and
710 return the reg_entry structure; otherwise return NULL.
711 It does not issue diagnostics. */
714 parse_reg (char **ccp
)
720 #ifdef REGISTER_PREFIX
721 if (*start
!= REGISTER_PREFIX
)
727 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
732 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
734 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
743 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
746 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
748 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
751 /* Try to parse a base or offset register. Allow SVE base and offset
752 registers if REG_TYPE includes SVE registers. Return the register
753 entry on success, setting *QUALIFIER to the register qualifier.
754 Return null otherwise.
756 Note that this function does not issue any diagnostics. */
758 static const reg_entry
*
759 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
760 aarch64_opnd_qualifier_t
*qualifier
)
763 const reg_entry
*reg
= parse_reg (&str
);
773 *qualifier
= AARCH64_OPND_QLF_W
;
779 *qualifier
= AARCH64_OPND_QLF_X
;
783 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
786 switch (TOLOWER (str
[1]))
789 *qualifier
= AARCH64_OPND_QLF_S_S
;
792 *qualifier
= AARCH64_OPND_QLF_S_D
;
809 /* Try to parse a base or offset register. Return the register entry
810 on success, setting *QUALIFIER to the register qualifier. Return null
813 Note that this function does not issue any diagnostics. */
815 static const reg_entry
*
816 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
818 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
821 /* Parse the qualifier of a vector register or vector element of type
822 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
823 succeeds; otherwise return FALSE.
825 Accept only one occurrence of:
826 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
829 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
830 struct vector_type_el
*parsed_type
, char **str
)
834 unsigned element_size
;
835 enum vector_el_type type
;
838 gas_assert (*ptr
== '.');
841 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
846 width
= strtoul (ptr
, &ptr
, 10);
847 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
849 first_error_fmt (_("bad size %d in vector width specifier"), width
);
854 switch (TOLOWER (*ptr
))
873 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
882 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
884 first_error (_("missing element size"));
887 if (width
!= 0 && width
* element_size
!= 64
888 && width
* element_size
!= 128
889 && !(width
== 2 && element_size
== 16)
890 && !(width
== 4 && element_size
== 8))
893 ("invalid element size %d and vector size combination %c"),
899 parsed_type
->type
= type
;
900 parsed_type
->width
= width
;
907 /* *STR contains an SVE zero/merge predication suffix. Parse it into
908 *PARSED_TYPE and point *STR at the end of the suffix. */
911 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
916 gas_assert (*ptr
== '/');
918 switch (TOLOWER (*ptr
))
921 parsed_type
->type
= NT_zero
;
924 parsed_type
->type
= NT_merge
;
927 if (*ptr
!= '\0' && *ptr
!= ',')
928 first_error_fmt (_("unexpected character `%c' in predication type"),
931 first_error (_("missing predication type"));
934 parsed_type
->width
= 0;
939 /* Parse a register of the type TYPE.
941 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
942 name or the parsed register is not of TYPE.
944 Otherwise return the register number, and optionally fill in the actual
945 type of the register in *RTYPE when multiple alternatives were given, and
946 return the register shape and element index information in *TYPEINFO.
948 IN_REG_LIST should be set with TRUE if the caller is parsing a register
952 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
953 struct vector_type_el
*typeinfo
, bool in_reg_list
)
956 const reg_entry
*reg
= parse_reg (&str
);
957 struct vector_type_el atype
;
958 struct vector_type_el parsetype
;
959 bool is_typed_vecreg
= false;
962 atype
.type
= NT_invtype
;
970 set_default_error ();
974 if (! aarch64_check_reg_type (reg
, type
))
976 DEBUG_TRACE ("reg type check failed");
977 set_default_error ();
982 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
983 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
987 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
992 if (!parse_predication_for_operand (&parsetype
, &str
))
996 /* Register if of the form Vn.[bhsdq]. */
997 is_typed_vecreg
= true;
999 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1001 /* The width is always variable; we don't allow an integer width
1003 gas_assert (parsetype
.width
== 0);
1004 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1006 else if (parsetype
.width
== 0)
1007 /* Expect index. In the new scheme we cannot have
1008 Vn.[bhsdq] represent a scalar. Therefore any
1009 Vn.[bhsdq] should have an index following it.
1010 Except in reglists of course. */
1011 atype
.defined
|= NTA_HASINDEX
;
1013 atype
.defined
|= NTA_HASTYPE
;
1015 atype
.type
= parsetype
.type
;
1016 atype
.width
= parsetype
.width
;
1019 if (skip_past_char (&str
, '['))
1023 /* Reject Sn[index] syntax. */
1024 if (!is_typed_vecreg
)
1026 first_error (_("this type of register can't be indexed"));
1032 first_error (_("index not allowed inside register list"));
1036 atype
.defined
|= NTA_HASINDEX
;
1038 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1041 if (exp
.X_op
!= O_constant
)
1043 first_error (_("constant expression required"));
1047 if (! skip_past_char (&str
, ']'))
1050 atype
.index
= exp
.X_add_number
;
1052 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1054 /* Indexed vector register expected. */
1055 first_error (_("indexed vector register expected"));
1059 /* A vector reg Vn should be typed or indexed. */
1060 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1062 first_error (_("invalid use of vector register"));
1078 Return the register number on success; return PARSE_FAIL otherwise.
1080 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1081 the register (e.g. NEON double or quad reg when either has been requested).
1083 If this is a NEON vector register with additional type information, fill
1084 in the struct pointed to by VECTYPE (if non-NULL).
1086 This parser does not handle register list. */
1089 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1090 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1092 struct vector_type_el atype
;
1094 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1095 /*in_reg_list= */ false);
1097 if (reg
== PARSE_FAIL
)
1109 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1113 && e1
.defined
== e2
.defined
1114 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1117 /* This function parses a list of vector registers of type TYPE.
1118 On success, it returns the parsed register list information in the
1119 following encoded format:
1121 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1122 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1124 The information of the register shape and/or index is returned in
1127 It returns PARSE_FAIL if the register list is invalid.
1129 The list contains one to four registers.
1130 Each register can be one of:
1133 All <T> should be identical.
1134 All <index> should be identical.
1135 There are restrictions on <Vt> numbers which are checked later
1136 (by reg_list_valid_p). */
1139 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1140 struct vector_type_el
*vectype
)
1144 struct vector_type_el typeinfo
, typeinfo_first
;
1150 bool expect_index
= false;
1154 set_syntax_error (_("expecting {"));
1160 typeinfo_first
.defined
= 0;
1161 typeinfo_first
.type
= NT_invtype
;
1162 typeinfo_first
.width
= -1;
1163 typeinfo_first
.index
= 0;
1172 str
++; /* skip over '-' */
1175 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1176 /*in_reg_list= */ true);
1177 if (val
== PARSE_FAIL
)
1179 set_first_syntax_error (_("invalid vector register in list"));
1183 /* reject [bhsd]n */
1184 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1186 set_first_syntax_error (_("invalid scalar register in list"));
1191 if (typeinfo
.defined
& NTA_HASINDEX
)
1192 expect_index
= true;
1196 if (val
< val_range
)
1198 set_first_syntax_error
1199 (_("invalid range in vector register list"));
1208 typeinfo_first
= typeinfo
;
1209 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1211 set_first_syntax_error
1212 (_("type mismatch in vector register list"));
1217 for (i
= val_range
; i
<= val
; i
++)
1219 ret_val
|= i
<< (5 * nb_regs
);
1224 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1226 skip_whitespace (str
);
1229 set_first_syntax_error (_("end of vector register list not found"));
1234 skip_whitespace (str
);
1238 if (skip_past_char (&str
, '['))
1242 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1244 if (exp
.X_op
!= O_constant
)
1246 set_first_syntax_error (_("constant expression required."));
1249 if (! skip_past_char (&str
, ']'))
1252 typeinfo_first
.index
= exp
.X_add_number
;
1256 set_first_syntax_error (_("expected index"));
1263 set_first_syntax_error (_("too many registers in vector register list"));
1266 else if (nb_regs
== 0)
1268 set_first_syntax_error (_("empty vector register list"));
1274 *vectype
= typeinfo_first
;
1276 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1279 /* Directives: register aliases. */
1282 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1287 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1290 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1293 /* Only warn about a redefinition if it's not defined as the
1295 else if (new->number
!= number
|| new->type
!= type
)
1296 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1301 name
= xstrdup (str
);
1302 new = XNEW (reg_entry
);
1305 new->number
= number
;
1307 new->builtin
= false;
1309 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1314 /* Look for the .req directive. This is of the form:
1316 new_register_name .req existing_register_name
1318 If we find one, or if it looks sufficiently like one that we want to
1319 handle any error here, return TRUE. Otherwise return FALSE. */
1322 create_register_alias (char *newname
, char *p
)
1324 const reg_entry
*old
;
1325 char *oldname
, *nbuf
;
1328 /* The input scrubber ensures that whitespace after the mnemonic is
1329 collapsed to single spaces. */
1331 if (!startswith (oldname
, " .req "))
1335 if (*oldname
== '\0')
1338 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1341 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1345 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1346 the desired alias name, and p points to its end. If not, then
1347 the desired alias name is in the global original_case_string. */
1348 #ifdef TC_CASE_SENSITIVE
1351 newname
= original_case_string
;
1352 nlen
= strlen (newname
);
1355 nbuf
= xmemdup0 (newname
, nlen
);
1357 /* Create aliases under the new name as stated; an all-lowercase
1358 version of the new name; and an all-uppercase version of the new
1360 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1362 for (p
= nbuf
; *p
; p
++)
1365 if (strncmp (nbuf
, newname
, nlen
))
1367 /* If this attempt to create an additional alias fails, do not bother
1368 trying to create the all-lower case alias. We will fail and issue
1369 a second, duplicate error message. This situation arises when the
1370 programmer does something like:
1373 The second .req creates the "Foo" alias but then fails to create
1374 the artificial FOO alias because it has already been created by the
1376 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1383 for (p
= nbuf
; *p
; p
++)
1386 if (strncmp (nbuf
, newname
, nlen
))
1387 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1394 /* Should never be called, as .req goes between the alias and the
1395 register name, not at the beginning of the line. */
1397 s_req (int a ATTRIBUTE_UNUSED
)
1399 as_bad (_("invalid syntax for .req directive"));
1402 /* The .unreq directive deletes an alias which was previously defined
1403 by .req. For example:
1409 s_unreq (int a ATTRIBUTE_UNUSED
)
1414 name
= input_line_pointer
;
1416 while (*input_line_pointer
!= 0
1417 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1418 ++input_line_pointer
;
1420 saved_char
= *input_line_pointer
;
1421 *input_line_pointer
= 0;
1424 as_bad (_("invalid syntax for .unreq directive"));
1427 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1430 as_bad (_("unknown register alias '%s'"), name
);
1431 else if (reg
->builtin
)
1432 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1439 str_hash_delete (aarch64_reg_hsh
, name
);
1440 free ((char *) reg
->name
);
1443 /* Also locate the all upper case and all lower case versions.
1444 Do not complain if we cannot find one or the other as it
1445 was probably deleted above. */
1447 nbuf
= strdup (name
);
1448 for (p
= nbuf
; *p
; p
++)
1450 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1453 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1454 free ((char *) reg
->name
);
1458 for (p
= nbuf
; *p
; p
++)
1460 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1463 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1464 free ((char *) reg
->name
);
1472 *input_line_pointer
= saved_char
;
1473 demand_empty_rest_of_line ();
1476 /* Directives: Instruction set selection. */
1479 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1480 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1481 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1482 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1484 /* Create a new mapping symbol for the transition to STATE. */
1487 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1490 const char *symname
;
1497 type
= BSF_NO_FLAGS
;
1501 type
= BSF_NO_FLAGS
;
1507 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1508 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1510 /* Save the mapping symbols for future reference. Also check that
1511 we do not place two mapping symbols at the same offset within a
1512 frag. We'll handle overlap between frags in
1513 check_mapping_symbols.
1515 If .fill or other data filling directive generates zero sized data,
1516 the mapping symbol for the following code will have the same value
1517 as the one generated for the data filling directive. In this case,
1518 we replace the old symbol with the new one at the same address. */
1521 if (frag
->tc_frag_data
.first_map
!= NULL
)
1523 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1524 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1527 frag
->tc_frag_data
.first_map
= symbolP
;
1529 if (frag
->tc_frag_data
.last_map
!= NULL
)
1531 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1532 S_GET_VALUE (symbolP
));
1533 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1534 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1537 frag
->tc_frag_data
.last_map
= symbolP
;
1540 /* We must sometimes convert a region marked as code to data during
1541 code alignment, if an odd number of bytes have to be padded. The
1542 code mapping symbol is pushed to an aligned address. */
1545 insert_data_mapping_symbol (enum mstate state
,
1546 valueT value
, fragS
* frag
, offsetT bytes
)
1548 /* If there was already a mapping symbol, remove it. */
1549 if (frag
->tc_frag_data
.last_map
!= NULL
1550 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1551 frag
->fr_address
+ value
)
1553 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1557 know (frag
->tc_frag_data
.first_map
== symp
);
1558 frag
->tc_frag_data
.first_map
= NULL
;
1560 frag
->tc_frag_data
.last_map
= NULL
;
1561 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1564 make_mapping_symbol (MAP_DATA
, value
, frag
);
1565 make_mapping_symbol (state
, value
+ bytes
, frag
);
1568 static void mapping_state_2 (enum mstate state
, int max_chars
);
1570 /* Set the mapping state to STATE. Only call this when about to
1571 emit some STATE bytes to the file. */
1574 mapping_state (enum mstate state
)
1576 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1578 if (state
== MAP_INSN
)
1579 /* AArch64 instructions require 4-byte alignment. When emitting
1580 instructions into any section, record the appropriate section
1582 record_alignment (now_seg
, 2);
1584 if (mapstate
== state
)
1585 /* The mapping symbol has already been emitted.
1586 There is nothing else to do. */
1589 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1590 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1591 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1592 evaluated later in the next else. */
1594 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1596 /* Only add the symbol if the offset is > 0:
1597 if we're at the first frag, check it's size > 0;
1598 if we're not at the first frag, then for sure
1599 the offset is > 0. */
1600 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1601 const int add_symbol
= (frag_now
!= frag_first
)
1602 || (frag_now_fix () > 0);
1605 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1609 mapping_state_2 (state
, 0);
1612 /* Same as mapping_state, but MAX_CHARS bytes have already been
1613 allocated. Put the mapping symbol that far back. */
1616 mapping_state_2 (enum mstate state
, int max_chars
)
1618 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1620 if (!SEG_NORMAL (now_seg
))
1623 if (mapstate
== state
)
1624 /* The mapping symbol has already been emitted.
1625 There is nothing else to do. */
1628 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1629 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1632 #define mapping_state(x) /* nothing */
1633 #define mapping_state_2(x, y) /* nothing */
1636 /* Directives: sectioning and alignment. */
1639 s_bss (int ignore ATTRIBUTE_UNUSED
)
1641 /* We don't support putting frags in the BSS segment, we fake it by
1642 marking in_bss, then looking at s_skip for clues. */
1643 subseg_set (bss_section
, 0);
1644 demand_empty_rest_of_line ();
1645 mapping_state (MAP_DATA
);
1649 s_even (int ignore ATTRIBUTE_UNUSED
)
1651 /* Never make frag if expect extra pass. */
1653 frag_align (1, 0, 0);
1655 record_alignment (now_seg
, 1);
1657 demand_empty_rest_of_line ();
1660 /* Directives: Literal pools. */
1662 static literal_pool
*
1663 find_literal_pool (int size
)
1667 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1669 if (pool
->section
== now_seg
1670 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1677 static literal_pool
*
1678 find_or_make_literal_pool (int size
)
1680 /* Next literal pool ID number. */
1681 static unsigned int latest_pool_num
= 1;
1684 pool
= find_literal_pool (size
);
1688 /* Create a new pool. */
1689 pool
= XNEW (literal_pool
);
1693 /* Currently we always put the literal pool in the current text
1694 section. If we were generating "small" model code where we
1695 knew that all code and initialised data was within 1MB then
1696 we could output literals to mergeable, read-only data
1699 pool
->next_free_entry
= 0;
1700 pool
->section
= now_seg
;
1701 pool
->sub_section
= now_subseg
;
1703 pool
->next
= list_of_pools
;
1704 pool
->symbol
= NULL
;
1706 /* Add it to the list. */
1707 list_of_pools
= pool
;
1710 /* New pools, and emptied pools, will have a NULL symbol. */
1711 if (pool
->symbol
== NULL
)
1713 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1714 &zero_address_frag
, 0);
1715 pool
->id
= latest_pool_num
++;
1722 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1723 Return TRUE on success, otherwise return FALSE. */
1725 add_to_lit_pool (expressionS
*exp
, int size
)
1730 pool
= find_or_make_literal_pool (size
);
1732 /* Check if this literal value is already in the pool. */
1733 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1735 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1737 if ((litexp
->X_op
== exp
->X_op
)
1738 && (exp
->X_op
== O_constant
)
1739 && (litexp
->X_add_number
== exp
->X_add_number
)
1740 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1743 if ((litexp
->X_op
== exp
->X_op
)
1744 && (exp
->X_op
== O_symbol
)
1745 && (litexp
->X_add_number
== exp
->X_add_number
)
1746 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1747 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1751 /* Do we need to create a new entry? */
1752 if (entry
== pool
->next_free_entry
)
1754 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1756 set_syntax_error (_("literal pool overflow"));
1760 pool
->literals
[entry
].exp
= *exp
;
1761 pool
->next_free_entry
+= 1;
1762 if (exp
->X_op
== O_big
)
1764 /* PR 16688: Bignums are held in a single global array. We must
1765 copy and preserve that value now, before it is overwritten. */
1766 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1768 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1769 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1772 pool
->literals
[entry
].bignum
= NULL
;
1775 exp
->X_op
= O_symbol
;
1776 exp
->X_add_number
= ((int) entry
) * size
;
1777 exp
->X_add_symbol
= pool
->symbol
;
1782 /* Can't use symbol_new here, so have to create a symbol and then at
1783 a later date assign it a value. That's what these functions do. */
1786 symbol_locate (symbolS
* symbolP
,
1787 const char *name
,/* It is copied, the caller can modify. */
1788 segT segment
, /* Segment identifier (SEG_<something>). */
1789 valueT valu
, /* Symbol value. */
1790 fragS
* frag
) /* Associated fragment. */
1793 char *preserved_copy_of_name
;
1795 name_length
= strlen (name
) + 1; /* +1 for \0. */
1796 obstack_grow (¬es
, name
, name_length
);
1797 preserved_copy_of_name
= obstack_finish (¬es
);
1799 #ifdef tc_canonicalize_symbol_name
1800 preserved_copy_of_name
=
1801 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1804 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1806 S_SET_SEGMENT (symbolP
, segment
);
1807 S_SET_VALUE (symbolP
, valu
);
1808 symbol_clear_list_pointers (symbolP
);
1810 symbol_set_frag (symbolP
, frag
);
1812 /* Link to end of symbol chain. */
1814 extern int symbol_table_frozen
;
1816 if (symbol_table_frozen
)
1820 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1822 obj_symbol_new_hook (symbolP
);
1824 #ifdef tc_symbol_new_hook
1825 tc_symbol_new_hook (symbolP
);
1829 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1830 #endif /* DEBUG_SYMS */
1835 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1842 for (align
= 2; align
<= 4; align
++)
1844 int size
= 1 << align
;
1846 pool
= find_literal_pool (size
);
1847 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1850 /* Align pool as you have word accesses.
1851 Only make a frag if we have to. */
1853 frag_align (align
, 0, 0);
1855 mapping_state (MAP_DATA
);
1857 record_alignment (now_seg
, align
);
1859 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1861 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1862 (valueT
) frag_now_fix (), frag_now
);
1863 symbol_table_insert (pool
->symbol
);
1865 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1867 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1869 if (exp
->X_op
== O_big
)
1871 /* PR 16688: Restore the global bignum value. */
1872 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1873 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1874 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1877 /* First output the expression in the instruction to the pool. */
1878 emit_expr (exp
, size
); /* .word|.xword */
1880 if (exp
->X_op
== O_big
)
1882 free (pool
->literals
[entry
].bignum
);
1883 pool
->literals
[entry
].bignum
= NULL
;
1887 /* Mark the pool as empty. */
1888 pool
->next_free_entry
= 0;
1889 pool
->symbol
= NULL
;
1894 /* Forward declarations for functions below, in the MD interface
1896 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1897 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1899 /* Directives: Data. */
1900 /* N.B. the support for relocation suffix in this directive needs to be
1901 implemented properly. */
1904 s_aarch64_elf_cons (int nbytes
)
1908 #ifdef md_flush_pending_output
1909 md_flush_pending_output ();
1912 if (is_it_end_of_statement ())
1914 demand_empty_rest_of_line ();
1918 #ifdef md_cons_align
1919 md_cons_align (nbytes
);
1922 mapping_state (MAP_DATA
);
1925 struct reloc_table_entry
*reloc
;
1929 if (exp
.X_op
!= O_symbol
)
1930 emit_expr (&exp
, (unsigned int) nbytes
);
1933 skip_past_char (&input_line_pointer
, '#');
1934 if (skip_past_char (&input_line_pointer
, ':'))
1936 reloc
= find_reloc_table_entry (&input_line_pointer
);
1938 as_bad (_("unrecognized relocation suffix"));
1940 as_bad (_("unimplemented relocation suffix"));
1941 ignore_rest_of_line ();
1945 emit_expr (&exp
, (unsigned int) nbytes
);
1948 while (*input_line_pointer
++ == ',');
1950 /* Put terminator back into stream. */
1951 input_line_pointer
--;
1952 demand_empty_rest_of_line ();
1955 /* Mark symbol that it follows a variant PCS convention. */
1958 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1964 elf_symbol_type
*elfsym
;
1966 c
= get_symbol_name (&name
);
1968 as_bad (_("Missing symbol name in directive"));
1969 sym
= symbol_find_or_make (name
);
1970 restore_line_pointer (c
);
1971 demand_empty_rest_of_line ();
1972 bfdsym
= symbol_get_bfdsym (sym
);
1973 elfsym
= elf_symbol_from (bfdsym
);
1974 gas_assert (elfsym
);
1975 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1977 #endif /* OBJ_ELF */
1979 /* Output a 32-bit word, but mark as an instruction. */
1982 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1987 #ifdef md_flush_pending_output
1988 md_flush_pending_output ();
1991 if (is_it_end_of_statement ())
1993 demand_empty_rest_of_line ();
1997 /* Sections are assumed to start aligned. In executable section, there is no
1998 MAP_DATA symbol pending. So we only align the address during
1999 MAP_DATA --> MAP_INSN transition.
2000 For other sections, this is not guaranteed. */
2001 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2002 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2003 frag_align_code (2, 0);
2006 mapping_state (MAP_INSN
);
2012 if (exp
.X_op
!= O_constant
)
2014 as_bad (_("constant expression required"));
2015 ignore_rest_of_line ();
2019 if (target_big_endian
)
2021 unsigned int val
= exp
.X_add_number
;
2022 exp
.X_add_number
= SWAP_32 (val
);
2024 emit_expr (&exp
, INSN_SIZE
);
2027 while (*input_line_pointer
++ == ',');
2029 dwarf2_emit_insn (n
* INSN_SIZE
);
2031 /* Put terminator back into stream. */
2032 input_line_pointer
--;
2033 demand_empty_rest_of_line ();
2037 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2039 demand_empty_rest_of_line ();
2040 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2041 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2045 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2048 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2054 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2055 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2057 demand_empty_rest_of_line ();
2060 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2063 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2067 /* Since we're just labelling the code, there's no need to define a
2070 /* Make sure there is enough room in this frag for the following
2071 blr. This trick only works if the blr follows immediately after
2072 the .tlsdesc directive. */
2074 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2075 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2077 demand_empty_rest_of_line ();
2080 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2083 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2089 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2090 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2092 demand_empty_rest_of_line ();
2094 #endif /* OBJ_ELF */
2096 static void s_aarch64_arch (int);
2097 static void s_aarch64_cpu (int);
2098 static void s_aarch64_arch_extension (int);
2100 /* This table describes all the machine specific pseudo-ops the assembler
2101 has to support. The fields are:
2102 pseudo-op name without dot
2103 function to call to execute this pseudo-op
2104 Integer arg to pass to the function. */
2106 const pseudo_typeS md_pseudo_table
[] = {
2107 /* Never called because '.req' does not start a line. */
2109 {"unreq", s_unreq
, 0},
2111 {"even", s_even
, 0},
2112 {"ltorg", s_ltorg
, 0},
2113 {"pool", s_ltorg
, 0},
2114 {"cpu", s_aarch64_cpu
, 0},
2115 {"arch", s_aarch64_arch
, 0},
2116 {"arch_extension", s_aarch64_arch_extension
, 0},
2117 {"inst", s_aarch64_inst
, 0},
2118 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2120 {"tlsdescadd", s_tlsdescadd
, 0},
2121 {"tlsdesccall", s_tlsdesccall
, 0},
2122 {"tlsdescldr", s_tlsdescldr
, 0},
2123 {"word", s_aarch64_elf_cons
, 4},
2124 {"long", s_aarch64_elf_cons
, 4},
2125 {"xword", s_aarch64_elf_cons
, 8},
2126 {"dword", s_aarch64_elf_cons
, 8},
2127 {"variant_pcs", s_variant_pcs
, 0},
2129 {"float16", float_cons
, 'h'},
2130 {"bfloat16", float_cons
, 'b'},
2135 /* Check whether STR points to a register name followed by a comma or the
2136 end of line; REG_TYPE indicates which register types are checked
2137 against. Return TRUE if STR is such a register name; otherwise return
2138 FALSE. The function does not intend to produce any diagnostics, but since
2139 the register parser aarch64_reg_parse, which is called by this function,
2140 does produce diagnostics, we call clear_error to clear any diagnostics
2141 that may be generated by aarch64_reg_parse.
2142 Also, the function returns FALSE directly if there is any user error
2143 present at the function entry. This prevents the existing diagnostics
2144 state from being spoiled.
2145 The function currently serves parse_constant_immediate and
2146 parse_big_immediate only. */
2148 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2152 /* Prevent the diagnostics state from being spoiled. */
2156 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2158 /* Clear the parsing error that may be set by the reg parser. */
2161 if (reg
== PARSE_FAIL
)
2164 skip_whitespace (str
);
2165 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2171 /* Parser functions used exclusively in instruction operands. */
2173 /* Parse an immediate expression which may not be constant.
2175 To prevent the expression parser from pushing a register name
2176 into the symbol table as an undefined symbol, firstly a check is
2177 done to find out whether STR is a register of type REG_TYPE followed
2178 by a comma or the end of line. Return FALSE if STR is such a string. */
2181 parse_immediate_expression (char **str
, expressionS
*exp
,
2182 aarch64_reg_type reg_type
)
2184 if (reg_name_p (*str
, reg_type
))
2186 set_recoverable_error (_("immediate operand required"));
2190 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2193 if (exp
->X_op
== O_absent
)
2195 set_fatal_syntax_error (_("missing immediate expression"));
2202 /* Constant immediate-value read function for use in insn parsing.
2203 STR points to the beginning of the immediate (with the optional
2204 leading #); *VAL receives the value. REG_TYPE says which register
2205 names should be treated as registers rather than as symbolic immediates.
2207 Return TRUE on success; otherwise return FALSE. */
2210 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2214 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2217 if (exp
.X_op
!= O_constant
)
2219 set_syntax_error (_("constant expression required"));
2223 *val
= exp
.X_add_number
;
2228 encode_imm_float_bits (uint32_t imm
)
2230 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2231 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2234 /* Return TRUE if the single-precision floating-point value encoded in IMM
2235 can be expressed in the AArch64 8-bit signed floating-point format with
2236 3-bit exponent and normalized 4 bits of precision; in other words, the
2237 floating-point value must be expressable as
2238 (+/-) n / 16 * power (2, r)
2239 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2242 aarch64_imm_float_p (uint32_t imm
)
2244 /* If a single-precision floating-point value has the following bit
2245 pattern, it can be expressed in the AArch64 8-bit floating-point
2248 3 32222222 2221111111111
2249 1 09876543 21098765432109876543210
2250 n Eeeeeexx xxxx0000000000000000000
2252 where n, e and each x are either 0 or 1 independently, with
2257 /* Prepare the pattern for 'Eeeeee'. */
2258 if (((imm
>> 30) & 0x1) == 0)
2259 pattern
= 0x3e000000;
2261 pattern
= 0x40000000;
2263 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2264 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2267 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2268 as an IEEE float without any loss of precision. Store the value in
2272 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2274 /* If a double-precision floating-point value has the following bit
2275 pattern, it can be expressed in a float:
2277 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2278 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2279 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2281 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2282 if Eeee_eeee != 1111_1111
2284 where n, e, s and S are either 0 or 1 independently and where ~ is the
2288 uint32_t high32
= imm
>> 32;
2289 uint32_t low32
= imm
;
2291 /* Lower 29 bits need to be 0s. */
2292 if ((imm
& 0x1fffffff) != 0)
2295 /* Prepare the pattern for 'Eeeeeeeee'. */
2296 if (((high32
>> 30) & 0x1) == 0)
2297 pattern
= 0x38000000;
2299 pattern
= 0x40000000;
2302 if ((high32
& 0x78000000) != pattern
)
2305 /* Check Eeee_eeee != 1111_1111. */
2306 if ((high32
& 0x7ff00000) == 0x47f00000)
2309 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2310 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2311 | (low32
>> 29)); /* 3 S bits. */
2315 /* Return true if we should treat OPERAND as a double-precision
2316 floating-point operand rather than a single-precision one. */
2318 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2320 /* Check for unsuffixed SVE registers, which are allowed
2321 for LDR and STR but not in instructions that require an
2322 immediate. We get better error messages if we arbitrarily
2323 pick one size, parse the immediate normally, and then
2324 report the match failure in the normal way. */
2325 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2326 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2329 /* Parse a floating-point immediate. Return TRUE on success and return the
2330 value in *IMMED in the format of IEEE754 single-precision encoding.
2331 *CCP points to the start of the string; DP_P is TRUE when the immediate
2332 is expected to be in double-precision (N.B. this only matters when
2333 hexadecimal representation is involved). REG_TYPE says which register
2334 names should be treated as registers rather than as symbolic immediates.
2336 This routine accepts any IEEE float; it is up to the callers to reject
2340 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2341 aarch64_reg_type reg_type
)
2345 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2347 unsigned fpword
= 0;
2350 skip_past_char (&str
, '#');
2353 skip_whitespace (fpnum
);
2355 if (startswith (fpnum
, "0x"))
2357 /* Support the hexadecimal representation of the IEEE754 encoding.
2358 Double-precision is expected when DP_P is TRUE, otherwise the
2359 representation should be in single-precision. */
2360 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2365 if (!can_convert_double_to_float (val
, &fpword
))
2368 else if ((uint64_t) val
> 0xffffffff)
2375 else if (reg_name_p (str
, reg_type
))
2377 set_recoverable_error (_("immediate operand required"));
2385 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2388 /* Our FP word must be 32 bits (single-precision FP). */
2389 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2391 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2401 set_fatal_syntax_error (_("invalid floating-point constant"));
2405 /* Less-generic immediate-value read function with the possibility of loading
2406 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2409 To prevent the expression parser from pushing a register name into the
2410 symbol table as an undefined symbol, a check is firstly done to find
2411 out whether STR is a register of type REG_TYPE followed by a comma or
2412 the end of line. Return FALSE if STR is such a register. */
2415 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2419 if (reg_name_p (ptr
, reg_type
))
2421 set_syntax_error (_("immediate operand required"));
2425 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2428 if (inst
.reloc
.exp
.X_op
== O_constant
)
2429 *imm
= inst
.reloc
.exp
.X_add_number
;
2436 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2437 if NEED_LIBOPCODES is non-zero, the fixup will need
2438 assistance from the libopcodes. */
2441 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2442 const aarch64_opnd_info
*operand
,
2443 int need_libopcodes_p
)
2445 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2446 reloc
->opnd
= operand
->type
;
2447 if (need_libopcodes_p
)
2448 reloc
->need_libopcodes_p
= 1;
2451 /* Return TRUE if the instruction needs to be fixed up later internally by
2452 the GAS; otherwise return FALSE. */
2455 aarch64_gas_internal_fixup_p (void)
2457 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2460 /* Assign the immediate value to the relevant field in *OPERAND if
2461 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2462 needs an internal fixup in a later stage.
2463 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2464 IMM.VALUE that may get assigned with the constant. */
2466 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2467 aarch64_opnd_info
*operand
,
2469 int need_libopcodes_p
,
2472 if (reloc
->exp
.X_op
== O_constant
)
2475 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2477 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2478 reloc
->type
= BFD_RELOC_UNUSED
;
2482 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2483 /* Tell libopcodes to ignore this operand or not. This is helpful
2484 when one of the operands needs to be fixed up later but we need
2485 libopcodes to check the other operands. */
2486 operand
->skip
= skip_p
;
2490 /* Relocation modifiers. Each entry in the table contains the textual
2491 name for the relocation which may be placed before a symbol used as
2492 a load/store offset, or add immediate. It must be surrounded by a
2493 leading and trailing colon, for example:
2495 ldr x0, [x1, #:rello:varsym]
2496 add x0, x1, #:rello:varsym */
2498 struct reloc_table_entry
2502 bfd_reloc_code_real_type adr_type
;
2503 bfd_reloc_code_real_type adrp_type
;
2504 bfd_reloc_code_real_type movw_type
;
2505 bfd_reloc_code_real_type add_type
;
2506 bfd_reloc_code_real_type ldst_type
;
2507 bfd_reloc_code_real_type ld_literal_type
;
2510 static struct reloc_table_entry reloc_table
[] =
2512 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2517 BFD_RELOC_AARCH64_ADD_LO12
,
2518 BFD_RELOC_AARCH64_LDST_LO12
,
2521 /* Higher 21 bits of pc-relative page offset: ADRP */
2524 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2530 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2533 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2539 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2543 BFD_RELOC_AARCH64_MOVW_G0
,
2548 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2552 BFD_RELOC_AARCH64_MOVW_G0_S
,
2557 /* Less significant bits 0-15 of address/value: MOVK, no check */
2561 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2566 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2570 BFD_RELOC_AARCH64_MOVW_G1
,
2575 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2579 BFD_RELOC_AARCH64_MOVW_G1_S
,
2584 /* Less significant bits 16-31 of address/value: MOVK, no check */
2588 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2593 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2597 BFD_RELOC_AARCH64_MOVW_G2
,
2602 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2606 BFD_RELOC_AARCH64_MOVW_G2_S
,
2611 /* Less significant bits 32-47 of address/value: MOVK, no check */
2615 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2620 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2624 BFD_RELOC_AARCH64_MOVW_G3
,
2629 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2633 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2638 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2642 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2647 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2651 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2656 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2660 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2665 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2669 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2674 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2678 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2683 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2687 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2692 /* Get to the page containing GOT entry for a symbol. */
2695 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2699 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2701 /* 12 bit offset into the page containing GOT entry for that symbol. */
2707 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2710 /* 0-15 bits of address/value: MOVk, no check. */
2714 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2719 /* Most significant bits 16-31 of address/value: MOVZ. */
2723 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2728 /* 15 bit offset into the page containing GOT entry for that symbol. */
2734 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2737 /* Get to the page containing GOT TLS entry for a symbol */
2738 {"gottprel_g0_nc", 0,
2741 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2746 /* Get to the page containing GOT TLS entry for a symbol */
2750 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2755 /* Get to the page containing GOT TLS entry for a symbol */
2757 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2758 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2764 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2769 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2773 /* Lower 16 bits address/value: MOVk. */
2777 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2782 /* Most significant bits 16-31 of address/value: MOVZ. */
2786 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2791 /* Get to the page containing GOT TLS entry for a symbol */
2793 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2794 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2798 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2800 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2805 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2806 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2809 /* Get to the page containing GOT TLS entry for a symbol.
2810 The same as GD, we allocate two consecutive GOT slots
2811 for module index and module offset, the only difference
2812 with GD is the module offset should be initialized to
2813 zero without any outstanding runtime relocation. */
2815 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2816 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2822 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2823 {"tlsldm_lo12_nc", 0,
2827 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2831 /* 12 bit offset into the module TLS base address. */
2836 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2837 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2840 /* Same as dtprel_lo12, no overflow check. */
2841 {"dtprel_lo12_nc", 0,
2845 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2846 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2849 /* bits[23:12] of offset to the module TLS base address. */
2854 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2858 /* bits[15:0] of offset to the module TLS base address. */
2862 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2867 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2871 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2876 /* bits[31:16] of offset to the module TLS base address. */
2880 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2885 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2889 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2894 /* bits[47:32] of offset to the module TLS base address. */
2898 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2903 /* Lower 16 bit offset into GOT entry for a symbol */
2904 {"tlsdesc_off_g0_nc", 0,
2907 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2912 /* Higher 16 bit offset into GOT entry for a symbol */
2913 {"tlsdesc_off_g1", 0,
2916 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2921 /* Get to the page containing GOT TLS entry for a symbol */
2924 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2928 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2930 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2931 {"gottprel_lo12", 0,
2936 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2939 /* Get tp offset for a symbol. */
2944 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2948 /* Get tp offset for a symbol. */
2953 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2954 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2957 /* Get tp offset for a symbol. */
2962 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2966 /* Get tp offset for a symbol. */
2967 {"tprel_lo12_nc", 0,
2971 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2972 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2975 /* Most significant bits 32-47 of address/value: MOVZ. */
2979 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2984 /* Most significant bits 16-31 of address/value: MOVZ. */
2988 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2993 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2997 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3002 /* Most significant bits 0-15 of address/value: MOVZ. */
3006 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3011 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3015 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3020 /* 15bit offset from got entry to base address of GOT table. */
3026 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3029 /* 14bit offset from got entry to base address of GOT table. */
3035 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3039 /* Given the address of a pointer pointing to the textual name of a
3040 relocation as may appear in assembler source, attempt to find its
3041 details in reloc_table. The pointer will be updated to the character
3042 after the trailing colon. On failure, NULL will be returned;
3043 otherwise return the reloc_table_entry. */
3045 static struct reloc_table_entry
*
3046 find_reloc_table_entry (char **str
)
3049 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3051 int length
= strlen (reloc_table
[i
].name
);
3053 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3054 && (*str
)[length
] == ':')
3056 *str
+= (length
+ 1);
3057 return &reloc_table
[i
];
3064 /* Returns 0 if the relocation should never be forced,
3065 1 if the relocation must be forced, and -1 if either
3069 aarch64_force_reloc (unsigned int type
)
3073 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3074 /* Perform these "immediate" internal relocations
3075 even if the symbol is extern or weak. */
3078 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3079 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3080 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3081 /* Pseudo relocs that need to be fixed up according to
3085 case BFD_RELOC_AARCH64_ADD_LO12
:
3086 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3087 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3088 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3089 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3090 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3091 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3092 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3093 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3094 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3095 case BFD_RELOC_AARCH64_LDST128_LO12
:
3096 case BFD_RELOC_AARCH64_LDST16_LO12
:
3097 case BFD_RELOC_AARCH64_LDST32_LO12
:
3098 case BFD_RELOC_AARCH64_LDST64_LO12
:
3099 case BFD_RELOC_AARCH64_LDST8_LO12
:
3100 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3101 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3102 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3103 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3104 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3105 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3106 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3107 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3108 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3109 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3110 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3111 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3112 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3113 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3114 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3115 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3116 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3117 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3118 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3119 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3120 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3121 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3122 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3123 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3124 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3125 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3126 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3127 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3128 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3129 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3130 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3131 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3132 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3133 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3134 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3135 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3136 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3137 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3138 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3139 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3140 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3141 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3142 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3143 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3144 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3145 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3146 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3147 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3148 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3149 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3150 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3151 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3154 /* Always leave these relocations for the linker. */
3163 aarch64_force_relocation (struct fix
*fixp
)
3165 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3168 return generic_force_reloc (fixp
);
3172 /* Mode argument to parse_shift and parser_shifter_operand. */
3173 enum parse_shift_mode
3175 SHIFTED_NONE
, /* no shifter allowed */
3176 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3178 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3180 SHIFTED_LSL
, /* bare "lsl #n" */
3181 SHIFTED_MUL
, /* bare "mul #n" */
3182 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3183 SHIFTED_MUL_VL
, /* "mul vl" */
3184 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3187 /* Parse a <shift> operator on an AArch64 data processing instruction.
3188 Return TRUE on success; otherwise return FALSE. */
3190 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3192 const struct aarch64_name_value_pair
*shift_op
;
3193 enum aarch64_modifier_kind kind
;
3199 for (p
= *str
; ISALPHA (*p
); p
++)
3204 set_syntax_error (_("shift expression expected"));
3208 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3210 if (shift_op
== NULL
)
3212 set_syntax_error (_("shift operator expected"));
3216 kind
= aarch64_get_operand_modifier (shift_op
);
3218 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3220 set_syntax_error (_("invalid use of 'MSL'"));
3224 if (kind
== AARCH64_MOD_MUL
3225 && mode
!= SHIFTED_MUL
3226 && mode
!= SHIFTED_MUL_VL
)
3228 set_syntax_error (_("invalid use of 'MUL'"));
3234 case SHIFTED_LOGIC_IMM
:
3235 if (aarch64_extend_operator_p (kind
))
3237 set_syntax_error (_("extending shift is not permitted"));
3242 case SHIFTED_ARITH_IMM
:
3243 if (kind
== AARCH64_MOD_ROR
)
3245 set_syntax_error (_("'ROR' shift is not permitted"));
3251 if (kind
!= AARCH64_MOD_LSL
)
3253 set_syntax_error (_("only 'LSL' shift is permitted"));
3259 if (kind
!= AARCH64_MOD_MUL
)
3261 set_syntax_error (_("only 'MUL' is permitted"));
3266 case SHIFTED_MUL_VL
:
3267 /* "MUL VL" consists of two separate tokens. Require the first
3268 token to be "MUL" and look for a following "VL". */
3269 if (kind
== AARCH64_MOD_MUL
)
3271 skip_whitespace (p
);
3272 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3275 kind
= AARCH64_MOD_MUL_VL
;
3279 set_syntax_error (_("only 'MUL VL' is permitted"));
3282 case SHIFTED_REG_OFFSET
:
3283 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3284 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3286 set_fatal_syntax_error
3287 (_("invalid shift for the register offset addressing mode"));
3292 case SHIFTED_LSL_MSL
:
3293 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3295 set_syntax_error (_("invalid shift operator"));
3304 /* Whitespace can appear here if the next thing is a bare digit. */
3305 skip_whitespace (p
);
3307 /* Parse shift amount. */
3309 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3310 exp
.X_op
= O_absent
;
3313 if (is_immediate_prefix (*p
))
3318 (void) aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
,
3321 if (kind
== AARCH64_MOD_MUL_VL
)
3322 /* For consistency, give MUL VL the same shift amount as an implicit
3324 operand
->shifter
.amount
= 1;
3325 else if (exp
.X_op
== O_absent
)
3327 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3329 set_syntax_error (_("missing shift amount"));
3332 operand
->shifter
.amount
= 0;
3334 else if (exp
.X_op
!= O_constant
)
3336 set_syntax_error (_("constant shift amount required"));
3339 /* For parsing purposes, MUL #n has no inherent range. The range
3340 depends on the operand and will be checked by operand-specific
3342 else if (kind
!= AARCH64_MOD_MUL
3343 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3345 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3350 operand
->shifter
.amount
= exp
.X_add_number
;
3351 operand
->shifter
.amount_present
= 1;
3354 operand
->shifter
.operator_present
= 1;
3355 operand
->shifter
.kind
= kind
;
3361 /* Parse a <shifter_operand> for a data processing instruction:
3364 #<immediate>, LSL #imm
3366 Validation of immediate operands is deferred to md_apply_fix.
3368 Return TRUE on success; otherwise return FALSE. */
3371 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3372 enum parse_shift_mode mode
)
3376 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3381 /* Accept an immediate expression. */
3382 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3383 REJECT_ABSENT
, NORMAL_RESOLUTION
))
3386 /* Accept optional LSL for arithmetic immediate values. */
3387 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3388 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3391 /* Not accept any shifter for logical immediate values. */
3392 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3393 && parse_shift (&p
, operand
, mode
))
3395 set_syntax_error (_("unexpected shift operator"));
3403 /* Parse a <shifter_operand> for a data processing instruction:
3408 #<immediate>, LSL #imm
3410 where <shift> is handled by parse_shift above, and the last two
3411 cases are handled by the function above.
3413 Validation of immediate operands is deferred to md_apply_fix.
3415 Return TRUE on success; otherwise return FALSE. */
3418 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3419 enum parse_shift_mode mode
)
3421 const reg_entry
*reg
;
3422 aarch64_opnd_qualifier_t qualifier
;
3423 enum aarch64_operand_class opd_class
3424 = aarch64_get_operand_class (operand
->type
);
3426 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3429 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3431 set_syntax_error (_("unexpected register in the immediate operand"));
3435 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3437 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3441 operand
->reg
.regno
= reg
->number
;
3442 operand
->qualifier
= qualifier
;
3444 /* Accept optional shift operation on register. */
3445 if (! skip_past_comma (str
))
3448 if (! parse_shift (str
, operand
, mode
))
3453 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3456 (_("integer register expected in the extended/shifted operand "
3461 /* We have a shifted immediate variable. */
3462 return parse_shifter_operand_imm (str
, operand
, mode
);
3465 /* Return TRUE on success; return FALSE otherwise. */
3468 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3469 enum parse_shift_mode mode
)
3473 /* Determine if we have the sequence of characters #: or just :
3474 coming next. If we do, then we check for a :rello: relocation
3475 modifier. If we don't, punt the whole lot to
3476 parse_shifter_operand. */
3478 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3480 struct reloc_table_entry
*entry
;
3488 /* Try to parse a relocation. Anything else is an error. */
3489 if (!(entry
= find_reloc_table_entry (str
)))
3491 set_syntax_error (_("unknown relocation modifier"));
3495 if (entry
->add_type
== 0)
3498 (_("this relocation modifier is not allowed on this instruction"));
3502 /* Save str before we decompose it. */
3505 /* Next, we parse the expression. */
3506 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3508 aarch64_force_reloc (entry
->add_type
) == 1))
3511 /* Record the relocation type (use the ADD variant here). */
3512 inst
.reloc
.type
= entry
->add_type
;
3513 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3515 /* If str is empty, we've reached the end, stop here. */
3519 /* Otherwise, we have a shifted reloc modifier, so rewind to
3520 recover the variable name and continue parsing for the shifter. */
3522 return parse_shifter_operand_imm (str
, operand
, mode
);
3525 return parse_shifter_operand (str
, operand
, mode
);
3528 /* Parse all forms of an address expression. Information is written
3529 to *OPERAND and/or inst.reloc.
3531 The A64 instruction set has the following addressing modes:
3534 [base] // in SIMD ld/st structure
3535 [base{,#0}] // in ld/st exclusive
3537 [base,Xm{,LSL #imm}]
3538 [base,Xm,SXTX {#imm}]
3539 [base,Wm,(S|U)XTW {#imm}]
3541 [base]! // in ldraa/ldrab exclusive
3545 [base],Xm // in SIMD ld/st structure
3546 PC-relative (literal)
3550 [base,Zm.D{,LSL #imm}]
3551 [base,Zm.S,(S|U)XTW {#imm}]
3552 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3556 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3557 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3558 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3560 (As a convenience, the notation "=immediate" is permitted in conjunction
3561 with the pc-relative literal load instructions to automatically place an
3562 immediate value or symbolic address in a nearby literal pool and generate
3563 a hidden label which references it.)
3565 Upon a successful parsing, the address structure in *OPERAND will be
3566 filled in the following way:
3568 .base_regno = <base>
3569 .offset.is_reg // 1 if the offset is a register
3571 .offset.regno = <Rm>
3573 For different addressing modes defined in the A64 ISA:
3576 .pcrel=0; .preind=1; .postind=0; .writeback=0
3578 .pcrel=0; .preind=1; .postind=0; .writeback=1
3580 .pcrel=0; .preind=0; .postind=1; .writeback=1
3581 PC-relative (literal)
3582 .pcrel=1; .preind=1; .postind=0; .writeback=0
3584 The shift/extension information, if any, will be stored in .shifter.
3585 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3586 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3587 corresponding register.
3589 BASE_TYPE says which types of base register should be accepted and
3590 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3591 is the type of shifter that is allowed for immediate offsets,
3592 or SHIFTED_NONE if none.
3594 In all other respects, it is the caller's responsibility to check
3595 for addressing modes not supported by the instruction, and to set
3599 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3600 aarch64_opnd_qualifier_t
*base_qualifier
,
3601 aarch64_opnd_qualifier_t
*offset_qualifier
,
3602 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3603 enum parse_shift_mode imm_shift_mode
)
3606 const reg_entry
*reg
;
3607 expressionS
*exp
= &inst
.reloc
.exp
;
3609 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3610 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3611 if (! skip_past_char (&p
, '['))
3613 /* =immediate or label. */
3614 operand
->addr
.pcrel
= 1;
3615 operand
->addr
.preind
= 1;
3617 /* #:<reloc_op>:<symbol> */
3618 skip_past_char (&p
, '#');
3619 if (skip_past_char (&p
, ':'))
3621 bfd_reloc_code_real_type ty
;
3622 struct reloc_table_entry
*entry
;
3624 /* Try to parse a relocation modifier. Anything else is
3626 entry
= find_reloc_table_entry (&p
);
3629 set_syntax_error (_("unknown relocation modifier"));
3633 switch (operand
->type
)
3635 case AARCH64_OPND_ADDR_PCREL21
:
3637 ty
= entry
->adr_type
;
3641 ty
= entry
->ld_literal_type
;
3648 (_("this relocation modifier is not allowed on this "
3654 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3655 aarch64_force_reloc (entry
->add_type
) == 1))
3657 set_syntax_error (_("invalid relocation expression"));
3660 /* #:<reloc_op>:<expr> */
3661 /* Record the relocation type. */
3662 inst
.reloc
.type
= ty
;
3663 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3667 if (skip_past_char (&p
, '='))
3668 /* =immediate; need to generate the literal in the literal pool. */
3669 inst
.gen_lit_pool
= 1;
3671 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3674 set_syntax_error (_("invalid address"));
3685 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3686 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3688 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3691 operand
->addr
.base_regno
= reg
->number
;
3694 if (skip_past_comma (&p
))
3697 operand
->addr
.preind
= 1;
3699 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3702 if (!aarch64_check_reg_type (reg
, offset_type
))
3704 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3709 operand
->addr
.offset
.regno
= reg
->number
;
3710 operand
->addr
.offset
.is_reg
= 1;
3711 /* Shifted index. */
3712 if (skip_past_comma (&p
))
3715 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3716 /* Use the diagnostics set in parse_shift, so not set new
3717 error message here. */
3721 [base,Xm] # For vector plus scalar SVE2 indexing.
3722 [base,Xm{,LSL #imm}]
3723 [base,Xm,SXTX {#imm}]
3724 [base,Wm,(S|U)XTW {#imm}] */
3725 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3726 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3727 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3729 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3731 set_syntax_error (_("invalid use of 32-bit register offset"));
3734 if (aarch64_get_qualifier_esize (*base_qualifier
)
3735 != aarch64_get_qualifier_esize (*offset_qualifier
)
3736 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3737 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3738 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3740 set_syntax_error (_("offset has different size from base"));
3744 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3746 set_syntax_error (_("invalid use of 64-bit register offset"));
3752 /* [Xn,#:<reloc_op>:<symbol> */
3753 skip_past_char (&p
, '#');
3754 if (skip_past_char (&p
, ':'))
3756 struct reloc_table_entry
*entry
;
3758 /* Try to parse a relocation modifier. Anything else is
3760 if (!(entry
= find_reloc_table_entry (&p
)))
3762 set_syntax_error (_("unknown relocation modifier"));
3766 if (entry
->ldst_type
== 0)
3769 (_("this relocation modifier is not allowed on this "
3774 /* [Xn,#:<reloc_op>: */
3775 /* We now have the group relocation table entry corresponding to
3776 the name in the assembler source. Next, we parse the
3778 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3779 aarch64_force_reloc (entry
->add_type
) == 1))
3781 set_syntax_error (_("invalid relocation expression"));
3785 /* [Xn,#:<reloc_op>:<expr> */
3786 /* Record the load/store relocation type. */
3787 inst
.reloc
.type
= entry
->ldst_type
;
3788 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3792 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3795 set_syntax_error (_("invalid expression in the address"));
3799 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3800 /* [Xn,<expr>,<shifter> */
3801 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3807 if (! skip_past_char (&p
, ']'))
3809 set_syntax_error (_("']' expected"));
3813 if (skip_past_char (&p
, '!'))
3815 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3817 set_syntax_error (_("register offset not allowed in pre-indexed "
3818 "addressing mode"));
3822 operand
->addr
.writeback
= 1;
3824 else if (skip_past_comma (&p
))
3827 operand
->addr
.postind
= 1;
3828 operand
->addr
.writeback
= 1;
3830 if (operand
->addr
.preind
)
3832 set_syntax_error (_("cannot combine pre- and post-indexing"));
3836 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3840 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3842 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3846 operand
->addr
.offset
.regno
= reg
->number
;
3847 operand
->addr
.offset
.is_reg
= 1;
3849 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3853 set_syntax_error (_("invalid expression in the address"));
3858 /* If at this point neither .preind nor .postind is set, we have a
3859 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3860 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3861 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3863 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3865 if (operand
->addr
.writeback
)
3867 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3869 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3870 operand
->addr
.offset
.is_reg
= 0;
3871 operand
->addr
.offset
.imm
= 0;
3872 operand
->addr
.preind
= 1;
3877 set_syntax_error (_("missing offset in the pre-indexed address"));
3883 operand
->addr
.preind
= 1;
3884 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3886 operand
->addr
.offset
.is_reg
= 1;
3887 operand
->addr
.offset
.regno
= REG_ZR
;
3888 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3892 inst
.reloc
.exp
.X_op
= O_constant
;
3893 inst
.reloc
.exp
.X_add_number
= 0;
3902 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3905 parse_address (char **str
, aarch64_opnd_info
*operand
)
3907 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3908 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3909 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3912 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3913 The arguments have the same meaning as for parse_address_main.
3914 Return TRUE on success. */
3916 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3917 aarch64_opnd_qualifier_t
*base_qualifier
,
3918 aarch64_opnd_qualifier_t
*offset_qualifier
)
3920 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3921 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3925 /* Parse a register X0-X30. The register must be 64-bit and register 31
3928 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
3930 const reg_entry
*reg
= parse_reg (str
);
3931 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3933 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3936 operand
->reg
.regno
= reg
->number
;
3937 operand
->qualifier
= AARCH64_OPND_QLF_X
;
3941 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3942 Return TRUE on success; otherwise return FALSE. */
3944 parse_half (char **str
, int *internal_fixup_p
)
3948 skip_past_char (&p
, '#');
3950 gas_assert (internal_fixup_p
);
3951 *internal_fixup_p
= 0;
3955 struct reloc_table_entry
*entry
;
3957 /* Try to parse a relocation. Anything else is an error. */
3960 if (!(entry
= find_reloc_table_entry (&p
)))
3962 set_syntax_error (_("unknown relocation modifier"));
3966 if (entry
->movw_type
== 0)
3969 (_("this relocation modifier is not allowed on this instruction"));
3973 inst
.reloc
.type
= entry
->movw_type
;
3976 *internal_fixup_p
= 1;
3978 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3979 aarch64_force_reloc (inst
.reloc
.type
) == 1))
3986 /* Parse an operand for an ADRP instruction:
3988 Return TRUE on success; otherwise return FALSE. */
3991 parse_adrp (char **str
)
3998 struct reloc_table_entry
*entry
;
4000 /* Try to parse a relocation. Anything else is an error. */
4002 if (!(entry
= find_reloc_table_entry (&p
)))
4004 set_syntax_error (_("unknown relocation modifier"));
4008 if (entry
->adrp_type
== 0)
4011 (_("this relocation modifier is not allowed on this instruction"));
4015 inst
.reloc
.type
= entry
->adrp_type
;
4018 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4020 inst
.reloc
.pc_rel
= 1;
4021 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
4022 aarch64_force_reloc (inst
.reloc
.type
) == 1))
4028 /* Miscellaneous. */
4030 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4031 of SIZE tokens in which index I gives the token for field value I,
4032 or is null if field value I is invalid. REG_TYPE says which register
4033 names should be treated as registers rather than as symbolic immediates.
4035 Return true on success, moving *STR past the operand and storing the
4036 field value in *VAL. */
4039 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4040 size_t size
, aarch64_reg_type reg_type
)
4046 /* Match C-like tokens. */
4048 while (ISALNUM (*q
))
4051 for (i
= 0; i
< size
; ++i
)
4053 && strncasecmp (array
[i
], p
, q
- p
) == 0
4054 && array
[i
][q
- p
] == 0)
4061 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4064 if (exp
.X_op
== O_constant
4065 && (uint64_t) exp
.X_add_number
< size
)
4067 *val
= exp
.X_add_number
;
4072 /* Use the default error for this operand. */
4076 /* Parse an option for a preload instruction. Returns the encoding for the
4077 option, or PARSE_FAIL. */
4080 parse_pldop (char **str
)
4083 const struct aarch64_name_value_pair
*o
;
4086 while (ISALNUM (*q
))
4089 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4097 /* Parse an option for a barrier instruction. Returns the encoding for the
4098 option, or PARSE_FAIL. */
4101 parse_barrier (char **str
)
4104 const struct aarch64_name_value_pair
*o
;
4107 while (ISALPHA (*q
))
4110 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4118 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4119 return 0 if successful. Otherwise return PARSE_FAIL. */
4122 parse_barrier_psb (char **str
,
4123 const struct aarch64_name_value_pair
** hint_opt
)
4126 const struct aarch64_name_value_pair
*o
;
4129 while (ISALPHA (*q
))
4132 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4135 set_fatal_syntax_error
4136 ( _("unknown or missing option to PSB/TSB"));
4140 if (o
->value
!= 0x11)
4142 /* PSB only accepts option name 'CSYNC'. */
4144 (_("the specified option is not accepted for PSB/TSB"));
4153 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4154 return 0 if successful. Otherwise return PARSE_FAIL. */
4157 parse_bti_operand (char **str
,
4158 const struct aarch64_name_value_pair
** hint_opt
)
4161 const struct aarch64_name_value_pair
*o
;
4164 while (ISALPHA (*q
))
4167 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4170 set_fatal_syntax_error
4171 ( _("unknown option to BTI"));
4177 /* Valid BTI operands. */
4185 (_("unknown option to BTI"));
4194 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4195 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4200 Side effect: Update STR with current parse position of success.
4203 static const reg_entry
*
4204 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4205 aarch64_opnd_qualifier_t
*qualifier
)
4209 reg_entry
*reg
= parse_reg (str
);
4210 if (reg
!= NULL
&& reg
->type
== reg_type
)
4212 if (!skip_past_char (str
, '.'))
4214 set_syntax_error (_("missing ZA tile element size separator"));
4219 switch (TOLOWER (*q
))
4222 *qualifier
= AARCH64_OPND_QLF_S_B
;
4225 *qualifier
= AARCH64_OPND_QLF_S_H
;
4228 *qualifier
= AARCH64_OPND_QLF_S_S
;
4231 *qualifier
= AARCH64_OPND_QLF_S_D
;
4234 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4248 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4249 Function return tile QUALIFIER on success.
4251 Tiles are in example format: za[0-9]\.[bhsd]
4253 Function returns <ZAda> register number or PARSE_FAIL.
4256 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4259 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4263 regno
= reg
->number
;
4267 case AARCH64_OPND_QLF_S_B
:
4270 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4274 case AARCH64_OPND_QLF_S_H
:
4277 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4281 case AARCH64_OPND_QLF_S_S
:
4284 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4285 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4289 case AARCH64_OPND_QLF_S_D
:
4292 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4293 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4298 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4305 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4310 Function return TRUE if immediate was found, or FALSE.
4313 parse_sme_immediate (char **str
, int64_t *imm
)
4316 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4323 /* Parse index with vector select register and immediate:
4327 where <Wv> is in W12-W15 range and # is optional for immediate.
4329 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4332 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4336 parse_sme_za_hv_tiles_operand_index (char **str
,
4337 int *vector_select_register
,
4340 const reg_entry
*reg
;
4342 if (!skip_past_char (str
, '['))
4344 set_syntax_error (_("expected '['"));
4348 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4349 reg
= parse_reg (str
);
4350 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4351 || reg
->number
< 12 || reg
->number
> 15)
4353 set_syntax_error (_("expected vector select register W12-W15"));
4356 *vector_select_register
= reg
->number
;
4358 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4360 set_syntax_error (_("expected ','"));
4364 if (!parse_sme_immediate (str
, imm
))
4366 set_syntax_error (_("index offset immediate expected"));
4370 if (!skip_past_char (str
, ']'))
4372 set_syntax_error (_("expected ']'"));
4379 /* Parse SME ZA horizontal or vertical vector access to tiles.
4380 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4381 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4382 contains <Wv> select register and corresponding optional IMMEDIATE.
4383 In addition QUALIFIER is extracted.
4385 Field format examples:
4387 ZA0<HV>.B[<Wv>, #<imm>]
4388 <ZAn><HV>.H[<Wv>, #<imm>]
4389 <ZAn><HV>.S[<Wv>, #<imm>]
4390 <ZAn><HV>.D[<Wv>, #<imm>]
4391 <ZAn><HV>.Q[<Wv>, #<imm>]
4393 Function returns <ZAda> register number or PARSE_FAIL.
4396 parse_sme_za_hv_tiles_operand (char **str
,
4397 enum sme_hv_slice
*slice_indicator
,
4398 int *vector_select_register
,
4400 aarch64_opnd_qualifier_t
*qualifier
)
4407 const reg_entry
*reg
;
4410 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4412 *slice_indicator
= HV_horizontal
;
4415 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4417 *slice_indicator
= HV_vertical
;
4422 regno
= reg
->number
;
4426 case AARCH64_OPND_QLF_S_B
:
4430 case AARCH64_OPND_QLF_S_H
:
4434 case AARCH64_OPND_QLF_S_S
:
4438 case AARCH64_OPND_QLF_S_D
:
4442 case AARCH64_OPND_QLF_S_Q
:
4447 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4451 /* Check if destination register ZA tile vector is in range for given
4452 instruction variant. */
4453 if (regno
< 0 || regno
> regno_limit
)
4455 set_syntax_error (_("ZA tile vector out of range"));
4459 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4463 /* Check if optional index offset is in the range for instruction
4465 if (imm_value
< 0 || imm_value
> imm_limit
)
4467 set_syntax_error (_("index offset out of range"));
4478 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4479 enum sme_hv_slice
*slice_indicator
,
4480 int *vector_select_register
,
4482 aarch64_opnd_qualifier_t
*qualifier
)
4486 if (!skip_past_char (str
, '{'))
4488 set_syntax_error (_("expected '{'"));
4492 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4493 vector_select_register
, imm
,
4496 if (regno
== PARSE_FAIL
)
4499 if (!skip_past_char (str
, '}'))
4501 set_syntax_error (_("expected '}'"));
4508 /* Parse list of up to eight 64-bit element tile names separated by commas in
4509 SME's ZERO instruction:
4513 Function returns <mask>:
4515 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4518 parse_sme_zero_mask(char **str
)
4522 aarch64_opnd_qualifier_t qualifier
;
4528 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4531 int regno
= reg
->number
;
4532 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4534 /* { ZA0.B } is assembled as all-ones immediate. */
4537 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4538 mask
|= 0x55 << regno
;
4539 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4540 mask
|= 0x11 << regno
;
4541 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4542 mask
|= 0x01 << regno
;
4545 set_syntax_error (_("wrong ZA tile element format"));
4550 else if (strncasecmp (q
, "za", 2) == 0
4553 /* { ZA } is assembled as all-ones immediate. */
4560 set_syntax_error (_("wrong ZA tile element format"));
4564 while (skip_past_char (&q
, ','));
4570 /* Wraps in curly braces <mask> operand ZERO instruction:
4574 Function returns value of <mask> bit-field.
4577 parse_sme_list_of_64bit_tiles (char **str
)
4581 if (!skip_past_char (str
, '{'))
4583 set_syntax_error (_("expected '{'"));
4587 /* Empty <mask> list is an all-zeros immediate. */
4588 if (!skip_past_char (str
, '}'))
4590 regno
= parse_sme_zero_mask (str
);
4591 if (regno
== PARSE_FAIL
)
4594 if (!skip_past_char (str
, '}'))
4596 set_syntax_error (_("expected '}'"));
4606 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4612 Function returns <Wv> or PARSE_FAIL.
4615 parse_sme_za_array (char **str
, int *imm
)
4622 while (ISALPHA (*q
))
4625 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4627 set_syntax_error (_("expected ZA array"));
4631 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4634 if (imm_value
< 0 || imm_value
> 15)
4636 set_syntax_error (_("offset out of range"));
4645 /* Parse streaming mode operand for SMSTART and SMSTOP.
4649 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4652 parse_sme_sm_za (char **str
)
4657 while (ISALPHA (*q
))
4661 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4663 set_syntax_error (_("expected SM or ZA operand"));
4668 return TOLOWER (p
[0]);
4671 /* Parse the name of the source scalable predicate register, the index base
4672 register W12-W15 and the element index. Function performs element index
4673 limit checks as well as qualifier type checks.
4675 <Pn>.<T>[<Wv>, <imm>]
4676 <Pn>.<T>[<Wv>, #<imm>]
4678 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4680 Function returns <Pn>, or PARSE_FAIL.
4683 parse_sme_pred_reg_with_index(char **str
,
4684 int *index_base_reg
,
4686 aarch64_opnd_qualifier_t
*qualifier
)
4691 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4695 regno
= reg
->number
;
4699 case AARCH64_OPND_QLF_S_B
:
4702 case AARCH64_OPND_QLF_S_H
:
4705 case AARCH64_OPND_QLF_S_S
:
4708 case AARCH64_OPND_QLF_S_D
:
4712 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4716 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4719 if (imm_value
< 0 || imm_value
> imm_limit
)
4721 set_syntax_error (_("element index out of range for given variant"));
4730 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4731 Returns the encoding for the option, or PARSE_FAIL.
4733 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4734 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4736 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4737 field, otherwise as a system register.
4741 parse_sys_reg (char **str
, htab_t sys_regs
,
4742 int imple_defined_p
, int pstatefield_p
,
4746 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4747 const aarch64_sys_reg
*o
;
4751 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4752 if (p
< buf
+ (sizeof (buf
) - 1))
4753 *p
++ = TOLOWER (*q
);
4756 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4757 valid system register. This is enforced by construction of the hash
4759 if (p
- buf
!= q
- *str
)
4762 o
= str_hash_find (sys_regs
, buf
);
4765 if (!imple_defined_p
)
4769 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4770 unsigned int op0
, op1
, cn
, cm
, op2
;
4772 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4775 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4777 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4784 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4785 as_bad (_("selected processor does not support PSTATE field "
4788 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4789 o
->value
, o
->flags
, o
->features
))
4790 as_bad (_("selected processor does not support system register "
4792 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4793 as_warn (_("system register name '%s' is deprecated and may be "
4794 "removed in a future release"), buf
);
4804 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4805 for the option, or NULL. */
4807 static const aarch64_sys_ins_reg
*
4808 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4811 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4812 const aarch64_sys_ins_reg
*o
;
4815 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4816 if (p
< buf
+ (sizeof (buf
) - 1))
4817 *p
++ = TOLOWER (*q
);
4820 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4821 valid system register. This is enforced by construction of the hash
4823 if (p
- buf
!= q
- *str
)
4826 o
= str_hash_find (sys_ins_regs
, buf
);
4830 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4831 o
->name
, o
->value
, o
->flags
, 0))
4832 as_bad (_("selected processor does not support system register "
4834 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4835 as_warn (_("system register name '%s' is deprecated and may be "
4836 "removed in a future release"), buf
);
4842 #define po_char_or_fail(chr) do { \
4843 if (! skip_past_char (&str, chr)) \
4847 #define po_reg_or_fail(regtype) do { \
4848 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4849 if (val == PARSE_FAIL) \
4851 set_default_error (); \
4856 #define po_int_reg_or_fail(reg_type) do { \
4857 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4858 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4860 set_default_error (); \
4863 info->reg.regno = reg->number; \
4864 info->qualifier = qualifier; \
4867 #define po_imm_nc_or_fail() do { \
4868 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4872 #define po_imm_or_fail(min, max) do { \
4873 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4875 if (val < min || val > max) \
4877 set_fatal_syntax_error (_("immediate value out of range "\
4878 #min " to "#max)); \
4883 #define po_enum_or_fail(array) do { \
4884 if (!parse_enum_string (&str, &val, array, \
4885 ARRAY_SIZE (array), imm_reg_type)) \
4889 #define po_misc_or_fail(expr) do { \
4894 /* encode the 12-bit imm field of Add/sub immediate */
4895 static inline uint32_t
4896 encode_addsub_imm (uint32_t imm
)
4901 /* encode the shift amount field of Add/sub immediate */
4902 static inline uint32_t
4903 encode_addsub_imm_shift_amount (uint32_t cnt
)
4909 /* encode the imm field of Adr instruction */
4910 static inline uint32_t
4911 encode_adr_imm (uint32_t imm
)
4913 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4914 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4917 /* encode the immediate field of Move wide immediate */
4918 static inline uint32_t
4919 encode_movw_imm (uint32_t imm
)
4924 /* encode the 26-bit offset of unconditional branch */
4925 static inline uint32_t
4926 encode_branch_ofs_26 (uint32_t ofs
)
4928 return ofs
& ((1 << 26) - 1);
4931 /* encode the 19-bit offset of conditional branch and compare & branch */
4932 static inline uint32_t
4933 encode_cond_branch_ofs_19 (uint32_t ofs
)
4935 return (ofs
& ((1 << 19) - 1)) << 5;
4938 /* encode the 19-bit offset of ld literal */
4939 static inline uint32_t
4940 encode_ld_lit_ofs_19 (uint32_t ofs
)
4942 return (ofs
& ((1 << 19) - 1)) << 5;
4945 /* Encode the 14-bit offset of test & branch. */
4946 static inline uint32_t
4947 encode_tst_branch_ofs_14 (uint32_t ofs
)
4949 return (ofs
& ((1 << 14) - 1)) << 5;
4952 /* Encode the 16-bit imm field of svc/hvc/smc. */
4953 static inline uint32_t
4954 encode_svc_imm (uint32_t imm
)
4959 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4960 static inline uint32_t
4961 reencode_addsub_switch_add_sub (uint32_t opcode
)
4963 return opcode
^ (1 << 30);
4966 static inline uint32_t
4967 reencode_movzn_to_movz (uint32_t opcode
)
4969 return opcode
| (1 << 30);
4972 static inline uint32_t
4973 reencode_movzn_to_movn (uint32_t opcode
)
4975 return opcode
& ~(1 << 30);
4978 /* Overall per-instruction processing. */
4980 /* We need to be able to fix up arbitrary expressions in some statements.
4981 This is so that we can handle symbols that are an arbitrary distance from
4982 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4983 which returns part of an address in a form which will be valid for
4984 a data instruction. We do this by pushing the expression into a symbol
4985 in the expr_section, and creating a fix for that. */
4988 fix_new_aarch64 (fragS
* frag
,
5003 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5007 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5014 /* Diagnostics on operands errors. */
5016 /* By default, output verbose error message.
5017 Disable the verbose error message by -mno-verbose-error. */
5018 static int verbose_error_p
= 1;
5020 #ifdef DEBUG_AARCH64
5021 /* N.B. this is only for the purpose of debugging. */
5022 const char* operand_mismatch_kind_names
[] =
5025 "AARCH64_OPDE_RECOVERABLE",
5026 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5027 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5028 "AARCH64_OPDE_SYNTAX_ERROR",
5029 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5030 "AARCH64_OPDE_INVALID_VARIANT",
5031 "AARCH64_OPDE_OUT_OF_RANGE",
5032 "AARCH64_OPDE_UNALIGNED",
5033 "AARCH64_OPDE_REG_LIST",
5034 "AARCH64_OPDE_OTHER_ERROR",
5036 #endif /* DEBUG_AARCH64 */
5038 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5040 When multiple errors of different kinds are found in the same assembly
5041 line, only the error of the highest severity will be picked up for
5042 issuing the diagnostics. */
5045 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5046 enum aarch64_operand_error_kind rhs
)
5048 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5049 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5050 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5051 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5052 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5053 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5054 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5055 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5056 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5057 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5058 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5062 /* Helper routine to get the mnemonic name from the assembly instruction
5063 line; should only be called for the diagnosis purpose, as there is
5064 string copy operation involved, which may affect the runtime
5065 performance if used in elsewhere. */
5068 get_mnemonic_name (const char *str
)
5070 static char mnemonic
[32];
5073 /* Get the first 15 bytes and assume that the full name is included. */
5074 strncpy (mnemonic
, str
, 31);
5075 mnemonic
[31] = '\0';
5077 /* Scan up to the end of the mnemonic, which must end in white space,
5078 '.', or end of string. */
5079 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5084 /* Append '...' to the truncated long name. */
5085 if (ptr
- mnemonic
== 31)
5086 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5092 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5094 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5095 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5098 /* Data structures storing one user error in the assembly code related to
5101 struct operand_error_record
5103 const aarch64_opcode
*opcode
;
5104 aarch64_operand_error detail
;
5105 struct operand_error_record
*next
;
5108 typedef struct operand_error_record operand_error_record
;
5110 struct operand_errors
5112 operand_error_record
*head
;
5113 operand_error_record
*tail
;
5116 typedef struct operand_errors operand_errors
;
5118 /* Top-level data structure reporting user errors for the current line of
5120 The way md_assemble works is that all opcodes sharing the same mnemonic
5121 name are iterated to find a match to the assembly line. In this data
5122 structure, each of the such opcodes will have one operand_error_record
5123 allocated and inserted. In other words, excessive errors related with
5124 a single opcode are disregarded. */
5125 operand_errors operand_error_report
;
5127 /* Free record nodes. */
5128 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5130 /* Initialize the data structure that stores the operand mismatch
5131 information on assembling one line of the assembly code. */
5133 init_operand_error_report (void)
5135 if (operand_error_report
.head
!= NULL
)
5137 gas_assert (operand_error_report
.tail
!= NULL
);
5138 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5139 free_opnd_error_record_nodes
= operand_error_report
.head
;
5140 operand_error_report
.head
= NULL
;
5141 operand_error_report
.tail
= NULL
;
5144 gas_assert (operand_error_report
.tail
== NULL
);
5147 /* Return TRUE if some operand error has been recorded during the
5148 parsing of the current assembly line using the opcode *OPCODE;
5149 otherwise return FALSE. */
5151 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5153 operand_error_record
*record
= operand_error_report
.head
;
5154 return record
&& record
->opcode
== opcode
;
5157 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5158 OPCODE field is initialized with OPCODE.
5159 N.B. only one record for each opcode, i.e. the maximum of one error is
5160 recorded for each instruction template. */
5163 add_operand_error_record (const operand_error_record
* new_record
)
5165 const aarch64_opcode
*opcode
= new_record
->opcode
;
5166 operand_error_record
* record
= operand_error_report
.head
;
5168 /* The record may have been created for this opcode. If not, we need
5170 if (! opcode_has_operand_error_p (opcode
))
5172 /* Get one empty record. */
5173 if (free_opnd_error_record_nodes
== NULL
)
5175 record
= XNEW (operand_error_record
);
5179 record
= free_opnd_error_record_nodes
;
5180 free_opnd_error_record_nodes
= record
->next
;
5182 record
->opcode
= opcode
;
5183 /* Insert at the head. */
5184 record
->next
= operand_error_report
.head
;
5185 operand_error_report
.head
= record
;
5186 if (operand_error_report
.tail
== NULL
)
5187 operand_error_report
.tail
= record
;
5189 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5190 && record
->detail
.index
<= new_record
->detail
.index
5191 && operand_error_higher_severity_p (record
->detail
.kind
,
5192 new_record
->detail
.kind
))
5194 /* In the case of multiple errors found on operands related with a
5195 single opcode, only record the error of the leftmost operand and
5196 only if the error is of higher severity. */
5197 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5198 " the existing error %s on operand %d",
5199 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5200 new_record
->detail
.index
,
5201 operand_mismatch_kind_names
[record
->detail
.kind
],
5202 record
->detail
.index
);
5206 record
->detail
= new_record
->detail
;
5210 record_operand_error_info (const aarch64_opcode
*opcode
,
5211 aarch64_operand_error
*error_info
)
5213 operand_error_record record
;
5214 record
.opcode
= opcode
;
5215 record
.detail
= *error_info
;
5216 add_operand_error_record (&record
);
5219 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5220 error message *ERROR, for operand IDX (count from 0). */
5223 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5224 enum aarch64_operand_error_kind kind
,
5227 aarch64_operand_error info
;
5228 memset(&info
, 0, sizeof (info
));
5232 info
.non_fatal
= false;
5233 record_operand_error_info (opcode
, &info
);
5237 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5238 enum aarch64_operand_error_kind kind
,
5239 const char* error
, const int *extra_data
)
5241 aarch64_operand_error info
;
5245 info
.data
[0].i
= extra_data
[0];
5246 info
.data
[1].i
= extra_data
[1];
5247 info
.data
[2].i
= extra_data
[2];
5248 info
.non_fatal
= false;
5249 record_operand_error_info (opcode
, &info
);
5253 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5254 const char* error
, int lower_bound
,
5257 int data
[3] = {lower_bound
, upper_bound
, 0};
5258 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5262 /* Remove the operand error record for *OPCODE. */
5263 static void ATTRIBUTE_UNUSED
5264 remove_operand_error_record (const aarch64_opcode
*opcode
)
5266 if (opcode_has_operand_error_p (opcode
))
5268 operand_error_record
* record
= operand_error_report
.head
;
5269 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5270 operand_error_report
.head
= record
->next
;
5271 record
->next
= free_opnd_error_record_nodes
;
5272 free_opnd_error_record_nodes
= record
;
5273 if (operand_error_report
.head
== NULL
)
5275 gas_assert (operand_error_report
.tail
== record
);
5276 operand_error_report
.tail
= NULL
;
5281 /* Given the instruction in *INSTR, return the index of the best matched
5282 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5284 Return -1 if there is no qualifier sequence; return the first match
5285 if there is multiple matches found. */
5288 find_best_match (const aarch64_inst
*instr
,
5289 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5291 int i
, num_opnds
, max_num_matched
, idx
;
5293 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5296 DEBUG_TRACE ("no operand");
5300 max_num_matched
= 0;
5303 /* For each pattern. */
5304 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5307 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5309 /* Most opcodes has much fewer patterns in the list. */
5310 if (empty_qualifier_sequence_p (qualifiers
))
5312 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5316 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5317 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5320 if (num_matched
> max_num_matched
)
5322 max_num_matched
= num_matched
;
5327 DEBUG_TRACE ("return with %d", idx
);
5331 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5332 corresponding operands in *INSTR. */
5335 assign_qualifier_sequence (aarch64_inst
*instr
,
5336 const aarch64_opnd_qualifier_t
*qualifiers
)
5339 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5340 gas_assert (num_opnds
);
5341 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5342 instr
->operands
[i
].qualifier
= *qualifiers
;
5345 /* Print operands for the diagnosis purpose. */
5348 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5349 const aarch64_opnd_info
*opnds
)
5353 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5357 /* We regard the opcode operand info more, however we also look into
5358 the inst->operands to support the disassembling of the optional
5360 The two operand code should be the same in all cases, apart from
5361 when the operand can be optional. */
5362 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5363 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5366 /* Generate the operand string in STR. */
5367 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5372 strcat (buf
, i
== 0 ? " " : ", ");
5374 /* Append the operand string. */
5379 /* Send to stderr a string as information. */
5382 output_info (const char *format
, ...)
5388 file
= as_where (&line
);
5392 fprintf (stderr
, "%s:%u: ", file
, line
);
5394 fprintf (stderr
, "%s: ", file
);
5396 fprintf (stderr
, _("Info: "));
5397 va_start (args
, format
);
5398 vfprintf (stderr
, format
, args
);
5400 (void) putc ('\n', stderr
);
5403 /* Output one operand error record. */
5406 output_operand_error_record (const operand_error_record
*record
, char *str
)
5408 const aarch64_operand_error
*detail
= &record
->detail
;
5409 int idx
= detail
->index
;
5410 const aarch64_opcode
*opcode
= record
->opcode
;
5411 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5412 : AARCH64_OPND_NIL
);
5414 typedef void (*handler_t
)(const char *format
, ...);
5415 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5417 switch (detail
->kind
)
5419 case AARCH64_OPDE_NIL
:
5423 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5424 handler (_("this `%s' should have an immediately preceding `%s'"
5426 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5429 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5430 handler (_("the preceding `%s' should be followed by `%s` rather"
5431 " than `%s` -- `%s'"),
5432 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5435 case AARCH64_OPDE_SYNTAX_ERROR
:
5436 case AARCH64_OPDE_RECOVERABLE
:
5437 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5438 case AARCH64_OPDE_OTHER_ERROR
:
5439 /* Use the prepared error message if there is, otherwise use the
5440 operand description string to describe the error. */
5441 if (detail
->error
!= NULL
)
5444 handler (_("%s -- `%s'"), detail
->error
, str
);
5446 handler (_("%s at operand %d -- `%s'"),
5447 detail
->error
, idx
+ 1, str
);
5451 gas_assert (idx
>= 0);
5452 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5453 aarch64_get_operand_desc (opd_code
), str
);
5457 case AARCH64_OPDE_INVALID_VARIANT
:
5458 handler (_("operand mismatch -- `%s'"), str
);
5459 if (verbose_error_p
)
5461 /* We will try to correct the erroneous instruction and also provide
5462 more information e.g. all other valid variants.
5464 The string representation of the corrected instruction and other
5465 valid variants are generated by
5467 1) obtaining the intermediate representation of the erroneous
5469 2) manipulating the IR, e.g. replacing the operand qualifier;
5470 3) printing out the instruction by calling the printer functions
5471 shared with the disassembler.
5473 The limitation of this method is that the exact input assembly
5474 line cannot be accurately reproduced in some cases, for example an
5475 optional operand present in the actual assembly line will be
5476 omitted in the output; likewise for the optional syntax rules,
5477 e.g. the # before the immediate. Another limitation is that the
5478 assembly symbols and relocation operations in the assembly line
5479 currently cannot be printed out in the error report. Last but not
5480 least, when there is other error(s) co-exist with this error, the
5481 'corrected' instruction may be still incorrect, e.g. given
5482 'ldnp h0,h1,[x0,#6]!'
5483 this diagnosis will provide the version:
5484 'ldnp s0,s1,[x0,#6]!'
5485 which is still not right. */
5486 size_t len
= strlen (get_mnemonic_name (str
));
5490 aarch64_inst
*inst_base
= &inst
.base
;
5491 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5494 reset_aarch64_instruction (&inst
);
5495 inst_base
->opcode
= opcode
;
5497 /* Reset the error report so that there is no side effect on the
5498 following operand parsing. */
5499 init_operand_error_report ();
5502 result
= parse_operands (str
+ len
, opcode
)
5503 && programmer_friendly_fixup (&inst
);
5504 gas_assert (result
);
5505 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5506 NULL
, NULL
, insn_sequence
);
5507 gas_assert (!result
);
5509 /* Find the most matched qualifier sequence. */
5510 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5511 gas_assert (qlf_idx
> -1);
5513 /* Assign the qualifiers. */
5514 assign_qualifier_sequence (inst_base
,
5515 opcode
->qualifiers_list
[qlf_idx
]);
5517 /* Print the hint. */
5518 output_info (_(" did you mean this?"));
5519 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5520 print_operands (buf
, opcode
, inst_base
->operands
);
5521 output_info (_(" %s"), buf
);
5523 /* Print out other variant(s) if there is any. */
5525 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5526 output_info (_(" other valid variant(s):"));
5528 /* For each pattern. */
5529 qualifiers_list
= opcode
->qualifiers_list
;
5530 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5532 /* Most opcodes has much fewer patterns in the list.
5533 First NIL qualifier indicates the end in the list. */
5534 if (empty_qualifier_sequence_p (*qualifiers_list
))
5539 /* Mnemonics name. */
5540 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5542 /* Assign the qualifiers. */
5543 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5545 /* Print instruction. */
5546 print_operands (buf
, opcode
, inst_base
->operands
);
5548 output_info (_(" %s"), buf
);
5554 case AARCH64_OPDE_UNTIED_IMMS
:
5555 handler (_("operand %d must have the same immediate value "
5556 "as operand 1 -- `%s'"),
5557 detail
->index
+ 1, str
);
5560 case AARCH64_OPDE_UNTIED_OPERAND
:
5561 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5562 detail
->index
+ 1, str
);
5565 case AARCH64_OPDE_OUT_OF_RANGE
:
5566 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5567 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5568 detail
->error
? detail
->error
: _("immediate value"),
5569 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5571 handler (_("%s must be %d at operand %d -- `%s'"),
5572 detail
->error
? detail
->error
: _("immediate value"),
5573 detail
->data
[0].i
, idx
+ 1, str
);
5576 case AARCH64_OPDE_REG_LIST
:
5577 if (detail
->data
[0].i
== 1)
5578 handler (_("invalid number of registers in the list; "
5579 "only 1 register is expected at operand %d -- `%s'"),
5582 handler (_("invalid number of registers in the list; "
5583 "%d registers are expected at operand %d -- `%s'"),
5584 detail
->data
[0].i
, idx
+ 1, str
);
5587 case AARCH64_OPDE_UNALIGNED
:
5588 handler (_("immediate value must be a multiple of "
5589 "%d at operand %d -- `%s'"),
5590 detail
->data
[0].i
, idx
+ 1, str
);
5599 /* Process and output the error message about the operand mismatching.
5601 When this function is called, the operand error information had
5602 been collected for an assembly line and there will be multiple
5603 errors in the case of multiple instruction templates; output the
5604 error message that most closely describes the problem.
5606 The errors to be printed can be filtered on printing all errors
5607 or only non-fatal errors. This distinction has to be made because
5608 the error buffer may already be filled with fatal errors we don't want to
5609 print due to the different instruction templates. */
5612 output_operand_error_report (char *str
, bool non_fatal_only
)
5614 int largest_error_pos
;
5615 const char *msg
= NULL
;
5616 enum aarch64_operand_error_kind kind
;
5617 operand_error_record
*curr
;
5618 operand_error_record
*head
= operand_error_report
.head
;
5619 operand_error_record
*record
= NULL
;
5621 /* No error to report. */
5625 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5627 /* Only one error. */
5628 if (head
== operand_error_report
.tail
)
5630 /* If the only error is a non-fatal one and we don't want to print it,
5632 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5634 DEBUG_TRACE ("single opcode entry with error kind: %s",
5635 operand_mismatch_kind_names
[head
->detail
.kind
]);
5636 output_operand_error_record (head
, str
);
5641 /* Find the error kind of the highest severity. */
5642 DEBUG_TRACE ("multiple opcode entries with error kind");
5643 kind
= AARCH64_OPDE_NIL
;
5644 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5646 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5647 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5648 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5649 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5650 kind
= curr
->detail
.kind
;
5653 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5655 /* Pick up one of errors of KIND to report. */
5656 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5657 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5659 /* If we don't want to print non-fatal errors then don't consider them
5661 if (curr
->detail
.kind
!= kind
5662 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5664 /* If there are multiple errors, pick up the one with the highest
5665 mismatching operand index. In the case of multiple errors with
5666 the equally highest operand index, pick up the first one or the
5667 first one with non-NULL error message. */
5668 if (curr
->detail
.index
> largest_error_pos
5669 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5670 && curr
->detail
.error
!= NULL
))
5672 largest_error_pos
= curr
->detail
.index
;
5674 msg
= record
->detail
.error
;
5678 /* The way errors are collected in the back-end is a bit non-intuitive. But
5679 essentially, because each operand template is tried recursively you may
5680 always have errors collected from the previous tried OPND. These are
5681 usually skipped if there is one successful match. However now with the
5682 non-fatal errors we have to ignore those previously collected hard errors
5683 when we're only interested in printing the non-fatal ones. This condition
5684 prevents us from printing errors that are not appropriate, since we did
5685 match a condition, but it also has warnings that it wants to print. */
5686 if (non_fatal_only
&& !record
)
5689 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5690 DEBUG_TRACE ("Pick up error kind %s to report",
5691 operand_mismatch_kind_names
[record
->detail
.kind
]);
5694 output_operand_error_record (record
, str
);
5697 /* Write an AARCH64 instruction to buf - always little-endian. */
5699 put_aarch64_insn (char *buf
, uint32_t insn
)
5701 unsigned char *where
= (unsigned char *) buf
;
5703 where
[1] = insn
>> 8;
5704 where
[2] = insn
>> 16;
5705 where
[3] = insn
>> 24;
5709 get_aarch64_insn (char *buf
)
5711 unsigned char *where
= (unsigned char *) buf
;
5713 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5714 | ((uint32_t) where
[3] << 24)));
5719 output_inst (struct aarch64_inst
*new_inst
)
5723 to
= frag_more (INSN_SIZE
);
5725 frag_now
->tc_frag_data
.recorded
= 1;
5727 put_aarch64_insn (to
, inst
.base
.value
);
5729 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5731 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5732 INSN_SIZE
, &inst
.reloc
.exp
,
5735 DEBUG_TRACE ("Prepared relocation fix up");
5736 /* Don't check the addend value against the instruction size,
5737 that's the job of our code in md_apply_fix(). */
5738 fixp
->fx_no_overflow
= 1;
5739 if (new_inst
!= NULL
)
5740 fixp
->tc_fix_data
.inst
= new_inst
;
5741 if (aarch64_gas_internal_fixup_p ())
5743 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5744 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5745 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5749 dwarf2_emit_insn (INSN_SIZE
);
5752 /* Link together opcodes of the same name. */
5756 const aarch64_opcode
*opcode
;
5757 struct templates
*next
;
5760 typedef struct templates templates
;
5763 lookup_mnemonic (const char *start
, int len
)
5765 templates
*templ
= NULL
;
5767 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5771 /* Subroutine of md_assemble, responsible for looking up the primary
5772 opcode from the mnemonic the user wrote. BASE points to the beginning
5773 of the mnemonic, DOT points to the first '.' within the mnemonic
5774 (if any) and END points to the end of the mnemonic. */
5777 opcode_lookup (char *base
, char *dot
, char *end
)
5779 const aarch64_cond
*cond
;
5786 inst
.cond
= COND_ALWAYS
;
5788 /* Handle a possible condition. */
5791 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5794 inst
.cond
= cond
->value
;
5800 if (inst
.cond
== COND_ALWAYS
)
5802 /* Look for unaffixed mnemonic. */
5803 return lookup_mnemonic (base
, len
);
5807 /* append ".c" to mnemonic if conditional */
5808 memcpy (condname
, base
, len
);
5809 memcpy (condname
+ len
, ".c", 2);
5812 return lookup_mnemonic (base
, len
);
5818 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5819 to a corresponding operand qualifier. */
5821 static inline aarch64_opnd_qualifier_t
5822 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5824 /* Element size in bytes indexed by vector_el_type. */
5825 const unsigned char ele_size
[5]
5827 const unsigned int ele_base
[5] =
5829 AARCH64_OPND_QLF_V_4B
,
5830 AARCH64_OPND_QLF_V_2H
,
5831 AARCH64_OPND_QLF_V_2S
,
5832 AARCH64_OPND_QLF_V_1D
,
5833 AARCH64_OPND_QLF_V_1Q
5836 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5837 goto vectype_conversion_fail
;
5839 if (vectype
->type
== NT_zero
)
5840 return AARCH64_OPND_QLF_P_Z
;
5841 if (vectype
->type
== NT_merge
)
5842 return AARCH64_OPND_QLF_P_M
;
5844 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5846 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5848 /* Special case S_4B. */
5849 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5850 return AARCH64_OPND_QLF_S_4B
;
5852 /* Special case S_2H. */
5853 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5854 return AARCH64_OPND_QLF_S_2H
;
5856 /* Vector element register. */
5857 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5861 /* Vector register. */
5862 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5865 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5866 goto vectype_conversion_fail
;
5868 /* The conversion is by calculating the offset from the base operand
5869 qualifier for the vector type. The operand qualifiers are regular
5870 enough that the offset can established by shifting the vector width by
5871 a vector-type dependent amount. */
5873 if (vectype
->type
== NT_b
)
5875 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5877 else if (vectype
->type
>= NT_d
)
5882 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5883 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5884 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5888 vectype_conversion_fail
:
5889 first_error (_("bad vector arrangement type"));
5890 return AARCH64_OPND_QLF_NIL
;
5893 /* Process an optional operand that is found omitted from the assembly line.
5894 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5895 instruction's opcode entry while IDX is the index of this omitted operand.
5899 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5900 int idx
, aarch64_opnd_info
*operand
)
5902 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5903 gas_assert (optional_operand_p (opcode
, idx
));
5904 gas_assert (!operand
->present
);
5908 case AARCH64_OPND_Rd
:
5909 case AARCH64_OPND_Rn
:
5910 case AARCH64_OPND_Rm
:
5911 case AARCH64_OPND_Rt
:
5912 case AARCH64_OPND_Rt2
:
5913 case AARCH64_OPND_Rt_LS64
:
5914 case AARCH64_OPND_Rt_SP
:
5915 case AARCH64_OPND_Rs
:
5916 case AARCH64_OPND_Ra
:
5917 case AARCH64_OPND_Rt_SYS
:
5918 case AARCH64_OPND_Rd_SP
:
5919 case AARCH64_OPND_Rn_SP
:
5920 case AARCH64_OPND_Rm_SP
:
5921 case AARCH64_OPND_Fd
:
5922 case AARCH64_OPND_Fn
:
5923 case AARCH64_OPND_Fm
:
5924 case AARCH64_OPND_Fa
:
5925 case AARCH64_OPND_Ft
:
5926 case AARCH64_OPND_Ft2
:
5927 case AARCH64_OPND_Sd
:
5928 case AARCH64_OPND_Sn
:
5929 case AARCH64_OPND_Sm
:
5930 case AARCH64_OPND_Va
:
5931 case AARCH64_OPND_Vd
:
5932 case AARCH64_OPND_Vn
:
5933 case AARCH64_OPND_Vm
:
5934 case AARCH64_OPND_VdD1
:
5935 case AARCH64_OPND_VnD1
:
5936 operand
->reg
.regno
= default_value
;
5939 case AARCH64_OPND_Ed
:
5940 case AARCH64_OPND_En
:
5941 case AARCH64_OPND_Em
:
5942 case AARCH64_OPND_Em16
:
5943 case AARCH64_OPND_SM3_IMM2
:
5944 operand
->reglane
.regno
= default_value
;
5947 case AARCH64_OPND_IDX
:
5948 case AARCH64_OPND_BIT_NUM
:
5949 case AARCH64_OPND_IMMR
:
5950 case AARCH64_OPND_IMMS
:
5951 case AARCH64_OPND_SHLL_IMM
:
5952 case AARCH64_OPND_IMM_VLSL
:
5953 case AARCH64_OPND_IMM_VLSR
:
5954 case AARCH64_OPND_CCMP_IMM
:
5955 case AARCH64_OPND_FBITS
:
5956 case AARCH64_OPND_UIMM4
:
5957 case AARCH64_OPND_UIMM3_OP1
:
5958 case AARCH64_OPND_UIMM3_OP2
:
5959 case AARCH64_OPND_IMM
:
5960 case AARCH64_OPND_IMM_2
:
5961 case AARCH64_OPND_WIDTH
:
5962 case AARCH64_OPND_UIMM7
:
5963 case AARCH64_OPND_NZCV
:
5964 case AARCH64_OPND_SVE_PATTERN
:
5965 case AARCH64_OPND_SVE_PRFOP
:
5966 operand
->imm
.value
= default_value
;
5969 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5970 operand
->imm
.value
= default_value
;
5971 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5972 operand
->shifter
.amount
= 1;
5975 case AARCH64_OPND_EXCEPTION
:
5976 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5979 case AARCH64_OPND_BARRIER_ISB
:
5980 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5983 case AARCH64_OPND_BTI_TARGET
:
5984 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5992 /* Process the relocation type for move wide instructions.
5993 Return TRUE on success; otherwise return FALSE. */
5996 process_movw_reloc_info (void)
6001 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6003 if (inst
.base
.opcode
->op
== OP_MOVK
)
6004 switch (inst
.reloc
.type
)
6006 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6007 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6008 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6009 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6010 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6011 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6012 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6013 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6014 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6015 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6016 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6018 (_("the specified relocation type is not allowed for MOVK"));
6024 switch (inst
.reloc
.type
)
6026 case BFD_RELOC_AARCH64_MOVW_G0
:
6027 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6028 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6029 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6030 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6031 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6032 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6033 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6034 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6035 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6036 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6037 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6038 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6041 case BFD_RELOC_AARCH64_MOVW_G1
:
6042 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6043 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6044 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6045 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6046 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6047 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6048 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6049 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6050 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6051 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6052 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6053 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6056 case BFD_RELOC_AARCH64_MOVW_G2
:
6057 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6058 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6059 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6060 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6061 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6062 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6065 set_fatal_syntax_error
6066 (_("the specified relocation type is not allowed for 32-bit "
6072 case BFD_RELOC_AARCH64_MOVW_G3
:
6073 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6076 set_fatal_syntax_error
6077 (_("the specified relocation type is not allowed for 32-bit "
6084 /* More cases should be added when more MOVW-related relocation types
6085 are supported in GAS. */
6086 gas_assert (aarch64_gas_internal_fixup_p ());
6087 /* The shift amount should have already been set by the parser. */
6090 inst
.base
.operands
[1].shifter
.amount
= shift
;
6094 /* A primitive log calculator. */
6096 static inline unsigned int
6097 get_logsz (unsigned int size
)
6099 const unsigned char ls
[16] =
6100 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6106 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6107 return ls
[size
- 1];
6110 /* Determine and return the real reloc type code for an instruction
6111 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6113 static inline bfd_reloc_code_real_type
6114 ldst_lo12_determine_real_reloc_type (void)
6116 unsigned logsz
, max_logsz
;
6117 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6118 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6120 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6122 BFD_RELOC_AARCH64_LDST8_LO12
,
6123 BFD_RELOC_AARCH64_LDST16_LO12
,
6124 BFD_RELOC_AARCH64_LDST32_LO12
,
6125 BFD_RELOC_AARCH64_LDST64_LO12
,
6126 BFD_RELOC_AARCH64_LDST128_LO12
6129 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6130 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6131 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6132 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6133 BFD_RELOC_AARCH64_NONE
6136 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6137 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6138 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6139 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6140 BFD_RELOC_AARCH64_NONE
6143 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6144 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6145 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6146 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6147 BFD_RELOC_AARCH64_NONE
6150 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6151 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6152 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6153 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6154 BFD_RELOC_AARCH64_NONE
6158 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6159 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6161 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6163 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6165 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6166 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6168 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6170 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6172 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6174 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6176 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6177 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6178 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6179 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6184 if (logsz
> max_logsz
)
6186 /* SEE PR 27904 for an example of this. */
6187 set_fatal_syntax_error
6188 (_("relocation qualifier does not match instruction size"));
6189 return BFD_RELOC_AARCH64_NONE
;
6192 /* In reloc.c, these pseudo relocation types should be defined in similar
6193 order as above reloc_ldst_lo12 array. Because the array index calculation
6194 below relies on this. */
6195 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6198 /* Check whether a register list REGINFO is valid. The registers must be
6199 numbered in increasing order (modulo 32), in increments of one or two.
6201 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6204 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6207 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6209 uint32_t i
, nb_regs
, prev_regno
, incr
;
6211 nb_regs
= 1 + (reginfo
& 0x3);
6213 prev_regno
= reginfo
& 0x1f;
6214 incr
= accept_alternate
? 2 : 1;
6216 for (i
= 1; i
< nb_regs
; ++i
)
6218 uint32_t curr_regno
;
6220 curr_regno
= reginfo
& 0x1f;
6221 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6223 prev_regno
= curr_regno
;
6229 /* Generic instruction operand parser. This does no encoding and no
6230 semantic validation; it merely squirrels values away in the inst
6231 structure. Returns TRUE or FALSE depending on whether the
6232 specified grammar matched. */
6235 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6238 char *backtrack_pos
= 0;
6239 const enum aarch64_opnd
*operands
= opcode
->operands
;
6240 aarch64_reg_type imm_reg_type
;
6243 skip_whitespace (str
);
6245 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6246 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6248 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6250 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6253 const reg_entry
*reg
;
6254 int comma_skipped_p
= 0;
6255 aarch64_reg_type rtype
;
6256 struct vector_type_el vectype
;
6257 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6258 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6259 aarch64_reg_type reg_type
;
6261 DEBUG_TRACE ("parse operand %d", i
);
6263 /* Assign the operand code. */
6264 info
->type
= operands
[i
];
6266 if (optional_operand_p (opcode
, i
))
6268 /* Remember where we are in case we need to backtrack. */
6269 gas_assert (!backtrack_pos
);
6270 backtrack_pos
= str
;
6273 /* Expect comma between operands; the backtrack mechanism will take
6274 care of cases of omitted optional operand. */
6275 if (i
> 0 && ! skip_past_char (&str
, ','))
6277 set_syntax_error (_("comma expected between operands"));
6281 comma_skipped_p
= 1;
6283 switch (operands
[i
])
6285 case AARCH64_OPND_Rd
:
6286 case AARCH64_OPND_Rn
:
6287 case AARCH64_OPND_Rm
:
6288 case AARCH64_OPND_Rt
:
6289 case AARCH64_OPND_Rt2
:
6290 case AARCH64_OPND_Rs
:
6291 case AARCH64_OPND_Ra
:
6292 case AARCH64_OPND_Rt_LS64
:
6293 case AARCH64_OPND_Rt_SYS
:
6294 case AARCH64_OPND_PAIRREG
:
6295 case AARCH64_OPND_SVE_Rm
:
6296 po_int_reg_or_fail (REG_TYPE_R_Z
);
6298 /* In LS64 load/store instructions Rt register number must be even
6300 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6302 /* We've already checked if this is valid register.
6303 This will check if register number (Rt) is not undefined for LS64
6305 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6306 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6308 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6314 case AARCH64_OPND_Rd_SP
:
6315 case AARCH64_OPND_Rn_SP
:
6316 case AARCH64_OPND_Rt_SP
:
6317 case AARCH64_OPND_SVE_Rn_SP
:
6318 case AARCH64_OPND_Rm_SP
:
6319 po_int_reg_or_fail (REG_TYPE_R_SP
);
6322 case AARCH64_OPND_Rm_EXT
:
6323 case AARCH64_OPND_Rm_SFT
:
6324 po_misc_or_fail (parse_shifter_operand
6325 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6327 : SHIFTED_LOGIC_IMM
)));
6328 if (!info
->shifter
.operator_present
)
6330 /* Default to LSL if not present. Libopcodes prefers shifter
6331 kind to be explicit. */
6332 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6333 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6334 /* For Rm_EXT, libopcodes will carry out further check on whether
6335 or not stack pointer is used in the instruction (Recall that
6336 "the extend operator is not optional unless at least one of
6337 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6341 case AARCH64_OPND_Fd
:
6342 case AARCH64_OPND_Fn
:
6343 case AARCH64_OPND_Fm
:
6344 case AARCH64_OPND_Fa
:
6345 case AARCH64_OPND_Ft
:
6346 case AARCH64_OPND_Ft2
:
6347 case AARCH64_OPND_Sd
:
6348 case AARCH64_OPND_Sn
:
6349 case AARCH64_OPND_Sm
:
6350 case AARCH64_OPND_SVE_VZn
:
6351 case AARCH64_OPND_SVE_Vd
:
6352 case AARCH64_OPND_SVE_Vm
:
6353 case AARCH64_OPND_SVE_Vn
:
6354 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6355 if (val
== PARSE_FAIL
)
6357 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6360 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6362 info
->reg
.regno
= val
;
6363 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6366 case AARCH64_OPND_SVE_Pd
:
6367 case AARCH64_OPND_SVE_Pg3
:
6368 case AARCH64_OPND_SVE_Pg4_5
:
6369 case AARCH64_OPND_SVE_Pg4_10
:
6370 case AARCH64_OPND_SVE_Pg4_16
:
6371 case AARCH64_OPND_SVE_Pm
:
6372 case AARCH64_OPND_SVE_Pn
:
6373 case AARCH64_OPND_SVE_Pt
:
6374 case AARCH64_OPND_SME_Pm
:
6375 reg_type
= REG_TYPE_PN
;
6378 case AARCH64_OPND_SVE_Za_5
:
6379 case AARCH64_OPND_SVE_Za_16
:
6380 case AARCH64_OPND_SVE_Zd
:
6381 case AARCH64_OPND_SVE_Zm_5
:
6382 case AARCH64_OPND_SVE_Zm_16
:
6383 case AARCH64_OPND_SVE_Zn
:
6384 case AARCH64_OPND_SVE_Zt
:
6385 reg_type
= REG_TYPE_ZN
;
6388 case AARCH64_OPND_Va
:
6389 case AARCH64_OPND_Vd
:
6390 case AARCH64_OPND_Vn
:
6391 case AARCH64_OPND_Vm
:
6392 reg_type
= REG_TYPE_VN
;
6394 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6395 if (val
== PARSE_FAIL
)
6397 first_error (_(get_reg_expected_msg (reg_type
)));
6400 if (vectype
.defined
& NTA_HASINDEX
)
6403 info
->reg
.regno
= val
;
6404 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6405 && vectype
.type
== NT_invtype
)
6406 /* Unqualified Pn and Zn registers are allowed in certain
6407 contexts. Rely on F_STRICT qualifier checking to catch
6409 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6412 info
->qualifier
= vectype_to_qualifier (&vectype
);
6413 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6418 case AARCH64_OPND_VdD1
:
6419 case AARCH64_OPND_VnD1
:
6420 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6421 if (val
== PARSE_FAIL
)
6423 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6426 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6428 set_fatal_syntax_error
6429 (_("the top half of a 128-bit FP/SIMD register is expected"));
6432 info
->reg
.regno
= val
;
6433 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6434 here; it is correct for the purpose of encoding/decoding since
6435 only the register number is explicitly encoded in the related
6436 instructions, although this appears a bit hacky. */
6437 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6440 case AARCH64_OPND_SVE_Zm3_INDEX
:
6441 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6442 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6443 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6444 case AARCH64_OPND_SVE_Zm4_INDEX
:
6445 case AARCH64_OPND_SVE_Zn_INDEX
:
6446 reg_type
= REG_TYPE_ZN
;
6447 goto vector_reg_index
;
6449 case AARCH64_OPND_Ed
:
6450 case AARCH64_OPND_En
:
6451 case AARCH64_OPND_Em
:
6452 case AARCH64_OPND_Em16
:
6453 case AARCH64_OPND_SM3_IMM2
:
6454 reg_type
= REG_TYPE_VN
;
6456 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6457 if (val
== PARSE_FAIL
)
6459 first_error (_(get_reg_expected_msg (reg_type
)));
6462 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6465 info
->reglane
.regno
= val
;
6466 info
->reglane
.index
= vectype
.index
;
6467 info
->qualifier
= vectype_to_qualifier (&vectype
);
6468 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6472 case AARCH64_OPND_SVE_ZnxN
:
6473 case AARCH64_OPND_SVE_ZtxN
:
6474 reg_type
= REG_TYPE_ZN
;
6475 goto vector_reg_list
;
6477 case AARCH64_OPND_LVn
:
6478 case AARCH64_OPND_LVt
:
6479 case AARCH64_OPND_LVt_AL
:
6480 case AARCH64_OPND_LEt
:
6481 reg_type
= REG_TYPE_VN
;
6483 if (reg_type
== REG_TYPE_ZN
6484 && get_opcode_dependent_value (opcode
) == 1
6487 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6488 if (val
== PARSE_FAIL
)
6490 first_error (_(get_reg_expected_msg (reg_type
)));
6493 info
->reglist
.first_regno
= val
;
6494 info
->reglist
.num_regs
= 1;
6498 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6499 if (val
== PARSE_FAIL
)
6502 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6504 set_fatal_syntax_error (_("invalid register list"));
6508 if (vectype
.width
!= 0 && *str
!= ',')
6510 set_fatal_syntax_error
6511 (_("expected element type rather than vector type"));
6515 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6516 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6518 if (operands
[i
] == AARCH64_OPND_LEt
)
6520 if (!(vectype
.defined
& NTA_HASINDEX
))
6522 info
->reglist
.has_index
= 1;
6523 info
->reglist
.index
= vectype
.index
;
6527 if (vectype
.defined
& NTA_HASINDEX
)
6529 if (!(vectype
.defined
& NTA_HASTYPE
))
6531 if (reg_type
== REG_TYPE_ZN
)
6532 set_fatal_syntax_error (_("missing type suffix"));
6536 info
->qualifier
= vectype_to_qualifier (&vectype
);
6537 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6541 case AARCH64_OPND_CRn
:
6542 case AARCH64_OPND_CRm
:
6544 char prefix
= *(str
++);
6545 if (prefix
!= 'c' && prefix
!= 'C')
6548 po_imm_nc_or_fail ();
6551 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6554 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6555 info
->imm
.value
= val
;
6559 case AARCH64_OPND_SHLL_IMM
:
6560 case AARCH64_OPND_IMM_VLSR
:
6561 po_imm_or_fail (1, 64);
6562 info
->imm
.value
= val
;
6565 case AARCH64_OPND_CCMP_IMM
:
6566 case AARCH64_OPND_SIMM5
:
6567 case AARCH64_OPND_FBITS
:
6568 case AARCH64_OPND_TME_UIMM16
:
6569 case AARCH64_OPND_UIMM4
:
6570 case AARCH64_OPND_UIMM4_ADDG
:
6571 case AARCH64_OPND_UIMM10
:
6572 case AARCH64_OPND_UIMM3_OP1
:
6573 case AARCH64_OPND_UIMM3_OP2
:
6574 case AARCH64_OPND_IMM_VLSL
:
6575 case AARCH64_OPND_IMM
:
6576 case AARCH64_OPND_IMM_2
:
6577 case AARCH64_OPND_WIDTH
:
6578 case AARCH64_OPND_SVE_INV_LIMM
:
6579 case AARCH64_OPND_SVE_LIMM
:
6580 case AARCH64_OPND_SVE_LIMM_MOV
:
6581 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6582 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6583 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6584 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6585 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6586 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6587 case AARCH64_OPND_SVE_SIMM5
:
6588 case AARCH64_OPND_SVE_SIMM5B
:
6589 case AARCH64_OPND_SVE_SIMM6
:
6590 case AARCH64_OPND_SVE_SIMM8
:
6591 case AARCH64_OPND_SVE_UIMM3
:
6592 case AARCH64_OPND_SVE_UIMM7
:
6593 case AARCH64_OPND_SVE_UIMM8
:
6594 case AARCH64_OPND_SVE_UIMM8_53
:
6595 case AARCH64_OPND_IMM_ROT1
:
6596 case AARCH64_OPND_IMM_ROT2
:
6597 case AARCH64_OPND_IMM_ROT3
:
6598 case AARCH64_OPND_SVE_IMM_ROT1
:
6599 case AARCH64_OPND_SVE_IMM_ROT2
:
6600 case AARCH64_OPND_SVE_IMM_ROT3
:
6601 po_imm_nc_or_fail ();
6602 info
->imm
.value
= val
;
6605 case AARCH64_OPND_SVE_AIMM
:
6606 case AARCH64_OPND_SVE_ASIMM
:
6607 po_imm_nc_or_fail ();
6608 info
->imm
.value
= val
;
6609 skip_whitespace (str
);
6610 if (skip_past_comma (&str
))
6611 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6613 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6616 case AARCH64_OPND_SVE_PATTERN
:
6617 po_enum_or_fail (aarch64_sve_pattern_array
);
6618 info
->imm
.value
= val
;
6621 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6622 po_enum_or_fail (aarch64_sve_pattern_array
);
6623 info
->imm
.value
= val
;
6624 if (skip_past_comma (&str
)
6625 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6627 if (!info
->shifter
.operator_present
)
6629 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6630 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6631 info
->shifter
.amount
= 1;
6635 case AARCH64_OPND_SVE_PRFOP
:
6636 po_enum_or_fail (aarch64_sve_prfop_array
);
6637 info
->imm
.value
= val
;
6640 case AARCH64_OPND_UIMM7
:
6641 po_imm_or_fail (0, 127);
6642 info
->imm
.value
= val
;
6645 case AARCH64_OPND_IDX
:
6646 case AARCH64_OPND_MASK
:
6647 case AARCH64_OPND_BIT_NUM
:
6648 case AARCH64_OPND_IMMR
:
6649 case AARCH64_OPND_IMMS
:
6650 po_imm_or_fail (0, 63);
6651 info
->imm
.value
= val
;
6654 case AARCH64_OPND_IMM0
:
6655 po_imm_nc_or_fail ();
6658 set_fatal_syntax_error (_("immediate zero expected"));
6661 info
->imm
.value
= 0;
6664 case AARCH64_OPND_FPIMM0
:
6667 bool res1
= false, res2
= false;
6668 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6669 it is probably not worth the effort to support it. */
6670 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6673 || !(res2
= parse_constant_immediate (&str
, &val
,
6676 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6678 info
->imm
.value
= 0;
6679 info
->imm
.is_fp
= 1;
6682 set_fatal_syntax_error (_("immediate zero expected"));
6686 case AARCH64_OPND_IMM_MOV
:
6689 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6690 reg_name_p (str
, REG_TYPE_VN
))
6693 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6694 GE_OPT_PREFIX
, REJECT_ABSENT
,
6695 NORMAL_RESOLUTION
));
6696 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6697 later. fix_mov_imm_insn will try to determine a machine
6698 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6699 message if the immediate cannot be moved by a single
6701 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6702 inst
.base
.operands
[i
].skip
= 1;
6706 case AARCH64_OPND_SIMD_IMM
:
6707 case AARCH64_OPND_SIMD_IMM_SFT
:
6708 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6710 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6712 /* need_libopcodes_p */ 1,
6715 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6716 shift, we don't check it here; we leave the checking to
6717 the libopcodes (operand_general_constraint_met_p). By
6718 doing this, we achieve better diagnostics. */
6719 if (skip_past_comma (&str
)
6720 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6722 if (!info
->shifter
.operator_present
6723 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6725 /* Default to LSL if not present. Libopcodes prefers shifter
6726 kind to be explicit. */
6727 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6728 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6732 case AARCH64_OPND_FPIMM
:
6733 case AARCH64_OPND_SIMD_FPIMM
:
6734 case AARCH64_OPND_SVE_FPIMM8
:
6739 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6740 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6741 || !aarch64_imm_float_p (qfloat
))
6744 set_fatal_syntax_error (_("invalid floating-point"
6748 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6749 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6753 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6754 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6755 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6760 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6761 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6764 set_fatal_syntax_error (_("invalid floating-point"
6768 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6769 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6773 case AARCH64_OPND_LIMM
:
6774 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6775 SHIFTED_LOGIC_IMM
));
6776 if (info
->shifter
.operator_present
)
6778 set_fatal_syntax_error
6779 (_("shift not allowed for bitmask immediate"));
6782 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6784 /* need_libopcodes_p */ 1,
6788 case AARCH64_OPND_AIMM
:
6789 if (opcode
->op
== OP_ADD
)
6790 /* ADD may have relocation types. */
6791 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6792 SHIFTED_ARITH_IMM
));
6794 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6795 SHIFTED_ARITH_IMM
));
6796 switch (inst
.reloc
.type
)
6798 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6799 info
->shifter
.amount
= 12;
6801 case BFD_RELOC_UNUSED
:
6802 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6803 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6804 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6805 inst
.reloc
.pc_rel
= 0;
6810 info
->imm
.value
= 0;
6811 if (!info
->shifter
.operator_present
)
6813 /* Default to LSL if not present. Libopcodes prefers shifter
6814 kind to be explicit. */
6815 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6816 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6820 case AARCH64_OPND_HALF
:
6822 /* #<imm16> or relocation. */
6823 int internal_fixup_p
;
6824 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6825 if (internal_fixup_p
)
6826 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6827 skip_whitespace (str
);
6828 if (skip_past_comma (&str
))
6830 /* {, LSL #<shift>} */
6831 if (! aarch64_gas_internal_fixup_p ())
6833 set_fatal_syntax_error (_("can't mix relocation modifier "
6834 "with explicit shift"));
6837 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6840 inst
.base
.operands
[i
].shifter
.amount
= 0;
6841 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6842 inst
.base
.operands
[i
].imm
.value
= 0;
6843 if (! process_movw_reloc_info ())
6848 case AARCH64_OPND_EXCEPTION
:
6849 case AARCH64_OPND_UNDEFINED
:
6850 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6852 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6854 /* need_libopcodes_p */ 0,
6858 case AARCH64_OPND_NZCV
:
6860 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6864 info
->imm
.value
= nzcv
->value
;
6867 po_imm_or_fail (0, 15);
6868 info
->imm
.value
= val
;
6872 case AARCH64_OPND_COND
:
6873 case AARCH64_OPND_COND1
:
6878 while (ISALPHA (*str
));
6879 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6880 if (info
->cond
== NULL
)
6882 set_syntax_error (_("invalid condition"));
6885 else if (operands
[i
] == AARCH64_OPND_COND1
6886 && (info
->cond
->value
& 0xe) == 0xe)
6888 /* Do not allow AL or NV. */
6889 set_default_error ();
6895 case AARCH64_OPND_ADDR_ADRP
:
6896 po_misc_or_fail (parse_adrp (&str
));
6897 /* Clear the value as operand needs to be relocated. */
6898 info
->imm
.value
= 0;
6901 case AARCH64_OPND_ADDR_PCREL14
:
6902 case AARCH64_OPND_ADDR_PCREL19
:
6903 case AARCH64_OPND_ADDR_PCREL21
:
6904 case AARCH64_OPND_ADDR_PCREL26
:
6905 po_misc_or_fail (parse_address (&str
, info
));
6906 if (!info
->addr
.pcrel
)
6908 set_syntax_error (_("invalid pc-relative address"));
6911 if (inst
.gen_lit_pool
6912 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6914 /* Only permit "=value" in the literal load instructions.
6915 The literal will be generated by programmer_friendly_fixup. */
6916 set_syntax_error (_("invalid use of \"=immediate\""));
6919 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6921 set_syntax_error (_("unrecognized relocation suffix"));
6924 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6926 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6927 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6931 info
->imm
.value
= 0;
6932 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6933 switch (opcode
->iclass
)
6937 /* e.g. CBZ or B.COND */
6938 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6939 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6943 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6944 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6948 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6950 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6951 : BFD_RELOC_AARCH64_JUMP26
;
6954 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6955 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6958 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6959 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6965 inst
.reloc
.pc_rel
= 1;
6969 case AARCH64_OPND_ADDR_SIMPLE
:
6970 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6972 /* [<Xn|SP>{, #<simm>}] */
6974 /* First use the normal address-parsing routines, to get
6975 the usual syntax errors. */
6976 po_misc_or_fail (parse_address (&str
, info
));
6977 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6978 || !info
->addr
.preind
|| info
->addr
.postind
6979 || info
->addr
.writeback
)
6981 set_syntax_error (_("invalid addressing mode"));
6985 /* Then retry, matching the specific syntax of these addresses. */
6987 po_char_or_fail ('[');
6988 po_reg_or_fail (REG_TYPE_R64_SP
);
6989 /* Accept optional ", #0". */
6990 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6991 && skip_past_char (&str
, ','))
6993 skip_past_char (&str
, '#');
6994 if (! skip_past_char (&str
, '0'))
6996 set_fatal_syntax_error
6997 (_("the optional immediate offset can only be 0"));
7001 po_char_or_fail (']');
7005 case AARCH64_OPND_ADDR_REGOFF
:
7006 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7007 po_misc_or_fail (parse_address (&str
, info
));
7009 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7010 || !info
->addr
.preind
|| info
->addr
.postind
7011 || info
->addr
.writeback
)
7013 set_syntax_error (_("invalid addressing mode"));
7016 if (!info
->shifter
.operator_present
)
7018 /* Default to LSL if not present. Libopcodes prefers shifter
7019 kind to be explicit. */
7020 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7021 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7023 /* Qualifier to be deduced by libopcodes. */
7026 case AARCH64_OPND_ADDR_SIMM7
:
7027 po_misc_or_fail (parse_address (&str
, info
));
7028 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7029 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7031 set_syntax_error (_("invalid addressing mode"));
7034 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7036 set_syntax_error (_("relocation not allowed"));
7039 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7041 /* need_libopcodes_p */ 1,
7045 case AARCH64_OPND_ADDR_SIMM9
:
7046 case AARCH64_OPND_ADDR_SIMM9_2
:
7047 case AARCH64_OPND_ADDR_SIMM11
:
7048 case AARCH64_OPND_ADDR_SIMM13
:
7049 po_misc_or_fail (parse_address (&str
, info
));
7050 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7051 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7052 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7053 && info
->addr
.writeback
))
7055 set_syntax_error (_("invalid addressing mode"));
7058 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7060 set_syntax_error (_("relocation not allowed"));
7063 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7065 /* need_libopcodes_p */ 1,
7069 case AARCH64_OPND_ADDR_SIMM10
:
7070 case AARCH64_OPND_ADDR_OFFSET
:
7071 po_misc_or_fail (parse_address (&str
, info
));
7072 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7073 || !info
->addr
.preind
|| info
->addr
.postind
)
7075 set_syntax_error (_("invalid addressing mode"));
7078 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7080 set_syntax_error (_("relocation not allowed"));
7083 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7085 /* need_libopcodes_p */ 1,
7089 case AARCH64_OPND_ADDR_UIMM12
:
7090 po_misc_or_fail (parse_address (&str
, info
));
7091 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7092 || !info
->addr
.preind
|| info
->addr
.writeback
)
7094 set_syntax_error (_("invalid addressing mode"));
7097 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7098 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7099 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7101 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7103 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7105 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7107 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7108 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7109 /* Leave qualifier to be determined by libopcodes. */
7112 case AARCH64_OPND_SIMD_ADDR_POST
:
7113 /* [<Xn|SP>], <Xm|#<amount>> */
7114 po_misc_or_fail (parse_address (&str
, info
));
7115 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7117 set_syntax_error (_("invalid addressing mode"));
7120 if (!info
->addr
.offset
.is_reg
)
7122 if (inst
.reloc
.exp
.X_op
== O_constant
)
7123 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7126 set_fatal_syntax_error
7127 (_("writeback value must be an immediate constant"));
7134 case AARCH64_OPND_SME_SM_ZA
:
7136 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7138 set_syntax_error (_("unknown or missing PSTATE field name"));
7141 info
->reg
.regno
= val
;
7144 case AARCH64_OPND_SME_PnT_Wm_imm
:
7145 /* <Pn>.<T>[<Wm>, #<imm>] */
7149 val
= parse_sme_pred_reg_with_index (&str
,
7153 if (val
== PARSE_FAIL
)
7156 info
->za_tile_vector
.regno
= val
;
7157 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7158 info
->za_tile_vector
.index
.imm
= imm
;
7159 info
->qualifier
= qualifier
;
7163 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7164 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7165 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7166 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7167 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7168 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7169 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7170 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7171 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7172 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7173 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7174 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7175 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7176 /* [X<n>{, #imm, MUL VL}]
7178 but recognizing SVE registers. */
7179 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7180 &offset_qualifier
));
7181 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7183 set_syntax_error (_("invalid addressing mode"));
7187 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7188 || !info
->addr
.preind
|| info
->addr
.writeback
)
7190 set_syntax_error (_("invalid addressing mode"));
7193 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7194 || inst
.reloc
.exp
.X_op
!= O_constant
)
7196 /* Make sure this has priority over
7197 "invalid addressing mode". */
7198 set_fatal_syntax_error (_("constant offset required"));
7201 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7204 case AARCH64_OPND_SVE_ADDR_R
:
7205 /* [<Xn|SP>{, <R><m>}]
7206 but recognizing SVE registers. */
7207 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7208 &offset_qualifier
));
7209 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7211 offset_qualifier
= AARCH64_OPND_QLF_X
;
7212 info
->addr
.offset
.is_reg
= 1;
7213 info
->addr
.offset
.regno
= 31;
7215 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7216 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7218 set_syntax_error (_("invalid addressing mode"));
7223 case AARCH64_OPND_SVE_ADDR_RR
:
7224 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7225 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7226 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7227 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7228 case AARCH64_OPND_SVE_ADDR_RX
:
7229 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7230 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7231 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7232 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7233 but recognizing SVE registers. */
7234 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7235 &offset_qualifier
));
7236 if (base_qualifier
!= AARCH64_OPND_QLF_X
7237 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7239 set_syntax_error (_("invalid addressing mode"));
7244 case AARCH64_OPND_SVE_ADDR_RZ
:
7245 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7246 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7247 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7248 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7249 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7250 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7251 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7252 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7253 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7254 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7255 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7256 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7257 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7258 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7259 &offset_qualifier
));
7260 if (base_qualifier
!= AARCH64_OPND_QLF_X
7261 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7262 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7264 set_syntax_error (_("invalid addressing mode"));
7267 info
->qualifier
= offset_qualifier
;
7270 case AARCH64_OPND_SVE_ADDR_ZX
:
7271 /* [Zn.<T>{, <Xm>}]. */
7272 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7273 &offset_qualifier
));
7275 base_qualifier either S_S or S_D
7276 offset_qualifier must be X
7278 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7279 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7280 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7282 set_syntax_error (_("invalid addressing mode"));
7285 info
->qualifier
= base_qualifier
;
7286 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7287 || !info
->addr
.preind
|| info
->addr
.writeback
7288 || info
->shifter
.operator_present
!= 0)
7290 set_syntax_error (_("invalid addressing mode"));
7293 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7297 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7298 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7299 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7300 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7301 /* [Z<n>.<T>{, #imm}] */
7302 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7303 &offset_qualifier
));
7304 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7305 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7307 set_syntax_error (_("invalid addressing mode"));
7310 info
->qualifier
= base_qualifier
;
7313 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7314 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7315 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7316 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7317 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7321 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7323 here since we get better error messages by leaving it to
7324 the qualifier checking routines. */
7325 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7326 &offset_qualifier
));
7327 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7328 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7329 || offset_qualifier
!= base_qualifier
)
7331 set_syntax_error (_("invalid addressing mode"));
7334 info
->qualifier
= base_qualifier
;
7337 case AARCH64_OPND_SYSREG
:
7339 uint32_t sysreg_flags
;
7340 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7341 &sysreg_flags
)) == PARSE_FAIL
)
7343 set_syntax_error (_("unknown or missing system register name"));
7346 inst
.base
.operands
[i
].sysreg
.value
= val
;
7347 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7351 case AARCH64_OPND_PSTATEFIELD
:
7353 uint32_t sysreg_flags
;
7354 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7355 &sysreg_flags
)) == PARSE_FAIL
)
7357 set_syntax_error (_("unknown or missing PSTATE field name"));
7360 inst
.base
.operands
[i
].pstatefield
= val
;
7361 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7365 case AARCH64_OPND_SYSREG_IC
:
7366 inst
.base
.operands
[i
].sysins_op
=
7367 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7370 case AARCH64_OPND_SYSREG_DC
:
7371 inst
.base
.operands
[i
].sysins_op
=
7372 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7375 case AARCH64_OPND_SYSREG_AT
:
7376 inst
.base
.operands
[i
].sysins_op
=
7377 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7380 case AARCH64_OPND_SYSREG_SR
:
7381 inst
.base
.operands
[i
].sysins_op
=
7382 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7385 case AARCH64_OPND_SYSREG_TLBI
:
7386 inst
.base
.operands
[i
].sysins_op
=
7387 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7389 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7391 set_fatal_syntax_error ( _("unknown or missing operation name"));
7396 case AARCH64_OPND_BARRIER
:
7397 case AARCH64_OPND_BARRIER_ISB
:
7398 val
= parse_barrier (&str
);
7399 if (val
!= PARSE_FAIL
7400 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7402 /* ISB only accepts options name 'sy'. */
7404 (_("the specified option is not accepted in ISB"));
7405 /* Turn off backtrack as this optional operand is present. */
7409 if (val
!= PARSE_FAIL
7410 && operands
[i
] == AARCH64_OPND_BARRIER
)
7412 /* Regular barriers accept options CRm (C0-C15).
7413 DSB nXS barrier variant accepts values > 15. */
7414 if (val
< 0 || val
> 15)
7416 set_syntax_error (_("the specified option is not accepted in DSB"));
7420 /* This is an extension to accept a 0..15 immediate. */
7421 if (val
== PARSE_FAIL
)
7422 po_imm_or_fail (0, 15);
7423 info
->barrier
= aarch64_barrier_options
+ val
;
7426 case AARCH64_OPND_BARRIER_DSB_NXS
:
7427 val
= parse_barrier (&str
);
7428 if (val
!= PARSE_FAIL
)
7430 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7431 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7433 set_syntax_error (_("the specified option is not accepted in DSB"));
7434 /* Turn off backtrack as this optional operand is present. */
7441 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7442 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7443 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7445 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7447 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7451 /* Option index is encoded as 2-bit value in val<3:2>. */
7452 val
= (val
>> 2) - 4;
7453 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7456 case AARCH64_OPND_PRFOP
:
7457 val
= parse_pldop (&str
);
7458 /* This is an extension to accept a 0..31 immediate. */
7459 if (val
== PARSE_FAIL
)
7460 po_imm_or_fail (0, 31);
7461 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7464 case AARCH64_OPND_BARRIER_PSB
:
7465 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7466 if (val
== PARSE_FAIL
)
7470 case AARCH64_OPND_BTI_TARGET
:
7471 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7472 if (val
== PARSE_FAIL
)
7476 case AARCH64_OPND_SME_ZAda_2b
:
7477 case AARCH64_OPND_SME_ZAda_3b
:
7478 val
= parse_sme_zada_operand (&str
, &qualifier
);
7479 if (val
== PARSE_FAIL
)
7481 info
->reg
.regno
= val
;
7482 info
->qualifier
= qualifier
;
7485 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7486 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7487 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7489 enum sme_hv_slice slice_indicator
;
7490 int vector_select_register
;
7493 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7494 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7496 &vector_select_register
,
7500 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7501 &vector_select_register
,
7504 if (val
== PARSE_FAIL
)
7506 info
->za_tile_vector
.regno
= val
;
7507 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7508 info
->za_tile_vector
.index
.imm
= imm
;
7509 info
->za_tile_vector
.v
= slice_indicator
;
7510 info
->qualifier
= qualifier
;
7514 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7515 val
= parse_sme_list_of_64bit_tiles (&str
);
7516 if (val
== PARSE_FAIL
)
7518 info
->imm
.value
= val
;
7521 case AARCH64_OPND_SME_ZA_array
:
7524 val
= parse_sme_za_array (&str
, &imm
);
7525 if (val
== PARSE_FAIL
)
7527 info
->za_tile_vector
.index
.regno
= val
;
7528 info
->za_tile_vector
.index
.imm
= imm
;
7532 case AARCH64_OPND_MOPS_ADDR_Rd
:
7533 case AARCH64_OPND_MOPS_ADDR_Rs
:
7534 po_char_or_fail ('[');
7535 if (!parse_x0_to_x30 (&str
, info
))
7537 po_char_or_fail (']');
7538 po_char_or_fail ('!');
7541 case AARCH64_OPND_MOPS_WB_Rn
:
7542 if (!parse_x0_to_x30 (&str
, info
))
7544 po_char_or_fail ('!');
7548 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7551 /* If we get here, this operand was successfully parsed. */
7552 inst
.base
.operands
[i
].present
= 1;
7556 /* The parse routine should already have set the error, but in case
7557 not, set a default one here. */
7559 set_default_error ();
7561 if (! backtrack_pos
)
7562 goto parse_operands_return
;
7565 /* We reach here because this operand is marked as optional, and
7566 either no operand was supplied or the operand was supplied but it
7567 was syntactically incorrect. In the latter case we report an
7568 error. In the former case we perform a few more checks before
7569 dropping through to the code to insert the default operand. */
7571 char *tmp
= backtrack_pos
;
7572 char endchar
= END_OF_INSN
;
7574 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7576 skip_past_char (&tmp
, ',');
7578 if (*tmp
!= endchar
)
7579 /* The user has supplied an operand in the wrong format. */
7580 goto parse_operands_return
;
7582 /* Make sure there is not a comma before the optional operand.
7583 For example the fifth operand of 'sys' is optional:
7585 sys #0,c0,c0,#0, <--- wrong
7586 sys #0,c0,c0,#0 <--- correct. */
7587 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7589 set_fatal_syntax_error
7590 (_("unexpected comma before the omitted optional operand"));
7591 goto parse_operands_return
;
7595 /* Reaching here means we are dealing with an optional operand that is
7596 omitted from the assembly line. */
7597 gas_assert (optional_operand_p (opcode
, i
));
7599 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7601 /* Try again, skipping the optional operand at backtrack_pos. */
7602 str
= backtrack_pos
;
7605 /* Clear any error record after the omitted optional operand has been
7606 successfully handled. */
7610 /* Check if we have parsed all the operands. */
7611 if (*str
!= '\0' && ! error_p ())
7613 /* Set I to the index of the last present operand; this is
7614 for the purpose of diagnostics. */
7615 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7617 set_fatal_syntax_error
7618 (_("unexpected characters following instruction"));
7621 parse_operands_return
:
7625 DEBUG_TRACE ("parsing FAIL: %s - %s",
7626 operand_mismatch_kind_names
[get_error_kind ()],
7627 get_error_message ());
7628 /* Record the operand error properly; this is useful when there
7629 are multiple instruction templates for a mnemonic name, so that
7630 later on, we can select the error that most closely describes
7632 record_operand_error (opcode
, i
, get_error_kind (),
7633 get_error_message ());
7638 DEBUG_TRACE ("parsing SUCCESS");
7643 /* It does some fix-up to provide some programmer friendly feature while
7644 keeping the libopcodes happy, i.e. libopcodes only accepts
7645 the preferred architectural syntax.
7646 Return FALSE if there is any failure; otherwise return TRUE. */
7649 programmer_friendly_fixup (aarch64_instruction
*instr
)
7651 aarch64_inst
*base
= &instr
->base
;
7652 const aarch64_opcode
*opcode
= base
->opcode
;
7653 enum aarch64_op op
= opcode
->op
;
7654 aarch64_opnd_info
*operands
= base
->operands
;
7656 DEBUG_TRACE ("enter");
7658 switch (opcode
->iclass
)
7661 /* TBNZ Xn|Wn, #uimm6, label
7662 Test and Branch Not Zero: conditionally jumps to label if bit number
7663 uimm6 in register Xn is not zero. The bit number implies the width of
7664 the register, which may be written and should be disassembled as Wn if
7665 uimm is less than 32. */
7666 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7668 if (operands
[1].imm
.value
>= 32)
7670 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7674 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7678 /* LDR Wt, label | =value
7679 As a convenience assemblers will typically permit the notation
7680 "=value" in conjunction with the pc-relative literal load instructions
7681 to automatically place an immediate value or symbolic address in a
7682 nearby literal pool and generate a hidden label which references it.
7683 ISREG has been set to 0 in the case of =value. */
7684 if (instr
->gen_lit_pool
7685 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7687 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7688 if (op
== OP_LDRSW_LIT
)
7690 if (instr
->reloc
.exp
.X_op
!= O_constant
7691 && instr
->reloc
.exp
.X_op
!= O_big
7692 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7694 record_operand_error (opcode
, 1,
7695 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7696 _("constant expression expected"));
7699 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7701 record_operand_error (opcode
, 1,
7702 AARCH64_OPDE_OTHER_ERROR
,
7703 _("literal pool insertion failed"));
7711 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7712 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7713 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7714 A programmer-friendly assembler should accept a destination Xd in
7715 place of Wd, however that is not the preferred form for disassembly.
7717 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7718 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7719 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7720 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7725 /* In the 64-bit form, the final register operand is written as Wm
7726 for all but the (possibly omitted) UXTX/LSL and SXTX
7728 As a programmer-friendly assembler, we accept e.g.
7729 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7730 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7731 int idx
= aarch64_operand_index (opcode
->operands
,
7732 AARCH64_OPND_Rm_EXT
);
7733 gas_assert (idx
== 1 || idx
== 2);
7734 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7735 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7736 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7737 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7738 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7739 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7747 DEBUG_TRACE ("exit with SUCCESS");
7751 /* Check for loads and stores that will cause unpredictable behavior. */
7754 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7756 aarch64_inst
*base
= &instr
->base
;
7757 const aarch64_opcode
*opcode
= base
->opcode
;
7758 const aarch64_opnd_info
*opnds
= base
->operands
;
7759 switch (opcode
->iclass
)
7766 /* Loading/storing the base register is unpredictable if writeback. */
7767 if ((aarch64_get_operand_class (opnds
[0].type
)
7768 == AARCH64_OPND_CLASS_INT_REG
)
7769 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7770 && opnds
[1].addr
.base_regno
!= REG_SP
7771 /* Exempt STG/STZG/ST2G/STZ2G. */
7772 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7773 && opnds
[1].addr
.writeback
)
7774 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7778 case ldstnapair_offs
:
7779 case ldstpair_indexed
:
7780 /* Loading/storing the base register is unpredictable if writeback. */
7781 if ((aarch64_get_operand_class (opnds
[0].type
)
7782 == AARCH64_OPND_CLASS_INT_REG
)
7783 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7784 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7785 && opnds
[2].addr
.base_regno
!= REG_SP
7787 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7788 && opnds
[2].addr
.writeback
)
7789 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7790 /* Load operations must load different registers. */
7791 if ((opcode
->opcode
& (1 << 22))
7792 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7793 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7797 if ((aarch64_get_operand_class (opnds
[0].type
)
7798 == AARCH64_OPND_CLASS_INT_REG
)
7799 && (aarch64_get_operand_class (opnds
[1].type
)
7800 == AARCH64_OPND_CLASS_INT_REG
))
7802 if ((opcode
->opcode
& (1 << 22)))
7804 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7805 if ((opcode
->opcode
& (1 << 21))
7806 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7807 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7811 /* Store-Exclusive is unpredictable if Rt == Rs. */
7812 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7814 (_("unpredictable: identical transfer and status registers"
7817 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7819 if (!(opcode
->opcode
& (1 << 21)))
7820 /* Store-Exclusive is unpredictable if Rn == Rs. */
7822 (_("unpredictable: identical base and status registers"
7825 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7827 (_("unpredictable: "
7828 "identical transfer and status registers"
7832 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7833 if ((opcode
->opcode
& (1 << 21))
7834 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7835 && opnds
[3].reg
.regno
!= REG_SP
)
7836 as_warn (_("unpredictable: identical base and status registers"
7848 force_automatic_sequence_close (void)
7850 struct aarch64_segment_info_type
*tc_seg_info
;
7852 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7853 if (tc_seg_info
->insn_sequence
.instr
)
7855 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7856 _("previous `%s' sequence has not been closed"),
7857 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7858 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7862 /* A wrapper function to interface with libopcodes on encoding and
7863 record the error message if there is any.
7865 Return TRUE on success; otherwise return FALSE. */
7868 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7871 aarch64_operand_error error_info
;
7872 memset (&error_info
, '\0', sizeof (error_info
));
7873 error_info
.kind
= AARCH64_OPDE_NIL
;
7874 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7875 && !error_info
.non_fatal
)
7878 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7879 record_operand_error_info (opcode
, &error_info
);
7880 return error_info
.non_fatal
;
7883 #ifdef DEBUG_AARCH64
7885 dump_opcode_operands (const aarch64_opcode
*opcode
)
7888 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7890 aarch64_verbose ("\t\t opnd%d: %s", i
,
7891 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7892 ? aarch64_get_operand_name (opcode
->operands
[i
])
7893 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7897 #endif /* DEBUG_AARCH64 */
7899 /* This is the guts of the machine-dependent assembler. STR points to a
7900 machine dependent instruction. This function is supposed to emit
7901 the frags/bytes it assembles to. */
7904 md_assemble (char *str
)
7906 templates
*template;
7907 const aarch64_opcode
*opcode
;
7908 struct aarch64_segment_info_type
*tc_seg_info
;
7909 aarch64_inst
*inst_base
;
7910 unsigned saved_cond
;
7912 /* Align the previous label if needed. */
7913 if (last_label_seen
!= NULL
)
7915 symbol_set_frag (last_label_seen
, frag_now
);
7916 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7917 S_SET_SEGMENT (last_label_seen
, now_seg
);
7920 /* Update the current insn_sequence from the segment. */
7921 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7922 insn_sequence
= &tc_seg_info
->insn_sequence
;
7923 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7925 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7927 DEBUG_TRACE ("\n\n");
7928 DEBUG_TRACE ("==============================");
7929 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7931 /* Scan up to the end of the mnemonic, which must end in whitespace,
7932 '.', or end of string. */
7935 for (; is_part_of_name (*p
); p
++)
7936 if (*p
== '.' && !dot
)
7941 as_bad (_("unknown mnemonic -- `%s'"), str
);
7945 if (!dot
&& create_register_alias (str
, p
))
7948 template = opcode_lookup (str
, dot
, p
);
7951 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7956 skip_whitespace (p
);
7959 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7960 get_mnemonic_name (str
), str
);
7964 init_operand_error_report ();
7966 /* Sections are assumed to start aligned. In executable section, there is no
7967 MAP_DATA symbol pending. So we only align the address during
7968 MAP_DATA --> MAP_INSN transition.
7969 For other sections, this is not guaranteed. */
7970 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7971 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7972 frag_align_code (2, 0);
7974 saved_cond
= inst
.cond
;
7975 reset_aarch64_instruction (&inst
);
7976 inst
.cond
= saved_cond
;
7978 /* Iterate through all opcode entries with the same mnemonic name. */
7981 opcode
= template->opcode
;
7983 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7984 #ifdef DEBUG_AARCH64
7986 dump_opcode_operands (opcode
);
7987 #endif /* DEBUG_AARCH64 */
7989 mapping_state (MAP_INSN
);
7991 inst_base
= &inst
.base
;
7992 inst_base
->opcode
= opcode
;
7994 /* Truly conditionally executed instructions, e.g. b.cond. */
7995 if (opcode
->flags
& F_COND
)
7997 gas_assert (inst
.cond
!= COND_ALWAYS
);
7998 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7999 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8001 else if (inst
.cond
!= COND_ALWAYS
)
8003 /* It shouldn't arrive here, where the assembly looks like a
8004 conditional instruction but the found opcode is unconditional. */
8009 if (parse_operands (p
, opcode
)
8010 && programmer_friendly_fixup (&inst
)
8011 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8013 /* Check that this instruction is supported for this CPU. */
8014 if (!opcode
->avariant
8015 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8017 as_bad (_("selected processor does not support `%s'"), str
);
8021 warn_unpredictable_ldst (&inst
, str
);
8023 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8024 || !inst
.reloc
.need_libopcodes_p
)
8028 /* If there is relocation generated for the instruction,
8029 store the instruction information for the future fix-up. */
8030 struct aarch64_inst
*copy
;
8031 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8032 copy
= XNEW (struct aarch64_inst
);
8033 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8037 /* Issue non-fatal messages if any. */
8038 output_operand_error_report (str
, true);
8042 template = template->next
;
8043 if (template != NULL
)
8045 reset_aarch64_instruction (&inst
);
8046 inst
.cond
= saved_cond
;
8049 while (template != NULL
);
8051 /* Issue the error messages if any. */
8052 output_operand_error_report (str
, false);
8055 /* Various frobbings of labels and their addresses. */
8058 aarch64_start_line_hook (void)
8060 last_label_seen
= NULL
;
8064 aarch64_frob_label (symbolS
* sym
)
8066 last_label_seen
= sym
;
8068 dwarf2_emit_label (sym
);
8072 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8074 /* Check to see if we have a block to close. */
8075 force_automatic_sequence_close ();
8079 aarch64_data_in_code (void)
8081 if (startswith (input_line_pointer
+ 1, "data:"))
8083 *input_line_pointer
= '/';
8084 input_line_pointer
+= 5;
8085 *input_line_pointer
= 0;
8093 aarch64_canonicalize_symbol_name (char *name
)
8097 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8098 *(name
+ len
- 5) = 0;
8103 /* Table of all register names defined by default. The user can
8104 define additional names with .req. Note that all register names
8105 should appear in both upper and lowercase variants. Some registers
8106 also have mixed-case names. */
8108 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8109 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8110 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8111 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8112 #define REGSET16(p,t) \
8113 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8114 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8115 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8116 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8117 #define REGSET16S(p,s,t) \
8118 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8119 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8120 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8121 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8122 #define REGSET31(p,t) \
8124 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8125 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8126 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8127 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8128 #define REGSET(p,t) \
8129 REGSET31(p,t), REGNUM(p,31,t)
8131 /* These go into aarch64_reg_hsh hash-table. */
8132 static const reg_entry reg_names
[] = {
8133 /* Integer registers. */
8134 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8135 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8137 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8138 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8139 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8140 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8141 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8142 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8144 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8145 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8147 /* Floating-point single precision registers. */
8148 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8150 /* Floating-point double precision registers. */
8151 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8153 /* Floating-point half precision registers. */
8154 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8156 /* Floating-point byte precision registers. */
8157 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8159 /* Floating-point quad precision registers. */
8160 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8162 /* FP/SIMD registers. */
8163 REGSET (v
, VN
), REGSET (V
, VN
),
8165 /* SVE vector registers. */
8166 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8168 /* SVE predicate registers. */
8169 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8171 /* SME ZA tile registers. */
8172 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8174 /* SME ZA tile registers (horizontal slice). */
8175 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8177 /* SME ZA tile registers (vertical slice). */
8178 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8196 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8197 static const asm_nzcv nzcv_names
[] = {
8198 {"nzcv", B (n
, z
, c
, v
)},
8199 {"nzcV", B (n
, z
, c
, V
)},
8200 {"nzCv", B (n
, z
, C
, v
)},
8201 {"nzCV", B (n
, z
, C
, V
)},
8202 {"nZcv", B (n
, Z
, c
, v
)},
8203 {"nZcV", B (n
, Z
, c
, V
)},
8204 {"nZCv", B (n
, Z
, C
, v
)},
8205 {"nZCV", B (n
, Z
, C
, V
)},
8206 {"Nzcv", B (N
, z
, c
, v
)},
8207 {"NzcV", B (N
, z
, c
, V
)},
8208 {"NzCv", B (N
, z
, C
, v
)},
8209 {"NzCV", B (N
, z
, C
, V
)},
8210 {"NZcv", B (N
, Z
, c
, v
)},
8211 {"NZcV", B (N
, Z
, c
, V
)},
8212 {"NZCv", B (N
, Z
, C
, v
)},
8213 {"NZCV", B (N
, Z
, C
, V
)}
8226 /* MD interface: bits in the object file. */
8228 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8229 for use in the a.out file, and stores them in the array pointed to by buf.
8230 This knows about the endian-ness of the target machine and does
8231 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8232 2 (short) and 4 (long) Floating numbers are put out as a series of
8233 LITTLENUMS (shorts, here at least). */
8236 md_number_to_chars (char *buf
, valueT val
, int n
)
8238 if (target_big_endian
)
8239 number_to_chars_bigendian (buf
, val
, n
);
8241 number_to_chars_littleendian (buf
, val
, n
);
8244 /* MD interface: Sections. */
8246 /* Estimate the size of a frag before relaxing. Assume everything fits in
8250 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8256 /* Round up a section size to the appropriate boundary. */
8259 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8264 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8265 of an rs_align_code fragment.
8267 Here we fill the frag with the appropriate info for padding the
8268 output stream. The resulting frag will consist of a fixed (fr_fix)
8269 and of a repeating (fr_var) part.
8271 The fixed content is always emitted before the repeating content and
8272 these two parts are used as follows in constructing the output:
8273 - the fixed part will be used to align to a valid instruction word
8274 boundary, in case that we start at a misaligned address; as no
8275 executable instruction can live at the misaligned location, we
8276 simply fill with zeros;
8277 - the variable part will be used to cover the remaining padding and
8278 we fill using the AArch64 NOP instruction.
8280 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8281 enough storage space for up to 3 bytes for padding the back to a valid
8282 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8285 aarch64_handle_align (fragS
* fragP
)
8287 /* NOP = d503201f */
8288 /* AArch64 instructions are always little-endian. */
8289 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8291 int bytes
, fix
, noop_size
;
8294 if (fragP
->fr_type
!= rs_align_code
)
8297 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8298 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8301 gas_assert (fragP
->tc_frag_data
.recorded
);
8304 noop_size
= sizeof (aarch64_noop
);
8306 fix
= bytes
& (noop_size
- 1);
8310 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8314 fragP
->fr_fix
+= fix
;
8318 memcpy (p
, aarch64_noop
, noop_size
);
8319 fragP
->fr_var
= noop_size
;
8322 /* Perform target specific initialisation of a frag.
8323 Note - despite the name this initialisation is not done when the frag
8324 is created, but only when its type is assigned. A frag can be created
8325 and used a long time before its type is set, so beware of assuming that
8326 this initialisation is performed first. */
8330 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8331 int max_chars ATTRIBUTE_UNUSED
)
8335 #else /* OBJ_ELF is defined. */
8337 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8339 /* Record a mapping symbol for alignment frags. We will delete this
8340 later if the alignment ends up empty. */
8341 if (!fragP
->tc_frag_data
.recorded
)
8342 fragP
->tc_frag_data
.recorded
= 1;
8344 /* PR 21809: Do not set a mapping state for debug sections
8345 - it just confuses other tools. */
8346 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8349 switch (fragP
->fr_type
)
8353 mapping_state_2 (MAP_DATA
, max_chars
);
8356 /* PR 20364: We can get alignment frags in code sections,
8357 so do not just assume that we should use the MAP_DATA state. */
8358 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8361 mapping_state_2 (MAP_INSN
, max_chars
);
8368 /* Initialize the DWARF-2 unwind information for this procedure. */
8371 tc_aarch64_frame_initial_instructions (void)
8373 cfi_add_CFA_def_cfa (REG_SP
, 0);
8375 #endif /* OBJ_ELF */
8377 /* Convert REGNAME to a DWARF-2 register number. */
8380 tc_aarch64_regname_to_dw2regnum (char *regname
)
8382 const reg_entry
*reg
= parse_reg (®name
);
8388 case REG_TYPE_SP_32
:
8389 case REG_TYPE_SP_64
:
8399 return reg
->number
+ 64;
8407 /* Implement DWARF2_ADDR_SIZE. */
8410 aarch64_dwarf2_addr_size (void)
8412 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8416 return bfd_arch_bits_per_address (stdoutput
) / 8;
8419 /* MD interface: Symbol and relocation handling. */
8421 /* Return the address within the segment that a PC-relative fixup is
8422 relative to. For AArch64 PC-relative fixups applied to instructions
8423 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8426 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8428 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8430 /* If this is pc-relative and we are going to emit a relocation
8431 then we just want to put out any pipeline compensation that the linker
8432 will need. Otherwise we want to use the calculated base. */
8434 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8435 || aarch64_force_relocation (fixP
)))
8438 /* AArch64 should be consistent for all pc-relative relocations. */
8439 return base
+ AARCH64_PCREL_OFFSET
;
8442 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8443 Otherwise we have no need to default values of symbols. */
8446 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8449 if (name
[0] == '_' && name
[1] == 'G'
8450 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8454 if (symbol_find (name
))
8455 as_bad (_("GOT already in the symbol table"));
8457 GOT_symbol
= symbol_new (name
, undefined_section
,
8458 &zero_address_frag
, 0);
8468 /* Return non-zero if the indicated VALUE has overflowed the maximum
8469 range expressible by a unsigned number with the indicated number of
8473 unsigned_overflow (valueT value
, unsigned bits
)
8476 if (bits
>= sizeof (valueT
) * 8)
8478 lim
= (valueT
) 1 << bits
;
8479 return (value
>= lim
);
8483 /* Return non-zero if the indicated VALUE has overflowed the maximum
8484 range expressible by an signed number with the indicated number of
8488 signed_overflow (offsetT value
, unsigned bits
)
8491 if (bits
>= sizeof (offsetT
) * 8)
8493 lim
= (offsetT
) 1 << (bits
- 1);
8494 return (value
< -lim
|| value
>= lim
);
8497 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8498 unsigned immediate offset load/store instruction, try to encode it as
8499 an unscaled, 9-bit, signed immediate offset load/store instruction.
8500 Return TRUE if it is successful; otherwise return FALSE.
8502 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8503 in response to the standard LDR/STR mnemonics when the immediate offset is
8504 unambiguous, i.e. when it is negative or unaligned. */
8507 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8510 enum aarch64_op new_op
;
8511 const aarch64_opcode
*new_opcode
;
8513 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8515 switch (instr
->opcode
->op
)
8517 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8518 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8519 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8520 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8521 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8522 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8523 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8524 case OP_STR_POS
: new_op
= OP_STUR
; break;
8525 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8526 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8527 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8528 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8529 default: new_op
= OP_NIL
; break;
8532 if (new_op
== OP_NIL
)
8535 new_opcode
= aarch64_get_opcode (new_op
);
8536 gas_assert (new_opcode
!= NULL
);
8538 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8539 instr
->opcode
->op
, new_opcode
->op
);
8541 aarch64_replace_opcode (instr
, new_opcode
);
8543 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8544 qualifier matching may fail because the out-of-date qualifier will
8545 prevent the operand being updated with a new and correct qualifier. */
8546 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8547 AARCH64_OPND_ADDR_SIMM9
);
8548 gas_assert (idx
== 1);
8549 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8551 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8553 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8560 /* Called by fix_insn to fix a MOV immediate alias instruction.
8562 Operand for a generic move immediate instruction, which is an alias
8563 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8564 a 32-bit/64-bit immediate value into general register. An assembler error
8565 shall result if the immediate cannot be created by a single one of these
8566 instructions. If there is a choice, then to ensure reversability an
8567 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8570 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8572 const aarch64_opcode
*opcode
;
8574 /* Need to check if the destination is SP/ZR. The check has to be done
8575 before any aarch64_replace_opcode. */
8576 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8577 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8579 instr
->operands
[1].imm
.value
= value
;
8580 instr
->operands
[1].skip
= 0;
8584 /* Try the MOVZ alias. */
8585 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8586 aarch64_replace_opcode (instr
, opcode
);
8587 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8588 &instr
->value
, NULL
, NULL
, insn_sequence
))
8590 put_aarch64_insn (buf
, instr
->value
);
8593 /* Try the MOVK alias. */
8594 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8595 aarch64_replace_opcode (instr
, opcode
);
8596 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8597 &instr
->value
, NULL
, NULL
, insn_sequence
))
8599 put_aarch64_insn (buf
, instr
->value
);
8604 if (try_mov_bitmask_p
)
8606 /* Try the ORR alias. */
8607 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8608 aarch64_replace_opcode (instr
, opcode
);
8609 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8610 &instr
->value
, NULL
, NULL
, insn_sequence
))
8612 put_aarch64_insn (buf
, instr
->value
);
8617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8618 _("immediate cannot be moved by a single instruction"));
8621 /* An instruction operand which is immediate related may have symbol used
8622 in the assembly, e.g.
8625 .set u32, 0x00ffff00
8627 At the time when the assembly instruction is parsed, a referenced symbol,
8628 like 'u32' in the above example may not have been seen; a fixS is created
8629 in such a case and is handled here after symbols have been resolved.
8630 Instruction is fixed up with VALUE using the information in *FIXP plus
8631 extra information in FLAGS.
8633 This function is called by md_apply_fix to fix up instructions that need
8634 a fix-up described above but does not involve any linker-time relocation. */
8637 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8641 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8642 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8643 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8647 /* Now the instruction is about to be fixed-up, so the operand that
8648 was previously marked as 'ignored' needs to be unmarked in order
8649 to get the encoding done properly. */
8650 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8651 new_inst
->operands
[idx
].skip
= 0;
8654 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8658 case AARCH64_OPND_EXCEPTION
:
8659 case AARCH64_OPND_UNDEFINED
:
8660 if (unsigned_overflow (value
, 16))
8661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8662 _("immediate out of range"));
8663 insn
= get_aarch64_insn (buf
);
8664 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8665 put_aarch64_insn (buf
, insn
);
8668 case AARCH64_OPND_AIMM
:
8669 /* ADD or SUB with immediate.
8670 NOTE this assumes we come here with a add/sub shifted reg encoding
8671 3 322|2222|2 2 2 21111 111111
8672 1 098|7654|3 2 1 09876 543210 98765 43210
8673 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8674 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8675 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8676 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8678 3 322|2222|2 2 221111111111
8679 1 098|7654|3 2 109876543210 98765 43210
8680 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8681 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8682 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8683 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8684 Fields sf Rn Rd are already set. */
8685 insn
= get_aarch64_insn (buf
);
8689 insn
= reencode_addsub_switch_add_sub (insn
);
8693 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8694 && unsigned_overflow (value
, 12))
8696 /* Try to shift the value by 12 to make it fit. */
8697 if (((value
>> 12) << 12) == value
8698 && ! unsigned_overflow (value
, 12 + 12))
8701 insn
|= encode_addsub_imm_shift_amount (1);
8705 if (unsigned_overflow (value
, 12))
8706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8707 _("immediate out of range"));
8709 insn
|= encode_addsub_imm (value
);
8711 put_aarch64_insn (buf
, insn
);
8714 case AARCH64_OPND_SIMD_IMM
:
8715 case AARCH64_OPND_SIMD_IMM_SFT
:
8716 case AARCH64_OPND_LIMM
:
8717 /* Bit mask immediate. */
8718 gas_assert (new_inst
!= NULL
);
8719 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8720 new_inst
->operands
[idx
].imm
.value
= value
;
8721 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8722 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8723 put_aarch64_insn (buf
, new_inst
->value
);
8725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8726 _("invalid immediate"));
8729 case AARCH64_OPND_HALF
:
8730 /* 16-bit unsigned immediate. */
8731 if (unsigned_overflow (value
, 16))
8732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8733 _("immediate out of range"));
8734 insn
= get_aarch64_insn (buf
);
8735 insn
|= encode_movw_imm (value
& 0xffff);
8736 put_aarch64_insn (buf
, insn
);
8739 case AARCH64_OPND_IMM_MOV
:
8740 /* Operand for a generic move immediate instruction, which is
8741 an alias instruction that generates a single MOVZ, MOVN or ORR
8742 instruction to loads a 32-bit/64-bit immediate value into general
8743 register. An assembler error shall result if the immediate cannot be
8744 created by a single one of these instructions. If there is a choice,
8745 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8746 and MOVZ or MOVN to ORR. */
8747 gas_assert (new_inst
!= NULL
);
8748 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8751 case AARCH64_OPND_ADDR_SIMM7
:
8752 case AARCH64_OPND_ADDR_SIMM9
:
8753 case AARCH64_OPND_ADDR_SIMM9_2
:
8754 case AARCH64_OPND_ADDR_SIMM10
:
8755 case AARCH64_OPND_ADDR_UIMM12
:
8756 case AARCH64_OPND_ADDR_SIMM11
:
8757 case AARCH64_OPND_ADDR_SIMM13
:
8758 /* Immediate offset in an address. */
8759 insn
= get_aarch64_insn (buf
);
8761 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8762 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8763 || new_inst
->opcode
->operands
[2] == opnd
);
8765 /* Get the index of the address operand. */
8766 if (new_inst
->opcode
->operands
[1] == opnd
)
8767 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8770 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8773 /* Update the resolved offset value. */
8774 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8776 /* Encode/fix-up. */
8777 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8778 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8780 put_aarch64_insn (buf
, new_inst
->value
);
8783 else if (new_inst
->opcode
->iclass
== ldst_pos
8784 && try_to_encode_as_unscaled_ldst (new_inst
))
8786 put_aarch64_insn (buf
, new_inst
->value
);
8790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8791 _("immediate offset out of range"));
8796 as_fatal (_("unhandled operand code %d"), opnd
);
8800 /* Apply a fixup (fixP) to segment data, once it has been determined
8801 by our caller that we have all the info we need to fix it up.
8803 Parameter valP is the pointer to the value of the bits. */
8806 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8808 offsetT value
= *valP
;
8810 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8812 unsigned flags
= fixP
->fx_addnumber
;
8814 DEBUG_TRACE ("\n\n");
8815 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8816 DEBUG_TRACE ("Enter md_apply_fix");
8818 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8820 /* Note whether this will delete the relocation. */
8822 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8825 /* Process the relocations. */
8826 switch (fixP
->fx_r_type
)
8828 case BFD_RELOC_NONE
:
8829 /* This will need to go in the object file. */
8834 case BFD_RELOC_8_PCREL
:
8835 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8836 md_number_to_chars (buf
, value
, 1);
8840 case BFD_RELOC_16_PCREL
:
8841 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8842 md_number_to_chars (buf
, value
, 2);
8846 case BFD_RELOC_32_PCREL
:
8847 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8848 md_number_to_chars (buf
, value
, 4);
8852 case BFD_RELOC_64_PCREL
:
8853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8854 md_number_to_chars (buf
, value
, 8);
8857 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8858 /* We claim that these fixups have been processed here, even if
8859 in fact we generate an error because we do not have a reloc
8860 for them, so tc_gen_reloc() will reject them. */
8862 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8865 _("undefined symbol %s used as an immediate value"),
8866 S_GET_NAME (fixP
->fx_addsy
));
8867 goto apply_fix_return
;
8869 fix_insn (fixP
, flags
, value
);
8872 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8877 _("pc-relative load offset not word aligned"));
8878 if (signed_overflow (value
, 21))
8879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8880 _("pc-relative load offset out of range"));
8881 insn
= get_aarch64_insn (buf
);
8882 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8883 put_aarch64_insn (buf
, insn
);
8887 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8890 if (signed_overflow (value
, 21))
8891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8892 _("pc-relative address offset out of range"));
8893 insn
= get_aarch64_insn (buf
);
8894 insn
|= encode_adr_imm (value
);
8895 put_aarch64_insn (buf
, insn
);
8899 case BFD_RELOC_AARCH64_BRANCH19
:
8900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8904 _("conditional branch target not word aligned"));
8905 if (signed_overflow (value
, 21))
8906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8907 _("conditional branch out of range"));
8908 insn
= get_aarch64_insn (buf
);
8909 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8910 put_aarch64_insn (buf
, insn
);
8914 case BFD_RELOC_AARCH64_TSTBR14
:
8915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8919 _("conditional branch target not word aligned"));
8920 if (signed_overflow (value
, 16))
8921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8922 _("conditional branch out of range"));
8923 insn
= get_aarch64_insn (buf
);
8924 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8925 put_aarch64_insn (buf
, insn
);
8929 case BFD_RELOC_AARCH64_CALL26
:
8930 case BFD_RELOC_AARCH64_JUMP26
:
8931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8935 _("branch target not word aligned"));
8936 if (signed_overflow (value
, 28))
8937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8938 _("branch out of range"));
8939 insn
= get_aarch64_insn (buf
);
8940 insn
|= encode_branch_ofs_26 (value
>> 2);
8941 put_aarch64_insn (buf
, insn
);
8945 case BFD_RELOC_AARCH64_MOVW_G0
:
8946 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8947 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8948 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8949 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8950 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8953 case BFD_RELOC_AARCH64_MOVW_G1
:
8954 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8955 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8956 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8957 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8958 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8961 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8963 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8964 /* Should always be exported to object file, see
8965 aarch64_force_relocation(). */
8966 gas_assert (!fixP
->fx_done
);
8967 gas_assert (seg
->use_rela_p
);
8969 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8971 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8972 /* Should always be exported to object file, see
8973 aarch64_force_relocation(). */
8974 gas_assert (!fixP
->fx_done
);
8975 gas_assert (seg
->use_rela_p
);
8977 case BFD_RELOC_AARCH64_MOVW_G2
:
8978 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8979 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8980 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8981 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8984 case BFD_RELOC_AARCH64_MOVW_G3
:
8985 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8990 insn
= get_aarch64_insn (buf
);
8994 /* REL signed addend must fit in 16 bits */
8995 if (signed_overflow (value
, 16))
8996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8997 _("offset out of range"));
9001 /* Check for overflow and scale. */
9002 switch (fixP
->fx_r_type
)
9004 case BFD_RELOC_AARCH64_MOVW_G0
:
9005 case BFD_RELOC_AARCH64_MOVW_G1
:
9006 case BFD_RELOC_AARCH64_MOVW_G2
:
9007 case BFD_RELOC_AARCH64_MOVW_G3
:
9008 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9009 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9010 if (unsigned_overflow (value
, scale
+ 16))
9011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9012 _("unsigned value out of range"));
9014 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9015 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9016 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9017 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9018 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9019 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9020 /* NOTE: We can only come here with movz or movn. */
9021 if (signed_overflow (value
, scale
+ 16))
9022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9023 _("signed value out of range"));
9026 /* Force use of MOVN. */
9028 insn
= reencode_movzn_to_movn (insn
);
9032 /* Force use of MOVZ. */
9033 insn
= reencode_movzn_to_movz (insn
);
9037 /* Unchecked relocations. */
9043 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9044 insn
|= encode_movw_imm (value
& 0xffff);
9046 put_aarch64_insn (buf
, insn
);
9050 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9051 fixP
->fx_r_type
= (ilp32_p
9052 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9053 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9054 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9055 /* Should always be exported to object file, see
9056 aarch64_force_relocation(). */
9057 gas_assert (!fixP
->fx_done
);
9058 gas_assert (seg
->use_rela_p
);
9061 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9062 fixP
->fx_r_type
= (ilp32_p
9063 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9064 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9065 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9066 /* Should always be exported to object file, see
9067 aarch64_force_relocation(). */
9068 gas_assert (!fixP
->fx_done
);
9069 gas_assert (seg
->use_rela_p
);
9072 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9073 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9074 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9075 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9076 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9077 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9078 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9079 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9080 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9081 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9082 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9083 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9084 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9085 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9086 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9087 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9088 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9089 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9090 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9091 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9092 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9093 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9094 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9095 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9096 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9097 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9098 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9099 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9100 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9101 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9102 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9103 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9104 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9105 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9106 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9107 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9108 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9109 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9110 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9111 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9112 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9113 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9114 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9115 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9116 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9117 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9118 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9119 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9120 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9121 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9122 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9123 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9124 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9125 /* Should always be exported to object file, see
9126 aarch64_force_relocation(). */
9127 gas_assert (!fixP
->fx_done
);
9128 gas_assert (seg
->use_rela_p
);
9131 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9132 /* Should always be exported to object file, see
9133 aarch64_force_relocation(). */
9134 fixP
->fx_r_type
= (ilp32_p
9135 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9136 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9137 gas_assert (!fixP
->fx_done
);
9138 gas_assert (seg
->use_rela_p
);
9141 case BFD_RELOC_AARCH64_ADD_LO12
:
9142 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9143 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9144 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9145 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9146 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9147 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9148 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9149 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9150 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9151 case BFD_RELOC_AARCH64_LDST128_LO12
:
9152 case BFD_RELOC_AARCH64_LDST16_LO12
:
9153 case BFD_RELOC_AARCH64_LDST32_LO12
:
9154 case BFD_RELOC_AARCH64_LDST64_LO12
:
9155 case BFD_RELOC_AARCH64_LDST8_LO12
:
9156 /* Should always be exported to object file, see
9157 aarch64_force_relocation(). */
9158 gas_assert (!fixP
->fx_done
);
9159 gas_assert (seg
->use_rela_p
);
9162 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9163 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9164 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9167 case BFD_RELOC_UNUSED
:
9168 /* An error will already have been reported. */
9172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9173 _("unexpected %s fixup"),
9174 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9179 /* Free the allocated the struct aarch64_inst.
9180 N.B. currently there are very limited number of fix-up types actually use
9181 this field, so the impact on the performance should be minimal . */
9182 free (fixP
->tc_fix_data
.inst
);
9187 /* Translate internal representation of relocation info to BFD target
9191 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9194 bfd_reloc_code_real_type code
;
9196 reloc
= XNEW (arelent
);
9198 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9199 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9200 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9204 if (section
->use_rela_p
)
9205 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9207 fixp
->fx_offset
= reloc
->address
;
9209 reloc
->addend
= fixp
->fx_offset
;
9211 code
= fixp
->fx_r_type
;
9216 code
= BFD_RELOC_16_PCREL
;
9221 code
= BFD_RELOC_32_PCREL
;
9226 code
= BFD_RELOC_64_PCREL
;
9233 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9234 if (reloc
->howto
== NULL
)
9236 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9238 ("cannot represent %s relocation in this object file format"),
9239 bfd_get_reloc_code_name (code
));
9246 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9249 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9251 bfd_reloc_code_real_type type
;
9255 FIXME: @@ Should look at CPU word size. */
9262 type
= BFD_RELOC_16
;
9265 type
= BFD_RELOC_32
;
9268 type
= BFD_RELOC_64
;
9271 as_bad (_("cannot do %u-byte relocation"), size
);
9272 type
= BFD_RELOC_UNUSED
;
9276 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9281 /* Implement md_after_parse_args. This is the earliest time we need to decide
9282 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9285 aarch64_after_parse_args (void)
9287 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9290 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9291 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9292 aarch64_abi
= AARCH64_ABI_ILP32
;
9294 aarch64_abi
= AARCH64_ABI_LP64
;
9298 elf64_aarch64_target_format (void)
9301 /* FIXME: What to do for ilp32_p ? */
9302 if (target_big_endian
)
9303 return "elf64-bigaarch64-cloudabi";
9305 return "elf64-littleaarch64-cloudabi";
9307 if (target_big_endian
)
9308 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9310 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9315 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9317 elf_frob_symbol (symp
, puntp
);
9321 /* MD interface: Finalization. */
9323 /* A good place to do this, although this was probably not intended
9324 for this kind of use. We need to dump the literal pool before
9325 references are made to a null symbol pointer. */
9328 aarch64_cleanup (void)
9332 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9334 /* Put it at the end of the relevant section. */
9335 subseg_set (pool
->section
, pool
->sub_section
);
9341 /* Remove any excess mapping symbols generated for alignment frags in
9342 SEC. We may have created a mapping symbol before a zero byte
9343 alignment; remove it if there's a mapping symbol after the
9346 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9347 void *dummy ATTRIBUTE_UNUSED
)
9349 segment_info_type
*seginfo
= seg_info (sec
);
9352 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9355 for (fragp
= seginfo
->frchainP
->frch_root
;
9356 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9358 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9359 fragS
*next
= fragp
->fr_next
;
9361 /* Variable-sized frags have been converted to fixed size by
9362 this point. But if this was variable-sized to start with,
9363 there will be a fixed-size frag after it. So don't handle
9365 if (sym
== NULL
|| next
== NULL
)
9368 if (S_GET_VALUE (sym
) < next
->fr_address
)
9369 /* Not at the end of this frag. */
9371 know (S_GET_VALUE (sym
) == next
->fr_address
);
9375 if (next
->tc_frag_data
.first_map
!= NULL
)
9377 /* Next frag starts with a mapping symbol. Discard this
9379 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9383 if (next
->fr_next
== NULL
)
9385 /* This mapping symbol is at the end of the section. Discard
9387 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9388 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9392 /* As long as we have empty frags without any mapping symbols,
9394 /* If the next frag is non-empty and does not start with a
9395 mapping symbol, then this mapping symbol is required. */
9396 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9399 next
= next
->fr_next
;
9401 while (next
!= NULL
);
9406 /* Adjust the symbol table. */
9409 aarch64_adjust_symtab (void)
9412 /* Remove any overlapping mapping symbols generated by alignment frags. */
9413 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9414 /* Now do generic ELF adjustments. */
9415 elf_adjust_symtab ();
9420 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9422 str_hash_insert (table
, key
, value
, 0);
9426 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9428 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9429 checked_hash_insert (table
, key
, value
);
9433 fill_instruction_hash_table (void)
9435 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9437 while (opcode
->name
!= NULL
)
9439 templates
*templ
, *new_templ
;
9440 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9442 new_templ
= XNEW (templates
);
9443 new_templ
->opcode
= opcode
;
9444 new_templ
->next
= NULL
;
9447 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9450 new_templ
->next
= templ
->next
;
9451 templ
->next
= new_templ
;
9458 convert_to_upper (char *dst
, const char *src
, size_t num
)
9461 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9462 *dst
= TOUPPER (*src
);
9466 /* Assume STR point to a lower-case string, allocate, convert and return
9467 the corresponding upper-case string. */
9468 static inline const char*
9469 get_upper_str (const char *str
)
9472 size_t len
= strlen (str
);
9473 ret
= XNEWVEC (char, len
+ 1);
9474 convert_to_upper (ret
, str
, len
);
9478 /* MD interface: Initialization. */
9486 aarch64_ops_hsh
= str_htab_create ();
9487 aarch64_cond_hsh
= str_htab_create ();
9488 aarch64_shift_hsh
= str_htab_create ();
9489 aarch64_sys_regs_hsh
= str_htab_create ();
9490 aarch64_pstatefield_hsh
= str_htab_create ();
9491 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9492 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9493 aarch64_sys_regs_at_hsh
= str_htab_create ();
9494 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9495 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9496 aarch64_reg_hsh
= str_htab_create ();
9497 aarch64_barrier_opt_hsh
= str_htab_create ();
9498 aarch64_nzcv_hsh
= str_htab_create ();
9499 aarch64_pldop_hsh
= str_htab_create ();
9500 aarch64_hint_opt_hsh
= str_htab_create ();
9502 fill_instruction_hash_table ();
9504 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9505 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9506 (void *) (aarch64_sys_regs
+ i
));
9508 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9509 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9510 aarch64_pstatefields
[i
].name
,
9511 (void *) (aarch64_pstatefields
+ i
));
9513 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9514 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9515 aarch64_sys_regs_ic
[i
].name
,
9516 (void *) (aarch64_sys_regs_ic
+ i
));
9518 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9519 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9520 aarch64_sys_regs_dc
[i
].name
,
9521 (void *) (aarch64_sys_regs_dc
+ i
));
9523 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9524 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9525 aarch64_sys_regs_at
[i
].name
,
9526 (void *) (aarch64_sys_regs_at
+ i
));
9528 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9529 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9530 aarch64_sys_regs_tlbi
[i
].name
,
9531 (void *) (aarch64_sys_regs_tlbi
+ i
));
9533 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9534 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9535 aarch64_sys_regs_sr
[i
].name
,
9536 (void *) (aarch64_sys_regs_sr
+ i
));
9538 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9539 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9540 (void *) (reg_names
+ i
));
9542 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9543 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9544 (void *) (nzcv_names
+ i
));
9546 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9548 const char *name
= aarch64_operand_modifiers
[i
].name
;
9549 checked_hash_insert (aarch64_shift_hsh
, name
,
9550 (void *) (aarch64_operand_modifiers
+ i
));
9551 /* Also hash the name in the upper case. */
9552 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9553 (void *) (aarch64_operand_modifiers
+ i
));
9556 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9559 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9560 the same condition code. */
9561 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9563 const char *name
= aarch64_conds
[i
].names
[j
];
9566 checked_hash_insert (aarch64_cond_hsh
, name
,
9567 (void *) (aarch64_conds
+ i
));
9568 /* Also hash the name in the upper case. */
9569 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9570 (void *) (aarch64_conds
+ i
));
9574 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9576 const char *name
= aarch64_barrier_options
[i
].name
;
9577 /* Skip xx00 - the unallocated values of option. */
9580 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9581 (void *) (aarch64_barrier_options
+ i
));
9582 /* Also hash the name in the upper case. */
9583 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9584 (void *) (aarch64_barrier_options
+ i
));
9587 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9589 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9590 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9591 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9592 /* Also hash the name in the upper case. */
9593 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9594 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9597 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9599 const char* name
= aarch64_prfops
[i
].name
;
9600 /* Skip the unallocated hint encodings. */
9603 checked_hash_insert (aarch64_pldop_hsh
, name
,
9604 (void *) (aarch64_prfops
+ i
));
9605 /* Also hash the name in the upper case. */
9606 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9607 (void *) (aarch64_prfops
+ i
));
9610 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9612 const char* name
= aarch64_hint_options
[i
].name
;
9613 const char* upper_name
= get_upper_str(name
);
9615 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9616 (void *) (aarch64_hint_options
+ i
));
9618 /* Also hash the name in the upper case if not the same. */
9619 if (strcmp (name
, upper_name
) != 0)
9620 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9621 (void *) (aarch64_hint_options
+ i
));
9624 /* Set the cpu variant based on the command-line options. */
9626 mcpu_cpu_opt
= march_cpu_opt
;
9629 mcpu_cpu_opt
= &cpu_default
;
9631 cpu_variant
= *mcpu_cpu_opt
;
9633 /* Record the CPU type. */
9634 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9636 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9639 /* Command line processing. */
9641 const char *md_shortopts
= "m:";
9643 #ifdef AARCH64_BI_ENDIAN
9644 #define OPTION_EB (OPTION_MD_BASE + 0)
9645 #define OPTION_EL (OPTION_MD_BASE + 1)
9647 #if TARGET_BYTES_BIG_ENDIAN
9648 #define OPTION_EB (OPTION_MD_BASE + 0)
9650 #define OPTION_EL (OPTION_MD_BASE + 1)
9654 struct option md_longopts
[] = {
9656 {"EB", no_argument
, NULL
, OPTION_EB
},
9659 {"EL", no_argument
, NULL
, OPTION_EL
},
9661 {NULL
, no_argument
, NULL
, 0}
9664 size_t md_longopts_size
= sizeof (md_longopts
);
9666 struct aarch64_option_table
9668 const char *option
; /* Option name to match. */
9669 const char *help
; /* Help information. */
9670 int *var
; /* Variable to change. */
9671 int value
; /* What to change it to. */
9672 char *deprecated
; /* If non-null, print this message. */
9675 static struct aarch64_option_table aarch64_opts
[] = {
9676 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9677 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9679 #ifdef DEBUG_AARCH64
9680 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9681 #endif /* DEBUG_AARCH64 */
9682 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9684 {"mno-verbose-error", N_("do not output verbose error messages"),
9685 &verbose_error_p
, 0, NULL
},
9686 {NULL
, NULL
, NULL
, 0, NULL
}
9689 struct aarch64_cpu_option_table
9692 const aarch64_feature_set value
;
9693 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9695 const char *canonical_name
;
9698 /* This list should, at a minimum, contain all the cpu names
9699 recognized by GCC. */
9700 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9701 {"all", AARCH64_ANY
, NULL
},
9702 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9703 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9704 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9705 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9706 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9707 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9708 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9709 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9710 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9711 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9712 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9713 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9714 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9715 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9717 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9718 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9720 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9721 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9723 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9724 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9725 | AARCH64_FEATURE_DOTPROD
9726 | AARCH64_FEATURE_SSBS
),
9728 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9729 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9730 | AARCH64_FEATURE_DOTPROD
9731 | AARCH64_FEATURE_SSBS
),
9733 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9734 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9735 | AARCH64_FEATURE_DOTPROD
9736 | AARCH64_FEATURE_SSBS
),
9738 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9739 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9740 | AARCH64_FEATURE_DOTPROD
9741 | AARCH64_FEATURE_SSBS
),
9743 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9745 | AARCH64_FEATURE_RCPC
9746 | AARCH64_FEATURE_DOTPROD
9747 | AARCH64_FEATURE_SSBS
9748 | AARCH64_FEATURE_PROFILE
),
9750 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9752 | AARCH64_FEATURE_RCPC
9753 | AARCH64_FEATURE_DOTPROD
9754 | AARCH64_FEATURE_SSBS
9755 | AARCH64_FEATURE_PROFILE
),
9757 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9758 AARCH64_FEATURE_DOTPROD
9759 | AARCH64_FEATURE_F16
9760 | AARCH64_FEATURE_FLAGM
9761 | AARCH64_FEATURE_PAC
9762 | AARCH64_FEATURE_PROFILE
9763 | AARCH64_FEATURE_RCPC
9764 | AARCH64_FEATURE_SSBS
),
9766 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9767 AARCH64_FEATURE_BFLOAT16
9768 | AARCH64_FEATURE_I8MM
9769 | AARCH64_FEATURE_MEMTAG
9770 | AARCH64_FEATURE_SVE2_BITPERM
),
9772 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9773 AARCH64_FEATURE_BFLOAT16
9774 | AARCH64_FEATURE_I8MM
9775 | AARCH64_FEATURE_MEMTAG
9776 | AARCH64_FEATURE_SVE2_BITPERM
),
9778 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9779 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9780 | AARCH64_FEATURE_DOTPROD
9781 | AARCH64_FEATURE_PROFILE
),
9783 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9784 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9785 "Samsung Exynos M1"},
9786 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9787 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9788 | AARCH64_FEATURE_RDMA
),
9790 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9791 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9792 | AARCH64_FEATURE_DOTPROD
9793 | AARCH64_FEATURE_SSBS
),
9795 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9796 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9797 | AARCH64_FEATURE_DOTPROD
9798 | AARCH64_FEATURE_PROFILE
),
9800 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9801 AARCH64_FEATURE_BFLOAT16
9802 | AARCH64_FEATURE_I8MM
9803 | AARCH64_FEATURE_F16
9804 | AARCH64_FEATURE_SVE
9805 | AARCH64_FEATURE_SVE2
9806 | AARCH64_FEATURE_SVE2_BITPERM
9807 | AARCH64_FEATURE_MEMTAG
9808 | AARCH64_FEATURE_RNG
),
9810 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9811 AARCH64_FEATURE_PROFILE
9812 | AARCH64_FEATURE_CVADP
9813 | AARCH64_FEATURE_SVE
9814 | AARCH64_FEATURE_SSBS
9815 | AARCH64_FEATURE_RNG
9816 | AARCH64_FEATURE_F16
9817 | AARCH64_FEATURE_BFLOAT16
9818 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9819 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9820 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9821 | AARCH64_FEATURE_RDMA
),
9822 "Qualcomm QDF24XX"},
9823 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9824 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9825 "Qualcomm Saphira"},
9826 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9827 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9829 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9830 AARCH64_FEATURE_CRYPTO
),
9832 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9833 in earlier releases and is superseded by 'xgene1' in all
9835 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9836 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9837 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9838 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9839 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9840 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9842 | AARCH64_FEATURE_RCPC
9843 | AARCH64_FEATURE_DOTPROD
9844 | AARCH64_FEATURE_SSBS
9845 | AARCH64_FEATURE_PROFILE
),
9847 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9848 AARCH64_FEATURE_BFLOAT16
9849 | AARCH64_FEATURE_I8MM
9850 | AARCH64_FEATURE_MEMTAG
9851 | AARCH64_FEATURE_SVE2_BITPERM
),
9853 {"generic", AARCH64_ARCH_V8
, NULL
},
9855 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9858 struct aarch64_arch_option_table
9861 const aarch64_feature_set value
;
9864 /* This list should, at a minimum, contain all the architecture names
9865 recognized by GCC. */
9866 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9867 {"all", AARCH64_ANY
},
9868 {"armv8-a", AARCH64_ARCH_V8
},
9869 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9870 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9871 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9872 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9873 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9874 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9875 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9876 {"armv8.8-a", AARCH64_ARCH_V8_8
},
9877 {"armv8-r", AARCH64_ARCH_V8_R
},
9878 {"armv9-a", AARCH64_ARCH_V9
},
9879 {"armv9.1-a", AARCH64_ARCH_V9_1
},
9880 {"armv9.2-a", AARCH64_ARCH_V9_2
},
9881 {"armv9.3-a", AARCH64_ARCH_V9_3
},
9882 {NULL
, AARCH64_ARCH_NONE
}
9885 /* ISA extensions. */
9886 struct aarch64_option_cpu_value_table
9889 const aarch64_feature_set value
;
9890 const aarch64_feature_set require
; /* Feature dependencies. */
9893 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9894 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9896 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9897 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9898 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9900 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9902 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9903 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9904 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9906 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9908 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9910 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9911 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9912 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9913 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9914 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9915 AARCH64_FEATURE (AARCH64_FEATURE_FP
9916 | AARCH64_FEATURE_F16
, 0)},
9917 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9919 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9920 AARCH64_FEATURE (AARCH64_FEATURE_F16
9921 | AARCH64_FEATURE_SIMD
9922 | AARCH64_FEATURE_COMPNUM
, 0)},
9923 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9925 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9926 AARCH64_FEATURE (AARCH64_FEATURE_F16
9927 | AARCH64_FEATURE_SIMD
, 0)},
9928 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9930 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9932 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9934 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9936 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9938 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9940 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9942 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9943 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9944 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9946 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9948 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9950 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9951 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9952 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9953 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9954 | AARCH64_FEATURE_SM4
, 0)},
9955 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9956 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9957 | AARCH64_FEATURE_AES
, 0)},
9958 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9959 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9960 | AARCH64_FEATURE_SHA3
, 0)},
9961 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9962 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9963 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
9964 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9965 | AARCH64_FEATURE_BFLOAT16
, 0)},
9966 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
9967 AARCH64_FEATURE (AARCH64_FEATURE_SME
9968 | AARCH64_FEATURE_SVE2
9969 | AARCH64_FEATURE_BFLOAT16
, 0)},
9970 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
9971 AARCH64_FEATURE (AARCH64_FEATURE_SME
9972 | AARCH64_FEATURE_SVE2
9973 | AARCH64_FEATURE_BFLOAT16
, 0)},
9974 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9976 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9978 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9979 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9980 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9981 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9982 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9984 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9986 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9988 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
9990 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
9992 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9995 struct aarch64_long_option_table
9997 const char *option
; /* Substring to match. */
9998 const char *help
; /* Help information. */
9999 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10000 char *deprecated
; /* If non-null, print this message. */
10003 /* Transitive closure of features depending on set. */
10004 static aarch64_feature_set
10005 aarch64_feature_disable_set (aarch64_feature_set set
)
10007 const struct aarch64_option_cpu_value_table
*opt
;
10008 aarch64_feature_set prev
= 0;
10010 while (prev
!= set
) {
10012 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10013 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10014 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10019 /* Transitive closure of dependencies of set. */
10020 static aarch64_feature_set
10021 aarch64_feature_enable_set (aarch64_feature_set set
)
10023 const struct aarch64_option_cpu_value_table
*opt
;
10024 aarch64_feature_set prev
= 0;
10026 while (prev
!= set
) {
10028 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10029 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10030 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10036 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10039 /* We insist on extensions being added before being removed. We achieve
10040 this by using the ADDING_VALUE variable to indicate whether we are
10041 adding an extension (1) or removing it (0) and only allowing it to
10042 change in the order -1 -> 1 -> 0. */
10043 int adding_value
= -1;
10044 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10046 /* Copy the feature set, so that we can modify it. */
10047 *ext_set
= **opt_p
;
10050 while (str
!= NULL
&& *str
!= 0)
10052 const struct aarch64_option_cpu_value_table
*opt
;
10053 const char *ext
= NULL
;
10060 as_bad (_("invalid architectural extension"));
10064 ext
= strchr (++str
, '+');
10068 optlen
= ext
- str
;
10070 optlen
= strlen (str
);
10072 if (optlen
>= 2 && startswith (str
, "no"))
10074 if (adding_value
!= 0)
10079 else if (optlen
> 0)
10081 if (adding_value
== -1)
10083 else if (adding_value
!= 1)
10085 as_bad (_("must specify extensions to add before specifying "
10086 "those to remove"));
10093 as_bad (_("missing architectural extension"));
10097 gas_assert (adding_value
!= -1);
10099 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10100 if (strncmp (opt
->name
, str
, optlen
) == 0)
10102 aarch64_feature_set set
;
10104 /* Add or remove the extension. */
10107 set
= aarch64_feature_enable_set (opt
->value
);
10108 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10112 set
= aarch64_feature_disable_set (opt
->value
);
10113 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10118 if (opt
->name
== NULL
)
10120 as_bad (_("unknown architectural extension `%s'"), str
);
10131 aarch64_parse_cpu (const char *str
)
10133 const struct aarch64_cpu_option_table
*opt
;
10134 const char *ext
= strchr (str
, '+');
10138 optlen
= ext
- str
;
10140 optlen
= strlen (str
);
10144 as_bad (_("missing cpu name `%s'"), str
);
10148 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10149 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10151 mcpu_cpu_opt
= &opt
->value
;
10153 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10158 as_bad (_("unknown cpu `%s'"), str
);
10163 aarch64_parse_arch (const char *str
)
10165 const struct aarch64_arch_option_table
*opt
;
10166 const char *ext
= strchr (str
, '+');
10170 optlen
= ext
- str
;
10172 optlen
= strlen (str
);
10176 as_bad (_("missing architecture name `%s'"), str
);
10180 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10181 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10183 march_cpu_opt
= &opt
->value
;
10185 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10190 as_bad (_("unknown architecture `%s'\n"), str
);
10195 struct aarch64_option_abi_value_table
10198 enum aarch64_abi_type value
;
10201 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10202 {"ilp32", AARCH64_ABI_ILP32
},
10203 {"lp64", AARCH64_ABI_LP64
},
10207 aarch64_parse_abi (const char *str
)
10211 if (str
[0] == '\0')
10213 as_bad (_("missing abi name `%s'"), str
);
10217 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10218 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10220 aarch64_abi
= aarch64_abis
[i
].value
;
10224 as_bad (_("unknown abi `%s'\n"), str
);
10228 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10230 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10231 aarch64_parse_abi
, NULL
},
10232 #endif /* OBJ_ELF */
10233 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10234 aarch64_parse_cpu
, NULL
},
10235 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10236 aarch64_parse_arch
, NULL
},
10237 {NULL
, NULL
, 0, NULL
}
10241 md_parse_option (int c
, const char *arg
)
10243 struct aarch64_option_table
*opt
;
10244 struct aarch64_long_option_table
*lopt
;
10250 target_big_endian
= 1;
10256 target_big_endian
= 0;
10261 /* Listing option. Just ignore these, we don't support additional
10266 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10268 if (c
== opt
->option
[0]
10269 && ((arg
== NULL
&& opt
->option
[1] == 0)
10270 || streq (arg
, opt
->option
+ 1)))
10272 /* If the option is deprecated, tell the user. */
10273 if (opt
->deprecated
!= NULL
)
10274 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10275 arg
? arg
: "", _(opt
->deprecated
));
10277 if (opt
->var
!= NULL
)
10278 *opt
->var
= opt
->value
;
10284 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10286 /* These options are expected to have an argument. */
10287 if (c
== lopt
->option
[0]
10289 && startswith (arg
, lopt
->option
+ 1))
10291 /* If the option is deprecated, tell the user. */
10292 if (lopt
->deprecated
!= NULL
)
10293 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10294 _(lopt
->deprecated
));
10296 /* Call the sup-option parser. */
10297 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10308 md_show_usage (FILE * fp
)
10310 struct aarch64_option_table
*opt
;
10311 struct aarch64_long_option_table
*lopt
;
10313 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10315 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10316 if (opt
->help
!= NULL
)
10317 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10319 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10320 if (lopt
->help
!= NULL
)
10321 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10325 -EB assemble code for a big-endian cpu\n"));
10330 -EL assemble code for a little-endian cpu\n"));
10334 /* Parse a .cpu directive. */
10337 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10339 const struct aarch64_cpu_option_table
*opt
;
10345 name
= input_line_pointer
;
10346 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10347 input_line_pointer
++;
10348 saved_char
= *input_line_pointer
;
10349 *input_line_pointer
= 0;
10351 ext
= strchr (name
, '+');
10354 optlen
= ext
- name
;
10356 optlen
= strlen (name
);
10358 /* Skip the first "all" entry. */
10359 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10360 if (strlen (opt
->name
) == optlen
10361 && strncmp (name
, opt
->name
, optlen
) == 0)
10363 mcpu_cpu_opt
= &opt
->value
;
10365 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10368 cpu_variant
= *mcpu_cpu_opt
;
10370 *input_line_pointer
= saved_char
;
10371 demand_empty_rest_of_line ();
10374 as_bad (_("unknown cpu `%s'"), name
);
10375 *input_line_pointer
= saved_char
;
10376 ignore_rest_of_line ();
10380 /* Parse a .arch directive. */
10383 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10385 const struct aarch64_arch_option_table
*opt
;
10391 name
= input_line_pointer
;
10392 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10393 input_line_pointer
++;
10394 saved_char
= *input_line_pointer
;
10395 *input_line_pointer
= 0;
10397 ext
= strchr (name
, '+');
10400 optlen
= ext
- name
;
10402 optlen
= strlen (name
);
10404 /* Skip the first "all" entry. */
10405 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10406 if (strlen (opt
->name
) == optlen
10407 && strncmp (name
, opt
->name
, optlen
) == 0)
10409 mcpu_cpu_opt
= &opt
->value
;
10411 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10414 cpu_variant
= *mcpu_cpu_opt
;
10416 *input_line_pointer
= saved_char
;
10417 demand_empty_rest_of_line ();
10421 as_bad (_("unknown architecture `%s'\n"), name
);
10422 *input_line_pointer
= saved_char
;
10423 ignore_rest_of_line ();
10426 /* Parse a .arch_extension directive. */
10429 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10432 char *ext
= input_line_pointer
;;
10434 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10435 input_line_pointer
++;
10436 saved_char
= *input_line_pointer
;
10437 *input_line_pointer
= 0;
10439 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10442 cpu_variant
= *mcpu_cpu_opt
;
10444 *input_line_pointer
= saved_char
;
10445 demand_empty_rest_of_line ();
10448 /* Copy symbol information. */
10451 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10453 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10457 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10458 This is needed so AArch64 specific st_other values can be independently
10459 specified for an IFUNC resolver (that is called by the dynamic linker)
10460 and the symbol it resolves (aliased to the resolver). In particular,
10461 if a function symbol has special st_other value set via directives,
10462 then attaching an IFUNC resolver to that symbol should not override
10463 the st_other setting. Requiring the directive on the IFUNC resolver
10464 symbol would be unexpected and problematic in C code, where the two
10465 symbols appear as two independent function declarations. */
10468 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10470 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10471 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10472 /* If size is unset, copy size from src. Because we don't track whether
10473 .size has been used, we can't differentiate .size dest, 0 from the case
10474 where dest's size is unset. */
10475 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10479 destelf
->size
= XNEW (expressionS
);
10480 *destelf
->size
= *srcelf
->size
;
10482 S_SET_SIZE (dest
, S_GET_SIZE (src
));