1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
288 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
292 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
293 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: same, plus SVE registers. */ \
296 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
299 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
300 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
302 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
306 /* Typecheck: any [BHSDQ]P FP. */ \
307 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
308 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
309 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
310 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
312 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
313 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
314 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
315 be used for SVE instructions, since Zn and Pn are valid symbols \
316 in other contexts. */ \
317 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
322 | REG_TYPE(ZN) | REG_TYPE(PN)) \
323 /* Any integer register; used for error messages only. */ \
324 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
326 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
327 /* Pseudo type to mark the end of the enumerator sequence. */ \
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
332 #undef MULTI_REG_TYPE
333 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
335 /* Register type enumerators. */
336 typedef enum aarch64_reg_type_
338 /* A list of REG_TYPE_*. */
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
345 #define REG_TYPE(T) (1 << REG_TYPE_##T)
346 #undef MULTI_REG_TYPE
347 #define MULTI_REG_TYPE(T,V) V,
349 /* Structure for a hash table entry for a register. */
353 unsigned char number
;
354 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
355 unsigned char builtin
;
358 /* Values indexed by aarch64_reg_type to assist the type checking. */
359 static const unsigned reg_type_masks
[] =
364 #undef BASIC_REG_TYPE
366 #undef MULTI_REG_TYPE
367 #undef AARCH64_REG_TYPES
369 /* Diagnostics used when we don't get a register of the expected type.
370 Note: this has to synchronized with aarch64_reg_type definitions
373 get_reg_expected_msg (aarch64_reg_type reg_type
)
380 msg
= N_("integer 32-bit register expected");
383 msg
= N_("integer 64-bit register expected");
386 msg
= N_("integer register expected");
388 case REG_TYPE_R64_SP
:
389 msg
= N_("64-bit integer or SP register expected");
391 case REG_TYPE_SVE_BASE
:
392 msg
= N_("base register expected");
395 msg
= N_("integer or zero register expected");
397 case REG_TYPE_SVE_OFFSET
:
398 msg
= N_("offset register expected");
401 msg
= N_("integer or SP register expected");
403 case REG_TYPE_R_Z_SP
:
404 msg
= N_("integer, zero or SP register expected");
407 msg
= N_("8-bit SIMD scalar register expected");
410 msg
= N_("16-bit SIMD scalar or floating-point half precision "
411 "register expected");
414 msg
= N_("32-bit SIMD scalar or floating-point single precision "
415 "register expected");
418 msg
= N_("64-bit SIMD scalar or floating-point double precision "
419 "register expected");
422 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
423 "register expected");
425 case REG_TYPE_R_Z_BHSDQ_V
:
426 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
427 msg
= N_("register expected");
429 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
430 msg
= N_("SIMD scalar or floating-point register expected");
432 case REG_TYPE_VN
: /* any V reg */
433 msg
= N_("vector register expected");
436 msg
= N_("SVE vector register expected");
439 msg
= N_("SVE predicate register expected");
442 as_fatal (_("invalid register type %d"), reg_type
);
447 /* Some well known registers that we refer to directly elsewhere. */
451 /* Instructions take 4 bytes in the object file. */
454 static struct hash_control
*aarch64_ops_hsh
;
455 static struct hash_control
*aarch64_cond_hsh
;
456 static struct hash_control
*aarch64_shift_hsh
;
457 static struct hash_control
*aarch64_sys_regs_hsh
;
458 static struct hash_control
*aarch64_pstatefield_hsh
;
459 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
460 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
461 static struct hash_control
*aarch64_sys_regs_at_hsh
;
462 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
463 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
464 static struct hash_control
*aarch64_reg_hsh
;
465 static struct hash_control
*aarch64_barrier_opt_hsh
;
466 static struct hash_control
*aarch64_nzcv_hsh
;
467 static struct hash_control
*aarch64_pldop_hsh
;
468 static struct hash_control
*aarch64_hint_opt_hsh
;
470 /* Stuff needed to resolve the label ambiguity
479 static symbolS
*last_label_seen
;
481 /* Literal pool structure. Held on a per-section
482 and per-sub-section basis. */
484 #define MAX_LITERAL_POOL_SIZE 1024
485 typedef struct literal_expression
488 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
489 LITTLENUM_TYPE
* bignum
;
490 } literal_expression
;
492 typedef struct literal_pool
494 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
495 unsigned int next_free_entry
;
501 struct literal_pool
*next
;
504 /* Pointer to a linked list of literal pools. */
505 static literal_pool
*list_of_pools
= NULL
;
509 /* This array holds the chars that always start a comment. If the
510 pre-processor is disabled, these aren't very useful. */
511 const char comment_chars
[] = "";
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output. */
516 /* Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output. */
519 /* Also note that comments like this one will always work. */
520 const char line_comment_chars
[] = "#";
522 const char line_separator_chars
[] = ";";
524 /* Chars that can be used to separate mant
525 from exp in floating point numbers. */
526 const char EXP_CHARS
[] = "eE";
528 /* Chars that mean this number is a floating point constant. */
532 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
534 /* Prefix character that indicates the start of an immediate value. */
535 #define is_immediate_prefix(C) ((C) == '#')
537 /* Separator character handling. */
539 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
541 static inline bfd_boolean
542 skip_past_char (char **str
, char c
)
553 #define skip_past_comma(str) skip_past_char (str, ',')
555 /* Arithmetic expressions (possibly involving symbols). */
557 static bfd_boolean in_my_get_expression_p
= FALSE
;
559 /* Third argument to my_get_expression. */
560 #define GE_NO_PREFIX 0
561 #define GE_OPT_PREFIX 1
563 /* Return TRUE if the string pointed by *STR is successfully parsed
564 as an valid expression; *EP will be filled with the information of
565 such an expression. Otherwise return FALSE. */
568 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
573 int prefix_present_p
= 0;
580 if (is_immediate_prefix (**str
))
583 prefix_present_p
= 1;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_my_get_expression_p
= TRUE
;
595 seg
= expression (ep
);
596 in_my_get_expression_p
= FALSE
;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present_p
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
&& seg
!= undefined_section
)
616 set_syntax_error (_("bad segment"));
617 *str
= input_line_pointer
;
618 input_line_pointer
= save_in
;
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
630 /* Turn a string in input_line_pointer into a floating point constant
631 of type TYPE, and store the appropriate bytes in *LITP. The number
632 of LITTLENUMS emitted is stored in *SIZEP. An error message is
633 returned, or NULL on OK. */
636 md_atof (int type
, char *litP
, int *sizeP
)
638 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
641 /* We handle all bad expressions here, so that we can report the faulty
642 instruction in the error message. */
644 md_operand (expressionS
* exp
)
646 if (in_my_get_expression_p
)
647 exp
->X_op
= O_illegal
;
650 /* Immediate values. */
652 /* Errors may be set multiple times during parsing or bit encoding
653 (particularly in the Neon bits), but usually the earliest error which is set
654 will be the most meaningful. Avoid overwriting it with later (cascading)
655 errors by calling this function. */
658 first_error (const char *error
)
661 set_syntax_error (error
);
664 /* Similar to first_error, but this function accepts formatted error
667 first_error_fmt (const char *format
, ...)
672 /* N.B. this single buffer will not cause error messages for different
673 instructions to pollute each other; this is because at the end of
674 processing of each assembly line, error message if any will be
675 collected by as_bad. */
676 static char buffer
[size
];
680 int ret ATTRIBUTE_UNUSED
;
681 va_start (args
, format
);
682 ret
= vsnprintf (buffer
, size
, format
, args
);
683 know (ret
<= size
- 1 && ret
>= 0);
685 set_syntax_error (buffer
);
689 /* Register parsing. */
691 /* Generic register parser which is called by other specialized
693 CCP points to what should be the beginning of a register name.
694 If it is indeed a valid register name, advance CCP over it and
695 return the reg_entry structure; otherwise return NULL.
696 It does not issue diagnostics. */
699 parse_reg (char **ccp
)
705 #ifdef REGISTER_PREFIX
706 if (*start
!= REGISTER_PREFIX
)
712 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
717 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
719 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
728 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
731 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
733 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
736 /* Try to parse a base or offset register. Allow SVE base and offset
737 registers if REG_TYPE includes SVE registers. Return the register
738 entry on success, setting *QUALIFIER to the register qualifier.
739 Return null otherwise.
741 Note that this function does not issue any diagnostics. */
743 static const reg_entry
*
744 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
745 aarch64_opnd_qualifier_t
*qualifier
)
748 const reg_entry
*reg
= parse_reg (&str
);
758 *qualifier
= AARCH64_OPND_QLF_W
;
764 *qualifier
= AARCH64_OPND_QLF_X
;
768 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
771 switch (TOLOWER (str
[1]))
774 *qualifier
= AARCH64_OPND_QLF_S_S
;
777 *qualifier
= AARCH64_OPND_QLF_S_D
;
794 /* Try to parse a base or offset register. Return the register entry
795 on success, setting *QUALIFIER to the register qualifier. Return null
798 Note that this function does not issue any diagnostics. */
800 static const reg_entry
*
801 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
803 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
806 /* Parse the qualifier of a vector register or vector element of type
807 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
808 succeeds; otherwise return FALSE.
810 Accept only one occurrence of:
811 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
814 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
815 struct vector_type_el
*parsed_type
, char **str
)
819 unsigned element_size
;
820 enum vector_el_type type
;
823 gas_assert (*ptr
== '.');
826 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
831 width
= strtoul (ptr
, &ptr
, 10);
832 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
834 first_error_fmt (_("bad size %d in vector width specifier"), width
);
839 switch (TOLOWER (*ptr
))
858 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
867 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
869 first_error (_("missing element size"));
872 if (width
!= 0 && width
* element_size
!= 64
873 && width
* element_size
!= 128
874 && !(width
== 2 && element_size
== 16)
875 && !(width
== 4 && element_size
== 8))
878 ("invalid element size %d and vector size combination %c"),
884 parsed_type
->type
= type
;
885 parsed_type
->width
= width
;
892 /* *STR contains an SVE zero/merge predication suffix. Parse it into
893 *PARSED_TYPE and point *STR at the end of the suffix. */
896 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
901 gas_assert (*ptr
== '/');
903 switch (TOLOWER (*ptr
))
906 parsed_type
->type
= NT_zero
;
909 parsed_type
->type
= NT_merge
;
912 if (*ptr
!= '\0' && *ptr
!= ',')
913 first_error_fmt (_("unexpected character `%c' in predication type"),
916 first_error (_("missing predication type"));
919 parsed_type
->width
= 0;
924 /* Parse a register of the type TYPE.
926 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
927 name or the parsed register is not of TYPE.
929 Otherwise return the register number, and optionally fill in the actual
930 type of the register in *RTYPE when multiple alternatives were given, and
931 return the register shape and element index information in *TYPEINFO.
933 IN_REG_LIST should be set with TRUE if the caller is parsing a register
937 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
938 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
941 const reg_entry
*reg
= parse_reg (&str
);
942 struct vector_type_el atype
;
943 struct vector_type_el parsetype
;
944 bfd_boolean is_typed_vecreg
= FALSE
;
947 atype
.type
= NT_invtype
;
955 set_default_error ();
959 if (! aarch64_check_reg_type (reg
, type
))
961 DEBUG_TRACE ("reg type check failed");
962 set_default_error ();
967 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
968 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
972 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
977 if (!parse_predication_for_operand (&parsetype
, &str
))
981 /* Register if of the form Vn.[bhsdq]. */
982 is_typed_vecreg
= TRUE
;
984 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
986 /* The width is always variable; we don't allow an integer width
988 gas_assert (parsetype
.width
== 0);
989 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
991 else if (parsetype
.width
== 0)
992 /* Expect index. In the new scheme we cannot have
993 Vn.[bhsdq] represent a scalar. Therefore any
994 Vn.[bhsdq] should have an index following it.
995 Except in reglists of course. */
996 atype
.defined
|= NTA_HASINDEX
;
998 atype
.defined
|= NTA_HASTYPE
;
1000 atype
.type
= parsetype
.type
;
1001 atype
.width
= parsetype
.width
;
1004 if (skip_past_char (&str
, '['))
1008 /* Reject Sn[index] syntax. */
1009 if (!is_typed_vecreg
)
1011 first_error (_("this type of register can't be indexed"));
1017 first_error (_("index not allowed inside register list"));
1021 atype
.defined
|= NTA_HASINDEX
;
1023 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1025 if (exp
.X_op
!= O_constant
)
1027 first_error (_("constant expression required"));
1031 if (! skip_past_char (&str
, ']'))
1034 atype
.index
= exp
.X_add_number
;
1036 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1038 /* Indexed vector register expected. */
1039 first_error (_("indexed vector register expected"));
1043 /* A vector reg Vn should be typed or indexed. */
1044 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1046 first_error (_("invalid use of vector register"));
1062 Return the register number on success; return PARSE_FAIL otherwise.
1064 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1065 the register (e.g. NEON double or quad reg when either has been requested).
1067 If this is a NEON vector register with additional type information, fill
1068 in the struct pointed to by VECTYPE (if non-NULL).
1070 This parser does not handle register list. */
1073 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1074 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1076 struct vector_type_el atype
;
1078 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1079 /*in_reg_list= */ FALSE
);
1081 if (reg
== PARSE_FAIL
)
1092 static inline bfd_boolean
1093 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1097 && e1
.defined
== e2
.defined
1098 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1101 /* This function parses a list of vector registers of type TYPE.
1102 On success, it returns the parsed register list information in the
1103 following encoded format:
1105 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1106 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1108 The information of the register shape and/or index is returned in
1111 It returns PARSE_FAIL if the register list is invalid.
1113 The list contains one to four registers.
1114 Each register can be one of:
1117 All <T> should be identical.
1118 All <index> should be identical.
1119 There are restrictions on <Vt> numbers which are checked later
1120 (by reg_list_valid_p). */
1123 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1124 struct vector_type_el
*vectype
)
1128 struct vector_type_el typeinfo
, typeinfo_first
;
1133 bfd_boolean error
= FALSE
;
1134 bfd_boolean expect_index
= FALSE
;
1138 set_syntax_error (_("expecting {"));
1144 typeinfo_first
.defined
= 0;
1145 typeinfo_first
.type
= NT_invtype
;
1146 typeinfo_first
.width
= -1;
1147 typeinfo_first
.index
= 0;
1156 str
++; /* skip over '-' */
1159 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1160 /*in_reg_list= */ TRUE
);
1161 if (val
== PARSE_FAIL
)
1163 set_first_syntax_error (_("invalid vector register in list"));
1167 /* reject [bhsd]n */
1168 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1170 set_first_syntax_error (_("invalid scalar register in list"));
1175 if (typeinfo
.defined
& NTA_HASINDEX
)
1176 expect_index
= TRUE
;
1180 if (val
< val_range
)
1182 set_first_syntax_error
1183 (_("invalid range in vector register list"));
1192 typeinfo_first
= typeinfo
;
1193 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1195 set_first_syntax_error
1196 (_("type mismatch in vector register list"));
1201 for (i
= val_range
; i
<= val
; i
++)
1203 ret_val
|= i
<< (5 * nb_regs
);
1208 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1210 skip_whitespace (str
);
1213 set_first_syntax_error (_("end of vector register list not found"));
1218 skip_whitespace (str
);
1222 if (skip_past_char (&str
, '['))
1226 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1227 if (exp
.X_op
!= O_constant
)
1229 set_first_syntax_error (_("constant expression required."));
1232 if (! skip_past_char (&str
, ']'))
1235 typeinfo_first
.index
= exp
.X_add_number
;
1239 set_first_syntax_error (_("expected index"));
1246 set_first_syntax_error (_("too many registers in vector register list"));
1249 else if (nb_regs
== 0)
1251 set_first_syntax_error (_("empty vector register list"));
1257 *vectype
= typeinfo_first
;
1259 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1262 /* Directives: register aliases. */
1265 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1270 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1273 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1276 /* Only warn about a redefinition if it's not defined as the
1278 else if (new->number
!= number
|| new->type
!= type
)
1279 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1284 name
= xstrdup (str
);
1285 new = XNEW (reg_entry
);
1288 new->number
= number
;
1290 new->builtin
= FALSE
;
1292 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1298 /* Look for the .req directive. This is of the form:
1300 new_register_name .req existing_register_name
1302 If we find one, or if it looks sufficiently like one that we want to
1303 handle any error here, return TRUE. Otherwise return FALSE. */
1306 create_register_alias (char *newname
, char *p
)
1308 const reg_entry
*old
;
1309 char *oldname
, *nbuf
;
1312 /* The input scrubber ensures that whitespace after the mnemonic is
1313 collapsed to single spaces. */
1315 if (strncmp (oldname
, " .req ", 6) != 0)
1319 if (*oldname
== '\0')
1322 old
= hash_find (aarch64_reg_hsh
, oldname
);
1325 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1329 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1330 the desired alias name, and p points to its end. If not, then
1331 the desired alias name is in the global original_case_string. */
1332 #ifdef TC_CASE_SENSITIVE
1335 newname
= original_case_string
;
1336 nlen
= strlen (newname
);
1339 nbuf
= xmemdup0 (newname
, nlen
);
1341 /* Create aliases under the new name as stated; an all-lowercase
1342 version of the new name; and an all-uppercase version of the new
1344 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1346 for (p
= nbuf
; *p
; p
++)
1349 if (strncmp (nbuf
, newname
, nlen
))
1351 /* If this attempt to create an additional alias fails, do not bother
1352 trying to create the all-lower case alias. We will fail and issue
1353 a second, duplicate error message. This situation arises when the
1354 programmer does something like:
1357 The second .req creates the "Foo" alias but then fails to create
1358 the artificial FOO alias because it has already been created by the
1360 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1367 for (p
= nbuf
; *p
; p
++)
1370 if (strncmp (nbuf
, newname
, nlen
))
1371 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1378 /* Should never be called, as .req goes between the alias and the
1379 register name, not at the beginning of the line. */
1381 s_req (int a ATTRIBUTE_UNUSED
)
1383 as_bad (_("invalid syntax for .req directive"));
1386 /* The .unreq directive deletes an alias which was previously defined
1387 by .req. For example:
1393 s_unreq (int a ATTRIBUTE_UNUSED
)
1398 name
= input_line_pointer
;
1400 while (*input_line_pointer
!= 0
1401 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1402 ++input_line_pointer
;
1404 saved_char
= *input_line_pointer
;
1405 *input_line_pointer
= 0;
1408 as_bad (_("invalid syntax for .unreq directive"));
1411 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1414 as_bad (_("unknown register alias '%s'"), name
);
1415 else if (reg
->builtin
)
1416 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1423 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1424 free ((char *) reg
->name
);
1427 /* Also locate the all upper case and all lower case versions.
1428 Do not complain if we cannot find one or the other as it
1429 was probably deleted above. */
1431 nbuf
= strdup (name
);
1432 for (p
= nbuf
; *p
; p
++)
1434 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1437 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1438 free ((char *) reg
->name
);
1442 for (p
= nbuf
; *p
; p
++)
1444 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1447 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1448 free ((char *) reg
->name
);
1456 *input_line_pointer
= saved_char
;
1457 demand_empty_rest_of_line ();
1460 /* Directives: Instruction set selection. */
1463 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1464 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1465 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1466 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1468 /* Create a new mapping symbol for the transition to STATE. */
1471 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1474 const char *symname
;
1481 type
= BSF_NO_FLAGS
;
1485 type
= BSF_NO_FLAGS
;
1491 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1492 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1494 /* Save the mapping symbols for future reference. Also check that
1495 we do not place two mapping symbols at the same offset within a
1496 frag. We'll handle overlap between frags in
1497 check_mapping_symbols.
1499 If .fill or other data filling directive generates zero sized data,
1500 the mapping symbol for the following code will have the same value
1501 as the one generated for the data filling directive. In this case,
1502 we replace the old symbol with the new one at the same address. */
1505 if (frag
->tc_frag_data
.first_map
!= NULL
)
1507 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1508 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1511 frag
->tc_frag_data
.first_map
= symbolP
;
1513 if (frag
->tc_frag_data
.last_map
!= NULL
)
1515 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1516 S_GET_VALUE (symbolP
));
1517 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1518 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1521 frag
->tc_frag_data
.last_map
= symbolP
;
1524 /* We must sometimes convert a region marked as code to data during
1525 code alignment, if an odd number of bytes have to be padded. The
1526 code mapping symbol is pushed to an aligned address. */
1529 insert_data_mapping_symbol (enum mstate state
,
1530 valueT value
, fragS
* frag
, offsetT bytes
)
1532 /* If there was already a mapping symbol, remove it. */
1533 if (frag
->tc_frag_data
.last_map
!= NULL
1534 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1535 frag
->fr_address
+ value
)
1537 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1541 know (frag
->tc_frag_data
.first_map
== symp
);
1542 frag
->tc_frag_data
.first_map
= NULL
;
1544 frag
->tc_frag_data
.last_map
= NULL
;
1545 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1548 make_mapping_symbol (MAP_DATA
, value
, frag
);
1549 make_mapping_symbol (state
, value
+ bytes
, frag
);
1552 static void mapping_state_2 (enum mstate state
, int max_chars
);
1554 /* Set the mapping state to STATE. Only call this when about to
1555 emit some STATE bytes to the file. */
1558 mapping_state (enum mstate state
)
1560 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1562 if (state
== MAP_INSN
)
1563 /* AArch64 instructions require 4-byte alignment. When emitting
1564 instructions into any section, record the appropriate section
1566 record_alignment (now_seg
, 2);
1568 if (mapstate
== state
)
1569 /* The mapping symbol has already been emitted.
1570 There is nothing else to do. */
1573 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1574 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1575 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1576 evaluated later in the next else. */
1578 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1580 /* Only add the symbol if the offset is > 0:
1581 if we're at the first frag, check it's size > 0;
1582 if we're not at the first frag, then for sure
1583 the offset is > 0. */
1584 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1585 const int add_symbol
= (frag_now
!= frag_first
)
1586 || (frag_now_fix () > 0);
1589 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1593 mapping_state_2 (state
, 0);
1596 /* Same as mapping_state, but MAX_CHARS bytes have already been
1597 allocated. Put the mapping symbol that far back. */
1600 mapping_state_2 (enum mstate state
, int max_chars
)
1602 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1604 if (!SEG_NORMAL (now_seg
))
1607 if (mapstate
== state
)
1608 /* The mapping symbol has already been emitted.
1609 There is nothing else to do. */
1612 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1613 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1616 #define mapping_state(x) /* nothing */
1617 #define mapping_state_2(x, y) /* nothing */
1620 /* Directives: sectioning and alignment. */
1623 s_bss (int ignore ATTRIBUTE_UNUSED
)
1625 /* We don't support putting frags in the BSS segment, we fake it by
1626 marking in_bss, then looking at s_skip for clues. */
1627 subseg_set (bss_section
, 0);
1628 demand_empty_rest_of_line ();
1629 mapping_state (MAP_DATA
);
1633 s_even (int ignore ATTRIBUTE_UNUSED
)
1635 /* Never make frag if expect extra pass. */
1637 frag_align (1, 0, 0);
1639 record_alignment (now_seg
, 1);
1641 demand_empty_rest_of_line ();
1644 /* Directives: Literal pools. */
1646 static literal_pool
*
1647 find_literal_pool (int size
)
1651 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1653 if (pool
->section
== now_seg
1654 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1661 static literal_pool
*
1662 find_or_make_literal_pool (int size
)
1664 /* Next literal pool ID number. */
1665 static unsigned int latest_pool_num
= 1;
1668 pool
= find_literal_pool (size
);
1672 /* Create a new pool. */
1673 pool
= XNEW (literal_pool
);
1677 /* Currently we always put the literal pool in the current text
1678 section. If we were generating "small" model code where we
1679 knew that all code and initialised data was within 1MB then
1680 we could output literals to mergeable, read-only data
1683 pool
->next_free_entry
= 0;
1684 pool
->section
= now_seg
;
1685 pool
->sub_section
= now_subseg
;
1687 pool
->next
= list_of_pools
;
1688 pool
->symbol
= NULL
;
1690 /* Add it to the list. */
1691 list_of_pools
= pool
;
1694 /* New pools, and emptied pools, will have a NULL symbol. */
1695 if (pool
->symbol
== NULL
)
1697 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1698 (valueT
) 0, &zero_address_frag
);
1699 pool
->id
= latest_pool_num
++;
1706 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1707 Return TRUE on success, otherwise return FALSE. */
1709 add_to_lit_pool (expressionS
*exp
, int size
)
1714 pool
= find_or_make_literal_pool (size
);
1716 /* Check if this literal value is already in the pool. */
1717 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1719 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1721 if ((litexp
->X_op
== exp
->X_op
)
1722 && (exp
->X_op
== O_constant
)
1723 && (litexp
->X_add_number
== exp
->X_add_number
)
1724 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1727 if ((litexp
->X_op
== exp
->X_op
)
1728 && (exp
->X_op
== O_symbol
)
1729 && (litexp
->X_add_number
== exp
->X_add_number
)
1730 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1731 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1735 /* Do we need to create a new entry? */
1736 if (entry
== pool
->next_free_entry
)
1738 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1740 set_syntax_error (_("literal pool overflow"));
1744 pool
->literals
[entry
].exp
= *exp
;
1745 pool
->next_free_entry
+= 1;
1746 if (exp
->X_op
== O_big
)
1748 /* PR 16688: Bignums are held in a single global array. We must
1749 copy and preserve that value now, before it is overwritten. */
1750 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1752 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1753 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1756 pool
->literals
[entry
].bignum
= NULL
;
1759 exp
->X_op
= O_symbol
;
1760 exp
->X_add_number
= ((int) entry
) * size
;
1761 exp
->X_add_symbol
= pool
->symbol
;
1766 /* Can't use symbol_new here, so have to create a symbol and then at
1767 a later date assign it a value. That's what these functions do. */
1770 symbol_locate (symbolS
* symbolP
,
1771 const char *name
,/* It is copied, the caller can modify. */
1772 segT segment
, /* Segment identifier (SEG_<something>). */
1773 valueT valu
, /* Symbol value. */
1774 fragS
* frag
) /* Associated fragment. */
1777 char *preserved_copy_of_name
;
1779 name_length
= strlen (name
) + 1; /* +1 for \0. */
1780 obstack_grow (¬es
, name
, name_length
);
1781 preserved_copy_of_name
= obstack_finish (¬es
);
1783 #ifdef tc_canonicalize_symbol_name
1784 preserved_copy_of_name
=
1785 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1788 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1790 S_SET_SEGMENT (symbolP
, segment
);
1791 S_SET_VALUE (symbolP
, valu
);
1792 symbol_clear_list_pointers (symbolP
);
1794 symbol_set_frag (symbolP
, frag
);
1796 /* Link to end of symbol chain. */
1798 extern int symbol_table_frozen
;
1800 if (symbol_table_frozen
)
1804 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1806 obj_symbol_new_hook (symbolP
);
1808 #ifdef tc_symbol_new_hook
1809 tc_symbol_new_hook (symbolP
);
1813 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1814 #endif /* DEBUG_SYMS */
1819 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1826 for (align
= 2; align
<= 4; align
++)
1828 int size
= 1 << align
;
1830 pool
= find_literal_pool (size
);
1831 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1834 /* Align pool as you have word accesses.
1835 Only make a frag if we have to. */
1837 frag_align (align
, 0, 0);
1839 mapping_state (MAP_DATA
);
1841 record_alignment (now_seg
, align
);
1843 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1845 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1846 (valueT
) frag_now_fix (), frag_now
);
1847 symbol_table_insert (pool
->symbol
);
1849 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1851 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1853 if (exp
->X_op
== O_big
)
1855 /* PR 16688: Restore the global bignum value. */
1856 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1857 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1858 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1861 /* First output the expression in the instruction to the pool. */
1862 emit_expr (exp
, size
); /* .word|.xword */
1864 if (exp
->X_op
== O_big
)
1866 free (pool
->literals
[entry
].bignum
);
1867 pool
->literals
[entry
].bignum
= NULL
;
1871 /* Mark the pool as empty. */
1872 pool
->next_free_entry
= 0;
1873 pool
->symbol
= NULL
;
1878 /* Forward declarations for functions below, in the MD interface
1880 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1881 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1883 /* Directives: Data. */
1884 /* N.B. the support for relocation suffix in this directive needs to be
1885 implemented properly. */
1888 s_aarch64_elf_cons (int nbytes
)
1892 #ifdef md_flush_pending_output
1893 md_flush_pending_output ();
1896 if (is_it_end_of_statement ())
1898 demand_empty_rest_of_line ();
1902 #ifdef md_cons_align
1903 md_cons_align (nbytes
);
1906 mapping_state (MAP_DATA
);
1909 struct reloc_table_entry
*reloc
;
1913 if (exp
.X_op
!= O_symbol
)
1914 emit_expr (&exp
, (unsigned int) nbytes
);
1917 skip_past_char (&input_line_pointer
, '#');
1918 if (skip_past_char (&input_line_pointer
, ':'))
1920 reloc
= find_reloc_table_entry (&input_line_pointer
);
1922 as_bad (_("unrecognized relocation suffix"));
1924 as_bad (_("unimplemented relocation suffix"));
1925 ignore_rest_of_line ();
1929 emit_expr (&exp
, (unsigned int) nbytes
);
1932 while (*input_line_pointer
++ == ',');
1934 /* Put terminator back into stream. */
1935 input_line_pointer
--;
1936 demand_empty_rest_of_line ();
1939 /* Mark symbol that it follows a variant PCS convention. */
1942 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1948 elf_symbol_type
*elfsym
;
1950 c
= get_symbol_name (&name
);
1952 as_bad (_("Missing symbol name in directive"));
1953 sym
= symbol_find_or_make (name
);
1954 restore_line_pointer (c
);
1955 demand_empty_rest_of_line ();
1956 bfdsym
= symbol_get_bfdsym (sym
);
1957 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
1958 gas_assert (elfsym
);
1959 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1961 #endif /* OBJ_ELF */
1963 /* Output a 32-bit word, but mark as an instruction. */
1966 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1970 #ifdef md_flush_pending_output
1971 md_flush_pending_output ();
1974 if (is_it_end_of_statement ())
1976 demand_empty_rest_of_line ();
1980 /* Sections are assumed to start aligned. In executable section, there is no
1981 MAP_DATA symbol pending. So we only align the address during
1982 MAP_DATA --> MAP_INSN transition.
1983 For other sections, this is not guaranteed. */
1984 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1985 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1986 frag_align_code (2, 0);
1989 mapping_state (MAP_INSN
);
1995 if (exp
.X_op
!= O_constant
)
1997 as_bad (_("constant expression required"));
1998 ignore_rest_of_line ();
2002 if (target_big_endian
)
2004 unsigned int val
= exp
.X_add_number
;
2005 exp
.X_add_number
= SWAP_32 (val
);
2007 emit_expr (&exp
, 4);
2009 while (*input_line_pointer
++ == ',');
2011 /* Put terminator back into stream. */
2012 input_line_pointer
--;
2013 demand_empty_rest_of_line ();
2017 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2019 demand_empty_rest_of_line ();
2020 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2021 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2025 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2028 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2034 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2035 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2037 demand_empty_rest_of_line ();
2040 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2043 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2047 /* Since we're just labelling the code, there's no need to define a
2050 /* Make sure there is enough room in this frag for the following
2051 blr. This trick only works if the blr follows immediately after
2052 the .tlsdesc directive. */
2054 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2055 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2057 demand_empty_rest_of_line ();
2060 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2063 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2069 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2070 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2072 demand_empty_rest_of_line ();
2074 #endif /* OBJ_ELF */
2076 static void s_aarch64_arch (int);
2077 static void s_aarch64_cpu (int);
2078 static void s_aarch64_arch_extension (int);
2080 /* This table describes all the machine specific pseudo-ops the assembler
2081 has to support. The fields are:
2082 pseudo-op name without dot
2083 function to call to execute this pseudo-op
2084 Integer arg to pass to the function. */
2086 const pseudo_typeS md_pseudo_table
[] = {
2087 /* Never called because '.req' does not start a line. */
2089 {"unreq", s_unreq
, 0},
2091 {"even", s_even
, 0},
2092 {"ltorg", s_ltorg
, 0},
2093 {"pool", s_ltorg
, 0},
2094 {"cpu", s_aarch64_cpu
, 0},
2095 {"arch", s_aarch64_arch
, 0},
2096 {"arch_extension", s_aarch64_arch_extension
, 0},
2097 {"inst", s_aarch64_inst
, 0},
2098 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2100 {"tlsdescadd", s_tlsdescadd
, 0},
2101 {"tlsdesccall", s_tlsdesccall
, 0},
2102 {"tlsdescldr", s_tlsdescldr
, 0},
2103 {"word", s_aarch64_elf_cons
, 4},
2104 {"long", s_aarch64_elf_cons
, 4},
2105 {"xword", s_aarch64_elf_cons
, 8},
2106 {"dword", s_aarch64_elf_cons
, 8},
2107 {"variant_pcs", s_variant_pcs
, 0},
2109 {"float16", float_cons
, 'h'},
2114 /* Check whether STR points to a register name followed by a comma or the
2115 end of line; REG_TYPE indicates which register types are checked
2116 against. Return TRUE if STR is such a register name; otherwise return
2117 FALSE. The function does not intend to produce any diagnostics, but since
2118 the register parser aarch64_reg_parse, which is called by this function,
2119 does produce diagnostics, we call clear_error to clear any diagnostics
2120 that may be generated by aarch64_reg_parse.
2121 Also, the function returns FALSE directly if there is any user error
2122 present at the function entry. This prevents the existing diagnostics
2123 state from being spoiled.
2124 The function currently serves parse_constant_immediate and
2125 parse_big_immediate only. */
2127 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2131 /* Prevent the diagnostics state from being spoiled. */
2135 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2137 /* Clear the parsing error that may be set by the reg parser. */
2140 if (reg
== PARSE_FAIL
)
2143 skip_whitespace (str
);
2144 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2150 /* Parser functions used exclusively in instruction operands. */
2152 /* Parse an immediate expression which may not be constant.
2154 To prevent the expression parser from pushing a register name
2155 into the symbol table as an undefined symbol, firstly a check is
2156 done to find out whether STR is a register of type REG_TYPE followed
2157 by a comma or the end of line. Return FALSE if STR is such a string. */
2160 parse_immediate_expression (char **str
, expressionS
*exp
,
2161 aarch64_reg_type reg_type
)
2163 if (reg_name_p (*str
, reg_type
))
2165 set_recoverable_error (_("immediate operand required"));
2169 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2171 if (exp
->X_op
== O_absent
)
2173 set_fatal_syntax_error (_("missing immediate expression"));
2180 /* Constant immediate-value read function for use in insn parsing.
2181 STR points to the beginning of the immediate (with the optional
2182 leading #); *VAL receives the value. REG_TYPE says which register
2183 names should be treated as registers rather than as symbolic immediates.
2185 Return TRUE on success; otherwise return FALSE. */
2188 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2192 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2195 if (exp
.X_op
!= O_constant
)
2197 set_syntax_error (_("constant expression required"));
2201 *val
= exp
.X_add_number
;
2206 encode_imm_float_bits (uint32_t imm
)
2208 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2209 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2212 /* Return TRUE if the single-precision floating-point value encoded in IMM
2213 can be expressed in the AArch64 8-bit signed floating-point format with
2214 3-bit exponent and normalized 4 bits of precision; in other words, the
2215 floating-point value must be expressable as
2216 (+/-) n / 16 * power (2, r)
2217 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2220 aarch64_imm_float_p (uint32_t imm
)
2222 /* If a single-precision floating-point value has the following bit
2223 pattern, it can be expressed in the AArch64 8-bit floating-point
2226 3 32222222 2221111111111
2227 1 09876543 21098765432109876543210
2228 n Eeeeeexx xxxx0000000000000000000
2230 where n, e and each x are either 0 or 1 independently, with
2235 /* Prepare the pattern for 'Eeeeee'. */
2236 if (((imm
>> 30) & 0x1) == 0)
2237 pattern
= 0x3e000000;
2239 pattern
= 0x40000000;
2241 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2242 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2245 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2246 as an IEEE float without any loss of precision. Store the value in
2250 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2252 /* If a double-precision floating-point value has the following bit
2253 pattern, it can be expressed in a float:
2255 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2256 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2257 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2259 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2260 if Eeee_eeee != 1111_1111
2262 where n, e, s and S are either 0 or 1 independently and where ~ is the
2266 uint32_t high32
= imm
>> 32;
2267 uint32_t low32
= imm
;
2269 /* Lower 29 bits need to be 0s. */
2270 if ((imm
& 0x1fffffff) != 0)
2273 /* Prepare the pattern for 'Eeeeeeeee'. */
2274 if (((high32
>> 30) & 0x1) == 0)
2275 pattern
= 0x38000000;
2277 pattern
= 0x40000000;
2280 if ((high32
& 0x78000000) != pattern
)
2283 /* Check Eeee_eeee != 1111_1111. */
2284 if ((high32
& 0x7ff00000) == 0x47f00000)
2287 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2288 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2289 | (low32
>> 29)); /* 3 S bits. */
2293 /* Return true if we should treat OPERAND as a double-precision
2294 floating-point operand rather than a single-precision one. */
2296 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2298 /* Check for unsuffixed SVE registers, which are allowed
2299 for LDR and STR but not in instructions that require an
2300 immediate. We get better error messages if we arbitrarily
2301 pick one size, parse the immediate normally, and then
2302 report the match failure in the normal way. */
2303 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2304 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2307 /* Parse a floating-point immediate. Return TRUE on success and return the
2308 value in *IMMED in the format of IEEE754 single-precision encoding.
2309 *CCP points to the start of the string; DP_P is TRUE when the immediate
2310 is expected to be in double-precision (N.B. this only matters when
2311 hexadecimal representation is involved). REG_TYPE says which register
2312 names should be treated as registers rather than as symbolic immediates.
2314 This routine accepts any IEEE float; it is up to the callers to reject
2318 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2319 aarch64_reg_type reg_type
)
2323 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2325 unsigned fpword
= 0;
2326 bfd_boolean hex_p
= FALSE
;
2328 skip_past_char (&str
, '#');
2331 skip_whitespace (fpnum
);
2333 if (strncmp (fpnum
, "0x", 2) == 0)
2335 /* Support the hexadecimal representation of the IEEE754 encoding.
2336 Double-precision is expected when DP_P is TRUE, otherwise the
2337 representation should be in single-precision. */
2338 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2343 if (!can_convert_double_to_float (val
, &fpword
))
2346 else if ((uint64_t) val
> 0xffffffff)
2353 else if (reg_name_p (str
, reg_type
))
2355 set_recoverable_error (_("immediate operand required"));
2363 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2366 /* Our FP word must be 32 bits (single-precision FP). */
2367 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2369 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2379 set_fatal_syntax_error (_("invalid floating-point constant"));
2383 /* Less-generic immediate-value read function with the possibility of loading
2384 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2387 To prevent the expression parser from pushing a register name into the
2388 symbol table as an undefined symbol, a check is firstly done to find
2389 out whether STR is a register of type REG_TYPE followed by a comma or
2390 the end of line. Return FALSE if STR is such a register. */
2393 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2397 if (reg_name_p (ptr
, reg_type
))
2399 set_syntax_error (_("immediate operand required"));
2403 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2405 if (inst
.reloc
.exp
.X_op
== O_constant
)
2406 *imm
= inst
.reloc
.exp
.X_add_number
;
2413 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2414 if NEED_LIBOPCODES is non-zero, the fixup will need
2415 assistance from the libopcodes. */
2418 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2419 const aarch64_opnd_info
*operand
,
2420 int need_libopcodes_p
)
2422 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2423 reloc
->opnd
= operand
->type
;
2424 if (need_libopcodes_p
)
2425 reloc
->need_libopcodes_p
= 1;
2428 /* Return TRUE if the instruction needs to be fixed up later internally by
2429 the GAS; otherwise return FALSE. */
2431 static inline bfd_boolean
2432 aarch64_gas_internal_fixup_p (void)
2434 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2437 /* Assign the immediate value to the relevant field in *OPERAND if
2438 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2439 needs an internal fixup in a later stage.
2440 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2441 IMM.VALUE that may get assigned with the constant. */
2443 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2444 aarch64_opnd_info
*operand
,
2446 int need_libopcodes_p
,
2449 if (reloc
->exp
.X_op
== O_constant
)
2452 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2454 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2455 reloc
->type
= BFD_RELOC_UNUSED
;
2459 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2460 /* Tell libopcodes to ignore this operand or not. This is helpful
2461 when one of the operands needs to be fixed up later but we need
2462 libopcodes to check the other operands. */
2463 operand
->skip
= skip_p
;
2467 /* Relocation modifiers. Each entry in the table contains the textual
2468 name for the relocation which may be placed before a symbol used as
2469 a load/store offset, or add immediate. It must be surrounded by a
2470 leading and trailing colon, for example:
2472 ldr x0, [x1, #:rello:varsym]
2473 add x0, x1, #:rello:varsym */
2475 struct reloc_table_entry
2479 bfd_reloc_code_real_type adr_type
;
2480 bfd_reloc_code_real_type adrp_type
;
2481 bfd_reloc_code_real_type movw_type
;
2482 bfd_reloc_code_real_type add_type
;
2483 bfd_reloc_code_real_type ldst_type
;
2484 bfd_reloc_code_real_type ld_literal_type
;
2487 static struct reloc_table_entry reloc_table
[] = {
2488 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2493 BFD_RELOC_AARCH64_ADD_LO12
,
2494 BFD_RELOC_AARCH64_LDST_LO12
,
2497 /* Higher 21 bits of pc-relative page offset: ADRP */
2500 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2506 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2509 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2515 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2519 BFD_RELOC_AARCH64_MOVW_G0
,
2524 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2528 BFD_RELOC_AARCH64_MOVW_G0_S
,
2533 /* Less significant bits 0-15 of address/value: MOVK, no check */
2537 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2542 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2546 BFD_RELOC_AARCH64_MOVW_G1
,
2551 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2555 BFD_RELOC_AARCH64_MOVW_G1_S
,
2560 /* Less significant bits 16-31 of address/value: MOVK, no check */
2564 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2569 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2573 BFD_RELOC_AARCH64_MOVW_G2
,
2578 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2582 BFD_RELOC_AARCH64_MOVW_G2_S
,
2587 /* Less significant bits 32-47 of address/value: MOVK, no check */
2591 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2596 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2600 BFD_RELOC_AARCH64_MOVW_G3
,
2605 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2609 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2614 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2618 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2623 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2627 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2632 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2636 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2641 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2645 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2650 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2654 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2659 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2663 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2668 /* Get to the page containing GOT entry for a symbol. */
2671 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2675 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2677 /* 12 bit offset into the page containing GOT entry for that symbol. */
2683 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2686 /* 0-15 bits of address/value: MOVk, no check. */
2690 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2695 /* Most significant bits 16-31 of address/value: MOVZ. */
2699 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2704 /* 15 bit offset into the page containing GOT entry for that symbol. */
2710 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2713 /* Get to the page containing GOT TLS entry for a symbol */
2714 {"gottprel_g0_nc", 0,
2717 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2722 /* Get to the page containing GOT TLS entry for a symbol */
2726 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2731 /* Get to the page containing GOT TLS entry for a symbol */
2733 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2734 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2740 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2745 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2749 /* Lower 16 bits address/value: MOVk. */
2753 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2758 /* Most significant bits 16-31 of address/value: MOVZ. */
2762 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2767 /* Get to the page containing GOT TLS entry for a symbol */
2769 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2770 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2774 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2776 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2781 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2782 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2785 /* Get to the page containing GOT TLS entry for a symbol.
2786 The same as GD, we allocate two consecutive GOT slots
2787 for module index and module offset, the only difference
2788 with GD is the module offset should be initialized to
2789 zero without any outstanding runtime relocation. */
2791 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2792 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2798 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2799 {"tlsldm_lo12_nc", 0,
2803 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2807 /* 12 bit offset into the module TLS base address. */
2812 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2813 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2816 /* Same as dtprel_lo12, no overflow check. */
2817 {"dtprel_lo12_nc", 0,
2821 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2822 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2825 /* bits[23:12] of offset to the module TLS base address. */
2830 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2834 /* bits[15:0] of offset to the module TLS base address. */
2838 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2843 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2847 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2852 /* bits[31:16] of offset to the module TLS base address. */
2856 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2861 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2865 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2870 /* bits[47:32] of offset to the module TLS base address. */
2874 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2879 /* Lower 16 bit offset into GOT entry for a symbol */
2880 {"tlsdesc_off_g0_nc", 0,
2883 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2888 /* Higher 16 bit offset into GOT entry for a symbol */
2889 {"tlsdesc_off_g1", 0,
2892 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2897 /* Get to the page containing GOT TLS entry for a symbol */
2900 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2904 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2906 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2907 {"gottprel_lo12", 0,
2912 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2915 /* Get tp offset for a symbol. */
2920 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2924 /* Get tp offset for a symbol. */
2929 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2930 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2933 /* Get tp offset for a symbol. */
2938 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2942 /* Get tp offset for a symbol. */
2943 {"tprel_lo12_nc", 0,
2947 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2948 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2951 /* Most significant bits 32-47 of address/value: MOVZ. */
2955 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2960 /* Most significant bits 16-31 of address/value: MOVZ. */
2964 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2969 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2973 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2978 /* Most significant bits 0-15 of address/value: MOVZ. */
2982 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2987 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2991 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2996 /* 15bit offset from got entry to base address of GOT table. */
3002 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3005 /* 14bit offset from got entry to base address of GOT table. */
3011 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3015 /* Given the address of a pointer pointing to the textual name of a
3016 relocation as may appear in assembler source, attempt to find its
3017 details in reloc_table. The pointer will be updated to the character
3018 after the trailing colon. On failure, NULL will be returned;
3019 otherwise return the reloc_table_entry. */
3021 static struct reloc_table_entry
*
3022 find_reloc_table_entry (char **str
)
3025 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3027 int length
= strlen (reloc_table
[i
].name
);
3029 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3030 && (*str
)[length
] == ':')
3032 *str
+= (length
+ 1);
3033 return &reloc_table
[i
];
3040 /* Mode argument to parse_shift and parser_shifter_operand. */
3041 enum parse_shift_mode
3043 SHIFTED_NONE
, /* no shifter allowed */
3044 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3046 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3048 SHIFTED_LSL
, /* bare "lsl #n" */
3049 SHIFTED_MUL
, /* bare "mul #n" */
3050 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3051 SHIFTED_MUL_VL
, /* "mul vl" */
3052 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3055 /* Parse a <shift> operator on an AArch64 data processing instruction.
3056 Return TRUE on success; otherwise return FALSE. */
3058 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3060 const struct aarch64_name_value_pair
*shift_op
;
3061 enum aarch64_modifier_kind kind
;
3067 for (p
= *str
; ISALPHA (*p
); p
++)
3072 set_syntax_error (_("shift expression expected"));
3076 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3078 if (shift_op
== NULL
)
3080 set_syntax_error (_("shift operator expected"));
3084 kind
= aarch64_get_operand_modifier (shift_op
);
3086 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3088 set_syntax_error (_("invalid use of 'MSL'"));
3092 if (kind
== AARCH64_MOD_MUL
3093 && mode
!= SHIFTED_MUL
3094 && mode
!= SHIFTED_MUL_VL
)
3096 set_syntax_error (_("invalid use of 'MUL'"));
3102 case SHIFTED_LOGIC_IMM
:
3103 if (aarch64_extend_operator_p (kind
))
3105 set_syntax_error (_("extending shift is not permitted"));
3110 case SHIFTED_ARITH_IMM
:
3111 if (kind
== AARCH64_MOD_ROR
)
3113 set_syntax_error (_("'ROR' shift is not permitted"));
3119 if (kind
!= AARCH64_MOD_LSL
)
3121 set_syntax_error (_("only 'LSL' shift is permitted"));
3127 if (kind
!= AARCH64_MOD_MUL
)
3129 set_syntax_error (_("only 'MUL' is permitted"));
3134 case SHIFTED_MUL_VL
:
3135 /* "MUL VL" consists of two separate tokens. Require the first
3136 token to be "MUL" and look for a following "VL". */
3137 if (kind
== AARCH64_MOD_MUL
)
3139 skip_whitespace (p
);
3140 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3143 kind
= AARCH64_MOD_MUL_VL
;
3147 set_syntax_error (_("only 'MUL VL' is permitted"));
3150 case SHIFTED_REG_OFFSET
:
3151 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3152 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3154 set_fatal_syntax_error
3155 (_("invalid shift for the register offset addressing mode"));
3160 case SHIFTED_LSL_MSL
:
3161 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3163 set_syntax_error (_("invalid shift operator"));
3172 /* Whitespace can appear here if the next thing is a bare digit. */
3173 skip_whitespace (p
);
3175 /* Parse shift amount. */
3177 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3178 exp
.X_op
= O_absent
;
3181 if (is_immediate_prefix (*p
))
3186 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3188 if (kind
== AARCH64_MOD_MUL_VL
)
3189 /* For consistency, give MUL VL the same shift amount as an implicit
3191 operand
->shifter
.amount
= 1;
3192 else if (exp
.X_op
== O_absent
)
3194 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3196 set_syntax_error (_("missing shift amount"));
3199 operand
->shifter
.amount
= 0;
3201 else if (exp
.X_op
!= O_constant
)
3203 set_syntax_error (_("constant shift amount required"));
3206 /* For parsing purposes, MUL #n has no inherent range. The range
3207 depends on the operand and will be checked by operand-specific
3209 else if (kind
!= AARCH64_MOD_MUL
3210 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3212 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3217 operand
->shifter
.amount
= exp
.X_add_number
;
3218 operand
->shifter
.amount_present
= 1;
3221 operand
->shifter
.operator_present
= 1;
3222 operand
->shifter
.kind
= kind
;
3228 /* Parse a <shifter_operand> for a data processing instruction:
3231 #<immediate>, LSL #imm
3233 Validation of immediate operands is deferred to md_apply_fix.
3235 Return TRUE on success; otherwise return FALSE. */
3238 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3239 enum parse_shift_mode mode
)
3243 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3248 /* Accept an immediate expression. */
3249 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3252 /* Accept optional LSL for arithmetic immediate values. */
3253 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3254 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3257 /* Not accept any shifter for logical immediate values. */
3258 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3259 && parse_shift (&p
, operand
, mode
))
3261 set_syntax_error (_("unexpected shift operator"));
3269 /* Parse a <shifter_operand> for a data processing instruction:
3274 #<immediate>, LSL #imm
3276 where <shift> is handled by parse_shift above, and the last two
3277 cases are handled by the function above.
3279 Validation of immediate operands is deferred to md_apply_fix.
3281 Return TRUE on success; otherwise return FALSE. */
3284 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3285 enum parse_shift_mode mode
)
3287 const reg_entry
*reg
;
3288 aarch64_opnd_qualifier_t qualifier
;
3289 enum aarch64_operand_class opd_class
3290 = aarch64_get_operand_class (operand
->type
);
3292 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3295 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3297 set_syntax_error (_("unexpected register in the immediate operand"));
3301 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3303 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3307 operand
->reg
.regno
= reg
->number
;
3308 operand
->qualifier
= qualifier
;
3310 /* Accept optional shift operation on register. */
3311 if (! skip_past_comma (str
))
3314 if (! parse_shift (str
, operand
, mode
))
3319 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3322 (_("integer register expected in the extended/shifted operand "
3327 /* We have a shifted immediate variable. */
3328 return parse_shifter_operand_imm (str
, operand
, mode
);
3331 /* Return TRUE on success; return FALSE otherwise. */
3334 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3335 enum parse_shift_mode mode
)
3339 /* Determine if we have the sequence of characters #: or just :
3340 coming next. If we do, then we check for a :rello: relocation
3341 modifier. If we don't, punt the whole lot to
3342 parse_shifter_operand. */
3344 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3346 struct reloc_table_entry
*entry
;
3354 /* Try to parse a relocation. Anything else is an error. */
3355 if (!(entry
= find_reloc_table_entry (str
)))
3357 set_syntax_error (_("unknown relocation modifier"));
3361 if (entry
->add_type
== 0)
3364 (_("this relocation modifier is not allowed on this instruction"));
3368 /* Save str before we decompose it. */
3371 /* Next, we parse the expression. */
3372 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3375 /* Record the relocation type (use the ADD variant here). */
3376 inst
.reloc
.type
= entry
->add_type
;
3377 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3379 /* If str is empty, we've reached the end, stop here. */
3383 /* Otherwise, we have a shifted reloc modifier, so rewind to
3384 recover the variable name and continue parsing for the shifter. */
3386 return parse_shifter_operand_imm (str
, operand
, mode
);
3389 return parse_shifter_operand (str
, operand
, mode
);
3392 /* Parse all forms of an address expression. Information is written
3393 to *OPERAND and/or inst.reloc.
3395 The A64 instruction set has the following addressing modes:
3398 [base] // in SIMD ld/st structure
3399 [base{,#0}] // in ld/st exclusive
3401 [base,Xm{,LSL #imm}]
3402 [base,Xm,SXTX {#imm}]
3403 [base,Wm,(S|U)XTW {#imm}]
3405 [base]! // in ldraa/ldrab exclusive
3409 [base],Xm // in SIMD ld/st structure
3410 PC-relative (literal)
3414 [base,Zm.D{,LSL #imm}]
3415 [base,Zm.S,(S|U)XTW {#imm}]
3416 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3420 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3421 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3422 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3424 (As a convenience, the notation "=immediate" is permitted in conjunction
3425 with the pc-relative literal load instructions to automatically place an
3426 immediate value or symbolic address in a nearby literal pool and generate
3427 a hidden label which references it.)
3429 Upon a successful parsing, the address structure in *OPERAND will be
3430 filled in the following way:
3432 .base_regno = <base>
3433 .offset.is_reg // 1 if the offset is a register
3435 .offset.regno = <Rm>
3437 For different addressing modes defined in the A64 ISA:
3440 .pcrel=0; .preind=1; .postind=0; .writeback=0
3442 .pcrel=0; .preind=1; .postind=0; .writeback=1
3444 .pcrel=0; .preind=0; .postind=1; .writeback=1
3445 PC-relative (literal)
3446 .pcrel=1; .preind=1; .postind=0; .writeback=0
3448 The shift/extension information, if any, will be stored in .shifter.
3449 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3450 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3451 corresponding register.
3453 BASE_TYPE says which types of base register should be accepted and
3454 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3455 is the type of shifter that is allowed for immediate offsets,
3456 or SHIFTED_NONE if none.
3458 In all other respects, it is the caller's responsibility to check
3459 for addressing modes not supported by the instruction, and to set
3463 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3464 aarch64_opnd_qualifier_t
*base_qualifier
,
3465 aarch64_opnd_qualifier_t
*offset_qualifier
,
3466 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3467 enum parse_shift_mode imm_shift_mode
)
3470 const reg_entry
*reg
;
3471 expressionS
*exp
= &inst
.reloc
.exp
;
3473 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3474 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3475 if (! skip_past_char (&p
, '['))
3477 /* =immediate or label. */
3478 operand
->addr
.pcrel
= 1;
3479 operand
->addr
.preind
= 1;
3481 /* #:<reloc_op>:<symbol> */
3482 skip_past_char (&p
, '#');
3483 if (skip_past_char (&p
, ':'))
3485 bfd_reloc_code_real_type ty
;
3486 struct reloc_table_entry
*entry
;
3488 /* Try to parse a relocation modifier. Anything else is
3490 entry
= find_reloc_table_entry (&p
);
3493 set_syntax_error (_("unknown relocation modifier"));
3497 switch (operand
->type
)
3499 case AARCH64_OPND_ADDR_PCREL21
:
3501 ty
= entry
->adr_type
;
3505 ty
= entry
->ld_literal_type
;
3512 (_("this relocation modifier is not allowed on this "
3518 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3520 set_syntax_error (_("invalid relocation expression"));
3524 /* #:<reloc_op>:<expr> */
3525 /* Record the relocation type. */
3526 inst
.reloc
.type
= ty
;
3527 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3532 if (skip_past_char (&p
, '='))
3533 /* =immediate; need to generate the literal in the literal pool. */
3534 inst
.gen_lit_pool
= 1;
3536 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3538 set_syntax_error (_("invalid address"));
3549 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3550 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3552 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3555 operand
->addr
.base_regno
= reg
->number
;
3558 if (skip_past_comma (&p
))
3561 operand
->addr
.preind
= 1;
3563 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3566 if (!aarch64_check_reg_type (reg
, offset_type
))
3568 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3573 operand
->addr
.offset
.regno
= reg
->number
;
3574 operand
->addr
.offset
.is_reg
= 1;
3575 /* Shifted index. */
3576 if (skip_past_comma (&p
))
3579 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3580 /* Use the diagnostics set in parse_shift, so not set new
3581 error message here. */
3585 [base,Xm] # For vector plus scalar SVE2 indexing.
3586 [base,Xm{,LSL #imm}]
3587 [base,Xm,SXTX {#imm}]
3588 [base,Wm,(S|U)XTW {#imm}] */
3589 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3590 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3591 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3593 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3595 set_syntax_error (_("invalid use of 32-bit register offset"));
3598 if (aarch64_get_qualifier_esize (*base_qualifier
)
3599 != aarch64_get_qualifier_esize (*offset_qualifier
)
3600 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3601 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3602 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3604 set_syntax_error (_("offset has different size from base"));
3608 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3610 set_syntax_error (_("invalid use of 64-bit register offset"));
3616 /* [Xn,#:<reloc_op>:<symbol> */
3617 skip_past_char (&p
, '#');
3618 if (skip_past_char (&p
, ':'))
3620 struct reloc_table_entry
*entry
;
3622 /* Try to parse a relocation modifier. Anything else is
3624 if (!(entry
= find_reloc_table_entry (&p
)))
3626 set_syntax_error (_("unknown relocation modifier"));
3630 if (entry
->ldst_type
== 0)
3633 (_("this relocation modifier is not allowed on this "
3638 /* [Xn,#:<reloc_op>: */
3639 /* We now have the group relocation table entry corresponding to
3640 the name in the assembler source. Next, we parse the
3642 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3644 set_syntax_error (_("invalid relocation expression"));
3648 /* [Xn,#:<reloc_op>:<expr> */
3649 /* Record the load/store relocation type. */
3650 inst
.reloc
.type
= entry
->ldst_type
;
3651 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3655 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3657 set_syntax_error (_("invalid expression in the address"));
3661 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3662 /* [Xn,<expr>,<shifter> */
3663 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3669 if (! skip_past_char (&p
, ']'))
3671 set_syntax_error (_("']' expected"));
3675 if (skip_past_char (&p
, '!'))
3677 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3679 set_syntax_error (_("register offset not allowed in pre-indexed "
3680 "addressing mode"));
3684 operand
->addr
.writeback
= 1;
3686 else if (skip_past_comma (&p
))
3689 operand
->addr
.postind
= 1;
3690 operand
->addr
.writeback
= 1;
3692 if (operand
->addr
.preind
)
3694 set_syntax_error (_("cannot combine pre- and post-indexing"));
3698 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3702 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3704 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3708 operand
->addr
.offset
.regno
= reg
->number
;
3709 operand
->addr
.offset
.is_reg
= 1;
3711 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3714 set_syntax_error (_("invalid expression in the address"));
3719 /* If at this point neither .preind nor .postind is set, we have a
3720 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3721 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3722 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3724 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3726 if (operand
->addr
.writeback
)
3728 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3730 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3731 operand
->addr
.offset
.is_reg
= 0;
3732 operand
->addr
.offset
.imm
= 0;
3733 operand
->addr
.preind
= 1;
3738 set_syntax_error (_("missing offset in the pre-indexed address"));
3744 operand
->addr
.preind
= 1;
3745 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3747 operand
->addr
.offset
.is_reg
= 1;
3748 operand
->addr
.offset
.regno
= REG_ZR
;
3749 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3753 inst
.reloc
.exp
.X_op
= O_constant
;
3754 inst
.reloc
.exp
.X_add_number
= 0;
3763 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3766 parse_address (char **str
, aarch64_opnd_info
*operand
)
3768 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3769 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3770 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3773 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3774 The arguments have the same meaning as for parse_address_main.
3775 Return TRUE on success. */
3777 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3778 aarch64_opnd_qualifier_t
*base_qualifier
,
3779 aarch64_opnd_qualifier_t
*offset_qualifier
)
3781 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3782 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3786 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3787 Return TRUE on success; otherwise return FALSE. */
3789 parse_half (char **str
, int *internal_fixup_p
)
3793 skip_past_char (&p
, '#');
3795 gas_assert (internal_fixup_p
);
3796 *internal_fixup_p
= 0;
3800 struct reloc_table_entry
*entry
;
3802 /* Try to parse a relocation. Anything else is an error. */
3804 if (!(entry
= find_reloc_table_entry (&p
)))
3806 set_syntax_error (_("unknown relocation modifier"));
3810 if (entry
->movw_type
== 0)
3813 (_("this relocation modifier is not allowed on this instruction"));
3817 inst
.reloc
.type
= entry
->movw_type
;
3820 *internal_fixup_p
= 1;
3822 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3829 /* Parse an operand for an ADRP instruction:
3831 Return TRUE on success; otherwise return FALSE. */
3834 parse_adrp (char **str
)
3841 struct reloc_table_entry
*entry
;
3843 /* Try to parse a relocation. Anything else is an error. */
3845 if (!(entry
= find_reloc_table_entry (&p
)))
3847 set_syntax_error (_("unknown relocation modifier"));
3851 if (entry
->adrp_type
== 0)
3854 (_("this relocation modifier is not allowed on this instruction"));
3858 inst
.reloc
.type
= entry
->adrp_type
;
3861 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3863 inst
.reloc
.pc_rel
= 1;
3865 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3872 /* Miscellaneous. */
3874 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3875 of SIZE tokens in which index I gives the token for field value I,
3876 or is null if field value I is invalid. REG_TYPE says which register
3877 names should be treated as registers rather than as symbolic immediates.
3879 Return true on success, moving *STR past the operand and storing the
3880 field value in *VAL. */
3883 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3884 size_t size
, aarch64_reg_type reg_type
)
3890 /* Match C-like tokens. */
3892 while (ISALNUM (*q
))
3895 for (i
= 0; i
< size
; ++i
)
3897 && strncasecmp (array
[i
], p
, q
- p
) == 0
3898 && array
[i
][q
- p
] == 0)
3905 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3908 if (exp
.X_op
== O_constant
3909 && (uint64_t) exp
.X_add_number
< size
)
3911 *val
= exp
.X_add_number
;
3916 /* Use the default error for this operand. */
3920 /* Parse an option for a preload instruction. Returns the encoding for the
3921 option, or PARSE_FAIL. */
3924 parse_pldop (char **str
)
3927 const struct aarch64_name_value_pair
*o
;
3930 while (ISALNUM (*q
))
3933 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3941 /* Parse an option for a barrier instruction. Returns the encoding for the
3942 option, or PARSE_FAIL. */
3945 parse_barrier (char **str
)
3948 const asm_barrier_opt
*o
;
3951 while (ISALPHA (*q
))
3954 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3962 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3963 return 0 if successful. Otherwise return PARSE_FAIL. */
3966 parse_barrier_psb (char **str
,
3967 const struct aarch64_name_value_pair
** hint_opt
)
3970 const struct aarch64_name_value_pair
*o
;
3973 while (ISALPHA (*q
))
3976 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3979 set_fatal_syntax_error
3980 ( _("unknown or missing option to PSB"));
3984 if (o
->value
!= 0x11)
3986 /* PSB only accepts option name 'CSYNC'. */
3988 (_("the specified option is not accepted for PSB"));
3997 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3998 return 0 if successful. Otherwise return PARSE_FAIL. */
4001 parse_bti_operand (char **str
,
4002 const struct aarch64_name_value_pair
** hint_opt
)
4005 const struct aarch64_name_value_pair
*o
;
4008 while (ISALPHA (*q
))
4011 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4014 set_fatal_syntax_error
4015 ( _("unknown option to BTI"));
4021 /* Valid BTI operands. */
4029 (_("unknown option to BTI"));
4038 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4039 Returns the encoding for the option, or PARSE_FAIL.
4041 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4042 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4044 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4045 field, otherwise as a system register.
4049 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
4050 int imple_defined_p
, int pstatefield_p
,
4055 const aarch64_sys_reg
*o
;
4059 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4061 *p
++ = TOLOWER (*q
);
4063 /* Assert that BUF be large enough. */
4064 gas_assert (p
- buf
== q
- *str
);
4066 o
= hash_find (sys_regs
, buf
);
4069 if (!imple_defined_p
)
4073 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4074 unsigned int op0
, op1
, cn
, cm
, op2
;
4076 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4079 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4081 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4088 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4089 as_bad (_("selected processor does not support PSTATE field "
4091 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4092 as_bad (_("selected processor does not support system register "
4094 if (aarch64_sys_reg_deprecated_p (o
))
4095 as_warn (_("system register name '%s' is deprecated and may be "
4096 "removed in a future release"), buf
);
4106 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4107 for the option, or NULL. */
4109 static const aarch64_sys_ins_reg
*
4110 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4114 const aarch64_sys_ins_reg
*o
;
4117 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4119 *p
++ = TOLOWER (*q
);
4122 o
= hash_find (sys_ins_regs
, buf
);
4126 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4127 as_bad (_("selected processor does not support system register "
4134 #define po_char_or_fail(chr) do { \
4135 if (! skip_past_char (&str, chr)) \
4139 #define po_reg_or_fail(regtype) do { \
4140 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4141 if (val == PARSE_FAIL) \
4143 set_default_error (); \
4148 #define po_int_reg_or_fail(reg_type) do { \
4149 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4150 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4152 set_default_error (); \
4155 info->reg.regno = reg->number; \
4156 info->qualifier = qualifier; \
4159 #define po_imm_nc_or_fail() do { \
4160 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4164 #define po_imm_or_fail(min, max) do { \
4165 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4167 if (val < min || val > max) \
4169 set_fatal_syntax_error (_("immediate value out of range "\
4170 #min " to "#max)); \
4175 #define po_enum_or_fail(array) do { \
4176 if (!parse_enum_string (&str, &val, array, \
4177 ARRAY_SIZE (array), imm_reg_type)) \
4181 #define po_misc_or_fail(expr) do { \
4186 /* encode the 12-bit imm field of Add/sub immediate */
4187 static inline uint32_t
4188 encode_addsub_imm (uint32_t imm
)
4193 /* encode the shift amount field of Add/sub immediate */
4194 static inline uint32_t
4195 encode_addsub_imm_shift_amount (uint32_t cnt
)
4201 /* encode the imm field of Adr instruction */
4202 static inline uint32_t
4203 encode_adr_imm (uint32_t imm
)
4205 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4206 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4209 /* encode the immediate field of Move wide immediate */
4210 static inline uint32_t
4211 encode_movw_imm (uint32_t imm
)
4216 /* encode the 26-bit offset of unconditional branch */
4217 static inline uint32_t
4218 encode_branch_ofs_26 (uint32_t ofs
)
4220 return ofs
& ((1 << 26) - 1);
4223 /* encode the 19-bit offset of conditional branch and compare & branch */
4224 static inline uint32_t
4225 encode_cond_branch_ofs_19 (uint32_t ofs
)
4227 return (ofs
& ((1 << 19) - 1)) << 5;
4230 /* encode the 19-bit offset of ld literal */
4231 static inline uint32_t
4232 encode_ld_lit_ofs_19 (uint32_t ofs
)
4234 return (ofs
& ((1 << 19) - 1)) << 5;
4237 /* Encode the 14-bit offset of test & branch. */
4238 static inline uint32_t
4239 encode_tst_branch_ofs_14 (uint32_t ofs
)
4241 return (ofs
& ((1 << 14) - 1)) << 5;
4244 /* Encode the 16-bit imm field of svc/hvc/smc. */
4245 static inline uint32_t
4246 encode_svc_imm (uint32_t imm
)
4251 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4252 static inline uint32_t
4253 reencode_addsub_switch_add_sub (uint32_t opcode
)
4255 return opcode
^ (1 << 30);
4258 static inline uint32_t
4259 reencode_movzn_to_movz (uint32_t opcode
)
4261 return opcode
| (1 << 30);
4264 static inline uint32_t
4265 reencode_movzn_to_movn (uint32_t opcode
)
4267 return opcode
& ~(1 << 30);
4270 /* Overall per-instruction processing. */
4272 /* We need to be able to fix up arbitrary expressions in some statements.
4273 This is so that we can handle symbols that are an arbitrary distance from
4274 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4275 which returns part of an address in a form which will be valid for
4276 a data instruction. We do this by pushing the expression into a symbol
4277 in the expr_section, and creating a fix for that. */
4280 fix_new_aarch64 (fragS
* frag
,
4282 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4292 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4296 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4303 /* Diagnostics on operands errors. */
4305 /* By default, output verbose error message.
4306 Disable the verbose error message by -mno-verbose-error. */
4307 static int verbose_error_p
= 1;
4309 #ifdef DEBUG_AARCH64
4310 /* N.B. this is only for the purpose of debugging. */
4311 const char* operand_mismatch_kind_names
[] =
4314 "AARCH64_OPDE_RECOVERABLE",
4315 "AARCH64_OPDE_SYNTAX_ERROR",
4316 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4317 "AARCH64_OPDE_INVALID_VARIANT",
4318 "AARCH64_OPDE_OUT_OF_RANGE",
4319 "AARCH64_OPDE_UNALIGNED",
4320 "AARCH64_OPDE_REG_LIST",
4321 "AARCH64_OPDE_OTHER_ERROR",
4323 #endif /* DEBUG_AARCH64 */
4325 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4327 When multiple errors of different kinds are found in the same assembly
4328 line, only the error of the highest severity will be picked up for
4329 issuing the diagnostics. */
4331 static inline bfd_boolean
4332 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4333 enum aarch64_operand_error_kind rhs
)
4335 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4336 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4337 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4338 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4339 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4340 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4341 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4342 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4346 /* Helper routine to get the mnemonic name from the assembly instruction
4347 line; should only be called for the diagnosis purpose, as there is
4348 string copy operation involved, which may affect the runtime
4349 performance if used in elsewhere. */
4352 get_mnemonic_name (const char *str
)
4354 static char mnemonic
[32];
4357 /* Get the first 15 bytes and assume that the full name is included. */
4358 strncpy (mnemonic
, str
, 31);
4359 mnemonic
[31] = '\0';
4361 /* Scan up to the end of the mnemonic, which must end in white space,
4362 '.', or end of string. */
4363 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4368 /* Append '...' to the truncated long name. */
4369 if (ptr
- mnemonic
== 31)
4370 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4376 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4378 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4379 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4382 /* Data structures storing one user error in the assembly code related to
4385 struct operand_error_record
4387 const aarch64_opcode
*opcode
;
4388 aarch64_operand_error detail
;
4389 struct operand_error_record
*next
;
4392 typedef struct operand_error_record operand_error_record
;
4394 struct operand_errors
4396 operand_error_record
*head
;
4397 operand_error_record
*tail
;
4400 typedef struct operand_errors operand_errors
;
4402 /* Top-level data structure reporting user errors for the current line of
4404 The way md_assemble works is that all opcodes sharing the same mnemonic
4405 name are iterated to find a match to the assembly line. In this data
4406 structure, each of the such opcodes will have one operand_error_record
4407 allocated and inserted. In other words, excessive errors related with
4408 a single opcode are disregarded. */
4409 operand_errors operand_error_report
;
4411 /* Free record nodes. */
4412 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4414 /* Initialize the data structure that stores the operand mismatch
4415 information on assembling one line of the assembly code. */
4417 init_operand_error_report (void)
4419 if (operand_error_report
.head
!= NULL
)
4421 gas_assert (operand_error_report
.tail
!= NULL
);
4422 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4423 free_opnd_error_record_nodes
= operand_error_report
.head
;
4424 operand_error_report
.head
= NULL
;
4425 operand_error_report
.tail
= NULL
;
4428 gas_assert (operand_error_report
.tail
== NULL
);
4431 /* Return TRUE if some operand error has been recorded during the
4432 parsing of the current assembly line using the opcode *OPCODE;
4433 otherwise return FALSE. */
4434 static inline bfd_boolean
4435 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4437 operand_error_record
*record
= operand_error_report
.head
;
4438 return record
&& record
->opcode
== opcode
;
4441 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4442 OPCODE field is initialized with OPCODE.
4443 N.B. only one record for each opcode, i.e. the maximum of one error is
4444 recorded for each instruction template. */
4447 add_operand_error_record (const operand_error_record
* new_record
)
4449 const aarch64_opcode
*opcode
= new_record
->opcode
;
4450 operand_error_record
* record
= operand_error_report
.head
;
4452 /* The record may have been created for this opcode. If not, we need
4454 if (! opcode_has_operand_error_p (opcode
))
4456 /* Get one empty record. */
4457 if (free_opnd_error_record_nodes
== NULL
)
4459 record
= XNEW (operand_error_record
);
4463 record
= free_opnd_error_record_nodes
;
4464 free_opnd_error_record_nodes
= record
->next
;
4466 record
->opcode
= opcode
;
4467 /* Insert at the head. */
4468 record
->next
= operand_error_report
.head
;
4469 operand_error_report
.head
= record
;
4470 if (operand_error_report
.tail
== NULL
)
4471 operand_error_report
.tail
= record
;
4473 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4474 && record
->detail
.index
<= new_record
->detail
.index
4475 && operand_error_higher_severity_p (record
->detail
.kind
,
4476 new_record
->detail
.kind
))
4478 /* In the case of multiple errors found on operands related with a
4479 single opcode, only record the error of the leftmost operand and
4480 only if the error is of higher severity. */
4481 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4482 " the existing error %s on operand %d",
4483 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4484 new_record
->detail
.index
,
4485 operand_mismatch_kind_names
[record
->detail
.kind
],
4486 record
->detail
.index
);
4490 record
->detail
= new_record
->detail
;
4494 record_operand_error_info (const aarch64_opcode
*opcode
,
4495 aarch64_operand_error
*error_info
)
4497 operand_error_record record
;
4498 record
.opcode
= opcode
;
4499 record
.detail
= *error_info
;
4500 add_operand_error_record (&record
);
4503 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4504 error message *ERROR, for operand IDX (count from 0). */
4507 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4508 enum aarch64_operand_error_kind kind
,
4511 aarch64_operand_error info
;
4512 memset(&info
, 0, sizeof (info
));
4516 info
.non_fatal
= FALSE
;
4517 record_operand_error_info (opcode
, &info
);
4521 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4522 enum aarch64_operand_error_kind kind
,
4523 const char* error
, const int *extra_data
)
4525 aarch64_operand_error info
;
4529 info
.data
[0] = extra_data
[0];
4530 info
.data
[1] = extra_data
[1];
4531 info
.data
[2] = extra_data
[2];
4532 info
.non_fatal
= FALSE
;
4533 record_operand_error_info (opcode
, &info
);
4537 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4538 const char* error
, int lower_bound
,
4541 int data
[3] = {lower_bound
, upper_bound
, 0};
4542 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4546 /* Remove the operand error record for *OPCODE. */
4547 static void ATTRIBUTE_UNUSED
4548 remove_operand_error_record (const aarch64_opcode
*opcode
)
4550 if (opcode_has_operand_error_p (opcode
))
4552 operand_error_record
* record
= operand_error_report
.head
;
4553 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4554 operand_error_report
.head
= record
->next
;
4555 record
->next
= free_opnd_error_record_nodes
;
4556 free_opnd_error_record_nodes
= record
;
4557 if (operand_error_report
.head
== NULL
)
4559 gas_assert (operand_error_report
.tail
== record
);
4560 operand_error_report
.tail
= NULL
;
4565 /* Given the instruction in *INSTR, return the index of the best matched
4566 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4568 Return -1 if there is no qualifier sequence; return the first match
4569 if there is multiple matches found. */
4572 find_best_match (const aarch64_inst
*instr
,
4573 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4575 int i
, num_opnds
, max_num_matched
, idx
;
4577 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4580 DEBUG_TRACE ("no operand");
4584 max_num_matched
= 0;
4587 /* For each pattern. */
4588 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4591 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4593 /* Most opcodes has much fewer patterns in the list. */
4594 if (empty_qualifier_sequence_p (qualifiers
))
4596 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4600 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4601 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4604 if (num_matched
> max_num_matched
)
4606 max_num_matched
= num_matched
;
4611 DEBUG_TRACE ("return with %d", idx
);
4615 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4616 corresponding operands in *INSTR. */
4619 assign_qualifier_sequence (aarch64_inst
*instr
,
4620 const aarch64_opnd_qualifier_t
*qualifiers
)
4623 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4624 gas_assert (num_opnds
);
4625 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4626 instr
->operands
[i
].qualifier
= *qualifiers
;
4629 /* Print operands for the diagnosis purpose. */
4632 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4633 const aarch64_opnd_info
*opnds
)
4637 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4641 /* We regard the opcode operand info more, however we also look into
4642 the inst->operands to support the disassembling of the optional
4644 The two operand code should be the same in all cases, apart from
4645 when the operand can be optional. */
4646 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4647 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4650 /* Generate the operand string in STR. */
4651 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4656 strcat (buf
, i
== 0 ? " " : ", ");
4658 /* Append the operand string. */
4663 /* Send to stderr a string as information. */
4666 output_info (const char *format
, ...)
4672 file
= as_where (&line
);
4676 fprintf (stderr
, "%s:%u: ", file
, line
);
4678 fprintf (stderr
, "%s: ", file
);
4680 fprintf (stderr
, _("Info: "));
4681 va_start (args
, format
);
4682 vfprintf (stderr
, format
, args
);
4684 (void) putc ('\n', stderr
);
4687 /* Output one operand error record. */
4690 output_operand_error_record (const operand_error_record
*record
, char *str
)
4692 const aarch64_operand_error
*detail
= &record
->detail
;
4693 int idx
= detail
->index
;
4694 const aarch64_opcode
*opcode
= record
->opcode
;
4695 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4696 : AARCH64_OPND_NIL
);
4698 typedef void (*handler_t
)(const char *format
, ...);
4699 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4701 switch (detail
->kind
)
4703 case AARCH64_OPDE_NIL
:
4706 case AARCH64_OPDE_SYNTAX_ERROR
:
4707 case AARCH64_OPDE_RECOVERABLE
:
4708 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4709 case AARCH64_OPDE_OTHER_ERROR
:
4710 /* Use the prepared error message if there is, otherwise use the
4711 operand description string to describe the error. */
4712 if (detail
->error
!= NULL
)
4715 handler (_("%s -- `%s'"), detail
->error
, str
);
4717 handler (_("%s at operand %d -- `%s'"),
4718 detail
->error
, idx
+ 1, str
);
4722 gas_assert (idx
>= 0);
4723 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4724 aarch64_get_operand_desc (opd_code
), str
);
4728 case AARCH64_OPDE_INVALID_VARIANT
:
4729 handler (_("operand mismatch -- `%s'"), str
);
4730 if (verbose_error_p
)
4732 /* We will try to correct the erroneous instruction and also provide
4733 more information e.g. all other valid variants.
4735 The string representation of the corrected instruction and other
4736 valid variants are generated by
4738 1) obtaining the intermediate representation of the erroneous
4740 2) manipulating the IR, e.g. replacing the operand qualifier;
4741 3) printing out the instruction by calling the printer functions
4742 shared with the disassembler.
4744 The limitation of this method is that the exact input assembly
4745 line cannot be accurately reproduced in some cases, for example an
4746 optional operand present in the actual assembly line will be
4747 omitted in the output; likewise for the optional syntax rules,
4748 e.g. the # before the immediate. Another limitation is that the
4749 assembly symbols and relocation operations in the assembly line
4750 currently cannot be printed out in the error report. Last but not
4751 least, when there is other error(s) co-exist with this error, the
4752 'corrected' instruction may be still incorrect, e.g. given
4753 'ldnp h0,h1,[x0,#6]!'
4754 this diagnosis will provide the version:
4755 'ldnp s0,s1,[x0,#6]!'
4756 which is still not right. */
4757 size_t len
= strlen (get_mnemonic_name (str
));
4761 aarch64_inst
*inst_base
= &inst
.base
;
4762 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4765 reset_aarch64_instruction (&inst
);
4766 inst_base
->opcode
= opcode
;
4768 /* Reset the error report so that there is no side effect on the
4769 following operand parsing. */
4770 init_operand_error_report ();
4773 result
= parse_operands (str
+ len
, opcode
)
4774 && programmer_friendly_fixup (&inst
);
4775 gas_assert (result
);
4776 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4777 NULL
, NULL
, insn_sequence
);
4778 gas_assert (!result
);
4780 /* Find the most matched qualifier sequence. */
4781 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4782 gas_assert (qlf_idx
> -1);
4784 /* Assign the qualifiers. */
4785 assign_qualifier_sequence (inst_base
,
4786 opcode
->qualifiers_list
[qlf_idx
]);
4788 /* Print the hint. */
4789 output_info (_(" did you mean this?"));
4790 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4791 print_operands (buf
, opcode
, inst_base
->operands
);
4792 output_info (_(" %s"), buf
);
4794 /* Print out other variant(s) if there is any. */
4796 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4797 output_info (_(" other valid variant(s):"));
4799 /* For each pattern. */
4800 qualifiers_list
= opcode
->qualifiers_list
;
4801 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4803 /* Most opcodes has much fewer patterns in the list.
4804 First NIL qualifier indicates the end in the list. */
4805 if (empty_qualifier_sequence_p (*qualifiers_list
))
4810 /* Mnemonics name. */
4811 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4813 /* Assign the qualifiers. */
4814 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4816 /* Print instruction. */
4817 print_operands (buf
, opcode
, inst_base
->operands
);
4819 output_info (_(" %s"), buf
);
4825 case AARCH64_OPDE_UNTIED_OPERAND
:
4826 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4827 detail
->index
+ 1, str
);
4830 case AARCH64_OPDE_OUT_OF_RANGE
:
4831 if (detail
->data
[0] != detail
->data
[1])
4832 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4833 detail
->error
? detail
->error
: _("immediate value"),
4834 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4836 handler (_("%s must be %d at operand %d -- `%s'"),
4837 detail
->error
? detail
->error
: _("immediate value"),
4838 detail
->data
[0], idx
+ 1, str
);
4841 case AARCH64_OPDE_REG_LIST
:
4842 if (detail
->data
[0] == 1)
4843 handler (_("invalid number of registers in the list; "
4844 "only 1 register is expected at operand %d -- `%s'"),
4847 handler (_("invalid number of registers in the list; "
4848 "%d registers are expected at operand %d -- `%s'"),
4849 detail
->data
[0], idx
+ 1, str
);
4852 case AARCH64_OPDE_UNALIGNED
:
4853 handler (_("immediate value must be a multiple of "
4854 "%d at operand %d -- `%s'"),
4855 detail
->data
[0], idx
+ 1, str
);
4864 /* Process and output the error message about the operand mismatching.
4866 When this function is called, the operand error information had
4867 been collected for an assembly line and there will be multiple
4868 errors in the case of multiple instruction templates; output the
4869 error message that most closely describes the problem.
4871 The errors to be printed can be filtered on printing all errors
4872 or only non-fatal errors. This distinction has to be made because
4873 the error buffer may already be filled with fatal errors we don't want to
4874 print due to the different instruction templates. */
4877 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4879 int largest_error_pos
;
4880 const char *msg
= NULL
;
4881 enum aarch64_operand_error_kind kind
;
4882 operand_error_record
*curr
;
4883 operand_error_record
*head
= operand_error_report
.head
;
4884 operand_error_record
*record
= NULL
;
4886 /* No error to report. */
4890 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4892 /* Only one error. */
4893 if (head
== operand_error_report
.tail
)
4895 /* If the only error is a non-fatal one and we don't want to print it,
4897 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4899 DEBUG_TRACE ("single opcode entry with error kind: %s",
4900 operand_mismatch_kind_names
[head
->detail
.kind
]);
4901 output_operand_error_record (head
, str
);
4906 /* Find the error kind of the highest severity. */
4907 DEBUG_TRACE ("multiple opcode entries with error kind");
4908 kind
= AARCH64_OPDE_NIL
;
4909 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4911 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4912 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4913 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4914 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4915 kind
= curr
->detail
.kind
;
4918 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4920 /* Pick up one of errors of KIND to report. */
4921 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4922 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4924 /* If we don't want to print non-fatal errors then don't consider them
4926 if (curr
->detail
.kind
!= kind
4927 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4929 /* If there are multiple errors, pick up the one with the highest
4930 mismatching operand index. In the case of multiple errors with
4931 the equally highest operand index, pick up the first one or the
4932 first one with non-NULL error message. */
4933 if (curr
->detail
.index
> largest_error_pos
4934 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4935 && curr
->detail
.error
!= NULL
))
4937 largest_error_pos
= curr
->detail
.index
;
4939 msg
= record
->detail
.error
;
4943 /* The way errors are collected in the back-end is a bit non-intuitive. But
4944 essentially, because each operand template is tried recursively you may
4945 always have errors collected from the previous tried OPND. These are
4946 usually skipped if there is one successful match. However now with the
4947 non-fatal errors we have to ignore those previously collected hard errors
4948 when we're only interested in printing the non-fatal ones. This condition
4949 prevents us from printing errors that are not appropriate, since we did
4950 match a condition, but it also has warnings that it wants to print. */
4951 if (non_fatal_only
&& !record
)
4954 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4955 DEBUG_TRACE ("Pick up error kind %s to report",
4956 operand_mismatch_kind_names
[record
->detail
.kind
]);
4959 output_operand_error_record (record
, str
);
4962 /* Write an AARCH64 instruction to buf - always little-endian. */
4964 put_aarch64_insn (char *buf
, uint32_t insn
)
4966 unsigned char *where
= (unsigned char *) buf
;
4968 where
[1] = insn
>> 8;
4969 where
[2] = insn
>> 16;
4970 where
[3] = insn
>> 24;
4974 get_aarch64_insn (char *buf
)
4976 unsigned char *where
= (unsigned char *) buf
;
4978 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4983 output_inst (struct aarch64_inst
*new_inst
)
4987 to
= frag_more (INSN_SIZE
);
4989 frag_now
->tc_frag_data
.recorded
= 1;
4991 put_aarch64_insn (to
, inst
.base
.value
);
4993 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4995 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4996 INSN_SIZE
, &inst
.reloc
.exp
,
4999 DEBUG_TRACE ("Prepared relocation fix up");
5000 /* Don't check the addend value against the instruction size,
5001 that's the job of our code in md_apply_fix(). */
5002 fixp
->fx_no_overflow
= 1;
5003 if (new_inst
!= NULL
)
5004 fixp
->tc_fix_data
.inst
= new_inst
;
5005 if (aarch64_gas_internal_fixup_p ())
5007 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5008 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5009 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5013 dwarf2_emit_insn (INSN_SIZE
);
5016 /* Link together opcodes of the same name. */
5020 aarch64_opcode
*opcode
;
5021 struct templates
*next
;
5024 typedef struct templates templates
;
5027 lookup_mnemonic (const char *start
, int len
)
5029 templates
*templ
= NULL
;
5031 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
5035 /* Subroutine of md_assemble, responsible for looking up the primary
5036 opcode from the mnemonic the user wrote. STR points to the
5037 beginning of the mnemonic. */
5040 opcode_lookup (char **str
)
5042 char *end
, *base
, *dot
;
5043 const aarch64_cond
*cond
;
5047 /* Scan up to the end of the mnemonic, which must end in white space,
5048 '.', or end of string. */
5050 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5051 if (*end
== '.' && !dot
)
5054 if (end
== base
|| dot
== base
)
5057 inst
.cond
= COND_ALWAYS
;
5059 /* Handle a possible condition. */
5062 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5065 inst
.cond
= cond
->value
;
5081 if (inst
.cond
== COND_ALWAYS
)
5083 /* Look for unaffixed mnemonic. */
5084 return lookup_mnemonic (base
, len
);
5088 /* append ".c" to mnemonic if conditional */
5089 memcpy (condname
, base
, len
);
5090 memcpy (condname
+ len
, ".c", 2);
5093 return lookup_mnemonic (base
, len
);
5099 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5100 to a corresponding operand qualifier. */
5102 static inline aarch64_opnd_qualifier_t
5103 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5105 /* Element size in bytes indexed by vector_el_type. */
5106 const unsigned char ele_size
[5]
5108 const unsigned int ele_base
[5] =
5110 AARCH64_OPND_QLF_V_4B
,
5111 AARCH64_OPND_QLF_V_2H
,
5112 AARCH64_OPND_QLF_V_2S
,
5113 AARCH64_OPND_QLF_V_1D
,
5114 AARCH64_OPND_QLF_V_1Q
5117 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5118 goto vectype_conversion_fail
;
5120 if (vectype
->type
== NT_zero
)
5121 return AARCH64_OPND_QLF_P_Z
;
5122 if (vectype
->type
== NT_merge
)
5123 return AARCH64_OPND_QLF_P_M
;
5125 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5127 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5129 /* Special case S_4B. */
5130 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5131 return AARCH64_OPND_QLF_S_4B
;
5133 /* Special case S_2H. */
5134 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5135 return AARCH64_OPND_QLF_S_2H
;
5137 /* Vector element register. */
5138 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5142 /* Vector register. */
5143 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5146 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5147 goto vectype_conversion_fail
;
5149 /* The conversion is by calculating the offset from the base operand
5150 qualifier for the vector type. The operand qualifiers are regular
5151 enough that the offset can established by shifting the vector width by
5152 a vector-type dependent amount. */
5154 if (vectype
->type
== NT_b
)
5156 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5158 else if (vectype
->type
>= NT_d
)
5163 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5164 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5165 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5169 vectype_conversion_fail
:
5170 first_error (_("bad vector arrangement type"));
5171 return AARCH64_OPND_QLF_NIL
;
5174 /* Process an optional operand that is found omitted from the assembly line.
5175 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5176 instruction's opcode entry while IDX is the index of this omitted operand.
5180 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5181 int idx
, aarch64_opnd_info
*operand
)
5183 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5184 gas_assert (optional_operand_p (opcode
, idx
));
5185 gas_assert (!operand
->present
);
5189 case AARCH64_OPND_Rd
:
5190 case AARCH64_OPND_Rn
:
5191 case AARCH64_OPND_Rm
:
5192 case AARCH64_OPND_Rt
:
5193 case AARCH64_OPND_Rt2
:
5194 case AARCH64_OPND_Rt_SP
:
5195 case AARCH64_OPND_Rs
:
5196 case AARCH64_OPND_Ra
:
5197 case AARCH64_OPND_Rt_SYS
:
5198 case AARCH64_OPND_Rd_SP
:
5199 case AARCH64_OPND_Rn_SP
:
5200 case AARCH64_OPND_Rm_SP
:
5201 case AARCH64_OPND_Fd
:
5202 case AARCH64_OPND_Fn
:
5203 case AARCH64_OPND_Fm
:
5204 case AARCH64_OPND_Fa
:
5205 case AARCH64_OPND_Ft
:
5206 case AARCH64_OPND_Ft2
:
5207 case AARCH64_OPND_Sd
:
5208 case AARCH64_OPND_Sn
:
5209 case AARCH64_OPND_Sm
:
5210 case AARCH64_OPND_Va
:
5211 case AARCH64_OPND_Vd
:
5212 case AARCH64_OPND_Vn
:
5213 case AARCH64_OPND_Vm
:
5214 case AARCH64_OPND_VdD1
:
5215 case AARCH64_OPND_VnD1
:
5216 operand
->reg
.regno
= default_value
;
5219 case AARCH64_OPND_Ed
:
5220 case AARCH64_OPND_En
:
5221 case AARCH64_OPND_Em
:
5222 case AARCH64_OPND_Em16
:
5223 case AARCH64_OPND_SM3_IMM2
:
5224 operand
->reglane
.regno
= default_value
;
5227 case AARCH64_OPND_IDX
:
5228 case AARCH64_OPND_BIT_NUM
:
5229 case AARCH64_OPND_IMMR
:
5230 case AARCH64_OPND_IMMS
:
5231 case AARCH64_OPND_SHLL_IMM
:
5232 case AARCH64_OPND_IMM_VLSL
:
5233 case AARCH64_OPND_IMM_VLSR
:
5234 case AARCH64_OPND_CCMP_IMM
:
5235 case AARCH64_OPND_FBITS
:
5236 case AARCH64_OPND_UIMM4
:
5237 case AARCH64_OPND_UIMM3_OP1
:
5238 case AARCH64_OPND_UIMM3_OP2
:
5239 case AARCH64_OPND_IMM
:
5240 case AARCH64_OPND_IMM_2
:
5241 case AARCH64_OPND_WIDTH
:
5242 case AARCH64_OPND_UIMM7
:
5243 case AARCH64_OPND_NZCV
:
5244 case AARCH64_OPND_SVE_PATTERN
:
5245 case AARCH64_OPND_SVE_PRFOP
:
5246 operand
->imm
.value
= default_value
;
5249 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5250 operand
->imm
.value
= default_value
;
5251 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5252 operand
->shifter
.amount
= 1;
5255 case AARCH64_OPND_EXCEPTION
:
5256 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5259 case AARCH64_OPND_BARRIER_ISB
:
5260 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5263 case AARCH64_OPND_BTI_TARGET
:
5264 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5272 /* Process the relocation type for move wide instructions.
5273 Return TRUE on success; otherwise return FALSE. */
5276 process_movw_reloc_info (void)
5281 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5283 if (inst
.base
.opcode
->op
== OP_MOVK
)
5284 switch (inst
.reloc
.type
)
5286 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5287 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5288 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5289 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5290 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5291 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5292 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5293 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5294 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5295 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5296 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5298 (_("the specified relocation type is not allowed for MOVK"));
5304 switch (inst
.reloc
.type
)
5306 case BFD_RELOC_AARCH64_MOVW_G0
:
5307 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5308 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5309 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5310 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5311 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5312 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5313 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5314 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5315 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5316 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5317 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5318 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5321 case BFD_RELOC_AARCH64_MOVW_G1
:
5322 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5323 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5324 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5325 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5326 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5327 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5328 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5329 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5330 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5331 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5332 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5333 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5336 case BFD_RELOC_AARCH64_MOVW_G2
:
5337 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5338 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5339 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5340 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5341 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5342 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5345 set_fatal_syntax_error
5346 (_("the specified relocation type is not allowed for 32-bit "
5352 case BFD_RELOC_AARCH64_MOVW_G3
:
5353 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5356 set_fatal_syntax_error
5357 (_("the specified relocation type is not allowed for 32-bit "
5364 /* More cases should be added when more MOVW-related relocation types
5365 are supported in GAS. */
5366 gas_assert (aarch64_gas_internal_fixup_p ());
5367 /* The shift amount should have already been set by the parser. */
5370 inst
.base
.operands
[1].shifter
.amount
= shift
;
5374 /* A primitive log calculator. */
5376 static inline unsigned int
5377 get_logsz (unsigned int size
)
5379 const unsigned char ls
[16] =
5380 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5386 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5387 return ls
[size
- 1];
5390 /* Determine and return the real reloc type code for an instruction
5391 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5393 static inline bfd_reloc_code_real_type
5394 ldst_lo12_determine_real_reloc_type (void)
5397 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5398 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5400 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5402 BFD_RELOC_AARCH64_LDST8_LO12
,
5403 BFD_RELOC_AARCH64_LDST16_LO12
,
5404 BFD_RELOC_AARCH64_LDST32_LO12
,
5405 BFD_RELOC_AARCH64_LDST64_LO12
,
5406 BFD_RELOC_AARCH64_LDST128_LO12
5409 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5410 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5411 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5412 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5413 BFD_RELOC_AARCH64_NONE
5416 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5417 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5418 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5419 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5420 BFD_RELOC_AARCH64_NONE
5423 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5424 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5425 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5426 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5427 BFD_RELOC_AARCH64_NONE
5430 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5431 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5432 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5433 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5434 BFD_RELOC_AARCH64_NONE
5438 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5439 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5441 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5443 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5445 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5446 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5448 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5450 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5452 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5454 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5455 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5456 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5457 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5458 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5459 gas_assert (logsz
<= 3);
5461 gas_assert (logsz
<= 4);
5463 /* In reloc.c, these pseudo relocation types should be defined in similar
5464 order as above reloc_ldst_lo12 array. Because the array index calculation
5465 below relies on this. */
5466 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5469 /* Check whether a register list REGINFO is valid. The registers must be
5470 numbered in increasing order (modulo 32), in increments of one or two.
5472 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5475 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5478 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5480 uint32_t i
, nb_regs
, prev_regno
, incr
;
5482 nb_regs
= 1 + (reginfo
& 0x3);
5484 prev_regno
= reginfo
& 0x1f;
5485 incr
= accept_alternate
? 2 : 1;
5487 for (i
= 1; i
< nb_regs
; ++i
)
5489 uint32_t curr_regno
;
5491 curr_regno
= reginfo
& 0x1f;
5492 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5494 prev_regno
= curr_regno
;
5500 /* Generic instruction operand parser. This does no encoding and no
5501 semantic validation; it merely squirrels values away in the inst
5502 structure. Returns TRUE or FALSE depending on whether the
5503 specified grammar matched. */
5506 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5509 char *backtrack_pos
= 0;
5510 const enum aarch64_opnd
*operands
= opcode
->operands
;
5511 aarch64_reg_type imm_reg_type
;
5514 skip_whitespace (str
);
5516 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5517 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5519 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5521 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5524 const reg_entry
*reg
;
5525 int comma_skipped_p
= 0;
5526 aarch64_reg_type rtype
;
5527 struct vector_type_el vectype
;
5528 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5529 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5530 aarch64_reg_type reg_type
;
5532 DEBUG_TRACE ("parse operand %d", i
);
5534 /* Assign the operand code. */
5535 info
->type
= operands
[i
];
5537 if (optional_operand_p (opcode
, i
))
5539 /* Remember where we are in case we need to backtrack. */
5540 gas_assert (!backtrack_pos
);
5541 backtrack_pos
= str
;
5544 /* Expect comma between operands; the backtrack mechanism will take
5545 care of cases of omitted optional operand. */
5546 if (i
> 0 && ! skip_past_char (&str
, ','))
5548 set_syntax_error (_("comma expected between operands"));
5552 comma_skipped_p
= 1;
5554 switch (operands
[i
])
5556 case AARCH64_OPND_Rd
:
5557 case AARCH64_OPND_Rn
:
5558 case AARCH64_OPND_Rm
:
5559 case AARCH64_OPND_Rt
:
5560 case AARCH64_OPND_Rt2
:
5561 case AARCH64_OPND_Rs
:
5562 case AARCH64_OPND_Ra
:
5563 case AARCH64_OPND_Rt_SYS
:
5564 case AARCH64_OPND_PAIRREG
:
5565 case AARCH64_OPND_SVE_Rm
:
5566 po_int_reg_or_fail (REG_TYPE_R_Z
);
5569 case AARCH64_OPND_Rd_SP
:
5570 case AARCH64_OPND_Rn_SP
:
5571 case AARCH64_OPND_Rt_SP
:
5572 case AARCH64_OPND_SVE_Rn_SP
:
5573 case AARCH64_OPND_Rm_SP
:
5574 po_int_reg_or_fail (REG_TYPE_R_SP
);
5577 case AARCH64_OPND_Rm_EXT
:
5578 case AARCH64_OPND_Rm_SFT
:
5579 po_misc_or_fail (parse_shifter_operand
5580 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5582 : SHIFTED_LOGIC_IMM
)));
5583 if (!info
->shifter
.operator_present
)
5585 /* Default to LSL if not present. Libopcodes prefers shifter
5586 kind to be explicit. */
5587 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5588 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5589 /* For Rm_EXT, libopcodes will carry out further check on whether
5590 or not stack pointer is used in the instruction (Recall that
5591 "the extend operator is not optional unless at least one of
5592 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5596 case AARCH64_OPND_Fd
:
5597 case AARCH64_OPND_Fn
:
5598 case AARCH64_OPND_Fm
:
5599 case AARCH64_OPND_Fa
:
5600 case AARCH64_OPND_Ft
:
5601 case AARCH64_OPND_Ft2
:
5602 case AARCH64_OPND_Sd
:
5603 case AARCH64_OPND_Sn
:
5604 case AARCH64_OPND_Sm
:
5605 case AARCH64_OPND_SVE_VZn
:
5606 case AARCH64_OPND_SVE_Vd
:
5607 case AARCH64_OPND_SVE_Vm
:
5608 case AARCH64_OPND_SVE_Vn
:
5609 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5610 if (val
== PARSE_FAIL
)
5612 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5615 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5617 info
->reg
.regno
= val
;
5618 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5621 case AARCH64_OPND_SVE_Pd
:
5622 case AARCH64_OPND_SVE_Pg3
:
5623 case AARCH64_OPND_SVE_Pg4_5
:
5624 case AARCH64_OPND_SVE_Pg4_10
:
5625 case AARCH64_OPND_SVE_Pg4_16
:
5626 case AARCH64_OPND_SVE_Pm
:
5627 case AARCH64_OPND_SVE_Pn
:
5628 case AARCH64_OPND_SVE_Pt
:
5629 reg_type
= REG_TYPE_PN
;
5632 case AARCH64_OPND_SVE_Za_5
:
5633 case AARCH64_OPND_SVE_Za_16
:
5634 case AARCH64_OPND_SVE_Zd
:
5635 case AARCH64_OPND_SVE_Zm_5
:
5636 case AARCH64_OPND_SVE_Zm_16
:
5637 case AARCH64_OPND_SVE_Zn
:
5638 case AARCH64_OPND_SVE_Zt
:
5639 reg_type
= REG_TYPE_ZN
;
5642 case AARCH64_OPND_Va
:
5643 case AARCH64_OPND_Vd
:
5644 case AARCH64_OPND_Vn
:
5645 case AARCH64_OPND_Vm
:
5646 reg_type
= REG_TYPE_VN
;
5648 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5649 if (val
== PARSE_FAIL
)
5651 first_error (_(get_reg_expected_msg (reg_type
)));
5654 if (vectype
.defined
& NTA_HASINDEX
)
5657 info
->reg
.regno
= val
;
5658 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5659 && vectype
.type
== NT_invtype
)
5660 /* Unqualified Pn and Zn registers are allowed in certain
5661 contexts. Rely on F_STRICT qualifier checking to catch
5663 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5666 info
->qualifier
= vectype_to_qualifier (&vectype
);
5667 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5672 case AARCH64_OPND_VdD1
:
5673 case AARCH64_OPND_VnD1
:
5674 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5675 if (val
== PARSE_FAIL
)
5677 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5680 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5682 set_fatal_syntax_error
5683 (_("the top half of a 128-bit FP/SIMD register is expected"));
5686 info
->reg
.regno
= val
;
5687 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5688 here; it is correct for the purpose of encoding/decoding since
5689 only the register number is explicitly encoded in the related
5690 instructions, although this appears a bit hacky. */
5691 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5694 case AARCH64_OPND_SVE_Zm3_INDEX
:
5695 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5696 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5697 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5698 case AARCH64_OPND_SVE_Zm4_INDEX
:
5699 case AARCH64_OPND_SVE_Zn_INDEX
:
5700 reg_type
= REG_TYPE_ZN
;
5701 goto vector_reg_index
;
5703 case AARCH64_OPND_Ed
:
5704 case AARCH64_OPND_En
:
5705 case AARCH64_OPND_Em
:
5706 case AARCH64_OPND_Em16
:
5707 case AARCH64_OPND_SM3_IMM2
:
5708 reg_type
= REG_TYPE_VN
;
5710 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5711 if (val
== PARSE_FAIL
)
5713 first_error (_(get_reg_expected_msg (reg_type
)));
5716 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5719 info
->reglane
.regno
= val
;
5720 info
->reglane
.index
= vectype
.index
;
5721 info
->qualifier
= vectype_to_qualifier (&vectype
);
5722 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5726 case AARCH64_OPND_SVE_ZnxN
:
5727 case AARCH64_OPND_SVE_ZtxN
:
5728 reg_type
= REG_TYPE_ZN
;
5729 goto vector_reg_list
;
5731 case AARCH64_OPND_LVn
:
5732 case AARCH64_OPND_LVt
:
5733 case AARCH64_OPND_LVt_AL
:
5734 case AARCH64_OPND_LEt
:
5735 reg_type
= REG_TYPE_VN
;
5737 if (reg_type
== REG_TYPE_ZN
5738 && get_opcode_dependent_value (opcode
) == 1
5741 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5742 if (val
== PARSE_FAIL
)
5744 first_error (_(get_reg_expected_msg (reg_type
)));
5747 info
->reglist
.first_regno
= val
;
5748 info
->reglist
.num_regs
= 1;
5752 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5753 if (val
== PARSE_FAIL
)
5756 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5758 set_fatal_syntax_error (_("invalid register list"));
5762 if (vectype
.width
!= 0 && *str
!= ',')
5764 set_fatal_syntax_error
5765 (_("expected element type rather than vector type"));
5769 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5770 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5772 if (operands
[i
] == AARCH64_OPND_LEt
)
5774 if (!(vectype
.defined
& NTA_HASINDEX
))
5776 info
->reglist
.has_index
= 1;
5777 info
->reglist
.index
= vectype
.index
;
5781 if (vectype
.defined
& NTA_HASINDEX
)
5783 if (!(vectype
.defined
& NTA_HASTYPE
))
5785 if (reg_type
== REG_TYPE_ZN
)
5786 set_fatal_syntax_error (_("missing type suffix"));
5790 info
->qualifier
= vectype_to_qualifier (&vectype
);
5791 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5795 case AARCH64_OPND_CRn
:
5796 case AARCH64_OPND_CRm
:
5798 char prefix
= *(str
++);
5799 if (prefix
!= 'c' && prefix
!= 'C')
5802 po_imm_nc_or_fail ();
5805 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5808 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5809 info
->imm
.value
= val
;
5813 case AARCH64_OPND_SHLL_IMM
:
5814 case AARCH64_OPND_IMM_VLSR
:
5815 po_imm_or_fail (1, 64);
5816 info
->imm
.value
= val
;
5819 case AARCH64_OPND_CCMP_IMM
:
5820 case AARCH64_OPND_SIMM5
:
5821 case AARCH64_OPND_FBITS
:
5822 case AARCH64_OPND_TME_UIMM16
:
5823 case AARCH64_OPND_UIMM4
:
5824 case AARCH64_OPND_UIMM4_ADDG
:
5825 case AARCH64_OPND_UIMM10
:
5826 case AARCH64_OPND_UIMM3_OP1
:
5827 case AARCH64_OPND_UIMM3_OP2
:
5828 case AARCH64_OPND_IMM_VLSL
:
5829 case AARCH64_OPND_IMM
:
5830 case AARCH64_OPND_IMM_2
:
5831 case AARCH64_OPND_WIDTH
:
5832 case AARCH64_OPND_SVE_INV_LIMM
:
5833 case AARCH64_OPND_SVE_LIMM
:
5834 case AARCH64_OPND_SVE_LIMM_MOV
:
5835 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5836 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5837 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5838 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5839 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5840 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5841 case AARCH64_OPND_SVE_SIMM5
:
5842 case AARCH64_OPND_SVE_SIMM5B
:
5843 case AARCH64_OPND_SVE_SIMM6
:
5844 case AARCH64_OPND_SVE_SIMM8
:
5845 case AARCH64_OPND_SVE_UIMM3
:
5846 case AARCH64_OPND_SVE_UIMM7
:
5847 case AARCH64_OPND_SVE_UIMM8
:
5848 case AARCH64_OPND_SVE_UIMM8_53
:
5849 case AARCH64_OPND_IMM_ROT1
:
5850 case AARCH64_OPND_IMM_ROT2
:
5851 case AARCH64_OPND_IMM_ROT3
:
5852 case AARCH64_OPND_SVE_IMM_ROT1
:
5853 case AARCH64_OPND_SVE_IMM_ROT2
:
5854 case AARCH64_OPND_SVE_IMM_ROT3
:
5855 po_imm_nc_or_fail ();
5856 info
->imm
.value
= val
;
5859 case AARCH64_OPND_SVE_AIMM
:
5860 case AARCH64_OPND_SVE_ASIMM
:
5861 po_imm_nc_or_fail ();
5862 info
->imm
.value
= val
;
5863 skip_whitespace (str
);
5864 if (skip_past_comma (&str
))
5865 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5867 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5870 case AARCH64_OPND_SVE_PATTERN
:
5871 po_enum_or_fail (aarch64_sve_pattern_array
);
5872 info
->imm
.value
= val
;
5875 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5876 po_enum_or_fail (aarch64_sve_pattern_array
);
5877 info
->imm
.value
= val
;
5878 if (skip_past_comma (&str
)
5879 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5881 if (!info
->shifter
.operator_present
)
5883 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5884 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5885 info
->shifter
.amount
= 1;
5889 case AARCH64_OPND_SVE_PRFOP
:
5890 po_enum_or_fail (aarch64_sve_prfop_array
);
5891 info
->imm
.value
= val
;
5894 case AARCH64_OPND_UIMM7
:
5895 po_imm_or_fail (0, 127);
5896 info
->imm
.value
= val
;
5899 case AARCH64_OPND_IDX
:
5900 case AARCH64_OPND_MASK
:
5901 case AARCH64_OPND_BIT_NUM
:
5902 case AARCH64_OPND_IMMR
:
5903 case AARCH64_OPND_IMMS
:
5904 po_imm_or_fail (0, 63);
5905 info
->imm
.value
= val
;
5908 case AARCH64_OPND_IMM0
:
5909 po_imm_nc_or_fail ();
5912 set_fatal_syntax_error (_("immediate zero expected"));
5915 info
->imm
.value
= 0;
5918 case AARCH64_OPND_FPIMM0
:
5921 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5922 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5923 it is probably not worth the effort to support it. */
5924 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5927 || !(res2
= parse_constant_immediate (&str
, &val
,
5930 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5932 info
->imm
.value
= 0;
5933 info
->imm
.is_fp
= 1;
5936 set_fatal_syntax_error (_("immediate zero expected"));
5940 case AARCH64_OPND_IMM_MOV
:
5943 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5944 reg_name_p (str
, REG_TYPE_VN
))
5947 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5949 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5950 later. fix_mov_imm_insn will try to determine a machine
5951 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5952 message if the immediate cannot be moved by a single
5954 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5955 inst
.base
.operands
[i
].skip
= 1;
5959 case AARCH64_OPND_SIMD_IMM
:
5960 case AARCH64_OPND_SIMD_IMM_SFT
:
5961 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5963 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5965 /* need_libopcodes_p */ 1,
5968 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5969 shift, we don't check it here; we leave the checking to
5970 the libopcodes (operand_general_constraint_met_p). By
5971 doing this, we achieve better diagnostics. */
5972 if (skip_past_comma (&str
)
5973 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5975 if (!info
->shifter
.operator_present
5976 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5978 /* Default to LSL if not present. Libopcodes prefers shifter
5979 kind to be explicit. */
5980 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5981 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5985 case AARCH64_OPND_FPIMM
:
5986 case AARCH64_OPND_SIMD_FPIMM
:
5987 case AARCH64_OPND_SVE_FPIMM8
:
5992 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5993 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5994 || !aarch64_imm_float_p (qfloat
))
5997 set_fatal_syntax_error (_("invalid floating-point"
6001 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6002 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6006 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6007 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6008 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6013 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6014 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6017 set_fatal_syntax_error (_("invalid floating-point"
6021 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6022 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6026 case AARCH64_OPND_LIMM
:
6027 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6028 SHIFTED_LOGIC_IMM
));
6029 if (info
->shifter
.operator_present
)
6031 set_fatal_syntax_error
6032 (_("shift not allowed for bitmask immediate"));
6035 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6037 /* need_libopcodes_p */ 1,
6041 case AARCH64_OPND_AIMM
:
6042 if (opcode
->op
== OP_ADD
)
6043 /* ADD may have relocation types. */
6044 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6045 SHIFTED_ARITH_IMM
));
6047 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6048 SHIFTED_ARITH_IMM
));
6049 switch (inst
.reloc
.type
)
6051 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6052 info
->shifter
.amount
= 12;
6054 case BFD_RELOC_UNUSED
:
6055 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6056 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6057 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6058 inst
.reloc
.pc_rel
= 0;
6063 info
->imm
.value
= 0;
6064 if (!info
->shifter
.operator_present
)
6066 /* Default to LSL if not present. Libopcodes prefers shifter
6067 kind to be explicit. */
6068 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6069 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6073 case AARCH64_OPND_HALF
:
6075 /* #<imm16> or relocation. */
6076 int internal_fixup_p
;
6077 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6078 if (internal_fixup_p
)
6079 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6080 skip_whitespace (str
);
6081 if (skip_past_comma (&str
))
6083 /* {, LSL #<shift>} */
6084 if (! aarch64_gas_internal_fixup_p ())
6086 set_fatal_syntax_error (_("can't mix relocation modifier "
6087 "with explicit shift"));
6090 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6093 inst
.base
.operands
[i
].shifter
.amount
= 0;
6094 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6095 inst
.base
.operands
[i
].imm
.value
= 0;
6096 if (! process_movw_reloc_info ())
6101 case AARCH64_OPND_EXCEPTION
:
6102 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6104 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6106 /* need_libopcodes_p */ 0,
6110 case AARCH64_OPND_NZCV
:
6112 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6116 info
->imm
.value
= nzcv
->value
;
6119 po_imm_or_fail (0, 15);
6120 info
->imm
.value
= val
;
6124 case AARCH64_OPND_COND
:
6125 case AARCH64_OPND_COND1
:
6130 while (ISALPHA (*str
));
6131 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6132 if (info
->cond
== NULL
)
6134 set_syntax_error (_("invalid condition"));
6137 else if (operands
[i
] == AARCH64_OPND_COND1
6138 && (info
->cond
->value
& 0xe) == 0xe)
6140 /* Do not allow AL or NV. */
6141 set_default_error ();
6147 case AARCH64_OPND_ADDR_ADRP
:
6148 po_misc_or_fail (parse_adrp (&str
));
6149 /* Clear the value as operand needs to be relocated. */
6150 info
->imm
.value
= 0;
6153 case AARCH64_OPND_ADDR_PCREL14
:
6154 case AARCH64_OPND_ADDR_PCREL19
:
6155 case AARCH64_OPND_ADDR_PCREL21
:
6156 case AARCH64_OPND_ADDR_PCREL26
:
6157 po_misc_or_fail (parse_address (&str
, info
));
6158 if (!info
->addr
.pcrel
)
6160 set_syntax_error (_("invalid pc-relative address"));
6163 if (inst
.gen_lit_pool
6164 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6166 /* Only permit "=value" in the literal load instructions.
6167 The literal will be generated by programmer_friendly_fixup. */
6168 set_syntax_error (_("invalid use of \"=immediate\""));
6171 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6173 set_syntax_error (_("unrecognized relocation suffix"));
6176 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6178 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6179 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6183 info
->imm
.value
= 0;
6184 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6185 switch (opcode
->iclass
)
6189 /* e.g. CBZ or B.COND */
6190 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6191 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6195 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6196 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6200 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6202 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6203 : BFD_RELOC_AARCH64_JUMP26
;
6206 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6207 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6210 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6211 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6217 inst
.reloc
.pc_rel
= 1;
6221 case AARCH64_OPND_ADDR_SIMPLE
:
6222 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6224 /* [<Xn|SP>{, #<simm>}] */
6226 /* First use the normal address-parsing routines, to get
6227 the usual syntax errors. */
6228 po_misc_or_fail (parse_address (&str
, info
));
6229 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6230 || !info
->addr
.preind
|| info
->addr
.postind
6231 || info
->addr
.writeback
)
6233 set_syntax_error (_("invalid addressing mode"));
6237 /* Then retry, matching the specific syntax of these addresses. */
6239 po_char_or_fail ('[');
6240 po_reg_or_fail (REG_TYPE_R64_SP
);
6241 /* Accept optional ", #0". */
6242 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6243 && skip_past_char (&str
, ','))
6245 skip_past_char (&str
, '#');
6246 if (! skip_past_char (&str
, '0'))
6248 set_fatal_syntax_error
6249 (_("the optional immediate offset can only be 0"));
6253 po_char_or_fail (']');
6257 case AARCH64_OPND_ADDR_REGOFF
:
6258 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6259 po_misc_or_fail (parse_address (&str
, info
));
6261 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6262 || !info
->addr
.preind
|| info
->addr
.postind
6263 || info
->addr
.writeback
)
6265 set_syntax_error (_("invalid addressing mode"));
6268 if (!info
->shifter
.operator_present
)
6270 /* Default to LSL if not present. Libopcodes prefers shifter
6271 kind to be explicit. */
6272 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6273 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6275 /* Qualifier to be deduced by libopcodes. */
6278 case AARCH64_OPND_ADDR_SIMM7
:
6279 po_misc_or_fail (parse_address (&str
, info
));
6280 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6281 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6283 set_syntax_error (_("invalid addressing mode"));
6286 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6288 set_syntax_error (_("relocation not allowed"));
6291 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6293 /* need_libopcodes_p */ 1,
6297 case AARCH64_OPND_ADDR_SIMM9
:
6298 case AARCH64_OPND_ADDR_SIMM9_2
:
6299 case AARCH64_OPND_ADDR_SIMM11
:
6300 case AARCH64_OPND_ADDR_SIMM13
:
6301 po_misc_or_fail (parse_address (&str
, info
));
6302 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6303 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6304 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6305 && info
->addr
.writeback
))
6307 set_syntax_error (_("invalid addressing mode"));
6310 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6312 set_syntax_error (_("relocation not allowed"));
6315 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6317 /* need_libopcodes_p */ 1,
6321 case AARCH64_OPND_ADDR_SIMM10
:
6322 case AARCH64_OPND_ADDR_OFFSET
:
6323 po_misc_or_fail (parse_address (&str
, info
));
6324 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6325 || !info
->addr
.preind
|| info
->addr
.postind
)
6327 set_syntax_error (_("invalid addressing mode"));
6330 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6332 set_syntax_error (_("relocation not allowed"));
6335 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6337 /* need_libopcodes_p */ 1,
6341 case AARCH64_OPND_ADDR_UIMM12
:
6342 po_misc_or_fail (parse_address (&str
, info
));
6343 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6344 || !info
->addr
.preind
|| info
->addr
.writeback
)
6346 set_syntax_error (_("invalid addressing mode"));
6349 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6350 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6351 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6353 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6355 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6357 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6359 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6360 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6361 /* Leave qualifier to be determined by libopcodes. */
6364 case AARCH64_OPND_SIMD_ADDR_POST
:
6365 /* [<Xn|SP>], <Xm|#<amount>> */
6366 po_misc_or_fail (parse_address (&str
, info
));
6367 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6369 set_syntax_error (_("invalid addressing mode"));
6372 if (!info
->addr
.offset
.is_reg
)
6374 if (inst
.reloc
.exp
.X_op
== O_constant
)
6375 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6378 set_fatal_syntax_error
6379 (_("writeback value must be an immediate constant"));
6386 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6387 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6388 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6389 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6390 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6391 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6392 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6393 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6394 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6395 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6396 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6397 /* [X<n>{, #imm, MUL VL}]
6399 but recognizing SVE registers. */
6400 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6401 &offset_qualifier
));
6402 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6404 set_syntax_error (_("invalid addressing mode"));
6408 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6409 || !info
->addr
.preind
|| info
->addr
.writeback
)
6411 set_syntax_error (_("invalid addressing mode"));
6414 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6415 || inst
.reloc
.exp
.X_op
!= O_constant
)
6417 /* Make sure this has priority over
6418 "invalid addressing mode". */
6419 set_fatal_syntax_error (_("constant offset required"));
6422 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6425 case AARCH64_OPND_SVE_ADDR_R
:
6426 /* [<Xn|SP>{, <R><m>}]
6427 but recognizing SVE registers. */
6428 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6429 &offset_qualifier
));
6430 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6432 offset_qualifier
= AARCH64_OPND_QLF_X
;
6433 info
->addr
.offset
.is_reg
= 1;
6434 info
->addr
.offset
.regno
= 31;
6436 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6437 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6439 set_syntax_error (_("invalid addressing mode"));
6444 case AARCH64_OPND_SVE_ADDR_RR
:
6445 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6446 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6447 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6448 case AARCH64_OPND_SVE_ADDR_RX
:
6449 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6450 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6451 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6452 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6453 but recognizing SVE registers. */
6454 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6455 &offset_qualifier
));
6456 if (base_qualifier
!= AARCH64_OPND_QLF_X
6457 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6459 set_syntax_error (_("invalid addressing mode"));
6464 case AARCH64_OPND_SVE_ADDR_RZ
:
6465 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6466 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6467 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6468 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6469 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6470 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6471 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6472 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6473 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6474 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6475 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6476 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6477 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6478 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6479 &offset_qualifier
));
6480 if (base_qualifier
!= AARCH64_OPND_QLF_X
6481 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6482 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6484 set_syntax_error (_("invalid addressing mode"));
6487 info
->qualifier
= offset_qualifier
;
6490 case AARCH64_OPND_SVE_ADDR_ZX
:
6491 /* [Zn.<T>{, <Xm>}]. */
6492 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6493 &offset_qualifier
));
6495 base_qualifier either S_S or S_D
6496 offset_qualifier must be X
6498 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6499 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6500 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6502 set_syntax_error (_("invalid addressing mode"));
6505 info
->qualifier
= base_qualifier
;
6506 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6507 || !info
->addr
.preind
|| info
->addr
.writeback
6508 || info
->shifter
.operator_present
!= 0)
6510 set_syntax_error (_("invalid addressing mode"));
6513 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6517 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6518 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6519 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6520 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6521 /* [Z<n>.<T>{, #imm}] */
6522 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6523 &offset_qualifier
));
6524 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6525 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6527 set_syntax_error (_("invalid addressing mode"));
6530 info
->qualifier
= base_qualifier
;
6533 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6534 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6535 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6536 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6537 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6541 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6543 here since we get better error messages by leaving it to
6544 the qualifier checking routines. */
6545 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6546 &offset_qualifier
));
6547 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6548 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6549 || offset_qualifier
!= base_qualifier
)
6551 set_syntax_error (_("invalid addressing mode"));
6554 info
->qualifier
= base_qualifier
;
6557 case AARCH64_OPND_SYSREG
:
6559 uint32_t sysreg_flags
;
6560 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6561 &sysreg_flags
)) == PARSE_FAIL
)
6563 set_syntax_error (_("unknown or missing system register name"));
6566 inst
.base
.operands
[i
].sysreg
.value
= val
;
6567 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6571 case AARCH64_OPND_PSTATEFIELD
:
6572 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6575 set_syntax_error (_("unknown or missing PSTATE field name"));
6578 inst
.base
.operands
[i
].pstatefield
= val
;
6581 case AARCH64_OPND_SYSREG_IC
:
6582 inst
.base
.operands
[i
].sysins_op
=
6583 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6586 case AARCH64_OPND_SYSREG_DC
:
6587 inst
.base
.operands
[i
].sysins_op
=
6588 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6591 case AARCH64_OPND_SYSREG_AT
:
6592 inst
.base
.operands
[i
].sysins_op
=
6593 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6596 case AARCH64_OPND_SYSREG_SR
:
6597 inst
.base
.operands
[i
].sysins_op
=
6598 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6601 case AARCH64_OPND_SYSREG_TLBI
:
6602 inst
.base
.operands
[i
].sysins_op
=
6603 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6605 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6607 set_fatal_syntax_error ( _("unknown or missing operation name"));
6612 case AARCH64_OPND_BARRIER
:
6613 case AARCH64_OPND_BARRIER_ISB
:
6614 val
= parse_barrier (&str
);
6615 if (val
!= PARSE_FAIL
6616 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6618 /* ISB only accepts options name 'sy'. */
6620 (_("the specified option is not accepted in ISB"));
6621 /* Turn off backtrack as this optional operand is present. */
6625 /* This is an extension to accept a 0..15 immediate. */
6626 if (val
== PARSE_FAIL
)
6627 po_imm_or_fail (0, 15);
6628 info
->barrier
= aarch64_barrier_options
+ val
;
6631 case AARCH64_OPND_PRFOP
:
6632 val
= parse_pldop (&str
);
6633 /* This is an extension to accept a 0..31 immediate. */
6634 if (val
== PARSE_FAIL
)
6635 po_imm_or_fail (0, 31);
6636 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6639 case AARCH64_OPND_BARRIER_PSB
:
6640 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6641 if (val
== PARSE_FAIL
)
6645 case AARCH64_OPND_BTI_TARGET
:
6646 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6647 if (val
== PARSE_FAIL
)
6652 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6655 /* If we get here, this operand was successfully parsed. */
6656 inst
.base
.operands
[i
].present
= 1;
6660 /* The parse routine should already have set the error, but in case
6661 not, set a default one here. */
6663 set_default_error ();
6665 if (! backtrack_pos
)
6666 goto parse_operands_return
;
6669 /* We reach here because this operand is marked as optional, and
6670 either no operand was supplied or the operand was supplied but it
6671 was syntactically incorrect. In the latter case we report an
6672 error. In the former case we perform a few more checks before
6673 dropping through to the code to insert the default operand. */
6675 char *tmp
= backtrack_pos
;
6676 char endchar
= END_OF_INSN
;
6678 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6680 skip_past_char (&tmp
, ',');
6682 if (*tmp
!= endchar
)
6683 /* The user has supplied an operand in the wrong format. */
6684 goto parse_operands_return
;
6686 /* Make sure there is not a comma before the optional operand.
6687 For example the fifth operand of 'sys' is optional:
6689 sys #0,c0,c0,#0, <--- wrong
6690 sys #0,c0,c0,#0 <--- correct. */
6691 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6693 set_fatal_syntax_error
6694 (_("unexpected comma before the omitted optional operand"));
6695 goto parse_operands_return
;
6699 /* Reaching here means we are dealing with an optional operand that is
6700 omitted from the assembly line. */
6701 gas_assert (optional_operand_p (opcode
, i
));
6703 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6705 /* Try again, skipping the optional operand at backtrack_pos. */
6706 str
= backtrack_pos
;
6709 /* Clear any error record after the omitted optional operand has been
6710 successfully handled. */
6714 /* Check if we have parsed all the operands. */
6715 if (*str
!= '\0' && ! error_p ())
6717 /* Set I to the index of the last present operand; this is
6718 for the purpose of diagnostics. */
6719 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6721 set_fatal_syntax_error
6722 (_("unexpected characters following instruction"));
6725 parse_operands_return
:
6729 DEBUG_TRACE ("parsing FAIL: %s - %s",
6730 operand_mismatch_kind_names
[get_error_kind ()],
6731 get_error_message ());
6732 /* Record the operand error properly; this is useful when there
6733 are multiple instruction templates for a mnemonic name, so that
6734 later on, we can select the error that most closely describes
6736 record_operand_error (opcode
, i
, get_error_kind (),
6737 get_error_message ());
6742 DEBUG_TRACE ("parsing SUCCESS");
6747 /* It does some fix-up to provide some programmer friendly feature while
6748 keeping the libopcodes happy, i.e. libopcodes only accepts
6749 the preferred architectural syntax.
6750 Return FALSE if there is any failure; otherwise return TRUE. */
6753 programmer_friendly_fixup (aarch64_instruction
*instr
)
6755 aarch64_inst
*base
= &instr
->base
;
6756 const aarch64_opcode
*opcode
= base
->opcode
;
6757 enum aarch64_op op
= opcode
->op
;
6758 aarch64_opnd_info
*operands
= base
->operands
;
6760 DEBUG_TRACE ("enter");
6762 switch (opcode
->iclass
)
6765 /* TBNZ Xn|Wn, #uimm6, label
6766 Test and Branch Not Zero: conditionally jumps to label if bit number
6767 uimm6 in register Xn is not zero. The bit number implies the width of
6768 the register, which may be written and should be disassembled as Wn if
6769 uimm is less than 32. */
6770 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6772 if (operands
[1].imm
.value
>= 32)
6774 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6778 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6782 /* LDR Wt, label | =value
6783 As a convenience assemblers will typically permit the notation
6784 "=value" in conjunction with the pc-relative literal load instructions
6785 to automatically place an immediate value or symbolic address in a
6786 nearby literal pool and generate a hidden label which references it.
6787 ISREG has been set to 0 in the case of =value. */
6788 if (instr
->gen_lit_pool
6789 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6791 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6792 if (op
== OP_LDRSW_LIT
)
6794 if (instr
->reloc
.exp
.X_op
!= O_constant
6795 && instr
->reloc
.exp
.X_op
!= O_big
6796 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6798 record_operand_error (opcode
, 1,
6799 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6800 _("constant expression expected"));
6803 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6805 record_operand_error (opcode
, 1,
6806 AARCH64_OPDE_OTHER_ERROR
,
6807 _("literal pool insertion failed"));
6815 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6816 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6817 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6818 A programmer-friendly assembler should accept a destination Xd in
6819 place of Wd, however that is not the preferred form for disassembly.
6821 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6822 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6823 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6824 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6829 /* In the 64-bit form, the final register operand is written as Wm
6830 for all but the (possibly omitted) UXTX/LSL and SXTX
6832 As a programmer-friendly assembler, we accept e.g.
6833 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6834 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6835 int idx
= aarch64_operand_index (opcode
->operands
,
6836 AARCH64_OPND_Rm_EXT
);
6837 gas_assert (idx
== 1 || idx
== 2);
6838 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6839 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6840 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6841 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6842 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6843 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6851 DEBUG_TRACE ("exit with SUCCESS");
6855 /* Check for loads and stores that will cause unpredictable behavior. */
6858 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6860 aarch64_inst
*base
= &instr
->base
;
6861 const aarch64_opcode
*opcode
= base
->opcode
;
6862 const aarch64_opnd_info
*opnds
= base
->operands
;
6863 switch (opcode
->iclass
)
6870 /* Loading/storing the base register is unpredictable if writeback. */
6871 if ((aarch64_get_operand_class (opnds
[0].type
)
6872 == AARCH64_OPND_CLASS_INT_REG
)
6873 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6874 && opnds
[1].addr
.base_regno
!= REG_SP
6875 /* Exempt STG/STZG/ST2G/STZ2G. */
6876 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6877 && opnds
[1].addr
.writeback
)
6878 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6882 case ldstnapair_offs
:
6883 case ldstpair_indexed
:
6884 /* Loading/storing the base register is unpredictable if writeback. */
6885 if ((aarch64_get_operand_class (opnds
[0].type
)
6886 == AARCH64_OPND_CLASS_INT_REG
)
6887 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6888 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6889 && opnds
[2].addr
.base_regno
!= REG_SP
6891 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6892 && opnds
[2].addr
.writeback
)
6893 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6894 /* Load operations must load different registers. */
6895 if ((opcode
->opcode
& (1 << 22))
6896 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6897 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6901 /* It is unpredictable if the destination and status registers are the
6903 if ((aarch64_get_operand_class (opnds
[0].type
)
6904 == AARCH64_OPND_CLASS_INT_REG
)
6905 && (aarch64_get_operand_class (opnds
[1].type
)
6906 == AARCH64_OPND_CLASS_INT_REG
)
6907 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6908 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6909 as_warn (_("unpredictable: identical transfer and status registers"
6921 force_automatic_sequence_close (void)
6923 if (now_instr_sequence
.instr
)
6925 as_warn (_("previous `%s' sequence has not been closed"),
6926 now_instr_sequence
.instr
->opcode
->name
);
6927 init_insn_sequence (NULL
, &now_instr_sequence
);
6931 /* A wrapper function to interface with libopcodes on encoding and
6932 record the error message if there is any.
6934 Return TRUE on success; otherwise return FALSE. */
6937 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6940 aarch64_operand_error error_info
;
6941 memset (&error_info
, '\0', sizeof (error_info
));
6942 error_info
.kind
= AARCH64_OPDE_NIL
;
6943 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6944 && !error_info
.non_fatal
)
6947 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6948 record_operand_error_info (opcode
, &error_info
);
6949 return error_info
.non_fatal
;
6952 #ifdef DEBUG_AARCH64
6954 dump_opcode_operands (const aarch64_opcode
*opcode
)
6957 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6959 aarch64_verbose ("\t\t opnd%d: %s", i
,
6960 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6961 ? aarch64_get_operand_name (opcode
->operands
[i
])
6962 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6966 #endif /* DEBUG_AARCH64 */
6968 /* This is the guts of the machine-dependent assembler. STR points to a
6969 machine dependent instruction. This function is supposed to emit
6970 the frags/bytes it assembles to. */
6973 md_assemble (char *str
)
6976 templates
*template;
6977 aarch64_opcode
*opcode
;
6978 aarch64_inst
*inst_base
;
6979 unsigned saved_cond
;
6981 /* Align the previous label if needed. */
6982 if (last_label_seen
!= NULL
)
6984 symbol_set_frag (last_label_seen
, frag_now
);
6985 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6986 S_SET_SEGMENT (last_label_seen
, now_seg
);
6989 /* Update the current insn_sequence from the segment. */
6990 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6992 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6994 DEBUG_TRACE ("\n\n");
6995 DEBUG_TRACE ("==============================");
6996 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6998 template = opcode_lookup (&p
);
7001 /* It wasn't an instruction, but it might be a register alias of
7002 the form alias .req reg directive. */
7003 if (!create_register_alias (str
, p
))
7004 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7009 skip_whitespace (p
);
7012 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7013 get_mnemonic_name (str
), str
);
7017 init_operand_error_report ();
7019 /* Sections are assumed to start aligned. In executable section, there is no
7020 MAP_DATA symbol pending. So we only align the address during
7021 MAP_DATA --> MAP_INSN transition.
7022 For other sections, this is not guaranteed. */
7023 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7024 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7025 frag_align_code (2, 0);
7027 saved_cond
= inst
.cond
;
7028 reset_aarch64_instruction (&inst
);
7029 inst
.cond
= saved_cond
;
7031 /* Iterate through all opcode entries with the same mnemonic name. */
7034 opcode
= template->opcode
;
7036 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7037 #ifdef DEBUG_AARCH64
7039 dump_opcode_operands (opcode
);
7040 #endif /* DEBUG_AARCH64 */
7042 mapping_state (MAP_INSN
);
7044 inst_base
= &inst
.base
;
7045 inst_base
->opcode
= opcode
;
7047 /* Truly conditionally executed instructions, e.g. b.cond. */
7048 if (opcode
->flags
& F_COND
)
7050 gas_assert (inst
.cond
!= COND_ALWAYS
);
7051 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7052 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7054 else if (inst
.cond
!= COND_ALWAYS
)
7056 /* It shouldn't arrive here, where the assembly looks like a
7057 conditional instruction but the found opcode is unconditional. */
7062 if (parse_operands (p
, opcode
)
7063 && programmer_friendly_fixup (&inst
)
7064 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7066 /* Check that this instruction is supported for this CPU. */
7067 if (!opcode
->avariant
7068 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7070 as_bad (_("selected processor does not support `%s'"), str
);
7074 warn_unpredictable_ldst (&inst
, str
);
7076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7077 || !inst
.reloc
.need_libopcodes_p
)
7081 /* If there is relocation generated for the instruction,
7082 store the instruction information for the future fix-up. */
7083 struct aarch64_inst
*copy
;
7084 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7085 copy
= XNEW (struct aarch64_inst
);
7086 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7090 /* Issue non-fatal messages if any. */
7091 output_operand_error_report (str
, TRUE
);
7095 template = template->next
;
7096 if (template != NULL
)
7098 reset_aarch64_instruction (&inst
);
7099 inst
.cond
= saved_cond
;
7102 while (template != NULL
);
7104 /* Issue the error messages if any. */
7105 output_operand_error_report (str
, FALSE
);
7108 /* Various frobbings of labels and their addresses. */
7111 aarch64_start_line_hook (void)
7113 last_label_seen
= NULL
;
7117 aarch64_frob_label (symbolS
* sym
)
7119 last_label_seen
= sym
;
7121 dwarf2_emit_label (sym
);
7125 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7127 /* Check to see if we have a block to close. */
7128 force_automatic_sequence_close ();
7132 aarch64_data_in_code (void)
7134 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7136 *input_line_pointer
= '/';
7137 input_line_pointer
+= 5;
7138 *input_line_pointer
= 0;
7146 aarch64_canonicalize_symbol_name (char *name
)
7150 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7151 *(name
+ len
- 5) = 0;
7156 /* Table of all register names defined by default. The user can
7157 define additional names with .req. Note that all register names
7158 should appear in both upper and lowercase variants. Some registers
7159 also have mixed-case names. */
7161 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7162 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7163 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7164 #define REGSET16(p,t) \
7165 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7166 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7167 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7168 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7169 #define REGSET31(p,t) \
7171 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7172 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7173 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7174 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7175 #define REGSET(p,t) \
7176 REGSET31(p,t), REGNUM(p,31,t)
7178 /* These go into aarch64_reg_hsh hash-table. */
7179 static const reg_entry reg_names
[] = {
7180 /* Integer registers. */
7181 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7182 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7184 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7185 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7186 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7187 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7188 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7189 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7191 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7192 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7194 /* Floating-point single precision registers. */
7195 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7197 /* Floating-point double precision registers. */
7198 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7200 /* Floating-point half precision registers. */
7201 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7203 /* Floating-point byte precision registers. */
7204 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7206 /* Floating-point quad precision registers. */
7207 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7209 /* FP/SIMD registers. */
7210 REGSET (v
, VN
), REGSET (V
, VN
),
7212 /* SVE vector registers. */
7213 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7215 /* SVE predicate registers. */
7216 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7234 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7235 static const asm_nzcv nzcv_names
[] = {
7236 {"nzcv", B (n
, z
, c
, v
)},
7237 {"nzcV", B (n
, z
, c
, V
)},
7238 {"nzCv", B (n
, z
, C
, v
)},
7239 {"nzCV", B (n
, z
, C
, V
)},
7240 {"nZcv", B (n
, Z
, c
, v
)},
7241 {"nZcV", B (n
, Z
, c
, V
)},
7242 {"nZCv", B (n
, Z
, C
, v
)},
7243 {"nZCV", B (n
, Z
, C
, V
)},
7244 {"Nzcv", B (N
, z
, c
, v
)},
7245 {"NzcV", B (N
, z
, c
, V
)},
7246 {"NzCv", B (N
, z
, C
, v
)},
7247 {"NzCV", B (N
, z
, C
, V
)},
7248 {"NZcv", B (N
, Z
, c
, v
)},
7249 {"NZcV", B (N
, Z
, c
, V
)},
7250 {"NZCv", B (N
, Z
, C
, v
)},
7251 {"NZCV", B (N
, Z
, C
, V
)}
7264 /* MD interface: bits in the object file. */
7266 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7267 for use in the a.out file, and stores them in the array pointed to by buf.
7268 This knows about the endian-ness of the target machine and does
7269 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7270 2 (short) and 4 (long) Floating numbers are put out as a series of
7271 LITTLENUMS (shorts, here at least). */
7274 md_number_to_chars (char *buf
, valueT val
, int n
)
7276 if (target_big_endian
)
7277 number_to_chars_bigendian (buf
, val
, n
);
7279 number_to_chars_littleendian (buf
, val
, n
);
7282 /* MD interface: Sections. */
7284 /* Estimate the size of a frag before relaxing. Assume everything fits in
7288 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7294 /* Round up a section size to the appropriate boundary. */
7297 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7302 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7303 of an rs_align_code fragment.
7305 Here we fill the frag with the appropriate info for padding the
7306 output stream. The resulting frag will consist of a fixed (fr_fix)
7307 and of a repeating (fr_var) part.
7309 The fixed content is always emitted before the repeating content and
7310 these two parts are used as follows in constructing the output:
7311 - the fixed part will be used to align to a valid instruction word
7312 boundary, in case that we start at a misaligned address; as no
7313 executable instruction can live at the misaligned location, we
7314 simply fill with zeros;
7315 - the variable part will be used to cover the remaining padding and
7316 we fill using the AArch64 NOP instruction.
7318 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7319 enough storage space for up to 3 bytes for padding the back to a valid
7320 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7323 aarch64_handle_align (fragS
* fragP
)
7325 /* NOP = d503201f */
7326 /* AArch64 instructions are always little-endian. */
7327 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7329 int bytes
, fix
, noop_size
;
7332 if (fragP
->fr_type
!= rs_align_code
)
7335 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7336 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7339 gas_assert (fragP
->tc_frag_data
.recorded
);
7342 noop_size
= sizeof (aarch64_noop
);
7344 fix
= bytes
& (noop_size
- 1);
7348 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7352 fragP
->fr_fix
+= fix
;
7356 memcpy (p
, aarch64_noop
, noop_size
);
7357 fragP
->fr_var
= noop_size
;
7360 /* Perform target specific initialisation of a frag.
7361 Note - despite the name this initialisation is not done when the frag
7362 is created, but only when its type is assigned. A frag can be created
7363 and used a long time before its type is set, so beware of assuming that
7364 this initialisation is performed first. */
7368 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7369 int max_chars ATTRIBUTE_UNUSED
)
7373 #else /* OBJ_ELF is defined. */
7375 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7377 /* Record a mapping symbol for alignment frags. We will delete this
7378 later if the alignment ends up empty. */
7379 if (!fragP
->tc_frag_data
.recorded
)
7380 fragP
->tc_frag_data
.recorded
= 1;
7382 /* PR 21809: Do not set a mapping state for debug sections
7383 - it just confuses other tools. */
7384 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7387 switch (fragP
->fr_type
)
7391 mapping_state_2 (MAP_DATA
, max_chars
);
7394 /* PR 20364: We can get alignment frags in code sections,
7395 so do not just assume that we should use the MAP_DATA state. */
7396 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7399 mapping_state_2 (MAP_INSN
, max_chars
);
7406 /* Initialize the DWARF-2 unwind information for this procedure. */
7409 tc_aarch64_frame_initial_instructions (void)
7411 cfi_add_CFA_def_cfa (REG_SP
, 0);
7413 #endif /* OBJ_ELF */
7415 /* Convert REGNAME to a DWARF-2 register number. */
7418 tc_aarch64_regname_to_dw2regnum (char *regname
)
7420 const reg_entry
*reg
= parse_reg (®name
);
7426 case REG_TYPE_SP_32
:
7427 case REG_TYPE_SP_64
:
7437 return reg
->number
+ 64;
7445 /* Implement DWARF2_ADDR_SIZE. */
7448 aarch64_dwarf2_addr_size (void)
7450 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7454 return bfd_arch_bits_per_address (stdoutput
) / 8;
7457 /* MD interface: Symbol and relocation handling. */
7459 /* Return the address within the segment that a PC-relative fixup is
7460 relative to. For AArch64 PC-relative fixups applied to instructions
7461 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7464 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7466 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7468 /* If this is pc-relative and we are going to emit a relocation
7469 then we just want to put out any pipeline compensation that the linker
7470 will need. Otherwise we want to use the calculated base. */
7472 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7473 || aarch64_force_relocation (fixP
)))
7476 /* AArch64 should be consistent for all pc-relative relocations. */
7477 return base
+ AARCH64_PCREL_OFFSET
;
7480 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7481 Otherwise we have no need to default values of symbols. */
7484 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7487 if (name
[0] == '_' && name
[1] == 'G'
7488 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7492 if (symbol_find (name
))
7493 as_bad (_("GOT already in the symbol table"));
7495 GOT_symbol
= symbol_new (name
, undefined_section
,
7496 (valueT
) 0, &zero_address_frag
);
7506 /* Return non-zero if the indicated VALUE has overflowed the maximum
7507 range expressible by a unsigned number with the indicated number of
7511 unsigned_overflow (valueT value
, unsigned bits
)
7514 if (bits
>= sizeof (valueT
) * 8)
7516 lim
= (valueT
) 1 << bits
;
7517 return (value
>= lim
);
7521 /* Return non-zero if the indicated VALUE has overflowed the maximum
7522 range expressible by an signed number with the indicated number of
7526 signed_overflow (offsetT value
, unsigned bits
)
7529 if (bits
>= sizeof (offsetT
) * 8)
7531 lim
= (offsetT
) 1 << (bits
- 1);
7532 return (value
< -lim
|| value
>= lim
);
7535 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7536 unsigned immediate offset load/store instruction, try to encode it as
7537 an unscaled, 9-bit, signed immediate offset load/store instruction.
7538 Return TRUE if it is successful; otherwise return FALSE.
7540 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7541 in response to the standard LDR/STR mnemonics when the immediate offset is
7542 unambiguous, i.e. when it is negative or unaligned. */
7545 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7548 enum aarch64_op new_op
;
7549 const aarch64_opcode
*new_opcode
;
7551 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7553 switch (instr
->opcode
->op
)
7555 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7556 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7557 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7558 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7559 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7560 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7561 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7562 case OP_STR_POS
: new_op
= OP_STUR
; break;
7563 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7564 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7565 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7566 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7567 default: new_op
= OP_NIL
; break;
7570 if (new_op
== OP_NIL
)
7573 new_opcode
= aarch64_get_opcode (new_op
);
7574 gas_assert (new_opcode
!= NULL
);
7576 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7577 instr
->opcode
->op
, new_opcode
->op
);
7579 aarch64_replace_opcode (instr
, new_opcode
);
7581 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7582 qualifier matching may fail because the out-of-date qualifier will
7583 prevent the operand being updated with a new and correct qualifier. */
7584 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7585 AARCH64_OPND_ADDR_SIMM9
);
7586 gas_assert (idx
== 1);
7587 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7589 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7591 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7598 /* Called by fix_insn to fix a MOV immediate alias instruction.
7600 Operand for a generic move immediate instruction, which is an alias
7601 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7602 a 32-bit/64-bit immediate value into general register. An assembler error
7603 shall result if the immediate cannot be created by a single one of these
7604 instructions. If there is a choice, then to ensure reversability an
7605 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7608 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7610 const aarch64_opcode
*opcode
;
7612 /* Need to check if the destination is SP/ZR. The check has to be done
7613 before any aarch64_replace_opcode. */
7614 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7615 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7617 instr
->operands
[1].imm
.value
= value
;
7618 instr
->operands
[1].skip
= 0;
7622 /* Try the MOVZ alias. */
7623 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7624 aarch64_replace_opcode (instr
, opcode
);
7625 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7626 &instr
->value
, NULL
, NULL
, insn_sequence
))
7628 put_aarch64_insn (buf
, instr
->value
);
7631 /* Try the MOVK alias. */
7632 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7633 aarch64_replace_opcode (instr
, opcode
);
7634 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7635 &instr
->value
, NULL
, NULL
, insn_sequence
))
7637 put_aarch64_insn (buf
, instr
->value
);
7642 if (try_mov_bitmask_p
)
7644 /* Try the ORR alias. */
7645 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7646 aarch64_replace_opcode (instr
, opcode
);
7647 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7648 &instr
->value
, NULL
, NULL
, insn_sequence
))
7650 put_aarch64_insn (buf
, instr
->value
);
7655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7656 _("immediate cannot be moved by a single instruction"));
7659 /* An instruction operand which is immediate related may have symbol used
7660 in the assembly, e.g.
7663 .set u32, 0x00ffff00
7665 At the time when the assembly instruction is parsed, a referenced symbol,
7666 like 'u32' in the above example may not have been seen; a fixS is created
7667 in such a case and is handled here after symbols have been resolved.
7668 Instruction is fixed up with VALUE using the information in *FIXP plus
7669 extra information in FLAGS.
7671 This function is called by md_apply_fix to fix up instructions that need
7672 a fix-up described above but does not involve any linker-time relocation. */
7675 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7679 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7680 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7681 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7685 /* Now the instruction is about to be fixed-up, so the operand that
7686 was previously marked as 'ignored' needs to be unmarked in order
7687 to get the encoding done properly. */
7688 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7689 new_inst
->operands
[idx
].skip
= 0;
7692 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7696 case AARCH64_OPND_EXCEPTION
:
7697 if (unsigned_overflow (value
, 16))
7698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7699 _("immediate out of range"));
7700 insn
= get_aarch64_insn (buf
);
7701 insn
|= encode_svc_imm (value
);
7702 put_aarch64_insn (buf
, insn
);
7705 case AARCH64_OPND_AIMM
:
7706 /* ADD or SUB with immediate.
7707 NOTE this assumes we come here with a add/sub shifted reg encoding
7708 3 322|2222|2 2 2 21111 111111
7709 1 098|7654|3 2 1 09876 543210 98765 43210
7710 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7711 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7712 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7713 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7715 3 322|2222|2 2 221111111111
7716 1 098|7654|3 2 109876543210 98765 43210
7717 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7718 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7719 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7720 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7721 Fields sf Rn Rd are already set. */
7722 insn
= get_aarch64_insn (buf
);
7726 insn
= reencode_addsub_switch_add_sub (insn
);
7730 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7731 && unsigned_overflow (value
, 12))
7733 /* Try to shift the value by 12 to make it fit. */
7734 if (((value
>> 12) << 12) == value
7735 && ! unsigned_overflow (value
, 12 + 12))
7738 insn
|= encode_addsub_imm_shift_amount (1);
7742 if (unsigned_overflow (value
, 12))
7743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7744 _("immediate out of range"));
7746 insn
|= encode_addsub_imm (value
);
7748 put_aarch64_insn (buf
, insn
);
7751 case AARCH64_OPND_SIMD_IMM
:
7752 case AARCH64_OPND_SIMD_IMM_SFT
:
7753 case AARCH64_OPND_LIMM
:
7754 /* Bit mask immediate. */
7755 gas_assert (new_inst
!= NULL
);
7756 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7757 new_inst
->operands
[idx
].imm
.value
= value
;
7758 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7759 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7760 put_aarch64_insn (buf
, new_inst
->value
);
7762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7763 _("invalid immediate"));
7766 case AARCH64_OPND_HALF
:
7767 /* 16-bit unsigned immediate. */
7768 if (unsigned_overflow (value
, 16))
7769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7770 _("immediate out of range"));
7771 insn
= get_aarch64_insn (buf
);
7772 insn
|= encode_movw_imm (value
& 0xffff);
7773 put_aarch64_insn (buf
, insn
);
7776 case AARCH64_OPND_IMM_MOV
:
7777 /* Operand for a generic move immediate instruction, which is
7778 an alias instruction that generates a single MOVZ, MOVN or ORR
7779 instruction to loads a 32-bit/64-bit immediate value into general
7780 register. An assembler error shall result if the immediate cannot be
7781 created by a single one of these instructions. If there is a choice,
7782 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7783 and MOVZ or MOVN to ORR. */
7784 gas_assert (new_inst
!= NULL
);
7785 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7788 case AARCH64_OPND_ADDR_SIMM7
:
7789 case AARCH64_OPND_ADDR_SIMM9
:
7790 case AARCH64_OPND_ADDR_SIMM9_2
:
7791 case AARCH64_OPND_ADDR_SIMM10
:
7792 case AARCH64_OPND_ADDR_UIMM12
:
7793 case AARCH64_OPND_ADDR_SIMM11
:
7794 case AARCH64_OPND_ADDR_SIMM13
:
7795 /* Immediate offset in an address. */
7796 insn
= get_aarch64_insn (buf
);
7798 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7799 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7800 || new_inst
->opcode
->operands
[2] == opnd
);
7802 /* Get the index of the address operand. */
7803 if (new_inst
->opcode
->operands
[1] == opnd
)
7804 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7807 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7810 /* Update the resolved offset value. */
7811 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7813 /* Encode/fix-up. */
7814 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7815 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7817 put_aarch64_insn (buf
, new_inst
->value
);
7820 else if (new_inst
->opcode
->iclass
== ldst_pos
7821 && try_to_encode_as_unscaled_ldst (new_inst
))
7823 put_aarch64_insn (buf
, new_inst
->value
);
7827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7828 _("immediate offset out of range"));
7833 as_fatal (_("unhandled operand code %d"), opnd
);
7837 /* Apply a fixup (fixP) to segment data, once it has been determined
7838 by our caller that we have all the info we need to fix it up.
7840 Parameter valP is the pointer to the value of the bits. */
7843 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7845 offsetT value
= *valP
;
7847 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7849 unsigned flags
= fixP
->fx_addnumber
;
7851 DEBUG_TRACE ("\n\n");
7852 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7853 DEBUG_TRACE ("Enter md_apply_fix");
7855 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7857 /* Note whether this will delete the relocation. */
7859 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7862 /* Process the relocations. */
7863 switch (fixP
->fx_r_type
)
7865 case BFD_RELOC_NONE
:
7866 /* This will need to go in the object file. */
7871 case BFD_RELOC_8_PCREL
:
7872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7873 md_number_to_chars (buf
, value
, 1);
7877 case BFD_RELOC_16_PCREL
:
7878 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7879 md_number_to_chars (buf
, value
, 2);
7883 case BFD_RELOC_32_PCREL
:
7884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7885 md_number_to_chars (buf
, value
, 4);
7889 case BFD_RELOC_64_PCREL
:
7890 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7891 md_number_to_chars (buf
, value
, 8);
7894 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7895 /* We claim that these fixups have been processed here, even if
7896 in fact we generate an error because we do not have a reloc
7897 for them, so tc_gen_reloc() will reject them. */
7899 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7902 _("undefined symbol %s used as an immediate value"),
7903 S_GET_NAME (fixP
->fx_addsy
));
7904 goto apply_fix_return
;
7906 fix_insn (fixP
, flags
, value
);
7909 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7910 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7914 _("pc-relative load offset not word aligned"));
7915 if (signed_overflow (value
, 21))
7916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7917 _("pc-relative load offset out of range"));
7918 insn
= get_aarch64_insn (buf
);
7919 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7920 put_aarch64_insn (buf
, insn
);
7924 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7925 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7927 if (signed_overflow (value
, 21))
7928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7929 _("pc-relative address offset out of range"));
7930 insn
= get_aarch64_insn (buf
);
7931 insn
|= encode_adr_imm (value
);
7932 put_aarch64_insn (buf
, insn
);
7936 case BFD_RELOC_AARCH64_BRANCH19
:
7937 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7941 _("conditional branch target not word aligned"));
7942 if (signed_overflow (value
, 21))
7943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7944 _("conditional branch out of range"));
7945 insn
= get_aarch64_insn (buf
);
7946 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7947 put_aarch64_insn (buf
, insn
);
7951 case BFD_RELOC_AARCH64_TSTBR14
:
7952 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7956 _("conditional branch target not word aligned"));
7957 if (signed_overflow (value
, 16))
7958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7959 _("conditional branch out of range"));
7960 insn
= get_aarch64_insn (buf
);
7961 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7962 put_aarch64_insn (buf
, insn
);
7966 case BFD_RELOC_AARCH64_CALL26
:
7967 case BFD_RELOC_AARCH64_JUMP26
:
7968 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7972 _("branch target not word aligned"));
7973 if (signed_overflow (value
, 28))
7974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7975 _("branch out of range"));
7976 insn
= get_aarch64_insn (buf
);
7977 insn
|= encode_branch_ofs_26 (value
>> 2);
7978 put_aarch64_insn (buf
, insn
);
7982 case BFD_RELOC_AARCH64_MOVW_G0
:
7983 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7984 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7985 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7986 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7987 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7990 case BFD_RELOC_AARCH64_MOVW_G1
:
7991 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7992 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7993 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7994 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7995 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7998 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8000 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8001 /* Should always be exported to object file, see
8002 aarch64_force_relocation(). */
8003 gas_assert (!fixP
->fx_done
);
8004 gas_assert (seg
->use_rela_p
);
8006 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8008 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8009 /* Should always be exported to object file, see
8010 aarch64_force_relocation(). */
8011 gas_assert (!fixP
->fx_done
);
8012 gas_assert (seg
->use_rela_p
);
8014 case BFD_RELOC_AARCH64_MOVW_G2
:
8015 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8016 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8017 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8018 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8021 case BFD_RELOC_AARCH64_MOVW_G3
:
8022 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8025 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8027 insn
= get_aarch64_insn (buf
);
8031 /* REL signed addend must fit in 16 bits */
8032 if (signed_overflow (value
, 16))
8033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8034 _("offset out of range"));
8038 /* Check for overflow and scale. */
8039 switch (fixP
->fx_r_type
)
8041 case BFD_RELOC_AARCH64_MOVW_G0
:
8042 case BFD_RELOC_AARCH64_MOVW_G1
:
8043 case BFD_RELOC_AARCH64_MOVW_G2
:
8044 case BFD_RELOC_AARCH64_MOVW_G3
:
8045 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8046 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8047 if (unsigned_overflow (value
, scale
+ 16))
8048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8049 _("unsigned value out of range"));
8051 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8052 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8053 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8054 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8055 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8056 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8057 /* NOTE: We can only come here with movz or movn. */
8058 if (signed_overflow (value
, scale
+ 16))
8059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8060 _("signed value out of range"));
8063 /* Force use of MOVN. */
8065 insn
= reencode_movzn_to_movn (insn
);
8069 /* Force use of MOVZ. */
8070 insn
= reencode_movzn_to_movz (insn
);
8074 /* Unchecked relocations. */
8080 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8081 insn
|= encode_movw_imm (value
& 0xffff);
8083 put_aarch64_insn (buf
, insn
);
8087 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8088 fixP
->fx_r_type
= (ilp32_p
8089 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8090 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8091 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8092 /* Should always be exported to object file, see
8093 aarch64_force_relocation(). */
8094 gas_assert (!fixP
->fx_done
);
8095 gas_assert (seg
->use_rela_p
);
8098 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8099 fixP
->fx_r_type
= (ilp32_p
8100 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8101 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8102 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8103 /* Should always be exported to object file, see
8104 aarch64_force_relocation(). */
8105 gas_assert (!fixP
->fx_done
);
8106 gas_assert (seg
->use_rela_p
);
8109 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8110 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8111 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8112 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8113 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8114 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8115 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8116 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8117 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8118 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8119 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8120 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8121 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8122 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8123 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8124 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8125 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8126 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8127 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8128 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8129 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8130 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8131 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8132 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8133 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8134 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8135 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8136 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8137 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8138 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8139 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8140 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8141 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8142 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8143 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8144 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8145 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8146 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8147 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8148 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8149 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8150 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8151 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8152 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8153 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8154 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8155 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8156 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8157 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8158 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8159 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8160 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8161 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8162 /* Should always be exported to object file, see
8163 aarch64_force_relocation(). */
8164 gas_assert (!fixP
->fx_done
);
8165 gas_assert (seg
->use_rela_p
);
8168 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8169 /* Should always be exported to object file, see
8170 aarch64_force_relocation(). */
8171 fixP
->fx_r_type
= (ilp32_p
8172 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8173 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8174 gas_assert (!fixP
->fx_done
);
8175 gas_assert (seg
->use_rela_p
);
8178 case BFD_RELOC_AARCH64_ADD_LO12
:
8179 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8180 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8181 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8182 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8183 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8184 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8185 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8186 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8187 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8188 case BFD_RELOC_AARCH64_LDST128_LO12
:
8189 case BFD_RELOC_AARCH64_LDST16_LO12
:
8190 case BFD_RELOC_AARCH64_LDST32_LO12
:
8191 case BFD_RELOC_AARCH64_LDST64_LO12
:
8192 case BFD_RELOC_AARCH64_LDST8_LO12
:
8193 /* Should always be exported to object file, see
8194 aarch64_force_relocation(). */
8195 gas_assert (!fixP
->fx_done
);
8196 gas_assert (seg
->use_rela_p
);
8199 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8200 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8201 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8204 case BFD_RELOC_UNUSED
:
8205 /* An error will already have been reported. */
8209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8210 _("unexpected %s fixup"),
8211 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8216 /* Free the allocated the struct aarch64_inst.
8217 N.B. currently there are very limited number of fix-up types actually use
8218 this field, so the impact on the performance should be minimal . */
8219 if (fixP
->tc_fix_data
.inst
!= NULL
)
8220 free (fixP
->tc_fix_data
.inst
);
8225 /* Translate internal representation of relocation info to BFD target
8229 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8232 bfd_reloc_code_real_type code
;
8234 reloc
= XNEW (arelent
);
8236 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8237 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8238 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8242 if (section
->use_rela_p
)
8243 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8245 fixp
->fx_offset
= reloc
->address
;
8247 reloc
->addend
= fixp
->fx_offset
;
8249 code
= fixp
->fx_r_type
;
8254 code
= BFD_RELOC_16_PCREL
;
8259 code
= BFD_RELOC_32_PCREL
;
8264 code
= BFD_RELOC_64_PCREL
;
8271 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8272 if (reloc
->howto
== NULL
)
8274 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8276 ("cannot represent %s relocation in this object file format"),
8277 bfd_get_reloc_code_name (code
));
8284 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8287 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8289 bfd_reloc_code_real_type type
;
8293 FIXME: @@ Should look at CPU word size. */
8300 type
= BFD_RELOC_16
;
8303 type
= BFD_RELOC_32
;
8306 type
= BFD_RELOC_64
;
8309 as_bad (_("cannot do %u-byte relocation"), size
);
8310 type
= BFD_RELOC_UNUSED
;
8314 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8318 aarch64_force_relocation (struct fix
*fixp
)
8320 switch (fixp
->fx_r_type
)
8322 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8323 /* Perform these "immediate" internal relocations
8324 even if the symbol is extern or weak. */
8327 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8328 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8329 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8330 /* Pseudo relocs that need to be fixed up according to
8334 case BFD_RELOC_AARCH64_ADD_LO12
:
8335 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8336 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8337 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8338 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8339 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8340 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8341 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8342 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8343 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8344 case BFD_RELOC_AARCH64_LDST128_LO12
:
8345 case BFD_RELOC_AARCH64_LDST16_LO12
:
8346 case BFD_RELOC_AARCH64_LDST32_LO12
:
8347 case BFD_RELOC_AARCH64_LDST64_LO12
:
8348 case BFD_RELOC_AARCH64_LDST8_LO12
:
8349 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8350 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8351 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8352 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8353 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8354 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8355 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8356 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8357 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8358 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8359 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8360 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8361 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8362 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8363 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8364 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8365 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8366 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8367 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8368 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8369 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8370 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8371 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8372 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8373 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8374 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8375 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8376 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8377 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8378 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8379 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8380 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8381 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8382 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8383 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8384 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8385 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8386 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8387 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8388 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8389 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8390 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8391 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8392 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8393 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8394 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8395 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8396 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8397 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8398 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8399 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8400 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8401 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8402 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8403 /* Always leave these relocations for the linker. */
8410 return generic_force_reloc (fixp
);
8415 /* Implement md_after_parse_args. This is the earliest time we need to decide
8416 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8419 aarch64_after_parse_args (void)
8421 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8424 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8425 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8426 aarch64_abi
= AARCH64_ABI_ILP32
;
8428 aarch64_abi
= AARCH64_ABI_LP64
;
8432 elf64_aarch64_target_format (void)
8435 /* FIXME: What to do for ilp32_p ? */
8436 if (target_big_endian
)
8437 return "elf64-bigaarch64-cloudabi";
8439 return "elf64-littleaarch64-cloudabi";
8441 if (target_big_endian
)
8442 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8444 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8449 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8451 elf_frob_symbol (symp
, puntp
);
8455 /* MD interface: Finalization. */
8457 /* A good place to do this, although this was probably not intended
8458 for this kind of use. We need to dump the literal pool before
8459 references are made to a null symbol pointer. */
8462 aarch64_cleanup (void)
8466 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8468 /* Put it at the end of the relevant section. */
8469 subseg_set (pool
->section
, pool
->sub_section
);
8475 /* Remove any excess mapping symbols generated for alignment frags in
8476 SEC. We may have created a mapping symbol before a zero byte
8477 alignment; remove it if there's a mapping symbol after the
8480 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8481 void *dummy ATTRIBUTE_UNUSED
)
8483 segment_info_type
*seginfo
= seg_info (sec
);
8486 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8489 for (fragp
= seginfo
->frchainP
->frch_root
;
8490 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8492 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8493 fragS
*next
= fragp
->fr_next
;
8495 /* Variable-sized frags have been converted to fixed size by
8496 this point. But if this was variable-sized to start with,
8497 there will be a fixed-size frag after it. So don't handle
8499 if (sym
== NULL
|| next
== NULL
)
8502 if (S_GET_VALUE (sym
) < next
->fr_address
)
8503 /* Not at the end of this frag. */
8505 know (S_GET_VALUE (sym
) == next
->fr_address
);
8509 if (next
->tc_frag_data
.first_map
!= NULL
)
8511 /* Next frag starts with a mapping symbol. Discard this
8513 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8517 if (next
->fr_next
== NULL
)
8519 /* This mapping symbol is at the end of the section. Discard
8521 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8522 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8526 /* As long as we have empty frags without any mapping symbols,
8528 /* If the next frag is non-empty and does not start with a
8529 mapping symbol, then this mapping symbol is required. */
8530 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8533 next
= next
->fr_next
;
8535 while (next
!= NULL
);
8540 /* Adjust the symbol table. */
8543 aarch64_adjust_symtab (void)
8546 /* Remove any overlapping mapping symbols generated by alignment frags. */
8547 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8548 /* Now do generic ELF adjustments. */
8549 elf_adjust_symtab ();
8554 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8556 const char *hash_err
;
8558 hash_err
= hash_insert (table
, key
, value
);
8560 printf ("Internal Error: Can't hash %s\n", key
);
8564 fill_instruction_hash_table (void)
8566 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8568 while (opcode
->name
!= NULL
)
8570 templates
*templ
, *new_templ
;
8571 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8573 new_templ
= XNEW (templates
);
8574 new_templ
->opcode
= opcode
;
8575 new_templ
->next
= NULL
;
8578 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8581 new_templ
->next
= templ
->next
;
8582 templ
->next
= new_templ
;
8589 convert_to_upper (char *dst
, const char *src
, size_t num
)
8592 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8593 *dst
= TOUPPER (*src
);
8597 /* Assume STR point to a lower-case string, allocate, convert and return
8598 the corresponding upper-case string. */
8599 static inline const char*
8600 get_upper_str (const char *str
)
8603 size_t len
= strlen (str
);
8604 ret
= XNEWVEC (char, len
+ 1);
8605 convert_to_upper (ret
, str
, len
);
8609 /* MD interface: Initialization. */
8617 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8618 || (aarch64_cond_hsh
= hash_new ()) == NULL
8619 || (aarch64_shift_hsh
= hash_new ()) == NULL
8620 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8621 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8622 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8623 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8624 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8625 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8626 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8627 || (aarch64_reg_hsh
= hash_new ()) == NULL
8628 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8629 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8630 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8631 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8632 as_fatal (_("virtual memory exhausted"));
8634 fill_instruction_hash_table ();
8636 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8637 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8638 (void *) (aarch64_sys_regs
+ i
));
8640 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8641 checked_hash_insert (aarch64_pstatefield_hsh
,
8642 aarch64_pstatefields
[i
].name
,
8643 (void *) (aarch64_pstatefields
+ i
));
8645 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8646 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8647 aarch64_sys_regs_ic
[i
].name
,
8648 (void *) (aarch64_sys_regs_ic
+ i
));
8650 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8651 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8652 aarch64_sys_regs_dc
[i
].name
,
8653 (void *) (aarch64_sys_regs_dc
+ i
));
8655 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8656 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8657 aarch64_sys_regs_at
[i
].name
,
8658 (void *) (aarch64_sys_regs_at
+ i
));
8660 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8661 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8662 aarch64_sys_regs_tlbi
[i
].name
,
8663 (void *) (aarch64_sys_regs_tlbi
+ i
));
8665 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8666 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8667 aarch64_sys_regs_sr
[i
].name
,
8668 (void *) (aarch64_sys_regs_sr
+ i
));
8670 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8671 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8672 (void *) (reg_names
+ i
));
8674 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8675 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8676 (void *) (nzcv_names
+ i
));
8678 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8680 const char *name
= aarch64_operand_modifiers
[i
].name
;
8681 checked_hash_insert (aarch64_shift_hsh
, name
,
8682 (void *) (aarch64_operand_modifiers
+ i
));
8683 /* Also hash the name in the upper case. */
8684 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8685 (void *) (aarch64_operand_modifiers
+ i
));
8688 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8691 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8692 the same condition code. */
8693 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8695 const char *name
= aarch64_conds
[i
].names
[j
];
8698 checked_hash_insert (aarch64_cond_hsh
, name
,
8699 (void *) (aarch64_conds
+ i
));
8700 /* Also hash the name in the upper case. */
8701 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8702 (void *) (aarch64_conds
+ i
));
8706 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8708 const char *name
= aarch64_barrier_options
[i
].name
;
8709 /* Skip xx00 - the unallocated values of option. */
8712 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8713 (void *) (aarch64_barrier_options
+ i
));
8714 /* Also hash the name in the upper case. */
8715 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8716 (void *) (aarch64_barrier_options
+ i
));
8719 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8721 const char* name
= aarch64_prfops
[i
].name
;
8722 /* Skip the unallocated hint encodings. */
8725 checked_hash_insert (aarch64_pldop_hsh
, name
,
8726 (void *) (aarch64_prfops
+ i
));
8727 /* Also hash the name in the upper case. */
8728 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8729 (void *) (aarch64_prfops
+ i
));
8732 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8734 const char* name
= aarch64_hint_options
[i
].name
;
8736 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8737 (void *) (aarch64_hint_options
+ i
));
8738 /* Also hash the name in the upper case. */
8739 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8740 (void *) (aarch64_hint_options
+ i
));
8743 /* Set the cpu variant based on the command-line options. */
8745 mcpu_cpu_opt
= march_cpu_opt
;
8748 mcpu_cpu_opt
= &cpu_default
;
8750 cpu_variant
= *mcpu_cpu_opt
;
8752 /* Record the CPU type. */
8753 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8755 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8758 /* Command line processing. */
8760 const char *md_shortopts
= "m:";
8762 #ifdef AARCH64_BI_ENDIAN
8763 #define OPTION_EB (OPTION_MD_BASE + 0)
8764 #define OPTION_EL (OPTION_MD_BASE + 1)
8766 #if TARGET_BYTES_BIG_ENDIAN
8767 #define OPTION_EB (OPTION_MD_BASE + 0)
8769 #define OPTION_EL (OPTION_MD_BASE + 1)
8773 struct option md_longopts
[] = {
8775 {"EB", no_argument
, NULL
, OPTION_EB
},
8778 {"EL", no_argument
, NULL
, OPTION_EL
},
8780 {NULL
, no_argument
, NULL
, 0}
8783 size_t md_longopts_size
= sizeof (md_longopts
);
8785 struct aarch64_option_table
8787 const char *option
; /* Option name to match. */
8788 const char *help
; /* Help information. */
8789 int *var
; /* Variable to change. */
8790 int value
; /* What to change it to. */
8791 char *deprecated
; /* If non-null, print this message. */
8794 static struct aarch64_option_table aarch64_opts
[] = {
8795 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8796 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8798 #ifdef DEBUG_AARCH64
8799 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8800 #endif /* DEBUG_AARCH64 */
8801 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8803 {"mno-verbose-error", N_("do not output verbose error messages"),
8804 &verbose_error_p
, 0, NULL
},
8805 {NULL
, NULL
, NULL
, 0, NULL
}
8808 struct aarch64_cpu_option_table
8811 const aarch64_feature_set value
;
8812 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8814 const char *canonical_name
;
8817 /* This list should, at a minimum, contain all the cpu names
8818 recognized by GCC. */
8819 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8820 {"all", AARCH64_ANY
, NULL
},
8821 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8822 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8823 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8824 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8825 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8826 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8827 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8828 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8829 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8830 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8831 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8832 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8833 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8834 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8836 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8837 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8839 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8840 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8842 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8843 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8844 | AARCH64_FEATURE_DOTPROD
8845 | AARCH64_FEATURE_SSBS
),
8847 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8848 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8849 | AARCH64_FEATURE_DOTPROD
8850 | AARCH64_FEATURE_SSBS
),
8852 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8853 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8854 | AARCH64_FEATURE_DOTPROD
8855 | AARCH64_FEATURE_SSBS
),
8857 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8858 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8859 | AARCH64_FEATURE_DOTPROD
8860 | AARCH64_FEATURE_SSBS
),
8862 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8863 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8864 | AARCH64_FEATURE_DOTPROD
8865 | AARCH64_FEATURE_PROFILE
),
8867 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8868 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8869 "Samsung Exynos M1"},
8870 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8871 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8872 | AARCH64_FEATURE_RDMA
),
8874 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8875 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8876 | AARCH64_FEATURE_DOTPROD
8877 | AARCH64_FEATURE_SSBS
),
8879 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8880 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8881 | AARCH64_FEATURE_DOTPROD
8882 | AARCH64_FEATURE_PROFILE
),
8884 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8885 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8886 | AARCH64_FEATURE_RDMA
),
8887 "Qualcomm QDF24XX"},
8888 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8889 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8890 "Qualcomm Saphira"},
8891 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8892 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8894 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8895 AARCH64_FEATURE_CRYPTO
),
8897 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8898 in earlier releases and is superseded by 'xgene1' in all
8900 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8901 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8902 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8903 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8904 {"generic", AARCH64_ARCH_V8
, NULL
},
8906 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8909 struct aarch64_arch_option_table
8912 const aarch64_feature_set value
;
8915 /* This list should, at a minimum, contain all the architecture names
8916 recognized by GCC. */
8917 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8918 {"all", AARCH64_ANY
},
8919 {"armv8-a", AARCH64_ARCH_V8
},
8920 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8921 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8922 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8923 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8924 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8925 {"armv8.6-a", AARCH64_ARCH_V8_6
},
8926 {NULL
, AARCH64_ARCH_NONE
}
8929 /* ISA extensions. */
8930 struct aarch64_option_cpu_value_table
8933 const aarch64_feature_set value
;
8934 const aarch64_feature_set require
; /* Feature dependencies. */
8937 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8938 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8940 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8941 | AARCH64_FEATURE_AES
8942 | AARCH64_FEATURE_SHA2
, 0),
8943 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8944 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8946 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8948 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8949 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8950 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8952 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8954 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8956 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8957 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8958 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8959 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8960 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8961 AARCH64_FEATURE (AARCH64_FEATURE_FP
8962 | AARCH64_FEATURE_F16
, 0)},
8963 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8965 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8966 AARCH64_FEATURE (AARCH64_FEATURE_F16
8967 | AARCH64_FEATURE_SIMD
8968 | AARCH64_FEATURE_COMPNUM
, 0)},
8969 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
8971 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8972 AARCH64_FEATURE (AARCH64_FEATURE_F16
8973 | AARCH64_FEATURE_SIMD
, 0)},
8974 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8976 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8978 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8980 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8982 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8984 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8986 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8988 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8989 | AARCH64_FEATURE_SHA3
, 0),
8991 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8993 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8995 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8997 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
8998 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
8999 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9000 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9001 | AARCH64_FEATURE_SM4
, 0)},
9002 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9003 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9004 | AARCH64_FEATURE_AES
, 0)},
9005 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9006 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9007 | AARCH64_FEATURE_SHA3
, 0)},
9008 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9009 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9010 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9012 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9015 struct aarch64_long_option_table
9017 const char *option
; /* Substring to match. */
9018 const char *help
; /* Help information. */
9019 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9020 char *deprecated
; /* If non-null, print this message. */
9023 /* Transitive closure of features depending on set. */
9024 static aarch64_feature_set
9025 aarch64_feature_disable_set (aarch64_feature_set set
)
9027 const struct aarch64_option_cpu_value_table
*opt
;
9028 aarch64_feature_set prev
= 0;
9030 while (prev
!= set
) {
9032 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9033 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9034 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9039 /* Transitive closure of dependencies of set. */
9040 static aarch64_feature_set
9041 aarch64_feature_enable_set (aarch64_feature_set set
)
9043 const struct aarch64_option_cpu_value_table
*opt
;
9044 aarch64_feature_set prev
= 0;
9046 while (prev
!= set
) {
9048 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9049 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9050 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9056 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9057 bfd_boolean ext_only
)
9059 /* We insist on extensions being added before being removed. We achieve
9060 this by using the ADDING_VALUE variable to indicate whether we are
9061 adding an extension (1) or removing it (0) and only allowing it to
9062 change in the order -1 -> 1 -> 0. */
9063 int adding_value
= -1;
9064 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9066 /* Copy the feature set, so that we can modify it. */
9070 while (str
!= NULL
&& *str
!= 0)
9072 const struct aarch64_option_cpu_value_table
*opt
;
9073 const char *ext
= NULL
;
9080 as_bad (_("invalid architectural extension"));
9084 ext
= strchr (++str
, '+');
9090 optlen
= strlen (str
);
9092 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9094 if (adding_value
!= 0)
9099 else if (optlen
> 0)
9101 if (adding_value
== -1)
9103 else if (adding_value
!= 1)
9105 as_bad (_("must specify extensions to add before specifying "
9106 "those to remove"));
9113 as_bad (_("missing architectural extension"));
9117 gas_assert (adding_value
!= -1);
9119 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9120 if (strncmp (opt
->name
, str
, optlen
) == 0)
9122 aarch64_feature_set set
;
9124 /* Add or remove the extension. */
9127 set
= aarch64_feature_enable_set (opt
->value
);
9128 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9132 set
= aarch64_feature_disable_set (opt
->value
);
9133 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9138 if (opt
->name
== NULL
)
9140 as_bad (_("unknown architectural extension `%s'"), str
);
9151 aarch64_parse_cpu (const char *str
)
9153 const struct aarch64_cpu_option_table
*opt
;
9154 const char *ext
= strchr (str
, '+');
9160 optlen
= strlen (str
);
9164 as_bad (_("missing cpu name `%s'"), str
);
9168 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9169 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9171 mcpu_cpu_opt
= &opt
->value
;
9173 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9178 as_bad (_("unknown cpu `%s'"), str
);
9183 aarch64_parse_arch (const char *str
)
9185 const struct aarch64_arch_option_table
*opt
;
9186 const char *ext
= strchr (str
, '+');
9192 optlen
= strlen (str
);
9196 as_bad (_("missing architecture name `%s'"), str
);
9200 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9201 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9203 march_cpu_opt
= &opt
->value
;
9205 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9210 as_bad (_("unknown architecture `%s'\n"), str
);
9215 struct aarch64_option_abi_value_table
9218 enum aarch64_abi_type value
;
9221 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9222 {"ilp32", AARCH64_ABI_ILP32
},
9223 {"lp64", AARCH64_ABI_LP64
},
9227 aarch64_parse_abi (const char *str
)
9233 as_bad (_("missing abi name `%s'"), str
);
9237 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9238 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9240 aarch64_abi
= aarch64_abis
[i
].value
;
9244 as_bad (_("unknown abi `%s'\n"), str
);
9248 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9250 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9251 aarch64_parse_abi
, NULL
},
9252 #endif /* OBJ_ELF */
9253 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9254 aarch64_parse_cpu
, NULL
},
9255 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9256 aarch64_parse_arch
, NULL
},
9257 {NULL
, NULL
, 0, NULL
}
9261 md_parse_option (int c
, const char *arg
)
9263 struct aarch64_option_table
*opt
;
9264 struct aarch64_long_option_table
*lopt
;
9270 target_big_endian
= 1;
9276 target_big_endian
= 0;
9281 /* Listing option. Just ignore these, we don't support additional
9286 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9288 if (c
== opt
->option
[0]
9289 && ((arg
== NULL
&& opt
->option
[1] == 0)
9290 || streq (arg
, opt
->option
+ 1)))
9292 /* If the option is deprecated, tell the user. */
9293 if (opt
->deprecated
!= NULL
)
9294 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9295 arg
? arg
: "", _(opt
->deprecated
));
9297 if (opt
->var
!= NULL
)
9298 *opt
->var
= opt
->value
;
9304 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9306 /* These options are expected to have an argument. */
9307 if (c
== lopt
->option
[0]
9309 && strncmp (arg
, lopt
->option
+ 1,
9310 strlen (lopt
->option
+ 1)) == 0)
9312 /* If the option is deprecated, tell the user. */
9313 if (lopt
->deprecated
!= NULL
)
9314 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9315 _(lopt
->deprecated
));
9317 /* Call the sup-option parser. */
9318 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9329 md_show_usage (FILE * fp
)
9331 struct aarch64_option_table
*opt
;
9332 struct aarch64_long_option_table
*lopt
;
9334 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9336 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9337 if (opt
->help
!= NULL
)
9338 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9340 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9341 if (lopt
->help
!= NULL
)
9342 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9346 -EB assemble code for a big-endian cpu\n"));
9351 -EL assemble code for a little-endian cpu\n"));
9355 /* Parse a .cpu directive. */
9358 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9360 const struct aarch64_cpu_option_table
*opt
;
9366 name
= input_line_pointer
;
9367 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9368 input_line_pointer
++;
9369 saved_char
= *input_line_pointer
;
9370 *input_line_pointer
= 0;
9372 ext
= strchr (name
, '+');
9375 optlen
= ext
- name
;
9377 optlen
= strlen (name
);
9379 /* Skip the first "all" entry. */
9380 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9381 if (strlen (opt
->name
) == optlen
9382 && strncmp (name
, opt
->name
, optlen
) == 0)
9384 mcpu_cpu_opt
= &opt
->value
;
9386 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9389 cpu_variant
= *mcpu_cpu_opt
;
9391 *input_line_pointer
= saved_char
;
9392 demand_empty_rest_of_line ();
9395 as_bad (_("unknown cpu `%s'"), name
);
9396 *input_line_pointer
= saved_char
;
9397 ignore_rest_of_line ();
9401 /* Parse a .arch directive. */
9404 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9406 const struct aarch64_arch_option_table
*opt
;
9412 name
= input_line_pointer
;
9413 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9414 input_line_pointer
++;
9415 saved_char
= *input_line_pointer
;
9416 *input_line_pointer
= 0;
9418 ext
= strchr (name
, '+');
9421 optlen
= ext
- name
;
9423 optlen
= strlen (name
);
9425 /* Skip the first "all" entry. */
9426 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9427 if (strlen (opt
->name
) == optlen
9428 && strncmp (name
, opt
->name
, optlen
) == 0)
9430 mcpu_cpu_opt
= &opt
->value
;
9432 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9435 cpu_variant
= *mcpu_cpu_opt
;
9437 *input_line_pointer
= saved_char
;
9438 demand_empty_rest_of_line ();
9442 as_bad (_("unknown architecture `%s'\n"), name
);
9443 *input_line_pointer
= saved_char
;
9444 ignore_rest_of_line ();
9447 /* Parse a .arch_extension directive. */
9450 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9453 char *ext
= input_line_pointer
;;
9455 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9456 input_line_pointer
++;
9457 saved_char
= *input_line_pointer
;
9458 *input_line_pointer
= 0;
9460 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9463 cpu_variant
= *mcpu_cpu_opt
;
9465 *input_line_pointer
= saved_char
;
9466 demand_empty_rest_of_line ();
9469 /* Copy symbol information. */
9472 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9474 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9478 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9479 This is needed so AArch64 specific st_other values can be independently
9480 specified for an IFUNC resolver (that is called by the dynamic linker)
9481 and the symbol it resolves (aliased to the resolver). In particular,
9482 if a function symbol has special st_other value set via directives,
9483 then attaching an IFUNC resolver to that symbol should not override
9484 the st_other setting. Requiring the directive on the IFUNC resolver
9485 symbol would be unexpected and problematic in C code, where the two
9486 symbols appear as two independent function declarations. */
9489 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9491 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9492 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9495 if (destelf
->size
== NULL
)
9496 destelf
->size
= XNEW (expressionS
);
9497 *destelf
->size
= *srcelf
->size
;
9501 if (destelf
->size
!= NULL
)
9502 free (destelf
->size
);
9503 destelf
->size
= NULL
;
9505 S_SET_SIZE (dest
, S_GET_SIZE (src
));