1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
165 data fields contain the following information:
168 A mask of register types that would have been acceptable as bare
169 operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
170 is set if a general parsing error occured for an operand (that is,
171 an error not related to registers, and having no error string).
174 A mask of register types that would have been acceptable inside
175 a register list. In addition, SEF_IN_REGLIST is set if the
176 operand contained a '{' and if we got to the point of trying
177 to parse a register inside a list.
180 The mask associated with the register that was actually seen, or 0
181 if none. A nonzero value describes a register inside a register
182 list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
185 The idea is that stringless errors from multiple opcode templates can
186 be ORed together to give a summary of the available alternatives. */
187 #define SEF_DEFAULT_ERROR (1U << 31)
188 #define SEF_IN_REGLIST (1U << 31)
190 /* Diagnostics inline function utilities.
192 These are lightweight utilities which should only be called by parse_operands
193 and other parsers. GAS processes each assembly line by parsing it against
194 instruction template(s), in the case of multiple templates (for the same
195 mnemonic name), those templates are tried one by one until one succeeds or
196 all fail. An assembly line may fail a few templates before being
197 successfully parsed; an error saved here in most cases is not a user error
198 but an error indicating the current template is not the right template.
199 Therefore it is very important that errors can be saved at a low cost during
200 the parsing; we don't want to slow down the whole parsing by recording
201 non-user errors in detail.
203 Remember that the objective is to help GAS pick up the most appropriate
204 error message in the case of multiple templates, e.g. FMOV which has 8
210 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
211 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
217 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
224 inst
.parsing_error
.index
= -1;
225 inst
.parsing_error
.kind
= kind
;
226 inst
.parsing_error
.error
= error
;
230 set_recoverable_error (const char *error
)
232 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
235 /* Use the DESC field of the corresponding aarch64_operand entry to compose
236 the error message. */
238 set_default_error (void)
240 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
241 inst
.parsing_error
.data
[0].i
= SEF_DEFAULT_ERROR
;
245 set_expected_error (unsigned int flags
)
247 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
248 inst
.parsing_error
.data
[0].i
= flags
;
252 set_syntax_error (const char *error
)
254 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
258 set_first_syntax_error (const char *error
)
261 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
265 set_fatal_syntax_error (const char *error
)
267 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
270 /* Return value for certain parsers when the parsing fails; those parsers
271 return the information of the parsed result, e.g. register number, on
273 #define PARSE_FAIL -1
275 /* This is an invalid condition code that means no conditional field is
277 #define COND_ALWAYS 0x10
281 const char *template;
288 bfd_reloc_code_real_type reloc
;
291 /* Macros to define the register types and masks for the purpose
294 #undef AARCH64_REG_TYPES
295 #define AARCH64_REG_TYPES \
296 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
297 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
298 BASIC_REG_TYPE(SP_32) /* wsp */ \
299 BASIC_REG_TYPE(SP_64) /* sp */ \
300 BASIC_REG_TYPE(ZR_32) /* wzr */ \
301 BASIC_REG_TYPE(ZR_64) /* xzr */ \
302 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
303 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
304 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
305 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
306 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
307 BASIC_REG_TYPE(V) /* v[0-31] */ \
308 BASIC_REG_TYPE(Z) /* z[0-31] */ \
309 BASIC_REG_TYPE(P) /* p[0-15] */ \
310 BASIC_REG_TYPE(PN) /* pn[0-15] */ \
311 BASIC_REG_TYPE(ZA) /* za */ \
312 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
313 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
314 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
315 BASIC_REG_TYPE(ZT0) /* zt0 */ \
316 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
317 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
318 /* Typecheck: same, plus SVE registers. */ \
319 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
321 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
322 MULTI_REG_TYPE(R_ZR, REG_TYPE(R_32) | REG_TYPE(R_64) \
323 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
324 /* Typecheck: same, plus SVE registers. */ \
325 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) \
328 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
329 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
330 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
331 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
332 MULTI_REG_TYPE(R_ZR_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
333 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
334 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
335 /* Typecheck: any [BHSDQ]P FP. */ \
336 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
337 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
338 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
339 MULTI_REG_TYPE(R_ZR_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
340 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
341 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
342 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
343 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
344 be used for SVE instructions, since Zn and Pn are valid symbols \
345 in other contexts. */ \
346 MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
347 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
348 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
349 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
350 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
351 | REG_TYPE(Z) | REG_TYPE(P)) \
352 /* Likewise, but with predicate-as-counter registers added. */ \
353 MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP_PN, REG_TYPE(R_32) | REG_TYPE(R_64) \
354 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
355 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
356 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
357 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
358 | REG_TYPE(Z) | REG_TYPE(P) | REG_TYPE(PN)) \
359 /* Any integer register; used for error messages only. */ \
360 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
361 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
362 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
363 /* Any vector register. */ \
364 MULTI_REG_TYPE(VZ, REG_TYPE(V) | REG_TYPE(Z)) \
365 /* An SVE vector or predicate register. */ \
366 MULTI_REG_TYPE(ZP, REG_TYPE(Z) | REG_TYPE(P)) \
367 /* Any vector or predicate register. */ \
368 MULTI_REG_TYPE(VZP, REG_TYPE(V) | REG_TYPE(Z) | REG_TYPE(P)) \
369 /* The whole of ZA or a single tile. */ \
370 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
371 /* A horizontal or vertical slice of a ZA tile. */ \
372 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
373 /* Pseudo type to mark the end of the enumerator sequence. */ \
376 #undef BASIC_REG_TYPE
377 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
378 #undef MULTI_REG_TYPE
379 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
381 #define END_REG_TYPE(T) BASIC_REG_TYPE(T)
383 /* Register type enumerators. */
384 typedef enum aarch64_reg_type_
386 /* A list of REG_TYPE_*. */
390 #undef BASIC_REG_TYPE
391 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
393 #define REG_TYPE(T) (1 << REG_TYPE_##T)
394 #undef MULTI_REG_TYPE
395 #define MULTI_REG_TYPE(T,V) V,
397 #define END_REG_TYPE(T) 0
399 /* Structure for a hash table entry for a register. */
403 unsigned char number
;
404 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
405 unsigned char builtin
;
408 /* Values indexed by aarch64_reg_type to assist the type checking. */
409 static const unsigned reg_type_masks
[] =
414 #undef BASIC_REG_TYPE
416 #undef MULTI_REG_TYPE
418 #undef AARCH64_REG_TYPES
420 /* We expected one of the registers in MASK to be specified. If a register
421 of some kind was specified, SEEN is a mask that contains that register,
422 otherwise it is zero.
424 If it is possible to provide a relatively pithy message that describes
425 the error exactly, return a string that does so, reporting the error
426 against "operand %d". Return null otherwise.
428 From a QoI perspective, any REG_TYPE_* that is passed as the first
429 argument to set_expected_reg_error should generally have its own message.
430 Providing messages for combinations of such REG_TYPE_*s can be useful if
431 it is possible to summarize the combination in a relatively natural way.
432 On the other hand, it seems better to avoid long lists of unrelated
436 get_reg_expected_msg (unsigned int mask
, unsigned int seen
)
438 /* First handle messages that use SEEN. */
439 if ((mask
& reg_type_masks
[REG_TYPE_ZAT
])
440 && (seen
& reg_type_masks
[REG_TYPE_ZATHV
]))
441 return N_("expected an unsuffixed ZA tile at operand %d");
443 if ((mask
& reg_type_masks
[REG_TYPE_ZATHV
])
444 && (seen
& reg_type_masks
[REG_TYPE_ZAT
]))
445 return N_("missing horizontal or vertical suffix at operand %d");
447 if ((mask
& reg_type_masks
[REG_TYPE_ZA
])
448 && (seen
& (reg_type_masks
[REG_TYPE_ZAT
]
449 | reg_type_masks
[REG_TYPE_ZATHV
])))
450 return N_("expected 'za' rather than a ZA tile at operand %d");
452 if ((mask
& reg_type_masks
[REG_TYPE_PN
])
453 && (seen
& reg_type_masks
[REG_TYPE_P
]))
454 return N_("expected a predicate-as-counter rather than predicate-as-mask"
455 " register at operand %d");
457 if ((mask
& reg_type_masks
[REG_TYPE_P
])
458 && (seen
& reg_type_masks
[REG_TYPE_PN
]))
459 return N_("expected a predicate-as-mask rather than predicate-as-counter"
460 " register at operand %d");
462 /* Integer, zero and stack registers. */
463 if (mask
== reg_type_masks
[REG_TYPE_R_64
])
464 return N_("expected a 64-bit integer register at operand %d");
465 if (mask
== reg_type_masks
[REG_TYPE_R_ZR
])
466 return N_("expected an integer or zero register at operand %d");
467 if (mask
== reg_type_masks
[REG_TYPE_R_SP
])
468 return N_("expected an integer or stack pointer register at operand %d");
470 /* Floating-point and SIMD registers. */
471 if (mask
== reg_type_masks
[REG_TYPE_BHSDQ
])
472 return N_("expected a scalar SIMD or floating-point register"
474 if (mask
== reg_type_masks
[REG_TYPE_V
])
475 return N_("expected an Advanced SIMD vector register at operand %d");
476 if (mask
== reg_type_masks
[REG_TYPE_Z
])
477 return N_("expected an SVE vector register at operand %d");
478 if (mask
== reg_type_masks
[REG_TYPE_P
]
479 || mask
== (reg_type_masks
[REG_TYPE_P
] | reg_type_masks
[REG_TYPE_PN
]))
480 /* Use this error for "predicate-as-mask only" and "either kind of
481 predicate". We report a more specific error if P is used where
482 PN is expected, and vice versa, so the issue at this point is
483 "predicate-like" vs. "not predicate-like". */
484 return N_("expected an SVE predicate register at operand %d");
485 if (mask
== reg_type_masks
[REG_TYPE_PN
])
486 return N_("expected an SVE predicate-as-counter register at operand %d");
487 if (mask
== reg_type_masks
[REG_TYPE_VZ
])
488 return N_("expected a vector register at operand %d");
489 if (mask
== reg_type_masks
[REG_TYPE_ZP
])
490 return N_("expected an SVE vector or predicate register at operand %d");
491 if (mask
== reg_type_masks
[REG_TYPE_VZP
])
492 return N_("expected a vector or predicate register at operand %d");
494 /* SME-related registers. */
495 if (mask
== reg_type_masks
[REG_TYPE_ZA
])
496 return N_("expected a ZA array vector at operand %d");
497 if (mask
== (reg_type_masks
[REG_TYPE_ZA_ZAT
] | reg_type_masks
[REG_TYPE_ZT0
]))
498 return N_("expected ZT0 or a ZA mask at operand %d");
499 if (mask
== reg_type_masks
[REG_TYPE_ZAT
])
500 return N_("expected a ZA tile at operand %d");
501 if (mask
== reg_type_masks
[REG_TYPE_ZATHV
])
502 return N_("expected a ZA tile slice at operand %d");
504 /* Integer and vector combos. */
505 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_V
]))
506 return N_("expected an integer register or Advanced SIMD vector register"
508 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_Z
]))
509 return N_("expected an integer register or SVE vector register"
511 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZ
]))
512 return N_("expected an integer or vector register at operand %d");
513 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_P
]))
514 return N_("expected an integer or predicate register at operand %d");
515 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZP
]))
516 return N_("expected an integer, vector or predicate register"
519 /* SVE and SME combos. */
520 if (mask
== (reg_type_masks
[REG_TYPE_Z
] | reg_type_masks
[REG_TYPE_ZATHV
]))
521 return N_("expected an SVE vector register or ZA tile slice"
527 /* Record that we expected a register of type TYPE but didn't see one.
528 REG is the register that we actually saw, or null if we didn't see a
529 recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
530 contents of a register list, otherwise it is zero. */
533 set_expected_reg_error (aarch64_reg_type type
, const reg_entry
*reg
,
536 assert (flags
== 0 || flags
== SEF_IN_REGLIST
);
537 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
538 if (flags
& SEF_IN_REGLIST
)
539 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
] | flags
;
541 inst
.parsing_error
.data
[0].i
= reg_type_masks
[type
];
543 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
546 /* Record that we expected a register list containing registers of type TYPE,
547 but didn't see the opening '{'. If we saw a register instead, REG is the
548 register that we saw, otherwise it is null. */
551 set_expected_reglist_error (aarch64_reg_type type
, const reg_entry
*reg
)
553 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
554 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
];
556 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
559 /* Some well known registers that we refer to directly elsewhere. */
563 /* Instructions take 4 bytes in the object file. */
566 static htab_t aarch64_ops_hsh
;
567 static htab_t aarch64_cond_hsh
;
568 static htab_t aarch64_shift_hsh
;
569 static htab_t aarch64_sys_regs_hsh
;
570 static htab_t aarch64_pstatefield_hsh
;
571 static htab_t aarch64_sys_regs_ic_hsh
;
572 static htab_t aarch64_sys_regs_dc_hsh
;
573 static htab_t aarch64_sys_regs_at_hsh
;
574 static htab_t aarch64_sys_regs_tlbi_hsh
;
575 static htab_t aarch64_sys_regs_sr_hsh
;
576 static htab_t aarch64_reg_hsh
;
577 static htab_t aarch64_barrier_opt_hsh
;
578 static htab_t aarch64_nzcv_hsh
;
579 static htab_t aarch64_pldop_hsh
;
580 static htab_t aarch64_hint_opt_hsh
;
582 /* Stuff needed to resolve the label ambiguity
591 static symbolS
*last_label_seen
;
593 /* Literal pool structure. Held on a per-section
594 and per-sub-section basis. */
596 #define MAX_LITERAL_POOL_SIZE 1024
597 typedef struct literal_expression
600 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
601 LITTLENUM_TYPE
* bignum
;
602 } literal_expression
;
604 typedef struct literal_pool
606 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
607 unsigned int next_free_entry
;
613 struct literal_pool
*next
;
616 /* Pointer to a linked list of literal pools. */
617 static literal_pool
*list_of_pools
= NULL
;
621 /* This array holds the chars that always start a comment. If the
622 pre-processor is disabled, these aren't very useful. */
623 const char comment_chars
[] = "";
625 /* This array holds the chars that only start a comment at the beginning of
626 a line. If the line seems to have the form '# 123 filename'
627 .line and .file directives will appear in the pre-processed output. */
628 /* Note that input_file.c hand checks for '#' at the beginning of the
629 first line of the input file. This is because the compiler outputs
630 #NO_APP at the beginning of its output. */
631 /* Also note that comments like this one will always work. */
632 const char line_comment_chars
[] = "#";
634 const char line_separator_chars
[] = ";";
636 /* Chars that can be used to separate mant
637 from exp in floating point numbers. */
638 const char EXP_CHARS
[] = "eE";
640 /* Chars that mean this number is a floating point constant. */
644 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
646 /* Prefix character that indicates the start of an immediate value. */
647 #define is_immediate_prefix(C) ((C) == '#')
649 /* Separator character handling. */
651 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
654 skip_past_char (char **str
, char c
)
665 #define skip_past_comma(str) skip_past_char (str, ',')
667 /* Arithmetic expressions (possibly involving symbols). */
669 static bool in_aarch64_get_expression
= false;
671 /* Third argument to aarch64_get_expression. */
672 #define GE_NO_PREFIX false
673 #define GE_OPT_PREFIX true
675 /* Fourth argument to aarch64_get_expression. */
676 #define ALLOW_ABSENT false
677 #define REJECT_ABSENT true
679 /* Return TRUE if the string pointed by *STR is successfully parsed
680 as an valid expression; *EP will be filled with the information of
681 such an expression. Otherwise return FALSE.
683 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
684 If REJECT_ABSENT is true then trat missing expressions as an error. */
687 aarch64_get_expression (expressionS
* ep
,
689 bool allow_immediate_prefix
,
694 bool prefix_present
= false;
696 if (allow_immediate_prefix
)
698 if (is_immediate_prefix (**str
))
701 prefix_present
= true;
705 memset (ep
, 0, sizeof (expressionS
));
707 save_in
= input_line_pointer
;
708 input_line_pointer
= *str
;
709 in_aarch64_get_expression
= true;
710 seg
= expression (ep
);
711 in_aarch64_get_expression
= false;
713 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
715 /* We found a bad expression in md_operand(). */
716 *str
= input_line_pointer
;
717 input_line_pointer
= save_in
;
718 if (prefix_present
&& ! error_p ())
719 set_fatal_syntax_error (_("bad expression"));
721 set_first_syntax_error (_("bad expression"));
726 if (seg
!= absolute_section
727 && seg
!= text_section
728 && seg
!= data_section
729 && seg
!= bss_section
730 && seg
!= undefined_section
)
732 set_syntax_error (_("bad segment"));
733 *str
= input_line_pointer
;
734 input_line_pointer
= save_in
;
741 *str
= input_line_pointer
;
742 input_line_pointer
= save_in
;
746 /* Turn a string in input_line_pointer into a floating point constant
747 of type TYPE, and store the appropriate bytes in *LITP. The number
748 of LITTLENUMS emitted is stored in *SIZEP. An error message is
749 returned, or NULL on OK. */
752 md_atof (int type
, char *litP
, int *sizeP
)
754 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
757 /* We handle all bad expressions here, so that we can report the faulty
758 instruction in the error message. */
760 md_operand (expressionS
* exp
)
762 if (in_aarch64_get_expression
)
763 exp
->X_op
= O_illegal
;
766 /* Immediate values. */
768 /* Errors may be set multiple times during parsing or bit encoding
769 (particularly in the Neon bits), but usually the earliest error which is set
770 will be the most meaningful. Avoid overwriting it with later (cascading)
771 errors by calling this function. */
774 first_error (const char *error
)
777 set_syntax_error (error
);
780 /* Similar to first_error, but this function accepts formatted error
783 first_error_fmt (const char *format
, ...)
788 /* N.B. this single buffer will not cause error messages for different
789 instructions to pollute each other; this is because at the end of
790 processing of each assembly line, error message if any will be
791 collected by as_bad. */
792 static char buffer
[size
];
796 int ret ATTRIBUTE_UNUSED
;
797 va_start (args
, format
);
798 ret
= vsnprintf (buffer
, size
, format
, args
);
799 know (ret
<= size
- 1 && ret
>= 0);
801 set_syntax_error (buffer
);
805 /* Internal helper routine converting a vector_type_el structure *VECTYPE
806 to a corresponding operand qualifier. */
808 static inline aarch64_opnd_qualifier_t
809 vectype_to_qualifier (const struct vector_type_el
*vectype
)
811 /* Element size in bytes indexed by vector_el_type. */
812 const unsigned char ele_size
[5]
814 const unsigned int ele_base
[5] =
816 AARCH64_OPND_QLF_V_4B
,
817 AARCH64_OPND_QLF_V_2H
,
818 AARCH64_OPND_QLF_V_2S
,
819 AARCH64_OPND_QLF_V_1D
,
820 AARCH64_OPND_QLF_V_1Q
823 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
824 goto vectype_conversion_fail
;
826 if (vectype
->type
== NT_zero
)
827 return AARCH64_OPND_QLF_P_Z
;
828 if (vectype
->type
== NT_merge
)
829 return AARCH64_OPND_QLF_P_M
;
831 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
833 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
835 /* Special case S_4B. */
836 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
837 return AARCH64_OPND_QLF_S_4B
;
839 /* Special case S_2H. */
840 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
841 return AARCH64_OPND_QLF_S_2H
;
843 /* Vector element register. */
844 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
848 /* Vector register. */
849 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
852 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
853 goto vectype_conversion_fail
;
855 /* The conversion is by calculating the offset from the base operand
856 qualifier for the vector type. The operand qualifiers are regular
857 enough that the offset can established by shifting the vector width by
858 a vector-type dependent amount. */
860 if (vectype
->type
== NT_b
)
862 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
864 else if (vectype
->type
>= NT_d
)
869 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
870 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
871 && offset
<= AARCH64_OPND_QLF_V_1Q
);
875 vectype_conversion_fail
:
876 first_error (_("bad vector arrangement type"));
877 return AARCH64_OPND_QLF_NIL
;
880 /* Register parsing. */
882 /* Generic register parser which is called by other specialized
884 CCP points to what should be the beginning of a register name.
885 If it is indeed a valid register name, advance CCP over it and
886 return the reg_entry structure; otherwise return NULL.
887 It does not issue diagnostics. */
890 parse_reg (char **ccp
)
896 #ifdef REGISTER_PREFIX
897 if (*start
!= REGISTER_PREFIX
)
903 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
908 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
910 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
919 /* Return the operand qualifier associated with all uses of REG, or
920 AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
921 that qualifiers don't apply to REG or that qualifiers are added
924 static aarch64_opnd_qualifier_t
925 inherent_reg_qualifier (const reg_entry
*reg
)
932 return AARCH64_OPND_QLF_W
;
937 return AARCH64_OPND_QLF_X
;
944 return AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
947 return AARCH64_OPND_QLF_NIL
;
951 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
954 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
956 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
959 /* Try to parse a base or offset register. Allow SVE base and offset
960 registers if REG_TYPE includes SVE registers. Return the register
961 entry on success, setting *QUALIFIER to the register qualifier.
962 Return null otherwise.
964 Note that this function does not issue any diagnostics. */
966 static const reg_entry
*
967 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
968 aarch64_opnd_qualifier_t
*qualifier
)
971 const reg_entry
*reg
= parse_reg (&str
);
979 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_Z
)) == 0
982 switch (TOLOWER (str
[1]))
985 *qualifier
= AARCH64_OPND_QLF_S_S
;
988 *qualifier
= AARCH64_OPND_QLF_S_D
;
997 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR_SP
))
999 *qualifier
= inherent_reg_qualifier (reg
);
1008 /* Try to parse a base or offset register. Return the register entry
1009 on success, setting *QUALIFIER to the register qualifier. Return null
1012 Note that this function does not issue any diagnostics. */
1014 static const reg_entry
*
1015 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
1017 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_ZR_SP
, qualifier
);
1020 /* Parse the qualifier of a vector register or vector element of type
1021 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
1022 succeeds; otherwise return FALSE.
1024 Accept only one occurrence of:
1025 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
1028 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
1029 struct vector_type_el
*parsed_type
, char **str
)
1033 unsigned element_size
;
1034 enum vector_el_type type
;
1037 gas_assert (*ptr
== '.');
1040 if (reg_type
!= REG_TYPE_V
|| !ISDIGIT (*ptr
))
1045 width
= strtoul (ptr
, &ptr
, 10);
1046 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
1048 first_error_fmt (_("bad size %d in vector width specifier"), width
);
1053 switch (TOLOWER (*ptr
))
1072 if (reg_type
!= REG_TYPE_V
|| width
== 1)
1081 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
1083 first_error (_("missing element size"));
1086 if (width
!= 0 && width
* element_size
!= 64
1087 && width
* element_size
!= 128
1088 && !(width
== 2 && element_size
== 16)
1089 && !(width
== 4 && element_size
== 8))
1092 ("invalid element size %d and vector size combination %c"),
1098 parsed_type
->type
= type
;
1099 parsed_type
->width
= width
;
1100 parsed_type
->element_size
= element_size
;
1107 /* *STR contains an SVE zero/merge predication suffix. Parse it into
1108 *PARSED_TYPE and point *STR at the end of the suffix. */
1111 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
1116 gas_assert (*ptr
== '/');
1118 switch (TOLOWER (*ptr
))
1121 parsed_type
->type
= NT_zero
;
1124 parsed_type
->type
= NT_merge
;
1127 if (*ptr
!= '\0' && *ptr
!= ',')
1128 first_error_fmt (_("unexpected character `%c' in predication type"),
1131 first_error (_("missing predication type"));
1134 parsed_type
->width
= 0;
1139 /* Return true if CH is a valid suffix character for registers of
1143 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1157 return ch
== '.' || ch
== '/';
1164 /* Parse an index expression at *STR, storing it in *IMM on success. */
1167 parse_index_expression (char **str
, int64_t *imm
)
1171 aarch64_get_expression (&exp
, str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1172 if (exp
.X_op
!= O_constant
)
1174 first_error (_("constant expression required"));
1177 *imm
= exp
.X_add_number
;
1181 /* Parse a register of the type TYPE.
1183 Return null if the string pointed to by *CCP is not a valid register
1184 name or the parsed register is not of TYPE.
1186 Otherwise return the register, and optionally return the register
1187 shape and element index information in *TYPEINFO.
1189 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1191 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1194 FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
1195 an operand that we can be confident that it is a good match. */
1197 #define PTR_IN_REGLIST (1U << 0)
1198 #define PTR_FULL_REG (1U << 1)
1199 #define PTR_GOOD_MATCH (1U << 2)
1201 static const reg_entry
*
1202 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1203 struct vector_type_el
*typeinfo
, unsigned int flags
)
1206 bool isalpha
= ISALPHA (*str
);
1207 const reg_entry
*reg
= parse_reg (&str
);
1208 struct vector_type_el atype
;
1209 struct vector_type_el parsetype
;
1210 bool is_typed_vecreg
= false;
1211 unsigned int err_flags
= (flags
& PTR_IN_REGLIST
) ? SEF_IN_REGLIST
: 0;
1214 atype
.type
= NT_invtype
;
1216 atype
.element_size
= 0;
1223 if (!isalpha
&& (flags
& PTR_IN_REGLIST
))
1224 set_fatal_syntax_error (_("syntax error in register list"));
1225 else if (flags
& PTR_GOOD_MATCH
)
1226 set_fatal_syntax_error (NULL
);
1228 set_expected_reg_error (type
, reg
, err_flags
);
1232 if (! aarch64_check_reg_type (reg
, type
))
1234 DEBUG_TRACE ("reg type check failed");
1235 if (flags
& PTR_GOOD_MATCH
)
1236 set_fatal_syntax_error (NULL
);
1238 set_expected_reg_error (type
, reg
, err_flags
);
1243 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1247 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1249 if ((reg
->type
== REG_TYPE_ZAT
1250 || reg
->type
== REG_TYPE_ZATH
1251 || reg
->type
== REG_TYPE_ZATV
)
1252 && reg
->number
* 8 >= parsetype
.element_size
)
1254 set_syntax_error (_("ZA tile number out of range"));
1260 if (!parse_predication_for_operand (&parsetype
, &str
))
1264 /* Register if of the form Vn.[bhsdq]. */
1265 is_typed_vecreg
= true;
1267 if (type
!= REG_TYPE_V
)
1269 /* The width is always variable; we don't allow an integer width
1271 gas_assert (parsetype
.width
== 0);
1272 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1274 else if (parsetype
.width
== 0)
1275 /* Expect index. In the new scheme we cannot have
1276 Vn.[bhsdq] represent a scalar. Therefore any
1277 Vn.[bhsdq] should have an index following it.
1278 Except in reglists of course. */
1279 atype
.defined
|= NTA_HASINDEX
;
1281 atype
.defined
|= NTA_HASTYPE
;
1283 atype
.type
= parsetype
.type
;
1284 atype
.width
= parsetype
.width
;
1287 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1289 /* Reject Sn[index] syntax. */
1290 if (reg
->type
!= REG_TYPE_Z
1291 && reg
->type
!= REG_TYPE_PN
1292 && reg
->type
!= REG_TYPE_ZT0
1293 && !is_typed_vecreg
)
1295 first_error (_("this type of register can't be indexed"));
1299 if (flags
& PTR_IN_REGLIST
)
1301 first_error (_("index not allowed inside register list"));
1305 atype
.defined
|= NTA_HASINDEX
;
1307 if (!parse_index_expression (&str
, &atype
.index
))
1310 if (! skip_past_char (&str
, ']'))
1313 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1315 /* Indexed vector register expected. */
1316 first_error (_("indexed vector register expected"));
1320 /* A vector reg Vn should be typed or indexed. */
1321 if (type
== REG_TYPE_V
&& atype
.defined
== 0)
1323 first_error (_("invalid use of vector register"));
1336 Return the register on success; return null otherwise.
1338 If this is a NEON vector register with additional type information, fill
1339 in the struct pointed to by VECTYPE (if non-NULL).
1341 This parser does not handle register lists. */
1343 static const reg_entry
*
1344 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1345 struct vector_type_el
*vectype
)
1347 return parse_typed_reg (ccp
, type
, vectype
, 0);
1351 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1353 return (e1
.type
== e2
.type
1354 && e1
.defined
== e2
.defined
1355 && e1
.width
== e2
.width
1356 && e1
.element_size
== e2
.element_size
1357 && e1
.index
== e2
.index
);
1360 /* Return the register number mask for registers of type REG_TYPE. */
1363 reg_type_mask (aarch64_reg_type reg_type
)
1365 return reg_type
== REG_TYPE_P
? 15 : 31;
1368 /* This function parses a list of vector registers of type TYPE.
1369 On success, it returns the parsed register list information in the
1370 following encoded format:
1372 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1373 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1375 The information of the register shape and/or index is returned in
1378 It returns PARSE_FAIL if the register list is invalid.
1380 The list contains one to four registers.
1381 Each register can be one of:
1384 All <T> should be identical.
1385 All <index> should be identical.
1386 There are restrictions on <Vt> numbers which are checked later
1387 (by reg_list_valid_p). */
1390 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1391 struct vector_type_el
*vectype
)
1395 struct vector_type_el typeinfo
, typeinfo_first
;
1396 int val
, val_range
, mask
;
1400 bool expect_index
= false;
1401 unsigned int ptr_flags
= PTR_IN_REGLIST
;
1405 set_expected_reglist_error (type
, parse_reg (&str
));
1411 typeinfo_first
.defined
= 0;
1412 typeinfo_first
.type
= NT_invtype
;
1413 typeinfo_first
.width
= -1;
1414 typeinfo_first
.element_size
= 0;
1415 typeinfo_first
.index
= 0;
1420 mask
= reg_type_mask (type
);
1425 str
++; /* skip over '-' */
1428 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1432 set_first_syntax_error (_("invalid vector register in list"));
1437 /* reject [bhsd]n */
1438 if (type
== REG_TYPE_V
&& typeinfo
.defined
== 0)
1440 set_first_syntax_error (_("invalid scalar register in list"));
1445 if (typeinfo
.defined
& NTA_HASINDEX
)
1446 expect_index
= true;
1450 if (val
== val_range
)
1452 set_first_syntax_error
1453 (_("invalid range in vector register list"));
1456 val_range
= (val_range
+ 1) & mask
;
1462 typeinfo_first
= typeinfo
;
1463 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1465 set_first_syntax_error
1466 (_("type mismatch in vector register list"));
1473 ret_val
|= val_range
<< (5 * nb_regs
);
1475 if (val_range
== val
)
1477 val_range
= (val_range
+ 1) & mask
;
1480 ptr_flags
|= PTR_GOOD_MATCH
;
1482 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1484 skip_whitespace (str
);
1487 set_first_syntax_error (_("end of vector register list not found"));
1492 skip_whitespace (str
);
1496 if (skip_past_char (&str
, '['))
1498 if (!parse_index_expression (&str
, &typeinfo_first
.index
))
1500 if (! skip_past_char (&str
, ']'))
1505 set_first_syntax_error (_("expected index"));
1512 set_first_syntax_error (_("too many registers in vector register list"));
1515 else if (nb_regs
== 0)
1517 set_first_syntax_error (_("empty vector register list"));
1523 *vectype
= typeinfo_first
;
1525 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1528 /* Directives: register aliases. */
1531 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1536 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1539 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1542 /* Only warn about a redefinition if it's not defined as the
1544 else if (new->number
!= number
|| new->type
!= type
)
1545 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1550 name
= xstrdup (str
);
1551 new = XNEW (reg_entry
);
1554 new->number
= number
;
1556 new->builtin
= false;
1558 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1563 /* Look for the .req directive. This is of the form:
1565 new_register_name .req existing_register_name
1567 If we find one, or if it looks sufficiently like one that we want to
1568 handle any error here, return TRUE. Otherwise return FALSE. */
1571 create_register_alias (char *newname
, char *p
)
1573 const reg_entry
*old
;
1574 char *oldname
, *nbuf
;
1577 /* The input scrubber ensures that whitespace after the mnemonic is
1578 collapsed to single spaces. */
1580 if (!startswith (oldname
, " .req "))
1584 if (*oldname
== '\0')
1587 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1590 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1594 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1595 the desired alias name, and p points to its end. If not, then
1596 the desired alias name is in the global original_case_string. */
1597 #ifdef TC_CASE_SENSITIVE
1600 newname
= original_case_string
;
1601 nlen
= strlen (newname
);
1604 nbuf
= xmemdup0 (newname
, nlen
);
1606 /* Create aliases under the new name as stated; an all-lowercase
1607 version of the new name; and an all-uppercase version of the new
1609 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1611 for (p
= nbuf
; *p
; p
++)
1614 if (strncmp (nbuf
, newname
, nlen
))
1616 /* If this attempt to create an additional alias fails, do not bother
1617 trying to create the all-lower case alias. We will fail and issue
1618 a second, duplicate error message. This situation arises when the
1619 programmer does something like:
1622 The second .req creates the "Foo" alias but then fails to create
1623 the artificial FOO alias because it has already been created by the
1625 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1632 for (p
= nbuf
; *p
; p
++)
1635 if (strncmp (nbuf
, newname
, nlen
))
1636 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1643 /* Should never be called, as .req goes between the alias and the
1644 register name, not at the beginning of the line. */
1646 s_req (int a ATTRIBUTE_UNUSED
)
1648 as_bad (_("invalid syntax for .req directive"));
1651 /* The .unreq directive deletes an alias which was previously defined
1652 by .req. For example:
1658 s_unreq (int a ATTRIBUTE_UNUSED
)
1663 name
= input_line_pointer
;
1664 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1665 saved_char
= *input_line_pointer
;
1666 *input_line_pointer
= 0;
1669 as_bad (_("invalid syntax for .unreq directive"));
1672 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1675 as_bad (_("unknown register alias '%s'"), name
);
1676 else if (reg
->builtin
)
1677 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1684 str_hash_delete (aarch64_reg_hsh
, name
);
1685 free ((char *) reg
->name
);
1688 /* Also locate the all upper case and all lower case versions.
1689 Do not complain if we cannot find one or the other as it
1690 was probably deleted above. */
1692 nbuf
= strdup (name
);
1693 for (p
= nbuf
; *p
; p
++)
1695 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1698 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1699 free ((char *) reg
->name
);
1703 for (p
= nbuf
; *p
; p
++)
1705 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1708 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1709 free ((char *) reg
->name
);
1717 *input_line_pointer
= saved_char
;
1718 demand_empty_rest_of_line ();
1721 /* Directives: Instruction set selection. */
1723 #if defined OBJ_ELF || defined OBJ_COFF
1724 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1725 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1726 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1727 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1729 /* Create a new mapping symbol for the transition to STATE. */
1732 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1735 const char *symname
;
1742 type
= BSF_NO_FLAGS
;
1746 type
= BSF_NO_FLAGS
;
1752 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1753 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1755 /* Save the mapping symbols for future reference. Also check that
1756 we do not place two mapping symbols at the same offset within a
1757 frag. We'll handle overlap between frags in
1758 check_mapping_symbols.
1760 If .fill or other data filling directive generates zero sized data,
1761 the mapping symbol for the following code will have the same value
1762 as the one generated for the data filling directive. In this case,
1763 we replace the old symbol with the new one at the same address. */
1766 if (frag
->tc_frag_data
.first_map
!= NULL
)
1768 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1769 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1772 frag
->tc_frag_data
.first_map
= symbolP
;
1774 if (frag
->tc_frag_data
.last_map
!= NULL
)
1776 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1777 S_GET_VALUE (symbolP
));
1778 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1779 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1782 frag
->tc_frag_data
.last_map
= symbolP
;
1785 /* We must sometimes convert a region marked as code to data during
1786 code alignment, if an odd number of bytes have to be padded. The
1787 code mapping symbol is pushed to an aligned address. */
1790 insert_data_mapping_symbol (enum mstate state
,
1791 valueT value
, fragS
* frag
, offsetT bytes
)
1793 /* If there was already a mapping symbol, remove it. */
1794 if (frag
->tc_frag_data
.last_map
!= NULL
1795 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1796 frag
->fr_address
+ value
)
1798 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1802 know (frag
->tc_frag_data
.first_map
== symp
);
1803 frag
->tc_frag_data
.first_map
= NULL
;
1805 frag
->tc_frag_data
.last_map
= NULL
;
1806 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1809 make_mapping_symbol (MAP_DATA
, value
, frag
);
1810 make_mapping_symbol (state
, value
+ bytes
, frag
);
1813 static void mapping_state_2 (enum mstate state
, int max_chars
);
1815 /* Set the mapping state to STATE. Only call this when about to
1816 emit some STATE bytes to the file. */
1819 mapping_state (enum mstate state
)
1821 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1823 if (state
== MAP_INSN
)
1824 /* AArch64 instructions require 4-byte alignment. When emitting
1825 instructions into any section, record the appropriate section
1827 record_alignment (now_seg
, 2);
1829 if (mapstate
== state
)
1830 /* The mapping symbol has already been emitted.
1831 There is nothing else to do. */
1834 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1835 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1836 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1837 evaluated later in the next else. */
1839 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1841 /* Only add the symbol if the offset is > 0:
1842 if we're at the first frag, check it's size > 0;
1843 if we're not at the first frag, then for sure
1844 the offset is > 0. */
1845 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1846 const int add_symbol
= (frag_now
!= frag_first
)
1847 || (frag_now_fix () > 0);
1850 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1854 mapping_state_2 (state
, 0);
1857 /* Same as mapping_state, but MAX_CHARS bytes have already been
1858 allocated. Put the mapping symbol that far back. */
1861 mapping_state_2 (enum mstate state
, int max_chars
)
1863 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1865 if (!SEG_NORMAL (now_seg
))
1868 if (mapstate
== state
)
1869 /* The mapping symbol has already been emitted.
1870 There is nothing else to do. */
1873 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1874 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1877 #define mapping_state(x) /* nothing */
1878 #define mapping_state_2(x, y) /* nothing */
1881 /* Directives: sectioning and alignment. */
1884 s_bss (int ignore ATTRIBUTE_UNUSED
)
1886 /* We don't support putting frags in the BSS segment, we fake it by
1887 marking in_bss, then looking at s_skip for clues. */
1888 subseg_set (bss_section
, 0);
1889 demand_empty_rest_of_line ();
1890 mapping_state (MAP_DATA
);
1894 s_even (int ignore ATTRIBUTE_UNUSED
)
1896 /* Never make frag if expect extra pass. */
1898 frag_align (1, 0, 0);
1900 record_alignment (now_seg
, 1);
1902 demand_empty_rest_of_line ();
1905 /* Directives: Literal pools. */
1907 static literal_pool
*
1908 find_literal_pool (int size
)
1912 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1914 if (pool
->section
== now_seg
1915 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1922 static literal_pool
*
1923 find_or_make_literal_pool (int size
)
1925 /* Next literal pool ID number. */
1926 static unsigned int latest_pool_num
= 1;
1929 pool
= find_literal_pool (size
);
1933 /* Create a new pool. */
1934 pool
= XNEW (literal_pool
);
1938 /* Currently we always put the literal pool in the current text
1939 section. If we were generating "small" model code where we
1940 knew that all code and initialised data was within 1MB then
1941 we could output literals to mergeable, read-only data
1944 pool
->next_free_entry
= 0;
1945 pool
->section
= now_seg
;
1946 pool
->sub_section
= now_subseg
;
1948 pool
->next
= list_of_pools
;
1949 pool
->symbol
= NULL
;
1951 /* Add it to the list. */
1952 list_of_pools
= pool
;
1955 /* New pools, and emptied pools, will have a NULL symbol. */
1956 if (pool
->symbol
== NULL
)
1958 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1959 &zero_address_frag
, 0);
1960 pool
->id
= latest_pool_num
++;
1967 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1968 Return TRUE on success, otherwise return FALSE. */
1970 add_to_lit_pool (expressionS
*exp
, int size
)
1975 pool
= find_or_make_literal_pool (size
);
1977 /* Check if this literal value is already in the pool. */
1978 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1980 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1982 if ((litexp
->X_op
== exp
->X_op
)
1983 && (exp
->X_op
== O_constant
)
1984 && (litexp
->X_add_number
== exp
->X_add_number
)
1985 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1988 if ((litexp
->X_op
== exp
->X_op
)
1989 && (exp
->X_op
== O_symbol
)
1990 && (litexp
->X_add_number
== exp
->X_add_number
)
1991 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1992 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1996 /* Do we need to create a new entry? */
1997 if (entry
== pool
->next_free_entry
)
1999 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2001 set_syntax_error (_("literal pool overflow"));
2005 pool
->literals
[entry
].exp
= *exp
;
2006 pool
->next_free_entry
+= 1;
2007 if (exp
->X_op
== O_big
)
2009 /* PR 16688: Bignums are held in a single global array. We must
2010 copy and preserve that value now, before it is overwritten. */
2011 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
2013 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
2014 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2017 pool
->literals
[entry
].bignum
= NULL
;
2020 exp
->X_op
= O_symbol
;
2021 exp
->X_add_number
= ((int) entry
) * size
;
2022 exp
->X_add_symbol
= pool
->symbol
;
2027 /* Can't use symbol_new here, so have to create a symbol and then at
2028 a later date assign it a value. That's what these functions do. */
2031 symbol_locate (symbolS
* symbolP
,
2032 const char *name
,/* It is copied, the caller can modify. */
2033 segT segment
, /* Segment identifier (SEG_<something>). */
2034 valueT valu
, /* Symbol value. */
2035 fragS
* frag
) /* Associated fragment. */
2038 char *preserved_copy_of_name
;
2040 name_length
= strlen (name
) + 1; /* +1 for \0. */
2041 obstack_grow (¬es
, name
, name_length
);
2042 preserved_copy_of_name
= obstack_finish (¬es
);
2044 #ifdef tc_canonicalize_symbol_name
2045 preserved_copy_of_name
=
2046 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2049 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2051 S_SET_SEGMENT (symbolP
, segment
);
2052 S_SET_VALUE (symbolP
, valu
);
2053 symbol_clear_list_pointers (symbolP
);
2055 symbol_set_frag (symbolP
, frag
);
2057 /* Link to end of symbol chain. */
2059 extern int symbol_table_frozen
;
2061 if (symbol_table_frozen
)
2065 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
2067 obj_symbol_new_hook (symbolP
);
2069 #ifdef tc_symbol_new_hook
2070 tc_symbol_new_hook (symbolP
);
2074 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2075 #endif /* DEBUG_SYMS */
2080 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2087 for (align
= 2; align
<= 4; align
++)
2089 int size
= 1 << align
;
2091 pool
= find_literal_pool (size
);
2092 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
2095 /* Align pool as you have word accesses.
2096 Only make a frag if we have to. */
2098 frag_align (align
, 0, 0);
2100 mapping_state (MAP_DATA
);
2102 record_alignment (now_seg
, align
);
2104 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2106 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2107 (valueT
) frag_now_fix (), frag_now
);
2108 symbol_table_insert (pool
->symbol
);
2110 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2112 expressionS
* exp
= & pool
->literals
[entry
].exp
;
2114 if (exp
->X_op
== O_big
)
2116 /* PR 16688: Restore the global bignum value. */
2117 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
2118 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
2119 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2122 /* First output the expression in the instruction to the pool. */
2123 emit_expr (exp
, size
); /* .word|.xword */
2125 if (exp
->X_op
== O_big
)
2127 free (pool
->literals
[entry
].bignum
);
2128 pool
->literals
[entry
].bignum
= NULL
;
2132 /* Mark the pool as empty. */
2133 pool
->next_free_entry
= 0;
2134 pool
->symbol
= NULL
;
2138 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2139 /* Forward declarations for functions below, in the MD interface
2141 static struct reloc_table_entry
* find_reloc_table_entry (char **);
2143 /* Directives: Data. */
2144 /* N.B. the support for relocation suffix in this directive needs to be
2145 implemented properly. */
2148 s_aarch64_cons (int nbytes
)
2152 #ifdef md_flush_pending_output
2153 md_flush_pending_output ();
2156 if (is_it_end_of_statement ())
2158 demand_empty_rest_of_line ();
2162 #ifdef md_cons_align
2163 md_cons_align (nbytes
);
2166 mapping_state (MAP_DATA
);
2169 struct reloc_table_entry
*reloc
;
2173 if (exp
.X_op
!= O_symbol
)
2174 emit_expr (&exp
, (unsigned int) nbytes
);
2177 skip_past_char (&input_line_pointer
, '#');
2178 if (skip_past_char (&input_line_pointer
, ':'))
2180 reloc
= find_reloc_table_entry (&input_line_pointer
);
2182 as_bad (_("unrecognized relocation suffix"));
2184 as_bad (_("unimplemented relocation suffix"));
2185 ignore_rest_of_line ();
2189 emit_expr (&exp
, (unsigned int) nbytes
);
2192 while (*input_line_pointer
++ == ',');
2194 /* Put terminator back into stream. */
2195 input_line_pointer
--;
2196 demand_empty_rest_of_line ();
2201 /* Forward declarations for functions below, in the MD interface
2203 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2205 /* Mark symbol that it follows a variant PCS convention. */
2208 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2214 elf_symbol_type
*elfsym
;
2216 c
= get_symbol_name (&name
);
2218 as_bad (_("Missing symbol name in directive"));
2219 sym
= symbol_find_or_make (name
);
2220 restore_line_pointer (c
);
2221 demand_empty_rest_of_line ();
2222 bfdsym
= symbol_get_bfdsym (sym
);
2223 elfsym
= elf_symbol_from (bfdsym
);
2224 gas_assert (elfsym
);
2225 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2227 #endif /* OBJ_ELF */
2229 /* Output a 32-bit word, but mark as an instruction. */
2232 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2237 #ifdef md_flush_pending_output
2238 md_flush_pending_output ();
2241 if (is_it_end_of_statement ())
2243 demand_empty_rest_of_line ();
2247 /* Sections are assumed to start aligned. In executable section, there is no
2248 MAP_DATA symbol pending. So we only align the address during
2249 MAP_DATA --> MAP_INSN transition.
2250 For other sections, this is not guaranteed. */
2251 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2252 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2253 frag_align_code (2, 0);
2256 mapping_state (MAP_INSN
);
2262 if (exp
.X_op
!= O_constant
)
2264 as_bad (_("constant expression required"));
2265 ignore_rest_of_line ();
2269 if (target_big_endian
)
2271 unsigned int val
= exp
.X_add_number
;
2272 exp
.X_add_number
= SWAP_32 (val
);
2274 emit_expr (&exp
, INSN_SIZE
);
2277 while (*input_line_pointer
++ == ',');
2279 dwarf2_emit_insn (n
* INSN_SIZE
);
2281 /* Put terminator back into stream. */
2282 input_line_pointer
--;
2283 demand_empty_rest_of_line ();
2287 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2289 demand_empty_rest_of_line ();
2290 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2291 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2295 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2298 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2304 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2305 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2307 demand_empty_rest_of_line ();
2310 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2313 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2317 /* Since we're just labelling the code, there's no need to define a
2320 /* Make sure there is enough room in this frag for the following
2321 blr. This trick only works if the blr follows immediately after
2322 the .tlsdesc directive. */
2324 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2325 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2327 demand_empty_rest_of_line ();
2330 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2333 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2339 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2340 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2342 demand_empty_rest_of_line ();
2344 #endif /* OBJ_ELF */
2348 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2355 if (exp
.X_op
== O_symbol
)
2356 exp
.X_op
= O_secrel
;
2358 emit_expr (&exp
, 4);
2360 while (*input_line_pointer
++ == ',');
2362 input_line_pointer
--;
2363 demand_empty_rest_of_line ();
2367 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2371 exp
.X_op
= O_secrel
;
2372 exp
.X_add_symbol
= symbol
;
2373 exp
.X_add_number
= 0;
2374 emit_expr (&exp
, size
);
2378 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2385 if (exp
.X_op
== O_symbol
)
2386 exp
.X_op
= O_secidx
;
2388 emit_expr (&exp
, 2);
2390 while (*input_line_pointer
++ == ',');
2392 input_line_pointer
--;
2393 demand_empty_rest_of_line ();
2397 static void s_aarch64_arch (int);
2398 static void s_aarch64_cpu (int);
2399 static void s_aarch64_arch_extension (int);
2401 /* This table describes all the machine specific pseudo-ops the assembler
2402 has to support. The fields are:
2403 pseudo-op name without dot
2404 function to call to execute this pseudo-op
2405 Integer arg to pass to the function. */
2407 const pseudo_typeS md_pseudo_table
[] = {
2408 /* Never called because '.req' does not start a line. */
2410 {"unreq", s_unreq
, 0},
2412 {"even", s_even
, 0},
2413 {"ltorg", s_ltorg
, 0},
2414 {"pool", s_ltorg
, 0},
2415 {"cpu", s_aarch64_cpu
, 0},
2416 {"arch", s_aarch64_arch
, 0},
2417 {"arch_extension", s_aarch64_arch_extension
, 0},
2418 {"inst", s_aarch64_inst
, 0},
2419 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2421 {"tlsdescadd", s_tlsdescadd
, 0},
2422 {"tlsdesccall", s_tlsdesccall
, 0},
2423 {"tlsdescldr", s_tlsdescldr
, 0},
2424 {"variant_pcs", s_variant_pcs
, 0},
2426 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2427 {"word", s_aarch64_cons
, 4},
2428 {"long", s_aarch64_cons
, 4},
2429 {"xword", s_aarch64_cons
, 8},
2430 {"dword", s_aarch64_cons
, 8},
2433 {"secrel32", s_secrel
, 0},
2434 {"secidx", s_secidx
, 0},
2436 {"float16", float_cons
, 'h'},
2437 {"bfloat16", float_cons
, 'b'},
2442 /* Check whether STR points to a register name followed by a comma or the
2443 end of line; REG_TYPE indicates which register types are checked
2444 against. Return TRUE if STR is such a register name; otherwise return
2445 FALSE. The function does not intend to produce any diagnostics, but since
2446 the register parser aarch64_reg_parse, which is called by this function,
2447 does produce diagnostics, we call clear_error to clear any diagnostics
2448 that may be generated by aarch64_reg_parse.
2449 Also, the function returns FALSE directly if there is any user error
2450 present at the function entry. This prevents the existing diagnostics
2451 state from being spoiled.
2452 The function currently serves parse_constant_immediate and
2453 parse_big_immediate only. */
2455 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2457 const reg_entry
*reg
;
2459 /* Prevent the diagnostics state from being spoiled. */
2463 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2465 /* Clear the parsing error that may be set by the reg parser. */
2471 skip_whitespace (str
);
2472 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2478 /* Parser functions used exclusively in instruction operands. */
2480 /* Parse an immediate expression which may not be constant.
2482 To prevent the expression parser from pushing a register name
2483 into the symbol table as an undefined symbol, firstly a check is
2484 done to find out whether STR is a register of type REG_TYPE followed
2485 by a comma or the end of line. Return FALSE if STR is such a string. */
2488 parse_immediate_expression (char **str
, expressionS
*exp
,
2489 aarch64_reg_type reg_type
)
2491 if (reg_name_p (*str
, reg_type
))
2493 set_recoverable_error (_("immediate operand required"));
2497 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2499 if (exp
->X_op
== O_absent
)
2501 set_fatal_syntax_error (_("missing immediate expression"));
2508 /* Constant immediate-value read function for use in insn parsing.
2509 STR points to the beginning of the immediate (with the optional
2510 leading #); *VAL receives the value. REG_TYPE says which register
2511 names should be treated as registers rather than as symbolic immediates.
2513 Return TRUE on success; otherwise return FALSE. */
2516 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2520 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2523 if (exp
.X_op
!= O_constant
)
2525 set_syntax_error (_("constant expression required"));
2529 *val
= exp
.X_add_number
;
2534 encode_imm_float_bits (uint32_t imm
)
2536 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2537 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2540 /* Return TRUE if the single-precision floating-point value encoded in IMM
2541 can be expressed in the AArch64 8-bit signed floating-point format with
2542 3-bit exponent and normalized 4 bits of precision; in other words, the
2543 floating-point value must be expressable as
2544 (+/-) n / 16 * power (2, r)
2545 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2548 aarch64_imm_float_p (uint32_t imm
)
2550 /* If a single-precision floating-point value has the following bit
2551 pattern, it can be expressed in the AArch64 8-bit floating-point
2554 3 32222222 2221111111111
2555 1 09876543 21098765432109876543210
2556 n Eeeeeexx xxxx0000000000000000000
2558 where n, e and each x are either 0 or 1 independently, with
2563 /* Prepare the pattern for 'Eeeeee'. */
2564 if (((imm
>> 30) & 0x1) == 0)
2565 pattern
= 0x3e000000;
2567 pattern
= 0x40000000;
2569 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2570 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2573 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2574 as an IEEE float without any loss of precision. Store the value in
2578 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2580 /* If a double-precision floating-point value has the following bit
2581 pattern, it can be expressed in a float:
2583 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2584 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2585 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2587 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2588 if Eeee_eeee != 1111_1111
2590 where n, e, s and S are either 0 or 1 independently and where ~ is the
2594 uint32_t high32
= imm
>> 32;
2595 uint32_t low32
= imm
;
2597 /* Lower 29 bits need to be 0s. */
2598 if ((imm
& 0x1fffffff) != 0)
2601 /* Prepare the pattern for 'Eeeeeeeee'. */
2602 if (((high32
>> 30) & 0x1) == 0)
2603 pattern
= 0x38000000;
2605 pattern
= 0x40000000;
2608 if ((high32
& 0x78000000) != pattern
)
2611 /* Check Eeee_eeee != 1111_1111. */
2612 if ((high32
& 0x7ff00000) == 0x47f00000)
2615 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2616 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2617 | (low32
>> 29)); /* 3 S bits. */
2621 /* Return true if we should treat OPERAND as a double-precision
2622 floating-point operand rather than a single-precision one. */
2624 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2626 /* Check for unsuffixed SVE registers, which are allowed
2627 for LDR and STR but not in instructions that require an
2628 immediate. We get better error messages if we arbitrarily
2629 pick one size, parse the immediate normally, and then
2630 report the match failure in the normal way. */
2631 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2632 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2635 /* Parse a floating-point immediate. Return TRUE on success and return the
2636 value in *IMMED in the format of IEEE754 single-precision encoding.
2637 *CCP points to the start of the string; DP_P is TRUE when the immediate
2638 is expected to be in double-precision (N.B. this only matters when
2639 hexadecimal representation is involved). REG_TYPE says which register
2640 names should be treated as registers rather than as symbolic immediates.
2642 This routine accepts any IEEE float; it is up to the callers to reject
2646 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2647 aarch64_reg_type reg_type
)
2651 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2653 unsigned fpword
= 0;
2656 skip_past_char (&str
, '#');
2659 skip_whitespace (fpnum
);
2661 if (startswith (fpnum
, "0x"))
2663 /* Support the hexadecimal representation of the IEEE754 encoding.
2664 Double-precision is expected when DP_P is TRUE, otherwise the
2665 representation should be in single-precision. */
2666 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2671 if (!can_convert_double_to_float (val
, &fpword
))
2674 else if ((uint64_t) val
> 0xffffffff)
2681 else if (reg_name_p (str
, reg_type
))
2683 set_recoverable_error (_("immediate operand required"));
2691 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2694 /* Our FP word must be 32 bits (single-precision FP). */
2695 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2697 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2707 set_fatal_syntax_error (_("invalid floating-point constant"));
2711 /* Less-generic immediate-value read function with the possibility of loading
2712 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2715 To prevent the expression parser from pushing a register name into the
2716 symbol table as an undefined symbol, a check is firstly done to find
2717 out whether STR is a register of type REG_TYPE followed by a comma or
2718 the end of line. Return FALSE if STR is such a register. */
2721 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2725 if (reg_name_p (ptr
, reg_type
))
2727 set_syntax_error (_("immediate operand required"));
2731 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2733 if (inst
.reloc
.exp
.X_op
== O_constant
)
2734 *imm
= inst
.reloc
.exp
.X_add_number
;
2741 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2742 if NEED_LIBOPCODES is non-zero, the fixup will need
2743 assistance from the libopcodes. */
2746 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2747 const aarch64_opnd_info
*operand
,
2748 int need_libopcodes_p
)
2750 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2751 reloc
->opnd
= operand
->type
;
2752 if (need_libopcodes_p
)
2753 reloc
->need_libopcodes_p
= 1;
2756 /* Return TRUE if the instruction needs to be fixed up later internally by
2757 the GAS; otherwise return FALSE. */
2760 aarch64_gas_internal_fixup_p (void)
2762 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2765 /* Assign the immediate value to the relevant field in *OPERAND if
2766 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2767 needs an internal fixup in a later stage.
2768 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2769 IMM.VALUE that may get assigned with the constant. */
2771 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2772 aarch64_opnd_info
*operand
,
2774 int need_libopcodes_p
,
2777 if (reloc
->exp
.X_op
== O_constant
)
2780 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2782 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2783 reloc
->type
= BFD_RELOC_UNUSED
;
2787 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2788 /* Tell libopcodes to ignore this operand or not. This is helpful
2789 when one of the operands needs to be fixed up later but we need
2790 libopcodes to check the other operands. */
2791 operand
->skip
= skip_p
;
2795 /* Relocation modifiers. Each entry in the table contains the textual
2796 name for the relocation which may be placed before a symbol used as
2797 a load/store offset, or add immediate. It must be surrounded by a
2798 leading and trailing colon, for example:
2800 ldr x0, [x1, #:rello:varsym]
2801 add x0, x1, #:rello:varsym */
2803 struct reloc_table_entry
2807 bfd_reloc_code_real_type adr_type
;
2808 bfd_reloc_code_real_type adrp_type
;
2809 bfd_reloc_code_real_type movw_type
;
2810 bfd_reloc_code_real_type add_type
;
2811 bfd_reloc_code_real_type ldst_type
;
2812 bfd_reloc_code_real_type ld_literal_type
;
2815 static struct reloc_table_entry reloc_table
[] =
2817 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2822 BFD_RELOC_AARCH64_ADD_LO12
,
2823 BFD_RELOC_AARCH64_LDST_LO12
,
2826 /* Higher 21 bits of pc-relative page offset: ADRP */
2829 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2835 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2838 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2844 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2848 BFD_RELOC_AARCH64_MOVW_G0
,
2853 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2857 BFD_RELOC_AARCH64_MOVW_G0_S
,
2862 /* Less significant bits 0-15 of address/value: MOVK, no check */
2866 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2871 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2875 BFD_RELOC_AARCH64_MOVW_G1
,
2880 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2884 BFD_RELOC_AARCH64_MOVW_G1_S
,
2889 /* Less significant bits 16-31 of address/value: MOVK, no check */
2893 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2898 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2902 BFD_RELOC_AARCH64_MOVW_G2
,
2907 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2911 BFD_RELOC_AARCH64_MOVW_G2_S
,
2916 /* Less significant bits 32-47 of address/value: MOVK, no check */
2920 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2925 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2929 BFD_RELOC_AARCH64_MOVW_G3
,
2934 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2938 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2943 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2947 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2952 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2956 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2961 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2965 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2970 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2974 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2979 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2983 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2988 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2992 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2997 /* Get to the page containing GOT entry for a symbol. */
3000 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
3004 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
3006 /* 12 bit offset into the page containing GOT entry for that symbol. */
3012 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
3015 /* 0-15 bits of address/value: MOVk, no check. */
3019 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
3024 /* Most significant bits 16-31 of address/value: MOVZ. */
3028 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
3033 /* 15 bit offset into the page containing GOT entry for that symbol. */
3039 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
3042 /* Get to the page containing GOT TLS entry for a symbol */
3043 {"gottprel_g0_nc", 0,
3046 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
3051 /* Get to the page containing GOT TLS entry for a symbol */
3055 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
3060 /* Get to the page containing GOT TLS entry for a symbol */
3062 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
3063 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
3069 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3074 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
3078 /* Lower 16 bits address/value: MOVk. */
3082 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
3087 /* Most significant bits 16-31 of address/value: MOVZ. */
3091 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
3096 /* Get to the page containing GOT TLS entry for a symbol */
3098 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
3099 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
3103 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
3105 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3110 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
3111 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
3114 /* Get to the page containing GOT TLS entry for a symbol.
3115 The same as GD, we allocate two consecutive GOT slots
3116 for module index and module offset, the only difference
3117 with GD is the module offset should be initialized to
3118 zero without any outstanding runtime relocation. */
3120 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
3121 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
3127 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3128 {"tlsldm_lo12_nc", 0,
3132 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
3136 /* 12 bit offset into the module TLS base address. */
3141 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
3142 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
3145 /* Same as dtprel_lo12, no overflow check. */
3146 {"dtprel_lo12_nc", 0,
3150 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
3151 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3154 /* bits[23:12] of offset to the module TLS base address. */
3159 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3163 /* bits[15:0] of offset to the module TLS base address. */
3167 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3172 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3176 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3181 /* bits[31:16] of offset to the module TLS base address. */
3185 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3190 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3194 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3199 /* bits[47:32] of offset to the module TLS base address. */
3203 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3208 /* Lower 16 bit offset into GOT entry for a symbol */
3209 {"tlsdesc_off_g0_nc", 0,
3212 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3217 /* Higher 16 bit offset into GOT entry for a symbol */
3218 {"tlsdesc_off_g1", 0,
3221 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3226 /* Get to the page containing GOT TLS entry for a symbol */
3229 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3233 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3235 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3236 {"gottprel_lo12", 0,
3241 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3244 /* Get tp offset for a symbol. */
3249 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3253 /* Get tp offset for a symbol. */
3258 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3259 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3262 /* Get tp offset for a symbol. */
3267 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3271 /* Get tp offset for a symbol. */
3272 {"tprel_lo12_nc", 0,
3276 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3277 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3280 /* Most significant bits 32-47 of address/value: MOVZ. */
3284 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3289 /* Most significant bits 16-31 of address/value: MOVZ. */
3293 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3298 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3302 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3307 /* Most significant bits 0-15 of address/value: MOVZ. */
3311 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3316 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3320 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3325 /* 15bit offset from got entry to base address of GOT table. */
3331 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3334 /* 14bit offset from got entry to base address of GOT table. */
3340 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3344 /* Given the address of a pointer pointing to the textual name of a
3345 relocation as may appear in assembler source, attempt to find its
3346 details in reloc_table. The pointer will be updated to the character
3347 after the trailing colon. On failure, NULL will be returned;
3348 otherwise return the reloc_table_entry. */
3350 static struct reloc_table_entry
*
3351 find_reloc_table_entry (char **str
)
3354 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3356 int length
= strlen (reloc_table
[i
].name
);
3358 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3359 && (*str
)[length
] == ':')
3361 *str
+= (length
+ 1);
3362 return &reloc_table
[i
];
3369 /* Returns 0 if the relocation should never be forced,
3370 1 if the relocation must be forced, and -1 if either
3374 aarch64_force_reloc (unsigned int type
)
3378 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3379 /* Perform these "immediate" internal relocations
3380 even if the symbol is extern or weak. */
3383 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3384 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3385 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3386 /* Pseudo relocs that need to be fixed up according to
3390 case BFD_RELOC_AARCH64_ADD_LO12
:
3391 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3392 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3393 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3394 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3395 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3396 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3397 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3398 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3399 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3400 case BFD_RELOC_AARCH64_LDST128_LO12
:
3401 case BFD_RELOC_AARCH64_LDST16_LO12
:
3402 case BFD_RELOC_AARCH64_LDST32_LO12
:
3403 case BFD_RELOC_AARCH64_LDST64_LO12
:
3404 case BFD_RELOC_AARCH64_LDST8_LO12
:
3405 case BFD_RELOC_AARCH64_LDST_LO12
:
3406 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3407 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3408 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3409 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3410 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3411 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3412 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3413 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3414 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3415 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3416 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3417 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3418 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3419 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3420 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3421 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3422 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3423 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3424 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3425 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3426 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3427 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3428 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3429 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3430 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3431 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3432 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3433 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3434 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3435 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3436 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3437 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3438 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3439 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3440 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3441 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3442 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3443 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3444 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3445 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3446 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3447 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3448 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3449 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3450 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3451 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3452 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3453 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3454 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3455 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3456 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3457 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3458 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3459 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3460 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3461 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3462 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3463 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3464 /* Always leave these relocations for the linker. */
3473 aarch64_force_relocation (struct fix
*fixp
)
3475 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3478 return generic_force_reloc (fixp
);
3482 /* Mode argument to parse_shift and parser_shifter_operand. */
3483 enum parse_shift_mode
3485 SHIFTED_NONE
, /* no shifter allowed */
3486 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3488 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3490 SHIFTED_LSL
, /* bare "lsl #n" */
3491 SHIFTED_MUL
, /* bare "mul #n" */
3492 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3493 SHIFTED_MUL_VL
, /* "mul vl" */
3494 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3497 /* Parse a <shift> operator on an AArch64 data processing instruction.
3498 Return TRUE on success; otherwise return FALSE. */
3500 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3502 const struct aarch64_name_value_pair
*shift_op
;
3503 enum aarch64_modifier_kind kind
;
3509 for (p
= *str
; ISALPHA (*p
); p
++)
3514 set_syntax_error (_("shift expression expected"));
3518 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3520 if (shift_op
== NULL
)
3522 set_syntax_error (_("shift operator expected"));
3526 kind
= aarch64_get_operand_modifier (shift_op
);
3528 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3530 set_syntax_error (_("invalid use of 'MSL'"));
3534 if (kind
== AARCH64_MOD_MUL
3535 && mode
!= SHIFTED_MUL
3536 && mode
!= SHIFTED_MUL_VL
)
3538 set_syntax_error (_("invalid use of 'MUL'"));
3544 case SHIFTED_LOGIC_IMM
:
3545 if (aarch64_extend_operator_p (kind
))
3547 set_syntax_error (_("extending shift is not permitted"));
3552 case SHIFTED_ARITH_IMM
:
3553 if (kind
== AARCH64_MOD_ROR
)
3555 set_syntax_error (_("'ROR' shift is not permitted"));
3561 if (kind
!= AARCH64_MOD_LSL
)
3563 set_syntax_error (_("only 'LSL' shift is permitted"));
3569 if (kind
!= AARCH64_MOD_MUL
)
3571 set_syntax_error (_("only 'MUL' is permitted"));
3576 case SHIFTED_MUL_VL
:
3577 /* "MUL VL" consists of two separate tokens. Require the first
3578 token to be "MUL" and look for a following "VL". */
3579 if (kind
== AARCH64_MOD_MUL
)
3581 skip_whitespace (p
);
3582 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3585 kind
= AARCH64_MOD_MUL_VL
;
3589 set_syntax_error (_("only 'MUL VL' is permitted"));
3592 case SHIFTED_REG_OFFSET
:
3593 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3594 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3596 set_fatal_syntax_error
3597 (_("invalid shift for the register offset addressing mode"));
3602 case SHIFTED_LSL_MSL
:
3603 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3605 set_syntax_error (_("invalid shift operator"));
3614 /* Whitespace can appear here if the next thing is a bare digit. */
3615 skip_whitespace (p
);
3617 /* Parse shift amount. */
3619 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3620 exp
.X_op
= O_absent
;
3623 if (is_immediate_prefix (*p
))
3628 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3630 if (kind
== AARCH64_MOD_MUL_VL
)
3631 /* For consistency, give MUL VL the same shift amount as an implicit
3633 operand
->shifter
.amount
= 1;
3634 else if (exp
.X_op
== O_absent
)
3636 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3638 set_syntax_error (_("missing shift amount"));
3641 operand
->shifter
.amount
= 0;
3643 else if (exp
.X_op
!= O_constant
)
3645 set_syntax_error (_("constant shift amount required"));
3648 /* For parsing purposes, MUL #n has no inherent range. The range
3649 depends on the operand and will be checked by operand-specific
3651 else if (kind
!= AARCH64_MOD_MUL
3652 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3654 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3659 operand
->shifter
.amount
= exp
.X_add_number
;
3660 operand
->shifter
.amount_present
= 1;
3663 operand
->shifter
.operator_present
= 1;
3664 operand
->shifter
.kind
= kind
;
3670 /* Parse a <shifter_operand> for a data processing instruction:
3673 #<immediate>, LSL #imm
3675 Validation of immediate operands is deferred to md_apply_fix.
3677 Return TRUE on success; otherwise return FALSE. */
3680 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3681 enum parse_shift_mode mode
)
3685 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3690 /* Accept an immediate expression. */
3691 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3695 /* Accept optional LSL for arithmetic immediate values. */
3696 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3697 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3700 /* Not accept any shifter for logical immediate values. */
3701 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3702 && parse_shift (&p
, operand
, mode
))
3704 set_syntax_error (_("unexpected shift operator"));
3712 /* Parse a <shifter_operand> for a data processing instruction:
3717 #<immediate>, LSL #imm
3719 where <shift> is handled by parse_shift above, and the last two
3720 cases are handled by the function above.
3722 Validation of immediate operands is deferred to md_apply_fix.
3724 Return TRUE on success; otherwise return FALSE. */
3727 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3728 enum parse_shift_mode mode
)
3730 const reg_entry
*reg
;
3731 aarch64_opnd_qualifier_t qualifier
;
3732 enum aarch64_operand_class opd_class
3733 = aarch64_get_operand_class (operand
->type
);
3735 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3738 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3740 set_syntax_error (_("unexpected register in the immediate operand"));
3744 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR
))
3746 set_expected_reg_error (REG_TYPE_R_ZR
, reg
, 0);
3750 operand
->reg
.regno
= reg
->number
;
3751 operand
->qualifier
= qualifier
;
3753 /* Accept optional shift operation on register. */
3754 if (! skip_past_comma (str
))
3757 if (! parse_shift (str
, operand
, mode
))
3762 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3765 (_("integer register expected in the extended/shifted operand "
3770 /* We have a shifted immediate variable. */
3771 return parse_shifter_operand_imm (str
, operand
, mode
);
3774 /* Return TRUE on success; return FALSE otherwise. */
3777 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3778 enum parse_shift_mode mode
)
3782 /* Determine if we have the sequence of characters #: or just :
3783 coming next. If we do, then we check for a :rello: relocation
3784 modifier. If we don't, punt the whole lot to
3785 parse_shifter_operand. */
3787 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3789 struct reloc_table_entry
*entry
;
3797 /* Try to parse a relocation. Anything else is an error. */
3798 if (!(entry
= find_reloc_table_entry (str
)))
3800 set_syntax_error (_("unknown relocation modifier"));
3804 if (entry
->add_type
== 0)
3807 (_("this relocation modifier is not allowed on this instruction"));
3811 /* Save str before we decompose it. */
3814 /* Next, we parse the expression. */
3815 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3819 /* Record the relocation type (use the ADD variant here). */
3820 inst
.reloc
.type
= entry
->add_type
;
3821 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3823 /* If str is empty, we've reached the end, stop here. */
3827 /* Otherwise, we have a shifted reloc modifier, so rewind to
3828 recover the variable name and continue parsing for the shifter. */
3830 return parse_shifter_operand_imm (str
, operand
, mode
);
3833 return parse_shifter_operand (str
, operand
, mode
);
3836 /* Parse all forms of an address expression. Information is written
3837 to *OPERAND and/or inst.reloc.
3839 The A64 instruction set has the following addressing modes:
3842 [base] // in SIMD ld/st structure
3843 [base{,#0}] // in ld/st exclusive
3845 [base,Xm{,LSL #imm}]
3846 [base,Xm,SXTX {#imm}]
3847 [base,Wm,(S|U)XTW {#imm}]
3849 [base]! // in ldraa/ldrab exclusive
3853 [base],Xm // in SIMD ld/st structure
3854 PC-relative (literal)
3858 [base,Zm.D{,LSL #imm}]
3859 [base,Zm.S,(S|U)XTW {#imm}]
3860 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3864 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3865 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3866 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3868 (As a convenience, the notation "=immediate" is permitted in conjunction
3869 with the pc-relative literal load instructions to automatically place an
3870 immediate value or symbolic address in a nearby literal pool and generate
3871 a hidden label which references it.)
3873 Upon a successful parsing, the address structure in *OPERAND will be
3874 filled in the following way:
3876 .base_regno = <base>
3877 .offset.is_reg // 1 if the offset is a register
3879 .offset.regno = <Rm>
3881 For different addressing modes defined in the A64 ISA:
3884 .pcrel=0; .preind=1; .postind=0; .writeback=0
3886 .pcrel=0; .preind=1; .postind=0; .writeback=1
3888 .pcrel=0; .preind=0; .postind=1; .writeback=1
3889 PC-relative (literal)
3890 .pcrel=1; .preind=1; .postind=0; .writeback=0
3892 The shift/extension information, if any, will be stored in .shifter.
3893 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3894 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3895 corresponding register.
3897 BASE_TYPE says which types of base register should be accepted and
3898 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3899 is the type of shifter that is allowed for immediate offsets,
3900 or SHIFTED_NONE if none.
3902 In all other respects, it is the caller's responsibility to check
3903 for addressing modes not supported by the instruction, and to set
3907 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3908 aarch64_opnd_qualifier_t
*base_qualifier
,
3909 aarch64_opnd_qualifier_t
*offset_qualifier
,
3910 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3911 enum parse_shift_mode imm_shift_mode
)
3914 const reg_entry
*reg
;
3915 expressionS
*exp
= &inst
.reloc
.exp
;
3917 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3918 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3919 if (! skip_past_char (&p
, '['))
3921 /* =immediate or label. */
3922 operand
->addr
.pcrel
= 1;
3923 operand
->addr
.preind
= 1;
3925 /* #:<reloc_op>:<symbol> */
3926 skip_past_char (&p
, '#');
3927 if (skip_past_char (&p
, ':'))
3929 bfd_reloc_code_real_type ty
;
3930 struct reloc_table_entry
*entry
;
3932 /* Try to parse a relocation modifier. Anything else is
3934 entry
= find_reloc_table_entry (&p
);
3937 set_syntax_error (_("unknown relocation modifier"));
3941 switch (operand
->type
)
3943 case AARCH64_OPND_ADDR_PCREL21
:
3945 ty
= entry
->adr_type
;
3949 ty
= entry
->ld_literal_type
;
3956 (_("this relocation modifier is not allowed on this "
3962 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3964 set_syntax_error (_("invalid relocation expression"));
3967 /* #:<reloc_op>:<expr> */
3968 /* Record the relocation type. */
3969 inst
.reloc
.type
= ty
;
3970 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3974 if (skip_past_char (&p
, '='))
3975 /* =immediate; need to generate the literal in the literal pool. */
3976 inst
.gen_lit_pool
= 1;
3978 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3980 set_syntax_error (_("invalid address"));
3991 bool alpha_base_p
= ISALPHA (*p
);
3992 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3993 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3996 && aarch64_check_reg_type (reg
, REG_TYPE_R_SP
)
3997 && *base_qualifier
== AARCH64_OPND_QLF_W
)
3998 set_syntax_error (_("expected a 64-bit base register"));
3999 else if (alpha_base_p
)
4000 set_syntax_error (_("invalid base register"));
4002 set_syntax_error (_("expected a base register"));
4005 operand
->addr
.base_regno
= reg
->number
;
4008 if (skip_past_comma (&p
))
4011 operand
->addr
.preind
= 1;
4013 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
4016 if (!aarch64_check_reg_type (reg
, offset_type
))
4018 set_syntax_error (_("invalid offset register"));
4023 operand
->addr
.offset
.regno
= reg
->number
;
4024 operand
->addr
.offset
.is_reg
= 1;
4025 /* Shifted index. */
4026 if (skip_past_comma (&p
))
4029 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
4030 /* Use the diagnostics set in parse_shift, so not set new
4031 error message here. */
4035 [base,Xm] # For vector plus scalar SVE2 indexing.
4036 [base,Xm{,LSL #imm}]
4037 [base,Xm,SXTX {#imm}]
4038 [base,Wm,(S|U)XTW {#imm}] */
4039 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
4040 || operand
->shifter
.kind
== AARCH64_MOD_LSL
4041 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
4043 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
4045 set_syntax_error (_("invalid use of 32-bit register offset"));
4048 if (aarch64_get_qualifier_esize (*base_qualifier
)
4049 != aarch64_get_qualifier_esize (*offset_qualifier
)
4050 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
4051 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
4052 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
4054 set_syntax_error (_("offset has different size from base"));
4058 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
4060 set_syntax_error (_("invalid use of 64-bit register offset"));
4066 /* [Xn,#:<reloc_op>:<symbol> */
4067 skip_past_char (&p
, '#');
4068 if (skip_past_char (&p
, ':'))
4070 struct reloc_table_entry
*entry
;
4072 /* Try to parse a relocation modifier. Anything else is
4074 if (!(entry
= find_reloc_table_entry (&p
)))
4076 set_syntax_error (_("unknown relocation modifier"));
4080 if (entry
->ldst_type
== 0)
4083 (_("this relocation modifier is not allowed on this "
4088 /* [Xn,#:<reloc_op>: */
4089 /* We now have the group relocation table entry corresponding to
4090 the name in the assembler source. Next, we parse the
4092 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4094 set_syntax_error (_("invalid relocation expression"));
4098 /* [Xn,#:<reloc_op>:<expr> */
4099 /* Record the load/store relocation type. */
4100 inst
.reloc
.type
= entry
->ldst_type
;
4101 inst
.reloc
.pc_rel
= entry
->pc_rel
;
4105 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4107 set_syntax_error (_("invalid expression in the address"));
4111 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
4112 /* [Xn,<expr>,<shifter> */
4113 if (! parse_shift (&p
, operand
, imm_shift_mode
))
4119 if (! skip_past_char (&p
, ']'))
4121 set_syntax_error (_("']' expected"));
4125 if (skip_past_char (&p
, '!'))
4127 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
4129 set_syntax_error (_("register offset not allowed in pre-indexed "
4130 "addressing mode"));
4134 operand
->addr
.writeback
= 1;
4136 else if (skip_past_comma (&p
))
4139 operand
->addr
.postind
= 1;
4140 operand
->addr
.writeback
= 1;
4142 if (operand
->addr
.preind
)
4144 set_syntax_error (_("cannot combine pre- and post-indexing"));
4148 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
4152 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4154 set_syntax_error (_("invalid offset register"));
4158 operand
->addr
.offset
.regno
= reg
->number
;
4159 operand
->addr
.offset
.is_reg
= 1;
4161 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4164 set_syntax_error (_("invalid expression in the address"));
4169 /* If at this point neither .preind nor .postind is set, we have a
4170 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4171 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4172 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4174 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4176 if (operand
->addr
.writeback
)
4178 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4180 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4181 operand
->addr
.offset
.is_reg
= 0;
4182 operand
->addr
.offset
.imm
= 0;
4183 operand
->addr
.preind
= 1;
4188 set_syntax_error (_("missing offset in the pre-indexed address"));
4194 operand
->addr
.preind
= 1;
4195 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4197 operand
->addr
.offset
.is_reg
= 1;
4198 operand
->addr
.offset
.regno
= REG_ZR
;
4199 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4203 inst
.reloc
.exp
.X_op
= O_constant
;
4204 inst
.reloc
.exp
.X_add_number
= 0;
4213 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4216 parse_address (char **str
, aarch64_opnd_info
*operand
)
4218 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4219 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4220 REG_TYPE_R64_SP
, REG_TYPE_R_ZR
, SHIFTED_NONE
);
4223 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4224 The arguments have the same meaning as for parse_address_main.
4225 Return TRUE on success. */
4227 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4228 aarch64_opnd_qualifier_t
*base_qualifier
,
4229 aarch64_opnd_qualifier_t
*offset_qualifier
)
4231 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4232 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4236 /* Parse a register X0-X30. The register must be 64-bit and register 31
4239 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4241 const reg_entry
*reg
= parse_reg (str
);
4242 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4244 set_expected_reg_error (REG_TYPE_R_64
, reg
, 0);
4247 operand
->reg
.regno
= reg
->number
;
4248 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4252 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4253 Return TRUE on success; otherwise return FALSE. */
4255 parse_half (char **str
, int *internal_fixup_p
)
4259 skip_past_char (&p
, '#');
4261 gas_assert (internal_fixup_p
);
4262 *internal_fixup_p
= 0;
4266 struct reloc_table_entry
*entry
;
4268 /* Try to parse a relocation. Anything else is an error. */
4271 if (!(entry
= find_reloc_table_entry (&p
)))
4273 set_syntax_error (_("unknown relocation modifier"));
4277 if (entry
->movw_type
== 0)
4280 (_("this relocation modifier is not allowed on this instruction"));
4284 inst
.reloc
.type
= entry
->movw_type
;
4287 *internal_fixup_p
= 1;
4289 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4296 /* Parse an operand for an ADRP instruction:
4298 Return TRUE on success; otherwise return FALSE. */
4301 parse_adrp (char **str
)
4308 struct reloc_table_entry
*entry
;
4310 /* Try to parse a relocation. Anything else is an error. */
4312 if (!(entry
= find_reloc_table_entry (&p
)))
4314 set_syntax_error (_("unknown relocation modifier"));
4318 if (entry
->adrp_type
== 0)
4321 (_("this relocation modifier is not allowed on this instruction"));
4325 inst
.reloc
.type
= entry
->adrp_type
;
4328 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4330 inst
.reloc
.pc_rel
= 1;
4331 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4337 /* Miscellaneous. */
4339 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4340 of SIZE tokens in which index I gives the token for field value I,
4341 or is null if field value I is invalid. If the symbolic operand
4342 can also be given as a 0-based integer, REG_TYPE says which register
4343 names should be treated as registers rather than as symbolic immediates
4344 while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise.
4346 Return true on success, moving *STR past the operand and storing the
4347 field value in *VAL. */
4350 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4351 size_t size
, aarch64_reg_type reg_type
)
4357 /* Match C-like tokens. */
4359 while (ISALNUM (*q
))
4362 for (i
= 0; i
< size
; ++i
)
4364 && strncasecmp (array
[i
], p
, q
- p
) == 0
4365 && array
[i
][q
- p
] == 0)
4372 if (reg_type
== REG_TYPE_MAX
)
4375 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4378 if (exp
.X_op
== O_constant
4379 && (uint64_t) exp
.X_add_number
< size
)
4381 *val
= exp
.X_add_number
;
4386 /* Use the default error for this operand. */
4390 /* Parse an option for a preload instruction. Returns the encoding for the
4391 option, or PARSE_FAIL. */
4394 parse_pldop (char **str
)
4397 const struct aarch64_name_value_pair
*o
;
4400 while (ISALNUM (*q
))
4403 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4411 /* Parse an option for a barrier instruction. Returns the encoding for the
4412 option, or PARSE_FAIL. */
4415 parse_barrier (char **str
)
4418 const struct aarch64_name_value_pair
*o
;
4421 while (ISALPHA (*q
))
4424 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4432 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4433 return 0 if successful. Otherwise return PARSE_FAIL. */
4436 parse_barrier_psb (char **str
,
4437 const struct aarch64_name_value_pair
** hint_opt
)
4440 const struct aarch64_name_value_pair
*o
;
4443 while (ISALPHA (*q
))
4446 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4449 set_fatal_syntax_error
4450 ( _("unknown or missing option to PSB/TSB"));
4454 if (o
->value
!= 0x11)
4456 /* PSB only accepts option name 'CSYNC'. */
4458 (_("the specified option is not accepted for PSB/TSB"));
4467 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4468 return 0 if successful. Otherwise return PARSE_FAIL. */
4471 parse_bti_operand (char **str
,
4472 const struct aarch64_name_value_pair
** hint_opt
)
4475 const struct aarch64_name_value_pair
*o
;
4478 while (ISALPHA (*q
))
4481 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4484 set_fatal_syntax_error
4485 ( _("unknown option to BTI"));
4491 /* Valid BTI operands. */
4499 (_("unknown option to BTI"));
4508 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4509 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4514 Side effect: Update STR with current parse position of success.
4516 FLAGS is as for parse_typed_reg. */
4518 static const reg_entry
*
4519 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4520 aarch64_opnd_qualifier_t
*qualifier
, unsigned int flags
)
4522 struct vector_type_el vectype
;
4523 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4524 PTR_FULL_REG
| flags
);
4528 if (vectype
.type
== NT_invtype
)
4529 *qualifier
= AARCH64_OPND_QLF_NIL
;
4532 *qualifier
= vectype_to_qualifier (&vectype
);
4533 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4540 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4545 Function return TRUE if immediate was found, or FALSE.
4548 parse_sme_immediate (char **str
, int64_t *imm
)
4551 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4558 /* Parse index with selection register and immediate offset:
4563 Return true on success, populating OPND with the parsed index. */
4566 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4568 const reg_entry
*reg
;
4570 if (!skip_past_char (str
, '['))
4572 set_syntax_error (_("expected '['"));
4576 /* The selection register, encoded in the 2-bit Rv field. */
4577 reg
= parse_reg (str
);
4578 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
)
4580 set_syntax_error (_("expected a 32-bit selection register"));
4583 opnd
->index
.regno
= reg
->number
;
4585 if (!skip_past_char (str
, ','))
4587 set_syntax_error (_("missing immediate offset"));
4591 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4593 set_syntax_error (_("expected a constant immediate offset"));
4597 if (skip_past_char (str
, ':'))
4600 if (!parse_sme_immediate (str
, &end
))
4602 set_syntax_error (_("expected a constant immediate offset"));
4605 if (end
< opnd
->index
.imm
)
4607 set_syntax_error (_("the last offset is less than the"
4611 if (end
== opnd
->index
.imm
)
4613 set_syntax_error (_("the last offset is equal to the"
4617 opnd
->index
.countm1
= (uint64_t) end
- opnd
->index
.imm
;
4620 opnd
->group_size
= 0;
4621 if (skip_past_char (str
, ','))
4623 if (strncasecmp (*str
, "vgx2", 4) == 0 && !ISALPHA ((*str
)[4]))
4626 opnd
->group_size
= 2;
4628 else if (strncasecmp (*str
, "vgx4", 4) == 0 && !ISALPHA ((*str
)[4]))
4631 opnd
->group_size
= 4;
4635 set_syntax_error (_("invalid vector group size"));
4640 if (!skip_past_char (str
, ']'))
4642 set_syntax_error (_("expected ']'"));
4649 /* Parse a register of type REG_TYPE that might have an element type
4650 qualifier and that is indexed by two values: a 32-bit register,
4651 followed by an immediate. The ranges of the register and the
4652 immediate vary by opcode and are checked in libopcodes.
4654 Return true on success, populating OPND with information about
4655 the operand and setting QUALIFIER to the register qualifier.
4657 Field format examples:
4659 <Pm>.<T>[<Wv>< #<imm>]
4661 <ZAn><HV>.<T>[<Wv>, #<imm>]
4663 FLAGS is as for parse_typed_reg. */
4666 parse_dual_indexed_reg (char **str
, aarch64_reg_type reg_type
,
4667 struct aarch64_indexed_za
*opnd
,
4668 aarch64_opnd_qualifier_t
*qualifier
,
4671 const reg_entry
*reg
= parse_reg_with_qual (str
, reg_type
, qualifier
, flags
);
4675 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4676 opnd
->regno
= reg
->number
;
4678 return parse_sme_za_index (str
, opnd
);
4681 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4685 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4686 struct aarch64_indexed_za
*opnd
,
4687 aarch64_opnd_qualifier_t
*qualifier
)
4689 if (!skip_past_char (str
, '{'))
4691 set_expected_reglist_error (REG_TYPE_ZATHV
, parse_reg (str
));
4695 if (!parse_dual_indexed_reg (str
, REG_TYPE_ZATHV
, opnd
, qualifier
,
4699 if (!skip_past_char (str
, '}'))
4701 set_syntax_error (_("expected '}'"));
4708 /* Parse list of up to eight 64-bit element tile names separated by commas in
4709 SME's ZERO instruction:
4713 Function returns <mask>:
4715 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4718 parse_sme_zero_mask(char **str
)
4722 aarch64_opnd_qualifier_t qualifier
;
4723 unsigned int ptr_flags
= PTR_IN_REGLIST
;
4729 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4730 &qualifier
, ptr_flags
);
4734 if (reg
->type
== REG_TYPE_ZA
)
4736 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4738 set_syntax_error ("ZA should not have a size suffix");
4741 /* { ZA } is assembled as all-ones immediate. */
4746 int regno
= reg
->number
;
4747 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4749 /* { ZA0.B } is assembled as all-ones immediate. */
4752 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4753 mask
|= 0x55 << regno
;
4754 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4755 mask
|= 0x11 << regno
;
4756 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4757 mask
|= 0x01 << regno
;
4758 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4760 set_syntax_error (_("ZA tile masks do not operate at .Q"
4764 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4766 set_syntax_error (_("missing ZA tile size"));
4771 set_syntax_error (_("invalid ZA tile"));
4775 ptr_flags
|= PTR_GOOD_MATCH
;
4777 while (skip_past_char (&q
, ','));
4783 /* Wraps in curly braces <mask> operand ZERO instruction:
4787 Function returns value of <mask> bit-field.
4790 parse_sme_list_of_64bit_tiles (char **str
)
4794 if (!skip_past_char (str
, '{'))
4796 set_syntax_error (_("expected '{'"));
4800 /* Empty <mask> list is an all-zeros immediate. */
4801 if (!skip_past_char (str
, '}'))
4803 regno
= parse_sme_zero_mask (str
);
4804 if (regno
== PARSE_FAIL
)
4807 if (!skip_past_char (str
, '}'))
4809 set_syntax_error (_("expected '}'"));
4819 /* Parse streaming mode operand for SMSTART and SMSTOP.
4823 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4826 parse_sme_sm_za (char **str
)
4831 while (ISALPHA (*q
))
4835 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4837 set_syntax_error (_("expected SM or ZA operand"));
4842 return TOLOWER (p
[0]);
4845 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4846 Returns the encoding for the option, or PARSE_FAIL.
4848 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4849 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4851 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4852 field, otherwise as a system register.
4856 parse_sys_reg (char **str
, htab_t sys_regs
,
4857 int imple_defined_p
, int pstatefield_p
,
4861 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4862 const aarch64_sys_reg
*o
;
4866 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4867 if (p
< buf
+ (sizeof (buf
) - 1))
4868 *p
++ = TOLOWER (*q
);
4871 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4872 valid system register. This is enforced by construction of the hash
4874 if (p
- buf
!= q
- *str
)
4877 o
= str_hash_find (sys_regs
, buf
);
4880 if (!imple_defined_p
)
4884 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4885 unsigned int op0
, op1
, cn
, cm
, op2
;
4887 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4890 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4892 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4899 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4900 as_bad (_("selected processor does not support PSTATE field "
4903 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4904 o
->value
, o
->flags
, o
->features
))
4905 as_bad (_("selected processor does not support system register "
4907 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4908 as_warn (_("system register name '%s' is deprecated and may be "
4909 "removed in a future release"), buf
);
4919 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4920 for the option, or NULL. */
4922 static const aarch64_sys_ins_reg
*
4923 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4926 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4927 const aarch64_sys_ins_reg
*o
;
4930 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4931 if (p
< buf
+ (sizeof (buf
) - 1))
4932 *p
++ = TOLOWER (*q
);
4935 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4936 valid system register. This is enforced by construction of the hash
4938 if (p
- buf
!= q
- *str
)
4941 o
= str_hash_find (sys_ins_regs
, buf
);
4945 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4946 o
->name
, o
->value
, o
->flags
, 0))
4947 as_bad (_("selected processor does not support system register "
4949 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4950 as_warn (_("system register name '%s' is deprecated and may be "
4951 "removed in a future release"), buf
);
4957 #define po_char_or_fail(chr) do { \
4958 if (! skip_past_char (&str, chr)) \
4962 #define po_reg_or_fail(regtype) do { \
4963 reg = aarch64_reg_parse (&str, regtype, NULL); \
4968 #define po_int_fp_reg_or_fail(reg_type) do { \
4969 reg = parse_reg (&str); \
4970 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4972 set_expected_reg_error (reg_type, reg, 0); \
4975 info->reg.regno = reg->number; \
4976 info->qualifier = inherent_reg_qualifier (reg); \
4979 #define po_imm_nc_or_fail() do { \
4980 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4984 #define po_imm_or_fail(min, max) do { \
4985 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4987 if (val < min || val > max) \
4989 set_fatal_syntax_error (_("immediate value out of range "\
4990 #min " to "#max)); \
4995 #define po_enum_or_fail(array) do { \
4996 if (!parse_enum_string (&str, &val, array, \
4997 ARRAY_SIZE (array), imm_reg_type)) \
5001 #define po_strict_enum_or_fail(array) do { \
5002 if (!parse_enum_string (&str, &val, array, \
5003 ARRAY_SIZE (array), REG_TYPE_MAX)) \
5007 #define po_misc_or_fail(expr) do { \
5012 /* A primitive log calculator. */
5014 static inline unsigned int
5015 get_log2 (unsigned int n
)
5017 unsigned int count
= 0;
5026 /* encode the 12-bit imm field of Add/sub immediate */
5027 static inline uint32_t
5028 encode_addsub_imm (uint32_t imm
)
5033 /* encode the shift amount field of Add/sub immediate */
5034 static inline uint32_t
5035 encode_addsub_imm_shift_amount (uint32_t cnt
)
5041 /* encode the imm field of Adr instruction */
5042 static inline uint32_t
5043 encode_adr_imm (uint32_t imm
)
5045 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
5046 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
5049 /* encode the immediate field of Move wide immediate */
5050 static inline uint32_t
5051 encode_movw_imm (uint32_t imm
)
5056 /* encode the 26-bit offset of unconditional branch */
5057 static inline uint32_t
5058 encode_branch_ofs_26 (uint32_t ofs
)
5060 return ofs
& ((1 << 26) - 1);
5063 /* encode the 19-bit offset of conditional branch and compare & branch */
5064 static inline uint32_t
5065 encode_cond_branch_ofs_19 (uint32_t ofs
)
5067 return (ofs
& ((1 << 19) - 1)) << 5;
5070 /* encode the 19-bit offset of ld literal */
5071 static inline uint32_t
5072 encode_ld_lit_ofs_19 (uint32_t ofs
)
5074 return (ofs
& ((1 << 19) - 1)) << 5;
5077 /* Encode the 14-bit offset of test & branch. */
5078 static inline uint32_t
5079 encode_tst_branch_ofs_14 (uint32_t ofs
)
5081 return (ofs
& ((1 << 14) - 1)) << 5;
5084 /* Encode the 16-bit imm field of svc/hvc/smc. */
5085 static inline uint32_t
5086 encode_svc_imm (uint32_t imm
)
5091 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5092 static inline uint32_t
5093 reencode_addsub_switch_add_sub (uint32_t opcode
)
5095 return opcode
^ (1 << 30);
5098 static inline uint32_t
5099 reencode_movzn_to_movz (uint32_t opcode
)
5101 return opcode
| (1 << 30);
5104 static inline uint32_t
5105 reencode_movzn_to_movn (uint32_t opcode
)
5107 return opcode
& ~(1 << 30);
5110 /* Overall per-instruction processing. */
5112 /* We need to be able to fix up arbitrary expressions in some statements.
5113 This is so that we can handle symbols that are an arbitrary distance from
5114 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5115 which returns part of an address in a form which will be valid for
5116 a data instruction. We do this by pushing the expression into a symbol
5117 in the expr_section, and creating a fix for that. */
5120 fix_new_aarch64 (fragS
* frag
,
5135 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5139 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5146 /* Diagnostics on operands errors. */
5148 /* By default, output verbose error message.
5149 Disable the verbose error message by -mno-verbose-error. */
5150 static int verbose_error_p
= 1;
5152 #ifdef DEBUG_AARCH64
5153 /* N.B. this is only for the purpose of debugging. */
5154 const char* operand_mismatch_kind_names
[] =
5157 "AARCH64_OPDE_RECOVERABLE",
5158 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5159 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5160 "AARCH64_OPDE_SYNTAX_ERROR",
5161 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5162 "AARCH64_OPDE_INVALID_VARIANT",
5163 "AARCH64_OPDE_INVALID_VG_SIZE",
5164 "AARCH64_OPDE_REG_LIST_LENGTH",
5165 "AARCH64_OPDE_REG_LIST_STRIDE",
5166 "AARCH64_OPDE_UNTIED_IMMS",
5167 "AARCH64_OPDE_UNTIED_OPERAND",
5168 "AARCH64_OPDE_OUT_OF_RANGE",
5169 "AARCH64_OPDE_UNALIGNED",
5170 "AARCH64_OPDE_OTHER_ERROR",
5171 "AARCH64_OPDE_INVALID_REGNO",
5173 #endif /* DEBUG_AARCH64 */
5175 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5177 When multiple errors of different kinds are found in the same assembly
5178 line, only the error of the highest severity will be picked up for
5179 issuing the diagnostics. */
5182 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5183 enum aarch64_operand_error_kind rhs
)
5185 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5186 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5187 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5188 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5189 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5190 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5191 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5192 gas_assert (AARCH64_OPDE_INVALID_VG_SIZE
> AARCH64_OPDE_INVALID_VARIANT
);
5193 gas_assert (AARCH64_OPDE_REG_LIST_LENGTH
> AARCH64_OPDE_INVALID_VG_SIZE
);
5194 gas_assert (AARCH64_OPDE_REG_LIST_STRIDE
> AARCH64_OPDE_REG_LIST_LENGTH
);
5195 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_REG_LIST_STRIDE
);
5196 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5197 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST_STRIDE
);
5198 gas_assert (AARCH64_OPDE_INVALID_REGNO
> AARCH64_OPDE_OTHER_ERROR
);
5202 /* Helper routine to get the mnemonic name from the assembly instruction
5203 line; should only be called for the diagnosis purpose, as there is
5204 string copy operation involved, which may affect the runtime
5205 performance if used in elsewhere. */
5208 get_mnemonic_name (const char *str
)
5210 static char mnemonic
[32];
5213 /* Get the first 15 bytes and assume that the full name is included. */
5214 strncpy (mnemonic
, str
, 31);
5215 mnemonic
[31] = '\0';
5217 /* Scan up to the end of the mnemonic, which must end in white space,
5218 '.', or end of string. */
5219 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5224 /* Append '...' to the truncated long name. */
5225 if (ptr
- mnemonic
== 31)
5226 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5232 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5234 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5235 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5238 /* Data structures storing one user error in the assembly code related to
5241 struct operand_error_record
5243 const aarch64_opcode
*opcode
;
5244 aarch64_operand_error detail
;
5245 struct operand_error_record
*next
;
5248 typedef struct operand_error_record operand_error_record
;
5250 struct operand_errors
5252 operand_error_record
*head
;
5253 operand_error_record
*tail
;
5256 typedef struct operand_errors operand_errors
;
5258 /* Top-level data structure reporting user errors for the current line of
5260 The way md_assemble works is that all opcodes sharing the same mnemonic
5261 name are iterated to find a match to the assembly line. In this data
5262 structure, each of the such opcodes will have one operand_error_record
5263 allocated and inserted. In other words, excessive errors related with
5264 a single opcode are disregarded. */
5265 operand_errors operand_error_report
;
5267 /* Free record nodes. */
5268 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5270 /* Initialize the data structure that stores the operand mismatch
5271 information on assembling one line of the assembly code. */
5273 init_operand_error_report (void)
5275 if (operand_error_report
.head
!= NULL
)
5277 gas_assert (operand_error_report
.tail
!= NULL
);
5278 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5279 free_opnd_error_record_nodes
= operand_error_report
.head
;
5280 operand_error_report
.head
= NULL
;
5281 operand_error_report
.tail
= NULL
;
5284 gas_assert (operand_error_report
.tail
== NULL
);
5287 /* Return TRUE if some operand error has been recorded during the
5288 parsing of the current assembly line using the opcode *OPCODE;
5289 otherwise return FALSE. */
5291 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5293 operand_error_record
*record
= operand_error_report
.head
;
5294 return record
&& record
->opcode
== opcode
;
5297 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5298 OPCODE field is initialized with OPCODE.
5299 N.B. only one record for each opcode, i.e. the maximum of one error is
5300 recorded for each instruction template. */
5303 add_operand_error_record (const operand_error_record
* new_record
)
5305 const aarch64_opcode
*opcode
= new_record
->opcode
;
5306 operand_error_record
* record
= operand_error_report
.head
;
5308 /* The record may have been created for this opcode. If not, we need
5310 if (! opcode_has_operand_error_p (opcode
))
5312 /* Get one empty record. */
5313 if (free_opnd_error_record_nodes
== NULL
)
5315 record
= XNEW (operand_error_record
);
5319 record
= free_opnd_error_record_nodes
;
5320 free_opnd_error_record_nodes
= record
->next
;
5322 record
->opcode
= opcode
;
5323 /* Insert at the head. */
5324 record
->next
= operand_error_report
.head
;
5325 operand_error_report
.head
= record
;
5326 if (operand_error_report
.tail
== NULL
)
5327 operand_error_report
.tail
= record
;
5329 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5330 && record
->detail
.index
<= new_record
->detail
.index
5331 && operand_error_higher_severity_p (record
->detail
.kind
,
5332 new_record
->detail
.kind
))
5334 /* In the case of multiple errors found on operands related with a
5335 single opcode, only record the error of the leftmost operand and
5336 only if the error is of higher severity. */
5337 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5338 " the existing error %s on operand %d",
5339 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5340 new_record
->detail
.index
,
5341 operand_mismatch_kind_names
[record
->detail
.kind
],
5342 record
->detail
.index
);
5346 record
->detail
= new_record
->detail
;
5350 record_operand_error_info (const aarch64_opcode
*opcode
,
5351 aarch64_operand_error
*error_info
)
5353 operand_error_record record
;
5354 record
.opcode
= opcode
;
5355 record
.detail
= *error_info
;
5356 add_operand_error_record (&record
);
5359 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5360 error message *ERROR, for operand IDX (count from 0). */
5363 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5364 enum aarch64_operand_error_kind kind
,
5367 aarch64_operand_error info
;
5368 memset(&info
, 0, sizeof (info
));
5372 info
.non_fatal
= false;
5373 record_operand_error_info (opcode
, &info
);
5377 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5378 enum aarch64_operand_error_kind kind
,
5379 const char* error
, const int *extra_data
)
5381 aarch64_operand_error info
;
5385 info
.data
[0].i
= extra_data
[0];
5386 info
.data
[1].i
= extra_data
[1];
5387 info
.data
[2].i
= extra_data
[2];
5388 info
.non_fatal
= false;
5389 record_operand_error_info (opcode
, &info
);
5393 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5394 const char* error
, int lower_bound
,
5397 int data
[3] = {lower_bound
, upper_bound
, 0};
5398 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5402 /* Remove the operand error record for *OPCODE. */
5403 static void ATTRIBUTE_UNUSED
5404 remove_operand_error_record (const aarch64_opcode
*opcode
)
5406 if (opcode_has_operand_error_p (opcode
))
5408 operand_error_record
* record
= operand_error_report
.head
;
5409 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5410 operand_error_report
.head
= record
->next
;
5411 record
->next
= free_opnd_error_record_nodes
;
5412 free_opnd_error_record_nodes
= record
;
5413 if (operand_error_report
.head
== NULL
)
5415 gas_assert (operand_error_report
.tail
== record
);
5416 operand_error_report
.tail
= NULL
;
5421 /* Given the instruction in *INSTR, return the index of the best matched
5422 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5424 Return -1 if there is no qualifier sequence; return the first match
5425 if there is multiple matches found. */
5428 find_best_match (const aarch64_inst
*instr
,
5429 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5431 int i
, num_opnds
, max_num_matched
, idx
;
5433 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5436 DEBUG_TRACE ("no operand");
5440 max_num_matched
= 0;
5443 /* For each pattern. */
5444 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5447 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5449 /* Most opcodes has much fewer patterns in the list. */
5450 if (empty_qualifier_sequence_p (qualifiers
))
5452 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5456 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5457 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5460 if (num_matched
> max_num_matched
)
5462 max_num_matched
= num_matched
;
5467 DEBUG_TRACE ("return with %d", idx
);
5471 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5472 corresponding operands in *INSTR. */
5475 assign_qualifier_sequence (aarch64_inst
*instr
,
5476 const aarch64_opnd_qualifier_t
*qualifiers
)
5479 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5480 gas_assert (num_opnds
);
5481 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5482 instr
->operands
[i
].qualifier
= *qualifiers
;
5485 /* Callback used by aarch64_print_operand to apply STYLE to the
5486 disassembler output created from FMT and ARGS. The STYLER object holds
5487 any required state. Must return a pointer to a string (created from FMT
5488 and ARGS) that will continue to be valid until the complete disassembled
5489 instruction has been printed.
5491 We don't currently add any styling to the output of the disassembler as
5492 used within assembler error messages, and so STYLE is ignored here. A
5493 new string is allocated on the obstack help within STYLER and returned
5496 static const char *aarch64_apply_style
5497 (struct aarch64_styler
*styler
,
5498 enum disassembler_style style ATTRIBUTE_UNUSED
,
5499 const char *fmt
, va_list args
)
5503 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5506 /* Calculate the required space. */
5508 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5510 gas_assert (res
>= 0);
5512 /* Allocate space on the obstack and format the result. */
5513 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5514 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5515 gas_assert (res
>= 0);
5520 /* Print operands for the diagnosis purpose. */
5523 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5524 const aarch64_opnd_info
*opnds
)
5527 struct aarch64_styler styler
;
5528 struct obstack content
;
5529 obstack_init (&content
);
5531 styler
.apply_style
= aarch64_apply_style
;
5532 styler
.state
= (void *) &content
;
5534 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5539 /* We regard the opcode operand info more, however we also look into
5540 the inst->operands to support the disassembling of the optional
5542 The two operand code should be the same in all cases, apart from
5543 when the operand can be optional. */
5544 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5545 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5548 /* Generate the operand string in STR. */
5549 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5550 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5554 strcat (buf
, i
== 0 ? " " : ", ");
5556 /* Append the operand string. */
5559 /* Append a comment. This works because only the last operand ever
5560 adds a comment. If that ever changes then we'll need to be
5564 strcat (buf
, "\t// ");
5569 obstack_free (&content
, NULL
);
5572 /* Send to stderr a string as information. */
5575 output_info (const char *format
, ...)
5581 file
= as_where (&line
);
5585 fprintf (stderr
, "%s:%u: ", file
, line
);
5587 fprintf (stderr
, "%s: ", file
);
5589 fprintf (stderr
, _("Info: "));
5590 va_start (args
, format
);
5591 vfprintf (stderr
, format
, args
);
5593 (void) putc ('\n', stderr
);
5596 /* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
5597 relates to registers or register lists. If so, return a string that
5598 reports the error against "operand %d", otherwise return null. */
5601 get_reg_error_message (const aarch64_operand_error
*detail
)
5603 /* Handle the case where we found a register that was expected
5604 to be in a register list outside of a register list. */
5605 if ((detail
->data
[1].i
& detail
->data
[2].i
) != 0
5606 && (detail
->data
[1].i
& SEF_IN_REGLIST
) == 0)
5607 return _("missing braces at operand %d");
5609 /* If some opcodes expected a register, and we found a register,
5610 complain about the difference. */
5611 if (detail
->data
[2].i
)
5613 unsigned int expected
= (detail
->data
[1].i
& SEF_IN_REGLIST
5614 ? detail
->data
[1].i
& ~SEF_IN_REGLIST
5615 : detail
->data
[0].i
& ~SEF_DEFAULT_ERROR
);
5616 const char *msg
= get_reg_expected_msg (expected
, detail
->data
[2].i
);
5618 msg
= N_("unexpected register type at operand %d");
5622 /* Handle the case where we got to the point of trying to parse a
5623 register within a register list, but didn't find a known register. */
5624 if (detail
->data
[1].i
& SEF_IN_REGLIST
)
5626 unsigned int expected
= detail
->data
[1].i
& ~SEF_IN_REGLIST
;
5627 const char *msg
= get_reg_expected_msg (expected
, 0);
5629 msg
= _("invalid register list at operand %d");
5633 /* Punt if register-related problems weren't the only errors. */
5634 if (detail
->data
[0].i
& SEF_DEFAULT_ERROR
)
5637 /* Handle the case where the only acceptable things are registers. */
5638 if (detail
->data
[1].i
== 0)
5640 const char *msg
= get_reg_expected_msg (detail
->data
[0].i
, 0);
5642 msg
= _("expected a register at operand %d");
5646 /* Handle the case where the only acceptable things are register lists,
5647 and there was no opening '{'. */
5648 if (detail
->data
[0].i
== 0)
5649 return _("expected '{' at operand %d");
5651 return _("expected a register or register list at operand %d");
5654 /* Output one operand error record. */
5657 output_operand_error_record (const operand_error_record
*record
, char *str
)
5659 const aarch64_operand_error
*detail
= &record
->detail
;
5660 int idx
= detail
->index
;
5661 const aarch64_opcode
*opcode
= record
->opcode
;
5662 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5663 : AARCH64_OPND_NIL
);
5665 typedef void (*handler_t
)(const char *format
, ...);
5666 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5667 const char *msg
= detail
->error
;
5669 switch (detail
->kind
)
5671 case AARCH64_OPDE_NIL
:
5675 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5676 handler (_("this `%s' should have an immediately preceding `%s'"
5678 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5681 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5682 handler (_("the preceding `%s' should be followed by `%s` rather"
5683 " than `%s` -- `%s'"),
5684 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5687 case AARCH64_OPDE_SYNTAX_ERROR
:
5688 if (!msg
&& idx
>= 0)
5690 msg
= get_reg_error_message (detail
);
5693 char *full_msg
= xasprintf (msg
, idx
+ 1);
5694 handler (_("%s -- `%s'"), full_msg
, str
);
5701 case AARCH64_OPDE_RECOVERABLE
:
5702 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5703 case AARCH64_OPDE_OTHER_ERROR
:
5704 /* Use the prepared error message if there is, otherwise use the
5705 operand description string to describe the error. */
5709 handler (_("%s -- `%s'"), msg
, str
);
5711 handler (_("%s at operand %d -- `%s'"),
5716 gas_assert (idx
>= 0);
5717 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5718 aarch64_get_operand_desc (opd_code
), str
);
5722 case AARCH64_OPDE_INVALID_VARIANT
:
5723 handler (_("operand mismatch -- `%s'"), str
);
5724 if (verbose_error_p
)
5726 /* We will try to correct the erroneous instruction and also provide
5727 more information e.g. all other valid variants.
5729 The string representation of the corrected instruction and other
5730 valid variants are generated by
5732 1) obtaining the intermediate representation of the erroneous
5734 2) manipulating the IR, e.g. replacing the operand qualifier;
5735 3) printing out the instruction by calling the printer functions
5736 shared with the disassembler.
5738 The limitation of this method is that the exact input assembly
5739 line cannot be accurately reproduced in some cases, for example an
5740 optional operand present in the actual assembly line will be
5741 omitted in the output; likewise for the optional syntax rules,
5742 e.g. the # before the immediate. Another limitation is that the
5743 assembly symbols and relocation operations in the assembly line
5744 currently cannot be printed out in the error report. Last but not
5745 least, when there is other error(s) co-exist with this error, the
5746 'corrected' instruction may be still incorrect, e.g. given
5747 'ldnp h0,h1,[x0,#6]!'
5748 this diagnosis will provide the version:
5749 'ldnp s0,s1,[x0,#6]!'
5750 which is still not right. */
5751 size_t len
= strlen (get_mnemonic_name (str
));
5755 aarch64_inst
*inst_base
= &inst
.base
;
5756 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5759 reset_aarch64_instruction (&inst
);
5760 inst_base
->opcode
= opcode
;
5762 /* Reset the error report so that there is no side effect on the
5763 following operand parsing. */
5764 init_operand_error_report ();
5767 result
= parse_operands (str
+ len
, opcode
)
5768 && programmer_friendly_fixup (&inst
);
5769 gas_assert (result
);
5770 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5771 NULL
, NULL
, insn_sequence
);
5772 gas_assert (!result
);
5774 /* Find the most matched qualifier sequence. */
5775 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5776 gas_assert (qlf_idx
> -1);
5778 /* Assign the qualifiers. */
5779 assign_qualifier_sequence (inst_base
,
5780 opcode
->qualifiers_list
[qlf_idx
]);
5782 /* Print the hint. */
5783 output_info (_(" did you mean this?"));
5784 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5785 print_operands (buf
, opcode
, inst_base
->operands
);
5786 output_info (_(" %s"), buf
);
5788 /* Print out other variant(s) if there is any. */
5790 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5791 output_info (_(" other valid variant(s):"));
5793 /* For each pattern. */
5794 qualifiers_list
= opcode
->qualifiers_list
;
5795 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5797 /* Most opcodes has much fewer patterns in the list.
5798 First NIL qualifier indicates the end in the list. */
5799 if (empty_qualifier_sequence_p (*qualifiers_list
))
5804 /* Mnemonics name. */
5805 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5807 /* Assign the qualifiers. */
5808 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5810 /* Print instruction. */
5811 print_operands (buf
, opcode
, inst_base
->operands
);
5813 output_info (_(" %s"), buf
);
5819 case AARCH64_OPDE_UNTIED_IMMS
:
5820 handler (_("operand %d must have the same immediate value "
5821 "as operand 1 -- `%s'"),
5822 detail
->index
+ 1, str
);
5825 case AARCH64_OPDE_UNTIED_OPERAND
:
5826 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5827 detail
->index
+ 1, str
);
5830 case AARCH64_OPDE_INVALID_REGNO
:
5831 handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
5832 detail
->data
[0].s
, detail
->data
[1].i
,
5833 detail
->data
[0].s
, detail
->data
[2].i
, idx
+ 1, str
);
5836 case AARCH64_OPDE_OUT_OF_RANGE
:
5837 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5838 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5839 msg
? msg
: _("immediate value"),
5840 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5842 handler (_("%s must be %d at operand %d -- `%s'"),
5843 msg
? msg
: _("immediate value"),
5844 detail
->data
[0].i
, idx
+ 1, str
);
5847 case AARCH64_OPDE_INVALID_VG_SIZE
:
5848 if (detail
->data
[0].i
== 0)
5849 handler (_("unexpected vector group size at operand %d -- `%s'"),
5852 handler (_("operand %d must have a vector group size of %d -- `%s'"),
5853 idx
+ 1, detail
->data
[0].i
, str
);
5856 case AARCH64_OPDE_REG_LIST_LENGTH
:
5857 if (detail
->data
[0].i
== (1 << 1))
5858 handler (_("expected a single-register list at operand %d -- `%s'"),
5860 else if ((detail
->data
[0].i
& -detail
->data
[0].i
) == detail
->data
[0].i
)
5861 handler (_("expected a list of %d registers at operand %d -- `%s'"),
5862 get_log2 (detail
->data
[0].i
), idx
+ 1, str
);
5863 else if (detail
->data
[0].i
== 0x14)
5864 handler (_("expected a list of %d or %d registers at"
5865 " operand %d -- `%s'"),
5866 2, 4, idx
+ 1, str
);
5868 handler (_("invalid number of registers in the list"
5869 " at operand %d -- `%s'"), idx
+ 1, str
);
5872 case AARCH64_OPDE_REG_LIST_STRIDE
:
5873 if (detail
->data
[0].i
== (1 << 1))
5874 handler (_("the register list must have a stride of %d"
5875 " at operand %d -- `%s'"), 1, idx
+ 1, str
);
5876 else if (detail
->data
[0].i
== 0x12 || detail
->data
[0].i
== 0x102)
5877 handler (_("the register list must have a stride of %d or %d"
5878 " at operand %d -- `%s`"), 1,
5879 detail
->data
[0].i
== 0x12 ? 4 : 8, idx
+ 1, str
);
5881 handler (_("invalid register stride at operand %d -- `%s'"),
5885 case AARCH64_OPDE_UNALIGNED
:
5886 handler (_("immediate value must be a multiple of "
5887 "%d at operand %d -- `%s'"),
5888 detail
->data
[0].i
, idx
+ 1, str
);
5897 /* Return true if the presence of error A against an instruction means
5898 that error B should not be reported. This is only used as a first pass,
5899 to pick the kind of error that we should report. */
5902 better_error_p (operand_error_record
*a
, operand_error_record
*b
)
5904 /* For errors reported during parsing, prefer errors that relate to
5905 later operands, since that implies that the earlier operands were
5906 syntactically valid.
5908 For example, if we see a register R instead of an immediate in
5909 operand N, we'll report that as a recoverable "immediate operand
5910 required" error. This is because there is often another opcode
5911 entry that accepts a register operand N, and any errors about R
5912 should be reported against the register forms of the instruction.
5913 But if no such register form exists, the recoverable error should
5914 still win over a syntax error against operand N-1.
5916 For these purposes, count an error reported at the end of the
5917 assembly string as equivalent to an error reported against the
5918 final operand. This means that opcode entries that expect more
5919 operands win over "unexpected characters following instruction". */
5920 if (a
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
5921 && b
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
)
5923 int a_index
= (a
->detail
.index
< 0
5924 ? aarch64_num_of_operands (a
->opcode
) - 1
5926 int b_index
= (b
->detail
.index
< 0
5927 ? aarch64_num_of_operands (b
->opcode
) - 1
5929 if (a_index
!= b_index
)
5930 return a_index
> b_index
;
5932 return operand_error_higher_severity_p (a
->detail
.kind
, b
->detail
.kind
);
5935 /* Process and output the error message about the operand mismatching.
5937 When this function is called, the operand error information had
5938 been collected for an assembly line and there will be multiple
5939 errors in the case of multiple instruction templates; output the
5940 error message that most closely describes the problem.
5942 The errors to be printed can be filtered on printing all errors
5943 or only non-fatal errors. This distinction has to be made because
5944 the error buffer may already be filled with fatal errors we don't want to
5945 print due to the different instruction templates. */
5948 output_operand_error_report (char *str
, bool non_fatal_only
)
5950 enum aarch64_operand_error_kind kind
;
5951 operand_error_record
*curr
;
5952 operand_error_record
*head
= operand_error_report
.head
;
5953 operand_error_record
*record
;
5955 /* No error to report. */
5959 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5961 /* Only one error. */
5962 if (head
== operand_error_report
.tail
)
5964 /* If the only error is a non-fatal one and we don't want to print it,
5966 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5968 DEBUG_TRACE ("single opcode entry with error kind: %s",
5969 operand_mismatch_kind_names
[head
->detail
.kind
]);
5970 output_operand_error_record (head
, str
);
5975 /* Find the error kind of the highest severity. */
5976 DEBUG_TRACE ("multiple opcode entries with error kind");
5978 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5980 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5981 if (curr
->detail
.kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5983 DEBUG_TRACE ("\t%s [%x, %x, %x]",
5984 operand_mismatch_kind_names
[curr
->detail
.kind
],
5985 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5986 curr
->detail
.data
[2].i
);
5988 else if (curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_LENGTH
5989 || curr
->detail
.kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
5991 DEBUG_TRACE ("\t%s [%x]",
5992 operand_mismatch_kind_names
[curr
->detail
.kind
],
5993 curr
->detail
.data
[0].i
);
5997 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5999 if ((!non_fatal_only
|| curr
->detail
.non_fatal
)
6000 && (!record
|| better_error_p (curr
, record
)))
6004 kind
= (record
? record
->detail
.kind
: AARCH64_OPDE_NIL
);
6005 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
6007 /* Pick up one of errors of KIND to report. */
6009 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
6011 /* If we don't want to print non-fatal errors then don't consider them
6013 if (curr
->detail
.kind
!= kind
6014 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
6016 /* If there are multiple errors, pick up the one with the highest
6017 mismatching operand index. In the case of multiple errors with
6018 the equally highest operand index, pick up the first one or the
6019 first one with non-NULL error message. */
6020 if (!record
|| curr
->detail
.index
> record
->detail
.index
)
6022 else if (curr
->detail
.index
== record
->detail
.index
6023 && !record
->detail
.error
)
6025 if (curr
->detail
.error
)
6027 else if (kind
== AARCH64_OPDE_SYNTAX_ERROR
)
6029 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6030 record
->detail
.data
[1].i
|= curr
->detail
.data
[1].i
;
6031 record
->detail
.data
[2].i
|= curr
->detail
.data
[2].i
;
6032 DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
6033 operand_mismatch_kind_names
[kind
],
6034 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
6035 curr
->detail
.data
[2].i
);
6037 else if (kind
== AARCH64_OPDE_REG_LIST_LENGTH
6038 || kind
== AARCH64_OPDE_REG_LIST_STRIDE
)
6040 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
6041 DEBUG_TRACE ("\t--> %s [%x]",
6042 operand_mismatch_kind_names
[kind
],
6043 curr
->detail
.data
[0].i
);
6045 /* Pick the variant with the cloest match. */
6046 else if (kind
== AARCH64_OPDE_INVALID_VARIANT
6047 && record
->detail
.data
[0].i
> curr
->detail
.data
[0].i
)
6052 /* The way errors are collected in the back-end is a bit non-intuitive. But
6053 essentially, because each operand template is tried recursively you may
6054 always have errors collected from the previous tried OPND. These are
6055 usually skipped if there is one successful match. However now with the
6056 non-fatal errors we have to ignore those previously collected hard errors
6057 when we're only interested in printing the non-fatal ones. This condition
6058 prevents us from printing errors that are not appropriate, since we did
6059 match a condition, but it also has warnings that it wants to print. */
6060 if (non_fatal_only
&& !record
)
6063 gas_assert (record
);
6064 DEBUG_TRACE ("Pick up error kind %s to report",
6065 operand_mismatch_kind_names
[kind
]);
6068 output_operand_error_record (record
, str
);
6071 /* Write an AARCH64 instruction to buf - always little-endian. */
6073 put_aarch64_insn (char *buf
, uint32_t insn
)
6075 unsigned char *where
= (unsigned char *) buf
;
6077 where
[1] = insn
>> 8;
6078 where
[2] = insn
>> 16;
6079 where
[3] = insn
>> 24;
6083 get_aarch64_insn (char *buf
)
6085 unsigned char *where
= (unsigned char *) buf
;
6087 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
6088 | ((uint32_t) where
[3] << 24)));
6093 output_inst (struct aarch64_inst
*new_inst
)
6097 to
= frag_more (INSN_SIZE
);
6099 frag_now
->tc_frag_data
.recorded
= 1;
6101 put_aarch64_insn (to
, inst
.base
.value
);
6103 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6105 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
6106 INSN_SIZE
, &inst
.reloc
.exp
,
6109 DEBUG_TRACE ("Prepared relocation fix up");
6110 /* Don't check the addend value against the instruction size,
6111 that's the job of our code in md_apply_fix(). */
6112 fixp
->fx_no_overflow
= 1;
6113 if (new_inst
!= NULL
)
6114 fixp
->tc_fix_data
.inst
= new_inst
;
6115 if (aarch64_gas_internal_fixup_p ())
6117 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
6118 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
6119 fixp
->fx_addnumber
= inst
.reloc
.flags
;
6123 dwarf2_emit_insn (INSN_SIZE
);
6126 /* Link together opcodes of the same name. */
6130 const aarch64_opcode
*opcode
;
6131 struct templates
*next
;
6134 typedef struct templates templates
;
6137 lookup_mnemonic (const char *start
, int len
)
6139 templates
*templ
= NULL
;
6141 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
6145 /* Subroutine of md_assemble, responsible for looking up the primary
6146 opcode from the mnemonic the user wrote. BASE points to the beginning
6147 of the mnemonic, DOT points to the first '.' within the mnemonic
6148 (if any) and END points to the end of the mnemonic. */
6151 opcode_lookup (char *base
, char *dot
, char *end
)
6153 const aarch64_cond
*cond
;
6160 inst
.cond
= COND_ALWAYS
;
6162 /* Handle a possible condition. */
6165 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
6168 inst
.cond
= cond
->value
;
6174 if (inst
.cond
== COND_ALWAYS
)
6176 /* Look for unaffixed mnemonic. */
6177 return lookup_mnemonic (base
, len
);
6181 /* append ".c" to mnemonic if conditional */
6182 memcpy (condname
, base
, len
);
6183 memcpy (condname
+ len
, ".c", 2);
6186 return lookup_mnemonic (base
, len
);
6192 /* Process an optional operand that is found omitted from the assembly line.
6193 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
6194 instruction's opcode entry while IDX is the index of this omitted operand.
6198 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6199 int idx
, aarch64_opnd_info
*operand
)
6201 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6202 gas_assert (optional_operand_p (opcode
, idx
));
6203 gas_assert (!operand
->present
);
6207 case AARCH64_OPND_Rd
:
6208 case AARCH64_OPND_Rn
:
6209 case AARCH64_OPND_Rm
:
6210 case AARCH64_OPND_Rt
:
6211 case AARCH64_OPND_Rt2
:
6212 case AARCH64_OPND_Rt_LS64
:
6213 case AARCH64_OPND_Rt_SP
:
6214 case AARCH64_OPND_Rs
:
6215 case AARCH64_OPND_Ra
:
6216 case AARCH64_OPND_Rt_SYS
:
6217 case AARCH64_OPND_Rd_SP
:
6218 case AARCH64_OPND_Rn_SP
:
6219 case AARCH64_OPND_Rm_SP
:
6220 case AARCH64_OPND_Fd
:
6221 case AARCH64_OPND_Fn
:
6222 case AARCH64_OPND_Fm
:
6223 case AARCH64_OPND_Fa
:
6224 case AARCH64_OPND_Ft
:
6225 case AARCH64_OPND_Ft2
:
6226 case AARCH64_OPND_Sd
:
6227 case AARCH64_OPND_Sn
:
6228 case AARCH64_OPND_Sm
:
6229 case AARCH64_OPND_Va
:
6230 case AARCH64_OPND_Vd
:
6231 case AARCH64_OPND_Vn
:
6232 case AARCH64_OPND_Vm
:
6233 case AARCH64_OPND_VdD1
:
6234 case AARCH64_OPND_VnD1
:
6235 operand
->reg
.regno
= default_value
;
6238 case AARCH64_OPND_Ed
:
6239 case AARCH64_OPND_En
:
6240 case AARCH64_OPND_Em
:
6241 case AARCH64_OPND_Em16
:
6242 case AARCH64_OPND_SM3_IMM2
:
6243 operand
->reglane
.regno
= default_value
;
6246 case AARCH64_OPND_IDX
:
6247 case AARCH64_OPND_BIT_NUM
:
6248 case AARCH64_OPND_IMMR
:
6249 case AARCH64_OPND_IMMS
:
6250 case AARCH64_OPND_SHLL_IMM
:
6251 case AARCH64_OPND_IMM_VLSL
:
6252 case AARCH64_OPND_IMM_VLSR
:
6253 case AARCH64_OPND_CCMP_IMM
:
6254 case AARCH64_OPND_FBITS
:
6255 case AARCH64_OPND_UIMM4
:
6256 case AARCH64_OPND_UIMM3_OP1
:
6257 case AARCH64_OPND_UIMM3_OP2
:
6258 case AARCH64_OPND_IMM
:
6259 case AARCH64_OPND_IMM_2
:
6260 case AARCH64_OPND_WIDTH
:
6261 case AARCH64_OPND_UIMM7
:
6262 case AARCH64_OPND_NZCV
:
6263 case AARCH64_OPND_SVE_PATTERN
:
6264 case AARCH64_OPND_SVE_PRFOP
:
6265 operand
->imm
.value
= default_value
;
6268 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6269 operand
->imm
.value
= default_value
;
6270 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6271 operand
->shifter
.amount
= 1;
6274 case AARCH64_OPND_EXCEPTION
:
6275 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6278 case AARCH64_OPND_BARRIER_ISB
:
6279 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6282 case AARCH64_OPND_BTI_TARGET
:
6283 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6291 /* Process the relocation type for move wide instructions.
6292 Return TRUE on success; otherwise return FALSE. */
6295 process_movw_reloc_info (void)
6300 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6302 if (inst
.base
.opcode
->op
== OP_MOVK
)
6303 switch (inst
.reloc
.type
)
6305 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6306 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6307 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6308 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6309 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6310 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6311 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6312 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6313 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6314 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6315 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6317 (_("the specified relocation type is not allowed for MOVK"));
6323 switch (inst
.reloc
.type
)
6325 case BFD_RELOC_AARCH64_MOVW_G0
:
6326 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6327 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6328 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6329 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6330 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6331 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6332 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6333 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6334 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6335 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6336 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6337 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6340 case BFD_RELOC_AARCH64_MOVW_G1
:
6341 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6342 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6343 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6344 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6345 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6346 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6347 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6348 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6349 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6350 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6351 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6352 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6355 case BFD_RELOC_AARCH64_MOVW_G2
:
6356 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6357 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6358 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6359 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6360 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6361 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6364 set_fatal_syntax_error
6365 (_("the specified relocation type is not allowed for 32-bit "
6371 case BFD_RELOC_AARCH64_MOVW_G3
:
6372 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6375 set_fatal_syntax_error
6376 (_("the specified relocation type is not allowed for 32-bit "
6383 /* More cases should be added when more MOVW-related relocation types
6384 are supported in GAS. */
6385 gas_assert (aarch64_gas_internal_fixup_p ());
6386 /* The shift amount should have already been set by the parser. */
6389 inst
.base
.operands
[1].shifter
.amount
= shift
;
6393 /* Determine and return the real reloc type code for an instruction
6394 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6396 static inline bfd_reloc_code_real_type
6397 ldst_lo12_determine_real_reloc_type (void)
6399 unsigned logsz
, max_logsz
;
6400 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6401 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6403 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6405 BFD_RELOC_AARCH64_LDST8_LO12
,
6406 BFD_RELOC_AARCH64_LDST16_LO12
,
6407 BFD_RELOC_AARCH64_LDST32_LO12
,
6408 BFD_RELOC_AARCH64_LDST64_LO12
,
6409 BFD_RELOC_AARCH64_LDST128_LO12
6412 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6413 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6414 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6415 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6416 BFD_RELOC_AARCH64_NONE
6419 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6420 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6421 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6422 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6423 BFD_RELOC_AARCH64_NONE
6426 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6427 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6428 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6429 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6430 BFD_RELOC_AARCH64_NONE
6433 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6434 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6435 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6436 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6437 BFD_RELOC_AARCH64_NONE
6441 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6442 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6444 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6446 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6448 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6449 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6451 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6453 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6455 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6457 logsz
= get_log2 (aarch64_get_qualifier_esize (opd1_qlf
));
6459 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6460 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6461 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6462 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6467 if (logsz
> max_logsz
)
6469 /* SEE PR 27904 for an example of this. */
6470 set_fatal_syntax_error
6471 (_("relocation qualifier does not match instruction size"));
6472 return BFD_RELOC_AARCH64_NONE
;
6475 /* In reloc.c, these pseudo relocation types should be defined in similar
6476 order as above reloc_ldst_lo12 array. Because the array index calculation
6477 below relies on this. */
6478 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6481 /* Check whether a register list REGINFO is valid. The registers have type
6482 REG_TYPE and must be numbered in increasing order (modulo the register
6483 bank size). They must have a consistent stride.
6485 Return true if the list is valid, describing it in LIST if so. */
6488 reg_list_valid_p (uint32_t reginfo
, struct aarch64_reglist
*list
,
6489 aarch64_reg_type reg_type
)
6491 uint32_t i
, nb_regs
, prev_regno
, incr
, mask
;
6492 mask
= reg_type_mask (reg_type
);
6494 nb_regs
= 1 + (reginfo
& 0x3);
6496 prev_regno
= reginfo
& 0x1f;
6499 list
->first_regno
= prev_regno
;
6500 list
->num_regs
= nb_regs
;
6502 for (i
= 1; i
< nb_regs
; ++i
)
6504 uint32_t curr_regno
, curr_incr
;
6506 curr_regno
= reginfo
& 0x1f;
6507 curr_incr
= (curr_regno
- prev_regno
) & mask
;
6512 else if (curr_incr
!= incr
)
6514 prev_regno
= curr_regno
;
6517 list
->stride
= incr
;
6521 /* Generic instruction operand parser. This does no encoding and no
6522 semantic validation; it merely squirrels values away in the inst
6523 structure. Returns TRUE or FALSE depending on whether the
6524 specified grammar matched. */
6527 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6530 char *backtrack_pos
= 0;
6531 const enum aarch64_opnd
*operands
= opcode
->operands
;
6532 aarch64_reg_type imm_reg_type
;
6535 skip_whitespace (str
);
6537 if (AARCH64_CPU_HAS_FEATURE (*opcode
->avariant
, AARCH64_FEATURE_SME2
))
6538 imm_reg_type
= REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN
;
6539 else if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6541 | AARCH64_FEATURE_SVE2
))
6542 imm_reg_type
= REG_TYPE_R_ZR_SP_BHSDQ_VZP
;
6544 imm_reg_type
= REG_TYPE_R_ZR_BHSDQ_V
;
6546 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6549 const reg_entry
*reg
;
6550 int comma_skipped_p
= 0;
6551 struct vector_type_el vectype
;
6552 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6553 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6554 aarch64_reg_type reg_type
;
6556 DEBUG_TRACE ("parse operand %d", i
);
6558 /* Assign the operand code. */
6559 info
->type
= operands
[i
];
6561 if (optional_operand_p (opcode
, i
))
6563 /* Remember where we are in case we need to backtrack. */
6564 gas_assert (!backtrack_pos
);
6565 backtrack_pos
= str
;
6568 /* Expect comma between operands; the backtrack mechanism will take
6569 care of cases of omitted optional operand. */
6570 if (i
> 0 && ! skip_past_char (&str
, ','))
6572 set_syntax_error (_("comma expected between operands"));
6576 comma_skipped_p
= 1;
6578 switch (operands
[i
])
6580 case AARCH64_OPND_Rd
:
6581 case AARCH64_OPND_Rn
:
6582 case AARCH64_OPND_Rm
:
6583 case AARCH64_OPND_Rt
:
6584 case AARCH64_OPND_Rt2
:
6585 case AARCH64_OPND_Rs
:
6586 case AARCH64_OPND_Ra
:
6587 case AARCH64_OPND_Rt_LS64
:
6588 case AARCH64_OPND_Rt_SYS
:
6589 case AARCH64_OPND_PAIRREG
:
6590 case AARCH64_OPND_SVE_Rm
:
6591 po_int_fp_reg_or_fail (REG_TYPE_R_ZR
);
6593 /* In LS64 load/store instructions Rt register number must be even
6595 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6597 /* We've already checked if this is valid register.
6598 This will check if register number (Rt) is not undefined for LS64
6600 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6601 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6603 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6609 case AARCH64_OPND_Rd_SP
:
6610 case AARCH64_OPND_Rn_SP
:
6611 case AARCH64_OPND_Rt_SP
:
6612 case AARCH64_OPND_SVE_Rn_SP
:
6613 case AARCH64_OPND_Rm_SP
:
6614 po_int_fp_reg_or_fail (REG_TYPE_R_SP
);
6617 case AARCH64_OPND_Rm_EXT
:
6618 case AARCH64_OPND_Rm_SFT
:
6619 po_misc_or_fail (parse_shifter_operand
6620 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6622 : SHIFTED_LOGIC_IMM
)));
6623 if (!info
->shifter
.operator_present
)
6625 /* Default to LSL if not present. Libopcodes prefers shifter
6626 kind to be explicit. */
6627 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6628 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6629 /* For Rm_EXT, libopcodes will carry out further check on whether
6630 or not stack pointer is used in the instruction (Recall that
6631 "the extend operator is not optional unless at least one of
6632 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6636 case AARCH64_OPND_Fd
:
6637 case AARCH64_OPND_Fn
:
6638 case AARCH64_OPND_Fm
:
6639 case AARCH64_OPND_Fa
:
6640 case AARCH64_OPND_Ft
:
6641 case AARCH64_OPND_Ft2
:
6642 case AARCH64_OPND_Sd
:
6643 case AARCH64_OPND_Sn
:
6644 case AARCH64_OPND_Sm
:
6645 case AARCH64_OPND_SVE_VZn
:
6646 case AARCH64_OPND_SVE_Vd
:
6647 case AARCH64_OPND_SVE_Vm
:
6648 case AARCH64_OPND_SVE_Vn
:
6649 po_int_fp_reg_or_fail (REG_TYPE_BHSDQ
);
6652 case AARCH64_OPND_SVE_Pd
:
6653 case AARCH64_OPND_SVE_Pg3
:
6654 case AARCH64_OPND_SVE_Pg4_5
:
6655 case AARCH64_OPND_SVE_Pg4_10
:
6656 case AARCH64_OPND_SVE_Pg4_16
:
6657 case AARCH64_OPND_SVE_Pm
:
6658 case AARCH64_OPND_SVE_Pn
:
6659 case AARCH64_OPND_SVE_Pt
:
6660 case AARCH64_OPND_SME_Pm
:
6661 reg_type
= REG_TYPE_P
;
6664 case AARCH64_OPND_SVE_Za_5
:
6665 case AARCH64_OPND_SVE_Za_16
:
6666 case AARCH64_OPND_SVE_Zd
:
6667 case AARCH64_OPND_SVE_Zm_5
:
6668 case AARCH64_OPND_SVE_Zm_16
:
6669 case AARCH64_OPND_SVE_Zn
:
6670 case AARCH64_OPND_SVE_Zt
:
6671 case AARCH64_OPND_SME_Zm
:
6672 reg_type
= REG_TYPE_Z
;
6675 case AARCH64_OPND_SVE_PNd
:
6676 case AARCH64_OPND_SVE_PNg4_10
:
6677 case AARCH64_OPND_SVE_PNn
:
6678 case AARCH64_OPND_SVE_PNt
:
6679 case AARCH64_OPND_SME_PNd3
:
6680 case AARCH64_OPND_SME_PNg3
:
6681 case AARCH64_OPND_SME_PNn
:
6682 reg_type
= REG_TYPE_PN
;
6685 case AARCH64_OPND_Va
:
6686 case AARCH64_OPND_Vd
:
6687 case AARCH64_OPND_Vn
:
6688 case AARCH64_OPND_Vm
:
6689 reg_type
= REG_TYPE_V
;
6691 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6694 if (vectype
.defined
& NTA_HASINDEX
)
6697 info
->reg
.regno
= reg
->number
;
6698 if ((reg_type
== REG_TYPE_P
6699 || reg_type
== REG_TYPE_PN
6700 || reg_type
== REG_TYPE_Z
)
6701 && vectype
.type
== NT_invtype
)
6702 /* Unqualified P and Z registers are allowed in certain
6703 contexts. Rely on F_STRICT qualifier checking to catch
6705 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6708 info
->qualifier
= vectype_to_qualifier (&vectype
);
6709 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6714 case AARCH64_OPND_VdD1
:
6715 case AARCH64_OPND_VnD1
:
6716 reg
= aarch64_reg_parse (&str
, REG_TYPE_V
, &vectype
);
6719 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6721 set_fatal_syntax_error
6722 (_("the top half of a 128-bit FP/SIMD register is expected"));
6725 info
->reg
.regno
= reg
->number
;
6726 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6727 here; it is correct for the purpose of encoding/decoding since
6728 only the register number is explicitly encoded in the related
6729 instructions, although this appears a bit hacky. */
6730 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6733 case AARCH64_OPND_SVE_Zm3_INDEX
:
6734 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6735 case AARCH64_OPND_SVE_Zm3_19_INDEX
:
6736 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6737 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6738 case AARCH64_OPND_SVE_Zm4_INDEX
:
6739 case AARCH64_OPND_SVE_Zn_INDEX
:
6740 case AARCH64_OPND_SME_Zm_INDEX1
:
6741 case AARCH64_OPND_SME_Zm_INDEX2
:
6742 case AARCH64_OPND_SME_Zm_INDEX3_1
:
6743 case AARCH64_OPND_SME_Zm_INDEX3_2
:
6744 case AARCH64_OPND_SME_Zm_INDEX3_10
:
6745 case AARCH64_OPND_SME_Zm_INDEX4_1
:
6746 case AARCH64_OPND_SME_Zm_INDEX4_10
:
6747 case AARCH64_OPND_SME_Zn_INDEX1_16
:
6748 case AARCH64_OPND_SME_Zn_INDEX2_15
:
6749 case AARCH64_OPND_SME_Zn_INDEX2_16
:
6750 case AARCH64_OPND_SME_Zn_INDEX3_14
:
6751 case AARCH64_OPND_SME_Zn_INDEX3_15
:
6752 case AARCH64_OPND_SME_Zn_INDEX4_14
:
6753 reg_type
= REG_TYPE_Z
;
6754 goto vector_reg_index
;
6756 case AARCH64_OPND_Ed
:
6757 case AARCH64_OPND_En
:
6758 case AARCH64_OPND_Em
:
6759 case AARCH64_OPND_Em16
:
6760 case AARCH64_OPND_SM3_IMM2
:
6761 reg_type
= REG_TYPE_V
;
6763 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6766 if (!(vectype
.defined
& NTA_HASINDEX
))
6769 if (reg
->type
== REG_TYPE_Z
&& vectype
.type
== NT_invtype
)
6770 /* Unqualified Zn[index] is allowed in LUTI2 instructions. */
6771 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6774 if (vectype
.type
== NT_invtype
)
6776 info
->qualifier
= vectype_to_qualifier (&vectype
);
6777 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6781 info
->reglane
.regno
= reg
->number
;
6782 info
->reglane
.index
= vectype
.index
;
6785 case AARCH64_OPND_SVE_ZnxN
:
6786 case AARCH64_OPND_SVE_ZtxN
:
6787 case AARCH64_OPND_SME_Zdnx2
:
6788 case AARCH64_OPND_SME_Zdnx4
:
6789 case AARCH64_OPND_SME_Zmx2
:
6790 case AARCH64_OPND_SME_Zmx4
:
6791 case AARCH64_OPND_SME_Znx2
:
6792 case AARCH64_OPND_SME_Znx4
:
6793 case AARCH64_OPND_SME_Ztx2_STRIDED
:
6794 case AARCH64_OPND_SME_Ztx4_STRIDED
:
6795 reg_type
= REG_TYPE_Z
;
6796 goto vector_reg_list
;
6798 case AARCH64_OPND_SME_Pdx2
:
6799 case AARCH64_OPND_SME_PdxN
:
6800 reg_type
= REG_TYPE_P
;
6801 goto vector_reg_list
;
6803 case AARCH64_OPND_LVn
:
6804 case AARCH64_OPND_LVt
:
6805 case AARCH64_OPND_LVt_AL
:
6806 case AARCH64_OPND_LEt
:
6807 reg_type
= REG_TYPE_V
;
6809 if (reg_type
== REG_TYPE_Z
6810 && get_opcode_dependent_value (opcode
) == 1
6813 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6816 info
->reglist
.first_regno
= reg
->number
;
6817 info
->reglist
.num_regs
= 1;
6818 info
->reglist
.stride
= 1;
6822 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6823 if (val
== PARSE_FAIL
)
6826 if (! reg_list_valid_p (val
, &info
->reglist
, reg_type
))
6828 set_fatal_syntax_error (_("invalid register list"));
6832 if ((int) vectype
.width
> 0 && *str
!= ',')
6834 set_fatal_syntax_error
6835 (_("expected element type rather than vector type"));
6839 if (operands
[i
] == AARCH64_OPND_LEt
)
6841 if (!(vectype
.defined
& NTA_HASINDEX
))
6843 info
->reglist
.has_index
= 1;
6844 info
->reglist
.index
= vectype
.index
;
6848 if (vectype
.defined
& NTA_HASINDEX
)
6850 if (!(vectype
.defined
& NTA_HASTYPE
))
6852 if (reg_type
== REG_TYPE_Z
|| reg_type
== REG_TYPE_P
)
6853 set_fatal_syntax_error (_("missing type suffix"));
6857 info
->qualifier
= vectype_to_qualifier (&vectype
);
6858 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6862 case AARCH64_OPND_CRn
:
6863 case AARCH64_OPND_CRm
:
6865 char prefix
= *(str
++);
6866 if (prefix
!= 'c' && prefix
!= 'C')
6869 po_imm_nc_or_fail ();
6872 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6875 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6876 info
->imm
.value
= val
;
6880 case AARCH64_OPND_SHLL_IMM
:
6881 case AARCH64_OPND_IMM_VLSR
:
6882 po_imm_or_fail (1, 64);
6883 info
->imm
.value
= val
;
6886 case AARCH64_OPND_CCMP_IMM
:
6887 case AARCH64_OPND_SIMM5
:
6888 case AARCH64_OPND_FBITS
:
6889 case AARCH64_OPND_TME_UIMM16
:
6890 case AARCH64_OPND_UIMM4
:
6891 case AARCH64_OPND_UIMM4_ADDG
:
6892 case AARCH64_OPND_UIMM10
:
6893 case AARCH64_OPND_UIMM3_OP1
:
6894 case AARCH64_OPND_UIMM3_OP2
:
6895 case AARCH64_OPND_IMM_VLSL
:
6896 case AARCH64_OPND_IMM
:
6897 case AARCH64_OPND_IMM_2
:
6898 case AARCH64_OPND_WIDTH
:
6899 case AARCH64_OPND_SVE_INV_LIMM
:
6900 case AARCH64_OPND_SVE_LIMM
:
6901 case AARCH64_OPND_SVE_LIMM_MOV
:
6902 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6903 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6904 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6905 case AARCH64_OPND_SME_SHRIMM4
:
6906 case AARCH64_OPND_SME_SHRIMM5
:
6907 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6908 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6909 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6910 case AARCH64_OPND_SVE_SIMM5
:
6911 case AARCH64_OPND_SVE_SIMM5B
:
6912 case AARCH64_OPND_SVE_SIMM6
:
6913 case AARCH64_OPND_SVE_SIMM8
:
6914 case AARCH64_OPND_SVE_UIMM3
:
6915 case AARCH64_OPND_SVE_UIMM7
:
6916 case AARCH64_OPND_SVE_UIMM8
:
6917 case AARCH64_OPND_SVE_UIMM8_53
:
6918 case AARCH64_OPND_IMM_ROT1
:
6919 case AARCH64_OPND_IMM_ROT2
:
6920 case AARCH64_OPND_IMM_ROT3
:
6921 case AARCH64_OPND_SVE_IMM_ROT1
:
6922 case AARCH64_OPND_SVE_IMM_ROT2
:
6923 case AARCH64_OPND_SVE_IMM_ROT3
:
6924 case AARCH64_OPND_CSSC_SIMM8
:
6925 case AARCH64_OPND_CSSC_UIMM8
:
6926 po_imm_nc_or_fail ();
6927 info
->imm
.value
= val
;
6930 case AARCH64_OPND_SVE_AIMM
:
6931 case AARCH64_OPND_SVE_ASIMM
:
6932 po_imm_nc_or_fail ();
6933 info
->imm
.value
= val
;
6934 skip_whitespace (str
);
6935 if (skip_past_comma (&str
))
6936 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6938 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6941 case AARCH64_OPND_SVE_PATTERN
:
6942 po_enum_or_fail (aarch64_sve_pattern_array
);
6943 info
->imm
.value
= val
;
6946 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6947 po_enum_or_fail (aarch64_sve_pattern_array
);
6948 info
->imm
.value
= val
;
6949 if (skip_past_comma (&str
)
6950 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6952 if (!info
->shifter
.operator_present
)
6954 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6955 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6956 info
->shifter
.amount
= 1;
6960 case AARCH64_OPND_SVE_PRFOP
:
6961 po_enum_or_fail (aarch64_sve_prfop_array
);
6962 info
->imm
.value
= val
;
6965 case AARCH64_OPND_UIMM7
:
6966 po_imm_or_fail (0, 127);
6967 info
->imm
.value
= val
;
6970 case AARCH64_OPND_IDX
:
6971 case AARCH64_OPND_MASK
:
6972 case AARCH64_OPND_BIT_NUM
:
6973 case AARCH64_OPND_IMMR
:
6974 case AARCH64_OPND_IMMS
:
6975 po_imm_or_fail (0, 63);
6976 info
->imm
.value
= val
;
6979 case AARCH64_OPND_IMM0
:
6980 po_imm_nc_or_fail ();
6983 set_fatal_syntax_error (_("immediate zero expected"));
6986 info
->imm
.value
= 0;
6989 case AARCH64_OPND_FPIMM0
:
6992 bool res1
= false, res2
= false;
6993 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6994 it is probably not worth the effort to support it. */
6995 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6998 || !(res2
= parse_constant_immediate (&str
, &val
,
7001 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
7003 info
->imm
.value
= 0;
7004 info
->imm
.is_fp
= 1;
7007 set_fatal_syntax_error (_("immediate zero expected"));
7011 case AARCH64_OPND_IMM_MOV
:
7014 if (reg_name_p (str
, REG_TYPE_R_ZR_SP
)
7015 || reg_name_p (str
, REG_TYPE_V
))
7018 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
7019 GE_OPT_PREFIX
, REJECT_ABSENT
));
7020 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
7021 later. fix_mov_imm_insn will try to determine a machine
7022 instruction (MOVZ, MOVN or ORR) for it and will issue an error
7023 message if the immediate cannot be moved by a single
7025 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7026 inst
.base
.operands
[i
].skip
= 1;
7030 case AARCH64_OPND_SIMD_IMM
:
7031 case AARCH64_OPND_SIMD_IMM_SFT
:
7032 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
7034 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7036 /* need_libopcodes_p */ 1,
7039 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
7040 shift, we don't check it here; we leave the checking to
7041 the libopcodes (operand_general_constraint_met_p). By
7042 doing this, we achieve better diagnostics. */
7043 if (skip_past_comma (&str
)
7044 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
7046 if (!info
->shifter
.operator_present
7047 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
7049 /* Default to LSL if not present. Libopcodes prefers shifter
7050 kind to be explicit. */
7051 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7052 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7056 case AARCH64_OPND_FPIMM
:
7057 case AARCH64_OPND_SIMD_FPIMM
:
7058 case AARCH64_OPND_SVE_FPIMM8
:
7063 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7064 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
7065 || !aarch64_imm_float_p (qfloat
))
7068 set_fatal_syntax_error (_("invalid floating-point"
7072 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
7073 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7077 case AARCH64_OPND_SVE_I1_HALF_ONE
:
7078 case AARCH64_OPND_SVE_I1_HALF_TWO
:
7079 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
7084 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
7085 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
7088 set_fatal_syntax_error (_("invalid floating-point"
7092 inst
.base
.operands
[i
].imm
.value
= qfloat
;
7093 inst
.base
.operands
[i
].imm
.is_fp
= 1;
7097 case AARCH64_OPND_LIMM
:
7098 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7099 SHIFTED_LOGIC_IMM
));
7100 if (info
->shifter
.operator_present
)
7102 set_fatal_syntax_error
7103 (_("shift not allowed for bitmask immediate"));
7106 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7108 /* need_libopcodes_p */ 1,
7112 case AARCH64_OPND_AIMM
:
7113 if (opcode
->op
== OP_ADD
)
7114 /* ADD may have relocation types. */
7115 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
7116 SHIFTED_ARITH_IMM
));
7118 po_misc_or_fail (parse_shifter_operand (&str
, info
,
7119 SHIFTED_ARITH_IMM
));
7120 switch (inst
.reloc
.type
)
7122 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7123 info
->shifter
.amount
= 12;
7125 case BFD_RELOC_UNUSED
:
7126 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7127 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
7128 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
7129 inst
.reloc
.pc_rel
= 0;
7134 info
->imm
.value
= 0;
7135 if (!info
->shifter
.operator_present
)
7137 /* Default to LSL if not present. Libopcodes prefers shifter
7138 kind to be explicit. */
7139 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7140 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7144 case AARCH64_OPND_HALF
:
7146 /* #<imm16> or relocation. */
7147 int internal_fixup_p
;
7148 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
7149 if (internal_fixup_p
)
7150 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
7151 skip_whitespace (str
);
7152 if (skip_past_comma (&str
))
7154 /* {, LSL #<shift>} */
7155 if (! aarch64_gas_internal_fixup_p ())
7157 set_fatal_syntax_error (_("can't mix relocation modifier "
7158 "with explicit shift"));
7161 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
7164 inst
.base
.operands
[i
].shifter
.amount
= 0;
7165 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
7166 inst
.base
.operands
[i
].imm
.value
= 0;
7167 if (! process_movw_reloc_info ())
7172 case AARCH64_OPND_EXCEPTION
:
7173 case AARCH64_OPND_UNDEFINED
:
7174 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
7176 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7178 /* need_libopcodes_p */ 0,
7182 case AARCH64_OPND_NZCV
:
7184 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
7188 info
->imm
.value
= nzcv
->value
;
7191 po_imm_or_fail (0, 15);
7192 info
->imm
.value
= val
;
7196 case AARCH64_OPND_COND
:
7197 case AARCH64_OPND_COND1
:
7202 while (ISALPHA (*str
));
7203 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
7204 if (info
->cond
== NULL
)
7206 set_syntax_error (_("invalid condition"));
7209 else if (operands
[i
] == AARCH64_OPND_COND1
7210 && (info
->cond
->value
& 0xe) == 0xe)
7212 /* Do not allow AL or NV. */
7213 set_default_error ();
7219 case AARCH64_OPND_ADDR_ADRP
:
7220 po_misc_or_fail (parse_adrp (&str
));
7221 /* Clear the value as operand needs to be relocated. */
7222 info
->imm
.value
= 0;
7225 case AARCH64_OPND_ADDR_PCREL14
:
7226 case AARCH64_OPND_ADDR_PCREL19
:
7227 case AARCH64_OPND_ADDR_PCREL21
:
7228 case AARCH64_OPND_ADDR_PCREL26
:
7229 po_misc_or_fail (parse_address (&str
, info
));
7230 if (!info
->addr
.pcrel
)
7232 set_syntax_error (_("invalid pc-relative address"));
7235 if (inst
.gen_lit_pool
7236 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
7238 /* Only permit "=value" in the literal load instructions.
7239 The literal will be generated by programmer_friendly_fixup. */
7240 set_syntax_error (_("invalid use of \"=immediate\""));
7243 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7245 set_syntax_error (_("unrecognized relocation suffix"));
7248 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7250 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7251 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7255 info
->imm
.value
= 0;
7256 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7257 switch (opcode
->iclass
)
7261 /* e.g. CBZ or B.COND */
7262 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7263 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7267 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7268 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7272 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7274 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7275 : BFD_RELOC_AARCH64_JUMP26
;
7278 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7279 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7282 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7283 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7289 inst
.reloc
.pc_rel
= 1;
7293 case AARCH64_OPND_ADDR_SIMPLE
:
7294 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7296 /* [<Xn|SP>{, #<simm>}] */
7298 /* First use the normal address-parsing routines, to get
7299 the usual syntax errors. */
7300 po_misc_or_fail (parse_address (&str
, info
));
7301 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7302 || !info
->addr
.preind
|| info
->addr
.postind
7303 || info
->addr
.writeback
)
7305 set_syntax_error (_("invalid addressing mode"));
7309 /* Then retry, matching the specific syntax of these addresses. */
7311 po_char_or_fail ('[');
7312 po_reg_or_fail (REG_TYPE_R64_SP
);
7313 /* Accept optional ", #0". */
7314 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7315 && skip_past_char (&str
, ','))
7317 skip_past_char (&str
, '#');
7318 if (! skip_past_char (&str
, '0'))
7320 set_fatal_syntax_error
7321 (_("the optional immediate offset can only be 0"));
7325 po_char_or_fail (']');
7329 case AARCH64_OPND_ADDR_REGOFF
:
7330 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7331 po_misc_or_fail (parse_address (&str
, info
));
7333 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7334 || !info
->addr
.preind
|| info
->addr
.postind
7335 || info
->addr
.writeback
)
7337 set_syntax_error (_("invalid addressing mode"));
7340 if (!info
->shifter
.operator_present
)
7342 /* Default to LSL if not present. Libopcodes prefers shifter
7343 kind to be explicit. */
7344 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7345 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7347 /* Qualifier to be deduced by libopcodes. */
7350 case AARCH64_OPND_ADDR_SIMM7
:
7351 po_misc_or_fail (parse_address (&str
, info
));
7352 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7353 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7355 set_syntax_error (_("invalid addressing mode"));
7358 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7360 set_syntax_error (_("relocation not allowed"));
7363 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7365 /* need_libopcodes_p */ 1,
7369 case AARCH64_OPND_ADDR_SIMM9
:
7370 case AARCH64_OPND_ADDR_SIMM9_2
:
7371 case AARCH64_OPND_ADDR_SIMM11
:
7372 case AARCH64_OPND_ADDR_SIMM13
:
7373 po_misc_or_fail (parse_address (&str
, info
));
7374 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7375 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7376 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7377 && info
->addr
.writeback
))
7379 set_syntax_error (_("invalid addressing mode"));
7382 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7384 set_syntax_error (_("relocation not allowed"));
7387 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7389 /* need_libopcodes_p */ 1,
7393 case AARCH64_OPND_ADDR_SIMM10
:
7394 case AARCH64_OPND_ADDR_OFFSET
:
7395 po_misc_or_fail (parse_address (&str
, info
));
7396 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7397 || !info
->addr
.preind
|| info
->addr
.postind
)
7399 set_syntax_error (_("invalid addressing mode"));
7402 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7404 set_syntax_error (_("relocation not allowed"));
7407 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7409 /* need_libopcodes_p */ 1,
7413 case AARCH64_OPND_ADDR_UIMM12
:
7414 po_misc_or_fail (parse_address (&str
, info
));
7415 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7416 || !info
->addr
.preind
|| info
->addr
.writeback
)
7418 set_syntax_error (_("invalid addressing mode"));
7421 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7422 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7423 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7425 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7427 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7429 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7431 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7432 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7433 /* Leave qualifier to be determined by libopcodes. */
7436 case AARCH64_OPND_SIMD_ADDR_POST
:
7437 /* [<Xn|SP>], <Xm|#<amount>> */
7438 po_misc_or_fail (parse_address (&str
, info
));
7439 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7441 set_syntax_error (_("invalid addressing mode"));
7444 if (!info
->addr
.offset
.is_reg
)
7446 if (inst
.reloc
.exp
.X_op
== O_constant
)
7447 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7450 set_fatal_syntax_error
7451 (_("writeback value must be an immediate constant"));
7458 case AARCH64_OPND_SME_SM_ZA
:
7460 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7462 set_syntax_error (_("unknown or missing PSTATE field name"));
7465 info
->reg
.regno
= val
;
7468 case AARCH64_OPND_SME_PnT_Wm_imm
:
7469 if (!parse_dual_indexed_reg (&str
, REG_TYPE_P
,
7470 &info
->indexed_za
, &qualifier
, 0))
7472 info
->qualifier
= qualifier
;
7475 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7476 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7477 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7478 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7479 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7480 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7481 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7482 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7483 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7484 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7485 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7486 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7487 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7488 /* [X<n>{, #imm, MUL VL}]
7490 but recognizing SVE registers. */
7491 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7492 &offset_qualifier
));
7493 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7495 set_syntax_error (_("invalid addressing mode"));
7499 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7500 || !info
->addr
.preind
|| info
->addr
.writeback
)
7502 set_syntax_error (_("invalid addressing mode"));
7505 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7506 || inst
.reloc
.exp
.X_op
!= O_constant
)
7508 /* Make sure this has priority over
7509 "invalid addressing mode". */
7510 set_fatal_syntax_error (_("constant offset required"));
7513 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7516 case AARCH64_OPND_SVE_ADDR_R
:
7517 /* [<Xn|SP>{, <R><m>}]
7518 but recognizing SVE registers. */
7519 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7520 &offset_qualifier
));
7521 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7523 offset_qualifier
= AARCH64_OPND_QLF_X
;
7524 info
->addr
.offset
.is_reg
= 1;
7525 info
->addr
.offset
.regno
= 31;
7527 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7528 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7530 set_syntax_error (_("invalid addressing mode"));
7535 case AARCH64_OPND_SVE_ADDR_RR
:
7536 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7537 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7538 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7539 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7540 case AARCH64_OPND_SVE_ADDR_RX
:
7541 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7542 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7543 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7544 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7545 but recognizing SVE registers. */
7546 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7547 &offset_qualifier
));
7548 if (base_qualifier
!= AARCH64_OPND_QLF_X
7549 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7551 set_syntax_error (_("invalid addressing mode"));
7556 case AARCH64_OPND_SVE_ADDR_RZ
:
7557 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7558 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7559 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7560 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7561 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7562 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7563 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7564 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7565 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7566 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7567 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7568 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7569 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7570 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7571 &offset_qualifier
));
7572 if (base_qualifier
!= AARCH64_OPND_QLF_X
7573 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7574 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7576 set_syntax_error (_("invalid addressing mode"));
7579 info
->qualifier
= offset_qualifier
;
7582 case AARCH64_OPND_SVE_ADDR_ZX
:
7583 /* [Zn.<T>{, <Xm>}]. */
7584 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7585 &offset_qualifier
));
7587 base_qualifier either S_S or S_D
7588 offset_qualifier must be X
7590 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7591 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7592 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7594 set_syntax_error (_("invalid addressing mode"));
7597 info
->qualifier
= base_qualifier
;
7598 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7599 || !info
->addr
.preind
|| info
->addr
.writeback
7600 || info
->shifter
.operator_present
!= 0)
7602 set_syntax_error (_("invalid addressing mode"));
7605 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7609 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7610 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7611 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7612 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7613 /* [Z<n>.<T>{, #imm}] */
7614 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7615 &offset_qualifier
));
7616 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7617 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7619 set_syntax_error (_("invalid addressing mode"));
7622 info
->qualifier
= base_qualifier
;
7625 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7626 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7627 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7628 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7629 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7633 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7635 here since we get better error messages by leaving it to
7636 the qualifier checking routines. */
7637 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7638 &offset_qualifier
));
7639 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7640 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7641 || offset_qualifier
!= base_qualifier
)
7643 set_syntax_error (_("invalid addressing mode"));
7646 info
->qualifier
= base_qualifier
;
7649 case AARCH64_OPND_SYSREG
:
7651 uint32_t sysreg_flags
;
7652 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7653 &sysreg_flags
)) == PARSE_FAIL
)
7655 set_syntax_error (_("unknown or missing system register name"));
7658 inst
.base
.operands
[i
].sysreg
.value
= val
;
7659 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7663 case AARCH64_OPND_PSTATEFIELD
:
7665 uint32_t sysreg_flags
;
7666 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7667 &sysreg_flags
)) == PARSE_FAIL
)
7669 set_syntax_error (_("unknown or missing PSTATE field name"));
7672 inst
.base
.operands
[i
].pstatefield
= val
;
7673 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7677 case AARCH64_OPND_SYSREG_IC
:
7678 inst
.base
.operands
[i
].sysins_op
=
7679 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7682 case AARCH64_OPND_SYSREG_DC
:
7683 inst
.base
.operands
[i
].sysins_op
=
7684 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7687 case AARCH64_OPND_SYSREG_AT
:
7688 inst
.base
.operands
[i
].sysins_op
=
7689 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7692 case AARCH64_OPND_SYSREG_SR
:
7693 inst
.base
.operands
[i
].sysins_op
=
7694 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7697 case AARCH64_OPND_SYSREG_TLBI
:
7698 inst
.base
.operands
[i
].sysins_op
=
7699 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7701 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7703 set_fatal_syntax_error ( _("unknown or missing operation name"));
7708 case AARCH64_OPND_BARRIER
:
7709 case AARCH64_OPND_BARRIER_ISB
:
7710 val
= parse_barrier (&str
);
7711 if (val
!= PARSE_FAIL
7712 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7714 /* ISB only accepts options name 'sy'. */
7716 (_("the specified option is not accepted in ISB"));
7717 /* Turn off backtrack as this optional operand is present. */
7721 if (val
!= PARSE_FAIL
7722 && operands
[i
] == AARCH64_OPND_BARRIER
)
7724 /* Regular barriers accept options CRm (C0-C15).
7725 DSB nXS barrier variant accepts values > 15. */
7726 if (val
< 0 || val
> 15)
7728 set_syntax_error (_("the specified option is not accepted in DSB"));
7732 /* This is an extension to accept a 0..15 immediate. */
7733 if (val
== PARSE_FAIL
)
7734 po_imm_or_fail (0, 15);
7735 info
->barrier
= aarch64_barrier_options
+ val
;
7738 case AARCH64_OPND_BARRIER_DSB_NXS
:
7739 val
= parse_barrier (&str
);
7740 if (val
!= PARSE_FAIL
)
7742 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7743 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7745 set_syntax_error (_("the specified option is not accepted in DSB"));
7746 /* Turn off backtrack as this optional operand is present. */
7753 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7754 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7755 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7757 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7759 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7763 /* Option index is encoded as 2-bit value in val<3:2>. */
7764 val
= (val
>> 2) - 4;
7765 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7768 case AARCH64_OPND_PRFOP
:
7769 val
= parse_pldop (&str
);
7770 /* This is an extension to accept a 0..31 immediate. */
7771 if (val
== PARSE_FAIL
)
7772 po_imm_or_fail (0, 31);
7773 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7776 case AARCH64_OPND_BARRIER_PSB
:
7777 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7778 if (val
== PARSE_FAIL
)
7782 case AARCH64_OPND_SME_ZT0
:
7783 po_reg_or_fail (REG_TYPE_ZT0
);
7786 case AARCH64_OPND_SME_ZT0_INDEX
:
7787 reg
= aarch64_reg_parse (&str
, REG_TYPE_ZT0
, &vectype
);
7788 if (!reg
|| vectype
.type
!= NT_invtype
)
7790 if (!(vectype
.defined
& NTA_HASINDEX
))
7792 set_syntax_error (_("missing register index"));
7795 info
->imm
.value
= vectype
.index
;
7798 case AARCH64_OPND_SME_ZT0_LIST
:
7801 set_expected_reglist_error (REG_TYPE_ZT0
, parse_reg (&str
));
7805 if (!parse_typed_reg (&str
, REG_TYPE_ZT0
, &vectype
, PTR_IN_REGLIST
))
7809 set_syntax_error (_("expected '}' after ZT0"));
7815 case AARCH64_OPND_SME_PNn3_INDEX1
:
7816 case AARCH64_OPND_SME_PNn3_INDEX2
:
7817 reg
= aarch64_reg_parse (&str
, REG_TYPE_PN
, &vectype
);
7820 if (!(vectype
.defined
& NTA_HASINDEX
))
7822 set_syntax_error (_("missing register index"));
7825 info
->reglane
.regno
= reg
->number
;
7826 info
->reglane
.index
= vectype
.index
;
7827 if (vectype
.type
== NT_invtype
)
7828 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
7830 info
->qualifier
= vectype_to_qualifier (&vectype
);
7833 case AARCH64_OPND_BTI_TARGET
:
7834 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7835 if (val
== PARSE_FAIL
)
7839 case AARCH64_OPND_SME_ZAda_2b
:
7840 case AARCH64_OPND_SME_ZAda_3b
:
7841 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
, 0);
7844 info
->reg
.regno
= reg
->number
;
7845 info
->qualifier
= qualifier
;
7848 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7849 case AARCH64_OPND_SME_ZA_HV_idx_srcxN
:
7850 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7851 case AARCH64_OPND_SME_ZA_HV_idx_destxN
:
7852 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7853 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7854 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7857 : !parse_dual_indexed_reg (&str
, REG_TYPE_ZATHV
,
7858 &info
->indexed_za
, &qualifier
, 0))
7860 info
->qualifier
= qualifier
;
7863 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7864 val
= parse_sme_list_of_64bit_tiles (&str
);
7865 if (val
== PARSE_FAIL
)
7867 info
->imm
.value
= val
;
7870 case AARCH64_OPND_SME_ZA_array_off1x4
:
7871 case AARCH64_OPND_SME_ZA_array_off2x2
:
7872 case AARCH64_OPND_SME_ZA_array_off2x4
:
7873 case AARCH64_OPND_SME_ZA_array_off3_0
:
7874 case AARCH64_OPND_SME_ZA_array_off3_5
:
7875 case AARCH64_OPND_SME_ZA_array_off3x2
:
7876 case AARCH64_OPND_SME_ZA_array_off4
:
7877 if (!parse_dual_indexed_reg (&str
, REG_TYPE_ZA
,
7878 &info
->indexed_za
, &qualifier
, 0))
7880 info
->qualifier
= qualifier
;
7883 case AARCH64_OPND_SME_VLxN_10
:
7884 case AARCH64_OPND_SME_VLxN_13
:
7885 po_strict_enum_or_fail (aarch64_sme_vlxn_array
);
7886 info
->imm
.value
= val
;
7889 case AARCH64_OPND_MOPS_ADDR_Rd
:
7890 case AARCH64_OPND_MOPS_ADDR_Rs
:
7891 po_char_or_fail ('[');
7892 if (!parse_x0_to_x30 (&str
, info
))
7894 po_char_or_fail (']');
7895 po_char_or_fail ('!');
7898 case AARCH64_OPND_MOPS_WB_Rn
:
7899 if (!parse_x0_to_x30 (&str
, info
))
7901 po_char_or_fail ('!');
7905 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7908 /* If we get here, this operand was successfully parsed. */
7909 inst
.base
.operands
[i
].present
= 1;
7913 /* The parse routine should already have set the error, but in case
7914 not, set a default one here. */
7916 set_default_error ();
7918 if (! backtrack_pos
)
7919 goto parse_operands_return
;
7922 /* We reach here because this operand is marked as optional, and
7923 either no operand was supplied or the operand was supplied but it
7924 was syntactically incorrect. In the latter case we report an
7925 error. In the former case we perform a few more checks before
7926 dropping through to the code to insert the default operand. */
7928 char *tmp
= backtrack_pos
;
7929 char endchar
= END_OF_INSN
;
7931 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7933 skip_past_char (&tmp
, ',');
7935 if (*tmp
!= endchar
)
7936 /* The user has supplied an operand in the wrong format. */
7937 goto parse_operands_return
;
7939 /* Make sure there is not a comma before the optional operand.
7940 For example the fifth operand of 'sys' is optional:
7942 sys #0,c0,c0,#0, <--- wrong
7943 sys #0,c0,c0,#0 <--- correct. */
7944 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7946 set_fatal_syntax_error
7947 (_("unexpected comma before the omitted optional operand"));
7948 goto parse_operands_return
;
7952 /* Reaching here means we are dealing with an optional operand that is
7953 omitted from the assembly line. */
7954 gas_assert (optional_operand_p (opcode
, i
));
7956 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7958 /* Try again, skipping the optional operand at backtrack_pos. */
7959 str
= backtrack_pos
;
7962 /* Clear any error record after the omitted optional operand has been
7963 successfully handled. */
7967 /* Check if we have parsed all the operands. */
7968 if (*str
!= '\0' && ! error_p ())
7970 /* Set I to the index of the last present operand; this is
7971 for the purpose of diagnostics. */
7972 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7974 set_fatal_syntax_error
7975 (_("unexpected characters following instruction"));
7978 parse_operands_return
:
7982 inst
.parsing_error
.index
= i
;
7983 DEBUG_TRACE ("parsing FAIL: %s - %s",
7984 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7985 inst
.parsing_error
.error
);
7986 /* Record the operand error properly; this is useful when there
7987 are multiple instruction templates for a mnemonic name, so that
7988 later on, we can select the error that most closely describes
7990 record_operand_error_info (opcode
, &inst
.parsing_error
);
7995 DEBUG_TRACE ("parsing SUCCESS");
8000 /* It does some fix-up to provide some programmer friendly feature while
8001 keeping the libopcodes happy, i.e. libopcodes only accepts
8002 the preferred architectural syntax.
8003 Return FALSE if there is any failure; otherwise return TRUE. */
8006 programmer_friendly_fixup (aarch64_instruction
*instr
)
8008 aarch64_inst
*base
= &instr
->base
;
8009 const aarch64_opcode
*opcode
= base
->opcode
;
8010 enum aarch64_op op
= opcode
->op
;
8011 aarch64_opnd_info
*operands
= base
->operands
;
8013 DEBUG_TRACE ("enter");
8015 switch (opcode
->iclass
)
8018 /* TBNZ Xn|Wn, #uimm6, label
8019 Test and Branch Not Zero: conditionally jumps to label if bit number
8020 uimm6 in register Xn is not zero. The bit number implies the width of
8021 the register, which may be written and should be disassembled as Wn if
8022 uimm is less than 32. */
8023 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
8025 if (operands
[1].imm
.value
>= 32)
8027 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
8031 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
8035 /* LDR Wt, label | =value
8036 As a convenience assemblers will typically permit the notation
8037 "=value" in conjunction with the pc-relative literal load instructions
8038 to automatically place an immediate value or symbolic address in a
8039 nearby literal pool and generate a hidden label which references it.
8040 ISREG has been set to 0 in the case of =value. */
8041 if (instr
->gen_lit_pool
8042 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
8044 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
8045 if (op
== OP_LDRSW_LIT
)
8047 if (instr
->reloc
.exp
.X_op
!= O_constant
8048 && instr
->reloc
.exp
.X_op
!= O_big
8049 && instr
->reloc
.exp
.X_op
!= O_symbol
)
8051 record_operand_error (opcode
, 1,
8052 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
8053 _("constant expression expected"));
8056 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
8058 record_operand_error (opcode
, 1,
8059 AARCH64_OPDE_OTHER_ERROR
,
8060 _("literal pool insertion failed"));
8068 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
8069 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
8070 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
8071 A programmer-friendly assembler should accept a destination Xd in
8072 place of Wd, however that is not the preferred form for disassembly.
8074 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
8075 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
8076 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
8077 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
8082 /* In the 64-bit form, the final register operand is written as Wm
8083 for all but the (possibly omitted) UXTX/LSL and SXTX
8085 As a programmer-friendly assembler, we accept e.g.
8086 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
8087 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
8088 int idx
= aarch64_operand_index (opcode
->operands
,
8089 AARCH64_OPND_Rm_EXT
);
8090 gas_assert (idx
== 1 || idx
== 2);
8091 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
8092 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
8093 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
8094 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
8095 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
8096 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
8104 DEBUG_TRACE ("exit with SUCCESS");
8108 /* Check for loads and stores that will cause unpredictable behavior. */
8111 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
8113 aarch64_inst
*base
= &instr
->base
;
8114 const aarch64_opcode
*opcode
= base
->opcode
;
8115 const aarch64_opnd_info
*opnds
= base
->operands
;
8116 switch (opcode
->iclass
)
8123 /* Loading/storing the base register is unpredictable if writeback. */
8124 if ((aarch64_get_operand_class (opnds
[0].type
)
8125 == AARCH64_OPND_CLASS_INT_REG
)
8126 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
8127 && opnds
[1].addr
.base_regno
!= REG_SP
8128 /* Exempt STG/STZG/ST2G/STZ2G. */
8129 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
8130 && opnds
[1].addr
.writeback
)
8131 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8135 case ldstnapair_offs
:
8136 case ldstpair_indexed
:
8137 /* Loading/storing the base register is unpredictable if writeback. */
8138 if ((aarch64_get_operand_class (opnds
[0].type
)
8139 == AARCH64_OPND_CLASS_INT_REG
)
8140 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
8141 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
8142 && opnds
[2].addr
.base_regno
!= REG_SP
8144 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
8145 && opnds
[2].addr
.writeback
)
8146 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
8147 /* Load operations must load different registers. */
8148 if ((opcode
->opcode
& (1 << 22))
8149 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8150 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8154 if ((aarch64_get_operand_class (opnds
[0].type
)
8155 == AARCH64_OPND_CLASS_INT_REG
)
8156 && (aarch64_get_operand_class (opnds
[1].type
)
8157 == AARCH64_OPND_CLASS_INT_REG
))
8159 if ((opcode
->opcode
& (1 << 22)))
8161 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
8162 if ((opcode
->opcode
& (1 << 21))
8163 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8164 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
8168 /* Store-Exclusive is unpredictable if Rt == Rs. */
8169 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
8171 (_("unpredictable: identical transfer and status registers"
8174 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
8176 if (!(opcode
->opcode
& (1 << 21)))
8177 /* Store-Exclusive is unpredictable if Rn == Rs. */
8179 (_("unpredictable: identical base and status registers"
8182 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
8184 (_("unpredictable: "
8185 "identical transfer and status registers"
8189 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
8190 if ((opcode
->opcode
& (1 << 21))
8191 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
8192 && opnds
[3].reg
.regno
!= REG_SP
)
8193 as_warn (_("unpredictable: identical base and status registers"
8205 force_automatic_sequence_close (void)
8207 struct aarch64_segment_info_type
*tc_seg_info
;
8209 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8210 if (tc_seg_info
->insn_sequence
.instr
)
8212 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
8213 _("previous `%s' sequence has not been closed"),
8214 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
8215 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
8219 /* A wrapper function to interface with libopcodes on encoding and
8220 record the error message if there is any.
8222 Return TRUE on success; otherwise return FALSE. */
8225 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
8228 aarch64_operand_error error_info
;
8229 memset (&error_info
, '\0', sizeof (error_info
));
8230 error_info
.kind
= AARCH64_OPDE_NIL
;
8231 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
8232 && !error_info
.non_fatal
)
8235 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
8236 record_operand_error_info (opcode
, &error_info
);
8237 return error_info
.non_fatal
;
8240 #ifdef DEBUG_AARCH64
8242 dump_opcode_operands (const aarch64_opcode
*opcode
)
8245 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
8247 aarch64_verbose ("\t\t opnd%d: %s", i
,
8248 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
8249 ? aarch64_get_operand_name (opcode
->operands
[i
])
8250 : aarch64_get_operand_desc (opcode
->operands
[i
]));
8254 #endif /* DEBUG_AARCH64 */
8256 /* This is the guts of the machine-dependent assembler. STR points to a
8257 machine dependent instruction. This function is supposed to emit
8258 the frags/bytes it assembles to. */
8261 md_assemble (char *str
)
8263 templates
*template;
8264 const aarch64_opcode
*opcode
;
8265 struct aarch64_segment_info_type
*tc_seg_info
;
8266 aarch64_inst
*inst_base
;
8267 unsigned saved_cond
;
8269 /* Align the previous label if needed. */
8270 if (last_label_seen
!= NULL
)
8272 symbol_set_frag (last_label_seen
, frag_now
);
8273 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8274 S_SET_SEGMENT (last_label_seen
, now_seg
);
8277 /* Update the current insn_sequence from the segment. */
8278 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8279 insn_sequence
= &tc_seg_info
->insn_sequence
;
8280 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8282 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8284 DEBUG_TRACE ("\n\n");
8285 DEBUG_TRACE ("==============================");
8286 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8288 /* Scan up to the end of the mnemonic, which must end in whitespace,
8289 '.', or end of string. */
8292 for (; is_part_of_name (*p
); p
++)
8293 if (*p
== '.' && !dot
)
8298 as_bad (_("unknown mnemonic -- `%s'"), str
);
8302 if (!dot
&& create_register_alias (str
, p
))
8305 template = opcode_lookup (str
, dot
, p
);
8308 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8313 skip_whitespace (p
);
8316 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8317 get_mnemonic_name (str
), str
);
8321 init_operand_error_report ();
8323 /* Sections are assumed to start aligned. In executable section, there is no
8324 MAP_DATA symbol pending. So we only align the address during
8325 MAP_DATA --> MAP_INSN transition.
8326 For other sections, this is not guaranteed. */
8327 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8328 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8329 frag_align_code (2, 0);
8331 saved_cond
= inst
.cond
;
8332 reset_aarch64_instruction (&inst
);
8333 inst
.cond
= saved_cond
;
8335 /* Iterate through all opcode entries with the same mnemonic name. */
8338 opcode
= template->opcode
;
8340 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8341 #ifdef DEBUG_AARCH64
8343 dump_opcode_operands (opcode
);
8344 #endif /* DEBUG_AARCH64 */
8346 mapping_state (MAP_INSN
);
8348 inst_base
= &inst
.base
;
8349 inst_base
->opcode
= opcode
;
8351 /* Truly conditionally executed instructions, e.g. b.cond. */
8352 if (opcode
->flags
& F_COND
)
8354 gas_assert (inst
.cond
!= COND_ALWAYS
);
8355 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8356 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8358 else if (inst
.cond
!= COND_ALWAYS
)
8360 /* It shouldn't arrive here, where the assembly looks like a
8361 conditional instruction but the found opcode is unconditional. */
8366 if (parse_operands (p
, opcode
)
8367 && programmer_friendly_fixup (&inst
)
8368 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8370 /* Check that this instruction is supported for this CPU. */
8371 if (!aarch64_cpu_supports_inst_p (cpu_variant
, inst_base
))
8373 as_bad (_("selected processor does not support `%s'"), str
);
8377 warn_unpredictable_ldst (&inst
, str
);
8379 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8380 || !inst
.reloc
.need_libopcodes_p
)
8384 /* If there is relocation generated for the instruction,
8385 store the instruction information for the future fix-up. */
8386 struct aarch64_inst
*copy
;
8387 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8388 copy
= XNEW (struct aarch64_inst
);
8389 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8393 /* Issue non-fatal messages if any. */
8394 output_operand_error_report (str
, true);
8398 template = template->next
;
8399 if (template != NULL
)
8401 reset_aarch64_instruction (&inst
);
8402 inst
.cond
= saved_cond
;
8405 while (template != NULL
);
8407 /* Issue the error messages if any. */
8408 output_operand_error_report (str
, false);
8411 /* Various frobbings of labels and their addresses. */
8414 aarch64_start_line_hook (void)
8416 last_label_seen
= NULL
;
8420 aarch64_frob_label (symbolS
* sym
)
8422 last_label_seen
= sym
;
8424 dwarf2_emit_label (sym
);
8428 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8430 /* Check to see if we have a block to close. */
8431 force_automatic_sequence_close ();
8435 aarch64_data_in_code (void)
8437 if (startswith (input_line_pointer
+ 1, "data:"))
8439 *input_line_pointer
= '/';
8440 input_line_pointer
+= 5;
8441 *input_line_pointer
= 0;
8449 aarch64_canonicalize_symbol_name (char *name
)
8453 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8454 *(name
+ len
- 5) = 0;
8459 /* Table of all register names defined by default. The user can
8460 define additional names with .req. Note that all register names
8461 should appear in both upper and lowercase variants. Some registers
8462 also have mixed-case names. */
8464 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8465 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8466 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8467 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8468 #define REGSET16(p,t) \
8469 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8470 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8471 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8472 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8473 #define REGSET16S(p,s,t) \
8474 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8475 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8476 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8477 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8478 #define REGSET31(p,t) \
8480 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8481 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8482 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8483 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8484 #define REGSET(p,t) \
8485 REGSET31(p,t), REGNUM(p,31,t)
8487 /* These go into aarch64_reg_hsh hash-table. */
8488 static const reg_entry reg_names
[] = {
8489 /* Integer registers. */
8490 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8491 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8493 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8494 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8495 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8496 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8497 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8498 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8500 REGDEF (wzr
, 31, ZR_32
), REGDEF (WZR
, 31, ZR_32
),
8501 REGDEF (xzr
, 31, ZR_64
), REGDEF (XZR
, 31, ZR_64
),
8503 /* Floating-point single precision registers. */
8504 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8506 /* Floating-point double precision registers. */
8507 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8509 /* Floating-point half precision registers. */
8510 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8512 /* Floating-point byte precision registers. */
8513 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8515 /* Floating-point quad precision registers. */
8516 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8518 /* FP/SIMD registers. */
8519 REGSET (v
, V
), REGSET (V
, V
),
8521 /* SVE vector registers. */
8522 REGSET (z
, Z
), REGSET (Z
, Z
),
8524 /* SVE predicate(-as-mask) registers. */
8525 REGSET16 (p
, P
), REGSET16 (P
, P
),
8527 /* SVE predicate-as-counter registers. */
8528 REGSET16 (pn
, PN
), REGSET16 (PN
, PN
),
8530 /* SME ZA. We model this as a register because it acts syntactically
8531 like ZA0H, supporting qualifier suffixes and indexing. */
8532 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8534 /* SME ZA tile registers. */
8535 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8537 /* SME ZA tile registers (horizontal slice). */
8538 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8540 /* SME ZA tile registers (vertical slice). */
8541 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
),
8544 REGDEF (zt0
, 0, ZT0
), REGDEF (ZT0
, 0, ZT0
)
8562 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8563 static const asm_nzcv nzcv_names
[] = {
8564 {"nzcv", B (n
, z
, c
, v
)},
8565 {"nzcV", B (n
, z
, c
, V
)},
8566 {"nzCv", B (n
, z
, C
, v
)},
8567 {"nzCV", B (n
, z
, C
, V
)},
8568 {"nZcv", B (n
, Z
, c
, v
)},
8569 {"nZcV", B (n
, Z
, c
, V
)},
8570 {"nZCv", B (n
, Z
, C
, v
)},
8571 {"nZCV", B (n
, Z
, C
, V
)},
8572 {"Nzcv", B (N
, z
, c
, v
)},
8573 {"NzcV", B (N
, z
, c
, V
)},
8574 {"NzCv", B (N
, z
, C
, v
)},
8575 {"NzCV", B (N
, z
, C
, V
)},
8576 {"NZcv", B (N
, Z
, c
, v
)},
8577 {"NZcV", B (N
, Z
, c
, V
)},
8578 {"NZCv", B (N
, Z
, C
, v
)},
8579 {"NZCV", B (N
, Z
, C
, V
)}
8592 /* MD interface: bits in the object file. */
8594 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8595 for use in the a.out file, and stores them in the array pointed to by buf.
8596 This knows about the endian-ness of the target machine and does
8597 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8598 2 (short) and 4 (long) Floating numbers are put out as a series of
8599 LITTLENUMS (shorts, here at least). */
8602 md_number_to_chars (char *buf
, valueT val
, int n
)
8604 if (target_big_endian
)
8605 number_to_chars_bigendian (buf
, val
, n
);
8607 number_to_chars_littleendian (buf
, val
, n
);
8610 /* MD interface: Sections. */
8612 /* Estimate the size of a frag before relaxing. Assume everything fits in
8616 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8622 /* Round up a section size to the appropriate boundary. */
8625 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8630 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8631 of an rs_align_code fragment.
8633 Here we fill the frag with the appropriate info for padding the
8634 output stream. The resulting frag will consist of a fixed (fr_fix)
8635 and of a repeating (fr_var) part.
8637 The fixed content is always emitted before the repeating content and
8638 these two parts are used as follows in constructing the output:
8639 - the fixed part will be used to align to a valid instruction word
8640 boundary, in case that we start at a misaligned address; as no
8641 executable instruction can live at the misaligned location, we
8642 simply fill with zeros;
8643 - the variable part will be used to cover the remaining padding and
8644 we fill using the AArch64 NOP instruction.
8646 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8647 enough storage space for up to 3 bytes for padding the back to a valid
8648 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8651 aarch64_handle_align (fragS
* fragP
)
8653 /* NOP = d503201f */
8654 /* AArch64 instructions are always little-endian. */
8655 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8657 int bytes
, fix
, noop_size
;
8660 if (fragP
->fr_type
!= rs_align_code
)
8663 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8664 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8667 gas_assert (fragP
->tc_frag_data
.recorded
);
8670 noop_size
= sizeof (aarch64_noop
);
8672 fix
= bytes
& (noop_size
- 1);
8675 #if defined OBJ_ELF || defined OBJ_COFF
8676 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8680 fragP
->fr_fix
+= fix
;
8684 memcpy (p
, aarch64_noop
, noop_size
);
8685 fragP
->fr_var
= noop_size
;
8688 /* Perform target specific initialisation of a frag.
8689 Note - despite the name this initialisation is not done when the frag
8690 is created, but only when its type is assigned. A frag can be created
8691 and used a long time before its type is set, so beware of assuming that
8692 this initialisation is performed first. */
8696 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8697 int max_chars ATTRIBUTE_UNUSED
)
8701 #else /* OBJ_ELF is defined. */
8703 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8705 /* Record a mapping symbol for alignment frags. We will delete this
8706 later if the alignment ends up empty. */
8707 if (!fragP
->tc_frag_data
.recorded
)
8708 fragP
->tc_frag_data
.recorded
= 1;
8710 /* PR 21809: Do not set a mapping state for debug sections
8711 - it just confuses other tools. */
8712 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8715 switch (fragP
->fr_type
)
8719 mapping_state_2 (MAP_DATA
, max_chars
);
8722 /* PR 20364: We can get alignment frags in code sections,
8723 so do not just assume that we should use the MAP_DATA state. */
8724 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8727 mapping_state_2 (MAP_INSN
, max_chars
);
8734 /* Whether SFrame stack trace info is supported. */
8737 aarch64_support_sframe_p (void)
8739 /* At this time, SFrame is supported for aarch64 only. */
8740 return (aarch64_abi
== AARCH64_ABI_LP64
);
8743 /* Specify if RA tracking is needed. */
8746 aarch64_sframe_ra_tracking_p (void)
8751 /* Specify the fixed offset to recover RA from CFA.
8752 (useful only when RA tracking is not needed). */
8755 aarch64_sframe_cfa_ra_offset (void)
8757 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8760 /* Get the abi/arch indentifier for SFrame. */
8763 aarch64_sframe_get_abi_arch (void)
8765 unsigned char sframe_abi_arch
= 0;
8767 if (aarch64_support_sframe_p ())
8769 sframe_abi_arch
= target_big_endian
8770 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8771 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8774 return sframe_abi_arch
;
8777 #endif /* OBJ_ELF */
8779 /* Initialize the DWARF-2 unwind information for this procedure. */
8782 tc_aarch64_frame_initial_instructions (void)
8784 cfi_add_CFA_def_cfa (REG_SP
, 0);
8787 /* Convert REGNAME to a DWARF-2 register number. */
8790 tc_aarch64_regname_to_dw2regnum (char *regname
)
8792 const reg_entry
*reg
= parse_reg (®name
);
8798 case REG_TYPE_SP_32
:
8799 case REG_TYPE_SP_64
:
8809 return reg
->number
+ 64;
8817 /* Implement DWARF2_ADDR_SIZE. */
8820 aarch64_dwarf2_addr_size (void)
8826 return bfd_arch_bits_per_address (stdoutput
) / 8;
8829 /* MD interface: Symbol and relocation handling. */
8831 /* Return the address within the segment that a PC-relative fixup is
8832 relative to. For AArch64 PC-relative fixups applied to instructions
8833 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8836 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8838 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8840 /* If this is pc-relative and we are going to emit a relocation
8841 then we just want to put out any pipeline compensation that the linker
8842 will need. Otherwise we want to use the calculated base. */
8844 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8845 || aarch64_force_relocation (fixP
)))
8848 /* AArch64 should be consistent for all pc-relative relocations. */
8849 return base
+ AARCH64_PCREL_OFFSET
;
8852 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8853 Otherwise we have no need to default values of symbols. */
8856 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8859 if (name
[0] == '_' && name
[1] == 'G'
8860 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8864 if (symbol_find (name
))
8865 as_bad (_("GOT already in the symbol table"));
8867 GOT_symbol
= symbol_new (name
, undefined_section
,
8868 &zero_address_frag
, 0);
8878 /* Return non-zero if the indicated VALUE has overflowed the maximum
8879 range expressible by a unsigned number with the indicated number of
8883 unsigned_overflow (valueT value
, unsigned bits
)
8886 if (bits
>= sizeof (valueT
) * 8)
8888 lim
= (valueT
) 1 << bits
;
8889 return (value
>= lim
);
8893 /* Return non-zero if the indicated VALUE has overflowed the maximum
8894 range expressible by an signed number with the indicated number of
8898 signed_overflow (offsetT value
, unsigned bits
)
8901 if (bits
>= sizeof (offsetT
) * 8)
8903 lim
= (offsetT
) 1 << (bits
- 1);
8904 return (value
< -lim
|| value
>= lim
);
8907 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8908 unsigned immediate offset load/store instruction, try to encode it as
8909 an unscaled, 9-bit, signed immediate offset load/store instruction.
8910 Return TRUE if it is successful; otherwise return FALSE.
8912 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8913 in response to the standard LDR/STR mnemonics when the immediate offset is
8914 unambiguous, i.e. when it is negative or unaligned. */
8917 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8920 enum aarch64_op new_op
;
8921 const aarch64_opcode
*new_opcode
;
8923 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8925 switch (instr
->opcode
->op
)
8927 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8928 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8929 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8930 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8931 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8932 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8933 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8934 case OP_STR_POS
: new_op
= OP_STUR
; break;
8935 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8936 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8937 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8938 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8939 default: new_op
= OP_NIL
; break;
8942 if (new_op
== OP_NIL
)
8945 new_opcode
= aarch64_get_opcode (new_op
);
8946 gas_assert (new_opcode
!= NULL
);
8948 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8949 instr
->opcode
->op
, new_opcode
->op
);
8951 aarch64_replace_opcode (instr
, new_opcode
);
8953 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8954 qualifier matching may fail because the out-of-date qualifier will
8955 prevent the operand being updated with a new and correct qualifier. */
8956 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8957 AARCH64_OPND_ADDR_SIMM9
);
8958 gas_assert (idx
== 1);
8959 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8961 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8963 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8970 /* Called by fix_insn to fix a MOV immediate alias instruction.
8972 Operand for a generic move immediate instruction, which is an alias
8973 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8974 a 32-bit/64-bit immediate value into general register. An assembler error
8975 shall result if the immediate cannot be created by a single one of these
8976 instructions. If there is a choice, then to ensure reversability an
8977 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8980 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8982 const aarch64_opcode
*opcode
;
8984 /* Need to check if the destination is SP/ZR. The check has to be done
8985 before any aarch64_replace_opcode. */
8986 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8987 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8989 instr
->operands
[1].imm
.value
= value
;
8990 instr
->operands
[1].skip
= 0;
8994 /* Try the MOVZ alias. */
8995 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8996 aarch64_replace_opcode (instr
, opcode
);
8997 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8998 &instr
->value
, NULL
, NULL
, insn_sequence
))
9000 put_aarch64_insn (buf
, instr
->value
);
9003 /* Try the MOVK alias. */
9004 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
9005 aarch64_replace_opcode (instr
, opcode
);
9006 if (aarch64_opcode_encode (instr
->opcode
, instr
,
9007 &instr
->value
, NULL
, NULL
, insn_sequence
))
9009 put_aarch64_insn (buf
, instr
->value
);
9014 if (try_mov_bitmask_p
)
9016 /* Try the ORR alias. */
9017 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
9018 aarch64_replace_opcode (instr
, opcode
);
9019 if (aarch64_opcode_encode (instr
->opcode
, instr
,
9020 &instr
->value
, NULL
, NULL
, insn_sequence
))
9022 put_aarch64_insn (buf
, instr
->value
);
9027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9028 _("immediate cannot be moved by a single instruction"));
9031 /* An instruction operand which is immediate related may have symbol used
9032 in the assembly, e.g.
9035 .set u32, 0x00ffff00
9037 At the time when the assembly instruction is parsed, a referenced symbol,
9038 like 'u32' in the above example may not have been seen; a fixS is created
9039 in such a case and is handled here after symbols have been resolved.
9040 Instruction is fixed up with VALUE using the information in *FIXP plus
9041 extra information in FLAGS.
9043 This function is called by md_apply_fix to fix up instructions that need
9044 a fix-up described above but does not involve any linker-time relocation. */
9047 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
9051 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9052 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
9053 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
9057 /* Now the instruction is about to be fixed-up, so the operand that
9058 was previously marked as 'ignored' needs to be unmarked in order
9059 to get the encoding done properly. */
9060 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
9061 new_inst
->operands
[idx
].skip
= 0;
9064 gas_assert (opnd
!= AARCH64_OPND_NIL
);
9068 case AARCH64_OPND_EXCEPTION
:
9069 case AARCH64_OPND_UNDEFINED
:
9070 if (unsigned_overflow (value
, 16))
9071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9072 _("immediate out of range"));
9073 insn
= get_aarch64_insn (buf
);
9074 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
9075 put_aarch64_insn (buf
, insn
);
9078 case AARCH64_OPND_AIMM
:
9079 /* ADD or SUB with immediate.
9080 NOTE this assumes we come here with a add/sub shifted reg encoding
9081 3 322|2222|2 2 2 21111 111111
9082 1 098|7654|3 2 1 09876 543210 98765 43210
9083 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
9084 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
9085 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
9086 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
9088 3 322|2222|2 2 221111111111
9089 1 098|7654|3 2 109876543210 98765 43210
9090 11000000 sf 001|0001|shift imm12 Rn Rd ADD
9091 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
9092 51000000 sf 101|0001|shift imm12 Rn Rd SUB
9093 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
9094 Fields sf Rn Rd are already set. */
9095 insn
= get_aarch64_insn (buf
);
9099 insn
= reencode_addsub_switch_add_sub (insn
);
9103 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
9104 && unsigned_overflow (value
, 12))
9106 /* Try to shift the value by 12 to make it fit. */
9107 if (((value
>> 12) << 12) == value
9108 && ! unsigned_overflow (value
, 12 + 12))
9111 insn
|= encode_addsub_imm_shift_amount (1);
9115 if (unsigned_overflow (value
, 12))
9116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9117 _("immediate out of range"));
9119 insn
|= encode_addsub_imm (value
);
9121 put_aarch64_insn (buf
, insn
);
9124 case AARCH64_OPND_SIMD_IMM
:
9125 case AARCH64_OPND_SIMD_IMM_SFT
:
9126 case AARCH64_OPND_LIMM
:
9127 /* Bit mask immediate. */
9128 gas_assert (new_inst
!= NULL
);
9129 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
9130 new_inst
->operands
[idx
].imm
.value
= value
;
9131 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9132 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9133 put_aarch64_insn (buf
, new_inst
->value
);
9135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9136 _("invalid immediate"));
9139 case AARCH64_OPND_HALF
:
9140 /* 16-bit unsigned immediate. */
9141 if (unsigned_overflow (value
, 16))
9142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9143 _("immediate out of range"));
9144 insn
= get_aarch64_insn (buf
);
9145 insn
|= encode_movw_imm (value
& 0xffff);
9146 put_aarch64_insn (buf
, insn
);
9149 case AARCH64_OPND_IMM_MOV
:
9150 /* Operand for a generic move immediate instruction, which is
9151 an alias instruction that generates a single MOVZ, MOVN or ORR
9152 instruction to loads a 32-bit/64-bit immediate value into general
9153 register. An assembler error shall result if the immediate cannot be
9154 created by a single one of these instructions. If there is a choice,
9155 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
9156 and MOVZ or MOVN to ORR. */
9157 gas_assert (new_inst
!= NULL
);
9158 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
9161 case AARCH64_OPND_ADDR_SIMM7
:
9162 case AARCH64_OPND_ADDR_SIMM9
:
9163 case AARCH64_OPND_ADDR_SIMM9_2
:
9164 case AARCH64_OPND_ADDR_SIMM10
:
9165 case AARCH64_OPND_ADDR_UIMM12
:
9166 case AARCH64_OPND_ADDR_SIMM11
:
9167 case AARCH64_OPND_ADDR_SIMM13
:
9168 /* Immediate offset in an address. */
9169 insn
= get_aarch64_insn (buf
);
9171 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
9172 gas_assert (new_inst
->opcode
->operands
[1] == opnd
9173 || new_inst
->opcode
->operands
[2] == opnd
);
9175 /* Get the index of the address operand. */
9176 if (new_inst
->opcode
->operands
[1] == opnd
)
9177 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
9180 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
9183 /* Update the resolved offset value. */
9184 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
9186 /* Encode/fix-up. */
9187 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
9188 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
9190 put_aarch64_insn (buf
, new_inst
->value
);
9193 else if (new_inst
->opcode
->iclass
== ldst_pos
9194 && try_to_encode_as_unscaled_ldst (new_inst
))
9196 put_aarch64_insn (buf
, new_inst
->value
);
9200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9201 _("immediate offset out of range"));
9206 as_fatal (_("unhandled operand code %d"), opnd
);
9210 /* Apply a fixup (fixP) to segment data, once it has been determined
9211 by our caller that we have all the info we need to fix it up.
9213 Parameter valP is the pointer to the value of the bits. */
9216 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
9218 offsetT value
= *valP
;
9220 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9222 unsigned flags
= fixP
->fx_addnumber
;
9224 DEBUG_TRACE ("\n\n");
9225 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
9226 DEBUG_TRACE ("Enter md_apply_fix");
9228 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
9230 /* Note whether this will delete the relocation. */
9232 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
9233 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
9236 /* Process the relocations. */
9237 switch (fixP
->fx_r_type
)
9239 case BFD_RELOC_NONE
:
9240 /* This will need to go in the object file. */
9245 case BFD_RELOC_8_PCREL
:
9246 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9247 md_number_to_chars (buf
, value
, 1);
9251 case BFD_RELOC_16_PCREL
:
9252 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9253 md_number_to_chars (buf
, value
, 2);
9257 case BFD_RELOC_32_PCREL
:
9258 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9259 md_number_to_chars (buf
, value
, 4);
9263 case BFD_RELOC_64_PCREL
:
9264 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9265 md_number_to_chars (buf
, value
, 8);
9268 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9269 /* We claim that these fixups have been processed here, even if
9270 in fact we generate an error because we do not have a reloc
9271 for them, so tc_gen_reloc() will reject them. */
9273 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
9275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9276 _("undefined symbol %s used as an immediate value"),
9277 S_GET_NAME (fixP
->fx_addsy
));
9278 goto apply_fix_return
;
9280 fix_insn (fixP
, flags
, value
);
9283 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
9284 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9288 _("pc-relative load offset not word aligned"));
9289 if (signed_overflow (value
, 21))
9290 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9291 _("pc-relative load offset out of range"));
9292 insn
= get_aarch64_insn (buf
);
9293 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9294 put_aarch64_insn (buf
, insn
);
9298 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9299 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9301 if (signed_overflow (value
, 21))
9302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9303 _("pc-relative address offset out of range"));
9304 insn
= get_aarch64_insn (buf
);
9305 insn
|= encode_adr_imm (value
);
9306 put_aarch64_insn (buf
, insn
);
9310 case BFD_RELOC_AARCH64_BRANCH19
:
9311 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9315 _("conditional branch target not word aligned"));
9316 if (signed_overflow (value
, 21))
9317 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9318 _("conditional branch out of range"));
9319 insn
= get_aarch64_insn (buf
);
9320 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9321 put_aarch64_insn (buf
, insn
);
9325 case BFD_RELOC_AARCH64_TSTBR14
:
9326 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9330 _("conditional branch target not word aligned"));
9331 if (signed_overflow (value
, 16))
9332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9333 _("conditional branch out of range"));
9334 insn
= get_aarch64_insn (buf
);
9335 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9336 put_aarch64_insn (buf
, insn
);
9340 case BFD_RELOC_AARCH64_CALL26
:
9341 case BFD_RELOC_AARCH64_JUMP26
:
9342 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9346 _("branch target not word aligned"));
9347 if (signed_overflow (value
, 28))
9348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9349 _("branch out of range"));
9350 insn
= get_aarch64_insn (buf
);
9351 insn
|= encode_branch_ofs_26 (value
>> 2);
9352 put_aarch64_insn (buf
, insn
);
9356 case BFD_RELOC_AARCH64_MOVW_G0
:
9357 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9358 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9359 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9360 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9361 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9364 case BFD_RELOC_AARCH64_MOVW_G1
:
9365 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9366 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9367 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9368 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9369 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9372 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9374 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9375 /* Should always be exported to object file, see
9376 aarch64_force_relocation(). */
9377 gas_assert (!fixP
->fx_done
);
9378 gas_assert (seg
->use_rela_p
);
9380 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9382 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9383 /* Should always be exported to object file, see
9384 aarch64_force_relocation(). */
9385 gas_assert (!fixP
->fx_done
);
9386 gas_assert (seg
->use_rela_p
);
9388 case BFD_RELOC_AARCH64_MOVW_G2
:
9389 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9390 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9391 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9392 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9395 case BFD_RELOC_AARCH64_MOVW_G3
:
9396 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9399 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9401 insn
= get_aarch64_insn (buf
);
9405 /* REL signed addend must fit in 16 bits */
9406 if (signed_overflow (value
, 16))
9407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9408 _("offset out of range"));
9412 /* Check for overflow and scale. */
9413 switch (fixP
->fx_r_type
)
9415 case BFD_RELOC_AARCH64_MOVW_G0
:
9416 case BFD_RELOC_AARCH64_MOVW_G1
:
9417 case BFD_RELOC_AARCH64_MOVW_G2
:
9418 case BFD_RELOC_AARCH64_MOVW_G3
:
9419 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9420 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9421 if (unsigned_overflow (value
, scale
+ 16))
9422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9423 _("unsigned value out of range"));
9425 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9426 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9427 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9428 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9429 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9430 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9431 /* NOTE: We can only come here with movz or movn. */
9432 if (signed_overflow (value
, scale
+ 16))
9433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9434 _("signed value out of range"));
9437 /* Force use of MOVN. */
9439 insn
= reencode_movzn_to_movn (insn
);
9443 /* Force use of MOVZ. */
9444 insn
= reencode_movzn_to_movz (insn
);
9448 /* Unchecked relocations. */
9454 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9455 insn
|= encode_movw_imm (value
& 0xffff);
9457 put_aarch64_insn (buf
, insn
);
9461 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9462 fixP
->fx_r_type
= (ilp32_p
9463 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9464 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9465 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9466 /* Should always be exported to object file, see
9467 aarch64_force_relocation(). */
9468 gas_assert (!fixP
->fx_done
);
9469 gas_assert (seg
->use_rela_p
);
9472 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9473 fixP
->fx_r_type
= (ilp32_p
9474 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9475 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9476 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9477 /* Should always be exported to object file, see
9478 aarch64_force_relocation(). */
9479 gas_assert (!fixP
->fx_done
);
9480 gas_assert (seg
->use_rela_p
);
9483 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9484 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9485 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9486 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9487 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9488 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9489 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9490 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9491 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9492 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9493 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9494 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9495 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9496 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9497 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9498 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9499 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9500 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9501 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9502 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9503 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9504 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9505 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9506 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9507 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9508 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9509 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9510 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9511 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9512 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9513 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9514 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9515 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9516 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9517 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9518 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9519 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9520 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9521 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9522 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9523 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9524 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9525 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9526 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9527 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9528 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9529 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9530 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9531 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9532 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9533 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9534 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9535 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9536 /* Should always be exported to object file, see
9537 aarch64_force_relocation(). */
9538 gas_assert (!fixP
->fx_done
);
9539 gas_assert (seg
->use_rela_p
);
9542 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9543 /* Should always be exported to object file, see
9544 aarch64_force_relocation(). */
9545 fixP
->fx_r_type
= (ilp32_p
9546 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9547 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9548 gas_assert (!fixP
->fx_done
);
9549 gas_assert (seg
->use_rela_p
);
9552 case BFD_RELOC_AARCH64_ADD_LO12
:
9553 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9554 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9555 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9556 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9557 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9558 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9559 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9560 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9561 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9562 case BFD_RELOC_AARCH64_LDST128_LO12
:
9563 case BFD_RELOC_AARCH64_LDST16_LO12
:
9564 case BFD_RELOC_AARCH64_LDST32_LO12
:
9565 case BFD_RELOC_AARCH64_LDST64_LO12
:
9566 case BFD_RELOC_AARCH64_LDST8_LO12
:
9567 /* Should always be exported to object file, see
9568 aarch64_force_relocation(). */
9569 gas_assert (!fixP
->fx_done
);
9570 gas_assert (seg
->use_rela_p
);
9573 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9574 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9575 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9578 case BFD_RELOC_UNUSED
:
9579 /* An error will already have been reported. */
9583 case BFD_RELOC_32_SECREL
:
9584 case BFD_RELOC_16_SECIDX
:
9588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9589 _("unexpected %s fixup"),
9590 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9595 /* Free the allocated the struct aarch64_inst.
9596 N.B. currently there are very limited number of fix-up types actually use
9597 this field, so the impact on the performance should be minimal . */
9598 free (fixP
->tc_fix_data
.inst
);
9603 /* Translate internal representation of relocation info to BFD target
9607 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9610 bfd_reloc_code_real_type code
;
9612 reloc
= XNEW (arelent
);
9614 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9615 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9616 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9620 if (section
->use_rela_p
)
9621 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9623 fixp
->fx_offset
= reloc
->address
;
9625 reloc
->addend
= fixp
->fx_offset
;
9627 code
= fixp
->fx_r_type
;
9632 code
= BFD_RELOC_16_PCREL
;
9637 code
= BFD_RELOC_32_PCREL
;
9642 code
= BFD_RELOC_64_PCREL
;
9649 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9650 if (reloc
->howto
== NULL
)
9652 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9654 ("cannot represent %s relocation in this object file format"),
9655 bfd_get_reloc_code_name (code
));
9662 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9665 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9667 bfd_reloc_code_real_type type
;
9671 if (exp
->X_op
== O_secrel
)
9673 exp
->X_op
= O_symbol
;
9674 type
= BFD_RELOC_32_SECREL
;
9676 else if (exp
->X_op
== O_secidx
)
9678 exp
->X_op
= O_symbol
;
9679 type
= BFD_RELOC_16_SECIDX
;
9685 FIXME: @@ Should look at CPU word size. */
9692 type
= BFD_RELOC_16
;
9695 type
= BFD_RELOC_32
;
9698 type
= BFD_RELOC_64
;
9701 as_bad (_("cannot do %u-byte relocation"), size
);
9702 type
= BFD_RELOC_UNUSED
;
9709 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9712 /* Implement md_after_parse_args. This is the earliest time we need to decide
9713 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9716 aarch64_after_parse_args (void)
9718 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9722 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9723 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9724 aarch64_abi
= AARCH64_ABI_ILP32
;
9726 aarch64_abi
= AARCH64_ABI_LP64
;
9728 aarch64_abi
= AARCH64_ABI_LLP64
;
9734 elf64_aarch64_target_format (void)
9737 /* FIXME: What to do for ilp32_p ? */
9738 if (target_big_endian
)
9739 return "elf64-bigaarch64-cloudabi";
9741 return "elf64-littleaarch64-cloudabi";
9743 if (target_big_endian
)
9744 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9746 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9751 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9753 elf_frob_symbol (symp
, puntp
);
9755 #elif defined OBJ_COFF
9757 coff_aarch64_target_format (void)
9759 return "pe-aarch64-little";
9763 /* MD interface: Finalization. */
9765 /* A good place to do this, although this was probably not intended
9766 for this kind of use. We need to dump the literal pool before
9767 references are made to a null symbol pointer. */
9770 aarch64_cleanup (void)
9774 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9776 /* Put it at the end of the relevant section. */
9777 subseg_set (pool
->section
, pool
->sub_section
);
9783 /* Remove any excess mapping symbols generated for alignment frags in
9784 SEC. We may have created a mapping symbol before a zero byte
9785 alignment; remove it if there's a mapping symbol after the
9788 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9789 void *dummy ATTRIBUTE_UNUSED
)
9791 segment_info_type
*seginfo
= seg_info (sec
);
9794 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9797 for (fragp
= seginfo
->frchainP
->frch_root
;
9798 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9800 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9801 fragS
*next
= fragp
->fr_next
;
9803 /* Variable-sized frags have been converted to fixed size by
9804 this point. But if this was variable-sized to start with,
9805 there will be a fixed-size frag after it. So don't handle
9807 if (sym
== NULL
|| next
== NULL
)
9810 if (S_GET_VALUE (sym
) < next
->fr_address
)
9811 /* Not at the end of this frag. */
9813 know (S_GET_VALUE (sym
) == next
->fr_address
);
9817 if (next
->tc_frag_data
.first_map
!= NULL
)
9819 /* Next frag starts with a mapping symbol. Discard this
9821 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9825 if (next
->fr_next
== NULL
)
9827 /* This mapping symbol is at the end of the section. Discard
9829 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9830 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9834 /* As long as we have empty frags without any mapping symbols,
9836 /* If the next frag is non-empty and does not start with a
9837 mapping symbol, then this mapping symbol is required. */
9838 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9841 next
= next
->fr_next
;
9843 while (next
!= NULL
);
9848 /* Adjust the symbol table. */
9851 aarch64_adjust_symtab (void)
9854 /* Remove any overlapping mapping symbols generated by alignment frags. */
9855 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9856 /* Now do generic ELF adjustments. */
9857 elf_adjust_symtab ();
9862 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9864 str_hash_insert (table
, key
, value
, 0);
9868 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9870 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9871 checked_hash_insert (table
, key
, value
);
9875 fill_instruction_hash_table (void)
9877 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9879 while (opcode
->name
!= NULL
)
9881 templates
*templ
, *new_templ
;
9882 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9884 new_templ
= XNEW (templates
);
9885 new_templ
->opcode
= opcode
;
9886 new_templ
->next
= NULL
;
9889 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9892 new_templ
->next
= templ
->next
;
9893 templ
->next
= new_templ
;
9900 convert_to_upper (char *dst
, const char *src
, size_t num
)
9903 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9904 *dst
= TOUPPER (*src
);
9908 /* Assume STR point to a lower-case string, allocate, convert and return
9909 the corresponding upper-case string. */
9910 static inline const char*
9911 get_upper_str (const char *str
)
9914 size_t len
= strlen (str
);
9915 ret
= XNEWVEC (char, len
+ 1);
9916 convert_to_upper (ret
, str
, len
);
9920 /* MD interface: Initialization. */
9928 aarch64_ops_hsh
= str_htab_create ();
9929 aarch64_cond_hsh
= str_htab_create ();
9930 aarch64_shift_hsh
= str_htab_create ();
9931 aarch64_sys_regs_hsh
= str_htab_create ();
9932 aarch64_pstatefield_hsh
= str_htab_create ();
9933 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9934 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9935 aarch64_sys_regs_at_hsh
= str_htab_create ();
9936 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9937 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9938 aarch64_reg_hsh
= str_htab_create ();
9939 aarch64_barrier_opt_hsh
= str_htab_create ();
9940 aarch64_nzcv_hsh
= str_htab_create ();
9941 aarch64_pldop_hsh
= str_htab_create ();
9942 aarch64_hint_opt_hsh
= str_htab_create ();
9944 fill_instruction_hash_table ();
9946 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9947 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9948 (void *) (aarch64_sys_regs
+ i
));
9950 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9951 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9952 aarch64_pstatefields
[i
].name
,
9953 (void *) (aarch64_pstatefields
+ i
));
9955 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9956 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9957 aarch64_sys_regs_ic
[i
].name
,
9958 (void *) (aarch64_sys_regs_ic
+ i
));
9960 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9961 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9962 aarch64_sys_regs_dc
[i
].name
,
9963 (void *) (aarch64_sys_regs_dc
+ i
));
9965 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9966 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9967 aarch64_sys_regs_at
[i
].name
,
9968 (void *) (aarch64_sys_regs_at
+ i
));
9970 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9971 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9972 aarch64_sys_regs_tlbi
[i
].name
,
9973 (void *) (aarch64_sys_regs_tlbi
+ i
));
9975 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9976 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9977 aarch64_sys_regs_sr
[i
].name
,
9978 (void *) (aarch64_sys_regs_sr
+ i
));
9980 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9981 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9982 (void *) (reg_names
+ i
));
9984 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9985 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9986 (void *) (nzcv_names
+ i
));
9988 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9990 const char *name
= aarch64_operand_modifiers
[i
].name
;
9991 checked_hash_insert (aarch64_shift_hsh
, name
,
9992 (void *) (aarch64_operand_modifiers
+ i
));
9993 /* Also hash the name in the upper case. */
9994 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9995 (void *) (aarch64_operand_modifiers
+ i
));
9998 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
10001 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
10002 the same condition code. */
10003 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
10005 const char *name
= aarch64_conds
[i
].names
[j
];
10008 checked_hash_insert (aarch64_cond_hsh
, name
,
10009 (void *) (aarch64_conds
+ i
));
10010 /* Also hash the name in the upper case. */
10011 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
10012 (void *) (aarch64_conds
+ i
));
10016 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
10018 const char *name
= aarch64_barrier_options
[i
].name
;
10019 /* Skip xx00 - the unallocated values of option. */
10020 if ((i
& 0x3) == 0)
10022 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
10023 (void *) (aarch64_barrier_options
+ i
));
10024 /* Also hash the name in the upper case. */
10025 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
10026 (void *) (aarch64_barrier_options
+ i
));
10029 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
10031 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
10032 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
10033 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
10034 /* Also hash the name in the upper case. */
10035 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
10036 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
10039 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
10041 const char* name
= aarch64_prfops
[i
].name
;
10042 /* Skip the unallocated hint encodings. */
10045 checked_hash_insert (aarch64_pldop_hsh
, name
,
10046 (void *) (aarch64_prfops
+ i
));
10047 /* Also hash the name in the upper case. */
10048 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
10049 (void *) (aarch64_prfops
+ i
));
10052 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
10054 const char* name
= aarch64_hint_options
[i
].name
;
10055 const char* upper_name
= get_upper_str(name
);
10057 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
10058 (void *) (aarch64_hint_options
+ i
));
10060 /* Also hash the name in the upper case if not the same. */
10061 if (strcmp (name
, upper_name
) != 0)
10062 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
10063 (void *) (aarch64_hint_options
+ i
));
10066 /* Set the cpu variant based on the command-line options. */
10068 mcpu_cpu_opt
= march_cpu_opt
;
10071 mcpu_cpu_opt
= &cpu_default
;
10073 cpu_variant
= *mcpu_cpu_opt
;
10075 /* Record the CPU type. */
10077 mach
= bfd_mach_aarch64_ilp32
;
10079 mach
= bfd_mach_aarch64_llp64
;
10081 mach
= bfd_mach_aarch64
;
10083 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
10085 /* FIXME - is there a better way to do it ? */
10086 aarch64_sframe_cfa_sp_reg
= 31;
10087 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
10088 aarch64_sframe_cfa_ra_reg
= 30;
10092 /* Command line processing. */
10094 const char *md_shortopts
= "m:";
10096 #ifdef AARCH64_BI_ENDIAN
10097 #define OPTION_EB (OPTION_MD_BASE + 0)
10098 #define OPTION_EL (OPTION_MD_BASE + 1)
10100 #if TARGET_BYTES_BIG_ENDIAN
10101 #define OPTION_EB (OPTION_MD_BASE + 0)
10103 #define OPTION_EL (OPTION_MD_BASE + 1)
10107 struct option md_longopts
[] = {
10109 {"EB", no_argument
, NULL
, OPTION_EB
},
10112 {"EL", no_argument
, NULL
, OPTION_EL
},
10114 {NULL
, no_argument
, NULL
, 0}
10117 size_t md_longopts_size
= sizeof (md_longopts
);
10119 struct aarch64_option_table
10121 const char *option
; /* Option name to match. */
10122 const char *help
; /* Help information. */
10123 int *var
; /* Variable to change. */
10124 int value
; /* What to change it to. */
10125 char *deprecated
; /* If non-null, print this message. */
10128 static struct aarch64_option_table aarch64_opts
[] = {
10129 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
10130 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
10132 #ifdef DEBUG_AARCH64
10133 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
10134 #endif /* DEBUG_AARCH64 */
10135 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
10137 {"mno-verbose-error", N_("do not output verbose error messages"),
10138 &verbose_error_p
, 0, NULL
},
10139 {NULL
, NULL
, NULL
, 0, NULL
}
10142 struct aarch64_cpu_option_table
10145 const aarch64_feature_set value
;
10146 /* The canonical name of the CPU, or NULL to use NAME converted to upper
10148 const char *canonical_name
;
10151 /* This list should, at a minimum, contain all the cpu names
10152 recognized by GCC. */
10153 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
10154 {"all", AARCH64_ANY
, NULL
},
10155 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10156 AARCH64_FEATURE_CRC
), "Cortex-A34"},
10157 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10158 AARCH64_FEATURE_CRC
), "Cortex-A35"},
10159 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10160 AARCH64_FEATURE_CRC
), "Cortex-A53"},
10161 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10162 AARCH64_FEATURE_CRC
), "Cortex-A57"},
10163 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10164 AARCH64_FEATURE_CRC
), "Cortex-A72"},
10165 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10166 AARCH64_FEATURE_CRC
), "Cortex-A73"},
10167 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10168 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10170 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10171 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10173 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10174 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
10176 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10177 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10178 | AARCH64_FEATURE_DOTPROD
10179 | AARCH64_FEATURE_SSBS
),
10181 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10182 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10183 | AARCH64_FEATURE_DOTPROD
10184 | AARCH64_FEATURE_SSBS
),
10186 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10187 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10188 | AARCH64_FEATURE_DOTPROD
10189 | AARCH64_FEATURE_SSBS
),
10191 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10192 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
10193 | AARCH64_FEATURE_DOTPROD
10194 | AARCH64_FEATURE_SSBS
),
10196 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10197 AARCH64_FEATURE_F16
10198 | AARCH64_FEATURE_RCPC
10199 | AARCH64_FEATURE_DOTPROD
10200 | AARCH64_FEATURE_SSBS
10201 | AARCH64_FEATURE_PROFILE
),
10203 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10204 AARCH64_FEATURE_F16
10205 | AARCH64_FEATURE_RCPC
10206 | AARCH64_FEATURE_DOTPROD
10207 | AARCH64_FEATURE_SSBS
10208 | AARCH64_FEATURE_PROFILE
),
10210 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10211 AARCH64_FEATURE_DOTPROD
10212 | AARCH64_FEATURE_F16
10213 | AARCH64_FEATURE_FLAGM
10214 | AARCH64_FEATURE_PAC
10215 | AARCH64_FEATURE_PROFILE
10216 | AARCH64_FEATURE_RCPC
10217 | AARCH64_FEATURE_SSBS
),
10219 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10220 AARCH64_FEATURE_BFLOAT16
10221 | AARCH64_FEATURE_I8MM
10222 | AARCH64_FEATURE_MEMTAG
10223 | AARCH64_FEATURE_SVE2_BITPERM
),
10225 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10226 AARCH64_FEATURE_BFLOAT16
10227 | AARCH64_FEATURE_I8MM
10228 | AARCH64_FEATURE_MEMTAG
10229 | AARCH64_FEATURE_SVE2_BITPERM
),
10231 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10232 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10233 | AARCH64_FEATURE_DOTPROD
10234 | AARCH64_FEATURE_PROFILE
),
10236 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10237 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10238 "Samsung Exynos M1"},
10239 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10240 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10241 | AARCH64_FEATURE_RDMA
),
10242 "Qualcomm Falkor"},
10243 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10244 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10245 | AARCH64_FEATURE_DOTPROD
10246 | AARCH64_FEATURE_SSBS
),
10248 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10249 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
10250 | AARCH64_FEATURE_DOTPROD
10251 | AARCH64_FEATURE_PROFILE
),
10253 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
10254 AARCH64_FEATURE_BFLOAT16
10255 | AARCH64_FEATURE_I8MM
10256 | AARCH64_FEATURE_F16
10257 | AARCH64_FEATURE_SVE
10258 | AARCH64_FEATURE_SVE2
10259 | AARCH64_FEATURE_SVE2_BITPERM
10260 | AARCH64_FEATURE_MEMTAG
10261 | AARCH64_FEATURE_RNG
),
10263 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10264 AARCH64_FEATURE_PROFILE
10265 | AARCH64_FEATURE_CVADP
10266 | AARCH64_FEATURE_SVE
10267 | AARCH64_FEATURE_SSBS
10268 | AARCH64_FEATURE_RNG
10269 | AARCH64_FEATURE_F16
10270 | AARCH64_FEATURE_BFLOAT16
10271 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
10272 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10273 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10274 | AARCH64_FEATURE_RDMA
),
10275 "Qualcomm QDF24XX"},
10276 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10277 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
10278 "Qualcomm Saphira"},
10279 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10280 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10281 "Cavium ThunderX"},
10282 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
10283 AARCH64_FEATURE_CRYPTO
),
10284 "Broadcom Vulcan"},
10285 /* The 'xgene-1' name is an older name for 'xgene1', which was used
10286 in earlier releases and is superseded by 'xgene1' in all
10288 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10289 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10290 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10291 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10292 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10293 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10294 AARCH64_FEATURE_F16
10295 | AARCH64_FEATURE_RCPC
10296 | AARCH64_FEATURE_DOTPROD
10297 | AARCH64_FEATURE_SSBS
10298 | AARCH64_FEATURE_PROFILE
),
10300 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10301 AARCH64_FEATURE_BFLOAT16
10302 | AARCH64_FEATURE_I8MM
10303 | AARCH64_FEATURE_MEMTAG
10304 | AARCH64_FEATURE_SVE2_BITPERM
),
10306 {"generic", AARCH64_ARCH_V8
, NULL
},
10308 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10311 struct aarch64_arch_option_table
10314 const aarch64_feature_set value
;
10317 /* This list should, at a minimum, contain all the architecture names
10318 recognized by GCC. */
10319 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10320 {"all", AARCH64_ANY
},
10321 {"armv8-a", AARCH64_ARCH_V8
},
10322 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10323 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10324 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10325 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10326 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10327 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10328 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10329 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10330 {"armv8-r", AARCH64_ARCH_V8_R
},
10331 {"armv9-a", AARCH64_ARCH_V9
},
10332 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10333 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10334 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10335 {NULL
, AARCH64_ARCH_NONE
}
10338 /* ISA extensions. */
10339 struct aarch64_option_cpu_value_table
10342 const aarch64_feature_set value
;
10343 const aarch64_feature_set require
; /* Feature dependencies. */
10346 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10347 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10348 AARCH64_ARCH_NONE
},
10349 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10350 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10351 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10352 AARCH64_ARCH_NONE
},
10353 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10354 AARCH64_ARCH_NONE
},
10355 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10356 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10357 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10358 AARCH64_ARCH_NONE
},
10359 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10360 AARCH64_ARCH_NONE
},
10361 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10362 AARCH64_ARCH_NONE
},
10363 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10364 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10365 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10366 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10367 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10368 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10369 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10370 AARCH64_ARCH_NONE
},
10371 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10372 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10373 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10374 AARCH64_ARCH_NONE
},
10375 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10376 AARCH64_FEATURE (AARCH64_FEATURE_F16
10377 | AARCH64_FEATURE_SIMD
, 0)},
10378 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10379 AARCH64_ARCH_NONE
},
10380 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10381 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10382 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10383 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10384 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10385 AARCH64_ARCH_NONE
},
10386 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10387 AARCH64_ARCH_NONE
},
10388 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10389 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10390 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10391 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10392 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10393 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10394 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10395 AARCH64_ARCH_NONE
},
10396 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10397 AARCH64_ARCH_NONE
},
10398 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10399 AARCH64_ARCH_NONE
},
10400 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10401 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10402 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10403 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10404 | AARCH64_FEATURE_SM4
, 0)},
10405 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10406 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10407 | AARCH64_FEATURE_AES
, 0)},
10408 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10409 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10410 | AARCH64_FEATURE_SHA3
, 0)},
10411 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10412 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10413 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10414 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10415 | AARCH64_FEATURE_BFLOAT16
, 0)},
10416 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10417 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10418 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10419 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10420 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10421 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10422 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10423 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10424 {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2
, 0),
10425 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10426 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10427 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10428 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10429 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10430 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10431 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10432 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10433 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10434 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10435 AARCH64_ARCH_NONE
},
10436 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10437 AARCH64_ARCH_NONE
},
10438 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10439 AARCH64_ARCH_NONE
},
10440 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10441 AARCH64_ARCH_NONE
},
10442 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10443 AARCH64_ARCH_NONE
},
10444 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10445 AARCH64_ARCH_NONE
},
10446 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10449 struct aarch64_long_option_table
10451 const char *option
; /* Substring to match. */
10452 const char *help
; /* Help information. */
10453 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10454 char *deprecated
; /* If non-null, print this message. */
10457 /* Transitive closure of features depending on set. */
10458 static aarch64_feature_set
10459 aarch64_feature_disable_set (aarch64_feature_set set
)
10461 const struct aarch64_option_cpu_value_table
*opt
;
10462 aarch64_feature_set prev
= 0;
10464 while (prev
!= set
) {
10466 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10467 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10468 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10473 /* Transitive closure of dependencies of set. */
10474 static aarch64_feature_set
10475 aarch64_feature_enable_set (aarch64_feature_set set
)
10477 const struct aarch64_option_cpu_value_table
*opt
;
10478 aarch64_feature_set prev
= 0;
10480 while (prev
!= set
) {
10482 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10483 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10484 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10490 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10493 /* We insist on extensions being added before being removed. We achieve
10494 this by using the ADDING_VALUE variable to indicate whether we are
10495 adding an extension (1) or removing it (0) and only allowing it to
10496 change in the order -1 -> 1 -> 0. */
10497 int adding_value
= -1;
10498 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10500 /* Copy the feature set, so that we can modify it. */
10501 *ext_set
= **opt_p
;
10504 while (str
!= NULL
&& *str
!= 0)
10506 const struct aarch64_option_cpu_value_table
*opt
;
10507 const char *ext
= NULL
;
10514 as_bad (_("invalid architectural extension"));
10518 ext
= strchr (++str
, '+');
10522 optlen
= ext
- str
;
10524 optlen
= strlen (str
);
10526 if (optlen
>= 2 && startswith (str
, "no"))
10528 if (adding_value
!= 0)
10533 else if (optlen
> 0)
10535 if (adding_value
== -1)
10537 else if (adding_value
!= 1)
10539 as_bad (_("must specify extensions to add before specifying "
10540 "those to remove"));
10547 as_bad (_("missing architectural extension"));
10551 gas_assert (adding_value
!= -1);
10553 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10554 if (strncmp (opt
->name
, str
, optlen
) == 0)
10556 aarch64_feature_set set
;
10558 /* Add or remove the extension. */
10561 set
= aarch64_feature_enable_set (opt
->value
);
10562 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10566 set
= aarch64_feature_disable_set (opt
->value
);
10567 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10572 if (opt
->name
== NULL
)
10574 as_bad (_("unknown architectural extension `%s'"), str
);
10585 aarch64_parse_cpu (const char *str
)
10587 const struct aarch64_cpu_option_table
*opt
;
10588 const char *ext
= strchr (str
, '+');
10592 optlen
= ext
- str
;
10594 optlen
= strlen (str
);
10598 as_bad (_("missing cpu name `%s'"), str
);
10602 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10603 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10605 mcpu_cpu_opt
= &opt
->value
;
10607 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10612 as_bad (_("unknown cpu `%s'"), str
);
10617 aarch64_parse_arch (const char *str
)
10619 const struct aarch64_arch_option_table
*opt
;
10620 const char *ext
= strchr (str
, '+');
10624 optlen
= ext
- str
;
10626 optlen
= strlen (str
);
10630 as_bad (_("missing architecture name `%s'"), str
);
10634 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10635 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10637 march_cpu_opt
= &opt
->value
;
10639 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10644 as_bad (_("unknown architecture `%s'\n"), str
);
10649 struct aarch64_option_abi_value_table
10652 enum aarch64_abi_type value
;
10655 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10657 {"ilp32", AARCH64_ABI_ILP32
},
10658 {"lp64", AARCH64_ABI_LP64
},
10660 {"llp64", AARCH64_ABI_LLP64
},
10665 aarch64_parse_abi (const char *str
)
10669 if (str
[0] == '\0')
10671 as_bad (_("missing abi name `%s'"), str
);
10675 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10676 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10678 aarch64_abi
= aarch64_abis
[i
].value
;
10682 as_bad (_("unknown abi `%s'\n"), str
);
10686 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10687 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10688 aarch64_parse_abi
, NULL
},
10689 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10690 aarch64_parse_cpu
, NULL
},
10691 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10692 aarch64_parse_arch
, NULL
},
10693 {NULL
, NULL
, 0, NULL
}
10697 md_parse_option (int c
, const char *arg
)
10699 struct aarch64_option_table
*opt
;
10700 struct aarch64_long_option_table
*lopt
;
10706 target_big_endian
= 1;
10712 target_big_endian
= 0;
10717 /* Listing option. Just ignore these, we don't support additional
10722 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10724 if (c
== opt
->option
[0]
10725 && ((arg
== NULL
&& opt
->option
[1] == 0)
10726 || streq (arg
, opt
->option
+ 1)))
10728 /* If the option is deprecated, tell the user. */
10729 if (opt
->deprecated
!= NULL
)
10730 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10731 arg
? arg
: "", _(opt
->deprecated
));
10733 if (opt
->var
!= NULL
)
10734 *opt
->var
= opt
->value
;
10740 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10742 /* These options are expected to have an argument. */
10743 if (c
== lopt
->option
[0]
10745 && startswith (arg
, lopt
->option
+ 1))
10747 /* If the option is deprecated, tell the user. */
10748 if (lopt
->deprecated
!= NULL
)
10749 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10750 _(lopt
->deprecated
));
10752 /* Call the sup-option parser. */
10753 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10764 md_show_usage (FILE * fp
)
10766 struct aarch64_option_table
*opt
;
10767 struct aarch64_long_option_table
*lopt
;
10769 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10771 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10772 if (opt
->help
!= NULL
)
10773 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10775 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10776 if (lopt
->help
!= NULL
)
10777 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10781 -EB assemble code for a big-endian cpu\n"));
10786 -EL assemble code for a little-endian cpu\n"));
10790 /* Parse a .cpu directive. */
10793 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10795 const struct aarch64_cpu_option_table
*opt
;
10801 name
= input_line_pointer
;
10802 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10803 saved_char
= *input_line_pointer
;
10804 *input_line_pointer
= 0;
10806 ext
= strchr (name
, '+');
10809 optlen
= ext
- name
;
10811 optlen
= strlen (name
);
10813 /* Skip the first "all" entry. */
10814 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10815 if (strlen (opt
->name
) == optlen
10816 && strncmp (name
, opt
->name
, optlen
) == 0)
10818 mcpu_cpu_opt
= &opt
->value
;
10820 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10823 cpu_variant
= *mcpu_cpu_opt
;
10825 *input_line_pointer
= saved_char
;
10826 demand_empty_rest_of_line ();
10829 as_bad (_("unknown cpu `%s'"), name
);
10830 *input_line_pointer
= saved_char
;
10831 ignore_rest_of_line ();
10835 /* Parse a .arch directive. */
10838 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10840 const struct aarch64_arch_option_table
*opt
;
10846 name
= input_line_pointer
;
10847 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10848 saved_char
= *input_line_pointer
;
10849 *input_line_pointer
= 0;
10851 ext
= strchr (name
, '+');
10854 optlen
= ext
- name
;
10856 optlen
= strlen (name
);
10858 /* Skip the first "all" entry. */
10859 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10860 if (strlen (opt
->name
) == optlen
10861 && strncmp (name
, opt
->name
, optlen
) == 0)
10863 mcpu_cpu_opt
= &opt
->value
;
10865 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10868 cpu_variant
= *mcpu_cpu_opt
;
10870 *input_line_pointer
= saved_char
;
10871 demand_empty_rest_of_line ();
10875 as_bad (_("unknown architecture `%s'\n"), name
);
10876 *input_line_pointer
= saved_char
;
10877 ignore_rest_of_line ();
10880 /* Parse a .arch_extension directive. */
10883 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10886 char *ext
= input_line_pointer
;
10888 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10889 saved_char
= *input_line_pointer
;
10890 *input_line_pointer
= 0;
10892 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10895 cpu_variant
= *mcpu_cpu_opt
;
10897 *input_line_pointer
= saved_char
;
10898 demand_empty_rest_of_line ();
10901 /* Copy symbol information. */
10904 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10906 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10910 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10911 This is needed so AArch64 specific st_other values can be independently
10912 specified for an IFUNC resolver (that is called by the dynamic linker)
10913 and the symbol it resolves (aliased to the resolver). In particular,
10914 if a function symbol has special st_other value set via directives,
10915 then attaching an IFUNC resolver to that symbol should not override
10916 the st_other setting. Requiring the directive on the IFUNC resolver
10917 symbol would be unexpected and problematic in C code, where the two
10918 symbols appear as two independent function declarations. */
10921 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10923 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10924 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10925 /* If size is unset, copy size from src. Because we don't track whether
10926 .size has been used, we can't differentiate .size dest, 0 from the case
10927 where dest's size is unset. */
10928 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10932 destelf
->size
= XNEW (expressionS
);
10933 *destelf
->size
= *srcelf
->size
;
10935 S_SET_SIZE (dest
, S_GET_SIZE (src
));