1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* SME horizontal or vertical slice indicator, encoded in "V".
128 /* Bits for DEFINED field in vector_type_el. */
129 #define NTA_HASTYPE 1
130 #define NTA_HASINDEX 2
131 #define NTA_HASVARWIDTH 4
133 struct vector_type_el
135 enum vector_el_type type
;
136 unsigned char defined
;
137 unsigned element_size
;
142 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
146 bfd_reloc_code_real_type type
;
149 enum aarch64_opnd opnd
;
151 unsigned need_libopcodes_p
: 1;
154 struct aarch64_instruction
156 /* libopcodes structure for instruction intermediate representation. */
158 /* Record assembly errors found during the parsing. */
159 aarch64_operand_error parsing_error
;
160 /* The condition that appears in the assembly line. */
162 /* Relocation information (including the GAS internal fixup). */
164 /* Need to generate an immediate in the literal pool. */
165 unsigned gen_lit_pool
: 1;
168 typedef struct aarch64_instruction aarch64_instruction
;
170 static aarch64_instruction inst
;
172 static bool parse_operands (char *, const aarch64_opcode
*);
173 static bool programmer_friendly_fixup (aarch64_instruction
*);
175 /* Diagnostics inline function utilities.
177 These are lightweight utilities which should only be called by parse_operands
178 and other parsers. GAS processes each assembly line by parsing it against
179 instruction template(s), in the case of multiple templates (for the same
180 mnemonic name), those templates are tried one by one until one succeeds or
181 all fail. An assembly line may fail a few templates before being
182 successfully parsed; an error saved here in most cases is not a user error
183 but an error indicating the current template is not the right template.
184 Therefore it is very important that errors can be saved at a low cost during
185 the parsing; we don't want to slow down the whole parsing by recording
186 non-user errors in detail.
188 Remember that the objective is to help GAS pick up the most appropriate
189 error message in the case of multiple templates, e.g. FMOV which has 8
195 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
196 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
202 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
206 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
208 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
209 inst
.parsing_error
.index
= -1;
210 inst
.parsing_error
.kind
= kind
;
211 inst
.parsing_error
.error
= error
;
215 set_recoverable_error (const char *error
)
217 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
220 /* Use the DESC field of the corresponding aarch64_operand entry to compose
221 the error message. */
223 set_default_error (void)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
229 set_syntax_error (const char *error
)
231 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
235 set_first_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
242 set_fatal_syntax_error (const char *error
)
244 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
247 /* Return value for certain parsers when the parsing fails; those parsers
248 return the information of the parsed result, e.g. register number, on
250 #define PARSE_FAIL -1
252 /* This is an invalid condition code that means no conditional field is
254 #define COND_ALWAYS 0x10
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 BASIC_REG_TYPE(ZA) /* za */ \
288 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
289 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
290 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
291 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
292 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
293 /* Typecheck: same, plus SVE registers. */ \
294 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
296 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
297 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Typecheck: same, plus SVE registers. */ \
300 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
303 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
304 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
306 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
307 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
308 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
309 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
310 /* Typecheck: any [BHSDQ]P FP. */ \
311 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
312 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
313 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
314 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
315 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
316 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
317 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
318 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
319 be used for SVE instructions, since Zn and Pn are valid symbols \
320 in other contexts. */ \
321 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
322 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
323 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
324 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
325 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
326 | REG_TYPE(ZN) | REG_TYPE(PN)) \
327 /* Any integer register; used for error messages only. */ \
328 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
329 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
330 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
331 /* The whole of ZA or a single tile. */ \
332 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
333 /* A horizontal or vertical slice of a ZA tile. */ \
334 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
335 /* Pseudo type to mark the end of the enumerator sequence. */ \
338 #undef BASIC_REG_TYPE
339 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
343 /* Register type enumerators. */
344 typedef enum aarch64_reg_type_
346 /* A list of REG_TYPE_*. */
350 #undef BASIC_REG_TYPE
351 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
353 #define REG_TYPE(T) (1 << REG_TYPE_##T)
354 #undef MULTI_REG_TYPE
355 #define MULTI_REG_TYPE(T,V) V,
357 /* Structure for a hash table entry for a register. */
361 unsigned char number
;
362 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
363 unsigned char builtin
;
366 /* Values indexed by aarch64_reg_type to assist the type checking. */
367 static const unsigned reg_type_masks
[] =
372 #undef BASIC_REG_TYPE
374 #undef MULTI_REG_TYPE
375 #undef AARCH64_REG_TYPES
377 /* Diagnostics used when we don't get a register of the expected type.
378 Note: this has to synchronized with aarch64_reg_type definitions
381 get_reg_expected_msg (aarch64_reg_type reg_type
)
388 msg
= N_("integer 32-bit register expected");
391 msg
= N_("integer 64-bit register expected");
394 msg
= N_("integer register expected");
396 case REG_TYPE_R64_SP
:
397 msg
= N_("64-bit integer or SP register expected");
399 case REG_TYPE_SVE_BASE
:
400 msg
= N_("base register expected");
403 msg
= N_("integer or zero register expected");
405 case REG_TYPE_SVE_OFFSET
:
406 msg
= N_("offset register expected");
409 msg
= N_("integer or SP register expected");
411 case REG_TYPE_R_Z_SP
:
412 msg
= N_("integer, zero or SP register expected");
415 msg
= N_("8-bit SIMD scalar register expected");
418 msg
= N_("16-bit SIMD scalar or floating-point half precision "
419 "register expected");
422 msg
= N_("32-bit SIMD scalar or floating-point single precision "
423 "register expected");
426 msg
= N_("64-bit SIMD scalar or floating-point double precision "
427 "register expected");
430 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
431 "register expected");
433 case REG_TYPE_R_Z_BHSDQ_V
:
434 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
435 msg
= N_("register expected");
437 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
438 msg
= N_("SIMD scalar or floating-point register expected");
440 case REG_TYPE_VN
: /* any V reg */
441 msg
= N_("vector register expected");
444 msg
= N_("SVE vector register expected");
447 msg
= N_("SVE predicate register expected");
450 as_fatal (_("invalid register type %d"), reg_type
);
455 /* Some well known registers that we refer to directly elsewhere. */
459 /* Instructions take 4 bytes in the object file. */
462 static htab_t aarch64_ops_hsh
;
463 static htab_t aarch64_cond_hsh
;
464 static htab_t aarch64_shift_hsh
;
465 static htab_t aarch64_sys_regs_hsh
;
466 static htab_t aarch64_pstatefield_hsh
;
467 static htab_t aarch64_sys_regs_ic_hsh
;
468 static htab_t aarch64_sys_regs_dc_hsh
;
469 static htab_t aarch64_sys_regs_at_hsh
;
470 static htab_t aarch64_sys_regs_tlbi_hsh
;
471 static htab_t aarch64_sys_regs_sr_hsh
;
472 static htab_t aarch64_reg_hsh
;
473 static htab_t aarch64_barrier_opt_hsh
;
474 static htab_t aarch64_nzcv_hsh
;
475 static htab_t aarch64_pldop_hsh
;
476 static htab_t aarch64_hint_opt_hsh
;
478 /* Stuff needed to resolve the label ambiguity
487 static symbolS
*last_label_seen
;
489 /* Literal pool structure. Held on a per-section
490 and per-sub-section basis. */
492 #define MAX_LITERAL_POOL_SIZE 1024
493 typedef struct literal_expression
496 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
497 LITTLENUM_TYPE
* bignum
;
498 } literal_expression
;
500 typedef struct literal_pool
502 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
503 unsigned int next_free_entry
;
509 struct literal_pool
*next
;
512 /* Pointer to a linked list of literal pools. */
513 static literal_pool
*list_of_pools
= NULL
;
517 /* This array holds the chars that always start a comment. If the
518 pre-processor is disabled, these aren't very useful. */
519 const char comment_chars
[] = "";
521 /* This array holds the chars that only start a comment at the beginning of
522 a line. If the line seems to have the form '# 123 filename'
523 .line and .file directives will appear in the pre-processed output. */
524 /* Note that input_file.c hand checks for '#' at the beginning of the
525 first line of the input file. This is because the compiler outputs
526 #NO_APP at the beginning of its output. */
527 /* Also note that comments like this one will always work. */
528 const char line_comment_chars
[] = "#";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant
533 from exp in floating point numbers. */
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant. */
540 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
542 /* Prefix character that indicates the start of an immediate value. */
543 #define is_immediate_prefix(C) ((C) == '#')
545 /* Separator character handling. */
547 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
550 skip_past_char (char **str
, char c
)
561 #define skip_past_comma(str) skip_past_char (str, ',')
563 /* Arithmetic expressions (possibly involving symbols). */
565 static bool in_aarch64_get_expression
= false;
567 /* Third argument to aarch64_get_expression. */
568 #define GE_NO_PREFIX false
569 #define GE_OPT_PREFIX true
571 /* Fourth argument to aarch64_get_expression. */
572 #define ALLOW_ABSENT false
573 #define REJECT_ABSENT true
575 /* Return TRUE if the string pointed by *STR is successfully parsed
576 as an valid expression; *EP will be filled with the information of
577 such an expression. Otherwise return FALSE.
579 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
580 If REJECT_ABSENT is true then trat missing expressions as an error. */
583 aarch64_get_expression (expressionS
* ep
,
585 bool allow_immediate_prefix
,
590 bool prefix_present
= false;
592 if (allow_immediate_prefix
)
594 if (is_immediate_prefix (**str
))
597 prefix_present
= true;
601 memset (ep
, 0, sizeof (expressionS
));
603 save_in
= input_line_pointer
;
604 input_line_pointer
= *str
;
605 in_aarch64_get_expression
= true;
606 seg
= expression (ep
);
607 in_aarch64_get_expression
= false;
609 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
611 /* We found a bad expression in md_operand(). */
612 *str
= input_line_pointer
;
613 input_line_pointer
= save_in
;
614 if (prefix_present
&& ! error_p ())
615 set_fatal_syntax_error (_("bad expression"));
617 set_first_syntax_error (_("bad expression"));
622 if (seg
!= absolute_section
623 && seg
!= text_section
624 && seg
!= data_section
625 && seg
!= bss_section
626 && seg
!= undefined_section
)
628 set_syntax_error (_("bad segment"));
629 *str
= input_line_pointer
;
630 input_line_pointer
= save_in
;
637 *str
= input_line_pointer
;
638 input_line_pointer
= save_in
;
642 /* Turn a string in input_line_pointer into a floating point constant
643 of type TYPE, and store the appropriate bytes in *LITP. The number
644 of LITTLENUMS emitted is stored in *SIZEP. An error message is
645 returned, or NULL on OK. */
648 md_atof (int type
, char *litP
, int *sizeP
)
650 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
653 /* We handle all bad expressions here, so that we can report the faulty
654 instruction in the error message. */
656 md_operand (expressionS
* exp
)
658 if (in_aarch64_get_expression
)
659 exp
->X_op
= O_illegal
;
662 /* Immediate values. */
664 /* Errors may be set multiple times during parsing or bit encoding
665 (particularly in the Neon bits), but usually the earliest error which is set
666 will be the most meaningful. Avoid overwriting it with later (cascading)
667 errors by calling this function. */
670 first_error (const char *error
)
673 set_syntax_error (error
);
676 /* Similar to first_error, but this function accepts formatted error
679 first_error_fmt (const char *format
, ...)
684 /* N.B. this single buffer will not cause error messages for different
685 instructions to pollute each other; this is because at the end of
686 processing of each assembly line, error message if any will be
687 collected by as_bad. */
688 static char buffer
[size
];
692 int ret ATTRIBUTE_UNUSED
;
693 va_start (args
, format
);
694 ret
= vsnprintf (buffer
, size
, format
, args
);
695 know (ret
<= size
- 1 && ret
>= 0);
697 set_syntax_error (buffer
);
701 /* Internal helper routine converting a vector_type_el structure *VECTYPE
702 to a corresponding operand qualifier. */
704 static inline aarch64_opnd_qualifier_t
705 vectype_to_qualifier (const struct vector_type_el
*vectype
)
707 /* Element size in bytes indexed by vector_el_type. */
708 const unsigned char ele_size
[5]
710 const unsigned int ele_base
[5] =
712 AARCH64_OPND_QLF_V_4B
,
713 AARCH64_OPND_QLF_V_2H
,
714 AARCH64_OPND_QLF_V_2S
,
715 AARCH64_OPND_QLF_V_1D
,
716 AARCH64_OPND_QLF_V_1Q
719 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
720 goto vectype_conversion_fail
;
722 if (vectype
->type
== NT_zero
)
723 return AARCH64_OPND_QLF_P_Z
;
724 if (vectype
->type
== NT_merge
)
725 return AARCH64_OPND_QLF_P_M
;
727 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
729 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
731 /* Special case S_4B. */
732 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
733 return AARCH64_OPND_QLF_S_4B
;
735 /* Special case S_2H. */
736 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
737 return AARCH64_OPND_QLF_S_2H
;
739 /* Vector element register. */
740 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
744 /* Vector register. */
745 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
748 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
749 goto vectype_conversion_fail
;
751 /* The conversion is by calculating the offset from the base operand
752 qualifier for the vector type. The operand qualifiers are regular
753 enough that the offset can established by shifting the vector width by
754 a vector-type dependent amount. */
756 if (vectype
->type
== NT_b
)
758 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
760 else if (vectype
->type
>= NT_d
)
765 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
766 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
767 && offset
<= AARCH64_OPND_QLF_V_1Q
);
771 vectype_conversion_fail
:
772 first_error (_("bad vector arrangement type"));
773 return AARCH64_OPND_QLF_NIL
;
776 /* Register parsing. */
778 /* Generic register parser which is called by other specialized
780 CCP points to what should be the beginning of a register name.
781 If it is indeed a valid register name, advance CCP over it and
782 return the reg_entry structure; otherwise return NULL.
783 It does not issue diagnostics. */
786 parse_reg (char **ccp
)
792 #ifdef REGISTER_PREFIX
793 if (*start
!= REGISTER_PREFIX
)
799 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
804 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
806 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
815 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
818 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
820 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
823 /* Try to parse a base or offset register. Allow SVE base and offset
824 registers if REG_TYPE includes SVE registers. Return the register
825 entry on success, setting *QUALIFIER to the register qualifier.
826 Return null otherwise.
828 Note that this function does not issue any diagnostics. */
830 static const reg_entry
*
831 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
832 aarch64_opnd_qualifier_t
*qualifier
)
835 const reg_entry
*reg
= parse_reg (&str
);
845 *qualifier
= AARCH64_OPND_QLF_W
;
851 *qualifier
= AARCH64_OPND_QLF_X
;
855 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
858 switch (TOLOWER (str
[1]))
861 *qualifier
= AARCH64_OPND_QLF_S_S
;
864 *qualifier
= AARCH64_OPND_QLF_S_D
;
881 /* Try to parse a base or offset register. Return the register entry
882 on success, setting *QUALIFIER to the register qualifier. Return null
885 Note that this function does not issue any diagnostics. */
887 static const reg_entry
*
888 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
890 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
893 /* Parse the qualifier of a vector register or vector element of type
894 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
895 succeeds; otherwise return FALSE.
897 Accept only one occurrence of:
898 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
901 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
902 struct vector_type_el
*parsed_type
, char **str
)
906 unsigned element_size
;
907 enum vector_el_type type
;
910 gas_assert (*ptr
== '.');
913 if (reg_type
!= REG_TYPE_VN
|| !ISDIGIT (*ptr
))
918 width
= strtoul (ptr
, &ptr
, 10);
919 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
921 first_error_fmt (_("bad size %d in vector width specifier"), width
);
926 switch (TOLOWER (*ptr
))
945 if (reg_type
!= REG_TYPE_VN
|| width
== 1)
954 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
956 first_error (_("missing element size"));
959 if (width
!= 0 && width
* element_size
!= 64
960 && width
* element_size
!= 128
961 && !(width
== 2 && element_size
== 16)
962 && !(width
== 4 && element_size
== 8))
965 ("invalid element size %d and vector size combination %c"),
971 parsed_type
->type
= type
;
972 parsed_type
->width
= width
;
973 parsed_type
->element_size
= element_size
;
980 /* *STR contains an SVE zero/merge predication suffix. Parse it into
981 *PARSED_TYPE and point *STR at the end of the suffix. */
984 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
989 gas_assert (*ptr
== '/');
991 switch (TOLOWER (*ptr
))
994 parsed_type
->type
= NT_zero
;
997 parsed_type
->type
= NT_merge
;
1000 if (*ptr
!= '\0' && *ptr
!= ',')
1001 first_error_fmt (_("unexpected character `%c' in predication type"),
1004 first_error (_("missing predication type"));
1007 parsed_type
->width
= 0;
1012 /* Return true if CH is a valid suffix character for registers of
1016 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1029 return ch
== '.' || ch
== '/';
1036 /* Parse a register of the type TYPE.
1038 Return null if the string pointed to by *CCP is not a valid register
1039 name or the parsed register is not of TYPE.
1041 Otherwise return the register, and optionally return the register
1042 shape and element index information in *TYPEINFO.
1044 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1046 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1049 #define PTR_IN_REGLIST (1U << 0)
1050 #define PTR_FULL_REG (1U << 1)
1052 static const reg_entry
*
1053 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1054 struct vector_type_el
*typeinfo
, unsigned int flags
)
1057 const reg_entry
*reg
= parse_reg (&str
);
1058 struct vector_type_el atype
;
1059 struct vector_type_el parsetype
;
1060 bool is_typed_vecreg
= false;
1063 atype
.type
= NT_invtype
;
1065 atype
.element_size
= 0;
1072 set_default_error ();
1076 if (! aarch64_check_reg_type (reg
, type
))
1078 DEBUG_TRACE ("reg type check failed");
1079 set_default_error ();
1084 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1088 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1090 if ((reg
->type
== REG_TYPE_ZAT
1091 || reg
->type
== REG_TYPE_ZATH
1092 || reg
->type
== REG_TYPE_ZATV
)
1093 && reg
->number
* 8 >= parsetype
.element_size
)
1095 set_syntax_error (_("ZA tile number out of range"));
1101 if (!parse_predication_for_operand (&parsetype
, &str
))
1105 /* Register if of the form Vn.[bhsdq]. */
1106 is_typed_vecreg
= true;
1108 if (type
!= REG_TYPE_VN
)
1110 /* The width is always variable; we don't allow an integer width
1112 gas_assert (parsetype
.width
== 0);
1113 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1115 else if (parsetype
.width
== 0)
1116 /* Expect index. In the new scheme we cannot have
1117 Vn.[bhsdq] represent a scalar. Therefore any
1118 Vn.[bhsdq] should have an index following it.
1119 Except in reglists of course. */
1120 atype
.defined
|= NTA_HASINDEX
;
1122 atype
.defined
|= NTA_HASTYPE
;
1124 atype
.type
= parsetype
.type
;
1125 atype
.width
= parsetype
.width
;
1128 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1132 /* Reject Sn[index] syntax. */
1133 if (!is_typed_vecreg
)
1135 first_error (_("this type of register can't be indexed"));
1139 if (flags
& PTR_IN_REGLIST
)
1141 first_error (_("index not allowed inside register list"));
1145 atype
.defined
|= NTA_HASINDEX
;
1147 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1149 if (exp
.X_op
!= O_constant
)
1151 first_error (_("constant expression required"));
1155 if (! skip_past_char (&str
, ']'))
1158 atype
.index
= exp
.X_add_number
;
1160 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1162 /* Indexed vector register expected. */
1163 first_error (_("indexed vector register expected"));
1167 /* A vector reg Vn should be typed or indexed. */
1168 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1170 first_error (_("invalid use of vector register"));
1183 Return the register on success; return null otherwise.
1185 If this is a NEON vector register with additional type information, fill
1186 in the struct pointed to by VECTYPE (if non-NULL).
1188 This parser does not handle register lists. */
1190 static const reg_entry
*
1191 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1192 struct vector_type_el
*vectype
)
1194 return parse_typed_reg (ccp
, type
, vectype
, 0);
1198 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1200 return (e1
.type
== e2
.type
1201 && e1
.defined
== e2
.defined
1202 && e1
.width
== e2
.width
1203 && e1
.element_size
== e2
.element_size
1204 && e1
.index
== e2
.index
);
1207 /* This function parses a list of vector registers of type TYPE.
1208 On success, it returns the parsed register list information in the
1209 following encoded format:
1211 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1212 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1214 The information of the register shape and/or index is returned in
1217 It returns PARSE_FAIL if the register list is invalid.
1219 The list contains one to four registers.
1220 Each register can be one of:
1223 All <T> should be identical.
1224 All <index> should be identical.
1225 There are restrictions on <Vt> numbers which are checked later
1226 (by reg_list_valid_p). */
1229 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1230 struct vector_type_el
*vectype
)
1234 struct vector_type_el typeinfo
, typeinfo_first
;
1240 bool expect_index
= false;
1244 set_syntax_error (_("expecting {"));
1250 typeinfo_first
.defined
= 0;
1251 typeinfo_first
.type
= NT_invtype
;
1252 typeinfo_first
.width
= -1;
1253 typeinfo_first
.element_size
= 0;
1254 typeinfo_first
.index
= 0;
1263 str
++; /* skip over '-' */
1266 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1270 set_first_syntax_error (_("invalid vector register in list"));
1275 /* reject [bhsd]n */
1276 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1278 set_first_syntax_error (_("invalid scalar register in list"));
1283 if (typeinfo
.defined
& NTA_HASINDEX
)
1284 expect_index
= true;
1288 if (val
< val_range
)
1290 set_first_syntax_error
1291 (_("invalid range in vector register list"));
1300 typeinfo_first
= typeinfo
;
1301 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1303 set_first_syntax_error
1304 (_("type mismatch in vector register list"));
1309 for (i
= val_range
; i
<= val
; i
++)
1311 ret_val
|= i
<< (5 * nb_regs
);
1316 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1318 skip_whitespace (str
);
1321 set_first_syntax_error (_("end of vector register list not found"));
1326 skip_whitespace (str
);
1330 if (skip_past_char (&str
, '['))
1334 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1335 if (exp
.X_op
!= O_constant
)
1337 set_first_syntax_error (_("constant expression required."));
1340 if (! skip_past_char (&str
, ']'))
1343 typeinfo_first
.index
= exp
.X_add_number
;
1347 set_first_syntax_error (_("expected index"));
1354 set_first_syntax_error (_("too many registers in vector register list"));
1357 else if (nb_regs
== 0)
1359 set_first_syntax_error (_("empty vector register list"));
1365 *vectype
= typeinfo_first
;
1367 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1370 /* Directives: register aliases. */
1373 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1378 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1381 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1384 /* Only warn about a redefinition if it's not defined as the
1386 else if (new->number
!= number
|| new->type
!= type
)
1387 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1392 name
= xstrdup (str
);
1393 new = XNEW (reg_entry
);
1396 new->number
= number
;
1398 new->builtin
= false;
1400 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1405 /* Look for the .req directive. This is of the form:
1407 new_register_name .req existing_register_name
1409 If we find one, or if it looks sufficiently like one that we want to
1410 handle any error here, return TRUE. Otherwise return FALSE. */
1413 create_register_alias (char *newname
, char *p
)
1415 const reg_entry
*old
;
1416 char *oldname
, *nbuf
;
1419 /* The input scrubber ensures that whitespace after the mnemonic is
1420 collapsed to single spaces. */
1422 if (!startswith (oldname
, " .req "))
1426 if (*oldname
== '\0')
1429 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1432 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1436 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1437 the desired alias name, and p points to its end. If not, then
1438 the desired alias name is in the global original_case_string. */
1439 #ifdef TC_CASE_SENSITIVE
1442 newname
= original_case_string
;
1443 nlen
= strlen (newname
);
1446 nbuf
= xmemdup0 (newname
, nlen
);
1448 /* Create aliases under the new name as stated; an all-lowercase
1449 version of the new name; and an all-uppercase version of the new
1451 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1453 for (p
= nbuf
; *p
; p
++)
1456 if (strncmp (nbuf
, newname
, nlen
))
1458 /* If this attempt to create an additional alias fails, do not bother
1459 trying to create the all-lower case alias. We will fail and issue
1460 a second, duplicate error message. This situation arises when the
1461 programmer does something like:
1464 The second .req creates the "Foo" alias but then fails to create
1465 the artificial FOO alias because it has already been created by the
1467 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1474 for (p
= nbuf
; *p
; p
++)
1477 if (strncmp (nbuf
, newname
, nlen
))
1478 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1485 /* Should never be called, as .req goes between the alias and the
1486 register name, not at the beginning of the line. */
1488 s_req (int a ATTRIBUTE_UNUSED
)
1490 as_bad (_("invalid syntax for .req directive"));
1493 /* The .unreq directive deletes an alias which was previously defined
1494 by .req. For example:
1500 s_unreq (int a ATTRIBUTE_UNUSED
)
1505 name
= input_line_pointer
;
1506 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1507 saved_char
= *input_line_pointer
;
1508 *input_line_pointer
= 0;
1511 as_bad (_("invalid syntax for .unreq directive"));
1514 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1517 as_bad (_("unknown register alias '%s'"), name
);
1518 else if (reg
->builtin
)
1519 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1526 str_hash_delete (aarch64_reg_hsh
, name
);
1527 free ((char *) reg
->name
);
1530 /* Also locate the all upper case and all lower case versions.
1531 Do not complain if we cannot find one or the other as it
1532 was probably deleted above. */
1534 nbuf
= strdup (name
);
1535 for (p
= nbuf
; *p
; p
++)
1537 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1540 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1541 free ((char *) reg
->name
);
1545 for (p
= nbuf
; *p
; p
++)
1547 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1550 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1551 free ((char *) reg
->name
);
1559 *input_line_pointer
= saved_char
;
1560 demand_empty_rest_of_line ();
1563 /* Directives: Instruction set selection. */
1565 #if defined OBJ_ELF || defined OBJ_COFF
1566 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1567 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1568 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1569 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1571 /* Create a new mapping symbol for the transition to STATE. */
1574 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1577 const char *symname
;
1584 type
= BSF_NO_FLAGS
;
1588 type
= BSF_NO_FLAGS
;
1594 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1595 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1597 /* Save the mapping symbols for future reference. Also check that
1598 we do not place two mapping symbols at the same offset within a
1599 frag. We'll handle overlap between frags in
1600 check_mapping_symbols.
1602 If .fill or other data filling directive generates zero sized data,
1603 the mapping symbol for the following code will have the same value
1604 as the one generated for the data filling directive. In this case,
1605 we replace the old symbol with the new one at the same address. */
1608 if (frag
->tc_frag_data
.first_map
!= NULL
)
1610 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1611 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1614 frag
->tc_frag_data
.first_map
= symbolP
;
1616 if (frag
->tc_frag_data
.last_map
!= NULL
)
1618 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1619 S_GET_VALUE (symbolP
));
1620 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1621 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1624 frag
->tc_frag_data
.last_map
= symbolP
;
1627 /* We must sometimes convert a region marked as code to data during
1628 code alignment, if an odd number of bytes have to be padded. The
1629 code mapping symbol is pushed to an aligned address. */
1632 insert_data_mapping_symbol (enum mstate state
,
1633 valueT value
, fragS
* frag
, offsetT bytes
)
1635 /* If there was already a mapping symbol, remove it. */
1636 if (frag
->tc_frag_data
.last_map
!= NULL
1637 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1638 frag
->fr_address
+ value
)
1640 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1644 know (frag
->tc_frag_data
.first_map
== symp
);
1645 frag
->tc_frag_data
.first_map
= NULL
;
1647 frag
->tc_frag_data
.last_map
= NULL
;
1648 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1651 make_mapping_symbol (MAP_DATA
, value
, frag
);
1652 make_mapping_symbol (state
, value
+ bytes
, frag
);
1655 static void mapping_state_2 (enum mstate state
, int max_chars
);
1657 /* Set the mapping state to STATE. Only call this when about to
1658 emit some STATE bytes to the file. */
1661 mapping_state (enum mstate state
)
1663 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1665 if (state
== MAP_INSN
)
1666 /* AArch64 instructions require 4-byte alignment. When emitting
1667 instructions into any section, record the appropriate section
1669 record_alignment (now_seg
, 2);
1671 if (mapstate
== state
)
1672 /* The mapping symbol has already been emitted.
1673 There is nothing else to do. */
1676 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1677 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1678 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1679 evaluated later in the next else. */
1681 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1683 /* Only add the symbol if the offset is > 0:
1684 if we're at the first frag, check it's size > 0;
1685 if we're not at the first frag, then for sure
1686 the offset is > 0. */
1687 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1688 const int add_symbol
= (frag_now
!= frag_first
)
1689 || (frag_now_fix () > 0);
1692 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1696 mapping_state_2 (state
, 0);
1699 /* Same as mapping_state, but MAX_CHARS bytes have already been
1700 allocated. Put the mapping symbol that far back. */
1703 mapping_state_2 (enum mstate state
, int max_chars
)
1705 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1707 if (!SEG_NORMAL (now_seg
))
1710 if (mapstate
== state
)
1711 /* The mapping symbol has already been emitted.
1712 There is nothing else to do. */
1715 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1716 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1719 #define mapping_state(x) /* nothing */
1720 #define mapping_state_2(x, y) /* nothing */
1723 /* Directives: sectioning and alignment. */
1726 s_bss (int ignore ATTRIBUTE_UNUSED
)
1728 /* We don't support putting frags in the BSS segment, we fake it by
1729 marking in_bss, then looking at s_skip for clues. */
1730 subseg_set (bss_section
, 0);
1731 demand_empty_rest_of_line ();
1732 mapping_state (MAP_DATA
);
1736 s_even (int ignore ATTRIBUTE_UNUSED
)
1738 /* Never make frag if expect extra pass. */
1740 frag_align (1, 0, 0);
1742 record_alignment (now_seg
, 1);
1744 demand_empty_rest_of_line ();
1747 /* Directives: Literal pools. */
1749 static literal_pool
*
1750 find_literal_pool (int size
)
1754 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1756 if (pool
->section
== now_seg
1757 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1764 static literal_pool
*
1765 find_or_make_literal_pool (int size
)
1767 /* Next literal pool ID number. */
1768 static unsigned int latest_pool_num
= 1;
1771 pool
= find_literal_pool (size
);
1775 /* Create a new pool. */
1776 pool
= XNEW (literal_pool
);
1780 /* Currently we always put the literal pool in the current text
1781 section. If we were generating "small" model code where we
1782 knew that all code and initialised data was within 1MB then
1783 we could output literals to mergeable, read-only data
1786 pool
->next_free_entry
= 0;
1787 pool
->section
= now_seg
;
1788 pool
->sub_section
= now_subseg
;
1790 pool
->next
= list_of_pools
;
1791 pool
->symbol
= NULL
;
1793 /* Add it to the list. */
1794 list_of_pools
= pool
;
1797 /* New pools, and emptied pools, will have a NULL symbol. */
1798 if (pool
->symbol
== NULL
)
1800 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1801 &zero_address_frag
, 0);
1802 pool
->id
= latest_pool_num
++;
1809 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1810 Return TRUE on success, otherwise return FALSE. */
1812 add_to_lit_pool (expressionS
*exp
, int size
)
1817 pool
= find_or_make_literal_pool (size
);
1819 /* Check if this literal value is already in the pool. */
1820 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1822 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1824 if ((litexp
->X_op
== exp
->X_op
)
1825 && (exp
->X_op
== O_constant
)
1826 && (litexp
->X_add_number
== exp
->X_add_number
)
1827 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1830 if ((litexp
->X_op
== exp
->X_op
)
1831 && (exp
->X_op
== O_symbol
)
1832 && (litexp
->X_add_number
== exp
->X_add_number
)
1833 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1834 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1838 /* Do we need to create a new entry? */
1839 if (entry
== pool
->next_free_entry
)
1841 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1843 set_syntax_error (_("literal pool overflow"));
1847 pool
->literals
[entry
].exp
= *exp
;
1848 pool
->next_free_entry
+= 1;
1849 if (exp
->X_op
== O_big
)
1851 /* PR 16688: Bignums are held in a single global array. We must
1852 copy and preserve that value now, before it is overwritten. */
1853 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1855 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1856 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1859 pool
->literals
[entry
].bignum
= NULL
;
1862 exp
->X_op
= O_symbol
;
1863 exp
->X_add_number
= ((int) entry
) * size
;
1864 exp
->X_add_symbol
= pool
->symbol
;
1869 /* Can't use symbol_new here, so have to create a symbol and then at
1870 a later date assign it a value. That's what these functions do. */
1873 symbol_locate (symbolS
* symbolP
,
1874 const char *name
,/* It is copied, the caller can modify. */
1875 segT segment
, /* Segment identifier (SEG_<something>). */
1876 valueT valu
, /* Symbol value. */
1877 fragS
* frag
) /* Associated fragment. */
1880 char *preserved_copy_of_name
;
1882 name_length
= strlen (name
) + 1; /* +1 for \0. */
1883 obstack_grow (¬es
, name
, name_length
);
1884 preserved_copy_of_name
= obstack_finish (¬es
);
1886 #ifdef tc_canonicalize_symbol_name
1887 preserved_copy_of_name
=
1888 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1891 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1893 S_SET_SEGMENT (symbolP
, segment
);
1894 S_SET_VALUE (symbolP
, valu
);
1895 symbol_clear_list_pointers (symbolP
);
1897 symbol_set_frag (symbolP
, frag
);
1899 /* Link to end of symbol chain. */
1901 extern int symbol_table_frozen
;
1903 if (symbol_table_frozen
)
1907 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1909 obj_symbol_new_hook (symbolP
);
1911 #ifdef tc_symbol_new_hook
1912 tc_symbol_new_hook (symbolP
);
1916 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1917 #endif /* DEBUG_SYMS */
1922 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1929 for (align
= 2; align
<= 4; align
++)
1931 int size
= 1 << align
;
1933 pool
= find_literal_pool (size
);
1934 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1937 /* Align pool as you have word accesses.
1938 Only make a frag if we have to. */
1940 frag_align (align
, 0, 0);
1942 mapping_state (MAP_DATA
);
1944 record_alignment (now_seg
, align
);
1946 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1948 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1949 (valueT
) frag_now_fix (), frag_now
);
1950 symbol_table_insert (pool
->symbol
);
1952 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1954 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1956 if (exp
->X_op
== O_big
)
1958 /* PR 16688: Restore the global bignum value. */
1959 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1960 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1961 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1964 /* First output the expression in the instruction to the pool. */
1965 emit_expr (exp
, size
); /* .word|.xword */
1967 if (exp
->X_op
== O_big
)
1969 free (pool
->literals
[entry
].bignum
);
1970 pool
->literals
[entry
].bignum
= NULL
;
1974 /* Mark the pool as empty. */
1975 pool
->next_free_entry
= 0;
1976 pool
->symbol
= NULL
;
1980 #if defined(OBJ_ELF) || defined(OBJ_COFF)
1981 /* Forward declarations for functions below, in the MD interface
1983 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1985 /* Directives: Data. */
1986 /* N.B. the support for relocation suffix in this directive needs to be
1987 implemented properly. */
1990 s_aarch64_cons (int nbytes
)
1994 #ifdef md_flush_pending_output
1995 md_flush_pending_output ();
1998 if (is_it_end_of_statement ())
2000 demand_empty_rest_of_line ();
2004 #ifdef md_cons_align
2005 md_cons_align (nbytes
);
2008 mapping_state (MAP_DATA
);
2011 struct reloc_table_entry
*reloc
;
2015 if (exp
.X_op
!= O_symbol
)
2016 emit_expr (&exp
, (unsigned int) nbytes
);
2019 skip_past_char (&input_line_pointer
, '#');
2020 if (skip_past_char (&input_line_pointer
, ':'))
2022 reloc
= find_reloc_table_entry (&input_line_pointer
);
2024 as_bad (_("unrecognized relocation suffix"));
2026 as_bad (_("unimplemented relocation suffix"));
2027 ignore_rest_of_line ();
2031 emit_expr (&exp
, (unsigned int) nbytes
);
2034 while (*input_line_pointer
++ == ',');
2036 /* Put terminator back into stream. */
2037 input_line_pointer
--;
2038 demand_empty_rest_of_line ();
2043 /* Forward declarations for functions below, in the MD interface
2045 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2047 /* Mark symbol that it follows a variant PCS convention. */
2050 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2056 elf_symbol_type
*elfsym
;
2058 c
= get_symbol_name (&name
);
2060 as_bad (_("Missing symbol name in directive"));
2061 sym
= symbol_find_or_make (name
);
2062 restore_line_pointer (c
);
2063 demand_empty_rest_of_line ();
2064 bfdsym
= symbol_get_bfdsym (sym
);
2065 elfsym
= elf_symbol_from (bfdsym
);
2066 gas_assert (elfsym
);
2067 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2069 #endif /* OBJ_ELF */
2071 /* Output a 32-bit word, but mark as an instruction. */
2074 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2079 #ifdef md_flush_pending_output
2080 md_flush_pending_output ();
2083 if (is_it_end_of_statement ())
2085 demand_empty_rest_of_line ();
2089 /* Sections are assumed to start aligned. In executable section, there is no
2090 MAP_DATA symbol pending. So we only align the address during
2091 MAP_DATA --> MAP_INSN transition.
2092 For other sections, this is not guaranteed. */
2093 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2094 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2095 frag_align_code (2, 0);
2098 mapping_state (MAP_INSN
);
2104 if (exp
.X_op
!= O_constant
)
2106 as_bad (_("constant expression required"));
2107 ignore_rest_of_line ();
2111 if (target_big_endian
)
2113 unsigned int val
= exp
.X_add_number
;
2114 exp
.X_add_number
= SWAP_32 (val
);
2116 emit_expr (&exp
, INSN_SIZE
);
2119 while (*input_line_pointer
++ == ',');
2121 dwarf2_emit_insn (n
* INSN_SIZE
);
2123 /* Put terminator back into stream. */
2124 input_line_pointer
--;
2125 demand_empty_rest_of_line ();
2129 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2131 demand_empty_rest_of_line ();
2132 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2133 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2137 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2140 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2146 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2147 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2149 demand_empty_rest_of_line ();
2152 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2155 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2159 /* Since we're just labelling the code, there's no need to define a
2162 /* Make sure there is enough room in this frag for the following
2163 blr. This trick only works if the blr follows immediately after
2164 the .tlsdesc directive. */
2166 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2167 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2169 demand_empty_rest_of_line ();
2172 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2175 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2181 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2182 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2184 demand_empty_rest_of_line ();
2186 #endif /* OBJ_ELF */
2190 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2197 if (exp
.X_op
== O_symbol
)
2198 exp
.X_op
= O_secrel
;
2200 emit_expr (&exp
, 4);
2202 while (*input_line_pointer
++ == ',');
2204 input_line_pointer
--;
2205 demand_empty_rest_of_line ();
2209 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2213 exp
.X_op
= O_secrel
;
2214 exp
.X_add_symbol
= symbol
;
2215 exp
.X_add_number
= 0;
2216 emit_expr (&exp
, size
);
2220 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2227 if (exp
.X_op
== O_symbol
)
2228 exp
.X_op
= O_secidx
;
2230 emit_expr (&exp
, 2);
2232 while (*input_line_pointer
++ == ',');
2234 input_line_pointer
--;
2235 demand_empty_rest_of_line ();
2239 static void s_aarch64_arch (int);
2240 static void s_aarch64_cpu (int);
2241 static void s_aarch64_arch_extension (int);
2243 /* This table describes all the machine specific pseudo-ops the assembler
2244 has to support. The fields are:
2245 pseudo-op name without dot
2246 function to call to execute this pseudo-op
2247 Integer arg to pass to the function. */
2249 const pseudo_typeS md_pseudo_table
[] = {
2250 /* Never called because '.req' does not start a line. */
2252 {"unreq", s_unreq
, 0},
2254 {"even", s_even
, 0},
2255 {"ltorg", s_ltorg
, 0},
2256 {"pool", s_ltorg
, 0},
2257 {"cpu", s_aarch64_cpu
, 0},
2258 {"arch", s_aarch64_arch
, 0},
2259 {"arch_extension", s_aarch64_arch_extension
, 0},
2260 {"inst", s_aarch64_inst
, 0},
2261 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2263 {"tlsdescadd", s_tlsdescadd
, 0},
2264 {"tlsdesccall", s_tlsdesccall
, 0},
2265 {"tlsdescldr", s_tlsdescldr
, 0},
2266 {"variant_pcs", s_variant_pcs
, 0},
2268 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2269 {"word", s_aarch64_cons
, 4},
2270 {"long", s_aarch64_cons
, 4},
2271 {"xword", s_aarch64_cons
, 8},
2272 {"dword", s_aarch64_cons
, 8},
2275 {"secrel32", s_secrel
, 0},
2276 {"secidx", s_secidx
, 0},
2278 {"float16", float_cons
, 'h'},
2279 {"bfloat16", float_cons
, 'b'},
2284 /* Check whether STR points to a register name followed by a comma or the
2285 end of line; REG_TYPE indicates which register types are checked
2286 against. Return TRUE if STR is such a register name; otherwise return
2287 FALSE. The function does not intend to produce any diagnostics, but since
2288 the register parser aarch64_reg_parse, which is called by this function,
2289 does produce diagnostics, we call clear_error to clear any diagnostics
2290 that may be generated by aarch64_reg_parse.
2291 Also, the function returns FALSE directly if there is any user error
2292 present at the function entry. This prevents the existing diagnostics
2293 state from being spoiled.
2294 The function currently serves parse_constant_immediate and
2295 parse_big_immediate only. */
2297 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2299 const reg_entry
*reg
;
2301 /* Prevent the diagnostics state from being spoiled. */
2305 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2307 /* Clear the parsing error that may be set by the reg parser. */
2313 skip_whitespace (str
);
2314 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2320 /* Parser functions used exclusively in instruction operands. */
2322 /* Parse an immediate expression which may not be constant.
2324 To prevent the expression parser from pushing a register name
2325 into the symbol table as an undefined symbol, firstly a check is
2326 done to find out whether STR is a register of type REG_TYPE followed
2327 by a comma or the end of line. Return FALSE if STR is such a string. */
2330 parse_immediate_expression (char **str
, expressionS
*exp
,
2331 aarch64_reg_type reg_type
)
2333 if (reg_name_p (*str
, reg_type
))
2335 set_recoverable_error (_("immediate operand required"));
2339 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2341 if (exp
->X_op
== O_absent
)
2343 set_fatal_syntax_error (_("missing immediate expression"));
2350 /* Constant immediate-value read function for use in insn parsing.
2351 STR points to the beginning of the immediate (with the optional
2352 leading #); *VAL receives the value. REG_TYPE says which register
2353 names should be treated as registers rather than as symbolic immediates.
2355 Return TRUE on success; otherwise return FALSE. */
2358 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2362 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2365 if (exp
.X_op
!= O_constant
)
2367 set_syntax_error (_("constant expression required"));
2371 *val
= exp
.X_add_number
;
2376 encode_imm_float_bits (uint32_t imm
)
2378 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2379 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2382 /* Return TRUE if the single-precision floating-point value encoded in IMM
2383 can be expressed in the AArch64 8-bit signed floating-point format with
2384 3-bit exponent and normalized 4 bits of precision; in other words, the
2385 floating-point value must be expressable as
2386 (+/-) n / 16 * power (2, r)
2387 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2390 aarch64_imm_float_p (uint32_t imm
)
2392 /* If a single-precision floating-point value has the following bit
2393 pattern, it can be expressed in the AArch64 8-bit floating-point
2396 3 32222222 2221111111111
2397 1 09876543 21098765432109876543210
2398 n Eeeeeexx xxxx0000000000000000000
2400 where n, e and each x are either 0 or 1 independently, with
2405 /* Prepare the pattern for 'Eeeeee'. */
2406 if (((imm
>> 30) & 0x1) == 0)
2407 pattern
= 0x3e000000;
2409 pattern
= 0x40000000;
2411 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2412 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2415 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2416 as an IEEE float without any loss of precision. Store the value in
2420 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2422 /* If a double-precision floating-point value has the following bit
2423 pattern, it can be expressed in a float:
2425 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2426 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2427 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2429 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2430 if Eeee_eeee != 1111_1111
2432 where n, e, s and S are either 0 or 1 independently and where ~ is the
2436 uint32_t high32
= imm
>> 32;
2437 uint32_t low32
= imm
;
2439 /* Lower 29 bits need to be 0s. */
2440 if ((imm
& 0x1fffffff) != 0)
2443 /* Prepare the pattern for 'Eeeeeeeee'. */
2444 if (((high32
>> 30) & 0x1) == 0)
2445 pattern
= 0x38000000;
2447 pattern
= 0x40000000;
2450 if ((high32
& 0x78000000) != pattern
)
2453 /* Check Eeee_eeee != 1111_1111. */
2454 if ((high32
& 0x7ff00000) == 0x47f00000)
2457 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2458 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2459 | (low32
>> 29)); /* 3 S bits. */
2463 /* Return true if we should treat OPERAND as a double-precision
2464 floating-point operand rather than a single-precision one. */
2466 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2468 /* Check for unsuffixed SVE registers, which are allowed
2469 for LDR and STR but not in instructions that require an
2470 immediate. We get better error messages if we arbitrarily
2471 pick one size, parse the immediate normally, and then
2472 report the match failure in the normal way. */
2473 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2474 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2477 /* Parse a floating-point immediate. Return TRUE on success and return the
2478 value in *IMMED in the format of IEEE754 single-precision encoding.
2479 *CCP points to the start of the string; DP_P is TRUE when the immediate
2480 is expected to be in double-precision (N.B. this only matters when
2481 hexadecimal representation is involved). REG_TYPE says which register
2482 names should be treated as registers rather than as symbolic immediates.
2484 This routine accepts any IEEE float; it is up to the callers to reject
2488 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2489 aarch64_reg_type reg_type
)
2493 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2495 unsigned fpword
= 0;
2498 skip_past_char (&str
, '#');
2501 skip_whitespace (fpnum
);
2503 if (startswith (fpnum
, "0x"))
2505 /* Support the hexadecimal representation of the IEEE754 encoding.
2506 Double-precision is expected when DP_P is TRUE, otherwise the
2507 representation should be in single-precision. */
2508 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2513 if (!can_convert_double_to_float (val
, &fpword
))
2516 else if ((uint64_t) val
> 0xffffffff)
2523 else if (reg_name_p (str
, reg_type
))
2525 set_recoverable_error (_("immediate operand required"));
2533 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2536 /* Our FP word must be 32 bits (single-precision FP). */
2537 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2539 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2549 set_fatal_syntax_error (_("invalid floating-point constant"));
2553 /* Less-generic immediate-value read function with the possibility of loading
2554 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2557 To prevent the expression parser from pushing a register name into the
2558 symbol table as an undefined symbol, a check is firstly done to find
2559 out whether STR is a register of type REG_TYPE followed by a comma or
2560 the end of line. Return FALSE if STR is such a register. */
2563 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2567 if (reg_name_p (ptr
, reg_type
))
2569 set_syntax_error (_("immediate operand required"));
2573 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2575 if (inst
.reloc
.exp
.X_op
== O_constant
)
2576 *imm
= inst
.reloc
.exp
.X_add_number
;
2583 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2584 if NEED_LIBOPCODES is non-zero, the fixup will need
2585 assistance from the libopcodes. */
2588 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2589 const aarch64_opnd_info
*operand
,
2590 int need_libopcodes_p
)
2592 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2593 reloc
->opnd
= operand
->type
;
2594 if (need_libopcodes_p
)
2595 reloc
->need_libopcodes_p
= 1;
2598 /* Return TRUE if the instruction needs to be fixed up later internally by
2599 the GAS; otherwise return FALSE. */
2602 aarch64_gas_internal_fixup_p (void)
2604 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2607 /* Assign the immediate value to the relevant field in *OPERAND if
2608 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2609 needs an internal fixup in a later stage.
2610 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2611 IMM.VALUE that may get assigned with the constant. */
2613 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2614 aarch64_opnd_info
*operand
,
2616 int need_libopcodes_p
,
2619 if (reloc
->exp
.X_op
== O_constant
)
2622 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2624 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2625 reloc
->type
= BFD_RELOC_UNUSED
;
2629 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2630 /* Tell libopcodes to ignore this operand or not. This is helpful
2631 when one of the operands needs to be fixed up later but we need
2632 libopcodes to check the other operands. */
2633 operand
->skip
= skip_p
;
2637 /* Relocation modifiers. Each entry in the table contains the textual
2638 name for the relocation which may be placed before a symbol used as
2639 a load/store offset, or add immediate. It must be surrounded by a
2640 leading and trailing colon, for example:
2642 ldr x0, [x1, #:rello:varsym]
2643 add x0, x1, #:rello:varsym */
2645 struct reloc_table_entry
2649 bfd_reloc_code_real_type adr_type
;
2650 bfd_reloc_code_real_type adrp_type
;
2651 bfd_reloc_code_real_type movw_type
;
2652 bfd_reloc_code_real_type add_type
;
2653 bfd_reloc_code_real_type ldst_type
;
2654 bfd_reloc_code_real_type ld_literal_type
;
2657 static struct reloc_table_entry reloc_table
[] =
2659 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2664 BFD_RELOC_AARCH64_ADD_LO12
,
2665 BFD_RELOC_AARCH64_LDST_LO12
,
2668 /* Higher 21 bits of pc-relative page offset: ADRP */
2671 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2677 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2680 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2686 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2690 BFD_RELOC_AARCH64_MOVW_G0
,
2695 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2699 BFD_RELOC_AARCH64_MOVW_G0_S
,
2704 /* Less significant bits 0-15 of address/value: MOVK, no check */
2708 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2713 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2717 BFD_RELOC_AARCH64_MOVW_G1
,
2722 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2726 BFD_RELOC_AARCH64_MOVW_G1_S
,
2731 /* Less significant bits 16-31 of address/value: MOVK, no check */
2735 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2740 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2744 BFD_RELOC_AARCH64_MOVW_G2
,
2749 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2753 BFD_RELOC_AARCH64_MOVW_G2_S
,
2758 /* Less significant bits 32-47 of address/value: MOVK, no check */
2762 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2767 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2771 BFD_RELOC_AARCH64_MOVW_G3
,
2776 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2780 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2785 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2789 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2794 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2798 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2803 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2807 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2812 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2816 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2821 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2825 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2830 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2834 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2839 /* Get to the page containing GOT entry for a symbol. */
2842 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2846 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2848 /* 12 bit offset into the page containing GOT entry for that symbol. */
2854 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2857 /* 0-15 bits of address/value: MOVk, no check. */
2861 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2866 /* Most significant bits 16-31 of address/value: MOVZ. */
2870 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2875 /* 15 bit offset into the page containing GOT entry for that symbol. */
2881 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2884 /* Get to the page containing GOT TLS entry for a symbol */
2885 {"gottprel_g0_nc", 0,
2888 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2893 /* Get to the page containing GOT TLS entry for a symbol */
2897 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2902 /* Get to the page containing GOT TLS entry for a symbol */
2904 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2905 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2911 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2916 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2920 /* Lower 16 bits address/value: MOVk. */
2924 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2929 /* Most significant bits 16-31 of address/value: MOVZ. */
2933 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2938 /* Get to the page containing GOT TLS entry for a symbol */
2940 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2941 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2945 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2947 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2952 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2953 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2956 /* Get to the page containing GOT TLS entry for a symbol.
2957 The same as GD, we allocate two consecutive GOT slots
2958 for module index and module offset, the only difference
2959 with GD is the module offset should be initialized to
2960 zero without any outstanding runtime relocation. */
2962 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2963 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2969 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2970 {"tlsldm_lo12_nc", 0,
2974 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2978 /* 12 bit offset into the module TLS base address. */
2983 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2984 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2987 /* Same as dtprel_lo12, no overflow check. */
2988 {"dtprel_lo12_nc", 0,
2992 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2993 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2996 /* bits[23:12] of offset to the module TLS base address. */
3001 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3005 /* bits[15:0] of offset to the module TLS base address. */
3009 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3014 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3018 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3023 /* bits[31:16] of offset to the module TLS base address. */
3027 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3032 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3036 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3041 /* bits[47:32] of offset to the module TLS base address. */
3045 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3050 /* Lower 16 bit offset into GOT entry for a symbol */
3051 {"tlsdesc_off_g0_nc", 0,
3054 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3059 /* Higher 16 bit offset into GOT entry for a symbol */
3060 {"tlsdesc_off_g1", 0,
3063 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3068 /* Get to the page containing GOT TLS entry for a symbol */
3071 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3075 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3077 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3078 {"gottprel_lo12", 0,
3083 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3086 /* Get tp offset for a symbol. */
3091 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3095 /* Get tp offset for a symbol. */
3100 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3101 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3104 /* Get tp offset for a symbol. */
3109 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3113 /* Get tp offset for a symbol. */
3114 {"tprel_lo12_nc", 0,
3118 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3119 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3122 /* Most significant bits 32-47 of address/value: MOVZ. */
3126 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3131 /* Most significant bits 16-31 of address/value: MOVZ. */
3135 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3140 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3144 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3149 /* Most significant bits 0-15 of address/value: MOVZ. */
3153 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3158 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3162 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3167 /* 15bit offset from got entry to base address of GOT table. */
3173 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3176 /* 14bit offset from got entry to base address of GOT table. */
3182 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3186 /* Given the address of a pointer pointing to the textual name of a
3187 relocation as may appear in assembler source, attempt to find its
3188 details in reloc_table. The pointer will be updated to the character
3189 after the trailing colon. On failure, NULL will be returned;
3190 otherwise return the reloc_table_entry. */
3192 static struct reloc_table_entry
*
3193 find_reloc_table_entry (char **str
)
3196 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3198 int length
= strlen (reloc_table
[i
].name
);
3200 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3201 && (*str
)[length
] == ':')
3203 *str
+= (length
+ 1);
3204 return &reloc_table
[i
];
3211 /* Returns 0 if the relocation should never be forced,
3212 1 if the relocation must be forced, and -1 if either
3216 aarch64_force_reloc (unsigned int type
)
3220 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3221 /* Perform these "immediate" internal relocations
3222 even if the symbol is extern or weak. */
3225 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3226 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3227 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3228 /* Pseudo relocs that need to be fixed up according to
3232 case BFD_RELOC_AARCH64_ADD_LO12
:
3233 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3234 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3235 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3236 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3237 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3238 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3239 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3240 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3241 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3242 case BFD_RELOC_AARCH64_LDST128_LO12
:
3243 case BFD_RELOC_AARCH64_LDST16_LO12
:
3244 case BFD_RELOC_AARCH64_LDST32_LO12
:
3245 case BFD_RELOC_AARCH64_LDST64_LO12
:
3246 case BFD_RELOC_AARCH64_LDST8_LO12
:
3247 case BFD_RELOC_AARCH64_LDST_LO12
:
3248 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3249 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3250 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3251 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3252 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3253 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3254 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3255 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3256 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3257 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3258 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3259 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3260 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3261 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3262 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3263 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3264 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3265 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3266 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3267 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3268 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3269 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3270 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3271 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3272 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3273 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3274 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3275 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3276 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3277 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3278 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3279 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3280 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3281 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3282 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3283 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3284 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3285 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3286 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3287 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3288 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3289 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3290 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3291 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3292 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3293 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3294 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3295 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3296 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3297 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3298 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3299 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3300 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3301 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3302 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3303 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3304 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3305 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3306 /* Always leave these relocations for the linker. */
3315 aarch64_force_relocation (struct fix
*fixp
)
3317 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3320 return generic_force_reloc (fixp
);
3324 /* Mode argument to parse_shift and parser_shifter_operand. */
3325 enum parse_shift_mode
3327 SHIFTED_NONE
, /* no shifter allowed */
3328 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3330 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3332 SHIFTED_LSL
, /* bare "lsl #n" */
3333 SHIFTED_MUL
, /* bare "mul #n" */
3334 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3335 SHIFTED_MUL_VL
, /* "mul vl" */
3336 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3339 /* Parse a <shift> operator on an AArch64 data processing instruction.
3340 Return TRUE on success; otherwise return FALSE. */
3342 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3344 const struct aarch64_name_value_pair
*shift_op
;
3345 enum aarch64_modifier_kind kind
;
3351 for (p
= *str
; ISALPHA (*p
); p
++)
3356 set_syntax_error (_("shift expression expected"));
3360 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3362 if (shift_op
== NULL
)
3364 set_syntax_error (_("shift operator expected"));
3368 kind
= aarch64_get_operand_modifier (shift_op
);
3370 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3372 set_syntax_error (_("invalid use of 'MSL'"));
3376 if (kind
== AARCH64_MOD_MUL
3377 && mode
!= SHIFTED_MUL
3378 && mode
!= SHIFTED_MUL_VL
)
3380 set_syntax_error (_("invalid use of 'MUL'"));
3386 case SHIFTED_LOGIC_IMM
:
3387 if (aarch64_extend_operator_p (kind
))
3389 set_syntax_error (_("extending shift is not permitted"));
3394 case SHIFTED_ARITH_IMM
:
3395 if (kind
== AARCH64_MOD_ROR
)
3397 set_syntax_error (_("'ROR' shift is not permitted"));
3403 if (kind
!= AARCH64_MOD_LSL
)
3405 set_syntax_error (_("only 'LSL' shift is permitted"));
3411 if (kind
!= AARCH64_MOD_MUL
)
3413 set_syntax_error (_("only 'MUL' is permitted"));
3418 case SHIFTED_MUL_VL
:
3419 /* "MUL VL" consists of two separate tokens. Require the first
3420 token to be "MUL" and look for a following "VL". */
3421 if (kind
== AARCH64_MOD_MUL
)
3423 skip_whitespace (p
);
3424 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3427 kind
= AARCH64_MOD_MUL_VL
;
3431 set_syntax_error (_("only 'MUL VL' is permitted"));
3434 case SHIFTED_REG_OFFSET
:
3435 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3436 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3438 set_fatal_syntax_error
3439 (_("invalid shift for the register offset addressing mode"));
3444 case SHIFTED_LSL_MSL
:
3445 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3447 set_syntax_error (_("invalid shift operator"));
3456 /* Whitespace can appear here if the next thing is a bare digit. */
3457 skip_whitespace (p
);
3459 /* Parse shift amount. */
3461 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3462 exp
.X_op
= O_absent
;
3465 if (is_immediate_prefix (*p
))
3470 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3472 if (kind
== AARCH64_MOD_MUL_VL
)
3473 /* For consistency, give MUL VL the same shift amount as an implicit
3475 operand
->shifter
.amount
= 1;
3476 else if (exp
.X_op
== O_absent
)
3478 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3480 set_syntax_error (_("missing shift amount"));
3483 operand
->shifter
.amount
= 0;
3485 else if (exp
.X_op
!= O_constant
)
3487 set_syntax_error (_("constant shift amount required"));
3490 /* For parsing purposes, MUL #n has no inherent range. The range
3491 depends on the operand and will be checked by operand-specific
3493 else if (kind
!= AARCH64_MOD_MUL
3494 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3496 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3501 operand
->shifter
.amount
= exp
.X_add_number
;
3502 operand
->shifter
.amount_present
= 1;
3505 operand
->shifter
.operator_present
= 1;
3506 operand
->shifter
.kind
= kind
;
3512 /* Parse a <shifter_operand> for a data processing instruction:
3515 #<immediate>, LSL #imm
3517 Validation of immediate operands is deferred to md_apply_fix.
3519 Return TRUE on success; otherwise return FALSE. */
3522 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3523 enum parse_shift_mode mode
)
3527 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3532 /* Accept an immediate expression. */
3533 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3537 /* Accept optional LSL for arithmetic immediate values. */
3538 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3539 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3542 /* Not accept any shifter for logical immediate values. */
3543 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3544 && parse_shift (&p
, operand
, mode
))
3546 set_syntax_error (_("unexpected shift operator"));
3554 /* Parse a <shifter_operand> for a data processing instruction:
3559 #<immediate>, LSL #imm
3561 where <shift> is handled by parse_shift above, and the last two
3562 cases are handled by the function above.
3564 Validation of immediate operands is deferred to md_apply_fix.
3566 Return TRUE on success; otherwise return FALSE. */
3569 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3570 enum parse_shift_mode mode
)
3572 const reg_entry
*reg
;
3573 aarch64_opnd_qualifier_t qualifier
;
3574 enum aarch64_operand_class opd_class
3575 = aarch64_get_operand_class (operand
->type
);
3577 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3580 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3582 set_syntax_error (_("unexpected register in the immediate operand"));
3586 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3588 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3592 operand
->reg
.regno
= reg
->number
;
3593 operand
->qualifier
= qualifier
;
3595 /* Accept optional shift operation on register. */
3596 if (! skip_past_comma (str
))
3599 if (! parse_shift (str
, operand
, mode
))
3604 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3607 (_("integer register expected in the extended/shifted operand "
3612 /* We have a shifted immediate variable. */
3613 return parse_shifter_operand_imm (str
, operand
, mode
);
3616 /* Return TRUE on success; return FALSE otherwise. */
3619 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3620 enum parse_shift_mode mode
)
3624 /* Determine if we have the sequence of characters #: or just :
3625 coming next. If we do, then we check for a :rello: relocation
3626 modifier. If we don't, punt the whole lot to
3627 parse_shifter_operand. */
3629 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3631 struct reloc_table_entry
*entry
;
3639 /* Try to parse a relocation. Anything else is an error. */
3640 if (!(entry
= find_reloc_table_entry (str
)))
3642 set_syntax_error (_("unknown relocation modifier"));
3646 if (entry
->add_type
== 0)
3649 (_("this relocation modifier is not allowed on this instruction"));
3653 /* Save str before we decompose it. */
3656 /* Next, we parse the expression. */
3657 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3661 /* Record the relocation type (use the ADD variant here). */
3662 inst
.reloc
.type
= entry
->add_type
;
3663 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3665 /* If str is empty, we've reached the end, stop here. */
3669 /* Otherwise, we have a shifted reloc modifier, so rewind to
3670 recover the variable name and continue parsing for the shifter. */
3672 return parse_shifter_operand_imm (str
, operand
, mode
);
3675 return parse_shifter_operand (str
, operand
, mode
);
3678 /* Parse all forms of an address expression. Information is written
3679 to *OPERAND and/or inst.reloc.
3681 The A64 instruction set has the following addressing modes:
3684 [base] // in SIMD ld/st structure
3685 [base{,#0}] // in ld/st exclusive
3687 [base,Xm{,LSL #imm}]
3688 [base,Xm,SXTX {#imm}]
3689 [base,Wm,(S|U)XTW {#imm}]
3691 [base]! // in ldraa/ldrab exclusive
3695 [base],Xm // in SIMD ld/st structure
3696 PC-relative (literal)
3700 [base,Zm.D{,LSL #imm}]
3701 [base,Zm.S,(S|U)XTW {#imm}]
3702 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3706 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3707 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3708 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3710 (As a convenience, the notation "=immediate" is permitted in conjunction
3711 with the pc-relative literal load instructions to automatically place an
3712 immediate value or symbolic address in a nearby literal pool and generate
3713 a hidden label which references it.)
3715 Upon a successful parsing, the address structure in *OPERAND will be
3716 filled in the following way:
3718 .base_regno = <base>
3719 .offset.is_reg // 1 if the offset is a register
3721 .offset.regno = <Rm>
3723 For different addressing modes defined in the A64 ISA:
3726 .pcrel=0; .preind=1; .postind=0; .writeback=0
3728 .pcrel=0; .preind=1; .postind=0; .writeback=1
3730 .pcrel=0; .preind=0; .postind=1; .writeback=1
3731 PC-relative (literal)
3732 .pcrel=1; .preind=1; .postind=0; .writeback=0
3734 The shift/extension information, if any, will be stored in .shifter.
3735 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3736 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3737 corresponding register.
3739 BASE_TYPE says which types of base register should be accepted and
3740 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3741 is the type of shifter that is allowed for immediate offsets,
3742 or SHIFTED_NONE if none.
3744 In all other respects, it is the caller's responsibility to check
3745 for addressing modes not supported by the instruction, and to set
3749 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3750 aarch64_opnd_qualifier_t
*base_qualifier
,
3751 aarch64_opnd_qualifier_t
*offset_qualifier
,
3752 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3753 enum parse_shift_mode imm_shift_mode
)
3756 const reg_entry
*reg
;
3757 expressionS
*exp
= &inst
.reloc
.exp
;
3759 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3760 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3761 if (! skip_past_char (&p
, '['))
3763 /* =immediate or label. */
3764 operand
->addr
.pcrel
= 1;
3765 operand
->addr
.preind
= 1;
3767 /* #:<reloc_op>:<symbol> */
3768 skip_past_char (&p
, '#');
3769 if (skip_past_char (&p
, ':'))
3771 bfd_reloc_code_real_type ty
;
3772 struct reloc_table_entry
*entry
;
3774 /* Try to parse a relocation modifier. Anything else is
3776 entry
= find_reloc_table_entry (&p
);
3779 set_syntax_error (_("unknown relocation modifier"));
3783 switch (operand
->type
)
3785 case AARCH64_OPND_ADDR_PCREL21
:
3787 ty
= entry
->adr_type
;
3791 ty
= entry
->ld_literal_type
;
3798 (_("this relocation modifier is not allowed on this "
3804 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3806 set_syntax_error (_("invalid relocation expression"));
3809 /* #:<reloc_op>:<expr> */
3810 /* Record the relocation type. */
3811 inst
.reloc
.type
= ty
;
3812 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3816 if (skip_past_char (&p
, '='))
3817 /* =immediate; need to generate the literal in the literal pool. */
3818 inst
.gen_lit_pool
= 1;
3820 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3822 set_syntax_error (_("invalid address"));
3833 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3834 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3836 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3839 operand
->addr
.base_regno
= reg
->number
;
3842 if (skip_past_comma (&p
))
3845 operand
->addr
.preind
= 1;
3847 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3850 if (!aarch64_check_reg_type (reg
, offset_type
))
3852 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3857 operand
->addr
.offset
.regno
= reg
->number
;
3858 operand
->addr
.offset
.is_reg
= 1;
3859 /* Shifted index. */
3860 if (skip_past_comma (&p
))
3863 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3864 /* Use the diagnostics set in parse_shift, so not set new
3865 error message here. */
3869 [base,Xm] # For vector plus scalar SVE2 indexing.
3870 [base,Xm{,LSL #imm}]
3871 [base,Xm,SXTX {#imm}]
3872 [base,Wm,(S|U)XTW {#imm}] */
3873 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3874 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3875 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3877 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3879 set_syntax_error (_("invalid use of 32-bit register offset"));
3882 if (aarch64_get_qualifier_esize (*base_qualifier
)
3883 != aarch64_get_qualifier_esize (*offset_qualifier
)
3884 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3885 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3886 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3888 set_syntax_error (_("offset has different size from base"));
3892 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3894 set_syntax_error (_("invalid use of 64-bit register offset"));
3900 /* [Xn,#:<reloc_op>:<symbol> */
3901 skip_past_char (&p
, '#');
3902 if (skip_past_char (&p
, ':'))
3904 struct reloc_table_entry
*entry
;
3906 /* Try to parse a relocation modifier. Anything else is
3908 if (!(entry
= find_reloc_table_entry (&p
)))
3910 set_syntax_error (_("unknown relocation modifier"));
3914 if (entry
->ldst_type
== 0)
3917 (_("this relocation modifier is not allowed on this "
3922 /* [Xn,#:<reloc_op>: */
3923 /* We now have the group relocation table entry corresponding to
3924 the name in the assembler source. Next, we parse the
3926 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3928 set_syntax_error (_("invalid relocation expression"));
3932 /* [Xn,#:<reloc_op>:<expr> */
3933 /* Record the load/store relocation type. */
3934 inst
.reloc
.type
= entry
->ldst_type
;
3935 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3939 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3941 set_syntax_error (_("invalid expression in the address"));
3945 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3946 /* [Xn,<expr>,<shifter> */
3947 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3953 if (! skip_past_char (&p
, ']'))
3955 set_syntax_error (_("']' expected"));
3959 if (skip_past_char (&p
, '!'))
3961 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3963 set_syntax_error (_("register offset not allowed in pre-indexed "
3964 "addressing mode"));
3968 operand
->addr
.writeback
= 1;
3970 else if (skip_past_comma (&p
))
3973 operand
->addr
.postind
= 1;
3974 operand
->addr
.writeback
= 1;
3976 if (operand
->addr
.preind
)
3978 set_syntax_error (_("cannot combine pre- and post-indexing"));
3982 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3986 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3988 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3992 operand
->addr
.offset
.regno
= reg
->number
;
3993 operand
->addr
.offset
.is_reg
= 1;
3995 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3998 set_syntax_error (_("invalid expression in the address"));
4003 /* If at this point neither .preind nor .postind is set, we have a
4004 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4005 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4006 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4008 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4010 if (operand
->addr
.writeback
)
4012 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4014 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4015 operand
->addr
.offset
.is_reg
= 0;
4016 operand
->addr
.offset
.imm
= 0;
4017 operand
->addr
.preind
= 1;
4022 set_syntax_error (_("missing offset in the pre-indexed address"));
4028 operand
->addr
.preind
= 1;
4029 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4031 operand
->addr
.offset
.is_reg
= 1;
4032 operand
->addr
.offset
.regno
= REG_ZR
;
4033 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4037 inst
.reloc
.exp
.X_op
= O_constant
;
4038 inst
.reloc
.exp
.X_add_number
= 0;
4047 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4050 parse_address (char **str
, aarch64_opnd_info
*operand
)
4052 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4053 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4054 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4057 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4058 The arguments have the same meaning as for parse_address_main.
4059 Return TRUE on success. */
4061 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4062 aarch64_opnd_qualifier_t
*base_qualifier
,
4063 aarch64_opnd_qualifier_t
*offset_qualifier
)
4065 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4066 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4070 /* Parse a register X0-X30. The register must be 64-bit and register 31
4073 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4075 const reg_entry
*reg
= parse_reg (str
);
4076 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4078 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
4081 operand
->reg
.regno
= reg
->number
;
4082 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4086 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4087 Return TRUE on success; otherwise return FALSE. */
4089 parse_half (char **str
, int *internal_fixup_p
)
4093 skip_past_char (&p
, '#');
4095 gas_assert (internal_fixup_p
);
4096 *internal_fixup_p
= 0;
4100 struct reloc_table_entry
*entry
;
4102 /* Try to parse a relocation. Anything else is an error. */
4105 if (!(entry
= find_reloc_table_entry (&p
)))
4107 set_syntax_error (_("unknown relocation modifier"));
4111 if (entry
->movw_type
== 0)
4114 (_("this relocation modifier is not allowed on this instruction"));
4118 inst
.reloc
.type
= entry
->movw_type
;
4121 *internal_fixup_p
= 1;
4123 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4130 /* Parse an operand for an ADRP instruction:
4132 Return TRUE on success; otherwise return FALSE. */
4135 parse_adrp (char **str
)
4142 struct reloc_table_entry
*entry
;
4144 /* Try to parse a relocation. Anything else is an error. */
4146 if (!(entry
= find_reloc_table_entry (&p
)))
4148 set_syntax_error (_("unknown relocation modifier"));
4152 if (entry
->adrp_type
== 0)
4155 (_("this relocation modifier is not allowed on this instruction"));
4159 inst
.reloc
.type
= entry
->adrp_type
;
4162 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4164 inst
.reloc
.pc_rel
= 1;
4165 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4171 /* Miscellaneous. */
4173 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4174 of SIZE tokens in which index I gives the token for field value I,
4175 or is null if field value I is invalid. REG_TYPE says which register
4176 names should be treated as registers rather than as symbolic immediates.
4178 Return true on success, moving *STR past the operand and storing the
4179 field value in *VAL. */
4182 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4183 size_t size
, aarch64_reg_type reg_type
)
4189 /* Match C-like tokens. */
4191 while (ISALNUM (*q
))
4194 for (i
= 0; i
< size
; ++i
)
4196 && strncasecmp (array
[i
], p
, q
- p
) == 0
4197 && array
[i
][q
- p
] == 0)
4204 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4207 if (exp
.X_op
== O_constant
4208 && (uint64_t) exp
.X_add_number
< size
)
4210 *val
= exp
.X_add_number
;
4215 /* Use the default error for this operand. */
4219 /* Parse an option for a preload instruction. Returns the encoding for the
4220 option, or PARSE_FAIL. */
4223 parse_pldop (char **str
)
4226 const struct aarch64_name_value_pair
*o
;
4229 while (ISALNUM (*q
))
4232 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4240 /* Parse an option for a barrier instruction. Returns the encoding for the
4241 option, or PARSE_FAIL. */
4244 parse_barrier (char **str
)
4247 const struct aarch64_name_value_pair
*o
;
4250 while (ISALPHA (*q
))
4253 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4261 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4262 return 0 if successful. Otherwise return PARSE_FAIL. */
4265 parse_barrier_psb (char **str
,
4266 const struct aarch64_name_value_pair
** hint_opt
)
4269 const struct aarch64_name_value_pair
*o
;
4272 while (ISALPHA (*q
))
4275 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4278 set_fatal_syntax_error
4279 ( _("unknown or missing option to PSB/TSB"));
4283 if (o
->value
!= 0x11)
4285 /* PSB only accepts option name 'CSYNC'. */
4287 (_("the specified option is not accepted for PSB/TSB"));
4296 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4297 return 0 if successful. Otherwise return PARSE_FAIL. */
4300 parse_bti_operand (char **str
,
4301 const struct aarch64_name_value_pair
** hint_opt
)
4304 const struct aarch64_name_value_pair
*o
;
4307 while (ISALPHA (*q
))
4310 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4313 set_fatal_syntax_error
4314 ( _("unknown option to BTI"));
4320 /* Valid BTI operands. */
4328 (_("unknown option to BTI"));
4337 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4338 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4343 Side effect: Update STR with current parse position of success.
4346 static const reg_entry
*
4347 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4348 aarch64_opnd_qualifier_t
*qualifier
)
4350 struct vector_type_el vectype
;
4351 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4356 if (vectype
.type
== NT_invtype
)
4357 *qualifier
= AARCH64_OPND_QLF_NIL
;
4360 *qualifier
= vectype_to_qualifier (&vectype
);
4361 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4368 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4373 Function return TRUE if immediate was found, or FALSE.
4376 parse_sme_immediate (char **str
, int64_t *imm
)
4379 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4386 /* Parse index with vector select register and immediate:
4390 where <Wv> is in W12-W15 range and # is optional for immediate.
4392 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4395 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4399 parse_sme_za_hv_tiles_operand_index (char **str
,
4400 int *vector_select_register
,
4403 const reg_entry
*reg
;
4405 if (!skip_past_char (str
, '['))
4407 set_syntax_error (_("expected '['"));
4411 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4412 reg
= parse_reg (str
);
4413 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4414 || reg
->number
< 12 || reg
->number
> 15)
4416 set_syntax_error (_("expected vector select register W12-W15"));
4419 *vector_select_register
= reg
->number
;
4421 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4423 set_syntax_error (_("expected ','"));
4427 if (!parse_sme_immediate (str
, imm
))
4429 set_syntax_error (_("index offset immediate expected"));
4433 if (!skip_past_char (str
, ']'))
4435 set_syntax_error (_("expected ']'"));
4442 /* Parse SME ZA horizontal or vertical vector access to tiles.
4443 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4444 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4445 contains <Wv> select register and corresponding optional IMMEDIATE.
4446 In addition QUALIFIER is extracted.
4448 Field format examples:
4450 ZA0<HV>.B[<Wv>, #<imm>]
4451 <ZAn><HV>.H[<Wv>, #<imm>]
4452 <ZAn><HV>.S[<Wv>, #<imm>]
4453 <ZAn><HV>.D[<Wv>, #<imm>]
4454 <ZAn><HV>.Q[<Wv>, #<imm>]
4456 Function returns <ZAda> register number or PARSE_FAIL.
4459 parse_sme_za_hv_tiles_operand (char **str
,
4460 enum sme_hv_slice
*slice_indicator
,
4461 int *vector_select_register
,
4463 aarch64_opnd_qualifier_t
*qualifier
)
4468 const reg_entry
*reg
;
4470 reg
= parse_reg_with_qual (str
, REG_TYPE_ZATHV
, qualifier
);
4474 *slice_indicator
= (aarch64_check_reg_type (reg
, REG_TYPE_ZATH
)
4477 regno
= reg
->number
;
4481 case AARCH64_OPND_QLF_S_B
:
4484 case AARCH64_OPND_QLF_S_H
:
4487 case AARCH64_OPND_QLF_S_S
:
4490 case AARCH64_OPND_QLF_S_D
:
4493 case AARCH64_OPND_QLF_S_Q
:
4497 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4501 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4505 /* Check if optional index offset is in the range for instruction
4507 if (imm_value
< 0 || imm_value
> imm_limit
)
4509 set_syntax_error (_("index offset out of range"));
4520 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4521 enum sme_hv_slice
*slice_indicator
,
4522 int *vector_select_register
,
4524 aarch64_opnd_qualifier_t
*qualifier
)
4528 if (!skip_past_char (str
, '{'))
4530 set_syntax_error (_("expected '{'"));
4534 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4535 vector_select_register
, imm
,
4538 if (regno
== PARSE_FAIL
)
4541 if (!skip_past_char (str
, '}'))
4543 set_syntax_error (_("expected '}'"));
4550 /* Parse list of up to eight 64-bit element tile names separated by commas in
4551 SME's ZERO instruction:
4555 Function returns <mask>:
4557 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4560 parse_sme_zero_mask(char **str
)
4564 aarch64_opnd_qualifier_t qualifier
;
4570 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4575 if (reg
->type
== REG_TYPE_ZA
)
4577 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4579 set_syntax_error ("ZA should not have a size suffix");
4582 /* { ZA } is assembled as all-ones immediate. */
4587 int regno
= reg
->number
;
4588 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4590 /* { ZA0.B } is assembled as all-ones immediate. */
4593 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4594 mask
|= 0x55 << regno
;
4595 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4596 mask
|= 0x11 << regno
;
4597 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4598 mask
|= 0x01 << regno
;
4599 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4601 set_syntax_error (_("ZA tile masks do not operate at .Q"
4605 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4607 set_syntax_error (_("missing ZA tile size"));
4612 set_syntax_error (_("invalid ZA tile"));
4617 while (skip_past_char (&q
, ','));
4623 /* Wraps in curly braces <mask> operand ZERO instruction:
4627 Function returns value of <mask> bit-field.
4630 parse_sme_list_of_64bit_tiles (char **str
)
4634 if (!skip_past_char (str
, '{'))
4636 set_syntax_error (_("expected '{'"));
4640 /* Empty <mask> list is an all-zeros immediate. */
4641 if (!skip_past_char (str
, '}'))
4643 regno
= parse_sme_zero_mask (str
);
4644 if (regno
== PARSE_FAIL
)
4647 if (!skip_past_char (str
, '}'))
4649 set_syntax_error (_("expected '}'"));
4659 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4665 Function returns <Wv> or PARSE_FAIL.
4668 parse_sme_za_array (char **str
, int *imm
)
4675 const reg_entry
*reg
= parse_reg (&q
);
4676 if (!reg
|| reg
->type
!= REG_TYPE_ZA
)
4678 set_syntax_error (_("expected ZA array"));
4682 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4685 if (imm_value
< 0 || imm_value
> 15)
4687 set_syntax_error (_("offset out of range"));
4696 /* Parse streaming mode operand for SMSTART and SMSTOP.
4700 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4703 parse_sme_sm_za (char **str
)
4708 while (ISALPHA (*q
))
4712 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4714 set_syntax_error (_("expected SM or ZA operand"));
4719 return TOLOWER (p
[0]);
4722 /* Parse the name of the source scalable predicate register, the index base
4723 register W12-W15 and the element index. Function performs element index
4724 limit checks as well as qualifier type checks.
4726 <Pn>.<T>[<Wv>, <imm>]
4727 <Pn>.<T>[<Wv>, #<imm>]
4729 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4731 Function returns <Pn>, or PARSE_FAIL.
4734 parse_sme_pred_reg_with_index(char **str
,
4735 int *index_base_reg
,
4737 aarch64_opnd_qualifier_t
*qualifier
)
4742 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4746 regno
= reg
->number
;
4750 case AARCH64_OPND_QLF_S_B
:
4753 case AARCH64_OPND_QLF_S_H
:
4756 case AARCH64_OPND_QLF_S_S
:
4759 case AARCH64_OPND_QLF_S_D
:
4763 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4767 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4770 if (imm_value
< 0 || imm_value
> imm_limit
)
4772 set_syntax_error (_("element index out of range for given variant"));
4781 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4782 Returns the encoding for the option, or PARSE_FAIL.
4784 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4785 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4787 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4788 field, otherwise as a system register.
4792 parse_sys_reg (char **str
, htab_t sys_regs
,
4793 int imple_defined_p
, int pstatefield_p
,
4797 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4798 const aarch64_sys_reg
*o
;
4802 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4803 if (p
< buf
+ (sizeof (buf
) - 1))
4804 *p
++ = TOLOWER (*q
);
4807 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4808 valid system register. This is enforced by construction of the hash
4810 if (p
- buf
!= q
- *str
)
4813 o
= str_hash_find (sys_regs
, buf
);
4816 if (!imple_defined_p
)
4820 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4821 unsigned int op0
, op1
, cn
, cm
, op2
;
4823 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4826 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4828 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4835 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4836 as_bad (_("selected processor does not support PSTATE field "
4839 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4840 o
->value
, o
->flags
, o
->features
))
4841 as_bad (_("selected processor does not support system register "
4843 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4844 as_warn (_("system register name '%s' is deprecated and may be "
4845 "removed in a future release"), buf
);
4855 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4856 for the option, or NULL. */
4858 static const aarch64_sys_ins_reg
*
4859 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4862 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4863 const aarch64_sys_ins_reg
*o
;
4866 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4867 if (p
< buf
+ (sizeof (buf
) - 1))
4868 *p
++ = TOLOWER (*q
);
4871 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4872 valid system register. This is enforced by construction of the hash
4874 if (p
- buf
!= q
- *str
)
4877 o
= str_hash_find (sys_ins_regs
, buf
);
4881 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4882 o
->name
, o
->value
, o
->flags
, 0))
4883 as_bad (_("selected processor does not support system register "
4885 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4886 as_warn (_("system register name '%s' is deprecated and may be "
4887 "removed in a future release"), buf
);
4893 #define po_char_or_fail(chr) do { \
4894 if (! skip_past_char (&str, chr)) \
4898 #define po_reg_or_fail(regtype) do { \
4899 reg = aarch64_reg_parse (&str, regtype, NULL); \
4902 set_default_error (); \
4907 #define po_int_reg_or_fail(reg_type) do { \
4908 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4909 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4911 set_default_error (); \
4914 info->reg.regno = reg->number; \
4915 info->qualifier = qualifier; \
4918 #define po_imm_nc_or_fail() do { \
4919 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4923 #define po_imm_or_fail(min, max) do { \
4924 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4926 if (val < min || val > max) \
4928 set_fatal_syntax_error (_("immediate value out of range "\
4929 #min " to "#max)); \
4934 #define po_enum_or_fail(array) do { \
4935 if (!parse_enum_string (&str, &val, array, \
4936 ARRAY_SIZE (array), imm_reg_type)) \
4940 #define po_misc_or_fail(expr) do { \
4945 /* encode the 12-bit imm field of Add/sub immediate */
4946 static inline uint32_t
4947 encode_addsub_imm (uint32_t imm
)
4952 /* encode the shift amount field of Add/sub immediate */
4953 static inline uint32_t
4954 encode_addsub_imm_shift_amount (uint32_t cnt
)
4960 /* encode the imm field of Adr instruction */
4961 static inline uint32_t
4962 encode_adr_imm (uint32_t imm
)
4964 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4965 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4968 /* encode the immediate field of Move wide immediate */
4969 static inline uint32_t
4970 encode_movw_imm (uint32_t imm
)
4975 /* encode the 26-bit offset of unconditional branch */
4976 static inline uint32_t
4977 encode_branch_ofs_26 (uint32_t ofs
)
4979 return ofs
& ((1 << 26) - 1);
4982 /* encode the 19-bit offset of conditional branch and compare & branch */
4983 static inline uint32_t
4984 encode_cond_branch_ofs_19 (uint32_t ofs
)
4986 return (ofs
& ((1 << 19) - 1)) << 5;
4989 /* encode the 19-bit offset of ld literal */
4990 static inline uint32_t
4991 encode_ld_lit_ofs_19 (uint32_t ofs
)
4993 return (ofs
& ((1 << 19) - 1)) << 5;
4996 /* Encode the 14-bit offset of test & branch. */
4997 static inline uint32_t
4998 encode_tst_branch_ofs_14 (uint32_t ofs
)
5000 return (ofs
& ((1 << 14) - 1)) << 5;
5003 /* Encode the 16-bit imm field of svc/hvc/smc. */
5004 static inline uint32_t
5005 encode_svc_imm (uint32_t imm
)
5010 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5011 static inline uint32_t
5012 reencode_addsub_switch_add_sub (uint32_t opcode
)
5014 return opcode
^ (1 << 30);
5017 static inline uint32_t
5018 reencode_movzn_to_movz (uint32_t opcode
)
5020 return opcode
| (1 << 30);
5023 static inline uint32_t
5024 reencode_movzn_to_movn (uint32_t opcode
)
5026 return opcode
& ~(1 << 30);
5029 /* Overall per-instruction processing. */
5031 /* We need to be able to fix up arbitrary expressions in some statements.
5032 This is so that we can handle symbols that are an arbitrary distance from
5033 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5034 which returns part of an address in a form which will be valid for
5035 a data instruction. We do this by pushing the expression into a symbol
5036 in the expr_section, and creating a fix for that. */
5039 fix_new_aarch64 (fragS
* frag
,
5054 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5058 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5065 /* Diagnostics on operands errors. */
5067 /* By default, output verbose error message.
5068 Disable the verbose error message by -mno-verbose-error. */
5069 static int verbose_error_p
= 1;
5071 #ifdef DEBUG_AARCH64
5072 /* N.B. this is only for the purpose of debugging. */
5073 const char* operand_mismatch_kind_names
[] =
5076 "AARCH64_OPDE_RECOVERABLE",
5077 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5078 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5079 "AARCH64_OPDE_SYNTAX_ERROR",
5080 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5081 "AARCH64_OPDE_INVALID_VARIANT",
5082 "AARCH64_OPDE_OUT_OF_RANGE",
5083 "AARCH64_OPDE_UNALIGNED",
5084 "AARCH64_OPDE_REG_LIST",
5085 "AARCH64_OPDE_OTHER_ERROR",
5087 #endif /* DEBUG_AARCH64 */
5089 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5091 When multiple errors of different kinds are found in the same assembly
5092 line, only the error of the highest severity will be picked up for
5093 issuing the diagnostics. */
5096 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5097 enum aarch64_operand_error_kind rhs
)
5099 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5100 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5101 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5102 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5103 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5104 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5105 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5106 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5107 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5108 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5109 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5113 /* Helper routine to get the mnemonic name from the assembly instruction
5114 line; should only be called for the diagnosis purpose, as there is
5115 string copy operation involved, which may affect the runtime
5116 performance if used in elsewhere. */
5119 get_mnemonic_name (const char *str
)
5121 static char mnemonic
[32];
5124 /* Get the first 15 bytes and assume that the full name is included. */
5125 strncpy (mnemonic
, str
, 31);
5126 mnemonic
[31] = '\0';
5128 /* Scan up to the end of the mnemonic, which must end in white space,
5129 '.', or end of string. */
5130 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5135 /* Append '...' to the truncated long name. */
5136 if (ptr
- mnemonic
== 31)
5137 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5143 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5145 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5146 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5149 /* Data structures storing one user error in the assembly code related to
5152 struct operand_error_record
5154 const aarch64_opcode
*opcode
;
5155 aarch64_operand_error detail
;
5156 struct operand_error_record
*next
;
5159 typedef struct operand_error_record operand_error_record
;
5161 struct operand_errors
5163 operand_error_record
*head
;
5164 operand_error_record
*tail
;
5167 typedef struct operand_errors operand_errors
;
5169 /* Top-level data structure reporting user errors for the current line of
5171 The way md_assemble works is that all opcodes sharing the same mnemonic
5172 name are iterated to find a match to the assembly line. In this data
5173 structure, each of the such opcodes will have one operand_error_record
5174 allocated and inserted. In other words, excessive errors related with
5175 a single opcode are disregarded. */
5176 operand_errors operand_error_report
;
5178 /* Free record nodes. */
5179 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5181 /* Initialize the data structure that stores the operand mismatch
5182 information on assembling one line of the assembly code. */
5184 init_operand_error_report (void)
5186 if (operand_error_report
.head
!= NULL
)
5188 gas_assert (operand_error_report
.tail
!= NULL
);
5189 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5190 free_opnd_error_record_nodes
= operand_error_report
.head
;
5191 operand_error_report
.head
= NULL
;
5192 operand_error_report
.tail
= NULL
;
5195 gas_assert (operand_error_report
.tail
== NULL
);
5198 /* Return TRUE if some operand error has been recorded during the
5199 parsing of the current assembly line using the opcode *OPCODE;
5200 otherwise return FALSE. */
5202 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5204 operand_error_record
*record
= operand_error_report
.head
;
5205 return record
&& record
->opcode
== opcode
;
5208 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5209 OPCODE field is initialized with OPCODE.
5210 N.B. only one record for each opcode, i.e. the maximum of one error is
5211 recorded for each instruction template. */
5214 add_operand_error_record (const operand_error_record
* new_record
)
5216 const aarch64_opcode
*opcode
= new_record
->opcode
;
5217 operand_error_record
* record
= operand_error_report
.head
;
5219 /* The record may have been created for this opcode. If not, we need
5221 if (! opcode_has_operand_error_p (opcode
))
5223 /* Get one empty record. */
5224 if (free_opnd_error_record_nodes
== NULL
)
5226 record
= XNEW (operand_error_record
);
5230 record
= free_opnd_error_record_nodes
;
5231 free_opnd_error_record_nodes
= record
->next
;
5233 record
->opcode
= opcode
;
5234 /* Insert at the head. */
5235 record
->next
= operand_error_report
.head
;
5236 operand_error_report
.head
= record
;
5237 if (operand_error_report
.tail
== NULL
)
5238 operand_error_report
.tail
= record
;
5240 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5241 && record
->detail
.index
<= new_record
->detail
.index
5242 && operand_error_higher_severity_p (record
->detail
.kind
,
5243 new_record
->detail
.kind
))
5245 /* In the case of multiple errors found on operands related with a
5246 single opcode, only record the error of the leftmost operand and
5247 only if the error is of higher severity. */
5248 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5249 " the existing error %s on operand %d",
5250 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5251 new_record
->detail
.index
,
5252 operand_mismatch_kind_names
[record
->detail
.kind
],
5253 record
->detail
.index
);
5257 record
->detail
= new_record
->detail
;
5261 record_operand_error_info (const aarch64_opcode
*opcode
,
5262 aarch64_operand_error
*error_info
)
5264 operand_error_record record
;
5265 record
.opcode
= opcode
;
5266 record
.detail
= *error_info
;
5267 add_operand_error_record (&record
);
5270 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5271 error message *ERROR, for operand IDX (count from 0). */
5274 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5275 enum aarch64_operand_error_kind kind
,
5278 aarch64_operand_error info
;
5279 memset(&info
, 0, sizeof (info
));
5283 info
.non_fatal
= false;
5284 record_operand_error_info (opcode
, &info
);
5288 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5289 enum aarch64_operand_error_kind kind
,
5290 const char* error
, const int *extra_data
)
5292 aarch64_operand_error info
;
5296 info
.data
[0].i
= extra_data
[0];
5297 info
.data
[1].i
= extra_data
[1];
5298 info
.data
[2].i
= extra_data
[2];
5299 info
.non_fatal
= false;
5300 record_operand_error_info (opcode
, &info
);
5304 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5305 const char* error
, int lower_bound
,
5308 int data
[3] = {lower_bound
, upper_bound
, 0};
5309 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5313 /* Remove the operand error record for *OPCODE. */
5314 static void ATTRIBUTE_UNUSED
5315 remove_operand_error_record (const aarch64_opcode
*opcode
)
5317 if (opcode_has_operand_error_p (opcode
))
5319 operand_error_record
* record
= operand_error_report
.head
;
5320 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5321 operand_error_report
.head
= record
->next
;
5322 record
->next
= free_opnd_error_record_nodes
;
5323 free_opnd_error_record_nodes
= record
;
5324 if (operand_error_report
.head
== NULL
)
5326 gas_assert (operand_error_report
.tail
== record
);
5327 operand_error_report
.tail
= NULL
;
5332 /* Given the instruction in *INSTR, return the index of the best matched
5333 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5335 Return -1 if there is no qualifier sequence; return the first match
5336 if there is multiple matches found. */
5339 find_best_match (const aarch64_inst
*instr
,
5340 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5342 int i
, num_opnds
, max_num_matched
, idx
;
5344 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5347 DEBUG_TRACE ("no operand");
5351 max_num_matched
= 0;
5354 /* For each pattern. */
5355 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5358 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5360 /* Most opcodes has much fewer patterns in the list. */
5361 if (empty_qualifier_sequence_p (qualifiers
))
5363 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5367 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5368 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5371 if (num_matched
> max_num_matched
)
5373 max_num_matched
= num_matched
;
5378 DEBUG_TRACE ("return with %d", idx
);
5382 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5383 corresponding operands in *INSTR. */
5386 assign_qualifier_sequence (aarch64_inst
*instr
,
5387 const aarch64_opnd_qualifier_t
*qualifiers
)
5390 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5391 gas_assert (num_opnds
);
5392 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5393 instr
->operands
[i
].qualifier
= *qualifiers
;
5396 /* Callback used by aarch64_print_operand to apply STYLE to the
5397 disassembler output created from FMT and ARGS. The STYLER object holds
5398 any required state. Must return a pointer to a string (created from FMT
5399 and ARGS) that will continue to be valid until the complete disassembled
5400 instruction has been printed.
5402 We don't currently add any styling to the output of the disassembler as
5403 used within assembler error messages, and so STYLE is ignored here. A
5404 new string is allocated on the obstack help within STYLER and returned
5407 static const char *aarch64_apply_style
5408 (struct aarch64_styler
*styler
,
5409 enum disassembler_style style ATTRIBUTE_UNUSED
,
5410 const char *fmt
, va_list args
)
5414 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5417 /* Calculate the required space. */
5419 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5421 gas_assert (res
>= 0);
5423 /* Allocate space on the obstack and format the result. */
5424 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5425 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5426 gas_assert (res
>= 0);
5431 /* Print operands for the diagnosis purpose. */
5434 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5435 const aarch64_opnd_info
*opnds
)
5438 struct aarch64_styler styler
;
5439 struct obstack content
;
5440 obstack_init (&content
);
5442 styler
.apply_style
= aarch64_apply_style
;
5443 styler
.state
= (void *) &content
;
5445 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5450 /* We regard the opcode operand info more, however we also look into
5451 the inst->operands to support the disassembling of the optional
5453 The two operand code should be the same in all cases, apart from
5454 when the operand can be optional. */
5455 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5456 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5459 /* Generate the operand string in STR. */
5460 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5461 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5465 strcat (buf
, i
== 0 ? " " : ", ");
5467 /* Append the operand string. */
5470 /* Append a comment. This works because only the last operand ever
5471 adds a comment. If that ever changes then we'll need to be
5475 strcat (buf
, "\t// ");
5480 obstack_free (&content
, NULL
);
5483 /* Send to stderr a string as information. */
5486 output_info (const char *format
, ...)
5492 file
= as_where (&line
);
5496 fprintf (stderr
, "%s:%u: ", file
, line
);
5498 fprintf (stderr
, "%s: ", file
);
5500 fprintf (stderr
, _("Info: "));
5501 va_start (args
, format
);
5502 vfprintf (stderr
, format
, args
);
5504 (void) putc ('\n', stderr
);
5507 /* Output one operand error record. */
5510 output_operand_error_record (const operand_error_record
*record
, char *str
)
5512 const aarch64_operand_error
*detail
= &record
->detail
;
5513 int idx
= detail
->index
;
5514 const aarch64_opcode
*opcode
= record
->opcode
;
5515 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5516 : AARCH64_OPND_NIL
);
5518 typedef void (*handler_t
)(const char *format
, ...);
5519 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5521 switch (detail
->kind
)
5523 case AARCH64_OPDE_NIL
:
5527 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5528 handler (_("this `%s' should have an immediately preceding `%s'"
5530 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5533 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5534 handler (_("the preceding `%s' should be followed by `%s` rather"
5535 " than `%s` -- `%s'"),
5536 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5539 case AARCH64_OPDE_SYNTAX_ERROR
:
5540 case AARCH64_OPDE_RECOVERABLE
:
5541 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5542 case AARCH64_OPDE_OTHER_ERROR
:
5543 /* Use the prepared error message if there is, otherwise use the
5544 operand description string to describe the error. */
5545 if (detail
->error
!= NULL
)
5548 handler (_("%s -- `%s'"), detail
->error
, str
);
5550 handler (_("%s at operand %d -- `%s'"),
5551 detail
->error
, idx
+ 1, str
);
5555 gas_assert (idx
>= 0);
5556 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5557 aarch64_get_operand_desc (opd_code
), str
);
5561 case AARCH64_OPDE_INVALID_VARIANT
:
5562 handler (_("operand mismatch -- `%s'"), str
);
5563 if (verbose_error_p
)
5565 /* We will try to correct the erroneous instruction and also provide
5566 more information e.g. all other valid variants.
5568 The string representation of the corrected instruction and other
5569 valid variants are generated by
5571 1) obtaining the intermediate representation of the erroneous
5573 2) manipulating the IR, e.g. replacing the operand qualifier;
5574 3) printing out the instruction by calling the printer functions
5575 shared with the disassembler.
5577 The limitation of this method is that the exact input assembly
5578 line cannot be accurately reproduced in some cases, for example an
5579 optional operand present in the actual assembly line will be
5580 omitted in the output; likewise for the optional syntax rules,
5581 e.g. the # before the immediate. Another limitation is that the
5582 assembly symbols and relocation operations in the assembly line
5583 currently cannot be printed out in the error report. Last but not
5584 least, when there is other error(s) co-exist with this error, the
5585 'corrected' instruction may be still incorrect, e.g. given
5586 'ldnp h0,h1,[x0,#6]!'
5587 this diagnosis will provide the version:
5588 'ldnp s0,s1,[x0,#6]!'
5589 which is still not right. */
5590 size_t len
= strlen (get_mnemonic_name (str
));
5594 aarch64_inst
*inst_base
= &inst
.base
;
5595 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5598 reset_aarch64_instruction (&inst
);
5599 inst_base
->opcode
= opcode
;
5601 /* Reset the error report so that there is no side effect on the
5602 following operand parsing. */
5603 init_operand_error_report ();
5606 result
= parse_operands (str
+ len
, opcode
)
5607 && programmer_friendly_fixup (&inst
);
5608 gas_assert (result
);
5609 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5610 NULL
, NULL
, insn_sequence
);
5611 gas_assert (!result
);
5613 /* Find the most matched qualifier sequence. */
5614 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5615 gas_assert (qlf_idx
> -1);
5617 /* Assign the qualifiers. */
5618 assign_qualifier_sequence (inst_base
,
5619 opcode
->qualifiers_list
[qlf_idx
]);
5621 /* Print the hint. */
5622 output_info (_(" did you mean this?"));
5623 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5624 print_operands (buf
, opcode
, inst_base
->operands
);
5625 output_info (_(" %s"), buf
);
5627 /* Print out other variant(s) if there is any. */
5629 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5630 output_info (_(" other valid variant(s):"));
5632 /* For each pattern. */
5633 qualifiers_list
= opcode
->qualifiers_list
;
5634 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5636 /* Most opcodes has much fewer patterns in the list.
5637 First NIL qualifier indicates the end in the list. */
5638 if (empty_qualifier_sequence_p (*qualifiers_list
))
5643 /* Mnemonics name. */
5644 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5646 /* Assign the qualifiers. */
5647 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5649 /* Print instruction. */
5650 print_operands (buf
, opcode
, inst_base
->operands
);
5652 output_info (_(" %s"), buf
);
5658 case AARCH64_OPDE_UNTIED_IMMS
:
5659 handler (_("operand %d must have the same immediate value "
5660 "as operand 1 -- `%s'"),
5661 detail
->index
+ 1, str
);
5664 case AARCH64_OPDE_UNTIED_OPERAND
:
5665 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5666 detail
->index
+ 1, str
);
5669 case AARCH64_OPDE_OUT_OF_RANGE
:
5670 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5671 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5672 detail
->error
? detail
->error
: _("immediate value"),
5673 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5675 handler (_("%s must be %d at operand %d -- `%s'"),
5676 detail
->error
? detail
->error
: _("immediate value"),
5677 detail
->data
[0].i
, idx
+ 1, str
);
5680 case AARCH64_OPDE_REG_LIST
:
5681 if (detail
->data
[0].i
== 1)
5682 handler (_("invalid number of registers in the list; "
5683 "only 1 register is expected at operand %d -- `%s'"),
5686 handler (_("invalid number of registers in the list; "
5687 "%d registers are expected at operand %d -- `%s'"),
5688 detail
->data
[0].i
, idx
+ 1, str
);
5691 case AARCH64_OPDE_UNALIGNED
:
5692 handler (_("immediate value must be a multiple of "
5693 "%d at operand %d -- `%s'"),
5694 detail
->data
[0].i
, idx
+ 1, str
);
5703 /* Process and output the error message about the operand mismatching.
5705 When this function is called, the operand error information had
5706 been collected for an assembly line and there will be multiple
5707 errors in the case of multiple instruction templates; output the
5708 error message that most closely describes the problem.
5710 The errors to be printed can be filtered on printing all errors
5711 or only non-fatal errors. This distinction has to be made because
5712 the error buffer may already be filled with fatal errors we don't want to
5713 print due to the different instruction templates. */
5716 output_operand_error_report (char *str
, bool non_fatal_only
)
5718 int largest_error_pos
;
5719 const char *msg
= NULL
;
5720 enum aarch64_operand_error_kind kind
;
5721 operand_error_record
*curr
;
5722 operand_error_record
*head
= operand_error_report
.head
;
5723 operand_error_record
*record
= NULL
;
5725 /* No error to report. */
5729 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5731 /* Only one error. */
5732 if (head
== operand_error_report
.tail
)
5734 /* If the only error is a non-fatal one and we don't want to print it,
5736 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5738 DEBUG_TRACE ("single opcode entry with error kind: %s",
5739 operand_mismatch_kind_names
[head
->detail
.kind
]);
5740 output_operand_error_record (head
, str
);
5745 /* Find the error kind of the highest severity. */
5746 DEBUG_TRACE ("multiple opcode entries with error kind");
5747 kind
= AARCH64_OPDE_NIL
;
5748 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5750 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5751 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5752 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5753 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5754 kind
= curr
->detail
.kind
;
5757 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5759 /* Pick up one of errors of KIND to report. */
5760 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5761 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5763 /* If we don't want to print non-fatal errors then don't consider them
5765 if (curr
->detail
.kind
!= kind
5766 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5768 /* If there are multiple errors, pick up the one with the highest
5769 mismatching operand index. In the case of multiple errors with
5770 the equally highest operand index, pick up the first one or the
5771 first one with non-NULL error message. */
5772 if (curr
->detail
.index
> largest_error_pos
5773 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5774 && curr
->detail
.error
!= NULL
))
5776 largest_error_pos
= curr
->detail
.index
;
5778 msg
= record
->detail
.error
;
5782 /* The way errors are collected in the back-end is a bit non-intuitive. But
5783 essentially, because each operand template is tried recursively you may
5784 always have errors collected from the previous tried OPND. These are
5785 usually skipped if there is one successful match. However now with the
5786 non-fatal errors we have to ignore those previously collected hard errors
5787 when we're only interested in printing the non-fatal ones. This condition
5788 prevents us from printing errors that are not appropriate, since we did
5789 match a condition, but it also has warnings that it wants to print. */
5790 if (non_fatal_only
&& !record
)
5793 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5794 DEBUG_TRACE ("Pick up error kind %s to report",
5795 operand_mismatch_kind_names
[record
->detail
.kind
]);
5798 output_operand_error_record (record
, str
);
5801 /* Write an AARCH64 instruction to buf - always little-endian. */
5803 put_aarch64_insn (char *buf
, uint32_t insn
)
5805 unsigned char *where
= (unsigned char *) buf
;
5807 where
[1] = insn
>> 8;
5808 where
[2] = insn
>> 16;
5809 where
[3] = insn
>> 24;
5813 get_aarch64_insn (char *buf
)
5815 unsigned char *where
= (unsigned char *) buf
;
5817 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5818 | ((uint32_t) where
[3] << 24)));
5823 output_inst (struct aarch64_inst
*new_inst
)
5827 to
= frag_more (INSN_SIZE
);
5829 frag_now
->tc_frag_data
.recorded
= 1;
5831 put_aarch64_insn (to
, inst
.base
.value
);
5833 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5835 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5836 INSN_SIZE
, &inst
.reloc
.exp
,
5839 DEBUG_TRACE ("Prepared relocation fix up");
5840 /* Don't check the addend value against the instruction size,
5841 that's the job of our code in md_apply_fix(). */
5842 fixp
->fx_no_overflow
= 1;
5843 if (new_inst
!= NULL
)
5844 fixp
->tc_fix_data
.inst
= new_inst
;
5845 if (aarch64_gas_internal_fixup_p ())
5847 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5848 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5849 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5853 dwarf2_emit_insn (INSN_SIZE
);
5856 /* Link together opcodes of the same name. */
5860 const aarch64_opcode
*opcode
;
5861 struct templates
*next
;
5864 typedef struct templates templates
;
5867 lookup_mnemonic (const char *start
, int len
)
5869 templates
*templ
= NULL
;
5871 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5875 /* Subroutine of md_assemble, responsible for looking up the primary
5876 opcode from the mnemonic the user wrote. BASE points to the beginning
5877 of the mnemonic, DOT points to the first '.' within the mnemonic
5878 (if any) and END points to the end of the mnemonic. */
5881 opcode_lookup (char *base
, char *dot
, char *end
)
5883 const aarch64_cond
*cond
;
5890 inst
.cond
= COND_ALWAYS
;
5892 /* Handle a possible condition. */
5895 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5898 inst
.cond
= cond
->value
;
5904 if (inst
.cond
== COND_ALWAYS
)
5906 /* Look for unaffixed mnemonic. */
5907 return lookup_mnemonic (base
, len
);
5911 /* append ".c" to mnemonic if conditional */
5912 memcpy (condname
, base
, len
);
5913 memcpy (condname
+ len
, ".c", 2);
5916 return lookup_mnemonic (base
, len
);
5922 /* Process an optional operand that is found omitted from the assembly line.
5923 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5924 instruction's opcode entry while IDX is the index of this omitted operand.
5928 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5929 int idx
, aarch64_opnd_info
*operand
)
5931 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5932 gas_assert (optional_operand_p (opcode
, idx
));
5933 gas_assert (!operand
->present
);
5937 case AARCH64_OPND_Rd
:
5938 case AARCH64_OPND_Rn
:
5939 case AARCH64_OPND_Rm
:
5940 case AARCH64_OPND_Rt
:
5941 case AARCH64_OPND_Rt2
:
5942 case AARCH64_OPND_Rt_LS64
:
5943 case AARCH64_OPND_Rt_SP
:
5944 case AARCH64_OPND_Rs
:
5945 case AARCH64_OPND_Ra
:
5946 case AARCH64_OPND_Rt_SYS
:
5947 case AARCH64_OPND_Rd_SP
:
5948 case AARCH64_OPND_Rn_SP
:
5949 case AARCH64_OPND_Rm_SP
:
5950 case AARCH64_OPND_Fd
:
5951 case AARCH64_OPND_Fn
:
5952 case AARCH64_OPND_Fm
:
5953 case AARCH64_OPND_Fa
:
5954 case AARCH64_OPND_Ft
:
5955 case AARCH64_OPND_Ft2
:
5956 case AARCH64_OPND_Sd
:
5957 case AARCH64_OPND_Sn
:
5958 case AARCH64_OPND_Sm
:
5959 case AARCH64_OPND_Va
:
5960 case AARCH64_OPND_Vd
:
5961 case AARCH64_OPND_Vn
:
5962 case AARCH64_OPND_Vm
:
5963 case AARCH64_OPND_VdD1
:
5964 case AARCH64_OPND_VnD1
:
5965 operand
->reg
.regno
= default_value
;
5968 case AARCH64_OPND_Ed
:
5969 case AARCH64_OPND_En
:
5970 case AARCH64_OPND_Em
:
5971 case AARCH64_OPND_Em16
:
5972 case AARCH64_OPND_SM3_IMM2
:
5973 operand
->reglane
.regno
= default_value
;
5976 case AARCH64_OPND_IDX
:
5977 case AARCH64_OPND_BIT_NUM
:
5978 case AARCH64_OPND_IMMR
:
5979 case AARCH64_OPND_IMMS
:
5980 case AARCH64_OPND_SHLL_IMM
:
5981 case AARCH64_OPND_IMM_VLSL
:
5982 case AARCH64_OPND_IMM_VLSR
:
5983 case AARCH64_OPND_CCMP_IMM
:
5984 case AARCH64_OPND_FBITS
:
5985 case AARCH64_OPND_UIMM4
:
5986 case AARCH64_OPND_UIMM3_OP1
:
5987 case AARCH64_OPND_UIMM3_OP2
:
5988 case AARCH64_OPND_IMM
:
5989 case AARCH64_OPND_IMM_2
:
5990 case AARCH64_OPND_WIDTH
:
5991 case AARCH64_OPND_UIMM7
:
5992 case AARCH64_OPND_NZCV
:
5993 case AARCH64_OPND_SVE_PATTERN
:
5994 case AARCH64_OPND_SVE_PRFOP
:
5995 operand
->imm
.value
= default_value
;
5998 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5999 operand
->imm
.value
= default_value
;
6000 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6001 operand
->shifter
.amount
= 1;
6004 case AARCH64_OPND_EXCEPTION
:
6005 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6008 case AARCH64_OPND_BARRIER_ISB
:
6009 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6012 case AARCH64_OPND_BTI_TARGET
:
6013 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6021 /* Process the relocation type for move wide instructions.
6022 Return TRUE on success; otherwise return FALSE. */
6025 process_movw_reloc_info (void)
6030 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6032 if (inst
.base
.opcode
->op
== OP_MOVK
)
6033 switch (inst
.reloc
.type
)
6035 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6036 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6037 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6038 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6039 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6040 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6041 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6042 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6043 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6044 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6045 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6047 (_("the specified relocation type is not allowed for MOVK"));
6053 switch (inst
.reloc
.type
)
6055 case BFD_RELOC_AARCH64_MOVW_G0
:
6056 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6057 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6058 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6059 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6060 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6061 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6062 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6063 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6064 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6065 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6066 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6067 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6070 case BFD_RELOC_AARCH64_MOVW_G1
:
6071 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6072 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6073 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6074 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6075 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6076 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6077 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6078 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6079 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6080 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6081 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6082 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6085 case BFD_RELOC_AARCH64_MOVW_G2
:
6086 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6087 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6088 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6089 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6090 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6091 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6094 set_fatal_syntax_error
6095 (_("the specified relocation type is not allowed for 32-bit "
6101 case BFD_RELOC_AARCH64_MOVW_G3
:
6102 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6105 set_fatal_syntax_error
6106 (_("the specified relocation type is not allowed for 32-bit "
6113 /* More cases should be added when more MOVW-related relocation types
6114 are supported in GAS. */
6115 gas_assert (aarch64_gas_internal_fixup_p ());
6116 /* The shift amount should have already been set by the parser. */
6119 inst
.base
.operands
[1].shifter
.amount
= shift
;
6123 /* A primitive log calculator. */
6125 static inline unsigned int
6126 get_logsz (unsigned int size
)
6128 const unsigned char ls
[16] =
6129 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6135 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6136 return ls
[size
- 1];
6139 /* Determine and return the real reloc type code for an instruction
6140 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6142 static inline bfd_reloc_code_real_type
6143 ldst_lo12_determine_real_reloc_type (void)
6145 unsigned logsz
, max_logsz
;
6146 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6147 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6149 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6151 BFD_RELOC_AARCH64_LDST8_LO12
,
6152 BFD_RELOC_AARCH64_LDST16_LO12
,
6153 BFD_RELOC_AARCH64_LDST32_LO12
,
6154 BFD_RELOC_AARCH64_LDST64_LO12
,
6155 BFD_RELOC_AARCH64_LDST128_LO12
6158 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6159 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6160 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6161 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6162 BFD_RELOC_AARCH64_NONE
6165 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6166 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6167 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6168 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6169 BFD_RELOC_AARCH64_NONE
6172 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6173 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6174 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6175 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6176 BFD_RELOC_AARCH64_NONE
6179 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6180 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6181 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6182 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6183 BFD_RELOC_AARCH64_NONE
6187 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6188 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6190 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6192 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6194 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6195 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6197 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6199 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6201 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6203 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6205 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6206 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6207 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6208 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6213 if (logsz
> max_logsz
)
6215 /* SEE PR 27904 for an example of this. */
6216 set_fatal_syntax_error
6217 (_("relocation qualifier does not match instruction size"));
6218 return BFD_RELOC_AARCH64_NONE
;
6221 /* In reloc.c, these pseudo relocation types should be defined in similar
6222 order as above reloc_ldst_lo12 array. Because the array index calculation
6223 below relies on this. */
6224 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6227 /* Check whether a register list REGINFO is valid. The registers must be
6228 numbered in increasing order (modulo 32), in increments of one or two.
6230 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6233 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6236 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6238 uint32_t i
, nb_regs
, prev_regno
, incr
;
6240 nb_regs
= 1 + (reginfo
& 0x3);
6242 prev_regno
= reginfo
& 0x1f;
6243 incr
= accept_alternate
? 2 : 1;
6245 for (i
= 1; i
< nb_regs
; ++i
)
6247 uint32_t curr_regno
;
6249 curr_regno
= reginfo
& 0x1f;
6250 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6252 prev_regno
= curr_regno
;
6258 /* Generic instruction operand parser. This does no encoding and no
6259 semantic validation; it merely squirrels values away in the inst
6260 structure. Returns TRUE or FALSE depending on whether the
6261 specified grammar matched. */
6264 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6267 char *backtrack_pos
= 0;
6268 const enum aarch64_opnd
*operands
= opcode
->operands
;
6269 aarch64_reg_type imm_reg_type
;
6272 skip_whitespace (str
);
6274 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6276 | AARCH64_FEATURE_SVE2
))
6277 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6279 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6281 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6284 const reg_entry
*reg
;
6285 int comma_skipped_p
= 0;
6286 struct vector_type_el vectype
;
6287 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6288 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6289 aarch64_reg_type reg_type
;
6291 DEBUG_TRACE ("parse operand %d", i
);
6293 /* Assign the operand code. */
6294 info
->type
= operands
[i
];
6296 if (optional_operand_p (opcode
, i
))
6298 /* Remember where we are in case we need to backtrack. */
6299 gas_assert (!backtrack_pos
);
6300 backtrack_pos
= str
;
6303 /* Expect comma between operands; the backtrack mechanism will take
6304 care of cases of omitted optional operand. */
6305 if (i
> 0 && ! skip_past_char (&str
, ','))
6307 set_syntax_error (_("comma expected between operands"));
6311 comma_skipped_p
= 1;
6313 switch (operands
[i
])
6315 case AARCH64_OPND_Rd
:
6316 case AARCH64_OPND_Rn
:
6317 case AARCH64_OPND_Rm
:
6318 case AARCH64_OPND_Rt
:
6319 case AARCH64_OPND_Rt2
:
6320 case AARCH64_OPND_Rs
:
6321 case AARCH64_OPND_Ra
:
6322 case AARCH64_OPND_Rt_LS64
:
6323 case AARCH64_OPND_Rt_SYS
:
6324 case AARCH64_OPND_PAIRREG
:
6325 case AARCH64_OPND_SVE_Rm
:
6326 po_int_reg_or_fail (REG_TYPE_R_Z
);
6328 /* In LS64 load/store instructions Rt register number must be even
6330 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6332 /* We've already checked if this is valid register.
6333 This will check if register number (Rt) is not undefined for LS64
6335 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6336 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6338 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6344 case AARCH64_OPND_Rd_SP
:
6345 case AARCH64_OPND_Rn_SP
:
6346 case AARCH64_OPND_Rt_SP
:
6347 case AARCH64_OPND_SVE_Rn_SP
:
6348 case AARCH64_OPND_Rm_SP
:
6349 po_int_reg_or_fail (REG_TYPE_R_SP
);
6352 case AARCH64_OPND_Rm_EXT
:
6353 case AARCH64_OPND_Rm_SFT
:
6354 po_misc_or_fail (parse_shifter_operand
6355 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6357 : SHIFTED_LOGIC_IMM
)));
6358 if (!info
->shifter
.operator_present
)
6360 /* Default to LSL if not present. Libopcodes prefers shifter
6361 kind to be explicit. */
6362 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6363 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6364 /* For Rm_EXT, libopcodes will carry out further check on whether
6365 or not stack pointer is used in the instruction (Recall that
6366 "the extend operator is not optional unless at least one of
6367 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6371 case AARCH64_OPND_Fd
:
6372 case AARCH64_OPND_Fn
:
6373 case AARCH64_OPND_Fm
:
6374 case AARCH64_OPND_Fa
:
6375 case AARCH64_OPND_Ft
:
6376 case AARCH64_OPND_Ft2
:
6377 case AARCH64_OPND_Sd
:
6378 case AARCH64_OPND_Sn
:
6379 case AARCH64_OPND_Sm
:
6380 case AARCH64_OPND_SVE_VZn
:
6381 case AARCH64_OPND_SVE_Vd
:
6382 case AARCH64_OPND_SVE_Vm
:
6383 case AARCH64_OPND_SVE_Vn
:
6384 reg
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, NULL
);
6387 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6390 gas_assert (reg
->type
>= REG_TYPE_FP_B
6391 && reg
->type
<= REG_TYPE_FP_Q
);
6393 info
->reg
.regno
= reg
->number
;
6394 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
6397 case AARCH64_OPND_SVE_Pd
:
6398 case AARCH64_OPND_SVE_Pg3
:
6399 case AARCH64_OPND_SVE_Pg4_5
:
6400 case AARCH64_OPND_SVE_Pg4_10
:
6401 case AARCH64_OPND_SVE_Pg4_16
:
6402 case AARCH64_OPND_SVE_Pm
:
6403 case AARCH64_OPND_SVE_Pn
:
6404 case AARCH64_OPND_SVE_Pt
:
6405 case AARCH64_OPND_SME_Pm
:
6406 reg_type
= REG_TYPE_PN
;
6409 case AARCH64_OPND_SVE_Za_5
:
6410 case AARCH64_OPND_SVE_Za_16
:
6411 case AARCH64_OPND_SVE_Zd
:
6412 case AARCH64_OPND_SVE_Zm_5
:
6413 case AARCH64_OPND_SVE_Zm_16
:
6414 case AARCH64_OPND_SVE_Zn
:
6415 case AARCH64_OPND_SVE_Zt
:
6416 reg_type
= REG_TYPE_ZN
;
6419 case AARCH64_OPND_Va
:
6420 case AARCH64_OPND_Vd
:
6421 case AARCH64_OPND_Vn
:
6422 case AARCH64_OPND_Vm
:
6423 reg_type
= REG_TYPE_VN
;
6425 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6428 first_error (_(get_reg_expected_msg (reg_type
)));
6431 if (vectype
.defined
& NTA_HASINDEX
)
6434 info
->reg
.regno
= reg
->number
;
6435 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6436 && vectype
.type
== NT_invtype
)
6437 /* Unqualified Pn and Zn registers are allowed in certain
6438 contexts. Rely on F_STRICT qualifier checking to catch
6440 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6443 info
->qualifier
= vectype_to_qualifier (&vectype
);
6444 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6449 case AARCH64_OPND_VdD1
:
6450 case AARCH64_OPND_VnD1
:
6451 reg
= aarch64_reg_parse (&str
, REG_TYPE_VN
, &vectype
);
6454 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6457 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6459 set_fatal_syntax_error
6460 (_("the top half of a 128-bit FP/SIMD register is expected"));
6463 info
->reg
.regno
= reg
->number
;
6464 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6465 here; it is correct for the purpose of encoding/decoding since
6466 only the register number is explicitly encoded in the related
6467 instructions, although this appears a bit hacky. */
6468 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6471 case AARCH64_OPND_SVE_Zm3_INDEX
:
6472 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6473 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6474 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6475 case AARCH64_OPND_SVE_Zm4_INDEX
:
6476 case AARCH64_OPND_SVE_Zn_INDEX
:
6477 reg_type
= REG_TYPE_ZN
;
6478 goto vector_reg_index
;
6480 case AARCH64_OPND_Ed
:
6481 case AARCH64_OPND_En
:
6482 case AARCH64_OPND_Em
:
6483 case AARCH64_OPND_Em16
:
6484 case AARCH64_OPND_SM3_IMM2
:
6485 reg_type
= REG_TYPE_VN
;
6487 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6490 first_error (_(get_reg_expected_msg (reg_type
)));
6493 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6496 info
->reglane
.regno
= reg
->number
;
6497 info
->reglane
.index
= vectype
.index
;
6498 info
->qualifier
= vectype_to_qualifier (&vectype
);
6499 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6503 case AARCH64_OPND_SVE_ZnxN
:
6504 case AARCH64_OPND_SVE_ZtxN
:
6505 reg_type
= REG_TYPE_ZN
;
6506 goto vector_reg_list
;
6508 case AARCH64_OPND_LVn
:
6509 case AARCH64_OPND_LVt
:
6510 case AARCH64_OPND_LVt_AL
:
6511 case AARCH64_OPND_LEt
:
6512 reg_type
= REG_TYPE_VN
;
6514 if (reg_type
== REG_TYPE_ZN
6515 && get_opcode_dependent_value (opcode
) == 1
6518 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6521 first_error (_(get_reg_expected_msg (reg_type
)));
6524 info
->reglist
.first_regno
= reg
->number
;
6525 info
->reglist
.num_regs
= 1;
6529 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6530 if (val
== PARSE_FAIL
)
6533 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6535 set_fatal_syntax_error (_("invalid register list"));
6539 if (vectype
.width
!= 0 && *str
!= ',')
6541 set_fatal_syntax_error
6542 (_("expected element type rather than vector type"));
6546 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6547 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6549 if (operands
[i
] == AARCH64_OPND_LEt
)
6551 if (!(vectype
.defined
& NTA_HASINDEX
))
6553 info
->reglist
.has_index
= 1;
6554 info
->reglist
.index
= vectype
.index
;
6558 if (vectype
.defined
& NTA_HASINDEX
)
6560 if (!(vectype
.defined
& NTA_HASTYPE
))
6562 if (reg_type
== REG_TYPE_ZN
)
6563 set_fatal_syntax_error (_("missing type suffix"));
6567 info
->qualifier
= vectype_to_qualifier (&vectype
);
6568 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6572 case AARCH64_OPND_CRn
:
6573 case AARCH64_OPND_CRm
:
6575 char prefix
= *(str
++);
6576 if (prefix
!= 'c' && prefix
!= 'C')
6579 po_imm_nc_or_fail ();
6582 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6585 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6586 info
->imm
.value
= val
;
6590 case AARCH64_OPND_SHLL_IMM
:
6591 case AARCH64_OPND_IMM_VLSR
:
6592 po_imm_or_fail (1, 64);
6593 info
->imm
.value
= val
;
6596 case AARCH64_OPND_CCMP_IMM
:
6597 case AARCH64_OPND_SIMM5
:
6598 case AARCH64_OPND_FBITS
:
6599 case AARCH64_OPND_TME_UIMM16
:
6600 case AARCH64_OPND_UIMM4
:
6601 case AARCH64_OPND_UIMM4_ADDG
:
6602 case AARCH64_OPND_UIMM10
:
6603 case AARCH64_OPND_UIMM3_OP1
:
6604 case AARCH64_OPND_UIMM3_OP2
:
6605 case AARCH64_OPND_IMM_VLSL
:
6606 case AARCH64_OPND_IMM
:
6607 case AARCH64_OPND_IMM_2
:
6608 case AARCH64_OPND_WIDTH
:
6609 case AARCH64_OPND_SVE_INV_LIMM
:
6610 case AARCH64_OPND_SVE_LIMM
:
6611 case AARCH64_OPND_SVE_LIMM_MOV
:
6612 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6613 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6614 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6615 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6616 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6617 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6618 case AARCH64_OPND_SVE_SIMM5
:
6619 case AARCH64_OPND_SVE_SIMM5B
:
6620 case AARCH64_OPND_SVE_SIMM6
:
6621 case AARCH64_OPND_SVE_SIMM8
:
6622 case AARCH64_OPND_SVE_UIMM3
:
6623 case AARCH64_OPND_SVE_UIMM7
:
6624 case AARCH64_OPND_SVE_UIMM8
:
6625 case AARCH64_OPND_SVE_UIMM8_53
:
6626 case AARCH64_OPND_IMM_ROT1
:
6627 case AARCH64_OPND_IMM_ROT2
:
6628 case AARCH64_OPND_IMM_ROT3
:
6629 case AARCH64_OPND_SVE_IMM_ROT1
:
6630 case AARCH64_OPND_SVE_IMM_ROT2
:
6631 case AARCH64_OPND_SVE_IMM_ROT3
:
6632 case AARCH64_OPND_CSSC_SIMM8
:
6633 case AARCH64_OPND_CSSC_UIMM8
:
6634 po_imm_nc_or_fail ();
6635 info
->imm
.value
= val
;
6638 case AARCH64_OPND_SVE_AIMM
:
6639 case AARCH64_OPND_SVE_ASIMM
:
6640 po_imm_nc_or_fail ();
6641 info
->imm
.value
= val
;
6642 skip_whitespace (str
);
6643 if (skip_past_comma (&str
))
6644 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6646 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6649 case AARCH64_OPND_SVE_PATTERN
:
6650 po_enum_or_fail (aarch64_sve_pattern_array
);
6651 info
->imm
.value
= val
;
6654 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6655 po_enum_or_fail (aarch64_sve_pattern_array
);
6656 info
->imm
.value
= val
;
6657 if (skip_past_comma (&str
)
6658 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6660 if (!info
->shifter
.operator_present
)
6662 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6663 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6664 info
->shifter
.amount
= 1;
6668 case AARCH64_OPND_SVE_PRFOP
:
6669 po_enum_or_fail (aarch64_sve_prfop_array
);
6670 info
->imm
.value
= val
;
6673 case AARCH64_OPND_UIMM7
:
6674 po_imm_or_fail (0, 127);
6675 info
->imm
.value
= val
;
6678 case AARCH64_OPND_IDX
:
6679 case AARCH64_OPND_MASK
:
6680 case AARCH64_OPND_BIT_NUM
:
6681 case AARCH64_OPND_IMMR
:
6682 case AARCH64_OPND_IMMS
:
6683 po_imm_or_fail (0, 63);
6684 info
->imm
.value
= val
;
6687 case AARCH64_OPND_IMM0
:
6688 po_imm_nc_or_fail ();
6691 set_fatal_syntax_error (_("immediate zero expected"));
6694 info
->imm
.value
= 0;
6697 case AARCH64_OPND_FPIMM0
:
6700 bool res1
= false, res2
= false;
6701 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6702 it is probably not worth the effort to support it. */
6703 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6706 || !(res2
= parse_constant_immediate (&str
, &val
,
6709 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6711 info
->imm
.value
= 0;
6712 info
->imm
.is_fp
= 1;
6715 set_fatal_syntax_error (_("immediate zero expected"));
6719 case AARCH64_OPND_IMM_MOV
:
6722 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6723 reg_name_p (str
, REG_TYPE_VN
))
6726 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6727 GE_OPT_PREFIX
, REJECT_ABSENT
));
6728 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6729 later. fix_mov_imm_insn will try to determine a machine
6730 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6731 message if the immediate cannot be moved by a single
6733 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6734 inst
.base
.operands
[i
].skip
= 1;
6738 case AARCH64_OPND_SIMD_IMM
:
6739 case AARCH64_OPND_SIMD_IMM_SFT
:
6740 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6742 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6744 /* need_libopcodes_p */ 1,
6747 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6748 shift, we don't check it here; we leave the checking to
6749 the libopcodes (operand_general_constraint_met_p). By
6750 doing this, we achieve better diagnostics. */
6751 if (skip_past_comma (&str
)
6752 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6754 if (!info
->shifter
.operator_present
6755 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6757 /* Default to LSL if not present. Libopcodes prefers shifter
6758 kind to be explicit. */
6759 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6760 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6764 case AARCH64_OPND_FPIMM
:
6765 case AARCH64_OPND_SIMD_FPIMM
:
6766 case AARCH64_OPND_SVE_FPIMM8
:
6771 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6772 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6773 || !aarch64_imm_float_p (qfloat
))
6776 set_fatal_syntax_error (_("invalid floating-point"
6780 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6781 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6785 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6786 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6787 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6792 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6793 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6796 set_fatal_syntax_error (_("invalid floating-point"
6800 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6801 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6805 case AARCH64_OPND_LIMM
:
6806 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6807 SHIFTED_LOGIC_IMM
));
6808 if (info
->shifter
.operator_present
)
6810 set_fatal_syntax_error
6811 (_("shift not allowed for bitmask immediate"));
6814 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6816 /* need_libopcodes_p */ 1,
6820 case AARCH64_OPND_AIMM
:
6821 if (opcode
->op
== OP_ADD
)
6822 /* ADD may have relocation types. */
6823 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6824 SHIFTED_ARITH_IMM
));
6826 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6827 SHIFTED_ARITH_IMM
));
6828 switch (inst
.reloc
.type
)
6830 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6831 info
->shifter
.amount
= 12;
6833 case BFD_RELOC_UNUSED
:
6834 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6835 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6836 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6837 inst
.reloc
.pc_rel
= 0;
6842 info
->imm
.value
= 0;
6843 if (!info
->shifter
.operator_present
)
6845 /* Default to LSL if not present. Libopcodes prefers shifter
6846 kind to be explicit. */
6847 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6848 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6852 case AARCH64_OPND_HALF
:
6854 /* #<imm16> or relocation. */
6855 int internal_fixup_p
;
6856 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6857 if (internal_fixup_p
)
6858 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6859 skip_whitespace (str
);
6860 if (skip_past_comma (&str
))
6862 /* {, LSL #<shift>} */
6863 if (! aarch64_gas_internal_fixup_p ())
6865 set_fatal_syntax_error (_("can't mix relocation modifier "
6866 "with explicit shift"));
6869 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6872 inst
.base
.operands
[i
].shifter
.amount
= 0;
6873 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6874 inst
.base
.operands
[i
].imm
.value
= 0;
6875 if (! process_movw_reloc_info ())
6880 case AARCH64_OPND_EXCEPTION
:
6881 case AARCH64_OPND_UNDEFINED
:
6882 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6884 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6886 /* need_libopcodes_p */ 0,
6890 case AARCH64_OPND_NZCV
:
6892 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6896 info
->imm
.value
= nzcv
->value
;
6899 po_imm_or_fail (0, 15);
6900 info
->imm
.value
= val
;
6904 case AARCH64_OPND_COND
:
6905 case AARCH64_OPND_COND1
:
6910 while (ISALPHA (*str
));
6911 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6912 if (info
->cond
== NULL
)
6914 set_syntax_error (_("invalid condition"));
6917 else if (operands
[i
] == AARCH64_OPND_COND1
6918 && (info
->cond
->value
& 0xe) == 0xe)
6920 /* Do not allow AL or NV. */
6921 set_default_error ();
6927 case AARCH64_OPND_ADDR_ADRP
:
6928 po_misc_or_fail (parse_adrp (&str
));
6929 /* Clear the value as operand needs to be relocated. */
6930 info
->imm
.value
= 0;
6933 case AARCH64_OPND_ADDR_PCREL14
:
6934 case AARCH64_OPND_ADDR_PCREL19
:
6935 case AARCH64_OPND_ADDR_PCREL21
:
6936 case AARCH64_OPND_ADDR_PCREL26
:
6937 po_misc_or_fail (parse_address (&str
, info
));
6938 if (!info
->addr
.pcrel
)
6940 set_syntax_error (_("invalid pc-relative address"));
6943 if (inst
.gen_lit_pool
6944 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6946 /* Only permit "=value" in the literal load instructions.
6947 The literal will be generated by programmer_friendly_fixup. */
6948 set_syntax_error (_("invalid use of \"=immediate\""));
6951 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6953 set_syntax_error (_("unrecognized relocation suffix"));
6956 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6958 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6959 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6963 info
->imm
.value
= 0;
6964 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6965 switch (opcode
->iclass
)
6969 /* e.g. CBZ or B.COND */
6970 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6971 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6975 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6976 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6980 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6982 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6983 : BFD_RELOC_AARCH64_JUMP26
;
6986 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6987 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6990 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6991 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6997 inst
.reloc
.pc_rel
= 1;
7001 case AARCH64_OPND_ADDR_SIMPLE
:
7002 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7004 /* [<Xn|SP>{, #<simm>}] */
7006 /* First use the normal address-parsing routines, to get
7007 the usual syntax errors. */
7008 po_misc_or_fail (parse_address (&str
, info
));
7009 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7010 || !info
->addr
.preind
|| info
->addr
.postind
7011 || info
->addr
.writeback
)
7013 set_syntax_error (_("invalid addressing mode"));
7017 /* Then retry, matching the specific syntax of these addresses. */
7019 po_char_or_fail ('[');
7020 po_reg_or_fail (REG_TYPE_R64_SP
);
7021 /* Accept optional ", #0". */
7022 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7023 && skip_past_char (&str
, ','))
7025 skip_past_char (&str
, '#');
7026 if (! skip_past_char (&str
, '0'))
7028 set_fatal_syntax_error
7029 (_("the optional immediate offset can only be 0"));
7033 po_char_or_fail (']');
7037 case AARCH64_OPND_ADDR_REGOFF
:
7038 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7039 po_misc_or_fail (parse_address (&str
, info
));
7041 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7042 || !info
->addr
.preind
|| info
->addr
.postind
7043 || info
->addr
.writeback
)
7045 set_syntax_error (_("invalid addressing mode"));
7048 if (!info
->shifter
.operator_present
)
7050 /* Default to LSL if not present. Libopcodes prefers shifter
7051 kind to be explicit. */
7052 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7053 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7055 /* Qualifier to be deduced by libopcodes. */
7058 case AARCH64_OPND_ADDR_SIMM7
:
7059 po_misc_or_fail (parse_address (&str
, info
));
7060 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7061 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7063 set_syntax_error (_("invalid addressing mode"));
7066 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7068 set_syntax_error (_("relocation not allowed"));
7071 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7073 /* need_libopcodes_p */ 1,
7077 case AARCH64_OPND_ADDR_SIMM9
:
7078 case AARCH64_OPND_ADDR_SIMM9_2
:
7079 case AARCH64_OPND_ADDR_SIMM11
:
7080 case AARCH64_OPND_ADDR_SIMM13
:
7081 po_misc_or_fail (parse_address (&str
, info
));
7082 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7083 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7084 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7085 && info
->addr
.writeback
))
7087 set_syntax_error (_("invalid addressing mode"));
7090 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7092 set_syntax_error (_("relocation not allowed"));
7095 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7097 /* need_libopcodes_p */ 1,
7101 case AARCH64_OPND_ADDR_SIMM10
:
7102 case AARCH64_OPND_ADDR_OFFSET
:
7103 po_misc_or_fail (parse_address (&str
, info
));
7104 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7105 || !info
->addr
.preind
|| info
->addr
.postind
)
7107 set_syntax_error (_("invalid addressing mode"));
7110 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7112 set_syntax_error (_("relocation not allowed"));
7115 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7117 /* need_libopcodes_p */ 1,
7121 case AARCH64_OPND_ADDR_UIMM12
:
7122 po_misc_or_fail (parse_address (&str
, info
));
7123 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7124 || !info
->addr
.preind
|| info
->addr
.writeback
)
7126 set_syntax_error (_("invalid addressing mode"));
7129 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7130 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7131 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7133 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7135 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7137 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7139 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7140 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7141 /* Leave qualifier to be determined by libopcodes. */
7144 case AARCH64_OPND_SIMD_ADDR_POST
:
7145 /* [<Xn|SP>], <Xm|#<amount>> */
7146 po_misc_or_fail (parse_address (&str
, info
));
7147 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7149 set_syntax_error (_("invalid addressing mode"));
7152 if (!info
->addr
.offset
.is_reg
)
7154 if (inst
.reloc
.exp
.X_op
== O_constant
)
7155 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7158 set_fatal_syntax_error
7159 (_("writeback value must be an immediate constant"));
7166 case AARCH64_OPND_SME_SM_ZA
:
7168 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7170 set_syntax_error (_("unknown or missing PSTATE field name"));
7173 info
->reg
.regno
= val
;
7176 case AARCH64_OPND_SME_PnT_Wm_imm
:
7177 /* <Pn>.<T>[<Wm>, #<imm>] */
7181 val
= parse_sme_pred_reg_with_index (&str
,
7185 if (val
== PARSE_FAIL
)
7188 info
->za_tile_vector
.regno
= val
;
7189 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7190 info
->za_tile_vector
.index
.imm
= imm
;
7191 info
->qualifier
= qualifier
;
7195 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7196 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7197 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7198 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7199 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7200 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7201 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7202 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7203 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7204 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7205 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7206 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7207 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7208 /* [X<n>{, #imm, MUL VL}]
7210 but recognizing SVE registers. */
7211 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7212 &offset_qualifier
));
7213 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7215 set_syntax_error (_("invalid addressing mode"));
7219 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7220 || !info
->addr
.preind
|| info
->addr
.writeback
)
7222 set_syntax_error (_("invalid addressing mode"));
7225 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7226 || inst
.reloc
.exp
.X_op
!= O_constant
)
7228 /* Make sure this has priority over
7229 "invalid addressing mode". */
7230 set_fatal_syntax_error (_("constant offset required"));
7233 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7236 case AARCH64_OPND_SVE_ADDR_R
:
7237 /* [<Xn|SP>{, <R><m>}]
7238 but recognizing SVE registers. */
7239 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7240 &offset_qualifier
));
7241 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7243 offset_qualifier
= AARCH64_OPND_QLF_X
;
7244 info
->addr
.offset
.is_reg
= 1;
7245 info
->addr
.offset
.regno
= 31;
7247 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7248 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7250 set_syntax_error (_("invalid addressing mode"));
7255 case AARCH64_OPND_SVE_ADDR_RR
:
7256 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7257 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7258 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7259 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7260 case AARCH64_OPND_SVE_ADDR_RX
:
7261 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7262 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7263 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7264 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7265 but recognizing SVE registers. */
7266 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7267 &offset_qualifier
));
7268 if (base_qualifier
!= AARCH64_OPND_QLF_X
7269 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7271 set_syntax_error (_("invalid addressing mode"));
7276 case AARCH64_OPND_SVE_ADDR_RZ
:
7277 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7278 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7279 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7280 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7281 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7282 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7283 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7284 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7285 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7286 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7287 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7288 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7289 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7290 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7291 &offset_qualifier
));
7292 if (base_qualifier
!= AARCH64_OPND_QLF_X
7293 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7294 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7296 set_syntax_error (_("invalid addressing mode"));
7299 info
->qualifier
= offset_qualifier
;
7302 case AARCH64_OPND_SVE_ADDR_ZX
:
7303 /* [Zn.<T>{, <Xm>}]. */
7304 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7305 &offset_qualifier
));
7307 base_qualifier either S_S or S_D
7308 offset_qualifier must be X
7310 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7311 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7312 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7314 set_syntax_error (_("invalid addressing mode"));
7317 info
->qualifier
= base_qualifier
;
7318 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7319 || !info
->addr
.preind
|| info
->addr
.writeback
7320 || info
->shifter
.operator_present
!= 0)
7322 set_syntax_error (_("invalid addressing mode"));
7325 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7329 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7330 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7331 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7332 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7333 /* [Z<n>.<T>{, #imm}] */
7334 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7335 &offset_qualifier
));
7336 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7337 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7339 set_syntax_error (_("invalid addressing mode"));
7342 info
->qualifier
= base_qualifier
;
7345 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7346 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7347 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7348 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7349 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7353 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7355 here since we get better error messages by leaving it to
7356 the qualifier checking routines. */
7357 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7358 &offset_qualifier
));
7359 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7360 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7361 || offset_qualifier
!= base_qualifier
)
7363 set_syntax_error (_("invalid addressing mode"));
7366 info
->qualifier
= base_qualifier
;
7369 case AARCH64_OPND_SYSREG
:
7371 uint32_t sysreg_flags
;
7372 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7373 &sysreg_flags
)) == PARSE_FAIL
)
7375 set_syntax_error (_("unknown or missing system register name"));
7378 inst
.base
.operands
[i
].sysreg
.value
= val
;
7379 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7383 case AARCH64_OPND_PSTATEFIELD
:
7385 uint32_t sysreg_flags
;
7386 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7387 &sysreg_flags
)) == PARSE_FAIL
)
7389 set_syntax_error (_("unknown or missing PSTATE field name"));
7392 inst
.base
.operands
[i
].pstatefield
= val
;
7393 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7397 case AARCH64_OPND_SYSREG_IC
:
7398 inst
.base
.operands
[i
].sysins_op
=
7399 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7402 case AARCH64_OPND_SYSREG_DC
:
7403 inst
.base
.operands
[i
].sysins_op
=
7404 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7407 case AARCH64_OPND_SYSREG_AT
:
7408 inst
.base
.operands
[i
].sysins_op
=
7409 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7412 case AARCH64_OPND_SYSREG_SR
:
7413 inst
.base
.operands
[i
].sysins_op
=
7414 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7417 case AARCH64_OPND_SYSREG_TLBI
:
7418 inst
.base
.operands
[i
].sysins_op
=
7419 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7421 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7423 set_fatal_syntax_error ( _("unknown or missing operation name"));
7428 case AARCH64_OPND_BARRIER
:
7429 case AARCH64_OPND_BARRIER_ISB
:
7430 val
= parse_barrier (&str
);
7431 if (val
!= PARSE_FAIL
7432 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7434 /* ISB only accepts options name 'sy'. */
7436 (_("the specified option is not accepted in ISB"));
7437 /* Turn off backtrack as this optional operand is present. */
7441 if (val
!= PARSE_FAIL
7442 && operands
[i
] == AARCH64_OPND_BARRIER
)
7444 /* Regular barriers accept options CRm (C0-C15).
7445 DSB nXS barrier variant accepts values > 15. */
7446 if (val
< 0 || val
> 15)
7448 set_syntax_error (_("the specified option is not accepted in DSB"));
7452 /* This is an extension to accept a 0..15 immediate. */
7453 if (val
== PARSE_FAIL
)
7454 po_imm_or_fail (0, 15);
7455 info
->barrier
= aarch64_barrier_options
+ val
;
7458 case AARCH64_OPND_BARRIER_DSB_NXS
:
7459 val
= parse_barrier (&str
);
7460 if (val
!= PARSE_FAIL
)
7462 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7463 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7465 set_syntax_error (_("the specified option is not accepted in DSB"));
7466 /* Turn off backtrack as this optional operand is present. */
7473 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7474 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7475 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7477 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7479 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7483 /* Option index is encoded as 2-bit value in val<3:2>. */
7484 val
= (val
>> 2) - 4;
7485 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7488 case AARCH64_OPND_PRFOP
:
7489 val
= parse_pldop (&str
);
7490 /* This is an extension to accept a 0..31 immediate. */
7491 if (val
== PARSE_FAIL
)
7492 po_imm_or_fail (0, 31);
7493 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7496 case AARCH64_OPND_BARRIER_PSB
:
7497 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7498 if (val
== PARSE_FAIL
)
7502 case AARCH64_OPND_BTI_TARGET
:
7503 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7504 if (val
== PARSE_FAIL
)
7508 case AARCH64_OPND_SME_ZAda_2b
:
7509 case AARCH64_OPND_SME_ZAda_3b
:
7510 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
);
7513 info
->reg
.regno
= reg
->number
;
7514 info
->qualifier
= qualifier
;
7517 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7518 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7519 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7521 enum sme_hv_slice slice_indicator
;
7522 int vector_select_register
;
7525 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7526 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7528 &vector_select_register
,
7532 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7533 &vector_select_register
,
7536 if (val
== PARSE_FAIL
)
7538 info
->za_tile_vector
.regno
= val
;
7539 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7540 info
->za_tile_vector
.index
.imm
= imm
;
7541 info
->za_tile_vector
.v
= slice_indicator
;
7542 info
->qualifier
= qualifier
;
7546 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7547 val
= parse_sme_list_of_64bit_tiles (&str
);
7548 if (val
== PARSE_FAIL
)
7550 info
->imm
.value
= val
;
7553 case AARCH64_OPND_SME_ZA_array
:
7556 val
= parse_sme_za_array (&str
, &imm
);
7557 if (val
== PARSE_FAIL
)
7559 info
->za_tile_vector
.index
.regno
= val
;
7560 info
->za_tile_vector
.index
.imm
= imm
;
7564 case AARCH64_OPND_MOPS_ADDR_Rd
:
7565 case AARCH64_OPND_MOPS_ADDR_Rs
:
7566 po_char_or_fail ('[');
7567 if (!parse_x0_to_x30 (&str
, info
))
7569 po_char_or_fail (']');
7570 po_char_or_fail ('!');
7573 case AARCH64_OPND_MOPS_WB_Rn
:
7574 if (!parse_x0_to_x30 (&str
, info
))
7576 po_char_or_fail ('!');
7580 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7583 /* If we get here, this operand was successfully parsed. */
7584 inst
.base
.operands
[i
].present
= 1;
7588 /* The parse routine should already have set the error, but in case
7589 not, set a default one here. */
7591 set_default_error ();
7593 if (! backtrack_pos
)
7594 goto parse_operands_return
;
7597 /* We reach here because this operand is marked as optional, and
7598 either no operand was supplied or the operand was supplied but it
7599 was syntactically incorrect. In the latter case we report an
7600 error. In the former case we perform a few more checks before
7601 dropping through to the code to insert the default operand. */
7603 char *tmp
= backtrack_pos
;
7604 char endchar
= END_OF_INSN
;
7606 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7608 skip_past_char (&tmp
, ',');
7610 if (*tmp
!= endchar
)
7611 /* The user has supplied an operand in the wrong format. */
7612 goto parse_operands_return
;
7614 /* Make sure there is not a comma before the optional operand.
7615 For example the fifth operand of 'sys' is optional:
7617 sys #0,c0,c0,#0, <--- wrong
7618 sys #0,c0,c0,#0 <--- correct. */
7619 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7621 set_fatal_syntax_error
7622 (_("unexpected comma before the omitted optional operand"));
7623 goto parse_operands_return
;
7627 /* Reaching here means we are dealing with an optional operand that is
7628 omitted from the assembly line. */
7629 gas_assert (optional_operand_p (opcode
, i
));
7631 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7633 /* Try again, skipping the optional operand at backtrack_pos. */
7634 str
= backtrack_pos
;
7637 /* Clear any error record after the omitted optional operand has been
7638 successfully handled. */
7642 /* Check if we have parsed all the operands. */
7643 if (*str
!= '\0' && ! error_p ())
7645 /* Set I to the index of the last present operand; this is
7646 for the purpose of diagnostics. */
7647 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7649 set_fatal_syntax_error
7650 (_("unexpected characters following instruction"));
7653 parse_operands_return
:
7657 inst
.parsing_error
.index
= i
;
7658 DEBUG_TRACE ("parsing FAIL: %s - %s",
7659 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7660 inst
.parsing_error
.error
);
7661 /* Record the operand error properly; this is useful when there
7662 are multiple instruction templates for a mnemonic name, so that
7663 later on, we can select the error that most closely describes
7665 record_operand_error_info (opcode
, &inst
.parsing_error
);
7670 DEBUG_TRACE ("parsing SUCCESS");
7675 /* It does some fix-up to provide some programmer friendly feature while
7676 keeping the libopcodes happy, i.e. libopcodes only accepts
7677 the preferred architectural syntax.
7678 Return FALSE if there is any failure; otherwise return TRUE. */
7681 programmer_friendly_fixup (aarch64_instruction
*instr
)
7683 aarch64_inst
*base
= &instr
->base
;
7684 const aarch64_opcode
*opcode
= base
->opcode
;
7685 enum aarch64_op op
= opcode
->op
;
7686 aarch64_opnd_info
*operands
= base
->operands
;
7688 DEBUG_TRACE ("enter");
7690 switch (opcode
->iclass
)
7693 /* TBNZ Xn|Wn, #uimm6, label
7694 Test and Branch Not Zero: conditionally jumps to label if bit number
7695 uimm6 in register Xn is not zero. The bit number implies the width of
7696 the register, which may be written and should be disassembled as Wn if
7697 uimm is less than 32. */
7698 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7700 if (operands
[1].imm
.value
>= 32)
7702 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7706 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7710 /* LDR Wt, label | =value
7711 As a convenience assemblers will typically permit the notation
7712 "=value" in conjunction with the pc-relative literal load instructions
7713 to automatically place an immediate value or symbolic address in a
7714 nearby literal pool and generate a hidden label which references it.
7715 ISREG has been set to 0 in the case of =value. */
7716 if (instr
->gen_lit_pool
7717 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7719 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7720 if (op
== OP_LDRSW_LIT
)
7722 if (instr
->reloc
.exp
.X_op
!= O_constant
7723 && instr
->reloc
.exp
.X_op
!= O_big
7724 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7726 record_operand_error (opcode
, 1,
7727 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7728 _("constant expression expected"));
7731 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7733 record_operand_error (opcode
, 1,
7734 AARCH64_OPDE_OTHER_ERROR
,
7735 _("literal pool insertion failed"));
7743 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7744 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7745 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7746 A programmer-friendly assembler should accept a destination Xd in
7747 place of Wd, however that is not the preferred form for disassembly.
7749 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7750 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7751 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7752 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7757 /* In the 64-bit form, the final register operand is written as Wm
7758 for all but the (possibly omitted) UXTX/LSL and SXTX
7760 As a programmer-friendly assembler, we accept e.g.
7761 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7762 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7763 int idx
= aarch64_operand_index (opcode
->operands
,
7764 AARCH64_OPND_Rm_EXT
);
7765 gas_assert (idx
== 1 || idx
== 2);
7766 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7767 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7768 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7769 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7770 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7771 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7779 DEBUG_TRACE ("exit with SUCCESS");
7783 /* Check for loads and stores that will cause unpredictable behavior. */
7786 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7788 aarch64_inst
*base
= &instr
->base
;
7789 const aarch64_opcode
*opcode
= base
->opcode
;
7790 const aarch64_opnd_info
*opnds
= base
->operands
;
7791 switch (opcode
->iclass
)
7798 /* Loading/storing the base register is unpredictable if writeback. */
7799 if ((aarch64_get_operand_class (opnds
[0].type
)
7800 == AARCH64_OPND_CLASS_INT_REG
)
7801 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7802 && opnds
[1].addr
.base_regno
!= REG_SP
7803 /* Exempt STG/STZG/ST2G/STZ2G. */
7804 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7805 && opnds
[1].addr
.writeback
)
7806 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7810 case ldstnapair_offs
:
7811 case ldstpair_indexed
:
7812 /* Loading/storing the base register is unpredictable if writeback. */
7813 if ((aarch64_get_operand_class (opnds
[0].type
)
7814 == AARCH64_OPND_CLASS_INT_REG
)
7815 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7816 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7817 && opnds
[2].addr
.base_regno
!= REG_SP
7819 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7820 && opnds
[2].addr
.writeback
)
7821 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7822 /* Load operations must load different registers. */
7823 if ((opcode
->opcode
& (1 << 22))
7824 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7825 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7829 if ((aarch64_get_operand_class (opnds
[0].type
)
7830 == AARCH64_OPND_CLASS_INT_REG
)
7831 && (aarch64_get_operand_class (opnds
[1].type
)
7832 == AARCH64_OPND_CLASS_INT_REG
))
7834 if ((opcode
->opcode
& (1 << 22)))
7836 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7837 if ((opcode
->opcode
& (1 << 21))
7838 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7839 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7843 /* Store-Exclusive is unpredictable if Rt == Rs. */
7844 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7846 (_("unpredictable: identical transfer and status registers"
7849 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7851 if (!(opcode
->opcode
& (1 << 21)))
7852 /* Store-Exclusive is unpredictable if Rn == Rs. */
7854 (_("unpredictable: identical base and status registers"
7857 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7859 (_("unpredictable: "
7860 "identical transfer and status registers"
7864 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7865 if ((opcode
->opcode
& (1 << 21))
7866 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7867 && opnds
[3].reg
.regno
!= REG_SP
)
7868 as_warn (_("unpredictable: identical base and status registers"
7880 force_automatic_sequence_close (void)
7882 struct aarch64_segment_info_type
*tc_seg_info
;
7884 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7885 if (tc_seg_info
->insn_sequence
.instr
)
7887 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7888 _("previous `%s' sequence has not been closed"),
7889 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7890 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7894 /* A wrapper function to interface with libopcodes on encoding and
7895 record the error message if there is any.
7897 Return TRUE on success; otherwise return FALSE. */
7900 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7903 aarch64_operand_error error_info
;
7904 memset (&error_info
, '\0', sizeof (error_info
));
7905 error_info
.kind
= AARCH64_OPDE_NIL
;
7906 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7907 && !error_info
.non_fatal
)
7910 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7911 record_operand_error_info (opcode
, &error_info
);
7912 return error_info
.non_fatal
;
7915 #ifdef DEBUG_AARCH64
7917 dump_opcode_operands (const aarch64_opcode
*opcode
)
7920 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7922 aarch64_verbose ("\t\t opnd%d: %s", i
,
7923 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7924 ? aarch64_get_operand_name (opcode
->operands
[i
])
7925 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7929 #endif /* DEBUG_AARCH64 */
7931 /* This is the guts of the machine-dependent assembler. STR points to a
7932 machine dependent instruction. This function is supposed to emit
7933 the frags/bytes it assembles to. */
7936 md_assemble (char *str
)
7938 templates
*template;
7939 const aarch64_opcode
*opcode
;
7940 struct aarch64_segment_info_type
*tc_seg_info
;
7941 aarch64_inst
*inst_base
;
7942 unsigned saved_cond
;
7944 /* Align the previous label if needed. */
7945 if (last_label_seen
!= NULL
)
7947 symbol_set_frag (last_label_seen
, frag_now
);
7948 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7949 S_SET_SEGMENT (last_label_seen
, now_seg
);
7952 /* Update the current insn_sequence from the segment. */
7953 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7954 insn_sequence
= &tc_seg_info
->insn_sequence
;
7955 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7957 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7959 DEBUG_TRACE ("\n\n");
7960 DEBUG_TRACE ("==============================");
7961 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7963 /* Scan up to the end of the mnemonic, which must end in whitespace,
7964 '.', or end of string. */
7967 for (; is_part_of_name (*p
); p
++)
7968 if (*p
== '.' && !dot
)
7973 as_bad (_("unknown mnemonic -- `%s'"), str
);
7977 if (!dot
&& create_register_alias (str
, p
))
7980 template = opcode_lookup (str
, dot
, p
);
7983 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7988 skip_whitespace (p
);
7991 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7992 get_mnemonic_name (str
), str
);
7996 init_operand_error_report ();
7998 /* Sections are assumed to start aligned. In executable section, there is no
7999 MAP_DATA symbol pending. So we only align the address during
8000 MAP_DATA --> MAP_INSN transition.
8001 For other sections, this is not guaranteed. */
8002 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8003 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8004 frag_align_code (2, 0);
8006 saved_cond
= inst
.cond
;
8007 reset_aarch64_instruction (&inst
);
8008 inst
.cond
= saved_cond
;
8010 /* Iterate through all opcode entries with the same mnemonic name. */
8013 opcode
= template->opcode
;
8015 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8016 #ifdef DEBUG_AARCH64
8018 dump_opcode_operands (opcode
);
8019 #endif /* DEBUG_AARCH64 */
8021 mapping_state (MAP_INSN
);
8023 inst_base
= &inst
.base
;
8024 inst_base
->opcode
= opcode
;
8026 /* Truly conditionally executed instructions, e.g. b.cond. */
8027 if (opcode
->flags
& F_COND
)
8029 gas_assert (inst
.cond
!= COND_ALWAYS
);
8030 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8031 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8033 else if (inst
.cond
!= COND_ALWAYS
)
8035 /* It shouldn't arrive here, where the assembly looks like a
8036 conditional instruction but the found opcode is unconditional. */
8041 if (parse_operands (p
, opcode
)
8042 && programmer_friendly_fixup (&inst
)
8043 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8045 /* Check that this instruction is supported for this CPU. */
8046 if (!opcode
->avariant
8047 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8049 as_bad (_("selected processor does not support `%s'"), str
);
8053 warn_unpredictable_ldst (&inst
, str
);
8055 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8056 || !inst
.reloc
.need_libopcodes_p
)
8060 /* If there is relocation generated for the instruction,
8061 store the instruction information for the future fix-up. */
8062 struct aarch64_inst
*copy
;
8063 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8064 copy
= XNEW (struct aarch64_inst
);
8065 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8069 /* Issue non-fatal messages if any. */
8070 output_operand_error_report (str
, true);
8074 template = template->next
;
8075 if (template != NULL
)
8077 reset_aarch64_instruction (&inst
);
8078 inst
.cond
= saved_cond
;
8081 while (template != NULL
);
8083 /* Issue the error messages if any. */
8084 output_operand_error_report (str
, false);
8087 /* Various frobbings of labels and their addresses. */
8090 aarch64_start_line_hook (void)
8092 last_label_seen
= NULL
;
8096 aarch64_frob_label (symbolS
* sym
)
8098 last_label_seen
= sym
;
8100 dwarf2_emit_label (sym
);
8104 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8106 /* Check to see if we have a block to close. */
8107 force_automatic_sequence_close ();
8111 aarch64_data_in_code (void)
8113 if (startswith (input_line_pointer
+ 1, "data:"))
8115 *input_line_pointer
= '/';
8116 input_line_pointer
+= 5;
8117 *input_line_pointer
= 0;
8125 aarch64_canonicalize_symbol_name (char *name
)
8129 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8130 *(name
+ len
- 5) = 0;
8135 /* Table of all register names defined by default. The user can
8136 define additional names with .req. Note that all register names
8137 should appear in both upper and lowercase variants. Some registers
8138 also have mixed-case names. */
8140 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8141 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8142 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8143 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8144 #define REGSET16(p,t) \
8145 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8146 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8147 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8148 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8149 #define REGSET16S(p,s,t) \
8150 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8151 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8152 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8153 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8154 #define REGSET31(p,t) \
8156 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8157 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8158 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8159 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8160 #define REGSET(p,t) \
8161 REGSET31(p,t), REGNUM(p,31,t)
8163 /* These go into aarch64_reg_hsh hash-table. */
8164 static const reg_entry reg_names
[] = {
8165 /* Integer registers. */
8166 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8167 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8169 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8170 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8171 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8172 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8173 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8174 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8176 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8177 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8179 /* Floating-point single precision registers. */
8180 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8182 /* Floating-point double precision registers. */
8183 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8185 /* Floating-point half precision registers. */
8186 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8188 /* Floating-point byte precision registers. */
8189 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8191 /* Floating-point quad precision registers. */
8192 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8194 /* FP/SIMD registers. */
8195 REGSET (v
, VN
), REGSET (V
, VN
),
8197 /* SVE vector registers. */
8198 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8200 /* SVE predicate registers. */
8201 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8203 /* SME ZA. We model this as a register because it acts syntactically
8204 like ZA0H, supporting qualifier suffixes and indexing. */
8205 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8207 /* SME ZA tile registers. */
8208 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8210 /* SME ZA tile registers (horizontal slice). */
8211 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8213 /* SME ZA tile registers (vertical slice). */
8214 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8232 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8233 static const asm_nzcv nzcv_names
[] = {
8234 {"nzcv", B (n
, z
, c
, v
)},
8235 {"nzcV", B (n
, z
, c
, V
)},
8236 {"nzCv", B (n
, z
, C
, v
)},
8237 {"nzCV", B (n
, z
, C
, V
)},
8238 {"nZcv", B (n
, Z
, c
, v
)},
8239 {"nZcV", B (n
, Z
, c
, V
)},
8240 {"nZCv", B (n
, Z
, C
, v
)},
8241 {"nZCV", B (n
, Z
, C
, V
)},
8242 {"Nzcv", B (N
, z
, c
, v
)},
8243 {"NzcV", B (N
, z
, c
, V
)},
8244 {"NzCv", B (N
, z
, C
, v
)},
8245 {"NzCV", B (N
, z
, C
, V
)},
8246 {"NZcv", B (N
, Z
, c
, v
)},
8247 {"NZcV", B (N
, Z
, c
, V
)},
8248 {"NZCv", B (N
, Z
, C
, v
)},
8249 {"NZCV", B (N
, Z
, C
, V
)}
8262 /* MD interface: bits in the object file. */
8264 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8265 for use in the a.out file, and stores them in the array pointed to by buf.
8266 This knows about the endian-ness of the target machine and does
8267 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8268 2 (short) and 4 (long) Floating numbers are put out as a series of
8269 LITTLENUMS (shorts, here at least). */
8272 md_number_to_chars (char *buf
, valueT val
, int n
)
8274 if (target_big_endian
)
8275 number_to_chars_bigendian (buf
, val
, n
);
8277 number_to_chars_littleendian (buf
, val
, n
);
8280 /* MD interface: Sections. */
8282 /* Estimate the size of a frag before relaxing. Assume everything fits in
8286 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8292 /* Round up a section size to the appropriate boundary. */
8295 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8300 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8301 of an rs_align_code fragment.
8303 Here we fill the frag with the appropriate info for padding the
8304 output stream. The resulting frag will consist of a fixed (fr_fix)
8305 and of a repeating (fr_var) part.
8307 The fixed content is always emitted before the repeating content and
8308 these two parts are used as follows in constructing the output:
8309 - the fixed part will be used to align to a valid instruction word
8310 boundary, in case that we start at a misaligned address; as no
8311 executable instruction can live at the misaligned location, we
8312 simply fill with zeros;
8313 - the variable part will be used to cover the remaining padding and
8314 we fill using the AArch64 NOP instruction.
8316 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8317 enough storage space for up to 3 bytes for padding the back to a valid
8318 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8321 aarch64_handle_align (fragS
* fragP
)
8323 /* NOP = d503201f */
8324 /* AArch64 instructions are always little-endian. */
8325 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8327 int bytes
, fix
, noop_size
;
8330 if (fragP
->fr_type
!= rs_align_code
)
8333 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8334 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8337 gas_assert (fragP
->tc_frag_data
.recorded
);
8340 noop_size
= sizeof (aarch64_noop
);
8342 fix
= bytes
& (noop_size
- 1);
8345 #if defined OBJ_ELF || defined OBJ_COFF
8346 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8350 fragP
->fr_fix
+= fix
;
8354 memcpy (p
, aarch64_noop
, noop_size
);
8355 fragP
->fr_var
= noop_size
;
8358 /* Perform target specific initialisation of a frag.
8359 Note - despite the name this initialisation is not done when the frag
8360 is created, but only when its type is assigned. A frag can be created
8361 and used a long time before its type is set, so beware of assuming that
8362 this initialisation is performed first. */
8366 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8367 int max_chars ATTRIBUTE_UNUSED
)
8371 #else /* OBJ_ELF is defined. */
8373 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8375 /* Record a mapping symbol for alignment frags. We will delete this
8376 later if the alignment ends up empty. */
8377 if (!fragP
->tc_frag_data
.recorded
)
8378 fragP
->tc_frag_data
.recorded
= 1;
8380 /* PR 21809: Do not set a mapping state for debug sections
8381 - it just confuses other tools. */
8382 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8385 switch (fragP
->fr_type
)
8389 mapping_state_2 (MAP_DATA
, max_chars
);
8392 /* PR 20364: We can get alignment frags in code sections,
8393 so do not just assume that we should use the MAP_DATA state. */
8394 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8397 mapping_state_2 (MAP_INSN
, max_chars
);
8404 /* Whether SFrame stack trace info is supported. */
8407 aarch64_support_sframe_p (void)
8409 /* At this time, SFrame is supported for aarch64 only. */
8410 return (aarch64_abi
== AARCH64_ABI_LP64
);
8413 /* Specify if RA tracking is needed. */
8416 aarch64_sframe_ra_tracking_p (void)
8421 /* Specify the fixed offset to recover RA from CFA.
8422 (useful only when RA tracking is not needed). */
8425 aarch64_sframe_cfa_ra_offset (void)
8427 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8430 /* Get the abi/arch indentifier for SFrame. */
8433 aarch64_sframe_get_abi_arch (void)
8435 unsigned char sframe_abi_arch
= 0;
8437 if (aarch64_support_sframe_p ())
8439 sframe_abi_arch
= target_big_endian
8440 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8441 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8444 return sframe_abi_arch
;
8447 #endif /* OBJ_ELF */
8449 /* Initialize the DWARF-2 unwind information for this procedure. */
8452 tc_aarch64_frame_initial_instructions (void)
8454 cfi_add_CFA_def_cfa (REG_SP
, 0);
8457 /* Convert REGNAME to a DWARF-2 register number. */
8460 tc_aarch64_regname_to_dw2regnum (char *regname
)
8462 const reg_entry
*reg
= parse_reg (®name
);
8468 case REG_TYPE_SP_32
:
8469 case REG_TYPE_SP_64
:
8479 return reg
->number
+ 64;
8487 /* Implement DWARF2_ADDR_SIZE. */
8490 aarch64_dwarf2_addr_size (void)
8496 return bfd_arch_bits_per_address (stdoutput
) / 8;
8499 /* MD interface: Symbol and relocation handling. */
8501 /* Return the address within the segment that a PC-relative fixup is
8502 relative to. For AArch64 PC-relative fixups applied to instructions
8503 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8506 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8508 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8510 /* If this is pc-relative and we are going to emit a relocation
8511 then we just want to put out any pipeline compensation that the linker
8512 will need. Otherwise we want to use the calculated base. */
8514 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8515 || aarch64_force_relocation (fixP
)))
8518 /* AArch64 should be consistent for all pc-relative relocations. */
8519 return base
+ AARCH64_PCREL_OFFSET
;
8522 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8523 Otherwise we have no need to default values of symbols. */
8526 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8529 if (name
[0] == '_' && name
[1] == 'G'
8530 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8534 if (symbol_find (name
))
8535 as_bad (_("GOT already in the symbol table"));
8537 GOT_symbol
= symbol_new (name
, undefined_section
,
8538 &zero_address_frag
, 0);
8548 /* Return non-zero if the indicated VALUE has overflowed the maximum
8549 range expressible by a unsigned number with the indicated number of
8553 unsigned_overflow (valueT value
, unsigned bits
)
8556 if (bits
>= sizeof (valueT
) * 8)
8558 lim
= (valueT
) 1 << bits
;
8559 return (value
>= lim
);
8563 /* Return non-zero if the indicated VALUE has overflowed the maximum
8564 range expressible by an signed number with the indicated number of
8568 signed_overflow (offsetT value
, unsigned bits
)
8571 if (bits
>= sizeof (offsetT
) * 8)
8573 lim
= (offsetT
) 1 << (bits
- 1);
8574 return (value
< -lim
|| value
>= lim
);
8577 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8578 unsigned immediate offset load/store instruction, try to encode it as
8579 an unscaled, 9-bit, signed immediate offset load/store instruction.
8580 Return TRUE if it is successful; otherwise return FALSE.
8582 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8583 in response to the standard LDR/STR mnemonics when the immediate offset is
8584 unambiguous, i.e. when it is negative or unaligned. */
8587 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8590 enum aarch64_op new_op
;
8591 const aarch64_opcode
*new_opcode
;
8593 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8595 switch (instr
->opcode
->op
)
8597 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8598 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8599 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8600 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8601 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8602 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8603 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8604 case OP_STR_POS
: new_op
= OP_STUR
; break;
8605 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8606 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8607 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8608 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8609 default: new_op
= OP_NIL
; break;
8612 if (new_op
== OP_NIL
)
8615 new_opcode
= aarch64_get_opcode (new_op
);
8616 gas_assert (new_opcode
!= NULL
);
8618 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8619 instr
->opcode
->op
, new_opcode
->op
);
8621 aarch64_replace_opcode (instr
, new_opcode
);
8623 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8624 qualifier matching may fail because the out-of-date qualifier will
8625 prevent the operand being updated with a new and correct qualifier. */
8626 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8627 AARCH64_OPND_ADDR_SIMM9
);
8628 gas_assert (idx
== 1);
8629 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8631 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8633 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8640 /* Called by fix_insn to fix a MOV immediate alias instruction.
8642 Operand for a generic move immediate instruction, which is an alias
8643 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8644 a 32-bit/64-bit immediate value into general register. An assembler error
8645 shall result if the immediate cannot be created by a single one of these
8646 instructions. If there is a choice, then to ensure reversability an
8647 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8650 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8652 const aarch64_opcode
*opcode
;
8654 /* Need to check if the destination is SP/ZR. The check has to be done
8655 before any aarch64_replace_opcode. */
8656 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8657 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8659 instr
->operands
[1].imm
.value
= value
;
8660 instr
->operands
[1].skip
= 0;
8664 /* Try the MOVZ alias. */
8665 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8666 aarch64_replace_opcode (instr
, opcode
);
8667 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8668 &instr
->value
, NULL
, NULL
, insn_sequence
))
8670 put_aarch64_insn (buf
, instr
->value
);
8673 /* Try the MOVK alias. */
8674 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8675 aarch64_replace_opcode (instr
, opcode
);
8676 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8677 &instr
->value
, NULL
, NULL
, insn_sequence
))
8679 put_aarch64_insn (buf
, instr
->value
);
8684 if (try_mov_bitmask_p
)
8686 /* Try the ORR alias. */
8687 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8688 aarch64_replace_opcode (instr
, opcode
);
8689 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8690 &instr
->value
, NULL
, NULL
, insn_sequence
))
8692 put_aarch64_insn (buf
, instr
->value
);
8697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8698 _("immediate cannot be moved by a single instruction"));
8701 /* An instruction operand which is immediate related may have symbol used
8702 in the assembly, e.g.
8705 .set u32, 0x00ffff00
8707 At the time when the assembly instruction is parsed, a referenced symbol,
8708 like 'u32' in the above example may not have been seen; a fixS is created
8709 in such a case and is handled here after symbols have been resolved.
8710 Instruction is fixed up with VALUE using the information in *FIXP plus
8711 extra information in FLAGS.
8713 This function is called by md_apply_fix to fix up instructions that need
8714 a fix-up described above but does not involve any linker-time relocation. */
8717 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8721 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8722 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8723 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8727 /* Now the instruction is about to be fixed-up, so the operand that
8728 was previously marked as 'ignored' needs to be unmarked in order
8729 to get the encoding done properly. */
8730 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8731 new_inst
->operands
[idx
].skip
= 0;
8734 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8738 case AARCH64_OPND_EXCEPTION
:
8739 case AARCH64_OPND_UNDEFINED
:
8740 if (unsigned_overflow (value
, 16))
8741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8742 _("immediate out of range"));
8743 insn
= get_aarch64_insn (buf
);
8744 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8745 put_aarch64_insn (buf
, insn
);
8748 case AARCH64_OPND_AIMM
:
8749 /* ADD or SUB with immediate.
8750 NOTE this assumes we come here with a add/sub shifted reg encoding
8751 3 322|2222|2 2 2 21111 111111
8752 1 098|7654|3 2 1 09876 543210 98765 43210
8753 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8754 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8755 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8756 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8758 3 322|2222|2 2 221111111111
8759 1 098|7654|3 2 109876543210 98765 43210
8760 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8761 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8762 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8763 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8764 Fields sf Rn Rd are already set. */
8765 insn
= get_aarch64_insn (buf
);
8769 insn
= reencode_addsub_switch_add_sub (insn
);
8773 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8774 && unsigned_overflow (value
, 12))
8776 /* Try to shift the value by 12 to make it fit. */
8777 if (((value
>> 12) << 12) == value
8778 && ! unsigned_overflow (value
, 12 + 12))
8781 insn
|= encode_addsub_imm_shift_amount (1);
8785 if (unsigned_overflow (value
, 12))
8786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8787 _("immediate out of range"));
8789 insn
|= encode_addsub_imm (value
);
8791 put_aarch64_insn (buf
, insn
);
8794 case AARCH64_OPND_SIMD_IMM
:
8795 case AARCH64_OPND_SIMD_IMM_SFT
:
8796 case AARCH64_OPND_LIMM
:
8797 /* Bit mask immediate. */
8798 gas_assert (new_inst
!= NULL
);
8799 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8800 new_inst
->operands
[idx
].imm
.value
= value
;
8801 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8802 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8803 put_aarch64_insn (buf
, new_inst
->value
);
8805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8806 _("invalid immediate"));
8809 case AARCH64_OPND_HALF
:
8810 /* 16-bit unsigned immediate. */
8811 if (unsigned_overflow (value
, 16))
8812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8813 _("immediate out of range"));
8814 insn
= get_aarch64_insn (buf
);
8815 insn
|= encode_movw_imm (value
& 0xffff);
8816 put_aarch64_insn (buf
, insn
);
8819 case AARCH64_OPND_IMM_MOV
:
8820 /* Operand for a generic move immediate instruction, which is
8821 an alias instruction that generates a single MOVZ, MOVN or ORR
8822 instruction to loads a 32-bit/64-bit immediate value into general
8823 register. An assembler error shall result if the immediate cannot be
8824 created by a single one of these instructions. If there is a choice,
8825 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8826 and MOVZ or MOVN to ORR. */
8827 gas_assert (new_inst
!= NULL
);
8828 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8831 case AARCH64_OPND_ADDR_SIMM7
:
8832 case AARCH64_OPND_ADDR_SIMM9
:
8833 case AARCH64_OPND_ADDR_SIMM9_2
:
8834 case AARCH64_OPND_ADDR_SIMM10
:
8835 case AARCH64_OPND_ADDR_UIMM12
:
8836 case AARCH64_OPND_ADDR_SIMM11
:
8837 case AARCH64_OPND_ADDR_SIMM13
:
8838 /* Immediate offset in an address. */
8839 insn
= get_aarch64_insn (buf
);
8841 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8842 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8843 || new_inst
->opcode
->operands
[2] == opnd
);
8845 /* Get the index of the address operand. */
8846 if (new_inst
->opcode
->operands
[1] == opnd
)
8847 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8850 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8853 /* Update the resolved offset value. */
8854 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8856 /* Encode/fix-up. */
8857 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8858 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8860 put_aarch64_insn (buf
, new_inst
->value
);
8863 else if (new_inst
->opcode
->iclass
== ldst_pos
8864 && try_to_encode_as_unscaled_ldst (new_inst
))
8866 put_aarch64_insn (buf
, new_inst
->value
);
8870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8871 _("immediate offset out of range"));
8876 as_fatal (_("unhandled operand code %d"), opnd
);
8880 /* Apply a fixup (fixP) to segment data, once it has been determined
8881 by our caller that we have all the info we need to fix it up.
8883 Parameter valP is the pointer to the value of the bits. */
8886 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8888 offsetT value
= *valP
;
8890 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8892 unsigned flags
= fixP
->fx_addnumber
;
8894 DEBUG_TRACE ("\n\n");
8895 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8896 DEBUG_TRACE ("Enter md_apply_fix");
8898 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8900 /* Note whether this will delete the relocation. */
8902 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8903 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8906 /* Process the relocations. */
8907 switch (fixP
->fx_r_type
)
8909 case BFD_RELOC_NONE
:
8910 /* This will need to go in the object file. */
8915 case BFD_RELOC_8_PCREL
:
8916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8917 md_number_to_chars (buf
, value
, 1);
8921 case BFD_RELOC_16_PCREL
:
8922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8923 md_number_to_chars (buf
, value
, 2);
8927 case BFD_RELOC_32_PCREL
:
8928 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8929 md_number_to_chars (buf
, value
, 4);
8933 case BFD_RELOC_64_PCREL
:
8934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8935 md_number_to_chars (buf
, value
, 8);
8938 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8939 /* We claim that these fixups have been processed here, even if
8940 in fact we generate an error because we do not have a reloc
8941 for them, so tc_gen_reloc() will reject them. */
8943 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8946 _("undefined symbol %s used as an immediate value"),
8947 S_GET_NAME (fixP
->fx_addsy
));
8948 goto apply_fix_return
;
8950 fix_insn (fixP
, flags
, value
);
8953 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8954 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8958 _("pc-relative load offset not word aligned"));
8959 if (signed_overflow (value
, 21))
8960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8961 _("pc-relative load offset out of range"));
8962 insn
= get_aarch64_insn (buf
);
8963 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8964 put_aarch64_insn (buf
, insn
);
8968 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8969 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8971 if (signed_overflow (value
, 21))
8972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8973 _("pc-relative address offset out of range"));
8974 insn
= get_aarch64_insn (buf
);
8975 insn
|= encode_adr_imm (value
);
8976 put_aarch64_insn (buf
, insn
);
8980 case BFD_RELOC_AARCH64_BRANCH19
:
8981 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8985 _("conditional branch target not word aligned"));
8986 if (signed_overflow (value
, 21))
8987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8988 _("conditional branch out of range"));
8989 insn
= get_aarch64_insn (buf
);
8990 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8991 put_aarch64_insn (buf
, insn
);
8995 case BFD_RELOC_AARCH64_TSTBR14
:
8996 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9000 _("conditional branch target not word aligned"));
9001 if (signed_overflow (value
, 16))
9002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9003 _("conditional branch out of range"));
9004 insn
= get_aarch64_insn (buf
);
9005 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9006 put_aarch64_insn (buf
, insn
);
9010 case BFD_RELOC_AARCH64_CALL26
:
9011 case BFD_RELOC_AARCH64_JUMP26
:
9012 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9016 _("branch target not word aligned"));
9017 if (signed_overflow (value
, 28))
9018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9019 _("branch out of range"));
9020 insn
= get_aarch64_insn (buf
);
9021 insn
|= encode_branch_ofs_26 (value
>> 2);
9022 put_aarch64_insn (buf
, insn
);
9026 case BFD_RELOC_AARCH64_MOVW_G0
:
9027 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9028 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9029 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9030 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9031 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9034 case BFD_RELOC_AARCH64_MOVW_G1
:
9035 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9036 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9037 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9038 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9039 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9042 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9044 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9045 /* Should always be exported to object file, see
9046 aarch64_force_relocation(). */
9047 gas_assert (!fixP
->fx_done
);
9048 gas_assert (seg
->use_rela_p
);
9050 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9052 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9053 /* Should always be exported to object file, see
9054 aarch64_force_relocation(). */
9055 gas_assert (!fixP
->fx_done
);
9056 gas_assert (seg
->use_rela_p
);
9058 case BFD_RELOC_AARCH64_MOVW_G2
:
9059 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9060 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9061 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9062 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9065 case BFD_RELOC_AARCH64_MOVW_G3
:
9066 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9069 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9071 insn
= get_aarch64_insn (buf
);
9075 /* REL signed addend must fit in 16 bits */
9076 if (signed_overflow (value
, 16))
9077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9078 _("offset out of range"));
9082 /* Check for overflow and scale. */
9083 switch (fixP
->fx_r_type
)
9085 case BFD_RELOC_AARCH64_MOVW_G0
:
9086 case BFD_RELOC_AARCH64_MOVW_G1
:
9087 case BFD_RELOC_AARCH64_MOVW_G2
:
9088 case BFD_RELOC_AARCH64_MOVW_G3
:
9089 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9090 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9091 if (unsigned_overflow (value
, scale
+ 16))
9092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9093 _("unsigned value out of range"));
9095 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9096 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9097 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9098 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9099 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9100 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9101 /* NOTE: We can only come here with movz or movn. */
9102 if (signed_overflow (value
, scale
+ 16))
9103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9104 _("signed value out of range"));
9107 /* Force use of MOVN. */
9109 insn
= reencode_movzn_to_movn (insn
);
9113 /* Force use of MOVZ. */
9114 insn
= reencode_movzn_to_movz (insn
);
9118 /* Unchecked relocations. */
9124 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9125 insn
|= encode_movw_imm (value
& 0xffff);
9127 put_aarch64_insn (buf
, insn
);
9131 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9132 fixP
->fx_r_type
= (ilp32_p
9133 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9134 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9135 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9136 /* Should always be exported to object file, see
9137 aarch64_force_relocation(). */
9138 gas_assert (!fixP
->fx_done
);
9139 gas_assert (seg
->use_rela_p
);
9142 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9143 fixP
->fx_r_type
= (ilp32_p
9144 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9145 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9146 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9147 /* Should always be exported to object file, see
9148 aarch64_force_relocation(). */
9149 gas_assert (!fixP
->fx_done
);
9150 gas_assert (seg
->use_rela_p
);
9153 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9154 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9155 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9156 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9157 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9158 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9159 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9160 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9161 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9162 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9163 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9164 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9165 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9166 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9167 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9168 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9169 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9170 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9171 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9172 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9173 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9174 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9175 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9176 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9177 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9178 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9179 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9180 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9181 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9182 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9183 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9184 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9185 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9186 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9187 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9188 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9189 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9190 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9191 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9192 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9193 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9194 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9195 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9196 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9197 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9198 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9199 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9200 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9201 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9202 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9203 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9204 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9205 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9206 /* Should always be exported to object file, see
9207 aarch64_force_relocation(). */
9208 gas_assert (!fixP
->fx_done
);
9209 gas_assert (seg
->use_rela_p
);
9212 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9213 /* Should always be exported to object file, see
9214 aarch64_force_relocation(). */
9215 fixP
->fx_r_type
= (ilp32_p
9216 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9217 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9218 gas_assert (!fixP
->fx_done
);
9219 gas_assert (seg
->use_rela_p
);
9222 case BFD_RELOC_AARCH64_ADD_LO12
:
9223 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9224 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9225 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9226 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9227 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9228 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9229 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9230 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9231 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9232 case BFD_RELOC_AARCH64_LDST128_LO12
:
9233 case BFD_RELOC_AARCH64_LDST16_LO12
:
9234 case BFD_RELOC_AARCH64_LDST32_LO12
:
9235 case BFD_RELOC_AARCH64_LDST64_LO12
:
9236 case BFD_RELOC_AARCH64_LDST8_LO12
:
9237 /* Should always be exported to object file, see
9238 aarch64_force_relocation(). */
9239 gas_assert (!fixP
->fx_done
);
9240 gas_assert (seg
->use_rela_p
);
9243 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9244 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9245 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9248 case BFD_RELOC_UNUSED
:
9249 /* An error will already have been reported. */
9253 case BFD_RELOC_32_SECREL
:
9254 case BFD_RELOC_16_SECIDX
:
9258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9259 _("unexpected %s fixup"),
9260 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9265 /* Free the allocated the struct aarch64_inst.
9266 N.B. currently there are very limited number of fix-up types actually use
9267 this field, so the impact on the performance should be minimal . */
9268 free (fixP
->tc_fix_data
.inst
);
9273 /* Translate internal representation of relocation info to BFD target
9277 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9280 bfd_reloc_code_real_type code
;
9282 reloc
= XNEW (arelent
);
9284 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9285 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9286 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9290 if (section
->use_rela_p
)
9291 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9293 fixp
->fx_offset
= reloc
->address
;
9295 reloc
->addend
= fixp
->fx_offset
;
9297 code
= fixp
->fx_r_type
;
9302 code
= BFD_RELOC_16_PCREL
;
9307 code
= BFD_RELOC_32_PCREL
;
9312 code
= BFD_RELOC_64_PCREL
;
9319 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9320 if (reloc
->howto
== NULL
)
9322 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9324 ("cannot represent %s relocation in this object file format"),
9325 bfd_get_reloc_code_name (code
));
9332 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9335 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9337 bfd_reloc_code_real_type type
;
9341 if (exp
->X_op
== O_secrel
)
9343 exp
->X_op
= O_symbol
;
9344 type
= BFD_RELOC_32_SECREL
;
9346 else if (exp
->X_op
== O_secidx
)
9348 exp
->X_op
= O_symbol
;
9349 type
= BFD_RELOC_16_SECIDX
;
9355 FIXME: @@ Should look at CPU word size. */
9362 type
= BFD_RELOC_16
;
9365 type
= BFD_RELOC_32
;
9368 type
= BFD_RELOC_64
;
9371 as_bad (_("cannot do %u-byte relocation"), size
);
9372 type
= BFD_RELOC_UNUSED
;
9379 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9382 /* Implement md_after_parse_args. This is the earliest time we need to decide
9383 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9386 aarch64_after_parse_args (void)
9388 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9392 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9393 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9394 aarch64_abi
= AARCH64_ABI_ILP32
;
9396 aarch64_abi
= AARCH64_ABI_LP64
;
9398 aarch64_abi
= AARCH64_ABI_LLP64
;
9404 elf64_aarch64_target_format (void)
9407 /* FIXME: What to do for ilp32_p ? */
9408 if (target_big_endian
)
9409 return "elf64-bigaarch64-cloudabi";
9411 return "elf64-littleaarch64-cloudabi";
9413 if (target_big_endian
)
9414 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9416 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9421 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9423 elf_frob_symbol (symp
, puntp
);
9425 #elif defined OBJ_COFF
9427 coff_aarch64_target_format (void)
9429 return "pe-aarch64-little";
9433 /* MD interface: Finalization. */
9435 /* A good place to do this, although this was probably not intended
9436 for this kind of use. We need to dump the literal pool before
9437 references are made to a null symbol pointer. */
9440 aarch64_cleanup (void)
9444 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9446 /* Put it at the end of the relevant section. */
9447 subseg_set (pool
->section
, pool
->sub_section
);
9453 /* Remove any excess mapping symbols generated for alignment frags in
9454 SEC. We may have created a mapping symbol before a zero byte
9455 alignment; remove it if there's a mapping symbol after the
9458 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9459 void *dummy ATTRIBUTE_UNUSED
)
9461 segment_info_type
*seginfo
= seg_info (sec
);
9464 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9467 for (fragp
= seginfo
->frchainP
->frch_root
;
9468 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9470 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9471 fragS
*next
= fragp
->fr_next
;
9473 /* Variable-sized frags have been converted to fixed size by
9474 this point. But if this was variable-sized to start with,
9475 there will be a fixed-size frag after it. So don't handle
9477 if (sym
== NULL
|| next
== NULL
)
9480 if (S_GET_VALUE (sym
) < next
->fr_address
)
9481 /* Not at the end of this frag. */
9483 know (S_GET_VALUE (sym
) == next
->fr_address
);
9487 if (next
->tc_frag_data
.first_map
!= NULL
)
9489 /* Next frag starts with a mapping symbol. Discard this
9491 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9495 if (next
->fr_next
== NULL
)
9497 /* This mapping symbol is at the end of the section. Discard
9499 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9500 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9504 /* As long as we have empty frags without any mapping symbols,
9506 /* If the next frag is non-empty and does not start with a
9507 mapping symbol, then this mapping symbol is required. */
9508 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9511 next
= next
->fr_next
;
9513 while (next
!= NULL
);
9518 /* Adjust the symbol table. */
9521 aarch64_adjust_symtab (void)
9524 /* Remove any overlapping mapping symbols generated by alignment frags. */
9525 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9526 /* Now do generic ELF adjustments. */
9527 elf_adjust_symtab ();
9532 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9534 str_hash_insert (table
, key
, value
, 0);
9538 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9540 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9541 checked_hash_insert (table
, key
, value
);
9545 fill_instruction_hash_table (void)
9547 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9549 while (opcode
->name
!= NULL
)
9551 templates
*templ
, *new_templ
;
9552 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9554 new_templ
= XNEW (templates
);
9555 new_templ
->opcode
= opcode
;
9556 new_templ
->next
= NULL
;
9559 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9562 new_templ
->next
= templ
->next
;
9563 templ
->next
= new_templ
;
9570 convert_to_upper (char *dst
, const char *src
, size_t num
)
9573 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9574 *dst
= TOUPPER (*src
);
9578 /* Assume STR point to a lower-case string, allocate, convert and return
9579 the corresponding upper-case string. */
9580 static inline const char*
9581 get_upper_str (const char *str
)
9584 size_t len
= strlen (str
);
9585 ret
= XNEWVEC (char, len
+ 1);
9586 convert_to_upper (ret
, str
, len
);
9590 /* MD interface: Initialization. */
9598 aarch64_ops_hsh
= str_htab_create ();
9599 aarch64_cond_hsh
= str_htab_create ();
9600 aarch64_shift_hsh
= str_htab_create ();
9601 aarch64_sys_regs_hsh
= str_htab_create ();
9602 aarch64_pstatefield_hsh
= str_htab_create ();
9603 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9604 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9605 aarch64_sys_regs_at_hsh
= str_htab_create ();
9606 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9607 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9608 aarch64_reg_hsh
= str_htab_create ();
9609 aarch64_barrier_opt_hsh
= str_htab_create ();
9610 aarch64_nzcv_hsh
= str_htab_create ();
9611 aarch64_pldop_hsh
= str_htab_create ();
9612 aarch64_hint_opt_hsh
= str_htab_create ();
9614 fill_instruction_hash_table ();
9616 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9617 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9618 (void *) (aarch64_sys_regs
+ i
));
9620 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9621 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9622 aarch64_pstatefields
[i
].name
,
9623 (void *) (aarch64_pstatefields
+ i
));
9625 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9626 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9627 aarch64_sys_regs_ic
[i
].name
,
9628 (void *) (aarch64_sys_regs_ic
+ i
));
9630 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9631 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9632 aarch64_sys_regs_dc
[i
].name
,
9633 (void *) (aarch64_sys_regs_dc
+ i
));
9635 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9636 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9637 aarch64_sys_regs_at
[i
].name
,
9638 (void *) (aarch64_sys_regs_at
+ i
));
9640 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9641 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9642 aarch64_sys_regs_tlbi
[i
].name
,
9643 (void *) (aarch64_sys_regs_tlbi
+ i
));
9645 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9646 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9647 aarch64_sys_regs_sr
[i
].name
,
9648 (void *) (aarch64_sys_regs_sr
+ i
));
9650 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9651 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9652 (void *) (reg_names
+ i
));
9654 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9655 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9656 (void *) (nzcv_names
+ i
));
9658 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9660 const char *name
= aarch64_operand_modifiers
[i
].name
;
9661 checked_hash_insert (aarch64_shift_hsh
, name
,
9662 (void *) (aarch64_operand_modifiers
+ i
));
9663 /* Also hash the name in the upper case. */
9664 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9665 (void *) (aarch64_operand_modifiers
+ i
));
9668 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9671 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9672 the same condition code. */
9673 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9675 const char *name
= aarch64_conds
[i
].names
[j
];
9678 checked_hash_insert (aarch64_cond_hsh
, name
,
9679 (void *) (aarch64_conds
+ i
));
9680 /* Also hash the name in the upper case. */
9681 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9682 (void *) (aarch64_conds
+ i
));
9686 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9688 const char *name
= aarch64_barrier_options
[i
].name
;
9689 /* Skip xx00 - the unallocated values of option. */
9692 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9693 (void *) (aarch64_barrier_options
+ i
));
9694 /* Also hash the name in the upper case. */
9695 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9696 (void *) (aarch64_barrier_options
+ i
));
9699 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9701 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9702 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9703 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9704 /* Also hash the name in the upper case. */
9705 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9706 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9709 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9711 const char* name
= aarch64_prfops
[i
].name
;
9712 /* Skip the unallocated hint encodings. */
9715 checked_hash_insert (aarch64_pldop_hsh
, name
,
9716 (void *) (aarch64_prfops
+ i
));
9717 /* Also hash the name in the upper case. */
9718 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9719 (void *) (aarch64_prfops
+ i
));
9722 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9724 const char* name
= aarch64_hint_options
[i
].name
;
9725 const char* upper_name
= get_upper_str(name
);
9727 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9728 (void *) (aarch64_hint_options
+ i
));
9730 /* Also hash the name in the upper case if not the same. */
9731 if (strcmp (name
, upper_name
) != 0)
9732 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9733 (void *) (aarch64_hint_options
+ i
));
9736 /* Set the cpu variant based on the command-line options. */
9738 mcpu_cpu_opt
= march_cpu_opt
;
9741 mcpu_cpu_opt
= &cpu_default
;
9743 cpu_variant
= *mcpu_cpu_opt
;
9745 /* Record the CPU type. */
9747 mach
= bfd_mach_aarch64_ilp32
;
9749 mach
= bfd_mach_aarch64_llp64
;
9751 mach
= bfd_mach_aarch64
;
9753 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9755 /* FIXME - is there a better way to do it ? */
9756 aarch64_sframe_cfa_sp_reg
= 31;
9757 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9758 aarch64_sframe_cfa_ra_reg
= 30;
9762 /* Command line processing. */
9764 const char *md_shortopts
= "m:";
9766 #ifdef AARCH64_BI_ENDIAN
9767 #define OPTION_EB (OPTION_MD_BASE + 0)
9768 #define OPTION_EL (OPTION_MD_BASE + 1)
9770 #if TARGET_BYTES_BIG_ENDIAN
9771 #define OPTION_EB (OPTION_MD_BASE + 0)
9773 #define OPTION_EL (OPTION_MD_BASE + 1)
9777 struct option md_longopts
[] = {
9779 {"EB", no_argument
, NULL
, OPTION_EB
},
9782 {"EL", no_argument
, NULL
, OPTION_EL
},
9784 {NULL
, no_argument
, NULL
, 0}
9787 size_t md_longopts_size
= sizeof (md_longopts
);
9789 struct aarch64_option_table
9791 const char *option
; /* Option name to match. */
9792 const char *help
; /* Help information. */
9793 int *var
; /* Variable to change. */
9794 int value
; /* What to change it to. */
9795 char *deprecated
; /* If non-null, print this message. */
9798 static struct aarch64_option_table aarch64_opts
[] = {
9799 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9800 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9802 #ifdef DEBUG_AARCH64
9803 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9804 #endif /* DEBUG_AARCH64 */
9805 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9807 {"mno-verbose-error", N_("do not output verbose error messages"),
9808 &verbose_error_p
, 0, NULL
},
9809 {NULL
, NULL
, NULL
, 0, NULL
}
9812 struct aarch64_cpu_option_table
9815 const aarch64_feature_set value
;
9816 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9818 const char *canonical_name
;
9821 /* This list should, at a minimum, contain all the cpu names
9822 recognized by GCC. */
9823 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9824 {"all", AARCH64_ANY
, NULL
},
9825 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9826 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9827 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9828 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9829 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9830 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9831 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9832 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9833 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9834 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9835 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9836 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9837 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9838 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9840 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9841 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9843 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9844 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9846 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9847 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9848 | AARCH64_FEATURE_DOTPROD
9849 | AARCH64_FEATURE_SSBS
),
9851 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9852 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9853 | AARCH64_FEATURE_DOTPROD
9854 | AARCH64_FEATURE_SSBS
),
9856 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9857 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9858 | AARCH64_FEATURE_DOTPROD
9859 | AARCH64_FEATURE_SSBS
),
9861 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9862 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9863 | AARCH64_FEATURE_DOTPROD
9864 | AARCH64_FEATURE_SSBS
),
9866 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9868 | AARCH64_FEATURE_RCPC
9869 | AARCH64_FEATURE_DOTPROD
9870 | AARCH64_FEATURE_SSBS
9871 | AARCH64_FEATURE_PROFILE
),
9873 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9875 | AARCH64_FEATURE_RCPC
9876 | AARCH64_FEATURE_DOTPROD
9877 | AARCH64_FEATURE_SSBS
9878 | AARCH64_FEATURE_PROFILE
),
9880 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9881 AARCH64_FEATURE_DOTPROD
9882 | AARCH64_FEATURE_F16
9883 | AARCH64_FEATURE_FLAGM
9884 | AARCH64_FEATURE_PAC
9885 | AARCH64_FEATURE_PROFILE
9886 | AARCH64_FEATURE_RCPC
9887 | AARCH64_FEATURE_SSBS
),
9889 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9890 AARCH64_FEATURE_BFLOAT16
9891 | AARCH64_FEATURE_I8MM
9892 | AARCH64_FEATURE_MEMTAG
9893 | AARCH64_FEATURE_SVE2_BITPERM
),
9895 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9896 AARCH64_FEATURE_BFLOAT16
9897 | AARCH64_FEATURE_I8MM
9898 | AARCH64_FEATURE_MEMTAG
9899 | AARCH64_FEATURE_SVE2_BITPERM
),
9901 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9902 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9903 | AARCH64_FEATURE_DOTPROD
9904 | AARCH64_FEATURE_PROFILE
),
9906 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9907 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9908 "Samsung Exynos M1"},
9909 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9910 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9911 | AARCH64_FEATURE_RDMA
),
9913 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9914 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9915 | AARCH64_FEATURE_DOTPROD
9916 | AARCH64_FEATURE_SSBS
),
9918 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9919 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9920 | AARCH64_FEATURE_DOTPROD
9921 | AARCH64_FEATURE_PROFILE
),
9923 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9924 AARCH64_FEATURE_BFLOAT16
9925 | AARCH64_FEATURE_I8MM
9926 | AARCH64_FEATURE_F16
9927 | AARCH64_FEATURE_SVE
9928 | AARCH64_FEATURE_SVE2
9929 | AARCH64_FEATURE_SVE2_BITPERM
9930 | AARCH64_FEATURE_MEMTAG
9931 | AARCH64_FEATURE_RNG
),
9933 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9934 AARCH64_FEATURE_PROFILE
9935 | AARCH64_FEATURE_CVADP
9936 | AARCH64_FEATURE_SVE
9937 | AARCH64_FEATURE_SSBS
9938 | AARCH64_FEATURE_RNG
9939 | AARCH64_FEATURE_F16
9940 | AARCH64_FEATURE_BFLOAT16
9941 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9942 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9943 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9944 | AARCH64_FEATURE_RDMA
),
9945 "Qualcomm QDF24XX"},
9946 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9947 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9948 "Qualcomm Saphira"},
9949 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9950 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9952 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9953 AARCH64_FEATURE_CRYPTO
),
9955 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9956 in earlier releases and is superseded by 'xgene1' in all
9958 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9959 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9960 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9961 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9962 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9963 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9965 | AARCH64_FEATURE_RCPC
9966 | AARCH64_FEATURE_DOTPROD
9967 | AARCH64_FEATURE_SSBS
9968 | AARCH64_FEATURE_PROFILE
),
9970 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9971 AARCH64_FEATURE_BFLOAT16
9972 | AARCH64_FEATURE_I8MM
9973 | AARCH64_FEATURE_MEMTAG
9974 | AARCH64_FEATURE_SVE2_BITPERM
),
9976 {"generic", AARCH64_ARCH_V8
, NULL
},
9978 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9981 struct aarch64_arch_option_table
9984 const aarch64_feature_set value
;
9987 /* This list should, at a minimum, contain all the architecture names
9988 recognized by GCC. */
9989 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9990 {"all", AARCH64_ANY
},
9991 {"armv8-a", AARCH64_ARCH_V8
},
9992 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9993 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9994 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9995 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9996 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9997 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9998 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9999 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10000 {"armv8-r", AARCH64_ARCH_V8_R
},
10001 {"armv9-a", AARCH64_ARCH_V9
},
10002 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10003 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10004 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10005 {NULL
, AARCH64_ARCH_NONE
}
10008 /* ISA extensions. */
10009 struct aarch64_option_cpu_value_table
10012 const aarch64_feature_set value
;
10013 const aarch64_feature_set require
; /* Feature dependencies. */
10016 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10017 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10018 AARCH64_ARCH_NONE
},
10019 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10020 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10021 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10022 AARCH64_ARCH_NONE
},
10023 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10024 AARCH64_ARCH_NONE
},
10025 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10026 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10027 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10028 AARCH64_ARCH_NONE
},
10029 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10030 AARCH64_ARCH_NONE
},
10031 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10032 AARCH64_ARCH_NONE
},
10033 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10034 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10035 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10036 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10037 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10038 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10039 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10040 AARCH64_ARCH_NONE
},
10041 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10042 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10043 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10044 AARCH64_ARCH_NONE
},
10045 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10046 AARCH64_FEATURE (AARCH64_FEATURE_F16
10047 | AARCH64_FEATURE_SIMD
, 0)},
10048 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10049 AARCH64_ARCH_NONE
},
10050 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10051 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10052 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10053 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10054 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10055 AARCH64_ARCH_NONE
},
10056 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10057 AARCH64_ARCH_NONE
},
10058 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10059 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10060 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10061 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10062 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10063 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10064 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10065 AARCH64_ARCH_NONE
},
10066 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10067 AARCH64_ARCH_NONE
},
10068 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10069 AARCH64_ARCH_NONE
},
10070 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10071 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10072 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10073 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10074 | AARCH64_FEATURE_SM4
, 0)},
10075 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10076 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10077 | AARCH64_FEATURE_AES
, 0)},
10078 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10079 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10080 | AARCH64_FEATURE_SHA3
, 0)},
10081 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10082 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10083 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10084 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10085 | AARCH64_FEATURE_BFLOAT16
, 0)},
10086 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10087 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10088 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10089 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10090 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10091 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10092 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10093 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10094 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10095 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10096 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10097 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10098 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10099 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10100 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10101 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10102 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10103 AARCH64_ARCH_NONE
},
10104 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10105 AARCH64_ARCH_NONE
},
10106 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10107 AARCH64_ARCH_NONE
},
10108 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10109 AARCH64_ARCH_NONE
},
10110 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10111 AARCH64_ARCH_NONE
},
10112 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10113 AARCH64_ARCH_NONE
},
10114 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10117 struct aarch64_long_option_table
10119 const char *option
; /* Substring to match. */
10120 const char *help
; /* Help information. */
10121 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10122 char *deprecated
; /* If non-null, print this message. */
10125 /* Transitive closure of features depending on set. */
10126 static aarch64_feature_set
10127 aarch64_feature_disable_set (aarch64_feature_set set
)
10129 const struct aarch64_option_cpu_value_table
*opt
;
10130 aarch64_feature_set prev
= 0;
10132 while (prev
!= set
) {
10134 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10135 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10136 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10141 /* Transitive closure of dependencies of set. */
10142 static aarch64_feature_set
10143 aarch64_feature_enable_set (aarch64_feature_set set
)
10145 const struct aarch64_option_cpu_value_table
*opt
;
10146 aarch64_feature_set prev
= 0;
10148 while (prev
!= set
) {
10150 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10151 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10152 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10158 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10161 /* We insist on extensions being added before being removed. We achieve
10162 this by using the ADDING_VALUE variable to indicate whether we are
10163 adding an extension (1) or removing it (0) and only allowing it to
10164 change in the order -1 -> 1 -> 0. */
10165 int adding_value
= -1;
10166 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10168 /* Copy the feature set, so that we can modify it. */
10169 *ext_set
= **opt_p
;
10172 while (str
!= NULL
&& *str
!= 0)
10174 const struct aarch64_option_cpu_value_table
*opt
;
10175 const char *ext
= NULL
;
10182 as_bad (_("invalid architectural extension"));
10186 ext
= strchr (++str
, '+');
10190 optlen
= ext
- str
;
10192 optlen
= strlen (str
);
10194 if (optlen
>= 2 && startswith (str
, "no"))
10196 if (adding_value
!= 0)
10201 else if (optlen
> 0)
10203 if (adding_value
== -1)
10205 else if (adding_value
!= 1)
10207 as_bad (_("must specify extensions to add before specifying "
10208 "those to remove"));
10215 as_bad (_("missing architectural extension"));
10219 gas_assert (adding_value
!= -1);
10221 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10222 if (strncmp (opt
->name
, str
, optlen
) == 0)
10224 aarch64_feature_set set
;
10226 /* Add or remove the extension. */
10229 set
= aarch64_feature_enable_set (opt
->value
);
10230 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10234 set
= aarch64_feature_disable_set (opt
->value
);
10235 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10240 if (opt
->name
== NULL
)
10242 as_bad (_("unknown architectural extension `%s'"), str
);
10253 aarch64_parse_cpu (const char *str
)
10255 const struct aarch64_cpu_option_table
*opt
;
10256 const char *ext
= strchr (str
, '+');
10260 optlen
= ext
- str
;
10262 optlen
= strlen (str
);
10266 as_bad (_("missing cpu name `%s'"), str
);
10270 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10271 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10273 mcpu_cpu_opt
= &opt
->value
;
10275 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10280 as_bad (_("unknown cpu `%s'"), str
);
10285 aarch64_parse_arch (const char *str
)
10287 const struct aarch64_arch_option_table
*opt
;
10288 const char *ext
= strchr (str
, '+');
10292 optlen
= ext
- str
;
10294 optlen
= strlen (str
);
10298 as_bad (_("missing architecture name `%s'"), str
);
10302 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10303 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10305 march_cpu_opt
= &opt
->value
;
10307 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10312 as_bad (_("unknown architecture `%s'\n"), str
);
10317 struct aarch64_option_abi_value_table
10320 enum aarch64_abi_type value
;
10323 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10325 {"ilp32", AARCH64_ABI_ILP32
},
10326 {"lp64", AARCH64_ABI_LP64
},
10328 {"llp64", AARCH64_ABI_LLP64
},
10333 aarch64_parse_abi (const char *str
)
10337 if (str
[0] == '\0')
10339 as_bad (_("missing abi name `%s'"), str
);
10343 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10344 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10346 aarch64_abi
= aarch64_abis
[i
].value
;
10350 as_bad (_("unknown abi `%s'\n"), str
);
10354 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10355 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10356 aarch64_parse_abi
, NULL
},
10357 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10358 aarch64_parse_cpu
, NULL
},
10359 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10360 aarch64_parse_arch
, NULL
},
10361 {NULL
, NULL
, 0, NULL
}
10365 md_parse_option (int c
, const char *arg
)
10367 struct aarch64_option_table
*opt
;
10368 struct aarch64_long_option_table
*lopt
;
10374 target_big_endian
= 1;
10380 target_big_endian
= 0;
10385 /* Listing option. Just ignore these, we don't support additional
10390 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10392 if (c
== opt
->option
[0]
10393 && ((arg
== NULL
&& opt
->option
[1] == 0)
10394 || streq (arg
, opt
->option
+ 1)))
10396 /* If the option is deprecated, tell the user. */
10397 if (opt
->deprecated
!= NULL
)
10398 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10399 arg
? arg
: "", _(opt
->deprecated
));
10401 if (opt
->var
!= NULL
)
10402 *opt
->var
= opt
->value
;
10408 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10410 /* These options are expected to have an argument. */
10411 if (c
== lopt
->option
[0]
10413 && startswith (arg
, lopt
->option
+ 1))
10415 /* If the option is deprecated, tell the user. */
10416 if (lopt
->deprecated
!= NULL
)
10417 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10418 _(lopt
->deprecated
));
10420 /* Call the sup-option parser. */
10421 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10432 md_show_usage (FILE * fp
)
10434 struct aarch64_option_table
*opt
;
10435 struct aarch64_long_option_table
*lopt
;
10437 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10439 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10440 if (opt
->help
!= NULL
)
10441 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10443 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10444 if (lopt
->help
!= NULL
)
10445 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10449 -EB assemble code for a big-endian cpu\n"));
10454 -EL assemble code for a little-endian cpu\n"));
10458 /* Parse a .cpu directive. */
10461 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10463 const struct aarch64_cpu_option_table
*opt
;
10469 name
= input_line_pointer
;
10470 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10471 saved_char
= *input_line_pointer
;
10472 *input_line_pointer
= 0;
10474 ext
= strchr (name
, '+');
10477 optlen
= ext
- name
;
10479 optlen
= strlen (name
);
10481 /* Skip the first "all" entry. */
10482 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10483 if (strlen (opt
->name
) == optlen
10484 && strncmp (name
, opt
->name
, optlen
) == 0)
10486 mcpu_cpu_opt
= &opt
->value
;
10488 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10491 cpu_variant
= *mcpu_cpu_opt
;
10493 *input_line_pointer
= saved_char
;
10494 demand_empty_rest_of_line ();
10497 as_bad (_("unknown cpu `%s'"), name
);
10498 *input_line_pointer
= saved_char
;
10499 ignore_rest_of_line ();
10503 /* Parse a .arch directive. */
10506 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10508 const struct aarch64_arch_option_table
*opt
;
10514 name
= input_line_pointer
;
10515 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10516 saved_char
= *input_line_pointer
;
10517 *input_line_pointer
= 0;
10519 ext
= strchr (name
, '+');
10522 optlen
= ext
- name
;
10524 optlen
= strlen (name
);
10526 /* Skip the first "all" entry. */
10527 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10528 if (strlen (opt
->name
) == optlen
10529 && strncmp (name
, opt
->name
, optlen
) == 0)
10531 mcpu_cpu_opt
= &opt
->value
;
10533 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10536 cpu_variant
= *mcpu_cpu_opt
;
10538 *input_line_pointer
= saved_char
;
10539 demand_empty_rest_of_line ();
10543 as_bad (_("unknown architecture `%s'\n"), name
);
10544 *input_line_pointer
= saved_char
;
10545 ignore_rest_of_line ();
10548 /* Parse a .arch_extension directive. */
10551 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10554 char *ext
= input_line_pointer
;
10556 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10557 saved_char
= *input_line_pointer
;
10558 *input_line_pointer
= 0;
10560 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10563 cpu_variant
= *mcpu_cpu_opt
;
10565 *input_line_pointer
= saved_char
;
10566 demand_empty_rest_of_line ();
10569 /* Copy symbol information. */
10572 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10574 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10578 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10579 This is needed so AArch64 specific st_other values can be independently
10580 specified for an IFUNC resolver (that is called by the dynamic linker)
10581 and the symbol it resolves (aliased to the resolver). In particular,
10582 if a function symbol has special st_other value set via directives,
10583 then attaching an IFUNC resolver to that symbol should not override
10584 the st_other setting. Requiring the directive on the IFUNC resolver
10585 symbol would be unexpected and problematic in C code, where the two
10586 symbols appear as two independent function declarations. */
10589 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10591 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10592 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10593 /* If size is unset, copy size from src. Because we don't track whether
10594 .size has been used, we can't differentiate .size dest, 0 from the case
10595 where dest's size is unset. */
10596 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10600 destelf
->size
= XNEW (expressionS
);
10601 *destelf
->size
= *srcelf
->size
;
10603 S_SET_SIZE (dest
, S_GET_SIZE (src
));