1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 #include "safe-ctype.h"
29 #include "opcode/arc.h"
30 #include "opcode/arc-attrs.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 #ifndef TARGET_WITH_CPU
52 #define TARGET_WITH_CPU "arc700"
53 #endif /* TARGET_WITH_CPU */
55 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57 #define streq(a, b) (strcmp (a, b) == 0)
59 /* Enum used to enumerate the relaxable ins operands. */
64 REGISTER_S
, /* Register for short instruction(s). */
65 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
66 REGISTER_DUP
, /* Duplication of previous operand of type register. */
100 #define regno(x) ((x) & 0x3F)
101 #define is_ir_num(x) (((x) & ~0x3F) == 0)
102 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103 #define is_spfp_p(op) (((sc) == SPX))
104 #define is_dpfp_p(op) (((sc) == DPX))
105 #define is_fpuda_p(op) (((sc) == DPA))
106 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
118 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
119 #define is_nps400_p(op) (((sc) == NPS400))
121 /* Generic assembler global variables which must be defined by all
124 /* Characters which always start a comment. */
125 const char comment_chars
[] = "#;";
127 /* Characters which start a comment at the beginning of a line. */
128 const char line_comment_chars
[] = "#";
130 /* Characters which may be used to separate multiple commands on a
132 const char line_separator_chars
[] = "`";
134 /* Characters which are used to indicate an exponent in a floating
136 const char EXP_CHARS
[] = "eE";
138 /* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
140 const char FLT_CHARS
[] = "rRsSfFdD";
143 extern int target_big_endian
;
144 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
145 static int byte_order
= DEFAULT_BYTE_ORDER
;
147 /* Arc extension section. */
148 static segT arcext_section
;
150 /* By default relaxation is disabled. */
151 static int relaxation_state
= 0;
153 extern int arc_get_mach (char *);
155 /* Forward declarations. */
156 static void arc_lcomm (int);
157 static void arc_option (int);
158 static void arc_extra_reloc (int);
159 static void arc_extinsn (int);
160 static void arc_extcorereg (int);
161 static void arc_attribute (int);
163 const pseudo_typeS md_pseudo_table
[] =
165 /* Make sure that .word is 32 bits. */
168 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm
, 0 },
170 { "lcommon", arc_lcomm
, 0 },
171 { "cpu", arc_option
, 0 },
173 { "arc_attribute", arc_attribute
, 0 },
174 { "extinstruction", arc_extinsn
, 0 },
175 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
176 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
177 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
179 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
180 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
185 const char *md_shortopts
= "";
189 OPTION_EB
= OPTION_MD_BASE
,
207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
231 struct option md_longopts
[] =
233 { "EB", no_argument
, NULL
, OPTION_EB
},
234 { "EL", no_argument
, NULL
, OPTION_EL
},
235 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
236 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
237 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
238 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
239 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
240 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
241 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
242 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
243 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
244 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
245 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
247 /* Floating point options */
248 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
249 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
250 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
251 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
252 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
253 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
254 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
255 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
256 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
257 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
258 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
263 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
264 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
265 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
266 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
267 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
268 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
269 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
270 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
271 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
272 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
273 { "mea", no_argument
, NULL
, OPTION_EA
},
274 { "mEA", no_argument
, NULL
, OPTION_EA
},
275 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
276 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
277 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
278 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
279 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
280 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
281 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
282 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
283 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
284 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
285 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
286 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
287 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
288 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
289 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
291 { NULL
, no_argument
, NULL
, 0 }
294 size_t md_longopts_size
= sizeof (md_longopts
);
296 /* Local data and data types. */
298 /* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300 typedef int extended_bfd_reloc_code_real_type
;
306 extended_bfd_reloc_code_real_type reloc
;
308 /* index into arc_operands. */
309 unsigned int opindex
;
311 /* PC-relative, used by internals fixups. */
314 /* TRUE if this fixup is for LIMM operand. */
320 unsigned long long int insn
;
322 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
324 unsigned int len
; /* Length of instruction in bytes. */
325 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
327 bfd_boolean relax
; /* Boolean value: TRUE if needs
331 /* Structure to hold any last two instructions. */
332 static struct arc_last_insn
334 /* Saved instruction opcode. */
335 const struct arc_opcode
*opcode
;
337 /* Boolean value: TRUE if current insn is short. */
338 bfd_boolean has_limm
;
340 /* Boolean value: TRUE if current insn has delay slot. */
341 bfd_boolean has_delay_slot
;
344 /* Extension instruction suffix classes. */
352 static const attributes_t suffixclass
[] =
354 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
355 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
356 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
359 /* Extension instruction syntax classes. */
360 static const attributes_t syntaxclass
[] =
362 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
363 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
364 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
365 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
368 /* Extension instruction syntax classes modifiers. */
369 static const attributes_t syntaxclassmod
[] =
371 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
372 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
375 /* Extension register type. */
383 /* A structure to hold the additional conditional codes. */
386 struct arc_flag_operand
*arc_ext_condcode
;
388 } ext_condcode
= { NULL
, 0 };
390 /* Structure to hold an entry in ARC_OPCODE_HASH. */
391 struct arc_opcode_hash_entry
393 /* The number of pointers in the OPCODE list. */
396 /* Points to a list of opcode pointers. */
397 const struct arc_opcode
**opcode
;
400 /* Structure used for iterating through an arc_opcode_hash_entry. */
401 struct arc_opcode_hash_entry_iterator
403 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
406 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
407 returned by this iterator. */
408 const struct arc_opcode
*opcode
;
411 /* Forward declaration. */
412 static void assemble_insn
413 (const struct arc_opcode
*, const expressionS
*, int,
414 const struct arc_flags
*, int, struct arc_insn
*);
416 /* The selection of the machine type can come from different sources. This
417 enum is used to track how the selection was made in order to perform
419 enum mach_selection_type
422 MACH_SELECTION_FROM_DEFAULT
,
423 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
424 MACH_SELECTION_FROM_COMMAND_LINE
427 /* How the current machine type was selected. */
428 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
430 /* The hash table of instruction opcodes. */
431 static htab_t arc_opcode_hash
;
433 /* The hash table of register symbols. */
434 static htab_t arc_reg_hash
;
436 /* The hash table of aux register symbols. */
437 static htab_t arc_aux_hash
;
439 /* The hash table of address types. */
440 static htab_t arc_addrtype_hash
;
442 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
444 E_ARC_MACH_ARC600, EXTRA}
445 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
447 E_ARC_MACH_ARC700, EXTRA}
448 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
449 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
450 EF_ARC_CPU_ARCV2EM, EXTRA}
451 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
452 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
453 EF_ARC_CPU_ARCV2HS, EXTRA}
454 #define ARC_CPU_TYPE_NONE \
457 /* A table of CPU names and opcode sets. */
458 static const struct cpu_type
468 #include "elf/arc-cpu.def"
471 /* Information about the cpu/variant we're assembling for. */
472 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
474 /* TRUE if current assembly code uses RF16 only registers. */
475 static bfd_boolean rf16_only
= TRUE
;
478 static unsigned mpy_option
= 0;
481 static unsigned pic_option
= 0;
483 /* Use small data. */
484 static unsigned sda_option
= 0;
487 static unsigned tls_option
= 0;
489 /* Command line given features. */
490 static unsigned cl_features
= 0;
492 /* Used by the arc_reloc_op table. Order is important. */
493 #define O_gotoff O_md1 /* @gotoff relocation. */
494 #define O_gotpc O_md2 /* @gotpc relocation. */
495 #define O_plt O_md3 /* @plt relocation. */
496 #define O_sda O_md4 /* @sda relocation. */
497 #define O_pcl O_md5 /* @pcl relocation. */
498 #define O_tlsgd O_md6 /* @tlsgd relocation. */
499 #define O_tlsie O_md7 /* @tlsie relocation. */
500 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
501 #define O_tpoff O_md9 /* @tpoff relocation. */
502 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
503 #define O_dtpoff O_md11 /* @dtpoff relocation. */
504 #define O_last O_dtpoff
506 /* Used to define a bracket as operand in tokens. */
507 #define O_bracket O_md32
509 /* Used to define a colon as an operand in tokens. */
510 #define O_colon O_md31
512 /* Used to define address types in nps400. */
513 #define O_addrtype O_md30
515 /* Dummy relocation, to be sorted out. */
516 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
518 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
520 /* A table to map the spelling of a relocation operand into an appropriate
521 bfd_reloc_code_real_type type. The table is assumed to be ordered such
522 that op-O_literal indexes into it. */
523 #define ARC_RELOC_TABLE(op) \
524 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
526 : (int) (op) - (int) O_gotoff) ])
528 #define DEF(NAME, RELOC, REQ) \
529 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
531 static const struct arc_reloc_op_tag
533 /* String to lookup. */
535 /* Size of the string. */
537 /* Which operator to use. */
539 extended_bfd_reloc_code_real_type reloc
;
540 /* Allows complex relocation expression like identifier@reloc +
542 unsigned int complex_expr
: 1;
546 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
547 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
548 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
549 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
550 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
551 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
552 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
553 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
554 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
555 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
556 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
559 static const int arc_num_reloc_op
560 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
562 /* Structure for relaxable instruction that have to be swapped with a
563 smaller alternative instruction. */
564 struct arc_relaxable_ins
566 /* Mnemonic that should be checked. */
567 const char *mnemonic_r
;
569 /* Operands that should be checked.
570 Indexes of operands from operand array. */
571 enum rlx_operand_type operands
[6];
573 /* Flags that should be checked. */
574 unsigned flag_classes
[5];
576 /* Mnemonic (smaller) alternative to be used later for relaxation. */
577 const char *mnemonic_alt
;
579 /* Index of operand that generic relaxation has to check. */
582 /* Base subtype index used. */
583 enum arc_rlx_types subtype
;
586 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
587 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
588 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
592 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
593 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
594 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
599 /* ARC relaxation table. */
600 const relax_typeS md_relax_table
[] =
607 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
608 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
612 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
613 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
618 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
622 /* LD_S a, [b, u7] ->
623 LD<zz><.x><.aa><.di> a, [b, s9] ->
624 LD<zz><.x><.aa><.di> a, [b, limm] */
625 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
626 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
627 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
632 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
633 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
638 SUB<.f> a, b, limm. */
639 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
640 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
641 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
643 /* MPY<.f> a, b, u6 ->
644 MPY<.f> a, b, limm. */
645 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
646 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
648 /* MOV<.f><.cc> b, u6 ->
649 MOV<.f><.cc> b, limm. */
650 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
651 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
653 /* ADD<.f><.cc> b, b, u6 ->
654 ADD<.f><.cc> b, b, limm. */
655 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
656 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
659 /* Order of this table's entries matters! */
660 const struct arc_relaxable_ins arc_relaxable_insns
[] =
662 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
663 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
664 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
665 2, ARC_RLX_ADD_RRU6
},
666 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
668 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
670 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
671 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
672 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
673 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
674 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
675 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
676 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
677 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
679 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
681 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
685 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 symbolS
* GOT_symbol
= 0;
690 /* Set to TRUE when we assemble instructions. */
691 static bfd_boolean assembling_insn
= FALSE
;
693 /* List with attributes set explicitly. */
694 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
696 /* Functions implementation. */
698 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
699 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
700 are no matching entries in ARC_OPCODE_HASH. */
702 static const struct arc_opcode_hash_entry
*
703 arc_find_opcode (const char *name
)
705 const struct arc_opcode_hash_entry
*entry
;
707 entry
= str_hash_find (arc_opcode_hash
, name
);
711 /* Initialise the iterator ITER. */
714 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
720 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
721 calls to this function. Return NULL when all ARC_OPCODE entries have
724 static const struct arc_opcode
*
725 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
726 struct arc_opcode_hash_entry_iterator
*iter
)
728 if (iter
->opcode
== NULL
&& iter
->index
== 0)
730 gas_assert (entry
->count
> 0);
731 iter
->opcode
= entry
->opcode
[iter
->index
];
733 else if (iter
->opcode
!= NULL
)
735 const char *old_name
= iter
->opcode
->name
;
738 if (iter
->opcode
->name
== NULL
739 || strcmp (old_name
, iter
->opcode
->name
) != 0)
742 if (iter
->index
== entry
->count
)
745 iter
->opcode
= entry
->opcode
[iter
->index
];
752 /* Insert an opcode into opcode hash structure. */
755 arc_insert_opcode (const struct arc_opcode
*opcode
)
758 struct arc_opcode_hash_entry
*entry
;
761 entry
= str_hash_find (arc_opcode_hash
, name
);
764 entry
= XNEW (struct arc_opcode_hash_entry
);
766 entry
->opcode
= NULL
;
768 str_hash_insert (arc_opcode_hash
, name
, (void *) entry
);
771 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
774 if (entry
->opcode
== NULL
)
775 as_fatal (_("Virtual memory exhausted"));
777 entry
->opcode
[entry
->count
] = opcode
;
782 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
783 value, is encoded as 'middle-endian' for a little-endian target. This
784 function is used for regular 4, 6, and 8 byte instructions as well. */
787 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
792 md_number_to_chars (buf
, val
, n
);
795 md_number_to_chars (buf
, (val
& 0xffff00000000ull
) >> 32, 2);
796 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
799 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
800 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
803 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000ull
) >> 32, 4);
804 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
811 /* Check if a feature is allowed for a specific CPU. */
814 arc_check_feature (void)
818 if (!selected_cpu
.features
819 || !selected_cpu
.name
)
822 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
823 if ((selected_cpu
.features
& feature_list
[i
].feature
)
824 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
825 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
828 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
829 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
830 as_bad(_("conflicting ISA extension attributes."));
833 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
834 the relevant static global variables. Parameter SEL describes where
835 this selection originated from. */
838 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
841 static struct cpu_type old_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
843 /* We should only set a default if we've not made a selection from some
845 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
846 || mach_selection_mode
== MACH_SELECTION_NONE
);
848 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
849 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
850 as_bad (_("Multiple .cpu directives found"));
852 /* Look for a matching entry in CPU_TYPES array. */
853 for (i
= 0; cpu_types
[i
].name
; ++i
)
855 if (!strcasecmp (cpu_types
[i
].name
, arg
))
857 /* If a previous selection was made on the command line, then we
858 allow later selections on the command line to override earlier
859 ones. However, a selection from a '.cpu NAME' directive must
860 match the command line selection, or we give a warning. */
861 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
863 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
864 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
865 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
866 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
868 as_warn (_("Command-line value overrides \".cpu\" directive"));
872 /* Initialise static global data about selected machine type. */
873 selected_cpu
.flags
= cpu_types
[i
].flags
;
874 selected_cpu
.name
= cpu_types
[i
].name
;
875 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
876 selected_cpu
.mach
= cpu_types
[i
].mach
;
877 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
878 | cpu_types
[i
].eflags
);
883 if (!cpu_types
[i
].name
)
884 as_fatal (_("unknown architecture: %s\n"), arg
);
886 /* Check if set features are compatible with the chosen CPU. */
887 arc_check_feature ();
889 /* If we change the CPU, we need to re-init the bfd. */
890 if (mach_selection_mode
!= MACH_SELECTION_NONE
891 && (old_cpu
.mach
!= selected_cpu
.mach
))
893 bfd_find_target (arc_target_format
, stdoutput
);
894 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
895 as_warn (_("Could not set architecture and machine"));
898 mach_selection_mode
= sel
;
899 old_cpu
= selected_cpu
;
902 /* Here ends all the ARCompact extension instruction assembling
906 arc_extra_reloc (int r_type
)
909 symbolS
*sym
, *lab
= NULL
;
911 if (*input_line_pointer
== '@')
912 input_line_pointer
++;
913 c
= get_symbol_name (&sym_name
);
914 sym
= symbol_find_or_make (sym_name
);
915 restore_line_pointer (c
);
916 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
918 ++input_line_pointer
;
920 c
= get_symbol_name (&lab_name
);
921 lab
= symbol_find_or_make (lab_name
);
922 restore_line_pointer (c
);
925 /* These relocations exist as a mechanism for the compiler to tell the
926 linker how to patch the code if the tls model is optimised. However,
927 the relocation itself does not require any space within the assembler
928 fragment, and so we pass a size of 0.
930 The lines that generate these relocations look like this:
932 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
934 The '.tls_gd_ld @.tdata' is processed first and generates the
935 additional relocation, while the 'bl __tls_get_addr@plt' is processed
936 second and generates the additional branch.
938 It is possible that the additional relocation generated by the
939 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
940 while the 'bl __tls_get_addr@plt' will be generated as the first thing
941 in the next fragment. This will be fine; both relocations will still
942 appear to be at the same address in the generated object file.
943 However, this only works as the additional relocation is generated
944 with size of 0 bytes. */
946 = fix_new (frag_now
, /* Which frag? */
947 frag_now_fix (), /* Where in that frag? */
948 0, /* size: 1, 2, or 4 usually. */
949 sym
, /* X_add_symbol. */
950 0, /* X_add_number. */
951 FALSE
, /* TRUE if PC-relative relocation. */
952 r_type
/* Relocation type. */);
953 fixP
->fx_subsy
= lab
;
957 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
958 symbolS
*symbolP
, addressT size
)
963 if (*input_line_pointer
== ',')
965 align
= parse_align (1);
967 if (align
== (addressT
) -1)
982 bss_alloc (symbolP
, size
, align
);
983 S_CLEAR_EXTERNAL (symbolP
);
989 arc_lcomm (int ignore
)
991 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
994 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
997 /* Select the cpu we're assembling for. */
1000 arc_option (int ignore ATTRIBUTE_UNUSED
)
1004 const char *cpu_name
;
1006 c
= get_symbol_name (&cpu
);
1009 if ((!strcmp ("ARC600", cpu
))
1010 || (!strcmp ("ARC601", cpu
))
1011 || (!strcmp ("A6", cpu
)))
1012 cpu_name
= "arc600";
1013 else if ((!strcmp ("ARC700", cpu
))
1014 || (!strcmp ("A7", cpu
)))
1015 cpu_name
= "arc700";
1016 else if (!strcmp ("EM", cpu
))
1018 else if (!strcmp ("HS", cpu
))
1020 else if (!strcmp ("NPS400", cpu
))
1021 cpu_name
= "nps400";
1023 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1025 restore_line_pointer (c
);
1026 demand_empty_rest_of_line ();
1029 /* Smartly print an expression. */
1032 debug_exp (expressionS
*t
)
1034 const char *name ATTRIBUTE_UNUSED
;
1035 const char *namemd ATTRIBUTE_UNUSED
;
1037 pr_debug ("debug_exp: ");
1041 default: name
= "unknown"; break;
1042 case O_illegal
: name
= "O_illegal"; break;
1043 case O_absent
: name
= "O_absent"; break;
1044 case O_constant
: name
= "O_constant"; break;
1045 case O_symbol
: name
= "O_symbol"; break;
1046 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1047 case O_register
: name
= "O_register"; break;
1048 case O_big
: name
= "O_big"; break;
1049 case O_uminus
: name
= "O_uminus"; break;
1050 case O_bit_not
: name
= "O_bit_not"; break;
1051 case O_logical_not
: name
= "O_logical_not"; break;
1052 case O_multiply
: name
= "O_multiply"; break;
1053 case O_divide
: name
= "O_divide"; break;
1054 case O_modulus
: name
= "O_modulus"; break;
1055 case O_left_shift
: name
= "O_left_shift"; break;
1056 case O_right_shift
: name
= "O_right_shift"; break;
1057 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1058 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1059 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1060 case O_bit_and
: name
= "O_bit_and"; break;
1061 case O_add
: name
= "O_add"; break;
1062 case O_subtract
: name
= "O_subtract"; break;
1063 case O_eq
: name
= "O_eq"; break;
1064 case O_ne
: name
= "O_ne"; break;
1065 case O_lt
: name
= "O_lt"; break;
1066 case O_le
: name
= "O_le"; break;
1067 case O_ge
: name
= "O_ge"; break;
1068 case O_gt
: name
= "O_gt"; break;
1069 case O_logical_and
: name
= "O_logical_and"; break;
1070 case O_logical_or
: name
= "O_logical_or"; break;
1071 case O_index
: name
= "O_index"; break;
1072 case O_bracket
: name
= "O_bracket"; break;
1073 case O_colon
: name
= "O_colon"; break;
1074 case O_addrtype
: name
= "O_addrtype"; break;
1079 default: namemd
= "unknown"; break;
1080 case O_gotoff
: namemd
= "O_gotoff"; break;
1081 case O_gotpc
: namemd
= "O_gotpc"; break;
1082 case O_plt
: namemd
= "O_plt"; break;
1083 case O_sda
: namemd
= "O_sda"; break;
1084 case O_pcl
: namemd
= "O_pcl"; break;
1085 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1086 case O_tlsie
: namemd
= "O_tlsie"; break;
1087 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1088 case O_tpoff
: namemd
= "O_tpoff"; break;
1089 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1090 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1093 pr_debug ("%s (%s, %s, %d, %s)", name
,
1094 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1095 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1096 (int) t
->X_add_number
,
1097 (t
->X_md
) ? namemd
: "--");
1102 /* Helper for parsing an argument, used for sorting out the relocation
1106 parse_reloc_symbol (expressionS
*resultP
)
1108 char *reloc_name
, c
, *sym_name
;
1111 const struct arc_reloc_op_tag
*r
;
1115 /* A relocation operand has the following form
1116 @identifier@relocation_type. The identifier is already in
1118 if (resultP
->X_op
!= O_symbol
)
1120 as_bad (_("No valid label relocation operand"));
1121 resultP
->X_op
= O_illegal
;
1125 /* Parse @relocation_type. */
1126 input_line_pointer
++;
1127 c
= get_symbol_name (&reloc_name
);
1128 len
= input_line_pointer
- reloc_name
;
1131 as_bad (_("No relocation operand"));
1132 resultP
->X_op
= O_illegal
;
1136 /* Go through known relocation and try to find a match. */
1137 r
= &arc_reloc_op
[0];
1138 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1139 if (len
== r
->length
1140 && memcmp (reloc_name
, r
->name
, len
) == 0)
1144 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1145 resultP
->X_op
= O_illegal
;
1149 *input_line_pointer
= c
;
1150 SKIP_WHITESPACE_AFTER_NAME ();
1151 /* Extra check for TLS: base. */
1152 if (*input_line_pointer
== '@')
1154 if (resultP
->X_op_symbol
!= NULL
1155 || resultP
->X_op
!= O_symbol
)
1157 as_bad (_("Unable to parse TLS base: %s"),
1158 input_line_pointer
);
1159 resultP
->X_op
= O_illegal
;
1162 input_line_pointer
++;
1163 c
= get_symbol_name (&sym_name
);
1164 base
= symbol_find_or_make (sym_name
);
1165 resultP
->X_op
= O_subtract
;
1166 resultP
->X_op_symbol
= base
;
1167 restore_line_pointer (c
);
1168 right
.X_add_number
= 0;
1171 if ((*input_line_pointer
!= '+')
1172 && (*input_line_pointer
!= '-'))
1173 right
.X_add_number
= 0;
1176 /* Parse the constant of a complex relocation expression
1177 like @identifier@reloc +/- const. */
1178 if (! r
->complex_expr
)
1180 as_bad (_("@%s is not a complex relocation."), r
->name
);
1181 resultP
->X_op
= O_illegal
;
1184 expression (&right
);
1185 if (right
.X_op
!= O_constant
)
1187 as_bad (_("Bad expression: @%s + %s."),
1188 r
->name
, input_line_pointer
);
1189 resultP
->X_op
= O_illegal
;
1194 resultP
->X_md
= r
->op
;
1195 resultP
->X_add_number
= right
.X_add_number
;
1198 /* Parse the arguments to an opcode. */
1201 tokenize_arguments (char *str
,
1205 char *old_input_line_pointer
;
1206 bfd_boolean saw_comma
= FALSE
;
1207 bfd_boolean saw_arg
= FALSE
;
1211 memset (tok
, 0, sizeof (*tok
) * ntok
);
1213 /* Save and restore input_line_pointer around this function. */
1214 old_input_line_pointer
= input_line_pointer
;
1215 input_line_pointer
= str
;
1217 while (*input_line_pointer
)
1220 switch (*input_line_pointer
)
1226 input_line_pointer
++;
1227 if (saw_comma
|| !saw_arg
)
1234 ++input_line_pointer
;
1236 if (!saw_arg
|| num_args
== ntok
)
1238 tok
->X_op
= O_bracket
;
1245 input_line_pointer
++;
1246 if (brk_lvl
|| num_args
== ntok
)
1249 tok
->X_op
= O_bracket
;
1255 input_line_pointer
++;
1256 if (!saw_arg
|| num_args
== ntok
)
1258 tok
->X_op
= O_colon
;
1265 /* We have labels, function names and relocations, all
1266 starting with @ symbol. Sort them out. */
1267 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1271 input_line_pointer
++;
1272 tok
->X_op
= O_symbol
;
1273 tok
->X_md
= O_absent
;
1276 if (*input_line_pointer
== '@')
1277 parse_reloc_symbol (tok
);
1281 if (tok
->X_op
== O_illegal
1282 || tok
->X_op
== O_absent
1283 || num_args
== ntok
)
1293 /* Can be a register. */
1294 ++input_line_pointer
;
1298 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1301 tok
->X_op
= O_absent
;
1302 tok
->X_md
= O_absent
;
1305 /* Legacy: There are cases when we have
1306 identifier@relocation_type, if it is the case parse the
1307 relocation type as well. */
1308 if (*input_line_pointer
== '@')
1309 parse_reloc_symbol (tok
);
1313 if (tok
->X_op
== O_illegal
1314 || tok
->X_op
== O_absent
1315 || num_args
== ntok
)
1327 if (saw_comma
|| brk_lvl
)
1329 input_line_pointer
= old_input_line_pointer
;
1335 as_bad (_("Brackets in operand field incorrect"));
1337 as_bad (_("extra comma"));
1339 as_bad (_("missing argument"));
1341 as_bad (_("missing comma or colon"));
1342 input_line_pointer
= old_input_line_pointer
;
1346 /* Parse the flags to a structure. */
1349 tokenize_flags (const char *str
,
1350 struct arc_flags flags
[],
1353 char *old_input_line_pointer
;
1354 bfd_boolean saw_flg
= FALSE
;
1355 bfd_boolean saw_dot
= FALSE
;
1359 memset (flags
, 0, sizeof (*flags
) * nflg
);
1361 /* Save and restore input_line_pointer around this function. */
1362 old_input_line_pointer
= input_line_pointer
;
1363 input_line_pointer
= (char *) str
;
1365 while (*input_line_pointer
)
1367 switch (*input_line_pointer
)
1374 input_line_pointer
++;
1382 if (saw_flg
&& !saw_dot
)
1385 if (num_flags
>= nflg
)
1388 flgnamelen
= strspn (input_line_pointer
,
1389 "abcdefghijklmnopqrstuvwxyz0123456789");
1390 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1393 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1395 input_line_pointer
+= flgnamelen
;
1405 input_line_pointer
= old_input_line_pointer
;
1410 as_bad (_("extra dot"));
1412 as_bad (_("unrecognized flag"));
1414 as_bad (_("failed to parse flags"));
1415 input_line_pointer
= old_input_line_pointer
;
1419 /* Apply the fixups in order. */
1422 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1426 for (i
= 0; i
< insn
->nfixups
; i
++)
1428 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1429 int size
, pcrel
, offset
= 0;
1431 /* FIXME! the reloc size is wrong in the BFD file.
1432 When it is fixed please delete me. */
1433 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1438 /* Some fixups are only used internally, thus no howto. */
1439 if ((int) fixup
->reloc
== 0)
1440 as_fatal (_("Unhandled reloc type"));
1442 if ((int) fixup
->reloc
< 0)
1444 /* FIXME! the reloc size is wrong in the BFD file.
1445 When it is fixed please enable me.
1446 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1447 pcrel
= fixup
->pcrel
;
1451 reloc_howto_type
*reloc_howto
=
1452 bfd_reloc_type_lookup (stdoutput
,
1453 (bfd_reloc_code_real_type
) fixup
->reloc
);
1454 gas_assert (reloc_howto
);
1456 /* FIXME! the reloc size is wrong in the BFD file.
1457 When it is fixed please enable me.
1458 size = bfd_get_reloc_size (reloc_howto); */
1459 pcrel
= reloc_howto
->pc_relative
;
1462 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1464 fragP
->fr_file
, fragP
->fr_line
,
1465 (fixup
->reloc
< 0) ? "Internal" :
1466 bfd_get_reloc_code_name (fixup
->reloc
),
1469 fix_new_exp (fragP
, fix
+ offset
,
1470 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1472 /* Check for ZOLs, and update symbol info if any. */
1473 if (LP_INSN (insn
->insn
))
1475 gas_assert (fixup
->exp
.X_add_symbol
);
1476 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1481 /* Actually output an instruction with its fixup. */
1484 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1489 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1490 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1491 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1493 /* Write out the instruction. */
1494 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1496 f
= frag_more (total_len
);
1498 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1501 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1502 dwarf2_emit_insn (total_len
);
1505 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1509 emit_insn1 (struct arc_insn
*insn
)
1511 /* How frag_var's args are currently configured:
1512 - rs_machine_dependent, to dictate it's a relaxation frag.
1513 - FRAG_MAX_GROWTH, maximum size of instruction
1514 - 0, variable size that might grow...unused by generic relaxation.
1515 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1516 - s, opand expression.
1517 - 0, offset but it's unused.
1518 - 0, opcode but it's unused. */
1519 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1520 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1522 if (frag_room () < FRAG_MAX_GROWTH
)
1524 /* Handle differently when frag literal memory is exhausted.
1525 This is used because when there's not enough memory left in
1526 the current frag, a new frag is created and the information
1527 we put into frag_now->tc_frag_data is disregarded. */
1529 struct arc_relax_type relax_info_copy
;
1530 relax_substateT subtype
= frag_now
->fr_subtype
;
1532 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1533 sizeof (struct arc_relax_type
));
1535 frag_wane (frag_now
);
1536 frag_grow (FRAG_MAX_GROWTH
);
1538 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1539 sizeof (struct arc_relax_type
));
1541 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1545 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1546 frag_now
->fr_subtype
, s
, 0, 0);
1550 emit_insn (struct arc_insn
*insn
)
1555 emit_insn0 (insn
, NULL
, FALSE
);
1558 /* Check whether a symbol involves a register. */
1561 contains_register (symbolS
*sym
)
1565 expressionS
*ex
= symbol_get_value_expression (sym
);
1567 return ((O_register
== ex
->X_op
)
1568 && !contains_register (ex
->X_add_symbol
)
1569 && !contains_register (ex
->X_op_symbol
));
1575 /* Returns the register number within a symbol. */
1578 get_register (symbolS
*sym
)
1580 if (!contains_register (sym
))
1583 expressionS
*ex
= symbol_get_value_expression (sym
);
1584 return regno (ex
->X_add_number
);
1587 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1588 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1591 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1598 case BFD_RELOC_ARC_SDA_LDST
:
1599 case BFD_RELOC_ARC_SDA_LDST1
:
1600 case BFD_RELOC_ARC_SDA_LDST2
:
1601 case BFD_RELOC_ARC_SDA16_LD
:
1602 case BFD_RELOC_ARC_SDA16_LD1
:
1603 case BFD_RELOC_ARC_SDA16_LD2
:
1604 case BFD_RELOC_ARC_SDA16_ST2
:
1605 case BFD_RELOC_ARC_SDA32_ME
:
1612 /* Allocates a tok entry. */
1615 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1617 if (ntok
> MAX_INSN_ARGS
- 2)
1618 return 0; /* No space left. */
1621 return 0; /* Incorrect args. */
1623 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1626 return 1; /* Success. */
1627 return allocate_tok (tok
, ntok
- 1, cidx
);
1630 /* Check if an particular ARC feature is enabled. */
1633 check_cpu_feature (insn_subclass_t sc
)
1635 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1638 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1641 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1644 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1647 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1653 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1654 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1655 array and returns TRUE if the flag operands all match, otherwise,
1656 returns FALSE, in which case the FIRST_PFLAG array may have been
1660 parse_opcode_flags (const struct arc_opcode
*opcode
,
1662 struct arc_flags
*first_pflag
)
1665 const unsigned char *flgidx
;
1668 for (i
= 0; i
< nflgs
; i
++)
1669 first_pflag
[i
].flgp
= NULL
;
1671 /* Check the flags. Iterate over the valid flag classes. */
1672 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1674 /* Get a valid flag class. */
1675 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1676 const unsigned *flgopridx
;
1678 struct arc_flags
*pflag
= NULL
;
1680 /* Check if opcode has implicit flag classes. */
1681 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1684 /* Check for extension conditional codes. */
1685 if (ext_condcode
.arc_ext_condcode
1686 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1688 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1691 pflag
= first_pflag
;
1692 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1694 if (!strcmp (pf
->name
, pflag
->name
))
1696 if (pflag
->flgp
!= NULL
)
1709 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1711 const struct arc_flag_operand
*flg_operand
;
1713 pflag
= first_pflag
;
1714 flg_operand
= &arc_flag_operands
[*flgopridx
];
1715 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1717 /* Match against the parsed flags. */
1718 if (!strcmp (flg_operand
->name
, pflag
->name
))
1720 if (pflag
->flgp
!= NULL
)
1723 pflag
->flgp
= flg_operand
;
1725 break; /* goto next flag class and parsed flag. */
1730 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1732 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1736 /* Did I check all the parsed flags? */
1737 return lnflg
? FALSE
: TRUE
;
1741 /* Search forward through all variants of an opcode looking for a
1744 static const struct arc_opcode
*
1745 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1748 struct arc_flags
*first_pflag
,
1751 const char **errmsg
)
1753 const struct arc_opcode
*opcode
;
1754 struct arc_opcode_hash_entry_iterator iter
;
1756 int got_cpu_match
= 0;
1757 expressionS bktok
[MAX_INSN_ARGS
];
1758 int bkntok
, maxerridx
= 0;
1760 const char *tmpmsg
= NULL
;
1762 arc_opcode_hash_entry_iterator_init (&iter
);
1763 memset (&emptyE
, 0, sizeof (emptyE
));
1764 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1767 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1769 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1771 const unsigned char *opidx
;
1773 const expressionS
*t
= &emptyE
;
1775 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1776 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1778 /* Don't match opcodes that don't exist on this
1780 if (!(opcode
->cpu
& selected_cpu
.flags
))
1783 if (!check_cpu_feature (opcode
->subclass
))
1789 /* Check the operands. */
1790 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1792 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1794 /* Only take input from real operands. */
1795 if (ARC_OPERAND_IS_FAKE (operand
))
1798 /* When we expect input, make sure we have it. */
1802 /* Match operand type with expression type. */
1803 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1805 case ARC_OPERAND_ADDRTYPE
:
1809 /* Check to be an address type. */
1810 if (tok
[tokidx
].X_op
!= O_addrtype
)
1813 /* All address type operands need to have an insert
1814 method in order to check that we have the correct
1816 gas_assert (operand
->insert
!= NULL
);
1817 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1824 case ARC_OPERAND_IR
:
1825 /* Check to be a register. */
1826 if ((tok
[tokidx
].X_op
!= O_register
1827 || !is_ir_num (tok
[tokidx
].X_add_number
))
1828 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1831 /* If expect duplicate, make sure it is duplicate. */
1832 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1834 /* Check for duplicate. */
1835 if (t
->X_op
!= O_register
1836 || !is_ir_num (t
->X_add_number
)
1837 || (regno (t
->X_add_number
) !=
1838 regno (tok
[tokidx
].X_add_number
)))
1842 /* Special handling? */
1843 if (operand
->insert
)
1846 (*operand
->insert
)(0,
1847 regno (tok
[tokidx
].X_add_number
),
1851 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1853 /* Missing argument, create one. */
1854 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1857 tok
[tokidx
].X_op
= O_absent
;
1868 case ARC_OPERAND_BRAKET
:
1869 /* Check if bracket is also in opcode table as
1871 if (tok
[tokidx
].X_op
!= O_bracket
)
1875 case ARC_OPERAND_COLON
:
1876 /* Check if colon is also in opcode table as operand. */
1877 if (tok
[tokidx
].X_op
!= O_colon
)
1881 case ARC_OPERAND_LIMM
:
1882 case ARC_OPERAND_SIGNED
:
1883 case ARC_OPERAND_UNSIGNED
:
1884 switch (tok
[tokidx
].X_op
)
1892 /* Got an (too) early bracket, check if it is an
1893 ignored operand. N.B. This procedure works only
1894 when bracket is the last operand! */
1895 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1897 /* Insert the missing operand. */
1898 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1901 tok
[tokidx
].X_op
= O_absent
;
1909 const struct arc_aux_reg
*auxr
;
1911 if (opcode
->insn_class
!= AUXREG
)
1913 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1915 /* For compatibility reasons, an aux register can
1916 be spelled with upper or lower case
1919 for (pp
= tmpp
; *pp
; ++pp
) *pp
= TOLOWER (*pp
);
1921 auxr
= str_hash_find (arc_aux_hash
, tmpp
);
1924 /* We modify the token array here, safe in the
1925 knowledge, that if this was the wrong
1926 choice then the original contents will be
1927 restored from BKTOK. */
1928 tok
[tokidx
].X_op
= O_constant
;
1929 tok
[tokidx
].X_add_number
= auxr
->address
;
1930 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1934 if (tok
[tokidx
].X_op
!= O_constant
)
1939 /* Check the range. */
1940 if (operand
->bits
!= 32
1941 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1943 offsetT min
, max
, val
;
1944 val
= tok
[tokidx
].X_add_number
;
1946 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1948 max
= (1 << (operand
->bits
- 1)) - 1;
1949 min
= -(1 << (operand
->bits
- 1));
1953 max
= (1 << operand
->bits
) - 1;
1957 if (val
< min
|| val
> max
)
1959 tmpmsg
= _("immediate is out of bounds");
1963 /* Check alignments. */
1964 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1967 tmpmsg
= _("immediate is not 32bit aligned");
1971 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1974 tmpmsg
= _("immediate is not 16bit aligned");
1978 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1980 if (operand
->insert
)
1983 (*operand
->insert
)(0,
1984 tok
[tokidx
].X_add_number
,
1989 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1995 /* Check if it is register range. */
1996 if ((tok
[tokidx
].X_add_number
== 0)
1997 && contains_register (tok
[tokidx
].X_add_symbol
)
1998 && contains_register (tok
[tokidx
].X_op_symbol
))
2002 regs
= get_register (tok
[tokidx
].X_add_symbol
);
2004 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
2005 if (operand
->insert
)
2008 (*operand
->insert
)(0,
2021 if (operand
->default_reloc
== 0)
2022 goto match_failed
; /* The operand needs relocation. */
2024 /* Relocs requiring long immediate. FIXME! make it
2025 generic and move it to a function. */
2026 switch (tok
[tokidx
].X_md
)
2035 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2039 if (!generic_reloc_p (operand
->default_reloc
))
2047 /* If expect duplicate, make sure it is duplicate. */
2048 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2050 if (t
->X_op
== O_illegal
2051 || t
->X_op
== O_absent
2052 || t
->X_op
== O_register
2053 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2055 tmpmsg
= _("operand is not duplicate of the "
2064 /* Everything else should have been fake. */
2072 /* Setup ready for flag parsing. */
2073 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2075 tmpmsg
= _("flag mismatch");
2080 /* Possible match -- did we use all of our input? */
2087 tmpmsg
= _("too many arguments");
2091 /* Restore the original parameters. */
2092 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2094 if (tokidx
>= maxerridx
2103 *pcpumatch
= got_cpu_match
;
2108 /* Swap operand tokens. */
2111 swap_operand (expressionS
*operand_array
,
2113 unsigned destination
)
2115 expressionS cpy_operand
;
2116 expressionS
*src_operand
;
2117 expressionS
*dst_operand
;
2120 if (source
== destination
)
2123 src_operand
= &operand_array
[source
];
2124 dst_operand
= &operand_array
[destination
];
2125 size
= sizeof (expressionS
);
2127 /* Make copy of operand to swap with and swap. */
2128 memcpy (&cpy_operand
, dst_operand
, size
);
2129 memcpy (dst_operand
, src_operand
, size
);
2130 memcpy (src_operand
, &cpy_operand
, size
);
2133 /* Check if *op matches *tok type.
2134 Returns FALSE if they don't match, TRUE if they match. */
2137 pseudo_operand_match (const expressionS
*tok
,
2138 const struct arc_operand_operation
*op
)
2140 offsetT min
, max
, val
;
2142 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2148 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2150 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2152 val
= tok
->X_add_number
+ op
->count
;
2153 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2155 max
= (1 << (operand_real
->bits
- 1)) - 1;
2156 min
= -(1 << (operand_real
->bits
- 1));
2160 max
= (1 << operand_real
->bits
) - 1;
2163 if (min
<= val
&& val
<= max
)
2169 /* Handle all symbols as long immediates or signed 9. */
2170 if (operand_real
->flags
& ARC_OPERAND_LIMM
2171 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2172 && operand_real
->bits
== 9))
2177 if (operand_real
->flags
& ARC_OPERAND_IR
)
2182 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2193 /* Find pseudo instruction in array. */
2195 static const struct arc_pseudo_insn
*
2196 find_pseudo_insn (const char *opname
,
2198 const expressionS
*tok
)
2200 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2201 const struct arc_operand_operation
*op
;
2205 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2207 pseudo_insn
= &arc_pseudo_insns
[i
];
2208 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2210 op
= pseudo_insn
->operand
;
2211 for (j
= 0; j
< ntok
; ++j
)
2212 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2215 /* Found the right instruction. */
2223 /* Assumes the expressionS *tok is of sufficient size. */
2225 static const struct arc_opcode_hash_entry
*
2226 find_special_case_pseudo (const char *opname
,
2230 struct arc_flags
*pflags
)
2232 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2233 const struct arc_operand_operation
*operand_pseudo
;
2234 const struct arc_operand
*operand_real
;
2236 char construct_operand
[MAX_CONSTR_STR
];
2238 /* Find whether opname is in pseudo instruction array. */
2239 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2241 if (pseudo_insn
== NULL
)
2244 /* Handle flag, Limited to one flag at the moment. */
2245 if (pseudo_insn
->flag_r
!= NULL
)
2246 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2247 MAX_INSN_FLGS
- *nflgs
);
2249 /* Handle operand operations. */
2250 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2252 operand_pseudo
= &pseudo_insn
->operand
[i
];
2253 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2255 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2256 && !operand_pseudo
->needs_insert
)
2259 /* Has to be inserted (i.e. this token does not exist yet). */
2260 if (operand_pseudo
->needs_insert
)
2262 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2264 tok
[i
].X_op
= O_bracket
;
2269 /* Check if operand is a register or constant and handle it
2271 if (operand_real
->flags
& ARC_OPERAND_IR
)
2272 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2273 operand_pseudo
->count
);
2275 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2276 operand_pseudo
->count
);
2278 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2282 else if (operand_pseudo
->count
)
2284 /* Operand number has to be adjusted accordingly (by operand
2286 switch (tok
[i
].X_op
)
2289 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2302 /* Swap operands if necessary. Only supports one swap at the
2304 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2306 operand_pseudo
= &pseudo_insn
->operand
[i
];
2308 if (operand_pseudo
->swap_operand_idx
== i
)
2311 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2313 /* Prevent a swap back later by breaking out. */
2317 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2320 static const struct arc_opcode_hash_entry
*
2321 find_special_case_flag (const char *opname
,
2323 struct arc_flags
*pflags
)
2327 unsigned flag_idx
, flag_arr_idx
;
2328 size_t flaglen
, oplen
;
2329 const struct arc_flag_special
*arc_flag_special_opcode
;
2330 const struct arc_opcode_hash_entry
*entry
;
2332 /* Search for special case instruction. */
2333 for (i
= 0; i
< arc_num_flag_special
; i
++)
2335 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2336 oplen
= strlen (arc_flag_special_opcode
->name
);
2338 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2341 /* Found a potential special case instruction, now test for
2343 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2345 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2347 break; /* End of array, nothing found. */
2349 flagnm
= arc_flag_operands
[flag_idx
].name
;
2350 flaglen
= strlen (flagnm
);
2351 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2353 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2355 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2357 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2358 pflags
[*nflgs
].name
[flaglen
] = '\0';
2367 /* Used to find special case opcode. */
2369 static const struct arc_opcode_hash_entry
*
2370 find_special_case (const char *opname
,
2372 struct arc_flags
*pflags
,
2376 const struct arc_opcode_hash_entry
*entry
;
2378 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2381 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2386 /* Autodetect cpu attribute list. */
2389 autodetect_attributes (const struct arc_opcode
*opcode
,
2390 const expressionS
*tok
,
2398 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2401 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2402 if (opcode
->subclass
== feature_list
[i
].feature
)
2403 selected_cpu
.features
|= feature_list
[i
].feature
;
2405 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2406 if (opcode
->subclass
== mpy_list
[i
].feature
)
2407 mpy_option
= mpy_list
[i
].encoding
;
2409 for (i
= 0; i
< (unsigned) ntok
; i
++)
2411 switch (tok
[i
].X_md
)
2433 switch (tok
[i
].X_op
)
2436 if ((tok
[i
].X_add_number
>= 4 && tok
[i
].X_add_number
<= 9)
2437 || (tok
[i
].X_add_number
>= 16 && tok
[i
].X_add_number
<= 25))
2446 /* Given an opcode name, pre-tockenized set of argumenst and the
2447 opcode flags, take it all the way through emission. */
2450 assemble_tokens (const char *opname
,
2453 struct arc_flags
*pflags
,
2456 bfd_boolean found_something
= FALSE
;
2457 const struct arc_opcode_hash_entry
*entry
;
2459 const char *errmsg
= NULL
;
2461 /* Search opcodes. */
2462 entry
= arc_find_opcode (opname
);
2464 /* Couldn't find opcode conventional way, try special cases. */
2466 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2470 const struct arc_opcode
*opcode
;
2472 pr_debug ("%s:%d: assemble_tokens: %s\n",
2473 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2474 found_something
= TRUE
;
2475 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2476 nflgs
, &cpumatch
, &errmsg
);
2479 struct arc_insn insn
;
2481 autodetect_attributes (opcode
, tok
, ntok
);
2482 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2488 if (found_something
)
2492 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2494 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2496 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2500 as_bad (_("unknown opcode '%s'"), opname
);
2503 /* The public interface to the instruction assembler. */
2506 md_assemble (char *str
)
2509 expressionS tok
[MAX_INSN_ARGS
];
2512 struct arc_flags flags
[MAX_INSN_FLGS
];
2514 /* Split off the opcode. */
2515 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2516 opname
= xmemdup0 (str
, opnamelen
);
2518 /* Signalize we are assembling the instructions. */
2519 assembling_insn
= TRUE
;
2521 /* Tokenize the flags. */
2522 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2524 as_bad (_("syntax error"));
2528 /* Scan up to the end of the mnemonic which must end in space or end
2531 for (; *str
!= '\0'; str
++)
2535 /* Tokenize the rest of the line. */
2536 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2538 as_bad (_("syntax error"));
2542 /* Finish it off. */
2543 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2544 assembling_insn
= FALSE
;
2547 /* Callback to insert a register into the hash table. */
2550 declare_register (const char *name
, int number
)
2552 symbolS
*regS
= symbol_create (name
, reg_section
,
2553 number
, &zero_address_frag
);
2555 str_hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2558 /* Construct symbols for each of the general registers. */
2561 declare_register_set (void)
2564 for (i
= 0; i
< 64; ++i
)
2568 sprintf (name
, "r%d", i
);
2569 declare_register (name
, i
);
2570 if ((i
& 0x01) == 0)
2572 sprintf (name
, "r%dr%d", i
, i
+1);
2573 declare_register (name
, i
);
2578 /* Construct a symbol for an address type. */
2581 declare_addrtype (const char *name
, int number
)
2583 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2584 number
, &zero_address_frag
);
2586 str_hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2587 (void *) addrtypeS
);
2590 /* Port-specific assembler initialization. This function is called
2591 once, at assembler startup time. */
2596 const struct arc_opcode
*opcode
= arc_opcodes
;
2598 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2599 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2601 /* The endianness can be chosen "at the factory". */
2602 target_big_endian
= byte_order
== BIG_ENDIAN
;
2604 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2605 as_warn (_("could not set architecture and machine"));
2607 /* Set elf header flags. */
2608 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2610 /* Set up a hash table for the instructions. */
2611 arc_opcode_hash
= str_htab_create ();
2612 if (arc_opcode_hash
== NULL
)
2613 as_fatal (_("Virtual memory exhausted"));
2615 /* Initialize the hash table with the insns. */
2618 const char *name
= opcode
->name
;
2620 arc_insert_opcode (opcode
);
2622 while (++opcode
&& opcode
->name
2623 && (opcode
->name
== name
2624 || !strcmp (opcode
->name
, name
)))
2626 }while (opcode
->name
);
2628 /* Register declaration. */
2629 arc_reg_hash
= str_htab_create ();
2630 if (arc_reg_hash
== NULL
)
2631 as_fatal (_("Virtual memory exhausted"));
2633 declare_register_set ();
2634 declare_register ("gp", 26);
2635 declare_register ("fp", 27);
2636 declare_register ("sp", 28);
2637 declare_register ("ilink", 29);
2638 declare_register ("ilink1", 29);
2639 declare_register ("ilink2", 30);
2640 declare_register ("blink", 31);
2642 /* XY memory registers. */
2643 declare_register ("x0_u0", 32);
2644 declare_register ("x0_u1", 33);
2645 declare_register ("x1_u0", 34);
2646 declare_register ("x1_u1", 35);
2647 declare_register ("x2_u0", 36);
2648 declare_register ("x2_u1", 37);
2649 declare_register ("x3_u0", 38);
2650 declare_register ("x3_u1", 39);
2651 declare_register ("y0_u0", 40);
2652 declare_register ("y0_u1", 41);
2653 declare_register ("y1_u0", 42);
2654 declare_register ("y1_u1", 43);
2655 declare_register ("y2_u0", 44);
2656 declare_register ("y2_u1", 45);
2657 declare_register ("y3_u0", 46);
2658 declare_register ("y3_u1", 47);
2659 declare_register ("x0_nu", 48);
2660 declare_register ("x1_nu", 49);
2661 declare_register ("x2_nu", 50);
2662 declare_register ("x3_nu", 51);
2663 declare_register ("y0_nu", 52);
2664 declare_register ("y1_nu", 53);
2665 declare_register ("y2_nu", 54);
2666 declare_register ("y3_nu", 55);
2668 declare_register ("mlo", 57);
2669 declare_register ("mmid", 58);
2670 declare_register ("mhi", 59);
2672 declare_register ("acc1", 56);
2673 declare_register ("acc2", 57);
2675 declare_register ("lp_count", 60);
2676 declare_register ("pcl", 63);
2678 /* Initialize the last instructions. */
2679 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2681 /* Aux register declaration. */
2682 arc_aux_hash
= str_htab_create ();
2683 if (arc_aux_hash
== NULL
)
2684 as_fatal (_("Virtual memory exhausted"));
2686 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2688 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2690 if (!(auxr
->cpu
& selected_cpu
.flags
))
2693 if ((auxr
->subclass
!= NONE
)
2694 && !check_cpu_feature (auxr
->subclass
))
2697 str_hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2700 /* Address type declaration. */
2701 arc_addrtype_hash
= str_htab_create ();
2702 if (arc_addrtype_hash
== NULL
)
2703 as_fatal (_("Virtual memory exhausted"));
2705 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2706 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2707 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2708 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2709 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2710 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2711 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2712 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2713 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2714 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2715 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2716 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2717 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2718 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2719 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2720 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2723 /* Write a value out to the object file, using the appropriate
2727 md_number_to_chars (char *buf
,
2731 if (target_big_endian
)
2732 number_to_chars_bigendian (buf
, val
, n
);
2734 number_to_chars_littleendian (buf
, val
, n
);
2737 /* Round up a section size to the appropriate boundary. */
2740 md_section_align (segT segment
,
2743 int align
= bfd_section_alignment (segment
);
2745 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2748 /* The location from which a PC relative jump should be calculated,
2749 given a PC relative reloc. */
2752 md_pcrel_from_section (fixS
*fixP
,
2755 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2757 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2759 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2760 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2761 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2763 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2765 /* The symbol is undefined (or is defined but not in this section).
2766 Let the linker figure it out. */
2770 if ((int) fixP
->fx_r_type
< 0)
2772 /* These are the "internal" relocations. Align them to
2773 32 bit boundary (PCL), for the moment. */
2778 switch (fixP
->fx_r_type
)
2780 case BFD_RELOC_ARC_PC32
:
2781 /* The hardware calculates relative to the start of the
2782 insn, but this relocation is relative to location of the
2783 LIMM, compensate. The base always needs to be
2784 subtracted by 4 as we do not support this type of PCrel
2785 relocation for short instructions. */
2788 case BFD_RELOC_ARC_PLT32
:
2789 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2790 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2791 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2792 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2794 case BFD_RELOC_ARC_S21H_PCREL
:
2795 case BFD_RELOC_ARC_S25H_PCREL
:
2796 case BFD_RELOC_ARC_S13_PCREL
:
2797 case BFD_RELOC_ARC_S21W_PCREL
:
2798 case BFD_RELOC_ARC_S25W_PCREL
:
2802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2803 _("unhandled reloc %s in md_pcrel_from_section"),
2804 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2809 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2810 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2811 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2812 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2813 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2818 /* Given a BFD relocation find the corresponding operand. */
2820 static const struct arc_operand
*
2821 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2825 for (i
= 0; i
< arc_num_operands
; i
++)
2826 if (arc_operands
[i
].default_reloc
== reloc
)
2827 return &arc_operands
[i
];
2831 /* Insert an operand value into an instruction. */
2833 static unsigned long long
2834 insert_operand (unsigned long long insn
,
2835 const struct arc_operand
*operand
,
2840 offsetT min
= 0, max
= 0;
2842 if (operand
->bits
!= 32
2843 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2844 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2846 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2848 max
= (1 << (operand
->bits
- 1)) - 1;
2849 min
= -(1 << (operand
->bits
- 1));
2853 max
= (1 << operand
->bits
) - 1;
2857 if (val
< min
|| val
> max
)
2858 as_bad_value_out_of_range (_("operand"),
2859 val
, min
, max
, file
, line
);
2862 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2863 min
, val
, max
, insn
);
2865 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2867 as_bad_where (file
, line
,
2868 _("Unaligned operand. Needs to be 32bit aligned"));
2870 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2872 as_bad_where (file
, line
,
2873 _("Unaligned operand. Needs to be 16bit aligned"));
2875 if (operand
->insert
)
2877 const char *errmsg
= NULL
;
2879 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2881 as_warn_where (file
, line
, "%s", errmsg
);
2885 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2887 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2889 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2892 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2897 /* Apply a fixup to the object code. At this point all symbol values
2898 should be fully resolved, and we attempt to completely resolve the
2899 reloc. If we can not do that, we determine the correct reloc code
2900 and put it back in the fixup. To indicate that a fixup has been
2901 eliminated, set fixP->fx_done. */
2904 md_apply_fix (fixS
*fixP
,
2908 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2909 valueT value
= *valP
;
2911 symbolS
*fx_addsy
, *fx_subsy
;
2913 segT add_symbol_segment
= absolute_section
;
2914 segT sub_symbol_segment
= absolute_section
;
2915 const struct arc_operand
*operand
= NULL
;
2916 extended_bfd_reloc_code_real_type reloc
;
2918 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2919 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2920 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2921 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2924 fx_addsy
= fixP
->fx_addsy
;
2925 fx_subsy
= fixP
->fx_subsy
;
2930 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2934 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2935 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2936 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2938 resolve_symbol_value (fx_subsy
);
2939 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2941 if (sub_symbol_segment
== absolute_section
)
2943 /* The symbol is really a constant. */
2944 fx_offset
-= S_GET_VALUE (fx_subsy
);
2949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2950 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2951 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2952 segment_name (add_symbol_segment
),
2953 S_GET_NAME (fx_subsy
),
2954 segment_name (sub_symbol_segment
));
2960 && !S_IS_WEAK (fx_addsy
))
2962 if (add_symbol_segment
== seg
2965 value
+= S_GET_VALUE (fx_addsy
);
2966 value
-= md_pcrel_from_section (fixP
, seg
);
2968 fixP
->fx_pcrel
= FALSE
;
2970 else if (add_symbol_segment
== absolute_section
)
2972 value
= fixP
->fx_offset
;
2973 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2975 fixP
->fx_pcrel
= FALSE
;
2980 fixP
->fx_done
= TRUE
;
2985 && ((S_IS_DEFINED (fx_addsy
)
2986 && S_GET_SEGMENT (fx_addsy
) != seg
)
2987 || S_IS_WEAK (fx_addsy
)))
2988 value
+= md_pcrel_from_section (fixP
, seg
);
2990 switch (fixP
->fx_r_type
)
2992 case BFD_RELOC_ARC_32_ME
:
2993 /* This is a pc-relative value in a LIMM. Adjust it to the
2994 address of the instruction not to the address of the
2995 LIMM. Note: it is not any longer valid this affirmation as
2996 the linker consider ARC_PC32 a fixup to entire 64 bit
2998 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
3001 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
3003 case BFD_RELOC_ARC_PC32
:
3004 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
3007 if ((int) fixP
->fx_r_type
< 0)
3008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3009 _("PC relative relocation not allowed for (internal)"
3016 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3017 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
3018 ((int) fixP
->fx_r_type
< 0) ? "Internal":
3019 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
3023 /* Now check for TLS relocations. */
3024 reloc
= fixP
->fx_r_type
;
3027 case BFD_RELOC_ARC_TLS_DTPOFF
:
3028 case BFD_RELOC_ARC_TLS_LE_32
:
3032 case BFD_RELOC_ARC_TLS_GD_GOT
:
3033 case BFD_RELOC_ARC_TLS_IE_GOT
:
3034 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3037 case BFD_RELOC_ARC_TLS_GD_LD
:
3038 gas_assert (!fixP
->fx_offset
);
3041 = (S_GET_VALUE (fixP
->fx_subsy
)
3042 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3043 fixP
->fx_subsy
= NULL
;
3045 case BFD_RELOC_ARC_TLS_GD_CALL
:
3046 /* These two relocs are there just to allow ld to change the tls
3047 model for this symbol, by patching the code. The offset -
3048 and scale, if any - will be installed by the linker. */
3049 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3052 case BFD_RELOC_ARC_TLS_LE_S9
:
3053 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3054 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3066 /* Adjust the value if we have a constant. */
3069 /* For hosts with longs bigger than 32-bits make sure that the top
3070 bits of a 32-bit negative value read in by the parser are set,
3071 so that the correct comparisons are made. */
3072 if (value
& 0x80000000)
3073 value
|= (-1UL << 31);
3075 reloc
= fixP
->fx_r_type
;
3083 case BFD_RELOC_ARC_32_PCREL
:
3084 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3087 case BFD_RELOC_ARC_GOTPC32
:
3088 /* I cannot fix an GOTPC relocation because I need to relax it
3089 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3090 as_bad (_("Unsupported operation on reloc"));
3093 case BFD_RELOC_ARC_TLS_DTPOFF
:
3094 case BFD_RELOC_ARC_TLS_LE_32
:
3095 gas_assert (!fixP
->fx_addsy
);
3096 gas_assert (!fixP
->fx_subsy
);
3099 case BFD_RELOC_ARC_GOTOFF
:
3100 case BFD_RELOC_ARC_32_ME
:
3101 case BFD_RELOC_ARC_PC32
:
3102 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3105 case BFD_RELOC_ARC_PLT32
:
3106 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3109 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3110 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3113 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3114 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3117 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3118 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3121 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3122 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3125 case BFD_RELOC_ARC_S25W_PCREL
:
3126 case BFD_RELOC_ARC_S21W_PCREL
:
3127 case BFD_RELOC_ARC_S21H_PCREL
:
3128 case BFD_RELOC_ARC_S25H_PCREL
:
3129 case BFD_RELOC_ARC_S13_PCREL
:
3131 operand
= find_operand_for_reloc (reloc
);
3132 gas_assert (operand
);
3137 if ((int) fixP
->fx_r_type
>= 0)
3138 as_fatal (_("unhandled relocation type %s"),
3139 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3141 /* The rest of these fixups needs to be completely resolved as
3143 if (fixP
->fx_addsy
!= 0
3144 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3146 _("non-absolute expression in constant field"));
3148 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3149 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3154 if (target_big_endian
)
3156 switch (fixP
->fx_size
)
3159 insn
= bfd_getb32 (fixpos
);
3162 insn
= bfd_getb16 (fixpos
);
3165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3166 _("unknown fixup size"));
3172 switch (fixP
->fx_size
)
3175 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3178 insn
= bfd_getl16 (fixpos
);
3181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3182 _("unknown fixup size"));
3186 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3187 fixP
->fx_file
, fixP
->fx_line
);
3189 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3192 /* Prepare machine-dependent frags for relaxation.
3194 Called just before relaxation starts. Any symbol that is now undefined
3195 will not become defined.
3197 Return the correct fr_subtype in the frag.
3199 Return the initial "guess for fr_var" to caller. The guess for fr_var
3200 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3201 or fr_var contributes to our returned value.
3203 Although it may not be explicit in the frag, pretend
3204 fr_var starts with a value. */
3207 md_estimate_size_before_relax (fragS
*fragP
,
3212 /* If the symbol is not located within the same section AND it's not
3213 an absolute section, use the maximum. OR if the symbol is a
3214 constant AND the insn is by nature not pc-rel, use the maximum.
3215 OR if the symbol is being equated against another symbol, use the
3216 maximum. OR if the symbol is weak use the maximum. */
3217 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3218 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3219 || (symbol_constant_p (fragP
->fr_symbol
)
3220 && !fragP
->tc_frag_data
.pcrel
)
3221 || symbol_equated_p (fragP
->fr_symbol
)
3222 || S_IS_WEAK (fragP
->fr_symbol
))
3224 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3225 ++fragP
->fr_subtype
;
3228 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3229 fragP
->fr_var
= growth
;
3231 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3232 fragP
->fr_file
, fragP
->fr_line
, growth
);
3237 /* Translate internal representation of relocation info to BFD target
3241 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3245 bfd_reloc_code_real_type code
;
3247 reloc
= XNEW (arelent
);
3248 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3249 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3250 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3252 /* Make sure none of our internal relocations make it this far.
3253 They'd better have been fully resolved by this point. */
3254 gas_assert ((int) fixP
->fx_r_type
> 0);
3256 code
= fixP
->fx_r_type
;
3258 /* if we have something like add gp, pcl,
3259 _GLOBAL_OFFSET_TABLE_@gotpc. */
3260 if (code
== BFD_RELOC_ARC_GOTPC32
3262 && fixP
->fx_addsy
== GOT_symbol
)
3263 code
= BFD_RELOC_ARC_GOTPC
;
3265 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3266 if (reloc
->howto
== NULL
)
3268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3269 _("cannot represent `%s' relocation in object file"),
3270 bfd_get_reloc_code_name (code
));
3274 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3275 as_fatal (_("internal error? cannot generate `%s' relocation"),
3276 bfd_get_reloc_code_name (code
));
3278 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3280 reloc
->addend
= fixP
->fx_offset
;
3285 /* Perform post-processing of machine-dependent frags after relaxation.
3286 Called after relaxation is finished.
3287 In: Address of frag.
3288 fr_type == rs_machine_dependent.
3289 fr_subtype is what the address relaxed to.
3291 Out: Any fixS:s and constants are set up. */
3294 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3295 segT segment ATTRIBUTE_UNUSED
,
3298 const relax_typeS
*table_entry
;
3300 const struct arc_opcode
*opcode
;
3301 struct arc_insn insn
;
3303 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3305 fix
= fragP
->fr_fix
;
3306 dest
= fragP
->fr_literal
+ fix
;
3307 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3309 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3310 "var: %"BFD_VMA_FMT
"d\n",
3311 fragP
->fr_file
, fragP
->fr_line
,
3312 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3314 if (fragP
->fr_subtype
<= 0
3315 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3316 as_fatal (_("no relaxation found for this instruction."));
3318 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3320 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3321 relax_arg
->nflg
, &insn
);
3323 apply_fixups (&insn
, fragP
, fix
);
3325 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3326 gas_assert (table_entry
->rlx_length
== size
);
3327 emit_insn0 (&insn
, dest
, TRUE
);
3329 fragP
->fr_fix
+= table_entry
->rlx_length
;
3333 /* We have no need to default values of symbols. We could catch
3334 register names here, but that is handled by inserting them all in
3335 the symbol table to begin with. */
3338 md_undefined_symbol (char *name
)
3340 /* The arc abi demands that a GOT[0] should be referencible as
3341 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3342 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3344 && (*(name
+1) == 'G')
3345 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3349 if (symbol_find (name
))
3350 as_bad ("GOT already in symbol table");
3352 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3353 (valueT
) 0, &zero_address_frag
);
3360 /* Turn a string in input_line_pointer into a floating point constant
3361 of type type, and store the appropriate bytes in *litP. The number
3362 of LITTLENUMS emitted is stored in *sizeP. An error message is
3363 returned, or NULL on OK. */
3366 md_atof (int type
, char *litP
, int *sizeP
)
3368 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3371 /* Called for any expression that can not be recognized. When the
3372 function is called, `input_line_pointer' will point to the start of
3373 the expression. We use it when we have complex operations like
3374 @label1 - @label2. */
3377 md_operand (expressionS
*expressionP
)
3379 char *p
= input_line_pointer
;
3382 input_line_pointer
++;
3383 expressionP
->X_op
= O_symbol
;
3384 expressionP
->X_md
= O_absent
;
3385 expression (expressionP
);
3389 /* This function is called from the function 'expression', it attempts
3390 to parse special names (in our case register names). It fills in
3391 the expression with the identified register. It returns TRUE if
3392 it is a register and FALSE otherwise. */
3395 arc_parse_name (const char *name
,
3396 struct expressionS
*e
)
3400 if (!assembling_insn
)
3403 if (e
->X_op
== O_symbol
3404 && e
->X_md
== O_absent
)
3407 sym
= str_hash_find (arc_reg_hash
, name
);
3410 e
->X_op
= O_register
;
3411 e
->X_add_number
= S_GET_VALUE (sym
);
3415 sym
= str_hash_find (arc_addrtype_hash
, name
);
3418 e
->X_op
= O_addrtype
;
3419 e
->X_add_number
= S_GET_VALUE (sym
);
3427 Invocation line includes a switch not recognized by the base assembler.
3428 See if it's a processor-specific option.
3430 New options (supported) are:
3432 -mcpu=<cpu name> Assemble for selected processor
3433 -EB/-mbig-endian Big-endian
3434 -EL/-mlittle-endian Little-endian
3435 -mrelax Enable relaxation
3437 The following CPU names are recognized:
3438 arc600, arc700, arcem, archs, nps400. */
3441 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3447 return md_parse_option (OPTION_MCPU
, "arc600");
3450 return md_parse_option (OPTION_MCPU
, "arc700");
3453 return md_parse_option (OPTION_MCPU
, "arcem");
3456 return md_parse_option (OPTION_MCPU
, "archs");
3460 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3465 arc_target_format
= "elf32-bigarc";
3466 byte_order
= BIG_ENDIAN
;
3470 arc_target_format
= "elf32-littlearc";
3471 byte_order
= LITTLE_ENDIAN
;
3475 selected_cpu
.features
|= CD
;
3477 arc_check_feature ();
3481 relaxation_state
= 1;
3485 selected_cpu
.features
|= NPS400
;
3486 cl_features
|= NPS400
;
3487 arc_check_feature ();
3491 selected_cpu
.features
|= SPX
;
3493 arc_check_feature ();
3497 selected_cpu
.features
|= DPX
;
3499 arc_check_feature ();
3503 selected_cpu
.features
|= DPA
;
3505 arc_check_feature ();
3508 /* Dummy options are accepted but have no effect. */
3509 case OPTION_USER_MODE
:
3510 case OPTION_LD_EXT_MASK
:
3513 case OPTION_BARREL_SHIFT
:
3514 case OPTION_MIN_MAX
:
3519 case OPTION_XMAC_D16
:
3520 case OPTION_XMAC_24
:
3521 case OPTION_DSP_PACKA
:
3524 case OPTION_TELEPHONY
:
3525 case OPTION_XYMEMORY
:
3538 /* Display the list of cpu names for use in the help text. */
3541 arc_show_cpu_list (FILE *stream
)
3544 static const char *space_buf
= " ";
3546 fprintf (stream
, "%s", space_buf
);
3547 offset
= strlen (space_buf
);
3548 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3550 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3552 /* If displaying the new cpu name string, and the ', ' (for all
3553 but the last one) will take us past a target width of 80
3554 characters, then it's time for a new line. */
3555 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3557 fprintf (stream
, "\n%s", space_buf
);
3558 offset
= strlen (space_buf
);
3561 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3562 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3567 md_show_usage (FILE *stream
)
3569 fprintf (stream
, _("ARC-specific assembler options:\n"));
3571 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3572 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3573 arc_show_cpu_list (stream
);
3574 fprintf (stream
, "\n");
3575 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3576 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3577 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3578 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3580 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3581 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3583 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3585 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3586 "point\n\t\t\t instructions for ARC EM\n");
3589 " -mcode-density\t enable code density option for ARC EM\n");
3591 fprintf (stream
, _("\
3592 -EB assemble code for a big-endian cpu\n"));
3593 fprintf (stream
, _("\
3594 -EL assemble code for a little-endian cpu\n"));
3595 fprintf (stream
, _("\
3596 -mrelax enable relaxation\n"));
3598 fprintf (stream
, _("The following ARC-specific assembler options are "
3599 "deprecated and are accepted\nfor compatibility only:\n"));
3601 fprintf (stream
, _(" -mEA\n"
3602 " -mbarrel-shifter\n"
3603 " -mbarrel_shifter\n"
3608 " -mld-extension-reg-mask\n"
3624 " -muser-mode-only\n"
3628 /* Find the proper relocation for the given opcode. */
3630 static extended_bfd_reloc_code_real_type
3631 find_reloc (const char *name
,
3632 const char *opcodename
,
3633 const struct arc_flags
*pflags
,
3635 extended_bfd_reloc_code_real_type reloc
)
3639 bfd_boolean found_flag
, tmp
;
3640 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3642 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3644 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3646 /* Find the entry. */
3647 if (strcmp (name
, r
->name
))
3649 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3656 unsigned * psflg
= (unsigned *)r
->flags
;
3660 for (j
= 0; j
< nflg
; j
++)
3661 if (!strcmp (pflags
[j
].name
,
3662 arc_flag_operands
[*psflg
].name
))
3683 if (reloc
!= r
->oldreloc
)
3690 if (ret
== BFD_RELOC_UNUSED
)
3691 as_bad (_("Unable to find %s relocation for instruction %s"),
3696 /* All the symbol types that are allowed to be used for
3700 may_relax_expr (expressionS tok
)
3702 /* Check if we have unrelaxable relocs. */
3727 /* Checks if flags are in line with relaxable insn. */
3730 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3731 const struct arc_flags
*pflags
,
3734 unsigned flag_class
,
3739 const struct arc_flag_operand
*flag_opand
;
3740 int i
, counttrue
= 0;
3742 /* Iterate through flags classes. */
3743 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3745 /* Iterate through flags in flag class. */
3746 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3749 flag_opand
= &arc_flag_operands
[flag
];
3750 /* Iterate through flags in ins to compare. */
3751 for (i
= 0; i
< nflgs
; ++i
)
3753 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3764 /* If counttrue == nflgs, then all flags have been found. */
3765 return (counttrue
== nflgs
? TRUE
: FALSE
);
3768 /* Checks if operands are in line with relaxable insn. */
3771 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3772 const expressionS
*tok
,
3775 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3778 while (*operand
!= EMPTY
)
3780 const expressionS
*epr
= &tok
[i
];
3782 if (i
!= 0 && i
>= ntok
)
3788 if (!(epr
->X_op
== O_multiply
3789 || epr
->X_op
== O_divide
3790 || epr
->X_op
== O_modulus
3791 || epr
->X_op
== O_add
3792 || epr
->X_op
== O_subtract
3793 || epr
->X_op
== O_symbol
))
3799 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3803 if (epr
->X_op
!= O_register
)
3808 if (epr
->X_op
!= O_register
)
3811 switch (epr
->X_add_number
)
3813 case 0: case 1: case 2: case 3:
3814 case 12: case 13: case 14: case 15:
3821 case REGISTER_NO_GP
:
3822 if ((epr
->X_op
!= O_register
)
3823 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3828 if (epr
->X_op
!= O_bracket
)
3833 /* Don't understand, bail out. */
3839 operand
= &ins
->operands
[i
];
3842 return (i
== ntok
? TRUE
: FALSE
);
3845 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3848 relax_insn_p (const struct arc_opcode
*opcode
,
3849 const expressionS
*tok
,
3851 const struct arc_flags
*pflags
,
3855 bfd_boolean rv
= FALSE
;
3857 /* Check the relaxation table. */
3858 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3860 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3862 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3863 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3864 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3865 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3868 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3869 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3870 sizeof (expressionS
) * ntok
);
3871 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3872 sizeof (struct arc_flags
) * nflg
);
3873 frag_now
->tc_frag_data
.nflg
= nflg
;
3874 frag_now
->tc_frag_data
.ntok
= ntok
;
3882 /* Turn an opcode description and a set of arguments into
3883 an instruction and a fixup. */
3886 assemble_insn (const struct arc_opcode
*opcode
,
3887 const expressionS
*tok
,
3889 const struct arc_flags
*pflags
,
3891 struct arc_insn
*insn
)
3893 const expressionS
*reloc_exp
= NULL
;
3894 unsigned long long image
;
3895 const unsigned char *argidx
;
3898 unsigned char pcrel
= 0;
3899 bfd_boolean needGOTSymbol
;
3900 bfd_boolean has_delay_slot
= FALSE
;
3901 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3903 memset (insn
, 0, sizeof (*insn
));
3904 image
= opcode
->opcode
;
3906 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3907 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3910 /* Handle operands. */
3911 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3913 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3914 const expressionS
*t
= (const expressionS
*) 0;
3916 if (ARC_OPERAND_IS_FAKE (operand
))
3919 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3921 /* Duplicate operand, already inserted. */
3933 /* Regardless if we have a reloc or not mark the instruction
3934 limm if it is the case. */
3935 if (operand
->flags
& ARC_OPERAND_LIMM
)
3936 insn
->has_limm
= TRUE
;
3941 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3946 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3948 if (operand
->flags
& ARC_OPERAND_LIMM
)
3949 insn
->limm
= t
->X_add_number
;
3955 /* Ignore brackets, colons, and address types. */
3959 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3963 /* Maybe register range. */
3964 if ((t
->X_add_number
== 0)
3965 && contains_register (t
->X_add_symbol
)
3966 && contains_register (t
->X_op_symbol
))
3970 regs
= get_register (t
->X_add_symbol
);
3972 regs
|= get_register (t
->X_op_symbol
);
3973 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3979 /* This operand needs a relocation. */
3980 needGOTSymbol
= FALSE
;
3985 if (opcode
->insn_class
== JUMP
)
3986 as_bad (_("Unable to use @plt relocation for insn %s"),
3988 needGOTSymbol
= TRUE
;
3989 reloc
= find_reloc ("plt", opcode
->name
,
3991 operand
->default_reloc
);
3996 needGOTSymbol
= TRUE
;
3997 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4000 if (operand
->flags
& ARC_OPERAND_LIMM
)
4002 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4003 if (arc_opcode_len (opcode
) == 2
4004 || opcode
->insn_class
== JUMP
)
4005 as_bad (_("Unable to use @pcl relocation for insn %s"),
4010 /* This is a relaxed operand which initially was
4011 limm, choose whatever we have defined in the
4013 reloc
= operand
->default_reloc
;
4017 reloc
= find_reloc ("sda", opcode
->name
,
4019 operand
->default_reloc
);
4023 needGOTSymbol
= TRUE
;
4028 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4031 case O_tpoff9
: /*FIXME! Check for the conditionality of
4033 case O_dtpoff9
: /*FIXME! Check for the conditionality of
4035 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4039 /* Just consider the default relocation. */
4040 reloc
= operand
->default_reloc
;
4044 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4045 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4052 /* sanity checks. */
4053 reloc_howto_type
*reloc_howto
4054 = bfd_reloc_type_lookup (stdoutput
,
4055 (bfd_reloc_code_real_type
) reloc
);
4056 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4057 if (reloc_howto
->rightshift
)
4058 reloc_bitsize
-= reloc_howto
->rightshift
;
4059 if (reloc_bitsize
!= operand
->bits
)
4061 as_bad (_("invalid relocation %s for field"),
4062 bfd_get_reloc_code_name (reloc
));
4067 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4068 as_fatal (_("too many fixups"));
4070 struct arc_fixup
*fixup
;
4071 fixup
= &insn
->fixups
[insn
->nfixups
++];
4073 fixup
->reloc
= reloc
;
4074 if ((int) reloc
< 0)
4075 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4078 reloc_howto_type
*reloc_howto
=
4079 bfd_reloc_type_lookup (stdoutput
,
4080 (bfd_reloc_code_real_type
) fixup
->reloc
);
4081 pcrel
= reloc_howto
->pc_relative
;
4083 fixup
->pcrel
= pcrel
;
4084 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4091 for (i
= 0; i
< nflg
; i
++)
4093 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4095 /* Check if the instruction has a delay slot. */
4096 if (!strcmp (flg_operand
->name
, "d"))
4097 has_delay_slot
= TRUE
;
4099 /* There is an exceptional case when we cannot insert a flag just as
4100 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4101 relation with the relative address. Unfortunately, some of the
4102 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4103 handled in the normal way.
4105 Flag operands don't have an architecture field, so we can't
4106 directly validate that FLAG_OPERAND is valid for the current
4107 architecture, what we do instead is just validate that we're
4108 assembling for an ARCv2 architecture. */
4109 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4110 && (!strcmp (flg_operand
->name
, "t")
4111 || !strcmp (flg_operand
->name
, "nt")))
4113 unsigned bitYoperand
= 0;
4114 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4115 if (!strcmp (flg_operand
->name
, "t"))
4116 if (!strcmp (opcode
->name
, "bbit0")
4117 || !strcmp (opcode
->name
, "bbit1"))
4118 bitYoperand
= arc_NToperand
;
4120 bitYoperand
= arc_Toperand
;
4122 if (!strcmp (opcode
->name
, "bbit0")
4123 || !strcmp (opcode
->name
, "bbit1"))
4124 bitYoperand
= arc_Toperand
;
4126 bitYoperand
= arc_NToperand
;
4128 gas_assert (reloc_exp
!= NULL
);
4129 if (reloc_exp
->X_op
== O_constant
)
4131 /* Check if we have a constant and solved it
4133 offsetT val
= reloc_exp
->X_add_number
;
4134 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4139 struct arc_fixup
*fixup
;
4141 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4142 as_fatal (_("too many fixups"));
4144 fixup
= &insn
->fixups
[insn
->nfixups
++];
4145 fixup
->exp
= *reloc_exp
;
4146 fixup
->reloc
= -bitYoperand
;
4147 fixup
->pcrel
= pcrel
;
4148 fixup
->islong
= FALSE
;
4152 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4153 << flg_operand
->shift
;
4156 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4158 /* Instruction length. */
4159 insn
->len
= arc_opcode_len (opcode
);
4163 /* Update last insn status. */
4164 arc_last_insns
[1] = arc_last_insns
[0];
4165 arc_last_insns
[0].opcode
= opcode
;
4166 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4167 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4169 /* Check if the current instruction is legally used. */
4170 if (arc_last_insns
[1].has_delay_slot
4171 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4172 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4173 arc_last_insns
[1].opcode
->name
,
4174 arc_last_insns
[0].opcode
->name
);
4175 if (arc_last_insns
[1].has_delay_slot
4176 && arc_last_insns
[0].has_limm
)
4177 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4178 arc_last_insns
[1].opcode
->name
,
4179 arc_last_insns
[0].opcode
->name
);
4183 arc_handle_align (fragS
* fragP
)
4185 if ((fragP
)->fr_type
== rs_align_code
)
4187 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4188 valueT count
= ((fragP
)->fr_next
->fr_address
4189 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4191 (fragP
)->fr_var
= 2;
4193 if (count
& 1)/* Padding in the gap till the next 2-byte
4194 boundary with 0s. */
4199 /* Writing nop_s. */
4200 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4204 /* Here we decide which fixups can be adjusted to make them relative
4205 to the beginning of the section instead of the symbol. Basically
4206 we need to make sure that the dynamic relocations are done
4207 correctly, so in some cases we force the original symbol to be
4211 tc_arc_fix_adjustable (fixS
*fixP
)
4214 /* Prevent all adjustments to global symbols. */
4215 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4217 if (S_IS_WEAK (fixP
->fx_addsy
))
4220 /* Adjust_reloc_syms doesn't know about the GOT. */
4221 switch (fixP
->fx_r_type
)
4223 case BFD_RELOC_ARC_GOTPC32
:
4224 case BFD_RELOC_ARC_PLT32
:
4225 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4226 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4227 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4228 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4238 /* Compute the reloc type of an expression EXP. */
4241 arc_check_reloc (expressionS
*exp
,
4242 bfd_reloc_code_real_type
*r_type_p
)
4244 if (*r_type_p
== BFD_RELOC_32
4245 && exp
->X_op
== O_subtract
4246 && exp
->X_op_symbol
!= NULL
4247 && S_GET_SEGMENT (exp
->X_op_symbol
) == now_seg
)
4248 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4252 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4255 arc_cons_fix_new (fragS
*frag
,
4259 bfd_reloc_code_real_type r_type
)
4261 r_type
= BFD_RELOC_UNUSED
;
4266 r_type
= BFD_RELOC_8
;
4270 r_type
= BFD_RELOC_16
;
4274 r_type
= BFD_RELOC_24
;
4278 r_type
= BFD_RELOC_32
;
4279 arc_check_reloc (exp
, &r_type
);
4283 r_type
= BFD_RELOC_64
;
4287 as_bad (_("unsupported BFD relocation size %u"), size
);
4288 r_type
= BFD_RELOC_UNUSED
;
4291 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4294 /* The actual routine that checks the ZOL conditions. */
4297 check_zol (symbolS
*s
)
4299 switch (selected_cpu
.mach
)
4301 case bfd_mach_arc_arcv2
:
4302 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4305 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4306 || arc_last_insns
[1].has_delay_slot
)
4307 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4311 case bfd_mach_arc_arc600
:
4313 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4314 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4317 if (arc_last_insns
[0].has_limm
4318 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4319 as_bad (_("A jump instruction with long immediate detected at the \
4320 end of the ZOL label @%s"), S_GET_NAME (s
));
4323 case bfd_mach_arc_arc700
:
4324 if (arc_last_insns
[0].has_delay_slot
)
4325 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4334 /* If ZOL end check the last two instruction for illegals. */
4336 arc_frob_label (symbolS
* sym
)
4338 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4341 dwarf2_emit_label (sym
);
4344 /* Used because generic relaxation assumes a pc-rel value whilst we
4345 also relax instructions that use an absolute value resolved out of
4346 relative values (if that makes any sense). An example: 'add r1,
4347 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4348 but if they're in the same section we can subtract the section
4349 offset relocation which ends up in a resolved value. So if @.L2 is
4350 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4351 .text + 0x40 = 0x10. */
4353 arc_pcrel_adjust (fragS
*fragP
)
4355 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4356 fragP
->fr_address
, fragP
->fr_fix
,
4357 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4359 if (!fragP
->tc_frag_data
.pcrel
)
4360 return fragP
->fr_address
+ fragP
->fr_fix
;
4362 /* Take into account the PCL rounding. */
4363 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4366 /* Initialize the DWARF-2 unwind information for this procedure. */
4369 tc_arc_frame_initial_instructions (void)
4371 /* Stack pointer is register 28. */
4372 cfi_add_CFA_def_cfa (28, 0);
4376 tc_arc_regname_to_dw2regnum (char *regname
)
4380 sym
= str_hash_find (arc_reg_hash
, regname
);
4382 return S_GET_VALUE (sym
);
4387 /* Adjust the symbol table. Delete found AUX register symbols. */
4390 arc_adjust_symtab (void)
4394 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4396 /* I've created a symbol during parsing process. Now, remove
4397 the symbol as it is found to be an AUX register. */
4398 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4399 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4402 /* Now do generic ELF adjustments. */
4403 elf_adjust_symtab ();
4407 tokenize_extinsn (extInstruction_t
*einsn
)
4411 unsigned char major_opcode
;
4412 unsigned char sub_opcode
;
4413 unsigned char syntax_class
= 0;
4414 unsigned char syntax_class_modifiers
= 0;
4415 unsigned char suffix_class
= 0;
4420 /* 1st: get instruction name. */
4421 p
= input_line_pointer
;
4422 c
= get_symbol_name (&p
);
4424 insn_name
= xstrdup (p
);
4425 restore_line_pointer (c
);
4427 /* Convert to lower case. */
4428 for (p
= insn_name
; *p
; ++p
)
4431 /* 2nd: get major opcode. */
4432 if (*input_line_pointer
!= ',')
4434 as_bad (_("expected comma after instruction name"));
4435 ignore_rest_of_line ();
4438 input_line_pointer
++;
4439 major_opcode
= get_absolute_expression ();
4441 /* 3rd: get sub-opcode. */
4444 if (*input_line_pointer
!= ',')
4446 as_bad (_("expected comma after major opcode"));
4447 ignore_rest_of_line ();
4450 input_line_pointer
++;
4451 sub_opcode
= get_absolute_expression ();
4453 /* 4th: get suffix class. */
4456 if (*input_line_pointer
!= ',')
4458 as_bad ("expected comma after sub opcode");
4459 ignore_rest_of_line ();
4462 input_line_pointer
++;
4468 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4470 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4471 suffixclass
[i
].len
))
4473 suffix_class
|= suffixclass
[i
].attr_class
;
4474 input_line_pointer
+= suffixclass
[i
].len
;
4479 if (i
== ARRAY_SIZE (suffixclass
))
4481 as_bad ("invalid suffix class");
4482 ignore_rest_of_line ();
4488 if (*input_line_pointer
== '|')
4489 input_line_pointer
++;
4494 /* 5th: get syntax class and syntax class modifiers. */
4495 if (*input_line_pointer
!= ',')
4497 as_bad ("expected comma after suffix class");
4498 ignore_rest_of_line ();
4501 input_line_pointer
++;
4507 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4509 if (!strncmp (syntaxclassmod
[i
].name
,
4511 syntaxclassmod
[i
].len
))
4513 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4514 input_line_pointer
+= syntaxclassmod
[i
].len
;
4519 if (i
== ARRAY_SIZE (syntaxclassmod
))
4521 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4523 if (!strncmp (syntaxclass
[i
].name
,
4525 syntaxclass
[i
].len
))
4527 syntax_class
|= syntaxclass
[i
].attr_class
;
4528 input_line_pointer
+= syntaxclass
[i
].len
;
4533 if (i
== ARRAY_SIZE (syntaxclass
))
4535 as_bad ("missing syntax class");
4536 ignore_rest_of_line ();
4543 if (*input_line_pointer
== '|')
4544 input_line_pointer
++;
4549 demand_empty_rest_of_line ();
4551 einsn
->name
= insn_name
;
4552 einsn
->major
= major_opcode
;
4553 einsn
->minor
= sub_opcode
;
4554 einsn
->syntax
= syntax_class
;
4555 einsn
->modsyn
= syntax_class_modifiers
;
4556 einsn
->suffix
= suffix_class
;
4557 einsn
->flags
= syntax_class
4558 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4561 /* Generate an extension section. */
4564 arc_set_ext_seg (void)
4566 if (!arcext_section
)
4568 arcext_section
= subseg_new (".arcextmap", 0);
4569 bfd_set_section_flags (arcext_section
, SEC_READONLY
| SEC_HAS_CONTENTS
);
4572 subseg_set (arcext_section
, 0);
4576 /* Create an extension instruction description in the arc extension
4577 section of the output file.
4578 The structure for an instruction is like this:
4579 [0]: Length of the record.
4580 [1]: Type of the record.
4584 [4]: Syntax (flags).
4585 [5]+ Name instruction.
4587 The sequence is terminated by an empty entry. */
4590 create_extinst_section (extInstruction_t
*einsn
)
4593 segT old_sec
= now_seg
;
4594 int old_subsec
= now_subseg
;
4596 int name_len
= strlen (einsn
->name
);
4601 *p
= 5 + name_len
+ 1;
4603 *p
= EXT_INSTRUCTION
;
4610 p
= frag_more (name_len
+ 1);
4611 strcpy (p
, einsn
->name
);
4613 subseg_set (old_sec
, old_subsec
);
4616 /* Handler .extinstruction pseudo-op. */
4619 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4621 extInstruction_t einsn
;
4622 struct arc_opcode
*arc_ext_opcodes
;
4623 const char *errmsg
= NULL
;
4624 unsigned char moplow
, mophigh
;
4626 memset (&einsn
, 0, sizeof (einsn
));
4627 tokenize_extinsn (&einsn
);
4629 /* Check if the name is already used. */
4630 if (arc_find_opcode (einsn
.name
))
4631 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4633 /* Check the opcode ranges. */
4635 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4636 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4638 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4639 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4641 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4642 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4643 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4645 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4647 case ARC_SYNTAX_3OP
:
4648 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4649 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4651 case ARC_SYNTAX_2OP
:
4652 case ARC_SYNTAX_1OP
:
4653 case ARC_SYNTAX_NOP
:
4654 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4655 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4661 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4662 if (arc_ext_opcodes
== NULL
)
4665 as_fatal ("%s", errmsg
);
4667 as_fatal (_("Couldn't generate extension instruction opcodes"));
4670 as_warn ("%s", errmsg
);
4672 /* Insert the extension instruction. */
4673 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4675 create_extinst_section (&einsn
);
4679 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4685 int number
, imode
= 0;
4686 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4687 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4688 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4690 /* 1st: get register name. */
4692 p
= input_line_pointer
;
4693 c
= get_symbol_name (&p
);
4696 restore_line_pointer (c
);
4698 /* 2nd: get register number. */
4701 if (*input_line_pointer
!= ',')
4703 as_bad (_("expected comma after name"));
4704 ignore_rest_of_line ();
4708 input_line_pointer
++;
4709 number
= get_absolute_expression ();
4712 && (opertype
!= EXT_AUX_REGISTER
))
4714 as_bad (_("%s second argument cannot be a negative number %d"),
4715 isCore_p
? "extCoreRegister's" : "extCondCode's",
4717 ignore_rest_of_line ();
4724 /* 3rd: get register mode. */
4727 if (*input_line_pointer
!= ',')
4729 as_bad (_("expected comma after register number"));
4730 ignore_rest_of_line ();
4735 input_line_pointer
++;
4736 mode
= input_line_pointer
;
4738 if (!strncmp (mode
, "r|w", 3))
4741 input_line_pointer
+= 3;
4743 else if (!strncmp (mode
, "r", 1))
4745 imode
= ARC_REGISTER_READONLY
;
4746 input_line_pointer
+= 1;
4748 else if (strncmp (mode
, "w", 1))
4750 as_bad (_("invalid mode"));
4751 ignore_rest_of_line ();
4757 imode
= ARC_REGISTER_WRITEONLY
;
4758 input_line_pointer
+= 1;
4764 /* 4th: get core register shortcut. */
4766 if (*input_line_pointer
!= ',')
4768 as_bad (_("expected comma after register mode"));
4769 ignore_rest_of_line ();
4774 input_line_pointer
++;
4776 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4778 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4779 input_line_pointer
+= 15;
4781 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4783 as_bad (_("shortcut designator invalid"));
4784 ignore_rest_of_line ();
4790 input_line_pointer
+= 12;
4793 demand_empty_rest_of_line ();
4796 ereg
->number
= number
;
4797 ereg
->imode
= imode
;
4801 /* Create an extension register/condition description in the arc
4802 extension section of the output file.
4804 The structure for an instruction is like this:
4805 [0]: Length of the record.
4806 [1]: Type of the record.
4808 For core regs and condition codes:
4812 For auxiliary registers:
4816 The sequence is terminated by an empty entry. */
4819 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4821 segT old_sec
= now_seg
;
4822 int old_subsec
= now_subseg
;
4824 int name_len
= strlen (ereg
->name
);
4831 case EXT_CORE_REGISTER
:
4833 *p
= 3 + name_len
+ 1;
4839 case EXT_AUX_REGISTER
:
4841 *p
= 6 + name_len
+ 1;
4843 *p
= EXT_AUX_REGISTER
;
4845 *p
= (ereg
->number
>> 24) & 0xff;
4847 *p
= (ereg
->number
>> 16) & 0xff;
4849 *p
= (ereg
->number
>> 8) & 0xff;
4851 *p
= (ereg
->number
) & 0xff;
4857 p
= frag_more (name_len
+ 1);
4858 strcpy (p
, ereg
->name
);
4860 subseg_set (old_sec
, old_subsec
);
4863 /* Handler .extCoreRegister pseudo-op. */
4866 arc_extcorereg (int opertype
)
4869 struct arc_aux_reg
*auxr
;
4870 struct arc_flag_operand
*ccode
;
4872 memset (&ereg
, 0, sizeof (ereg
));
4873 if (!tokenize_extregister (&ereg
, opertype
))
4878 case EXT_CORE_REGISTER
:
4879 /* Core register. */
4880 if (ereg
.number
> 60)
4881 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4883 declare_register (ereg
.name
, ereg
.number
);
4885 case EXT_AUX_REGISTER
:
4886 /* Auxiliary register. */
4887 auxr
= XNEW (struct arc_aux_reg
);
4888 auxr
->name
= ereg
.name
;
4889 auxr
->cpu
= selected_cpu
.flags
;
4890 auxr
->subclass
= NONE
;
4891 auxr
->address
= ereg
.number
;
4892 str_hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4895 /* Condition code. */
4896 if (ereg
.number
> 31)
4897 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4899 ext_condcode
.size
++;
4900 ext_condcode
.arc_ext_condcode
=
4901 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4902 ext_condcode
.size
+ 1);
4903 if (ext_condcode
.arc_ext_condcode
== NULL
)
4904 as_fatal (_("Virtual memory exhausted"));
4906 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4907 ccode
->name
= ereg
.name
;
4908 ccode
->code
= ereg
.number
;
4911 ccode
->favail
= 0; /* not used. */
4913 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4916 as_bad (_("Unknown extension"));
4919 create_extcore_section (&ereg
, opertype
);
4922 /* Parse a .arc_attribute directive. */
4925 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4927 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4929 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4930 attributes_set_explicitly
[tag
] = TRUE
;
4933 /* Set an attribute if it has not already been set by the user. */
4936 arc_set_attribute_int (int tag
, int value
)
4939 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4940 || !attributes_set_explicitly
[tag
])
4941 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4945 arc_set_attribute_string (int tag
, const char *value
)
4948 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4949 || !attributes_set_explicitly
[tag
])
4950 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4953 /* Allocate and concatenate two strings. s1 can be NULL but not
4954 s2. s1 pointer is freed at end of this procedure. */
4957 arc_stralloc (char * s1
, const char * s2
)
4963 len
= strlen (s1
) + 1;
4965 /* Only s1 can be null. */
4967 len
+= strlen (s2
) + 1;
4969 p
= (char *) xmalloc (len
);
4971 as_fatal (_("Virtual memory exhausted"));
4986 /* Set the public ARC object attributes. */
4989 arc_set_public_attributes (void)
4995 /* Tag_ARC_CPU_name. */
4996 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4998 /* Tag_ARC_CPU_base. */
4999 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
5001 case E_ARC_MACH_ARC600
:
5002 case E_ARC_MACH_ARC601
:
5003 base
= TAG_CPU_ARC6xx
;
5005 case E_ARC_MACH_ARC700
:
5006 base
= TAG_CPU_ARC7xx
;
5008 case EF_ARC_CPU_ARCV2EM
:
5009 base
= TAG_CPU_ARCEM
;
5011 case EF_ARC_CPU_ARCV2HS
:
5012 base
= TAG_CPU_ARCHS
;
5018 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
5019 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5021 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5022 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
5024 /* Tag_ARC_ABI_osver. */
5025 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
5027 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5030 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
5031 | (val
& 0x0f << 8));
5035 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
5038 /* Tag_ARC_ISA_config. */
5039 arc_check_feature();
5041 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
5042 if (selected_cpu
.features
& feature_list
[i
].feature
)
5043 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5046 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5048 /* Tag_ARC_ISA_mpy_option. */
5049 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5051 /* Tag_ARC_ABI_pic. */
5052 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5054 /* Tag_ARC_ABI_sda. */
5055 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5057 /* Tag_ARC_ABI_tls. */
5058 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5060 /* Tag_ARC_ATR_version. */
5061 arc_set_attribute_int (Tag_ARC_ATR_version
, 1);
5063 /* Tag_ARC_ABI_rf16. */
5064 if (attributes_set_explicitly
[Tag_ARC_ABI_rf16
]
5065 && bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5069 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5071 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_ABI_rf16
, 0);
5075 /* Add the default contents for the .ARC.attributes section. */
5080 arc_set_public_attributes ();
5082 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5083 as_fatal (_("could not set architecture and machine"));
5085 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5088 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5090 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5093 int arc_convert_symbolic_attribute (const char *name
)
5102 #define T(tag) {#tag, tag}
5103 T (Tag_ARC_PCS_config
),
5104 T (Tag_ARC_CPU_base
),
5105 T (Tag_ARC_CPU_variation
),
5106 T (Tag_ARC_CPU_name
),
5107 T (Tag_ARC_ABI_rf16
),
5108 T (Tag_ARC_ABI_osver
),
5109 T (Tag_ARC_ABI_sda
),
5110 T (Tag_ARC_ABI_pic
),
5111 T (Tag_ARC_ABI_tls
),
5112 T (Tag_ARC_ABI_enumsize
),
5113 T (Tag_ARC_ABI_exceptions
),
5114 T (Tag_ARC_ABI_double_size
),
5115 T (Tag_ARC_ISA_config
),
5116 T (Tag_ARC_ISA_apex
),
5117 T (Tag_ARC_ISA_mpy_option
),
5118 T (Tag_ARC_ATR_version
)
5126 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5127 if (streq (name
, attribute_table
[i
].name
))
5128 return attribute_table
[i
].tag
;
5134 eval: (c-set-style "gnu")