1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR
, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR
, /* ARM LR register */
6930 OP_RRe
, /* ARM register, only even numbered. */
6931 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST
, /* ARM register list */
6935 OP_CLRMLST
, /* CLRM register list */
6936 OP_VRSLST
, /* VFP single-precision register list */
6937 OP_VRDLST
, /* VFP double-precision register list */
6938 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST
, /* Neon element/structure list */
6941 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2
, /* MVE vector list with two elements. */
6943 OP_MSTRLST4
, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV
, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6969 OP_VLDR
, /* VLDR operand. */
6971 OP_I0
, /* immediate zero */
6972 OP_I7
, /* immediate value 0 .. 7 */
6973 OP_I15
, /* 0 .. 15 */
6974 OP_I16
, /* 1 .. 16 */
6975 OP_I16z
, /* 0 .. 16 */
6976 OP_I31
, /* 0 .. 31 */
6977 OP_I31w
, /* 0 .. 31, optional trailing ! */
6978 OP_I32
, /* 1 .. 32 */
6979 OP_I32z
, /* 0 .. 32 */
6980 OP_I63
, /* 0 .. 63 */
6981 OP_I63s
, /* -64 .. 63 */
6982 OP_I64
, /* 1 .. 64 */
6983 OP_I64z
, /* 0 .. 64 */
6984 OP_I255
, /* 0 .. 255 */
6986 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6987 OP_I7b
, /* 0 .. 7 */
6988 OP_I15b
, /* 0 .. 15 */
6989 OP_I31b
, /* 0 .. 31 */
6991 OP_SH
, /* shifter operand */
6992 OP_SHG
, /* shifter operand with possible group relocation */
6993 OP_ADDR
, /* Memory address expression (any mode) */
6994 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6995 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6996 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6997 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6998 OP_EXP
, /* arbitrary expression */
6999 OP_EXPi
, /* same, with optional immediate prefix */
7000 OP_EXPr
, /* same, with optional relocation suffix */
7001 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7002 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7003 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7004 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7006 OP_CPSF
, /* CPS flags */
7007 OP_ENDI
, /* Endianness specifier */
7008 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7009 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7010 OP_COND
, /* conditional code */
7011 OP_TB
, /* Table branch. */
7013 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7015 OP_RRnpc_I0
, /* ARM register or literal 0 */
7016 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7017 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7018 OP_RF_IF
, /* FPA register or immediate */
7019 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7020 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7022 /* Optional operands. */
7023 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7024 OP_oI31b
, /* 0 .. 31 */
7025 OP_oI32b
, /* 1 .. 32 */
7026 OP_oI32z
, /* 0 .. 32 */
7027 OP_oIffffb
, /* 0 .. 65535 */
7028 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7030 OP_oRR
, /* ARM register */
7031 OP_oLR
, /* ARM LR register */
7032 OP_oRRnpc
, /* ARM register, not the PC */
7033 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7034 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7035 OP_oRND
, /* Optional Neon double precision register */
7036 OP_oRNQ
, /* Optional Neon quad precision register */
7037 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7038 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7039 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7040 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7042 OP_oSHll
, /* LSL immediate */
7043 OP_oSHar
, /* ASR immediate */
7044 OP_oSHllar
, /* LSL or ASR immediate */
7045 OP_oROR
, /* ROR 0/8/16/24 */
7046 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7048 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7050 /* Some pre-defined mixed (ARM/THUMB) operands. */
7051 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7052 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7053 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7055 OP_FIRST_OPTIONAL
= OP_oI7b
7058 /* Generic instruction operand parser. This does no encoding and no
7059 semantic validation; it merely squirrels values away in the inst
7060 structure. Returns SUCCESS or FAIL depending on whether the
7061 specified grammar matched. */
7063 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7065 unsigned const int *upat
= pattern
;
7066 char *backtrack_pos
= 0;
7067 const char *backtrack_error
= 0;
7068 int i
, val
= 0, backtrack_index
= 0;
7069 enum arm_reg_type rtype
;
7070 parse_operand_result result
;
7071 unsigned int op_parse_code
;
7072 bfd_boolean partial_match
;
7074 #define po_char_or_fail(chr) \
7077 if (skip_past_char (&str, chr) == FAIL) \
7082 #define po_reg_or_fail(regtype) \
7085 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7086 & inst.operands[i].vectype); \
7089 first_error (_(reg_expected_msgs[regtype])); \
7092 inst.operands[i].reg = val; \
7093 inst.operands[i].isreg = 1; \
7094 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7095 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7096 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7097 || rtype == REG_TYPE_VFD \
7098 || rtype == REG_TYPE_NQ); \
7099 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7103 #define po_reg_or_goto(regtype, label) \
7106 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7107 & inst.operands[i].vectype); \
7111 inst.operands[i].reg = val; \
7112 inst.operands[i].isreg = 1; \
7113 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7114 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7115 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7116 || rtype == REG_TYPE_VFD \
7117 || rtype == REG_TYPE_NQ); \
7118 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7122 #define po_imm_or_fail(min, max, popt) \
7125 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7127 inst.operands[i].imm = val; \
7131 #define po_scalar_or_goto(elsz, label, reg_type) \
7134 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7138 inst.operands[i].reg = val; \
7139 inst.operands[i].isscalar = 1; \
7143 #define po_misc_or_fail(expr) \
7151 #define po_misc_or_fail_no_backtrack(expr) \
7155 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7156 backtrack_pos = 0; \
7157 if (result != PARSE_OPERAND_SUCCESS) \
7162 #define po_barrier_or_imm(str) \
7165 val = parse_barrier (&str); \
7166 if (val == FAIL && ! ISALPHA (*str)) \
7169 /* ISB can only take SY as an option. */ \
7170 || ((inst.instruction & 0xf0) == 0x60 \
7173 inst.error = _("invalid barrier type"); \
7174 backtrack_pos = 0; \
7180 skip_whitespace (str
);
7182 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7184 op_parse_code
= upat
[i
];
7185 if (op_parse_code
>= 1<<16)
7186 op_parse_code
= thumb
? (op_parse_code
>> 16)
7187 : (op_parse_code
& ((1<<16)-1));
7189 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7191 /* Remember where we are in case we need to backtrack. */
7192 backtrack_pos
= str
;
7193 backtrack_error
= inst
.error
;
7194 backtrack_index
= i
;
7197 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7198 po_char_or_fail (',');
7200 switch (op_parse_code
)
7212 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7213 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7214 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7215 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7216 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7217 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7220 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7224 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7227 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7229 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7231 /* Also accept generic coprocessor regs for unknown registers. */
7233 po_reg_or_fail (REG_TYPE_CN
);
7235 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7236 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7237 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7238 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7239 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7240 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7241 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7242 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7243 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7244 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7247 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7250 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7251 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7253 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7258 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7262 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7264 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7267 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7269 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7272 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7274 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7279 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7282 po_reg_or_fail (REG_TYPE_NSDQ
);
7286 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7290 po_reg_or_fail (REG_TYPE_MQ
);
7292 /* Neon scalar. Using an element size of 8 means that some invalid
7293 scalars are accepted here, so deal with those in later code. */
7294 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7298 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7301 po_imm_or_fail (0, 0, TRUE
);
7306 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7310 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7315 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7318 if (parse_ifimm_zero (&str
))
7319 inst
.operands
[i
].imm
= 0;
7323 = _("only floating point zero is allowed as immediate value");
7331 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7334 po_reg_or_fail (REG_TYPE_RN
);
7338 case OP_RNSDQ_RNSC_MQ_RR
:
7339 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7342 case OP_RNSDQ_RNSC_MQ
:
7343 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7348 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7352 po_reg_or_fail (REG_TYPE_NSDQ
);
7359 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7362 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7365 po_reg_or_fail (REG_TYPE_NSD
);
7369 case OP_RNDQMQ_RNSC_RR
:
7370 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7373 case OP_RNDQ_RNSC_RR
:
7374 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7376 case OP_RNDQMQ_RNSC
:
7377 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7382 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7385 po_reg_or_fail (REG_TYPE_NDQ
);
7391 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7394 po_reg_or_fail (REG_TYPE_VFD
);
7399 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7400 not careful then bad things might happen. */
7401 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7404 case OP_RNDQMQ_Ibig
:
7405 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7410 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7413 /* There's a possibility of getting a 64-bit immediate here, so
7414 we need special handling. */
7415 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7418 inst
.error
= _("immediate value is out of range");
7426 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7429 po_imm_or_fail (0, 63, TRUE
);
7434 po_char_or_fail ('[');
7435 po_reg_or_fail (REG_TYPE_RN
);
7436 po_char_or_fail (']');
7442 po_reg_or_fail (REG_TYPE_RN
);
7443 if (skip_past_char (&str
, '!') == SUCCESS
)
7444 inst
.operands
[i
].writeback
= 1;
7448 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7449 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7450 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7451 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7452 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7453 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7454 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7455 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7456 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7457 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7458 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7459 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7461 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7463 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7464 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7466 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7467 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7468 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7469 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7471 /* Immediate variants */
7473 po_char_or_fail ('{');
7474 po_imm_or_fail (0, 255, TRUE
);
7475 po_char_or_fail ('}');
7479 /* The expression parser chokes on a trailing !, so we have
7480 to find it first and zap it. */
7483 while (*s
&& *s
!= ',')
7488 inst
.operands
[i
].writeback
= 1;
7490 po_imm_or_fail (0, 31, TRUE
);
7498 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7503 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7508 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7510 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7512 val
= parse_reloc (&str
);
7515 inst
.error
= _("unrecognized relocation suffix");
7518 else if (val
!= BFD_RELOC_UNUSED
)
7520 inst
.operands
[i
].imm
= val
;
7521 inst
.operands
[i
].hasreloc
= 1;
7527 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7529 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7531 inst
.operands
[i
].hasreloc
= 1;
7533 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7535 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7536 inst
.operands
[i
].hasreloc
= 0;
7540 /* Operand for MOVW or MOVT. */
7542 po_misc_or_fail (parse_half (&str
));
7545 /* Register or expression. */
7546 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7547 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7549 /* Register or immediate. */
7550 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7551 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7553 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7555 if (!is_immediate_prefix (*str
))
7558 val
= parse_fpa_immediate (&str
);
7561 /* FPA immediates are encoded as registers 8-15.
7562 parse_fpa_immediate has already applied the offset. */
7563 inst
.operands
[i
].reg
= val
;
7564 inst
.operands
[i
].isreg
= 1;
7567 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7568 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7570 /* Two kinds of register. */
7573 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7575 || (rege
->type
!= REG_TYPE_MMXWR
7576 && rege
->type
!= REG_TYPE_MMXWC
7577 && rege
->type
!= REG_TYPE_MMXWCG
))
7579 inst
.error
= _("iWMMXt data or control register expected");
7582 inst
.operands
[i
].reg
= rege
->number
;
7583 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7589 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7591 || (rege
->type
!= REG_TYPE_MMXWC
7592 && rege
->type
!= REG_TYPE_MMXWCG
))
7594 inst
.error
= _("iWMMXt control register expected");
7597 inst
.operands
[i
].reg
= rege
->number
;
7598 inst
.operands
[i
].isreg
= 1;
7603 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7604 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7605 case OP_oROR
: val
= parse_ror (&str
); break;
7607 case OP_COND
: val
= parse_cond (&str
); break;
7608 case OP_oBARRIER_I15
:
7609 po_barrier_or_imm (str
); break;
7611 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7617 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7618 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7620 inst
.error
= _("Banked registers are not available with this "
7626 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7630 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7633 val
= parse_sys_vldr_vstr (&str
);
7637 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7640 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7642 if (strncasecmp (str
, "APSR_", 5) == 0)
7649 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7650 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7651 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7652 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7653 default: found
= 16;
7657 inst
.operands
[i
].isvec
= 1;
7658 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7659 inst
.operands
[i
].reg
= REG_PC
;
7666 po_misc_or_fail (parse_tb (&str
));
7669 /* Register lists. */
7671 val
= parse_reg_list (&str
, REGLIST_RN
);
7674 inst
.operands
[i
].writeback
= 1;
7680 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7684 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7689 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7694 /* Allow Q registers too. */
7695 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7696 REGLIST_NEON_D
, &partial_match
);
7700 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7701 REGLIST_VFP_S
, &partial_match
);
7702 inst
.operands
[i
].issingle
= 1;
7707 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7708 REGLIST_VFP_D_VPR
, &partial_match
);
7709 if (val
== FAIL
&& !partial_match
)
7712 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7713 REGLIST_VFP_S_VPR
, &partial_match
);
7714 inst
.operands
[i
].issingle
= 1;
7719 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7720 REGLIST_NEON_D
, &partial_match
);
7725 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7726 1, &inst
.operands
[i
].vectype
);
7727 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7731 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7732 0, &inst
.operands
[i
].vectype
);
7735 /* Addressing modes */
7737 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7741 po_misc_or_fail (parse_address (&str
, i
));
7745 po_misc_or_fail_no_backtrack (
7746 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7750 po_misc_or_fail_no_backtrack (
7751 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7755 po_misc_or_fail_no_backtrack (
7756 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7760 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7764 po_misc_or_fail_no_backtrack (
7765 parse_shifter_operand_group_reloc (&str
, i
));
7769 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7773 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7777 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7782 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7785 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7788 po_reg_or_fail (REG_TYPE_ZR
);
7792 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7795 /* Various value-based sanity checks and shared operations. We
7796 do not signal immediate failures for the register constraints;
7797 this allows a syntax error to take precedence. */
7798 switch (op_parse_code
)
7806 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7807 inst
.error
= BAD_PC
;
7812 if (inst
.operands
[i
].isreg
)
7814 if (inst
.operands
[i
].reg
== REG_PC
)
7815 inst
.error
= BAD_PC
;
7816 else if (inst
.operands
[i
].reg
== REG_SP
7817 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7818 relaxed since ARMv8-A. */
7819 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7822 inst
.error
= BAD_SP
;
7828 if (inst
.operands
[i
].isreg
7829 && inst
.operands
[i
].reg
== REG_PC
7830 && (inst
.operands
[i
].writeback
|| thumb
))
7831 inst
.error
= BAD_PC
;
7836 if (inst
.operands
[i
].isreg
)
7846 case OP_oBARRIER_I15
:
7859 inst
.operands
[i
].imm
= val
;
7864 if (inst
.operands
[i
].reg
!= REG_LR
)
7865 inst
.error
= _("operand must be LR register");
7870 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7871 inst
.error
= BAD_PC
;
7875 if (inst
.operands
[i
].isreg
7876 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7877 inst
.error
= BAD_ODD
;
7881 if (inst
.operands
[i
].isreg
)
7883 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7884 inst
.error
= BAD_EVEN
;
7885 else if (inst
.operands
[i
].reg
== REG_SP
)
7886 as_tsktsk (MVE_BAD_SP
);
7887 else if (inst
.operands
[i
].reg
== REG_PC
)
7888 inst
.error
= BAD_PC
;
7896 /* If we get here, this operand was successfully parsed. */
7897 inst
.operands
[i
].present
= 1;
7901 inst
.error
= BAD_ARGS
;
7906 /* The parse routine should already have set inst.error, but set a
7907 default here just in case. */
7909 inst
.error
= BAD_SYNTAX
;
7913 /* Do not backtrack over a trailing optional argument that
7914 absorbed some text. We will only fail again, with the
7915 'garbage following instruction' error message, which is
7916 probably less helpful than the current one. */
7917 if (backtrack_index
== i
&& backtrack_pos
!= str
7918 && upat
[i
+1] == OP_stop
)
7921 inst
.error
= BAD_SYNTAX
;
7925 /* Try again, skipping the optional argument at backtrack_pos. */
7926 str
= backtrack_pos
;
7927 inst
.error
= backtrack_error
;
7928 inst
.operands
[backtrack_index
].present
= 0;
7929 i
= backtrack_index
;
7933 /* Check that we have parsed all the arguments. */
7934 if (*str
!= '\0' && !inst
.error
)
7935 inst
.error
= _("garbage following instruction");
7937 return inst
.error
? FAIL
: SUCCESS
;
7940 #undef po_char_or_fail
7941 #undef po_reg_or_fail
7942 #undef po_reg_or_goto
7943 #undef po_imm_or_fail
7944 #undef po_scalar_or_fail
7945 #undef po_barrier_or_imm
7947 /* Shorthand macro for instruction encoding functions issuing errors. */
7948 #define constraint(expr, err) \
7959 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7960 instructions are unpredictable if these registers are used. This
7961 is the BadReg predicate in ARM's Thumb-2 documentation.
7963 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7964 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7965 #define reject_bad_reg(reg) \
7967 if (reg == REG_PC) \
7969 inst.error = BAD_PC; \
7972 else if (reg == REG_SP \
7973 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7975 inst.error = BAD_SP; \
7980 /* If REG is R13 (the stack pointer), warn that its use is
7982 #define warn_deprecated_sp(reg) \
7984 if (warn_on_deprecated && reg == REG_SP) \
7985 as_tsktsk (_("use of r13 is deprecated")); \
7988 /* Functions for operand encoding. ARM, then Thumb. */
7990 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7992 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7994 The only binary encoding difference is the Coprocessor number. Coprocessor
7995 9 is used for half-precision calculations or conversions. The format of the
7996 instruction is the same as the equivalent Coprocessor 10 instruction that
7997 exists for Single-Precision operation. */
8000 do_scalar_fp16_v82_encode (void)
8002 if (inst
.cond
< COND_ALWAYS
)
8003 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8004 " the behaviour is UNPREDICTABLE"));
8005 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8008 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8009 mark_feature_used (&arm_ext_fp16
);
8012 /* If VAL can be encoded in the immediate field of an ARM instruction,
8013 return the encoded form. Otherwise, return FAIL. */
8016 encode_arm_immediate (unsigned int val
)
8023 for (i
= 2; i
< 32; i
+= 2)
8024 if ((a
= rotate_left (val
, i
)) <= 0xff)
8025 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8030 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8031 return the encoded form. Otherwise, return FAIL. */
8033 encode_thumb32_immediate (unsigned int val
)
8040 for (i
= 1; i
<= 24; i
++)
8043 if ((val
& ~(0xff << i
)) == 0)
8044 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8048 if (val
== ((a
<< 16) | a
))
8050 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8054 if (val
== ((a
<< 16) | a
))
8055 return 0x200 | (a
>> 8);
8059 /* Encode a VFP SP or DP register number into inst.instruction. */
8062 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8064 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8067 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8070 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8073 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8078 first_error (_("D register out of range for selected VFP version"));
8086 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8090 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8094 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8098 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8102 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8106 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8114 /* Encode a <shift> in an ARM-format instruction. The immediate,
8115 if any, is handled by md_apply_fix. */
8117 encode_arm_shift (int i
)
8119 /* register-shifted register. */
8120 if (inst
.operands
[i
].immisreg
)
8123 for (op_index
= 0; op_index
<= i
; ++op_index
)
8125 /* Check the operand only when it's presented. In pre-UAL syntax,
8126 if the destination register is the same as the first operand, two
8127 register form of the instruction can be used. */
8128 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8129 && inst
.operands
[op_index
].reg
== REG_PC
)
8130 as_warn (UNPRED_REG ("r15"));
8133 if (inst
.operands
[i
].imm
== REG_PC
)
8134 as_warn (UNPRED_REG ("r15"));
8137 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8138 inst
.instruction
|= SHIFT_ROR
<< 5;
8141 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8142 if (inst
.operands
[i
].immisreg
)
8144 inst
.instruction
|= SHIFT_BY_REG
;
8145 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8148 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8153 encode_arm_shifter_operand (int i
)
8155 if (inst
.operands
[i
].isreg
)
8157 inst
.instruction
|= inst
.operands
[i
].reg
;
8158 encode_arm_shift (i
);
8162 inst
.instruction
|= INST_IMMEDIATE
;
8163 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8164 inst
.instruction
|= inst
.operands
[i
].imm
;
8168 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8170 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8173 Generate an error if the operand is not a register. */
8174 constraint (!inst
.operands
[i
].isreg
,
8175 _("Instruction does not support =N addresses"));
8177 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8179 if (inst
.operands
[i
].preind
)
8183 inst
.error
= _("instruction does not accept preindexed addressing");
8186 inst
.instruction
|= PRE_INDEX
;
8187 if (inst
.operands
[i
].writeback
)
8188 inst
.instruction
|= WRITE_BACK
;
8191 else if (inst
.operands
[i
].postind
)
8193 gas_assert (inst
.operands
[i
].writeback
);
8195 inst
.instruction
|= WRITE_BACK
;
8197 else /* unindexed - only for coprocessor */
8199 inst
.error
= _("instruction does not accept unindexed addressing");
8203 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8204 && (((inst
.instruction
& 0x000f0000) >> 16)
8205 == ((inst
.instruction
& 0x0000f000) >> 12)))
8206 as_warn ((inst
.instruction
& LOAD_BIT
)
8207 ? _("destination register same as write-back base")
8208 : _("source register same as write-back base"));
8211 /* inst.operands[i] was set up by parse_address. Encode it into an
8212 ARM-format mode 2 load or store instruction. If is_t is true,
8213 reject forms that cannot be used with a T instruction (i.e. not
8216 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8218 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8220 encode_arm_addr_mode_common (i
, is_t
);
8222 if (inst
.operands
[i
].immisreg
)
8224 constraint ((inst
.operands
[i
].imm
== REG_PC
8225 || (is_pc
&& inst
.operands
[i
].writeback
)),
8227 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8228 inst
.instruction
|= inst
.operands
[i
].imm
;
8229 if (!inst
.operands
[i
].negative
)
8230 inst
.instruction
|= INDEX_UP
;
8231 if (inst
.operands
[i
].shifted
)
8233 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8234 inst
.instruction
|= SHIFT_ROR
<< 5;
8237 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8238 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8242 else /* immediate offset in inst.relocs[0] */
8244 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8246 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8248 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8249 cannot use PC in addressing.
8250 PC cannot be used in writeback addressing, either. */
8251 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8254 /* Use of PC in str is deprecated for ARMv7. */
8255 if (warn_on_deprecated
8257 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8258 as_tsktsk (_("use of PC in this instruction is deprecated"));
8261 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8263 /* Prefer + for zero encoded value. */
8264 if (!inst
.operands
[i
].negative
)
8265 inst
.instruction
|= INDEX_UP
;
8266 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8271 /* inst.operands[i] was set up by parse_address. Encode it into an
8272 ARM-format mode 3 load or store instruction. Reject forms that
8273 cannot be used with such instructions. If is_t is true, reject
8274 forms that cannot be used with a T instruction (i.e. not
8277 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8279 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8281 inst
.error
= _("instruction does not accept scaled register index");
8285 encode_arm_addr_mode_common (i
, is_t
);
8287 if (inst
.operands
[i
].immisreg
)
8289 constraint ((inst
.operands
[i
].imm
== REG_PC
8290 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8292 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8294 inst
.instruction
|= inst
.operands
[i
].imm
;
8295 if (!inst
.operands
[i
].negative
)
8296 inst
.instruction
|= INDEX_UP
;
8298 else /* immediate offset in inst.relocs[0] */
8300 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8301 && inst
.operands
[i
].writeback
),
8303 inst
.instruction
|= HWOFFSET_IMM
;
8304 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8306 /* Prefer + for zero encoded value. */
8307 if (!inst
.operands
[i
].negative
)
8308 inst
.instruction
|= INDEX_UP
;
8310 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8315 /* Write immediate bits [7:0] to the following locations:
8317 |28/24|23 19|18 16|15 4|3 0|
8318 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8320 This function is used by VMOV/VMVN/VORR/VBIC. */
8323 neon_write_immbits (unsigned immbits
)
8325 inst
.instruction
|= immbits
& 0xf;
8326 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8327 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8330 /* Invert low-order SIZE bits of XHI:XLO. */
8333 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8335 unsigned immlo
= xlo
? *xlo
: 0;
8336 unsigned immhi
= xhi
? *xhi
: 0;
8341 immlo
= (~immlo
) & 0xff;
8345 immlo
= (~immlo
) & 0xffff;
8349 immhi
= (~immhi
) & 0xffffffff;
8353 immlo
= (~immlo
) & 0xffffffff;
8367 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8371 neon_bits_same_in_bytes (unsigned imm
)
8373 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8374 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8375 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8376 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8379 /* For immediate of above form, return 0bABCD. */
8382 neon_squash_bits (unsigned imm
)
8384 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8385 | ((imm
& 0x01000000) >> 21);
8388 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8391 neon_qfloat_bits (unsigned imm
)
8393 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8396 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8397 the instruction. *OP is passed as the initial value of the op field, and
8398 may be set to a different value depending on the constant (i.e.
8399 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8400 MVN). If the immediate looks like a repeated pattern then also
8401 try smaller element sizes. */
8404 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8405 unsigned *immbits
, int *op
, int size
,
8406 enum neon_el_type type
)
8408 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8410 if (type
== NT_float
&& !float_p
)
8413 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8415 if (size
!= 32 || *op
== 1)
8417 *immbits
= neon_qfloat_bits (immlo
);
8423 if (neon_bits_same_in_bytes (immhi
)
8424 && neon_bits_same_in_bytes (immlo
))
8428 *immbits
= (neon_squash_bits (immhi
) << 4)
8429 | neon_squash_bits (immlo
);
8440 if (immlo
== (immlo
& 0x000000ff))
8445 else if (immlo
== (immlo
& 0x0000ff00))
8447 *immbits
= immlo
>> 8;
8450 else if (immlo
== (immlo
& 0x00ff0000))
8452 *immbits
= immlo
>> 16;
8455 else if (immlo
== (immlo
& 0xff000000))
8457 *immbits
= immlo
>> 24;
8460 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8462 *immbits
= (immlo
>> 8) & 0xff;
8465 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8467 *immbits
= (immlo
>> 16) & 0xff;
8471 if ((immlo
& 0xffff) != (immlo
>> 16))
8478 if (immlo
== (immlo
& 0x000000ff))
8483 else if (immlo
== (immlo
& 0x0000ff00))
8485 *immbits
= immlo
>> 8;
8489 if ((immlo
& 0xff) != (immlo
>> 8))
8494 if (immlo
== (immlo
& 0x000000ff))
8496 /* Don't allow MVN with 8-bit immediate. */
8506 #if defined BFD_HOST_64_BIT
8507 /* Returns TRUE if double precision value V may be cast
8508 to single precision without loss of accuracy. */
8511 is_double_a_single (bfd_int64_t v
)
8513 int exp
= (int)((v
>> 52) & 0x7FF);
8514 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8516 return (exp
== 0 || exp
== 0x7FF
8517 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8518 && (mantissa
& 0x1FFFFFFFl
) == 0;
8521 /* Returns a double precision value casted to single precision
8522 (ignoring the least significant bits in exponent and mantissa). */
8525 double_to_single (bfd_int64_t v
)
8527 int sign
= (int) ((v
>> 63) & 1l);
8528 int exp
= (int) ((v
>> 52) & 0x7FF);
8529 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8535 exp
= exp
- 1023 + 127;
8544 /* No denormalized numbers. */
8550 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8552 #endif /* BFD_HOST_64_BIT */
8561 static void do_vfp_nsyn_opcode (const char *);
8563 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8564 Determine whether it can be performed with a move instruction; if
8565 it can, convert inst.instruction to that move instruction and
8566 return TRUE; if it can't, convert inst.instruction to a literal-pool
8567 load and return FALSE. If this is not a valid thing to do in the
8568 current context, set inst.error and return TRUE.
8570 inst.operands[i] describes the destination register. */
8573 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8576 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8577 bfd_boolean arm_p
= (t
== CONST_ARM
);
8580 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8584 if ((inst
.instruction
& tbit
) == 0)
8586 inst
.error
= _("invalid pseudo operation");
8590 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8591 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8592 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8594 inst
.error
= _("constant expression expected");
8598 if (inst
.relocs
[0].exp
.X_op
== O_constant
8599 || inst
.relocs
[0].exp
.X_op
== O_big
)
8601 #if defined BFD_HOST_64_BIT
8606 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8608 LITTLENUM_TYPE w
[X_PRECISION
];
8611 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8613 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8615 /* FIXME: Should we check words w[2..5] ? */
8620 #if defined BFD_HOST_64_BIT
8622 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8623 << LITTLENUM_NUMBER_OF_BITS
)
8624 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8625 << LITTLENUM_NUMBER_OF_BITS
)
8626 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8627 << LITTLENUM_NUMBER_OF_BITS
)
8628 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8630 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8631 | (l
[0] & LITTLENUM_MASK
);
8635 v
= inst
.relocs
[0].exp
.X_add_number
;
8637 if (!inst
.operands
[i
].issingle
)
8641 /* LDR should not use lead in a flag-setting instruction being
8642 chosen so we do not check whether movs can be used. */
8644 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8645 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8646 && inst
.operands
[i
].reg
!= 13
8647 && inst
.operands
[i
].reg
!= 15)
8649 /* Check if on thumb2 it can be done with a mov.w, mvn or
8650 movw instruction. */
8651 unsigned int newimm
;
8652 bfd_boolean isNegated
;
8654 newimm
= encode_thumb32_immediate (v
);
8655 if (newimm
!= (unsigned int) FAIL
)
8659 newimm
= encode_thumb32_immediate (~v
);
8660 if (newimm
!= (unsigned int) FAIL
)
8664 /* The number can be loaded with a mov.w or mvn
8666 if (newimm
!= (unsigned int) FAIL
8667 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8669 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8670 | (inst
.operands
[i
].reg
<< 8));
8671 /* Change to MOVN. */
8672 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8673 inst
.instruction
|= (newimm
& 0x800) << 15;
8674 inst
.instruction
|= (newimm
& 0x700) << 4;
8675 inst
.instruction
|= (newimm
& 0x0ff);
8678 /* The number can be loaded with a movw instruction. */
8679 else if ((v
& ~0xFFFF) == 0
8680 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8682 int imm
= v
& 0xFFFF;
8684 inst
.instruction
= 0xf2400000; /* MOVW. */
8685 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8686 inst
.instruction
|= (imm
& 0xf000) << 4;
8687 inst
.instruction
|= (imm
& 0x0800) << 15;
8688 inst
.instruction
|= (imm
& 0x0700) << 4;
8689 inst
.instruction
|= (imm
& 0x00ff);
8696 int value
= encode_arm_immediate (v
);
8700 /* This can be done with a mov instruction. */
8701 inst
.instruction
&= LITERAL_MASK
;
8702 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8703 inst
.instruction
|= value
& 0xfff;
8707 value
= encode_arm_immediate (~ v
);
8710 /* This can be done with a mvn instruction. */
8711 inst
.instruction
&= LITERAL_MASK
;
8712 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8713 inst
.instruction
|= value
& 0xfff;
8717 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8720 unsigned immbits
= 0;
8721 unsigned immlo
= inst
.operands
[1].imm
;
8722 unsigned immhi
= inst
.operands
[1].regisimm
8723 ? inst
.operands
[1].reg
8724 : inst
.relocs
[0].exp
.X_unsigned
8726 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8727 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8728 &op
, 64, NT_invtype
);
8732 neon_invert_size (&immlo
, &immhi
, 64);
8734 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8735 &op
, 64, NT_invtype
);
8740 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8746 /* Fill other bits in vmov encoding for both thumb and arm. */
8748 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8750 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8751 neon_write_immbits (immbits
);
8759 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8760 if (inst
.operands
[i
].issingle
8761 && is_quarter_float (inst
.operands
[1].imm
)
8762 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8764 inst
.operands
[1].imm
=
8765 neon_qfloat_bits (v
);
8766 do_vfp_nsyn_opcode ("fconsts");
8770 /* If our host does not support a 64-bit type then we cannot perform
8771 the following optimization. This mean that there will be a
8772 discrepancy between the output produced by an assembler built for
8773 a 32-bit-only host and the output produced from a 64-bit host, but
8774 this cannot be helped. */
8775 #if defined BFD_HOST_64_BIT
8776 else if (!inst
.operands
[1].issingle
8777 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8779 if (is_double_a_single (v
)
8780 && is_quarter_float (double_to_single (v
)))
8782 inst
.operands
[1].imm
=
8783 neon_qfloat_bits (double_to_single (v
));
8784 do_vfp_nsyn_opcode ("fconstd");
8792 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8793 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8796 inst
.operands
[1].reg
= REG_PC
;
8797 inst
.operands
[1].isreg
= 1;
8798 inst
.operands
[1].preind
= 1;
8799 inst
.relocs
[0].pc_rel
= 1;
8800 inst
.relocs
[0].type
= (thumb_p
8801 ? BFD_RELOC_ARM_THUMB_OFFSET
8803 ? BFD_RELOC_ARM_HWLITERAL
8804 : BFD_RELOC_ARM_LITERAL
));
8808 /* inst.operands[i] was set up by parse_address. Encode it into an
8809 ARM-format instruction. Reject all forms which cannot be encoded
8810 into a coprocessor load/store instruction. If wb_ok is false,
8811 reject use of writeback; if unind_ok is false, reject use of
8812 unindexed addressing. If reloc_override is not 0, use it instead
8813 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8814 (in which case it is preserved). */
8817 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8819 if (!inst
.operands
[i
].isreg
)
8822 if (! inst
.operands
[0].isvec
)
8824 inst
.error
= _("invalid co-processor operand");
8827 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8831 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8833 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8835 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8837 gas_assert (!inst
.operands
[i
].writeback
);
8840 inst
.error
= _("instruction does not support unindexed addressing");
8843 inst
.instruction
|= inst
.operands
[i
].imm
;
8844 inst
.instruction
|= INDEX_UP
;
8848 if (inst
.operands
[i
].preind
)
8849 inst
.instruction
|= PRE_INDEX
;
8851 if (inst
.operands
[i
].writeback
)
8853 if (inst
.operands
[i
].reg
== REG_PC
)
8855 inst
.error
= _("pc may not be used with write-back");
8860 inst
.error
= _("instruction does not support writeback");
8863 inst
.instruction
|= WRITE_BACK
;
8867 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8868 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8869 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8870 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8873 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8875 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8878 /* Prefer + for zero encoded value. */
8879 if (!inst
.operands
[i
].negative
)
8880 inst
.instruction
|= INDEX_UP
;
8885 /* Functions for instruction encoding, sorted by sub-architecture.
8886 First some generics; their names are taken from the conventional
8887 bit positions for register arguments in ARM format instructions. */
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8910 inst
.instruction
|= inst
.operands
[1].reg
;
8916 inst
.instruction
|= inst
.operands
[0].reg
;
8917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8930 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8931 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8937 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8938 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8942 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8944 if (ARM_CPU_IS_ANY (cpu_variant
))
8946 as_tsktsk ("%s", msg
);
8949 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8961 unsigned Rn
= inst
.operands
[2].reg
;
8962 /* Enforce restrictions on SWP instruction. */
8963 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8965 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8966 _("Rn must not overlap other operands"));
8968 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8970 if (!check_obsolete (&arm_ext_v8
,
8971 _("swp{b} use is obsoleted for ARMv8 and later"))
8972 && warn_on_deprecated
8973 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8974 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8978 inst
.instruction
|= inst
.operands
[1].reg
;
8979 inst
.instruction
|= Rn
<< 16;
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8986 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8987 inst
.instruction
|= inst
.operands
[2].reg
;
8993 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8994 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8995 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8996 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8998 inst
.instruction
|= inst
.operands
[0].reg
;
8999 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9000 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9006 inst
.instruction
|= inst
.operands
[0].imm
;
9012 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9013 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9016 /* ARM instructions, in alphabetical order by function name (except
9017 that wrapper functions appear immediately after the function they
9020 /* This is a pseudo-op of the form "adr rd, label" to be converted
9021 into a relative address of the form "add rd, pc, #label-.-8". */
9026 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9028 /* Frag hacking will turn this into a sub instruction if the offset turns
9029 out to be negative. */
9030 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9031 inst
.relocs
[0].pc_rel
= 1;
9032 inst
.relocs
[0].exp
.X_add_number
-= 8;
9034 if (support_interwork
9035 && inst
.relocs
[0].exp
.X_op
== O_symbol
9036 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9037 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9038 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9039 inst
.relocs
[0].exp
.X_add_number
|= 1;
9042 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9043 into a relative address of the form:
9044 add rd, pc, #low(label-.-8)"
9045 add rd, rd, #high(label-.-8)" */
9050 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9052 /* Frag hacking will turn this into a sub instruction if the offset turns
9053 out to be negative. */
9054 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9055 inst
.relocs
[0].pc_rel
= 1;
9056 inst
.size
= INSN_SIZE
* 2;
9057 inst
.relocs
[0].exp
.X_add_number
-= 8;
9059 if (support_interwork
9060 && inst
.relocs
[0].exp
.X_op
== O_symbol
9061 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9062 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9063 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9064 inst
.relocs
[0].exp
.X_add_number
|= 1;
9070 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9071 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9073 if (!inst
.operands
[1].present
)
9074 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9077 encode_arm_shifter_operand (2);
9083 if (inst
.operands
[0].present
)
9084 inst
.instruction
|= inst
.operands
[0].imm
;
9086 inst
.instruction
|= 0xf;
9092 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9093 constraint (msb
> 32, _("bit-field extends past end of register"));
9094 /* The instruction encoding stores the LSB and MSB,
9095 not the LSB and width. */
9096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9097 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9098 inst
.instruction
|= (msb
- 1) << 16;
9106 /* #0 in second position is alternative syntax for bfc, which is
9107 the same instruction but with REG_PC in the Rm field. */
9108 if (!inst
.operands
[1].isreg
)
9109 inst
.operands
[1].reg
= REG_PC
;
9111 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9112 constraint (msb
> 32, _("bit-field extends past end of register"));
9113 /* The instruction encoding stores the LSB and MSB,
9114 not the LSB and width. */
9115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9116 inst
.instruction
|= inst
.operands
[1].reg
;
9117 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9118 inst
.instruction
|= (msb
- 1) << 16;
9124 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9125 _("bit-field extends past end of register"));
9126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9127 inst
.instruction
|= inst
.operands
[1].reg
;
9128 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9129 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9132 /* ARM V5 breakpoint instruction (argument parse)
9133 BKPT <16 bit unsigned immediate>
9134 Instruction is not conditional.
9135 The bit pattern given in insns[] has the COND_ALWAYS condition,
9136 and it is an error if the caller tried to override that. */
9141 /* Top 12 of 16 bits to bits 19:8. */
9142 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9144 /* Bottom 4 of 16 bits to bits 3:0. */
9145 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9149 encode_branch (int default_reloc
)
9151 if (inst
.operands
[0].hasreloc
)
9153 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9154 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9155 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9156 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9157 ? BFD_RELOC_ARM_PLT32
9158 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9161 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9162 inst
.relocs
[0].pc_rel
= 1;
9169 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9170 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9173 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9180 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9182 if (inst
.cond
== COND_ALWAYS
)
9183 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9185 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9189 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9192 /* ARM V5 branch-link-exchange instruction (argument parse)
9193 BLX <target_addr> ie BLX(1)
9194 BLX{<condition>} <Rm> ie BLX(2)
9195 Unfortunately, there are two different opcodes for this mnemonic.
9196 So, the insns[].value is not used, and the code here zaps values
9197 into inst.instruction.
9198 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9203 if (inst
.operands
[0].isreg
)
9205 /* Arg is a register; the opcode provided by insns[] is correct.
9206 It is not illegal to do "blx pc", just useless. */
9207 if (inst
.operands
[0].reg
== REG_PC
)
9208 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9210 inst
.instruction
|= inst
.operands
[0].reg
;
9214 /* Arg is an address; this instruction cannot be executed
9215 conditionally, and the opcode must be adjusted.
9216 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9217 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9218 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9219 inst
.instruction
= 0xfa000000;
9220 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9227 bfd_boolean want_reloc
;
9229 if (inst
.operands
[0].reg
== REG_PC
)
9230 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9232 inst
.instruction
|= inst
.operands
[0].reg
;
9233 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9234 it is for ARMv4t or earlier. */
9235 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9236 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9237 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9241 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9246 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9250 /* ARM v5TEJ. Jump to Jazelle code. */
9255 if (inst
.operands
[0].reg
== REG_PC
)
9256 as_tsktsk (_("use of r15 in bxj is not really useful"));
9258 inst
.instruction
|= inst
.operands
[0].reg
;
9261 /* Co-processor data operation:
9262 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9263 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9267 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9268 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9269 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9270 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9271 inst
.instruction
|= inst
.operands
[4].reg
;
9272 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9278 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9279 encode_arm_shifter_operand (1);
9282 /* Transfer between coprocessor and ARM registers.
9283 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9288 No special properties. */
9290 struct deprecated_coproc_regs_s
9297 arm_feature_set deprecated
;
9298 arm_feature_set obsoleted
;
9299 const char *dep_msg
;
9300 const char *obs_msg
;
9303 #define DEPR_ACCESS_V8 \
9304 N_("This coprocessor register access is deprecated in ARMv8")
9306 /* Table of all deprecated coprocessor registers. */
9307 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9309 {15, 0, 7, 10, 5, /* CP15DMB. */
9310 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9311 DEPR_ACCESS_V8
, NULL
},
9312 {15, 0, 7, 10, 4, /* CP15DSB. */
9313 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9314 DEPR_ACCESS_V8
, NULL
},
9315 {15, 0, 7, 5, 4, /* CP15ISB. */
9316 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9317 DEPR_ACCESS_V8
, NULL
},
9318 {14, 6, 1, 0, 0, /* TEEHBR. */
9319 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9320 DEPR_ACCESS_V8
, NULL
},
9321 {14, 6, 0, 0, 0, /* TEECR. */
9322 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9323 DEPR_ACCESS_V8
, NULL
},
9326 #undef DEPR_ACCESS_V8
9328 static const size_t deprecated_coproc_reg_count
=
9329 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9337 Rd
= inst
.operands
[2].reg
;
9340 if (inst
.instruction
== 0xee000010
9341 || inst
.instruction
== 0xfe000010)
9343 reject_bad_reg (Rd
);
9344 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9346 constraint (Rd
== REG_SP
, BAD_SP
);
9351 if (inst
.instruction
== 0xe000010)
9352 constraint (Rd
== REG_PC
, BAD_PC
);
9355 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9357 const struct deprecated_coproc_regs_s
*r
=
9358 deprecated_coproc_regs
+ i
;
9360 if (inst
.operands
[0].reg
== r
->cp
9361 && inst
.operands
[1].imm
== r
->opc1
9362 && inst
.operands
[3].reg
== r
->crn
9363 && inst
.operands
[4].reg
== r
->crm
9364 && inst
.operands
[5].imm
== r
->opc2
)
9366 if (! ARM_CPU_IS_ANY (cpu_variant
)
9367 && warn_on_deprecated
9368 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9369 as_tsktsk ("%s", r
->dep_msg
);
9373 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9374 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9375 inst
.instruction
|= Rd
<< 12;
9376 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9377 inst
.instruction
|= inst
.operands
[4].reg
;
9378 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9381 /* Transfer between coprocessor register and pair of ARM registers.
9382 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9387 Two XScale instructions are special cases of these:
9389 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9390 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9392 Result unpredictable if Rd or Rn is R15. */
9399 Rd
= inst
.operands
[2].reg
;
9400 Rn
= inst
.operands
[3].reg
;
9404 reject_bad_reg (Rd
);
9405 reject_bad_reg (Rn
);
9409 constraint (Rd
== REG_PC
, BAD_PC
);
9410 constraint (Rn
== REG_PC
, BAD_PC
);
9413 /* Only check the MRRC{2} variants. */
9414 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9416 /* If Rd == Rn, error that the operation is
9417 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9418 constraint (Rd
== Rn
, BAD_OVERLAP
);
9421 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9422 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9423 inst
.instruction
|= Rd
<< 12;
9424 inst
.instruction
|= Rn
<< 16;
9425 inst
.instruction
|= inst
.operands
[4].reg
;
9431 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9432 if (inst
.operands
[1].present
)
9434 inst
.instruction
|= CPSI_MMOD
;
9435 inst
.instruction
|= inst
.operands
[1].imm
;
9442 inst
.instruction
|= inst
.operands
[0].imm
;
9448 unsigned Rd
, Rn
, Rm
;
9450 Rd
= inst
.operands
[0].reg
;
9451 Rn
= (inst
.operands
[1].present
9452 ? inst
.operands
[1].reg
: Rd
);
9453 Rm
= inst
.operands
[2].reg
;
9455 constraint ((Rd
== REG_PC
), BAD_PC
);
9456 constraint ((Rn
== REG_PC
), BAD_PC
);
9457 constraint ((Rm
== REG_PC
), BAD_PC
);
9459 inst
.instruction
|= Rd
<< 16;
9460 inst
.instruction
|= Rn
<< 0;
9461 inst
.instruction
|= Rm
<< 8;
9467 /* There is no IT instruction in ARM mode. We
9468 process it to do the validation as if in
9469 thumb mode, just in case the code gets
9470 assembled for thumb using the unified syntax. */
9475 set_pred_insn_type (IT_INSN
);
9476 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9477 now_pred
.cc
= inst
.operands
[0].imm
;
9481 /* If there is only one register in the register list,
9482 then return its register number. Otherwise return -1. */
9484 only_one_reg_in_list (int range
)
9486 int i
= ffs (range
) - 1;
9487 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9491 encode_ldmstm(int from_push_pop_mnem
)
9493 int base_reg
= inst
.operands
[0].reg
;
9494 int range
= inst
.operands
[1].imm
;
9497 inst
.instruction
|= base_reg
<< 16;
9498 inst
.instruction
|= range
;
9500 if (inst
.operands
[1].writeback
)
9501 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9503 if (inst
.operands
[0].writeback
)
9505 inst
.instruction
|= WRITE_BACK
;
9506 /* Check for unpredictable uses of writeback. */
9507 if (inst
.instruction
& LOAD_BIT
)
9509 /* Not allowed in LDM type 2. */
9510 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9511 && ((range
& (1 << REG_PC
)) == 0))
9512 as_warn (_("writeback of base register is UNPREDICTABLE"));
9513 /* Only allowed if base reg not in list for other types. */
9514 else if (range
& (1 << base_reg
))
9515 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9519 /* Not allowed for type 2. */
9520 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9521 as_warn (_("writeback of base register is UNPREDICTABLE"));
9522 /* Only allowed if base reg not in list, or first in list. */
9523 else if ((range
& (1 << base_reg
))
9524 && (range
& ((1 << base_reg
) - 1)))
9525 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9529 /* If PUSH/POP has only one register, then use the A2 encoding. */
9530 one_reg
= only_one_reg_in_list (range
);
9531 if (from_push_pop_mnem
&& one_reg
>= 0)
9533 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9535 if (is_push
&& one_reg
== 13 /* SP */)
9536 /* PR 22483: The A2 encoding cannot be used when
9537 pushing the stack pointer as this is UNPREDICTABLE. */
9540 inst
.instruction
&= A_COND_MASK
;
9541 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9542 inst
.instruction
|= one_reg
<< 12;
9549 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9552 /* ARMv5TE load-consecutive (argument parse)
9561 constraint (inst
.operands
[0].reg
% 2 != 0,
9562 _("first transfer register must be even"));
9563 constraint (inst
.operands
[1].present
9564 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9565 _("can only transfer two consecutive registers"));
9566 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9567 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9569 if (!inst
.operands
[1].present
)
9570 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9572 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9573 register and the first register written; we have to diagnose
9574 overlap between the base and the second register written here. */
9576 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9577 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9578 as_warn (_("base register written back, and overlaps "
9579 "second transfer register"));
9581 if (!(inst
.instruction
& V4_STR_BIT
))
9583 /* For an index-register load, the index register must not overlap the
9584 destination (even if not write-back). */
9585 if (inst
.operands
[2].immisreg
9586 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9587 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9588 as_warn (_("index register overlaps transfer register"));
9590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9591 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9597 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9598 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9599 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9600 || inst
.operands
[1].negative
9601 /* This can arise if the programmer has written
9603 or if they have mistakenly used a register name as the last
9606 It is very difficult to distinguish between these two cases
9607 because "rX" might actually be a label. ie the register
9608 name has been occluded by a symbol of the same name. So we
9609 just generate a general 'bad addressing mode' type error
9610 message and leave it up to the programmer to discover the
9611 true cause and fix their mistake. */
9612 || (inst
.operands
[1].reg
== REG_PC
),
9615 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9616 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9617 _("offset must be zero in ARM encoding"));
9619 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9621 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9622 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9623 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9629 constraint (inst
.operands
[0].reg
% 2 != 0,
9630 _("even register required"));
9631 constraint (inst
.operands
[1].present
9632 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9633 _("can only load two consecutive registers"));
9634 /* If op 1 were present and equal to PC, this function wouldn't
9635 have been called in the first place. */
9636 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9638 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9639 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9642 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9643 which is not a multiple of four is UNPREDICTABLE. */
9645 check_ldr_r15_aligned (void)
9647 constraint (!(inst
.operands
[1].immisreg
)
9648 && (inst
.operands
[0].reg
== REG_PC
9649 && inst
.operands
[1].reg
== REG_PC
9650 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9651 _("ldr to register 15 must be 4-byte aligned"));
9657 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9658 if (!inst
.operands
[1].isreg
)
9659 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9661 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9662 check_ldr_r15_aligned ();
9668 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9670 if (inst
.operands
[1].preind
)
9672 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9673 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9674 _("this instruction requires a post-indexed address"));
9676 inst
.operands
[1].preind
= 0;
9677 inst
.operands
[1].postind
= 1;
9678 inst
.operands
[1].writeback
= 1;
9680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9681 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9684 /* Halfword and signed-byte load/store operations. */
9689 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9690 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9691 if (!inst
.operands
[1].isreg
)
9692 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9694 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9700 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9702 if (inst
.operands
[1].preind
)
9704 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9705 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9706 _("this instruction requires a post-indexed address"));
9708 inst
.operands
[1].preind
= 0;
9709 inst
.operands
[1].postind
= 1;
9710 inst
.operands
[1].writeback
= 1;
9712 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9713 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9716 /* Co-processor register load/store.
9717 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9722 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9723 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9729 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9730 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9731 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9732 && !(inst
.instruction
& 0x00400000))
9733 as_tsktsk (_("Rd and Rm should be different in mla"));
9735 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9736 inst
.instruction
|= inst
.operands
[1].reg
;
9737 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9738 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9744 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9745 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9747 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9748 encode_arm_shifter_operand (1);
9751 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9758 top
= (inst
.instruction
& 0x00400000) != 0;
9759 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9760 _(":lower16: not allowed in this instruction"));
9761 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9762 _(":upper16: not allowed in this instruction"));
9763 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9764 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9766 imm
= inst
.relocs
[0].exp
.X_add_number
;
9767 /* The value is in two pieces: 0:11, 16:19. */
9768 inst
.instruction
|= (imm
& 0x00000fff);
9769 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9774 do_vfp_nsyn_mrs (void)
9776 if (inst
.operands
[0].isvec
)
9778 if (inst
.operands
[1].reg
!= 1)
9779 first_error (_("operand 1 must be FPSCR"));
9780 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9781 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9782 do_vfp_nsyn_opcode ("fmstat");
9784 else if (inst
.operands
[1].isvec
)
9785 do_vfp_nsyn_opcode ("fmrx");
9793 do_vfp_nsyn_msr (void)
9795 if (inst
.operands
[0].isvec
)
9796 do_vfp_nsyn_opcode ("fmxr");
9806 unsigned Rt
= inst
.operands
[0].reg
;
9808 if (thumb_mode
&& Rt
== REG_SP
)
9810 inst
.error
= BAD_SP
;
9814 /* MVFR2 is only valid at ARMv8-A. */
9815 if (inst
.operands
[1].reg
== 5)
9816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9819 /* APSR_ sets isvec. All other refs to PC are illegal. */
9820 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9822 inst
.error
= BAD_PC
;
9826 /* If we get through parsing the register name, we just insert the number
9827 generated into the instruction without further validation. */
9828 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9829 inst
.instruction
|= (Rt
<< 12);
9835 unsigned Rt
= inst
.operands
[1].reg
;
9838 reject_bad_reg (Rt
);
9839 else if (Rt
== REG_PC
)
9841 inst
.error
= BAD_PC
;
9845 /* MVFR2 is only valid for ARMv8-A. */
9846 if (inst
.operands
[0].reg
== 5)
9847 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9850 /* If we get through parsing the register name, we just insert the number
9851 generated into the instruction without further validation. */
9852 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9853 inst
.instruction
|= (Rt
<< 12);
9861 if (do_vfp_nsyn_mrs () == SUCCESS
)
9864 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9865 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9867 if (inst
.operands
[1].isreg
)
9869 br
= inst
.operands
[1].reg
;
9870 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9871 as_bad (_("bad register for mrs"));
9875 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9876 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9878 _("'APSR', 'CPSR' or 'SPSR' expected"));
9879 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9882 inst
.instruction
|= br
;
9885 /* Two possible forms:
9886 "{C|S}PSR_<field>, Rm",
9887 "{C|S}PSR_f, #expression". */
9892 if (do_vfp_nsyn_msr () == SUCCESS
)
9895 inst
.instruction
|= inst
.operands
[0].imm
;
9896 if (inst
.operands
[1].isreg
)
9897 inst
.instruction
|= inst
.operands
[1].reg
;
9900 inst
.instruction
|= INST_IMMEDIATE
;
9901 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9902 inst
.relocs
[0].pc_rel
= 0;
9909 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9911 if (!inst
.operands
[2].present
)
9912 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9913 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9914 inst
.instruction
|= inst
.operands
[1].reg
;
9915 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9917 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9918 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9919 as_tsktsk (_("Rd and Rm should be different in mul"));
9922 /* Long Multiply Parser
9923 UMULL RdLo, RdHi, Rm, Rs
9924 SMULL RdLo, RdHi, Rm, Rs
9925 UMLAL RdLo, RdHi, Rm, Rs
9926 SMLAL RdLo, RdHi, Rm, Rs. */
9931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9932 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9933 inst
.instruction
|= inst
.operands
[2].reg
;
9934 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9936 /* rdhi and rdlo must be different. */
9937 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9938 as_tsktsk (_("rdhi and rdlo must be different"));
9940 /* rdhi, rdlo and rm must all be different before armv6. */
9941 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9942 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9943 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9944 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9950 if (inst
.operands
[0].present
9951 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9953 /* Architectural NOP hints are CPSR sets with no bits selected. */
9954 inst
.instruction
&= 0xf0000000;
9955 inst
.instruction
|= 0x0320f000;
9956 if (inst
.operands
[0].present
)
9957 inst
.instruction
|= inst
.operands
[0].imm
;
9961 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9962 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9963 Condition defaults to COND_ALWAYS.
9964 Error if Rd, Rn or Rm are R15. */
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9971 inst
.instruction
|= inst
.operands
[2].reg
;
9972 if (inst
.operands
[3].present
)
9973 encode_arm_shift (3);
9976 /* ARM V6 PKHTB (Argument Parse). */
9981 if (!inst
.operands
[3].present
)
9983 /* If the shift specifier is omitted, turn the instruction
9984 into pkhbt rd, rm, rn. */
9985 inst
.instruction
&= 0xfff00010;
9986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9987 inst
.instruction
|= inst
.operands
[1].reg
;
9988 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9994 inst
.instruction
|= inst
.operands
[2].reg
;
9995 encode_arm_shift (3);
9999 /* ARMv5TE: Preload-Cache
10000 MP Extensions: Preload for write
10004 Syntactically, like LDR with B=1, W=0, L=1. */
10009 constraint (!inst
.operands
[0].isreg
,
10010 _("'[' expected after PLD mnemonic"));
10011 constraint (inst
.operands
[0].postind
,
10012 _("post-indexed expression used in preload instruction"));
10013 constraint (inst
.operands
[0].writeback
,
10014 _("writeback used in preload instruction"));
10015 constraint (!inst
.operands
[0].preind
,
10016 _("unindexed addressing used in preload instruction"));
10017 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10020 /* ARMv7: PLI <addr_mode> */
10024 constraint (!inst
.operands
[0].isreg
,
10025 _("'[' expected after PLI mnemonic"));
10026 constraint (inst
.operands
[0].postind
,
10027 _("post-indexed expression used in preload instruction"));
10028 constraint (inst
.operands
[0].writeback
,
10029 _("writeback used in preload instruction"));
10030 constraint (!inst
.operands
[0].preind
,
10031 _("unindexed addressing used in preload instruction"));
10032 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10033 inst
.instruction
&= ~PRE_INDEX
;
10039 constraint (inst
.operands
[0].writeback
,
10040 _("push/pop do not support {reglist}^"));
10041 inst
.operands
[1] = inst
.operands
[0];
10042 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10043 inst
.operands
[0].isreg
= 1;
10044 inst
.operands
[0].writeback
= 1;
10045 inst
.operands
[0].reg
= REG_SP
;
10046 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10049 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10050 word at the specified address and the following word
10052 Unconditionally executed.
10053 Error if Rn is R15. */
10058 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10059 if (inst
.operands
[0].writeback
)
10060 inst
.instruction
|= WRITE_BACK
;
10063 /* ARM V6 ssat (argument parse). */
10068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10069 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10070 inst
.instruction
|= inst
.operands
[2].reg
;
10072 if (inst
.operands
[3].present
)
10073 encode_arm_shift (3);
10076 /* ARM V6 usat (argument parse). */
10081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10082 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10083 inst
.instruction
|= inst
.operands
[2].reg
;
10085 if (inst
.operands
[3].present
)
10086 encode_arm_shift (3);
10089 /* ARM V6 ssat16 (argument parse). */
10094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10095 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10096 inst
.instruction
|= inst
.operands
[2].reg
;
10102 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10103 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10104 inst
.instruction
|= inst
.operands
[2].reg
;
10107 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10108 preserving the other bits.
10110 setend <endian_specifier>, where <endian_specifier> is either
10116 if (warn_on_deprecated
10117 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10118 as_tsktsk (_("setend use is deprecated for ARMv8"));
10120 if (inst
.operands
[0].imm
)
10121 inst
.instruction
|= 0x200;
10127 unsigned int Rm
= (inst
.operands
[1].present
10128 ? inst
.operands
[1].reg
10129 : inst
.operands
[0].reg
);
10131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10132 inst
.instruction
|= Rm
;
10133 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10135 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10136 inst
.instruction
|= SHIFT_BY_REG
;
10137 /* PR 12854: Error on extraneous shifts. */
10138 constraint (inst
.operands
[2].shifted
,
10139 _("extraneous shift as part of operand to shift insn"));
10142 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10148 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10149 inst
.relocs
[0].pc_rel
= 0;
10155 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10156 inst
.relocs
[0].pc_rel
= 0;
10162 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10163 inst
.relocs
[0].pc_rel
= 0;
10169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10170 _("selected processor does not support SETPAN instruction"));
10172 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10179 _("selected processor does not support SETPAN instruction"));
10181 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10184 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10185 SMLAxy{cond} Rd,Rm,Rs,Rn
10186 SMLAWy{cond} Rd,Rm,Rs,Rn
10187 Error if any register is R15. */
10192 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10193 inst
.instruction
|= inst
.operands
[1].reg
;
10194 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10195 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10198 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10199 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10200 Error if any register is R15.
10201 Warning if Rdlo == Rdhi. */
10206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10208 inst
.instruction
|= inst
.operands
[2].reg
;
10209 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10211 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10212 as_tsktsk (_("rdhi and rdlo must be different"));
10215 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10216 SMULxy{cond} Rd,Rm,Rs
10217 Error if any register is R15. */
10222 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10223 inst
.instruction
|= inst
.operands
[1].reg
;
10224 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10227 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10228 the same for both ARM and Thumb-2. */
10235 if (inst
.operands
[0].present
)
10237 reg
= inst
.operands
[0].reg
;
10238 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10243 inst
.instruction
|= reg
<< 16;
10244 inst
.instruction
|= inst
.operands
[1].imm
;
10245 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10246 inst
.instruction
|= WRITE_BACK
;
10249 /* ARM V6 strex (argument parse). */
10254 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10255 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10256 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10257 || inst
.operands
[2].negative
10258 /* See comment in do_ldrex(). */
10259 || (inst
.operands
[2].reg
== REG_PC
),
10262 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10263 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10265 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10266 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10267 _("offset must be zero in ARM encoding"));
10269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10270 inst
.instruction
|= inst
.operands
[1].reg
;
10271 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10272 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10276 do_t_strexbh (void)
10278 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10279 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10280 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10281 || inst
.operands
[2].negative
,
10284 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10285 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10293 constraint (inst
.operands
[1].reg
% 2 != 0,
10294 _("even register required"));
10295 constraint (inst
.operands
[2].present
10296 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10297 _("can only store two consecutive registers"));
10298 /* If op 2 were present and equal to PC, this function wouldn't
10299 have been called in the first place. */
10300 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10302 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10303 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10304 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10308 inst
.instruction
|= inst
.operands
[1].reg
;
10309 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10316 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10317 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10326 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10331 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10332 extends it to 32-bits, and adds the result to a value in another
10333 register. You can specify a rotation by 0, 8, 16, or 24 bits
10334 before extracting the 16-bit value.
10335 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10336 Condition defaults to COND_ALWAYS.
10337 Error if any register uses R15. */
10342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10343 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10344 inst
.instruction
|= inst
.operands
[2].reg
;
10345 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10350 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10351 Condition defaults to COND_ALWAYS.
10352 Error if any register uses R15. */
10357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10358 inst
.instruction
|= inst
.operands
[1].reg
;
10359 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10362 /* VFP instructions. In a logical order: SP variant first, monad
10363 before dyad, arithmetic then move then load/store. */
10366 do_vfp_sp_monadic (void)
10368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10369 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10372 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10373 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10377 do_vfp_sp_dyadic (void)
10379 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10380 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10381 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10385 do_vfp_sp_compare_z (void)
10387 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10391 do_vfp_dp_sp_cvt (void)
10393 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10394 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10398 do_vfp_sp_dp_cvt (void)
10400 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10401 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10405 do_vfp_reg_from_sp (void)
10407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10408 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10412 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10416 do_vfp_reg2_from_sp2 (void)
10418 constraint (inst
.operands
[2].imm
!= 2,
10419 _("only two consecutive VFP SP registers allowed here"));
10420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10421 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10422 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10426 do_vfp_sp_from_reg (void)
10428 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10429 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10432 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10433 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10437 do_vfp_sp2_from_reg2 (void)
10439 constraint (inst
.operands
[0].imm
!= 2,
10440 _("only two consecutive VFP SP registers allowed here"));
10441 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10442 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10443 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10447 do_vfp_sp_ldst (void)
10449 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10450 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10454 do_vfp_dp_ldst (void)
10456 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10457 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10462 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10464 if (inst
.operands
[0].writeback
)
10465 inst
.instruction
|= WRITE_BACK
;
10467 constraint (ldstm_type
!= VFP_LDSTMIA
,
10468 _("this addressing mode requires base-register writeback"));
10469 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10470 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10471 inst
.instruction
|= inst
.operands
[1].imm
;
10475 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10479 if (inst
.operands
[0].writeback
)
10480 inst
.instruction
|= WRITE_BACK
;
10482 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10483 _("this addressing mode requires base-register writeback"));
10485 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10486 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10488 count
= inst
.operands
[1].imm
<< 1;
10489 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10492 inst
.instruction
|= count
;
10496 do_vfp_sp_ldstmia (void)
10498 vfp_sp_ldstm (VFP_LDSTMIA
);
10502 do_vfp_sp_ldstmdb (void)
10504 vfp_sp_ldstm (VFP_LDSTMDB
);
10508 do_vfp_dp_ldstmia (void)
10510 vfp_dp_ldstm (VFP_LDSTMIA
);
10514 do_vfp_dp_ldstmdb (void)
10516 vfp_dp_ldstm (VFP_LDSTMDB
);
10520 do_vfp_xp_ldstmia (void)
10522 vfp_dp_ldstm (VFP_LDSTMIAX
);
10526 do_vfp_xp_ldstmdb (void)
10528 vfp_dp_ldstm (VFP_LDSTMDBX
);
10532 do_vfp_dp_rd_rm (void)
10534 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10535 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10538 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10539 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10543 do_vfp_dp_rn_rd (void)
10545 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10546 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10550 do_vfp_dp_rd_rn (void)
10552 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10553 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10557 do_vfp_dp_rd_rn_rm (void)
10559 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10560 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10563 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10564 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10565 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10569 do_vfp_dp_rd (void)
10571 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10575 do_vfp_dp_rm_rd_rn (void)
10577 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10578 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10581 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10582 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10583 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10586 /* VFPv3 instructions. */
10588 do_vfp_sp_const (void)
10590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10591 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10592 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10596 do_vfp_dp_const (void)
10598 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10599 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10600 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10604 vfp_conv (int srcsize
)
10606 int immbits
= srcsize
- inst
.operands
[1].imm
;
10608 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10610 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10611 i.e. immbits must be in range 0 - 16. */
10612 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10615 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10617 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10618 i.e. immbits must be in range 0 - 31. */
10619 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10623 inst
.instruction
|= (immbits
& 1) << 5;
10624 inst
.instruction
|= (immbits
>> 1);
10628 do_vfp_sp_conv_16 (void)
10630 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10635 do_vfp_dp_conv_16 (void)
10637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10642 do_vfp_sp_conv_32 (void)
10644 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10649 do_vfp_dp_conv_32 (void)
10651 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10655 /* FPA instructions. Also in a logical order. */
10660 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10661 inst
.instruction
|= inst
.operands
[1].reg
;
10665 do_fpa_ldmstm (void)
10667 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10668 switch (inst
.operands
[1].imm
)
10670 case 1: inst
.instruction
|= CP_T_X
; break;
10671 case 2: inst
.instruction
|= CP_T_Y
; break;
10672 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10677 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10679 /* The instruction specified "ea" or "fd", so we can only accept
10680 [Rn]{!}. The instruction does not really support stacking or
10681 unstacking, so we have to emulate these by setting appropriate
10682 bits and offsets. */
10683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10684 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10685 _("this instruction does not support indexing"));
10687 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10688 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10690 if (!(inst
.instruction
& INDEX_UP
))
10691 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10693 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10695 inst
.operands
[2].preind
= 0;
10696 inst
.operands
[2].postind
= 1;
10700 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10703 /* iWMMXt instructions: strictly in alphabetical order. */
10706 do_iwmmxt_tandorc (void)
10708 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10712 do_iwmmxt_textrc (void)
10714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10715 inst
.instruction
|= inst
.operands
[1].imm
;
10719 do_iwmmxt_textrm (void)
10721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10722 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10723 inst
.instruction
|= inst
.operands
[2].imm
;
10727 do_iwmmxt_tinsr (void)
10729 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10730 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10731 inst
.instruction
|= inst
.operands
[2].imm
;
10735 do_iwmmxt_tmia (void)
10737 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10738 inst
.instruction
|= inst
.operands
[1].reg
;
10739 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10743 do_iwmmxt_waligni (void)
10745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10746 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10747 inst
.instruction
|= inst
.operands
[2].reg
;
10748 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10752 do_iwmmxt_wmerge (void)
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10755 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10756 inst
.instruction
|= inst
.operands
[2].reg
;
10757 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10761 do_iwmmxt_wmov (void)
10763 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10765 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10766 inst
.instruction
|= inst
.operands
[1].reg
;
10770 do_iwmmxt_wldstbh (void)
10773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10775 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10777 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10778 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10782 do_iwmmxt_wldstw (void)
10784 /* RIWR_RIWC clears .isreg for a control register. */
10785 if (!inst
.operands
[0].isreg
)
10787 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10788 inst
.instruction
|= 0xf0000000;
10791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10792 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10796 do_iwmmxt_wldstd (void)
10798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10799 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10800 && inst
.operands
[1].immisreg
)
10802 inst
.instruction
&= ~0x1a000ff;
10803 inst
.instruction
|= (0xfU
<< 28);
10804 if (inst
.operands
[1].preind
)
10805 inst
.instruction
|= PRE_INDEX
;
10806 if (!inst
.operands
[1].negative
)
10807 inst
.instruction
|= INDEX_UP
;
10808 if (inst
.operands
[1].writeback
)
10809 inst
.instruction
|= WRITE_BACK
;
10810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10811 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10812 inst
.instruction
|= inst
.operands
[1].imm
;
10815 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10819 do_iwmmxt_wshufh (void)
10821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10822 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10823 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10824 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10828 do_iwmmxt_wzero (void)
10830 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10831 inst
.instruction
|= inst
.operands
[0].reg
;
10832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10833 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10837 do_iwmmxt_wrwrwr_or_imm5 (void)
10839 if (inst
.operands
[2].isreg
)
10842 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10843 _("immediate operand requires iWMMXt2"));
10845 if (inst
.operands
[2].imm
== 0)
10847 switch ((inst
.instruction
>> 20) & 0xf)
10853 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10854 inst
.operands
[2].imm
= 16;
10855 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10861 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10862 inst
.operands
[2].imm
= 32;
10863 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10870 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10872 wrn
= (inst
.instruction
>> 16) & 0xf;
10873 inst
.instruction
&= 0xff0fff0f;
10874 inst
.instruction
|= wrn
;
10875 /* Bail out here; the instruction is now assembled. */
10880 /* Map 32 -> 0, etc. */
10881 inst
.operands
[2].imm
&= 0x1f;
10882 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10886 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10887 operations first, then control, shift, and load/store. */
10889 /* Insns like "foo X,Y,Z". */
10892 do_mav_triple (void)
10894 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10895 inst
.instruction
|= inst
.operands
[1].reg
;
10896 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10899 /* Insns like "foo W,X,Y,Z".
10900 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10905 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10906 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10907 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10908 inst
.instruction
|= inst
.operands
[3].reg
;
10911 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10913 do_mav_dspsc (void)
10915 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10918 /* Maverick shift immediate instructions.
10919 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10920 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10923 do_mav_shift (void)
10925 int imm
= inst
.operands
[2].imm
;
10927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10930 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10931 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10932 Bit 4 should be 0. */
10933 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10935 inst
.instruction
|= imm
;
10938 /* XScale instructions. Also sorted arithmetic before move. */
10940 /* Xscale multiply-accumulate (argument parse)
10943 MIAxycc acc0,Rm,Rs. */
10948 inst
.instruction
|= inst
.operands
[1].reg
;
10949 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10952 /* Xscale move-accumulator-register (argument parse)
10954 MARcc acc0,RdLo,RdHi. */
10959 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10960 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10963 /* Xscale move-register-accumulator (argument parse)
10965 MRAcc RdLo,RdHi,acc0. */
10970 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10972 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10975 /* Encoding functions relevant only to Thumb. */
10977 /* inst.operands[i] is a shifted-register operand; encode
10978 it into inst.instruction in the format used by Thumb32. */
10981 encode_thumb32_shifted_operand (int i
)
10983 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10984 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10986 constraint (inst
.operands
[i
].immisreg
,
10987 _("shift by register not allowed in thumb mode"));
10988 inst
.instruction
|= inst
.operands
[i
].reg
;
10989 if (shift
== SHIFT_RRX
)
10990 inst
.instruction
|= SHIFT_ROR
<< 4;
10993 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10994 _("expression too complex"));
10996 constraint (value
> 32
10997 || (value
== 32 && (shift
== SHIFT_LSL
10998 || shift
== SHIFT_ROR
)),
10999 _("shift expression is too large"));
11003 else if (value
== 32)
11006 inst
.instruction
|= shift
<< 4;
11007 inst
.instruction
|= (value
& 0x1c) << 10;
11008 inst
.instruction
|= (value
& 0x03) << 6;
11013 /* inst.operands[i] was set up by parse_address. Encode it into a
11014 Thumb32 format load or store instruction. Reject forms that cannot
11015 be used with such instructions. If is_t is true, reject forms that
11016 cannot be used with a T instruction; if is_d is true, reject forms
11017 that cannot be used with a D instruction. If it is a store insn,
11018 reject PC in Rn. */
11021 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11023 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11025 constraint (!inst
.operands
[i
].isreg
,
11026 _("Instruction does not support =N addresses"));
11028 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11029 if (inst
.operands
[i
].immisreg
)
11031 constraint (is_pc
, BAD_PC_ADDRESSING
);
11032 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11033 constraint (inst
.operands
[i
].negative
,
11034 _("Thumb does not support negative register indexing"));
11035 constraint (inst
.operands
[i
].postind
,
11036 _("Thumb does not support register post-indexing"));
11037 constraint (inst
.operands
[i
].writeback
,
11038 _("Thumb does not support register indexing with writeback"));
11039 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11040 _("Thumb supports only LSL in shifted register indexing"));
11042 inst
.instruction
|= inst
.operands
[i
].imm
;
11043 if (inst
.operands
[i
].shifted
)
11045 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11046 _("expression too complex"));
11047 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11048 || inst
.relocs
[0].exp
.X_add_number
> 3,
11049 _("shift out of range"));
11050 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11052 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11054 else if (inst
.operands
[i
].preind
)
11056 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11057 constraint (is_t
&& inst
.operands
[i
].writeback
,
11058 _("cannot use writeback with this instruction"));
11059 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11060 BAD_PC_ADDRESSING
);
11064 inst
.instruction
|= 0x01000000;
11065 if (inst
.operands
[i
].writeback
)
11066 inst
.instruction
|= 0x00200000;
11070 inst
.instruction
|= 0x00000c00;
11071 if (inst
.operands
[i
].writeback
)
11072 inst
.instruction
|= 0x00000100;
11074 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11076 else if (inst
.operands
[i
].postind
)
11078 gas_assert (inst
.operands
[i
].writeback
);
11079 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11080 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11083 inst
.instruction
|= 0x00200000;
11085 inst
.instruction
|= 0x00000900;
11086 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11088 else /* unindexed - only for coprocessor */
11089 inst
.error
= _("instruction does not accept unindexed addressing");
11092 /* Table of Thumb instructions which exist in both 16- and 32-bit
11093 encodings (the latter only in post-V6T2 cores). The index is the
11094 value used in the insns table below. When there is more than one
11095 possible 16-bit encoding for the instruction, this table always
11097 Also contains several pseudo-instructions used during relaxation. */
11098 #define T16_32_TAB \
11099 X(_adc, 4140, eb400000), \
11100 X(_adcs, 4140, eb500000), \
11101 X(_add, 1c00, eb000000), \
11102 X(_adds, 1c00, eb100000), \
11103 X(_addi, 0000, f1000000), \
11104 X(_addis, 0000, f1100000), \
11105 X(_add_pc,000f, f20f0000), \
11106 X(_add_sp,000d, f10d0000), \
11107 X(_adr, 000f, f20f0000), \
11108 X(_and, 4000, ea000000), \
11109 X(_ands, 4000, ea100000), \
11110 X(_asr, 1000, fa40f000), \
11111 X(_asrs, 1000, fa50f000), \
11112 X(_b, e000, f000b000), \
11113 X(_bcond, d000, f0008000), \
11114 X(_bf, 0000, f040e001), \
11115 X(_bfcsel,0000, f000e001), \
11116 X(_bfx, 0000, f060e001), \
11117 X(_bfl, 0000, f000c001), \
11118 X(_bflx, 0000, f070e001), \
11119 X(_bic, 4380, ea200000), \
11120 X(_bics, 4380, ea300000), \
11121 X(_cmn, 42c0, eb100f00), \
11122 X(_cmp, 2800, ebb00f00), \
11123 X(_cpsie, b660, f3af8400), \
11124 X(_cpsid, b670, f3af8600), \
11125 X(_cpy, 4600, ea4f0000), \
11126 X(_dec_sp,80dd, f1ad0d00), \
11127 X(_dls, 0000, f040e001), \
11128 X(_eor, 4040, ea800000), \
11129 X(_eors, 4040, ea900000), \
11130 X(_inc_sp,00dd, f10d0d00), \
11131 X(_ldmia, c800, e8900000), \
11132 X(_ldr, 6800, f8500000), \
11133 X(_ldrb, 7800, f8100000), \
11134 X(_ldrh, 8800, f8300000), \
11135 X(_ldrsb, 5600, f9100000), \
11136 X(_ldrsh, 5e00, f9300000), \
11137 X(_ldr_pc,4800, f85f0000), \
11138 X(_ldr_pc2,4800, f85f0000), \
11139 X(_ldr_sp,9800, f85d0000), \
11140 X(_le, 0000, f00fc001), \
11141 X(_lsl, 0000, fa00f000), \
11142 X(_lsls, 0000, fa10f000), \
11143 X(_lsr, 0800, fa20f000), \
11144 X(_lsrs, 0800, fa30f000), \
11145 X(_mov, 2000, ea4f0000), \
11146 X(_movs, 2000, ea5f0000), \
11147 X(_mul, 4340, fb00f000), \
11148 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11149 X(_mvn, 43c0, ea6f0000), \
11150 X(_mvns, 43c0, ea7f0000), \
11151 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11152 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11153 X(_orr, 4300, ea400000), \
11154 X(_orrs, 4300, ea500000), \
11155 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11156 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11157 X(_rev, ba00, fa90f080), \
11158 X(_rev16, ba40, fa90f090), \
11159 X(_revsh, bac0, fa90f0b0), \
11160 X(_ror, 41c0, fa60f000), \
11161 X(_rors, 41c0, fa70f000), \
11162 X(_sbc, 4180, eb600000), \
11163 X(_sbcs, 4180, eb700000), \
11164 X(_stmia, c000, e8800000), \
11165 X(_str, 6000, f8400000), \
11166 X(_strb, 7000, f8000000), \
11167 X(_strh, 8000, f8200000), \
11168 X(_str_sp,9000, f84d0000), \
11169 X(_sub, 1e00, eba00000), \
11170 X(_subs, 1e00, ebb00000), \
11171 X(_subi, 8000, f1a00000), \
11172 X(_subis, 8000, f1b00000), \
11173 X(_sxtb, b240, fa4ff080), \
11174 X(_sxth, b200, fa0ff080), \
11175 X(_tst, 4200, ea100f00), \
11176 X(_uxtb, b2c0, fa5ff080), \
11177 X(_uxth, b280, fa1ff080), \
11178 X(_nop, bf00, f3af8000), \
11179 X(_yield, bf10, f3af8001), \
11180 X(_wfe, bf20, f3af8002), \
11181 X(_wfi, bf30, f3af8003), \
11182 X(_wls, 0000, f040c001), \
11183 X(_sev, bf40, f3af8004), \
11184 X(_sevl, bf50, f3af8005), \
11185 X(_udf, de00, f7f0a000)
11187 /* To catch errors in encoding functions, the codes are all offset by
11188 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11189 as 16-bit instructions. */
11190 #define X(a,b,c) T_MNEM##a
11191 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11194 #define X(a,b,c) 0x##b
11195 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11196 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11199 #define X(a,b,c) 0x##c
11200 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11201 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11202 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11206 /* Thumb instruction encoders, in alphabetical order. */
11208 /* ADDW or SUBW. */
11211 do_t_add_sub_w (void)
11215 Rd
= inst
.operands
[0].reg
;
11216 Rn
= inst
.operands
[1].reg
;
11218 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11219 is the SP-{plus,minus}-immediate form of the instruction. */
11221 constraint (Rd
== REG_PC
, BAD_PC
);
11223 reject_bad_reg (Rd
);
11225 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11226 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11229 /* Parse an add or subtract instruction. We get here with inst.instruction
11230 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11233 do_t_add_sub (void)
11237 Rd
= inst
.operands
[0].reg
;
11238 Rs
= (inst
.operands
[1].present
11239 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11240 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11243 set_pred_insn_type_last ();
11245 if (unified_syntax
)
11248 bfd_boolean narrow
;
11251 flags
= (inst
.instruction
== T_MNEM_adds
11252 || inst
.instruction
== T_MNEM_subs
);
11254 narrow
= !in_pred_block ();
11256 narrow
= in_pred_block ();
11257 if (!inst
.operands
[2].isreg
)
11261 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11262 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11264 add
= (inst
.instruction
== T_MNEM_add
11265 || inst
.instruction
== T_MNEM_adds
);
11267 if (inst
.size_req
!= 4)
11269 /* Attempt to use a narrow opcode, with relaxation if
11271 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11272 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11273 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11274 opcode
= T_MNEM_add_sp
;
11275 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11276 opcode
= T_MNEM_add_pc
;
11277 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11280 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11282 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11286 inst
.instruction
= THUMB_OP16(opcode
);
11287 inst
.instruction
|= (Rd
<< 4) | Rs
;
11288 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11289 || (inst
.relocs
[0].type
11290 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11292 if (inst
.size_req
== 2)
11293 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11295 inst
.relax
= opcode
;
11299 constraint (inst
.size_req
== 2, BAD_HIREG
);
11301 if (inst
.size_req
== 4
11302 || (inst
.size_req
!= 2 && !opcode
))
11304 constraint ((inst
.relocs
[0].type
11305 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11306 && (inst
.relocs
[0].type
11307 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11308 THUMB1_RELOC_ONLY
);
11311 constraint (add
, BAD_PC
);
11312 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11313 _("only SUBS PC, LR, #const allowed"));
11314 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11315 _("expression too complex"));
11316 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11317 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11318 _("immediate value out of range"));
11319 inst
.instruction
= T2_SUBS_PC_LR
11320 | inst
.relocs
[0].exp
.X_add_number
;
11321 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11324 else if (Rs
== REG_PC
)
11326 /* Always use addw/subw. */
11327 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11328 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11332 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11333 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11336 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11338 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11340 inst
.instruction
|= Rd
<< 8;
11341 inst
.instruction
|= Rs
<< 16;
11346 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11347 unsigned int shift
= inst
.operands
[2].shift_kind
;
11349 Rn
= inst
.operands
[2].reg
;
11350 /* See if we can do this with a 16-bit instruction. */
11351 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11353 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11358 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11359 || inst
.instruction
== T_MNEM_add
)
11361 : T_OPCODE_SUB_R3
);
11362 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11366 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11368 /* Thumb-1 cores (except v6-M) require at least one high
11369 register in a narrow non flag setting add. */
11370 if (Rd
> 7 || Rn
> 7
11371 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11372 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11379 inst
.instruction
= T_OPCODE_ADD_HI
;
11380 inst
.instruction
|= (Rd
& 8) << 4;
11381 inst
.instruction
|= (Rd
& 7);
11382 inst
.instruction
|= Rn
<< 3;
11388 constraint (Rd
== REG_PC
, BAD_PC
);
11389 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11390 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11391 constraint (Rs
== REG_PC
, BAD_PC
);
11392 reject_bad_reg (Rn
);
11394 /* If we get here, it can't be done in 16 bits. */
11395 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11396 _("shift must be constant"));
11397 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11398 inst
.instruction
|= Rd
<< 8;
11399 inst
.instruction
|= Rs
<< 16;
11400 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11401 _("shift value over 3 not allowed in thumb mode"));
11402 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11403 _("only LSL shift allowed in thumb mode"));
11404 encode_thumb32_shifted_operand (2);
11409 constraint (inst
.instruction
== T_MNEM_adds
11410 || inst
.instruction
== T_MNEM_subs
,
11413 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11415 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11416 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11419 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11420 ? 0x0000 : 0x8000);
11421 inst
.instruction
|= (Rd
<< 4) | Rs
;
11422 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11426 Rn
= inst
.operands
[2].reg
;
11427 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11429 /* We now have Rd, Rs, and Rn set to registers. */
11430 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11432 /* Can't do this for SUB. */
11433 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11434 inst
.instruction
= T_OPCODE_ADD_HI
;
11435 inst
.instruction
|= (Rd
& 8) << 4;
11436 inst
.instruction
|= (Rd
& 7);
11438 inst
.instruction
|= Rn
<< 3;
11440 inst
.instruction
|= Rs
<< 3;
11442 constraint (1, _("dest must overlap one source register"));
11446 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11447 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11448 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11458 Rd
= inst
.operands
[0].reg
;
11459 reject_bad_reg (Rd
);
11461 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11463 /* Defer to section relaxation. */
11464 inst
.relax
= inst
.instruction
;
11465 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11466 inst
.instruction
|= Rd
<< 4;
11468 else if (unified_syntax
&& inst
.size_req
!= 2)
11470 /* Generate a 32-bit opcode. */
11471 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11472 inst
.instruction
|= Rd
<< 8;
11473 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11474 inst
.relocs
[0].pc_rel
= 1;
11478 /* Generate a 16-bit opcode. */
11479 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11480 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11481 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11482 inst
.relocs
[0].pc_rel
= 1;
11483 inst
.instruction
|= Rd
<< 4;
11486 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11487 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11488 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11489 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11490 inst
.relocs
[0].exp
.X_add_number
+= 1;
11493 /* Arithmetic instructions for which there is just one 16-bit
11494 instruction encoding, and it allows only two low registers.
11495 For maximal compatibility with ARM syntax, we allow three register
11496 operands even when Thumb-32 instructions are not available, as long
11497 as the first two are identical. For instance, both "sbc r0,r1" and
11498 "sbc r0,r0,r1" are allowed. */
11504 Rd
= inst
.operands
[0].reg
;
11505 Rs
= (inst
.operands
[1].present
11506 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11507 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11508 Rn
= inst
.operands
[2].reg
;
11510 reject_bad_reg (Rd
);
11511 reject_bad_reg (Rs
);
11512 if (inst
.operands
[2].isreg
)
11513 reject_bad_reg (Rn
);
11515 if (unified_syntax
)
11517 if (!inst
.operands
[2].isreg
)
11519 /* For an immediate, we always generate a 32-bit opcode;
11520 section relaxation will shrink it later if possible. */
11521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11522 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11523 inst
.instruction
|= Rd
<< 8;
11524 inst
.instruction
|= Rs
<< 16;
11525 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11529 bfd_boolean narrow
;
11531 /* See if we can do this with a 16-bit instruction. */
11532 if (THUMB_SETS_FLAGS (inst
.instruction
))
11533 narrow
= !in_pred_block ();
11535 narrow
= in_pred_block ();
11537 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11539 if (inst
.operands
[2].shifted
)
11541 if (inst
.size_req
== 4)
11547 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11548 inst
.instruction
|= Rd
;
11549 inst
.instruction
|= Rn
<< 3;
11553 /* If we get here, it can't be done in 16 bits. */
11554 constraint (inst
.operands
[2].shifted
11555 && inst
.operands
[2].immisreg
,
11556 _("shift must be constant"));
11557 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11558 inst
.instruction
|= Rd
<< 8;
11559 inst
.instruction
|= Rs
<< 16;
11560 encode_thumb32_shifted_operand (2);
11565 /* On its face this is a lie - the instruction does set the
11566 flags. However, the only supported mnemonic in this mode
11567 says it doesn't. */
11568 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11570 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11571 _("unshifted register required"));
11572 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11573 constraint (Rd
!= Rs
,
11574 _("dest and source1 must be the same register"));
11576 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11577 inst
.instruction
|= Rd
;
11578 inst
.instruction
|= Rn
<< 3;
11582 /* Similarly, but for instructions where the arithmetic operation is
11583 commutative, so we can allow either of them to be different from
11584 the destination operand in a 16-bit instruction. For instance, all
11585 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11592 Rd
= inst
.operands
[0].reg
;
11593 Rs
= (inst
.operands
[1].present
11594 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11595 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11596 Rn
= inst
.operands
[2].reg
;
11598 reject_bad_reg (Rd
);
11599 reject_bad_reg (Rs
);
11600 if (inst
.operands
[2].isreg
)
11601 reject_bad_reg (Rn
);
11603 if (unified_syntax
)
11605 if (!inst
.operands
[2].isreg
)
11607 /* For an immediate, we always generate a 32-bit opcode;
11608 section relaxation will shrink it later if possible. */
11609 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11610 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11611 inst
.instruction
|= Rd
<< 8;
11612 inst
.instruction
|= Rs
<< 16;
11613 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11617 bfd_boolean narrow
;
11619 /* See if we can do this with a 16-bit instruction. */
11620 if (THUMB_SETS_FLAGS (inst
.instruction
))
11621 narrow
= !in_pred_block ();
11623 narrow
= in_pred_block ();
11625 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11627 if (inst
.operands
[2].shifted
)
11629 if (inst
.size_req
== 4)
11636 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11637 inst
.instruction
|= Rd
;
11638 inst
.instruction
|= Rn
<< 3;
11643 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11644 inst
.instruction
|= Rd
;
11645 inst
.instruction
|= Rs
<< 3;
11650 /* If we get here, it can't be done in 16 bits. */
11651 constraint (inst
.operands
[2].shifted
11652 && inst
.operands
[2].immisreg
,
11653 _("shift must be constant"));
11654 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11655 inst
.instruction
|= Rd
<< 8;
11656 inst
.instruction
|= Rs
<< 16;
11657 encode_thumb32_shifted_operand (2);
11662 /* On its face this is a lie - the instruction does set the
11663 flags. However, the only supported mnemonic in this mode
11664 says it doesn't. */
11665 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11667 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11668 _("unshifted register required"));
11669 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11671 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11672 inst
.instruction
|= Rd
;
11675 inst
.instruction
|= Rn
<< 3;
11677 inst
.instruction
|= Rs
<< 3;
11679 constraint (1, _("dest must overlap one source register"));
11687 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11688 constraint (msb
> 32, _("bit-field extends past end of register"));
11689 /* The instruction encoding stores the LSB and MSB,
11690 not the LSB and width. */
11691 Rd
= inst
.operands
[0].reg
;
11692 reject_bad_reg (Rd
);
11693 inst
.instruction
|= Rd
<< 8;
11694 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11695 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11696 inst
.instruction
|= msb
- 1;
11705 Rd
= inst
.operands
[0].reg
;
11706 reject_bad_reg (Rd
);
11708 /* #0 in second position is alternative syntax for bfc, which is
11709 the same instruction but with REG_PC in the Rm field. */
11710 if (!inst
.operands
[1].isreg
)
11714 Rn
= inst
.operands
[1].reg
;
11715 reject_bad_reg (Rn
);
11718 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11719 constraint (msb
> 32, _("bit-field extends past end of register"));
11720 /* The instruction encoding stores the LSB and MSB,
11721 not the LSB and width. */
11722 inst
.instruction
|= Rd
<< 8;
11723 inst
.instruction
|= Rn
<< 16;
11724 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11725 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11726 inst
.instruction
|= msb
- 1;
11734 Rd
= inst
.operands
[0].reg
;
11735 Rn
= inst
.operands
[1].reg
;
11737 reject_bad_reg (Rd
);
11738 reject_bad_reg (Rn
);
11740 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11741 _("bit-field extends past end of register"));
11742 inst
.instruction
|= Rd
<< 8;
11743 inst
.instruction
|= Rn
<< 16;
11744 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11745 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11746 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11749 /* ARM V5 Thumb BLX (argument parse)
11750 BLX <target_addr> which is BLX(1)
11751 BLX <Rm> which is BLX(2)
11752 Unfortunately, there are two different opcodes for this mnemonic.
11753 So, the insns[].value is not used, and the code here zaps values
11754 into inst.instruction.
11756 ??? How to take advantage of the additional two bits of displacement
11757 available in Thumb32 mode? Need new relocation? */
11762 set_pred_insn_type_last ();
11764 if (inst
.operands
[0].isreg
)
11766 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11767 /* We have a register, so this is BLX(2). */
11768 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11772 /* No register. This must be BLX(1). */
11773 inst
.instruction
= 0xf000e800;
11774 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11783 bfd_reloc_code_real_type reloc
;
11786 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11788 if (in_pred_block ())
11790 /* Conditional branches inside IT blocks are encoded as unconditional
11792 cond
= COND_ALWAYS
;
11797 if (cond
!= COND_ALWAYS
)
11798 opcode
= T_MNEM_bcond
;
11800 opcode
= inst
.instruction
;
11803 && (inst
.size_req
== 4
11804 || (inst
.size_req
!= 2
11805 && (inst
.operands
[0].hasreloc
11806 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11808 inst
.instruction
= THUMB_OP32(opcode
);
11809 if (cond
== COND_ALWAYS
)
11810 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11813 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11814 _("selected architecture does not support "
11815 "wide conditional branch instruction"));
11817 gas_assert (cond
!= 0xF);
11818 inst
.instruction
|= cond
<< 22;
11819 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11824 inst
.instruction
= THUMB_OP16(opcode
);
11825 if (cond
== COND_ALWAYS
)
11826 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11829 inst
.instruction
|= cond
<< 8;
11830 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11832 /* Allow section relaxation. */
11833 if (unified_syntax
&& inst
.size_req
!= 2)
11834 inst
.relax
= opcode
;
11836 inst
.relocs
[0].type
= reloc
;
11837 inst
.relocs
[0].pc_rel
= 1;
11840 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11841 between the two is the maximum immediate allowed - which is passed in
11844 do_t_bkpt_hlt1 (int range
)
11846 constraint (inst
.cond
!= COND_ALWAYS
,
11847 _("instruction is always unconditional"));
11848 if (inst
.operands
[0].present
)
11850 constraint (inst
.operands
[0].imm
> range
,
11851 _("immediate value out of range"));
11852 inst
.instruction
|= inst
.operands
[0].imm
;
11855 set_pred_insn_type (NEUTRAL_IT_INSN
);
11861 do_t_bkpt_hlt1 (63);
11867 do_t_bkpt_hlt1 (255);
11871 do_t_branch23 (void)
11873 set_pred_insn_type_last ();
11874 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11876 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11877 this file. We used to simply ignore the PLT reloc type here --
11878 the branch encoding is now needed to deal with TLSCALL relocs.
11879 So if we see a PLT reloc now, put it back to how it used to be to
11880 keep the preexisting behaviour. */
11881 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11882 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11884 #if defined(OBJ_COFF)
11885 /* If the destination of the branch is a defined symbol which does not have
11886 the THUMB_FUNC attribute, then we must be calling a function which has
11887 the (interfacearm) attribute. We look for the Thumb entry point to that
11888 function and change the branch to refer to that function instead. */
11889 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11890 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11891 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11892 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11893 inst
.relocs
[0].exp
.X_add_symbol
11894 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11901 set_pred_insn_type_last ();
11902 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11903 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11904 should cause the alignment to be checked once it is known. This is
11905 because BX PC only works if the instruction is word aligned. */
11913 set_pred_insn_type_last ();
11914 Rm
= inst
.operands
[0].reg
;
11915 reject_bad_reg (Rm
);
11916 inst
.instruction
|= Rm
<< 16;
11925 Rd
= inst
.operands
[0].reg
;
11926 Rm
= inst
.operands
[1].reg
;
11928 reject_bad_reg (Rd
);
11929 reject_bad_reg (Rm
);
11931 inst
.instruction
|= Rd
<< 8;
11932 inst
.instruction
|= Rm
<< 16;
11933 inst
.instruction
|= Rm
;
11939 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11945 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11946 inst
.instruction
|= inst
.operands
[0].imm
;
11952 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11954 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11955 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11957 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11958 inst
.instruction
= 0xf3af8000;
11959 inst
.instruction
|= imod
<< 9;
11960 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11961 if (inst
.operands
[1].present
)
11962 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11967 && (inst
.operands
[0].imm
& 4),
11968 _("selected processor does not support 'A' form "
11969 "of this instruction"));
11970 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11971 _("Thumb does not support the 2-argument "
11972 "form of this instruction"));
11973 inst
.instruction
|= inst
.operands
[0].imm
;
11977 /* THUMB CPY instruction (argument parse). */
11982 if (inst
.size_req
== 4)
11984 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11985 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11986 inst
.instruction
|= inst
.operands
[1].reg
;
11990 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11991 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11992 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11999 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12000 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12001 inst
.instruction
|= inst
.operands
[0].reg
;
12002 inst
.relocs
[0].pc_rel
= 1;
12003 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12009 inst
.instruction
|= inst
.operands
[0].imm
;
12015 unsigned Rd
, Rn
, Rm
;
12017 Rd
= inst
.operands
[0].reg
;
12018 Rn
= (inst
.operands
[1].present
12019 ? inst
.operands
[1].reg
: Rd
);
12020 Rm
= inst
.operands
[2].reg
;
12022 reject_bad_reg (Rd
);
12023 reject_bad_reg (Rn
);
12024 reject_bad_reg (Rm
);
12026 inst
.instruction
|= Rd
<< 8;
12027 inst
.instruction
|= Rn
<< 16;
12028 inst
.instruction
|= Rm
;
12034 if (unified_syntax
&& inst
.size_req
== 4)
12035 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12037 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12043 unsigned int cond
= inst
.operands
[0].imm
;
12045 set_pred_insn_type (IT_INSN
);
12046 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12047 now_pred
.cc
= cond
;
12048 now_pred
.warn_deprecated
= FALSE
;
12049 now_pred
.type
= SCALAR_PRED
;
12051 /* If the condition is a negative condition, invert the mask. */
12052 if ((cond
& 0x1) == 0x0)
12054 unsigned int mask
= inst
.instruction
& 0x000f;
12056 if ((mask
& 0x7) == 0)
12058 /* No conversion needed. */
12059 now_pred
.block_length
= 1;
12061 else if ((mask
& 0x3) == 0)
12064 now_pred
.block_length
= 2;
12066 else if ((mask
& 0x1) == 0)
12069 now_pred
.block_length
= 3;
12074 now_pred
.block_length
= 4;
12077 inst
.instruction
&= 0xfff0;
12078 inst
.instruction
|= mask
;
12081 inst
.instruction
|= cond
<< 4;
12084 /* Helper function used for both push/pop and ldm/stm. */
12086 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12087 bfd_boolean writeback
)
12089 bfd_boolean load
, store
;
12091 gas_assert (base
!= -1 || !do_io
);
12092 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12093 store
= do_io
&& !load
;
12095 if (mask
& (1 << 13))
12096 inst
.error
= _("SP not allowed in register list");
12098 if (do_io
&& (mask
& (1 << base
)) != 0
12100 inst
.error
= _("having the base register in the register list when "
12101 "using write back is UNPREDICTABLE");
12105 if (mask
& (1 << 15))
12107 if (mask
& (1 << 14))
12108 inst
.error
= _("LR and PC should not both be in register list");
12110 set_pred_insn_type_last ();
12115 if (mask
& (1 << 15))
12116 inst
.error
= _("PC not allowed in register list");
12119 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12121 /* Single register transfers implemented as str/ldr. */
12124 if (inst
.instruction
& (1 << 23))
12125 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12127 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12131 if (inst
.instruction
& (1 << 23))
12132 inst
.instruction
= 0x00800000; /* ia -> [base] */
12134 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12137 inst
.instruction
|= 0xf8400000;
12139 inst
.instruction
|= 0x00100000;
12141 mask
= ffs (mask
) - 1;
12144 else if (writeback
)
12145 inst
.instruction
|= WRITE_BACK
;
12147 inst
.instruction
|= mask
;
12149 inst
.instruction
|= base
<< 16;
12155 /* This really doesn't seem worth it. */
12156 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12157 _("expression too complex"));
12158 constraint (inst
.operands
[1].writeback
,
12159 _("Thumb load/store multiple does not support {reglist}^"));
12161 if (unified_syntax
)
12163 bfd_boolean narrow
;
12167 /* See if we can use a 16-bit instruction. */
12168 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12169 && inst
.size_req
!= 4
12170 && !(inst
.operands
[1].imm
& ~0xff))
12172 mask
= 1 << inst
.operands
[0].reg
;
12174 if (inst
.operands
[0].reg
<= 7)
12176 if (inst
.instruction
== T_MNEM_stmia
12177 ? inst
.operands
[0].writeback
12178 : (inst
.operands
[0].writeback
12179 == !(inst
.operands
[1].imm
& mask
)))
12181 if (inst
.instruction
== T_MNEM_stmia
12182 && (inst
.operands
[1].imm
& mask
)
12183 && (inst
.operands
[1].imm
& (mask
- 1)))
12184 as_warn (_("value stored for r%d is UNKNOWN"),
12185 inst
.operands
[0].reg
);
12187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12189 inst
.instruction
|= inst
.operands
[1].imm
;
12192 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12194 /* This means 1 register in reg list one of 3 situations:
12195 1. Instruction is stmia, but without writeback.
12196 2. lmdia without writeback, but with Rn not in
12198 3. ldmia with writeback, but with Rn in reglist.
12199 Case 3 is UNPREDICTABLE behaviour, so we handle
12200 case 1 and 2 which can be converted into a 16-bit
12201 str or ldr. The SP cases are handled below. */
12202 unsigned long opcode
;
12203 /* First, record an error for Case 3. */
12204 if (inst
.operands
[1].imm
& mask
12205 && inst
.operands
[0].writeback
)
12207 _("having the base register in the register list when "
12208 "using write back is UNPREDICTABLE");
12210 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12212 inst
.instruction
= THUMB_OP16 (opcode
);
12213 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12214 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12218 else if (inst
.operands
[0] .reg
== REG_SP
)
12220 if (inst
.operands
[0].writeback
)
12223 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12224 ? T_MNEM_push
: T_MNEM_pop
);
12225 inst
.instruction
|= inst
.operands
[1].imm
;
12228 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12231 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12232 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12233 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12241 if (inst
.instruction
< 0xffff)
12242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12244 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12245 inst
.operands
[1].imm
,
12246 inst
.operands
[0].writeback
);
12251 constraint (inst
.operands
[0].reg
> 7
12252 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12253 constraint (inst
.instruction
!= T_MNEM_ldmia
12254 && inst
.instruction
!= T_MNEM_stmia
,
12255 _("Thumb-2 instruction only valid in unified syntax"));
12256 if (inst
.instruction
== T_MNEM_stmia
)
12258 if (!inst
.operands
[0].writeback
)
12259 as_warn (_("this instruction will write back the base register"));
12260 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12261 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12262 as_warn (_("value stored for r%d is UNKNOWN"),
12263 inst
.operands
[0].reg
);
12267 if (!inst
.operands
[0].writeback
12268 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12269 as_warn (_("this instruction will write back the base register"));
12270 else if (inst
.operands
[0].writeback
12271 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12272 as_warn (_("this instruction will not write back the base register"));
12275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12277 inst
.instruction
|= inst
.operands
[1].imm
;
12284 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12285 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12286 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12287 || inst
.operands
[1].negative
,
12290 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12294 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12300 if (!inst
.operands
[1].present
)
12302 constraint (inst
.operands
[0].reg
== REG_LR
,
12303 _("r14 not allowed as first register "
12304 "when second register is omitted"));
12305 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12307 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12311 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12312 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12318 unsigned long opcode
;
12321 if (inst
.operands
[0].isreg
12322 && !inst
.operands
[0].preind
12323 && inst
.operands
[0].reg
== REG_PC
)
12324 set_pred_insn_type_last ();
12326 opcode
= inst
.instruction
;
12327 if (unified_syntax
)
12329 if (!inst
.operands
[1].isreg
)
12331 if (opcode
<= 0xffff)
12332 inst
.instruction
= THUMB_OP32 (opcode
);
12333 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12336 if (inst
.operands
[1].isreg
12337 && !inst
.operands
[1].writeback
12338 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12339 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12340 && opcode
<= 0xffff
12341 && inst
.size_req
!= 4)
12343 /* Insn may have a 16-bit form. */
12344 Rn
= inst
.operands
[1].reg
;
12345 if (inst
.operands
[1].immisreg
)
12347 inst
.instruction
= THUMB_OP16 (opcode
);
12349 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12351 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12352 reject_bad_reg (inst
.operands
[1].imm
);
12354 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12355 && opcode
!= T_MNEM_ldrsb
)
12356 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12357 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12364 if (inst
.relocs
[0].pc_rel
)
12365 opcode
= T_MNEM_ldr_pc2
;
12367 opcode
= T_MNEM_ldr_pc
;
12371 if (opcode
== T_MNEM_ldr
)
12372 opcode
= T_MNEM_ldr_sp
;
12374 opcode
= T_MNEM_str_sp
;
12376 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12380 inst
.instruction
= inst
.operands
[0].reg
;
12381 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12383 inst
.instruction
|= THUMB_OP16 (opcode
);
12384 if (inst
.size_req
== 2)
12385 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12387 inst
.relax
= opcode
;
12391 /* Definitely a 32-bit variant. */
12393 /* Warning for Erratum 752419. */
12394 if (opcode
== T_MNEM_ldr
12395 && inst
.operands
[0].reg
== REG_SP
12396 && inst
.operands
[1].writeback
== 1
12397 && !inst
.operands
[1].immisreg
)
12399 if (no_cpu_selected ()
12400 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12401 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12402 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12403 as_warn (_("This instruction may be unpredictable "
12404 "if executed on M-profile cores "
12405 "with interrupts enabled."));
12408 /* Do some validations regarding addressing modes. */
12409 if (inst
.operands
[1].immisreg
)
12410 reject_bad_reg (inst
.operands
[1].imm
);
12412 constraint (inst
.operands
[1].writeback
== 1
12413 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12416 inst
.instruction
= THUMB_OP32 (opcode
);
12417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12418 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12419 check_ldr_r15_aligned ();
12423 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12425 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12427 /* Only [Rn,Rm] is acceptable. */
12428 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12429 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12430 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12431 || inst
.operands
[1].negative
,
12432 _("Thumb does not support this addressing mode"));
12433 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12437 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12438 if (!inst
.operands
[1].isreg
)
12439 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12442 constraint (!inst
.operands
[1].preind
12443 || inst
.operands
[1].shifted
12444 || inst
.operands
[1].writeback
,
12445 _("Thumb does not support this addressing mode"));
12446 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12448 constraint (inst
.instruction
& 0x0600,
12449 _("byte or halfword not valid for base register"));
12450 constraint (inst
.operands
[1].reg
== REG_PC
12451 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12452 _("r15 based store not allowed"));
12453 constraint (inst
.operands
[1].immisreg
,
12454 _("invalid base register for register offset"));
12456 if (inst
.operands
[1].reg
== REG_PC
)
12457 inst
.instruction
= T_OPCODE_LDR_PC
;
12458 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12459 inst
.instruction
= T_OPCODE_LDR_SP
;
12461 inst
.instruction
= T_OPCODE_STR_SP
;
12463 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12464 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12468 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12469 if (!inst
.operands
[1].immisreg
)
12471 /* Immediate offset. */
12472 inst
.instruction
|= inst
.operands
[0].reg
;
12473 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12474 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12478 /* Register offset. */
12479 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12480 constraint (inst
.operands
[1].negative
,
12481 _("Thumb does not support this addressing mode"));
12484 switch (inst
.instruction
)
12486 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12487 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12488 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12489 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12490 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12491 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12492 case 0x5600 /* ldrsb */:
12493 case 0x5e00 /* ldrsh */: break;
12497 inst
.instruction
|= inst
.operands
[0].reg
;
12498 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12499 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12505 if (!inst
.operands
[1].present
)
12507 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12508 constraint (inst
.operands
[0].reg
== REG_LR
,
12509 _("r14 not allowed here"));
12510 constraint (inst
.operands
[0].reg
== REG_R12
,
12511 _("r12 not allowed here"));
12514 if (inst
.operands
[2].writeback
12515 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12516 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12517 as_warn (_("base register written back, and overlaps "
12518 "one of transfer registers"));
12520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12521 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12522 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12528 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12529 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12535 unsigned Rd
, Rn
, Rm
, Ra
;
12537 Rd
= inst
.operands
[0].reg
;
12538 Rn
= inst
.operands
[1].reg
;
12539 Rm
= inst
.operands
[2].reg
;
12540 Ra
= inst
.operands
[3].reg
;
12542 reject_bad_reg (Rd
);
12543 reject_bad_reg (Rn
);
12544 reject_bad_reg (Rm
);
12545 reject_bad_reg (Ra
);
12547 inst
.instruction
|= Rd
<< 8;
12548 inst
.instruction
|= Rn
<< 16;
12549 inst
.instruction
|= Rm
;
12550 inst
.instruction
|= Ra
<< 12;
12556 unsigned RdLo
, RdHi
, Rn
, Rm
;
12558 RdLo
= inst
.operands
[0].reg
;
12559 RdHi
= inst
.operands
[1].reg
;
12560 Rn
= inst
.operands
[2].reg
;
12561 Rm
= inst
.operands
[3].reg
;
12563 reject_bad_reg (RdLo
);
12564 reject_bad_reg (RdHi
);
12565 reject_bad_reg (Rn
);
12566 reject_bad_reg (Rm
);
12568 inst
.instruction
|= RdLo
<< 12;
12569 inst
.instruction
|= RdHi
<< 8;
12570 inst
.instruction
|= Rn
<< 16;
12571 inst
.instruction
|= Rm
;
12575 do_t_mov_cmp (void)
12579 Rn
= inst
.operands
[0].reg
;
12580 Rm
= inst
.operands
[1].reg
;
12583 set_pred_insn_type_last ();
12585 if (unified_syntax
)
12587 int r0off
= (inst
.instruction
== T_MNEM_mov
12588 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12589 unsigned long opcode
;
12590 bfd_boolean narrow
;
12591 bfd_boolean low_regs
;
12593 low_regs
= (Rn
<= 7 && Rm
<= 7);
12594 opcode
= inst
.instruction
;
12595 if (in_pred_block ())
12596 narrow
= opcode
!= T_MNEM_movs
;
12598 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12599 if (inst
.size_req
== 4
12600 || inst
.operands
[1].shifted
)
12603 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12604 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12605 && !inst
.operands
[1].shifted
12609 inst
.instruction
= T2_SUBS_PC_LR
;
12613 if (opcode
== T_MNEM_cmp
)
12615 constraint (Rn
== REG_PC
, BAD_PC
);
12618 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12620 warn_deprecated_sp (Rm
);
12621 /* R15 was documented as a valid choice for Rm in ARMv6,
12622 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12623 tools reject R15, so we do too. */
12624 constraint (Rm
== REG_PC
, BAD_PC
);
12627 reject_bad_reg (Rm
);
12629 else if (opcode
== T_MNEM_mov
12630 || opcode
== T_MNEM_movs
)
12632 if (inst
.operands
[1].isreg
)
12634 if (opcode
== T_MNEM_movs
)
12636 reject_bad_reg (Rn
);
12637 reject_bad_reg (Rm
);
12641 /* This is mov.n. */
12642 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12643 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12645 as_tsktsk (_("Use of r%u as a source register is "
12646 "deprecated when r%u is the destination "
12647 "register."), Rm
, Rn
);
12652 /* This is mov.w. */
12653 constraint (Rn
== REG_PC
, BAD_PC
);
12654 constraint (Rm
== REG_PC
, BAD_PC
);
12655 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12656 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12660 reject_bad_reg (Rn
);
12663 if (!inst
.operands
[1].isreg
)
12665 /* Immediate operand. */
12666 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12668 if (low_regs
&& narrow
)
12670 inst
.instruction
= THUMB_OP16 (opcode
);
12671 inst
.instruction
|= Rn
<< 8;
12672 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12673 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12675 if (inst
.size_req
== 2)
12676 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12678 inst
.relax
= opcode
;
12683 constraint ((inst
.relocs
[0].type
12684 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12685 && (inst
.relocs
[0].type
12686 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12687 THUMB1_RELOC_ONLY
);
12689 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12690 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12691 inst
.instruction
|= Rn
<< r0off
;
12692 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12695 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12696 && (inst
.instruction
== T_MNEM_mov
12697 || inst
.instruction
== T_MNEM_movs
))
12699 /* Register shifts are encoded as separate shift instructions. */
12700 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12702 if (in_pred_block ())
12707 if (inst
.size_req
== 4)
12710 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12716 switch (inst
.operands
[1].shift_kind
)
12719 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12722 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12725 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12728 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12734 inst
.instruction
= opcode
;
12737 inst
.instruction
|= Rn
;
12738 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12743 inst
.instruction
|= CONDS_BIT
;
12745 inst
.instruction
|= Rn
<< 8;
12746 inst
.instruction
|= Rm
<< 16;
12747 inst
.instruction
|= inst
.operands
[1].imm
;
12752 /* Some mov with immediate shift have narrow variants.
12753 Register shifts are handled above. */
12754 if (low_regs
&& inst
.operands
[1].shifted
12755 && (inst
.instruction
== T_MNEM_mov
12756 || inst
.instruction
== T_MNEM_movs
))
12758 if (in_pred_block ())
12759 narrow
= (inst
.instruction
== T_MNEM_mov
);
12761 narrow
= (inst
.instruction
== T_MNEM_movs
);
12766 switch (inst
.operands
[1].shift_kind
)
12768 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12769 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12770 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12771 default: narrow
= FALSE
; break;
12777 inst
.instruction
|= Rn
;
12778 inst
.instruction
|= Rm
<< 3;
12779 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12783 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12784 inst
.instruction
|= Rn
<< r0off
;
12785 encode_thumb32_shifted_operand (1);
12789 switch (inst
.instruction
)
12792 /* In v4t or v5t a move of two lowregs produces unpredictable
12793 results. Don't allow this. */
12796 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12797 "MOV Rd, Rs with two low registers is not "
12798 "permitted on this architecture");
12799 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12803 inst
.instruction
= T_OPCODE_MOV_HR
;
12804 inst
.instruction
|= (Rn
& 0x8) << 4;
12805 inst
.instruction
|= (Rn
& 0x7);
12806 inst
.instruction
|= Rm
<< 3;
12810 /* We know we have low registers at this point.
12811 Generate LSLS Rd, Rs, #0. */
12812 inst
.instruction
= T_OPCODE_LSL_I
;
12813 inst
.instruction
|= Rn
;
12814 inst
.instruction
|= Rm
<< 3;
12820 inst
.instruction
= T_OPCODE_CMP_LR
;
12821 inst
.instruction
|= Rn
;
12822 inst
.instruction
|= Rm
<< 3;
12826 inst
.instruction
= T_OPCODE_CMP_HR
;
12827 inst
.instruction
|= (Rn
& 0x8) << 4;
12828 inst
.instruction
|= (Rn
& 0x7);
12829 inst
.instruction
|= Rm
<< 3;
12836 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12838 /* PR 10443: Do not silently ignore shifted operands. */
12839 constraint (inst
.operands
[1].shifted
,
12840 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12842 if (inst
.operands
[1].isreg
)
12844 if (Rn
< 8 && Rm
< 8)
12846 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12847 since a MOV instruction produces unpredictable results. */
12848 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12849 inst
.instruction
= T_OPCODE_ADD_I3
;
12851 inst
.instruction
= T_OPCODE_CMP_LR
;
12853 inst
.instruction
|= Rn
;
12854 inst
.instruction
|= Rm
<< 3;
12858 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12859 inst
.instruction
= T_OPCODE_MOV_HR
;
12861 inst
.instruction
= T_OPCODE_CMP_HR
;
12867 constraint (Rn
> 7,
12868 _("only lo regs allowed with immediate"));
12869 inst
.instruction
|= Rn
<< 8;
12870 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12881 top
= (inst
.instruction
& 0x00800000) != 0;
12882 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12884 constraint (top
, _(":lower16: not allowed in this instruction"));
12885 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12887 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12889 constraint (!top
, _(":upper16: not allowed in this instruction"));
12890 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12893 Rd
= inst
.operands
[0].reg
;
12894 reject_bad_reg (Rd
);
12896 inst
.instruction
|= Rd
<< 8;
12897 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12899 imm
= inst
.relocs
[0].exp
.X_add_number
;
12900 inst
.instruction
|= (imm
& 0xf000) << 4;
12901 inst
.instruction
|= (imm
& 0x0800) << 15;
12902 inst
.instruction
|= (imm
& 0x0700) << 4;
12903 inst
.instruction
|= (imm
& 0x00ff);
12908 do_t_mvn_tst (void)
12912 Rn
= inst
.operands
[0].reg
;
12913 Rm
= inst
.operands
[1].reg
;
12915 if (inst
.instruction
== T_MNEM_cmp
12916 || inst
.instruction
== T_MNEM_cmn
)
12917 constraint (Rn
== REG_PC
, BAD_PC
);
12919 reject_bad_reg (Rn
);
12920 reject_bad_reg (Rm
);
12922 if (unified_syntax
)
12924 int r0off
= (inst
.instruction
== T_MNEM_mvn
12925 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12926 bfd_boolean narrow
;
12928 if (inst
.size_req
== 4
12929 || inst
.instruction
> 0xffff
12930 || inst
.operands
[1].shifted
12931 || Rn
> 7 || Rm
> 7)
12933 else if (inst
.instruction
== T_MNEM_cmn
12934 || inst
.instruction
== T_MNEM_tst
)
12936 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12937 narrow
= !in_pred_block ();
12939 narrow
= in_pred_block ();
12941 if (!inst
.operands
[1].isreg
)
12943 /* For an immediate, we always generate a 32-bit opcode;
12944 section relaxation will shrink it later if possible. */
12945 if (inst
.instruction
< 0xffff)
12946 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12947 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12948 inst
.instruction
|= Rn
<< r0off
;
12949 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12953 /* See if we can do this with a 16-bit instruction. */
12956 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12957 inst
.instruction
|= Rn
;
12958 inst
.instruction
|= Rm
<< 3;
12962 constraint (inst
.operands
[1].shifted
12963 && inst
.operands
[1].immisreg
,
12964 _("shift must be constant"));
12965 if (inst
.instruction
< 0xffff)
12966 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12967 inst
.instruction
|= Rn
<< r0off
;
12968 encode_thumb32_shifted_operand (1);
12974 constraint (inst
.instruction
> 0xffff
12975 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12976 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12977 _("unshifted register required"));
12978 constraint (Rn
> 7 || Rm
> 7,
12981 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12982 inst
.instruction
|= Rn
;
12983 inst
.instruction
|= Rm
<< 3;
12992 if (do_vfp_nsyn_mrs () == SUCCESS
)
12995 Rd
= inst
.operands
[0].reg
;
12996 reject_bad_reg (Rd
);
12997 inst
.instruction
|= Rd
<< 8;
12999 if (inst
.operands
[1].isreg
)
13001 unsigned br
= inst
.operands
[1].reg
;
13002 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13003 as_bad (_("bad register for mrs"));
13005 inst
.instruction
|= br
& (0xf << 16);
13006 inst
.instruction
|= (br
& 0x300) >> 4;
13007 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13011 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13013 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13015 /* PR gas/12698: The constraint is only applied for m_profile.
13016 If the user has specified -march=all, we want to ignore it as
13017 we are building for any CPU type, including non-m variants. */
13018 bfd_boolean m_profile
=
13019 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13020 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13021 "not support requested special purpose register"));
13024 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13026 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13027 _("'APSR', 'CPSR' or 'SPSR' expected"));
13029 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13030 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13031 inst
.instruction
|= 0xf0000;
13041 if (do_vfp_nsyn_msr () == SUCCESS
)
13044 constraint (!inst
.operands
[1].isreg
,
13045 _("Thumb encoding does not support an immediate here"));
13047 if (inst
.operands
[0].isreg
)
13048 flags
= (int)(inst
.operands
[0].reg
);
13050 flags
= inst
.operands
[0].imm
;
13052 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13054 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13056 /* PR gas/12698: The constraint is only applied for m_profile.
13057 If the user has specified -march=all, we want to ignore it as
13058 we are building for any CPU type, including non-m variants. */
13059 bfd_boolean m_profile
=
13060 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13061 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13062 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13063 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13064 && bits
!= PSR_f
)) && m_profile
,
13065 _("selected processor does not support requested special "
13066 "purpose register"));
13069 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13070 "requested special purpose register"));
13072 Rn
= inst
.operands
[1].reg
;
13073 reject_bad_reg (Rn
);
13075 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13076 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13077 inst
.instruction
|= (flags
& 0x300) >> 4;
13078 inst
.instruction
|= (flags
& 0xff);
13079 inst
.instruction
|= Rn
<< 16;
13085 bfd_boolean narrow
;
13086 unsigned Rd
, Rn
, Rm
;
13088 if (!inst
.operands
[2].present
)
13089 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13091 Rd
= inst
.operands
[0].reg
;
13092 Rn
= inst
.operands
[1].reg
;
13093 Rm
= inst
.operands
[2].reg
;
13095 if (unified_syntax
)
13097 if (inst
.size_req
== 4
13103 else if (inst
.instruction
== T_MNEM_muls
)
13104 narrow
= !in_pred_block ();
13106 narrow
= in_pred_block ();
13110 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13111 constraint (Rn
> 7 || Rm
> 7,
13118 /* 16-bit MULS/Conditional MUL. */
13119 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13120 inst
.instruction
|= Rd
;
13123 inst
.instruction
|= Rm
<< 3;
13125 inst
.instruction
|= Rn
<< 3;
13127 constraint (1, _("dest must overlap one source register"));
13131 constraint (inst
.instruction
!= T_MNEM_mul
,
13132 _("Thumb-2 MUL must not set flags"));
13134 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13135 inst
.instruction
|= Rd
<< 8;
13136 inst
.instruction
|= Rn
<< 16;
13137 inst
.instruction
|= Rm
<< 0;
13139 reject_bad_reg (Rd
);
13140 reject_bad_reg (Rn
);
13141 reject_bad_reg (Rm
);
13148 unsigned RdLo
, RdHi
, Rn
, Rm
;
13150 RdLo
= inst
.operands
[0].reg
;
13151 RdHi
= inst
.operands
[1].reg
;
13152 Rn
= inst
.operands
[2].reg
;
13153 Rm
= inst
.operands
[3].reg
;
13155 reject_bad_reg (RdLo
);
13156 reject_bad_reg (RdHi
);
13157 reject_bad_reg (Rn
);
13158 reject_bad_reg (Rm
);
13160 inst
.instruction
|= RdLo
<< 12;
13161 inst
.instruction
|= RdHi
<< 8;
13162 inst
.instruction
|= Rn
<< 16;
13163 inst
.instruction
|= Rm
;
13166 as_tsktsk (_("rdhi and rdlo must be different"));
13172 set_pred_insn_type (NEUTRAL_IT_INSN
);
13174 if (unified_syntax
)
13176 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13178 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13179 inst
.instruction
|= inst
.operands
[0].imm
;
13183 /* PR9722: Check for Thumb2 availability before
13184 generating a thumb2 nop instruction. */
13185 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13188 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13191 inst
.instruction
= 0x46c0;
13196 constraint (inst
.operands
[0].present
,
13197 _("Thumb does not support NOP with hints"));
13198 inst
.instruction
= 0x46c0;
13205 if (unified_syntax
)
13207 bfd_boolean narrow
;
13209 if (THUMB_SETS_FLAGS (inst
.instruction
))
13210 narrow
= !in_pred_block ();
13212 narrow
= in_pred_block ();
13213 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13215 if (inst
.size_req
== 4)
13220 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13221 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13222 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13227 inst
.instruction
|= inst
.operands
[0].reg
;
13228 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13233 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13235 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13237 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13238 inst
.instruction
|= inst
.operands
[0].reg
;
13239 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13248 Rd
= inst
.operands
[0].reg
;
13249 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13251 reject_bad_reg (Rd
);
13252 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13253 reject_bad_reg (Rn
);
13255 inst
.instruction
|= Rd
<< 8;
13256 inst
.instruction
|= Rn
<< 16;
13258 if (!inst
.operands
[2].isreg
)
13260 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13261 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13267 Rm
= inst
.operands
[2].reg
;
13268 reject_bad_reg (Rm
);
13270 constraint (inst
.operands
[2].shifted
13271 && inst
.operands
[2].immisreg
,
13272 _("shift must be constant"));
13273 encode_thumb32_shifted_operand (2);
13280 unsigned Rd
, Rn
, Rm
;
13282 Rd
= inst
.operands
[0].reg
;
13283 Rn
= inst
.operands
[1].reg
;
13284 Rm
= inst
.operands
[2].reg
;
13286 reject_bad_reg (Rd
);
13287 reject_bad_reg (Rn
);
13288 reject_bad_reg (Rm
);
13290 inst
.instruction
|= Rd
<< 8;
13291 inst
.instruction
|= Rn
<< 16;
13292 inst
.instruction
|= Rm
;
13293 if (inst
.operands
[3].present
)
13295 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13296 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13297 _("expression too complex"));
13298 inst
.instruction
|= (val
& 0x1c) << 10;
13299 inst
.instruction
|= (val
& 0x03) << 6;
13306 if (!inst
.operands
[3].present
)
13310 inst
.instruction
&= ~0x00000020;
13312 /* PR 10168. Swap the Rm and Rn registers. */
13313 Rtmp
= inst
.operands
[1].reg
;
13314 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13315 inst
.operands
[2].reg
= Rtmp
;
13323 if (inst
.operands
[0].immisreg
)
13324 reject_bad_reg (inst
.operands
[0].imm
);
13326 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13330 do_t_push_pop (void)
13334 constraint (inst
.operands
[0].writeback
,
13335 _("push/pop do not support {reglist}^"));
13336 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13337 _("expression too complex"));
13339 mask
= inst
.operands
[0].imm
;
13340 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13341 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13342 else if (inst
.size_req
!= 4
13343 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13344 ? REG_LR
: REG_PC
)))
13346 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13347 inst
.instruction
|= THUMB_PP_PC_LR
;
13348 inst
.instruction
|= mask
& 0xff;
13350 else if (unified_syntax
)
13352 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13353 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13357 inst
.error
= _("invalid register list to push/pop instruction");
13365 if (unified_syntax
)
13366 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13369 inst
.error
= _("invalid register list to push/pop instruction");
13375 do_t_vscclrm (void)
13377 if (inst
.operands
[0].issingle
)
13379 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13380 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13381 inst
.instruction
|= inst
.operands
[0].imm
;
13385 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13386 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13387 inst
.instruction
|= 1 << 8;
13388 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13397 Rd
= inst
.operands
[0].reg
;
13398 Rm
= inst
.operands
[1].reg
;
13400 reject_bad_reg (Rd
);
13401 reject_bad_reg (Rm
);
13403 inst
.instruction
|= Rd
<< 8;
13404 inst
.instruction
|= Rm
<< 16;
13405 inst
.instruction
|= Rm
;
13413 Rd
= inst
.operands
[0].reg
;
13414 Rm
= inst
.operands
[1].reg
;
13416 reject_bad_reg (Rd
);
13417 reject_bad_reg (Rm
);
13419 if (Rd
<= 7 && Rm
<= 7
13420 && inst
.size_req
!= 4)
13422 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13423 inst
.instruction
|= Rd
;
13424 inst
.instruction
|= Rm
<< 3;
13426 else if (unified_syntax
)
13428 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13429 inst
.instruction
|= Rd
<< 8;
13430 inst
.instruction
|= Rm
<< 16;
13431 inst
.instruction
|= Rm
;
13434 inst
.error
= BAD_HIREG
;
13442 Rd
= inst
.operands
[0].reg
;
13443 Rm
= inst
.operands
[1].reg
;
13445 reject_bad_reg (Rd
);
13446 reject_bad_reg (Rm
);
13448 inst
.instruction
|= Rd
<< 8;
13449 inst
.instruction
|= Rm
;
13457 Rd
= inst
.operands
[0].reg
;
13458 Rs
= (inst
.operands
[1].present
13459 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13460 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13462 reject_bad_reg (Rd
);
13463 reject_bad_reg (Rs
);
13464 if (inst
.operands
[2].isreg
)
13465 reject_bad_reg (inst
.operands
[2].reg
);
13467 inst
.instruction
|= Rd
<< 8;
13468 inst
.instruction
|= Rs
<< 16;
13469 if (!inst
.operands
[2].isreg
)
13471 bfd_boolean narrow
;
13473 if ((inst
.instruction
& 0x00100000) != 0)
13474 narrow
= !in_pred_block ();
13476 narrow
= in_pred_block ();
13478 if (Rd
> 7 || Rs
> 7)
13481 if (inst
.size_req
== 4 || !unified_syntax
)
13484 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13485 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13488 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13489 relaxation, but it doesn't seem worth the hassle. */
13492 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13493 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13494 inst
.instruction
|= Rs
<< 3;
13495 inst
.instruction
|= Rd
;
13499 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13500 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13504 encode_thumb32_shifted_operand (2);
13510 if (warn_on_deprecated
13511 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13512 as_tsktsk (_("setend use is deprecated for ARMv8"));
13514 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13515 if (inst
.operands
[0].imm
)
13516 inst
.instruction
|= 0x8;
13522 if (!inst
.operands
[1].present
)
13523 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13525 if (unified_syntax
)
13527 bfd_boolean narrow
;
13530 switch (inst
.instruction
)
13533 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13535 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13537 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13539 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13543 if (THUMB_SETS_FLAGS (inst
.instruction
))
13544 narrow
= !in_pred_block ();
13546 narrow
= in_pred_block ();
13547 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13549 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13551 if (inst
.operands
[2].isreg
13552 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13553 || inst
.operands
[2].reg
> 7))
13555 if (inst
.size_req
== 4)
13558 reject_bad_reg (inst
.operands
[0].reg
);
13559 reject_bad_reg (inst
.operands
[1].reg
);
13563 if (inst
.operands
[2].isreg
)
13565 reject_bad_reg (inst
.operands
[2].reg
);
13566 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13567 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13568 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13569 inst
.instruction
|= inst
.operands
[2].reg
;
13571 /* PR 12854: Error on extraneous shifts. */
13572 constraint (inst
.operands
[2].shifted
,
13573 _("extraneous shift as part of operand to shift insn"));
13577 inst
.operands
[1].shifted
= 1;
13578 inst
.operands
[1].shift_kind
= shift_kind
;
13579 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13580 ? T_MNEM_movs
: T_MNEM_mov
);
13581 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13582 encode_thumb32_shifted_operand (1);
13583 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13584 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13589 if (inst
.operands
[2].isreg
)
13591 switch (shift_kind
)
13593 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13594 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13595 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13596 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13600 inst
.instruction
|= inst
.operands
[0].reg
;
13601 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13603 /* PR 12854: Error on extraneous shifts. */
13604 constraint (inst
.operands
[2].shifted
,
13605 _("extraneous shift as part of operand to shift insn"));
13609 switch (shift_kind
)
13611 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13612 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13613 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13616 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13617 inst
.instruction
|= inst
.operands
[0].reg
;
13618 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13624 constraint (inst
.operands
[0].reg
> 7
13625 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13626 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13628 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13630 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13631 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13632 _("source1 and dest must be same register"));
13634 switch (inst
.instruction
)
13636 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13637 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13638 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13639 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13643 inst
.instruction
|= inst
.operands
[0].reg
;
13644 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13646 /* PR 12854: Error on extraneous shifts. */
13647 constraint (inst
.operands
[2].shifted
,
13648 _("extraneous shift as part of operand to shift insn"));
13652 switch (inst
.instruction
)
13654 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13655 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13656 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13657 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13660 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13661 inst
.instruction
|= inst
.operands
[0].reg
;
13662 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13670 unsigned Rd
, Rn
, Rm
;
13672 Rd
= inst
.operands
[0].reg
;
13673 Rn
= inst
.operands
[1].reg
;
13674 Rm
= inst
.operands
[2].reg
;
13676 reject_bad_reg (Rd
);
13677 reject_bad_reg (Rn
);
13678 reject_bad_reg (Rm
);
13680 inst
.instruction
|= Rd
<< 8;
13681 inst
.instruction
|= Rn
<< 16;
13682 inst
.instruction
|= Rm
;
13688 unsigned Rd
, Rn
, Rm
;
13690 Rd
= inst
.operands
[0].reg
;
13691 Rm
= inst
.operands
[1].reg
;
13692 Rn
= inst
.operands
[2].reg
;
13694 reject_bad_reg (Rd
);
13695 reject_bad_reg (Rn
);
13696 reject_bad_reg (Rm
);
13698 inst
.instruction
|= Rd
<< 8;
13699 inst
.instruction
|= Rn
<< 16;
13700 inst
.instruction
|= Rm
;
13706 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13708 _("SMC is not permitted on this architecture"));
13709 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13710 _("expression too complex"));
13711 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13712 inst
.instruction
|= (value
& 0xf000) >> 12;
13713 inst
.instruction
|= (value
& 0x0ff0);
13714 inst
.instruction
|= (value
& 0x000f) << 16;
13715 /* PR gas/15623: SMC instructions must be last in an IT block. */
13716 set_pred_insn_type_last ();
13722 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13724 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13725 inst
.instruction
|= (value
& 0x0fff);
13726 inst
.instruction
|= (value
& 0xf000) << 4;
13730 do_t_ssat_usat (int bias
)
13734 Rd
= inst
.operands
[0].reg
;
13735 Rn
= inst
.operands
[2].reg
;
13737 reject_bad_reg (Rd
);
13738 reject_bad_reg (Rn
);
13740 inst
.instruction
|= Rd
<< 8;
13741 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13742 inst
.instruction
|= Rn
<< 16;
13744 if (inst
.operands
[3].present
)
13746 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13748 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13750 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13751 _("expression too complex"));
13753 if (shift_amount
!= 0)
13755 constraint (shift_amount
> 31,
13756 _("shift expression is too large"));
13758 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13759 inst
.instruction
|= 0x00200000; /* sh bit. */
13761 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13762 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13770 do_t_ssat_usat (1);
13778 Rd
= inst
.operands
[0].reg
;
13779 Rn
= inst
.operands
[2].reg
;
13781 reject_bad_reg (Rd
);
13782 reject_bad_reg (Rn
);
13784 inst
.instruction
|= Rd
<< 8;
13785 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13786 inst
.instruction
|= Rn
<< 16;
13792 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13793 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13794 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13795 || inst
.operands
[2].negative
,
13798 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13800 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13801 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13802 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13803 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13809 if (!inst
.operands
[2].present
)
13810 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13812 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13813 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13814 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13817 inst
.instruction
|= inst
.operands
[0].reg
;
13818 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13819 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13820 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13826 unsigned Rd
, Rn
, Rm
;
13828 Rd
= inst
.operands
[0].reg
;
13829 Rn
= inst
.operands
[1].reg
;
13830 Rm
= inst
.operands
[2].reg
;
13832 reject_bad_reg (Rd
);
13833 reject_bad_reg (Rn
);
13834 reject_bad_reg (Rm
);
13836 inst
.instruction
|= Rd
<< 8;
13837 inst
.instruction
|= Rn
<< 16;
13838 inst
.instruction
|= Rm
;
13839 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13847 Rd
= inst
.operands
[0].reg
;
13848 Rm
= inst
.operands
[1].reg
;
13850 reject_bad_reg (Rd
);
13851 reject_bad_reg (Rm
);
13853 if (inst
.instruction
<= 0xffff
13854 && inst
.size_req
!= 4
13855 && Rd
<= 7 && Rm
<= 7
13856 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13859 inst
.instruction
|= Rd
;
13860 inst
.instruction
|= Rm
<< 3;
13862 else if (unified_syntax
)
13864 if (inst
.instruction
<= 0xffff)
13865 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13866 inst
.instruction
|= Rd
<< 8;
13867 inst
.instruction
|= Rm
;
13868 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13872 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13873 _("Thumb encoding does not support rotation"));
13874 constraint (1, BAD_HIREG
);
13881 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13890 half
= (inst
.instruction
& 0x10) != 0;
13891 set_pred_insn_type_last ();
13892 constraint (inst
.operands
[0].immisreg
,
13893 _("instruction requires register index"));
13895 Rn
= inst
.operands
[0].reg
;
13896 Rm
= inst
.operands
[0].imm
;
13898 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13899 constraint (Rn
== REG_SP
, BAD_SP
);
13900 reject_bad_reg (Rm
);
13902 constraint (!half
&& inst
.operands
[0].shifted
,
13903 _("instruction does not allow shifted index"));
13904 inst
.instruction
|= (Rn
<< 16) | Rm
;
13910 if (!inst
.operands
[0].present
)
13911 inst
.operands
[0].imm
= 0;
13913 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13915 constraint (inst
.size_req
== 2,
13916 _("immediate value out of range"));
13917 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13918 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13919 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13923 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13924 inst
.instruction
|= inst
.operands
[0].imm
;
13927 set_pred_insn_type (NEUTRAL_IT_INSN
);
13934 do_t_ssat_usat (0);
13942 Rd
= inst
.operands
[0].reg
;
13943 Rn
= inst
.operands
[2].reg
;
13945 reject_bad_reg (Rd
);
13946 reject_bad_reg (Rn
);
13948 inst
.instruction
|= Rd
<< 8;
13949 inst
.instruction
|= inst
.operands
[1].imm
;
13950 inst
.instruction
|= Rn
<< 16;
13953 /* Checking the range of the branch offset (VAL) with NBITS bits
13954 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13956 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13958 gas_assert (nbits
> 0 && nbits
<= 32);
13961 int cmp
= (1 << (nbits
- 1));
13962 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13967 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13973 /* For branches in Armv8.1-M Mainline. */
13975 do_t_branch_future (void)
13977 unsigned long insn
= inst
.instruction
;
13979 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13980 if (inst
.operands
[0].hasreloc
== 0)
13982 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13983 as_bad (BAD_BRANCH_OFF
);
13985 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13989 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13990 inst
.relocs
[0].pc_rel
= 1;
13996 if (inst
.operands
[1].hasreloc
== 0)
13998 int val
= inst
.operands
[1].imm
;
13999 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14000 as_bad (BAD_BRANCH_OFF
);
14002 int immA
= (val
& 0x0001f000) >> 12;
14003 int immB
= (val
& 0x00000ffc) >> 2;
14004 int immC
= (val
& 0x00000002) >> 1;
14005 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14009 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14010 inst
.relocs
[1].pc_rel
= 1;
14015 if (inst
.operands
[1].hasreloc
== 0)
14017 int val
= inst
.operands
[1].imm
;
14018 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14019 as_bad (BAD_BRANCH_OFF
);
14021 int immA
= (val
& 0x0007f000) >> 12;
14022 int immB
= (val
& 0x00000ffc) >> 2;
14023 int immC
= (val
& 0x00000002) >> 1;
14024 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14028 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14029 inst
.relocs
[1].pc_rel
= 1;
14033 case T_MNEM_bfcsel
:
14035 if (inst
.operands
[1].hasreloc
== 0)
14037 int val
= inst
.operands
[1].imm
;
14038 int immA
= (val
& 0x00001000) >> 12;
14039 int immB
= (val
& 0x00000ffc) >> 2;
14040 int immC
= (val
& 0x00000002) >> 1;
14041 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14045 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14046 inst
.relocs
[1].pc_rel
= 1;
14050 if (inst
.operands
[2].hasreloc
== 0)
14052 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14053 int val2
= inst
.operands
[2].imm
;
14054 int val0
= inst
.operands
[0].imm
& 0x1f;
14055 int diff
= val2
- val0
;
14057 inst
.instruction
|= 1 << 17; /* T bit. */
14058 else if (diff
!= 2)
14059 as_bad (_("out of range label-relative fixup value"));
14063 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14064 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14065 inst
.relocs
[2].pc_rel
= 1;
14069 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14070 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14082 /* Helper function for do_t_loloop to handle relocations. */
14084 v8_1_loop_reloc (int is_le
)
14086 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14088 int value
= inst
.relocs
[0].exp
.X_add_number
;
14089 value
= (is_le
) ? -value
: value
;
14091 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14092 as_bad (BAD_BRANCH_OFF
);
14096 immh
= (value
& 0x00000ffc) >> 2;
14097 imml
= (value
& 0x00000002) >> 1;
14099 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14103 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14104 inst
.relocs
[0].pc_rel
= 1;
14108 /* To handle the Scalar Low Overhead Loop instructions
14109 in Armv8.1-M Mainline. */
14113 unsigned long insn
= inst
.instruction
;
14115 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14116 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14122 if (!inst
.operands
[0].present
)
14123 inst
.instruction
|= 1 << 21;
14125 v8_1_loop_reloc (TRUE
);
14129 v8_1_loop_reloc (FALSE
);
14130 /* Fall through. */
14132 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14133 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14140 /* MVE instruction encoder helpers. */
14141 #define M_MNEM_vabav 0xee800f01
14142 #define M_MNEM_vmladav 0xeef00e00
14143 #define M_MNEM_vmladava 0xeef00e20
14144 #define M_MNEM_vmladavx 0xeef01e00
14145 #define M_MNEM_vmladavax 0xeef01e20
14146 #define M_MNEM_vmlsdav 0xeef00e01
14147 #define M_MNEM_vmlsdava 0xeef00e21
14148 #define M_MNEM_vmlsdavx 0xeef01e01
14149 #define M_MNEM_vmlsdavax 0xeef01e21
14150 #define M_MNEM_vmullt 0xee011e00
14151 #define M_MNEM_vmullb 0xee010e00
14152 #define M_MNEM_vst20 0xfc801e00
14153 #define M_MNEM_vst21 0xfc801e20
14154 #define M_MNEM_vst40 0xfc801e01
14155 #define M_MNEM_vst41 0xfc801e21
14156 #define M_MNEM_vst42 0xfc801e41
14157 #define M_MNEM_vst43 0xfc801e61
14158 #define M_MNEM_vld20 0xfc901e00
14159 #define M_MNEM_vld21 0xfc901e20
14160 #define M_MNEM_vld40 0xfc901e01
14161 #define M_MNEM_vld41 0xfc901e21
14162 #define M_MNEM_vld42 0xfc901e41
14163 #define M_MNEM_vld43 0xfc901e61
14164 #define M_MNEM_vstrb 0xec000e00
14165 #define M_MNEM_vstrh 0xec000e10
14166 #define M_MNEM_vstrw 0xec000e40
14167 #define M_MNEM_vstrd 0xec000e50
14168 #define M_MNEM_vldrb 0xec100e00
14169 #define M_MNEM_vldrh 0xec100e10
14170 #define M_MNEM_vldrw 0xec100e40
14171 #define M_MNEM_vldrd 0xec100e50
14172 #define M_MNEM_vmovlt 0xeea01f40
14173 #define M_MNEM_vmovlb 0xeea00f40
14174 #define M_MNEM_vmovnt 0xfe311e81
14175 #define M_MNEM_vmovnb 0xfe310e81
14176 #define M_MNEM_vadc 0xee300f00
14177 #define M_MNEM_vadci 0xee301f00
14178 #define M_MNEM_vbrsr 0xfe011e60
14179 #define M_MNEM_vaddlv 0xee890f00
14180 #define M_MNEM_vaddlva 0xee890f20
14181 #define M_MNEM_vaddv 0xeef10f00
14182 #define M_MNEM_vaddva 0xeef10f20
14183 #define M_MNEM_vddup 0xee011f6e
14184 #define M_MNEM_vdwdup 0xee011f60
14185 #define M_MNEM_vidup 0xee010f6e
14186 #define M_MNEM_viwdup 0xee010f60
14187 #define M_MNEM_vmaxv 0xeee20f00
14188 #define M_MNEM_vmaxav 0xeee00f00
14189 #define M_MNEM_vminv 0xeee20f80
14190 #define M_MNEM_vminav 0xeee00f80
14191 #define M_MNEM_vmlaldav 0xee800e00
14192 #define M_MNEM_vmlaldava 0xee800e20
14193 #define M_MNEM_vmlaldavx 0xee801e00
14194 #define M_MNEM_vmlaldavax 0xee801e20
14195 #define M_MNEM_vmlsldav 0xee800e01
14196 #define M_MNEM_vmlsldava 0xee800e21
14197 #define M_MNEM_vmlsldavx 0xee801e01
14198 #define M_MNEM_vmlsldavax 0xee801e21
14199 #define M_MNEM_vrmlaldavhx 0xee801f00
14200 #define M_MNEM_vrmlaldavhax 0xee801f20
14201 #define M_MNEM_vrmlsldavh 0xfe800e01
14202 #define M_MNEM_vrmlsldavha 0xfe800e21
14203 #define M_MNEM_vrmlsldavhx 0xfe801e01
14204 #define M_MNEM_vrmlsldavhax 0xfe801e21
14205 #define M_MNEM_vqmovnt 0xee331e01
14206 #define M_MNEM_vqmovnb 0xee330e01
14207 #define M_MNEM_vqmovunt 0xee311e81
14208 #define M_MNEM_vqmovunb 0xee310e81
14209 #define M_MNEM_vshrnt 0xee801fc1
14210 #define M_MNEM_vshrnb 0xee800fc1
14211 #define M_MNEM_vrshrnt 0xfe801fc1
14212 #define M_MNEM_vqshrnt 0xee801f40
14213 #define M_MNEM_vqshrnb 0xee800f40
14214 #define M_MNEM_vqshrunt 0xee801fc0
14215 #define M_MNEM_vqshrunb 0xee800fc0
14216 #define M_MNEM_vrshrnb 0xfe800fc1
14217 #define M_MNEM_vqrshrnt 0xee801f41
14218 #define M_MNEM_vqrshrnb 0xee800f41
14219 #define M_MNEM_vqrshrunt 0xfe801fc0
14220 #define M_MNEM_vqrshrunb 0xfe800fc0
14222 /* Neon instruction encoder helpers. */
14224 /* Encodings for the different types for various Neon opcodes. */
14226 /* An "invalid" code for the following tables. */
14229 struct neon_tab_entry
14232 unsigned float_or_poly
;
14233 unsigned scalar_or_imm
;
14236 /* Map overloaded Neon opcodes to their respective encodings. */
14237 #define NEON_ENC_TAB \
14238 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14239 X(vabdl, 0x0800700, N_INV, N_INV), \
14240 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14241 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14242 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14243 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14244 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14245 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14246 X(vaddl, 0x0800000, N_INV, N_INV), \
14247 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14248 X(vsubl, 0x0800200, N_INV, N_INV), \
14249 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14250 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14251 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14252 /* Register variants of the following two instructions are encoded as
14253 vcge / vcgt with the operands reversed. */ \
14254 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14255 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14256 X(vfma, N_INV, 0x0000c10, N_INV), \
14257 X(vfms, N_INV, 0x0200c10, N_INV), \
14258 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14259 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14260 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14261 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14262 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14263 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14264 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14265 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14266 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14267 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14268 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14269 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14270 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14271 X(vshl, 0x0000400, N_INV, 0x0800510), \
14272 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14273 X(vand, 0x0000110, N_INV, 0x0800030), \
14274 X(vbic, 0x0100110, N_INV, 0x0800030), \
14275 X(veor, 0x1000110, N_INV, N_INV), \
14276 X(vorn, 0x0300110, N_INV, 0x0800010), \
14277 X(vorr, 0x0200110, N_INV, 0x0800010), \
14278 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14279 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14280 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14281 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14282 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14283 X(vst1, 0x0000000, 0x0800000, N_INV), \
14284 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14285 X(vst2, 0x0000100, 0x0800100, N_INV), \
14286 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14287 X(vst3, 0x0000200, 0x0800200, N_INV), \
14288 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14289 X(vst4, 0x0000300, 0x0800300, N_INV), \
14290 X(vmovn, 0x1b20200, N_INV, N_INV), \
14291 X(vtrn, 0x1b20080, N_INV, N_INV), \
14292 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14293 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14294 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14295 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14296 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14297 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14298 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14299 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14300 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14301 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14302 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14303 X(vseleq, 0xe000a00, N_INV, N_INV), \
14304 X(vselvs, 0xe100a00, N_INV, N_INV), \
14305 X(vselge, 0xe200a00, N_INV, N_INV), \
14306 X(vselgt, 0xe300a00, N_INV, N_INV), \
14307 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14308 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14309 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14310 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14311 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14312 X(aes, 0x3b00300, N_INV, N_INV), \
14313 X(sha3op, 0x2000c00, N_INV, N_INV), \
14314 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14315 X(sha2op, 0x3ba0380, N_INV, N_INV)
14319 #define X(OPC,I,F,S) N_MNEM_##OPC
14324 static const struct neon_tab_entry neon_enc_tab
[] =
14326 #define X(OPC,I,F,S) { (I), (F), (S) }
14331 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14332 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14333 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14334 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14335 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14336 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14337 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14338 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14339 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14340 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14341 #define NEON_ENC_SINGLE_(X) \
14342 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14343 #define NEON_ENC_DOUBLE_(X) \
14344 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14345 #define NEON_ENC_FPV8_(X) \
14346 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14348 #define NEON_ENCODE(type, inst) \
14351 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14352 inst.is_neon = 1; \
14356 #define check_neon_suffixes \
14359 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14361 as_bad (_("invalid neon suffix for non neon instruction")); \
14367 /* Define shapes for instruction operands. The following mnemonic characters
14368 are used in this table:
14370 F - VFP S<n> register
14371 D - Neon D<n> register
14372 Q - Neon Q<n> register
14376 L - D<n> register list
14378 This table is used to generate various data:
14379 - enumerations of the form NS_DDR to be used as arguments to
14381 - a table classifying shapes into single, double, quad, mixed.
14382 - a table used to drive neon_select_shape. */
14384 #define NEON_SHAPE_DEF \
14385 X(4, (R, R, Q, Q), QUAD), \
14386 X(4, (Q, R, R, I), QUAD), \
14387 X(4, (R, R, S, S), QUAD), \
14388 X(4, (S, S, R, R), QUAD), \
14389 X(3, (Q, R, I), QUAD), \
14390 X(3, (I, Q, Q), QUAD), \
14391 X(3, (I, Q, R), QUAD), \
14392 X(3, (R, Q, Q), QUAD), \
14393 X(3, (D, D, D), DOUBLE), \
14394 X(3, (Q, Q, Q), QUAD), \
14395 X(3, (D, D, I), DOUBLE), \
14396 X(3, (Q, Q, I), QUAD), \
14397 X(3, (D, D, S), DOUBLE), \
14398 X(3, (Q, Q, S), QUAD), \
14399 X(3, (Q, Q, R), QUAD), \
14400 X(3, (R, R, Q), QUAD), \
14401 X(2, (R, Q), QUAD), \
14402 X(2, (D, D), DOUBLE), \
14403 X(2, (Q, Q), QUAD), \
14404 X(2, (D, S), DOUBLE), \
14405 X(2, (Q, S), QUAD), \
14406 X(2, (D, R), DOUBLE), \
14407 X(2, (Q, R), QUAD), \
14408 X(2, (D, I), DOUBLE), \
14409 X(2, (Q, I), QUAD), \
14410 X(3, (D, L, D), DOUBLE), \
14411 X(2, (D, Q), MIXED), \
14412 X(2, (Q, D), MIXED), \
14413 X(3, (D, Q, I), MIXED), \
14414 X(3, (Q, D, I), MIXED), \
14415 X(3, (Q, D, D), MIXED), \
14416 X(3, (D, Q, Q), MIXED), \
14417 X(3, (Q, Q, D), MIXED), \
14418 X(3, (Q, D, S), MIXED), \
14419 X(3, (D, Q, S), MIXED), \
14420 X(4, (D, D, D, I), DOUBLE), \
14421 X(4, (Q, Q, Q, I), QUAD), \
14422 X(4, (D, D, S, I), DOUBLE), \
14423 X(4, (Q, Q, S, I), QUAD), \
14424 X(2, (F, F), SINGLE), \
14425 X(3, (F, F, F), SINGLE), \
14426 X(2, (F, I), SINGLE), \
14427 X(2, (F, D), MIXED), \
14428 X(2, (D, F), MIXED), \
14429 X(3, (F, F, I), MIXED), \
14430 X(4, (R, R, F, F), SINGLE), \
14431 X(4, (F, F, R, R), SINGLE), \
14432 X(3, (D, R, R), DOUBLE), \
14433 X(3, (R, R, D), DOUBLE), \
14434 X(2, (S, R), SINGLE), \
14435 X(2, (R, S), SINGLE), \
14436 X(2, (F, R), SINGLE), \
14437 X(2, (R, F), SINGLE), \
14438 /* Half float shape supported so far. */\
14439 X (2, (H, D), MIXED), \
14440 X (2, (D, H), MIXED), \
14441 X (2, (H, F), MIXED), \
14442 X (2, (F, H), MIXED), \
14443 X (2, (H, H), HALF), \
14444 X (2, (H, R), HALF), \
14445 X (2, (R, H), HALF), \
14446 X (2, (H, I), HALF), \
14447 X (3, (H, H, H), HALF), \
14448 X (3, (H, F, I), MIXED), \
14449 X (3, (F, H, I), MIXED), \
14450 X (3, (D, H, H), MIXED), \
14451 X (3, (D, H, S), MIXED)
14453 #define S2(A,B) NS_##A##B
14454 #define S3(A,B,C) NS_##A##B##C
14455 #define S4(A,B,C,D) NS_##A##B##C##D
14457 #define X(N, L, C) S##N L
14470 enum neon_shape_class
14479 #define X(N, L, C) SC_##C
14481 static enum neon_shape_class neon_shape_class
[] =
14500 /* Register widths of above. */
14501 static unsigned neon_shape_el_size
[] =
14513 struct neon_shape_info
14516 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14519 #define S2(A,B) { SE_##A, SE_##B }
14520 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14521 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14523 #define X(N, L, C) { N, S##N L }
14525 static struct neon_shape_info neon_shape_tab
[] =
14535 /* Bit masks used in type checking given instructions.
14536 'N_EQK' means the type must be the same as (or based on in some way) the key
14537 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14538 set, various other bits can be set as well in order to modify the meaning of
14539 the type constraint. */
14541 enum neon_type_mask
14565 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14566 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14567 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14568 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14569 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14570 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14571 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14572 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14573 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14574 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14575 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14577 N_MAX_NONSPECIAL
= N_P64
14580 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14582 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14583 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14584 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14585 #define N_S_32 (N_S8 | N_S16 | N_S32)
14586 #define N_F_16_32 (N_F16 | N_F32)
14587 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14588 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14589 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14590 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14591 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14592 #define N_F_MVE (N_F16 | N_F32)
14593 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14595 /* Pass this as the first type argument to neon_check_type to ignore types
14597 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14599 /* Select a "shape" for the current instruction (describing register types or
14600 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14601 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14602 function of operand parsing, so this function doesn't need to be called.
14603 Shapes should be listed in order of decreasing length. */
14605 static enum neon_shape
14606 neon_select_shape (enum neon_shape shape
, ...)
14609 enum neon_shape first_shape
= shape
;
14611 /* Fix missing optional operands. FIXME: we don't know at this point how
14612 many arguments we should have, so this makes the assumption that we have
14613 > 1. This is true of all current Neon opcodes, I think, but may not be
14614 true in the future. */
14615 if (!inst
.operands
[1].present
)
14616 inst
.operands
[1] = inst
.operands
[0];
14618 va_start (ap
, shape
);
14620 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14625 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14627 if (!inst
.operands
[j
].present
)
14633 switch (neon_shape_tab
[shape
].el
[j
])
14635 /* If a .f16, .16, .u16, .s16 type specifier is given over
14636 a VFP single precision register operand, it's essentially
14637 means only half of the register is used.
14639 If the type specifier is given after the mnemonics, the
14640 information is stored in inst.vectype. If the type specifier
14641 is given after register operand, the information is stored
14642 in inst.operands[].vectype.
14644 When there is only one type specifier, and all the register
14645 operands are the same type of hardware register, the type
14646 specifier applies to all register operands.
14648 If no type specifier is given, the shape is inferred from
14649 operand information.
14652 vadd.f16 s0, s1, s2: NS_HHH
14653 vabs.f16 s0, s1: NS_HH
14654 vmov.f16 s0, r1: NS_HR
14655 vmov.f16 r0, s1: NS_RH
14656 vcvt.f16 r0, s1: NS_RH
14657 vcvt.f16.s32 s2, s2, #29: NS_HFI
14658 vcvt.f16.s32 s2, s2: NS_HF
14661 if (!(inst
.operands
[j
].isreg
14662 && inst
.operands
[j
].isvec
14663 && inst
.operands
[j
].issingle
14664 && !inst
.operands
[j
].isquad
14665 && ((inst
.vectype
.elems
== 1
14666 && inst
.vectype
.el
[0].size
== 16)
14667 || (inst
.vectype
.elems
> 1
14668 && inst
.vectype
.el
[j
].size
== 16)
14669 || (inst
.vectype
.elems
== 0
14670 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14671 && inst
.operands
[j
].vectype
.size
== 16))))
14676 if (!(inst
.operands
[j
].isreg
14677 && inst
.operands
[j
].isvec
14678 && inst
.operands
[j
].issingle
14679 && !inst
.operands
[j
].isquad
14680 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14681 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14682 || (inst
.vectype
.elems
== 0
14683 && (inst
.operands
[j
].vectype
.size
== 32
14684 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14689 if (!(inst
.operands
[j
].isreg
14690 && inst
.operands
[j
].isvec
14691 && !inst
.operands
[j
].isquad
14692 && !inst
.operands
[j
].issingle
))
14697 if (!(inst
.operands
[j
].isreg
14698 && !inst
.operands
[j
].isvec
))
14703 if (!(inst
.operands
[j
].isreg
14704 && inst
.operands
[j
].isvec
14705 && inst
.operands
[j
].isquad
14706 && !inst
.operands
[j
].issingle
))
14711 if (!(!inst
.operands
[j
].isreg
14712 && !inst
.operands
[j
].isscalar
))
14717 if (!(!inst
.operands
[j
].isreg
14718 && inst
.operands
[j
].isscalar
))
14728 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14729 /* We've matched all the entries in the shape table, and we don't
14730 have any left over operands which have not been matched. */
14736 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14737 first_error (_("invalid instruction shape"));
14742 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14743 means the Q bit should be set). */
14746 neon_quad (enum neon_shape shape
)
14748 return neon_shape_class
[shape
] == SC_QUAD
;
14752 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14755 /* Allow modification to be made to types which are constrained to be
14756 based on the key element, based on bits set alongside N_EQK. */
14757 if ((typebits
& N_EQK
) != 0)
14759 if ((typebits
& N_HLF
) != 0)
14761 else if ((typebits
& N_DBL
) != 0)
14763 if ((typebits
& N_SGN
) != 0)
14764 *g_type
= NT_signed
;
14765 else if ((typebits
& N_UNS
) != 0)
14766 *g_type
= NT_unsigned
;
14767 else if ((typebits
& N_INT
) != 0)
14768 *g_type
= NT_integer
;
14769 else if ((typebits
& N_FLT
) != 0)
14770 *g_type
= NT_float
;
14771 else if ((typebits
& N_SIZ
) != 0)
14772 *g_type
= NT_untyped
;
14776 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14777 operand type, i.e. the single type specified in a Neon instruction when it
14778 is the only one given. */
14780 static struct neon_type_el
14781 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14783 struct neon_type_el dest
= *key
;
14785 gas_assert ((thisarg
& N_EQK
) != 0);
14787 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14792 /* Convert Neon type and size into compact bitmask representation. */
14794 static enum neon_type_mask
14795 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14802 case 8: return N_8
;
14803 case 16: return N_16
;
14804 case 32: return N_32
;
14805 case 64: return N_64
;
14813 case 8: return N_I8
;
14814 case 16: return N_I16
;
14815 case 32: return N_I32
;
14816 case 64: return N_I64
;
14824 case 16: return N_F16
;
14825 case 32: return N_F32
;
14826 case 64: return N_F64
;
14834 case 8: return N_P8
;
14835 case 16: return N_P16
;
14836 case 64: return N_P64
;
14844 case 8: return N_S8
;
14845 case 16: return N_S16
;
14846 case 32: return N_S32
;
14847 case 64: return N_S64
;
14855 case 8: return N_U8
;
14856 case 16: return N_U16
;
14857 case 32: return N_U32
;
14858 case 64: return N_U64
;
14869 /* Convert compact Neon bitmask type representation to a type and size. Only
14870 handles the case where a single bit is set in the mask. */
14873 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14874 enum neon_type_mask mask
)
14876 if ((mask
& N_EQK
) != 0)
14879 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14881 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14883 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14885 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14890 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14892 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14893 *type
= NT_unsigned
;
14894 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14895 *type
= NT_integer
;
14896 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14897 *type
= NT_untyped
;
14898 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14900 else if ((mask
& (N_F_ALL
)) != 0)
14908 /* Modify a bitmask of allowed types. This is only needed for type
14912 modify_types_allowed (unsigned allowed
, unsigned mods
)
14915 enum neon_el_type type
;
14921 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14923 if (el_type_of_type_chk (&type
, &size
,
14924 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14926 neon_modify_type_size (mods
, &type
, &size
);
14927 destmask
|= type_chk_of_el_type (type
, size
);
14934 /* Check type and return type classification.
14935 The manual states (paraphrase): If one datatype is given, it indicates the
14937 - the second operand, if there is one
14938 - the operand, if there is no second operand
14939 - the result, if there are no operands.
14940 This isn't quite good enough though, so we use a concept of a "key" datatype
14941 which is set on a per-instruction basis, which is the one which matters when
14942 only one data type is written.
14943 Note: this function has side-effects (e.g. filling in missing operands). All
14944 Neon instructions should call it before performing bit encoding. */
14946 static struct neon_type_el
14947 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14950 unsigned i
, pass
, key_el
= 0;
14951 unsigned types
[NEON_MAX_TYPE_ELS
];
14952 enum neon_el_type k_type
= NT_invtype
;
14953 unsigned k_size
= -1u;
14954 struct neon_type_el badtype
= {NT_invtype
, -1};
14955 unsigned key_allowed
= 0;
14957 /* Optional registers in Neon instructions are always (not) in operand 1.
14958 Fill in the missing operand here, if it was omitted. */
14959 if (els
> 1 && !inst
.operands
[1].present
)
14960 inst
.operands
[1] = inst
.operands
[0];
14962 /* Suck up all the varargs. */
14964 for (i
= 0; i
< els
; i
++)
14966 unsigned thisarg
= va_arg (ap
, unsigned);
14967 if (thisarg
== N_IGNORE_TYPE
)
14972 types
[i
] = thisarg
;
14973 if ((thisarg
& N_KEY
) != 0)
14978 if (inst
.vectype
.elems
> 0)
14979 for (i
= 0; i
< els
; i
++)
14980 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14982 first_error (_("types specified in both the mnemonic and operands"));
14986 /* Duplicate inst.vectype elements here as necessary.
14987 FIXME: No idea if this is exactly the same as the ARM assembler,
14988 particularly when an insn takes one register and one non-register
14990 if (inst
.vectype
.elems
== 1 && els
> 1)
14993 inst
.vectype
.elems
= els
;
14994 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14995 for (j
= 0; j
< els
; j
++)
14997 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15000 else if (inst
.vectype
.elems
== 0 && els
> 0)
15003 /* No types were given after the mnemonic, so look for types specified
15004 after each operand. We allow some flexibility here; as long as the
15005 "key" operand has a type, we can infer the others. */
15006 for (j
= 0; j
< els
; j
++)
15007 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15008 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15010 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15012 for (j
= 0; j
< els
; j
++)
15013 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15014 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15019 first_error (_("operand types can't be inferred"));
15023 else if (inst
.vectype
.elems
!= els
)
15025 first_error (_("type specifier has the wrong number of parts"));
15029 for (pass
= 0; pass
< 2; pass
++)
15031 for (i
= 0; i
< els
; i
++)
15033 unsigned thisarg
= types
[i
];
15034 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15035 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15036 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15037 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15039 /* Decay more-specific signed & unsigned types to sign-insensitive
15040 integer types if sign-specific variants are unavailable. */
15041 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15042 && (types_allowed
& N_SU_ALL
) == 0)
15043 g_type
= NT_integer
;
15045 /* If only untyped args are allowed, decay any more specific types to
15046 them. Some instructions only care about signs for some element
15047 sizes, so handle that properly. */
15048 if (((types_allowed
& N_UNT
) == 0)
15049 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15050 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15051 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15052 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15053 g_type
= NT_untyped
;
15057 if ((thisarg
& N_KEY
) != 0)
15061 key_allowed
= thisarg
& ~N_KEY
;
15063 /* Check architecture constraint on FP16 extension. */
15065 && k_type
== NT_float
15066 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15068 inst
.error
= _(BAD_FP16
);
15075 if ((thisarg
& N_VFP
) != 0)
15077 enum neon_shape_el regshape
;
15078 unsigned regwidth
, match
;
15080 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15083 first_error (_("invalid instruction shape"));
15086 regshape
= neon_shape_tab
[ns
].el
[i
];
15087 regwidth
= neon_shape_el_size
[regshape
];
15089 /* In VFP mode, operands must match register widths. If we
15090 have a key operand, use its width, else use the width of
15091 the current operand. */
15097 /* FP16 will use a single precision register. */
15098 if (regwidth
== 32 && match
== 16)
15100 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15104 inst
.error
= _(BAD_FP16
);
15109 if (regwidth
!= match
)
15111 first_error (_("operand size must match register width"));
15116 if ((thisarg
& N_EQK
) == 0)
15118 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15120 if ((given_type
& types_allowed
) == 0)
15122 first_error (BAD_SIMD_TYPE
);
15128 enum neon_el_type mod_k_type
= k_type
;
15129 unsigned mod_k_size
= k_size
;
15130 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15131 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15133 first_error (_("inconsistent types in Neon instruction"));
15141 return inst
.vectype
.el
[key_el
];
15144 /* Neon-style VFP instruction forwarding. */
15146 /* Thumb VFP instructions have 0xE in the condition field. */
15149 do_vfp_cond_or_thumb (void)
15154 inst
.instruction
|= 0xe0000000;
15156 inst
.instruction
|= inst
.cond
<< 28;
15159 /* Look up and encode a simple mnemonic, for use as a helper function for the
15160 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15161 etc. It is assumed that operand parsing has already been done, and that the
15162 operands are in the form expected by the given opcode (this isn't necessarily
15163 the same as the form in which they were parsed, hence some massaging must
15164 take place before this function is called).
15165 Checks current arch version against that in the looked-up opcode. */
15168 do_vfp_nsyn_opcode (const char *opname
)
15170 const struct asm_opcode
*opcode
;
15172 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15177 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15178 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15185 inst
.instruction
= opcode
->tvalue
;
15186 opcode
->tencode ();
15190 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15191 opcode
->aencode ();
15196 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15198 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15200 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15203 do_vfp_nsyn_opcode ("fadds");
15205 do_vfp_nsyn_opcode ("fsubs");
15207 /* ARMv8.2 fp16 instruction. */
15209 do_scalar_fp16_v82_encode ();
15214 do_vfp_nsyn_opcode ("faddd");
15216 do_vfp_nsyn_opcode ("fsubd");
15220 /* Check operand types to see if this is a VFP instruction, and if so call
15224 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15226 enum neon_shape rs
;
15227 struct neon_type_el et
;
15232 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15233 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15237 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15238 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15239 N_F_ALL
| N_KEY
| N_VFP
);
15246 if (et
.type
!= NT_invtype
)
15257 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15259 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15261 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15264 do_vfp_nsyn_opcode ("fmacs");
15266 do_vfp_nsyn_opcode ("fnmacs");
15268 /* ARMv8.2 fp16 instruction. */
15270 do_scalar_fp16_v82_encode ();
15275 do_vfp_nsyn_opcode ("fmacd");
15277 do_vfp_nsyn_opcode ("fnmacd");
15282 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15284 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15286 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15289 do_vfp_nsyn_opcode ("ffmas");
15291 do_vfp_nsyn_opcode ("ffnmas");
15293 /* ARMv8.2 fp16 instruction. */
15295 do_scalar_fp16_v82_encode ();
15300 do_vfp_nsyn_opcode ("ffmad");
15302 do_vfp_nsyn_opcode ("ffnmad");
15307 do_vfp_nsyn_mul (enum neon_shape rs
)
15309 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15311 do_vfp_nsyn_opcode ("fmuls");
15313 /* ARMv8.2 fp16 instruction. */
15315 do_scalar_fp16_v82_encode ();
15318 do_vfp_nsyn_opcode ("fmuld");
15322 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15324 int is_neg
= (inst
.instruction
& 0x80) != 0;
15325 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15327 if (rs
== NS_FF
|| rs
== NS_HH
)
15330 do_vfp_nsyn_opcode ("fnegs");
15332 do_vfp_nsyn_opcode ("fabss");
15334 /* ARMv8.2 fp16 instruction. */
15336 do_scalar_fp16_v82_encode ();
15341 do_vfp_nsyn_opcode ("fnegd");
15343 do_vfp_nsyn_opcode ("fabsd");
15347 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15348 insns belong to Neon, and are handled elsewhere. */
15351 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15353 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15357 do_vfp_nsyn_opcode ("fldmdbs");
15359 do_vfp_nsyn_opcode ("fldmias");
15364 do_vfp_nsyn_opcode ("fstmdbs");
15366 do_vfp_nsyn_opcode ("fstmias");
15371 do_vfp_nsyn_sqrt (void)
15373 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15374 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15376 if (rs
== NS_FF
|| rs
== NS_HH
)
15378 do_vfp_nsyn_opcode ("fsqrts");
15380 /* ARMv8.2 fp16 instruction. */
15382 do_scalar_fp16_v82_encode ();
15385 do_vfp_nsyn_opcode ("fsqrtd");
15389 do_vfp_nsyn_div (void)
15391 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15392 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15393 N_F_ALL
| N_KEY
| N_VFP
);
15395 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15397 do_vfp_nsyn_opcode ("fdivs");
15399 /* ARMv8.2 fp16 instruction. */
15401 do_scalar_fp16_v82_encode ();
15404 do_vfp_nsyn_opcode ("fdivd");
15408 do_vfp_nsyn_nmul (void)
15410 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15411 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15412 N_F_ALL
| N_KEY
| N_VFP
);
15414 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15416 NEON_ENCODE (SINGLE
, inst
);
15417 do_vfp_sp_dyadic ();
15419 /* ARMv8.2 fp16 instruction. */
15421 do_scalar_fp16_v82_encode ();
15425 NEON_ENCODE (DOUBLE
, inst
);
15426 do_vfp_dp_rd_rn_rm ();
15428 do_vfp_cond_or_thumb ();
15432 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15436 neon_logbits (unsigned x
)
15438 return ffs (x
) - 4;
15441 #define LOW4(R) ((R) & 0xf)
15442 #define HI1(R) (((R) >> 4) & 1)
15445 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15450 first_error (BAD_EL_TYPE
);
15453 switch (inst
.operands
[0].imm
)
15456 first_error (_("invalid condition"));
15478 /* only accept eq and ne. */
15479 if (inst
.operands
[0].imm
> 1)
15481 first_error (_("invalid condition"));
15484 return inst
.operands
[0].imm
;
15486 if (inst
.operands
[0].imm
== 0x2)
15488 else if (inst
.operands
[0].imm
== 0x8)
15492 first_error (_("invalid condition"));
15496 switch (inst
.operands
[0].imm
)
15499 first_error (_("invalid condition"));
15515 /* Should be unreachable. */
15522 /* We are dealing with a vector predicated block. */
15523 if (inst
.operands
[0].present
)
15525 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15526 struct neon_type_el et
15527 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15530 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15532 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15534 if (et
.type
== NT_invtype
)
15537 if (et
.type
== NT_float
)
15539 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15541 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15542 inst
.instruction
|= (et
.size
== 16) << 28;
15543 inst
.instruction
|= 0x3 << 20;
15547 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15549 inst
.instruction
|= 1 << 28;
15550 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15553 if (inst
.operands
[2].isquad
)
15555 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15556 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15557 inst
.instruction
|= (fcond
& 0x2) >> 1;
15561 if (inst
.operands
[2].reg
== REG_SP
)
15562 as_tsktsk (MVE_BAD_SP
);
15563 inst
.instruction
|= 1 << 6;
15564 inst
.instruction
|= (fcond
& 0x2) << 4;
15565 inst
.instruction
|= inst
.operands
[2].reg
;
15567 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15568 inst
.instruction
|= (fcond
& 0x4) << 10;
15569 inst
.instruction
|= (fcond
& 0x1) << 7;
15572 set_pred_insn_type (VPT_INSN
);
15574 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15575 | ((inst
.instruction
& 0xe000) >> 13);
15576 now_pred
.warn_deprecated
= FALSE
;
15577 now_pred
.type
= VECTOR_PRED
;
15584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15585 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15586 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15587 if (!inst
.operands
[2].present
)
15588 first_error (_("MVE vector or ARM register expected"));
15589 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15591 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15592 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15593 && inst
.operands
[1].isquad
)
15595 inst
.instruction
= N_MNEM_vcmp
;
15599 if (inst
.cond
> COND_ALWAYS
)
15600 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15602 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15604 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15605 struct neon_type_el et
15606 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15609 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15610 && !inst
.operands
[2].iszr
, BAD_PC
);
15612 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15614 inst
.instruction
= 0xee010f00;
15615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15616 inst
.instruction
|= (fcond
& 0x4) << 10;
15617 inst
.instruction
|= (fcond
& 0x1) << 7;
15618 if (et
.type
== NT_float
)
15620 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15622 inst
.instruction
|= (et
.size
== 16) << 28;
15623 inst
.instruction
|= 0x3 << 20;
15627 inst
.instruction
|= 1 << 28;
15628 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15630 if (inst
.operands
[2].isquad
)
15632 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15633 inst
.instruction
|= (fcond
& 0x2) >> 1;
15634 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15638 if (inst
.operands
[2].reg
== REG_SP
)
15639 as_tsktsk (MVE_BAD_SP
);
15640 inst
.instruction
|= 1 << 6;
15641 inst
.instruction
|= (fcond
& 0x2) << 4;
15642 inst
.instruction
|= inst
.operands
[2].reg
;
15650 do_mve_vmaxa_vmina (void)
15652 if (inst
.cond
> COND_ALWAYS
)
15653 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15655 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15657 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15658 struct neon_type_el et
15659 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15661 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15662 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15663 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15664 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15665 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15670 do_mve_vfmas (void)
15672 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15673 struct neon_type_el et
15674 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15676 if (inst
.cond
> COND_ALWAYS
)
15677 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15679 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15681 if (inst
.operands
[2].reg
== REG_SP
)
15682 as_tsktsk (MVE_BAD_SP
);
15683 else if (inst
.operands
[2].reg
== REG_PC
)
15684 as_tsktsk (MVE_BAD_PC
);
15686 inst
.instruction
|= (et
.size
== 16) << 28;
15687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15689 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15690 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15691 inst
.instruction
|= inst
.operands
[2].reg
;
15696 do_mve_viddup (void)
15698 if (inst
.cond
> COND_ALWAYS
)
15699 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15701 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15703 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15704 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15705 _("immediate must be either 1, 2, 4 or 8"));
15707 enum neon_shape rs
;
15708 struct neon_type_el et
;
15710 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15712 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15713 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15718 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15719 if (inst
.operands
[2].reg
== REG_SP
)
15720 as_tsktsk (MVE_BAD_SP
);
15721 else if (inst
.operands
[2].reg
== REG_PC
)
15722 first_error (BAD_PC
);
15724 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15725 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15726 Rm
= inst
.operands
[2].reg
>> 1;
15728 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15729 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15730 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15731 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15732 inst
.instruction
|= (imm
> 2) << 7;
15733 inst
.instruction
|= Rm
<< 1;
15734 inst
.instruction
|= (imm
== 2 || imm
== 8);
15739 do_mve_vmlas (void)
15741 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15742 struct neon_type_el et
15743 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15745 if (inst
.operands
[2].reg
== REG_PC
)
15746 as_tsktsk (MVE_BAD_PC
);
15747 else if (inst
.operands
[2].reg
== REG_SP
)
15748 as_tsktsk (MVE_BAD_SP
);
15750 if (inst
.cond
> COND_ALWAYS
)
15751 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15753 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15755 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15757 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15758 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15759 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15761 inst
.instruction
|= inst
.operands
[2].reg
;
15766 do_mve_vshrn (void)
15769 switch (inst
.instruction
)
15771 case M_MNEM_vshrnt
:
15772 case M_MNEM_vshrnb
:
15773 case M_MNEM_vrshrnt
:
15774 case M_MNEM_vrshrnb
:
15775 types
= N_I16
| N_I32
;
15777 case M_MNEM_vqshrnt
:
15778 case M_MNEM_vqshrnb
:
15779 case M_MNEM_vqrshrnt
:
15780 case M_MNEM_vqrshrnb
:
15781 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15783 case M_MNEM_vqshrunt
:
15784 case M_MNEM_vqshrunb
:
15785 case M_MNEM_vqrshrunt
:
15786 case M_MNEM_vqrshrunb
:
15787 types
= N_S16
| N_S32
;
15793 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15795 if (inst
.cond
> COND_ALWAYS
)
15796 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15798 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15800 unsigned Qd
= inst
.operands
[0].reg
;
15801 unsigned Qm
= inst
.operands
[1].reg
;
15802 unsigned imm
= inst
.operands
[2].imm
;
15803 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15805 ? _("immediate operand expected in the range [1,8]")
15806 : _("immediate operand expected in the range [1,16]"));
15808 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15809 inst
.instruction
|= HI1 (Qd
) << 22;
15810 inst
.instruction
|= (et
.size
- imm
) << 16;
15811 inst
.instruction
|= LOW4 (Qd
) << 12;
15812 inst
.instruction
|= HI1 (Qm
) << 5;
15813 inst
.instruction
|= LOW4 (Qm
);
15818 do_mve_vqmovn (void)
15820 struct neon_type_el et
;
15821 if (inst
.instruction
== M_MNEM_vqmovnt
15822 || inst
.instruction
== M_MNEM_vqmovnb
)
15823 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15824 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15826 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15828 if (inst
.cond
> COND_ALWAYS
)
15829 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15831 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15833 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15834 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15835 inst
.instruction
|= (et
.size
== 32) << 18;
15836 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15837 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15838 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15843 do_mve_vpsel (void)
15845 neon_select_shape (NS_QQQ
, NS_NULL
);
15847 if (inst
.cond
> COND_ALWAYS
)
15848 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15850 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15852 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15853 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15854 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15855 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15856 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15857 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15862 do_mve_vpnot (void)
15864 if (inst
.cond
> COND_ALWAYS
)
15865 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15867 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15871 do_mve_vmaxnma_vminnma (void)
15873 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15874 struct neon_type_el et
15875 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15877 if (inst
.cond
> COND_ALWAYS
)
15878 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15880 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15882 inst
.instruction
|= (et
.size
== 16) << 28;
15883 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15884 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15885 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15886 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15891 do_mve_vcmul (void)
15893 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15894 struct neon_type_el et
15895 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15897 if (inst
.cond
> COND_ALWAYS
)
15898 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15900 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15902 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15903 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15904 _("immediate out of range"));
15906 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15907 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15908 as_tsktsk (BAD_MVE_SRCDEST
);
15910 inst
.instruction
|= (et
.size
== 32) << 28;
15911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15913 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15914 inst
.instruction
|= (rot
> 90) << 12;
15915 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15916 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15917 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15918 inst
.instruction
|= (rot
== 90 || rot
== 270);
15923 do_vfp_nsyn_cmp (void)
15925 enum neon_shape rs
;
15926 if (!inst
.operands
[0].isreg
)
15933 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15934 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15938 if (inst
.operands
[1].isreg
)
15940 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15941 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15943 if (rs
== NS_FF
|| rs
== NS_HH
)
15945 NEON_ENCODE (SINGLE
, inst
);
15946 do_vfp_sp_monadic ();
15950 NEON_ENCODE (DOUBLE
, inst
);
15951 do_vfp_dp_rd_rm ();
15956 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15957 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15959 switch (inst
.instruction
& 0x0fffffff)
15962 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15965 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15971 if (rs
== NS_FI
|| rs
== NS_HI
)
15973 NEON_ENCODE (SINGLE
, inst
);
15974 do_vfp_sp_compare_z ();
15978 NEON_ENCODE (DOUBLE
, inst
);
15982 do_vfp_cond_or_thumb ();
15984 /* ARMv8.2 fp16 instruction. */
15985 if (rs
== NS_HI
|| rs
== NS_HH
)
15986 do_scalar_fp16_v82_encode ();
15990 nsyn_insert_sp (void)
15992 inst
.operands
[1] = inst
.operands
[0];
15993 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15994 inst
.operands
[0].reg
= REG_SP
;
15995 inst
.operands
[0].isreg
= 1;
15996 inst
.operands
[0].writeback
= 1;
15997 inst
.operands
[0].present
= 1;
16001 do_vfp_nsyn_push (void)
16005 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16006 _("register list must contain at least 1 and at most 16 "
16009 if (inst
.operands
[1].issingle
)
16010 do_vfp_nsyn_opcode ("fstmdbs");
16012 do_vfp_nsyn_opcode ("fstmdbd");
16016 do_vfp_nsyn_pop (void)
16020 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16021 _("register list must contain at least 1 and at most 16 "
16024 if (inst
.operands
[1].issingle
)
16025 do_vfp_nsyn_opcode ("fldmias");
16027 do_vfp_nsyn_opcode ("fldmiad");
16030 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16031 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16034 neon_dp_fixup (struct arm_it
* insn
)
16036 unsigned int i
= insn
->instruction
;
16041 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16052 insn
->instruction
= i
;
16056 mve_encode_qqr (int size
, int U
, int fp
)
16058 if (inst
.operands
[2].reg
== REG_SP
)
16059 as_tsktsk (MVE_BAD_SP
);
16060 else if (inst
.operands
[2].reg
== REG_PC
)
16061 as_tsktsk (MVE_BAD_PC
);
16066 if (((unsigned)inst
.instruction
) == 0xd00)
16067 inst
.instruction
= 0xee300f40;
16069 else if (((unsigned)inst
.instruction
) == 0x200d00)
16070 inst
.instruction
= 0xee301f40;
16072 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16073 inst
.instruction
= 0xee310e60;
16075 /* Setting size which is 1 for F16 and 0 for F32. */
16076 inst
.instruction
|= (size
== 16) << 28;
16081 if (((unsigned)inst
.instruction
) == 0x800)
16082 inst
.instruction
= 0xee010f40;
16084 else if (((unsigned)inst
.instruction
) == 0x1000800)
16085 inst
.instruction
= 0xee011f40;
16087 else if (((unsigned)inst
.instruction
) == 0)
16088 inst
.instruction
= 0xee000f40;
16090 else if (((unsigned)inst
.instruction
) == 0x200)
16091 inst
.instruction
= 0xee001f40;
16093 else if (((unsigned)inst
.instruction
) == 0x900)
16094 inst
.instruction
= 0xee010e40;
16096 else if (((unsigned)inst
.instruction
) == 0x910)
16097 inst
.instruction
= 0xee011e60;
16099 else if (((unsigned)inst
.instruction
) == 0x10)
16100 inst
.instruction
= 0xee000f60;
16102 else if (((unsigned)inst
.instruction
) == 0x210)
16103 inst
.instruction
= 0xee001f60;
16105 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16106 inst
.instruction
= 0xee000e40;
16108 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16109 inst
.instruction
= 0xee010e60;
16111 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16112 inst
.instruction
= 0xfe010e60;
16115 inst
.instruction
|= U
<< 28;
16117 /* Setting bits for size. */
16118 inst
.instruction
|= neon_logbits (size
) << 20;
16120 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16121 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16122 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16123 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16124 inst
.instruction
|= inst
.operands
[2].reg
;
16129 mve_encode_rqq (unsigned bit28
, unsigned size
)
16131 inst
.instruction
|= bit28
<< 28;
16132 inst
.instruction
|= neon_logbits (size
) << 20;
16133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16136 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16137 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16142 mve_encode_qqq (int ubit
, int size
)
16145 inst
.instruction
|= (ubit
!= 0) << 28;
16146 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16147 inst
.instruction
|= neon_logbits (size
) << 20;
16148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16149 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16150 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16151 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16152 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16158 mve_encode_rq (unsigned bit28
, unsigned size
)
16160 inst
.instruction
|= bit28
<< 28;
16161 inst
.instruction
|= neon_logbits (size
) << 18;
16162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16163 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16168 mve_encode_rrqq (unsigned U
, unsigned size
)
16170 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16172 inst
.instruction
|= U
<< 28;
16173 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16174 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16175 inst
.instruction
|= (size
== 32) << 16;
16176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16177 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16178 inst
.instruction
|= inst
.operands
[3].reg
;
16182 /* Encode insns with bit pattern:
16184 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16185 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16187 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16188 different meaning for some instruction. */
16191 neon_three_same (int isquad
, int ubit
, int size
)
16193 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16194 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16195 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16196 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16197 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16198 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16199 inst
.instruction
|= (isquad
!= 0) << 6;
16200 inst
.instruction
|= (ubit
!= 0) << 24;
16202 inst
.instruction
|= neon_logbits (size
) << 20;
16204 neon_dp_fixup (&inst
);
16207 /* Encode instructions of the form:
16209 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16210 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16212 Don't write size if SIZE == -1. */
16215 neon_two_same (int qbit
, int ubit
, int size
)
16217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16219 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16220 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16221 inst
.instruction
|= (qbit
!= 0) << 6;
16222 inst
.instruction
|= (ubit
!= 0) << 24;
16225 inst
.instruction
|= neon_logbits (size
) << 18;
16227 neon_dp_fixup (&inst
);
16230 enum vfp_or_neon_is_neon_bits
16233 NEON_CHECK_ARCH
= 2,
16234 NEON_CHECK_ARCH8
= 4
16237 /* Call this function if an instruction which may have belonged to the VFP or
16238 Neon instruction sets, but turned out to be a Neon instruction (due to the
16239 operand types involved, etc.). We have to check and/or fix-up a couple of
16242 - Make sure the user hasn't attempted to make a Neon instruction
16244 - Alter the value in the condition code field if necessary.
16245 - Make sure that the arch supports Neon instructions.
16247 Which of these operations take place depends on bits from enum
16248 vfp_or_neon_is_neon_bits.
16250 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16251 current instruction's condition is COND_ALWAYS, the condition field is
16252 changed to inst.uncond_value. This is necessary because instructions shared
16253 between VFP and Neon may be conditional for the VFP variants only, and the
16254 unconditional Neon version must have, e.g., 0xF in the condition field. */
16257 vfp_or_neon_is_neon (unsigned check
)
16259 /* Conditions are always legal in Thumb mode (IT blocks). */
16260 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16262 if (inst
.cond
!= COND_ALWAYS
)
16264 first_error (_(BAD_COND
));
16267 if (inst
.uncond_value
!= -1)
16268 inst
.instruction
|= inst
.uncond_value
<< 28;
16272 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16273 || ((check
& NEON_CHECK_ARCH8
)
16274 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16276 first_error (_(BAD_FPU
));
16284 check_simd_pred_availability (int fp
, unsigned check
)
16286 if (inst
.cond
> COND_ALWAYS
)
16288 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16290 inst
.error
= BAD_FPU
;
16293 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16295 else if (inst
.cond
< COND_ALWAYS
)
16297 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16298 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16299 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16304 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16305 && vfp_or_neon_is_neon (check
) == FAIL
)
16308 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16309 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16314 /* Neon instruction encoders, in approximate order of appearance. */
16317 do_neon_dyadic_i_su (void)
16319 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16322 enum neon_shape rs
;
16323 struct neon_type_el et
;
16324 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16325 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16327 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16329 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16333 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16335 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16339 do_neon_dyadic_i64_su (void)
16341 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16343 enum neon_shape rs
;
16344 struct neon_type_el et
;
16345 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16347 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16348 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16352 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16353 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16356 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16358 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16362 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16365 unsigned size
= et
.size
>> 3;
16366 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16367 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16368 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16369 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16370 inst
.instruction
|= (isquad
!= 0) << 6;
16371 inst
.instruction
|= immbits
<< 16;
16372 inst
.instruction
|= (size
>> 3) << 7;
16373 inst
.instruction
|= (size
& 0x7) << 19;
16375 inst
.instruction
|= (uval
!= 0) << 24;
16377 neon_dp_fixup (&inst
);
16381 do_neon_shl_imm (void)
16383 if (!inst
.operands
[2].isreg
)
16385 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16386 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16387 int imm
= inst
.operands
[2].imm
;
16389 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16390 _("immediate out of range for shift"));
16391 NEON_ENCODE (IMMED
, inst
);
16392 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16396 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16397 struct neon_type_el et
= neon_check_type (3, rs
,
16398 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16401 /* VSHL/VQSHL 3-register variants have syntax such as:
16403 whereas other 3-register operations encoded by neon_three_same have
16406 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
16408 tmp
= inst
.operands
[2].reg
;
16409 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16410 inst
.operands
[1].reg
= tmp
;
16411 NEON_ENCODE (INTEGER
, inst
);
16412 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16417 do_neon_qshl_imm (void)
16419 if (!inst
.operands
[2].isreg
)
16421 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16422 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16423 int imm
= inst
.operands
[2].imm
;
16425 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16426 _("immediate out of range for shift"));
16427 NEON_ENCODE (IMMED
, inst
);
16428 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16432 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16433 struct neon_type_el et
= neon_check_type (3, rs
,
16434 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16437 /* See note in do_neon_shl_imm. */
16438 tmp
= inst
.operands
[2].reg
;
16439 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16440 inst
.operands
[1].reg
= tmp
;
16441 NEON_ENCODE (INTEGER
, inst
);
16442 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16447 do_neon_rshl (void)
16449 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16452 enum neon_shape rs
;
16453 struct neon_type_el et
;
16454 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16456 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16457 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16461 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16462 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16469 if (inst
.operands
[2].reg
== REG_PC
)
16470 as_tsktsk (MVE_BAD_PC
);
16471 else if (inst
.operands
[2].reg
== REG_SP
)
16472 as_tsktsk (MVE_BAD_SP
);
16474 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16475 _("invalid instruction shape"));
16477 if (inst
.instruction
== 0x0000510)
16478 /* We are dealing with vqrshl. */
16479 inst
.instruction
= 0xee331ee0;
16481 /* We are dealing with vrshl. */
16482 inst
.instruction
= 0xee331e60;
16484 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16486 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16487 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16488 inst
.instruction
|= inst
.operands
[2].reg
;
16493 tmp
= inst
.operands
[2].reg
;
16494 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16495 inst
.operands
[1].reg
= tmp
;
16496 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16501 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16503 /* Handle .I8 pseudo-instructions. */
16506 /* Unfortunately, this will make everything apart from zero out-of-range.
16507 FIXME is this the intended semantics? There doesn't seem much point in
16508 accepting .I8 if so. */
16509 immediate
|= immediate
<< 8;
16515 if (immediate
== (immediate
& 0x000000ff))
16517 *immbits
= immediate
;
16520 else if (immediate
== (immediate
& 0x0000ff00))
16522 *immbits
= immediate
>> 8;
16525 else if (immediate
== (immediate
& 0x00ff0000))
16527 *immbits
= immediate
>> 16;
16530 else if (immediate
== (immediate
& 0xff000000))
16532 *immbits
= immediate
>> 24;
16535 if ((immediate
& 0xffff) != (immediate
>> 16))
16536 goto bad_immediate
;
16537 immediate
&= 0xffff;
16540 if (immediate
== (immediate
& 0x000000ff))
16542 *immbits
= immediate
;
16545 else if (immediate
== (immediate
& 0x0000ff00))
16547 *immbits
= immediate
>> 8;
16552 first_error (_("immediate value out of range"));
16557 do_neon_logic (void)
16559 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16561 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16563 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16566 else if (rs
!= NS_QQQ
16567 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16568 first_error (BAD_FPU
);
16570 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16571 /* U bit and size field were set as part of the bitmask. */
16572 NEON_ENCODE (INTEGER
, inst
);
16573 neon_three_same (neon_quad (rs
), 0, -1);
16577 const int three_ops_form
= (inst
.operands
[2].present
16578 && !inst
.operands
[2].isreg
);
16579 const int immoperand
= (three_ops_form
? 2 : 1);
16580 enum neon_shape rs
= (three_ops_form
16581 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16582 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16583 /* Because neon_select_shape makes the second operand a copy of the first
16584 if the second operand is not present. */
16586 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16589 else if (rs
!= NS_QQI
16590 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16591 first_error (BAD_FPU
);
16593 struct neon_type_el et
;
16594 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16595 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16597 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16600 if (et
.type
== NT_invtype
)
16602 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16607 if (three_ops_form
)
16608 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16609 _("first and second operands shall be the same register"));
16611 NEON_ENCODE (IMMED
, inst
);
16613 immbits
= inst
.operands
[immoperand
].imm
;
16616 /* .i64 is a pseudo-op, so the immediate must be a repeating
16618 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16619 inst
.operands
[immoperand
].reg
: 0))
16621 /* Set immbits to an invalid constant. */
16622 immbits
= 0xdeadbeef;
16629 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16633 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16637 /* Pseudo-instruction for VBIC. */
16638 neon_invert_size (&immbits
, 0, et
.size
);
16639 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16643 /* Pseudo-instruction for VORR. */
16644 neon_invert_size (&immbits
, 0, et
.size
);
16645 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16655 inst
.instruction
|= neon_quad (rs
) << 6;
16656 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16657 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16658 inst
.instruction
|= cmode
<< 8;
16659 neon_write_immbits (immbits
);
16661 neon_dp_fixup (&inst
);
16666 do_neon_bitfield (void)
16668 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16669 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16670 neon_three_same (neon_quad (rs
), 0, -1);
16674 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16677 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16678 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16680 if (et
.type
== NT_float
)
16682 NEON_ENCODE (FLOAT
, inst
);
16684 mve_encode_qqr (et
.size
, 0, 1);
16686 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16690 NEON_ENCODE (INTEGER
, inst
);
16692 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16694 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16700 do_neon_dyadic_if_su_d (void)
16702 /* This version only allow D registers, but that constraint is enforced during
16703 operand parsing so we don't need to do anything extra here. */
16704 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16708 do_neon_dyadic_if_i_d (void)
16710 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16711 affected if we specify unsigned args. */
16712 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16716 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16718 constraint (size
< 32, BAD_ADDR_MODE
);
16719 constraint (size
!= elsize
, BAD_EL_TYPE
);
16720 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16721 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16722 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16723 _("destination register and offset register may not be the"
16726 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16733 constraint ((imm
% (size
/ 8) != 0)
16734 || imm
> (0x7f << neon_logbits (size
)),
16735 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16736 " range of +/-[0,508]")
16737 : _("immediate must be a multiple of 8 in the"
16738 " range of +/-[0,1016]"));
16739 inst
.instruction
|= 0x11 << 24;
16740 inst
.instruction
|= add
<< 23;
16741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16742 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16743 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16744 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16745 inst
.instruction
|= 1 << 12;
16746 inst
.instruction
|= (size
== 64) << 8;
16747 inst
.instruction
&= 0xffffff00;
16748 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16749 inst
.instruction
|= imm
>> neon_logbits (size
);
16753 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16755 unsigned os
= inst
.operands
[1].imm
>> 5;
16756 constraint (os
!= 0 && size
== 8,
16757 _("can not shift offsets when accessing less than half-word"));
16758 constraint (os
&& os
!= neon_logbits (size
),
16759 _("shift immediate must be 1, 2 or 3 for half-word, word"
16760 " or double-word accesses respectively"));
16761 if (inst
.operands
[1].reg
== REG_PC
)
16762 as_tsktsk (MVE_BAD_PC
);
16767 constraint (elsize
>= 64, BAD_EL_TYPE
);
16770 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16774 constraint (elsize
!= size
, BAD_EL_TYPE
);
16779 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16783 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16784 _("destination register and offset register may not be"
16786 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16788 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16789 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16790 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16794 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16797 inst
.instruction
|= 1 << 23;
16798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16799 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16801 inst
.instruction
|= neon_logbits (elsize
) << 7;
16802 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16803 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16804 inst
.instruction
|= !!os
;
16808 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16810 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16812 constraint (size
>= 64, BAD_ADDR_MODE
);
16816 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16819 constraint (elsize
!= size
, BAD_EL_TYPE
);
16826 constraint (elsize
!= size
&& type
!= NT_unsigned
16827 && type
!= NT_signed
, BAD_EL_TYPE
);
16831 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16834 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16842 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16847 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16850 constraint (1, _("immediate must be a multiple of 2 in the"
16851 " range of +/-[0,254]"));
16854 constraint (1, _("immediate must be a multiple of 4 in the"
16855 " range of +/-[0,508]"));
16860 if (size
!= elsize
)
16862 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16863 constraint (inst
.operands
[0].reg
> 14,
16864 _("MVE vector register in the range [Q0..Q7] expected"));
16865 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16866 inst
.instruction
|= (size
== 16) << 19;
16867 inst
.instruction
|= neon_logbits (elsize
) << 7;
16871 if (inst
.operands
[1].reg
== REG_PC
)
16872 as_tsktsk (MVE_BAD_PC
);
16873 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16874 as_tsktsk (MVE_BAD_SP
);
16875 inst
.instruction
|= 1 << 12;
16876 inst
.instruction
|= neon_logbits (size
) << 7;
16878 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16879 inst
.instruction
|= add
<< 23;
16880 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16881 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16883 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16884 inst
.instruction
&= 0xffffff80;
16885 inst
.instruction
|= imm
>> neon_logbits (size
);
16890 do_mve_vstr_vldr (void)
16895 if (inst
.cond
> COND_ALWAYS
)
16896 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16898 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16900 switch (inst
.instruction
)
16907 /* fall through. */
16913 /* fall through. */
16919 /* fall through. */
16925 /* fall through. */
16930 unsigned elsize
= inst
.vectype
.el
[0].size
;
16932 if (inst
.operands
[1].isquad
)
16934 /* We are dealing with [Q, imm]{!} cases. */
16935 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16939 if (inst
.operands
[1].immisreg
== 2)
16941 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16942 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16944 else if (!inst
.operands
[1].immisreg
)
16946 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16947 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16950 constraint (1, BAD_ADDR_MODE
);
16957 do_mve_vst_vld (void)
16959 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16962 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16963 || inst
.relocs
[0].exp
.X_add_number
!= 0
16964 || inst
.operands
[1].immisreg
!= 0,
16966 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16967 if (inst
.operands
[1].reg
== REG_PC
)
16968 as_tsktsk (MVE_BAD_PC
);
16969 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16970 as_tsktsk (MVE_BAD_SP
);
16973 /* These instructions are one of the "exceptions" mentioned in
16974 handle_pred_state. They are MVE instructions that are not VPT compatible
16975 and do not accept a VPT code, thus appending such a code is a syntax
16977 if (inst
.cond
> COND_ALWAYS
)
16978 first_error (BAD_SYNTAX
);
16979 /* If we append a scalar condition code we can set this to
16980 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16981 else if (inst
.cond
< COND_ALWAYS
)
16982 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16984 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16986 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16987 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16988 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16989 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16990 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16995 do_mve_vaddlv (void)
16997 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
16998 struct neon_type_el et
16999 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17001 if (et
.type
== NT_invtype
)
17002 first_error (BAD_EL_TYPE
);
17004 if (inst
.cond
> COND_ALWAYS
)
17005 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17007 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17009 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17011 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17012 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17014 inst
.instruction
|= inst
.operands
[2].reg
;
17019 do_neon_dyadic_if_su (void)
17021 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17022 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17025 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17026 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17027 && et
.type
== NT_float
17028 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17030 if (check_simd_pred_availability (et
.type
== NT_float
,
17031 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17034 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17038 do_neon_addsub_if_i (void)
17040 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17041 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17044 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17045 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17046 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17048 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17049 /* If we are parsing Q registers and the element types match MVE, which NEON
17050 also supports, then we must check whether this is an instruction that can
17051 be used by both MVE/NEON. This distinction can be made based on whether
17052 they are predicated or not. */
17053 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17055 if (check_simd_pred_availability (et
.type
== NT_float
,
17056 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17061 /* If they are either in a D register or are using an unsupported. */
17063 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17067 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17068 affected if we specify unsigned args. */
17069 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17072 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17074 V<op> A,B (A is operand 0, B is operand 2)
17079 so handle that case specially. */
17082 neon_exchange_operands (void)
17084 if (inst
.operands
[1].present
)
17086 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17088 /* Swap operands[1] and operands[2]. */
17089 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17090 inst
.operands
[1] = inst
.operands
[2];
17091 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17096 inst
.operands
[1] = inst
.operands
[2];
17097 inst
.operands
[2] = inst
.operands
[0];
17102 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17104 if (inst
.operands
[2].isreg
)
17107 neon_exchange_operands ();
17108 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17112 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17113 struct neon_type_el et
= neon_check_type (2, rs
,
17114 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17116 NEON_ENCODE (IMMED
, inst
);
17117 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17118 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17119 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17120 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17121 inst
.instruction
|= neon_quad (rs
) << 6;
17122 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17123 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17125 neon_dp_fixup (&inst
);
17132 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17136 do_neon_cmp_inv (void)
17138 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17144 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17147 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17148 scalars, which are encoded in 5 bits, M : Rm.
17149 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17150 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17153 Dot Product instructions are similar to multiply instructions except elsize
17154 should always be 32.
17156 This function translates SCALAR, which is GAS's internal encoding of indexed
17157 scalar register, to raw encoding. There is also register and index range
17158 check based on ELSIZE. */
17161 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17163 unsigned regno
= NEON_SCALAR_REG (scalar
);
17164 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17169 if (regno
> 7 || elno
> 3)
17171 return regno
| (elno
<< 3);
17174 if (regno
> 15 || elno
> 1)
17176 return regno
| (elno
<< 4);
17180 first_error (_("scalar out of range for multiply instruction"));
17186 /* Encode multiply / multiply-accumulate scalar instructions. */
17189 neon_mul_mac (struct neon_type_el et
, int ubit
)
17193 /* Give a more helpful error message if we have an invalid type. */
17194 if (et
.type
== NT_invtype
)
17197 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17198 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17199 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17200 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17201 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17202 inst
.instruction
|= LOW4 (scalar
);
17203 inst
.instruction
|= HI1 (scalar
) << 5;
17204 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17205 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17206 inst
.instruction
|= (ubit
!= 0) << 24;
17208 neon_dp_fixup (&inst
);
17212 do_neon_mac_maybe_scalar (void)
17214 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17217 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17220 if (inst
.operands
[2].isscalar
)
17222 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17223 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17224 struct neon_type_el et
= neon_check_type (3, rs
,
17225 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17226 NEON_ENCODE (SCALAR
, inst
);
17227 neon_mul_mac (et
, neon_quad (rs
));
17229 else if (!inst
.operands
[2].isvec
)
17231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17233 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17234 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17236 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17240 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17241 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17242 affected if we specify unsigned args. */
17243 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17248 do_neon_fmac (void)
17250 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17251 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17254 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17257 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17259 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17260 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17265 if (inst
.operands
[2].reg
== REG_SP
)
17266 as_tsktsk (MVE_BAD_SP
);
17267 else if (inst
.operands
[2].reg
== REG_PC
)
17268 as_tsktsk (MVE_BAD_PC
);
17270 inst
.instruction
= 0xee310e40;
17271 inst
.instruction
|= (et
.size
== 16) << 28;
17272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17274 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17275 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17276 inst
.instruction
|= inst
.operands
[2].reg
;
17283 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17286 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17292 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17293 struct neon_type_el et
= neon_check_type (3, rs
,
17294 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17295 neon_three_same (neon_quad (rs
), 0, et
.size
);
17298 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17299 same types as the MAC equivalents. The polynomial type for this instruction
17300 is encoded the same as the integer type. */
17305 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17308 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17311 if (inst
.operands
[2].isscalar
)
17313 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17314 do_neon_mac_maybe_scalar ();
17318 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17320 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17321 struct neon_type_el et
17322 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17323 if (et
.type
== NT_float
)
17324 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17327 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17331 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17332 neon_dyadic_misc (NT_poly
,
17333 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17339 do_neon_qdmulh (void)
17341 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17344 if (inst
.operands
[2].isscalar
)
17346 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17347 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17348 struct neon_type_el et
= neon_check_type (3, rs
,
17349 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17350 NEON_ENCODE (SCALAR
, inst
);
17351 neon_mul_mac (et
, neon_quad (rs
));
17355 enum neon_shape rs
;
17356 struct neon_type_el et
;
17357 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17359 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17360 et
= neon_check_type (3, rs
,
17361 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17365 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17366 et
= neon_check_type (3, rs
,
17367 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17370 NEON_ENCODE (INTEGER
, inst
);
17372 mve_encode_qqr (et
.size
, 0, 0);
17374 /* The U bit (rounding) comes from bit mask. */
17375 neon_three_same (neon_quad (rs
), 0, et
.size
);
17380 do_mve_vaddv (void)
17382 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17383 struct neon_type_el et
17384 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17386 if (et
.type
== NT_invtype
)
17387 first_error (BAD_EL_TYPE
);
17389 if (inst
.cond
> COND_ALWAYS
)
17390 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17392 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17394 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17396 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17400 do_mve_vhcadd (void)
17402 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17403 struct neon_type_el et
17404 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17406 if (inst
.cond
> COND_ALWAYS
)
17407 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17409 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17411 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17412 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17414 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17415 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17416 "operand makes instruction UNPREDICTABLE"));
17418 mve_encode_qqq (0, et
.size
);
17419 inst
.instruction
|= (rot
== 270) << 12;
17424 do_mve_vqdmull (void)
17426 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17427 struct neon_type_el et
17428 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17431 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17432 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17433 as_tsktsk (BAD_MVE_SRCDEST
);
17435 if (inst
.cond
> COND_ALWAYS
)
17436 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17438 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17442 mve_encode_qqq (et
.size
== 32, 64);
17443 inst
.instruction
|= 1;
17447 mve_encode_qqr (64, et
.size
== 32, 0);
17448 inst
.instruction
|= 0x3 << 5;
17455 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17456 struct neon_type_el et
17457 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17459 if (et
.type
== NT_invtype
)
17460 first_error (BAD_EL_TYPE
);
17462 if (inst
.cond
> COND_ALWAYS
)
17463 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17465 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17467 mve_encode_qqq (0, 64);
17471 do_mve_vbrsr (void)
17473 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17474 struct neon_type_el et
17475 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17477 if (inst
.cond
> COND_ALWAYS
)
17478 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17480 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17482 mve_encode_qqr (et
.size
, 0, 0);
17488 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17490 if (inst
.cond
> COND_ALWAYS
)
17491 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17493 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17495 mve_encode_qqq (1, 64);
17499 do_mve_vmulh (void)
17501 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17502 struct neon_type_el et
17503 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17505 if (inst
.cond
> COND_ALWAYS
)
17506 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17508 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17510 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17514 do_mve_vqdmlah (void)
17516 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17517 struct neon_type_el et
17518 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17520 if (inst
.cond
> COND_ALWAYS
)
17521 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17523 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17525 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17529 do_mve_vqdmladh (void)
17531 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17532 struct neon_type_el et
17533 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17535 if (inst
.cond
> COND_ALWAYS
)
17536 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17538 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17541 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17542 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17543 as_tsktsk (BAD_MVE_SRCDEST
);
17545 mve_encode_qqq (0, et
.size
);
17550 do_mve_vmull (void)
17553 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17554 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17555 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17556 && inst
.cond
== COND_ALWAYS
17557 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17562 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17563 N_SUF_32
| N_F64
| N_P8
17564 | N_P16
| N_I_MVE
| N_KEY
);
17565 if (((et
.type
== NT_poly
) && et
.size
== 8
17566 && ARM_CPU_IS_ANY (cpu_variant
))
17567 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17574 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17575 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17576 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17578 /* We are dealing with MVE's vmullt. */
17580 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17581 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17582 as_tsktsk (BAD_MVE_SRCDEST
);
17584 if (inst
.cond
> COND_ALWAYS
)
17585 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17587 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17589 if (et
.type
== NT_poly
)
17590 mve_encode_qqq (neon_logbits (et
.size
), 64);
17592 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17597 inst
.instruction
= N_MNEM_vmul
;
17600 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17605 do_mve_vabav (void)
17607 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17612 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17615 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17616 | N_S16
| N_S32
| N_U8
| N_U16
17619 if (inst
.cond
> COND_ALWAYS
)
17620 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17622 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17624 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17628 do_mve_vmladav (void)
17630 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17631 struct neon_type_el et
= neon_check_type (3, rs
,
17632 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17634 if (et
.type
== NT_unsigned
17635 && (inst
.instruction
== M_MNEM_vmladavx
17636 || inst
.instruction
== M_MNEM_vmladavax
17637 || inst
.instruction
== M_MNEM_vmlsdav
17638 || inst
.instruction
== M_MNEM_vmlsdava
17639 || inst
.instruction
== M_MNEM_vmlsdavx
17640 || inst
.instruction
== M_MNEM_vmlsdavax
))
17641 first_error (BAD_SIMD_TYPE
);
17643 constraint (inst
.operands
[2].reg
> 14,
17644 _("MVE vector register in the range [Q0..Q7] expected"));
17646 if (inst
.cond
> COND_ALWAYS
)
17647 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17649 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17651 if (inst
.instruction
== M_MNEM_vmlsdav
17652 || inst
.instruction
== M_MNEM_vmlsdava
17653 || inst
.instruction
== M_MNEM_vmlsdavx
17654 || inst
.instruction
== M_MNEM_vmlsdavax
)
17655 inst
.instruction
|= (et
.size
== 8) << 28;
17657 inst
.instruction
|= (et
.size
== 8) << 8;
17659 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17660 inst
.instruction
|= (et
.size
== 32) << 16;
17664 do_mve_vmlaldav (void)
17666 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17667 struct neon_type_el et
17668 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17669 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17671 if (et
.type
== NT_unsigned
17672 && (inst
.instruction
== M_MNEM_vmlsldav
17673 || inst
.instruction
== M_MNEM_vmlsldava
17674 || inst
.instruction
== M_MNEM_vmlsldavx
17675 || inst
.instruction
== M_MNEM_vmlsldavax
))
17676 first_error (BAD_SIMD_TYPE
);
17678 if (inst
.cond
> COND_ALWAYS
)
17679 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17681 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17683 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17687 do_mve_vrmlaldavh (void)
17689 struct neon_type_el et
;
17690 if (inst
.instruction
== M_MNEM_vrmlsldavh
17691 || inst
.instruction
== M_MNEM_vrmlsldavha
17692 || inst
.instruction
== M_MNEM_vrmlsldavhx
17693 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17695 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17696 if (inst
.operands
[1].reg
== REG_SP
)
17697 as_tsktsk (MVE_BAD_SP
);
17701 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17702 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17703 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17705 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17706 N_U32
| N_S32
| N_KEY
);
17707 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17708 with vmax/min instructions, making the use of SP in assembly really
17709 nonsensical, so instead of issuing a warning like we do for other uses
17710 of SP for the odd register operand we error out. */
17711 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17714 /* Make sure we still check the second operand is an odd one and that PC is
17715 disallowed. This because we are parsing for any GPR operand, to be able
17716 to distinguish between giving a warning or an error for SP as described
17718 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17719 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17721 if (inst
.cond
> COND_ALWAYS
)
17722 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17724 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17726 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17731 do_mve_vmaxnmv (void)
17733 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17734 struct neon_type_el et
17735 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17737 if (inst
.cond
> COND_ALWAYS
)
17738 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17740 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17742 if (inst
.operands
[0].reg
== REG_SP
)
17743 as_tsktsk (MVE_BAD_SP
);
17744 else if (inst
.operands
[0].reg
== REG_PC
)
17745 as_tsktsk (MVE_BAD_PC
);
17747 mve_encode_rq (et
.size
== 16, 64);
17751 do_mve_vmaxv (void)
17753 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17754 struct neon_type_el et
;
17756 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17757 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17759 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17761 if (inst
.cond
> COND_ALWAYS
)
17762 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17764 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17766 if (inst
.operands
[0].reg
== REG_SP
)
17767 as_tsktsk (MVE_BAD_SP
);
17768 else if (inst
.operands
[0].reg
== REG_PC
)
17769 as_tsktsk (MVE_BAD_PC
);
17771 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17776 do_neon_qrdmlah (void)
17778 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17780 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17782 /* Check we're on the correct architecture. */
17783 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17785 = _("instruction form not available on this architecture.");
17786 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17788 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17789 record_feature_use (&fpu_neon_ext_v8_1
);
17791 if (inst
.operands
[2].isscalar
)
17793 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17794 struct neon_type_el et
= neon_check_type (3, rs
,
17795 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17796 NEON_ENCODE (SCALAR
, inst
);
17797 neon_mul_mac (et
, neon_quad (rs
));
17801 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17802 struct neon_type_el et
= neon_check_type (3, rs
,
17803 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17804 NEON_ENCODE (INTEGER
, inst
);
17805 /* The U bit (rounding) comes from bit mask. */
17806 neon_three_same (neon_quad (rs
), 0, et
.size
);
17811 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17812 struct neon_type_el et
17813 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17815 NEON_ENCODE (INTEGER
, inst
);
17816 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17821 do_neon_fcmp_absolute (void)
17823 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17824 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17825 N_F_16_32
| N_KEY
);
17826 /* Size field comes from bit mask. */
17827 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17831 do_neon_fcmp_absolute_inv (void)
17833 neon_exchange_operands ();
17834 do_neon_fcmp_absolute ();
17838 do_neon_step (void)
17840 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17841 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17842 N_F_16_32
| N_KEY
);
17843 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17847 do_neon_abs_neg (void)
17849 enum neon_shape rs
;
17850 struct neon_type_el et
;
17852 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
17855 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17856 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
17858 if (check_simd_pred_availability (et
.type
== NT_float
,
17859 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17862 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17863 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17864 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17865 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17866 inst
.instruction
|= neon_quad (rs
) << 6;
17867 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17868 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17870 neon_dp_fixup (&inst
);
17876 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17879 enum neon_shape rs
;
17880 struct neon_type_el et
;
17881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17883 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17884 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17888 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17889 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17893 int imm
= inst
.operands
[2].imm
;
17894 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17895 _("immediate out of range for insert"));
17896 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17902 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17905 enum neon_shape rs
;
17906 struct neon_type_el et
;
17907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17909 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17910 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17914 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17915 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17918 int imm
= inst
.operands
[2].imm
;
17919 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17920 _("immediate out of range for insert"));
17921 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
17925 do_neon_qshlu_imm (void)
17927 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17928 struct neon_type_el et
= neon_check_type (2, rs
,
17929 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
17930 int imm
= inst
.operands
[2].imm
;
17931 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17932 _("immediate out of range for shift"));
17933 /* Only encodes the 'U present' variant of the instruction.
17934 In this case, signed types have OP (bit 8) set to 0.
17935 Unsigned types have OP set to 1. */
17936 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
17937 /* The rest of the bits are the same as other immediate shifts. */
17938 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17942 do_neon_qmovn (void)
17944 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17945 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17946 /* Saturating move where operands can be signed or unsigned, and the
17947 destination has the same signedness. */
17948 NEON_ENCODE (INTEGER
, inst
);
17949 if (et
.type
== NT_unsigned
)
17950 inst
.instruction
|= 0xc0;
17952 inst
.instruction
|= 0x80;
17953 neon_two_same (0, 1, et
.size
/ 2);
17957 do_neon_qmovun (void)
17959 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17960 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17961 /* Saturating move with unsigned results. Operands must be signed. */
17962 NEON_ENCODE (INTEGER
, inst
);
17963 neon_two_same (0, 1, et
.size
/ 2);
17967 do_neon_rshift_sat_narrow (void)
17969 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17970 or unsigned. If operands are unsigned, results must also be unsigned. */
17971 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17972 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17973 int imm
= inst
.operands
[2].imm
;
17974 /* This gets the bounds check, size encoding and immediate bits calculation
17978 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17979 VQMOVN.I<size> <Dd>, <Qm>. */
17982 inst
.operands
[2].present
= 0;
17983 inst
.instruction
= N_MNEM_vqmovn
;
17988 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17989 _("immediate out of range"));
17990 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17994 do_neon_rshift_sat_narrow_u (void)
17996 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17997 or unsigned. If operands are unsigned, results must also be unsigned. */
17998 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17999 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18000 int imm
= inst
.operands
[2].imm
;
18001 /* This gets the bounds check, size encoding and immediate bits calculation
18005 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18006 VQMOVUN.I<size> <Dd>, <Qm>. */
18009 inst
.operands
[2].present
= 0;
18010 inst
.instruction
= N_MNEM_vqmovun
;
18015 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18016 _("immediate out of range"));
18017 /* FIXME: The manual is kind of unclear about what value U should have in
18018 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18020 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18024 do_neon_movn (void)
18026 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18027 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18028 NEON_ENCODE (INTEGER
, inst
);
18029 neon_two_same (0, 1, et
.size
/ 2);
18033 do_neon_rshift_narrow (void)
18035 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18036 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18037 int imm
= inst
.operands
[2].imm
;
18038 /* This gets the bounds check, size encoding and immediate bits calculation
18042 /* If immediate is zero then we are a pseudo-instruction for
18043 VMOVN.I<size> <Dd>, <Qm> */
18046 inst
.operands
[2].present
= 0;
18047 inst
.instruction
= N_MNEM_vmovn
;
18052 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18053 _("immediate out of range for narrowing operation"));
18054 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18058 do_neon_shll (void)
18060 /* FIXME: Type checking when lengthening. */
18061 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18062 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18063 unsigned imm
= inst
.operands
[2].imm
;
18065 if (imm
== et
.size
)
18067 /* Maximum shift variant. */
18068 NEON_ENCODE (INTEGER
, inst
);
18069 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18073 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18075 neon_dp_fixup (&inst
);
18079 /* A more-specific type check for non-max versions. */
18080 et
= neon_check_type (2, NS_QDI
,
18081 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18082 NEON_ENCODE (IMMED
, inst
);
18083 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18087 /* Check the various types for the VCVT instruction, and return which version
18088 the current instruction is. */
18090 #define CVT_FLAVOUR_VAR \
18091 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18092 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18093 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18094 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18095 /* Half-precision conversions. */ \
18096 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18097 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18098 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18099 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18100 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18101 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18102 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18103 Compared with single/double precision variants, only the co-processor \
18104 field is different, so the encoding flow is reused here. */ \
18105 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18106 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18107 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18108 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18109 /* VFP instructions. */ \
18110 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18111 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18112 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18113 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18114 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18115 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18116 /* VFP instructions with bitshift. */ \
18117 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18118 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18119 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18120 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18121 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18122 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18123 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18124 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18126 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18127 neon_cvt_flavour_##C,
18129 /* The different types of conversions we can do. */
18130 enum neon_cvt_flavour
18133 neon_cvt_flavour_invalid
,
18134 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18139 static enum neon_cvt_flavour
18140 get_neon_cvt_flavour (enum neon_shape rs
)
18142 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18143 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18144 if (et.type != NT_invtype) \
18146 inst.error = NULL; \
18147 return (neon_cvt_flavour_##C); \
18150 struct neon_type_el et
;
18151 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18152 || rs
== NS_FF
) ? N_VFP
: 0;
18153 /* The instruction versions which take an immediate take one register
18154 argument, which is extended to the width of the full register. Thus the
18155 "source" and "destination" registers must have the same width. Hack that
18156 here by making the size equal to the key (wider, in this case) operand. */
18157 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18161 return neon_cvt_flavour_invalid
;
18176 /* Neon-syntax VFP conversions. */
18179 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18181 const char *opname
= 0;
18183 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18184 || rs
== NS_FHI
|| rs
== NS_HFI
)
18186 /* Conversions with immediate bitshift. */
18187 const char *enc
[] =
18189 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18195 if (flavour
< (int) ARRAY_SIZE (enc
))
18197 opname
= enc
[flavour
];
18198 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18199 _("operands 0 and 1 must be the same register"));
18200 inst
.operands
[1] = inst
.operands
[2];
18201 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18206 /* Conversions without bitshift. */
18207 const char *enc
[] =
18209 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18215 if (flavour
< (int) ARRAY_SIZE (enc
))
18216 opname
= enc
[flavour
];
18220 do_vfp_nsyn_opcode (opname
);
18222 /* ARMv8.2 fp16 VCVT instruction. */
18223 if (flavour
== neon_cvt_flavour_s32_f16
18224 || flavour
== neon_cvt_flavour_u32_f16
18225 || flavour
== neon_cvt_flavour_f16_u32
18226 || flavour
== neon_cvt_flavour_f16_s32
)
18227 do_scalar_fp16_v82_encode ();
18231 do_vfp_nsyn_cvtz (void)
18233 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18234 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18235 const char *enc
[] =
18237 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18243 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18244 do_vfp_nsyn_opcode (enc
[flavour
]);
18248 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18249 enum neon_cvt_mode mode
)
18254 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18255 D register operands. */
18256 if (flavour
== neon_cvt_flavour_s32_f64
18257 || flavour
== neon_cvt_flavour_u32_f64
)
18258 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18261 if (flavour
== neon_cvt_flavour_s32_f16
18262 || flavour
== neon_cvt_flavour_u32_f16
)
18263 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18266 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18270 case neon_cvt_flavour_s32_f64
:
18274 case neon_cvt_flavour_s32_f32
:
18278 case neon_cvt_flavour_s32_f16
:
18282 case neon_cvt_flavour_u32_f64
:
18286 case neon_cvt_flavour_u32_f32
:
18290 case neon_cvt_flavour_u32_f16
:
18295 first_error (_("invalid instruction shape"));
18301 case neon_cvt_mode_a
: rm
= 0; break;
18302 case neon_cvt_mode_n
: rm
= 1; break;
18303 case neon_cvt_mode_p
: rm
= 2; break;
18304 case neon_cvt_mode_m
: rm
= 3; break;
18305 default: first_error (_("invalid rounding mode")); return;
18308 NEON_ENCODE (FPV8
, inst
);
18309 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18310 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18311 inst
.instruction
|= sz
<< 8;
18313 /* ARMv8.2 fp16 VCVT instruction. */
18314 if (flavour
== neon_cvt_flavour_s32_f16
18315 ||flavour
== neon_cvt_flavour_u32_f16
)
18316 do_scalar_fp16_v82_encode ();
18317 inst
.instruction
|= op
<< 7;
18318 inst
.instruction
|= rm
<< 16;
18319 inst
.instruction
|= 0xf0000000;
18320 inst
.is_neon
= TRUE
;
18324 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18326 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18327 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18328 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18330 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18332 if (flavour
== neon_cvt_flavour_invalid
)
18335 /* PR11109: Handle round-to-zero for VCVT conversions. */
18336 if (mode
== neon_cvt_mode_z
18337 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18338 && (flavour
== neon_cvt_flavour_s16_f16
18339 || flavour
== neon_cvt_flavour_u16_f16
18340 || flavour
== neon_cvt_flavour_s32_f32
18341 || flavour
== neon_cvt_flavour_u32_f32
18342 || flavour
== neon_cvt_flavour_s32_f64
18343 || flavour
== neon_cvt_flavour_u32_f64
)
18344 && (rs
== NS_FD
|| rs
== NS_FF
))
18346 do_vfp_nsyn_cvtz ();
18350 /* ARMv8.2 fp16 VCVT conversions. */
18351 if (mode
== neon_cvt_mode_z
18352 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18353 && (flavour
== neon_cvt_flavour_s32_f16
18354 || flavour
== neon_cvt_flavour_u32_f16
)
18357 do_vfp_nsyn_cvtz ();
18358 do_scalar_fp16_v82_encode ();
18362 /* VFP rather than Neon conversions. */
18363 if (flavour
>= neon_cvt_flavour_first_fp
)
18365 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18366 do_vfp_nsyn_cvt (rs
, flavour
);
18368 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18376 if (mode
== neon_cvt_mode_z
18377 && (flavour
== neon_cvt_flavour_f16_s16
18378 || flavour
== neon_cvt_flavour_f16_u16
18379 || flavour
== neon_cvt_flavour_s16_f16
18380 || flavour
== neon_cvt_flavour_u16_f16
18381 || flavour
== neon_cvt_flavour_f32_u32
18382 || flavour
== neon_cvt_flavour_f32_s32
18383 || flavour
== neon_cvt_flavour_s32_f32
18384 || flavour
== neon_cvt_flavour_u32_f32
))
18386 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18389 else if (mode
== neon_cvt_mode_n
)
18391 /* We are dealing with vcvt with the 'ne' condition. */
18393 inst
.instruction
= N_MNEM_vcvt
;
18394 do_neon_cvt_1 (neon_cvt_mode_z
);
18397 /* fall through. */
18401 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18402 0x0000100, 0x1000100, 0x0, 0x1000000};
18404 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18405 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18410 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18411 _("immediate value out of range"));
18414 case neon_cvt_flavour_f16_s16
:
18415 case neon_cvt_flavour_f16_u16
:
18416 case neon_cvt_flavour_s16_f16
:
18417 case neon_cvt_flavour_u16_f16
:
18418 constraint (inst
.operands
[2].imm
> 16,
18419 _("immediate value out of range"));
18421 case neon_cvt_flavour_f32_u32
:
18422 case neon_cvt_flavour_f32_s32
:
18423 case neon_cvt_flavour_s32_f32
:
18424 case neon_cvt_flavour_u32_f32
:
18425 constraint (inst
.operands
[2].imm
> 32,
18426 _("immediate value out of range"));
18429 inst
.error
= BAD_FPU
;
18434 /* Fixed-point conversion with #0 immediate is encoded as an
18435 integer conversion. */
18436 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18438 NEON_ENCODE (IMMED
, inst
);
18439 if (flavour
!= neon_cvt_flavour_invalid
)
18440 inst
.instruction
|= enctab
[flavour
];
18441 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18442 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18443 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18444 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18445 inst
.instruction
|= neon_quad (rs
) << 6;
18446 inst
.instruction
|= 1 << 21;
18447 if (flavour
< neon_cvt_flavour_s16_f16
)
18449 inst
.instruction
|= 1 << 21;
18450 immbits
= 32 - inst
.operands
[2].imm
;
18451 inst
.instruction
|= immbits
<< 16;
18455 inst
.instruction
|= 3 << 20;
18456 immbits
= 16 - inst
.operands
[2].imm
;
18457 inst
.instruction
|= immbits
<< 16;
18458 inst
.instruction
&= ~(1 << 9);
18461 neon_dp_fixup (&inst
);
18466 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18467 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18468 && (flavour
== neon_cvt_flavour_s16_f16
18469 || flavour
== neon_cvt_flavour_u16_f16
18470 || flavour
== neon_cvt_flavour_s32_f32
18471 || flavour
== neon_cvt_flavour_u32_f32
))
18473 if (check_simd_pred_availability (1,
18474 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18477 else if (mode
== neon_cvt_mode_z
18478 && (flavour
== neon_cvt_flavour_f16_s16
18479 || flavour
== neon_cvt_flavour_f16_u16
18480 || flavour
== neon_cvt_flavour_s16_f16
18481 || flavour
== neon_cvt_flavour_u16_f16
18482 || flavour
== neon_cvt_flavour_f32_u32
18483 || flavour
== neon_cvt_flavour_f32_s32
18484 || flavour
== neon_cvt_flavour_s32_f32
18485 || flavour
== neon_cvt_flavour_u32_f32
))
18487 if (check_simd_pred_availability (1,
18488 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18491 /* fall through. */
18493 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18496 NEON_ENCODE (FLOAT
, inst
);
18497 if (check_simd_pred_availability (1,
18498 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18501 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18502 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18503 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18504 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18505 inst
.instruction
|= neon_quad (rs
) << 6;
18506 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18507 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18508 inst
.instruction
|= mode
<< 8;
18509 if (flavour
== neon_cvt_flavour_u16_f16
18510 || flavour
== neon_cvt_flavour_s16_f16
)
18511 /* Mask off the original size bits and reencode them. */
18512 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18515 inst
.instruction
|= 0xfc000000;
18517 inst
.instruction
|= 0xf0000000;
18523 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18524 0x100, 0x180, 0x0, 0x080};
18526 NEON_ENCODE (INTEGER
, inst
);
18528 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18530 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18534 if (flavour
!= neon_cvt_flavour_invalid
)
18535 inst
.instruction
|= enctab
[flavour
];
18537 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18538 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18539 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18540 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18541 inst
.instruction
|= neon_quad (rs
) << 6;
18542 if (flavour
>= neon_cvt_flavour_s16_f16
18543 && flavour
<= neon_cvt_flavour_f16_u16
)
18544 /* Half precision. */
18545 inst
.instruction
|= 1 << 18;
18547 inst
.instruction
|= 2 << 18;
18549 neon_dp_fixup (&inst
);
18554 /* Half-precision conversions for Advanced SIMD -- neon. */
18557 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18561 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18563 as_bad (_("operand size must match register width"));
18568 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18570 as_bad (_("operand size must match register width"));
18575 inst
.instruction
= 0x3b60600;
18577 inst
.instruction
= 0x3b60700;
18579 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18580 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18581 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18582 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18583 neon_dp_fixup (&inst
);
18587 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18588 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18589 do_vfp_nsyn_cvt (rs
, flavour
);
18591 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18596 do_neon_cvtr (void)
18598 do_neon_cvt_1 (neon_cvt_mode_x
);
18604 do_neon_cvt_1 (neon_cvt_mode_z
);
18608 do_neon_cvta (void)
18610 do_neon_cvt_1 (neon_cvt_mode_a
);
18614 do_neon_cvtn (void)
18616 do_neon_cvt_1 (neon_cvt_mode_n
);
18620 do_neon_cvtp (void)
18622 do_neon_cvt_1 (neon_cvt_mode_p
);
18626 do_neon_cvtm (void)
18628 do_neon_cvt_1 (neon_cvt_mode_m
);
18632 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18635 mark_feature_used (&fpu_vfp_ext_armv8
);
18637 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18638 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18639 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18640 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18641 inst
.instruction
|= to
? 0x10000 : 0;
18642 inst
.instruction
|= t
? 0x80 : 0;
18643 inst
.instruction
|= is_double
? 0x100 : 0;
18644 do_vfp_cond_or_thumb ();
18648 do_neon_cvttb_1 (bfd_boolean t
)
18650 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18651 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18655 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18657 int single_to_half
= 0;
18658 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
18661 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18663 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18664 && (flavour
== neon_cvt_flavour_u16_f16
18665 || flavour
== neon_cvt_flavour_s16_f16
18666 || flavour
== neon_cvt_flavour_f16_s16
18667 || flavour
== neon_cvt_flavour_f16_u16
18668 || flavour
== neon_cvt_flavour_u32_f32
18669 || flavour
== neon_cvt_flavour_s32_f32
18670 || flavour
== neon_cvt_flavour_f32_s32
18671 || flavour
== neon_cvt_flavour_f32_u32
))
18674 inst
.instruction
= N_MNEM_vcvt
;
18675 set_pred_insn_type (INSIDE_VPT_INSN
);
18676 do_neon_cvt_1 (neon_cvt_mode_z
);
18679 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18680 single_to_half
= 1;
18681 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18683 first_error (BAD_FPU
);
18687 inst
.instruction
= 0xee3f0e01;
18688 inst
.instruction
|= single_to_half
<< 28;
18689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18690 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18691 inst
.instruction
|= t
<< 12;
18692 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18696 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18699 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18701 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18704 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18706 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18708 /* The VCVTB and VCVTT instructions with D-register operands
18709 don't work for SP only targets. */
18710 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18714 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18716 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18718 /* The VCVTB and VCVTT instructions with D-register operands
18719 don't work for SP only targets. */
18720 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18724 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18731 do_neon_cvtb (void)
18733 do_neon_cvttb_1 (FALSE
);
18738 do_neon_cvtt (void)
18740 do_neon_cvttb_1 (TRUE
);
18744 neon_move_immediate (void)
18746 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18747 struct neon_type_el et
= neon_check_type (2, rs
,
18748 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18749 unsigned immlo
, immhi
= 0, immbits
;
18750 int op
, cmode
, float_p
;
18752 constraint (et
.type
== NT_invtype
,
18753 _("operand size must be specified for immediate VMOV"));
18755 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18756 op
= (inst
.instruction
& (1 << 5)) != 0;
18758 immlo
= inst
.operands
[1].imm
;
18759 if (inst
.operands
[1].regisimm
)
18760 immhi
= inst
.operands
[1].reg
;
18762 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18763 _("immediate has bits set outside the operand size"));
18765 float_p
= inst
.operands
[1].immisfloat
;
18767 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18768 et
.size
, et
.type
)) == FAIL
)
18770 /* Invert relevant bits only. */
18771 neon_invert_size (&immlo
, &immhi
, et
.size
);
18772 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18773 with one or the other; those cases are caught by
18774 neon_cmode_for_move_imm. */
18776 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18777 &op
, et
.size
, et
.type
)) == FAIL
)
18779 first_error (_("immediate out of range"));
18784 inst
.instruction
&= ~(1 << 5);
18785 inst
.instruction
|= op
<< 5;
18787 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18788 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18789 inst
.instruction
|= neon_quad (rs
) << 6;
18790 inst
.instruction
|= cmode
<< 8;
18792 neon_write_immbits (immbits
);
18798 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18801 if (inst
.operands
[1].isreg
)
18803 enum neon_shape rs
;
18804 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18805 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
18807 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18809 NEON_ENCODE (INTEGER
, inst
);
18810 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18812 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18813 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18814 inst
.instruction
|= neon_quad (rs
) << 6;
18818 NEON_ENCODE (IMMED
, inst
);
18819 neon_move_immediate ();
18822 neon_dp_fixup (&inst
);
18824 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18826 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
18827 constraint ((inst
.instruction
& 0xd00) == 0xd00,
18828 _("immediate value out of range"));
18832 /* Encode instructions of form:
18834 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18835 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18838 neon_mixed_length (struct neon_type_el et
, unsigned size
)
18840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18843 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18844 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18845 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18846 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
18847 inst
.instruction
|= neon_logbits (size
) << 20;
18849 neon_dp_fixup (&inst
);
18853 do_neon_dyadic_long (void)
18855 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
18858 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
18861 NEON_ENCODE (INTEGER
, inst
);
18862 /* FIXME: Type checking for lengthening op. */
18863 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18864 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18865 neon_mixed_length (et
, et
.size
);
18867 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18868 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
18870 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18871 in an IT block with le/lt conditions. */
18873 if (inst
.cond
== 0xf)
18875 else if (inst
.cond
== 0x10)
18878 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18880 if (inst
.instruction
== N_MNEM_vaddl
)
18882 inst
.instruction
= N_MNEM_vadd
;
18883 do_neon_addsub_if_i ();
18885 else if (inst
.instruction
== N_MNEM_vsubl
)
18887 inst
.instruction
= N_MNEM_vsub
;
18888 do_neon_addsub_if_i ();
18890 else if (inst
.instruction
== N_MNEM_vabdl
)
18892 inst
.instruction
= N_MNEM_vabd
;
18893 do_neon_dyadic_if_su ();
18897 first_error (BAD_FPU
);
18901 do_neon_abal (void)
18903 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18904 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18905 neon_mixed_length (et
, et
.size
);
18909 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
18911 if (inst
.operands
[2].isscalar
)
18913 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
18914 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
18915 NEON_ENCODE (SCALAR
, inst
);
18916 neon_mul_mac (et
, et
.type
== NT_unsigned
);
18920 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18921 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
18922 NEON_ENCODE (INTEGER
, inst
);
18923 neon_mixed_length (et
, et
.size
);
18928 do_neon_mac_maybe_scalar_long (void)
18930 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
18933 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18934 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18937 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
18939 unsigned regno
= NEON_SCALAR_REG (scalar
);
18940 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
18944 if (regno
> 7 || elno
> 3)
18947 return ((regno
& 0x7)
18948 | ((elno
& 0x1) << 3)
18949 | (((elno
>> 1) & 0x1) << 5));
18953 if (regno
> 15 || elno
> 1)
18956 return (((regno
& 0x1) << 5)
18957 | ((regno
>> 1) & 0x7)
18958 | ((elno
& 0x1) << 3));
18962 first_error (_("scalar out of range for multiply instruction"));
18967 do_neon_fmac_maybe_scalar_long (int subtype
)
18969 enum neon_shape rs
;
18971 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18972 field (bits[21:20]) has different meaning. For scalar index variant, it's
18973 used to differentiate add and subtract, otherwise it's with fixed value
18977 if (inst
.cond
!= COND_ALWAYS
)
18978 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18979 "behaviour is UNPREDICTABLE"));
18981 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18987 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18988 be a scalar index register. */
18989 if (inst
.operands
[2].isscalar
)
18991 high8
= 0xfe000000;
18994 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18998 high8
= 0xfc000000;
19001 inst
.instruction
|= (0x1 << 23);
19002 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19005 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19007 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19008 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19009 so we simply pass -1 as size. */
19010 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19011 neon_three_same (quad_p
, 0, size
);
19013 /* Undo neon_dp_fixup. Redo the high eight bits. */
19014 inst
.instruction
&= 0x00ffffff;
19015 inst
.instruction
|= high8
;
19017 #define LOW1(R) ((R) & 0x1)
19018 #define HI4(R) (((R) >> 1) & 0xf)
19019 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19020 whether the instruction is in Q form and whether Vm is a scalar indexed
19022 if (inst
.operands
[2].isscalar
)
19025 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19026 inst
.instruction
&= 0xffffffd0;
19027 inst
.instruction
|= rm
;
19031 /* Redo Rn as well. */
19032 inst
.instruction
&= 0xfff0ff7f;
19033 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19034 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19039 /* Redo Rn and Rm. */
19040 inst
.instruction
&= 0xfff0ff50;
19041 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19042 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19043 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19044 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19049 do_neon_vfmal (void)
19051 return do_neon_fmac_maybe_scalar_long (0);
19055 do_neon_vfmsl (void)
19057 return do_neon_fmac_maybe_scalar_long (1);
19061 do_neon_dyadic_wide (void)
19063 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19064 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19065 neon_mixed_length (et
, et
.size
);
19069 do_neon_dyadic_narrow (void)
19071 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19072 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19073 /* Operand sign is unimportant, and the U bit is part of the opcode,
19074 so force the operand type to integer. */
19075 et
.type
= NT_integer
;
19076 neon_mixed_length (et
, et
.size
/ 2);
19080 do_neon_mul_sat_scalar_long (void)
19082 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19086 do_neon_vmull (void)
19088 if (inst
.operands
[2].isscalar
)
19089 do_neon_mac_maybe_scalar_long ();
19092 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19093 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19095 if (et
.type
== NT_poly
)
19096 NEON_ENCODE (POLY
, inst
);
19098 NEON_ENCODE (INTEGER
, inst
);
19100 /* For polynomial encoding the U bit must be zero, and the size must
19101 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19102 obviously, as 0b10). */
19105 /* Check we're on the correct architecture. */
19106 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19108 _("Instruction form not available on this architecture.");
19113 neon_mixed_length (et
, et
.size
);
19120 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19121 struct neon_type_el et
= neon_check_type (3, rs
,
19122 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19123 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19125 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19126 _("shift out of range"));
19127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19128 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19130 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19131 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19132 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19133 inst
.instruction
|= neon_quad (rs
) << 6;
19134 inst
.instruction
|= imm
<< 8;
19136 neon_dp_fixup (&inst
);
19142 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19145 enum neon_shape rs
;
19146 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19147 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19149 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19151 struct neon_type_el et
= neon_check_type (2, rs
,
19152 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19154 unsigned op
= (inst
.instruction
>> 7) & 3;
19155 /* N (width of reversed regions) is encoded as part of the bitmask. We
19156 extract it here to check the elements to be reversed are smaller.
19157 Otherwise we'd get a reserved instruction. */
19158 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19160 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19161 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19162 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19163 " operands makes instruction UNPREDICTABLE"));
19165 gas_assert (elsize
!= 0);
19166 constraint (et
.size
>= elsize
,
19167 _("elements must be smaller than reversal region"));
19168 neon_two_same (neon_quad (rs
), 1, et
.size
);
19174 if (inst
.operands
[1].isscalar
)
19176 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19178 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19179 struct neon_type_el et
= neon_check_type (2, rs
,
19180 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19181 unsigned sizebits
= et
.size
>> 3;
19182 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19183 int logsize
= neon_logbits (et
.size
);
19184 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19186 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19189 NEON_ENCODE (SCALAR
, inst
);
19190 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19191 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19192 inst
.instruction
|= LOW4 (dm
);
19193 inst
.instruction
|= HI1 (dm
) << 5;
19194 inst
.instruction
|= neon_quad (rs
) << 6;
19195 inst
.instruction
|= x
<< 17;
19196 inst
.instruction
|= sizebits
<< 16;
19198 neon_dp_fixup (&inst
);
19202 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19203 struct neon_type_el et
= neon_check_type (2, rs
,
19204 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19207 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
))
19211 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19214 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19216 if (inst
.operands
[1].reg
== REG_SP
)
19217 as_tsktsk (MVE_BAD_SP
);
19218 else if (inst
.operands
[1].reg
== REG_PC
)
19219 as_tsktsk (MVE_BAD_PC
);
19222 /* Duplicate ARM register to lanes of vector. */
19223 NEON_ENCODE (ARMREG
, inst
);
19226 case 8: inst
.instruction
|= 0x400000; break;
19227 case 16: inst
.instruction
|= 0x000020; break;
19228 case 32: inst
.instruction
|= 0x000000; break;
19231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19234 inst
.instruction
|= neon_quad (rs
) << 21;
19235 /* The encoding for this instruction is identical for the ARM and Thumb
19236 variants, except for the condition field. */
19237 do_vfp_cond_or_thumb ();
19242 do_mve_mov (int toQ
)
19244 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19246 if (inst
.cond
> COND_ALWAYS
)
19247 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19249 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19258 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19259 _("Index one must be [2,3] and index two must be two less than"
19261 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19262 _("General purpose registers may not be the same"));
19263 constraint (inst
.operands
[Rt
].reg
== REG_SP
19264 || inst
.operands
[Rt2
].reg
== REG_SP
,
19266 constraint (inst
.operands
[Rt
].reg
== REG_PC
19267 || inst
.operands
[Rt2
].reg
== REG_PC
,
19270 inst
.instruction
= 0xec000f00;
19271 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19272 inst
.instruction
|= !!toQ
<< 20;
19273 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19274 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19275 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19276 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19282 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19285 if (inst
.cond
> COND_ALWAYS
)
19286 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19288 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19290 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19293 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19294 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19295 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19296 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19297 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19302 /* VMOV has particularly many variations. It can be one of:
19303 0. VMOV<c><q> <Qd>, <Qm>
19304 1. VMOV<c><q> <Dd>, <Dm>
19305 (Register operations, which are VORR with Rm = Rn.)
19306 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19307 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19309 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19310 (ARM register to scalar.)
19311 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19312 (Two ARM registers to vector.)
19313 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19314 (Scalar to ARM register.)
19315 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19316 (Vector to two ARM registers.)
19317 8. VMOV.F32 <Sd>, <Sm>
19318 9. VMOV.F64 <Dd>, <Dm>
19319 (VFP register moves.)
19320 10. VMOV.F32 <Sd>, #imm
19321 11. VMOV.F64 <Dd>, #imm
19322 (VFP float immediate load.)
19323 12. VMOV <Rd>, <Sm>
19324 (VFP single to ARM reg.)
19325 13. VMOV <Sd>, <Rm>
19326 (ARM reg to VFP single.)
19327 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19328 (Two ARM regs to two VFP singles.)
19329 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19330 (Two VFP singles to two ARM regs.)
19331 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19332 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19333 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19334 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19336 These cases can be disambiguated using neon_select_shape, except cases 1/9
19337 and 3/11 which depend on the operand type too.
19339 All the encoded bits are hardcoded by this function.
19341 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19342 Cases 5, 7 may be used with VFPv2 and above.
19344 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19345 can specify a type where it doesn't make sense to, and is ignored). */
19350 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19351 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19352 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19353 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19355 struct neon_type_el et
;
19356 const char *ldconst
= 0;
19360 case NS_DD
: /* case 1/9. */
19361 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19362 /* It is not an error here if no type is given. */
19364 if (et
.type
== NT_float
&& et
.size
== 64)
19366 do_vfp_nsyn_opcode ("fcpyd");
19369 /* fall through. */
19371 case NS_QQ
: /* case 0/1. */
19373 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19375 /* The architecture manual I have doesn't explicitly state which
19376 value the U bit should have for register->register moves, but
19377 the equivalent VORR instruction has U = 0, so do that. */
19378 inst
.instruction
= 0x0200110;
19379 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19380 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19381 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19382 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19384 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19385 inst
.instruction
|= neon_quad (rs
) << 6;
19387 neon_dp_fixup (&inst
);
19391 case NS_DI
: /* case 3/11. */
19392 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19394 if (et
.type
== NT_float
&& et
.size
== 64)
19396 /* case 11 (fconstd). */
19397 ldconst
= "fconstd";
19398 goto encode_fconstd
;
19400 /* fall through. */
19402 case NS_QI
: /* case 2/3. */
19403 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19405 inst
.instruction
= 0x0800010;
19406 neon_move_immediate ();
19407 neon_dp_fixup (&inst
);
19410 case NS_SR
: /* case 4. */
19412 unsigned bcdebits
= 0;
19414 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19415 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19417 /* .<size> is optional here, defaulting to .32. */
19418 if (inst
.vectype
.elems
== 0
19419 && inst
.operands
[0].vectype
.type
== NT_invtype
19420 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19422 inst
.vectype
.el
[0].type
= NT_untyped
;
19423 inst
.vectype
.el
[0].size
= 32;
19424 inst
.vectype
.elems
= 1;
19427 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19428 logsize
= neon_logbits (et
.size
);
19432 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19433 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19438 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19439 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19443 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19445 if (inst
.operands
[1].reg
== REG_SP
)
19446 as_tsktsk (MVE_BAD_SP
);
19447 else if (inst
.operands
[1].reg
== REG_PC
)
19448 as_tsktsk (MVE_BAD_PC
);
19450 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19452 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19453 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19458 case 8: bcdebits
= 0x8; break;
19459 case 16: bcdebits
= 0x1; break;
19460 case 32: bcdebits
= 0x0; break;
19464 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19466 inst
.instruction
= 0xe000b10;
19467 do_vfp_cond_or_thumb ();
19468 inst
.instruction
|= LOW4 (dn
) << 16;
19469 inst
.instruction
|= HI1 (dn
) << 7;
19470 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19471 inst
.instruction
|= (bcdebits
& 3) << 5;
19472 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19473 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19477 case NS_DRR
: /* case 5 (fmdrr). */
19478 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19479 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19482 inst
.instruction
= 0xc400b10;
19483 do_vfp_cond_or_thumb ();
19484 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19486 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19487 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19490 case NS_RS
: /* case 6. */
19493 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19494 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19495 unsigned abcdebits
= 0;
19497 /* .<dt> is optional here, defaulting to .32. */
19498 if (inst
.vectype
.elems
== 0
19499 && inst
.operands
[0].vectype
.type
== NT_invtype
19500 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19502 inst
.vectype
.el
[0].type
= NT_untyped
;
19503 inst
.vectype
.el
[0].size
= 32;
19504 inst
.vectype
.elems
= 1;
19507 et
= neon_check_type (2, NS_NULL
,
19508 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19509 logsize
= neon_logbits (et
.size
);
19513 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19514 && vfp_or_neon_is_neon (NEON_CHECK_CC
19515 | NEON_CHECK_ARCH
) == FAIL
)
19520 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19521 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19525 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19527 if (inst
.operands
[0].reg
== REG_SP
)
19528 as_tsktsk (MVE_BAD_SP
);
19529 else if (inst
.operands
[0].reg
== REG_PC
)
19530 as_tsktsk (MVE_BAD_PC
);
19533 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19535 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19536 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19540 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19541 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19542 case 32: abcdebits
= 0x00; break;
19546 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19547 inst
.instruction
= 0xe100b10;
19548 do_vfp_cond_or_thumb ();
19549 inst
.instruction
|= LOW4 (dn
) << 16;
19550 inst
.instruction
|= HI1 (dn
) << 7;
19551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19552 inst
.instruction
|= (abcdebits
& 3) << 5;
19553 inst
.instruction
|= (abcdebits
>> 2) << 21;
19554 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19558 case NS_RRD
: /* case 7 (fmrrd). */
19559 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19560 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19563 inst
.instruction
= 0xc500b10;
19564 do_vfp_cond_or_thumb ();
19565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19566 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19567 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19568 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19571 case NS_FF
: /* case 8 (fcpys). */
19572 do_vfp_nsyn_opcode ("fcpys");
19576 case NS_FI
: /* case 10 (fconsts). */
19577 ldconst
= "fconsts";
19579 if (!inst
.operands
[1].immisfloat
)
19582 /* Immediate has to fit in 8 bits so float is enough. */
19583 float imm
= (float) inst
.operands
[1].imm
;
19584 memcpy (&new_imm
, &imm
, sizeof (float));
19585 /* But the assembly may have been written to provide an integer
19586 bit pattern that equates to a float, so check that the
19587 conversion has worked. */
19588 if (is_quarter_float (new_imm
))
19590 if (is_quarter_float (inst
.operands
[1].imm
))
19591 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19593 inst
.operands
[1].imm
= new_imm
;
19594 inst
.operands
[1].immisfloat
= 1;
19598 if (is_quarter_float (inst
.operands
[1].imm
))
19600 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19601 do_vfp_nsyn_opcode (ldconst
);
19603 /* ARMv8.2 fp16 vmov.f16 instruction. */
19605 do_scalar_fp16_v82_encode ();
19608 first_error (_("immediate out of range"));
19612 case NS_RF
: /* case 12 (fmrs). */
19613 do_vfp_nsyn_opcode ("fmrs");
19614 /* ARMv8.2 fp16 vmov.f16 instruction. */
19616 do_scalar_fp16_v82_encode ();
19620 case NS_FR
: /* case 13 (fmsr). */
19621 do_vfp_nsyn_opcode ("fmsr");
19622 /* ARMv8.2 fp16 vmov.f16 instruction. */
19624 do_scalar_fp16_v82_encode ();
19634 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19635 (one of which is a list), but we have parsed four. Do some fiddling to
19636 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19638 case NS_RRFF
: /* case 14 (fmrrs). */
19639 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19640 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19642 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19643 _("VFP registers must be adjacent"));
19644 inst
.operands
[2].imm
= 2;
19645 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19646 do_vfp_nsyn_opcode ("fmrrs");
19649 case NS_FFRR
: /* case 15 (fmsrr). */
19650 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19651 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19653 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19654 _("VFP registers must be adjacent"));
19655 inst
.operands
[1] = inst
.operands
[2];
19656 inst
.operands
[2] = inst
.operands
[3];
19657 inst
.operands
[0].imm
= 2;
19658 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19659 do_vfp_nsyn_opcode ("fmsrr");
19663 /* neon_select_shape has determined that the instruction
19664 shape is wrong and has already set the error message. */
19675 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19676 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19677 && !inst
.operands
[2].present
))
19679 inst
.instruction
= 0;
19682 set_pred_insn_type (INSIDE_IT_INSN
);
19687 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19690 if (inst
.cond
!= COND_ALWAYS
)
19691 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19693 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19694 | N_S16
| N_U16
| N_KEY
);
19696 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19697 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19698 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19701 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19706 do_neon_rshift_round_imm (void)
19708 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19711 enum neon_shape rs
;
19712 struct neon_type_el et
;
19714 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19716 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
19717 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
19721 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19722 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19724 int imm
= inst
.operands
[2].imm
;
19726 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19729 inst
.operands
[2].present
= 0;
19734 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19735 _("immediate out of range for shift"));
19736 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19741 do_neon_movhf (void)
19743 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19744 constraint (rs
!= NS_HH
, _("invalid suffix"));
19746 if (inst
.cond
!= COND_ALWAYS
)
19750 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19751 " the behaviour is UNPREDICTABLE"));
19755 inst
.error
= BAD_COND
;
19760 do_vfp_sp_monadic ();
19763 inst
.instruction
|= 0xf0000000;
19767 do_neon_movl (void)
19769 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19770 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19771 unsigned sizebits
= et
.size
>> 3;
19772 inst
.instruction
|= sizebits
<< 19;
19773 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19779 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19780 struct neon_type_el et
= neon_check_type (2, rs
,
19781 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19782 NEON_ENCODE (INTEGER
, inst
);
19783 neon_two_same (neon_quad (rs
), 1, et
.size
);
19787 do_neon_zip_uzp (void)
19789 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19790 struct neon_type_el et
= neon_check_type (2, rs
,
19791 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19792 if (rs
== NS_DD
&& et
.size
== 32)
19794 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19795 inst
.instruction
= N_MNEM_vtrn
;
19799 neon_two_same (neon_quad (rs
), 1, et
.size
);
19803 do_neon_sat_abs_neg (void)
19805 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19808 enum neon_shape rs
;
19809 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19810 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19812 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19813 struct neon_type_el et
= neon_check_type (2, rs
,
19814 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19815 neon_two_same (neon_quad (rs
), 1, et
.size
);
19819 do_neon_pair_long (void)
19821 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19822 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
19823 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19824 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
19825 neon_two_same (neon_quad (rs
), 1, et
.size
);
19829 do_neon_recip_est (void)
19831 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19832 struct neon_type_el et
= neon_check_type (2, rs
,
19833 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
19834 inst
.instruction
|= (et
.type
== NT_float
) << 8;
19835 neon_two_same (neon_quad (rs
), 1, et
.size
);
19841 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19844 enum neon_shape rs
;
19845 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19846 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19848 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19850 struct neon_type_el et
= neon_check_type (2, rs
,
19851 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19852 neon_two_same (neon_quad (rs
), 1, et
.size
);
19858 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19861 enum neon_shape rs
;
19862 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19863 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19865 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19867 struct neon_type_el et
= neon_check_type (2, rs
,
19868 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
19869 neon_two_same (neon_quad (rs
), 1, et
.size
);
19875 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19876 struct neon_type_el et
= neon_check_type (2, rs
,
19877 N_EQK
| N_INT
, N_8
| N_KEY
);
19878 neon_two_same (neon_quad (rs
), 1, et
.size
);
19884 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19885 neon_two_same (neon_quad (rs
), 1, -1);
19889 do_neon_tbl_tbx (void)
19891 unsigned listlenbits
;
19892 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
19894 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
19896 first_error (_("bad list length for table lookup"));
19900 listlenbits
= inst
.operands
[1].imm
- 1;
19901 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19903 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19904 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19905 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19906 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19907 inst
.instruction
|= listlenbits
<< 8;
19909 neon_dp_fixup (&inst
);
19913 do_neon_ldm_stm (void)
19915 /* P, U and L bits are part of bitmask. */
19916 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
19917 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
19919 if (inst
.operands
[1].issingle
)
19921 do_vfp_nsyn_ldm_stm (is_dbmode
);
19925 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
19926 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19928 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
19929 _("register list must contain at least 1 and at most 16 "
19932 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
19933 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
19934 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19935 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
19937 inst
.instruction
|= offsetbits
;
19939 do_vfp_cond_or_thumb ();
19943 do_neon_ldr_str (void)
19945 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
19947 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19948 And is UNPREDICTABLE in thumb mode. */
19950 && inst
.operands
[1].reg
== REG_PC
19951 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
19954 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19955 else if (warn_on_deprecated
)
19956 as_tsktsk (_("Use of PC here is deprecated"));
19959 if (inst
.operands
[0].issingle
)
19962 do_vfp_nsyn_opcode ("flds");
19964 do_vfp_nsyn_opcode ("fsts");
19966 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19967 if (inst
.vectype
.el
[0].size
== 16)
19968 do_scalar_fp16_v82_encode ();
19973 do_vfp_nsyn_opcode ("fldd");
19975 do_vfp_nsyn_opcode ("fstd");
19980 do_t_vldr_vstr_sysreg (void)
19982 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
19983 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
19985 /* Use of PC is UNPREDICTABLE. */
19986 if (inst
.operands
[1].reg
== REG_PC
)
19987 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19989 if (inst
.operands
[1].immisreg
)
19990 inst
.error
= _("instruction does not accept register index");
19992 if (!inst
.operands
[1].isreg
)
19993 inst
.error
= _("instruction does not accept PC-relative addressing");
19995 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
19996 inst
.error
= _("immediate value out of range");
19998 inst
.instruction
= 0xec000f80;
20000 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20001 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20002 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20003 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20007 do_vldr_vstr (void)
20009 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20011 /* VLDR/VSTR (System Register). */
20014 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20015 as_bad (_("Instruction not permitted on this architecture"));
20017 do_t_vldr_vstr_sysreg ();
20022 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20023 as_bad (_("Instruction not permitted on this architecture"));
20024 do_neon_ldr_str ();
20028 /* "interleave" version also handles non-interleaving register VLD1/VST1
20032 do_neon_ld_st_interleave (void)
20034 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20035 N_8
| N_16
| N_32
| N_64
);
20036 unsigned alignbits
= 0;
20038 /* The bits in this table go:
20039 0: register stride of one (0) or two (1)
20040 1,2: register list length, minus one (1, 2, 3, 4).
20041 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20042 We use -1 for invalid entries. */
20043 const int typetable
[] =
20045 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20046 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20047 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20048 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20052 if (et
.type
== NT_invtype
)
20055 if (inst
.operands
[1].immisalign
)
20056 switch (inst
.operands
[1].imm
>> 8)
20058 case 64: alignbits
= 1; break;
20060 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20061 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20062 goto bad_alignment
;
20066 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20067 goto bad_alignment
;
20072 first_error (_("bad alignment"));
20076 inst
.instruction
|= alignbits
<< 4;
20077 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20079 /* Bits [4:6] of the immediate in a list specifier encode register stride
20080 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20081 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20082 up the right value for "type" in a table based on this value and the given
20083 list style, then stick it back. */
20084 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20085 | (((inst
.instruction
>> 8) & 3) << 3);
20087 typebits
= typetable
[idx
];
20089 constraint (typebits
== -1, _("bad list type for instruction"));
20090 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20093 inst
.instruction
&= ~0xf00;
20094 inst
.instruction
|= typebits
<< 8;
20097 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20098 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20099 otherwise. The variable arguments are a list of pairs of legal (size, align)
20100 values, terminated with -1. */
20103 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20106 int result
= FAIL
, thissize
, thisalign
;
20108 if (!inst
.operands
[1].immisalign
)
20114 va_start (ap
, do_alignment
);
20118 thissize
= va_arg (ap
, int);
20119 if (thissize
== -1)
20121 thisalign
= va_arg (ap
, int);
20123 if (size
== thissize
&& align
== thisalign
)
20126 while (result
!= SUCCESS
);
20130 if (result
== SUCCESS
)
20133 first_error (_("unsupported alignment for instruction"));
20139 do_neon_ld_st_lane (void)
20141 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20142 int align_good
, do_alignment
= 0;
20143 int logsize
= neon_logbits (et
.size
);
20144 int align
= inst
.operands
[1].imm
>> 8;
20145 int n
= (inst
.instruction
>> 8) & 3;
20146 int max_el
= 64 / et
.size
;
20148 if (et
.type
== NT_invtype
)
20151 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20152 _("bad list length"));
20153 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20154 _("scalar index out of range"));
20155 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20157 _("stride of 2 unavailable when element size is 8"));
20161 case 0: /* VLD1 / VST1. */
20162 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20164 if (align_good
== FAIL
)
20168 unsigned alignbits
= 0;
20171 case 16: alignbits
= 0x1; break;
20172 case 32: alignbits
= 0x3; break;
20175 inst
.instruction
|= alignbits
<< 4;
20179 case 1: /* VLD2 / VST2. */
20180 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20181 16, 32, 32, 64, -1);
20182 if (align_good
== FAIL
)
20185 inst
.instruction
|= 1 << 4;
20188 case 2: /* VLD3 / VST3. */
20189 constraint (inst
.operands
[1].immisalign
,
20190 _("can't use alignment with this instruction"));
20193 case 3: /* VLD4 / VST4. */
20194 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20195 16, 64, 32, 64, 32, 128, -1);
20196 if (align_good
== FAIL
)
20200 unsigned alignbits
= 0;
20203 case 8: alignbits
= 0x1; break;
20204 case 16: alignbits
= 0x1; break;
20205 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20208 inst
.instruction
|= alignbits
<< 4;
20215 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20216 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20217 inst
.instruction
|= 1 << (4 + logsize
);
20219 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20220 inst
.instruction
|= logsize
<< 10;
20223 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20226 do_neon_ld_dup (void)
20228 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20229 int align_good
, do_alignment
= 0;
20231 if (et
.type
== NT_invtype
)
20234 switch ((inst
.instruction
>> 8) & 3)
20236 case 0: /* VLD1. */
20237 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20238 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20239 &do_alignment
, 16, 16, 32, 32, -1);
20240 if (align_good
== FAIL
)
20242 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20245 case 2: inst
.instruction
|= 1 << 5; break;
20246 default: first_error (_("bad list length")); return;
20248 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20251 case 1: /* VLD2. */
20252 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20253 &do_alignment
, 8, 16, 16, 32, 32, 64,
20255 if (align_good
== FAIL
)
20257 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20258 _("bad list length"));
20259 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20260 inst
.instruction
|= 1 << 5;
20261 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20264 case 2: /* VLD3. */
20265 constraint (inst
.operands
[1].immisalign
,
20266 _("can't use alignment with this instruction"));
20267 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20268 _("bad list length"));
20269 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20270 inst
.instruction
|= 1 << 5;
20271 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20274 case 3: /* VLD4. */
20276 int align
= inst
.operands
[1].imm
>> 8;
20277 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20278 16, 64, 32, 64, 32, 128, -1);
20279 if (align_good
== FAIL
)
20281 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20282 _("bad list length"));
20283 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20284 inst
.instruction
|= 1 << 5;
20285 if (et
.size
== 32 && align
== 128)
20286 inst
.instruction
|= 0x3 << 6;
20288 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20295 inst
.instruction
|= do_alignment
<< 4;
20298 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20299 apart from bits [11:4]. */
20302 do_neon_ldx_stx (void)
20304 if (inst
.operands
[1].isreg
)
20305 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20307 switch (NEON_LANE (inst
.operands
[0].imm
))
20309 case NEON_INTERLEAVE_LANES
:
20310 NEON_ENCODE (INTERLV
, inst
);
20311 do_neon_ld_st_interleave ();
20314 case NEON_ALL_LANES
:
20315 NEON_ENCODE (DUP
, inst
);
20316 if (inst
.instruction
== N_INV
)
20318 first_error ("only loads support such operands");
20325 NEON_ENCODE (LANE
, inst
);
20326 do_neon_ld_st_lane ();
20329 /* L bit comes from bit mask. */
20330 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20331 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20332 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20334 if (inst
.operands
[1].postind
)
20336 int postreg
= inst
.operands
[1].imm
& 0xf;
20337 constraint (!inst
.operands
[1].immisreg
,
20338 _("post-index must be a register"));
20339 constraint (postreg
== 0xd || postreg
== 0xf,
20340 _("bad register for post-index"));
20341 inst
.instruction
|= postreg
;
20345 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20346 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20347 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20350 if (inst
.operands
[1].writeback
)
20352 inst
.instruction
|= 0xd;
20355 inst
.instruction
|= 0xf;
20359 inst
.instruction
|= 0xf9000000;
20361 inst
.instruction
|= 0xf4000000;
20366 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20368 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20369 D register operands. */
20370 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20374 NEON_ENCODE (FPV8
, inst
);
20376 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20378 do_vfp_sp_dyadic ();
20380 /* ARMv8.2 fp16 instruction. */
20382 do_scalar_fp16_v82_encode ();
20385 do_vfp_dp_rd_rn_rm ();
20388 inst
.instruction
|= 0x100;
20390 inst
.instruction
|= 0xf0000000;
20396 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20398 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20399 first_error (_("invalid instruction shape"));
20405 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20406 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20408 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20411 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20414 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20418 do_vrint_1 (enum neon_cvt_mode mode
)
20420 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20421 struct neon_type_el et
;
20426 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20427 D register operands. */
20428 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20432 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20434 if (et
.type
!= NT_invtype
)
20436 /* VFP encodings. */
20437 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20438 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20439 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20441 NEON_ENCODE (FPV8
, inst
);
20442 if (rs
== NS_FF
|| rs
== NS_HH
)
20443 do_vfp_sp_monadic ();
20445 do_vfp_dp_rd_rm ();
20449 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20450 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20451 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20452 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20453 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20454 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20455 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20459 inst
.instruction
|= (rs
== NS_DD
) << 8;
20460 do_vfp_cond_or_thumb ();
20462 /* ARMv8.2 fp16 vrint instruction. */
20464 do_scalar_fp16_v82_encode ();
20468 /* Neon encodings (or something broken...). */
20470 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20472 if (et
.type
== NT_invtype
)
20475 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20478 NEON_ENCODE (FLOAT
, inst
);
20480 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20481 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20482 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20483 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20484 inst
.instruction
|= neon_quad (rs
) << 6;
20485 /* Mask off the original size bits and reencode them. */
20486 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20487 | neon_logbits (et
.size
) << 18);
20491 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20492 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20493 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20494 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20495 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20496 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20497 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20502 inst
.instruction
|= 0xfc000000;
20504 inst
.instruction
|= 0xf0000000;
20511 do_vrint_1 (neon_cvt_mode_x
);
20517 do_vrint_1 (neon_cvt_mode_z
);
20523 do_vrint_1 (neon_cvt_mode_r
);
20529 do_vrint_1 (neon_cvt_mode_a
);
20535 do_vrint_1 (neon_cvt_mode_n
);
20541 do_vrint_1 (neon_cvt_mode_p
);
20547 do_vrint_1 (neon_cvt_mode_m
);
20551 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20553 unsigned regno
= NEON_SCALAR_REG (opnd
);
20554 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20556 if (elsize
== 16 && elno
< 2 && regno
< 16)
20557 return regno
| (elno
<< 4);
20558 else if (elsize
== 32 && elno
== 0)
20561 first_error (_("scalar out of range"));
20568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20569 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20570 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20571 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20572 _("expression too complex"));
20573 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20574 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20575 _("immediate out of range"));
20578 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20581 if (inst
.operands
[2].isscalar
)
20583 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20584 first_error (_("invalid instruction shape"));
20585 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20586 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20587 N_KEY
| N_F16
| N_F32
).size
;
20588 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20590 inst
.instruction
= 0xfe000800;
20591 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20592 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20593 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20594 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20595 inst
.instruction
|= LOW4 (m
);
20596 inst
.instruction
|= HI1 (m
) << 5;
20597 inst
.instruction
|= neon_quad (rs
) << 6;
20598 inst
.instruction
|= rot
<< 20;
20599 inst
.instruction
|= (size
== 32) << 23;
20603 enum neon_shape rs
;
20604 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20605 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20607 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20609 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20610 N_KEY
| N_F16
| N_F32
).size
;
20611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20612 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20613 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20614 as_tsktsk (BAD_MVE_SRCDEST
);
20616 neon_three_same (neon_quad (rs
), 0, -1);
20617 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20618 inst
.instruction
|= 0xfc200800;
20619 inst
.instruction
|= rot
<< 23;
20620 inst
.instruction
|= (size
== 32) << 20;
20627 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20628 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20629 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20630 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20631 _("expression too complex"));
20633 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20634 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20635 enum neon_shape rs
;
20636 struct neon_type_el et
;
20637 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20639 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20640 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20644 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20645 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20647 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20648 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20649 "operand makes instruction UNPREDICTABLE"));
20652 if (et
.type
== NT_invtype
)
20655 if (check_simd_pred_availability (et
.type
== NT_float
, NEON_CHECK_ARCH8
20659 if (et
.type
== NT_float
)
20661 neon_three_same (neon_quad (rs
), 0, -1);
20662 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20663 inst
.instruction
|= 0xfc800800;
20664 inst
.instruction
|= (rot
== 270) << 24;
20665 inst
.instruction
|= (et
.size
== 32) << 20;
20669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20670 inst
.instruction
= 0xfe000f00;
20671 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20672 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20673 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20674 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20675 inst
.instruction
|= (rot
== 270) << 12;
20676 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20677 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20678 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20683 /* Dot Product instructions encoding support. */
20686 do_neon_dotproduct (int unsigned_p
)
20688 enum neon_shape rs
;
20689 unsigned scalar_oprd2
= 0;
20692 if (inst
.cond
!= COND_ALWAYS
)
20693 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20694 "is UNPREDICTABLE"));
20696 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20699 /* Dot Product instructions are in three-same D/Q register format or the third
20700 operand can be a scalar index register. */
20701 if (inst
.operands
[2].isscalar
)
20703 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20704 high8
= 0xfe000000;
20705 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20709 high8
= 0xfc000000;
20710 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20714 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20716 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20718 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20719 Product instruction, so we pass 0 as the "ubit" parameter. And the
20720 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20721 neon_three_same (neon_quad (rs
), 0, 32);
20723 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20724 different NEON three-same encoding. */
20725 inst
.instruction
&= 0x00ffffff;
20726 inst
.instruction
|= high8
;
20727 /* Encode 'U' bit which indicates signedness. */
20728 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20729 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20730 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20731 the instruction encoding. */
20732 if (inst
.operands
[2].isscalar
)
20734 inst
.instruction
&= 0xffffffd0;
20735 inst
.instruction
|= LOW4 (scalar_oprd2
);
20736 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20740 /* Dot Product instructions for signed integer. */
20743 do_neon_dotproduct_s (void)
20745 return do_neon_dotproduct (0);
20748 /* Dot Product instructions for unsigned integer. */
20751 do_neon_dotproduct_u (void)
20753 return do_neon_dotproduct (1);
20756 /* Crypto v1 instructions. */
20758 do_crypto_2op_1 (unsigned elttype
, int op
)
20760 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20762 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20768 NEON_ENCODE (INTEGER
, inst
);
20769 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20770 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20771 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20772 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20774 inst
.instruction
|= op
<< 6;
20777 inst
.instruction
|= 0xfc000000;
20779 inst
.instruction
|= 0xf0000000;
20783 do_crypto_3op_1 (int u
, int op
)
20785 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20787 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
20788 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
20793 NEON_ENCODE (INTEGER
, inst
);
20794 neon_three_same (1, u
, 8 << op
);
20800 do_crypto_2op_1 (N_8
, 0);
20806 do_crypto_2op_1 (N_8
, 1);
20812 do_crypto_2op_1 (N_8
, 2);
20818 do_crypto_2op_1 (N_8
, 3);
20824 do_crypto_3op_1 (0, 0);
20830 do_crypto_3op_1 (0, 1);
20836 do_crypto_3op_1 (0, 2);
20842 do_crypto_3op_1 (0, 3);
20848 do_crypto_3op_1 (1, 0);
20854 do_crypto_3op_1 (1, 1);
20858 do_sha256su1 (void)
20860 do_crypto_3op_1 (1, 2);
20866 do_crypto_2op_1 (N_32
, -1);
20872 do_crypto_2op_1 (N_32
, 0);
20876 do_sha256su0 (void)
20878 do_crypto_2op_1 (N_32
, 1);
20882 do_crc32_1 (unsigned int poly
, unsigned int sz
)
20884 unsigned int Rd
= inst
.operands
[0].reg
;
20885 unsigned int Rn
= inst
.operands
[1].reg
;
20886 unsigned int Rm
= inst
.operands
[2].reg
;
20888 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20889 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
20890 inst
.instruction
|= LOW4 (Rn
) << 16;
20891 inst
.instruction
|= LOW4 (Rm
);
20892 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
20893 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
20895 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
20896 as_warn (UNPRED_REG ("r15"));
20938 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20940 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
20941 do_vfp_sp_dp_cvt ();
20942 do_vfp_cond_or_thumb ();
20946 /* Overall per-instruction processing. */
20948 /* We need to be able to fix up arbitrary expressions in some statements.
20949 This is so that we can handle symbols that are an arbitrary distance from
20950 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20951 which returns part of an address in a form which will be valid for
20952 a data instruction. We do this by pushing the expression into a symbol
20953 in the expr_section, and creating a fix for that. */
20956 fix_new_arm (fragS
* frag
,
20970 /* Create an absolute valued symbol, so we have something to
20971 refer to in the object file. Unfortunately for us, gas's
20972 generic expression parsing will already have folded out
20973 any use of .set foo/.type foo %function that may have
20974 been used to set type information of the target location,
20975 that's being specified symbolically. We have to presume
20976 the user knows what they are doing. */
20980 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
20982 symbol
= symbol_find_or_make (name
);
20983 S_SET_SEGMENT (symbol
, absolute_section
);
20984 symbol_set_frag (symbol
, &zero_address_frag
);
20985 S_SET_VALUE (symbol
, exp
->X_add_number
);
20986 exp
->X_op
= O_symbol
;
20987 exp
->X_add_symbol
= symbol
;
20988 exp
->X_add_number
= 0;
20994 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
20995 (enum bfd_reloc_code_real
) reloc
);
20999 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21000 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21004 /* Mark whether the fix is to a THUMB instruction, or an ARM
21006 new_fix
->tc_fix_data
= thumb_mode
;
21009 /* Create a frg for an instruction requiring relaxation. */
21011 output_relax_insn (void)
21017 /* The size of the instruction is unknown, so tie the debug info to the
21018 start of the instruction. */
21019 dwarf2_emit_insn (0);
21021 switch (inst
.relocs
[0].exp
.X_op
)
21024 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21025 offset
= inst
.relocs
[0].exp
.X_add_number
;
21029 offset
= inst
.relocs
[0].exp
.X_add_number
;
21032 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21036 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21037 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21038 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21041 /* Write a 32-bit thumb instruction to buf. */
21043 put_thumb32_insn (char * buf
, unsigned long insn
)
21045 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21046 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21050 output_inst (const char * str
)
21056 as_bad ("%s -- `%s'", inst
.error
, str
);
21061 output_relax_insn ();
21064 if (inst
.size
== 0)
21067 to
= frag_more (inst
.size
);
21068 /* PR 9814: Record the thumb mode into the current frag so that we know
21069 what type of NOP padding to use, if necessary. We override any previous
21070 setting so that if the mode has changed then the NOPS that we use will
21071 match the encoding of the last instruction in the frag. */
21072 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21074 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21076 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21077 put_thumb32_insn (to
, inst
.instruction
);
21079 else if (inst
.size
> INSN_SIZE
)
21081 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21082 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21083 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21086 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21089 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21091 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21092 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21093 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21094 inst
.relocs
[r
].type
);
21097 dwarf2_emit_insn (inst
.size
);
21101 output_it_inst (int cond
, int mask
, char * to
)
21103 unsigned long instruction
= 0xbf00;
21106 instruction
|= mask
;
21107 instruction
|= cond
<< 4;
21111 to
= frag_more (2);
21113 dwarf2_emit_insn (2);
21117 md_number_to_chars (to
, instruction
, 2);
21122 /* Tag values used in struct asm_opcode's tag field. */
21125 OT_unconditional
, /* Instruction cannot be conditionalized.
21126 The ARM condition field is still 0xE. */
21127 OT_unconditionalF
, /* Instruction cannot be conditionalized
21128 and carries 0xF in its ARM condition field. */
21129 OT_csuffix
, /* Instruction takes a conditional suffix. */
21130 OT_csuffixF
, /* Some forms of the instruction take a scalar
21131 conditional suffix, others place 0xF where the
21132 condition field would be, others take a vector
21133 conditional suffix. */
21134 OT_cinfix3
, /* Instruction takes a conditional infix,
21135 beginning at character index 3. (In
21136 unified mode, it becomes a suffix.) */
21137 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21138 tsts, cmps, cmns, and teqs. */
21139 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21140 character index 3, even in unified mode. Used for
21141 legacy instructions where suffix and infix forms
21142 may be ambiguous. */
21143 OT_csuf_or_in3
, /* Instruction takes either a conditional
21144 suffix or an infix at character index 3. */
21145 OT_odd_infix_unc
, /* This is the unconditional variant of an
21146 instruction that takes a conditional infix
21147 at an unusual position. In unified mode,
21148 this variant will accept a suffix. */
21149 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21150 are the conditional variants of instructions that
21151 take conditional infixes in unusual positions.
21152 The infix appears at character index
21153 (tag - OT_odd_infix_0). These are not accepted
21154 in unified mode. */
21157 /* Subroutine of md_assemble, responsible for looking up the primary
21158 opcode from the mnemonic the user wrote. STR points to the
21159 beginning of the mnemonic.
21161 This is not simply a hash table lookup, because of conditional
21162 variants. Most instructions have conditional variants, which are
21163 expressed with a _conditional affix_ to the mnemonic. If we were
21164 to encode each conditional variant as a literal string in the opcode
21165 table, it would have approximately 20,000 entries.
21167 Most mnemonics take this affix as a suffix, and in unified syntax,
21168 'most' is upgraded to 'all'. However, in the divided syntax, some
21169 instructions take the affix as an infix, notably the s-variants of
21170 the arithmetic instructions. Of those instructions, all but six
21171 have the infix appear after the third character of the mnemonic.
21173 Accordingly, the algorithm for looking up primary opcodes given
21176 1. Look up the identifier in the opcode table.
21177 If we find a match, go to step U.
21179 2. Look up the last two characters of the identifier in the
21180 conditions table. If we find a match, look up the first N-2
21181 characters of the identifier in the opcode table. If we
21182 find a match, go to step CE.
21184 3. Look up the fourth and fifth characters of the identifier in
21185 the conditions table. If we find a match, extract those
21186 characters from the identifier, and look up the remaining
21187 characters in the opcode table. If we find a match, go
21192 U. Examine the tag field of the opcode structure, in case this is
21193 one of the six instructions with its conditional infix in an
21194 unusual place. If it is, the tag tells us where to find the
21195 infix; look it up in the conditions table and set inst.cond
21196 accordingly. Otherwise, this is an unconditional instruction.
21197 Again set inst.cond accordingly. Return the opcode structure.
21199 CE. Examine the tag field to make sure this is an instruction that
21200 should receive a conditional suffix. If it is not, fail.
21201 Otherwise, set inst.cond from the suffix we already looked up,
21202 and return the opcode structure.
21204 CM. Examine the tag field to make sure this is an instruction that
21205 should receive a conditional infix after the third character.
21206 If it is not, fail. Otherwise, undo the edits to the current
21207 line of input and proceed as for case CE. */
21209 static const struct asm_opcode
*
21210 opcode_lookup (char **str
)
21214 const struct asm_opcode
*opcode
;
21215 const struct asm_cond
*cond
;
21218 /* Scan up to the end of the mnemonic, which must end in white space,
21219 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21220 for (base
= end
= *str
; *end
!= '\0'; end
++)
21221 if (*end
== ' ' || *end
== '.')
21227 /* Handle a possible width suffix and/or Neon type suffix. */
21232 /* The .w and .n suffixes are only valid if the unified syntax is in
21234 if (unified_syntax
&& end
[1] == 'w')
21236 else if (unified_syntax
&& end
[1] == 'n')
21241 inst
.vectype
.elems
= 0;
21243 *str
= end
+ offset
;
21245 if (end
[offset
] == '.')
21247 /* See if we have a Neon type suffix (possible in either unified or
21248 non-unified ARM syntax mode). */
21249 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21252 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21258 /* Look for unaffixed or special-case affixed mnemonic. */
21259 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21264 if (opcode
->tag
< OT_odd_infix_0
)
21266 inst
.cond
= COND_ALWAYS
;
21270 if (warn_on_deprecated
&& unified_syntax
)
21271 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21272 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21273 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21276 inst
.cond
= cond
->value
;
21279 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21281 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21283 if (end
- base
< 2)
21286 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21287 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21289 /* If this opcode can not be vector predicated then don't accept it with a
21290 vector predication code. */
21291 if (opcode
&& !opcode
->mayBeVecPred
)
21294 if (!opcode
|| !cond
)
21296 /* Cannot have a conditional suffix on a mnemonic of less than two
21298 if (end
- base
< 3)
21301 /* Look for suffixed mnemonic. */
21303 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21304 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21308 if (opcode
&& cond
)
21311 switch (opcode
->tag
)
21313 case OT_cinfix3_legacy
:
21314 /* Ignore conditional suffixes matched on infix only mnemonics. */
21318 case OT_cinfix3_deprecated
:
21319 case OT_odd_infix_unc
:
21320 if (!unified_syntax
)
21322 /* Fall through. */
21326 case OT_csuf_or_in3
:
21327 inst
.cond
= cond
->value
;
21330 case OT_unconditional
:
21331 case OT_unconditionalF
:
21333 inst
.cond
= cond
->value
;
21336 /* Delayed diagnostic. */
21337 inst
.error
= BAD_COND
;
21338 inst
.cond
= COND_ALWAYS
;
21347 /* Cannot have a usual-position infix on a mnemonic of less than
21348 six characters (five would be a suffix). */
21349 if (end
- base
< 6)
21352 /* Look for infixed mnemonic in the usual position. */
21354 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21358 memcpy (save
, affix
, 2);
21359 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21360 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21362 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21363 memcpy (affix
, save
, 2);
21366 && (opcode
->tag
== OT_cinfix3
21367 || opcode
->tag
== OT_cinfix3_deprecated
21368 || opcode
->tag
== OT_csuf_or_in3
21369 || opcode
->tag
== OT_cinfix3_legacy
))
21372 if (warn_on_deprecated
&& unified_syntax
21373 && (opcode
->tag
== OT_cinfix3
21374 || opcode
->tag
== OT_cinfix3_deprecated
))
21375 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21377 inst
.cond
= cond
->value
;
21384 /* This function generates an initial IT instruction, leaving its block
21385 virtually open for the new instructions. Eventually,
21386 the mask will be updated by now_pred_add_mask () each time
21387 a new instruction needs to be included in the IT block.
21388 Finally, the block is closed with close_automatic_it_block ().
21389 The block closure can be requested either from md_assemble (),
21390 a tencode (), or due to a label hook. */
21393 new_automatic_it_block (int cond
)
21395 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21396 now_pred
.mask
= 0x18;
21397 now_pred
.cc
= cond
;
21398 now_pred
.block_length
= 1;
21399 mapping_state (MAP_THUMB
);
21400 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21401 now_pred
.warn_deprecated
= FALSE
;
21402 now_pred
.insn_cond
= TRUE
;
21405 /* Close an automatic IT block.
21406 See comments in new_automatic_it_block (). */
21409 close_automatic_it_block (void)
21411 now_pred
.mask
= 0x10;
21412 now_pred
.block_length
= 0;
21415 /* Update the mask of the current automatically-generated IT
21416 instruction. See comments in new_automatic_it_block (). */
21419 now_pred_add_mask (int cond
)
21421 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21422 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21423 | ((bitvalue) << (nbit)))
21424 const int resulting_bit
= (cond
& 1);
21426 now_pred
.mask
&= 0xf;
21427 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21429 (5 - now_pred
.block_length
));
21430 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21432 ((5 - now_pred
.block_length
) - 1));
21433 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21436 #undef SET_BIT_VALUE
21439 /* The IT blocks handling machinery is accessed through the these functions:
21440 it_fsm_pre_encode () from md_assemble ()
21441 set_pred_insn_type () optional, from the tencode functions
21442 set_pred_insn_type_last () ditto
21443 in_pred_block () ditto
21444 it_fsm_post_encode () from md_assemble ()
21445 force_automatic_it_block_close () from label handling functions
21448 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21449 initializing the IT insn type with a generic initial value depending
21450 on the inst.condition.
21451 2) During the tencode function, two things may happen:
21452 a) The tencode function overrides the IT insn type by
21453 calling either set_pred_insn_type (type) or
21454 set_pred_insn_type_last ().
21455 b) The tencode function queries the IT block state by
21456 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21458 Both set_pred_insn_type and in_pred_block run the internal FSM state
21459 handling function (handle_pred_state), because: a) setting the IT insn
21460 type may incur in an invalid state (exiting the function),
21461 and b) querying the state requires the FSM to be updated.
21462 Specifically we want to avoid creating an IT block for conditional
21463 branches, so it_fsm_pre_encode is actually a guess and we can't
21464 determine whether an IT block is required until the tencode () routine
21465 has decided what type of instruction this actually it.
21466 Because of this, if set_pred_insn_type and in_pred_block have to be
21467 used, set_pred_insn_type has to be called first.
21469 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21470 that determines the insn IT type depending on the inst.cond code.
21471 When a tencode () routine encodes an instruction that can be
21472 either outside an IT block, or, in the case of being inside, has to be
21473 the last one, set_pred_insn_type_last () will determine the proper
21474 IT instruction type based on the inst.cond code. Otherwise,
21475 set_pred_insn_type can be called for overriding that logic or
21476 for covering other cases.
21478 Calling handle_pred_state () may not transition the IT block state to
21479 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21480 still queried. Instead, if the FSM determines that the state should
21481 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21482 after the tencode () function: that's what it_fsm_post_encode () does.
21484 Since in_pred_block () calls the state handling function to get an
21485 updated state, an error may occur (due to invalid insns combination).
21486 In that case, inst.error is set.
21487 Therefore, inst.error has to be checked after the execution of
21488 the tencode () routine.
21490 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21491 any pending state change (if any) that didn't take place in
21492 handle_pred_state () as explained above. */
21495 it_fsm_pre_encode (void)
21497 if (inst
.cond
!= COND_ALWAYS
)
21498 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21500 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21502 now_pred
.state_handled
= 0;
21505 /* IT state FSM handling function. */
21506 /* MVE instructions and non-MVE instructions are handled differently because of
21507 the introduction of VPT blocks.
21508 Specifications say that any non-MVE instruction inside a VPT block is
21509 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21510 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21511 few exceptions we have MVE_UNPREDICABLE_INSN.
21512 The error messages provided depending on the different combinations possible
21513 are described in the cases below:
21514 For 'most' MVE instructions:
21515 1) In an IT block, with an IT code: syntax error
21516 2) In an IT block, with a VPT code: error: must be in a VPT block
21517 3) In an IT block, with no code: warning: UNPREDICTABLE
21518 4) In a VPT block, with an IT code: syntax error
21519 5) In a VPT block, with a VPT code: OK!
21520 6) In a VPT block, with no code: error: missing code
21521 7) Outside a pred block, with an IT code: error: syntax error
21522 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21523 9) Outside a pred block, with no code: OK!
21524 For non-MVE instructions:
21525 10) In an IT block, with an IT code: OK!
21526 11) In an IT block, with a VPT code: syntax error
21527 12) In an IT block, with no code: error: missing code
21528 13) In a VPT block, with an IT code: error: should be in an IT block
21529 14) In a VPT block, with a VPT code: syntax error
21530 15) In a VPT block, with no code: UNPREDICTABLE
21531 16) Outside a pred block, with an IT code: error: should be in an IT block
21532 17) Outside a pred block, with a VPT code: syntax error
21533 18) Outside a pred block, with no code: OK!
21538 handle_pred_state (void)
21540 now_pred
.state_handled
= 1;
21541 now_pred
.insn_cond
= FALSE
;
21543 switch (now_pred
.state
)
21545 case OUTSIDE_PRED_BLOCK
:
21546 switch (inst
.pred_insn_type
)
21548 case MVE_UNPREDICABLE_INSN
:
21549 case MVE_OUTSIDE_PRED_INSN
:
21550 if (inst
.cond
< COND_ALWAYS
)
21552 /* Case 7: Outside a pred block, with an IT code: error: syntax
21554 inst
.error
= BAD_SYNTAX
;
21557 /* Case 9: Outside a pred block, with no code: OK! */
21559 case OUTSIDE_PRED_INSN
:
21560 if (inst
.cond
> COND_ALWAYS
)
21562 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21564 inst
.error
= BAD_SYNTAX
;
21567 /* Case 18: Outside a pred block, with no code: OK! */
21570 case INSIDE_VPT_INSN
:
21571 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21573 inst
.error
= BAD_OUT_VPT
;
21576 case INSIDE_IT_INSN
:
21577 case INSIDE_IT_LAST_INSN
:
21578 if (inst
.cond
< COND_ALWAYS
)
21580 /* Case 16: Outside a pred block, with an IT code: error: should
21581 be in an IT block. */
21582 if (thumb_mode
== 0)
21585 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21586 as_tsktsk (_("Warning: conditional outside an IT block"\
21591 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21592 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21594 /* Automatically generate the IT instruction. */
21595 new_automatic_it_block (inst
.cond
);
21596 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21597 close_automatic_it_block ();
21601 inst
.error
= BAD_OUT_IT
;
21607 else if (inst
.cond
> COND_ALWAYS
)
21609 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21611 inst
.error
= BAD_SYNTAX
;
21616 case IF_INSIDE_IT_LAST_INSN
:
21617 case NEUTRAL_IT_INSN
:
21621 if (inst
.cond
!= COND_ALWAYS
)
21622 first_error (BAD_SYNTAX
);
21623 now_pred
.state
= MANUAL_PRED_BLOCK
;
21624 now_pred
.block_length
= 0;
21625 now_pred
.type
= VECTOR_PRED
;
21629 now_pred
.state
= MANUAL_PRED_BLOCK
;
21630 now_pred
.block_length
= 0;
21631 now_pred
.type
= SCALAR_PRED
;
21636 case AUTOMATIC_PRED_BLOCK
:
21637 /* Three things may happen now:
21638 a) We should increment current it block size;
21639 b) We should close current it block (closing insn or 4 insns);
21640 c) We should close current it block and start a new one (due
21641 to incompatible conditions or
21642 4 insns-length block reached). */
21644 switch (inst
.pred_insn_type
)
21646 case INSIDE_VPT_INSN
:
21648 case MVE_UNPREDICABLE_INSN
:
21649 case MVE_OUTSIDE_PRED_INSN
:
21651 case OUTSIDE_PRED_INSN
:
21652 /* The closure of the block shall happen immediately,
21653 so any in_pred_block () call reports the block as closed. */
21654 force_automatic_it_block_close ();
21657 case INSIDE_IT_INSN
:
21658 case INSIDE_IT_LAST_INSN
:
21659 case IF_INSIDE_IT_LAST_INSN
:
21660 now_pred
.block_length
++;
21662 if (now_pred
.block_length
> 4
21663 || !now_pred_compatible (inst
.cond
))
21665 force_automatic_it_block_close ();
21666 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21667 new_automatic_it_block (inst
.cond
);
21671 now_pred
.insn_cond
= TRUE
;
21672 now_pred_add_mask (inst
.cond
);
21675 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21676 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21677 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21678 close_automatic_it_block ();
21681 case NEUTRAL_IT_INSN
:
21682 now_pred
.block_length
++;
21683 now_pred
.insn_cond
= TRUE
;
21685 if (now_pred
.block_length
> 4)
21686 force_automatic_it_block_close ();
21688 now_pred_add_mask (now_pred
.cc
& 1);
21692 close_automatic_it_block ();
21693 now_pred
.state
= MANUAL_PRED_BLOCK
;
21698 case MANUAL_PRED_BLOCK
:
21701 if (now_pred
.type
== SCALAR_PRED
)
21703 /* Check conditional suffixes. */
21704 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21705 now_pred
.mask
<<= 1;
21706 now_pred
.mask
&= 0x1f;
21707 is_last
= (now_pred
.mask
== 0x10);
21711 now_pred
.cc
^= (now_pred
.mask
>> 4);
21712 cond
= now_pred
.cc
+ 0xf;
21713 now_pred
.mask
<<= 1;
21714 now_pred
.mask
&= 0x1f;
21715 is_last
= now_pred
.mask
== 0x10;
21717 now_pred
.insn_cond
= TRUE
;
21719 switch (inst
.pred_insn_type
)
21721 case OUTSIDE_PRED_INSN
:
21722 if (now_pred
.type
== SCALAR_PRED
)
21724 if (inst
.cond
== COND_ALWAYS
)
21726 /* Case 12: In an IT block, with no code: error: missing
21728 inst
.error
= BAD_NOT_IT
;
21731 else if (inst
.cond
> COND_ALWAYS
)
21733 /* Case 11: In an IT block, with a VPT code: syntax error.
21735 inst
.error
= BAD_SYNTAX
;
21738 else if (thumb_mode
)
21740 /* This is for some special cases where a non-MVE
21741 instruction is not allowed in an IT block, such as cbz,
21742 but are put into one with a condition code.
21743 You could argue this should be a syntax error, but we
21744 gave the 'not allowed in IT block' diagnostic in the
21745 past so we will keep doing so. */
21746 inst
.error
= BAD_NOT_IT
;
21753 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21754 as_tsktsk (MVE_NOT_VPT
);
21757 case MVE_OUTSIDE_PRED_INSN
:
21758 if (now_pred
.type
== SCALAR_PRED
)
21760 if (inst
.cond
== COND_ALWAYS
)
21762 /* Case 3: In an IT block, with no code: warning:
21764 as_tsktsk (MVE_NOT_IT
);
21767 else if (inst
.cond
< COND_ALWAYS
)
21769 /* Case 1: In an IT block, with an IT code: syntax error.
21771 inst
.error
= BAD_SYNTAX
;
21779 if (inst
.cond
< COND_ALWAYS
)
21781 /* Case 4: In a VPT block, with an IT code: syntax error.
21783 inst
.error
= BAD_SYNTAX
;
21786 else if (inst
.cond
== COND_ALWAYS
)
21788 /* Case 6: In a VPT block, with no code: error: missing
21790 inst
.error
= BAD_NOT_VPT
;
21798 case MVE_UNPREDICABLE_INSN
:
21799 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
21801 case INSIDE_IT_INSN
:
21802 if (inst
.cond
> COND_ALWAYS
)
21804 /* Case 11: In an IT block, with a VPT code: syntax error. */
21805 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21806 inst
.error
= BAD_SYNTAX
;
21809 else if (now_pred
.type
== SCALAR_PRED
)
21811 /* Case 10: In an IT block, with an IT code: OK! */
21812 if (cond
!= inst
.cond
)
21814 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
21821 /* Case 13: In a VPT block, with an IT code: error: should be
21823 inst
.error
= BAD_OUT_IT
;
21828 case INSIDE_VPT_INSN
:
21829 if (now_pred
.type
== SCALAR_PRED
)
21831 /* Case 2: In an IT block, with a VPT code: error: must be in a
21833 inst
.error
= BAD_OUT_VPT
;
21836 /* Case 5: In a VPT block, with a VPT code: OK! */
21837 else if (cond
!= inst
.cond
)
21839 inst
.error
= BAD_VPT_COND
;
21843 case INSIDE_IT_LAST_INSN
:
21844 case IF_INSIDE_IT_LAST_INSN
:
21845 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
21847 /* Case 4: In a VPT block, with an IT code: syntax error. */
21848 /* Case 11: In an IT block, with a VPT code: syntax error. */
21849 inst
.error
= BAD_SYNTAX
;
21852 else if (cond
!= inst
.cond
)
21854 inst
.error
= BAD_IT_COND
;
21859 inst
.error
= BAD_BRANCH
;
21864 case NEUTRAL_IT_INSN
:
21865 /* The BKPT instruction is unconditional even in a IT or VPT
21870 if (now_pred
.type
== SCALAR_PRED
)
21872 inst
.error
= BAD_IT_IT
;
21875 /* fall through. */
21877 if (inst
.cond
== COND_ALWAYS
)
21879 /* Executing a VPT/VPST instruction inside an IT block or a
21880 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21882 if (now_pred
.type
== SCALAR_PRED
)
21883 as_tsktsk (MVE_NOT_IT
);
21885 as_tsktsk (MVE_NOT_VPT
);
21890 /* VPT/VPST do not accept condition codes. */
21891 inst
.error
= BAD_SYNTAX
;
21902 struct depr_insn_mask
21904 unsigned long pattern
;
21905 unsigned long mask
;
21906 const char* description
;
21909 /* List of 16-bit instruction patterns deprecated in an IT block in
21911 static const struct depr_insn_mask depr_it_insns
[] = {
21912 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21913 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21914 { 0xa000, 0xb800, N_("ADR") },
21915 { 0x4800, 0xf800, N_("Literal loads") },
21916 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21917 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21918 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21919 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21920 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21925 it_fsm_post_encode (void)
21929 if (!now_pred
.state_handled
)
21930 handle_pred_state ();
21932 if (now_pred
.insn_cond
21933 && !now_pred
.warn_deprecated
21934 && warn_on_deprecated
21935 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
21936 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
21938 if (inst
.instruction
>= 0x10000)
21940 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21941 "performance deprecated in ARMv8-A and ARMv8-R"));
21942 now_pred
.warn_deprecated
= TRUE
;
21946 const struct depr_insn_mask
*p
= depr_it_insns
;
21948 while (p
->mask
!= 0)
21950 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
21952 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21953 "instructions of the following class are "
21954 "performance deprecated in ARMv8-A and "
21955 "ARMv8-R: %s"), p
->description
);
21956 now_pred
.warn_deprecated
= TRUE
;
21964 if (now_pred
.block_length
> 1)
21966 as_tsktsk (_("IT blocks containing more than one conditional "
21967 "instruction are performance deprecated in ARMv8-A and "
21969 now_pred
.warn_deprecated
= TRUE
;
21973 is_last
= (now_pred
.mask
== 0x10);
21976 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21982 force_automatic_it_block_close (void)
21984 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
21986 close_automatic_it_block ();
21987 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21993 in_pred_block (void)
21995 if (!now_pred
.state_handled
)
21996 handle_pred_state ();
21998 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22001 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22002 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22003 here, hence the "known" in the function name. */
22006 known_t32_only_insn (const struct asm_opcode
*opcode
)
22008 /* Original Thumb-1 wide instruction. */
22009 if (opcode
->tencode
== do_t_blx
22010 || opcode
->tencode
== do_t_branch23
22011 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22012 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22015 /* Wide-only instruction added to ARMv8-M Baseline. */
22016 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22017 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22018 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22019 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22025 /* Whether wide instruction variant can be used if available for a valid OPCODE
22029 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22031 if (known_t32_only_insn (opcode
))
22034 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22035 of variant T3 of B.W is checked in do_t_branch. */
22036 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22037 && opcode
->tencode
== do_t_branch
)
22040 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22041 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22042 && opcode
->tencode
== do_t_mov_cmp
22043 /* Make sure CMP instruction is not affected. */
22044 && opcode
->aencode
== do_mov
)
22047 /* Wide instruction variants of all instructions with narrow *and* wide
22048 variants become available with ARMv6t2. Other opcodes are either
22049 narrow-only or wide-only and are thus available if OPCODE is valid. */
22050 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22053 /* OPCODE with narrow only instruction variant or wide variant not
22059 md_assemble (char *str
)
22062 const struct asm_opcode
* opcode
;
22064 /* Align the previous label if needed. */
22065 if (last_label_seen
!= NULL
)
22067 symbol_set_frag (last_label_seen
, frag_now
);
22068 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22069 S_SET_SEGMENT (last_label_seen
, now_seg
);
22072 memset (&inst
, '\0', sizeof (inst
));
22074 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22075 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22077 opcode
= opcode_lookup (&p
);
22080 /* It wasn't an instruction, but it might be a register alias of
22081 the form alias .req reg, or a Neon .dn/.qn directive. */
22082 if (! create_register_alias (str
, p
)
22083 && ! create_neon_reg_alias (str
, p
))
22084 as_bad (_("bad instruction `%s'"), str
);
22089 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22090 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22092 /* The value which unconditional instructions should have in place of the
22093 condition field. */
22094 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22098 arm_feature_set variant
;
22100 variant
= cpu_variant
;
22101 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22102 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22103 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22104 /* Check that this instruction is supported for this CPU. */
22105 if (!opcode
->tvariant
22106 || (thumb_mode
== 1
22107 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22109 if (opcode
->tencode
== do_t_swi
)
22110 as_bad (_("SVC is not permitted on this architecture"));
22112 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22115 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22116 && opcode
->tencode
!= do_t_branch
)
22118 as_bad (_("Thumb does not support conditional execution"));
22122 /* Two things are addressed here:
22123 1) Implicit require narrow instructions on Thumb-1.
22124 This avoids relaxation accidentally introducing Thumb-2
22126 2) Reject wide instructions in non Thumb-2 cores.
22128 Only instructions with narrow and wide variants need to be handled
22129 but selecting all non wide-only instructions is easier. */
22130 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22131 && !t32_insn_ok (variant
, opcode
))
22133 if (inst
.size_req
== 0)
22135 else if (inst
.size_req
== 4)
22137 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22138 as_bad (_("selected processor does not support 32bit wide "
22139 "variant of instruction `%s'"), str
);
22141 as_bad (_("selected processor does not support `%s' in "
22142 "Thumb-2 mode"), str
);
22147 inst
.instruction
= opcode
->tvalue
;
22149 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22151 /* Prepare the pred_insn_type for those encodings that don't set
22153 it_fsm_pre_encode ();
22155 opcode
->tencode ();
22157 it_fsm_post_encode ();
22160 if (!(inst
.error
|| inst
.relax
))
22162 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22163 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22164 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22166 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22171 /* Something has gone badly wrong if we try to relax a fixed size
22173 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22175 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22176 *opcode
->tvariant
);
22177 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22178 set those bits when Thumb-2 32-bit instructions are seen. The impact
22179 of relaxable instructions will be considered later after we finish all
22181 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22182 variant
= arm_arch_none
;
22184 variant
= cpu_variant
;
22185 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22186 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22189 check_neon_suffixes
;
22193 mapping_state (MAP_THUMB
);
22196 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22200 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22201 is_bx
= (opcode
->aencode
== do_bx
);
22203 /* Check that this instruction is supported for this CPU. */
22204 if (!(is_bx
&& fix_v4bx
)
22205 && !(opcode
->avariant
&&
22206 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22208 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22213 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22217 inst
.instruction
= opcode
->avalue
;
22218 if (opcode
->tag
== OT_unconditionalF
)
22219 inst
.instruction
|= 0xFU
<< 28;
22221 inst
.instruction
|= inst
.cond
<< 28;
22222 inst
.size
= INSN_SIZE
;
22223 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22225 it_fsm_pre_encode ();
22226 opcode
->aencode ();
22227 it_fsm_post_encode ();
22229 /* Arm mode bx is marked as both v4T and v5 because it's still required
22230 on a hypothetical non-thumb v5 core. */
22232 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22234 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22235 *opcode
->avariant
);
22237 check_neon_suffixes
;
22241 mapping_state (MAP_ARM
);
22246 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22254 check_pred_blocks_finished (void)
22259 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22260 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22261 == MANUAL_PRED_BLOCK
)
22263 if (now_pred
.type
== SCALAR_PRED
)
22264 as_warn (_("section '%s' finished with an open IT block."),
22267 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22271 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22273 if (now_pred
.type
== SCALAR_PRED
)
22274 as_warn (_("file finished with an open IT block."));
22276 as_warn (_("file finished with an open VPT/VPST block."));
22281 /* Various frobbings of labels and their addresses. */
22284 arm_start_line_hook (void)
22286 last_label_seen
= NULL
;
22290 arm_frob_label (symbolS
* sym
)
22292 last_label_seen
= sym
;
22294 ARM_SET_THUMB (sym
, thumb_mode
);
22296 #if defined OBJ_COFF || defined OBJ_ELF
22297 ARM_SET_INTERWORK (sym
, support_interwork
);
22300 force_automatic_it_block_close ();
22302 /* Note - do not allow local symbols (.Lxxx) to be labelled
22303 as Thumb functions. This is because these labels, whilst
22304 they exist inside Thumb code, are not the entry points for
22305 possible ARM->Thumb calls. Also, these labels can be used
22306 as part of a computed goto or switch statement. eg gcc
22307 can generate code that looks like this:
22309 ldr r2, [pc, .Laaa]
22319 The first instruction loads the address of the jump table.
22320 The second instruction converts a table index into a byte offset.
22321 The third instruction gets the jump address out of the table.
22322 The fourth instruction performs the jump.
22324 If the address stored at .Laaa is that of a symbol which has the
22325 Thumb_Func bit set, then the linker will arrange for this address
22326 to have the bottom bit set, which in turn would mean that the
22327 address computation performed by the third instruction would end
22328 up with the bottom bit set. Since the ARM is capable of unaligned
22329 word loads, the instruction would then load the incorrect address
22330 out of the jump table, and chaos would ensue. */
22331 if (label_is_thumb_function_name
22332 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22333 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22335 /* When the address of a Thumb function is taken the bottom
22336 bit of that address should be set. This will allow
22337 interworking between Arm and Thumb functions to work
22340 THUMB_SET_FUNC (sym
, 1);
22342 label_is_thumb_function_name
= FALSE
;
22345 dwarf2_emit_label (sym
);
22349 arm_data_in_code (void)
22351 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22353 *input_line_pointer
= '/';
22354 input_line_pointer
+= 5;
22355 *input_line_pointer
= 0;
22363 arm_canonicalize_symbol_name (char * name
)
22367 if (thumb_mode
&& (len
= strlen (name
)) > 5
22368 && streq (name
+ len
- 5, "/data"))
22369 *(name
+ len
- 5) = 0;
22374 /* Table of all register names defined by default. The user can
22375 define additional names with .req. Note that all register names
22376 should appear in both upper and lowercase variants. Some registers
22377 also have mixed-case names. */
22379 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22380 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22381 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22382 #define REGSET(p,t) \
22383 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22384 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22385 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22386 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22387 #define REGSETH(p,t) \
22388 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22389 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22390 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22391 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22392 #define REGSET2(p,t) \
22393 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22394 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22395 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22396 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22397 #define SPLRBANK(base,bank,t) \
22398 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22399 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22400 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22401 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22402 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22403 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22405 static const struct reg_entry reg_names
[] =
22407 /* ARM integer registers. */
22408 REGSET(r
, RN
), REGSET(R
, RN
),
22410 /* ATPCS synonyms. */
22411 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22412 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22413 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22415 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22416 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22417 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22419 /* Well-known aliases. */
22420 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22421 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22423 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22424 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22426 /* Defining the new Zero register from ARMv8.1-M. */
22430 /* Coprocessor numbers. */
22431 REGSET(p
, CP
), REGSET(P
, CP
),
22433 /* Coprocessor register numbers. The "cr" variants are for backward
22435 REGSET(c
, CN
), REGSET(C
, CN
),
22436 REGSET(cr
, CN
), REGSET(CR
, CN
),
22438 /* ARM banked registers. */
22439 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22440 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22441 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22442 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22443 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22444 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22445 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22447 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22448 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22449 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22450 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22451 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22452 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22453 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22454 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22456 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22457 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22458 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22459 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22460 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22461 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22462 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22463 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22464 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22466 /* FPA registers. */
22467 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22468 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22470 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22471 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22473 /* VFP SP registers. */
22474 REGSET(s
,VFS
), REGSET(S
,VFS
),
22475 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22477 /* VFP DP Registers. */
22478 REGSET(d
,VFD
), REGSET(D
,VFD
),
22479 /* Extra Neon DP registers. */
22480 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22482 /* Neon QP registers. */
22483 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22485 /* VFP control registers. */
22486 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22487 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22488 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22489 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22490 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22491 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22492 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22494 /* Maverick DSP coprocessor registers. */
22495 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22496 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22498 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22499 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22500 REGDEF(dspsc
,0,DSPSC
),
22502 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22503 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22504 REGDEF(DSPSC
,0,DSPSC
),
22506 /* iWMMXt data registers - p0, c0-15. */
22507 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22509 /* iWMMXt control registers - p1, c0-3. */
22510 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22511 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22512 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22513 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22515 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22516 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22517 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22518 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22519 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22521 /* XScale accumulator registers. */
22522 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22528 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22529 within psr_required_here. */
22530 static const struct asm_psr psrs
[] =
22532 /* Backward compatibility notation. Note that "all" is no longer
22533 truly all possible PSR bits. */
22534 {"all", PSR_c
| PSR_f
},
22538 /* Individual flags. */
22544 /* Combinations of flags. */
22545 {"fs", PSR_f
| PSR_s
},
22546 {"fx", PSR_f
| PSR_x
},
22547 {"fc", PSR_f
| PSR_c
},
22548 {"sf", PSR_s
| PSR_f
},
22549 {"sx", PSR_s
| PSR_x
},
22550 {"sc", PSR_s
| PSR_c
},
22551 {"xf", PSR_x
| PSR_f
},
22552 {"xs", PSR_x
| PSR_s
},
22553 {"xc", PSR_x
| PSR_c
},
22554 {"cf", PSR_c
| PSR_f
},
22555 {"cs", PSR_c
| PSR_s
},
22556 {"cx", PSR_c
| PSR_x
},
22557 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22558 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22559 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22560 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22561 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22562 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22563 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22564 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22565 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22566 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22567 {"scf", PSR_s
| PSR_c
| PSR_f
},
22568 {"scx", PSR_s
| PSR_c
| PSR_x
},
22569 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22570 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22571 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22572 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22573 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22574 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22575 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22576 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22577 {"csf", PSR_c
| PSR_s
| PSR_f
},
22578 {"csx", PSR_c
| PSR_s
| PSR_x
},
22579 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22580 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22581 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22582 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22583 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22584 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22585 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22586 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22587 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22588 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22589 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22590 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22591 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22592 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22593 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22594 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22595 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22596 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22597 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22598 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22599 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22600 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22601 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22602 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22603 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22604 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22607 /* Table of V7M psr names. */
22608 static const struct asm_psr v7m_psrs
[] =
22610 {"apsr", 0x0 }, {"APSR", 0x0 },
22611 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22612 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22613 {"psr", 0x3 }, {"PSR", 0x3 },
22614 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22615 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22616 {"epsr", 0x6 }, {"EPSR", 0x6 },
22617 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22618 {"msp", 0x8 }, {"MSP", 0x8 },
22619 {"psp", 0x9 }, {"PSP", 0x9 },
22620 {"msplim", 0xa }, {"MSPLIM", 0xa },
22621 {"psplim", 0xb }, {"PSPLIM", 0xb },
22622 {"primask", 0x10}, {"PRIMASK", 0x10},
22623 {"basepri", 0x11}, {"BASEPRI", 0x11},
22624 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22625 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22626 {"control", 0x14}, {"CONTROL", 0x14},
22627 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22628 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22629 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22630 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22631 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22632 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22633 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22634 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22635 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22638 /* Table of all shift-in-operand names. */
22639 static const struct asm_shift_name shift_names
[] =
22641 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22642 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22643 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22644 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22645 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22646 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22647 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22650 /* Table of all explicit relocation names. */
22652 static struct reloc_entry reloc_names
[] =
22654 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22655 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22656 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22657 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22658 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22659 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22660 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22661 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22662 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22663 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22664 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22665 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22666 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22667 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22668 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22669 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22670 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22671 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22672 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22673 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22674 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22675 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22676 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22677 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22678 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22679 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22680 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22684 /* Table of all conditional affixes. */
22685 static const struct asm_cond conds
[] =
22689 {"cs", 0x2}, {"hs", 0x2},
22690 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22703 static const struct asm_cond vconds
[] =
22709 #define UL_BARRIER(L,U,CODE,FEAT) \
22710 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22711 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22713 static struct asm_barrier_opt barrier_opt_names
[] =
22715 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22716 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22717 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22718 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22719 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22720 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22721 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22722 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22723 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22724 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22725 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22726 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22727 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22728 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22729 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22730 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22735 /* Table of ARM-format instructions. */
22737 /* Macros for gluing together operand strings. N.B. In all cases
22738 other than OPS0, the trailing OP_stop comes from default
22739 zero-initialization of the unspecified elements of the array. */
22740 #define OPS0() { OP_stop, }
22741 #define OPS1(a) { OP_##a, }
22742 #define OPS2(a,b) { OP_##a,OP_##b, }
22743 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22744 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22745 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22746 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22748 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22749 This is useful when mixing operands for ARM and THUMB, i.e. using the
22750 MIX_ARM_THUMB_OPERANDS macro.
22751 In order to use these macros, prefix the number of operands with _
22753 #define OPS_1(a) { a, }
22754 #define OPS_2(a,b) { a,b, }
22755 #define OPS_3(a,b,c) { a,b,c, }
22756 #define OPS_4(a,b,c,d) { a,b,c,d, }
22757 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22758 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22760 /* These macros abstract out the exact format of the mnemonic table and
22761 save some repeated characters. */
22763 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22764 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22765 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22766 THUMB_VARIANT, do_##ae, do_##te, 0 }
22768 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22769 a T_MNEM_xyz enumerator. */
22770 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22771 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22772 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22773 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22775 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22776 infix after the third character. */
22777 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22778 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22779 THUMB_VARIANT, do_##ae, do_##te, 0 }
22780 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22781 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22782 THUMB_VARIANT, do_##ae, do_##te, 0 }
22783 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22784 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22785 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22786 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22787 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22788 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22789 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22790 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22792 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22793 field is still 0xE. Many of the Thumb variants can be executed
22794 conditionally, so this is checked separately. */
22795 #define TUE(mnem, op, top, nops, ops, ae, te) \
22796 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22797 THUMB_VARIANT, do_##ae, do_##te, 0 }
22799 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22800 Used by mnemonics that have very minimal differences in the encoding for
22801 ARM and Thumb variants and can be handled in a common function. */
22802 #define TUEc(mnem, op, top, nops, ops, en) \
22803 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22804 THUMB_VARIANT, do_##en, do_##en, 0 }
22806 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22807 condition code field. */
22808 #define TUF(mnem, op, top, nops, ops, ae, te) \
22809 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22810 THUMB_VARIANT, do_##ae, do_##te, 0 }
22812 /* ARM-only variants of all the above. */
22813 #define CE(mnem, op, nops, ops, ae) \
22814 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22816 #define C3(mnem, op, nops, ops, ae) \
22817 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22819 /* Thumb-only variants of TCE and TUE. */
22820 #define ToC(mnem, top, nops, ops, te) \
22821 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22824 #define ToU(mnem, top, nops, ops, te) \
22825 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22828 /* T_MNEM_xyz enumerator variants of ToC. */
22829 #define toC(mnem, top, nops, ops, te) \
22830 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22833 /* T_MNEM_xyz enumerator variants of ToU. */
22834 #define toU(mnem, top, nops, ops, te) \
22835 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22838 /* Legacy mnemonics that always have conditional infix after the third
22840 #define CL(mnem, op, nops, ops, ae) \
22841 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22842 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22844 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22845 #define cCE(mnem, op, nops, ops, ae) \
22846 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22848 /* mov instructions that are shared between coprocessor and MVE. */
22849 #define mcCE(mnem, op, nops, ops, ae) \
22850 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22852 /* Legacy coprocessor instructions where conditional infix and conditional
22853 suffix are ambiguous. For consistency this includes all FPA instructions,
22854 not just the potentially ambiguous ones. */
22855 #define cCL(mnem, op, nops, ops, ae) \
22856 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22857 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22859 /* Coprocessor, takes either a suffix or a position-3 infix
22860 (for an FPA corner case). */
22861 #define C3E(mnem, op, nops, ops, ae) \
22862 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22863 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22865 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22866 { m1 #m2 m3, OPS##nops ops, \
22867 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22868 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22870 #define CM(m1, m2, op, nops, ops, ae) \
22871 xCM_ (m1, , m2, op, nops, ops, ae), \
22872 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22873 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22874 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22875 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22876 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22877 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22878 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22879 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22880 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22881 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22882 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22883 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22884 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22885 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22886 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22887 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22888 xCM_ (m1, le, m2, op, nops, ops, ae), \
22889 xCM_ (m1, al, m2, op, nops, ops, ae)
22891 #define UE(mnem, op, nops, ops, ae) \
22892 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22894 #define UF(mnem, op, nops, ops, ae) \
22895 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22897 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22898 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22899 use the same encoding function for each. */
22900 #define NUF(mnem, op, nops, ops, enc) \
22901 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22902 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22904 /* Neon data processing, version which indirects through neon_enc_tab for
22905 the various overloaded versions of opcodes. */
22906 #define nUF(mnem, op, nops, ops, enc) \
22907 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22908 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22910 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22912 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22913 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22914 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22916 #define NCE(mnem, op, nops, ops, enc) \
22917 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22919 #define NCEF(mnem, op, nops, ops, enc) \
22920 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22922 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22923 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22924 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22925 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22927 #define nCE(mnem, op, nops, ops, enc) \
22928 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22930 #define nCEF(mnem, op, nops, ops, enc) \
22931 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22934 #define mCEF(mnem, op, nops, ops, enc) \
22935 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22936 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22939 /* nCEF but for MVE predicated instructions. */
22940 #define mnCEF(mnem, op, nops, ops, enc) \
22941 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22943 /* nCE but for MVE predicated instructions. */
22944 #define mnCE(mnem, op, nops, ops, enc) \
22945 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22947 /* NUF but for potentially MVE predicated instructions. */
22948 #define MNUF(mnem, op, nops, ops, enc) \
22949 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22950 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22952 /* nUF but for potentially MVE predicated instructions. */
22953 #define mnUF(mnem, op, nops, ops, enc) \
22954 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22955 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22957 /* ToC but for potentially MVE predicated instructions. */
22958 #define mToC(mnem, top, nops, ops, te) \
22959 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22962 /* NCE but for MVE predicated instructions. */
22963 #define MNCE(mnem, op, nops, ops, enc) \
22964 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22966 /* NCEF but for MVE predicated instructions. */
22967 #define MNCEF(mnem, op, nops, ops, enc) \
22968 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22971 static const struct asm_opcode insns
[] =
22973 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22974 #define THUMB_VARIANT & arm_ext_v4t
22975 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22976 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22977 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22978 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22979 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22980 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22981 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22982 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22983 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22984 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22985 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22986 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22987 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22988 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22989 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22990 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22992 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22993 for setting PSR flag bits. They are obsolete in V6 and do not
22994 have Thumb equivalents. */
22995 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22996 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22997 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
22998 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22999 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23000 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23001 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23002 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23003 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23005 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23006 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23007 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23008 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23010 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23011 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23012 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23014 OP_ADDRGLDR
),ldst
, t_ldst
),
23015 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23017 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23018 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23019 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23020 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23021 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23022 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23024 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23025 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23028 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23029 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23030 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23031 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23033 /* Thumb-compatibility pseudo ops. */
23034 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23035 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23036 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23037 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23038 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23039 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23040 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23041 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23042 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23043 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23044 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23045 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23047 /* These may simplify to neg. */
23048 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23049 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23051 #undef THUMB_VARIANT
23052 #define THUMB_VARIANT & arm_ext_os
23054 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23055 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23057 #undef THUMB_VARIANT
23058 #define THUMB_VARIANT & arm_ext_v6
23060 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23062 /* V1 instructions with no Thumb analogue prior to V6T2. */
23063 #undef THUMB_VARIANT
23064 #define THUMB_VARIANT & arm_ext_v6t2
23066 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23067 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23068 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23070 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23071 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23072 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23073 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23075 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23076 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23078 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23079 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23081 /* V1 instructions with no Thumb analogue at all. */
23082 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23083 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23085 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23086 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23087 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23088 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23089 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23090 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23091 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23092 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23095 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23096 #undef THUMB_VARIANT
23097 #define THUMB_VARIANT & arm_ext_v4t
23099 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23100 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23102 #undef THUMB_VARIANT
23103 #define THUMB_VARIANT & arm_ext_v6t2
23105 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23106 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23108 /* Generic coprocessor instructions. */
23109 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23110 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23111 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23112 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23113 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23114 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23115 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23118 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23120 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23121 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23124 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23125 #undef THUMB_VARIANT
23126 #define THUMB_VARIANT & arm_ext_msr
23128 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23129 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23132 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23133 #undef THUMB_VARIANT
23134 #define THUMB_VARIANT & arm_ext_v6t2
23136 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23137 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23138 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23139 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23140 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23141 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23142 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23143 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23146 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23147 #undef THUMB_VARIANT
23148 #define THUMB_VARIANT & arm_ext_v4t
23150 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23151 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23152 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23153 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23154 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23155 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23158 #define ARM_VARIANT & arm_ext_v4t_5
23160 /* ARM Architecture 4T. */
23161 /* Note: bx (and blx) are required on V5, even if the processor does
23162 not support Thumb. */
23163 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23166 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23167 #undef THUMB_VARIANT
23168 #define THUMB_VARIANT & arm_ext_v5t
23170 /* Note: blx has 2 variants; the .value coded here is for
23171 BLX(2). Only this variant has conditional execution. */
23172 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23173 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23175 #undef THUMB_VARIANT
23176 #define THUMB_VARIANT & arm_ext_v6t2
23178 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23179 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23180 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23181 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23182 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23183 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23184 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23185 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23188 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23189 #undef THUMB_VARIANT
23190 #define THUMB_VARIANT & arm_ext_v5exp
23192 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23193 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23194 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23195 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23197 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23198 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23200 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23201 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23202 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23203 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23205 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23206 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23207 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23208 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23210 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23211 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23213 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23214 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23215 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23216 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23219 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23220 #undef THUMB_VARIANT
23221 #define THUMB_VARIANT & arm_ext_v6t2
23223 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23224 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23226 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23227 ADDRGLDRS
), ldrd
, t_ldstd
),
23229 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23230 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23233 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23235 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23238 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23239 #undef THUMB_VARIANT
23240 #define THUMB_VARIANT & arm_ext_v6
23242 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23243 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23244 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23245 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23246 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23247 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23248 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23249 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23250 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23251 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23253 #undef THUMB_VARIANT
23254 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23256 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23257 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23259 #undef THUMB_VARIANT
23260 #define THUMB_VARIANT & arm_ext_v6t2
23262 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23263 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23265 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23266 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23268 /* ARM V6 not included in V7M. */
23269 #undef THUMB_VARIANT
23270 #define THUMB_VARIANT & arm_ext_v6_notm
23271 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23272 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23273 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23274 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23275 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23276 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23277 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23278 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23279 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23280 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23281 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23282 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23283 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23284 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23285 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23286 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23287 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23288 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23289 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23291 /* ARM V6 not included in V7M (eg. integer SIMD). */
23292 #undef THUMB_VARIANT
23293 #define THUMB_VARIANT & arm_ext_v6_dsp
23294 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23295 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23296 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23297 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23298 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23299 /* Old name for QASX. */
23300 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23301 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23302 /* Old name for QSAX. */
23303 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23304 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23305 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23306 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23307 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23308 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23309 /* Old name for SASX. */
23310 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23311 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23312 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23313 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23314 /* Old name for SHASX. */
23315 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23316 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23317 /* Old name for SHSAX. */
23318 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23319 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23320 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23321 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23322 /* Old name for SSAX. */
23323 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23324 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23325 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23326 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23327 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23328 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23329 /* Old name for UASX. */
23330 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23331 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23332 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23333 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23334 /* Old name for UHASX. */
23335 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23336 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23337 /* Old name for UHSAX. */
23338 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23339 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23340 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23341 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23342 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23343 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23344 /* Old name for UQASX. */
23345 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23346 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23347 /* Old name for UQSAX. */
23348 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23349 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23350 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23351 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23352 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23353 /* Old name for USAX. */
23354 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23355 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23356 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23357 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23358 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23359 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23360 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23361 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23362 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23363 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23364 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23365 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23366 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23367 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23368 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23369 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23370 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23371 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23372 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23373 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23374 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23375 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23376 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23377 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23378 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23379 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23380 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23381 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23382 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23383 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23384 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23385 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23386 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23387 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23390 #define ARM_VARIANT & arm_ext_v6k_v6t2
23391 #undef THUMB_VARIANT
23392 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23394 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23395 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23396 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23397 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23399 #undef THUMB_VARIANT
23400 #define THUMB_VARIANT & arm_ext_v6_notm
23401 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23403 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23404 RRnpcb
), strexd
, t_strexd
),
23406 #undef THUMB_VARIANT
23407 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23408 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23410 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23412 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23414 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23416 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23419 #define ARM_VARIANT & arm_ext_sec
23420 #undef THUMB_VARIANT
23421 #define THUMB_VARIANT & arm_ext_sec
23423 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23426 #define ARM_VARIANT & arm_ext_virt
23427 #undef THUMB_VARIANT
23428 #define THUMB_VARIANT & arm_ext_virt
23430 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23431 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23434 #define ARM_VARIANT & arm_ext_pan
23435 #undef THUMB_VARIANT
23436 #define THUMB_VARIANT & arm_ext_pan
23438 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23441 #define ARM_VARIANT & arm_ext_v6t2
23442 #undef THUMB_VARIANT
23443 #define THUMB_VARIANT & arm_ext_v6t2
23445 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23446 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23447 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23448 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23450 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23451 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23453 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23454 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23455 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23456 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23459 #define ARM_VARIANT & arm_ext_v3
23460 #undef THUMB_VARIANT
23461 #define THUMB_VARIANT & arm_ext_v6t2
23463 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23464 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23465 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23468 #define ARM_VARIANT & arm_ext_v6t2
23469 #undef THUMB_VARIANT
23470 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23471 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23472 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23474 /* Thumb-only instructions. */
23476 #define ARM_VARIANT NULL
23477 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23478 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23480 /* ARM does not really have an IT instruction, so always allow it.
23481 The opcode is copied from Thumb in order to allow warnings in
23482 -mimplicit-it=[never | arm] modes. */
23484 #define ARM_VARIANT & arm_ext_v1
23485 #undef THUMB_VARIANT
23486 #define THUMB_VARIANT & arm_ext_v6t2
23488 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23489 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23490 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23491 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23492 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23493 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23494 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23495 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23496 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23497 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23498 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23499 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23500 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23501 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23502 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23503 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23504 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23505 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23507 /* Thumb2 only instructions. */
23509 #define ARM_VARIANT NULL
23511 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23512 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23513 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23514 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23515 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23516 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23518 /* Hardware division instructions. */
23520 #define ARM_VARIANT & arm_ext_adiv
23521 #undef THUMB_VARIANT
23522 #define THUMB_VARIANT & arm_ext_div
23524 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23525 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23527 /* ARM V6M/V7 instructions. */
23529 #define ARM_VARIANT & arm_ext_barrier
23530 #undef THUMB_VARIANT
23531 #define THUMB_VARIANT & arm_ext_barrier
23533 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23534 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23535 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23537 /* ARM V7 instructions. */
23539 #define ARM_VARIANT & arm_ext_v7
23540 #undef THUMB_VARIANT
23541 #define THUMB_VARIANT & arm_ext_v7
23543 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23544 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23547 #define ARM_VARIANT & arm_ext_mp
23548 #undef THUMB_VARIANT
23549 #define THUMB_VARIANT & arm_ext_mp
23551 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23553 /* AArchv8 instructions. */
23555 #define ARM_VARIANT & arm_ext_v8
23557 /* Instructions shared between armv8-a and armv8-m. */
23558 #undef THUMB_VARIANT
23559 #define THUMB_VARIANT & arm_ext_atomics
23561 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23562 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23563 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23564 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23565 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23566 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23567 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23568 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23569 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23570 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23572 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23574 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23576 #undef THUMB_VARIANT
23577 #define THUMB_VARIANT & arm_ext_v8
23579 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23580 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23582 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23585 /* Defined in V8 but is in undefined encoding space for earlier
23586 architectures. However earlier architectures are required to treat
23587 this instuction as a semihosting trap as well. Hence while not explicitly
23588 defined as such, it is in fact correct to define the instruction for all
23590 #undef THUMB_VARIANT
23591 #define THUMB_VARIANT & arm_ext_v1
23593 #define ARM_VARIANT & arm_ext_v1
23594 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23596 /* ARMv8 T32 only. */
23598 #define ARM_VARIANT NULL
23599 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23600 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23601 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23603 /* FP for ARMv8. */
23605 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23606 #undef THUMB_VARIANT
23607 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23609 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23610 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23611 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23612 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23613 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23614 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23615 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23616 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23617 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23618 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23619 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23621 /* Crypto v1 extensions. */
23623 #define ARM_VARIANT & fpu_crypto_ext_armv8
23624 #undef THUMB_VARIANT
23625 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23627 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23628 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23629 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23630 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23631 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23632 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23633 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23634 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23635 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23636 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23637 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23638 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23639 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23640 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23643 #define ARM_VARIANT & crc_ext_armv8
23644 #undef THUMB_VARIANT
23645 #define THUMB_VARIANT & crc_ext_armv8
23646 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23647 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23648 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23649 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23650 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23651 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23653 /* ARMv8.2 RAS extension. */
23655 #define ARM_VARIANT & arm_ext_ras
23656 #undef THUMB_VARIANT
23657 #define THUMB_VARIANT & arm_ext_ras
23658 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23661 #define ARM_VARIANT & arm_ext_v8_3
23662 #undef THUMB_VARIANT
23663 #define THUMB_VARIANT & arm_ext_v8_3
23664 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23667 #define ARM_VARIANT & fpu_neon_ext_dotprod
23668 #undef THUMB_VARIANT
23669 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23670 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23671 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23674 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23675 #undef THUMB_VARIANT
23676 #define THUMB_VARIANT NULL
23678 cCE("wfs", e200110
, 1, (RR
), rd
),
23679 cCE("rfs", e300110
, 1, (RR
), rd
),
23680 cCE("wfc", e400110
, 1, (RR
), rd
),
23681 cCE("rfc", e500110
, 1, (RR
), rd
),
23683 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23684 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23685 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23686 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23688 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23689 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23690 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23691 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23693 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23694 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23695 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23696 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23697 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23698 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23699 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23700 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23701 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23702 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23703 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23704 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23706 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23707 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23708 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23709 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23710 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23711 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23712 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23713 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23714 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23715 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23716 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23717 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23719 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23720 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23721 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23722 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23723 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23724 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23725 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23726 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23727 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23728 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23729 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23730 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23732 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23733 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23734 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23735 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23736 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23737 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23738 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23739 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23740 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23741 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23742 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23743 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23745 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23746 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23747 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23748 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23749 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23750 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23751 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23752 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23753 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23754 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23755 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23756 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23758 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23759 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23760 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23761 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23762 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23763 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23764 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23765 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23766 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23767 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23768 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23769 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23771 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23772 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23773 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23774 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23775 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23776 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23777 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23778 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23779 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23780 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23781 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
23782 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
23784 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
23785 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
23786 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
23787 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
23788 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
23789 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
23790 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
23791 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
23792 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
23793 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
23794 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
23795 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
23797 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
23798 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
23799 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
23800 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
23801 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
23802 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
23803 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
23804 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
23805 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
23806 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
23807 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
23808 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
23810 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
23811 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
23812 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
23813 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
23814 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
23815 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
23816 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
23817 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
23818 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
23819 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
23820 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
23821 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
23823 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
23824 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
23825 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
23826 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
23827 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
23828 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
23829 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
23830 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
23831 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
23832 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
23833 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
23834 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
23836 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
23837 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
23838 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
23839 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
23840 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
23841 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
23842 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
23843 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
23844 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
23845 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
23846 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
23847 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
23849 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
23850 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
23851 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
23852 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
23853 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
23854 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
23855 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
23856 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
23857 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
23858 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
23859 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
23860 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
23862 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
23863 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
23864 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
23865 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
23866 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
23867 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
23868 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
23869 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
23870 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
23871 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
23872 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
23873 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
23875 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
23876 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
23877 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
23878 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
23879 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
23880 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
23881 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
23882 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
23883 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
23884 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
23885 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
23886 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
23888 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
23889 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
23890 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
23891 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
23892 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
23893 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
23894 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
23895 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
23896 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
23897 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
23898 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
23899 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
23901 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23902 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23903 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23904 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23905 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23906 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23907 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23908 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23909 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23910 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23911 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23912 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23914 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23915 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23916 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23917 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23918 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23919 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23920 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23921 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23922 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23923 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23924 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23925 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23927 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23928 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23929 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23930 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23931 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23932 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23933 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23934 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23935 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23936 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23937 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23938 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23940 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23941 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23942 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23943 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23944 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23945 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23946 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23947 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23948 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23949 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23950 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23951 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23953 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23954 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23955 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23956 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23957 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23958 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23959 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23960 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23961 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23962 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23963 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23964 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23966 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23967 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23968 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23969 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23970 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23971 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23972 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23973 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23974 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23975 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23976 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23977 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23979 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23980 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23981 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23982 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23983 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23984 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23985 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23986 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23987 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23988 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23989 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23990 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23992 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23993 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23994 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23995 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23996 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23997 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23998 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23999 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24000 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24001 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24002 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24003 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24005 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24006 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24007 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24008 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24009 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24010 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24011 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24012 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24013 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24014 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24015 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24016 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24018 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24019 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24020 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24021 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24022 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24023 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24024 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24025 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24026 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24027 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24028 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24029 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24031 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24032 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24033 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24034 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24035 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24036 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24037 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24038 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24039 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24040 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24041 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24042 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24044 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24045 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24046 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24047 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24048 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24049 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24050 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24051 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24052 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24053 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24054 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24055 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24057 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24058 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24059 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24060 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24061 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24062 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24063 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24064 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24065 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24066 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24067 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24068 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24070 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24071 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24072 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24073 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24075 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24076 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24077 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24078 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24079 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24080 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24081 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24082 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24083 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24084 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24085 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24086 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24088 /* The implementation of the FIX instruction is broken on some
24089 assemblers, in that it accepts a precision specifier as well as a
24090 rounding specifier, despite the fact that this is meaningless.
24091 To be more compatible, we accept it as well, though of course it
24092 does not set any bits. */
24093 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24094 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24095 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24096 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24097 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24098 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24099 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24100 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24101 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24102 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24103 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24104 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24105 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24107 /* Instructions that were new with the real FPA, call them V2. */
24109 #define ARM_VARIANT & fpu_fpa_ext_v2
24111 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24112 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24113 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24114 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24115 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24116 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24119 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24121 /* Moves and type conversions. */
24122 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24123 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24124 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24125 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24126 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24127 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24128 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24129 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24130 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24131 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24132 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24134 /* Memory operations. */
24135 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24136 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24137 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24138 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24139 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24140 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24141 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24142 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24143 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24144 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24145 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24146 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24147 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24148 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24149 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24150 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24151 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24152 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24154 /* Monadic operations. */
24155 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24156 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24157 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24159 /* Dyadic operations. */
24160 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24161 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24162 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24163 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24164 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24165 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24166 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24167 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24168 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24171 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24172 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24173 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24174 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24176 /* Double precision load/store are still present on single precision
24177 implementations. */
24178 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24179 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24180 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24181 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24182 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24183 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24184 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24185 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24186 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24187 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24190 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24192 /* Moves and type conversions. */
24193 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24194 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24195 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24196 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24197 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24198 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24199 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24200 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24201 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24202 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24203 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24204 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24206 /* Monadic operations. */
24207 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24208 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24209 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24211 /* Dyadic operations. */
24212 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24213 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24214 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24215 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24216 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24217 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24218 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24219 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24220 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24223 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24224 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24225 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24226 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24228 /* Instructions which may belong to either the Neon or VFP instruction sets.
24229 Individual encoder functions perform additional architecture checks. */
24231 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24232 #undef THUMB_VARIANT
24233 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24235 /* These mnemonics are unique to VFP. */
24236 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24237 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24238 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24239 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24240 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24241 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24242 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24243 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24245 /* Mnemonics shared by Neon and VFP. */
24246 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24248 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24249 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24250 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24251 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24252 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24253 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24255 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24256 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24257 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24258 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24261 /* NOTE: All VMOV encoding is special-cased! */
24262 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24264 #undef THUMB_VARIANT
24265 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24266 by different feature bits. Since we are setting the Thumb guard, we can
24267 require Thumb-1 which makes it a nop guard and set the right feature bit in
24268 do_vldr_vstr (). */
24269 #define THUMB_VARIANT & arm_ext_v4t
24270 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24271 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24274 #define ARM_VARIANT & arm_ext_fp16
24275 #undef THUMB_VARIANT
24276 #define THUMB_VARIANT & arm_ext_fp16
24277 /* New instructions added from v8.2, allowing the extraction and insertion of
24278 the upper 16 bits of a 32-bit vector register. */
24279 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24280 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24282 /* New backported fma/fms instructions optional in v8.2. */
24283 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24284 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24286 #undef THUMB_VARIANT
24287 #define THUMB_VARIANT & fpu_neon_ext_v1
24289 #define ARM_VARIANT & fpu_neon_ext_v1
24291 /* Data processing with three registers of the same length. */
24292 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24293 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24294 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24295 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24296 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24297 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24298 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24299 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24300 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24301 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24302 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24303 /* If not immediate, fall back to neon_dyadic_i64_su.
24304 shl_imm should accept I8 I16 I32 I64,
24305 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24306 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
24307 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
24308 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
24309 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
24310 /* Logic ops, types optional & ignored. */
24311 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24312 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24313 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24314 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24315 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24316 /* Bitfield ops, untyped. */
24317 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24318 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24319 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24320 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24321 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24322 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24323 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24324 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24325 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24326 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24327 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24328 back to neon_dyadic_if_su. */
24329 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24330 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24331 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24332 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24333 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24334 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24335 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24336 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24337 /* Comparison. Type I8 I16 I32 F32. */
24338 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24339 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24340 /* As above, D registers only. */
24341 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24342 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24343 /* Int and float variants, signedness unimportant. */
24344 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24345 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24346 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24347 /* Add/sub take types I8 I16 I32 I64 F32. */
24348 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24349 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24350 /* vtst takes sizes 8, 16, 32. */
24351 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24352 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24353 /* VMUL takes I8 I16 I32 F32 P8. */
24354 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24355 /* VQD{R}MULH takes S16 S32. */
24356 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24357 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24358 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24359 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24360 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24361 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24362 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24363 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24364 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24365 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24366 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24367 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24368 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24369 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24370 /* ARM v8.1 extension. */
24371 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24372 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24373 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24375 /* Two address, int/float. Types S8 S16 S32 F32. */
24376 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24377 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24379 /* Data processing with two registers and a shift amount. */
24380 /* Right shifts, and variants with rounding.
24381 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24382 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24383 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24384 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24385 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24386 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24387 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24388 /* Shift and insert. Sizes accepted 8 16 32 64. */
24389 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24390 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24391 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24392 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
24393 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24394 /* Right shift immediate, saturating & narrowing, with rounding variants.
24395 Types accepted S16 S32 S64 U16 U32 U64. */
24396 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24397 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24398 /* As above, unsigned. Types accepted S16 S32 S64. */
24399 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24400 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24401 /* Right shift narrowing. Types accepted I16 I32 I64. */
24402 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24403 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24404 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24405 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24406 /* CVT with optional immediate for fixed-point variant. */
24407 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24409 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24411 /* Data processing, three registers of different lengths. */
24412 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24413 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24414 /* If not scalar, fall back to neon_dyadic_long.
24415 Vector types as above, scalar types S16 S32 U16 U32. */
24416 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24417 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24418 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24419 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24420 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24421 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24422 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24423 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24424 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24425 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24426 /* Saturating doubling multiplies. Types S16 S32. */
24427 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24428 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24429 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24430 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24431 S16 S32 U16 U32. */
24432 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24434 /* Extract. Size 8. */
24435 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24436 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24438 /* Two registers, miscellaneous. */
24439 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24440 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24441 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24442 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24443 /* Vector replicate. Sizes 8 16 32. */
24444 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24445 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24446 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24447 /* VMOVN. Types I16 I32 I64. */
24448 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24449 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24450 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24451 /* VQMOVUN. Types S16 S32 S64. */
24452 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24453 /* VZIP / VUZP. Sizes 8 16 32. */
24454 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24455 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24456 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24457 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24458 /* VQABS / VQNEG. Types S8 S16 S32. */
24459 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24460 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24461 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24462 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24463 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24464 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24465 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24466 /* Reciprocal estimates. Types U32 F16 F32. */
24467 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24468 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24469 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24470 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24471 /* VCLS. Types S8 S16 S32. */
24472 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24473 /* VCLZ. Types I8 I16 I32. */
24474 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24475 /* VCNT. Size 8. */
24476 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24477 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24478 /* Two address, untyped. */
24479 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24480 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24481 /* VTRN. Sizes 8 16 32. */
24482 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24483 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24485 /* Table lookup. Size 8. */
24486 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24487 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24489 #undef THUMB_VARIANT
24490 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24492 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24494 /* Neon element/structure load/store. */
24495 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24496 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24497 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24498 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24499 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24500 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24501 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24502 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24504 #undef THUMB_VARIANT
24505 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24507 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24508 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24509 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24510 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24511 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24512 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24513 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24514 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24515 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24516 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24518 #undef THUMB_VARIANT
24519 #define THUMB_VARIANT & fpu_vfp_ext_v3
24521 #define ARM_VARIANT & fpu_vfp_ext_v3
24523 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24524 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24525 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24526 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24527 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24528 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24529 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24530 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24531 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24534 #define ARM_VARIANT & fpu_vfp_ext_fma
24535 #undef THUMB_VARIANT
24536 #define THUMB_VARIANT & fpu_vfp_ext_fma
24537 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24538 VFP FMA variant; NEON and VFP FMA always includes the NEON
24539 FMA instructions. */
24540 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24541 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24543 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24544 the v form should always be used. */
24545 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24546 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24547 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24548 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24549 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24550 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24552 #undef THUMB_VARIANT
24554 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24556 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24557 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24558 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24559 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24560 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24561 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24562 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24563 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24566 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24568 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24569 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24570 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24571 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24572 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24573 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24574 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24575 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24576 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24577 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24578 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24579 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24580 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24581 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24582 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24583 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24584 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24585 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24586 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24587 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24588 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24589 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24590 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24591 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24592 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24593 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24594 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24595 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24596 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24597 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24598 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24599 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24600 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24601 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24602 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24603 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24604 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24605 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24606 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24607 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24608 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24609 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24610 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24611 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24612 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24613 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24614 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24615 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24616 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24617 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24618 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24619 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24620 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24621 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24622 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24623 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24624 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24625 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24626 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24627 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24628 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24629 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24630 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24631 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24632 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24633 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24634 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24635 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24636 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24637 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24638 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24639 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24640 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24641 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24642 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24643 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24644 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24645 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24646 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24647 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24648 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24649 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24650 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24651 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24652 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24653 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24654 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24655 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24656 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24657 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24658 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24659 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24660 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24661 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24662 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24663 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24664 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24665 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24666 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24667 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24668 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24669 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24670 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24671 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24672 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24673 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24674 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24675 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24676 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24677 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24678 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24679 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24680 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24681 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24682 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24683 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24684 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24685 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24686 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24687 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24688 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24689 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24690 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24691 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24692 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24693 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24694 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24695 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24696 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24697 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24698 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24699 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24700 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24701 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24702 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24703 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24704 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24705 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24706 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24707 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24708 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24709 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24710 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24711 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24712 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24713 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24714 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24715 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24716 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24717 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24718 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24719 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24720 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24721 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24722 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24723 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24724 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24725 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24726 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24727 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24728 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24729 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24732 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24734 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24735 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24736 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24737 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24738 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24739 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24740 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24741 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24742 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24743 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24744 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24745 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24746 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24747 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24748 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24749 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24750 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24751 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24752 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24753 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24754 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24755 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24756 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24757 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24758 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24759 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24760 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24761 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24762 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24763 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24764 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24765 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24766 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24767 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24768 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24769 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24770 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24771 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24772 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24773 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24774 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24775 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24776 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24777 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24778 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24779 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24780 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24781 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24782 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24783 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24784 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24785 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24786 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24787 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24788 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24789 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24790 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24793 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24795 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24796 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24797 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24798 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24799 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24800 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24801 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24802 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24803 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
24804 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
24805 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
24806 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
24807 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
24808 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
24809 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
24810 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
24811 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
24812 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
24813 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
24814 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
24815 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
24816 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
24817 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
24818 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
24819 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
24820 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
24821 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
24822 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
24823 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
24824 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
24825 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
24826 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
24827 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
24828 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
24829 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
24830 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
24831 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
24832 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
24833 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
24834 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
24835 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
24836 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
24837 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
24838 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
24839 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
24840 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
24841 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
24842 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
24843 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
24844 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
24845 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
24846 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
24847 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
24848 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
24849 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24850 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24851 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24852 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24853 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24854 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24855 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
24856 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
24857 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
24858 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
24859 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24860 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24861 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24862 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24863 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24864 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24865 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24866 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24867 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24868 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24869 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24870 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24872 /* ARMv8.5-A instructions. */
24874 #define ARM_VARIANT & arm_ext_sb
24875 #undef THUMB_VARIANT
24876 #define THUMB_VARIANT & arm_ext_sb
24877 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
24880 #define ARM_VARIANT & arm_ext_predres
24881 #undef THUMB_VARIANT
24882 #define THUMB_VARIANT & arm_ext_predres
24883 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
24884 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
24885 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
24887 /* ARMv8-M instructions. */
24889 #define ARM_VARIANT NULL
24890 #undef THUMB_VARIANT
24891 #define THUMB_VARIANT & arm_ext_v8m
24892 ToU("sg", e97fe97f
, 0, (), noargs
),
24893 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
24894 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
24895 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
24896 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
24897 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
24898 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
24900 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24901 instructions behave as nop if no VFP is present. */
24902 #undef THUMB_VARIANT
24903 #define THUMB_VARIANT & arm_ext_v8m_main
24904 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
24905 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
24907 /* Armv8.1-M Mainline instructions. */
24908 #undef THUMB_VARIANT
24909 #define THUMB_VARIANT & arm_ext_v8_1m_main
24910 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
24911 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
24912 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24913 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
24914 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24916 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
24917 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
24918 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
24920 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
24921 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
24923 #undef THUMB_VARIANT
24924 #define THUMB_VARIANT & mve_ext
24926 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24927 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24928 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24929 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24930 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24931 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24932 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24933 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24934 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24935 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24936 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24937 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24938 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24939 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24940 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24942 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
24943 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
24944 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
24945 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
24946 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
24947 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
24948 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
24949 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
24950 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
24951 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
24952 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
24953 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
24954 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
24955 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
24956 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
24958 /* MVE and MVE FP only. */
24959 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
24960 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24961 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24962 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24963 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24964 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
24965 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
24966 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24967 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24968 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24969 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24970 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24971 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24972 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24973 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24974 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24975 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24977 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24978 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24979 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24980 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24981 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24982 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24983 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24984 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24985 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24986 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24987 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24988 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24989 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24990 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24991 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24992 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24993 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24994 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24995 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24996 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24998 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
24999 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25000 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25001 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25002 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25003 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25004 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25005 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25006 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25007 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25008 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25009 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25010 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25011 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25012 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25013 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25014 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25016 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25017 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25018 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25019 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25020 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25021 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25022 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25023 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25024 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25025 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25026 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25027 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25028 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25029 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25030 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25031 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25032 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25033 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25034 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25035 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25037 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25038 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25039 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25040 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25041 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25043 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25044 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25045 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25046 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25047 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25048 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25049 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25050 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25051 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25052 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25053 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25054 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25055 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25056 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25057 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25058 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25059 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25061 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25062 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25063 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25064 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25065 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25066 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25067 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25068 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25069 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25070 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25071 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25072 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25074 #undef THUMB_VARIANT
25075 #define THUMB_VARIANT & mve_fp_ext
25076 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25077 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25078 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25079 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25080 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25081 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25082 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25083 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25086 #define ARM_VARIANT & fpu_vfp_ext_v1
25087 #undef THUMB_VARIANT
25088 #define THUMB_VARIANT & arm_ext_v6t2
25089 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25090 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25092 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25095 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25097 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25098 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25099 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25100 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25102 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25103 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25104 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25106 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25107 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25109 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25110 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25112 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25113 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25116 #define ARM_VARIANT & fpu_vfp_ext_v2
25118 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25119 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25120 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25121 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25124 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25125 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25126 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25127 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25128 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25129 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25130 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25133 #define ARM_VARIANT & fpu_neon_ext_v1
25134 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25135 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25136 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25137 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25138 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25139 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25140 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25141 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25142 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25143 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25144 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25145 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25146 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25147 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25148 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25149 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25150 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25151 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25152 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25153 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25154 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25155 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25156 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25157 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25158 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25159 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25160 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25161 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25162 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25163 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25164 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25165 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25166 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25167 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25170 #define ARM_VARIANT & arm_ext_v8_3
25171 #undef THUMB_VARIANT
25172 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25173 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25174 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25177 #undef THUMB_VARIANT
25209 /* MD interface: bits in the object file. */
25211 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25212 for use in the a.out file, and stores them in the array pointed to by buf.
25213 This knows about the endian-ness of the target machine and does
25214 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25215 2 (short) and 4 (long) Floating numbers are put out as a series of
25216 LITTLENUMS (shorts, here at least). */
25219 md_number_to_chars (char * buf
, valueT val
, int n
)
25221 if (target_big_endian
)
25222 number_to_chars_bigendian (buf
, val
, n
);
25224 number_to_chars_littleendian (buf
, val
, n
);
25228 md_chars_to_number (char * buf
, int n
)
25231 unsigned char * where
= (unsigned char *) buf
;
25233 if (target_big_endian
)
25238 result
|= (*where
++ & 255);
25246 result
|= (where
[n
] & 255);
25253 /* MD interface: Sections. */
25255 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25256 that an rs_machine_dependent frag may reach. */
25259 arm_frag_max_var (fragS
*fragp
)
25261 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25262 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25264 Note that we generate relaxable instructions even for cases that don't
25265 really need it, like an immediate that's a trivial constant. So we're
25266 overestimating the instruction size for some of those cases. Rather
25267 than putting more intelligence here, it would probably be better to
25268 avoid generating a relaxation frag in the first place when it can be
25269 determined up front that a short instruction will suffice. */
25271 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25275 /* Estimate the size of a frag before relaxing. Assume everything fits in
25279 md_estimate_size_before_relax (fragS
* fragp
,
25280 segT segtype ATTRIBUTE_UNUSED
)
25286 /* Convert a machine dependent frag. */
25289 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25291 unsigned long insn
;
25292 unsigned long old_op
;
25300 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25302 old_op
= bfd_get_16(abfd
, buf
);
25303 if (fragp
->fr_symbol
)
25305 exp
.X_op
= O_symbol
;
25306 exp
.X_add_symbol
= fragp
->fr_symbol
;
25310 exp
.X_op
= O_constant
;
25312 exp
.X_add_number
= fragp
->fr_offset
;
25313 opcode
= fragp
->fr_subtype
;
25316 case T_MNEM_ldr_pc
:
25317 case T_MNEM_ldr_pc2
:
25318 case T_MNEM_ldr_sp
:
25319 case T_MNEM_str_sp
:
25326 if (fragp
->fr_var
== 4)
25328 insn
= THUMB_OP32 (opcode
);
25329 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25331 insn
|= (old_op
& 0x700) << 4;
25335 insn
|= (old_op
& 7) << 12;
25336 insn
|= (old_op
& 0x38) << 13;
25338 insn
|= 0x00000c00;
25339 put_thumb32_insn (buf
, insn
);
25340 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25344 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25346 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25349 if (fragp
->fr_var
== 4)
25351 insn
= THUMB_OP32 (opcode
);
25352 insn
|= (old_op
& 0xf0) << 4;
25353 put_thumb32_insn (buf
, insn
);
25354 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25358 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25359 exp
.X_add_number
-= 4;
25367 if (fragp
->fr_var
== 4)
25369 int r0off
= (opcode
== T_MNEM_mov
25370 || opcode
== T_MNEM_movs
) ? 0 : 8;
25371 insn
= THUMB_OP32 (opcode
);
25372 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25373 insn
|= (old_op
& 0x700) << r0off
;
25374 put_thumb32_insn (buf
, insn
);
25375 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25379 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25384 if (fragp
->fr_var
== 4)
25386 insn
= THUMB_OP32(opcode
);
25387 put_thumb32_insn (buf
, insn
);
25388 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25391 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25395 if (fragp
->fr_var
== 4)
25397 insn
= THUMB_OP32(opcode
);
25398 insn
|= (old_op
& 0xf00) << 14;
25399 put_thumb32_insn (buf
, insn
);
25400 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25403 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25406 case T_MNEM_add_sp
:
25407 case T_MNEM_add_pc
:
25408 case T_MNEM_inc_sp
:
25409 case T_MNEM_dec_sp
:
25410 if (fragp
->fr_var
== 4)
25412 /* ??? Choose between add and addw. */
25413 insn
= THUMB_OP32 (opcode
);
25414 insn
|= (old_op
& 0xf0) << 4;
25415 put_thumb32_insn (buf
, insn
);
25416 if (opcode
== T_MNEM_add_pc
)
25417 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25419 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25422 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25430 if (fragp
->fr_var
== 4)
25432 insn
= THUMB_OP32 (opcode
);
25433 insn
|= (old_op
& 0xf0) << 4;
25434 insn
|= (old_op
& 0xf) << 16;
25435 put_thumb32_insn (buf
, insn
);
25436 if (insn
& (1 << 20))
25437 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25439 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25442 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25448 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25449 (enum bfd_reloc_code_real
) reloc_type
);
25450 fixp
->fx_file
= fragp
->fr_file
;
25451 fixp
->fx_line
= fragp
->fr_line
;
25452 fragp
->fr_fix
+= fragp
->fr_var
;
25454 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25455 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25456 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25457 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25460 /* Return the size of a relaxable immediate operand instruction.
25461 SHIFT and SIZE specify the form of the allowable immediate. */
25463 relax_immediate (fragS
*fragp
, int size
, int shift
)
25469 /* ??? Should be able to do better than this. */
25470 if (fragp
->fr_symbol
)
25473 low
= (1 << shift
) - 1;
25474 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25475 offset
= fragp
->fr_offset
;
25476 /* Force misaligned offsets to 32-bit variant. */
25479 if (offset
& ~mask
)
25484 /* Get the address of a symbol during relaxation. */
25486 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25492 sym
= fragp
->fr_symbol
;
25493 sym_frag
= symbol_get_frag (sym
);
25494 know (S_GET_SEGMENT (sym
) != absolute_section
25495 || sym_frag
== &zero_address_frag
);
25496 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25498 /* If frag has yet to be reached on this pass, assume it will
25499 move by STRETCH just as we did. If this is not so, it will
25500 be because some frag between grows, and that will force
25504 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25508 /* Adjust stretch for any alignment frag. Note that if have
25509 been expanding the earlier code, the symbol may be
25510 defined in what appears to be an earlier frag. FIXME:
25511 This doesn't handle the fr_subtype field, which specifies
25512 a maximum number of bytes to skip when doing an
25514 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25516 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25519 stretch
= - ((- stretch
)
25520 & ~ ((1 << (int) f
->fr_offset
) - 1));
25522 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25534 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25537 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25542 /* Assume worst case for symbols not known to be in the same section. */
25543 if (fragp
->fr_symbol
== NULL
25544 || !S_IS_DEFINED (fragp
->fr_symbol
)
25545 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25546 || S_IS_WEAK (fragp
->fr_symbol
))
25549 val
= relaxed_symbol_addr (fragp
, stretch
);
25550 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25551 addr
= (addr
+ 4) & ~3;
25552 /* Force misaligned targets to 32-bit variant. */
25556 if (val
< 0 || val
> 1020)
25561 /* Return the size of a relaxable add/sub immediate instruction. */
25563 relax_addsub (fragS
*fragp
, asection
*sec
)
25568 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25569 op
= bfd_get_16(sec
->owner
, buf
);
25570 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25571 return relax_immediate (fragp
, 8, 0);
25573 return relax_immediate (fragp
, 3, 0);
25576 /* Return TRUE iff the definition of symbol S could be pre-empted
25577 (overridden) at link or load time. */
25579 symbol_preemptible (symbolS
*s
)
25581 /* Weak symbols can always be pre-empted. */
25585 /* Non-global symbols cannot be pre-empted. */
25586 if (! S_IS_EXTERNAL (s
))
25590 /* In ELF, a global symbol can be marked protected, or private. In that
25591 case it can't be pre-empted (other definitions in the same link unit
25592 would violate the ODR). */
25593 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25597 /* Other global symbols might be pre-empted. */
25601 /* Return the size of a relaxable branch instruction. BITS is the
25602 size of the offset field in the narrow instruction. */
25605 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25611 /* Assume worst case for symbols not known to be in the same section. */
25612 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25613 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25614 || S_IS_WEAK (fragp
->fr_symbol
))
25618 /* A branch to a function in ARM state will require interworking. */
25619 if (S_IS_DEFINED (fragp
->fr_symbol
)
25620 && ARM_IS_FUNC (fragp
->fr_symbol
))
25624 if (symbol_preemptible (fragp
->fr_symbol
))
25627 val
= relaxed_symbol_addr (fragp
, stretch
);
25628 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25631 /* Offset is a signed value *2 */
25633 if (val
>= limit
|| val
< -limit
)
25639 /* Relax a machine dependent frag. This returns the amount by which
25640 the current size of the frag should change. */
25643 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25648 oldsize
= fragp
->fr_var
;
25649 switch (fragp
->fr_subtype
)
25651 case T_MNEM_ldr_pc2
:
25652 newsize
= relax_adr (fragp
, sec
, stretch
);
25654 case T_MNEM_ldr_pc
:
25655 case T_MNEM_ldr_sp
:
25656 case T_MNEM_str_sp
:
25657 newsize
= relax_immediate (fragp
, 8, 2);
25661 newsize
= relax_immediate (fragp
, 5, 2);
25665 newsize
= relax_immediate (fragp
, 5, 1);
25669 newsize
= relax_immediate (fragp
, 5, 0);
25672 newsize
= relax_adr (fragp
, sec
, stretch
);
25678 newsize
= relax_immediate (fragp
, 8, 0);
25681 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25684 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25686 case T_MNEM_add_sp
:
25687 case T_MNEM_add_pc
:
25688 newsize
= relax_immediate (fragp
, 8, 2);
25690 case T_MNEM_inc_sp
:
25691 case T_MNEM_dec_sp
:
25692 newsize
= relax_immediate (fragp
, 7, 2);
25698 newsize
= relax_addsub (fragp
, sec
);
25704 fragp
->fr_var
= newsize
;
25705 /* Freeze wide instructions that are at or before the same location as
25706 in the previous pass. This avoids infinite loops.
25707 Don't freeze them unconditionally because targets may be artificially
25708 misaligned by the expansion of preceding frags. */
25709 if (stretch
<= 0 && newsize
> 2)
25711 md_convert_frag (sec
->owner
, sec
, fragp
);
25715 return newsize
- oldsize
;
25718 /* Round up a section size to the appropriate boundary. */
25721 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25727 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25728 of an rs_align_code fragment. */
25731 arm_handle_align (fragS
* fragP
)
25733 static unsigned char const arm_noop
[2][2][4] =
25736 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25737 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25740 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25741 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25744 static unsigned char const thumb_noop
[2][2][2] =
25747 {0xc0, 0x46}, /* LE */
25748 {0x46, 0xc0}, /* BE */
25751 {0x00, 0xbf}, /* LE */
25752 {0xbf, 0x00} /* BE */
25755 static unsigned char const wide_thumb_noop
[2][4] =
25756 { /* Wide Thumb-2 */
25757 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25758 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25761 unsigned bytes
, fix
, noop_size
;
25763 const unsigned char * noop
;
25764 const unsigned char *narrow_noop
= NULL
;
25769 if (fragP
->fr_type
!= rs_align_code
)
25772 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
25773 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
25776 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25777 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
25779 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
25781 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
25783 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25784 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
25786 narrow_noop
= thumb_noop
[1][target_big_endian
];
25787 noop
= wide_thumb_noop
[target_big_endian
];
25790 noop
= thumb_noop
[0][target_big_endian
];
25798 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25799 ? selected_cpu
: arm_arch_none
,
25801 [target_big_endian
];
25808 fragP
->fr_var
= noop_size
;
25810 if (bytes
& (noop_size
- 1))
25812 fix
= bytes
& (noop_size
- 1);
25814 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
25816 memset (p
, 0, fix
);
25823 if (bytes
& noop_size
)
25825 /* Insert a narrow noop. */
25826 memcpy (p
, narrow_noop
, noop_size
);
25828 bytes
-= noop_size
;
25832 /* Use wide noops for the remainder */
25836 while (bytes
>= noop_size
)
25838 memcpy (p
, noop
, noop_size
);
25840 bytes
-= noop_size
;
25844 fragP
->fr_fix
+= fix
;
25847 /* Called from md_do_align. Used to create an alignment
25848 frag in a code section. */
25851 arm_frag_align_code (int n
, int max
)
25855 /* We assume that there will never be a requirement
25856 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25857 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25862 _("alignments greater than %d bytes not supported in .text sections."),
25863 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
25864 as_fatal ("%s", err_msg
);
25867 p
= frag_var (rs_align_code
,
25868 MAX_MEM_FOR_RS_ALIGN_CODE
,
25870 (relax_substateT
) max
,
25877 /* Perform target specific initialisation of a frag.
25878 Note - despite the name this initialisation is not done when the frag
25879 is created, but only when its type is assigned. A frag can be created
25880 and used a long time before its type is set, so beware of assuming that
25881 this initialisation is performed first. */
25885 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
25887 /* Record whether this frag is in an ARM or a THUMB area. */
25888 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25891 #else /* OBJ_ELF is defined. */
25893 arm_init_frag (fragS
* fragP
, int max_chars
)
25895 bfd_boolean frag_thumb_mode
;
25897 /* If the current ARM vs THUMB mode has not already
25898 been recorded into this frag then do so now. */
25899 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
25900 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25902 /* PR 21809: Do not set a mapping state for debug sections
25903 - it just confuses other tools. */
25904 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
25907 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
25909 /* Record a mapping symbol for alignment frags. We will delete this
25910 later if the alignment ends up empty. */
25911 switch (fragP
->fr_type
)
25914 case rs_align_test
:
25916 mapping_state_2 (MAP_DATA
, max_chars
);
25918 case rs_align_code
:
25919 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
25926 /* When we change sections we need to issue a new mapping symbol. */
25929 arm_elf_change_section (void)
25931 /* Link an unlinked unwind index table section to the .text section. */
25932 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
25933 && elf_linked_to_section (now_seg
) == NULL
)
25934 elf_linked_to_section (now_seg
) = text_section
;
25938 arm_elf_section_type (const char * str
, size_t len
)
25940 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
25941 return SHT_ARM_EXIDX
;
25946 /* Code to deal with unwinding tables. */
25948 static void add_unwind_adjustsp (offsetT
);
25950 /* Generate any deferred unwind frame offset. */
25953 flush_pending_unwind (void)
25957 offset
= unwind
.pending_offset
;
25958 unwind
.pending_offset
= 0;
25960 add_unwind_adjustsp (offset
);
25963 /* Add an opcode to this list for this function. Two-byte opcodes should
25964 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25968 add_unwind_opcode (valueT op
, int length
)
25970 /* Add any deferred stack adjustment. */
25971 if (unwind
.pending_offset
)
25972 flush_pending_unwind ();
25974 unwind
.sp_restored
= 0;
25976 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
25978 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
25979 if (unwind
.opcodes
)
25980 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
25981 unwind
.opcode_alloc
);
25983 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
25988 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
25990 unwind
.opcode_count
++;
25994 /* Add unwind opcodes to adjust the stack pointer. */
25997 add_unwind_adjustsp (offsetT offset
)
26001 if (offset
> 0x200)
26003 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26008 /* Long form: 0xb2, uleb128. */
26009 /* This might not fit in a word so add the individual bytes,
26010 remembering the list is built in reverse order. */
26011 o
= (valueT
) ((offset
- 0x204) >> 2);
26013 add_unwind_opcode (0, 1);
26015 /* Calculate the uleb128 encoding of the offset. */
26019 bytes
[n
] = o
& 0x7f;
26025 /* Add the insn. */
26027 add_unwind_opcode (bytes
[n
- 1], 1);
26028 add_unwind_opcode (0xb2, 1);
26030 else if (offset
> 0x100)
26032 /* Two short opcodes. */
26033 add_unwind_opcode (0x3f, 1);
26034 op
= (offset
- 0x104) >> 2;
26035 add_unwind_opcode (op
, 1);
26037 else if (offset
> 0)
26039 /* Short opcode. */
26040 op
= (offset
- 4) >> 2;
26041 add_unwind_opcode (op
, 1);
26043 else if (offset
< 0)
26046 while (offset
> 0x100)
26048 add_unwind_opcode (0x7f, 1);
26051 op
= ((offset
- 4) >> 2) | 0x40;
26052 add_unwind_opcode (op
, 1);
26056 /* Finish the list of unwind opcodes for this function. */
26059 finish_unwind_opcodes (void)
26063 if (unwind
.fp_used
)
26065 /* Adjust sp as necessary. */
26066 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26067 flush_pending_unwind ();
26069 /* After restoring sp from the frame pointer. */
26070 op
= 0x90 | unwind
.fp_reg
;
26071 add_unwind_opcode (op
, 1);
26074 flush_pending_unwind ();
26078 /* Start an exception table entry. If idx is nonzero this is an index table
26082 start_unwind_section (const segT text_seg
, int idx
)
26084 const char * text_name
;
26085 const char * prefix
;
26086 const char * prefix_once
;
26087 const char * group_name
;
26095 prefix
= ELF_STRING_ARM_unwind
;
26096 prefix_once
= ELF_STRING_ARM_unwind_once
;
26097 type
= SHT_ARM_EXIDX
;
26101 prefix
= ELF_STRING_ARM_unwind_info
;
26102 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26103 type
= SHT_PROGBITS
;
26106 text_name
= segment_name (text_seg
);
26107 if (streq (text_name
, ".text"))
26110 if (strncmp (text_name
, ".gnu.linkonce.t.",
26111 strlen (".gnu.linkonce.t.")) == 0)
26113 prefix
= prefix_once
;
26114 text_name
+= strlen (".gnu.linkonce.t.");
26117 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26123 /* Handle COMDAT group. */
26124 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26126 group_name
= elf_group_name (text_seg
);
26127 if (group_name
== NULL
)
26129 as_bad (_("Group section `%s' has no group signature"),
26130 segment_name (text_seg
));
26131 ignore_rest_of_line ();
26134 flags
|= SHF_GROUP
;
26138 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26141 /* Set the section link for index tables. */
26143 elf_linked_to_section (now_seg
) = text_seg
;
26147 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26148 personality routine data. Returns zero, or the index table value for
26149 an inline entry. */
26152 create_unwind_entry (int have_data
)
26157 /* The current word of data. */
26159 /* The number of bytes left in this word. */
26162 finish_unwind_opcodes ();
26164 /* Remember the current text section. */
26165 unwind
.saved_seg
= now_seg
;
26166 unwind
.saved_subseg
= now_subseg
;
26168 start_unwind_section (now_seg
, 0);
26170 if (unwind
.personality_routine
== NULL
)
26172 if (unwind
.personality_index
== -2)
26175 as_bad (_("handlerdata in cantunwind frame"));
26176 return 1; /* EXIDX_CANTUNWIND. */
26179 /* Use a default personality routine if none is specified. */
26180 if (unwind
.personality_index
== -1)
26182 if (unwind
.opcode_count
> 3)
26183 unwind
.personality_index
= 1;
26185 unwind
.personality_index
= 0;
26188 /* Space for the personality routine entry. */
26189 if (unwind
.personality_index
== 0)
26191 if (unwind
.opcode_count
> 3)
26192 as_bad (_("too many unwind opcodes for personality routine 0"));
26196 /* All the data is inline in the index table. */
26199 while (unwind
.opcode_count
> 0)
26201 unwind
.opcode_count
--;
26202 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26206 /* Pad with "finish" opcodes. */
26208 data
= (data
<< 8) | 0xb0;
26215 /* We get two opcodes "free" in the first word. */
26216 size
= unwind
.opcode_count
- 2;
26220 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26221 if (unwind
.personality_index
!= -1)
26223 as_bad (_("attempt to recreate an unwind entry"));
26227 /* An extra byte is required for the opcode count. */
26228 size
= unwind
.opcode_count
+ 1;
26231 size
= (size
+ 3) >> 2;
26233 as_bad (_("too many unwind opcodes"));
26235 frag_align (2, 0, 0);
26236 record_alignment (now_seg
, 2);
26237 unwind
.table_entry
= expr_build_dot ();
26239 /* Allocate the table entry. */
26240 ptr
= frag_more ((size
<< 2) + 4);
26241 /* PR 13449: Zero the table entries in case some of them are not used. */
26242 memset (ptr
, 0, (size
<< 2) + 4);
26243 where
= frag_now_fix () - ((size
<< 2) + 4);
26245 switch (unwind
.personality_index
)
26248 /* ??? Should this be a PLT generating relocation? */
26249 /* Custom personality routine. */
26250 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26251 BFD_RELOC_ARM_PREL31
);
26256 /* Set the first byte to the number of additional words. */
26257 data
= size
> 0 ? size
- 1 : 0;
26261 /* ABI defined personality routines. */
26263 /* Three opcodes bytes are packed into the first word. */
26270 /* The size and first two opcode bytes go in the first word. */
26271 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26276 /* Should never happen. */
26280 /* Pack the opcodes into words (MSB first), reversing the list at the same
26282 while (unwind
.opcode_count
> 0)
26286 md_number_to_chars (ptr
, data
, 4);
26291 unwind
.opcode_count
--;
26293 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26296 /* Finish off the last word. */
26299 /* Pad with "finish" opcodes. */
26301 data
= (data
<< 8) | 0xb0;
26303 md_number_to_chars (ptr
, data
, 4);
26308 /* Add an empty descriptor if there is no user-specified data. */
26309 ptr
= frag_more (4);
26310 md_number_to_chars (ptr
, 0, 4);
26317 /* Initialize the DWARF-2 unwind information for this procedure. */
26320 tc_arm_frame_initial_instructions (void)
26322 cfi_add_CFA_def_cfa (REG_SP
, 0);
26324 #endif /* OBJ_ELF */
26326 /* Convert REGNAME to a DWARF-2 register number. */
26329 tc_arm_regname_to_dw2regnum (char *regname
)
26331 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26335 /* PR 16694: Allow VFP registers as well. */
26336 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26340 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26349 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26353 exp
.X_op
= O_secrel
;
26354 exp
.X_add_symbol
= symbol
;
26355 exp
.X_add_number
= 0;
26356 emit_expr (&exp
, size
);
26360 /* MD interface: Symbol and relocation handling. */
26362 /* Return the address within the segment that a PC-relative fixup is
26363 relative to. For ARM, PC-relative fixups applied to instructions
26364 are generally relative to the location of the fixup plus 8 bytes.
26365 Thumb branches are offset by 4, and Thumb loads relative to PC
26366 require special handling. */
26369 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26371 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26373 /* If this is pc-relative and we are going to emit a relocation
26374 then we just want to put out any pipeline compensation that the linker
26375 will need. Otherwise we want to use the calculated base.
26376 For WinCE we skip the bias for externals as well, since this
26377 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26379 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26380 || (arm_force_relocation (fixP
)
26382 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26388 switch (fixP
->fx_r_type
)
26390 /* PC relative addressing on the Thumb is slightly odd as the
26391 bottom two bits of the PC are forced to zero for the
26392 calculation. This happens *after* application of the
26393 pipeline offset. However, Thumb adrl already adjusts for
26394 this, so we need not do it again. */
26395 case BFD_RELOC_ARM_THUMB_ADD
:
26398 case BFD_RELOC_ARM_THUMB_OFFSET
:
26399 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26400 case BFD_RELOC_ARM_T32_ADD_PC12
:
26401 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26402 return (base
+ 4) & ~3;
26404 /* Thumb branches are simply offset by +4. */
26405 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26406 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26407 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26408 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26409 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26410 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26411 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26412 case BFD_RELOC_ARM_THUMB_BF17
:
26413 case BFD_RELOC_ARM_THUMB_BF19
:
26414 case BFD_RELOC_ARM_THUMB_BF13
:
26415 case BFD_RELOC_ARM_THUMB_LOOP12
:
26418 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26420 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26421 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26422 && ARM_IS_FUNC (fixP
->fx_addsy
)
26423 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26424 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26427 /* BLX is like branches above, but forces the low two bits of PC to
26429 case BFD_RELOC_THUMB_PCREL_BLX
:
26431 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26432 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26433 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26434 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26435 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26436 return (base
+ 4) & ~3;
26438 /* ARM mode branches are offset by +8. However, the Windows CE
26439 loader expects the relocation not to take this into account. */
26440 case BFD_RELOC_ARM_PCREL_BLX
:
26442 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26443 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26444 && ARM_IS_FUNC (fixP
->fx_addsy
)
26445 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26446 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26449 case BFD_RELOC_ARM_PCREL_CALL
:
26451 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26452 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26453 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26454 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26455 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26458 case BFD_RELOC_ARM_PCREL_BRANCH
:
26459 case BFD_RELOC_ARM_PCREL_JUMP
:
26460 case BFD_RELOC_ARM_PLT32
:
26462 /* When handling fixups immediately, because we have already
26463 discovered the value of a symbol, or the address of the frag involved
26464 we must account for the offset by +8, as the OS loader will never see the reloc.
26465 see fixup_segment() in write.c
26466 The S_IS_EXTERNAL test handles the case of global symbols.
26467 Those need the calculated base, not just the pipe compensation the linker will need. */
26469 && fixP
->fx_addsy
!= NULL
26470 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26471 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26479 /* ARM mode loads relative to PC are also offset by +8. Unlike
26480 branches, the Windows CE loader *does* expect the relocation
26481 to take this into account. */
26482 case BFD_RELOC_ARM_OFFSET_IMM
:
26483 case BFD_RELOC_ARM_OFFSET_IMM8
:
26484 case BFD_RELOC_ARM_HWLITERAL
:
26485 case BFD_RELOC_ARM_LITERAL
:
26486 case BFD_RELOC_ARM_CP_OFF_IMM
:
26490 /* Other PC-relative relocations are un-offset. */
26496 static bfd_boolean flag_warn_syms
= TRUE
;
26499 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26501 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26502 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26503 does mean that the resulting code might be very confusing to the reader.
26504 Also this warning can be triggered if the user omits an operand before
26505 an immediate address, eg:
26509 GAS treats this as an assignment of the value of the symbol foo to a
26510 symbol LDR, and so (without this code) it will not issue any kind of
26511 warning or error message.
26513 Note - ARM instructions are case-insensitive but the strings in the hash
26514 table are all stored in lower case, so we must first ensure that name is
26516 if (flag_warn_syms
&& arm_ops_hsh
)
26518 char * nbuf
= strdup (name
);
26521 for (p
= nbuf
; *p
; p
++)
26523 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26525 static struct hash_control
* already_warned
= NULL
;
26527 if (already_warned
== NULL
)
26528 already_warned
= hash_new ();
26529 /* Only warn about the symbol once. To keep the code
26530 simple we let hash_insert do the lookup for us. */
26531 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26532 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26541 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26542 Otherwise we have no need to default values of symbols. */
26545 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26548 if (name
[0] == '_' && name
[1] == 'G'
26549 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26553 if (symbol_find (name
))
26554 as_bad (_("GOT already in the symbol table"));
26556 GOT_symbol
= symbol_new (name
, undefined_section
,
26557 (valueT
) 0, & zero_address_frag
);
26567 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26568 computed as two separate immediate values, added together. We
26569 already know that this value cannot be computed by just one ARM
26572 static unsigned int
26573 validate_immediate_twopart (unsigned int val
,
26574 unsigned int * highpart
)
26579 for (i
= 0; i
< 32; i
+= 2)
26580 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26586 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26588 else if (a
& 0xff0000)
26590 if (a
& 0xff000000)
26592 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26596 gas_assert (a
& 0xff000000);
26597 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26600 return (a
& 0xff) | (i
<< 7);
26607 validate_offset_imm (unsigned int val
, int hwse
)
26609 if ((hwse
&& val
> 255) || val
> 4095)
26614 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26615 negative immediate constant by altering the instruction. A bit of
26620 by inverting the second operand, and
26623 by negating the second operand. */
26626 negate_data_op (unsigned long * instruction
,
26627 unsigned long value
)
26630 unsigned long negated
, inverted
;
26632 negated
= encode_arm_immediate (-value
);
26633 inverted
= encode_arm_immediate (~value
);
26635 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26638 /* First negates. */
26639 case OPCODE_SUB
: /* ADD <-> SUB */
26640 new_inst
= OPCODE_ADD
;
26645 new_inst
= OPCODE_SUB
;
26649 case OPCODE_CMP
: /* CMP <-> CMN */
26650 new_inst
= OPCODE_CMN
;
26655 new_inst
= OPCODE_CMP
;
26659 /* Now Inverted ops. */
26660 case OPCODE_MOV
: /* MOV <-> MVN */
26661 new_inst
= OPCODE_MVN
;
26666 new_inst
= OPCODE_MOV
;
26670 case OPCODE_AND
: /* AND <-> BIC */
26671 new_inst
= OPCODE_BIC
;
26676 new_inst
= OPCODE_AND
;
26680 case OPCODE_ADC
: /* ADC <-> SBC */
26681 new_inst
= OPCODE_SBC
;
26686 new_inst
= OPCODE_ADC
;
26690 /* We cannot do anything. */
26695 if (value
== (unsigned) FAIL
)
26698 *instruction
&= OPCODE_MASK
;
26699 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26703 /* Like negate_data_op, but for Thumb-2. */
26705 static unsigned int
26706 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26710 unsigned int negated
, inverted
;
26712 negated
= encode_thumb32_immediate (-value
);
26713 inverted
= encode_thumb32_immediate (~value
);
26715 rd
= (*instruction
>> 8) & 0xf;
26716 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26719 /* ADD <-> SUB. Includes CMP <-> CMN. */
26720 case T2_OPCODE_SUB
:
26721 new_inst
= T2_OPCODE_ADD
;
26725 case T2_OPCODE_ADD
:
26726 new_inst
= T2_OPCODE_SUB
;
26730 /* ORR <-> ORN. Includes MOV <-> MVN. */
26731 case T2_OPCODE_ORR
:
26732 new_inst
= T2_OPCODE_ORN
;
26736 case T2_OPCODE_ORN
:
26737 new_inst
= T2_OPCODE_ORR
;
26741 /* AND <-> BIC. TST has no inverted equivalent. */
26742 case T2_OPCODE_AND
:
26743 new_inst
= T2_OPCODE_BIC
;
26750 case T2_OPCODE_BIC
:
26751 new_inst
= T2_OPCODE_AND
;
26756 case T2_OPCODE_ADC
:
26757 new_inst
= T2_OPCODE_SBC
;
26761 case T2_OPCODE_SBC
:
26762 new_inst
= T2_OPCODE_ADC
;
26766 /* We cannot do anything. */
26771 if (value
== (unsigned int)FAIL
)
26774 *instruction
&= T2_OPCODE_MASK
;
26775 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
26779 /* Read a 32-bit thumb instruction from buf. */
26781 static unsigned long
26782 get_thumb32_insn (char * buf
)
26784 unsigned long insn
;
26785 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
26786 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26791 /* We usually want to set the low bit on the address of thumb function
26792 symbols. In particular .word foo - . should have the low bit set.
26793 Generic code tries to fold the difference of two symbols to
26794 a constant. Prevent this and force a relocation when the first symbols
26795 is a thumb function. */
26798 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
26800 if (op
== O_subtract
26801 && l
->X_op
== O_symbol
26802 && r
->X_op
== O_symbol
26803 && THUMB_IS_FUNC (l
->X_add_symbol
))
26805 l
->X_op
= O_subtract
;
26806 l
->X_op_symbol
= r
->X_add_symbol
;
26807 l
->X_add_number
-= r
->X_add_number
;
26811 /* Process as normal. */
26815 /* Encode Thumb2 unconditional branches and calls. The encoding
26816 for the 2 are identical for the immediate values. */
26819 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
26821 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26824 addressT S
, I1
, I2
, lo
, hi
;
26826 S
= (value
>> 24) & 0x01;
26827 I1
= (value
>> 23) & 0x01;
26828 I2
= (value
>> 22) & 0x01;
26829 hi
= (value
>> 12) & 0x3ff;
26830 lo
= (value
>> 1) & 0x7ff;
26831 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26832 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26833 newval
|= (S
<< 10) | hi
;
26834 newval2
&= ~T2I1I2MASK
;
26835 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
26836 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26837 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26841 md_apply_fix (fixS
* fixP
,
26845 offsetT value
= * valP
;
26847 unsigned int newimm
;
26848 unsigned long temp
;
26850 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
26852 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
26854 /* Note whether this will delete the relocation. */
26856 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
26859 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26860 consistency with the behaviour on 32-bit hosts. Remember value
26862 value
&= 0xffffffff;
26863 value
^= 0x80000000;
26864 value
-= 0x80000000;
26867 fixP
->fx_addnumber
= value
;
26869 /* Same treatment for fixP->fx_offset. */
26870 fixP
->fx_offset
&= 0xffffffff;
26871 fixP
->fx_offset
^= 0x80000000;
26872 fixP
->fx_offset
-= 0x80000000;
26874 switch (fixP
->fx_r_type
)
26876 case BFD_RELOC_NONE
:
26877 /* This will need to go in the object file. */
26881 case BFD_RELOC_ARM_IMMEDIATE
:
26882 /* We claim that this fixup has been processed here,
26883 even if in fact we generate an error because we do
26884 not have a reloc for it, so tc_gen_reloc will reject it. */
26887 if (fixP
->fx_addsy
)
26889 const char *msg
= 0;
26891 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26892 msg
= _("undefined symbol %s used as an immediate value");
26893 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26894 msg
= _("symbol %s is in a different section");
26895 else if (S_IS_WEAK (fixP
->fx_addsy
))
26896 msg
= _("symbol %s is weak and may be overridden later");
26900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26901 msg
, S_GET_NAME (fixP
->fx_addsy
));
26906 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26908 /* If the offset is negative, we should use encoding A2 for ADR. */
26909 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
26910 newimm
= negate_data_op (&temp
, value
);
26913 newimm
= encode_arm_immediate (value
);
26915 /* If the instruction will fail, see if we can fix things up by
26916 changing the opcode. */
26917 if (newimm
== (unsigned int) FAIL
)
26918 newimm
= negate_data_op (&temp
, value
);
26919 /* MOV accepts both ARM modified immediate (A1 encoding) and
26920 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
26921 When disassembling, MOV is preferred when there is no encoding
26923 if (newimm
== (unsigned int) FAIL
26924 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
26925 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
26926 && !((temp
>> SBIT_SHIFT
) & 0x1)
26927 && value
>= 0 && value
<= 0xffff)
26929 /* Clear bits[23:20] to change encoding from A1 to A2. */
26930 temp
&= 0xff0fffff;
26931 /* Encoding high 4bits imm. Code below will encode the remaining
26933 temp
|= (value
& 0x0000f000) << 4;
26934 newimm
= value
& 0x00000fff;
26938 if (newimm
== (unsigned int) FAIL
)
26940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26941 _("invalid constant (%lx) after fixup"),
26942 (unsigned long) value
);
26946 newimm
|= (temp
& 0xfffff000);
26947 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26950 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
26952 unsigned int highpart
= 0;
26953 unsigned int newinsn
= 0xe1a00000; /* nop. */
26955 if (fixP
->fx_addsy
)
26957 const char *msg
= 0;
26959 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26960 msg
= _("undefined symbol %s used as an immediate value");
26961 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26962 msg
= _("symbol %s is in a different section");
26963 else if (S_IS_WEAK (fixP
->fx_addsy
))
26964 msg
= _("symbol %s is weak and may be overridden later");
26968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26969 msg
, S_GET_NAME (fixP
->fx_addsy
));
26974 newimm
= encode_arm_immediate (value
);
26975 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26977 /* If the instruction will fail, see if we can fix things up by
26978 changing the opcode. */
26979 if (newimm
== (unsigned int) FAIL
26980 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
26982 /* No ? OK - try using two ADD instructions to generate
26984 newimm
= validate_immediate_twopart (value
, & highpart
);
26986 /* Yes - then make sure that the second instruction is
26988 if (newimm
!= (unsigned int) FAIL
)
26990 /* Still No ? Try using a negated value. */
26991 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
26992 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
26993 /* Otherwise - give up. */
26996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26997 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27002 /* Replace the first operand in the 2nd instruction (which
27003 is the PC) with the destination register. We have
27004 already added in the PC in the first instruction and we
27005 do not want to do it again. */
27006 newinsn
&= ~ 0xf0000;
27007 newinsn
|= ((newinsn
& 0x0f000) << 4);
27010 newimm
|= (temp
& 0xfffff000);
27011 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27013 highpart
|= (newinsn
& 0xfffff000);
27014 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27018 case BFD_RELOC_ARM_OFFSET_IMM
:
27019 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27021 /* Fall through. */
27023 case BFD_RELOC_ARM_LITERAL
:
27029 if (validate_offset_imm (value
, 0) == FAIL
)
27031 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27033 _("invalid literal constant: pool needs to be closer"));
27035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27036 _("bad immediate value for offset (%ld)"),
27041 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27043 newval
&= 0xfffff000;
27046 newval
&= 0xff7ff000;
27047 newval
|= value
| (sign
? INDEX_UP
: 0);
27049 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27052 case BFD_RELOC_ARM_OFFSET_IMM8
:
27053 case BFD_RELOC_ARM_HWLITERAL
:
27059 if (validate_offset_imm (value
, 1) == FAIL
)
27061 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27063 _("invalid literal constant: pool needs to be closer"));
27065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27066 _("bad immediate value for 8-bit offset (%ld)"),
27071 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27073 newval
&= 0xfffff0f0;
27076 newval
&= 0xff7ff0f0;
27077 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27079 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27082 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27083 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27085 _("bad immediate value for offset (%ld)"), (long) value
);
27088 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27090 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27093 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27094 /* This is a complicated relocation used for all varieties of Thumb32
27095 load/store instruction with immediate offset:
27097 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27098 *4, optional writeback(W)
27099 (doubleword load/store)
27101 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27102 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27103 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27104 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27105 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27107 Uppercase letters indicate bits that are already encoded at
27108 this point. Lowercase letters are our problem. For the
27109 second block of instructions, the secondary opcode nybble
27110 (bits 8..11) is present, and bit 23 is zero, even if this is
27111 a PC-relative operation. */
27112 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27114 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27116 if ((newval
& 0xf0000000) == 0xe0000000)
27118 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27120 newval
|= (1 << 23);
27123 if (value
% 4 != 0)
27125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27126 _("offset not a multiple of 4"));
27132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27133 _("offset out of range"));
27138 else if ((newval
& 0x000f0000) == 0x000f0000)
27140 /* PC-relative, 12-bit offset. */
27142 newval
|= (1 << 23);
27147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27148 _("offset out of range"));
27153 else if ((newval
& 0x00000100) == 0x00000100)
27155 /* Writeback: 8-bit, +/- offset. */
27157 newval
|= (1 << 9);
27162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27163 _("offset out of range"));
27168 else if ((newval
& 0x00000f00) == 0x00000e00)
27170 /* T-instruction: positive 8-bit offset. */
27171 if (value
< 0 || value
> 0xff)
27173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27174 _("offset out of range"));
27182 /* Positive 12-bit or negative 8-bit offset. */
27186 newval
|= (1 << 23);
27196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27197 _("offset out of range"));
27204 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27205 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27208 case BFD_RELOC_ARM_SHIFT_IMM
:
27209 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27210 if (((unsigned long) value
) > 32
27212 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27215 _("shift expression is too large"));
27220 /* Shifts of zero must be done as lsl. */
27222 else if (value
== 32)
27224 newval
&= 0xfffff07f;
27225 newval
|= (value
& 0x1f) << 7;
27226 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27229 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27230 case BFD_RELOC_ARM_T32_ADD_IMM
:
27231 case BFD_RELOC_ARM_T32_IMM12
:
27232 case BFD_RELOC_ARM_T32_ADD_PC12
:
27233 /* We claim that this fixup has been processed here,
27234 even if in fact we generate an error because we do
27235 not have a reloc for it, so tc_gen_reloc will reject it. */
27239 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27242 _("undefined symbol %s used as an immediate value"),
27243 S_GET_NAME (fixP
->fx_addsy
));
27247 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27249 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27252 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27253 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27254 Thumb2 modified immediate encoding (T2). */
27255 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27256 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27258 newimm
= encode_thumb32_immediate (value
);
27259 if (newimm
== (unsigned int) FAIL
)
27260 newimm
= thumb32_negate_data_op (&newval
, value
);
27262 if (newimm
== (unsigned int) FAIL
)
27264 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27266 /* Turn add/sum into addw/subw. */
27267 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27268 newval
= (newval
& 0xfeffffff) | 0x02000000;
27269 /* No flat 12-bit imm encoding for addsw/subsw. */
27270 if ((newval
& 0x00100000) == 0)
27272 /* 12 bit immediate for addw/subw. */
27276 newval
^= 0x00a00000;
27279 newimm
= (unsigned int) FAIL
;
27286 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27287 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27288 disassembling, MOV is preferred when there is no encoding
27290 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27291 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27292 but with the Rn field [19:16] set to 1111. */
27293 && (((newval
>> 16) & 0xf) == 0xf)
27294 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27295 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27296 && value
>= 0 && value
<= 0xffff)
27298 /* Toggle bit[25] to change encoding from T2 to T3. */
27300 /* Clear bits[19:16]. */
27301 newval
&= 0xfff0ffff;
27302 /* Encoding high 4bits imm. Code below will encode the
27303 remaining low 12bits. */
27304 newval
|= (value
& 0x0000f000) << 4;
27305 newimm
= value
& 0x00000fff;
27310 if (newimm
== (unsigned int)FAIL
)
27312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27313 _("invalid constant (%lx) after fixup"),
27314 (unsigned long) value
);
27318 newval
|= (newimm
& 0x800) << 15;
27319 newval
|= (newimm
& 0x700) << 4;
27320 newval
|= (newimm
& 0x0ff);
27322 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27323 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27326 case BFD_RELOC_ARM_SMC
:
27327 if (((unsigned long) value
) > 0xffff)
27328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27329 _("invalid smc expression"));
27330 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27331 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27332 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27335 case BFD_RELOC_ARM_HVC
:
27336 if (((unsigned long) value
) > 0xffff)
27337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27338 _("invalid hvc expression"));
27339 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27340 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27341 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27344 case BFD_RELOC_ARM_SWI
:
27345 if (fixP
->tc_fix_data
!= 0)
27347 if (((unsigned long) value
) > 0xff)
27348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27349 _("invalid swi expression"));
27350 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27352 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27356 if (((unsigned long) value
) > 0x00ffffff)
27357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27358 _("invalid swi expression"));
27359 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27361 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27365 case BFD_RELOC_ARM_MULTI
:
27366 if (((unsigned long) value
) > 0xffff)
27367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27368 _("invalid expression in load/store multiple"));
27369 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27370 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27374 case BFD_RELOC_ARM_PCREL_CALL
:
27376 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27378 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27379 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27380 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27381 /* Flip the bl to blx. This is a simple flip
27382 bit here because we generate PCREL_CALL for
27383 unconditional bls. */
27385 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27386 newval
= newval
| 0x10000000;
27387 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27393 goto arm_branch_common
;
27395 case BFD_RELOC_ARM_PCREL_JUMP
:
27396 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27398 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27399 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27400 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27402 /* This would map to a bl<cond>, b<cond>,
27403 b<always> to a Thumb function. We
27404 need to force a relocation for this particular
27406 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27409 /* Fall through. */
27411 case BFD_RELOC_ARM_PLT32
:
27413 case BFD_RELOC_ARM_PCREL_BRANCH
:
27415 goto arm_branch_common
;
27417 case BFD_RELOC_ARM_PCREL_BLX
:
27420 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27422 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27423 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27424 && ARM_IS_FUNC (fixP
->fx_addsy
))
27426 /* Flip the blx to a bl and warn. */
27427 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27428 newval
= 0xeb000000;
27429 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27430 _("blx to '%s' an ARM ISA state function changed to bl"),
27432 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27438 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27439 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27443 /* We are going to store value (shifted right by two) in the
27444 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27445 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27449 _("misaligned branch destination"));
27450 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27451 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27456 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27457 newval
|= (value
>> 2) & 0x00ffffff;
27458 /* Set the H bit on BLX instructions. */
27462 newval
|= 0x01000000;
27464 newval
&= ~0x01000000;
27466 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27470 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27471 /* CBZ can only branch forward. */
27473 /* Attempts to use CBZ to branch to the next instruction
27474 (which, strictly speaking, are prohibited) will be turned into
27477 FIXME: It may be better to remove the instruction completely and
27478 perform relaxation. */
27481 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27482 newval
= 0xbf00; /* NOP encoding T1 */
27483 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27490 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27492 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27493 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27494 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27499 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27500 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27503 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27505 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27506 newval
|= (value
& 0x1ff) >> 1;
27507 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27511 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27512 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27515 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27517 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27518 newval
|= (value
& 0xfff) >> 1;
27519 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27523 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27525 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27526 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27527 && ARM_IS_FUNC (fixP
->fx_addsy
)
27528 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27530 /* Force a relocation for a branch 20 bits wide. */
27533 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27535 _("conditional branch out of range"));
27537 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27540 addressT S
, J1
, J2
, lo
, hi
;
27542 S
= (value
& 0x00100000) >> 20;
27543 J2
= (value
& 0x00080000) >> 19;
27544 J1
= (value
& 0x00040000) >> 18;
27545 hi
= (value
& 0x0003f000) >> 12;
27546 lo
= (value
& 0x00000ffe) >> 1;
27548 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27549 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27550 newval
|= (S
<< 10) | hi
;
27551 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27552 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27553 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27557 case BFD_RELOC_THUMB_PCREL_BLX
:
27558 /* If there is a blx from a thumb state function to
27559 another thumb function flip this to a bl and warn
27563 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27564 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27565 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27567 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27568 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27569 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27571 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27572 newval
= newval
| 0x1000;
27573 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27574 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27579 goto thumb_bl_common
;
27581 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27582 /* A bl from Thumb state ISA to an internal ARM state function
27583 is converted to a blx. */
27585 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27586 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27587 && ARM_IS_FUNC (fixP
->fx_addsy
)
27588 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27590 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27591 newval
= newval
& ~0x1000;
27592 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27593 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27599 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27600 /* For a BLX instruction, make sure that the relocation is rounded up
27601 to a word boundary. This follows the semantics of the instruction
27602 which specifies that bit 1 of the target address will come from bit
27603 1 of the base address. */
27604 value
= (value
+ 3) & ~ 3;
27607 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27608 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27609 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27612 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27614 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27616 else if ((value
& ~0x1ffffff)
27617 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27619 _("Thumb2 branch out of range"));
27622 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27623 encode_thumb2_b_bl_offset (buf
, value
);
27627 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27628 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27631 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27632 encode_thumb2_b_bl_offset (buf
, value
);
27637 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27642 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27643 md_number_to_chars (buf
, value
, 2);
27647 case BFD_RELOC_ARM_TLS_CALL
:
27648 case BFD_RELOC_ARM_THM_TLS_CALL
:
27649 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27650 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27651 case BFD_RELOC_ARM_TLS_GOTDESC
:
27652 case BFD_RELOC_ARM_TLS_GD32
:
27653 case BFD_RELOC_ARM_TLS_LE32
:
27654 case BFD_RELOC_ARM_TLS_IE32
:
27655 case BFD_RELOC_ARM_TLS_LDM32
:
27656 case BFD_RELOC_ARM_TLS_LDO32
:
27657 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27660 /* Same handling as above, but with the arm_fdpic guard. */
27661 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27662 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27663 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27666 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27671 _("Relocation supported only in FDPIC mode"));
27675 case BFD_RELOC_ARM_GOT32
:
27676 case BFD_RELOC_ARM_GOTOFF
:
27679 case BFD_RELOC_ARM_GOT_PREL
:
27680 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27681 md_number_to_chars (buf
, value
, 4);
27684 case BFD_RELOC_ARM_TARGET2
:
27685 /* TARGET2 is not partial-inplace, so we need to write the
27686 addend here for REL targets, because it won't be written out
27687 during reloc processing later. */
27688 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27689 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27692 /* Relocations for FDPIC. */
27693 case BFD_RELOC_ARM_GOTFUNCDESC
:
27694 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27695 case BFD_RELOC_ARM_FUNCDESC
:
27698 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27699 md_number_to_chars (buf
, 0, 4);
27703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27704 _("Relocation supported only in FDPIC mode"));
27709 case BFD_RELOC_RVA
:
27711 case BFD_RELOC_ARM_TARGET1
:
27712 case BFD_RELOC_ARM_ROSEGREL32
:
27713 case BFD_RELOC_ARM_SBREL32
:
27714 case BFD_RELOC_32_PCREL
:
27716 case BFD_RELOC_32_SECREL
:
27718 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27720 /* For WinCE we only do this for pcrel fixups. */
27721 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27723 md_number_to_chars (buf
, value
, 4);
27727 case BFD_RELOC_ARM_PREL31
:
27728 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27730 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27731 if ((value
^ (value
>> 1)) & 0x40000000)
27733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27734 _("rel31 relocation overflow"));
27736 newval
|= value
& 0x7fffffff;
27737 md_number_to_chars (buf
, newval
, 4);
27742 case BFD_RELOC_ARM_CP_OFF_IMM
:
27743 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27744 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27745 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27746 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27748 newval
= get_thumb32_insn (buf
);
27749 if ((newval
& 0x0f200f00) == 0x0d000900)
27751 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27752 has permitted values that are multiples of 2, in the range 0
27754 if (value
< -510 || value
> 510 || (value
& 1))
27755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27756 _("co-processor offset out of range"));
27758 else if ((newval
& 0xfe001f80) == 0xec000f80)
27760 if (value
< -511 || value
> 512 || (value
& 3))
27761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27762 _("co-processor offset out of range"));
27764 else if (value
< -1023 || value
> 1023 || (value
& 3))
27765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27766 _("co-processor offset out of range"));
27771 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27772 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27773 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27775 newval
= get_thumb32_insn (buf
);
27778 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27779 newval
&= 0xffffff80;
27781 newval
&= 0xffffff00;
27785 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27786 newval
&= 0xff7fff80;
27788 newval
&= 0xff7fff00;
27789 if ((newval
& 0x0f200f00) == 0x0d000900)
27791 /* This is a fp16 vstr/vldr.
27793 It requires the immediate offset in the instruction is shifted
27794 left by 1 to be a half-word offset.
27796 Here, left shift by 1 first, and later right shift by 2
27797 should get the right offset. */
27800 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
27802 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27803 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27804 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27806 put_thumb32_insn (buf
, newval
);
27809 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
27810 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
27811 if (value
< -255 || value
> 255)
27812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27813 _("co-processor offset out of range"));
27815 goto cp_off_common
;
27817 case BFD_RELOC_ARM_THUMB_OFFSET
:
27818 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27819 /* Exactly what ranges, and where the offset is inserted depends
27820 on the type of instruction, we can establish this from the
27822 switch (newval
>> 12)
27824 case 4: /* PC load. */
27825 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27826 forced to zero for these loads; md_pcrel_from has already
27827 compensated for this. */
27829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27830 _("invalid offset, target not word aligned (0x%08lX)"),
27831 (((unsigned long) fixP
->fx_frag
->fr_address
27832 + (unsigned long) fixP
->fx_where
) & ~3)
27833 + (unsigned long) value
);
27835 if (value
& ~0x3fc)
27836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27837 _("invalid offset, value too big (0x%08lX)"),
27840 newval
|= value
>> 2;
27843 case 9: /* SP load/store. */
27844 if (value
& ~0x3fc)
27845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27846 _("invalid offset, value too big (0x%08lX)"),
27848 newval
|= value
>> 2;
27851 case 6: /* Word load/store. */
27853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27854 _("invalid offset, value too big (0x%08lX)"),
27856 newval
|= value
<< 4; /* 6 - 2. */
27859 case 7: /* Byte load/store. */
27861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27862 _("invalid offset, value too big (0x%08lX)"),
27864 newval
|= value
<< 6;
27867 case 8: /* Halfword load/store. */
27869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27870 _("invalid offset, value too big (0x%08lX)"),
27872 newval
|= value
<< 5; /* 6 - 1. */
27876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27877 "Unable to process relocation for thumb opcode: %lx",
27878 (unsigned long) newval
);
27881 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27884 case BFD_RELOC_ARM_THUMB_ADD
:
27885 /* This is a complicated relocation, since we use it for all of
27886 the following immediate relocations:
27890 9bit ADD/SUB SP word-aligned
27891 10bit ADD PC/SP word-aligned
27893 The type of instruction being processed is encoded in the
27900 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27902 int rd
= (newval
>> 4) & 0xf;
27903 int rs
= newval
& 0xf;
27904 int subtract
= !!(newval
& 0x8000);
27906 /* Check for HI regs, only very restricted cases allowed:
27907 Adjusting SP, and using PC or SP to get an address. */
27908 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
27909 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
27910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27911 _("invalid Hi register with immediate"));
27913 /* If value is negative, choose the opposite instruction. */
27917 subtract
= !subtract
;
27919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27920 _("immediate value out of range"));
27925 if (value
& ~0x1fc)
27926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27927 _("invalid immediate for stack address calculation"));
27928 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
27929 newval
|= value
>> 2;
27931 else if (rs
== REG_PC
|| rs
== REG_SP
)
27933 /* PR gas/18541. If the addition is for a defined symbol
27934 within range of an ADR instruction then accept it. */
27937 && fixP
->fx_addsy
!= NULL
)
27941 if (! S_IS_DEFINED (fixP
->fx_addsy
)
27942 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
27943 || S_IS_WEAK (fixP
->fx_addsy
))
27945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27946 _("address calculation needs a strongly defined nearby symbol"));
27950 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27952 /* Round up to the next 4-byte boundary. */
27957 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
27961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27962 _("symbol too far away"));
27972 if (subtract
|| value
& ~0x3fc)
27973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27974 _("invalid immediate for address calculation (value = 0x%08lX)"),
27975 (unsigned long) (subtract
? - value
: value
));
27976 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
27978 newval
|= value
>> 2;
27983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27984 _("immediate value out of range"));
27985 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
27986 newval
|= (rd
<< 8) | value
;
27991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27992 _("immediate value out of range"));
27993 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
27994 newval
|= rd
| (rs
<< 3) | (value
<< 6);
27997 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28000 case BFD_RELOC_ARM_THUMB_IMM
:
28001 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28002 if (value
< 0 || value
> 255)
28003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28004 _("invalid immediate: %ld is out of range"),
28007 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28010 case BFD_RELOC_ARM_THUMB_SHIFT
:
28011 /* 5bit shift value (0..32). LSL cannot take 32. */
28012 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28013 temp
= newval
& 0xf800;
28014 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28016 _("invalid shift value: %ld"), (long) value
);
28017 /* Shifts of zero must be encoded as LSL. */
28019 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28020 /* Shifts of 32 are encoded as zero. */
28021 else if (value
== 32)
28023 newval
|= value
<< 6;
28024 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28027 case BFD_RELOC_VTABLE_INHERIT
:
28028 case BFD_RELOC_VTABLE_ENTRY
:
28032 case BFD_RELOC_ARM_MOVW
:
28033 case BFD_RELOC_ARM_MOVT
:
28034 case BFD_RELOC_ARM_THUMB_MOVW
:
28035 case BFD_RELOC_ARM_THUMB_MOVT
:
28036 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28038 /* REL format relocations are limited to a 16-bit addend. */
28039 if (!fixP
->fx_done
)
28041 if (value
< -0x8000 || value
> 0x7fff)
28042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28043 _("offset out of range"));
28045 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28046 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28051 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28052 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28054 newval
= get_thumb32_insn (buf
);
28055 newval
&= 0xfbf08f00;
28056 newval
|= (value
& 0xf000) << 4;
28057 newval
|= (value
& 0x0800) << 15;
28058 newval
|= (value
& 0x0700) << 4;
28059 newval
|= (value
& 0x00ff);
28060 put_thumb32_insn (buf
, newval
);
28064 newval
= md_chars_to_number (buf
, 4);
28065 newval
&= 0xfff0f000;
28066 newval
|= value
& 0x0fff;
28067 newval
|= (value
& 0xf000) << 4;
28068 md_number_to_chars (buf
, newval
, 4);
28073 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28074 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28075 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28076 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28077 gas_assert (!fixP
->fx_done
);
28080 bfd_boolean is_mov
;
28081 bfd_vma encoded_addend
= value
;
28083 /* Check that addend can be encoded in instruction. */
28084 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28086 _("the offset 0x%08lX is not representable"),
28087 (unsigned long) encoded_addend
);
28089 /* Extract the instruction. */
28090 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28091 is_mov
= (insn
& 0xf800) == 0x2000;
28096 if (!seg
->use_rela_p
)
28097 insn
|= encoded_addend
;
28103 /* Extract the instruction. */
28104 /* Encoding is the following
28109 /* The following conditions must be true :
28114 rd
= (insn
>> 4) & 0xf;
28116 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28118 _("Unable to process relocation for thumb opcode: %lx"),
28119 (unsigned long) insn
);
28121 /* Encode as ADD immediate8 thumb 1 code. */
28122 insn
= 0x3000 | (rd
<< 8);
28124 /* Place the encoded addend into the first 8 bits of the
28126 if (!seg
->use_rela_p
)
28127 insn
|= encoded_addend
;
28130 /* Update the instruction. */
28131 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28135 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28136 case BFD_RELOC_ARM_ALU_PC_G0
:
28137 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28138 case BFD_RELOC_ARM_ALU_PC_G1
:
28139 case BFD_RELOC_ARM_ALU_PC_G2
:
28140 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28141 case BFD_RELOC_ARM_ALU_SB_G0
:
28142 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28143 case BFD_RELOC_ARM_ALU_SB_G1
:
28144 case BFD_RELOC_ARM_ALU_SB_G2
:
28145 gas_assert (!fixP
->fx_done
);
28146 if (!seg
->use_rela_p
)
28149 bfd_vma encoded_addend
;
28150 bfd_vma addend_abs
= llabs (value
);
28152 /* Check that the absolute value of the addend can be
28153 expressed as an 8-bit constant plus a rotation. */
28154 encoded_addend
= encode_arm_immediate (addend_abs
);
28155 if (encoded_addend
== (unsigned int) FAIL
)
28156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28157 _("the offset 0x%08lX is not representable"),
28158 (unsigned long) addend_abs
);
28160 /* Extract the instruction. */
28161 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28163 /* If the addend is positive, use an ADD instruction.
28164 Otherwise use a SUB. Take care not to destroy the S bit. */
28165 insn
&= 0xff1fffff;
28171 /* Place the encoded addend into the first 12 bits of the
28173 insn
&= 0xfffff000;
28174 insn
|= encoded_addend
;
28176 /* Update the instruction. */
28177 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28181 case BFD_RELOC_ARM_LDR_PC_G0
:
28182 case BFD_RELOC_ARM_LDR_PC_G1
:
28183 case BFD_RELOC_ARM_LDR_PC_G2
:
28184 case BFD_RELOC_ARM_LDR_SB_G0
:
28185 case BFD_RELOC_ARM_LDR_SB_G1
:
28186 case BFD_RELOC_ARM_LDR_SB_G2
:
28187 gas_assert (!fixP
->fx_done
);
28188 if (!seg
->use_rela_p
)
28191 bfd_vma addend_abs
= llabs (value
);
28193 /* Check that the absolute value of the addend can be
28194 encoded in 12 bits. */
28195 if (addend_abs
>= 0x1000)
28196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28197 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28198 (unsigned long) addend_abs
);
28200 /* Extract the instruction. */
28201 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28203 /* If the addend is negative, clear bit 23 of the instruction.
28204 Otherwise set it. */
28206 insn
&= ~(1 << 23);
28210 /* Place the absolute value of the addend into the first 12 bits
28211 of the instruction. */
28212 insn
&= 0xfffff000;
28213 insn
|= addend_abs
;
28215 /* Update the instruction. */
28216 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28220 case BFD_RELOC_ARM_LDRS_PC_G0
:
28221 case BFD_RELOC_ARM_LDRS_PC_G1
:
28222 case BFD_RELOC_ARM_LDRS_PC_G2
:
28223 case BFD_RELOC_ARM_LDRS_SB_G0
:
28224 case BFD_RELOC_ARM_LDRS_SB_G1
:
28225 case BFD_RELOC_ARM_LDRS_SB_G2
:
28226 gas_assert (!fixP
->fx_done
);
28227 if (!seg
->use_rela_p
)
28230 bfd_vma addend_abs
= llabs (value
);
28232 /* Check that the absolute value of the addend can be
28233 encoded in 8 bits. */
28234 if (addend_abs
>= 0x100)
28235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28236 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28237 (unsigned long) addend_abs
);
28239 /* Extract the instruction. */
28240 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28242 /* If the addend is negative, clear bit 23 of the instruction.
28243 Otherwise set it. */
28245 insn
&= ~(1 << 23);
28249 /* Place the first four bits of the absolute value of the addend
28250 into the first 4 bits of the instruction, and the remaining
28251 four into bits 8 .. 11. */
28252 insn
&= 0xfffff0f0;
28253 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28255 /* Update the instruction. */
28256 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28260 case BFD_RELOC_ARM_LDC_PC_G0
:
28261 case BFD_RELOC_ARM_LDC_PC_G1
:
28262 case BFD_RELOC_ARM_LDC_PC_G2
:
28263 case BFD_RELOC_ARM_LDC_SB_G0
:
28264 case BFD_RELOC_ARM_LDC_SB_G1
:
28265 case BFD_RELOC_ARM_LDC_SB_G2
:
28266 gas_assert (!fixP
->fx_done
);
28267 if (!seg
->use_rela_p
)
28270 bfd_vma addend_abs
= llabs (value
);
28272 /* Check that the absolute value of the addend is a multiple of
28273 four and, when divided by four, fits in 8 bits. */
28274 if (addend_abs
& 0x3)
28275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28276 _("bad offset 0x%08lX (must be word-aligned)"),
28277 (unsigned long) addend_abs
);
28279 if ((addend_abs
>> 2) > 0xff)
28280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28281 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28282 (unsigned long) addend_abs
);
28284 /* Extract the instruction. */
28285 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28287 /* If the addend is negative, clear bit 23 of the instruction.
28288 Otherwise set it. */
28290 insn
&= ~(1 << 23);
28294 /* Place the addend (divided by four) into the first eight
28295 bits of the instruction. */
28296 insn
&= 0xfffffff0;
28297 insn
|= addend_abs
>> 2;
28299 /* Update the instruction. */
28300 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28304 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28306 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28307 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28308 && ARM_IS_FUNC (fixP
->fx_addsy
)
28309 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28311 /* Force a relocation for a branch 5 bits wide. */
28314 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28318 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28320 addressT boff
= value
>> 1;
28322 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28323 newval
|= (boff
<< 7);
28324 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28328 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28330 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28331 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28332 && ARM_IS_FUNC (fixP
->fx_addsy
)
28333 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28337 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28339 _("branch out of range"));
28341 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28343 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28345 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28346 addressT diff
= value
- boff
;
28350 newval
|= 1 << 1; /* T bit. */
28352 else if (diff
!= 2)
28354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28355 _("out of range label-relative fixup value"));
28357 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28361 case BFD_RELOC_ARM_THUMB_BF17
:
28363 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28364 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28365 && ARM_IS_FUNC (fixP
->fx_addsy
)
28366 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28368 /* Force a relocation for a branch 17 bits wide. */
28372 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28376 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28379 addressT immA
, immB
, immC
;
28381 immA
= (value
& 0x0001f000) >> 12;
28382 immB
= (value
& 0x00000ffc) >> 2;
28383 immC
= (value
& 0x00000002) >> 1;
28385 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28386 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28388 newval2
|= (immC
<< 11) | (immB
<< 1);
28389 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28390 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28394 case BFD_RELOC_ARM_THUMB_BF19
:
28396 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28397 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28398 && ARM_IS_FUNC (fixP
->fx_addsy
)
28399 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28401 /* Force a relocation for a branch 19 bits wide. */
28405 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28409 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28412 addressT immA
, immB
, immC
;
28414 immA
= (value
& 0x0007f000) >> 12;
28415 immB
= (value
& 0x00000ffc) >> 2;
28416 immC
= (value
& 0x00000002) >> 1;
28418 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28419 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28421 newval2
|= (immC
<< 11) | (immB
<< 1);
28422 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28423 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28427 case BFD_RELOC_ARM_THUMB_BF13
:
28429 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28430 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28431 && ARM_IS_FUNC (fixP
->fx_addsy
)
28432 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28434 /* Force a relocation for a branch 13 bits wide. */
28438 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28442 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28445 addressT immA
, immB
, immC
;
28447 immA
= (value
& 0x00001000) >> 12;
28448 immB
= (value
& 0x00000ffc) >> 2;
28449 immC
= (value
& 0x00000002) >> 1;
28451 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28452 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28454 newval2
|= (immC
<< 11) | (immB
<< 1);
28455 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28456 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28460 case BFD_RELOC_ARM_THUMB_LOOP12
:
28462 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28463 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28464 && ARM_IS_FUNC (fixP
->fx_addsy
)
28465 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28467 /* Force a relocation for a branch 12 bits wide. */
28471 bfd_vma insn
= get_thumb32_insn (buf
);
28472 /* le lr, <label> or le <label> */
28473 if (((insn
& 0xffffffff) == 0xf00fc001)
28474 || ((insn
& 0xffffffff) == 0xf02fc001))
28477 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28480 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28482 addressT imml
, immh
;
28484 immh
= (value
& 0x00000ffc) >> 2;
28485 imml
= (value
& 0x00000002) >> 1;
28487 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28488 newval
|= (imml
<< 11) | (immh
<< 1);
28489 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28493 case BFD_RELOC_ARM_V4BX
:
28494 /* This will need to go in the object file. */
28498 case BFD_RELOC_UNUSED
:
28500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28501 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28505 /* Translate internal representation of relocation info to BFD target
28509 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28512 bfd_reloc_code_real_type code
;
28514 reloc
= XNEW (arelent
);
28516 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28517 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28518 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28520 if (fixp
->fx_pcrel
)
28522 if (section
->use_rela_p
)
28523 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28525 fixp
->fx_offset
= reloc
->address
;
28527 reloc
->addend
= fixp
->fx_offset
;
28529 switch (fixp
->fx_r_type
)
28532 if (fixp
->fx_pcrel
)
28534 code
= BFD_RELOC_8_PCREL
;
28537 /* Fall through. */
28540 if (fixp
->fx_pcrel
)
28542 code
= BFD_RELOC_16_PCREL
;
28545 /* Fall through. */
28548 if (fixp
->fx_pcrel
)
28550 code
= BFD_RELOC_32_PCREL
;
28553 /* Fall through. */
28555 case BFD_RELOC_ARM_MOVW
:
28556 if (fixp
->fx_pcrel
)
28558 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28561 /* Fall through. */
28563 case BFD_RELOC_ARM_MOVT
:
28564 if (fixp
->fx_pcrel
)
28566 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28569 /* Fall through. */
28571 case BFD_RELOC_ARM_THUMB_MOVW
:
28572 if (fixp
->fx_pcrel
)
28574 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28577 /* Fall through. */
28579 case BFD_RELOC_ARM_THUMB_MOVT
:
28580 if (fixp
->fx_pcrel
)
28582 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28585 /* Fall through. */
28587 case BFD_RELOC_NONE
:
28588 case BFD_RELOC_ARM_PCREL_BRANCH
:
28589 case BFD_RELOC_ARM_PCREL_BLX
:
28590 case BFD_RELOC_RVA
:
28591 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28592 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28593 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28594 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28595 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28596 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28597 case BFD_RELOC_VTABLE_ENTRY
:
28598 case BFD_RELOC_VTABLE_INHERIT
:
28600 case BFD_RELOC_32_SECREL
:
28602 code
= fixp
->fx_r_type
;
28605 case BFD_RELOC_THUMB_PCREL_BLX
:
28607 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28608 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28611 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28614 case BFD_RELOC_ARM_LITERAL
:
28615 case BFD_RELOC_ARM_HWLITERAL
:
28616 /* If this is called then the a literal has
28617 been referenced across a section boundary. */
28618 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28619 _("literal referenced across section boundary"));
28623 case BFD_RELOC_ARM_TLS_CALL
:
28624 case BFD_RELOC_ARM_THM_TLS_CALL
:
28625 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28626 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28627 case BFD_RELOC_ARM_GOT32
:
28628 case BFD_RELOC_ARM_GOTOFF
:
28629 case BFD_RELOC_ARM_GOT_PREL
:
28630 case BFD_RELOC_ARM_PLT32
:
28631 case BFD_RELOC_ARM_TARGET1
:
28632 case BFD_RELOC_ARM_ROSEGREL32
:
28633 case BFD_RELOC_ARM_SBREL32
:
28634 case BFD_RELOC_ARM_PREL31
:
28635 case BFD_RELOC_ARM_TARGET2
:
28636 case BFD_RELOC_ARM_TLS_LDO32
:
28637 case BFD_RELOC_ARM_PCREL_CALL
:
28638 case BFD_RELOC_ARM_PCREL_JUMP
:
28639 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28640 case BFD_RELOC_ARM_ALU_PC_G0
:
28641 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28642 case BFD_RELOC_ARM_ALU_PC_G1
:
28643 case BFD_RELOC_ARM_ALU_PC_G2
:
28644 case BFD_RELOC_ARM_LDR_PC_G0
:
28645 case BFD_RELOC_ARM_LDR_PC_G1
:
28646 case BFD_RELOC_ARM_LDR_PC_G2
:
28647 case BFD_RELOC_ARM_LDRS_PC_G0
:
28648 case BFD_RELOC_ARM_LDRS_PC_G1
:
28649 case BFD_RELOC_ARM_LDRS_PC_G2
:
28650 case BFD_RELOC_ARM_LDC_PC_G0
:
28651 case BFD_RELOC_ARM_LDC_PC_G1
:
28652 case BFD_RELOC_ARM_LDC_PC_G2
:
28653 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28654 case BFD_RELOC_ARM_ALU_SB_G0
:
28655 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28656 case BFD_RELOC_ARM_ALU_SB_G1
:
28657 case BFD_RELOC_ARM_ALU_SB_G2
:
28658 case BFD_RELOC_ARM_LDR_SB_G0
:
28659 case BFD_RELOC_ARM_LDR_SB_G1
:
28660 case BFD_RELOC_ARM_LDR_SB_G2
:
28661 case BFD_RELOC_ARM_LDRS_SB_G0
:
28662 case BFD_RELOC_ARM_LDRS_SB_G1
:
28663 case BFD_RELOC_ARM_LDRS_SB_G2
:
28664 case BFD_RELOC_ARM_LDC_SB_G0
:
28665 case BFD_RELOC_ARM_LDC_SB_G1
:
28666 case BFD_RELOC_ARM_LDC_SB_G2
:
28667 case BFD_RELOC_ARM_V4BX
:
28668 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28669 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28670 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28671 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28672 case BFD_RELOC_ARM_GOTFUNCDESC
:
28673 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28674 case BFD_RELOC_ARM_FUNCDESC
:
28675 case BFD_RELOC_ARM_THUMB_BF17
:
28676 case BFD_RELOC_ARM_THUMB_BF19
:
28677 case BFD_RELOC_ARM_THUMB_BF13
:
28678 code
= fixp
->fx_r_type
;
28681 case BFD_RELOC_ARM_TLS_GOTDESC
:
28682 case BFD_RELOC_ARM_TLS_GD32
:
28683 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28684 case BFD_RELOC_ARM_TLS_LE32
:
28685 case BFD_RELOC_ARM_TLS_IE32
:
28686 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28687 case BFD_RELOC_ARM_TLS_LDM32
:
28688 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28689 /* BFD will include the symbol's address in the addend.
28690 But we don't want that, so subtract it out again here. */
28691 if (!S_IS_COMMON (fixp
->fx_addsy
))
28692 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28693 code
= fixp
->fx_r_type
;
28697 case BFD_RELOC_ARM_IMMEDIATE
:
28698 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28699 _("internal relocation (type: IMMEDIATE) not fixed up"));
28702 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28703 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28704 _("ADRL used for a symbol not defined in the same file"));
28707 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28708 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28709 case BFD_RELOC_ARM_THUMB_LOOP12
:
28710 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28711 _("%s used for a symbol not defined in the same file"),
28712 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28715 case BFD_RELOC_ARM_OFFSET_IMM
:
28716 if (section
->use_rela_p
)
28718 code
= fixp
->fx_r_type
;
28722 if (fixp
->fx_addsy
!= NULL
28723 && !S_IS_DEFINED (fixp
->fx_addsy
)
28724 && S_IS_LOCAL (fixp
->fx_addsy
))
28726 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28727 _("undefined local label `%s'"),
28728 S_GET_NAME (fixp
->fx_addsy
));
28732 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28733 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28740 switch (fixp
->fx_r_type
)
28742 case BFD_RELOC_NONE
: type
= "NONE"; break;
28743 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28744 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28745 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28746 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28747 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28748 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28749 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28750 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28751 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28752 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28753 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28754 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28755 default: type
= _("<unknown>"); break;
28757 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28758 _("cannot represent %s relocation in this object file format"),
28765 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28767 && fixp
->fx_addsy
== GOT_symbol
)
28769 code
= BFD_RELOC_ARM_GOTPC
;
28770 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
28774 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
28776 if (reloc
->howto
== NULL
)
28778 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28779 _("cannot represent %s relocation in this object file format"),
28780 bfd_get_reloc_code_name (code
));
28784 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28785 vtable entry to be used in the relocation's section offset. */
28786 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28787 reloc
->address
= fixp
->fx_offset
;
28792 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28795 cons_fix_new_arm (fragS
* frag
,
28799 bfd_reloc_code_real_type reloc
)
28804 FIXME: @@ Should look at CPU word size. */
28808 reloc
= BFD_RELOC_8
;
28811 reloc
= BFD_RELOC_16
;
28815 reloc
= BFD_RELOC_32
;
28818 reloc
= BFD_RELOC_64
;
28823 if (exp
->X_op
== O_secrel
)
28825 exp
->X_op
= O_symbol
;
28826 reloc
= BFD_RELOC_32_SECREL
;
28830 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
28833 #if defined (OBJ_COFF)
28835 arm_validate_fix (fixS
* fixP
)
28837 /* If the destination of the branch is a defined symbol which does not have
28838 the THUMB_FUNC attribute, then we must be calling a function which has
28839 the (interfacearm) attribute. We look for the Thumb entry point to that
28840 function and change the branch to refer to that function instead. */
28841 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
28842 && fixP
->fx_addsy
!= NULL
28843 && S_IS_DEFINED (fixP
->fx_addsy
)
28844 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
28846 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
28853 arm_force_relocation (struct fix
* fixp
)
28855 #if defined (OBJ_COFF) && defined (TE_PE)
28856 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
28860 /* In case we have a call or a branch to a function in ARM ISA mode from
28861 a thumb function or vice-versa force the relocation. These relocations
28862 are cleared off for some cores that might have blx and simple transformations
28866 switch (fixp
->fx_r_type
)
28868 case BFD_RELOC_ARM_PCREL_JUMP
:
28869 case BFD_RELOC_ARM_PCREL_CALL
:
28870 case BFD_RELOC_THUMB_PCREL_BLX
:
28871 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
28875 case BFD_RELOC_ARM_PCREL_BLX
:
28876 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28877 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28878 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28879 if (ARM_IS_FUNC (fixp
->fx_addsy
))
28888 /* Resolve these relocations even if the symbol is extern or weak.
28889 Technically this is probably wrong due to symbol preemption.
28890 In practice these relocations do not have enough range to be useful
28891 at dynamic link time, and some code (e.g. in the Linux kernel)
28892 expects these references to be resolved. */
28893 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
28894 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
28895 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
28896 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
28897 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28898 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
28899 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
28900 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
28901 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28902 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
28903 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
28904 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
28905 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
28906 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
28909 /* Always leave these relocations for the linker. */
28910 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28911 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28912 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28915 /* Always generate relocations against function symbols. */
28916 if (fixp
->fx_r_type
== BFD_RELOC_32
28918 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
28921 return generic_force_reloc (fixp
);
28924 #if defined (OBJ_ELF) || defined (OBJ_COFF)
28925 /* Relocations against function names must be left unadjusted,
28926 so that the linker can use this information to generate interworking
28927 stubs. The MIPS version of this function
28928 also prevents relocations that are mips-16 specific, but I do not
28929 know why it does this.
28932 There is one other problem that ought to be addressed here, but
28933 which currently is not: Taking the address of a label (rather
28934 than a function) and then later jumping to that address. Such
28935 addresses also ought to have their bottom bit set (assuming that
28936 they reside in Thumb code), but at the moment they will not. */
28939 arm_fix_adjustable (fixS
* fixP
)
28941 if (fixP
->fx_addsy
== NULL
)
28944 /* Preserve relocations against symbols with function type. */
28945 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
28948 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
28949 && fixP
->fx_subsy
== NULL
)
28952 /* We need the symbol name for the VTABLE entries. */
28953 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
28954 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28957 /* Don't allow symbols to be discarded on GOT related relocs. */
28958 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
28959 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
28960 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
28961 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
28962 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
28963 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
28964 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
28965 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
28966 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
28967 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
28968 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
28969 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
28970 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
28971 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
28972 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
28973 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
28974 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
28977 /* Similarly for group relocations. */
28978 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28979 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28980 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28983 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28984 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
28985 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28986 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
28987 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
28988 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28989 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
28990 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
28991 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
28994 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28995 offsets, so keep these symbols. */
28996 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28997 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29002 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29006 elf32_arm_target_format (void)
29009 return (target_big_endian
29010 ? "elf32-bigarm-symbian"
29011 : "elf32-littlearm-symbian");
29012 #elif defined (TE_VXWORKS)
29013 return (target_big_endian
29014 ? "elf32-bigarm-vxworks"
29015 : "elf32-littlearm-vxworks");
29016 #elif defined (TE_NACL)
29017 return (target_big_endian
29018 ? "elf32-bigarm-nacl"
29019 : "elf32-littlearm-nacl");
29023 if (target_big_endian
)
29024 return "elf32-bigarm-fdpic";
29026 return "elf32-littlearm-fdpic";
29030 if (target_big_endian
)
29031 return "elf32-bigarm";
29033 return "elf32-littlearm";
29039 armelf_frob_symbol (symbolS
* symp
,
29042 elf_frob_symbol (symp
, puntp
);
29046 /* MD interface: Finalization. */
29051 literal_pool
* pool
;
29053 /* Ensure that all the predication blocks are properly closed. */
29054 check_pred_blocks_finished ();
29056 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29058 /* Put it at the end of the relevant section. */
29059 subseg_set (pool
->section
, pool
->sub_section
);
29061 arm_elf_change_section ();
29068 /* Remove any excess mapping symbols generated for alignment frags in
29069 SEC. We may have created a mapping symbol before a zero byte
29070 alignment; remove it if there's a mapping symbol after the
29073 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29074 void *dummy ATTRIBUTE_UNUSED
)
29076 segment_info_type
*seginfo
= seg_info (sec
);
29079 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29082 for (fragp
= seginfo
->frchainP
->frch_root
;
29084 fragp
= fragp
->fr_next
)
29086 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29087 fragS
*next
= fragp
->fr_next
;
29089 /* Variable-sized frags have been converted to fixed size by
29090 this point. But if this was variable-sized to start with,
29091 there will be a fixed-size frag after it. So don't handle
29093 if (sym
== NULL
|| next
== NULL
)
29096 if (S_GET_VALUE (sym
) < next
->fr_address
)
29097 /* Not at the end of this frag. */
29099 know (S_GET_VALUE (sym
) == next
->fr_address
);
29103 if (next
->tc_frag_data
.first_map
!= NULL
)
29105 /* Next frag starts with a mapping symbol. Discard this
29107 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29111 if (next
->fr_next
== NULL
)
29113 /* This mapping symbol is at the end of the section. Discard
29115 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29116 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29120 /* As long as we have empty frags without any mapping symbols,
29122 /* If the next frag is non-empty and does not start with a
29123 mapping symbol, then this mapping symbol is required. */
29124 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29127 next
= next
->fr_next
;
29129 while (next
!= NULL
);
29134 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29138 arm_adjust_symtab (void)
29143 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29145 if (ARM_IS_THUMB (sym
))
29147 if (THUMB_IS_FUNC (sym
))
29149 /* Mark the symbol as a Thumb function. */
29150 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29151 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29152 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29154 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29155 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29157 as_bad (_("%s: unexpected function type: %d"),
29158 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29160 else switch (S_GET_STORAGE_CLASS (sym
))
29163 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29166 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29169 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29177 if (ARM_IS_INTERWORK (sym
))
29178 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29185 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29187 if (ARM_IS_THUMB (sym
))
29189 elf_symbol_type
* elf_sym
;
29191 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29192 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29194 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29195 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29197 /* If it's a .thumb_func, declare it as so,
29198 otherwise tag label as .code 16. */
29199 if (THUMB_IS_FUNC (sym
))
29200 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29201 ST_BRANCH_TO_THUMB
);
29202 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29203 elf_sym
->internal_elf_sym
.st_info
=
29204 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29209 /* Remove any overlapping mapping symbols generated by alignment frags. */
29210 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29211 /* Now do generic ELF adjustments. */
29212 elf_adjust_symtab ();
29216 /* MD interface: Initialization. */
29219 set_constant_flonums (void)
29223 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29224 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29228 /* Auto-select Thumb mode if it's the only available instruction set for the
29229 given architecture. */
29232 autoselect_thumb_from_cpu_variant (void)
29234 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29235 opcode_select (16);
29244 if ( (arm_ops_hsh
= hash_new ()) == NULL
29245 || (arm_cond_hsh
= hash_new ()) == NULL
29246 || (arm_vcond_hsh
= hash_new ()) == NULL
29247 || (arm_shift_hsh
= hash_new ()) == NULL
29248 || (arm_psr_hsh
= hash_new ()) == NULL
29249 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29250 || (arm_reg_hsh
= hash_new ()) == NULL
29251 || (arm_reloc_hsh
= hash_new ()) == NULL
29252 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29253 as_fatal (_("virtual memory exhausted"));
29255 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29256 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29257 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29258 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29259 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29260 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29261 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29262 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29263 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29264 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29265 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29266 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29267 (void *) (v7m_psrs
+ i
));
29268 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29269 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29271 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29273 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29274 (void *) (barrier_opt_names
+ i
));
29276 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29278 struct reloc_entry
* entry
= reloc_names
+ i
;
29280 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29281 /* This makes encode_branch() use the EABI versions of this relocation. */
29282 entry
->reloc
= BFD_RELOC_UNUSED
;
29284 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29288 set_constant_flonums ();
29290 /* Set the cpu variant based on the command-line options. We prefer
29291 -mcpu= over -march= if both are set (as for GCC); and we prefer
29292 -mfpu= over any other way of setting the floating point unit.
29293 Use of legacy options with new options are faulted. */
29296 if (mcpu_cpu_opt
|| march_cpu_opt
)
29297 as_bad (_("use of old and new-style options to set CPU type"));
29299 selected_arch
= *legacy_cpu
;
29301 else if (mcpu_cpu_opt
)
29303 selected_arch
= *mcpu_cpu_opt
;
29304 selected_ext
= *mcpu_ext_opt
;
29306 else if (march_cpu_opt
)
29308 selected_arch
= *march_cpu_opt
;
29309 selected_ext
= *march_ext_opt
;
29311 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29316 as_bad (_("use of old and new-style options to set FPU type"));
29318 selected_fpu
= *legacy_fpu
;
29321 selected_fpu
= *mfpu_opt
;
29324 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29325 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29326 /* Some environments specify a default FPU. If they don't, infer it
29327 from the processor. */
29329 selected_fpu
= *mcpu_fpu_opt
;
29330 else if (march_fpu_opt
)
29331 selected_fpu
= *march_fpu_opt
;
29333 selected_fpu
= fpu_default
;
29337 if (ARM_FEATURE_ZERO (selected_fpu
))
29339 if (!no_cpu_selected ())
29340 selected_fpu
= fpu_default
;
29342 selected_fpu
= fpu_arch_fpa
;
29346 if (ARM_FEATURE_ZERO (selected_arch
))
29348 selected_arch
= cpu_default
;
29349 selected_cpu
= selected_arch
;
29351 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29353 /* Autodection of feature mode: allow all features in cpu_variant but leave
29354 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29355 after all instruction have been processed and we can decide what CPU
29356 should be selected. */
29357 if (ARM_FEATURE_ZERO (selected_arch
))
29358 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29360 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29363 autoselect_thumb_from_cpu_variant ();
29365 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29367 #if defined OBJ_COFF || defined OBJ_ELF
29369 unsigned int flags
= 0;
29371 #if defined OBJ_ELF
29372 flags
= meabi_flags
;
29374 switch (meabi_flags
)
29376 case EF_ARM_EABI_UNKNOWN
:
29378 /* Set the flags in the private structure. */
29379 if (uses_apcs_26
) flags
|= F_APCS26
;
29380 if (support_interwork
) flags
|= F_INTERWORK
;
29381 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29382 if (pic_code
) flags
|= F_PIC
;
29383 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29384 flags
|= F_SOFT_FLOAT
;
29386 switch (mfloat_abi_opt
)
29388 case ARM_FLOAT_ABI_SOFT
:
29389 case ARM_FLOAT_ABI_SOFTFP
:
29390 flags
|= F_SOFT_FLOAT
;
29393 case ARM_FLOAT_ABI_HARD
:
29394 if (flags
& F_SOFT_FLOAT
)
29395 as_bad (_("hard-float conflicts with specified fpu"));
29399 /* Using pure-endian doubles (even if soft-float). */
29400 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29401 flags
|= F_VFP_FLOAT
;
29403 #if defined OBJ_ELF
29404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29405 flags
|= EF_ARM_MAVERICK_FLOAT
;
29408 case EF_ARM_EABI_VER4
:
29409 case EF_ARM_EABI_VER5
:
29410 /* No additional flags to set. */
29417 bfd_set_private_flags (stdoutput
, flags
);
29419 /* We have run out flags in the COFF header to encode the
29420 status of ATPCS support, so instead we create a dummy,
29421 empty, debug section called .arm.atpcs. */
29426 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29430 bfd_set_section_flags
29431 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29432 bfd_set_section_size (stdoutput
, sec
, 0);
29433 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29439 /* Record the CPU type as well. */
29440 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29441 mach
= bfd_mach_arm_iWMMXt2
;
29442 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29443 mach
= bfd_mach_arm_iWMMXt
;
29444 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29445 mach
= bfd_mach_arm_XScale
;
29446 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29447 mach
= bfd_mach_arm_ep9312
;
29448 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29449 mach
= bfd_mach_arm_5TE
;
29450 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29452 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29453 mach
= bfd_mach_arm_5T
;
29455 mach
= bfd_mach_arm_5
;
29457 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29459 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29460 mach
= bfd_mach_arm_4T
;
29462 mach
= bfd_mach_arm_4
;
29464 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29465 mach
= bfd_mach_arm_3M
;
29466 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29467 mach
= bfd_mach_arm_3
;
29468 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29469 mach
= bfd_mach_arm_2a
;
29470 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29471 mach
= bfd_mach_arm_2
;
29473 mach
= bfd_mach_arm_unknown
;
29475 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29478 /* Command line processing. */
29481 Invocation line includes a switch not recognized by the base assembler.
29482 See if it's a processor-specific option.
29484 This routine is somewhat complicated by the need for backwards
29485 compatibility (since older releases of gcc can't be changed).
29486 The new options try to make the interface as compatible as
29489 New options (supported) are:
29491 -mcpu=<cpu name> Assemble for selected processor
29492 -march=<architecture name> Assemble for selected architecture
29493 -mfpu=<fpu architecture> Assemble for selected FPU.
29494 -EB/-mbig-endian Big-endian
29495 -EL/-mlittle-endian Little-endian
29496 -k Generate PIC code
29497 -mthumb Start in Thumb mode
29498 -mthumb-interwork Code supports ARM/Thumb interworking
29500 -m[no-]warn-deprecated Warn about deprecated features
29501 -m[no-]warn-syms Warn when symbols match instructions
29503 For now we will also provide support for:
29505 -mapcs-32 32-bit Program counter
29506 -mapcs-26 26-bit Program counter
29507 -macps-float Floats passed in FP registers
29508 -mapcs-reentrant Reentrant code
29510 (sometime these will probably be replaced with -mapcs=<list of options>
29511 and -matpcs=<list of options>)
29513 The remaining options are only supported for back-wards compatibility.
29514 Cpu variants, the arm part is optional:
29515 -m[arm]1 Currently not supported.
29516 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29517 -m[arm]3 Arm 3 processor
29518 -m[arm]6[xx], Arm 6 processors
29519 -m[arm]7[xx][t][[d]m] Arm 7 processors
29520 -m[arm]8[10] Arm 8 processors
29521 -m[arm]9[20][tdmi] Arm 9 processors
29522 -mstrongarm[110[0]] StrongARM processors
29523 -mxscale XScale processors
29524 -m[arm]v[2345[t[e]]] Arm architectures
29525 -mall All (except the ARM1)
29527 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29528 -mfpe-old (No float load/store multiples)
29529 -mvfpxd VFP Single precision
29531 -mno-fpu Disable all floating point instructions
29533 The following CPU names are recognized:
29534 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29535 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29536 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29537 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29538 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29539 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29540 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29544 const char * md_shortopts
= "m:k";
29546 #ifdef ARM_BI_ENDIAN
29547 #define OPTION_EB (OPTION_MD_BASE + 0)
29548 #define OPTION_EL (OPTION_MD_BASE + 1)
29550 #if TARGET_BYTES_BIG_ENDIAN
29551 #define OPTION_EB (OPTION_MD_BASE + 0)
29553 #define OPTION_EL (OPTION_MD_BASE + 1)
29556 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29557 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29559 struct option md_longopts
[] =
29562 {"EB", no_argument
, NULL
, OPTION_EB
},
29565 {"EL", no_argument
, NULL
, OPTION_EL
},
29567 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29569 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29571 {NULL
, no_argument
, NULL
, 0}
29574 size_t md_longopts_size
= sizeof (md_longopts
);
29576 struct arm_option_table
29578 const char * option
; /* Option name to match. */
29579 const char * help
; /* Help information. */
29580 int * var
; /* Variable to change. */
29581 int value
; /* What to change it to. */
29582 const char * deprecated
; /* If non-null, print this message. */
29585 struct arm_option_table arm_opts
[] =
29587 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29588 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29589 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29590 &support_interwork
, 1, NULL
},
29591 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29592 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29593 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29595 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29596 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29597 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29598 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29601 /* These are recognized by the assembler, but have no affect on code. */
29602 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29603 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29605 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29606 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29607 &warn_on_deprecated
, 0, NULL
},
29608 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29609 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29610 {NULL
, NULL
, NULL
, 0, NULL
}
29613 struct arm_legacy_option_table
29615 const char * option
; /* Option name to match. */
29616 const arm_feature_set
** var
; /* Variable to change. */
29617 const arm_feature_set value
; /* What to change it to. */
29618 const char * deprecated
; /* If non-null, print this message. */
29621 const struct arm_legacy_option_table arm_legacy_opts
[] =
29623 /* DON'T add any new processors to this list -- we want the whole list
29624 to go away... Add them to the processors table instead. */
29625 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29626 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29627 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29628 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29629 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29630 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29631 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29632 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29633 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29634 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29635 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29636 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29637 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29638 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29639 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29640 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29641 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29642 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29643 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29644 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29645 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29646 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29647 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29648 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29649 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29650 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29651 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29652 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29653 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29654 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29655 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29656 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29657 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29658 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29659 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29660 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29661 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29662 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29663 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29664 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29665 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29666 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29667 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29668 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29669 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29670 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29671 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29672 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29673 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29674 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29675 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29676 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29677 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29678 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29679 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29680 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29681 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29682 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29683 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29684 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29685 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29686 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29687 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29688 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29689 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29690 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29691 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29692 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29693 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29694 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29695 N_("use -mcpu=strongarm110")},
29696 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29697 N_("use -mcpu=strongarm1100")},
29698 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29699 N_("use -mcpu=strongarm1110")},
29700 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29701 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29702 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29704 /* Architecture variants -- don't add any more to this list either. */
29705 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29706 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29707 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29708 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29709 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29710 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29711 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29712 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29713 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29714 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29715 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29716 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29717 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29718 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29719 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29720 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29721 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29722 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29724 /* Floating point variants -- don't add any more to this list either. */
29725 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29726 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29727 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29728 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29729 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29731 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29734 struct arm_cpu_option_table
29738 const arm_feature_set value
;
29739 const arm_feature_set ext
;
29740 /* For some CPUs we assume an FPU unless the user explicitly sets
29742 const arm_feature_set default_fpu
;
29743 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29745 const char * canonical_name
;
29748 /* This list should, at a minimum, contain all the cpu names
29749 recognized by GCC. */
29750 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29752 static const struct arm_cpu_option_table arm_cpus
[] =
29754 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29757 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29760 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29763 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29766 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29769 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
29772 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
29775 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
29778 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
29781 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
29784 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
29787 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
29790 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
29793 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
29796 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
29799 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
29802 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
29805 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
29808 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
29811 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
29814 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
29817 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
29820 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
29823 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
29826 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
29829 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
29832 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
29835 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
29838 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
29841 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
29844 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
29847 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
29850 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
29853 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
29856 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
29859 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
29862 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
29865 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
29868 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
29871 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
29874 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
29877 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
29880 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
29883 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
29886 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
29889 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
29893 /* For V5 or later processors we default to using VFP; but the user
29894 should really set the FPU type explicitly. */
29895 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
29898 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
29901 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29904 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29907 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
29910 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
29913 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
29916 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
29919 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
29922 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
29925 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
29928 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
29931 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
29934 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
29937 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
29940 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
29943 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
29946 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
29949 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
29952 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
29955 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
29958 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
29961 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
29964 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
29967 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
29970 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
29973 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
29976 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
29979 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
29982 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
29985 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
29988 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
29991 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
29994 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
29997 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30000 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30003 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30004 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30006 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30008 FPU_ARCH_NEON_VFP_V4
),
30009 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30010 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30011 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30012 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30013 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30014 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30015 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30017 FPU_ARCH_NEON_VFP_V4
),
30018 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30020 FPU_ARCH_NEON_VFP_V4
),
30021 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30023 FPU_ARCH_NEON_VFP_V4
),
30024 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30025 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30026 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30027 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30028 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30029 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30030 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30031 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30032 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30033 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30035 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30036 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30037 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30038 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30039 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30040 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30041 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30042 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30043 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30044 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30045 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30046 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30047 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30048 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30049 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30050 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30051 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30052 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30053 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30054 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30057 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30059 FPU_ARCH_VFP_V3D16
),
30060 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30061 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30063 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30064 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30065 FPU_ARCH_VFP_V3D16
),
30066 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30067 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30068 FPU_ARCH_VFP_V3D16
),
30069 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30070 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30071 FPU_ARCH_NEON_VFP_ARMV8
),
30072 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30073 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30075 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30078 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30081 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30084 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30087 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30090 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30093 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30096 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30097 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30098 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30099 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30100 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30101 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30102 /* ??? XSCALE is really an architecture. */
30103 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30107 /* ??? iwmmxt is not a processor. */
30108 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30111 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30114 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30119 ARM_CPU_OPT ("ep9312", "ARM920T",
30120 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30121 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30123 /* Marvell processors. */
30124 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30125 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30126 FPU_ARCH_VFP_V3D16
),
30127 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30128 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30129 FPU_ARCH_NEON_VFP_V4
),
30131 /* APM X-Gene family. */
30132 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30134 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30135 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30136 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30137 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30139 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30143 struct arm_ext_table
30147 const arm_feature_set merge
;
30148 const arm_feature_set clear
;
30151 struct arm_arch_option_table
30155 const arm_feature_set value
;
30156 const arm_feature_set default_fpu
;
30157 const struct arm_ext_table
* ext_table
;
30160 /* Used to add support for +E and +noE extension. */
30161 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30162 /* Used to add support for a +E extension. */
30163 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30164 /* Used to add support for a +noE extension. */
30165 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30167 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30168 ~0 & ~FPU_ENDIAN_PURE)
30170 static const struct arm_ext_table armv5te_ext_table
[] =
30172 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30173 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30176 static const struct arm_ext_table armv7_ext_table
[] =
30178 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30179 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30182 static const struct arm_ext_table armv7ve_ext_table
[] =
30184 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30185 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30186 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30187 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30188 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30189 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30190 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30192 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30193 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30195 /* Aliases for +simd. */
30196 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30198 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30199 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30200 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30202 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30205 static const struct arm_ext_table armv7a_ext_table
[] =
30207 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30208 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30209 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30210 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30211 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30212 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30213 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30215 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30216 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30218 /* Aliases for +simd. */
30219 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30220 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30222 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30223 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30225 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30226 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30227 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30230 static const struct arm_ext_table armv7r_ext_table
[] =
30232 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30233 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30234 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30235 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30236 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30237 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30238 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30239 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30240 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30243 static const struct arm_ext_table armv7em_ext_table
[] =
30245 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30246 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30247 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30248 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30249 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30250 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30251 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30254 static const struct arm_ext_table armv8a_ext_table
[] =
30256 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30257 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30258 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30259 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30261 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30262 should use the +simd option to turn on FP. */
30263 ARM_REMOVE ("fp", ALL_FP
),
30264 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30265 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30266 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30270 static const struct arm_ext_table armv81a_ext_table
[] =
30272 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30273 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30274 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30276 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30277 should use the +simd option to turn on FP. */
30278 ARM_REMOVE ("fp", ALL_FP
),
30279 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30280 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30281 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30284 static const struct arm_ext_table armv82a_ext_table
[] =
30286 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30287 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30288 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30289 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30290 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30291 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30293 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30294 should use the +simd option to turn on FP. */
30295 ARM_REMOVE ("fp", ALL_FP
),
30296 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30297 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30298 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30301 static const struct arm_ext_table armv84a_ext_table
[] =
30303 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30304 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30305 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30306 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30308 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30309 should use the +simd option to turn on FP. */
30310 ARM_REMOVE ("fp", ALL_FP
),
30311 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30312 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30313 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30316 static const struct arm_ext_table armv85a_ext_table
[] =
30318 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30319 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30320 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30321 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30323 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30324 should use the +simd option to turn on FP. */
30325 ARM_REMOVE ("fp", ALL_FP
),
30326 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30329 static const struct arm_ext_table armv8m_main_ext_table
[] =
30331 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30332 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30333 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30334 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30335 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30338 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30340 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30341 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30343 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30344 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30347 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30348 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30349 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30350 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30352 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30353 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30354 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30355 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30358 static const struct arm_ext_table armv8r_ext_table
[] =
30360 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30361 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30362 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30363 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30364 ARM_REMOVE ("fp", ALL_FP
),
30365 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30366 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30369 /* This list should, at a minimum, contain all the architecture names
30370 recognized by GCC. */
30371 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30372 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30373 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30375 static const struct arm_arch_option_table arm_archs
[] =
30377 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30378 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30379 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30380 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30381 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30382 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30383 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30384 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30385 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30386 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30387 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30388 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30389 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30390 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30391 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30392 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30393 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30394 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30395 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30396 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30397 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30398 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30399 kept to preserve existing behaviour. */
30400 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30401 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30402 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30403 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30404 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30405 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30406 kept to preserve existing behaviour. */
30407 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30408 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30409 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30410 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30411 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30412 /* The official spelling of the ARMv7 profile variants is the dashed form.
30413 Accept the non-dashed form for compatibility with old toolchains. */
30414 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30415 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30416 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30417 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30418 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30419 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30420 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30421 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30422 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30423 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30425 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30427 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30428 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30429 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30430 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30431 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30432 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30433 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30434 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30435 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30436 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30437 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30439 #undef ARM_ARCH_OPT
30441 /* ISA extensions in the co-processor and main instruction set space. */
30443 struct arm_option_extension_value_table
30447 const arm_feature_set merge_value
;
30448 const arm_feature_set clear_value
;
30449 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30450 indicates that an extension is available for all architectures while
30451 ARM_ANY marks an empty entry. */
30452 const arm_feature_set allowed_archs
[2];
30455 /* The following table must be in alphabetical order with a NULL last entry. */
30457 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30458 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30460 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30461 use the context sensitive approach using arm_ext_table's. */
30462 static const struct arm_option_extension_value_table arm_extensions
[] =
30464 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30465 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30466 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30467 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30468 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30469 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30470 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30472 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30473 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30474 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30475 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30476 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30477 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30478 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30480 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30481 | ARM_EXT2_FP16_FML
),
30482 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30483 | ARM_EXT2_FP16_FML
),
30485 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30486 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30487 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30488 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30489 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30490 Thumb divide instruction. Due to this having the same name as the
30491 previous entry, this will be ignored when doing command-line parsing and
30492 only considered by build attribute selection code. */
30493 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30494 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30495 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30496 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30497 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30498 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30499 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30500 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30501 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30502 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30503 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30504 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30505 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30506 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30507 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30508 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30509 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30510 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30511 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30512 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30515 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30516 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30517 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30518 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30519 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30520 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30521 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30524 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30525 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30526 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30527 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30528 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30529 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30530 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30531 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30533 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30534 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30535 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30536 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30537 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30541 /* ISA floating-point and Advanced SIMD extensions. */
30542 struct arm_option_fpu_value_table
30545 const arm_feature_set value
;
30548 /* This list should, at a minimum, contain all the fpu names
30549 recognized by GCC. */
30550 static const struct arm_option_fpu_value_table arm_fpus
[] =
30552 {"softfpa", FPU_NONE
},
30553 {"fpe", FPU_ARCH_FPE
},
30554 {"fpe2", FPU_ARCH_FPE
},
30555 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30556 {"fpa", FPU_ARCH_FPA
},
30557 {"fpa10", FPU_ARCH_FPA
},
30558 {"fpa11", FPU_ARCH_FPA
},
30559 {"arm7500fe", FPU_ARCH_FPA
},
30560 {"softvfp", FPU_ARCH_VFP
},
30561 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30562 {"vfp", FPU_ARCH_VFP_V2
},
30563 {"vfp9", FPU_ARCH_VFP_V2
},
30564 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30565 {"vfp10", FPU_ARCH_VFP_V2
},
30566 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30567 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30568 {"vfpv2", FPU_ARCH_VFP_V2
},
30569 {"vfpv3", FPU_ARCH_VFP_V3
},
30570 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30571 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30572 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30573 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30574 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30575 {"arm1020t", FPU_ARCH_VFP_V1
},
30576 {"arm1020e", FPU_ARCH_VFP_V2
},
30577 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30578 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30579 {"maverick", FPU_ARCH_MAVERICK
},
30580 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30581 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30582 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30583 {"vfpv4", FPU_ARCH_VFP_V4
},
30584 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30585 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30586 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30587 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30588 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30589 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30590 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30591 {"crypto-neon-fp-armv8",
30592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30593 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30594 {"crypto-neon-fp-armv8.1",
30595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30596 {NULL
, ARM_ARCH_NONE
}
30599 struct arm_option_value_table
30605 static const struct arm_option_value_table arm_float_abis
[] =
30607 {"hard", ARM_FLOAT_ABI_HARD
},
30608 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30609 {"soft", ARM_FLOAT_ABI_SOFT
},
30614 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30615 static const struct arm_option_value_table arm_eabis
[] =
30617 {"gnu", EF_ARM_EABI_UNKNOWN
},
30618 {"4", EF_ARM_EABI_VER4
},
30619 {"5", EF_ARM_EABI_VER5
},
30624 struct arm_long_option_table
30626 const char * option
; /* Substring to match. */
30627 const char * help
; /* Help information. */
30628 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30629 const char * deprecated
; /* If non-null, print this message. */
30633 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30634 arm_feature_set
*ext_set
,
30635 const struct arm_ext_table
*ext_table
)
30637 /* We insist on extensions being specified in alphabetical order, and with
30638 extensions being added before being removed. We achieve this by having
30639 the global ARM_EXTENSIONS table in alphabetical order, and using the
30640 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30641 or removing it (0) and only allowing it to change in the order
30643 const struct arm_option_extension_value_table
* opt
= NULL
;
30644 const arm_feature_set arm_any
= ARM_ANY
;
30645 int adding_value
= -1;
30647 while (str
!= NULL
&& *str
!= 0)
30654 as_bad (_("invalid architectural extension"));
30659 ext
= strchr (str
, '+');
30664 len
= strlen (str
);
30666 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30668 if (adding_value
!= 0)
30671 opt
= arm_extensions
;
30679 if (adding_value
== -1)
30682 opt
= arm_extensions
;
30684 else if (adding_value
!= 1)
30686 as_bad (_("must specify extensions to add before specifying "
30687 "those to remove"));
30694 as_bad (_("missing architectural extension"));
30698 gas_assert (adding_value
!= -1);
30699 gas_assert (opt
!= NULL
);
30701 if (ext_table
!= NULL
)
30703 const struct arm_ext_table
* ext_opt
= ext_table
;
30704 bfd_boolean found
= FALSE
;
30705 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30706 if (ext_opt
->name_len
== len
30707 && strncmp (ext_opt
->name
, str
, len
) == 0)
30711 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30712 /* TODO: Option not supported. When we remove the
30713 legacy table this case should error out. */
30716 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30720 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30721 /* TODO: Option not supported. When we remove the
30722 legacy table this case should error out. */
30724 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30736 /* Scan over the options table trying to find an exact match. */
30737 for (; opt
->name
!= NULL
; opt
++)
30738 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30740 int i
, nb_allowed_archs
=
30741 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30742 /* Check we can apply the extension to this architecture. */
30743 for (i
= 0; i
< nb_allowed_archs
; i
++)
30746 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30748 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30751 if (i
== nb_allowed_archs
)
30753 as_bad (_("extension does not apply to the base architecture"));
30757 /* Add or remove the extension. */
30759 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30761 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30763 /* Allowing Thumb division instructions for ARMv7 in autodetection
30764 rely on this break so that duplicate extensions (extensions
30765 with the same name as a previous extension in the list) are not
30766 considered for command-line parsing. */
30770 if (opt
->name
== NULL
)
30772 /* Did we fail to find an extension because it wasn't specified in
30773 alphabetical order, or because it does not exist? */
30775 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30776 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30779 if (opt
->name
== NULL
)
30780 as_bad (_("unknown architectural extension `%s'"), str
);
30782 as_bad (_("architectural extensions must be specified in "
30783 "alphabetical order"));
30789 /* We should skip the extension we've just matched the next time
30801 arm_parse_cpu (const char *str
)
30803 const struct arm_cpu_option_table
*opt
;
30804 const char *ext
= strchr (str
, '+');
30810 len
= strlen (str
);
30814 as_bad (_("missing cpu name `%s'"), str
);
30818 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
30819 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30821 mcpu_cpu_opt
= &opt
->value
;
30822 if (mcpu_ext_opt
== NULL
)
30823 mcpu_ext_opt
= XNEW (arm_feature_set
);
30824 *mcpu_ext_opt
= opt
->ext
;
30825 mcpu_fpu_opt
= &opt
->default_fpu
;
30826 if (opt
->canonical_name
)
30828 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
30829 strcpy (selected_cpu_name
, opt
->canonical_name
);
30835 if (len
>= sizeof selected_cpu_name
)
30836 len
= (sizeof selected_cpu_name
) - 1;
30838 for (i
= 0; i
< len
; i
++)
30839 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30840 selected_cpu_name
[i
] = 0;
30844 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
30849 as_bad (_("unknown cpu `%s'"), str
);
30854 arm_parse_arch (const char *str
)
30856 const struct arm_arch_option_table
*opt
;
30857 const char *ext
= strchr (str
, '+');
30863 len
= strlen (str
);
30867 as_bad (_("missing architecture name `%s'"), str
);
30871 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
30872 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30874 march_cpu_opt
= &opt
->value
;
30875 if (march_ext_opt
== NULL
)
30876 march_ext_opt
= XNEW (arm_feature_set
);
30877 *march_ext_opt
= arm_arch_none
;
30878 march_fpu_opt
= &opt
->default_fpu
;
30879 strcpy (selected_cpu_name
, opt
->name
);
30882 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
30888 as_bad (_("unknown architecture `%s'\n"), str
);
30893 arm_parse_fpu (const char * str
)
30895 const struct arm_option_fpu_value_table
* opt
;
30897 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30898 if (streq (opt
->name
, str
))
30900 mfpu_opt
= &opt
->value
;
30904 as_bad (_("unknown floating point format `%s'\n"), str
);
30909 arm_parse_float_abi (const char * str
)
30911 const struct arm_option_value_table
* opt
;
30913 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
30914 if (streq (opt
->name
, str
))
30916 mfloat_abi_opt
= opt
->value
;
30920 as_bad (_("unknown floating point abi `%s'\n"), str
);
30926 arm_parse_eabi (const char * str
)
30928 const struct arm_option_value_table
*opt
;
30930 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
30931 if (streq (opt
->name
, str
))
30933 meabi_flags
= opt
->value
;
30936 as_bad (_("unknown EABI `%s'\n"), str
);
30942 arm_parse_it_mode (const char * str
)
30944 bfd_boolean ret
= TRUE
;
30946 if (streq ("arm", str
))
30947 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
30948 else if (streq ("thumb", str
))
30949 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
30950 else if (streq ("always", str
))
30951 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
30952 else if (streq ("never", str
))
30953 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
30956 as_bad (_("unknown implicit IT mode `%s', should be "\
30957 "arm, thumb, always, or never."), str
);
30965 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
30967 codecomposer_syntax
= TRUE
;
30968 arm_comment_chars
[0] = ';';
30969 arm_line_separator_chars
[0] = 0;
30973 struct arm_long_option_table arm_long_opts
[] =
30975 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30976 arm_parse_cpu
, NULL
},
30977 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30978 arm_parse_arch
, NULL
},
30979 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30980 arm_parse_fpu
, NULL
},
30981 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30982 arm_parse_float_abi
, NULL
},
30984 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30985 arm_parse_eabi
, NULL
},
30987 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30988 arm_parse_it_mode
, NULL
},
30989 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30990 arm_ccs_mode
, NULL
},
30991 {NULL
, NULL
, 0, NULL
}
30995 md_parse_option (int c
, const char * arg
)
30997 struct arm_option_table
*opt
;
30998 const struct arm_legacy_option_table
*fopt
;
30999 struct arm_long_option_table
*lopt
;
31005 target_big_endian
= 1;
31011 target_big_endian
= 0;
31015 case OPTION_FIX_V4BX
:
31023 #endif /* OBJ_ELF */
31026 /* Listing option. Just ignore these, we don't support additional
31031 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31033 if (c
== opt
->option
[0]
31034 && ((arg
== NULL
&& opt
->option
[1] == 0)
31035 || streq (arg
, opt
->option
+ 1)))
31037 /* If the option is deprecated, tell the user. */
31038 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31039 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31040 arg
? arg
: "", _(opt
->deprecated
));
31042 if (opt
->var
!= NULL
)
31043 *opt
->var
= opt
->value
;
31049 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31051 if (c
== fopt
->option
[0]
31052 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31053 || streq (arg
, fopt
->option
+ 1)))
31055 /* If the option is deprecated, tell the user. */
31056 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31057 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31058 arg
? arg
: "", _(fopt
->deprecated
));
31060 if (fopt
->var
!= NULL
)
31061 *fopt
->var
= &fopt
->value
;
31067 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31069 /* These options are expected to have an argument. */
31070 if (c
== lopt
->option
[0]
31072 && strncmp (arg
, lopt
->option
+ 1,
31073 strlen (lopt
->option
+ 1)) == 0)
31075 /* If the option is deprecated, tell the user. */
31076 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31077 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31078 _(lopt
->deprecated
));
31080 /* Call the sup-option parser. */
31081 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31092 md_show_usage (FILE * fp
)
31094 struct arm_option_table
*opt
;
31095 struct arm_long_option_table
*lopt
;
31097 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31099 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31100 if (opt
->help
!= NULL
)
31101 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31103 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31104 if (lopt
->help
!= NULL
)
31105 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31109 -EB assemble code for a big-endian cpu\n"));
31114 -EL assemble code for a little-endian cpu\n"));
31118 --fix-v4bx Allow BX in ARMv4 code\n"));
31122 --fdpic generate an FDPIC object file\n"));
31123 #endif /* OBJ_ELF */
31131 arm_feature_set flags
;
31132 } cpu_arch_ver_table
;
31134 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31135 chronologically for architectures, with an exception for ARMv6-M and
31136 ARMv6S-M due to legacy reasons. No new architecture should have a
31137 special case. This allows for build attribute selection results to be
31138 stable when new architectures are added. */
31139 static const cpu_arch_ver_table cpu_arch_ver
[] =
31141 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31142 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31143 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31144 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31145 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31146 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31147 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31148 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31149 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31150 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31151 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31152 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31153 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31154 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31155 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31156 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31157 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31158 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31159 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31160 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31161 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31162 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31163 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31164 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31166 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31167 always selected build attributes to match those of ARMv6-M
31168 (resp. ARMv6S-M). However, due to these architectures being a strict
31169 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31170 would be selected when fully respecting chronology of architectures.
31171 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31172 move them before ARMv7 architectures. */
31173 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31174 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31176 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31177 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31178 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31179 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31180 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31181 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31182 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31183 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31184 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31185 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31186 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31187 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31188 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31189 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31190 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31191 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31192 {-1, ARM_ARCH_NONE
}
31195 /* Set an attribute if it has not already been set by the user. */
31198 aeabi_set_attribute_int (int tag
, int value
)
31201 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31202 || !attributes_set_explicitly
[tag
])
31203 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31207 aeabi_set_attribute_string (int tag
, const char *value
)
31210 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31211 || !attributes_set_explicitly
[tag
])
31212 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31215 /* Return whether features in the *NEEDED feature set are available via
31216 extensions for the architecture whose feature set is *ARCH_FSET. */
31219 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31220 const arm_feature_set
*needed
)
31222 int i
, nb_allowed_archs
;
31223 arm_feature_set ext_fset
;
31224 const struct arm_option_extension_value_table
*opt
;
31226 ext_fset
= arm_arch_none
;
31227 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31229 /* Extension does not provide any feature we need. */
31230 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31234 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31235 for (i
= 0; i
< nb_allowed_archs
; i
++)
31238 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31241 /* Extension is available, add it. */
31242 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31243 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31247 /* Can we enable all features in *needed? */
31248 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31251 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31252 a given architecture feature set *ARCH_EXT_FSET including extension feature
31253 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31254 - if true, check for an exact match of the architecture modulo extensions;
31255 - otherwise, select build attribute value of the first superset
31256 architecture released so that results remains stable when new architectures
31258 For -march/-mcpu=all the build attribute value of the most featureful
31259 architecture is returned. Tag_CPU_arch_profile result is returned in
31263 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31264 const arm_feature_set
*ext_fset
,
31265 char *profile
, int exact_match
)
31267 arm_feature_set arch_fset
;
31268 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31270 /* Select most featureful architecture with all its extensions if building
31271 for -march=all as the feature sets used to set build attributes. */
31272 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31274 /* Force revisiting of decision for each new architecture. */
31275 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31277 return TAG_CPU_ARCH_V8
;
31280 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31282 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31284 arm_feature_set known_arch_fset
;
31286 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31289 /* Base architecture match user-specified architecture and
31290 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31291 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31296 /* Base architecture match user-specified architecture only
31297 (eg. ARMv6-M in the same case as above). Record it in case we
31298 find a match with above condition. */
31299 else if (p_ver_ret
== NULL
31300 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31306 /* Architecture has all features wanted. */
31307 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31309 arm_feature_set added_fset
;
31311 /* Compute features added by this architecture over the one
31312 recorded in p_ver_ret. */
31313 if (p_ver_ret
!= NULL
)
31314 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31316 /* First architecture that match incl. with extensions, or the
31317 only difference in features over the recorded match is
31318 features that were optional and are now mandatory. */
31319 if (p_ver_ret
== NULL
31320 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31326 else if (p_ver_ret
== NULL
)
31328 arm_feature_set needed_ext_fset
;
31330 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31332 /* Architecture has all features needed when using some
31333 extensions. Record it and continue searching in case there
31334 exist an architecture providing all needed features without
31335 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31337 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31344 if (p_ver_ret
== NULL
)
31348 /* Tag_CPU_arch_profile. */
31349 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31350 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31351 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31352 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31354 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31356 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31360 return p_ver_ret
->val
;
31363 /* Set the public EABI object attributes. */
31366 aeabi_set_public_attributes (void)
31368 char profile
= '\0';
31371 int fp16_optional
= 0;
31372 int skip_exact_match
= 0;
31373 arm_feature_set flags
, flags_arch
, flags_ext
;
31375 /* Autodetection mode, choose the architecture based the instructions
31377 if (no_cpu_selected ())
31379 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31381 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31382 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31384 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31385 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31387 /* Code run during relaxation relies on selected_cpu being set. */
31388 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31389 flags_ext
= arm_arch_none
;
31390 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31391 selected_ext
= flags_ext
;
31392 selected_cpu
= flags
;
31394 /* Otherwise, choose the architecture based on the capabilities of the
31398 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31399 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31400 flags_ext
= selected_ext
;
31401 flags
= selected_cpu
;
31403 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31405 /* Allow the user to override the reported architecture. */
31406 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31408 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31409 flags_ext
= arm_arch_none
;
31412 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31414 /* When this function is run again after relaxation has happened there is no
31415 way to determine whether an architecture or CPU was specified by the user:
31416 - selected_cpu is set above for relaxation to work;
31417 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31418 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31419 Therefore, if not in -march=all case we first try an exact match and fall
31420 back to autodetection. */
31421 if (!skip_exact_match
)
31422 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31424 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31426 as_bad (_("no architecture contains all the instructions used\n"));
31428 /* Tag_CPU_name. */
31429 if (selected_cpu_name
[0])
31433 q
= selected_cpu_name
;
31434 if (strncmp (q
, "armv", 4) == 0)
31439 for (i
= 0; q
[i
]; i
++)
31440 q
[i
] = TOUPPER (q
[i
]);
31442 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31445 /* Tag_CPU_arch. */
31446 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31448 /* Tag_CPU_arch_profile. */
31449 if (profile
!= '\0')
31450 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31452 /* Tag_DSP_extension. */
31453 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31454 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31456 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31457 /* Tag_ARM_ISA_use. */
31458 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31459 || ARM_FEATURE_ZERO (flags_arch
))
31460 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31462 /* Tag_THUMB_ISA_use. */
31463 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31464 || ARM_FEATURE_ZERO (flags_arch
))
31468 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31469 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31471 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31475 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31478 /* Tag_VFP_arch. */
31479 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31480 aeabi_set_attribute_int (Tag_VFP_arch
,
31481 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31483 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31484 aeabi_set_attribute_int (Tag_VFP_arch
,
31485 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31487 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31490 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31492 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31494 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31497 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31498 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31499 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31500 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31501 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31503 /* Tag_ABI_HardFP_use. */
31504 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31505 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31506 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31508 /* Tag_WMMX_arch. */
31509 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31510 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31511 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31512 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31514 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31515 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31516 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31517 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31518 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31519 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31521 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31523 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31527 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31532 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31533 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31534 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31535 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31537 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31538 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31539 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31543 We set Tag_DIV_use to two when integer divide instructions have been used
31544 in ARM state, or when Thumb integer divide instructions have been used,
31545 but we have no architecture profile set, nor have we any ARM instructions.
31547 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31548 by the base architecture.
31550 For new architectures we will have to check these tests. */
31551 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31552 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31553 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31554 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31555 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31556 || (profile
== '\0'
31557 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31558 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31559 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31561 /* Tag_MP_extension_use. */
31562 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31563 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31565 /* Tag Virtualization_use. */
31566 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31568 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31571 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31574 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31575 finished and free extension feature bits which will not be used anymore. */
31578 arm_md_post_relax (void)
31580 aeabi_set_public_attributes ();
31581 XDELETE (mcpu_ext_opt
);
31582 mcpu_ext_opt
= NULL
;
31583 XDELETE (march_ext_opt
);
31584 march_ext_opt
= NULL
;
31587 /* Add the default contents for the .ARM.attributes section. */
31592 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31595 aeabi_set_public_attributes ();
31597 #endif /* OBJ_ELF */
31599 /* Parse a .cpu directive. */
31602 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31604 const struct arm_cpu_option_table
*opt
;
31608 name
= input_line_pointer
;
31609 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31610 input_line_pointer
++;
31611 saved_char
= *input_line_pointer
;
31612 *input_line_pointer
= 0;
31614 /* Skip the first "all" entry. */
31615 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31616 if (streq (opt
->name
, name
))
31618 selected_arch
= opt
->value
;
31619 selected_ext
= opt
->ext
;
31620 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31621 if (opt
->canonical_name
)
31622 strcpy (selected_cpu_name
, opt
->canonical_name
);
31626 for (i
= 0; opt
->name
[i
]; i
++)
31627 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31629 selected_cpu_name
[i
] = 0;
31631 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31633 *input_line_pointer
= saved_char
;
31634 demand_empty_rest_of_line ();
31637 as_bad (_("unknown cpu `%s'"), name
);
31638 *input_line_pointer
= saved_char
;
31639 ignore_rest_of_line ();
31642 /* Parse a .arch directive. */
31645 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31647 const struct arm_arch_option_table
*opt
;
31651 name
= input_line_pointer
;
31652 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31653 input_line_pointer
++;
31654 saved_char
= *input_line_pointer
;
31655 *input_line_pointer
= 0;
31657 /* Skip the first "all" entry. */
31658 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31659 if (streq (opt
->name
, name
))
31661 selected_arch
= opt
->value
;
31662 selected_ext
= arm_arch_none
;
31663 selected_cpu
= selected_arch
;
31664 strcpy (selected_cpu_name
, opt
->name
);
31665 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31666 *input_line_pointer
= saved_char
;
31667 demand_empty_rest_of_line ();
31671 as_bad (_("unknown architecture `%s'\n"), name
);
31672 *input_line_pointer
= saved_char
;
31673 ignore_rest_of_line ();
31676 /* Parse a .object_arch directive. */
31679 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31681 const struct arm_arch_option_table
*opt
;
31685 name
= input_line_pointer
;
31686 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31687 input_line_pointer
++;
31688 saved_char
= *input_line_pointer
;
31689 *input_line_pointer
= 0;
31691 /* Skip the first "all" entry. */
31692 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31693 if (streq (opt
->name
, name
))
31695 selected_object_arch
= opt
->value
;
31696 *input_line_pointer
= saved_char
;
31697 demand_empty_rest_of_line ();
31701 as_bad (_("unknown architecture `%s'\n"), name
);
31702 *input_line_pointer
= saved_char
;
31703 ignore_rest_of_line ();
31706 /* Parse a .arch_extension directive. */
31709 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31711 const struct arm_option_extension_value_table
*opt
;
31714 int adding_value
= 1;
31716 name
= input_line_pointer
;
31717 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31718 input_line_pointer
++;
31719 saved_char
= *input_line_pointer
;
31720 *input_line_pointer
= 0;
31722 if (strlen (name
) >= 2
31723 && strncmp (name
, "no", 2) == 0)
31729 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31730 if (streq (opt
->name
, name
))
31732 int i
, nb_allowed_archs
=
31733 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31734 for (i
= 0; i
< nb_allowed_archs
; i
++)
31737 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31739 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31743 if (i
== nb_allowed_archs
)
31745 as_bad (_("architectural extension `%s' is not allowed for the "
31746 "current base architecture"), name
);
31751 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31754 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31756 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31757 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31758 *input_line_pointer
= saved_char
;
31759 demand_empty_rest_of_line ();
31760 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31761 on this return so that duplicate extensions (extensions with the
31762 same name as a previous extension in the list) are not considered
31763 for command-line parsing. */
31767 if (opt
->name
== NULL
)
31768 as_bad (_("unknown architecture extension `%s'\n"), name
);
31770 *input_line_pointer
= saved_char
;
31771 ignore_rest_of_line ();
31774 /* Parse a .fpu directive. */
31777 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
31779 const struct arm_option_fpu_value_table
*opt
;
31783 name
= input_line_pointer
;
31784 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31785 input_line_pointer
++;
31786 saved_char
= *input_line_pointer
;
31787 *input_line_pointer
= 0;
31789 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31790 if (streq (opt
->name
, name
))
31792 selected_fpu
= opt
->value
;
31793 #ifndef CPU_DEFAULT
31794 if (no_cpu_selected ())
31795 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
31798 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31799 *input_line_pointer
= saved_char
;
31800 demand_empty_rest_of_line ();
31804 as_bad (_("unknown floating point format `%s'\n"), name
);
31805 *input_line_pointer
= saved_char
;
31806 ignore_rest_of_line ();
31809 /* Copy symbol information. */
31812 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
31814 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
31818 /* Given a symbolic attribute NAME, return the proper integer value.
31819 Returns -1 if the attribute is not known. */
31822 arm_convert_symbolic_attribute (const char *name
)
31824 static const struct
31829 attribute_table
[] =
31831 /* When you modify this table you should
31832 also modify the list in doc/c-arm.texi. */
31833 #define T(tag) {#tag, tag}
31834 T (Tag_CPU_raw_name
),
31837 T (Tag_CPU_arch_profile
),
31838 T (Tag_ARM_ISA_use
),
31839 T (Tag_THUMB_ISA_use
),
31843 T (Tag_Advanced_SIMD_arch
),
31844 T (Tag_PCS_config
),
31845 T (Tag_ABI_PCS_R9_use
),
31846 T (Tag_ABI_PCS_RW_data
),
31847 T (Tag_ABI_PCS_RO_data
),
31848 T (Tag_ABI_PCS_GOT_use
),
31849 T (Tag_ABI_PCS_wchar_t
),
31850 T (Tag_ABI_FP_rounding
),
31851 T (Tag_ABI_FP_denormal
),
31852 T (Tag_ABI_FP_exceptions
),
31853 T (Tag_ABI_FP_user_exceptions
),
31854 T (Tag_ABI_FP_number_model
),
31855 T (Tag_ABI_align_needed
),
31856 T (Tag_ABI_align8_needed
),
31857 T (Tag_ABI_align_preserved
),
31858 T (Tag_ABI_align8_preserved
),
31859 T (Tag_ABI_enum_size
),
31860 T (Tag_ABI_HardFP_use
),
31861 T (Tag_ABI_VFP_args
),
31862 T (Tag_ABI_WMMX_args
),
31863 T (Tag_ABI_optimization_goals
),
31864 T (Tag_ABI_FP_optimization_goals
),
31865 T (Tag_compatibility
),
31866 T (Tag_CPU_unaligned_access
),
31867 T (Tag_FP_HP_extension
),
31868 T (Tag_VFP_HP_extension
),
31869 T (Tag_ABI_FP_16bit_format
),
31870 T (Tag_MPextension_use
),
31872 T (Tag_nodefaults
),
31873 T (Tag_also_compatible_with
),
31874 T (Tag_conformance
),
31876 T (Tag_Virtualization_use
),
31877 T (Tag_DSP_extension
),
31879 /* We deliberately do not include Tag_MPextension_use_legacy. */
31887 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
31888 if (streq (name
, attribute_table
[i
].name
))
31889 return attribute_table
[i
].tag
;
31894 /* Apply sym value for relocations only in the case that they are for
31895 local symbols in the same segment as the fixup and you have the
31896 respective architectural feature for blx and simple switches. */
31899 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
31902 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
31903 /* PR 17444: If the local symbol is in a different section then a reloc
31904 will always be generated for it, so applying the symbol value now
31905 will result in a double offset being stored in the relocation. */
31906 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
31907 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
31909 switch (fixP
->fx_r_type
)
31911 case BFD_RELOC_ARM_PCREL_BLX
:
31912 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
31913 if (ARM_IS_FUNC (fixP
->fx_addsy
))
31917 case BFD_RELOC_ARM_PCREL_CALL
:
31918 case BFD_RELOC_THUMB_PCREL_BLX
:
31919 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
31930 #endif /* OBJ_ELF */