1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_vfp_ext_armv8xd
=
240 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD
);
241 static const arm_feature_set fpu_neon_ext_armv8
=
242 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
243 static const arm_feature_set fpu_crypto_ext_armv8
=
244 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
245 static const arm_feature_set crc_ext_armv8
=
246 ARM_FEATURE (0, CRC_EXT_ARMV8
);
248 static int mfloat_abi_opt
= -1;
249 /* Record user cpu selection for object attributes. */
250 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
251 /* Must be long enough to hold any of the names in arm_cpus. */
252 static char selected_cpu_name
[16];
254 extern FLONUM_TYPE generic_floating_point_number
;
256 /* Return if no cpu was selected on command-line. */
258 no_cpu_selected (void)
260 return selected_cpu
.core
== arm_arch_none
.core
261 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
266 static int meabi_flags
= EABI_DEFAULT
;
268 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
271 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
276 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
281 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
282 symbolS
* GOT_symbol
;
285 /* 0: assemble for ARM,
286 1: assemble for Thumb,
287 2: assemble for Thumb even though target CPU does not support thumb
289 static int thumb_mode
= 0;
290 /* A value distinct from the possible values for thumb_mode that we
291 can use to record whether thumb_mode has been copied into the
292 tc_frag_data field of a frag. */
293 #define MODE_RECORDED (1 << 4)
295 /* Specifies the intrinsic IT insn behavior mode. */
296 enum implicit_it_mode
298 IMPLICIT_IT_MODE_NEVER
= 0x00,
299 IMPLICIT_IT_MODE_ARM
= 0x01,
300 IMPLICIT_IT_MODE_THUMB
= 0x02,
301 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
303 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
305 /* If unified_syntax is true, we are processing the new unified
306 ARM/Thumb syntax. Important differences from the old ARM mode:
308 - Immediate operands do not require a # prefix.
309 - Conditional affixes always appear at the end of the
310 instruction. (For backward compatibility, those instructions
311 that formerly had them in the middle, continue to accept them
313 - The IT instruction may appear, and if it does is validated
314 against subsequent conditional affixes. It does not generate
317 Important differences from the old Thumb mode:
319 - Immediate operands do not require a # prefix.
320 - Most of the V6T2 instructions are only available in unified mode.
321 - The .N and .W suffixes are recognized and honored (it is an error
322 if they cannot be honored).
323 - All instructions set the flags if and only if they have an 's' affix.
324 - Conditional affixes may be used. They are validated against
325 preceding IT instructions. Unlike ARM mode, you cannot use a
326 conditional affix except in the scope of an IT instruction. */
328 static bfd_boolean unified_syntax
= FALSE
;
330 /* An immediate operand can start with #, and ld*, st*, pld operands
331 can contain [ and ]. We need to tell APP not to elide whitespace
332 before a [, which can appear as the first operand for pld.
333 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
334 const char arm_symbol_chars
[] = "#[]{}";
349 enum neon_el_type type
;
353 #define NEON_MAX_TYPE_ELS 4
357 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
361 enum it_instruction_type
366 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
367 if inside, should be the last one. */
368 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
369 i.e. BKPT and NOP. */
370 IT_INSN
/* The IT insn has been parsed. */
373 /* The maximum number of operands we need. */
374 #define ARM_IT_MAX_OPERANDS 6
379 unsigned long instruction
;
383 /* "uncond_value" is set to the value in place of the conditional field in
384 unconditional versions of the instruction, or -1 if nothing is
387 struct neon_type vectype
;
388 /* This does not indicate an actual NEON instruction, only that
389 the mnemonic accepts neon-style type suffixes. */
391 /* Set to the opcode if the instruction needs relaxation.
392 Zero if the instruction is not relaxed. */
396 bfd_reloc_code_real_type type
;
401 enum it_instruction_type it_insn_type
;
407 struct neon_type_el vectype
;
408 unsigned present
: 1; /* Operand present. */
409 unsigned isreg
: 1; /* Operand was a register. */
410 unsigned immisreg
: 1; /* .imm field is a second register. */
411 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
412 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
413 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
414 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
415 instructions. This allows us to disambiguate ARM <-> vector insns. */
416 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
417 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
418 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
419 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
420 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
421 unsigned writeback
: 1; /* Operand has trailing ! */
422 unsigned preind
: 1; /* Preindexed address. */
423 unsigned postind
: 1; /* Postindexed address. */
424 unsigned negative
: 1; /* Index register was negated. */
425 unsigned shifted
: 1; /* Shift applied to operation. */
426 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
427 } operands
[ARM_IT_MAX_OPERANDS
];
430 static struct arm_it inst
;
432 #define NUM_FLOAT_VALS 8
434 const char * fp_const
[] =
436 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
439 /* Number of littlenums required to hold an extended precision number. */
440 #define MAX_LITTLENUMS 6
442 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
452 #define CP_T_X 0x00008000
453 #define CP_T_Y 0x00400000
455 #define CONDS_BIT 0x00100000
456 #define LOAD_BIT 0x00100000
458 #define DOUBLE_LOAD_FLAG 0x00000001
462 const char * template_name
;
466 #define COND_ALWAYS 0xE
470 const char * template_name
;
474 struct asm_barrier_opt
476 const char * template_name
;
478 const arm_feature_set arch
;
481 /* The bit that distinguishes CPSR and SPSR. */
482 #define SPSR_BIT (1 << 22)
484 /* The individual PSR flag bits. */
485 #define PSR_c (1 << 16)
486 #define PSR_x (1 << 17)
487 #define PSR_s (1 << 18)
488 #define PSR_f (1 << 19)
493 bfd_reloc_code_real_type reloc
;
498 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
499 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
504 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
507 /* Bits for DEFINED field in neon_typed_alias. */
508 #define NTA_HASTYPE 1
509 #define NTA_HASINDEX 2
511 struct neon_typed_alias
513 unsigned char defined
;
515 struct neon_type_el eltype
;
518 /* ARM register categories. This includes coprocessor numbers and various
519 architecture extensions' registers. */
546 /* Structure for a hash table entry for a register.
547 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
548 information which states whether a vector type or index is specified (for a
549 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
555 unsigned char builtin
;
556 struct neon_typed_alias
* neon
;
559 /* Diagnostics used when we don't get a register of the expected type. */
560 const char * const reg_expected_msgs
[] =
562 N_("ARM register expected"),
563 N_("bad or missing co-processor number"),
564 N_("co-processor register expected"),
565 N_("FPA register expected"),
566 N_("VFP single precision register expected"),
567 N_("VFP/Neon double precision register expected"),
568 N_("Neon quad precision register expected"),
569 N_("VFP single or double precision register expected"),
570 N_("Neon double or quad precision register expected"),
571 N_("VFP single, double or Neon quad precision register expected"),
572 N_("VFP system register expected"),
573 N_("Maverick MVF register expected"),
574 N_("Maverick MVD register expected"),
575 N_("Maverick MVFX register expected"),
576 N_("Maverick MVDX register expected"),
577 N_("Maverick MVAX register expected"),
578 N_("Maverick DSPSC register expected"),
579 N_("iWMMXt data register expected"),
580 N_("iWMMXt control register expected"),
581 N_("iWMMXt scalar register expected"),
582 N_("XScale accumulator register expected"),
585 /* Some well known registers that we refer to directly elsewhere. */
591 /* ARM instructions take 4bytes in the object file, Thumb instructions
597 /* Basic string to match. */
598 const char * template_name
;
600 /* Parameters to instruction. */
601 unsigned int operands
[8];
603 /* Conditional tag - see opcode_lookup. */
604 unsigned int tag
: 4;
606 /* Basic instruction code. */
607 unsigned int avalue
: 28;
609 /* Thumb-format instruction code. */
612 /* Which architecture variant provides this instruction. */
613 const arm_feature_set
* avariant
;
614 const arm_feature_set
* tvariant
;
616 /* Function to call to encode instruction in ARM format. */
617 void (* aencode
) (void);
619 /* Function to call to encode instruction in Thumb format. */
620 void (* tencode
) (void);
623 /* Defines for various bits that we will want to toggle. */
624 #define INST_IMMEDIATE 0x02000000
625 #define OFFSET_REG 0x02000000
626 #define HWOFFSET_IMM 0x00400000
627 #define SHIFT_BY_REG 0x00000010
628 #define PRE_INDEX 0x01000000
629 #define INDEX_UP 0x00800000
630 #define WRITE_BACK 0x00200000
631 #define LDM_TYPE_2_OR_3 0x00400000
632 #define CPSI_MMOD 0x00020000
634 #define LITERAL_MASK 0xf000f000
635 #define OPCODE_MASK 0xfe1fffff
636 #define V4_STR_BIT 0x00000020
637 #define VLDR_VMOV_SAME 0x0040f000
639 #define T2_SUBS_PC_LR 0xf3de8f00
641 #define DATA_OP_SHIFT 21
643 #define T2_OPCODE_MASK 0xfe1fffff
644 #define T2_DATA_OP_SHIFT 21
646 #define A_COND_MASK 0xf0000000
647 #define A_PUSH_POP_OP_MASK 0x0fff0000
649 /* Opcodes for pushing/poping registers to/from the stack. */
650 #define A1_OPCODE_PUSH 0x092d0000
651 #define A2_OPCODE_PUSH 0x052d0004
652 #define A2_OPCODE_POP 0x049d0004
654 /* Codes to distinguish the arithmetic instructions. */
665 #define OPCODE_CMP 10
666 #define OPCODE_CMN 11
667 #define OPCODE_ORR 12
668 #define OPCODE_MOV 13
669 #define OPCODE_BIC 14
670 #define OPCODE_MVN 15
672 #define T2_OPCODE_AND 0
673 #define T2_OPCODE_BIC 1
674 #define T2_OPCODE_ORR 2
675 #define T2_OPCODE_ORN 3
676 #define T2_OPCODE_EOR 4
677 #define T2_OPCODE_ADD 8
678 #define T2_OPCODE_ADC 10
679 #define T2_OPCODE_SBC 11
680 #define T2_OPCODE_SUB 13
681 #define T2_OPCODE_RSB 14
683 #define T_OPCODE_MUL 0x4340
684 #define T_OPCODE_TST 0x4200
685 #define T_OPCODE_CMN 0x42c0
686 #define T_OPCODE_NEG 0x4240
687 #define T_OPCODE_MVN 0x43c0
689 #define T_OPCODE_ADD_R3 0x1800
690 #define T_OPCODE_SUB_R3 0x1a00
691 #define T_OPCODE_ADD_HI 0x4400
692 #define T_OPCODE_ADD_ST 0xb000
693 #define T_OPCODE_SUB_ST 0xb080
694 #define T_OPCODE_ADD_SP 0xa800
695 #define T_OPCODE_ADD_PC 0xa000
696 #define T_OPCODE_ADD_I8 0x3000
697 #define T_OPCODE_SUB_I8 0x3800
698 #define T_OPCODE_ADD_I3 0x1c00
699 #define T_OPCODE_SUB_I3 0x1e00
701 #define T_OPCODE_ASR_R 0x4100
702 #define T_OPCODE_LSL_R 0x4080
703 #define T_OPCODE_LSR_R 0x40c0
704 #define T_OPCODE_ROR_R 0x41c0
705 #define T_OPCODE_ASR_I 0x1000
706 #define T_OPCODE_LSL_I 0x0000
707 #define T_OPCODE_LSR_I 0x0800
709 #define T_OPCODE_MOV_I8 0x2000
710 #define T_OPCODE_CMP_I8 0x2800
711 #define T_OPCODE_CMP_LR 0x4280
712 #define T_OPCODE_MOV_HR 0x4600
713 #define T_OPCODE_CMP_HR 0x4500
715 #define T_OPCODE_LDR_PC 0x4800
716 #define T_OPCODE_LDR_SP 0x9800
717 #define T_OPCODE_STR_SP 0x9000
718 #define T_OPCODE_LDR_IW 0x6800
719 #define T_OPCODE_STR_IW 0x6000
720 #define T_OPCODE_LDR_IH 0x8800
721 #define T_OPCODE_STR_IH 0x8000
722 #define T_OPCODE_LDR_IB 0x7800
723 #define T_OPCODE_STR_IB 0x7000
724 #define T_OPCODE_LDR_RW 0x5800
725 #define T_OPCODE_STR_RW 0x5000
726 #define T_OPCODE_LDR_RH 0x5a00
727 #define T_OPCODE_STR_RH 0x5200
728 #define T_OPCODE_LDR_RB 0x5c00
729 #define T_OPCODE_STR_RB 0x5400
731 #define T_OPCODE_PUSH 0xb400
732 #define T_OPCODE_POP 0xbc00
734 #define T_OPCODE_BRANCH 0xe000
736 #define THUMB_SIZE 2 /* Size of thumb instruction. */
737 #define THUMB_PP_PC_LR 0x0100
738 #define THUMB_LOAD_BIT 0x0800
739 #define THUMB2_LOAD_BIT 0x00100000
741 #define BAD_ARGS _("bad arguments to instruction")
742 #define BAD_SP _("r13 not allowed here")
743 #define BAD_PC _("r15 not allowed here")
744 #define BAD_COND _("instruction cannot be conditional")
745 #define BAD_OVERLAP _("registers may not be the same")
746 #define BAD_HIREG _("lo register required")
747 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
748 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
749 #define BAD_BRANCH _("branch must be last instruction in IT block")
750 #define BAD_NOT_IT _("instruction not allowed in IT block")
751 #define BAD_FPU _("selected FPU does not support instruction")
752 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
753 #define BAD_IT_COND _("incorrect condition in IT block")
754 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
755 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
756 #define BAD_PC_ADDRESSING \
757 _("cannot use register index with PC-relative addressing")
758 #define BAD_PC_WRITEBACK \
759 _("cannot use writeback with PC-relative addressing")
760 #define BAD_RANGE _("branch out of range")
761 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
763 static struct hash_control
* arm_ops_hsh
;
764 static struct hash_control
* arm_cond_hsh
;
765 static struct hash_control
* arm_shift_hsh
;
766 static struct hash_control
* arm_psr_hsh
;
767 static struct hash_control
* arm_v7m_psr_hsh
;
768 static struct hash_control
* arm_reg_hsh
;
769 static struct hash_control
* arm_reloc_hsh
;
770 static struct hash_control
* arm_barrier_opt_hsh
;
772 /* Stuff needed to resolve the label ambiguity
781 symbolS
* last_label_seen
;
782 static int label_is_thumb_function_name
= FALSE
;
784 /* Literal pool structure. Held on a per-section
785 and per-sub-section basis. */
787 #define MAX_LITERAL_POOL_SIZE 1024
788 typedef struct literal_pool
790 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
791 unsigned int next_free_entry
;
797 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
799 struct literal_pool
* next
;
800 unsigned int alignment
;
803 /* Pointer to a linked list of literal pools. */
804 literal_pool
* list_of_pools
= NULL
;
806 typedef enum asmfunc_states
809 WAITING_ASMFUNC_NAME
,
813 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
816 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
818 static struct current_it now_it
;
822 now_it_compatible (int cond
)
824 return (cond
& ~1) == (now_it
.cc
& ~1);
828 conditional_insn (void)
830 return inst
.cond
!= COND_ALWAYS
;
833 static int in_it_block (void);
835 static int handle_it_state (void);
837 static void force_automatic_it_block_close (void);
839 static void it_fsm_post_encode (void);
841 #define set_it_insn_type(type) \
844 inst.it_insn_type = type; \
845 if (handle_it_state () == FAIL) \
850 #define set_it_insn_type_nonvoid(type, failret) \
853 inst.it_insn_type = type; \
854 if (handle_it_state () == FAIL) \
859 #define set_it_insn_type_last() \
862 if (inst.cond == COND_ALWAYS) \
863 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
865 set_it_insn_type (INSIDE_IT_LAST_INSN); \
871 /* This array holds the chars that always start a comment. If the
872 pre-processor is disabled, these aren't very useful. */
873 char arm_comment_chars
[] = "@";
875 /* This array holds the chars that only start a comment at the beginning of
876 a line. If the line seems to have the form '# 123 filename'
877 .line and .file directives will appear in the pre-processed output. */
878 /* Note that input_file.c hand checks for '#' at the beginning of the
879 first line of the input file. This is because the compiler outputs
880 #NO_APP at the beginning of its output. */
881 /* Also note that comments like this one will always work. */
882 const char line_comment_chars
[] = "#";
884 char arm_line_separator_chars
[] = ";";
886 /* Chars that can be used to separate mant
887 from exp in floating point numbers. */
888 const char EXP_CHARS
[] = "eE";
890 /* Chars that mean this number is a floating point constant. */
894 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
896 /* Prefix characters that indicate the start of an immediate
898 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
900 /* Separator character handling. */
902 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
905 skip_past_char (char ** str
, char c
)
907 /* PR gas/14987: Allow for whitespace before the expected character. */
908 skip_whitespace (*str
);
919 #define skip_past_comma(str) skip_past_char (str, ',')
921 /* Arithmetic expressions (possibly involving symbols). */
923 /* Return TRUE if anything in the expression is a bignum. */
926 walk_no_bignums (symbolS
* sp
)
928 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
931 if (symbol_get_value_expression (sp
)->X_add_symbol
)
933 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
934 || (symbol_get_value_expression (sp
)->X_op_symbol
935 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
941 static int in_my_get_expression
= 0;
943 /* Third argument to my_get_expression. */
944 #define GE_NO_PREFIX 0
945 #define GE_IMM_PREFIX 1
946 #define GE_OPT_PREFIX 2
947 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
948 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
949 #define GE_OPT_PREFIX_BIG 3
952 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
957 /* In unified syntax, all prefixes are optional. */
959 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
964 case GE_NO_PREFIX
: break;
966 if (!is_immediate_prefix (**str
))
968 inst
.error
= _("immediate expression requires a # prefix");
974 case GE_OPT_PREFIX_BIG
:
975 if (is_immediate_prefix (**str
))
981 memset (ep
, 0, sizeof (expressionS
));
983 save_in
= input_line_pointer
;
984 input_line_pointer
= *str
;
985 in_my_get_expression
= 1;
986 seg
= expression (ep
);
987 in_my_get_expression
= 0;
989 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
991 /* We found a bad or missing expression in md_operand(). */
992 *str
= input_line_pointer
;
993 input_line_pointer
= save_in
;
994 if (inst
.error
== NULL
)
995 inst
.error
= (ep
->X_op
== O_absent
996 ? _("missing expression") :_("bad expression"));
1001 if (seg
!= absolute_section
1002 && seg
!= text_section
1003 && seg
!= data_section
1004 && seg
!= bss_section
1005 && seg
!= undefined_section
)
1007 inst
.error
= _("bad segment");
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1016 /* Get rid of any bignums now, so that we don't generate an error for which
1017 we can't establish a line number later on. Big numbers are never valid
1018 in instructions, which is where this routine is always called. */
1019 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1020 && (ep
->X_op
== O_big
1021 || (ep
->X_add_symbol
1022 && (walk_no_bignums (ep
->X_add_symbol
)
1024 && walk_no_bignums (ep
->X_op_symbol
))))))
1026 inst
.error
= _("invalid constant");
1027 *str
= input_line_pointer
;
1028 input_line_pointer
= save_in
;
1032 *str
= input_line_pointer
;
1033 input_line_pointer
= save_in
;
1037 /* Turn a string in input_line_pointer into a floating point constant
1038 of type TYPE, and store the appropriate bytes in *LITP. The number
1039 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1040 returned, or NULL on OK.
1042 Note that fp constants aren't represent in the normal way on the ARM.
1043 In big endian mode, things are as expected. However, in little endian
1044 mode fp constants are big-endian word-wise, and little-endian byte-wise
1045 within the words. For example, (double) 1.1 in big endian mode is
1046 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1047 the byte sequence 99 99 f1 3f 9a 99 99 99.
1049 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1052 md_atof (int type
, char * litP
, int * sizeP
)
1055 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1087 return _("Unrecognized or unsupported floating point constant");
1090 t
= atof_ieee (input_line_pointer
, type
, words
);
1092 input_line_pointer
= t
;
1093 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1095 if (target_big_endian
)
1097 for (i
= 0; i
< prec
; i
++)
1099 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1100 litP
+= sizeof (LITTLENUM_TYPE
);
1105 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1106 for (i
= prec
- 1; i
>= 0; i
--)
1108 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1109 litP
+= sizeof (LITTLENUM_TYPE
);
1112 /* For a 4 byte float the order of elements in `words' is 1 0.
1113 For an 8 byte float the order is 1 0 3 2. */
1114 for (i
= 0; i
< prec
; i
+= 2)
1116 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1117 sizeof (LITTLENUM_TYPE
));
1118 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1119 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1120 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1127 /* We handle all bad expressions here, so that we can report the faulty
1128 instruction in the error message. */
1130 md_operand (expressionS
* exp
)
1132 if (in_my_get_expression
)
1133 exp
->X_op
= O_illegal
;
1136 /* Immediate values. */
1138 /* Generic immediate-value read function for use in directives.
1139 Accepts anything that 'expression' can fold to a constant.
1140 *val receives the number. */
1143 immediate_for_directive (int *val
)
1146 exp
.X_op
= O_illegal
;
1148 if (is_immediate_prefix (*input_line_pointer
))
1150 input_line_pointer
++;
1154 if (exp
.X_op
!= O_constant
)
1156 as_bad (_("expected #constant"));
1157 ignore_rest_of_line ();
1160 *val
= exp
.X_add_number
;
1165 /* Register parsing. */
1167 /* Generic register parser. CCP points to what should be the
1168 beginning of a register name. If it is indeed a valid register
1169 name, advance CCP over it and return the reg_entry structure;
1170 otherwise return NULL. Does not issue diagnostics. */
1172 static struct reg_entry
*
1173 arm_reg_parse_multi (char **ccp
)
1177 struct reg_entry
*reg
;
1179 skip_whitespace (start
);
1181 #ifdef REGISTER_PREFIX
1182 if (*start
!= REGISTER_PREFIX
)
1186 #ifdef OPTIONAL_REGISTER_PREFIX
1187 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1192 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1197 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1199 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1209 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1210 enum arm_reg_type type
)
1212 /* Alternative syntaxes are accepted for a few register classes. */
1219 /* Generic coprocessor register names are allowed for these. */
1220 if (reg
&& reg
->type
== REG_TYPE_CN
)
1225 /* For backward compatibility, a bare number is valid here. */
1227 unsigned long processor
= strtoul (start
, ccp
, 10);
1228 if (*ccp
!= start
&& processor
<= 15)
1232 case REG_TYPE_MMXWC
:
1233 /* WC includes WCG. ??? I'm not sure this is true for all
1234 instructions that take WC registers. */
1235 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1246 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1247 return value is the register number or FAIL. */
1250 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1253 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1256 /* Do not allow a scalar (reg+index) to parse as a register. */
1257 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1260 if (reg
&& reg
->type
== type
)
1263 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1270 /* Parse a Neon type specifier. *STR should point at the leading '.'
1271 character. Does no verification at this stage that the type fits the opcode
1278 Can all be legally parsed by this function.
1280 Fills in neon_type struct pointer with parsed information, and updates STR
1281 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1282 type, FAIL if not. */
1285 parse_neon_type (struct neon_type
*type
, char **str
)
1292 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1294 enum neon_el_type thistype
= NT_untyped
;
1295 unsigned thissize
= -1u;
1302 /* Just a size without an explicit type. */
1306 switch (TOLOWER (*ptr
))
1308 case 'i': thistype
= NT_integer
; break;
1309 case 'f': thistype
= NT_float
; break;
1310 case 'p': thistype
= NT_poly
; break;
1311 case 's': thistype
= NT_signed
; break;
1312 case 'u': thistype
= NT_unsigned
; break;
1314 thistype
= NT_float
;
1319 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1325 /* .f is an abbreviation for .f32. */
1326 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1331 thissize
= strtoul (ptr
, &ptr
, 10);
1333 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1336 as_bad (_("bad size %d in type specifier"), thissize
);
1344 type
->el
[type
->elems
].type
= thistype
;
1345 type
->el
[type
->elems
].size
= thissize
;
1350 /* Empty/missing type is not a successful parse. */
1351 if (type
->elems
== 0)
1359 /* Errors may be set multiple times during parsing or bit encoding
1360 (particularly in the Neon bits), but usually the earliest error which is set
1361 will be the most meaningful. Avoid overwriting it with later (cascading)
1362 errors by calling this function. */
1365 first_error (const char *err
)
1371 /* Parse a single type, e.g. ".s32", leading period included. */
1373 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1376 struct neon_type optype
;
1380 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1382 if (optype
.elems
== 1)
1383 *vectype
= optype
.el
[0];
1386 first_error (_("only one type should be specified for operand"));
1392 first_error (_("vector type expected"));
1404 /* Special meanings for indices (which have a range of 0-7), which will fit into
1407 #define NEON_ALL_LANES 15
1408 #define NEON_INTERLEAVE_LANES 14
1410 /* Parse either a register or a scalar, with an optional type. Return the
1411 register number, and optionally fill in the actual type of the register
1412 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1413 type/index information in *TYPEINFO. */
1416 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1417 enum arm_reg_type
*rtype
,
1418 struct neon_typed_alias
*typeinfo
)
1421 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1422 struct neon_typed_alias atype
;
1423 struct neon_type_el parsetype
;
1427 atype
.eltype
.type
= NT_invtype
;
1428 atype
.eltype
.size
= -1;
1430 /* Try alternate syntax for some types of register. Note these are mutually
1431 exclusive with the Neon syntax extensions. */
1434 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1442 /* Undo polymorphism when a set of register types may be accepted. */
1443 if ((type
== REG_TYPE_NDQ
1444 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1445 || (type
== REG_TYPE_VFSD
1446 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1447 || (type
== REG_TYPE_NSDQ
1448 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1449 || reg
->type
== REG_TYPE_NQ
))
1450 || (type
== REG_TYPE_MMXWC
1451 && (reg
->type
== REG_TYPE_MMXWCG
)))
1452 type
= (enum arm_reg_type
) reg
->type
;
1454 if (type
!= reg
->type
)
1460 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1462 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1464 first_error (_("can't redefine type for operand"));
1467 atype
.defined
|= NTA_HASTYPE
;
1468 atype
.eltype
= parsetype
;
1471 if (skip_past_char (&str
, '[') == SUCCESS
)
1473 if (type
!= REG_TYPE_VFD
)
1475 first_error (_("only D registers may be indexed"));
1479 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1481 first_error (_("can't change index for operand"));
1485 atype
.defined
|= NTA_HASINDEX
;
1487 if (skip_past_char (&str
, ']') == SUCCESS
)
1488 atype
.index
= NEON_ALL_LANES
;
1493 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1495 if (exp
.X_op
!= O_constant
)
1497 first_error (_("constant expression required"));
1501 if (skip_past_char (&str
, ']') == FAIL
)
1504 atype
.index
= exp
.X_add_number
;
1519 /* Like arm_reg_parse, but allow allow the following extra features:
1520 - If RTYPE is non-zero, return the (possibly restricted) type of the
1521 register (e.g. Neon double or quad reg when either has been requested).
1522 - If this is a Neon vector type with additional type information, fill
1523 in the struct pointed to by VECTYPE (if non-NULL).
1524 This function will fault on encountering a scalar. */
1527 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1528 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1530 struct neon_typed_alias atype
;
1532 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1537 /* Do not allow regname(... to parse as a register. */
1541 /* Do not allow a scalar (reg+index) to parse as a register. */
1542 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1544 first_error (_("register operand expected, but got scalar"));
1549 *vectype
= atype
.eltype
;
1556 #define NEON_SCALAR_REG(X) ((X) >> 4)
1557 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1559 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1560 have enough information to be able to do a good job bounds-checking. So, we
1561 just do easy checks here, and do further checks later. */
1564 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1568 struct neon_typed_alias atype
;
1570 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1572 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1575 if (atype
.index
== NEON_ALL_LANES
)
1577 first_error (_("scalar must have an index"));
1580 else if (atype
.index
>= 64 / elsize
)
1582 first_error (_("scalar index out of range"));
1587 *type
= atype
.eltype
;
1591 return reg
* 16 + atype
.index
;
1594 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1597 parse_reg_list (char ** strp
)
1599 char * str
= * strp
;
1603 /* We come back here if we get ranges concatenated by '+' or '|'. */
1606 skip_whitespace (str
);
1620 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1622 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1632 first_error (_("bad range in register list"));
1636 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1638 if (range
& (1 << i
))
1640 (_("Warning: duplicated register (r%d) in register list"),
1648 if (range
& (1 << reg
))
1649 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1651 else if (reg
<= cur_reg
)
1652 as_tsktsk (_("Warning: register range not in ascending order"));
1657 while (skip_past_comma (&str
) != FAIL
1658 || (in_range
= 1, *str
++ == '-'));
1661 if (skip_past_char (&str
, '}') == FAIL
)
1663 first_error (_("missing `}'"));
1671 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1674 if (exp
.X_op
== O_constant
)
1676 if (exp
.X_add_number
1677 != (exp
.X_add_number
& 0x0000ffff))
1679 inst
.error
= _("invalid register mask");
1683 if ((range
& exp
.X_add_number
) != 0)
1685 int regno
= range
& exp
.X_add_number
;
1688 regno
= (1 << regno
) - 1;
1690 (_("Warning: duplicated register (r%d) in register list"),
1694 range
|= exp
.X_add_number
;
1698 if (inst
.reloc
.type
!= 0)
1700 inst
.error
= _("expression too complex");
1704 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1705 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1706 inst
.reloc
.pc_rel
= 0;
1710 if (*str
== '|' || *str
== '+')
1716 while (another_range
);
1722 /* Types of registers in a list. */
1731 /* Parse a VFP register list. If the string is invalid return FAIL.
1732 Otherwise return the number of registers, and set PBASE to the first
1733 register. Parses registers of type ETYPE.
1734 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1735 - Q registers can be used to specify pairs of D registers
1736 - { } can be omitted from around a singleton register list
1737 FIXME: This is not implemented, as it would require backtracking in
1740 This could be done (the meaning isn't really ambiguous), but doesn't
1741 fit in well with the current parsing framework.
1742 - 32 D registers may be used (also true for VFPv3).
1743 FIXME: Types are ignored in these register lists, which is probably a
1747 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1752 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1756 unsigned long mask
= 0;
1759 if (skip_past_char (&str
, '{') == FAIL
)
1761 inst
.error
= _("expecting {");
1768 regtype
= REG_TYPE_VFS
;
1773 regtype
= REG_TYPE_VFD
;
1776 case REGLIST_NEON_D
:
1777 regtype
= REG_TYPE_NDQ
;
1781 if (etype
!= REGLIST_VFP_S
)
1783 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1784 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1788 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1791 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1798 base_reg
= max_regs
;
1802 int setmask
= 1, addregs
= 1;
1804 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1806 if (new_base
== FAIL
)
1808 first_error (_(reg_expected_msgs
[regtype
]));
1812 if (new_base
>= max_regs
)
1814 first_error (_("register out of range in list"));
1818 /* Note: a value of 2 * n is returned for the register Q<n>. */
1819 if (regtype
== REG_TYPE_NQ
)
1825 if (new_base
< base_reg
)
1826 base_reg
= new_base
;
1828 if (mask
& (setmask
<< new_base
))
1830 first_error (_("invalid register list"));
1834 if ((mask
>> new_base
) != 0 && ! warned
)
1836 as_tsktsk (_("register list not in ascending order"));
1840 mask
|= setmask
<< new_base
;
1843 if (*str
== '-') /* We have the start of a range expression */
1849 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1852 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1856 if (high_range
>= max_regs
)
1858 first_error (_("register out of range in list"));
1862 if (regtype
== REG_TYPE_NQ
)
1863 high_range
= high_range
+ 1;
1865 if (high_range
<= new_base
)
1867 inst
.error
= _("register range not in ascending order");
1871 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1873 if (mask
& (setmask
<< new_base
))
1875 inst
.error
= _("invalid register list");
1879 mask
|= setmask
<< new_base
;
1884 while (skip_past_comma (&str
) != FAIL
);
1888 /* Sanity check -- should have raised a parse error above. */
1889 if (count
== 0 || count
> max_regs
)
1894 /* Final test -- the registers must be consecutive. */
1896 for (i
= 0; i
< count
; i
++)
1898 if ((mask
& (1u << i
)) == 0)
1900 inst
.error
= _("non-contiguous register range");
1910 /* True if two alias types are the same. */
1913 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1921 if (a
->defined
!= b
->defined
)
1924 if ((a
->defined
& NTA_HASTYPE
) != 0
1925 && (a
->eltype
.type
!= b
->eltype
.type
1926 || a
->eltype
.size
!= b
->eltype
.size
))
1929 if ((a
->defined
& NTA_HASINDEX
) != 0
1930 && (a
->index
!= b
->index
))
1936 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1937 The base register is put in *PBASE.
1938 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1940 The register stride (minus one) is put in bit 4 of the return value.
1941 Bits [6:5] encode the list length (minus one).
1942 The type of the list elements is put in *ELTYPE, if non-NULL. */
1944 #define NEON_LANE(X) ((X) & 0xf)
1945 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1946 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1949 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1950 struct neon_type_el
*eltype
)
1957 int leading_brace
= 0;
1958 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1959 const char *const incr_error
= _("register stride must be 1 or 2");
1960 const char *const type_error
= _("mismatched element/structure types in list");
1961 struct neon_typed_alias firsttype
;
1963 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1968 struct neon_typed_alias atype
;
1969 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1973 first_error (_(reg_expected_msgs
[rtype
]));
1980 if (rtype
== REG_TYPE_NQ
)
1986 else if (reg_incr
== -1)
1988 reg_incr
= getreg
- base_reg
;
1989 if (reg_incr
< 1 || reg_incr
> 2)
1991 first_error (_(incr_error
));
1995 else if (getreg
!= base_reg
+ reg_incr
* count
)
1997 first_error (_(incr_error
));
2001 if (! neon_alias_types_same (&atype
, &firsttype
))
2003 first_error (_(type_error
));
2007 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2011 struct neon_typed_alias htype
;
2012 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2014 lane
= NEON_INTERLEAVE_LANES
;
2015 else if (lane
!= NEON_INTERLEAVE_LANES
)
2017 first_error (_(type_error
));
2022 else if (reg_incr
!= 1)
2024 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2028 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2031 first_error (_(reg_expected_msgs
[rtype
]));
2034 if (! neon_alias_types_same (&htype
, &firsttype
))
2036 first_error (_(type_error
));
2039 count
+= hireg
+ dregs
- getreg
;
2043 /* If we're using Q registers, we can't use [] or [n] syntax. */
2044 if (rtype
== REG_TYPE_NQ
)
2050 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2054 else if (lane
!= atype
.index
)
2056 first_error (_(type_error
));
2060 else if (lane
== -1)
2061 lane
= NEON_INTERLEAVE_LANES
;
2062 else if (lane
!= NEON_INTERLEAVE_LANES
)
2064 first_error (_(type_error
));
2069 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2071 /* No lane set by [x]. We must be interleaving structures. */
2073 lane
= NEON_INTERLEAVE_LANES
;
2076 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2077 || (count
> 1 && reg_incr
== -1))
2079 first_error (_("error parsing element/structure list"));
2083 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2085 first_error (_("expected }"));
2093 *eltype
= firsttype
.eltype
;
2098 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2101 /* Parse an explicit relocation suffix on an expression. This is
2102 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2103 arm_reloc_hsh contains no entries, so this function can only
2104 succeed if there is no () after the word. Returns -1 on error,
2105 BFD_RELOC_UNUSED if there wasn't any suffix. */
2108 parse_reloc (char **str
)
2110 struct reloc_entry
*r
;
2114 return BFD_RELOC_UNUSED
;
2119 while (*q
&& *q
!= ')' && *q
!= ',')
2124 if ((r
= (struct reloc_entry
*)
2125 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2132 /* Directives: register aliases. */
2134 static struct reg_entry
*
2135 insert_reg_alias (char *str
, unsigned number
, int type
)
2137 struct reg_entry
*new_reg
;
2140 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2142 if (new_reg
->builtin
)
2143 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2145 /* Only warn about a redefinition if it's not defined as the
2147 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2148 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2153 name
= xstrdup (str
);
2154 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2156 new_reg
->name
= name
;
2157 new_reg
->number
= number
;
2158 new_reg
->type
= type
;
2159 new_reg
->builtin
= FALSE
;
2160 new_reg
->neon
= NULL
;
2162 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2169 insert_neon_reg_alias (char *str
, int number
, int type
,
2170 struct neon_typed_alias
*atype
)
2172 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2176 first_error (_("attempt to redefine typed alias"));
2182 reg
->neon
= (struct neon_typed_alias
*)
2183 xmalloc (sizeof (struct neon_typed_alias
));
2184 *reg
->neon
= *atype
;
2188 /* Look for the .req directive. This is of the form:
2190 new_register_name .req existing_register_name
2192 If we find one, or if it looks sufficiently like one that we want to
2193 handle any error here, return TRUE. Otherwise return FALSE. */
2196 create_register_alias (char * newname
, char *p
)
2198 struct reg_entry
*old
;
2199 char *oldname
, *nbuf
;
2202 /* The input scrubber ensures that whitespace after the mnemonic is
2203 collapsed to single spaces. */
2205 if (strncmp (oldname
, " .req ", 6) != 0)
2209 if (*oldname
== '\0')
2212 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2215 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2219 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2220 the desired alias name, and p points to its end. If not, then
2221 the desired alias name is in the global original_case_string. */
2222 #ifdef TC_CASE_SENSITIVE
2225 newname
= original_case_string
;
2226 nlen
= strlen (newname
);
2229 nbuf
= (char *) alloca (nlen
+ 1);
2230 memcpy (nbuf
, newname
, nlen
);
2233 /* Create aliases under the new name as stated; an all-lowercase
2234 version of the new name; and an all-uppercase version of the new
2236 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2238 for (p
= nbuf
; *p
; p
++)
2241 if (strncmp (nbuf
, newname
, nlen
))
2243 /* If this attempt to create an additional alias fails, do not bother
2244 trying to create the all-lower case alias. We will fail and issue
2245 a second, duplicate error message. This situation arises when the
2246 programmer does something like:
2249 The second .req creates the "Foo" alias but then fails to create
2250 the artificial FOO alias because it has already been created by the
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2256 for (p
= nbuf
; *p
; p
++)
2259 if (strncmp (nbuf
, newname
, nlen
))
2260 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2266 /* Create a Neon typed/indexed register alias using directives, e.g.:
2271 These typed registers can be used instead of the types specified after the
2272 Neon mnemonic, so long as all operands given have types. Types can also be
2273 specified directly, e.g.:
2274 vadd d0.s32, d1.s32, d2.s32 */
2277 create_neon_reg_alias (char *newname
, char *p
)
2279 enum arm_reg_type basetype
;
2280 struct reg_entry
*basereg
;
2281 struct reg_entry mybasereg
;
2282 struct neon_type ntype
;
2283 struct neon_typed_alias typeinfo
;
2284 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2287 typeinfo
.defined
= 0;
2288 typeinfo
.eltype
.type
= NT_invtype
;
2289 typeinfo
.eltype
.size
= -1;
2290 typeinfo
.index
= -1;
2294 if (strncmp (p
, " .dn ", 5) == 0)
2295 basetype
= REG_TYPE_VFD
;
2296 else if (strncmp (p
, " .qn ", 5) == 0)
2297 basetype
= REG_TYPE_NQ
;
2306 basereg
= arm_reg_parse_multi (&p
);
2308 if (basereg
&& basereg
->type
!= basetype
)
2310 as_bad (_("bad type for register"));
2314 if (basereg
== NULL
)
2317 /* Try parsing as an integer. */
2318 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2319 if (exp
.X_op
!= O_constant
)
2321 as_bad (_("expression must be constant"));
2324 basereg
= &mybasereg
;
2325 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2331 typeinfo
= *basereg
->neon
;
2333 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2335 /* We got a type. */
2336 if (typeinfo
.defined
& NTA_HASTYPE
)
2338 as_bad (_("can't redefine the type of a register alias"));
2342 typeinfo
.defined
|= NTA_HASTYPE
;
2343 if (ntype
.elems
!= 1)
2345 as_bad (_("you must specify a single type only"));
2348 typeinfo
.eltype
= ntype
.el
[0];
2351 if (skip_past_char (&p
, '[') == SUCCESS
)
2354 /* We got a scalar index. */
2356 if (typeinfo
.defined
& NTA_HASINDEX
)
2358 as_bad (_("can't redefine the index of a scalar alias"));
2362 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2364 if (exp
.X_op
!= O_constant
)
2366 as_bad (_("scalar index must be constant"));
2370 typeinfo
.defined
|= NTA_HASINDEX
;
2371 typeinfo
.index
= exp
.X_add_number
;
2373 if (skip_past_char (&p
, ']') == FAIL
)
2375 as_bad (_("expecting ]"));
2380 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2381 the desired alias name, and p points to its end. If not, then
2382 the desired alias name is in the global original_case_string. */
2383 #ifdef TC_CASE_SENSITIVE
2384 namelen
= nameend
- newname
;
2386 newname
= original_case_string
;
2387 namelen
= strlen (newname
);
2390 namebuf
= (char *) alloca (namelen
+ 1);
2391 strncpy (namebuf
, newname
, namelen
);
2392 namebuf
[namelen
] = '\0';
2394 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2395 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2397 /* Insert name in all uppercase. */
2398 for (p
= namebuf
; *p
; p
++)
2401 if (strncmp (namebuf
, newname
, namelen
))
2402 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2403 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2405 /* Insert name in all lowercase. */
2406 for (p
= namebuf
; *p
; p
++)
2409 if (strncmp (namebuf
, newname
, namelen
))
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2416 /* Should never be called, as .req goes between the alias and the
2417 register name, not at the beginning of the line. */
2420 s_req (int a ATTRIBUTE_UNUSED
)
2422 as_bad (_("invalid syntax for .req directive"));
2426 s_dn (int a ATTRIBUTE_UNUSED
)
2428 as_bad (_("invalid syntax for .dn directive"));
2432 s_qn (int a ATTRIBUTE_UNUSED
)
2434 as_bad (_("invalid syntax for .qn directive"));
2437 /* The .unreq directive deletes an alias which was previously defined
2438 by .req. For example:
2444 s_unreq (int a ATTRIBUTE_UNUSED
)
2449 name
= input_line_pointer
;
2451 while (*input_line_pointer
!= 0
2452 && *input_line_pointer
!= ' '
2453 && *input_line_pointer
!= '\n')
2454 ++input_line_pointer
;
2456 saved_char
= *input_line_pointer
;
2457 *input_line_pointer
= 0;
2460 as_bad (_("invalid syntax for .unreq directive"));
2463 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2467 as_bad (_("unknown register alias '%s'"), name
);
2468 else if (reg
->builtin
)
2469 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2476 hash_delete (arm_reg_hsh
, name
, FALSE
);
2477 free ((char *) reg
->name
);
2482 /* Also locate the all upper case and all lower case versions.
2483 Do not complain if we cannot find one or the other as it
2484 was probably deleted above. */
2486 nbuf
= strdup (name
);
2487 for (p
= nbuf
; *p
; p
++)
2489 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2492 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2493 free ((char *) reg
->name
);
2499 for (p
= nbuf
; *p
; p
++)
2501 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2504 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2505 free ((char *) reg
->name
);
2515 *input_line_pointer
= saved_char
;
2516 demand_empty_rest_of_line ();
2519 /* Directives: Instruction set selection. */
2522 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2523 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2524 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2525 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2527 /* Create a new mapping symbol for the transition to STATE. */
2530 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2533 const char * symname
;
2540 type
= BSF_NO_FLAGS
;
2544 type
= BSF_NO_FLAGS
;
2548 type
= BSF_NO_FLAGS
;
2554 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2555 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2560 THUMB_SET_FUNC (symbolP
, 0);
2561 ARM_SET_THUMB (symbolP
, 0);
2562 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2566 THUMB_SET_FUNC (symbolP
, 1);
2567 ARM_SET_THUMB (symbolP
, 1);
2568 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2576 /* Save the mapping symbols for future reference. Also check that
2577 we do not place two mapping symbols at the same offset within a
2578 frag. We'll handle overlap between frags in
2579 check_mapping_symbols.
2581 If .fill or other data filling directive generates zero sized data,
2582 the mapping symbol for the following code will have the same value
2583 as the one generated for the data filling directive. In this case,
2584 we replace the old symbol with the new one at the same address. */
2587 if (frag
->tc_frag_data
.first_map
!= NULL
)
2589 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2590 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2592 frag
->tc_frag_data
.first_map
= symbolP
;
2594 if (frag
->tc_frag_data
.last_map
!= NULL
)
2596 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2597 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2598 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2600 frag
->tc_frag_data
.last_map
= symbolP
;
2603 /* We must sometimes convert a region marked as code to data during
2604 code alignment, if an odd number of bytes have to be padded. The
2605 code mapping symbol is pushed to an aligned address. */
2608 insert_data_mapping_symbol (enum mstate state
,
2609 valueT value
, fragS
*frag
, offsetT bytes
)
2611 /* If there was already a mapping symbol, remove it. */
2612 if (frag
->tc_frag_data
.last_map
!= NULL
2613 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2615 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2619 know (frag
->tc_frag_data
.first_map
== symp
);
2620 frag
->tc_frag_data
.first_map
= NULL
;
2622 frag
->tc_frag_data
.last_map
= NULL
;
2623 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2626 make_mapping_symbol (MAP_DATA
, value
, frag
);
2627 make_mapping_symbol (state
, value
+ bytes
, frag
);
2630 static void mapping_state_2 (enum mstate state
, int max_chars
);
2632 /* Set the mapping state to STATE. Only call this when about to
2633 emit some STATE bytes to the file. */
2635 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2637 mapping_state (enum mstate state
)
2639 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2641 if (mapstate
== state
)
2642 /* The mapping symbol has already been emitted.
2643 There is nothing else to do. */
2646 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2648 All ARM instructions require 4-byte alignment.
2649 (Almost) all Thumb instructions require 2-byte alignment.
2651 When emitting instructions into any section, mark the section
2654 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2655 but themselves require 2-byte alignment; this applies to some
2656 PC- relative forms. However, these cases will invovle implicit
2657 literal pool generation or an explicit .align >=2, both of
2658 which will cause the section to me marked with sufficient
2659 alignment. Thus, we don't handle those cases here. */
2660 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2662 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2663 /* This case will be evaluated later. */
2666 mapping_state_2 (state
, 0);
2669 /* Same as mapping_state, but MAX_CHARS bytes have already been
2670 allocated. Put the mapping symbol that far back. */
2673 mapping_state_2 (enum mstate state
, int max_chars
)
2675 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2677 if (!SEG_NORMAL (now_seg
))
2680 if (mapstate
== state
)
2681 /* The mapping symbol has already been emitted.
2682 There is nothing else to do. */
2685 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2686 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2688 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2689 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2692 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2695 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2696 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2700 #define mapping_state(x) ((void)0)
2701 #define mapping_state_2(x, y) ((void)0)
2704 /* Find the real, Thumb encoded start of a Thumb function. */
2708 find_real_start (symbolS
* symbolP
)
2711 const char * name
= S_GET_NAME (symbolP
);
2712 symbolS
* new_target
;
2714 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2715 #define STUB_NAME ".real_start_of"
2720 /* The compiler may generate BL instructions to local labels because
2721 it needs to perform a branch to a far away location. These labels
2722 do not have a corresponding ".real_start_of" label. We check
2723 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2724 the ".real_start_of" convention for nonlocal branches. */
2725 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2728 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2729 new_target
= symbol_find (real_start
);
2731 if (new_target
== NULL
)
2733 as_warn (_("Failed to find real start of function: %s\n"), name
);
2734 new_target
= symbolP
;
2742 opcode_select (int width
)
2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2750 as_bad (_("selected processor does not support THUMB opcodes"));
2753 /* No need to force the alignment, since we will have been
2754 coming from ARM mode, which is word-aligned. */
2755 record_alignment (now_seg
, 1);
2762 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2763 as_bad (_("selected processor does not support ARM opcodes"));
2768 frag_align (2, 0, 0);
2770 record_alignment (now_seg
, 1);
2775 as_bad (_("invalid instruction size selected (%d)"), width
);
2780 s_arm (int ignore ATTRIBUTE_UNUSED
)
2783 demand_empty_rest_of_line ();
2787 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2790 demand_empty_rest_of_line ();
2794 s_code (int unused ATTRIBUTE_UNUSED
)
2798 temp
= get_absolute_expression ();
2803 opcode_select (temp
);
2807 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2812 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2814 /* If we are not already in thumb mode go into it, EVEN if
2815 the target processor does not support thumb instructions.
2816 This is used by gcc/config/arm/lib1funcs.asm for example
2817 to compile interworking support functions even if the
2818 target processor should not support interworking. */
2822 record_alignment (now_seg
, 1);
2825 demand_empty_rest_of_line ();
2829 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2833 /* The following label is the name/address of the start of a Thumb function.
2834 We need to know this for the interworking support. */
2835 label_is_thumb_function_name
= TRUE
;
2838 /* Perform a .set directive, but also mark the alias as
2839 being a thumb function. */
2842 s_thumb_set (int equiv
)
2844 /* XXX the following is a duplicate of the code for s_set() in read.c
2845 We cannot just call that code as we need to get at the symbol that
2852 /* Especial apologies for the random logic:
2853 This just grew, and could be parsed much more simply!
2855 name
= input_line_pointer
;
2856 delim
= get_symbol_end ();
2857 end_name
= input_line_pointer
;
2860 if (*input_line_pointer
!= ',')
2863 as_bad (_("expected comma after name \"%s\""), name
);
2865 ignore_rest_of_line ();
2869 input_line_pointer
++;
2872 if (name
[0] == '.' && name
[1] == '\0')
2874 /* XXX - this should not happen to .thumb_set. */
2878 if ((symbolP
= symbol_find (name
)) == NULL
2879 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2882 /* When doing symbol listings, play games with dummy fragments living
2883 outside the normal fragment chain to record the file and line info
2885 if (listing
& LISTING_SYMBOLS
)
2887 extern struct list_info_struct
* listing_tail
;
2888 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2890 memset (dummy_frag
, 0, sizeof (fragS
));
2891 dummy_frag
->fr_type
= rs_fill
;
2892 dummy_frag
->line
= listing_tail
;
2893 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2894 dummy_frag
->fr_symbol
= symbolP
;
2898 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2901 /* "set" symbols are local unless otherwise specified. */
2902 SF_SET_LOCAL (symbolP
);
2903 #endif /* OBJ_COFF */
2904 } /* Make a new symbol. */
2906 symbol_table_insert (symbolP
);
2911 && S_IS_DEFINED (symbolP
)
2912 && S_GET_SEGMENT (symbolP
) != reg_section
)
2913 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2915 pseudo_set (symbolP
);
2917 demand_empty_rest_of_line ();
2919 /* XXX Now we come to the Thumb specific bit of code. */
2921 THUMB_SET_FUNC (symbolP
, 1);
2922 ARM_SET_THUMB (symbolP
, 1);
2923 #if defined OBJ_ELF || defined OBJ_COFF
2924 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2928 /* Directives: Mode selection. */
2930 /* .syntax [unified|divided] - choose the new unified syntax
2931 (same for Arm and Thumb encoding, modulo slight differences in what
2932 can be represented) or the old divergent syntax for each mode. */
2934 s_syntax (int unused ATTRIBUTE_UNUSED
)
2938 name
= input_line_pointer
;
2939 delim
= get_symbol_end ();
2941 if (!strcasecmp (name
, "unified"))
2942 unified_syntax
= TRUE
;
2943 else if (!strcasecmp (name
, "divided"))
2944 unified_syntax
= FALSE
;
2947 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2950 *input_line_pointer
= delim
;
2951 demand_empty_rest_of_line ();
2954 /* Directives: sectioning and alignment. */
2956 /* Same as s_align_ptwo but align 0 => align 2. */
2959 s_align (int unused ATTRIBUTE_UNUSED
)
2964 long max_alignment
= 15;
2966 temp
= get_absolute_expression ();
2967 if (temp
> max_alignment
)
2968 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2971 as_bad (_("alignment negative. 0 assumed."));
2975 if (*input_line_pointer
== ',')
2977 input_line_pointer
++;
2978 temp_fill
= get_absolute_expression ();
2990 /* Only make a frag if we HAVE to. */
2991 if (temp
&& !need_pass_2
)
2993 if (!fill_p
&& subseg_text_p (now_seg
))
2994 frag_align_code (temp
, 0);
2996 frag_align (temp
, (int) temp_fill
, 0);
2998 demand_empty_rest_of_line ();
3000 record_alignment (now_seg
, temp
);
3004 s_bss (int ignore ATTRIBUTE_UNUSED
)
3006 /* We don't support putting frags in the BSS segment, we fake it by
3007 marking in_bss, then looking at s_skip for clues. */
3008 subseg_set (bss_section
, 0);
3009 demand_empty_rest_of_line ();
3011 #ifdef md_elf_section_change_hook
3012 md_elf_section_change_hook ();
3017 s_even (int ignore ATTRIBUTE_UNUSED
)
3019 /* Never make frag if expect extra pass. */
3021 frag_align (1, 0, 0);
3023 record_alignment (now_seg
, 1);
3025 demand_empty_rest_of_line ();
3028 /* Directives: CodeComposer Studio. */
3030 /* .ref (for CodeComposer Studio syntax only). */
3032 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3034 if (codecomposer_syntax
)
3035 ignore_rest_of_line ();
3037 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3040 /* If name is not NULL, then it is used for marking the beginning of a
3041 function, wherease if it is NULL then it means the function end. */
3043 asmfunc_debug (const char * name
)
3045 static const char * last_name
= NULL
;
3049 gas_assert (last_name
== NULL
);
3052 if (debug_type
== DEBUG_STABS
)
3053 stabs_generate_asm_func (name
, name
);
3057 gas_assert (last_name
!= NULL
);
3059 if (debug_type
== DEBUG_STABS
)
3060 stabs_generate_asm_endfunc (last_name
, last_name
);
3067 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3069 if (codecomposer_syntax
)
3071 switch (asmfunc_state
)
3073 case OUTSIDE_ASMFUNC
:
3074 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3077 case WAITING_ASMFUNC_NAME
:
3078 as_bad (_(".asmfunc repeated."));
3081 case WAITING_ENDASMFUNC
:
3082 as_bad (_(".asmfunc without function."));
3085 demand_empty_rest_of_line ();
3088 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3092 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3094 if (codecomposer_syntax
)
3096 switch (asmfunc_state
)
3098 case OUTSIDE_ASMFUNC
:
3099 as_bad (_(".endasmfunc without a .asmfunc."));
3102 case WAITING_ASMFUNC_NAME
:
3103 as_bad (_(".endasmfunc without function."));
3106 case WAITING_ENDASMFUNC
:
3107 asmfunc_state
= OUTSIDE_ASMFUNC
;
3108 asmfunc_debug (NULL
);
3111 demand_empty_rest_of_line ();
3114 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3118 s_ccs_def (int name
)
3120 if (codecomposer_syntax
)
3123 as_bad (_(".def pseudo-op only available with -mccs flag."));
3126 /* Directives: Literal pools. */
3128 static literal_pool
*
3129 find_literal_pool (void)
3131 literal_pool
* pool
;
3133 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3135 if (pool
->section
== now_seg
3136 && pool
->sub_section
== now_subseg
)
3143 static literal_pool
*
3144 find_or_make_literal_pool (void)
3146 /* Next literal pool ID number. */
3147 static unsigned int latest_pool_num
= 1;
3148 literal_pool
* pool
;
3150 pool
= find_literal_pool ();
3154 /* Create a new pool. */
3155 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3159 pool
->next_free_entry
= 0;
3160 pool
->section
= now_seg
;
3161 pool
->sub_section
= now_subseg
;
3162 pool
->next
= list_of_pools
;
3163 pool
->symbol
= NULL
;
3164 pool
->alignment
= 2;
3166 /* Add it to the list. */
3167 list_of_pools
= pool
;
3170 /* New pools, and emptied pools, will have a NULL symbol. */
3171 if (pool
->symbol
== NULL
)
3173 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3174 (valueT
) 0, &zero_address_frag
);
3175 pool
->id
= latest_pool_num
++;
3182 /* Add the literal in the global 'inst'
3183 structure to the relevant literal pool. */
3186 add_to_lit_pool (unsigned int nbytes
)
3188 #define PADDING_SLOT 0x1
3189 #define LIT_ENTRY_SIZE_MASK 0xFF
3190 literal_pool
* pool
;
3191 unsigned int entry
, pool_size
= 0;
3192 bfd_boolean padding_slot_p
= FALSE
;
3198 imm1
= inst
.operands
[1].imm
;
3199 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3200 : inst
.reloc
.exp
.X_unsigned
? 0
3201 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3202 if (target_big_endian
)
3205 imm2
= inst
.operands
[1].imm
;
3209 pool
= find_or_make_literal_pool ();
3211 /* Check if this literal value is already in the pool. */
3212 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3216 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3217 && (inst
.reloc
.exp
.X_op
== O_constant
)
3218 && (pool
->literals
[entry
].X_add_number
3219 == inst
.reloc
.exp
.X_add_number
)
3220 && (pool
->literals
[entry
].X_md
== nbytes
)
3221 && (pool
->literals
[entry
].X_unsigned
3222 == inst
.reloc
.exp
.X_unsigned
))
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_add_symbol
3230 == inst
.reloc
.exp
.X_add_symbol
)
3231 && (pool
->literals
[entry
].X_op_symbol
3232 == inst
.reloc
.exp
.X_op_symbol
)
3233 && (pool
->literals
[entry
].X_md
== nbytes
))
3236 else if ((nbytes
== 8)
3237 && !(pool_size
& 0x7)
3238 && ((entry
+ 1) != pool
->next_free_entry
)
3239 && (pool
->literals
[entry
].X_op
== O_constant
)
3240 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3241 && (pool
->literals
[entry
].X_unsigned
3242 == inst
.reloc
.exp
.X_unsigned
)
3243 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3244 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3245 && (pool
->literals
[entry
+ 1].X_unsigned
3246 == inst
.reloc
.exp
.X_unsigned
))
3249 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3250 if (padding_slot_p
&& (nbytes
== 4))
3256 /* Do we need to create a new entry? */
3257 if (entry
== pool
->next_free_entry
)
3259 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3261 inst
.error
= _("literal pool overflow");
3267 /* For 8-byte entries, we align to an 8-byte boundary,
3268 and split it into two 4-byte entries, because on 32-bit
3269 host, 8-byte constants are treated as big num, thus
3270 saved in "generic_bignum" which will be overwritten
3271 by later assignments.
3273 We also need to make sure there is enough space for
3276 We also check to make sure the literal operand is a
3278 if (!(inst
.reloc
.exp
.X_op
== O_constant
3279 || inst
.reloc
.exp
.X_op
== O_big
))
3281 inst
.error
= _("invalid type for literal pool");
3284 else if (pool_size
& 0x7)
3286 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3288 inst
.error
= _("literal pool overflow");
3292 pool
->literals
[entry
] = inst
.reloc
.exp
;
3293 pool
->literals
[entry
].X_add_number
= 0;
3294 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3295 pool
->next_free_entry
+= 1;
3298 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3300 inst
.error
= _("literal pool overflow");
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_op
= O_constant
;
3306 pool
->literals
[entry
].X_add_number
= imm1
;
3307 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3308 pool
->literals
[entry
++].X_md
= 4;
3309 pool
->literals
[entry
] = inst
.reloc
.exp
;
3310 pool
->literals
[entry
].X_op
= O_constant
;
3311 pool
->literals
[entry
].X_add_number
= imm2
;
3312 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3313 pool
->literals
[entry
].X_md
= 4;
3314 pool
->alignment
= 3;
3315 pool
->next_free_entry
+= 1;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_md
= 4;
3324 /* PR ld/12974: Record the location of the first source line to reference
3325 this entry in the literal pool. If it turns out during linking that the
3326 symbol does not exist we will be able to give an accurate line number for
3327 the (first use of the) missing reference. */
3328 if (debug_type
== DEBUG_DWARF2
)
3329 dwarf2_where (pool
->locs
+ entry
);
3331 pool
->next_free_entry
+= 1;
3333 else if (padding_slot_p
)
3335 pool
->literals
[entry
] = inst
.reloc
.exp
;
3336 pool
->literals
[entry
].X_md
= nbytes
;
3339 inst
.reloc
.exp
.X_op
= O_symbol
;
3340 inst
.reloc
.exp
.X_add_number
= pool_size
;
3341 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3347 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3349 bfd_boolean ret
= TRUE
;
3351 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3353 const char *label
= rest
;
3355 while (!is_end_of_line
[(int) label
[-1]])
3360 as_bad (_("Invalid label '%s'"), label
);
3364 asmfunc_debug (label
);
3366 asmfunc_state
= WAITING_ENDASMFUNC
;
3372 /* Can't use symbol_new here, so have to create a symbol and then at
3373 a later date assign it a value. Thats what these functions do. */
3376 symbol_locate (symbolS
* symbolP
,
3377 const char * name
, /* It is copied, the caller can modify. */
3378 segT segment
, /* Segment identifier (SEG_<something>). */
3379 valueT valu
, /* Symbol value. */
3380 fragS
* frag
) /* Associated fragment. */
3383 char * preserved_copy_of_name
;
3385 name_length
= strlen (name
) + 1; /* +1 for \0. */
3386 obstack_grow (¬es
, name
, name_length
);
3387 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3389 #ifdef tc_canonicalize_symbol_name
3390 preserved_copy_of_name
=
3391 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3394 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3396 S_SET_SEGMENT (symbolP
, segment
);
3397 S_SET_VALUE (symbolP
, valu
);
3398 symbol_clear_list_pointers (symbolP
);
3400 symbol_set_frag (symbolP
, frag
);
3402 /* Link to end of symbol chain. */
3404 extern int symbol_table_frozen
;
3406 if (symbol_table_frozen
)
3410 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3412 obj_symbol_new_hook (symbolP
);
3414 #ifdef tc_symbol_new_hook
3415 tc_symbol_new_hook (symbolP
);
3419 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3420 #endif /* DEBUG_SYMS */
3424 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3427 literal_pool
* pool
;
3430 pool
= find_literal_pool ();
3432 || pool
->symbol
== NULL
3433 || pool
->next_free_entry
== 0)
3436 /* Align pool as you have word accesses.
3437 Only make a frag if we have to. */
3439 frag_align (pool
->alignment
, 0, 0);
3441 record_alignment (now_seg
, 2);
3444 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3445 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3447 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3449 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3450 (valueT
) frag_now_fix (), frag_now
);
3451 symbol_table_insert (pool
->symbol
);
3453 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3455 #if defined OBJ_COFF || defined OBJ_ELF
3456 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3459 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3462 if (debug_type
== DEBUG_DWARF2
)
3463 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3465 /* First output the expression in the instruction to the pool. */
3466 emit_expr (&(pool
->literals
[entry
]),
3467 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3470 /* Mark the pool as empty. */
3471 pool
->next_free_entry
= 0;
3472 pool
->symbol
= NULL
;
3476 /* Forward declarations for functions below, in the MD interface
3478 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3479 static valueT
create_unwind_entry (int);
3480 static void start_unwind_section (const segT
, int);
3481 static void add_unwind_opcode (valueT
, int);
3482 static void flush_pending_unwind (void);
3484 /* Directives: Data. */
3487 s_arm_elf_cons (int nbytes
)
3491 #ifdef md_flush_pending_output
3492 md_flush_pending_output ();
3495 if (is_it_end_of_statement ())
3497 demand_empty_rest_of_line ();
3501 #ifdef md_cons_align
3502 md_cons_align (nbytes
);
3505 mapping_state (MAP_DATA
);
3509 char *base
= input_line_pointer
;
3513 if (exp
.X_op
!= O_symbol
)
3514 emit_expr (&exp
, (unsigned int) nbytes
);
3517 char *before_reloc
= input_line_pointer
;
3518 reloc
= parse_reloc (&input_line_pointer
);
3521 as_bad (_("unrecognized relocation suffix"));
3522 ignore_rest_of_line ();
3525 else if (reloc
== BFD_RELOC_UNUSED
)
3526 emit_expr (&exp
, (unsigned int) nbytes
);
3529 reloc_howto_type
*howto
= (reloc_howto_type
*)
3530 bfd_reloc_type_lookup (stdoutput
,
3531 (bfd_reloc_code_real_type
) reloc
);
3532 int size
= bfd_get_reloc_size (howto
);
3534 if (reloc
== BFD_RELOC_ARM_PLT32
)
3536 as_bad (_("(plt) is only valid on branch targets"));
3537 reloc
= BFD_RELOC_UNUSED
;
3542 as_bad (_("%s relocations do not fit in %d bytes"),
3543 howto
->name
, nbytes
);
3546 /* We've parsed an expression stopping at O_symbol.
3547 But there may be more expression left now that we
3548 have parsed the relocation marker. Parse it again.
3549 XXX Surely there is a cleaner way to do this. */
3550 char *p
= input_line_pointer
;
3552 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3553 memcpy (save_buf
, base
, input_line_pointer
- base
);
3554 memmove (base
+ (input_line_pointer
- before_reloc
),
3555 base
, before_reloc
- base
);
3557 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3559 memcpy (base
, save_buf
, p
- base
);
3561 offset
= nbytes
- size
;
3562 p
= frag_more (nbytes
);
3563 memset (p
, 0, nbytes
);
3564 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3565 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3570 while (*input_line_pointer
++ == ',');
3572 /* Put terminator back into stream. */
3573 input_line_pointer
--;
3574 demand_empty_rest_of_line ();
3577 /* Emit an expression containing a 32-bit thumb instruction.
3578 Implementation based on put_thumb32_insn. */
3581 emit_thumb32_expr (expressionS
* exp
)
3583 expressionS exp_high
= *exp
;
3585 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3586 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3587 exp
->X_add_number
&= 0xffff;
3588 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3591 /* Guess the instruction size based on the opcode. */
3594 thumb_insn_size (int opcode
)
3596 if ((unsigned int) opcode
< 0xe800u
)
3598 else if ((unsigned int) opcode
>= 0xe8000000u
)
3605 emit_insn (expressionS
*exp
, int nbytes
)
3609 if (exp
->X_op
== O_constant
)
3614 size
= thumb_insn_size (exp
->X_add_number
);
3618 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3620 as_bad (_(".inst.n operand too big. "\
3621 "Use .inst.w instead"));
3626 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3627 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3629 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3631 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3632 emit_thumb32_expr (exp
);
3634 emit_expr (exp
, (unsigned int) size
);
3636 it_fsm_post_encode ();
3640 as_bad (_("cannot determine Thumb instruction size. " \
3641 "Use .inst.n/.inst.w instead"));
3644 as_bad (_("constant expression required"));
3649 /* Like s_arm_elf_cons but do not use md_cons_align and
3650 set the mapping state to MAP_ARM/MAP_THUMB. */
3653 s_arm_elf_inst (int nbytes
)
3655 if (is_it_end_of_statement ())
3657 demand_empty_rest_of_line ();
3661 /* Calling mapping_state () here will not change ARM/THUMB,
3662 but will ensure not to be in DATA state. */
3665 mapping_state (MAP_THUMB
);
3670 as_bad (_("width suffixes are invalid in ARM mode"));
3671 ignore_rest_of_line ();
3677 mapping_state (MAP_ARM
);
3686 if (! emit_insn (& exp
, nbytes
))
3688 ignore_rest_of_line ();
3692 while (*input_line_pointer
++ == ',');
3694 /* Put terminator back into stream. */
3695 input_line_pointer
--;
3696 demand_empty_rest_of_line ();
3699 /* Parse a .rel31 directive. */
3702 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3709 if (*input_line_pointer
== '1')
3710 highbit
= 0x80000000;
3711 else if (*input_line_pointer
!= '0')
3712 as_bad (_("expected 0 or 1"));
3714 input_line_pointer
++;
3715 if (*input_line_pointer
!= ',')
3716 as_bad (_("missing comma"));
3717 input_line_pointer
++;
3719 #ifdef md_flush_pending_output
3720 md_flush_pending_output ();
3723 #ifdef md_cons_align
3727 mapping_state (MAP_DATA
);
3732 md_number_to_chars (p
, highbit
, 4);
3733 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3734 BFD_RELOC_ARM_PREL31
);
3736 demand_empty_rest_of_line ();
3739 /* Directives: AEABI stack-unwind tables. */
3741 /* Parse an unwind_fnstart directive. Simply records the current location. */
3744 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3746 demand_empty_rest_of_line ();
3747 if (unwind
.proc_start
)
3749 as_bad (_("duplicate .fnstart directive"));
3753 /* Mark the start of the function. */
3754 unwind
.proc_start
= expr_build_dot ();
3756 /* Reset the rest of the unwind info. */
3757 unwind
.opcode_count
= 0;
3758 unwind
.table_entry
= NULL
;
3759 unwind
.personality_routine
= NULL
;
3760 unwind
.personality_index
= -1;
3761 unwind
.frame_size
= 0;
3762 unwind
.fp_offset
= 0;
3763 unwind
.fp_reg
= REG_SP
;
3765 unwind
.sp_restored
= 0;
3769 /* Parse a handlerdata directive. Creates the exception handling table entry
3770 for the function. */
3773 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3775 demand_empty_rest_of_line ();
3776 if (!unwind
.proc_start
)
3777 as_bad (MISSING_FNSTART
);
3779 if (unwind
.table_entry
)
3780 as_bad (_("duplicate .handlerdata directive"));
3782 create_unwind_entry (1);
3785 /* Parse an unwind_fnend directive. Generates the index table entry. */
3788 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3793 unsigned int marked_pr_dependency
;
3795 demand_empty_rest_of_line ();
3797 if (!unwind
.proc_start
)
3799 as_bad (_(".fnend directive without .fnstart"));
3803 /* Add eh table entry. */
3804 if (unwind
.table_entry
== NULL
)
3805 val
= create_unwind_entry (0);
3809 /* Add index table entry. This is two words. */
3810 start_unwind_section (unwind
.saved_seg
, 1);
3811 frag_align (2, 0, 0);
3812 record_alignment (now_seg
, 2);
3814 ptr
= frag_more (8);
3816 where
= frag_now_fix () - 8;
3818 /* Self relative offset of the function start. */
3819 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3820 BFD_RELOC_ARM_PREL31
);
3822 /* Indicate dependency on EHABI-defined personality routines to the
3823 linker, if it hasn't been done already. */
3824 marked_pr_dependency
3825 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3826 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3827 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3829 static const char *const name
[] =
3831 "__aeabi_unwind_cpp_pr0",
3832 "__aeabi_unwind_cpp_pr1",
3833 "__aeabi_unwind_cpp_pr2"
3835 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3836 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3837 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3838 |= 1 << unwind
.personality_index
;
3842 /* Inline exception table entry. */
3843 md_number_to_chars (ptr
+ 4, val
, 4);
3845 /* Self relative offset of the table entry. */
3846 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3847 BFD_RELOC_ARM_PREL31
);
3849 /* Restore the original section. */
3850 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3852 unwind
.proc_start
= NULL
;
3856 /* Parse an unwind_cantunwind directive. */
3859 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3861 demand_empty_rest_of_line ();
3862 if (!unwind
.proc_start
)
3863 as_bad (MISSING_FNSTART
);
3865 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3866 as_bad (_("personality routine specified for cantunwind frame"));
3868 unwind
.personality_index
= -2;
3872 /* Parse a personalityindex directive. */
3875 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3879 if (!unwind
.proc_start
)
3880 as_bad (MISSING_FNSTART
);
3882 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3883 as_bad (_("duplicate .personalityindex directive"));
3887 if (exp
.X_op
!= O_constant
3888 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3890 as_bad (_("bad personality routine number"));
3891 ignore_rest_of_line ();
3895 unwind
.personality_index
= exp
.X_add_number
;
3897 demand_empty_rest_of_line ();
3901 /* Parse a personality directive. */
3904 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3908 if (!unwind
.proc_start
)
3909 as_bad (MISSING_FNSTART
);
3911 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3912 as_bad (_("duplicate .personality directive"));
3914 name
= input_line_pointer
;
3915 c
= get_symbol_end ();
3916 p
= input_line_pointer
;
3917 unwind
.personality_routine
= symbol_find_or_make (name
);
3919 demand_empty_rest_of_line ();
3923 /* Parse a directive saving core registers. */
3926 s_arm_unwind_save_core (void)
3932 range
= parse_reg_list (&input_line_pointer
);
3935 as_bad (_("expected register list"));
3936 ignore_rest_of_line ();
3940 demand_empty_rest_of_line ();
3942 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3943 into .unwind_save {..., sp...}. We aren't bothered about the value of
3944 ip because it is clobbered by calls. */
3945 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3946 && (range
& 0x3000) == 0x1000)
3948 unwind
.opcode_count
--;
3949 unwind
.sp_restored
= 0;
3950 range
= (range
| 0x2000) & ~0x1000;
3951 unwind
.pending_offset
= 0;
3957 /* See if we can use the short opcodes. These pop a block of up to 8
3958 registers starting with r4, plus maybe r14. */
3959 for (n
= 0; n
< 8; n
++)
3961 /* Break at the first non-saved register. */
3962 if ((range
& (1 << (n
+ 4))) == 0)
3965 /* See if there are any other bits set. */
3966 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3968 /* Use the long form. */
3969 op
= 0x8000 | ((range
>> 4) & 0xfff);
3970 add_unwind_opcode (op
, 2);
3974 /* Use the short form. */
3976 op
= 0xa8; /* Pop r14. */
3978 op
= 0xa0; /* Do not pop r14. */
3980 add_unwind_opcode (op
, 1);
3987 op
= 0xb100 | (range
& 0xf);
3988 add_unwind_opcode (op
, 2);
3991 /* Record the number of bytes pushed. */
3992 for (n
= 0; n
< 16; n
++)
3994 if (range
& (1 << n
))
3995 unwind
.frame_size
+= 4;
4000 /* Parse a directive saving FPA registers. */
4003 s_arm_unwind_save_fpa (int reg
)
4009 /* Get Number of registers to transfer. */
4010 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4013 exp
.X_op
= O_illegal
;
4015 if (exp
.X_op
!= O_constant
)
4017 as_bad (_("expected , <constant>"));
4018 ignore_rest_of_line ();
4022 num_regs
= exp
.X_add_number
;
4024 if (num_regs
< 1 || num_regs
> 4)
4026 as_bad (_("number of registers must be in the range [1:4]"));
4027 ignore_rest_of_line ();
4031 demand_empty_rest_of_line ();
4036 op
= 0xb4 | (num_regs
- 1);
4037 add_unwind_opcode (op
, 1);
4042 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4043 add_unwind_opcode (op
, 2);
4045 unwind
.frame_size
+= num_regs
* 12;
4049 /* Parse a directive saving VFP registers for ARMv6 and above. */
4052 s_arm_unwind_save_vfp_armv6 (void)
4057 int num_vfpv3_regs
= 0;
4058 int num_regs_below_16
;
4060 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4063 as_bad (_("expected register list"));
4064 ignore_rest_of_line ();
4068 demand_empty_rest_of_line ();
4070 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4071 than FSTMX/FLDMX-style ones). */
4073 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4075 num_vfpv3_regs
= count
;
4076 else if (start
+ count
> 16)
4077 num_vfpv3_regs
= start
+ count
- 16;
4079 if (num_vfpv3_regs
> 0)
4081 int start_offset
= start
> 16 ? start
- 16 : 0;
4082 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4083 add_unwind_opcode (op
, 2);
4086 /* Generate opcode for registers numbered in the range 0 .. 15. */
4087 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4088 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4089 if (num_regs_below_16
> 0)
4091 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4092 add_unwind_opcode (op
, 2);
4095 unwind
.frame_size
+= count
* 8;
4099 /* Parse a directive saving VFP registers for pre-ARMv6. */
4102 s_arm_unwind_save_vfp (void)
4108 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4111 as_bad (_("expected register list"));
4112 ignore_rest_of_line ();
4116 demand_empty_rest_of_line ();
4121 op
= 0xb8 | (count
- 1);
4122 add_unwind_opcode (op
, 1);
4127 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4128 add_unwind_opcode (op
, 2);
4130 unwind
.frame_size
+= count
* 8 + 4;
4134 /* Parse a directive saving iWMMXt data registers. */
4137 s_arm_unwind_save_mmxwr (void)
4145 if (*input_line_pointer
== '{')
4146 input_line_pointer
++;
4150 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4154 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4159 as_tsktsk (_("register list not in ascending order"));
4162 if (*input_line_pointer
== '-')
4164 input_line_pointer
++;
4165 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4168 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4171 else if (reg
>= hi_reg
)
4173 as_bad (_("bad register range"));
4176 for (; reg
< hi_reg
; reg
++)
4180 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4182 skip_past_char (&input_line_pointer
, '}');
4184 demand_empty_rest_of_line ();
4186 /* Generate any deferred opcodes because we're going to be looking at
4188 flush_pending_unwind ();
4190 for (i
= 0; i
< 16; i
++)
4192 if (mask
& (1 << i
))
4193 unwind
.frame_size
+= 8;
4196 /* Attempt to combine with a previous opcode. We do this because gcc
4197 likes to output separate unwind directives for a single block of
4199 if (unwind
.opcode_count
> 0)
4201 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4202 if ((i
& 0xf8) == 0xc0)
4205 /* Only merge if the blocks are contiguous. */
4208 if ((mask
& 0xfe00) == (1 << 9))
4210 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4211 unwind
.opcode_count
--;
4214 else if (i
== 6 && unwind
.opcode_count
>= 2)
4216 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4220 op
= 0xffff << (reg
- 1);
4222 && ((mask
& op
) == (1u << (reg
- 1))))
4224 op
= (1 << (reg
+ i
+ 1)) - 1;
4225 op
&= ~((1 << reg
) - 1);
4227 unwind
.opcode_count
-= 2;
4234 /* We want to generate opcodes in the order the registers have been
4235 saved, ie. descending order. */
4236 for (reg
= 15; reg
>= -1; reg
--)
4238 /* Save registers in blocks. */
4240 || !(mask
& (1 << reg
)))
4242 /* We found an unsaved reg. Generate opcodes to save the
4249 op
= 0xc0 | (hi_reg
- 10);
4250 add_unwind_opcode (op
, 1);
4255 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4256 add_unwind_opcode (op
, 2);
4265 ignore_rest_of_line ();
4269 s_arm_unwind_save_mmxwcg (void)
4276 if (*input_line_pointer
== '{')
4277 input_line_pointer
++;
4279 skip_whitespace (input_line_pointer
);
4283 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4287 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4293 as_tsktsk (_("register list not in ascending order"));
4296 if (*input_line_pointer
== '-')
4298 input_line_pointer
++;
4299 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4302 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4305 else if (reg
>= hi_reg
)
4307 as_bad (_("bad register range"));
4310 for (; reg
< hi_reg
; reg
++)
4314 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4316 skip_past_char (&input_line_pointer
, '}');
4318 demand_empty_rest_of_line ();
4320 /* Generate any deferred opcodes because we're going to be looking at
4322 flush_pending_unwind ();
4324 for (reg
= 0; reg
< 16; reg
++)
4326 if (mask
& (1 << reg
))
4327 unwind
.frame_size
+= 4;
4330 add_unwind_opcode (op
, 2);
4333 ignore_rest_of_line ();
4337 /* Parse an unwind_save directive.
4338 If the argument is non-zero, this is a .vsave directive. */
4341 s_arm_unwind_save (int arch_v6
)
4344 struct reg_entry
*reg
;
4345 bfd_boolean had_brace
= FALSE
;
4347 if (!unwind
.proc_start
)
4348 as_bad (MISSING_FNSTART
);
4350 /* Figure out what sort of save we have. */
4351 peek
= input_line_pointer
;
4359 reg
= arm_reg_parse_multi (&peek
);
4363 as_bad (_("register expected"));
4364 ignore_rest_of_line ();
4373 as_bad (_("FPA .unwind_save does not take a register list"));
4374 ignore_rest_of_line ();
4377 input_line_pointer
= peek
;
4378 s_arm_unwind_save_fpa (reg
->number
);
4382 s_arm_unwind_save_core ();
4387 s_arm_unwind_save_vfp_armv6 ();
4389 s_arm_unwind_save_vfp ();
4392 case REG_TYPE_MMXWR
:
4393 s_arm_unwind_save_mmxwr ();
4396 case REG_TYPE_MMXWCG
:
4397 s_arm_unwind_save_mmxwcg ();
4401 as_bad (_(".unwind_save does not support this kind of register"));
4402 ignore_rest_of_line ();
4407 /* Parse an unwind_movsp directive. */
4410 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4416 if (!unwind
.proc_start
)
4417 as_bad (MISSING_FNSTART
);
4419 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4422 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4423 ignore_rest_of_line ();
4427 /* Optional constant. */
4428 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4430 if (immediate_for_directive (&offset
) == FAIL
)
4436 demand_empty_rest_of_line ();
4438 if (reg
== REG_SP
|| reg
== REG_PC
)
4440 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4444 if (unwind
.fp_reg
!= REG_SP
)
4445 as_bad (_("unexpected .unwind_movsp directive"));
4447 /* Generate opcode to restore the value. */
4449 add_unwind_opcode (op
, 1);
4451 /* Record the information for later. */
4452 unwind
.fp_reg
= reg
;
4453 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4454 unwind
.sp_restored
= 1;
4457 /* Parse an unwind_pad directive. */
4460 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4464 if (!unwind
.proc_start
)
4465 as_bad (MISSING_FNSTART
);
4467 if (immediate_for_directive (&offset
) == FAIL
)
4472 as_bad (_("stack increment must be multiple of 4"));
4473 ignore_rest_of_line ();
4477 /* Don't generate any opcodes, just record the details for later. */
4478 unwind
.frame_size
+= offset
;
4479 unwind
.pending_offset
+= offset
;
4481 demand_empty_rest_of_line ();
4484 /* Parse an unwind_setfp directive. */
4487 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4493 if (!unwind
.proc_start
)
4494 as_bad (MISSING_FNSTART
);
4496 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4497 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4500 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4502 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4504 as_bad (_("expected <reg>, <reg>"));
4505 ignore_rest_of_line ();
4509 /* Optional constant. */
4510 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4512 if (immediate_for_directive (&offset
) == FAIL
)
4518 demand_empty_rest_of_line ();
4520 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4522 as_bad (_("register must be either sp or set by a previous"
4523 "unwind_movsp directive"));
4527 /* Don't generate any opcodes, just record the information for later. */
4528 unwind
.fp_reg
= fp_reg
;
4530 if (sp_reg
== REG_SP
)
4531 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4533 unwind
.fp_offset
-= offset
;
4536 /* Parse an unwind_raw directive. */
4539 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4542 /* This is an arbitrary limit. */
4543 unsigned char op
[16];
4546 if (!unwind
.proc_start
)
4547 as_bad (MISSING_FNSTART
);
4550 if (exp
.X_op
== O_constant
4551 && skip_past_comma (&input_line_pointer
) != FAIL
)
4553 unwind
.frame_size
+= exp
.X_add_number
;
4557 exp
.X_op
= O_illegal
;
4559 if (exp
.X_op
!= O_constant
)
4561 as_bad (_("expected <offset>, <opcode>"));
4562 ignore_rest_of_line ();
4568 /* Parse the opcode. */
4573 as_bad (_("unwind opcode too long"));
4574 ignore_rest_of_line ();
4576 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4578 as_bad (_("invalid unwind opcode"));
4579 ignore_rest_of_line ();
4582 op
[count
++] = exp
.X_add_number
;
4584 /* Parse the next byte. */
4585 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4591 /* Add the opcode bytes in reverse order. */
4593 add_unwind_opcode (op
[count
], 1);
4595 demand_empty_rest_of_line ();
4599 /* Parse a .eabi_attribute directive. */
4602 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4604 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4606 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4607 attributes_set_explicitly
[tag
] = 1;
4610 /* Emit a tls fix for the symbol. */
4613 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4617 #ifdef md_flush_pending_output
4618 md_flush_pending_output ();
4621 #ifdef md_cons_align
4625 /* Since we're just labelling the code, there's no need to define a
4628 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4629 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4630 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4631 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4633 #endif /* OBJ_ELF */
4635 static void s_arm_arch (int);
4636 static void s_arm_object_arch (int);
4637 static void s_arm_cpu (int);
4638 static void s_arm_fpu (int);
4639 static void s_arm_arch_extension (int);
4644 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4651 if (exp
.X_op
== O_symbol
)
4652 exp
.X_op
= O_secrel
;
4654 emit_expr (&exp
, 4);
4656 while (*input_line_pointer
++ == ',');
4658 input_line_pointer
--;
4659 demand_empty_rest_of_line ();
4663 /* This table describes all the machine specific pseudo-ops the assembler
4664 has to support. The fields are:
4665 pseudo-op name without dot
4666 function to call to execute this pseudo-op
4667 Integer arg to pass to the function. */
4669 const pseudo_typeS md_pseudo_table
[] =
4671 /* Never called because '.req' does not start a line. */
4672 { "req", s_req
, 0 },
4673 /* Following two are likewise never called. */
4676 { "unreq", s_unreq
, 0 },
4677 { "bss", s_bss
, 0 },
4678 { "align", s_align
, 0 },
4679 { "arm", s_arm
, 0 },
4680 { "thumb", s_thumb
, 0 },
4681 { "code", s_code
, 0 },
4682 { "force_thumb", s_force_thumb
, 0 },
4683 { "thumb_func", s_thumb_func
, 0 },
4684 { "thumb_set", s_thumb_set
, 0 },
4685 { "even", s_even
, 0 },
4686 { "ltorg", s_ltorg
, 0 },
4687 { "pool", s_ltorg
, 0 },
4688 { "syntax", s_syntax
, 0 },
4689 { "cpu", s_arm_cpu
, 0 },
4690 { "arch", s_arm_arch
, 0 },
4691 { "object_arch", s_arm_object_arch
, 0 },
4692 { "fpu", s_arm_fpu
, 0 },
4693 { "arch_extension", s_arm_arch_extension
, 0 },
4695 { "word", s_arm_elf_cons
, 4 },
4696 { "long", s_arm_elf_cons
, 4 },
4697 { "inst.n", s_arm_elf_inst
, 2 },
4698 { "inst.w", s_arm_elf_inst
, 4 },
4699 { "inst", s_arm_elf_inst
, 0 },
4700 { "rel31", s_arm_rel31
, 0 },
4701 { "fnstart", s_arm_unwind_fnstart
, 0 },
4702 { "fnend", s_arm_unwind_fnend
, 0 },
4703 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4704 { "personality", s_arm_unwind_personality
, 0 },
4705 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4706 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4707 { "save", s_arm_unwind_save
, 0 },
4708 { "vsave", s_arm_unwind_save
, 1 },
4709 { "movsp", s_arm_unwind_movsp
, 0 },
4710 { "pad", s_arm_unwind_pad
, 0 },
4711 { "setfp", s_arm_unwind_setfp
, 0 },
4712 { "unwind_raw", s_arm_unwind_raw
, 0 },
4713 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4714 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4718 /* These are used for dwarf. */
4722 /* These are used for dwarf2. */
4723 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4724 { "loc", dwarf2_directive_loc
, 0 },
4725 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4727 { "extend", float_cons
, 'x' },
4728 { "ldouble", float_cons
, 'x' },
4729 { "packed", float_cons
, 'p' },
4731 {"secrel32", pe_directive_secrel
, 0},
4734 /* These are for compatibility with CodeComposer Studio. */
4735 {"ref", s_ccs_ref
, 0},
4736 {"def", s_ccs_def
, 0},
4737 {"asmfunc", s_ccs_asmfunc
, 0},
4738 {"endasmfunc", s_ccs_endasmfunc
, 0},
4743 /* Parser functions used exclusively in instruction operands. */
4745 /* Generic immediate-value read function for use in insn parsing.
4746 STR points to the beginning of the immediate (the leading #);
4747 VAL receives the value; if the value is outside [MIN, MAX]
4748 issue an error. PREFIX_OPT is true if the immediate prefix is
4752 parse_immediate (char **str
, int *val
, int min
, int max
,
4753 bfd_boolean prefix_opt
)
4756 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4757 if (exp
.X_op
!= O_constant
)
4759 inst
.error
= _("constant expression required");
4763 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4765 inst
.error
= _("immediate value out of range");
4769 *val
= exp
.X_add_number
;
4773 /* Less-generic immediate-value read function with the possibility of loading a
4774 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4775 instructions. Puts the result directly in inst.operands[i]. */
4778 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4779 bfd_boolean allow_symbol_p
)
4782 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4785 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4787 if (exp_p
->X_op
== O_constant
)
4789 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4790 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4791 O_constant. We have to be careful not to break compilation for
4792 32-bit X_add_number, though. */
4793 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4795 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4796 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4798 inst
.operands
[i
].regisimm
= 1;
4801 else if (exp_p
->X_op
== O_big
4802 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4804 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4806 /* Bignums have their least significant bits in
4807 generic_bignum[0]. Make sure we put 32 bits in imm and
4808 32 bits in reg, in a (hopefully) portable way. */
4809 gas_assert (parts
!= 0);
4811 /* Make sure that the number is not too big.
4812 PR 11972: Bignums can now be sign-extended to the
4813 size of a .octa so check that the out of range bits
4814 are all zero or all one. */
4815 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4817 LITTLENUM_TYPE m
= -1;
4819 if (generic_bignum
[parts
* 2] != 0
4820 && generic_bignum
[parts
* 2] != m
)
4823 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4824 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4828 inst
.operands
[i
].imm
= 0;
4829 for (j
= 0; j
< parts
; j
++, idx
++)
4830 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4831 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4832 inst
.operands
[i
].reg
= 0;
4833 for (j
= 0; j
< parts
; j
++, idx
++)
4834 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4835 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4836 inst
.operands
[i
].regisimm
= 1;
4838 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4846 /* Returns the pseudo-register number of an FPA immediate constant,
4847 or FAIL if there isn't a valid constant here. */
4850 parse_fpa_immediate (char ** str
)
4852 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4858 /* First try and match exact strings, this is to guarantee
4859 that some formats will work even for cross assembly. */
4861 for (i
= 0; fp_const
[i
]; i
++)
4863 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4867 *str
+= strlen (fp_const
[i
]);
4868 if (is_end_of_line
[(unsigned char) **str
])
4874 /* Just because we didn't get a match doesn't mean that the constant
4875 isn't valid, just that it is in a format that we don't
4876 automatically recognize. Try parsing it with the standard
4877 expression routines. */
4879 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4881 /* Look for a raw floating point number. */
4882 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4883 && is_end_of_line
[(unsigned char) *save_in
])
4885 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4887 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4889 if (words
[j
] != fp_values
[i
][j
])
4893 if (j
== MAX_LITTLENUMS
)
4901 /* Try and parse a more complex expression, this will probably fail
4902 unless the code uses a floating point prefix (eg "0f"). */
4903 save_in
= input_line_pointer
;
4904 input_line_pointer
= *str
;
4905 if (expression (&exp
) == absolute_section
4906 && exp
.X_op
== O_big
4907 && exp
.X_add_number
< 0)
4909 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4911 if (gen_to_words (words
, 5, (long) 15) == 0)
4913 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4915 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4917 if (words
[j
] != fp_values
[i
][j
])
4921 if (j
== MAX_LITTLENUMS
)
4923 *str
= input_line_pointer
;
4924 input_line_pointer
= save_in
;
4931 *str
= input_line_pointer
;
4932 input_line_pointer
= save_in
;
4933 inst
.error
= _("invalid FPA immediate expression");
4937 /* Returns 1 if a number has "quarter-precision" float format
4938 0baBbbbbbc defgh000 00000000 00000000. */
4941 is_quarter_float (unsigned imm
)
4943 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4944 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4948 /* Detect the presence of a floating point or integer zero constant,
4952 parse_ifimm_zero (char **in
)
4956 if (!is_immediate_prefix (**in
))
4961 /* Accept #0x0 as a synonym for #0. */
4962 if (strncmp (*in
, "0x", 2) == 0)
4965 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4970 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4971 &generic_floating_point_number
);
4974 && generic_floating_point_number
.sign
== '+'
4975 && (generic_floating_point_number
.low
4976 > generic_floating_point_number
.leader
))
4982 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4983 0baBbbbbbc defgh000 00000000 00000000.
4984 The zero and minus-zero cases need special handling, since they can't be
4985 encoded in the "quarter-precision" float format, but can nonetheless be
4986 loaded as integer constants. */
4989 parse_qfloat_immediate (char **ccp
, int *immed
)
4993 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4994 int found_fpchar
= 0;
4996 skip_past_char (&str
, '#');
4998 /* We must not accidentally parse an integer as a floating-point number. Make
4999 sure that the value we parse is not an integer by checking for special
5000 characters '.' or 'e'.
5001 FIXME: This is a horrible hack, but doing better is tricky because type
5002 information isn't in a very usable state at parse time. */
5004 skip_whitespace (fpnum
);
5006 if (strncmp (fpnum
, "0x", 2) == 0)
5010 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5011 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5021 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5023 unsigned fpword
= 0;
5026 /* Our FP word must be 32 bits (single-precision FP). */
5027 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5029 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5033 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5046 /* Shift operands. */
5049 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5052 struct asm_shift_name
5055 enum shift_kind kind
;
5058 /* Third argument to parse_shift. */
5059 enum parse_shift_mode
5061 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5062 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5063 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5064 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5065 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5068 /* Parse a <shift> specifier on an ARM data processing instruction.
5069 This has three forms:
5071 (LSL|LSR|ASL|ASR|ROR) Rs
5072 (LSL|LSR|ASL|ASR|ROR) #imm
5075 Note that ASL is assimilated to LSL in the instruction encoding, and
5076 RRX to ROR #0 (which cannot be written as such). */
5079 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5081 const struct asm_shift_name
*shift_name
;
5082 enum shift_kind shift
;
5087 for (p
= *str
; ISALPHA (*p
); p
++)
5092 inst
.error
= _("shift expression expected");
5096 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5099 if (shift_name
== NULL
)
5101 inst
.error
= _("shift expression expected");
5105 shift
= shift_name
->kind
;
5109 case NO_SHIFT_RESTRICT
:
5110 case SHIFT_IMMEDIATE
: break;
5112 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5113 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5115 inst
.error
= _("'LSL' or 'ASR' required");
5120 case SHIFT_LSL_IMMEDIATE
:
5121 if (shift
!= SHIFT_LSL
)
5123 inst
.error
= _("'LSL' required");
5128 case SHIFT_ASR_IMMEDIATE
:
5129 if (shift
!= SHIFT_ASR
)
5131 inst
.error
= _("'ASR' required");
5139 if (shift
!= SHIFT_RRX
)
5141 /* Whitespace can appear here if the next thing is a bare digit. */
5142 skip_whitespace (p
);
5144 if (mode
== NO_SHIFT_RESTRICT
5145 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5147 inst
.operands
[i
].imm
= reg
;
5148 inst
.operands
[i
].immisreg
= 1;
5150 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5153 inst
.operands
[i
].shift_kind
= shift
;
5154 inst
.operands
[i
].shifted
= 1;
5159 /* Parse a <shifter_operand> for an ARM data processing instruction:
5162 #<immediate>, <rotate>
5166 where <shift> is defined by parse_shift above, and <rotate> is a
5167 multiple of 2 between 0 and 30. Validation of immediate operands
5168 is deferred to md_apply_fix. */
5171 parse_shifter_operand (char **str
, int i
)
5176 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5178 inst
.operands
[i
].reg
= value
;
5179 inst
.operands
[i
].isreg
= 1;
5181 /* parse_shift will override this if appropriate */
5182 inst
.reloc
.exp
.X_op
= O_constant
;
5183 inst
.reloc
.exp
.X_add_number
= 0;
5185 if (skip_past_comma (str
) == FAIL
)
5188 /* Shift operation on register. */
5189 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5192 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5195 if (skip_past_comma (str
) == SUCCESS
)
5197 /* #x, y -- ie explicit rotation by Y. */
5198 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5201 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5203 inst
.error
= _("constant expression expected");
5207 value
= exp
.X_add_number
;
5208 if (value
< 0 || value
> 30 || value
% 2 != 0)
5210 inst
.error
= _("invalid rotation");
5213 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5215 inst
.error
= _("invalid constant");
5219 /* Encode as specified. */
5220 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5224 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5225 inst
.reloc
.pc_rel
= 0;
5229 /* Group relocation information. Each entry in the table contains the
5230 textual name of the relocation as may appear in assembler source
5231 and must end with a colon.
5232 Along with this textual name are the relocation codes to be used if
5233 the corresponding instruction is an ALU instruction (ADD or SUB only),
5234 an LDR, an LDRS, or an LDC. */
5236 struct group_reloc_table_entry
5247 /* Varieties of non-ALU group relocation. */
5254 static struct group_reloc_table_entry group_reloc_table
[] =
5255 { /* Program counter relative: */
5257 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5262 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5263 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5264 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5265 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5267 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5272 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5273 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5274 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5275 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5277 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5278 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5279 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5280 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5281 /* Section base relative */
5283 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5288 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5289 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5290 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5291 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5293 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5298 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5299 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5300 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5301 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5303 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5304 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5305 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5306 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5308 /* Given the address of a pointer pointing to the textual name of a group
5309 relocation as may appear in assembler source, attempt to find its details
5310 in group_reloc_table. The pointer will be updated to the character after
5311 the trailing colon. On failure, FAIL will be returned; SUCCESS
5312 otherwise. On success, *entry will be updated to point at the relevant
5313 group_reloc_table entry. */
5316 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5319 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5321 int length
= strlen (group_reloc_table
[i
].name
);
5323 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5324 && (*str
)[length
] == ':')
5326 *out
= &group_reloc_table
[i
];
5327 *str
+= (length
+ 1);
5335 /* Parse a <shifter_operand> for an ARM data processing instruction
5336 (as for parse_shifter_operand) where group relocations are allowed:
5339 #<immediate>, <rotate>
5340 #:<group_reloc>:<expression>
5344 where <group_reloc> is one of the strings defined in group_reloc_table.
5345 The hashes are optional.
5347 Everything else is as for parse_shifter_operand. */
5349 static parse_operand_result
5350 parse_shifter_operand_group_reloc (char **str
, int i
)
5352 /* Determine if we have the sequence of characters #: or just :
5353 coming next. If we do, then we check for a group relocation.
5354 If we don't, punt the whole lot to parse_shifter_operand. */
5356 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5357 || (*str
)[0] == ':')
5359 struct group_reloc_table_entry
*entry
;
5361 if ((*str
)[0] == '#')
5366 /* Try to parse a group relocation. Anything else is an error. */
5367 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5369 inst
.error
= _("unknown group relocation");
5370 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5373 /* We now have the group relocation table entry corresponding to
5374 the name in the assembler source. Next, we parse the expression. */
5375 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5376 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5378 /* Record the relocation type (always the ALU variant here). */
5379 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5380 gas_assert (inst
.reloc
.type
!= 0);
5382 return PARSE_OPERAND_SUCCESS
;
5385 return parse_shifter_operand (str
, i
) == SUCCESS
5386 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5388 /* Never reached. */
5391 /* Parse a Neon alignment expression. Information is written to
5392 inst.operands[i]. We assume the initial ':' has been skipped.
5394 align .imm = align << 8, .immisalign=1, .preind=0 */
5395 static parse_operand_result
5396 parse_neon_alignment (char **str
, int i
)
5401 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5403 if (exp
.X_op
!= O_constant
)
5405 inst
.error
= _("alignment must be constant");
5406 return PARSE_OPERAND_FAIL
;
5409 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5410 inst
.operands
[i
].immisalign
= 1;
5411 /* Alignments are not pre-indexes. */
5412 inst
.operands
[i
].preind
= 0;
5415 return PARSE_OPERAND_SUCCESS
;
5418 /* Parse all forms of an ARM address expression. Information is written
5419 to inst.operands[i] and/or inst.reloc.
5421 Preindexed addressing (.preind=1):
5423 [Rn, #offset] .reg=Rn .reloc.exp=offset
5424 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5425 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5426 .shift_kind=shift .reloc.exp=shift_imm
5428 These three may have a trailing ! which causes .writeback to be set also.
5430 Postindexed addressing (.postind=1, .writeback=1):
5432 [Rn], #offset .reg=Rn .reloc.exp=offset
5433 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5434 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5435 .shift_kind=shift .reloc.exp=shift_imm
5437 Unindexed addressing (.preind=0, .postind=0):
5439 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5443 [Rn]{!} shorthand for [Rn,#0]{!}
5444 =immediate .isreg=0 .reloc.exp=immediate
5445 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5447 It is the caller's responsibility to check for addressing modes not
5448 supported by the instruction, and to set inst.reloc.type. */
5450 static parse_operand_result
5451 parse_address_main (char **str
, int i
, int group_relocations
,
5452 group_reloc_type group_type
)
5457 if (skip_past_char (&p
, '[') == FAIL
)
5459 if (skip_past_char (&p
, '=') == FAIL
)
5461 /* Bare address - translate to PC-relative offset. */
5462 inst
.reloc
.pc_rel
= 1;
5463 inst
.operands
[i
].reg
= REG_PC
;
5464 inst
.operands
[i
].isreg
= 1;
5465 inst
.operands
[i
].preind
= 1;
5467 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5468 return PARSE_OPERAND_FAIL
;
5470 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5471 /*allow_symbol_p=*/TRUE
))
5472 return PARSE_OPERAND_FAIL
;
5475 return PARSE_OPERAND_SUCCESS
;
5478 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5479 skip_whitespace (p
);
5481 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5483 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5484 return PARSE_OPERAND_FAIL
;
5486 inst
.operands
[i
].reg
= reg
;
5487 inst
.operands
[i
].isreg
= 1;
5489 if (skip_past_comma (&p
) == SUCCESS
)
5491 inst
.operands
[i
].preind
= 1;
5494 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5496 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5498 inst
.operands
[i
].imm
= reg
;
5499 inst
.operands
[i
].immisreg
= 1;
5501 if (skip_past_comma (&p
) == SUCCESS
)
5502 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5503 return PARSE_OPERAND_FAIL
;
5505 else if (skip_past_char (&p
, ':') == SUCCESS
)
5507 /* FIXME: '@' should be used here, but it's filtered out by generic
5508 code before we get to see it here. This may be subject to
5510 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5512 if (result
!= PARSE_OPERAND_SUCCESS
)
5517 if (inst
.operands
[i
].negative
)
5519 inst
.operands
[i
].negative
= 0;
5523 if (group_relocations
5524 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5526 struct group_reloc_table_entry
*entry
;
5528 /* Skip over the #: or : sequence. */
5534 /* Try to parse a group relocation. Anything else is an
5536 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5538 inst
.error
= _("unknown group relocation");
5539 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5542 /* We now have the group relocation table entry corresponding to
5543 the name in the assembler source. Next, we parse the
5545 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5546 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5548 /* Record the relocation type. */
5552 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5556 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5560 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5567 if (inst
.reloc
.type
== 0)
5569 inst
.error
= _("this group relocation is not allowed on this instruction");
5570 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5576 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5577 return PARSE_OPERAND_FAIL
;
5578 /* If the offset is 0, find out if it's a +0 or -0. */
5579 if (inst
.reloc
.exp
.X_op
== O_constant
5580 && inst
.reloc
.exp
.X_add_number
== 0)
5582 skip_whitespace (q
);
5586 skip_whitespace (q
);
5589 inst
.operands
[i
].negative
= 1;
5594 else if (skip_past_char (&p
, ':') == SUCCESS
)
5596 /* FIXME: '@' should be used here, but it's filtered out by generic code
5597 before we get to see it here. This may be subject to change. */
5598 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5600 if (result
!= PARSE_OPERAND_SUCCESS
)
5604 if (skip_past_char (&p
, ']') == FAIL
)
5606 inst
.error
= _("']' expected");
5607 return PARSE_OPERAND_FAIL
;
5610 if (skip_past_char (&p
, '!') == SUCCESS
)
5611 inst
.operands
[i
].writeback
= 1;
5613 else if (skip_past_comma (&p
) == SUCCESS
)
5615 if (skip_past_char (&p
, '{') == SUCCESS
)
5617 /* [Rn], {expr} - unindexed, with option */
5618 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5619 0, 255, TRUE
) == FAIL
)
5620 return PARSE_OPERAND_FAIL
;
5622 if (skip_past_char (&p
, '}') == FAIL
)
5624 inst
.error
= _("'}' expected at end of 'option' field");
5625 return PARSE_OPERAND_FAIL
;
5627 if (inst
.operands
[i
].preind
)
5629 inst
.error
= _("cannot combine index with option");
5630 return PARSE_OPERAND_FAIL
;
5633 return PARSE_OPERAND_SUCCESS
;
5637 inst
.operands
[i
].postind
= 1;
5638 inst
.operands
[i
].writeback
= 1;
5640 if (inst
.operands
[i
].preind
)
5642 inst
.error
= _("cannot combine pre- and post-indexing");
5643 return PARSE_OPERAND_FAIL
;
5647 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5649 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5651 /* We might be using the immediate for alignment already. If we
5652 are, OR the register number into the low-order bits. */
5653 if (inst
.operands
[i
].immisalign
)
5654 inst
.operands
[i
].imm
|= reg
;
5656 inst
.operands
[i
].imm
= reg
;
5657 inst
.operands
[i
].immisreg
= 1;
5659 if (skip_past_comma (&p
) == SUCCESS
)
5660 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5661 return PARSE_OPERAND_FAIL
;
5666 if (inst
.operands
[i
].negative
)
5668 inst
.operands
[i
].negative
= 0;
5671 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5672 return PARSE_OPERAND_FAIL
;
5673 /* If the offset is 0, find out if it's a +0 or -0. */
5674 if (inst
.reloc
.exp
.X_op
== O_constant
5675 && inst
.reloc
.exp
.X_add_number
== 0)
5677 skip_whitespace (q
);
5681 skip_whitespace (q
);
5684 inst
.operands
[i
].negative
= 1;
5690 /* If at this point neither .preind nor .postind is set, we have a
5691 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5692 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5694 inst
.operands
[i
].preind
= 1;
5695 inst
.reloc
.exp
.X_op
= O_constant
;
5696 inst
.reloc
.exp
.X_add_number
= 0;
5699 return PARSE_OPERAND_SUCCESS
;
5703 parse_address (char **str
, int i
)
5705 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5709 static parse_operand_result
5710 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5712 return parse_address_main (str
, i
, 1, type
);
5715 /* Parse an operand for a MOVW or MOVT instruction. */
5717 parse_half (char **str
)
5722 skip_past_char (&p
, '#');
5723 if (strncasecmp (p
, ":lower16:", 9) == 0)
5724 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5725 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5726 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5728 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5731 skip_whitespace (p
);
5734 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5737 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5739 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5741 inst
.error
= _("constant expression expected");
5744 if (inst
.reloc
.exp
.X_add_number
< 0
5745 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5747 inst
.error
= _("immediate value out of range");
5755 /* Miscellaneous. */
5757 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5758 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5760 parse_psr (char **str
, bfd_boolean lhs
)
5763 unsigned long psr_field
;
5764 const struct asm_psr
*psr
;
5766 bfd_boolean is_apsr
= FALSE
;
5767 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5769 /* PR gas/12698: If the user has specified -march=all then m_profile will
5770 be TRUE, but we want to ignore it in this case as we are building for any
5771 CPU type, including non-m variants. */
5772 if (selected_cpu
.core
== arm_arch_any
.core
)
5775 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5776 feature for ease of use and backwards compatibility. */
5778 if (strncasecmp (p
, "SPSR", 4) == 0)
5781 goto unsupported_psr
;
5783 psr_field
= SPSR_BIT
;
5785 else if (strncasecmp (p
, "CPSR", 4) == 0)
5788 goto unsupported_psr
;
5792 else if (strncasecmp (p
, "APSR", 4) == 0)
5794 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5795 and ARMv7-R architecture CPUs. */
5804 while (ISALNUM (*p
) || *p
== '_');
5806 if (strncasecmp (start
, "iapsr", 5) == 0
5807 || strncasecmp (start
, "eapsr", 5) == 0
5808 || strncasecmp (start
, "xpsr", 4) == 0
5809 || strncasecmp (start
, "psr", 3) == 0)
5810 p
= start
+ strcspn (start
, "rR") + 1;
5812 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5818 /* If APSR is being written, a bitfield may be specified. Note that
5819 APSR itself is handled above. */
5820 if (psr
->field
<= 3)
5822 psr_field
= psr
->field
;
5828 /* M-profile MSR instructions have the mask field set to "10", except
5829 *PSR variants which modify APSR, which may use a different mask (and
5830 have been handled already). Do that by setting the PSR_f field
5832 return psr
->field
| (lhs
? PSR_f
: 0);
5835 goto unsupported_psr
;
5841 /* A suffix follows. */
5847 while (ISALNUM (*p
) || *p
== '_');
5851 /* APSR uses a notation for bits, rather than fields. */
5852 unsigned int nzcvq_bits
= 0;
5853 unsigned int g_bit
= 0;
5856 for (bit
= start
; bit
!= p
; bit
++)
5858 switch (TOLOWER (*bit
))
5861 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5865 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5869 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5873 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5877 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5881 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5885 inst
.error
= _("unexpected bit specified after APSR");
5890 if (nzcvq_bits
== 0x1f)
5895 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5897 inst
.error
= _("selected processor does not "
5898 "support DSP extension");
5905 if ((nzcvq_bits
& 0x20) != 0
5906 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5907 || (g_bit
& 0x2) != 0)
5909 inst
.error
= _("bad bitmask specified after APSR");
5915 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5920 psr_field
|= psr
->field
;
5926 goto error
; /* Garbage after "[CS]PSR". */
5928 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5929 is deprecated, but allow it anyway. */
5933 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5936 else if (!m_profile
)
5937 /* These bits are never right for M-profile devices: don't set them
5938 (only code paths which read/write APSR reach here). */
5939 psr_field
|= (PSR_c
| PSR_f
);
5945 inst
.error
= _("selected processor does not support requested special "
5946 "purpose register");
5950 inst
.error
= _("flag for {c}psr instruction expected");
5954 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5955 value suitable for splatting into the AIF field of the instruction. */
5958 parse_cps_flags (char **str
)
5967 case '\0': case ',':
5970 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5971 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5972 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5975 inst
.error
= _("unrecognized CPS flag");
5980 if (saw_a_flag
== 0)
5982 inst
.error
= _("missing CPS flags");
5990 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5991 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5994 parse_endian_specifier (char **str
)
5999 if (strncasecmp (s
, "BE", 2))
6001 else if (strncasecmp (s
, "LE", 2))
6005 inst
.error
= _("valid endian specifiers are be or le");
6009 if (ISALNUM (s
[2]) || s
[2] == '_')
6011 inst
.error
= _("valid endian specifiers are be or le");
6016 return little_endian
;
6019 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6020 value suitable for poking into the rotate field of an sxt or sxta
6021 instruction, or FAIL on error. */
6024 parse_ror (char **str
)
6029 if (strncasecmp (s
, "ROR", 3) == 0)
6033 inst
.error
= _("missing rotation field after comma");
6037 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6042 case 0: *str
= s
; return 0x0;
6043 case 8: *str
= s
; return 0x1;
6044 case 16: *str
= s
; return 0x2;
6045 case 24: *str
= s
; return 0x3;
6048 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6053 /* Parse a conditional code (from conds[] below). The value returned is in the
6054 range 0 .. 14, or FAIL. */
6056 parse_cond (char **str
)
6059 const struct asm_cond
*c
;
6061 /* Condition codes are always 2 characters, so matching up to
6062 3 characters is sufficient. */
6067 while (ISALPHA (*q
) && n
< 3)
6069 cond
[n
] = TOLOWER (*q
);
6074 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6077 inst
.error
= _("condition required");
6085 /* If the given feature available in the selected CPU, mark it as used.
6086 Returns TRUE iff feature is available. */
6088 mark_feature_used (const arm_feature_set
*feature
)
6090 /* Ensure the option is valid on the current architecture. */
6091 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6094 /* Add the appropriate architecture feature for the barrier option used.
6097 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6099 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6104 /* Parse an option for a barrier instruction. Returns the encoding for the
6107 parse_barrier (char **str
)
6110 const struct asm_barrier_opt
*o
;
6113 while (ISALPHA (*q
))
6116 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6121 if (!mark_feature_used (&o
->arch
))
6128 /* Parse the operands of a table branch instruction. Similar to a memory
6131 parse_tb (char **str
)
6136 if (skip_past_char (&p
, '[') == FAIL
)
6138 inst
.error
= _("'[' expected");
6142 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6144 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6147 inst
.operands
[0].reg
= reg
;
6149 if (skip_past_comma (&p
) == FAIL
)
6151 inst
.error
= _("',' expected");
6155 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6157 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6160 inst
.operands
[0].imm
= reg
;
6162 if (skip_past_comma (&p
) == SUCCESS
)
6164 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6166 if (inst
.reloc
.exp
.X_add_number
!= 1)
6168 inst
.error
= _("invalid shift");
6171 inst
.operands
[0].shifted
= 1;
6174 if (skip_past_char (&p
, ']') == FAIL
)
6176 inst
.error
= _("']' expected");
6183 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6184 information on the types the operands can take and how they are encoded.
6185 Up to four operands may be read; this function handles setting the
6186 ".present" field for each read operand itself.
6187 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6188 else returns FAIL. */
6191 parse_neon_mov (char **str
, int *which_operand
)
6193 int i
= *which_operand
, val
;
6194 enum arm_reg_type rtype
;
6196 struct neon_type_el optype
;
6198 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6200 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6201 inst
.operands
[i
].reg
= val
;
6202 inst
.operands
[i
].isscalar
= 1;
6203 inst
.operands
[i
].vectype
= optype
;
6204 inst
.operands
[i
++].present
= 1;
6206 if (skip_past_comma (&ptr
) == FAIL
)
6209 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6212 inst
.operands
[i
].reg
= val
;
6213 inst
.operands
[i
].isreg
= 1;
6214 inst
.operands
[i
].present
= 1;
6216 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6219 /* Cases 0, 1, 2, 3, 5 (D only). */
6220 if (skip_past_comma (&ptr
) == FAIL
)
6223 inst
.operands
[i
].reg
= val
;
6224 inst
.operands
[i
].isreg
= 1;
6225 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6226 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6227 inst
.operands
[i
].isvec
= 1;
6228 inst
.operands
[i
].vectype
= optype
;
6229 inst
.operands
[i
++].present
= 1;
6231 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6233 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6234 Case 13: VMOV <Sd>, <Rm> */
6235 inst
.operands
[i
].reg
= val
;
6236 inst
.operands
[i
].isreg
= 1;
6237 inst
.operands
[i
].present
= 1;
6239 if (rtype
== REG_TYPE_NQ
)
6241 first_error (_("can't use Neon quad register here"));
6244 else if (rtype
!= REG_TYPE_VFS
)
6247 if (skip_past_comma (&ptr
) == FAIL
)
6249 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isreg
= 1;
6253 inst
.operands
[i
].present
= 1;
6256 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6259 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6260 Case 1: VMOV<c><q> <Dd>, <Dm>
6261 Case 8: VMOV.F32 <Sd>, <Sm>
6262 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6264 inst
.operands
[i
].reg
= val
;
6265 inst
.operands
[i
].isreg
= 1;
6266 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6267 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6268 inst
.operands
[i
].isvec
= 1;
6269 inst
.operands
[i
].vectype
= optype
;
6270 inst
.operands
[i
].present
= 1;
6272 if (skip_past_comma (&ptr
) == SUCCESS
)
6277 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6280 inst
.operands
[i
].reg
= val
;
6281 inst
.operands
[i
].isreg
= 1;
6282 inst
.operands
[i
++].present
= 1;
6284 if (skip_past_comma (&ptr
) == FAIL
)
6287 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6290 inst
.operands
[i
].reg
= val
;
6291 inst
.operands
[i
].isreg
= 1;
6292 inst
.operands
[i
].present
= 1;
6295 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6296 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6297 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6298 Case 10: VMOV.F32 <Sd>, #<imm>
6299 Case 11: VMOV.F64 <Dd>, #<imm> */
6300 inst
.operands
[i
].immisfloat
= 1;
6301 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6303 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6304 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6308 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6312 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6315 inst
.operands
[i
].reg
= val
;
6316 inst
.operands
[i
].isreg
= 1;
6317 inst
.operands
[i
++].present
= 1;
6319 if (skip_past_comma (&ptr
) == FAIL
)
6322 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6324 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6325 inst
.operands
[i
].reg
= val
;
6326 inst
.operands
[i
].isscalar
= 1;
6327 inst
.operands
[i
].present
= 1;
6328 inst
.operands
[i
].vectype
= optype
;
6330 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6332 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
++].present
= 1;
6337 if (skip_past_comma (&ptr
) == FAIL
)
6340 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6343 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6347 inst
.operands
[i
].reg
= val
;
6348 inst
.operands
[i
].isreg
= 1;
6349 inst
.operands
[i
].isvec
= 1;
6350 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6351 inst
.operands
[i
].vectype
= optype
;
6352 inst
.operands
[i
].present
= 1;
6354 if (rtype
== REG_TYPE_VFS
)
6358 if (skip_past_comma (&ptr
) == FAIL
)
6360 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6363 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6366 inst
.operands
[i
].reg
= val
;
6367 inst
.operands
[i
].isreg
= 1;
6368 inst
.operands
[i
].isvec
= 1;
6369 inst
.operands
[i
].issingle
= 1;
6370 inst
.operands
[i
].vectype
= optype
;
6371 inst
.operands
[i
].present
= 1;
6374 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6378 inst
.operands
[i
].reg
= val
;
6379 inst
.operands
[i
].isreg
= 1;
6380 inst
.operands
[i
].isvec
= 1;
6381 inst
.operands
[i
].issingle
= 1;
6382 inst
.operands
[i
].vectype
= optype
;
6383 inst
.operands
[i
].present
= 1;
6388 first_error (_("parse error"));
6392 /* Successfully parsed the operands. Update args. */
6398 first_error (_("expected comma"));
6402 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6406 /* Use this macro when the operand constraints are different
6407 for ARM and THUMB (e.g. ldrd). */
6408 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6409 ((arm_operand) | ((thumb_operand) << 16))
6411 /* Matcher codes for parse_operands. */
6412 enum operand_parse_code
6414 OP_stop
, /* end of line */
6416 OP_RR
, /* ARM register */
6417 OP_RRnpc
, /* ARM register, not r15 */
6418 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6419 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6420 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6421 optional trailing ! */
6422 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6423 OP_RCP
, /* Coprocessor number */
6424 OP_RCN
, /* Coprocessor register */
6425 OP_RF
, /* FPA register */
6426 OP_RVS
, /* VFP single precision register */
6427 OP_RVD
, /* VFP double precision register (0..15) */
6428 OP_RND
, /* Neon double precision register (0..31) */
6429 OP_RNQ
, /* Neon quad precision register */
6430 OP_RVSD
, /* VFP single or double precision register */
6431 OP_RNDQ
, /* Neon double or quad precision register */
6432 OP_RNSDQ
, /* Neon single, double or quad precision register */
6433 OP_RNSC
, /* Neon scalar D[X] */
6434 OP_RVC
, /* VFP control register */
6435 OP_RMF
, /* Maverick F register */
6436 OP_RMD
, /* Maverick D register */
6437 OP_RMFX
, /* Maverick FX register */
6438 OP_RMDX
, /* Maverick DX register */
6439 OP_RMAX
, /* Maverick AX register */
6440 OP_RMDS
, /* Maverick DSPSC register */
6441 OP_RIWR
, /* iWMMXt wR register */
6442 OP_RIWC
, /* iWMMXt wC register */
6443 OP_RIWG
, /* iWMMXt wCG register */
6444 OP_RXA
, /* XScale accumulator register */
6446 OP_REGLST
, /* ARM register list */
6447 OP_VRSLST
, /* VFP single-precision register list */
6448 OP_VRDLST
, /* VFP double-precision register list */
6449 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6450 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6451 OP_NSTRLST
, /* Neon element/structure list */
6453 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6454 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6455 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6456 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6457 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6458 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6459 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6460 OP_VMOV
, /* Neon VMOV operands. */
6461 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6462 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6463 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6465 OP_I0
, /* immediate zero */
6466 OP_I7
, /* immediate value 0 .. 7 */
6467 OP_I15
, /* 0 .. 15 */
6468 OP_I16
, /* 1 .. 16 */
6469 OP_I16z
, /* 0 .. 16 */
6470 OP_I31
, /* 0 .. 31 */
6471 OP_I31w
, /* 0 .. 31, optional trailing ! */
6472 OP_I32
, /* 1 .. 32 */
6473 OP_I32z
, /* 0 .. 32 */
6474 OP_I63
, /* 0 .. 63 */
6475 OP_I63s
, /* -64 .. 63 */
6476 OP_I64
, /* 1 .. 64 */
6477 OP_I64z
, /* 0 .. 64 */
6478 OP_I255
, /* 0 .. 255 */
6480 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6481 OP_I7b
, /* 0 .. 7 */
6482 OP_I15b
, /* 0 .. 15 */
6483 OP_I31b
, /* 0 .. 31 */
6485 OP_SH
, /* shifter operand */
6486 OP_SHG
, /* shifter operand with possible group relocation */
6487 OP_ADDR
, /* Memory address expression (any mode) */
6488 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6489 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6490 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6491 OP_EXP
, /* arbitrary expression */
6492 OP_EXPi
, /* same, with optional immediate prefix */
6493 OP_EXPr
, /* same, with optional relocation suffix */
6494 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6496 OP_CPSF
, /* CPS flags */
6497 OP_ENDI
, /* Endianness specifier */
6498 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6499 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6500 OP_COND
, /* conditional code */
6501 OP_TB
, /* Table branch. */
6503 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6505 OP_RRnpc_I0
, /* ARM register or literal 0 */
6506 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6507 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6508 OP_RF_IF
, /* FPA register or immediate */
6509 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6510 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6512 /* Optional operands. */
6513 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6514 OP_oI31b
, /* 0 .. 31 */
6515 OP_oI32b
, /* 1 .. 32 */
6516 OP_oI32z
, /* 0 .. 32 */
6517 OP_oIffffb
, /* 0 .. 65535 */
6518 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6520 OP_oRR
, /* ARM register */
6521 OP_oRRnpc
, /* ARM register, not the PC */
6522 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6523 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6524 OP_oRND
, /* Optional Neon double precision register */
6525 OP_oRNQ
, /* Optional Neon quad precision register */
6526 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6527 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6528 OP_oSHll
, /* LSL immediate */
6529 OP_oSHar
, /* ASR immediate */
6530 OP_oSHllar
, /* LSL or ASR immediate */
6531 OP_oROR
, /* ROR 0/8/16/24 */
6532 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6534 /* Some pre-defined mixed (ARM/THUMB) operands. */
6535 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6536 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6537 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6539 OP_FIRST_OPTIONAL
= OP_oI7b
6542 /* Generic instruction operand parser. This does no encoding and no
6543 semantic validation; it merely squirrels values away in the inst
6544 structure. Returns SUCCESS or FAIL depending on whether the
6545 specified grammar matched. */
6547 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6549 unsigned const int *upat
= pattern
;
6550 char *backtrack_pos
= 0;
6551 const char *backtrack_error
= 0;
6552 int i
, val
= 0, backtrack_index
= 0;
6553 enum arm_reg_type rtype
;
6554 parse_operand_result result
;
6555 unsigned int op_parse_code
;
6557 #define po_char_or_fail(chr) \
6560 if (skip_past_char (&str, chr) == FAIL) \
6565 #define po_reg_or_fail(regtype) \
6568 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6569 & inst.operands[i].vectype); \
6572 first_error (_(reg_expected_msgs[regtype])); \
6575 inst.operands[i].reg = val; \
6576 inst.operands[i].isreg = 1; \
6577 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6578 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6579 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6580 || rtype == REG_TYPE_VFD \
6581 || rtype == REG_TYPE_NQ); \
6585 #define po_reg_or_goto(regtype, label) \
6588 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6589 & inst.operands[i].vectype); \
6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6598 || rtype == REG_TYPE_VFD \
6599 || rtype == REG_TYPE_NQ); \
6603 #define po_imm_or_fail(min, max, popt) \
6606 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6608 inst.operands[i].imm = val; \
6612 #define po_scalar_or_goto(elsz, label) \
6615 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6618 inst.operands[i].reg = val; \
6619 inst.operands[i].isscalar = 1; \
6623 #define po_misc_or_fail(expr) \
6631 #define po_misc_or_fail_no_backtrack(expr) \
6635 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6636 backtrack_pos = 0; \
6637 if (result != PARSE_OPERAND_SUCCESS) \
6642 #define po_barrier_or_imm(str) \
6645 val = parse_barrier (&str); \
6646 if (val == FAIL && ! ISALPHA (*str)) \
6649 /* ISB can only take SY as an option. */ \
6650 || ((inst.instruction & 0xf0) == 0x60 \
6653 inst.error = _("invalid barrier type"); \
6654 backtrack_pos = 0; \
6660 skip_whitespace (str
);
6662 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6664 op_parse_code
= upat
[i
];
6665 if (op_parse_code
>= 1<<16)
6666 op_parse_code
= thumb
? (op_parse_code
>> 16)
6667 : (op_parse_code
& ((1<<16)-1));
6669 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6671 /* Remember where we are in case we need to backtrack. */
6672 gas_assert (!backtrack_pos
);
6673 backtrack_pos
= str
;
6674 backtrack_error
= inst
.error
;
6675 backtrack_index
= i
;
6678 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6679 po_char_or_fail (',');
6681 switch (op_parse_code
)
6689 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6690 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6691 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6692 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6693 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6694 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6696 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6698 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6700 /* Also accept generic coprocessor regs for unknown registers. */
6702 po_reg_or_fail (REG_TYPE_CN
);
6704 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6705 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6706 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6707 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6708 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6709 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6710 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6711 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6712 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6713 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6715 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6717 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6718 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6720 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6722 /* Neon scalar. Using an element size of 8 means that some invalid
6723 scalars are accepted here, so deal with those in later code. */
6724 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6728 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6731 po_imm_or_fail (0, 0, TRUE
);
6736 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6741 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6744 if (parse_ifimm_zero (&str
))
6745 inst
.operands
[i
].imm
= 0;
6749 = _("only floating point zero is allowed as immediate value");
6757 po_scalar_or_goto (8, try_rr
);
6760 po_reg_or_fail (REG_TYPE_RN
);
6766 po_scalar_or_goto (8, try_nsdq
);
6769 po_reg_or_fail (REG_TYPE_NSDQ
);
6775 po_scalar_or_goto (8, try_ndq
);
6778 po_reg_or_fail (REG_TYPE_NDQ
);
6784 po_scalar_or_goto (8, try_vfd
);
6787 po_reg_or_fail (REG_TYPE_VFD
);
6792 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6793 not careful then bad things might happen. */
6794 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6799 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6802 /* There's a possibility of getting a 64-bit immediate here, so
6803 we need special handling. */
6804 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6807 inst
.error
= _("immediate value is out of range");
6815 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6818 po_imm_or_fail (0, 63, TRUE
);
6823 po_char_or_fail ('[');
6824 po_reg_or_fail (REG_TYPE_RN
);
6825 po_char_or_fail (']');
6831 po_reg_or_fail (REG_TYPE_RN
);
6832 if (skip_past_char (&str
, '!') == SUCCESS
)
6833 inst
.operands
[i
].writeback
= 1;
6837 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6838 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6839 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6840 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6841 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6842 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6843 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6844 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6845 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6846 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6847 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6848 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6850 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6852 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6853 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6855 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6856 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6857 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6858 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6860 /* Immediate variants */
6862 po_char_or_fail ('{');
6863 po_imm_or_fail (0, 255, TRUE
);
6864 po_char_or_fail ('}');
6868 /* The expression parser chokes on a trailing !, so we have
6869 to find it first and zap it. */
6872 while (*s
&& *s
!= ',')
6877 inst
.operands
[i
].writeback
= 1;
6879 po_imm_or_fail (0, 31, TRUE
);
6887 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6892 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6897 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6899 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6901 val
= parse_reloc (&str
);
6904 inst
.error
= _("unrecognized relocation suffix");
6907 else if (val
!= BFD_RELOC_UNUSED
)
6909 inst
.operands
[i
].imm
= val
;
6910 inst
.operands
[i
].hasreloc
= 1;
6915 /* Operand for MOVW or MOVT. */
6917 po_misc_or_fail (parse_half (&str
));
6920 /* Register or expression. */
6921 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6922 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6924 /* Register or immediate. */
6925 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6926 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6928 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6930 if (!is_immediate_prefix (*str
))
6933 val
= parse_fpa_immediate (&str
);
6936 /* FPA immediates are encoded as registers 8-15.
6937 parse_fpa_immediate has already applied the offset. */
6938 inst
.operands
[i
].reg
= val
;
6939 inst
.operands
[i
].isreg
= 1;
6942 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6943 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6945 /* Two kinds of register. */
6948 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6950 || (rege
->type
!= REG_TYPE_MMXWR
6951 && rege
->type
!= REG_TYPE_MMXWC
6952 && rege
->type
!= REG_TYPE_MMXWCG
))
6954 inst
.error
= _("iWMMXt data or control register expected");
6957 inst
.operands
[i
].reg
= rege
->number
;
6958 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6964 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6966 || (rege
->type
!= REG_TYPE_MMXWC
6967 && rege
->type
!= REG_TYPE_MMXWCG
))
6969 inst
.error
= _("iWMMXt control register expected");
6972 inst
.operands
[i
].reg
= rege
->number
;
6973 inst
.operands
[i
].isreg
= 1;
6978 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6979 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6980 case OP_oROR
: val
= parse_ror (&str
); break;
6981 case OP_COND
: val
= parse_cond (&str
); break;
6982 case OP_oBARRIER_I15
:
6983 po_barrier_or_imm (str
); break;
6985 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6991 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6992 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6994 inst
.error
= _("Banked registers are not available with this "
7000 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7004 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7007 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7009 if (strncasecmp (str
, "APSR_", 5) == 0)
7016 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7017 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7018 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7019 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7020 default: found
= 16;
7024 inst
.operands
[i
].isvec
= 1;
7025 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7026 inst
.operands
[i
].reg
= REG_PC
;
7033 po_misc_or_fail (parse_tb (&str
));
7036 /* Register lists. */
7038 val
= parse_reg_list (&str
);
7041 inst
.operands
[1].writeback
= 1;
7047 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7051 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7055 /* Allow Q registers too. */
7056 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7061 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7063 inst
.operands
[i
].issingle
= 1;
7068 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7073 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7074 &inst
.operands
[i
].vectype
);
7077 /* Addressing modes */
7079 po_misc_or_fail (parse_address (&str
, i
));
7083 po_misc_or_fail_no_backtrack (
7084 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7088 po_misc_or_fail_no_backtrack (
7089 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7093 po_misc_or_fail_no_backtrack (
7094 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7098 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7102 po_misc_or_fail_no_backtrack (
7103 parse_shifter_operand_group_reloc (&str
, i
));
7107 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7111 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7115 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7119 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7122 /* Various value-based sanity checks and shared operations. We
7123 do not signal immediate failures for the register constraints;
7124 this allows a syntax error to take precedence. */
7125 switch (op_parse_code
)
7133 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7134 inst
.error
= BAD_PC
;
7139 if (inst
.operands
[i
].isreg
)
7141 if (inst
.operands
[i
].reg
== REG_PC
)
7142 inst
.error
= BAD_PC
;
7143 else if (inst
.operands
[i
].reg
== REG_SP
)
7144 inst
.error
= BAD_SP
;
7149 if (inst
.operands
[i
].isreg
7150 && inst
.operands
[i
].reg
== REG_PC
7151 && (inst
.operands
[i
].writeback
|| thumb
))
7152 inst
.error
= BAD_PC
;
7161 case OP_oBARRIER_I15
:
7170 inst
.operands
[i
].imm
= val
;
7177 /* If we get here, this operand was successfully parsed. */
7178 inst
.operands
[i
].present
= 1;
7182 inst
.error
= BAD_ARGS
;
7187 /* The parse routine should already have set inst.error, but set a
7188 default here just in case. */
7190 inst
.error
= _("syntax error");
7194 /* Do not backtrack over a trailing optional argument that
7195 absorbed some text. We will only fail again, with the
7196 'garbage following instruction' error message, which is
7197 probably less helpful than the current one. */
7198 if (backtrack_index
== i
&& backtrack_pos
!= str
7199 && upat
[i
+1] == OP_stop
)
7202 inst
.error
= _("syntax error");
7206 /* Try again, skipping the optional argument at backtrack_pos. */
7207 str
= backtrack_pos
;
7208 inst
.error
= backtrack_error
;
7209 inst
.operands
[backtrack_index
].present
= 0;
7210 i
= backtrack_index
;
7214 /* Check that we have parsed all the arguments. */
7215 if (*str
!= '\0' && !inst
.error
)
7216 inst
.error
= _("garbage following instruction");
7218 return inst
.error
? FAIL
: SUCCESS
;
7221 #undef po_char_or_fail
7222 #undef po_reg_or_fail
7223 #undef po_reg_or_goto
7224 #undef po_imm_or_fail
7225 #undef po_scalar_or_fail
7226 #undef po_barrier_or_imm
7228 /* Shorthand macro for instruction encoding functions issuing errors. */
7229 #define constraint(expr, err) \
7240 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7241 instructions are unpredictable if these registers are used. This
7242 is the BadReg predicate in ARM's Thumb-2 documentation. */
7243 #define reject_bad_reg(reg) \
7245 if (reg == REG_SP || reg == REG_PC) \
7247 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7252 /* If REG is R13 (the stack pointer), warn that its use is
7254 #define warn_deprecated_sp(reg) \
7256 if (warn_on_deprecated && reg == REG_SP) \
7257 as_tsktsk (_("use of r13 is deprecated")); \
7260 /* Functions for operand encoding. ARM, then Thumb. */
7262 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7264 /* If VAL can be encoded in the immediate field of an ARM instruction,
7265 return the encoded form. Otherwise, return FAIL. */
7268 encode_arm_immediate (unsigned int val
)
7272 for (i
= 0; i
< 32; i
+= 2)
7273 if ((a
= rotate_left (val
, i
)) <= 0xff)
7274 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7279 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7280 return the encoded form. Otherwise, return FAIL. */
7282 encode_thumb32_immediate (unsigned int val
)
7289 for (i
= 1; i
<= 24; i
++)
7292 if ((val
& ~(0xff << i
)) == 0)
7293 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7297 if (val
== ((a
<< 16) | a
))
7299 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7303 if (val
== ((a
<< 16) | a
))
7304 return 0x200 | (a
>> 8);
7308 /* Encode a VFP SP or DP register number into inst.instruction. */
7311 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7313 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7316 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7319 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7327 first_error (_("D register out of range for selected VFP version"));
7335 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7339 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7343 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7347 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7351 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7355 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7363 /* Encode a <shift> in an ARM-format instruction. The immediate,
7364 if any, is handled by md_apply_fix. */
7366 encode_arm_shift (int i
)
7368 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7369 inst
.instruction
|= SHIFT_ROR
<< 5;
7372 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7373 if (inst
.operands
[i
].immisreg
)
7375 inst
.instruction
|= SHIFT_BY_REG
;
7376 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7379 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7384 encode_arm_shifter_operand (int i
)
7386 if (inst
.operands
[i
].isreg
)
7388 inst
.instruction
|= inst
.operands
[i
].reg
;
7389 encode_arm_shift (i
);
7393 inst
.instruction
|= INST_IMMEDIATE
;
7394 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7395 inst
.instruction
|= inst
.operands
[i
].imm
;
7399 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7401 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7404 Generate an error if the operand is not a register. */
7405 constraint (!inst
.operands
[i
].isreg
,
7406 _("Instruction does not support =N addresses"));
7408 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7410 if (inst
.operands
[i
].preind
)
7414 inst
.error
= _("instruction does not accept preindexed addressing");
7417 inst
.instruction
|= PRE_INDEX
;
7418 if (inst
.operands
[i
].writeback
)
7419 inst
.instruction
|= WRITE_BACK
;
7422 else if (inst
.operands
[i
].postind
)
7424 gas_assert (inst
.operands
[i
].writeback
);
7426 inst
.instruction
|= WRITE_BACK
;
7428 else /* unindexed - only for coprocessor */
7430 inst
.error
= _("instruction does not accept unindexed addressing");
7434 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7435 && (((inst
.instruction
& 0x000f0000) >> 16)
7436 == ((inst
.instruction
& 0x0000f000) >> 12)))
7437 as_warn ((inst
.instruction
& LOAD_BIT
)
7438 ? _("destination register same as write-back base")
7439 : _("source register same as write-back base"));
7442 /* inst.operands[i] was set up by parse_address. Encode it into an
7443 ARM-format mode 2 load or store instruction. If is_t is true,
7444 reject forms that cannot be used with a T instruction (i.e. not
7447 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7449 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7451 encode_arm_addr_mode_common (i
, is_t
);
7453 if (inst
.operands
[i
].immisreg
)
7455 constraint ((inst
.operands
[i
].imm
== REG_PC
7456 || (is_pc
&& inst
.operands
[i
].writeback
)),
7458 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7459 inst
.instruction
|= inst
.operands
[i
].imm
;
7460 if (!inst
.operands
[i
].negative
)
7461 inst
.instruction
|= INDEX_UP
;
7462 if (inst
.operands
[i
].shifted
)
7464 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7465 inst
.instruction
|= SHIFT_ROR
<< 5;
7468 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7469 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7473 else /* immediate offset in inst.reloc */
7475 if (is_pc
&& !inst
.reloc
.pc_rel
)
7477 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7479 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7480 cannot use PC in addressing.
7481 PC cannot be used in writeback addressing, either. */
7482 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7485 /* Use of PC in str is deprecated for ARMv7. */
7486 if (warn_on_deprecated
7488 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7489 as_tsktsk (_("use of PC in this instruction is deprecated"));
7492 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7494 /* Prefer + for zero encoded value. */
7495 if (!inst
.operands
[i
].negative
)
7496 inst
.instruction
|= INDEX_UP
;
7497 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7502 /* inst.operands[i] was set up by parse_address. Encode it into an
7503 ARM-format mode 3 load or store instruction. Reject forms that
7504 cannot be used with such instructions. If is_t is true, reject
7505 forms that cannot be used with a T instruction (i.e. not
7508 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7510 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7512 inst
.error
= _("instruction does not accept scaled register index");
7516 encode_arm_addr_mode_common (i
, is_t
);
7518 if (inst
.operands
[i
].immisreg
)
7520 constraint ((inst
.operands
[i
].imm
== REG_PC
7521 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7523 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7525 inst
.instruction
|= inst
.operands
[i
].imm
;
7526 if (!inst
.operands
[i
].negative
)
7527 inst
.instruction
|= INDEX_UP
;
7529 else /* immediate offset in inst.reloc */
7531 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7532 && inst
.operands
[i
].writeback
),
7534 inst
.instruction
|= HWOFFSET_IMM
;
7535 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7537 /* Prefer + for zero encoded value. */
7538 if (!inst
.operands
[i
].negative
)
7539 inst
.instruction
|= INDEX_UP
;
7541 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7546 /* Write immediate bits [7:0] to the following locations:
7548 |28/24|23 19|18 16|15 4|3 0|
7549 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7551 This function is used by VMOV/VMVN/VORR/VBIC. */
7554 neon_write_immbits (unsigned immbits
)
7556 inst
.instruction
|= immbits
& 0xf;
7557 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7558 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7561 /* Invert low-order SIZE bits of XHI:XLO. */
7564 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7566 unsigned immlo
= xlo
? *xlo
: 0;
7567 unsigned immhi
= xhi
? *xhi
: 0;
7572 immlo
= (~immlo
) & 0xff;
7576 immlo
= (~immlo
) & 0xffff;
7580 immhi
= (~immhi
) & 0xffffffff;
7584 immlo
= (~immlo
) & 0xffffffff;
7598 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7602 neon_bits_same_in_bytes (unsigned imm
)
7604 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7605 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7606 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7607 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7610 /* For immediate of above form, return 0bABCD. */
7613 neon_squash_bits (unsigned imm
)
7615 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7616 | ((imm
& 0x01000000) >> 21);
7619 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7622 neon_qfloat_bits (unsigned imm
)
7624 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7627 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7628 the instruction. *OP is passed as the initial value of the op field, and
7629 may be set to a different value depending on the constant (i.e.
7630 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7631 MVN). If the immediate looks like a repeated pattern then also
7632 try smaller element sizes. */
7635 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7636 unsigned *immbits
, int *op
, int size
,
7637 enum neon_el_type type
)
7639 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7641 if (type
== NT_float
&& !float_p
)
7644 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7646 if (size
!= 32 || *op
== 1)
7648 *immbits
= neon_qfloat_bits (immlo
);
7654 if (neon_bits_same_in_bytes (immhi
)
7655 && neon_bits_same_in_bytes (immlo
))
7659 *immbits
= (neon_squash_bits (immhi
) << 4)
7660 | neon_squash_bits (immlo
);
7671 if (immlo
== (immlo
& 0x000000ff))
7676 else if (immlo
== (immlo
& 0x0000ff00))
7678 *immbits
= immlo
>> 8;
7681 else if (immlo
== (immlo
& 0x00ff0000))
7683 *immbits
= immlo
>> 16;
7686 else if (immlo
== (immlo
& 0xff000000))
7688 *immbits
= immlo
>> 24;
7691 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7693 *immbits
= (immlo
>> 8) & 0xff;
7696 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7698 *immbits
= (immlo
>> 16) & 0xff;
7702 if ((immlo
& 0xffff) != (immlo
>> 16))
7709 if (immlo
== (immlo
& 0x000000ff))
7714 else if (immlo
== (immlo
& 0x0000ff00))
7716 *immbits
= immlo
>> 8;
7720 if ((immlo
& 0xff) != (immlo
>> 8))
7725 if (immlo
== (immlo
& 0x000000ff))
7727 /* Don't allow MVN with 8-bit immediate. */
7744 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7745 Determine whether it can be performed with a move instruction; if
7746 it can, convert inst.instruction to that move instruction and
7747 return TRUE; if it can't, convert inst.instruction to a literal-pool
7748 load and return FALSE. If this is not a valid thing to do in the
7749 current context, set inst.error and return TRUE.
7751 inst.operands[i] describes the destination register. */
7754 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7757 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7758 bfd_boolean arm_p
= (t
== CONST_ARM
);
7759 bfd_boolean vec64_p
= (t
== CONST_VEC
) && !inst
.operands
[i
].issingle
;
7762 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7766 if ((inst
.instruction
& tbit
) == 0)
7768 inst
.error
= _("invalid pseudo operation");
7771 if (inst
.reloc
.exp
.X_op
!= O_constant
7772 && inst
.reloc
.exp
.X_op
!= O_symbol
7773 && inst
.reloc
.exp
.X_op
!= O_big
)
7775 inst
.error
= _("constant expression expected");
7778 if ((inst
.reloc
.exp
.X_op
== O_constant
7779 || inst
.reloc
.exp
.X_op
== O_big
)
7780 && !inst
.operands
[i
].issingle
)
7782 if (thumb_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7784 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7786 /* This can be done with a mov(1) instruction. */
7787 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7788 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7792 else if (arm_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7794 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7797 /* This can be done with a mov instruction. */
7798 inst
.instruction
&= LITERAL_MASK
;
7799 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7800 inst
.instruction
|= value
& 0xfff;
7804 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7807 /* This can be done with a mvn instruction. */
7808 inst
.instruction
&= LITERAL_MASK
;
7809 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7810 inst
.instruction
|= value
& 0xfff;
7817 unsigned immbits
= 0;
7818 unsigned immlo
= inst
.operands
[1].imm
;
7819 unsigned immhi
= inst
.operands
[1].regisimm
7820 ? inst
.operands
[1].reg
7821 : inst
.reloc
.exp
.X_unsigned
7823 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7824 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7825 &op
, 64, NT_invtype
);
7829 neon_invert_size (&immlo
, &immhi
, 64);
7831 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7832 &op
, 64, NT_invtype
);
7836 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7841 /* Fill other bits in vmov encoding for both thumb and arm. */
7843 inst
.instruction
|= (0x7 << 29) | (0xF << 24);
7845 inst
.instruction
|= (0xF << 28) | (0x1 << 25);
7846 neon_write_immbits (immbits
);
7852 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
7853 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
7856 inst
.operands
[1].reg
= REG_PC
;
7857 inst
.operands
[1].isreg
= 1;
7858 inst
.operands
[1].preind
= 1;
7859 inst
.reloc
.pc_rel
= 1;
7860 inst
.reloc
.type
= (thumb_p
7861 ? BFD_RELOC_ARM_THUMB_OFFSET
7863 ? BFD_RELOC_ARM_HWLITERAL
7864 : BFD_RELOC_ARM_LITERAL
));
7868 /* inst.operands[i] was set up by parse_address. Encode it into an
7869 ARM-format instruction. Reject all forms which cannot be encoded
7870 into a coprocessor load/store instruction. If wb_ok is false,
7871 reject use of writeback; if unind_ok is false, reject use of
7872 unindexed addressing. If reloc_override is not 0, use it instead
7873 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7874 (in which case it is preserved). */
7877 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7879 if (!inst
.operands
[i
].isreg
)
7881 gas_assert (inst
.operands
[0].isvec
);
7882 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
7886 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7888 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7890 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7892 gas_assert (!inst
.operands
[i
].writeback
);
7895 inst
.error
= _("instruction does not support unindexed addressing");
7898 inst
.instruction
|= inst
.operands
[i
].imm
;
7899 inst
.instruction
|= INDEX_UP
;
7903 if (inst
.operands
[i
].preind
)
7904 inst
.instruction
|= PRE_INDEX
;
7906 if (inst
.operands
[i
].writeback
)
7908 if (inst
.operands
[i
].reg
== REG_PC
)
7910 inst
.error
= _("pc may not be used with write-back");
7915 inst
.error
= _("instruction does not support writeback");
7918 inst
.instruction
|= WRITE_BACK
;
7922 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7923 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7924 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7925 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7928 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7930 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7933 /* Prefer + for zero encoded value. */
7934 if (!inst
.operands
[i
].negative
)
7935 inst
.instruction
|= INDEX_UP
;
7940 /* Functions for instruction encoding, sorted by sub-architecture.
7941 First some generics; their names are taken from the conventional
7942 bit positions for register arguments in ARM format instructions. */
7952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7959 inst
.instruction
|= inst
.operands
[1].reg
;
7965 inst
.instruction
|= inst
.operands
[0].reg
;
7966 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7973 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7979 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7980 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7984 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7986 if (ARM_CPU_IS_ANY (cpu_variant
))
7988 as_tsktsk ("%s", msg
);
7991 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8003 unsigned Rn
= inst
.operands
[2].reg
;
8004 /* Enforce restrictions on SWP instruction. */
8005 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8007 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8008 _("Rn must not overlap other operands"));
8010 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8012 if (!check_obsolete (&arm_ext_v8
,
8013 _("swp{b} use is obsoleted for ARMv8 and later"))
8014 && warn_on_deprecated
8015 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8016 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8020 inst
.instruction
|= inst
.operands
[1].reg
;
8021 inst
.instruction
|= Rn
<< 16;
8027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8028 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8029 inst
.instruction
|= inst
.operands
[2].reg
;
8035 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8036 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8037 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8038 || inst
.reloc
.exp
.X_add_number
!= 0),
8040 inst
.instruction
|= inst
.operands
[0].reg
;
8041 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8042 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8048 inst
.instruction
|= inst
.operands
[0].imm
;
8054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8055 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8058 /* ARM instructions, in alphabetical order by function name (except
8059 that wrapper functions appear immediately after the function they
8062 /* This is a pseudo-op of the form "adr rd, label" to be converted
8063 into a relative address of the form "add rd, pc, #label-.-8". */
8068 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8070 /* Frag hacking will turn this into a sub instruction if the offset turns
8071 out to be negative. */
8072 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8073 inst
.reloc
.pc_rel
= 1;
8074 inst
.reloc
.exp
.X_add_number
-= 8;
8077 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8078 into a relative address of the form:
8079 add rd, pc, #low(label-.-8)"
8080 add rd, rd, #high(label-.-8)" */
8085 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8087 /* Frag hacking will turn this into a sub instruction if the offset turns
8088 out to be negative. */
8089 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8090 inst
.reloc
.pc_rel
= 1;
8091 inst
.size
= INSN_SIZE
* 2;
8092 inst
.reloc
.exp
.X_add_number
-= 8;
8098 if (!inst
.operands
[1].present
)
8099 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8102 encode_arm_shifter_operand (2);
8108 if (inst
.operands
[0].present
)
8109 inst
.instruction
|= inst
.operands
[0].imm
;
8111 inst
.instruction
|= 0xf;
8117 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8118 constraint (msb
> 32, _("bit-field extends past end of register"));
8119 /* The instruction encoding stores the LSB and MSB,
8120 not the LSB and width. */
8121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8122 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8123 inst
.instruction
|= (msb
- 1) << 16;
8131 /* #0 in second position is alternative syntax for bfc, which is
8132 the same instruction but with REG_PC in the Rm field. */
8133 if (!inst
.operands
[1].isreg
)
8134 inst
.operands
[1].reg
= REG_PC
;
8136 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8137 constraint (msb
> 32, _("bit-field extends past end of register"));
8138 /* The instruction encoding stores the LSB and MSB,
8139 not the LSB and width. */
8140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8141 inst
.instruction
|= inst
.operands
[1].reg
;
8142 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8143 inst
.instruction
|= (msb
- 1) << 16;
8149 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8150 _("bit-field extends past end of register"));
8151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8152 inst
.instruction
|= inst
.operands
[1].reg
;
8153 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8154 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8157 /* ARM V5 breakpoint instruction (argument parse)
8158 BKPT <16 bit unsigned immediate>
8159 Instruction is not conditional.
8160 The bit pattern given in insns[] has the COND_ALWAYS condition,
8161 and it is an error if the caller tried to override that. */
8166 /* Top 12 of 16 bits to bits 19:8. */
8167 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8169 /* Bottom 4 of 16 bits to bits 3:0. */
8170 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8174 encode_branch (int default_reloc
)
8176 if (inst
.operands
[0].hasreloc
)
8178 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8179 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8180 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8181 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8182 ? BFD_RELOC_ARM_PLT32
8183 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8186 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8187 inst
.reloc
.pc_rel
= 1;
8194 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8195 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8205 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8207 if (inst
.cond
== COND_ALWAYS
)
8208 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8210 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8214 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8217 /* ARM V5 branch-link-exchange instruction (argument parse)
8218 BLX <target_addr> ie BLX(1)
8219 BLX{<condition>} <Rm> ie BLX(2)
8220 Unfortunately, there are two different opcodes for this mnemonic.
8221 So, the insns[].value is not used, and the code here zaps values
8222 into inst.instruction.
8223 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8228 if (inst
.operands
[0].isreg
)
8230 /* Arg is a register; the opcode provided by insns[] is correct.
8231 It is not illegal to do "blx pc", just useless. */
8232 if (inst
.operands
[0].reg
== REG_PC
)
8233 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8235 inst
.instruction
|= inst
.operands
[0].reg
;
8239 /* Arg is an address; this instruction cannot be executed
8240 conditionally, and the opcode must be adjusted.
8241 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8242 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8243 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8244 inst
.instruction
= 0xfa000000;
8245 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8252 bfd_boolean want_reloc
;
8254 if (inst
.operands
[0].reg
== REG_PC
)
8255 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8257 inst
.instruction
|= inst
.operands
[0].reg
;
8258 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8259 it is for ARMv4t or earlier. */
8260 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8261 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8265 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8270 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8274 /* ARM v5TEJ. Jump to Jazelle code. */
8279 if (inst
.operands
[0].reg
== REG_PC
)
8280 as_tsktsk (_("use of r15 in bxj is not really useful"));
8282 inst
.instruction
|= inst
.operands
[0].reg
;
8285 /* Co-processor data operation:
8286 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8287 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8291 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8292 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8293 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8294 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8295 inst
.instruction
|= inst
.operands
[4].reg
;
8296 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8303 encode_arm_shifter_operand (1);
8306 /* Transfer between coprocessor and ARM registers.
8307 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8312 No special properties. */
8314 struct deprecated_coproc_regs_s
8321 arm_feature_set deprecated
;
8322 arm_feature_set obsoleted
;
8323 const char *dep_msg
;
8324 const char *obs_msg
;
8327 #define DEPR_ACCESS_V8 \
8328 N_("This coprocessor register access is deprecated in ARMv8")
8330 /* Table of all deprecated coprocessor registers. */
8331 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8333 {15, 0, 7, 10, 5, /* CP15DMB. */
8334 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8335 DEPR_ACCESS_V8
, NULL
},
8336 {15, 0, 7, 10, 4, /* CP15DSB. */
8337 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8338 DEPR_ACCESS_V8
, NULL
},
8339 {15, 0, 7, 5, 4, /* CP15ISB. */
8340 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8341 DEPR_ACCESS_V8
, NULL
},
8342 {14, 6, 1, 0, 0, /* TEEHBR. */
8343 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8344 DEPR_ACCESS_V8
, NULL
},
8345 {14, 6, 0, 0, 0, /* TEECR. */
8346 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8347 DEPR_ACCESS_V8
, NULL
},
8350 #undef DEPR_ACCESS_V8
8352 static const size_t deprecated_coproc_reg_count
=
8353 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8361 Rd
= inst
.operands
[2].reg
;
8364 if (inst
.instruction
== 0xee000010
8365 || inst
.instruction
== 0xfe000010)
8367 reject_bad_reg (Rd
);
8370 constraint (Rd
== REG_SP
, BAD_SP
);
8375 if (inst
.instruction
== 0xe000010)
8376 constraint (Rd
== REG_PC
, BAD_PC
);
8379 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8381 const struct deprecated_coproc_regs_s
*r
=
8382 deprecated_coproc_regs
+ i
;
8384 if (inst
.operands
[0].reg
== r
->cp
8385 && inst
.operands
[1].imm
== r
->opc1
8386 && inst
.operands
[3].reg
== r
->crn
8387 && inst
.operands
[4].reg
== r
->crm
8388 && inst
.operands
[5].imm
== r
->opc2
)
8390 if (! ARM_CPU_IS_ANY (cpu_variant
)
8391 && warn_on_deprecated
8392 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8393 as_tsktsk ("%s", r
->dep_msg
);
8397 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8398 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8399 inst
.instruction
|= Rd
<< 12;
8400 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8401 inst
.instruction
|= inst
.operands
[4].reg
;
8402 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8405 /* Transfer between coprocessor register and pair of ARM registers.
8406 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8411 Two XScale instructions are special cases of these:
8413 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8414 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8416 Result unpredictable if Rd or Rn is R15. */
8423 Rd
= inst
.operands
[2].reg
;
8424 Rn
= inst
.operands
[3].reg
;
8428 reject_bad_reg (Rd
);
8429 reject_bad_reg (Rn
);
8433 constraint (Rd
== REG_PC
, BAD_PC
);
8434 constraint (Rn
== REG_PC
, BAD_PC
);
8437 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8438 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8439 inst
.instruction
|= Rd
<< 12;
8440 inst
.instruction
|= Rn
<< 16;
8441 inst
.instruction
|= inst
.operands
[4].reg
;
8447 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8448 if (inst
.operands
[1].present
)
8450 inst
.instruction
|= CPSI_MMOD
;
8451 inst
.instruction
|= inst
.operands
[1].imm
;
8458 inst
.instruction
|= inst
.operands
[0].imm
;
8464 unsigned Rd
, Rn
, Rm
;
8466 Rd
= inst
.operands
[0].reg
;
8467 Rn
= (inst
.operands
[1].present
8468 ? inst
.operands
[1].reg
: Rd
);
8469 Rm
= inst
.operands
[2].reg
;
8471 constraint ((Rd
== REG_PC
), BAD_PC
);
8472 constraint ((Rn
== REG_PC
), BAD_PC
);
8473 constraint ((Rm
== REG_PC
), BAD_PC
);
8475 inst
.instruction
|= Rd
<< 16;
8476 inst
.instruction
|= Rn
<< 0;
8477 inst
.instruction
|= Rm
<< 8;
8483 /* There is no IT instruction in ARM mode. We
8484 process it to do the validation as if in
8485 thumb mode, just in case the code gets
8486 assembled for thumb using the unified syntax. */
8491 set_it_insn_type (IT_INSN
);
8492 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8493 now_it
.cc
= inst
.operands
[0].imm
;
8497 /* If there is only one register in the register list,
8498 then return its register number. Otherwise return -1. */
8500 only_one_reg_in_list (int range
)
8502 int i
= ffs (range
) - 1;
8503 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8507 encode_ldmstm(int from_push_pop_mnem
)
8509 int base_reg
= inst
.operands
[0].reg
;
8510 int range
= inst
.operands
[1].imm
;
8513 inst
.instruction
|= base_reg
<< 16;
8514 inst
.instruction
|= range
;
8516 if (inst
.operands
[1].writeback
)
8517 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8519 if (inst
.operands
[0].writeback
)
8521 inst
.instruction
|= WRITE_BACK
;
8522 /* Check for unpredictable uses of writeback. */
8523 if (inst
.instruction
& LOAD_BIT
)
8525 /* Not allowed in LDM type 2. */
8526 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8527 && ((range
& (1 << REG_PC
)) == 0))
8528 as_warn (_("writeback of base register is UNPREDICTABLE"));
8529 /* Only allowed if base reg not in list for other types. */
8530 else if (range
& (1 << base_reg
))
8531 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8535 /* Not allowed for type 2. */
8536 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8537 as_warn (_("writeback of base register is UNPREDICTABLE"));
8538 /* Only allowed if base reg not in list, or first in list. */
8539 else if ((range
& (1 << base_reg
))
8540 && (range
& ((1 << base_reg
) - 1)))
8541 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8545 /* If PUSH/POP has only one register, then use the A2 encoding. */
8546 one_reg
= only_one_reg_in_list (range
);
8547 if (from_push_pop_mnem
&& one_reg
>= 0)
8549 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8551 inst
.instruction
&= A_COND_MASK
;
8552 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8553 inst
.instruction
|= one_reg
<< 12;
8560 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8563 /* ARMv5TE load-consecutive (argument parse)
8572 constraint (inst
.operands
[0].reg
% 2 != 0,
8573 _("first transfer register must be even"));
8574 constraint (inst
.operands
[1].present
8575 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8576 _("can only transfer two consecutive registers"));
8577 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8578 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8580 if (!inst
.operands
[1].present
)
8581 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8583 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8584 register and the first register written; we have to diagnose
8585 overlap between the base and the second register written here. */
8587 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8588 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8589 as_warn (_("base register written back, and overlaps "
8590 "second transfer register"));
8592 if (!(inst
.instruction
& V4_STR_BIT
))
8594 /* For an index-register load, the index register must not overlap the
8595 destination (even if not write-back). */
8596 if (inst
.operands
[2].immisreg
8597 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8598 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8599 as_warn (_("index register overlaps transfer register"));
8601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8602 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8608 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8609 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8610 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8611 || inst
.operands
[1].negative
8612 /* This can arise if the programmer has written
8614 or if they have mistakenly used a register name as the last
8617 It is very difficult to distinguish between these two cases
8618 because "rX" might actually be a label. ie the register
8619 name has been occluded by a symbol of the same name. So we
8620 just generate a general 'bad addressing mode' type error
8621 message and leave it up to the programmer to discover the
8622 true cause and fix their mistake. */
8623 || (inst
.operands
[1].reg
== REG_PC
),
8626 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8627 || inst
.reloc
.exp
.X_add_number
!= 0,
8628 _("offset must be zero in ARM encoding"));
8630 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8633 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8634 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8640 constraint (inst
.operands
[0].reg
% 2 != 0,
8641 _("even register required"));
8642 constraint (inst
.operands
[1].present
8643 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8644 _("can only load two consecutive registers"));
8645 /* If op 1 were present and equal to PC, this function wouldn't
8646 have been called in the first place. */
8647 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8649 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8650 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8653 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8654 which is not a multiple of four is UNPREDICTABLE. */
8656 check_ldr_r15_aligned (void)
8658 constraint (!(inst
.operands
[1].immisreg
)
8659 && (inst
.operands
[0].reg
== REG_PC
8660 && inst
.operands
[1].reg
== REG_PC
8661 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8662 _("ldr to register 15 must be 4-byte alligned"));
8668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8669 if (!inst
.operands
[1].isreg
)
8670 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8672 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8673 check_ldr_r15_aligned ();
8679 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8681 if (inst
.operands
[1].preind
)
8683 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8684 || inst
.reloc
.exp
.X_add_number
!= 0,
8685 _("this instruction requires a post-indexed address"));
8687 inst
.operands
[1].preind
= 0;
8688 inst
.operands
[1].postind
= 1;
8689 inst
.operands
[1].writeback
= 1;
8691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8692 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8695 /* Halfword and signed-byte load/store operations. */
8700 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8701 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8702 if (!inst
.operands
[1].isreg
)
8703 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8705 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8711 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8713 if (inst
.operands
[1].preind
)
8715 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8716 || inst
.reloc
.exp
.X_add_number
!= 0,
8717 _("this instruction requires a post-indexed address"));
8719 inst
.operands
[1].preind
= 0;
8720 inst
.operands
[1].postind
= 1;
8721 inst
.operands
[1].writeback
= 1;
8723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8724 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8727 /* Co-processor register load/store.
8728 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8732 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8733 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8734 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8740 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8741 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8742 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8743 && !(inst
.instruction
& 0x00400000))
8744 as_tsktsk (_("Rd and Rm should be different in mla"));
8746 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8747 inst
.instruction
|= inst
.operands
[1].reg
;
8748 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8749 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8755 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8756 encode_arm_shifter_operand (1);
8759 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8766 top
= (inst
.instruction
& 0x00400000) != 0;
8767 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8768 _(":lower16: not allowed this instruction"));
8769 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8770 _(":upper16: not allowed instruction"));
8771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8772 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8774 imm
= inst
.reloc
.exp
.X_add_number
;
8775 /* The value is in two pieces: 0:11, 16:19. */
8776 inst
.instruction
|= (imm
& 0x00000fff);
8777 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8781 static void do_vfp_nsyn_opcode (const char *);
8784 do_vfp_nsyn_mrs (void)
8786 if (inst
.operands
[0].isvec
)
8788 if (inst
.operands
[1].reg
!= 1)
8789 first_error (_("operand 1 must be FPSCR"));
8790 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8791 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8792 do_vfp_nsyn_opcode ("fmstat");
8794 else if (inst
.operands
[1].isvec
)
8795 do_vfp_nsyn_opcode ("fmrx");
8803 do_vfp_nsyn_msr (void)
8805 if (inst
.operands
[0].isvec
)
8806 do_vfp_nsyn_opcode ("fmxr");
8816 unsigned Rt
= inst
.operands
[0].reg
;
8818 if (thumb_mode
&& Rt
== REG_SP
)
8820 inst
.error
= BAD_SP
;
8824 /* APSR_ sets isvec. All other refs to PC are illegal. */
8825 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8827 inst
.error
= BAD_PC
;
8831 /* If we get through parsing the register name, we just insert the number
8832 generated into the instruction without further validation. */
8833 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8834 inst
.instruction
|= (Rt
<< 12);
8840 unsigned Rt
= inst
.operands
[1].reg
;
8843 reject_bad_reg (Rt
);
8844 else if (Rt
== REG_PC
)
8846 inst
.error
= BAD_PC
;
8850 /* If we get through parsing the register name, we just insert the number
8851 generated into the instruction without further validation. */
8852 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8853 inst
.instruction
|= (Rt
<< 12);
8861 if (do_vfp_nsyn_mrs () == SUCCESS
)
8864 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8865 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8867 if (inst
.operands
[1].isreg
)
8869 br
= inst
.operands
[1].reg
;
8870 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8871 as_bad (_("bad register for mrs"));
8875 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8876 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8878 _("'APSR', 'CPSR' or 'SPSR' expected"));
8879 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8882 inst
.instruction
|= br
;
8885 /* Two possible forms:
8886 "{C|S}PSR_<field>, Rm",
8887 "{C|S}PSR_f, #expression". */
8892 if (do_vfp_nsyn_msr () == SUCCESS
)
8895 inst
.instruction
|= inst
.operands
[0].imm
;
8896 if (inst
.operands
[1].isreg
)
8897 inst
.instruction
|= inst
.operands
[1].reg
;
8900 inst
.instruction
|= INST_IMMEDIATE
;
8901 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8902 inst
.reloc
.pc_rel
= 0;
8909 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8911 if (!inst
.operands
[2].present
)
8912 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8913 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8914 inst
.instruction
|= inst
.operands
[1].reg
;
8915 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8917 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8918 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8919 as_tsktsk (_("Rd and Rm should be different in mul"));
8922 /* Long Multiply Parser
8923 UMULL RdLo, RdHi, Rm, Rs
8924 SMULL RdLo, RdHi, Rm, Rs
8925 UMLAL RdLo, RdHi, Rm, Rs
8926 SMLAL RdLo, RdHi, Rm, Rs. */
8931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8932 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8933 inst
.instruction
|= inst
.operands
[2].reg
;
8934 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8936 /* rdhi and rdlo must be different. */
8937 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8938 as_tsktsk (_("rdhi and rdlo must be different"));
8940 /* rdhi, rdlo and rm must all be different before armv6. */
8941 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8942 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8943 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8944 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8950 if (inst
.operands
[0].present
8951 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8953 /* Architectural NOP hints are CPSR sets with no bits selected. */
8954 inst
.instruction
&= 0xf0000000;
8955 inst
.instruction
|= 0x0320f000;
8956 if (inst
.operands
[0].present
)
8957 inst
.instruction
|= inst
.operands
[0].imm
;
8961 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8962 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8963 Condition defaults to COND_ALWAYS.
8964 Error if Rd, Rn or Rm are R15. */
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8971 inst
.instruction
|= inst
.operands
[2].reg
;
8972 if (inst
.operands
[3].present
)
8973 encode_arm_shift (3);
8976 /* ARM V6 PKHTB (Argument Parse). */
8981 if (!inst
.operands
[3].present
)
8983 /* If the shift specifier is omitted, turn the instruction
8984 into pkhbt rd, rm, rn. */
8985 inst
.instruction
&= 0xfff00010;
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 inst
.instruction
|= inst
.operands
[1].reg
;
8988 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8994 inst
.instruction
|= inst
.operands
[2].reg
;
8995 encode_arm_shift (3);
8999 /* ARMv5TE: Preload-Cache
9000 MP Extensions: Preload for write
9004 Syntactically, like LDR with B=1, W=0, L=1. */
9009 constraint (!inst
.operands
[0].isreg
,
9010 _("'[' expected after PLD mnemonic"));
9011 constraint (inst
.operands
[0].postind
,
9012 _("post-indexed expression used in preload instruction"));
9013 constraint (inst
.operands
[0].writeback
,
9014 _("writeback used in preload instruction"));
9015 constraint (!inst
.operands
[0].preind
,
9016 _("unindexed addressing used in preload instruction"));
9017 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9020 /* ARMv7: PLI <addr_mode> */
9024 constraint (!inst
.operands
[0].isreg
,
9025 _("'[' expected after PLI mnemonic"));
9026 constraint (inst
.operands
[0].postind
,
9027 _("post-indexed expression used in preload instruction"));
9028 constraint (inst
.operands
[0].writeback
,
9029 _("writeback used in preload instruction"));
9030 constraint (!inst
.operands
[0].preind
,
9031 _("unindexed addressing used in preload instruction"));
9032 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9033 inst
.instruction
&= ~PRE_INDEX
;
9039 inst
.operands
[1] = inst
.operands
[0];
9040 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9041 inst
.operands
[0].isreg
= 1;
9042 inst
.operands
[0].writeback
= 1;
9043 inst
.operands
[0].reg
= REG_SP
;
9044 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9047 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9048 word at the specified address and the following word
9050 Unconditionally executed.
9051 Error if Rn is R15. */
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9057 if (inst
.operands
[0].writeback
)
9058 inst
.instruction
|= WRITE_BACK
;
9061 /* ARM V6 ssat (argument parse). */
9066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9067 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9068 inst
.instruction
|= inst
.operands
[2].reg
;
9070 if (inst
.operands
[3].present
)
9071 encode_arm_shift (3);
9074 /* ARM V6 usat (argument parse). */
9079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9080 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9081 inst
.instruction
|= inst
.operands
[2].reg
;
9083 if (inst
.operands
[3].present
)
9084 encode_arm_shift (3);
9087 /* ARM V6 ssat16 (argument parse). */
9092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9093 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9094 inst
.instruction
|= inst
.operands
[2].reg
;
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9102 inst
.instruction
|= inst
.operands
[2].reg
;
9105 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9106 preserving the other bits.
9108 setend <endian_specifier>, where <endian_specifier> is either
9114 if (warn_on_deprecated
9115 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9116 as_tsktsk (_("setend use is deprecated for ARMv8"));
9118 if (inst
.operands
[0].imm
)
9119 inst
.instruction
|= 0x200;
9125 unsigned int Rm
= (inst
.operands
[1].present
9126 ? inst
.operands
[1].reg
9127 : inst
.operands
[0].reg
);
9129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9130 inst
.instruction
|= Rm
;
9131 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9133 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9134 inst
.instruction
|= SHIFT_BY_REG
;
9135 /* PR 12854: Error on extraneous shifts. */
9136 constraint (inst
.operands
[2].shifted
,
9137 _("extraneous shift as part of operand to shift insn"));
9140 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9146 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9147 inst
.reloc
.pc_rel
= 0;
9153 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9154 inst
.reloc
.pc_rel
= 0;
9160 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9161 inst
.reloc
.pc_rel
= 0;
9164 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9165 SMLAxy{cond} Rd,Rm,Rs,Rn
9166 SMLAWy{cond} Rd,Rm,Rs,Rn
9167 Error if any register is R15. */
9172 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9173 inst
.instruction
|= inst
.operands
[1].reg
;
9174 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9175 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9178 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9179 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9180 Error if any register is R15.
9181 Warning if Rdlo == Rdhi. */
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9188 inst
.instruction
|= inst
.operands
[2].reg
;
9189 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9191 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9192 as_tsktsk (_("rdhi and rdlo must be different"));
9195 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9196 SMULxy{cond} Rd,Rm,Rs
9197 Error if any register is R15. */
9202 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9203 inst
.instruction
|= inst
.operands
[1].reg
;
9204 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9207 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9208 the same for both ARM and Thumb-2. */
9215 if (inst
.operands
[0].present
)
9217 reg
= inst
.operands
[0].reg
;
9218 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9223 inst
.instruction
|= reg
<< 16;
9224 inst
.instruction
|= inst
.operands
[1].imm
;
9225 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9226 inst
.instruction
|= WRITE_BACK
;
9229 /* ARM V6 strex (argument parse). */
9234 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9235 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9236 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9237 || inst
.operands
[2].negative
9238 /* See comment in do_ldrex(). */
9239 || (inst
.operands
[2].reg
== REG_PC
),
9242 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9243 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9245 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9246 || inst
.reloc
.exp
.X_add_number
!= 0,
9247 _("offset must be zero in ARM encoding"));
9249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9250 inst
.instruction
|= inst
.operands
[1].reg
;
9251 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9252 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9258 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9259 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9260 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9261 || inst
.operands
[2].negative
,
9264 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9265 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9273 constraint (inst
.operands
[1].reg
% 2 != 0,
9274 _("even register required"));
9275 constraint (inst
.operands
[2].present
9276 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9277 _("can only store two consecutive registers"));
9278 /* If op 2 were present and equal to PC, this function wouldn't
9279 have been called in the first place. */
9280 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9282 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9283 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9284 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[1].reg
;
9289 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9296 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9297 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9305 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9306 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9311 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9312 extends it to 32-bits, and adds the result to a value in another
9313 register. You can specify a rotation by 0, 8, 16, or 24 bits
9314 before extracting the 16-bit value.
9315 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9316 Condition defaults to COND_ALWAYS.
9317 Error if any register uses R15. */
9322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9323 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9324 inst
.instruction
|= inst
.operands
[2].reg
;
9325 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9330 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9331 Condition defaults to COND_ALWAYS.
9332 Error if any register uses R15. */
9337 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9338 inst
.instruction
|= inst
.operands
[1].reg
;
9339 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9342 /* VFP instructions. In a logical order: SP variant first, monad
9343 before dyad, arithmetic then move then load/store. */
9346 do_vfp_sp_monadic (void)
9348 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9349 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9353 do_vfp_sp_dyadic (void)
9355 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9356 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9357 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9361 do_vfp_sp_compare_z (void)
9363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9367 do_vfp_dp_sp_cvt (void)
9369 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9370 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9374 do_vfp_sp_dp_cvt (void)
9376 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9377 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9381 do_vfp_reg_from_sp (void)
9383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9384 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9388 do_vfp_reg2_from_sp2 (void)
9390 constraint (inst
.operands
[2].imm
!= 2,
9391 _("only two consecutive VFP SP registers allowed here"));
9392 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9393 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9394 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9398 do_vfp_sp_from_reg (void)
9400 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9401 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9405 do_vfp_sp2_from_reg2 (void)
9407 constraint (inst
.operands
[0].imm
!= 2,
9408 _("only two consecutive VFP SP registers allowed here"));
9409 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9410 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9411 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9415 do_vfp_sp_ldst (void)
9417 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9418 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9422 do_vfp_dp_ldst (void)
9424 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9425 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9430 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9432 if (inst
.operands
[0].writeback
)
9433 inst
.instruction
|= WRITE_BACK
;
9435 constraint (ldstm_type
!= VFP_LDSTMIA
,
9436 _("this addressing mode requires base-register writeback"));
9437 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9438 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9439 inst
.instruction
|= inst
.operands
[1].imm
;
9443 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9447 if (inst
.operands
[0].writeback
)
9448 inst
.instruction
|= WRITE_BACK
;
9450 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9451 _("this addressing mode requires base-register writeback"));
9453 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9454 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9456 count
= inst
.operands
[1].imm
<< 1;
9457 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9460 inst
.instruction
|= count
;
9464 do_vfp_sp_ldstmia (void)
9466 vfp_sp_ldstm (VFP_LDSTMIA
);
9470 do_vfp_sp_ldstmdb (void)
9472 vfp_sp_ldstm (VFP_LDSTMDB
);
9476 do_vfp_dp_ldstmia (void)
9478 vfp_dp_ldstm (VFP_LDSTMIA
);
9482 do_vfp_dp_ldstmdb (void)
9484 vfp_dp_ldstm (VFP_LDSTMDB
);
9488 do_vfp_xp_ldstmia (void)
9490 vfp_dp_ldstm (VFP_LDSTMIAX
);
9494 do_vfp_xp_ldstmdb (void)
9496 vfp_dp_ldstm (VFP_LDSTMDBX
);
9500 do_vfp_dp_rd_rm (void)
9502 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9503 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9507 do_vfp_dp_rn_rd (void)
9509 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9510 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9514 do_vfp_dp_rd_rn (void)
9516 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9517 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9521 do_vfp_dp_rd_rn_rm (void)
9523 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9524 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9525 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9531 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9535 do_vfp_dp_rm_rd_rn (void)
9537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9538 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9539 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9542 /* VFPv3 instructions. */
9544 do_vfp_sp_const (void)
9546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9547 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9548 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9552 do_vfp_dp_const (void)
9554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9555 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9556 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9560 vfp_conv (int srcsize
)
9562 int immbits
= srcsize
- inst
.operands
[1].imm
;
9564 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9566 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9567 i.e. immbits must be in range 0 - 16. */
9568 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9571 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9573 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9574 i.e. immbits must be in range 0 - 31. */
9575 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9579 inst
.instruction
|= (immbits
& 1) << 5;
9580 inst
.instruction
|= (immbits
>> 1);
9584 do_vfp_sp_conv_16 (void)
9586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9591 do_vfp_dp_conv_16 (void)
9593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9598 do_vfp_sp_conv_32 (void)
9600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9605 do_vfp_dp_conv_32 (void)
9607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9611 /* FPA instructions. Also in a logical order. */
9616 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9617 inst
.instruction
|= inst
.operands
[1].reg
;
9621 do_fpa_ldmstm (void)
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9624 switch (inst
.operands
[1].imm
)
9626 case 1: inst
.instruction
|= CP_T_X
; break;
9627 case 2: inst
.instruction
|= CP_T_Y
; break;
9628 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9633 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9635 /* The instruction specified "ea" or "fd", so we can only accept
9636 [Rn]{!}. The instruction does not really support stacking or
9637 unstacking, so we have to emulate these by setting appropriate
9638 bits and offsets. */
9639 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9640 || inst
.reloc
.exp
.X_add_number
!= 0,
9641 _("this instruction does not support indexing"));
9643 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9644 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9646 if (!(inst
.instruction
& INDEX_UP
))
9647 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9649 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9651 inst
.operands
[2].preind
= 0;
9652 inst
.operands
[2].postind
= 1;
9656 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9659 /* iWMMXt instructions: strictly in alphabetical order. */
9662 do_iwmmxt_tandorc (void)
9664 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9668 do_iwmmxt_textrc (void)
9670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9671 inst
.instruction
|= inst
.operands
[1].imm
;
9675 do_iwmmxt_textrm (void)
9677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9678 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9679 inst
.instruction
|= inst
.operands
[2].imm
;
9683 do_iwmmxt_tinsr (void)
9685 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9686 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9687 inst
.instruction
|= inst
.operands
[2].imm
;
9691 do_iwmmxt_tmia (void)
9693 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9694 inst
.instruction
|= inst
.operands
[1].reg
;
9695 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9699 do_iwmmxt_waligni (void)
9701 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9702 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9703 inst
.instruction
|= inst
.operands
[2].reg
;
9704 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9708 do_iwmmxt_wmerge (void)
9710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9711 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9712 inst
.instruction
|= inst
.operands
[2].reg
;
9713 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9717 do_iwmmxt_wmov (void)
9719 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9720 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9721 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9722 inst
.instruction
|= inst
.operands
[1].reg
;
9726 do_iwmmxt_wldstbh (void)
9729 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9731 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9733 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9734 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9738 do_iwmmxt_wldstw (void)
9740 /* RIWR_RIWC clears .isreg for a control register. */
9741 if (!inst
.operands
[0].isreg
)
9743 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9744 inst
.instruction
|= 0xf0000000;
9747 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9748 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9752 do_iwmmxt_wldstd (void)
9754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9755 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9756 && inst
.operands
[1].immisreg
)
9758 inst
.instruction
&= ~0x1a000ff;
9759 inst
.instruction
|= (0xf << 28);
9760 if (inst
.operands
[1].preind
)
9761 inst
.instruction
|= PRE_INDEX
;
9762 if (!inst
.operands
[1].negative
)
9763 inst
.instruction
|= INDEX_UP
;
9764 if (inst
.operands
[1].writeback
)
9765 inst
.instruction
|= WRITE_BACK
;
9766 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9767 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9768 inst
.instruction
|= inst
.operands
[1].imm
;
9771 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9775 do_iwmmxt_wshufh (void)
9777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9778 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9779 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9780 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9784 do_iwmmxt_wzero (void)
9786 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9787 inst
.instruction
|= inst
.operands
[0].reg
;
9788 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9789 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9793 do_iwmmxt_wrwrwr_or_imm5 (void)
9795 if (inst
.operands
[2].isreg
)
9798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9799 _("immediate operand requires iWMMXt2"));
9801 if (inst
.operands
[2].imm
== 0)
9803 switch ((inst
.instruction
>> 20) & 0xf)
9809 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9810 inst
.operands
[2].imm
= 16;
9811 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9817 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9818 inst
.operands
[2].imm
= 32;
9819 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9826 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9828 wrn
= (inst
.instruction
>> 16) & 0xf;
9829 inst
.instruction
&= 0xff0fff0f;
9830 inst
.instruction
|= wrn
;
9831 /* Bail out here; the instruction is now assembled. */
9836 /* Map 32 -> 0, etc. */
9837 inst
.operands
[2].imm
&= 0x1f;
9838 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9842 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9843 operations first, then control, shift, and load/store. */
9845 /* Insns like "foo X,Y,Z". */
9848 do_mav_triple (void)
9850 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9851 inst
.instruction
|= inst
.operands
[1].reg
;
9852 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9855 /* Insns like "foo W,X,Y,Z".
9856 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9862 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9863 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9864 inst
.instruction
|= inst
.operands
[3].reg
;
9867 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9871 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9874 /* Maverick shift immediate instructions.
9875 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9876 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9881 int imm
= inst
.operands
[2].imm
;
9883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9884 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9886 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9887 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9888 Bit 4 should be 0. */
9889 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9891 inst
.instruction
|= imm
;
9894 /* XScale instructions. Also sorted arithmetic before move. */
9896 /* Xscale multiply-accumulate (argument parse)
9899 MIAxycc acc0,Rm,Rs. */
9904 inst
.instruction
|= inst
.operands
[1].reg
;
9905 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9908 /* Xscale move-accumulator-register (argument parse)
9910 MARcc acc0,RdLo,RdHi. */
9915 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9916 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9919 /* Xscale move-register-accumulator (argument parse)
9921 MRAcc RdLo,RdHi,acc0. */
9926 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9931 /* Encoding functions relevant only to Thumb. */
9933 /* inst.operands[i] is a shifted-register operand; encode
9934 it into inst.instruction in the format used by Thumb32. */
9937 encode_thumb32_shifted_operand (int i
)
9939 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9940 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9942 constraint (inst
.operands
[i
].immisreg
,
9943 _("shift by register not allowed in thumb mode"));
9944 inst
.instruction
|= inst
.operands
[i
].reg
;
9945 if (shift
== SHIFT_RRX
)
9946 inst
.instruction
|= SHIFT_ROR
<< 4;
9949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9950 _("expression too complex"));
9952 constraint (value
> 32
9953 || (value
== 32 && (shift
== SHIFT_LSL
9954 || shift
== SHIFT_ROR
)),
9955 _("shift expression is too large"));
9959 else if (value
== 32)
9962 inst
.instruction
|= shift
<< 4;
9963 inst
.instruction
|= (value
& 0x1c) << 10;
9964 inst
.instruction
|= (value
& 0x03) << 6;
9969 /* inst.operands[i] was set up by parse_address. Encode it into a
9970 Thumb32 format load or store instruction. Reject forms that cannot
9971 be used with such instructions. If is_t is true, reject forms that
9972 cannot be used with a T instruction; if is_d is true, reject forms
9973 that cannot be used with a D instruction. If it is a store insn,
9977 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9979 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9981 constraint (!inst
.operands
[i
].isreg
,
9982 _("Instruction does not support =N addresses"));
9984 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9985 if (inst
.operands
[i
].immisreg
)
9987 constraint (is_pc
, BAD_PC_ADDRESSING
);
9988 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9989 constraint (inst
.operands
[i
].negative
,
9990 _("Thumb does not support negative register indexing"));
9991 constraint (inst
.operands
[i
].postind
,
9992 _("Thumb does not support register post-indexing"));
9993 constraint (inst
.operands
[i
].writeback
,
9994 _("Thumb does not support register indexing with writeback"));
9995 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9996 _("Thumb supports only LSL in shifted register indexing"));
9998 inst
.instruction
|= inst
.operands
[i
].imm
;
9999 if (inst
.operands
[i
].shifted
)
10001 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10002 _("expression too complex"));
10003 constraint (inst
.reloc
.exp
.X_add_number
< 0
10004 || inst
.reloc
.exp
.X_add_number
> 3,
10005 _("shift out of range"));
10006 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10008 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10010 else if (inst
.operands
[i
].preind
)
10012 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10013 constraint (is_t
&& inst
.operands
[i
].writeback
,
10014 _("cannot use writeback with this instruction"));
10015 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10016 BAD_PC_ADDRESSING
);
10020 inst
.instruction
|= 0x01000000;
10021 if (inst
.operands
[i
].writeback
)
10022 inst
.instruction
|= 0x00200000;
10026 inst
.instruction
|= 0x00000c00;
10027 if (inst
.operands
[i
].writeback
)
10028 inst
.instruction
|= 0x00000100;
10030 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10032 else if (inst
.operands
[i
].postind
)
10034 gas_assert (inst
.operands
[i
].writeback
);
10035 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10036 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10039 inst
.instruction
|= 0x00200000;
10041 inst
.instruction
|= 0x00000900;
10042 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10044 else /* unindexed - only for coprocessor */
10045 inst
.error
= _("instruction does not accept unindexed addressing");
10048 /* Table of Thumb instructions which exist in both 16- and 32-bit
10049 encodings (the latter only in post-V6T2 cores). The index is the
10050 value used in the insns table below. When there is more than one
10051 possible 16-bit encoding for the instruction, this table always
10053 Also contains several pseudo-instructions used during relaxation. */
10054 #define T16_32_TAB \
10055 X(_adc, 4140, eb400000), \
10056 X(_adcs, 4140, eb500000), \
10057 X(_add, 1c00, eb000000), \
10058 X(_adds, 1c00, eb100000), \
10059 X(_addi, 0000, f1000000), \
10060 X(_addis, 0000, f1100000), \
10061 X(_add_pc,000f, f20f0000), \
10062 X(_add_sp,000d, f10d0000), \
10063 X(_adr, 000f, f20f0000), \
10064 X(_and, 4000, ea000000), \
10065 X(_ands, 4000, ea100000), \
10066 X(_asr, 1000, fa40f000), \
10067 X(_asrs, 1000, fa50f000), \
10068 X(_b, e000, f000b000), \
10069 X(_bcond, d000, f0008000), \
10070 X(_bic, 4380, ea200000), \
10071 X(_bics, 4380, ea300000), \
10072 X(_cmn, 42c0, eb100f00), \
10073 X(_cmp, 2800, ebb00f00), \
10074 X(_cpsie, b660, f3af8400), \
10075 X(_cpsid, b670, f3af8600), \
10076 X(_cpy, 4600, ea4f0000), \
10077 X(_dec_sp,80dd, f1ad0d00), \
10078 X(_eor, 4040, ea800000), \
10079 X(_eors, 4040, ea900000), \
10080 X(_inc_sp,00dd, f10d0d00), \
10081 X(_ldmia, c800, e8900000), \
10082 X(_ldr, 6800, f8500000), \
10083 X(_ldrb, 7800, f8100000), \
10084 X(_ldrh, 8800, f8300000), \
10085 X(_ldrsb, 5600, f9100000), \
10086 X(_ldrsh, 5e00, f9300000), \
10087 X(_ldr_pc,4800, f85f0000), \
10088 X(_ldr_pc2,4800, f85f0000), \
10089 X(_ldr_sp,9800, f85d0000), \
10090 X(_lsl, 0000, fa00f000), \
10091 X(_lsls, 0000, fa10f000), \
10092 X(_lsr, 0800, fa20f000), \
10093 X(_lsrs, 0800, fa30f000), \
10094 X(_mov, 2000, ea4f0000), \
10095 X(_movs, 2000, ea5f0000), \
10096 X(_mul, 4340, fb00f000), \
10097 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10098 X(_mvn, 43c0, ea6f0000), \
10099 X(_mvns, 43c0, ea7f0000), \
10100 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10101 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10102 X(_orr, 4300, ea400000), \
10103 X(_orrs, 4300, ea500000), \
10104 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10105 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10106 X(_rev, ba00, fa90f080), \
10107 X(_rev16, ba40, fa90f090), \
10108 X(_revsh, bac0, fa90f0b0), \
10109 X(_ror, 41c0, fa60f000), \
10110 X(_rors, 41c0, fa70f000), \
10111 X(_sbc, 4180, eb600000), \
10112 X(_sbcs, 4180, eb700000), \
10113 X(_stmia, c000, e8800000), \
10114 X(_str, 6000, f8400000), \
10115 X(_strb, 7000, f8000000), \
10116 X(_strh, 8000, f8200000), \
10117 X(_str_sp,9000, f84d0000), \
10118 X(_sub, 1e00, eba00000), \
10119 X(_subs, 1e00, ebb00000), \
10120 X(_subi, 8000, f1a00000), \
10121 X(_subis, 8000, f1b00000), \
10122 X(_sxtb, b240, fa4ff080), \
10123 X(_sxth, b200, fa0ff080), \
10124 X(_tst, 4200, ea100f00), \
10125 X(_uxtb, b2c0, fa5ff080), \
10126 X(_uxth, b280, fa1ff080), \
10127 X(_nop, bf00, f3af8000), \
10128 X(_yield, bf10, f3af8001), \
10129 X(_wfe, bf20, f3af8002), \
10130 X(_wfi, bf30, f3af8003), \
10131 X(_sev, bf40, f3af8004), \
10132 X(_sevl, bf50, f3af8005), \
10133 X(_udf, de00, f7f0a000)
10135 /* To catch errors in encoding functions, the codes are all offset by
10136 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10137 as 16-bit instructions. */
10138 #define X(a,b,c) T_MNEM##a
10139 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10142 #define X(a,b,c) 0x##b
10143 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10144 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10147 #define X(a,b,c) 0x##c
10148 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10149 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10150 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10154 /* Thumb instruction encoders, in alphabetical order. */
10156 /* ADDW or SUBW. */
10159 do_t_add_sub_w (void)
10163 Rd
= inst
.operands
[0].reg
;
10164 Rn
= inst
.operands
[1].reg
;
10166 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10167 is the SP-{plus,minus}-immediate form of the instruction. */
10169 constraint (Rd
== REG_PC
, BAD_PC
);
10171 reject_bad_reg (Rd
);
10173 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10174 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10177 /* Parse an add or subtract instruction. We get here with inst.instruction
10178 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10181 do_t_add_sub (void)
10185 Rd
= inst
.operands
[0].reg
;
10186 Rs
= (inst
.operands
[1].present
10187 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10188 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10191 set_it_insn_type_last ();
10193 if (unified_syntax
)
10196 bfd_boolean narrow
;
10199 flags
= (inst
.instruction
== T_MNEM_adds
10200 || inst
.instruction
== T_MNEM_subs
);
10202 narrow
= !in_it_block ();
10204 narrow
= in_it_block ();
10205 if (!inst
.operands
[2].isreg
)
10209 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10211 add
= (inst
.instruction
== T_MNEM_add
10212 || inst
.instruction
== T_MNEM_adds
);
10214 if (inst
.size_req
!= 4)
10216 /* Attempt to use a narrow opcode, with relaxation if
10218 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10219 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10220 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10221 opcode
= T_MNEM_add_sp
;
10222 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10223 opcode
= T_MNEM_add_pc
;
10224 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10227 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10229 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10233 inst
.instruction
= THUMB_OP16(opcode
);
10234 inst
.instruction
|= (Rd
<< 4) | Rs
;
10235 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10236 if (inst
.size_req
!= 2)
10237 inst
.relax
= opcode
;
10240 constraint (inst
.size_req
== 2, BAD_HIREG
);
10242 if (inst
.size_req
== 4
10243 || (inst
.size_req
!= 2 && !opcode
))
10247 constraint (add
, BAD_PC
);
10248 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10249 _("only SUBS PC, LR, #const allowed"));
10250 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10251 _("expression too complex"));
10252 constraint (inst
.reloc
.exp
.X_add_number
< 0
10253 || inst
.reloc
.exp
.X_add_number
> 0xff,
10254 _("immediate value out of range"));
10255 inst
.instruction
= T2_SUBS_PC_LR
10256 | inst
.reloc
.exp
.X_add_number
;
10257 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10260 else if (Rs
== REG_PC
)
10262 /* Always use addw/subw. */
10263 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10264 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10268 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10269 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10272 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10274 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10276 inst
.instruction
|= Rd
<< 8;
10277 inst
.instruction
|= Rs
<< 16;
10282 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10283 unsigned int shift
= inst
.operands
[2].shift_kind
;
10285 Rn
= inst
.operands
[2].reg
;
10286 /* See if we can do this with a 16-bit instruction. */
10287 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10289 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10294 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10295 || inst
.instruction
== T_MNEM_add
)
10297 : T_OPCODE_SUB_R3
);
10298 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10302 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10304 /* Thumb-1 cores (except v6-M) require at least one high
10305 register in a narrow non flag setting add. */
10306 if (Rd
> 7 || Rn
> 7
10307 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10308 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10315 inst
.instruction
= T_OPCODE_ADD_HI
;
10316 inst
.instruction
|= (Rd
& 8) << 4;
10317 inst
.instruction
|= (Rd
& 7);
10318 inst
.instruction
|= Rn
<< 3;
10324 constraint (Rd
== REG_PC
, BAD_PC
);
10325 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10326 constraint (Rs
== REG_PC
, BAD_PC
);
10327 reject_bad_reg (Rn
);
10329 /* If we get here, it can't be done in 16 bits. */
10330 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10331 _("shift must be constant"));
10332 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10333 inst
.instruction
|= Rd
<< 8;
10334 inst
.instruction
|= Rs
<< 16;
10335 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10336 _("shift value over 3 not allowed in thumb mode"));
10337 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10338 _("only LSL shift allowed in thumb mode"));
10339 encode_thumb32_shifted_operand (2);
10344 constraint (inst
.instruction
== T_MNEM_adds
10345 || inst
.instruction
== T_MNEM_subs
,
10348 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10350 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10351 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10354 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10355 ? 0x0000 : 0x8000);
10356 inst
.instruction
|= (Rd
<< 4) | Rs
;
10357 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10361 Rn
= inst
.operands
[2].reg
;
10362 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10364 /* We now have Rd, Rs, and Rn set to registers. */
10365 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10367 /* Can't do this for SUB. */
10368 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10369 inst
.instruction
= T_OPCODE_ADD_HI
;
10370 inst
.instruction
|= (Rd
& 8) << 4;
10371 inst
.instruction
|= (Rd
& 7);
10373 inst
.instruction
|= Rn
<< 3;
10375 inst
.instruction
|= Rs
<< 3;
10377 constraint (1, _("dest must overlap one source register"));
10381 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10382 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10383 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10393 Rd
= inst
.operands
[0].reg
;
10394 reject_bad_reg (Rd
);
10396 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10398 /* Defer to section relaxation. */
10399 inst
.relax
= inst
.instruction
;
10400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10401 inst
.instruction
|= Rd
<< 4;
10403 else if (unified_syntax
&& inst
.size_req
!= 2)
10405 /* Generate a 32-bit opcode. */
10406 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10407 inst
.instruction
|= Rd
<< 8;
10408 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10409 inst
.reloc
.pc_rel
= 1;
10413 /* Generate a 16-bit opcode. */
10414 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10415 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10416 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10417 inst
.reloc
.pc_rel
= 1;
10419 inst
.instruction
|= Rd
<< 4;
10423 /* Arithmetic instructions for which there is just one 16-bit
10424 instruction encoding, and it allows only two low registers.
10425 For maximal compatibility with ARM syntax, we allow three register
10426 operands even when Thumb-32 instructions are not available, as long
10427 as the first two are identical. For instance, both "sbc r0,r1" and
10428 "sbc r0,r0,r1" are allowed. */
10434 Rd
= inst
.operands
[0].reg
;
10435 Rs
= (inst
.operands
[1].present
10436 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10437 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10438 Rn
= inst
.operands
[2].reg
;
10440 reject_bad_reg (Rd
);
10441 reject_bad_reg (Rs
);
10442 if (inst
.operands
[2].isreg
)
10443 reject_bad_reg (Rn
);
10445 if (unified_syntax
)
10447 if (!inst
.operands
[2].isreg
)
10449 /* For an immediate, we always generate a 32-bit opcode;
10450 section relaxation will shrink it later if possible. */
10451 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10452 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10453 inst
.instruction
|= Rd
<< 8;
10454 inst
.instruction
|= Rs
<< 16;
10455 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10459 bfd_boolean narrow
;
10461 /* See if we can do this with a 16-bit instruction. */
10462 if (THUMB_SETS_FLAGS (inst
.instruction
))
10463 narrow
= !in_it_block ();
10465 narrow
= in_it_block ();
10467 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10469 if (inst
.operands
[2].shifted
)
10471 if (inst
.size_req
== 4)
10477 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10478 inst
.instruction
|= Rd
;
10479 inst
.instruction
|= Rn
<< 3;
10483 /* If we get here, it can't be done in 16 bits. */
10484 constraint (inst
.operands
[2].shifted
10485 && inst
.operands
[2].immisreg
,
10486 _("shift must be constant"));
10487 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10488 inst
.instruction
|= Rd
<< 8;
10489 inst
.instruction
|= Rs
<< 16;
10490 encode_thumb32_shifted_operand (2);
10495 /* On its face this is a lie - the instruction does set the
10496 flags. However, the only supported mnemonic in this mode
10497 says it doesn't. */
10498 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10500 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10501 _("unshifted register required"));
10502 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10503 constraint (Rd
!= Rs
,
10504 _("dest and source1 must be the same register"));
10506 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10507 inst
.instruction
|= Rd
;
10508 inst
.instruction
|= Rn
<< 3;
10512 /* Similarly, but for instructions where the arithmetic operation is
10513 commutative, so we can allow either of them to be different from
10514 the destination operand in a 16-bit instruction. For instance, all
10515 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10522 Rd
= inst
.operands
[0].reg
;
10523 Rs
= (inst
.operands
[1].present
10524 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10525 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10526 Rn
= inst
.operands
[2].reg
;
10528 reject_bad_reg (Rd
);
10529 reject_bad_reg (Rs
);
10530 if (inst
.operands
[2].isreg
)
10531 reject_bad_reg (Rn
);
10533 if (unified_syntax
)
10535 if (!inst
.operands
[2].isreg
)
10537 /* For an immediate, we always generate a 32-bit opcode;
10538 section relaxation will shrink it later if possible. */
10539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10540 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10541 inst
.instruction
|= Rd
<< 8;
10542 inst
.instruction
|= Rs
<< 16;
10543 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10547 bfd_boolean narrow
;
10549 /* See if we can do this with a 16-bit instruction. */
10550 if (THUMB_SETS_FLAGS (inst
.instruction
))
10551 narrow
= !in_it_block ();
10553 narrow
= in_it_block ();
10555 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10557 if (inst
.operands
[2].shifted
)
10559 if (inst
.size_req
== 4)
10566 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10567 inst
.instruction
|= Rd
;
10568 inst
.instruction
|= Rn
<< 3;
10573 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10574 inst
.instruction
|= Rd
;
10575 inst
.instruction
|= Rs
<< 3;
10580 /* If we get here, it can't be done in 16 bits. */
10581 constraint (inst
.operands
[2].shifted
10582 && inst
.operands
[2].immisreg
,
10583 _("shift must be constant"));
10584 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10585 inst
.instruction
|= Rd
<< 8;
10586 inst
.instruction
|= Rs
<< 16;
10587 encode_thumb32_shifted_operand (2);
10592 /* On its face this is a lie - the instruction does set the
10593 flags. However, the only supported mnemonic in this mode
10594 says it doesn't. */
10595 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10597 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10598 _("unshifted register required"));
10599 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10601 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10602 inst
.instruction
|= Rd
;
10605 inst
.instruction
|= Rn
<< 3;
10607 inst
.instruction
|= Rs
<< 3;
10609 constraint (1, _("dest must overlap one source register"));
10617 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10618 constraint (msb
> 32, _("bit-field extends past end of register"));
10619 /* The instruction encoding stores the LSB and MSB,
10620 not the LSB and width. */
10621 Rd
= inst
.operands
[0].reg
;
10622 reject_bad_reg (Rd
);
10623 inst
.instruction
|= Rd
<< 8;
10624 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10625 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10626 inst
.instruction
|= msb
- 1;
10635 Rd
= inst
.operands
[0].reg
;
10636 reject_bad_reg (Rd
);
10638 /* #0 in second position is alternative syntax for bfc, which is
10639 the same instruction but with REG_PC in the Rm field. */
10640 if (!inst
.operands
[1].isreg
)
10644 Rn
= inst
.operands
[1].reg
;
10645 reject_bad_reg (Rn
);
10648 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10649 constraint (msb
> 32, _("bit-field extends past end of register"));
10650 /* The instruction encoding stores the LSB and MSB,
10651 not the LSB and width. */
10652 inst
.instruction
|= Rd
<< 8;
10653 inst
.instruction
|= Rn
<< 16;
10654 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10655 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10656 inst
.instruction
|= msb
- 1;
10664 Rd
= inst
.operands
[0].reg
;
10665 Rn
= inst
.operands
[1].reg
;
10667 reject_bad_reg (Rd
);
10668 reject_bad_reg (Rn
);
10670 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10671 _("bit-field extends past end of register"));
10672 inst
.instruction
|= Rd
<< 8;
10673 inst
.instruction
|= Rn
<< 16;
10674 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10675 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10676 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10679 /* ARM V5 Thumb BLX (argument parse)
10680 BLX <target_addr> which is BLX(1)
10681 BLX <Rm> which is BLX(2)
10682 Unfortunately, there are two different opcodes for this mnemonic.
10683 So, the insns[].value is not used, and the code here zaps values
10684 into inst.instruction.
10686 ??? How to take advantage of the additional two bits of displacement
10687 available in Thumb32 mode? Need new relocation? */
10692 set_it_insn_type_last ();
10694 if (inst
.operands
[0].isreg
)
10696 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10697 /* We have a register, so this is BLX(2). */
10698 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10702 /* No register. This must be BLX(1). */
10703 inst
.instruction
= 0xf000e800;
10704 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10716 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10718 if (in_it_block ())
10720 /* Conditional branches inside IT blocks are encoded as unconditional
10722 cond
= COND_ALWAYS
;
10727 if (cond
!= COND_ALWAYS
)
10728 opcode
= T_MNEM_bcond
;
10730 opcode
= inst
.instruction
;
10733 && (inst
.size_req
== 4
10734 || (inst
.size_req
!= 2
10735 && (inst
.operands
[0].hasreloc
10736 || inst
.reloc
.exp
.X_op
== O_constant
))))
10738 inst
.instruction
= THUMB_OP32(opcode
);
10739 if (cond
== COND_ALWAYS
)
10740 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10743 gas_assert (cond
!= 0xF);
10744 inst
.instruction
|= cond
<< 22;
10745 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10750 inst
.instruction
= THUMB_OP16(opcode
);
10751 if (cond
== COND_ALWAYS
)
10752 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10755 inst
.instruction
|= cond
<< 8;
10756 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10758 /* Allow section relaxation. */
10759 if (unified_syntax
&& inst
.size_req
!= 2)
10760 inst
.relax
= opcode
;
10762 inst
.reloc
.type
= reloc
;
10763 inst
.reloc
.pc_rel
= 1;
10766 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10767 between the two is the maximum immediate allowed - which is passed in
10770 do_t_bkpt_hlt1 (int range
)
10772 constraint (inst
.cond
!= COND_ALWAYS
,
10773 _("instruction is always unconditional"));
10774 if (inst
.operands
[0].present
)
10776 constraint (inst
.operands
[0].imm
> range
,
10777 _("immediate value out of range"));
10778 inst
.instruction
|= inst
.operands
[0].imm
;
10781 set_it_insn_type (NEUTRAL_IT_INSN
);
10787 do_t_bkpt_hlt1 (63);
10793 do_t_bkpt_hlt1 (255);
10797 do_t_branch23 (void)
10799 set_it_insn_type_last ();
10800 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10802 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10803 this file. We used to simply ignore the PLT reloc type here --
10804 the branch encoding is now needed to deal with TLSCALL relocs.
10805 So if we see a PLT reloc now, put it back to how it used to be to
10806 keep the preexisting behaviour. */
10807 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10808 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10810 #if defined(OBJ_COFF)
10811 /* If the destination of the branch is a defined symbol which does not have
10812 the THUMB_FUNC attribute, then we must be calling a function which has
10813 the (interfacearm) attribute. We look for the Thumb entry point to that
10814 function and change the branch to refer to that function instead. */
10815 if ( inst
.reloc
.exp
.X_op
== O_symbol
10816 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10817 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10818 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10819 inst
.reloc
.exp
.X_add_symbol
=
10820 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10827 set_it_insn_type_last ();
10828 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10829 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10830 should cause the alignment to be checked once it is known. This is
10831 because BX PC only works if the instruction is word aligned. */
10839 set_it_insn_type_last ();
10840 Rm
= inst
.operands
[0].reg
;
10841 reject_bad_reg (Rm
);
10842 inst
.instruction
|= Rm
<< 16;
10851 Rd
= inst
.operands
[0].reg
;
10852 Rm
= inst
.operands
[1].reg
;
10854 reject_bad_reg (Rd
);
10855 reject_bad_reg (Rm
);
10857 inst
.instruction
|= Rd
<< 8;
10858 inst
.instruction
|= Rm
<< 16;
10859 inst
.instruction
|= Rm
;
10865 set_it_insn_type (OUTSIDE_IT_INSN
);
10866 inst
.instruction
|= inst
.operands
[0].imm
;
10872 set_it_insn_type (OUTSIDE_IT_INSN
);
10874 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10875 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10877 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10878 inst
.instruction
= 0xf3af8000;
10879 inst
.instruction
|= imod
<< 9;
10880 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10881 if (inst
.operands
[1].present
)
10882 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10886 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10887 && (inst
.operands
[0].imm
& 4),
10888 _("selected processor does not support 'A' form "
10889 "of this instruction"));
10890 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10891 _("Thumb does not support the 2-argument "
10892 "form of this instruction"));
10893 inst
.instruction
|= inst
.operands
[0].imm
;
10897 /* THUMB CPY instruction (argument parse). */
10902 if (inst
.size_req
== 4)
10904 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10905 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10906 inst
.instruction
|= inst
.operands
[1].reg
;
10910 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10911 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10912 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10919 set_it_insn_type (OUTSIDE_IT_INSN
);
10920 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10921 inst
.instruction
|= inst
.operands
[0].reg
;
10922 inst
.reloc
.pc_rel
= 1;
10923 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10929 inst
.instruction
|= inst
.operands
[0].imm
;
10935 unsigned Rd
, Rn
, Rm
;
10937 Rd
= inst
.operands
[0].reg
;
10938 Rn
= (inst
.operands
[1].present
10939 ? inst
.operands
[1].reg
: Rd
);
10940 Rm
= inst
.operands
[2].reg
;
10942 reject_bad_reg (Rd
);
10943 reject_bad_reg (Rn
);
10944 reject_bad_reg (Rm
);
10946 inst
.instruction
|= Rd
<< 8;
10947 inst
.instruction
|= Rn
<< 16;
10948 inst
.instruction
|= Rm
;
10954 if (unified_syntax
&& inst
.size_req
== 4)
10955 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10957 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10963 unsigned int cond
= inst
.operands
[0].imm
;
10965 set_it_insn_type (IT_INSN
);
10966 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10968 now_it
.warn_deprecated
= FALSE
;
10970 /* If the condition is a negative condition, invert the mask. */
10971 if ((cond
& 0x1) == 0x0)
10973 unsigned int mask
= inst
.instruction
& 0x000f;
10975 if ((mask
& 0x7) == 0)
10977 /* No conversion needed. */
10978 now_it
.block_length
= 1;
10980 else if ((mask
& 0x3) == 0)
10983 now_it
.block_length
= 2;
10985 else if ((mask
& 0x1) == 0)
10988 now_it
.block_length
= 3;
10993 now_it
.block_length
= 4;
10996 inst
.instruction
&= 0xfff0;
10997 inst
.instruction
|= mask
;
11000 inst
.instruction
|= cond
<< 4;
11003 /* Helper function used for both push/pop and ldm/stm. */
11005 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11009 load
= (inst
.instruction
& (1 << 20)) != 0;
11011 if (mask
& (1 << 13))
11012 inst
.error
= _("SP not allowed in register list");
11014 if ((mask
& (1 << base
)) != 0
11016 inst
.error
= _("having the base register in the register list when "
11017 "using write back is UNPREDICTABLE");
11021 if (mask
& (1 << 15))
11023 if (mask
& (1 << 14))
11024 inst
.error
= _("LR and PC should not both be in register list");
11026 set_it_insn_type_last ();
11031 if (mask
& (1 << 15))
11032 inst
.error
= _("PC not allowed in register list");
11035 if ((mask
& (mask
- 1)) == 0)
11037 /* Single register transfers implemented as str/ldr. */
11040 if (inst
.instruction
& (1 << 23))
11041 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11043 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11047 if (inst
.instruction
& (1 << 23))
11048 inst
.instruction
= 0x00800000; /* ia -> [base] */
11050 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11053 inst
.instruction
|= 0xf8400000;
11055 inst
.instruction
|= 0x00100000;
11057 mask
= ffs (mask
) - 1;
11060 else if (writeback
)
11061 inst
.instruction
|= WRITE_BACK
;
11063 inst
.instruction
|= mask
;
11064 inst
.instruction
|= base
<< 16;
11070 /* This really doesn't seem worth it. */
11071 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11072 _("expression too complex"));
11073 constraint (inst
.operands
[1].writeback
,
11074 _("Thumb load/store multiple does not support {reglist}^"));
11076 if (unified_syntax
)
11078 bfd_boolean narrow
;
11082 /* See if we can use a 16-bit instruction. */
11083 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11084 && inst
.size_req
!= 4
11085 && !(inst
.operands
[1].imm
& ~0xff))
11087 mask
= 1 << inst
.operands
[0].reg
;
11089 if (inst
.operands
[0].reg
<= 7)
11091 if (inst
.instruction
== T_MNEM_stmia
11092 ? inst
.operands
[0].writeback
11093 : (inst
.operands
[0].writeback
11094 == !(inst
.operands
[1].imm
& mask
)))
11096 if (inst
.instruction
== T_MNEM_stmia
11097 && (inst
.operands
[1].imm
& mask
)
11098 && (inst
.operands
[1].imm
& (mask
- 1)))
11099 as_warn (_("value stored for r%d is UNKNOWN"),
11100 inst
.operands
[0].reg
);
11102 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11103 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11104 inst
.instruction
|= inst
.operands
[1].imm
;
11107 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11109 /* This means 1 register in reg list one of 3 situations:
11110 1. Instruction is stmia, but without writeback.
11111 2. lmdia without writeback, but with Rn not in
11113 3. ldmia with writeback, but with Rn in reglist.
11114 Case 3 is UNPREDICTABLE behaviour, so we handle
11115 case 1 and 2 which can be converted into a 16-bit
11116 str or ldr. The SP cases are handled below. */
11117 unsigned long opcode
;
11118 /* First, record an error for Case 3. */
11119 if (inst
.operands
[1].imm
& mask
11120 && inst
.operands
[0].writeback
)
11122 _("having the base register in the register list when "
11123 "using write back is UNPREDICTABLE");
11125 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11127 inst
.instruction
= THUMB_OP16 (opcode
);
11128 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11129 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11133 else if (inst
.operands
[0] .reg
== REG_SP
)
11135 if (inst
.operands
[0].writeback
)
11138 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11139 ? T_MNEM_push
: T_MNEM_pop
);
11140 inst
.instruction
|= inst
.operands
[1].imm
;
11143 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11146 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11147 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11148 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11156 if (inst
.instruction
< 0xffff)
11157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11159 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11160 inst
.operands
[0].writeback
);
11165 constraint (inst
.operands
[0].reg
> 7
11166 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11167 constraint (inst
.instruction
!= T_MNEM_ldmia
11168 && inst
.instruction
!= T_MNEM_stmia
,
11169 _("Thumb-2 instruction only valid in unified syntax"));
11170 if (inst
.instruction
== T_MNEM_stmia
)
11172 if (!inst
.operands
[0].writeback
)
11173 as_warn (_("this instruction will write back the base register"));
11174 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11175 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11176 as_warn (_("value stored for r%d is UNKNOWN"),
11177 inst
.operands
[0].reg
);
11181 if (!inst
.operands
[0].writeback
11182 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11183 as_warn (_("this instruction will write back the base register"));
11184 else if (inst
.operands
[0].writeback
11185 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11186 as_warn (_("this instruction will not write back the base register"));
11189 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11190 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11191 inst
.instruction
|= inst
.operands
[1].imm
;
11198 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11199 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11200 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11201 || inst
.operands
[1].negative
,
11204 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11208 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11214 if (!inst
.operands
[1].present
)
11216 constraint (inst
.operands
[0].reg
== REG_LR
,
11217 _("r14 not allowed as first register "
11218 "when second register is omitted"));
11219 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11221 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11225 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11226 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11232 unsigned long opcode
;
11235 if (inst
.operands
[0].isreg
11236 && !inst
.operands
[0].preind
11237 && inst
.operands
[0].reg
== REG_PC
)
11238 set_it_insn_type_last ();
11240 opcode
= inst
.instruction
;
11241 if (unified_syntax
)
11243 if (!inst
.operands
[1].isreg
)
11245 if (opcode
<= 0xffff)
11246 inst
.instruction
= THUMB_OP32 (opcode
);
11247 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11250 if (inst
.operands
[1].isreg
11251 && !inst
.operands
[1].writeback
11252 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11253 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11254 && opcode
<= 0xffff
11255 && inst
.size_req
!= 4)
11257 /* Insn may have a 16-bit form. */
11258 Rn
= inst
.operands
[1].reg
;
11259 if (inst
.operands
[1].immisreg
)
11261 inst
.instruction
= THUMB_OP16 (opcode
);
11263 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11265 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11266 reject_bad_reg (inst
.operands
[1].imm
);
11268 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11269 && opcode
!= T_MNEM_ldrsb
)
11270 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11271 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11278 if (inst
.reloc
.pc_rel
)
11279 opcode
= T_MNEM_ldr_pc2
;
11281 opcode
= T_MNEM_ldr_pc
;
11285 if (opcode
== T_MNEM_ldr
)
11286 opcode
= T_MNEM_ldr_sp
;
11288 opcode
= T_MNEM_str_sp
;
11290 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11294 inst
.instruction
= inst
.operands
[0].reg
;
11295 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11297 inst
.instruction
|= THUMB_OP16 (opcode
);
11298 if (inst
.size_req
== 2)
11299 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11301 inst
.relax
= opcode
;
11305 /* Definitely a 32-bit variant. */
11307 /* Warning for Erratum 752419. */
11308 if (opcode
== T_MNEM_ldr
11309 && inst
.operands
[0].reg
== REG_SP
11310 && inst
.operands
[1].writeback
== 1
11311 && !inst
.operands
[1].immisreg
)
11313 if (no_cpu_selected ()
11314 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11316 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11317 as_warn (_("This instruction may be unpredictable "
11318 "if executed on M-profile cores "
11319 "with interrupts enabled."));
11322 /* Do some validations regarding addressing modes. */
11323 if (inst
.operands
[1].immisreg
)
11324 reject_bad_reg (inst
.operands
[1].imm
);
11326 constraint (inst
.operands
[1].writeback
== 1
11327 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11330 inst
.instruction
= THUMB_OP32 (opcode
);
11331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11332 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11333 check_ldr_r15_aligned ();
11337 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11339 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11341 /* Only [Rn,Rm] is acceptable. */
11342 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11343 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11344 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11345 || inst
.operands
[1].negative
,
11346 _("Thumb does not support this addressing mode"));
11347 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11352 if (!inst
.operands
[1].isreg
)
11353 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11356 constraint (!inst
.operands
[1].preind
11357 || inst
.operands
[1].shifted
11358 || inst
.operands
[1].writeback
,
11359 _("Thumb does not support this addressing mode"));
11360 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11362 constraint (inst
.instruction
& 0x0600,
11363 _("byte or halfword not valid for base register"));
11364 constraint (inst
.operands
[1].reg
== REG_PC
11365 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11366 _("r15 based store not allowed"));
11367 constraint (inst
.operands
[1].immisreg
,
11368 _("invalid base register for register offset"));
11370 if (inst
.operands
[1].reg
== REG_PC
)
11371 inst
.instruction
= T_OPCODE_LDR_PC
;
11372 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11373 inst
.instruction
= T_OPCODE_LDR_SP
;
11375 inst
.instruction
= T_OPCODE_STR_SP
;
11377 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11378 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11382 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11383 if (!inst
.operands
[1].immisreg
)
11385 /* Immediate offset. */
11386 inst
.instruction
|= inst
.operands
[0].reg
;
11387 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11388 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11392 /* Register offset. */
11393 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11394 constraint (inst
.operands
[1].negative
,
11395 _("Thumb does not support this addressing mode"));
11398 switch (inst
.instruction
)
11400 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11401 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11402 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11403 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11404 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11405 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11406 case 0x5600 /* ldrsb */:
11407 case 0x5e00 /* ldrsh */: break;
11411 inst
.instruction
|= inst
.operands
[0].reg
;
11412 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11413 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11419 if (!inst
.operands
[1].present
)
11421 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11422 constraint (inst
.operands
[0].reg
== REG_LR
,
11423 _("r14 not allowed here"));
11424 constraint (inst
.operands
[0].reg
== REG_R12
,
11425 _("r12 not allowed here"));
11428 if (inst
.operands
[2].writeback
11429 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11430 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11431 as_warn (_("base register written back, and overlaps "
11432 "one of transfer registers"));
11434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11435 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11436 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11443 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11449 unsigned Rd
, Rn
, Rm
, Ra
;
11451 Rd
= inst
.operands
[0].reg
;
11452 Rn
= inst
.operands
[1].reg
;
11453 Rm
= inst
.operands
[2].reg
;
11454 Ra
= inst
.operands
[3].reg
;
11456 reject_bad_reg (Rd
);
11457 reject_bad_reg (Rn
);
11458 reject_bad_reg (Rm
);
11459 reject_bad_reg (Ra
);
11461 inst
.instruction
|= Rd
<< 8;
11462 inst
.instruction
|= Rn
<< 16;
11463 inst
.instruction
|= Rm
;
11464 inst
.instruction
|= Ra
<< 12;
11470 unsigned RdLo
, RdHi
, Rn
, Rm
;
11472 RdLo
= inst
.operands
[0].reg
;
11473 RdHi
= inst
.operands
[1].reg
;
11474 Rn
= inst
.operands
[2].reg
;
11475 Rm
= inst
.operands
[3].reg
;
11477 reject_bad_reg (RdLo
);
11478 reject_bad_reg (RdHi
);
11479 reject_bad_reg (Rn
);
11480 reject_bad_reg (Rm
);
11482 inst
.instruction
|= RdLo
<< 12;
11483 inst
.instruction
|= RdHi
<< 8;
11484 inst
.instruction
|= Rn
<< 16;
11485 inst
.instruction
|= Rm
;
11489 do_t_mov_cmp (void)
11493 Rn
= inst
.operands
[0].reg
;
11494 Rm
= inst
.operands
[1].reg
;
11497 set_it_insn_type_last ();
11499 if (unified_syntax
)
11501 int r0off
= (inst
.instruction
== T_MNEM_mov
11502 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11503 unsigned long opcode
;
11504 bfd_boolean narrow
;
11505 bfd_boolean low_regs
;
11507 low_regs
= (Rn
<= 7 && Rm
<= 7);
11508 opcode
= inst
.instruction
;
11509 if (in_it_block ())
11510 narrow
= opcode
!= T_MNEM_movs
;
11512 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11513 if (inst
.size_req
== 4
11514 || inst
.operands
[1].shifted
)
11517 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11518 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11519 && !inst
.operands
[1].shifted
11523 inst
.instruction
= T2_SUBS_PC_LR
;
11527 if (opcode
== T_MNEM_cmp
)
11529 constraint (Rn
== REG_PC
, BAD_PC
);
11532 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11534 warn_deprecated_sp (Rm
);
11535 /* R15 was documented as a valid choice for Rm in ARMv6,
11536 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11537 tools reject R15, so we do too. */
11538 constraint (Rm
== REG_PC
, BAD_PC
);
11541 reject_bad_reg (Rm
);
11543 else if (opcode
== T_MNEM_mov
11544 || opcode
== T_MNEM_movs
)
11546 if (inst
.operands
[1].isreg
)
11548 if (opcode
== T_MNEM_movs
)
11550 reject_bad_reg (Rn
);
11551 reject_bad_reg (Rm
);
11555 /* This is mov.n. */
11556 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11557 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11559 as_tsktsk (_("Use of r%u as a source register is "
11560 "deprecated when r%u is the destination "
11561 "register."), Rm
, Rn
);
11566 /* This is mov.w. */
11567 constraint (Rn
== REG_PC
, BAD_PC
);
11568 constraint (Rm
== REG_PC
, BAD_PC
);
11569 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11573 reject_bad_reg (Rn
);
11576 if (!inst
.operands
[1].isreg
)
11578 /* Immediate operand. */
11579 if (!in_it_block () && opcode
== T_MNEM_mov
)
11581 if (low_regs
&& narrow
)
11583 inst
.instruction
= THUMB_OP16 (opcode
);
11584 inst
.instruction
|= Rn
<< 8;
11585 if (inst
.size_req
== 2)
11586 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11588 inst
.relax
= opcode
;
11592 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11593 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11594 inst
.instruction
|= Rn
<< r0off
;
11595 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11598 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11599 && (inst
.instruction
== T_MNEM_mov
11600 || inst
.instruction
== T_MNEM_movs
))
11602 /* Register shifts are encoded as separate shift instructions. */
11603 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11605 if (in_it_block ())
11610 if (inst
.size_req
== 4)
11613 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11619 switch (inst
.operands
[1].shift_kind
)
11622 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11625 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11628 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11631 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11637 inst
.instruction
= opcode
;
11640 inst
.instruction
|= Rn
;
11641 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11646 inst
.instruction
|= CONDS_BIT
;
11648 inst
.instruction
|= Rn
<< 8;
11649 inst
.instruction
|= Rm
<< 16;
11650 inst
.instruction
|= inst
.operands
[1].imm
;
11655 /* Some mov with immediate shift have narrow variants.
11656 Register shifts are handled above. */
11657 if (low_regs
&& inst
.operands
[1].shifted
11658 && (inst
.instruction
== T_MNEM_mov
11659 || inst
.instruction
== T_MNEM_movs
))
11661 if (in_it_block ())
11662 narrow
= (inst
.instruction
== T_MNEM_mov
);
11664 narrow
= (inst
.instruction
== T_MNEM_movs
);
11669 switch (inst
.operands
[1].shift_kind
)
11671 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11672 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11673 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11674 default: narrow
= FALSE
; break;
11680 inst
.instruction
|= Rn
;
11681 inst
.instruction
|= Rm
<< 3;
11682 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11686 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11687 inst
.instruction
|= Rn
<< r0off
;
11688 encode_thumb32_shifted_operand (1);
11692 switch (inst
.instruction
)
11695 /* In v4t or v5t a move of two lowregs produces unpredictable
11696 results. Don't allow this. */
11699 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11700 "MOV Rd, Rs with two low registers is not "
11701 "permitted on this architecture");
11702 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11706 inst
.instruction
= T_OPCODE_MOV_HR
;
11707 inst
.instruction
|= (Rn
& 0x8) << 4;
11708 inst
.instruction
|= (Rn
& 0x7);
11709 inst
.instruction
|= Rm
<< 3;
11713 /* We know we have low registers at this point.
11714 Generate LSLS Rd, Rs, #0. */
11715 inst
.instruction
= T_OPCODE_LSL_I
;
11716 inst
.instruction
|= Rn
;
11717 inst
.instruction
|= Rm
<< 3;
11723 inst
.instruction
= T_OPCODE_CMP_LR
;
11724 inst
.instruction
|= Rn
;
11725 inst
.instruction
|= Rm
<< 3;
11729 inst
.instruction
= T_OPCODE_CMP_HR
;
11730 inst
.instruction
|= (Rn
& 0x8) << 4;
11731 inst
.instruction
|= (Rn
& 0x7);
11732 inst
.instruction
|= Rm
<< 3;
11739 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11741 /* PR 10443: Do not silently ignore shifted operands. */
11742 constraint (inst
.operands
[1].shifted
,
11743 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11745 if (inst
.operands
[1].isreg
)
11747 if (Rn
< 8 && Rm
< 8)
11749 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11750 since a MOV instruction produces unpredictable results. */
11751 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11752 inst
.instruction
= T_OPCODE_ADD_I3
;
11754 inst
.instruction
= T_OPCODE_CMP_LR
;
11756 inst
.instruction
|= Rn
;
11757 inst
.instruction
|= Rm
<< 3;
11761 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11762 inst
.instruction
= T_OPCODE_MOV_HR
;
11764 inst
.instruction
= T_OPCODE_CMP_HR
;
11770 constraint (Rn
> 7,
11771 _("only lo regs allowed with immediate"));
11772 inst
.instruction
|= Rn
<< 8;
11773 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11784 top
= (inst
.instruction
& 0x00800000) != 0;
11785 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11787 constraint (top
, _(":lower16: not allowed this instruction"));
11788 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11790 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11792 constraint (!top
, _(":upper16: not allowed this instruction"));
11793 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11796 Rd
= inst
.operands
[0].reg
;
11797 reject_bad_reg (Rd
);
11799 inst
.instruction
|= Rd
<< 8;
11800 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11802 imm
= inst
.reloc
.exp
.X_add_number
;
11803 inst
.instruction
|= (imm
& 0xf000) << 4;
11804 inst
.instruction
|= (imm
& 0x0800) << 15;
11805 inst
.instruction
|= (imm
& 0x0700) << 4;
11806 inst
.instruction
|= (imm
& 0x00ff);
11811 do_t_mvn_tst (void)
11815 Rn
= inst
.operands
[0].reg
;
11816 Rm
= inst
.operands
[1].reg
;
11818 if (inst
.instruction
== T_MNEM_cmp
11819 || inst
.instruction
== T_MNEM_cmn
)
11820 constraint (Rn
== REG_PC
, BAD_PC
);
11822 reject_bad_reg (Rn
);
11823 reject_bad_reg (Rm
);
11825 if (unified_syntax
)
11827 int r0off
= (inst
.instruction
== T_MNEM_mvn
11828 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11829 bfd_boolean narrow
;
11831 if (inst
.size_req
== 4
11832 || inst
.instruction
> 0xffff
11833 || inst
.operands
[1].shifted
11834 || Rn
> 7 || Rm
> 7)
11836 else if (inst
.instruction
== T_MNEM_cmn
11837 || inst
.instruction
== T_MNEM_tst
)
11839 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11840 narrow
= !in_it_block ();
11842 narrow
= in_it_block ();
11844 if (!inst
.operands
[1].isreg
)
11846 /* For an immediate, we always generate a 32-bit opcode;
11847 section relaxation will shrink it later if possible. */
11848 if (inst
.instruction
< 0xffff)
11849 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11850 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11851 inst
.instruction
|= Rn
<< r0off
;
11852 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11856 /* See if we can do this with a 16-bit instruction. */
11859 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11860 inst
.instruction
|= Rn
;
11861 inst
.instruction
|= Rm
<< 3;
11865 constraint (inst
.operands
[1].shifted
11866 && inst
.operands
[1].immisreg
,
11867 _("shift must be constant"));
11868 if (inst
.instruction
< 0xffff)
11869 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11870 inst
.instruction
|= Rn
<< r0off
;
11871 encode_thumb32_shifted_operand (1);
11877 constraint (inst
.instruction
> 0xffff
11878 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11879 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11880 _("unshifted register required"));
11881 constraint (Rn
> 7 || Rm
> 7,
11884 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11885 inst
.instruction
|= Rn
;
11886 inst
.instruction
|= Rm
<< 3;
11895 if (do_vfp_nsyn_mrs () == SUCCESS
)
11898 Rd
= inst
.operands
[0].reg
;
11899 reject_bad_reg (Rd
);
11900 inst
.instruction
|= Rd
<< 8;
11902 if (inst
.operands
[1].isreg
)
11904 unsigned br
= inst
.operands
[1].reg
;
11905 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11906 as_bad (_("bad register for mrs"));
11908 inst
.instruction
|= br
& (0xf << 16);
11909 inst
.instruction
|= (br
& 0x300) >> 4;
11910 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11914 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11916 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11918 /* PR gas/12698: The constraint is only applied for m_profile.
11919 If the user has specified -march=all, we want to ignore it as
11920 we are building for any CPU type, including non-m variants. */
11921 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11922 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11923 "not support requested special purpose register"));
11926 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11928 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11929 _("'APSR', 'CPSR' or 'SPSR' expected"));
11931 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11932 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11933 inst
.instruction
|= 0xf0000;
11943 if (do_vfp_nsyn_msr () == SUCCESS
)
11946 constraint (!inst
.operands
[1].isreg
,
11947 _("Thumb encoding does not support an immediate here"));
11949 if (inst
.operands
[0].isreg
)
11950 flags
= (int)(inst
.operands
[0].reg
);
11952 flags
= inst
.operands
[0].imm
;
11954 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11956 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11958 /* PR gas/12698: The constraint is only applied for m_profile.
11959 If the user has specified -march=all, we want to ignore it as
11960 we are building for any CPU type, including non-m variants. */
11961 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11962 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11963 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11964 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11965 && bits
!= PSR_f
)) && m_profile
,
11966 _("selected processor does not support requested special "
11967 "purpose register"));
11970 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11971 "requested special purpose register"));
11973 Rn
= inst
.operands
[1].reg
;
11974 reject_bad_reg (Rn
);
11976 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11977 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11978 inst
.instruction
|= (flags
& 0x300) >> 4;
11979 inst
.instruction
|= (flags
& 0xff);
11980 inst
.instruction
|= Rn
<< 16;
11986 bfd_boolean narrow
;
11987 unsigned Rd
, Rn
, Rm
;
11989 if (!inst
.operands
[2].present
)
11990 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11992 Rd
= inst
.operands
[0].reg
;
11993 Rn
= inst
.operands
[1].reg
;
11994 Rm
= inst
.operands
[2].reg
;
11996 if (unified_syntax
)
11998 if (inst
.size_req
== 4
12004 else if (inst
.instruction
== T_MNEM_muls
)
12005 narrow
= !in_it_block ();
12007 narrow
= in_it_block ();
12011 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12012 constraint (Rn
> 7 || Rm
> 7,
12019 /* 16-bit MULS/Conditional MUL. */
12020 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12021 inst
.instruction
|= Rd
;
12024 inst
.instruction
|= Rm
<< 3;
12026 inst
.instruction
|= Rn
<< 3;
12028 constraint (1, _("dest must overlap one source register"));
12032 constraint (inst
.instruction
!= T_MNEM_mul
,
12033 _("Thumb-2 MUL must not set flags"));
12035 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12036 inst
.instruction
|= Rd
<< 8;
12037 inst
.instruction
|= Rn
<< 16;
12038 inst
.instruction
|= Rm
<< 0;
12040 reject_bad_reg (Rd
);
12041 reject_bad_reg (Rn
);
12042 reject_bad_reg (Rm
);
12049 unsigned RdLo
, RdHi
, Rn
, Rm
;
12051 RdLo
= inst
.operands
[0].reg
;
12052 RdHi
= inst
.operands
[1].reg
;
12053 Rn
= inst
.operands
[2].reg
;
12054 Rm
= inst
.operands
[3].reg
;
12056 reject_bad_reg (RdLo
);
12057 reject_bad_reg (RdHi
);
12058 reject_bad_reg (Rn
);
12059 reject_bad_reg (Rm
);
12061 inst
.instruction
|= RdLo
<< 12;
12062 inst
.instruction
|= RdHi
<< 8;
12063 inst
.instruction
|= Rn
<< 16;
12064 inst
.instruction
|= Rm
;
12067 as_tsktsk (_("rdhi and rdlo must be different"));
12073 set_it_insn_type (NEUTRAL_IT_INSN
);
12075 if (unified_syntax
)
12077 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12080 inst
.instruction
|= inst
.operands
[0].imm
;
12084 /* PR9722: Check for Thumb2 availability before
12085 generating a thumb2 nop instruction. */
12086 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12088 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12089 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12092 inst
.instruction
= 0x46c0;
12097 constraint (inst
.operands
[0].present
,
12098 _("Thumb does not support NOP with hints"));
12099 inst
.instruction
= 0x46c0;
12106 if (unified_syntax
)
12108 bfd_boolean narrow
;
12110 if (THUMB_SETS_FLAGS (inst
.instruction
))
12111 narrow
= !in_it_block ();
12113 narrow
= in_it_block ();
12114 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12116 if (inst
.size_req
== 4)
12121 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12122 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12127 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12128 inst
.instruction
|= inst
.operands
[0].reg
;
12129 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12134 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12136 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12138 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12139 inst
.instruction
|= inst
.operands
[0].reg
;
12140 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12149 Rd
= inst
.operands
[0].reg
;
12150 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12152 reject_bad_reg (Rd
);
12153 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12154 reject_bad_reg (Rn
);
12156 inst
.instruction
|= Rd
<< 8;
12157 inst
.instruction
|= Rn
<< 16;
12159 if (!inst
.operands
[2].isreg
)
12161 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12162 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12168 Rm
= inst
.operands
[2].reg
;
12169 reject_bad_reg (Rm
);
12171 constraint (inst
.operands
[2].shifted
12172 && inst
.operands
[2].immisreg
,
12173 _("shift must be constant"));
12174 encode_thumb32_shifted_operand (2);
12181 unsigned Rd
, Rn
, Rm
;
12183 Rd
= inst
.operands
[0].reg
;
12184 Rn
= inst
.operands
[1].reg
;
12185 Rm
= inst
.operands
[2].reg
;
12187 reject_bad_reg (Rd
);
12188 reject_bad_reg (Rn
);
12189 reject_bad_reg (Rm
);
12191 inst
.instruction
|= Rd
<< 8;
12192 inst
.instruction
|= Rn
<< 16;
12193 inst
.instruction
|= Rm
;
12194 if (inst
.operands
[3].present
)
12196 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12197 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12198 _("expression too complex"));
12199 inst
.instruction
|= (val
& 0x1c) << 10;
12200 inst
.instruction
|= (val
& 0x03) << 6;
12207 if (!inst
.operands
[3].present
)
12211 inst
.instruction
&= ~0x00000020;
12213 /* PR 10168. Swap the Rm and Rn registers. */
12214 Rtmp
= inst
.operands
[1].reg
;
12215 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12216 inst
.operands
[2].reg
= Rtmp
;
12224 if (inst
.operands
[0].immisreg
)
12225 reject_bad_reg (inst
.operands
[0].imm
);
12227 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12231 do_t_push_pop (void)
12235 constraint (inst
.operands
[0].writeback
,
12236 _("push/pop do not support {reglist}^"));
12237 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12238 _("expression too complex"));
12240 mask
= inst
.operands
[0].imm
;
12241 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12242 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12243 else if (inst
.size_req
!= 4
12244 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12245 ? REG_LR
: REG_PC
)))
12247 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12248 inst
.instruction
|= THUMB_PP_PC_LR
;
12249 inst
.instruction
|= mask
& 0xff;
12251 else if (unified_syntax
)
12253 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12254 encode_thumb2_ldmstm (13, mask
, TRUE
);
12258 inst
.error
= _("invalid register list to push/pop instruction");
12268 Rd
= inst
.operands
[0].reg
;
12269 Rm
= inst
.operands
[1].reg
;
12271 reject_bad_reg (Rd
);
12272 reject_bad_reg (Rm
);
12274 inst
.instruction
|= Rd
<< 8;
12275 inst
.instruction
|= Rm
<< 16;
12276 inst
.instruction
|= Rm
;
12284 Rd
= inst
.operands
[0].reg
;
12285 Rm
= inst
.operands
[1].reg
;
12287 reject_bad_reg (Rd
);
12288 reject_bad_reg (Rm
);
12290 if (Rd
<= 7 && Rm
<= 7
12291 && inst
.size_req
!= 4)
12293 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12294 inst
.instruction
|= Rd
;
12295 inst
.instruction
|= Rm
<< 3;
12297 else if (unified_syntax
)
12299 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12300 inst
.instruction
|= Rd
<< 8;
12301 inst
.instruction
|= Rm
<< 16;
12302 inst
.instruction
|= Rm
;
12305 inst
.error
= BAD_HIREG
;
12313 Rd
= inst
.operands
[0].reg
;
12314 Rm
= inst
.operands
[1].reg
;
12316 reject_bad_reg (Rd
);
12317 reject_bad_reg (Rm
);
12319 inst
.instruction
|= Rd
<< 8;
12320 inst
.instruction
|= Rm
;
12328 Rd
= inst
.operands
[0].reg
;
12329 Rs
= (inst
.operands
[1].present
12330 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12331 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12333 reject_bad_reg (Rd
);
12334 reject_bad_reg (Rs
);
12335 if (inst
.operands
[2].isreg
)
12336 reject_bad_reg (inst
.operands
[2].reg
);
12338 inst
.instruction
|= Rd
<< 8;
12339 inst
.instruction
|= Rs
<< 16;
12340 if (!inst
.operands
[2].isreg
)
12342 bfd_boolean narrow
;
12344 if ((inst
.instruction
& 0x00100000) != 0)
12345 narrow
= !in_it_block ();
12347 narrow
= in_it_block ();
12349 if (Rd
> 7 || Rs
> 7)
12352 if (inst
.size_req
== 4 || !unified_syntax
)
12355 if (inst
.reloc
.exp
.X_op
!= O_constant
12356 || inst
.reloc
.exp
.X_add_number
!= 0)
12359 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12360 relaxation, but it doesn't seem worth the hassle. */
12363 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12364 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12365 inst
.instruction
|= Rs
<< 3;
12366 inst
.instruction
|= Rd
;
12370 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12371 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12375 encode_thumb32_shifted_operand (2);
12381 if (warn_on_deprecated
12382 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12383 as_tsktsk (_("setend use is deprecated for ARMv8"));
12385 set_it_insn_type (OUTSIDE_IT_INSN
);
12386 if (inst
.operands
[0].imm
)
12387 inst
.instruction
|= 0x8;
12393 if (!inst
.operands
[1].present
)
12394 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12396 if (unified_syntax
)
12398 bfd_boolean narrow
;
12401 switch (inst
.instruction
)
12404 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12406 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12408 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12410 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12414 if (THUMB_SETS_FLAGS (inst
.instruction
))
12415 narrow
= !in_it_block ();
12417 narrow
= in_it_block ();
12418 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12420 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12422 if (inst
.operands
[2].isreg
12423 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12424 || inst
.operands
[2].reg
> 7))
12426 if (inst
.size_req
== 4)
12429 reject_bad_reg (inst
.operands
[0].reg
);
12430 reject_bad_reg (inst
.operands
[1].reg
);
12434 if (inst
.operands
[2].isreg
)
12436 reject_bad_reg (inst
.operands
[2].reg
);
12437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12438 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12439 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12440 inst
.instruction
|= inst
.operands
[2].reg
;
12442 /* PR 12854: Error on extraneous shifts. */
12443 constraint (inst
.operands
[2].shifted
,
12444 _("extraneous shift as part of operand to shift insn"));
12448 inst
.operands
[1].shifted
= 1;
12449 inst
.operands
[1].shift_kind
= shift_kind
;
12450 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12451 ? T_MNEM_movs
: T_MNEM_mov
);
12452 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12453 encode_thumb32_shifted_operand (1);
12454 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12455 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12460 if (inst
.operands
[2].isreg
)
12462 switch (shift_kind
)
12464 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12465 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12466 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12467 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12471 inst
.instruction
|= inst
.operands
[0].reg
;
12472 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12474 /* PR 12854: Error on extraneous shifts. */
12475 constraint (inst
.operands
[2].shifted
,
12476 _("extraneous shift as part of operand to shift insn"));
12480 switch (shift_kind
)
12482 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12483 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12484 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12487 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12488 inst
.instruction
|= inst
.operands
[0].reg
;
12489 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12495 constraint (inst
.operands
[0].reg
> 7
12496 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12497 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12499 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12501 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12502 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12503 _("source1 and dest must be same register"));
12505 switch (inst
.instruction
)
12507 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12508 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12509 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12510 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12514 inst
.instruction
|= inst
.operands
[0].reg
;
12515 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12517 /* PR 12854: Error on extraneous shifts. */
12518 constraint (inst
.operands
[2].shifted
,
12519 _("extraneous shift as part of operand to shift insn"));
12523 switch (inst
.instruction
)
12525 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12526 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12527 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12528 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12531 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12532 inst
.instruction
|= inst
.operands
[0].reg
;
12533 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12541 unsigned Rd
, Rn
, Rm
;
12543 Rd
= inst
.operands
[0].reg
;
12544 Rn
= inst
.operands
[1].reg
;
12545 Rm
= inst
.operands
[2].reg
;
12547 reject_bad_reg (Rd
);
12548 reject_bad_reg (Rn
);
12549 reject_bad_reg (Rm
);
12551 inst
.instruction
|= Rd
<< 8;
12552 inst
.instruction
|= Rn
<< 16;
12553 inst
.instruction
|= Rm
;
12559 unsigned Rd
, Rn
, Rm
;
12561 Rd
= inst
.operands
[0].reg
;
12562 Rm
= inst
.operands
[1].reg
;
12563 Rn
= inst
.operands
[2].reg
;
12565 reject_bad_reg (Rd
);
12566 reject_bad_reg (Rn
);
12567 reject_bad_reg (Rm
);
12569 inst
.instruction
|= Rd
<< 8;
12570 inst
.instruction
|= Rn
<< 16;
12571 inst
.instruction
|= Rm
;
12577 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12578 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12579 _("SMC is not permitted on this architecture"));
12580 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12581 _("expression too complex"));
12582 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12583 inst
.instruction
|= (value
& 0xf000) >> 12;
12584 inst
.instruction
|= (value
& 0x0ff0);
12585 inst
.instruction
|= (value
& 0x000f) << 16;
12586 /* PR gas/15623: SMC instructions must be last in an IT block. */
12587 set_it_insn_type_last ();
12593 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12595 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12596 inst
.instruction
|= (value
& 0x0fff);
12597 inst
.instruction
|= (value
& 0xf000) << 4;
12601 do_t_ssat_usat (int bias
)
12605 Rd
= inst
.operands
[0].reg
;
12606 Rn
= inst
.operands
[2].reg
;
12608 reject_bad_reg (Rd
);
12609 reject_bad_reg (Rn
);
12611 inst
.instruction
|= Rd
<< 8;
12612 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12613 inst
.instruction
|= Rn
<< 16;
12615 if (inst
.operands
[3].present
)
12617 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12619 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12621 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12622 _("expression too complex"));
12624 if (shift_amount
!= 0)
12626 constraint (shift_amount
> 31,
12627 _("shift expression is too large"));
12629 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12630 inst
.instruction
|= 0x00200000; /* sh bit. */
12632 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12633 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12641 do_t_ssat_usat (1);
12649 Rd
= inst
.operands
[0].reg
;
12650 Rn
= inst
.operands
[2].reg
;
12652 reject_bad_reg (Rd
);
12653 reject_bad_reg (Rn
);
12655 inst
.instruction
|= Rd
<< 8;
12656 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12657 inst
.instruction
|= Rn
<< 16;
12663 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12664 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12665 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12666 || inst
.operands
[2].negative
,
12669 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12671 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12672 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12673 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12674 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12680 if (!inst
.operands
[2].present
)
12681 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12683 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12684 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12685 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12688 inst
.instruction
|= inst
.operands
[0].reg
;
12689 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12690 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12691 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12697 unsigned Rd
, Rn
, Rm
;
12699 Rd
= inst
.operands
[0].reg
;
12700 Rn
= inst
.operands
[1].reg
;
12701 Rm
= inst
.operands
[2].reg
;
12703 reject_bad_reg (Rd
);
12704 reject_bad_reg (Rn
);
12705 reject_bad_reg (Rm
);
12707 inst
.instruction
|= Rd
<< 8;
12708 inst
.instruction
|= Rn
<< 16;
12709 inst
.instruction
|= Rm
;
12710 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12718 Rd
= inst
.operands
[0].reg
;
12719 Rm
= inst
.operands
[1].reg
;
12721 reject_bad_reg (Rd
);
12722 reject_bad_reg (Rm
);
12724 if (inst
.instruction
<= 0xffff
12725 && inst
.size_req
!= 4
12726 && Rd
<= 7 && Rm
<= 7
12727 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12729 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12730 inst
.instruction
|= Rd
;
12731 inst
.instruction
|= Rm
<< 3;
12733 else if (unified_syntax
)
12735 if (inst
.instruction
<= 0xffff)
12736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12737 inst
.instruction
|= Rd
<< 8;
12738 inst
.instruction
|= Rm
;
12739 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12743 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12744 _("Thumb encoding does not support rotation"));
12745 constraint (1, BAD_HIREG
);
12752 /* We have to do the following check manually as ARM_EXT_OS only applies
12754 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12756 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12757 /* This only applies to the v6m howver, not later architectures. */
12758 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12759 as_bad (_("SVC is not permitted on this architecture"));
12760 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12763 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12772 half
= (inst
.instruction
& 0x10) != 0;
12773 set_it_insn_type_last ();
12774 constraint (inst
.operands
[0].immisreg
,
12775 _("instruction requires register index"));
12777 Rn
= inst
.operands
[0].reg
;
12778 Rm
= inst
.operands
[0].imm
;
12780 constraint (Rn
== REG_SP
, BAD_SP
);
12781 reject_bad_reg (Rm
);
12783 constraint (!half
&& inst
.operands
[0].shifted
,
12784 _("instruction does not allow shifted index"));
12785 inst
.instruction
|= (Rn
<< 16) | Rm
;
12791 if (!inst
.operands
[0].present
)
12792 inst
.operands
[0].imm
= 0;
12794 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12796 constraint (inst
.size_req
== 2,
12797 _("immediate value out of range"));
12798 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12799 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12800 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12804 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12805 inst
.instruction
|= inst
.operands
[0].imm
;
12808 set_it_insn_type (NEUTRAL_IT_INSN
);
12815 do_t_ssat_usat (0);
12823 Rd
= inst
.operands
[0].reg
;
12824 Rn
= inst
.operands
[2].reg
;
12826 reject_bad_reg (Rd
);
12827 reject_bad_reg (Rn
);
12829 inst
.instruction
|= Rd
<< 8;
12830 inst
.instruction
|= inst
.operands
[1].imm
;
12831 inst
.instruction
|= Rn
<< 16;
12834 /* Neon instruction encoder helpers. */
12836 /* Encodings for the different types for various Neon opcodes. */
12838 /* An "invalid" code for the following tables. */
12841 struct neon_tab_entry
12844 unsigned float_or_poly
;
12845 unsigned scalar_or_imm
;
12848 /* Map overloaded Neon opcodes to their respective encodings. */
12849 #define NEON_ENC_TAB \
12850 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12851 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12852 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12853 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12854 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12855 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12856 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12857 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12858 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12859 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12860 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12861 /* Register variants of the following two instructions are encoded as
12862 vcge / vcgt with the operands reversed. */ \
12863 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12864 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12865 X(vfma, N_INV, 0x0000c10, N_INV), \
12866 X(vfms, N_INV, 0x0200c10, N_INV), \
12867 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12868 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12869 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12870 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12871 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12872 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12873 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12874 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12875 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12876 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12877 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12878 X(vshl, 0x0000400, N_INV, 0x0800510), \
12879 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12880 X(vand, 0x0000110, N_INV, 0x0800030), \
12881 X(vbic, 0x0100110, N_INV, 0x0800030), \
12882 X(veor, 0x1000110, N_INV, N_INV), \
12883 X(vorn, 0x0300110, N_INV, 0x0800010), \
12884 X(vorr, 0x0200110, N_INV, 0x0800010), \
12885 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12886 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12887 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12888 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12889 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12890 X(vst1, 0x0000000, 0x0800000, N_INV), \
12891 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12892 X(vst2, 0x0000100, 0x0800100, N_INV), \
12893 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12894 X(vst3, 0x0000200, 0x0800200, N_INV), \
12895 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12896 X(vst4, 0x0000300, 0x0800300, N_INV), \
12897 X(vmovn, 0x1b20200, N_INV, N_INV), \
12898 X(vtrn, 0x1b20080, N_INV, N_INV), \
12899 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12900 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12901 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12902 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12903 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12904 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12905 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12906 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12907 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12908 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12909 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12910 X(vseleq, 0xe000a00, N_INV, N_INV), \
12911 X(vselvs, 0xe100a00, N_INV, N_INV), \
12912 X(vselge, 0xe200a00, N_INV, N_INV), \
12913 X(vselgt, 0xe300a00, N_INV, N_INV), \
12914 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12915 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12916 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12917 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12918 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12919 X(aes, 0x3b00300, N_INV, N_INV), \
12920 X(sha3op, 0x2000c00, N_INV, N_INV), \
12921 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12922 X(sha2op, 0x3ba0380, N_INV, N_INV)
12926 #define X(OPC,I,F,S) N_MNEM_##OPC
12931 static const struct neon_tab_entry neon_enc_tab
[] =
12933 #define X(OPC,I,F,S) { (I), (F), (S) }
12938 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12939 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12940 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12941 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12942 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12943 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12944 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12945 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12946 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12947 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12948 #define NEON_ENC_SINGLE_(X) \
12949 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12950 #define NEON_ENC_DOUBLE_(X) \
12951 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12952 #define NEON_ENC_FPV8_(X) \
12953 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12955 #define NEON_ENCODE(type, inst) \
12958 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12959 inst.is_neon = 1; \
12963 #define check_neon_suffixes \
12966 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12968 as_bad (_("invalid neon suffix for non neon instruction")); \
12974 /* Define shapes for instruction operands. The following mnemonic characters
12975 are used in this table:
12977 F - VFP S<n> register
12978 D - Neon D<n> register
12979 Q - Neon Q<n> register
12983 L - D<n> register list
12985 This table is used to generate various data:
12986 - enumerations of the form NS_DDR to be used as arguments to
12988 - a table classifying shapes into single, double, quad, mixed.
12989 - a table used to drive neon_select_shape. */
12991 #define NEON_SHAPE_DEF \
12992 X(3, (D, D, D), DOUBLE), \
12993 X(3, (Q, Q, Q), QUAD), \
12994 X(3, (D, D, I), DOUBLE), \
12995 X(3, (Q, Q, I), QUAD), \
12996 X(3, (D, D, S), DOUBLE), \
12997 X(3, (Q, Q, S), QUAD), \
12998 X(2, (D, D), DOUBLE), \
12999 X(2, (Q, Q), QUAD), \
13000 X(2, (D, S), DOUBLE), \
13001 X(2, (Q, S), QUAD), \
13002 X(2, (D, R), DOUBLE), \
13003 X(2, (Q, R), QUAD), \
13004 X(2, (D, I), DOUBLE), \
13005 X(2, (Q, I), QUAD), \
13006 X(3, (D, L, D), DOUBLE), \
13007 X(2, (D, Q), MIXED), \
13008 X(2, (Q, D), MIXED), \
13009 X(3, (D, Q, I), MIXED), \
13010 X(3, (Q, D, I), MIXED), \
13011 X(3, (Q, D, D), MIXED), \
13012 X(3, (D, Q, Q), MIXED), \
13013 X(3, (Q, Q, D), MIXED), \
13014 X(3, (Q, D, S), MIXED), \
13015 X(3, (D, Q, S), MIXED), \
13016 X(4, (D, D, D, I), DOUBLE), \
13017 X(4, (Q, Q, Q, I), QUAD), \
13018 X(2, (F, F), SINGLE), \
13019 X(3, (F, F, F), SINGLE), \
13020 X(2, (F, I), SINGLE), \
13021 X(2, (F, D), MIXED), \
13022 X(2, (D, F), MIXED), \
13023 X(3, (F, F, I), MIXED), \
13024 X(4, (R, R, F, F), SINGLE), \
13025 X(4, (F, F, R, R), SINGLE), \
13026 X(3, (D, R, R), DOUBLE), \
13027 X(3, (R, R, D), DOUBLE), \
13028 X(2, (S, R), SINGLE), \
13029 X(2, (R, S), SINGLE), \
13030 X(2, (F, R), SINGLE), \
13031 X(2, (R, F), SINGLE)
13033 #define S2(A,B) NS_##A##B
13034 #define S3(A,B,C) NS_##A##B##C
13035 #define S4(A,B,C,D) NS_##A##B##C##D
13037 #define X(N, L, C) S##N L
13050 enum neon_shape_class
13058 #define X(N, L, C) SC_##C
13060 static enum neon_shape_class neon_shape_class
[] =
13078 /* Register widths of above. */
13079 static unsigned neon_shape_el_size
[] =
13090 struct neon_shape_info
13093 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13096 #define S2(A,B) { SE_##A, SE_##B }
13097 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13098 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13100 #define X(N, L, C) { N, S##N L }
13102 static struct neon_shape_info neon_shape_tab
[] =
13112 /* Bit masks used in type checking given instructions.
13113 'N_EQK' means the type must be the same as (or based on in some way) the key
13114 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13115 set, various other bits can be set as well in order to modify the meaning of
13116 the type constraint. */
13118 enum neon_type_mask
13142 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13143 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13144 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13145 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13146 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13147 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13148 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13149 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13150 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13151 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13152 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13154 N_MAX_NONSPECIAL
= N_P64
13157 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13159 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13160 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13161 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13162 #define N_SUF_32 (N_SU_32 | N_F32)
13163 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13164 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13166 /* Pass this as the first type argument to neon_check_type to ignore types
13168 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13170 /* Select a "shape" for the current instruction (describing register types or
13171 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13172 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13173 function of operand parsing, so this function doesn't need to be called.
13174 Shapes should be listed in order of decreasing length. */
13176 static enum neon_shape
13177 neon_select_shape (enum neon_shape shape
, ...)
13180 enum neon_shape first_shape
= shape
;
13182 /* Fix missing optional operands. FIXME: we don't know at this point how
13183 many arguments we should have, so this makes the assumption that we have
13184 > 1. This is true of all current Neon opcodes, I think, but may not be
13185 true in the future. */
13186 if (!inst
.operands
[1].present
)
13187 inst
.operands
[1] = inst
.operands
[0];
13189 va_start (ap
, shape
);
13191 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13196 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13198 if (!inst
.operands
[j
].present
)
13204 switch (neon_shape_tab
[shape
].el
[j
])
13207 if (!(inst
.operands
[j
].isreg
13208 && inst
.operands
[j
].isvec
13209 && inst
.operands
[j
].issingle
13210 && !inst
.operands
[j
].isquad
))
13215 if (!(inst
.operands
[j
].isreg
13216 && inst
.operands
[j
].isvec
13217 && !inst
.operands
[j
].isquad
13218 && !inst
.operands
[j
].issingle
))
13223 if (!(inst
.operands
[j
].isreg
13224 && !inst
.operands
[j
].isvec
))
13229 if (!(inst
.operands
[j
].isreg
13230 && inst
.operands
[j
].isvec
13231 && inst
.operands
[j
].isquad
13232 && !inst
.operands
[j
].issingle
))
13237 if (!(!inst
.operands
[j
].isreg
13238 && !inst
.operands
[j
].isscalar
))
13243 if (!(!inst
.operands
[j
].isreg
13244 && inst
.operands
[j
].isscalar
))
13254 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13255 /* We've matched all the entries in the shape table, and we don't
13256 have any left over operands which have not been matched. */
13262 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13263 first_error (_("invalid instruction shape"));
13268 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13269 means the Q bit should be set). */
13272 neon_quad (enum neon_shape shape
)
13274 return neon_shape_class
[shape
] == SC_QUAD
;
13278 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13281 /* Allow modification to be made to types which are constrained to be
13282 based on the key element, based on bits set alongside N_EQK. */
13283 if ((typebits
& N_EQK
) != 0)
13285 if ((typebits
& N_HLF
) != 0)
13287 else if ((typebits
& N_DBL
) != 0)
13289 if ((typebits
& N_SGN
) != 0)
13290 *g_type
= NT_signed
;
13291 else if ((typebits
& N_UNS
) != 0)
13292 *g_type
= NT_unsigned
;
13293 else if ((typebits
& N_INT
) != 0)
13294 *g_type
= NT_integer
;
13295 else if ((typebits
& N_FLT
) != 0)
13296 *g_type
= NT_float
;
13297 else if ((typebits
& N_SIZ
) != 0)
13298 *g_type
= NT_untyped
;
13302 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13303 operand type, i.e. the single type specified in a Neon instruction when it
13304 is the only one given. */
13306 static struct neon_type_el
13307 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13309 struct neon_type_el dest
= *key
;
13311 gas_assert ((thisarg
& N_EQK
) != 0);
13313 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13318 /* Convert Neon type and size into compact bitmask representation. */
13320 static enum neon_type_mask
13321 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13328 case 8: return N_8
;
13329 case 16: return N_16
;
13330 case 32: return N_32
;
13331 case 64: return N_64
;
13339 case 8: return N_I8
;
13340 case 16: return N_I16
;
13341 case 32: return N_I32
;
13342 case 64: return N_I64
;
13350 case 16: return N_F16
;
13351 case 32: return N_F32
;
13352 case 64: return N_F64
;
13360 case 8: return N_P8
;
13361 case 16: return N_P16
;
13362 case 64: return N_P64
;
13370 case 8: return N_S8
;
13371 case 16: return N_S16
;
13372 case 32: return N_S32
;
13373 case 64: return N_S64
;
13381 case 8: return N_U8
;
13382 case 16: return N_U16
;
13383 case 32: return N_U32
;
13384 case 64: return N_U64
;
13395 /* Convert compact Neon bitmask type representation to a type and size. Only
13396 handles the case where a single bit is set in the mask. */
13399 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13400 enum neon_type_mask mask
)
13402 if ((mask
& N_EQK
) != 0)
13405 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13407 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13409 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13411 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13416 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13418 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13419 *type
= NT_unsigned
;
13420 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13421 *type
= NT_integer
;
13422 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13423 *type
= NT_untyped
;
13424 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13426 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13434 /* Modify a bitmask of allowed types. This is only needed for type
13438 modify_types_allowed (unsigned allowed
, unsigned mods
)
13441 enum neon_el_type type
;
13447 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13449 if (el_type_of_type_chk (&type
, &size
,
13450 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13452 neon_modify_type_size (mods
, &type
, &size
);
13453 destmask
|= type_chk_of_el_type (type
, size
);
13460 /* Check type and return type classification.
13461 The manual states (paraphrase): If one datatype is given, it indicates the
13463 - the second operand, if there is one
13464 - the operand, if there is no second operand
13465 - the result, if there are no operands.
13466 This isn't quite good enough though, so we use a concept of a "key" datatype
13467 which is set on a per-instruction basis, which is the one which matters when
13468 only one data type is written.
13469 Note: this function has side-effects (e.g. filling in missing operands). All
13470 Neon instructions should call it before performing bit encoding. */
13472 static struct neon_type_el
13473 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13476 unsigned i
, pass
, key_el
= 0;
13477 unsigned types
[NEON_MAX_TYPE_ELS
];
13478 enum neon_el_type k_type
= NT_invtype
;
13479 unsigned k_size
= -1u;
13480 struct neon_type_el badtype
= {NT_invtype
, -1};
13481 unsigned key_allowed
= 0;
13483 /* Optional registers in Neon instructions are always (not) in operand 1.
13484 Fill in the missing operand here, if it was omitted. */
13485 if (els
> 1 && !inst
.operands
[1].present
)
13486 inst
.operands
[1] = inst
.operands
[0];
13488 /* Suck up all the varargs. */
13490 for (i
= 0; i
< els
; i
++)
13492 unsigned thisarg
= va_arg (ap
, unsigned);
13493 if (thisarg
== N_IGNORE_TYPE
)
13498 types
[i
] = thisarg
;
13499 if ((thisarg
& N_KEY
) != 0)
13504 if (inst
.vectype
.elems
> 0)
13505 for (i
= 0; i
< els
; i
++)
13506 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13508 first_error (_("types specified in both the mnemonic and operands"));
13512 /* Duplicate inst.vectype elements here as necessary.
13513 FIXME: No idea if this is exactly the same as the ARM assembler,
13514 particularly when an insn takes one register and one non-register
13516 if (inst
.vectype
.elems
== 1 && els
> 1)
13519 inst
.vectype
.elems
= els
;
13520 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13521 for (j
= 0; j
< els
; j
++)
13523 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13526 else if (inst
.vectype
.elems
== 0 && els
> 0)
13529 /* No types were given after the mnemonic, so look for types specified
13530 after each operand. We allow some flexibility here; as long as the
13531 "key" operand has a type, we can infer the others. */
13532 for (j
= 0; j
< els
; j
++)
13533 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13534 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13536 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13538 for (j
= 0; j
< els
; j
++)
13539 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13540 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13545 first_error (_("operand types can't be inferred"));
13549 else if (inst
.vectype
.elems
!= els
)
13551 first_error (_("type specifier has the wrong number of parts"));
13555 for (pass
= 0; pass
< 2; pass
++)
13557 for (i
= 0; i
< els
; i
++)
13559 unsigned thisarg
= types
[i
];
13560 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13561 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13562 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13563 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13565 /* Decay more-specific signed & unsigned types to sign-insensitive
13566 integer types if sign-specific variants are unavailable. */
13567 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13568 && (types_allowed
& N_SU_ALL
) == 0)
13569 g_type
= NT_integer
;
13571 /* If only untyped args are allowed, decay any more specific types to
13572 them. Some instructions only care about signs for some element
13573 sizes, so handle that properly. */
13574 if (((types_allowed
& N_UNT
) == 0)
13575 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13576 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13577 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13578 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13579 g_type
= NT_untyped
;
13583 if ((thisarg
& N_KEY
) != 0)
13587 key_allowed
= thisarg
& ~N_KEY
;
13592 if ((thisarg
& N_VFP
) != 0)
13594 enum neon_shape_el regshape
;
13595 unsigned regwidth
, match
;
13597 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13600 first_error (_("invalid instruction shape"));
13603 regshape
= neon_shape_tab
[ns
].el
[i
];
13604 regwidth
= neon_shape_el_size
[regshape
];
13606 /* In VFP mode, operands must match register widths. If we
13607 have a key operand, use its width, else use the width of
13608 the current operand. */
13614 if (regwidth
!= match
)
13616 first_error (_("operand size must match register width"));
13621 if ((thisarg
& N_EQK
) == 0)
13623 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13625 if ((given_type
& types_allowed
) == 0)
13627 first_error (_("bad type in Neon instruction"));
13633 enum neon_el_type mod_k_type
= k_type
;
13634 unsigned mod_k_size
= k_size
;
13635 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13636 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13638 first_error (_("inconsistent types in Neon instruction"));
13646 return inst
.vectype
.el
[key_el
];
13649 /* Neon-style VFP instruction forwarding. */
13651 /* Thumb VFP instructions have 0xE in the condition field. */
13654 do_vfp_cond_or_thumb (void)
13659 inst
.instruction
|= 0xe0000000;
13661 inst
.instruction
|= inst
.cond
<< 28;
13664 /* Look up and encode a simple mnemonic, for use as a helper function for the
13665 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13666 etc. It is assumed that operand parsing has already been done, and that the
13667 operands are in the form expected by the given opcode (this isn't necessarily
13668 the same as the form in which they were parsed, hence some massaging must
13669 take place before this function is called).
13670 Checks current arch version against that in the looked-up opcode. */
13673 do_vfp_nsyn_opcode (const char *opname
)
13675 const struct asm_opcode
*opcode
;
13677 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13682 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13683 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13690 inst
.instruction
= opcode
->tvalue
;
13691 opcode
->tencode ();
13695 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13696 opcode
->aencode ();
13701 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13703 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13708 do_vfp_nsyn_opcode ("fadds");
13710 do_vfp_nsyn_opcode ("fsubs");
13715 do_vfp_nsyn_opcode ("faddd");
13717 do_vfp_nsyn_opcode ("fsubd");
13721 /* Check operand types to see if this is a VFP instruction, and if so call
13725 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13727 enum neon_shape rs
;
13728 struct neon_type_el et
;
13733 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13734 et
= neon_check_type (2, rs
,
13735 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13739 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13740 et
= neon_check_type (3, rs
,
13741 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13748 if (et
.type
!= NT_invtype
)
13759 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13761 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13766 do_vfp_nsyn_opcode ("fmacs");
13768 do_vfp_nsyn_opcode ("fnmacs");
13773 do_vfp_nsyn_opcode ("fmacd");
13775 do_vfp_nsyn_opcode ("fnmacd");
13780 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13782 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13787 do_vfp_nsyn_opcode ("ffmas");
13789 do_vfp_nsyn_opcode ("ffnmas");
13794 do_vfp_nsyn_opcode ("ffmad");
13796 do_vfp_nsyn_opcode ("ffnmad");
13801 do_vfp_nsyn_mul (enum neon_shape rs
)
13804 do_vfp_nsyn_opcode ("fmuls");
13806 do_vfp_nsyn_opcode ("fmuld");
13810 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13812 int is_neg
= (inst
.instruction
& 0x80) != 0;
13813 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13818 do_vfp_nsyn_opcode ("fnegs");
13820 do_vfp_nsyn_opcode ("fabss");
13825 do_vfp_nsyn_opcode ("fnegd");
13827 do_vfp_nsyn_opcode ("fabsd");
13831 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13832 insns belong to Neon, and are handled elsewhere. */
13835 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13837 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13841 do_vfp_nsyn_opcode ("fldmdbs");
13843 do_vfp_nsyn_opcode ("fldmias");
13848 do_vfp_nsyn_opcode ("fstmdbs");
13850 do_vfp_nsyn_opcode ("fstmias");
13855 do_vfp_nsyn_sqrt (void)
13857 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13858 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13861 do_vfp_nsyn_opcode ("fsqrts");
13863 do_vfp_nsyn_opcode ("fsqrtd");
13867 do_vfp_nsyn_div (void)
13869 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13870 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13871 N_F32
| N_F64
| N_KEY
| N_VFP
);
13874 do_vfp_nsyn_opcode ("fdivs");
13876 do_vfp_nsyn_opcode ("fdivd");
13880 do_vfp_nsyn_nmul (void)
13882 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13883 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13884 N_F32
| N_F64
| N_KEY
| N_VFP
);
13888 NEON_ENCODE (SINGLE
, inst
);
13889 do_vfp_sp_dyadic ();
13893 NEON_ENCODE (DOUBLE
, inst
);
13894 do_vfp_dp_rd_rn_rm ();
13896 do_vfp_cond_or_thumb ();
13900 do_vfp_nsyn_cmp (void)
13902 if (inst
.operands
[1].isreg
)
13904 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13905 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13909 NEON_ENCODE (SINGLE
, inst
);
13910 do_vfp_sp_monadic ();
13914 NEON_ENCODE (DOUBLE
, inst
);
13915 do_vfp_dp_rd_rm ();
13920 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13921 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13923 switch (inst
.instruction
& 0x0fffffff)
13926 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13929 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13937 NEON_ENCODE (SINGLE
, inst
);
13938 do_vfp_sp_compare_z ();
13942 NEON_ENCODE (DOUBLE
, inst
);
13946 do_vfp_cond_or_thumb ();
13950 nsyn_insert_sp (void)
13952 inst
.operands
[1] = inst
.operands
[0];
13953 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13954 inst
.operands
[0].reg
= REG_SP
;
13955 inst
.operands
[0].isreg
= 1;
13956 inst
.operands
[0].writeback
= 1;
13957 inst
.operands
[0].present
= 1;
13961 do_vfp_nsyn_push (void)
13964 if (inst
.operands
[1].issingle
)
13965 do_vfp_nsyn_opcode ("fstmdbs");
13967 do_vfp_nsyn_opcode ("fstmdbd");
13971 do_vfp_nsyn_pop (void)
13974 if (inst
.operands
[1].issingle
)
13975 do_vfp_nsyn_opcode ("fldmias");
13977 do_vfp_nsyn_opcode ("fldmiad");
13980 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13981 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13984 neon_dp_fixup (struct arm_it
* insn
)
13986 unsigned int i
= insn
->instruction
;
13991 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14002 insn
->instruction
= i
;
14005 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14009 neon_logbits (unsigned x
)
14011 return ffs (x
) - 4;
14014 #define LOW4(R) ((R) & 0xf)
14015 #define HI1(R) (((R) >> 4) & 1)
14017 /* Encode insns with bit pattern:
14019 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14020 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14022 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14023 different meaning for some instruction. */
14026 neon_three_same (int isquad
, int ubit
, int size
)
14028 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14029 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14030 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14031 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14032 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14033 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14034 inst
.instruction
|= (isquad
!= 0) << 6;
14035 inst
.instruction
|= (ubit
!= 0) << 24;
14037 inst
.instruction
|= neon_logbits (size
) << 20;
14039 neon_dp_fixup (&inst
);
14042 /* Encode instructions of the form:
14044 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14045 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14047 Don't write size if SIZE == -1. */
14050 neon_two_same (int qbit
, int ubit
, int size
)
14052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14055 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14056 inst
.instruction
|= (qbit
!= 0) << 6;
14057 inst
.instruction
|= (ubit
!= 0) << 24;
14060 inst
.instruction
|= neon_logbits (size
) << 18;
14062 neon_dp_fixup (&inst
);
14065 /* Neon instruction encoders, in approximate order of appearance. */
14068 do_neon_dyadic_i_su (void)
14070 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14071 struct neon_type_el et
= neon_check_type (3, rs
,
14072 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14073 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14077 do_neon_dyadic_i64_su (void)
14079 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14080 struct neon_type_el et
= neon_check_type (3, rs
,
14081 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14082 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14086 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14089 unsigned size
= et
.size
>> 3;
14090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14091 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14092 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14093 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14094 inst
.instruction
|= (isquad
!= 0) << 6;
14095 inst
.instruction
|= immbits
<< 16;
14096 inst
.instruction
|= (size
>> 3) << 7;
14097 inst
.instruction
|= (size
& 0x7) << 19;
14099 inst
.instruction
|= (uval
!= 0) << 24;
14101 neon_dp_fixup (&inst
);
14105 do_neon_shl_imm (void)
14107 if (!inst
.operands
[2].isreg
)
14109 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14110 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14111 int imm
= inst
.operands
[2].imm
;
14113 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14114 _("immediate out of range for shift"));
14115 NEON_ENCODE (IMMED
, inst
);
14116 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14120 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14121 struct neon_type_el et
= neon_check_type (3, rs
,
14122 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14125 /* VSHL/VQSHL 3-register variants have syntax such as:
14127 whereas other 3-register operations encoded by neon_three_same have
14130 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14132 tmp
= inst
.operands
[2].reg
;
14133 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14134 inst
.operands
[1].reg
= tmp
;
14135 NEON_ENCODE (INTEGER
, inst
);
14136 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14141 do_neon_qshl_imm (void)
14143 if (!inst
.operands
[2].isreg
)
14145 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14146 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14147 int imm
= inst
.operands
[2].imm
;
14149 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14150 _("immediate out of range for shift"));
14151 NEON_ENCODE (IMMED
, inst
);
14152 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14156 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14157 struct neon_type_el et
= neon_check_type (3, rs
,
14158 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14161 /* See note in do_neon_shl_imm. */
14162 tmp
= inst
.operands
[2].reg
;
14163 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14164 inst
.operands
[1].reg
= tmp
;
14165 NEON_ENCODE (INTEGER
, inst
);
14166 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14171 do_neon_rshl (void)
14173 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14174 struct neon_type_el et
= neon_check_type (3, rs
,
14175 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14178 tmp
= inst
.operands
[2].reg
;
14179 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14180 inst
.operands
[1].reg
= tmp
;
14181 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14185 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14187 /* Handle .I8 pseudo-instructions. */
14190 /* Unfortunately, this will make everything apart from zero out-of-range.
14191 FIXME is this the intended semantics? There doesn't seem much point in
14192 accepting .I8 if so. */
14193 immediate
|= immediate
<< 8;
14199 if (immediate
== (immediate
& 0x000000ff))
14201 *immbits
= immediate
;
14204 else if (immediate
== (immediate
& 0x0000ff00))
14206 *immbits
= immediate
>> 8;
14209 else if (immediate
== (immediate
& 0x00ff0000))
14211 *immbits
= immediate
>> 16;
14214 else if (immediate
== (immediate
& 0xff000000))
14216 *immbits
= immediate
>> 24;
14219 if ((immediate
& 0xffff) != (immediate
>> 16))
14220 goto bad_immediate
;
14221 immediate
&= 0xffff;
14224 if (immediate
== (immediate
& 0x000000ff))
14226 *immbits
= immediate
;
14229 else if (immediate
== (immediate
& 0x0000ff00))
14231 *immbits
= immediate
>> 8;
14236 first_error (_("immediate value out of range"));
14241 do_neon_logic (void)
14243 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14245 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14246 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14247 /* U bit and size field were set as part of the bitmask. */
14248 NEON_ENCODE (INTEGER
, inst
);
14249 neon_three_same (neon_quad (rs
), 0, -1);
14253 const int three_ops_form
= (inst
.operands
[2].present
14254 && !inst
.operands
[2].isreg
);
14255 const int immoperand
= (three_ops_form
? 2 : 1);
14256 enum neon_shape rs
= (three_ops_form
14257 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14258 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14259 struct neon_type_el et
= neon_check_type (2, rs
,
14260 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14261 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14265 if (et
.type
== NT_invtype
)
14268 if (three_ops_form
)
14269 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14270 _("first and second operands shall be the same register"));
14272 NEON_ENCODE (IMMED
, inst
);
14274 immbits
= inst
.operands
[immoperand
].imm
;
14277 /* .i64 is a pseudo-op, so the immediate must be a repeating
14279 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14280 inst
.operands
[immoperand
].reg
: 0))
14282 /* Set immbits to an invalid constant. */
14283 immbits
= 0xdeadbeef;
14290 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14294 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14298 /* Pseudo-instruction for VBIC. */
14299 neon_invert_size (&immbits
, 0, et
.size
);
14300 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14304 /* Pseudo-instruction for VORR. */
14305 neon_invert_size (&immbits
, 0, et
.size
);
14306 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14316 inst
.instruction
|= neon_quad (rs
) << 6;
14317 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14318 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14319 inst
.instruction
|= cmode
<< 8;
14320 neon_write_immbits (immbits
);
14322 neon_dp_fixup (&inst
);
14327 do_neon_bitfield (void)
14329 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14330 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14331 neon_three_same (neon_quad (rs
), 0, -1);
14335 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14338 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14339 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14341 if (et
.type
== NT_float
)
14343 NEON_ENCODE (FLOAT
, inst
);
14344 neon_three_same (neon_quad (rs
), 0, -1);
14348 NEON_ENCODE (INTEGER
, inst
);
14349 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14354 do_neon_dyadic_if_su (void)
14356 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14360 do_neon_dyadic_if_su_d (void)
14362 /* This version only allow D registers, but that constraint is enforced during
14363 operand parsing so we don't need to do anything extra here. */
14364 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14368 do_neon_dyadic_if_i_d (void)
14370 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14371 affected if we specify unsigned args. */
14372 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14375 enum vfp_or_neon_is_neon_bits
14378 NEON_CHECK_ARCH
= 2,
14379 NEON_CHECK_ARCH8
= 4
14382 /* Call this function if an instruction which may have belonged to the VFP or
14383 Neon instruction sets, but turned out to be a Neon instruction (due to the
14384 operand types involved, etc.). We have to check and/or fix-up a couple of
14387 - Make sure the user hasn't attempted to make a Neon instruction
14389 - Alter the value in the condition code field if necessary.
14390 - Make sure that the arch supports Neon instructions.
14392 Which of these operations take place depends on bits from enum
14393 vfp_or_neon_is_neon_bits.
14395 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14396 current instruction's condition is COND_ALWAYS, the condition field is
14397 changed to inst.uncond_value. This is necessary because instructions shared
14398 between VFP and Neon may be conditional for the VFP variants only, and the
14399 unconditional Neon version must have, e.g., 0xF in the condition field. */
14402 vfp_or_neon_is_neon (unsigned check
)
14404 /* Conditions are always legal in Thumb mode (IT blocks). */
14405 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14407 if (inst
.cond
!= COND_ALWAYS
)
14409 first_error (_(BAD_COND
));
14412 if (inst
.uncond_value
!= -1)
14413 inst
.instruction
|= inst
.uncond_value
<< 28;
14416 if ((check
& NEON_CHECK_ARCH
)
14417 && !mark_feature_used (&fpu_neon_ext_v1
))
14419 first_error (_(BAD_FPU
));
14423 if ((check
& NEON_CHECK_ARCH8
)
14424 && !mark_feature_used (&fpu_neon_ext_armv8
))
14426 first_error (_(BAD_FPU
));
14434 do_neon_addsub_if_i (void)
14436 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14439 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14442 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14443 affected if we specify unsigned args. */
14444 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14447 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14449 V<op> A,B (A is operand 0, B is operand 2)
14454 so handle that case specially. */
14457 neon_exchange_operands (void)
14459 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14460 if (inst
.operands
[1].present
)
14462 /* Swap operands[1] and operands[2]. */
14463 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14464 inst
.operands
[1] = inst
.operands
[2];
14465 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14469 inst
.operands
[1] = inst
.operands
[2];
14470 inst
.operands
[2] = inst
.operands
[0];
14475 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14477 if (inst
.operands
[2].isreg
)
14480 neon_exchange_operands ();
14481 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14485 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14486 struct neon_type_el et
= neon_check_type (2, rs
,
14487 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14489 NEON_ENCODE (IMMED
, inst
);
14490 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14491 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14492 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14493 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14494 inst
.instruction
|= neon_quad (rs
) << 6;
14495 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14496 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14498 neon_dp_fixup (&inst
);
14505 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14509 do_neon_cmp_inv (void)
14511 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14517 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14520 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14521 scalars, which are encoded in 5 bits, M : Rm.
14522 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14523 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14527 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14529 unsigned regno
= NEON_SCALAR_REG (scalar
);
14530 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14535 if (regno
> 7 || elno
> 3)
14537 return regno
| (elno
<< 3);
14540 if (regno
> 15 || elno
> 1)
14542 return regno
| (elno
<< 4);
14546 first_error (_("scalar out of range for multiply instruction"));
14552 /* Encode multiply / multiply-accumulate scalar instructions. */
14555 neon_mul_mac (struct neon_type_el et
, int ubit
)
14559 /* Give a more helpful error message if we have an invalid type. */
14560 if (et
.type
== NT_invtype
)
14563 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14568 inst
.instruction
|= LOW4 (scalar
);
14569 inst
.instruction
|= HI1 (scalar
) << 5;
14570 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14571 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14572 inst
.instruction
|= (ubit
!= 0) << 24;
14574 neon_dp_fixup (&inst
);
14578 do_neon_mac_maybe_scalar (void)
14580 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14583 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14586 if (inst
.operands
[2].isscalar
)
14588 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14589 struct neon_type_el et
= neon_check_type (3, rs
,
14590 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14591 NEON_ENCODE (SCALAR
, inst
);
14592 neon_mul_mac (et
, neon_quad (rs
));
14596 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14597 affected if we specify unsigned args. */
14598 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14603 do_neon_fmac (void)
14605 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14608 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14611 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14617 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14618 struct neon_type_el et
= neon_check_type (3, rs
,
14619 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14620 neon_three_same (neon_quad (rs
), 0, et
.size
);
14623 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14624 same types as the MAC equivalents. The polynomial type for this instruction
14625 is encoded the same as the integer type. */
14630 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14633 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14636 if (inst
.operands
[2].isscalar
)
14637 do_neon_mac_maybe_scalar ();
14639 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14643 do_neon_qdmulh (void)
14645 if (inst
.operands
[2].isscalar
)
14647 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14648 struct neon_type_el et
= neon_check_type (3, rs
,
14649 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14650 NEON_ENCODE (SCALAR
, inst
);
14651 neon_mul_mac (et
, neon_quad (rs
));
14655 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14656 struct neon_type_el et
= neon_check_type (3, rs
,
14657 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14658 NEON_ENCODE (INTEGER
, inst
);
14659 /* The U bit (rounding) comes from bit mask. */
14660 neon_three_same (neon_quad (rs
), 0, et
.size
);
14665 do_neon_fcmp_absolute (void)
14667 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14668 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14669 /* Size field comes from bit mask. */
14670 neon_three_same (neon_quad (rs
), 1, -1);
14674 do_neon_fcmp_absolute_inv (void)
14676 neon_exchange_operands ();
14677 do_neon_fcmp_absolute ();
14681 do_neon_step (void)
14683 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14684 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14685 neon_three_same (neon_quad (rs
), 0, -1);
14689 do_neon_abs_neg (void)
14691 enum neon_shape rs
;
14692 struct neon_type_el et
;
14694 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14697 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14700 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14701 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14707 inst
.instruction
|= neon_quad (rs
) << 6;
14708 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14709 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14711 neon_dp_fixup (&inst
);
14717 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14718 struct neon_type_el et
= neon_check_type (2, rs
,
14719 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14720 int imm
= inst
.operands
[2].imm
;
14721 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14722 _("immediate out of range for insert"));
14723 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14729 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14730 struct neon_type_el et
= neon_check_type (2, rs
,
14731 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14732 int imm
= inst
.operands
[2].imm
;
14733 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14734 _("immediate out of range for insert"));
14735 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14739 do_neon_qshlu_imm (void)
14741 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14742 struct neon_type_el et
= neon_check_type (2, rs
,
14743 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14744 int imm
= inst
.operands
[2].imm
;
14745 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14746 _("immediate out of range for shift"));
14747 /* Only encodes the 'U present' variant of the instruction.
14748 In this case, signed types have OP (bit 8) set to 0.
14749 Unsigned types have OP set to 1. */
14750 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14751 /* The rest of the bits are the same as other immediate shifts. */
14752 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14756 do_neon_qmovn (void)
14758 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14759 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14760 /* Saturating move where operands can be signed or unsigned, and the
14761 destination has the same signedness. */
14762 NEON_ENCODE (INTEGER
, inst
);
14763 if (et
.type
== NT_unsigned
)
14764 inst
.instruction
|= 0xc0;
14766 inst
.instruction
|= 0x80;
14767 neon_two_same (0, 1, et
.size
/ 2);
14771 do_neon_qmovun (void)
14773 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14774 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14775 /* Saturating move with unsigned results. Operands must be signed. */
14776 NEON_ENCODE (INTEGER
, inst
);
14777 neon_two_same (0, 1, et
.size
/ 2);
14781 do_neon_rshift_sat_narrow (void)
14783 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14784 or unsigned. If operands are unsigned, results must also be unsigned. */
14785 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14786 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14787 int imm
= inst
.operands
[2].imm
;
14788 /* This gets the bounds check, size encoding and immediate bits calculation
14792 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14793 VQMOVN.I<size> <Dd>, <Qm>. */
14796 inst
.operands
[2].present
= 0;
14797 inst
.instruction
= N_MNEM_vqmovn
;
14802 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14803 _("immediate out of range"));
14804 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14808 do_neon_rshift_sat_narrow_u (void)
14810 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14811 or unsigned. If operands are unsigned, results must also be unsigned. */
14812 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14813 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14814 int imm
= inst
.operands
[2].imm
;
14815 /* This gets the bounds check, size encoding and immediate bits calculation
14819 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14820 VQMOVUN.I<size> <Dd>, <Qm>. */
14823 inst
.operands
[2].present
= 0;
14824 inst
.instruction
= N_MNEM_vqmovun
;
14829 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14830 _("immediate out of range"));
14831 /* FIXME: The manual is kind of unclear about what value U should have in
14832 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14834 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14838 do_neon_movn (void)
14840 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14841 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14842 NEON_ENCODE (INTEGER
, inst
);
14843 neon_two_same (0, 1, et
.size
/ 2);
14847 do_neon_rshift_narrow (void)
14849 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14850 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14851 int imm
= inst
.operands
[2].imm
;
14852 /* This gets the bounds check, size encoding and immediate bits calculation
14856 /* If immediate is zero then we are a pseudo-instruction for
14857 VMOVN.I<size> <Dd>, <Qm> */
14860 inst
.operands
[2].present
= 0;
14861 inst
.instruction
= N_MNEM_vmovn
;
14866 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14867 _("immediate out of range for narrowing operation"));
14868 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14872 do_neon_shll (void)
14874 /* FIXME: Type checking when lengthening. */
14875 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14876 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14877 unsigned imm
= inst
.operands
[2].imm
;
14879 if (imm
== et
.size
)
14881 /* Maximum shift variant. */
14882 NEON_ENCODE (INTEGER
, inst
);
14883 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14884 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14885 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14886 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14887 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14889 neon_dp_fixup (&inst
);
14893 /* A more-specific type check for non-max versions. */
14894 et
= neon_check_type (2, NS_QDI
,
14895 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14896 NEON_ENCODE (IMMED
, inst
);
14897 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14901 /* Check the various types for the VCVT instruction, and return which version
14902 the current instruction is. */
14904 #define CVT_FLAVOUR_VAR \
14905 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14906 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14907 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14908 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14909 /* Half-precision conversions. */ \
14910 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14911 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14912 /* VFP instructions. */ \
14913 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14914 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14915 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14916 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14917 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14918 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14919 /* VFP instructions with bitshift. */ \
14920 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14921 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14922 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14923 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14924 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14925 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14926 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14927 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14929 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14930 neon_cvt_flavour_##C,
14932 /* The different types of conversions we can do. */
14933 enum neon_cvt_flavour
14936 neon_cvt_flavour_invalid
,
14937 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14942 static enum neon_cvt_flavour
14943 get_neon_cvt_flavour (enum neon_shape rs
)
14945 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14946 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14947 if (et.type != NT_invtype) \
14949 inst.error = NULL; \
14950 return (neon_cvt_flavour_##C); \
14953 struct neon_type_el et
;
14954 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14955 || rs
== NS_FF
) ? N_VFP
: 0;
14956 /* The instruction versions which take an immediate take one register
14957 argument, which is extended to the width of the full register. Thus the
14958 "source" and "destination" registers must have the same width. Hack that
14959 here by making the size equal to the key (wider, in this case) operand. */
14960 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14964 return neon_cvt_flavour_invalid
;
14979 /* Neon-syntax VFP conversions. */
14982 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14984 const char *opname
= 0;
14986 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14988 /* Conversions with immediate bitshift. */
14989 const char *enc
[] =
14991 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14997 if (flavour
< (int) ARRAY_SIZE (enc
))
14999 opname
= enc
[flavour
];
15000 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15001 _("operands 0 and 1 must be the same register"));
15002 inst
.operands
[1] = inst
.operands
[2];
15003 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15008 /* Conversions without bitshift. */
15009 const char *enc
[] =
15011 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15017 if (flavour
< (int) ARRAY_SIZE (enc
))
15018 opname
= enc
[flavour
];
15022 do_vfp_nsyn_opcode (opname
);
15026 do_vfp_nsyn_cvtz (void)
15028 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15029 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15030 const char *enc
[] =
15032 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15038 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15039 do_vfp_nsyn_opcode (enc
[flavour
]);
15043 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15044 enum neon_cvt_mode mode
)
15049 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15050 D register operands. */
15051 if (flavour
== neon_cvt_flavour_s32_f64
15052 || flavour
== neon_cvt_flavour_u32_f64
)
15053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15056 set_it_insn_type (OUTSIDE_IT_INSN
);
15060 case neon_cvt_flavour_s32_f64
:
15064 case neon_cvt_flavour_s32_f32
:
15068 case neon_cvt_flavour_u32_f64
:
15072 case neon_cvt_flavour_u32_f32
:
15077 first_error (_("invalid instruction shape"));
15083 case neon_cvt_mode_a
: rm
= 0; break;
15084 case neon_cvt_mode_n
: rm
= 1; break;
15085 case neon_cvt_mode_p
: rm
= 2; break;
15086 case neon_cvt_mode_m
: rm
= 3; break;
15087 default: first_error (_("invalid rounding mode")); return;
15090 NEON_ENCODE (FPV8
, inst
);
15091 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15092 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15093 inst
.instruction
|= sz
<< 8;
15094 inst
.instruction
|= op
<< 7;
15095 inst
.instruction
|= rm
<< 16;
15096 inst
.instruction
|= 0xf0000000;
15097 inst
.is_neon
= TRUE
;
15101 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15103 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15104 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15105 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15107 /* PR11109: Handle round-to-zero for VCVT conversions. */
15108 if (mode
== neon_cvt_mode_z
15109 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15110 && (flavour
== neon_cvt_flavour_s32_f32
15111 || flavour
== neon_cvt_flavour_u32_f32
15112 || flavour
== neon_cvt_flavour_s32_f64
15113 || flavour
== neon_cvt_flavour_u32_f64
)
15114 && (rs
== NS_FD
|| rs
== NS_FF
))
15116 do_vfp_nsyn_cvtz ();
15120 /* VFP rather than Neon conversions. */
15121 if (flavour
>= neon_cvt_flavour_first_fp
)
15123 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15124 do_vfp_nsyn_cvt (rs
, flavour
);
15126 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15137 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15139 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15142 /* Fixed-point conversion with #0 immediate is encoded as an
15143 integer conversion. */
15144 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15146 immbits
= 32 - inst
.operands
[2].imm
;
15147 NEON_ENCODE (IMMED
, inst
);
15148 if (flavour
!= neon_cvt_flavour_invalid
)
15149 inst
.instruction
|= enctab
[flavour
];
15150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15154 inst
.instruction
|= neon_quad (rs
) << 6;
15155 inst
.instruction
|= 1 << 21;
15156 inst
.instruction
|= immbits
<< 16;
15158 neon_dp_fixup (&inst
);
15164 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15166 NEON_ENCODE (FLOAT
, inst
);
15167 set_it_insn_type (OUTSIDE_IT_INSN
);
15169 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15173 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15174 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15175 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15176 inst
.instruction
|= neon_quad (rs
) << 6;
15177 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15178 inst
.instruction
|= mode
<< 8;
15180 inst
.instruction
|= 0xfc000000;
15182 inst
.instruction
|= 0xf0000000;
15188 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15190 NEON_ENCODE (INTEGER
, inst
);
15192 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15195 if (flavour
!= neon_cvt_flavour_invalid
)
15196 inst
.instruction
|= enctab
[flavour
];
15198 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15199 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15200 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15201 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15202 inst
.instruction
|= neon_quad (rs
) << 6;
15203 inst
.instruction
|= 2 << 18;
15205 neon_dp_fixup (&inst
);
15210 /* Half-precision conversions for Advanced SIMD -- neon. */
15215 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15217 as_bad (_("operand size must match register width"));
15222 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15224 as_bad (_("operand size must match register width"));
15229 inst
.instruction
= 0x3b60600;
15231 inst
.instruction
= 0x3b60700;
15233 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15234 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15236 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15237 neon_dp_fixup (&inst
);
15241 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15242 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15243 do_vfp_nsyn_cvt (rs
, flavour
);
15245 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15250 do_neon_cvtr (void)
15252 do_neon_cvt_1 (neon_cvt_mode_x
);
15258 do_neon_cvt_1 (neon_cvt_mode_z
);
15262 do_neon_cvta (void)
15264 do_neon_cvt_1 (neon_cvt_mode_a
);
15268 do_neon_cvtn (void)
15270 do_neon_cvt_1 (neon_cvt_mode_n
);
15274 do_neon_cvtp (void)
15276 do_neon_cvt_1 (neon_cvt_mode_p
);
15280 do_neon_cvtm (void)
15282 do_neon_cvt_1 (neon_cvt_mode_m
);
15286 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15289 mark_feature_used (&fpu_vfp_ext_armv8
);
15291 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15292 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15293 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15294 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15295 inst
.instruction
|= to
? 0x10000 : 0;
15296 inst
.instruction
|= t
? 0x80 : 0;
15297 inst
.instruction
|= is_double
? 0x100 : 0;
15298 do_vfp_cond_or_thumb ();
15302 do_neon_cvttb_1 (bfd_boolean t
)
15304 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15308 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15311 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15313 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15316 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15318 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15320 /* The VCVTB and VCVTT instructions with D-register operands
15321 don't work for SP only targets. */
15322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15326 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15328 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15330 /* The VCVTB and VCVTT instructions with D-register operands
15331 don't work for SP only targets. */
15332 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15336 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15343 do_neon_cvtb (void)
15345 do_neon_cvttb_1 (FALSE
);
15350 do_neon_cvtt (void)
15352 do_neon_cvttb_1 (TRUE
);
15356 neon_move_immediate (void)
15358 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15359 struct neon_type_el et
= neon_check_type (2, rs
,
15360 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15361 unsigned immlo
, immhi
= 0, immbits
;
15362 int op
, cmode
, float_p
;
15364 constraint (et
.type
== NT_invtype
,
15365 _("operand size must be specified for immediate VMOV"));
15367 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15368 op
= (inst
.instruction
& (1 << 5)) != 0;
15370 immlo
= inst
.operands
[1].imm
;
15371 if (inst
.operands
[1].regisimm
)
15372 immhi
= inst
.operands
[1].reg
;
15374 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15375 _("immediate has bits set outside the operand size"));
15377 float_p
= inst
.operands
[1].immisfloat
;
15379 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15380 et
.size
, et
.type
)) == FAIL
)
15382 /* Invert relevant bits only. */
15383 neon_invert_size (&immlo
, &immhi
, et
.size
);
15384 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15385 with one or the other; those cases are caught by
15386 neon_cmode_for_move_imm. */
15388 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15389 &op
, et
.size
, et
.type
)) == FAIL
)
15391 first_error (_("immediate out of range"));
15396 inst
.instruction
&= ~(1 << 5);
15397 inst
.instruction
|= op
<< 5;
15399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15401 inst
.instruction
|= neon_quad (rs
) << 6;
15402 inst
.instruction
|= cmode
<< 8;
15404 neon_write_immbits (immbits
);
15410 if (inst
.operands
[1].isreg
)
15412 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15414 NEON_ENCODE (INTEGER
, inst
);
15415 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15416 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15417 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15418 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15419 inst
.instruction
|= neon_quad (rs
) << 6;
15423 NEON_ENCODE (IMMED
, inst
);
15424 neon_move_immediate ();
15427 neon_dp_fixup (&inst
);
15430 /* Encode instructions of form:
15432 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15433 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15436 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15438 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15439 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15440 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15442 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15443 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15444 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15445 inst
.instruction
|= neon_logbits (size
) << 20;
15447 neon_dp_fixup (&inst
);
15451 do_neon_dyadic_long (void)
15453 /* FIXME: Type checking for lengthening op. */
15454 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15455 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15456 neon_mixed_length (et
, et
.size
);
15460 do_neon_abal (void)
15462 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15463 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15464 neon_mixed_length (et
, et
.size
);
15468 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15470 if (inst
.operands
[2].isscalar
)
15472 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15473 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15474 NEON_ENCODE (SCALAR
, inst
);
15475 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15479 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15480 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15481 NEON_ENCODE (INTEGER
, inst
);
15482 neon_mixed_length (et
, et
.size
);
15487 do_neon_mac_maybe_scalar_long (void)
15489 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15493 do_neon_dyadic_wide (void)
15495 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15496 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15497 neon_mixed_length (et
, et
.size
);
15501 do_neon_dyadic_narrow (void)
15503 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15504 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15505 /* Operand sign is unimportant, and the U bit is part of the opcode,
15506 so force the operand type to integer. */
15507 et
.type
= NT_integer
;
15508 neon_mixed_length (et
, et
.size
/ 2);
15512 do_neon_mul_sat_scalar_long (void)
15514 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15518 do_neon_vmull (void)
15520 if (inst
.operands
[2].isscalar
)
15521 do_neon_mac_maybe_scalar_long ();
15524 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15525 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15527 if (et
.type
== NT_poly
)
15528 NEON_ENCODE (POLY
, inst
);
15530 NEON_ENCODE (INTEGER
, inst
);
15532 /* For polynomial encoding the U bit must be zero, and the size must
15533 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15534 obviously, as 0b10). */
15537 /* Check we're on the correct architecture. */
15538 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15540 _("Instruction form not available on this architecture.");
15545 neon_mixed_length (et
, et
.size
);
15552 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15553 struct neon_type_el et
= neon_check_type (3, rs
,
15554 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15555 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15557 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15558 _("shift out of range"));
15559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15560 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15561 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15562 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15563 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15564 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15565 inst
.instruction
|= neon_quad (rs
) << 6;
15566 inst
.instruction
|= imm
<< 8;
15568 neon_dp_fixup (&inst
);
15574 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15575 struct neon_type_el et
= neon_check_type (2, rs
,
15576 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15577 unsigned op
= (inst
.instruction
>> 7) & 3;
15578 /* N (width of reversed regions) is encoded as part of the bitmask. We
15579 extract it here to check the elements to be reversed are smaller.
15580 Otherwise we'd get a reserved instruction. */
15581 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15582 gas_assert (elsize
!= 0);
15583 constraint (et
.size
>= elsize
,
15584 _("elements must be smaller than reversal region"));
15585 neon_two_same (neon_quad (rs
), 1, et
.size
);
15591 if (inst
.operands
[1].isscalar
)
15593 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15594 struct neon_type_el et
= neon_check_type (2, rs
,
15595 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15596 unsigned sizebits
= et
.size
>> 3;
15597 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15598 int logsize
= neon_logbits (et
.size
);
15599 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15601 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15604 NEON_ENCODE (SCALAR
, inst
);
15605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15607 inst
.instruction
|= LOW4 (dm
);
15608 inst
.instruction
|= HI1 (dm
) << 5;
15609 inst
.instruction
|= neon_quad (rs
) << 6;
15610 inst
.instruction
|= x
<< 17;
15611 inst
.instruction
|= sizebits
<< 16;
15613 neon_dp_fixup (&inst
);
15617 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15618 struct neon_type_el et
= neon_check_type (2, rs
,
15619 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15620 /* Duplicate ARM register to lanes of vector. */
15621 NEON_ENCODE (ARMREG
, inst
);
15624 case 8: inst
.instruction
|= 0x400000; break;
15625 case 16: inst
.instruction
|= 0x000020; break;
15626 case 32: inst
.instruction
|= 0x000000; break;
15629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15630 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15631 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15632 inst
.instruction
|= neon_quad (rs
) << 21;
15633 /* The encoding for this instruction is identical for the ARM and Thumb
15634 variants, except for the condition field. */
15635 do_vfp_cond_or_thumb ();
15639 /* VMOV has particularly many variations. It can be one of:
15640 0. VMOV<c><q> <Qd>, <Qm>
15641 1. VMOV<c><q> <Dd>, <Dm>
15642 (Register operations, which are VORR with Rm = Rn.)
15643 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15644 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15646 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15647 (ARM register to scalar.)
15648 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15649 (Two ARM registers to vector.)
15650 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15651 (Scalar to ARM register.)
15652 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15653 (Vector to two ARM registers.)
15654 8. VMOV.F32 <Sd>, <Sm>
15655 9. VMOV.F64 <Dd>, <Dm>
15656 (VFP register moves.)
15657 10. VMOV.F32 <Sd>, #imm
15658 11. VMOV.F64 <Dd>, #imm
15659 (VFP float immediate load.)
15660 12. VMOV <Rd>, <Sm>
15661 (VFP single to ARM reg.)
15662 13. VMOV <Sd>, <Rm>
15663 (ARM reg to VFP single.)
15664 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15665 (Two ARM regs to two VFP singles.)
15666 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15667 (Two VFP singles to two ARM regs.)
15669 These cases can be disambiguated using neon_select_shape, except cases 1/9
15670 and 3/11 which depend on the operand type too.
15672 All the encoded bits are hardcoded by this function.
15674 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15675 Cases 5, 7 may be used with VFPv2 and above.
15677 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15678 can specify a type where it doesn't make sense to, and is ignored). */
15683 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15684 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15686 struct neon_type_el et
;
15687 const char *ldconst
= 0;
15691 case NS_DD
: /* case 1/9. */
15692 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15693 /* It is not an error here if no type is given. */
15695 if (et
.type
== NT_float
&& et
.size
== 64)
15697 do_vfp_nsyn_opcode ("fcpyd");
15700 /* fall through. */
15702 case NS_QQ
: /* case 0/1. */
15704 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15706 /* The architecture manual I have doesn't explicitly state which
15707 value the U bit should have for register->register moves, but
15708 the equivalent VORR instruction has U = 0, so do that. */
15709 inst
.instruction
= 0x0200110;
15710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15716 inst
.instruction
|= neon_quad (rs
) << 6;
15718 neon_dp_fixup (&inst
);
15722 case NS_DI
: /* case 3/11. */
15723 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15725 if (et
.type
== NT_float
&& et
.size
== 64)
15727 /* case 11 (fconstd). */
15728 ldconst
= "fconstd";
15729 goto encode_fconstd
;
15731 /* fall through. */
15733 case NS_QI
: /* case 2/3. */
15734 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15736 inst
.instruction
= 0x0800010;
15737 neon_move_immediate ();
15738 neon_dp_fixup (&inst
);
15741 case NS_SR
: /* case 4. */
15743 unsigned bcdebits
= 0;
15745 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15746 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15748 /* .<size> is optional here, defaulting to .32. */
15749 if (inst
.vectype
.elems
== 0
15750 && inst
.operands
[0].vectype
.type
== NT_invtype
15751 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15753 inst
.vectype
.el
[0].type
= NT_untyped
;
15754 inst
.vectype
.el
[0].size
= 32;
15755 inst
.vectype
.elems
= 1;
15758 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15759 logsize
= neon_logbits (et
.size
);
15761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15763 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15764 && et
.size
!= 32, _(BAD_FPU
));
15765 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15766 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15770 case 8: bcdebits
= 0x8; break;
15771 case 16: bcdebits
= 0x1; break;
15772 case 32: bcdebits
= 0x0; break;
15776 bcdebits
|= x
<< logsize
;
15778 inst
.instruction
= 0xe000b10;
15779 do_vfp_cond_or_thumb ();
15780 inst
.instruction
|= LOW4 (dn
) << 16;
15781 inst
.instruction
|= HI1 (dn
) << 7;
15782 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15783 inst
.instruction
|= (bcdebits
& 3) << 5;
15784 inst
.instruction
|= (bcdebits
>> 2) << 21;
15788 case NS_DRR
: /* case 5 (fmdrr). */
15789 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15792 inst
.instruction
= 0xc400b10;
15793 do_vfp_cond_or_thumb ();
15794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15796 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15797 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15800 case NS_RS
: /* case 6. */
15803 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15804 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15805 unsigned abcdebits
= 0;
15807 /* .<dt> is optional here, defaulting to .32. */
15808 if (inst
.vectype
.elems
== 0
15809 && inst
.operands
[0].vectype
.type
== NT_invtype
15810 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15812 inst
.vectype
.el
[0].type
= NT_untyped
;
15813 inst
.vectype
.el
[0].size
= 32;
15814 inst
.vectype
.elems
= 1;
15817 et
= neon_check_type (2, NS_NULL
,
15818 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15819 logsize
= neon_logbits (et
.size
);
15821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15823 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15824 && et
.size
!= 32, _(BAD_FPU
));
15825 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15826 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15830 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15831 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15832 case 32: abcdebits
= 0x00; break;
15836 abcdebits
|= x
<< logsize
;
15837 inst
.instruction
= 0xe100b10;
15838 do_vfp_cond_or_thumb ();
15839 inst
.instruction
|= LOW4 (dn
) << 16;
15840 inst
.instruction
|= HI1 (dn
) << 7;
15841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15842 inst
.instruction
|= (abcdebits
& 3) << 5;
15843 inst
.instruction
|= (abcdebits
>> 2) << 21;
15847 case NS_RRD
: /* case 7 (fmrrd). */
15848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15851 inst
.instruction
= 0xc500b10;
15852 do_vfp_cond_or_thumb ();
15853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15854 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15855 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15856 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15859 case NS_FF
: /* case 8 (fcpys). */
15860 do_vfp_nsyn_opcode ("fcpys");
15863 case NS_FI
: /* case 10 (fconsts). */
15864 ldconst
= "fconsts";
15866 if (is_quarter_float (inst
.operands
[1].imm
))
15868 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15869 do_vfp_nsyn_opcode (ldconst
);
15872 first_error (_("immediate out of range"));
15875 case NS_RF
: /* case 12 (fmrs). */
15876 do_vfp_nsyn_opcode ("fmrs");
15879 case NS_FR
: /* case 13 (fmsr). */
15880 do_vfp_nsyn_opcode ("fmsr");
15883 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15884 (one of which is a list), but we have parsed four. Do some fiddling to
15885 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15887 case NS_RRFF
: /* case 14 (fmrrs). */
15888 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15889 _("VFP registers must be adjacent"));
15890 inst
.operands
[2].imm
= 2;
15891 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15892 do_vfp_nsyn_opcode ("fmrrs");
15895 case NS_FFRR
: /* case 15 (fmsrr). */
15896 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15897 _("VFP registers must be adjacent"));
15898 inst
.operands
[1] = inst
.operands
[2];
15899 inst
.operands
[2] = inst
.operands
[3];
15900 inst
.operands
[0].imm
= 2;
15901 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15902 do_vfp_nsyn_opcode ("fmsrr");
15906 /* neon_select_shape has determined that the instruction
15907 shape is wrong and has already set the error message. */
15916 do_neon_rshift_round_imm (void)
15918 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15919 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15920 int imm
= inst
.operands
[2].imm
;
15922 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15925 inst
.operands
[2].present
= 0;
15930 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15931 _("immediate out of range for shift"));
15932 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15937 do_neon_movl (void)
15939 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15940 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15941 unsigned sizebits
= et
.size
>> 3;
15942 inst
.instruction
|= sizebits
<< 19;
15943 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15949 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15950 struct neon_type_el et
= neon_check_type (2, rs
,
15951 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15952 NEON_ENCODE (INTEGER
, inst
);
15953 neon_two_same (neon_quad (rs
), 1, et
.size
);
15957 do_neon_zip_uzp (void)
15959 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15960 struct neon_type_el et
= neon_check_type (2, rs
,
15961 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15962 if (rs
== NS_DD
&& et
.size
== 32)
15964 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15965 inst
.instruction
= N_MNEM_vtrn
;
15969 neon_two_same (neon_quad (rs
), 1, et
.size
);
15973 do_neon_sat_abs_neg (void)
15975 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15976 struct neon_type_el et
= neon_check_type (2, rs
,
15977 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15978 neon_two_same (neon_quad (rs
), 1, et
.size
);
15982 do_neon_pair_long (void)
15984 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15985 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15986 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15987 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15988 neon_two_same (neon_quad (rs
), 1, et
.size
);
15992 do_neon_recip_est (void)
15994 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15995 struct neon_type_el et
= neon_check_type (2, rs
,
15996 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15997 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15998 neon_two_same (neon_quad (rs
), 1, et
.size
);
16004 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16005 struct neon_type_el et
= neon_check_type (2, rs
,
16006 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16007 neon_two_same (neon_quad (rs
), 1, et
.size
);
16013 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16014 struct neon_type_el et
= neon_check_type (2, rs
,
16015 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16016 neon_two_same (neon_quad (rs
), 1, et
.size
);
16022 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16023 struct neon_type_el et
= neon_check_type (2, rs
,
16024 N_EQK
| N_INT
, N_8
| N_KEY
);
16025 neon_two_same (neon_quad (rs
), 1, et
.size
);
16031 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16032 neon_two_same (neon_quad (rs
), 1, -1);
16036 do_neon_tbl_tbx (void)
16038 unsigned listlenbits
;
16039 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16041 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16043 first_error (_("bad list length for table lookup"));
16047 listlenbits
= inst
.operands
[1].imm
- 1;
16048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16049 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16050 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16051 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16052 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16053 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16054 inst
.instruction
|= listlenbits
<< 8;
16056 neon_dp_fixup (&inst
);
16060 do_neon_ldm_stm (void)
16062 /* P, U and L bits are part of bitmask. */
16063 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16064 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16066 if (inst
.operands
[1].issingle
)
16068 do_vfp_nsyn_ldm_stm (is_dbmode
);
16072 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16073 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16075 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16076 _("register list must contain at least 1 and at most 16 "
16079 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16080 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16081 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16082 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16084 inst
.instruction
|= offsetbits
;
16086 do_vfp_cond_or_thumb ();
16090 do_neon_ldr_str (void)
16092 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16094 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16095 And is UNPREDICTABLE in thumb mode. */
16097 && inst
.operands
[1].reg
== REG_PC
16098 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16101 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16102 else if (warn_on_deprecated
)
16103 as_tsktsk (_("Use of PC here is deprecated"));
16106 if (inst
.operands
[0].issingle
)
16109 do_vfp_nsyn_opcode ("flds");
16111 do_vfp_nsyn_opcode ("fsts");
16116 do_vfp_nsyn_opcode ("fldd");
16118 do_vfp_nsyn_opcode ("fstd");
16122 /* "interleave" version also handles non-interleaving register VLD1/VST1
16126 do_neon_ld_st_interleave (void)
16128 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16129 N_8
| N_16
| N_32
| N_64
);
16130 unsigned alignbits
= 0;
16132 /* The bits in this table go:
16133 0: register stride of one (0) or two (1)
16134 1,2: register list length, minus one (1, 2, 3, 4).
16135 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16136 We use -1 for invalid entries. */
16137 const int typetable
[] =
16139 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16140 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16141 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16142 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16146 if (et
.type
== NT_invtype
)
16149 if (inst
.operands
[1].immisalign
)
16150 switch (inst
.operands
[1].imm
>> 8)
16152 case 64: alignbits
= 1; break;
16154 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16155 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16156 goto bad_alignment
;
16160 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16161 goto bad_alignment
;
16166 first_error (_("bad alignment"));
16170 inst
.instruction
|= alignbits
<< 4;
16171 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16173 /* Bits [4:6] of the immediate in a list specifier encode register stride
16174 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16175 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16176 up the right value for "type" in a table based on this value and the given
16177 list style, then stick it back. */
16178 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16179 | (((inst
.instruction
>> 8) & 3) << 3);
16181 typebits
= typetable
[idx
];
16183 constraint (typebits
== -1, _("bad list type for instruction"));
16184 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16185 _("bad element type for instruction"));
16187 inst
.instruction
&= ~0xf00;
16188 inst
.instruction
|= typebits
<< 8;
16191 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16192 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16193 otherwise. The variable arguments are a list of pairs of legal (size, align)
16194 values, terminated with -1. */
16197 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16200 int result
= FAIL
, thissize
, thisalign
;
16202 if (!inst
.operands
[1].immisalign
)
16208 va_start (ap
, do_align
);
16212 thissize
= va_arg (ap
, int);
16213 if (thissize
== -1)
16215 thisalign
= va_arg (ap
, int);
16217 if (size
== thissize
&& align
== thisalign
)
16220 while (result
!= SUCCESS
);
16224 if (result
== SUCCESS
)
16227 first_error (_("unsupported alignment for instruction"));
16233 do_neon_ld_st_lane (void)
16235 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16236 int align_good
, do_align
= 0;
16237 int logsize
= neon_logbits (et
.size
);
16238 int align
= inst
.operands
[1].imm
>> 8;
16239 int n
= (inst
.instruction
>> 8) & 3;
16240 int max_el
= 64 / et
.size
;
16242 if (et
.type
== NT_invtype
)
16245 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16246 _("bad list length"));
16247 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16248 _("scalar index out of range"));
16249 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16251 _("stride of 2 unavailable when element size is 8"));
16255 case 0: /* VLD1 / VST1. */
16256 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16258 if (align_good
== FAIL
)
16262 unsigned alignbits
= 0;
16265 case 16: alignbits
= 0x1; break;
16266 case 32: alignbits
= 0x3; break;
16269 inst
.instruction
|= alignbits
<< 4;
16273 case 1: /* VLD2 / VST2. */
16274 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16276 if (align_good
== FAIL
)
16279 inst
.instruction
|= 1 << 4;
16282 case 2: /* VLD3 / VST3. */
16283 constraint (inst
.operands
[1].immisalign
,
16284 _("can't use alignment with this instruction"));
16287 case 3: /* VLD4 / VST4. */
16288 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16289 16, 64, 32, 64, 32, 128, -1);
16290 if (align_good
== FAIL
)
16294 unsigned alignbits
= 0;
16297 case 8: alignbits
= 0x1; break;
16298 case 16: alignbits
= 0x1; break;
16299 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16302 inst
.instruction
|= alignbits
<< 4;
16309 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16310 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16311 inst
.instruction
|= 1 << (4 + logsize
);
16313 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16314 inst
.instruction
|= logsize
<< 10;
16317 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16320 do_neon_ld_dup (void)
16322 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16323 int align_good
, do_align
= 0;
16325 if (et
.type
== NT_invtype
)
16328 switch ((inst
.instruction
>> 8) & 3)
16330 case 0: /* VLD1. */
16331 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16332 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16333 &do_align
, 16, 16, 32, 32, -1);
16334 if (align_good
== FAIL
)
16336 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16339 case 2: inst
.instruction
|= 1 << 5; break;
16340 default: first_error (_("bad list length")); return;
16342 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16345 case 1: /* VLD2. */
16346 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16347 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16348 if (align_good
== FAIL
)
16350 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16351 _("bad list length"));
16352 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16353 inst
.instruction
|= 1 << 5;
16354 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16357 case 2: /* VLD3. */
16358 constraint (inst
.operands
[1].immisalign
,
16359 _("can't use alignment with this instruction"));
16360 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16361 _("bad list length"));
16362 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16363 inst
.instruction
|= 1 << 5;
16364 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16367 case 3: /* VLD4. */
16369 int align
= inst
.operands
[1].imm
>> 8;
16370 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16371 16, 64, 32, 64, 32, 128, -1);
16372 if (align_good
== FAIL
)
16374 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16375 _("bad list length"));
16376 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16377 inst
.instruction
|= 1 << 5;
16378 if (et
.size
== 32 && align
== 128)
16379 inst
.instruction
|= 0x3 << 6;
16381 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16388 inst
.instruction
|= do_align
<< 4;
16391 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16392 apart from bits [11:4]. */
16395 do_neon_ldx_stx (void)
16397 if (inst
.operands
[1].isreg
)
16398 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16400 switch (NEON_LANE (inst
.operands
[0].imm
))
16402 case NEON_INTERLEAVE_LANES
:
16403 NEON_ENCODE (INTERLV
, inst
);
16404 do_neon_ld_st_interleave ();
16407 case NEON_ALL_LANES
:
16408 NEON_ENCODE (DUP
, inst
);
16409 if (inst
.instruction
== N_INV
)
16411 first_error ("only loads support such operands");
16418 NEON_ENCODE (LANE
, inst
);
16419 do_neon_ld_st_lane ();
16422 /* L bit comes from bit mask. */
16423 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16424 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16425 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16427 if (inst
.operands
[1].postind
)
16429 int postreg
= inst
.operands
[1].imm
& 0xf;
16430 constraint (!inst
.operands
[1].immisreg
,
16431 _("post-index must be a register"));
16432 constraint (postreg
== 0xd || postreg
== 0xf,
16433 _("bad register for post-index"));
16434 inst
.instruction
|= postreg
;
16438 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16439 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16440 || inst
.reloc
.exp
.X_add_number
!= 0,
16443 if (inst
.operands
[1].writeback
)
16445 inst
.instruction
|= 0xd;
16448 inst
.instruction
|= 0xf;
16452 inst
.instruction
|= 0xf9000000;
16454 inst
.instruction
|= 0xf4000000;
16459 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16461 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16462 D register operands. */
16463 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16467 NEON_ENCODE (FPV8
, inst
);
16470 do_vfp_sp_dyadic ();
16472 do_vfp_dp_rd_rn_rm ();
16475 inst
.instruction
|= 0x100;
16477 inst
.instruction
|= 0xf0000000;
16483 set_it_insn_type (OUTSIDE_IT_INSN
);
16485 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16486 first_error (_("invalid instruction shape"));
16492 set_it_insn_type (OUTSIDE_IT_INSN
);
16494 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16497 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16500 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16504 do_vrint_1 (enum neon_cvt_mode mode
)
16506 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16507 struct neon_type_el et
;
16512 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16513 D register operands. */
16514 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16518 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16519 if (et
.type
!= NT_invtype
)
16521 /* VFP encodings. */
16522 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16523 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16524 set_it_insn_type (OUTSIDE_IT_INSN
);
16526 NEON_ENCODE (FPV8
, inst
);
16528 do_vfp_sp_monadic ();
16530 do_vfp_dp_rd_rm ();
16534 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16535 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16536 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16537 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16538 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16539 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16540 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16544 inst
.instruction
|= (rs
== NS_DD
) << 8;
16545 do_vfp_cond_or_thumb ();
16549 /* Neon encodings (or something broken...). */
16551 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16553 if (et
.type
== NT_invtype
)
16556 set_it_insn_type (OUTSIDE_IT_INSN
);
16557 NEON_ENCODE (FLOAT
, inst
);
16559 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16566 inst
.instruction
|= neon_quad (rs
) << 6;
16569 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16570 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16571 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16572 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16573 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16574 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16575 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16580 inst
.instruction
|= 0xfc000000;
16582 inst
.instruction
|= 0xf0000000;
16589 do_vrint_1 (neon_cvt_mode_x
);
16595 do_vrint_1 (neon_cvt_mode_z
);
16601 do_vrint_1 (neon_cvt_mode_r
);
16607 do_vrint_1 (neon_cvt_mode_a
);
16613 do_vrint_1 (neon_cvt_mode_n
);
16619 do_vrint_1 (neon_cvt_mode_p
);
16625 do_vrint_1 (neon_cvt_mode_m
);
16628 /* Crypto v1 instructions. */
16630 do_crypto_2op_1 (unsigned elttype
, int op
)
16632 set_it_insn_type (OUTSIDE_IT_INSN
);
16634 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16640 NEON_ENCODE (INTEGER
, inst
);
16641 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16642 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16643 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16644 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16646 inst
.instruction
|= op
<< 6;
16649 inst
.instruction
|= 0xfc000000;
16651 inst
.instruction
|= 0xf0000000;
16655 do_crypto_3op_1 (int u
, int op
)
16657 set_it_insn_type (OUTSIDE_IT_INSN
);
16659 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16660 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16665 NEON_ENCODE (INTEGER
, inst
);
16666 neon_three_same (1, u
, 8 << op
);
16672 do_crypto_2op_1 (N_8
, 0);
16678 do_crypto_2op_1 (N_8
, 1);
16684 do_crypto_2op_1 (N_8
, 2);
16690 do_crypto_2op_1 (N_8
, 3);
16696 do_crypto_3op_1 (0, 0);
16702 do_crypto_3op_1 (0, 1);
16708 do_crypto_3op_1 (0, 2);
16714 do_crypto_3op_1 (0, 3);
16720 do_crypto_3op_1 (1, 0);
16726 do_crypto_3op_1 (1, 1);
16730 do_sha256su1 (void)
16732 do_crypto_3op_1 (1, 2);
16738 do_crypto_2op_1 (N_32
, -1);
16744 do_crypto_2op_1 (N_32
, 0);
16748 do_sha256su0 (void)
16750 do_crypto_2op_1 (N_32
, 1);
16754 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16756 unsigned int Rd
= inst
.operands
[0].reg
;
16757 unsigned int Rn
= inst
.operands
[1].reg
;
16758 unsigned int Rm
= inst
.operands
[2].reg
;
16760 set_it_insn_type (OUTSIDE_IT_INSN
);
16761 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16762 inst
.instruction
|= LOW4 (Rn
) << 16;
16763 inst
.instruction
|= LOW4 (Rm
);
16764 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16765 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16767 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16768 as_warn (UNPRED_REG ("r15"));
16769 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16770 as_warn (UNPRED_REG ("r13"));
16810 /* Overall per-instruction processing. */
16812 /* We need to be able to fix up arbitrary expressions in some statements.
16813 This is so that we can handle symbols that are an arbitrary distance from
16814 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16815 which returns part of an address in a form which will be valid for
16816 a data instruction. We do this by pushing the expression into a symbol
16817 in the expr_section, and creating a fix for that. */
16820 fix_new_arm (fragS
* frag
,
16834 /* Create an absolute valued symbol, so we have something to
16835 refer to in the object file. Unfortunately for us, gas's
16836 generic expression parsing will already have folded out
16837 any use of .set foo/.type foo %function that may have
16838 been used to set type information of the target location,
16839 that's being specified symbolically. We have to presume
16840 the user knows what they are doing. */
16844 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16846 symbol
= symbol_find_or_make (name
);
16847 S_SET_SEGMENT (symbol
, absolute_section
);
16848 symbol_set_frag (symbol
, &zero_address_frag
);
16849 S_SET_VALUE (symbol
, exp
->X_add_number
);
16850 exp
->X_op
= O_symbol
;
16851 exp
->X_add_symbol
= symbol
;
16852 exp
->X_add_number
= 0;
16858 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16859 (enum bfd_reloc_code_real
) reloc
);
16863 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16864 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16868 /* Mark whether the fix is to a THUMB instruction, or an ARM
16870 new_fix
->tc_fix_data
= thumb_mode
;
16873 /* Create a frg for an instruction requiring relaxation. */
16875 output_relax_insn (void)
16881 /* The size of the instruction is unknown, so tie the debug info to the
16882 start of the instruction. */
16883 dwarf2_emit_insn (0);
16885 switch (inst
.reloc
.exp
.X_op
)
16888 sym
= inst
.reloc
.exp
.X_add_symbol
;
16889 offset
= inst
.reloc
.exp
.X_add_number
;
16893 offset
= inst
.reloc
.exp
.X_add_number
;
16896 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16900 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16901 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16902 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16905 /* Write a 32-bit thumb instruction to buf. */
16907 put_thumb32_insn (char * buf
, unsigned long insn
)
16909 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16910 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16914 output_inst (const char * str
)
16920 as_bad ("%s -- `%s'", inst
.error
, str
);
16925 output_relax_insn ();
16928 if (inst
.size
== 0)
16931 to
= frag_more (inst
.size
);
16932 /* PR 9814: Record the thumb mode into the current frag so that we know
16933 what type of NOP padding to use, if necessary. We override any previous
16934 setting so that if the mode has changed then the NOPS that we use will
16935 match the encoding of the last instruction in the frag. */
16936 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16938 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16940 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16941 put_thumb32_insn (to
, inst
.instruction
);
16943 else if (inst
.size
> INSN_SIZE
)
16945 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16946 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16947 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16950 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16952 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16953 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16954 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16957 dwarf2_emit_insn (inst
.size
);
16961 output_it_inst (int cond
, int mask
, char * to
)
16963 unsigned long instruction
= 0xbf00;
16966 instruction
|= mask
;
16967 instruction
|= cond
<< 4;
16971 to
= frag_more (2);
16973 dwarf2_emit_insn (2);
16977 md_number_to_chars (to
, instruction
, 2);
16982 /* Tag values used in struct asm_opcode's tag field. */
16985 OT_unconditional
, /* Instruction cannot be conditionalized.
16986 The ARM condition field is still 0xE. */
16987 OT_unconditionalF
, /* Instruction cannot be conditionalized
16988 and carries 0xF in its ARM condition field. */
16989 OT_csuffix
, /* Instruction takes a conditional suffix. */
16990 OT_csuffixF
, /* Some forms of the instruction take a conditional
16991 suffix, others place 0xF where the condition field
16993 OT_cinfix3
, /* Instruction takes a conditional infix,
16994 beginning at character index 3. (In
16995 unified mode, it becomes a suffix.) */
16996 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16997 tsts, cmps, cmns, and teqs. */
16998 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16999 character index 3, even in unified mode. Used for
17000 legacy instructions where suffix and infix forms
17001 may be ambiguous. */
17002 OT_csuf_or_in3
, /* Instruction takes either a conditional
17003 suffix or an infix at character index 3. */
17004 OT_odd_infix_unc
, /* This is the unconditional variant of an
17005 instruction that takes a conditional infix
17006 at an unusual position. In unified mode,
17007 this variant will accept a suffix. */
17008 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17009 are the conditional variants of instructions that
17010 take conditional infixes in unusual positions.
17011 The infix appears at character index
17012 (tag - OT_odd_infix_0). These are not accepted
17013 in unified mode. */
17016 /* Subroutine of md_assemble, responsible for looking up the primary
17017 opcode from the mnemonic the user wrote. STR points to the
17018 beginning of the mnemonic.
17020 This is not simply a hash table lookup, because of conditional
17021 variants. Most instructions have conditional variants, which are
17022 expressed with a _conditional affix_ to the mnemonic. If we were
17023 to encode each conditional variant as a literal string in the opcode
17024 table, it would have approximately 20,000 entries.
17026 Most mnemonics take this affix as a suffix, and in unified syntax,
17027 'most' is upgraded to 'all'. However, in the divided syntax, some
17028 instructions take the affix as an infix, notably the s-variants of
17029 the arithmetic instructions. Of those instructions, all but six
17030 have the infix appear after the third character of the mnemonic.
17032 Accordingly, the algorithm for looking up primary opcodes given
17035 1. Look up the identifier in the opcode table.
17036 If we find a match, go to step U.
17038 2. Look up the last two characters of the identifier in the
17039 conditions table. If we find a match, look up the first N-2
17040 characters of the identifier in the opcode table. If we
17041 find a match, go to step CE.
17043 3. Look up the fourth and fifth characters of the identifier in
17044 the conditions table. If we find a match, extract those
17045 characters from the identifier, and look up the remaining
17046 characters in the opcode table. If we find a match, go
17051 U. Examine the tag field of the opcode structure, in case this is
17052 one of the six instructions with its conditional infix in an
17053 unusual place. If it is, the tag tells us where to find the
17054 infix; look it up in the conditions table and set inst.cond
17055 accordingly. Otherwise, this is an unconditional instruction.
17056 Again set inst.cond accordingly. Return the opcode structure.
17058 CE. Examine the tag field to make sure this is an instruction that
17059 should receive a conditional suffix. If it is not, fail.
17060 Otherwise, set inst.cond from the suffix we already looked up,
17061 and return the opcode structure.
17063 CM. Examine the tag field to make sure this is an instruction that
17064 should receive a conditional infix after the third character.
17065 If it is not, fail. Otherwise, undo the edits to the current
17066 line of input and proceed as for case CE. */
17068 static const struct asm_opcode
*
17069 opcode_lookup (char **str
)
17073 const struct asm_opcode
*opcode
;
17074 const struct asm_cond
*cond
;
17077 /* Scan up to the end of the mnemonic, which must end in white space,
17078 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17079 for (base
= end
= *str
; *end
!= '\0'; end
++)
17080 if (*end
== ' ' || *end
== '.')
17086 /* Handle a possible width suffix and/or Neon type suffix. */
17091 /* The .w and .n suffixes are only valid if the unified syntax is in
17093 if (unified_syntax
&& end
[1] == 'w')
17095 else if (unified_syntax
&& end
[1] == 'n')
17100 inst
.vectype
.elems
= 0;
17102 *str
= end
+ offset
;
17104 if (end
[offset
] == '.')
17106 /* See if we have a Neon type suffix (possible in either unified or
17107 non-unified ARM syntax mode). */
17108 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17111 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17117 /* Look for unaffixed or special-case affixed mnemonic. */
17118 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17123 if (opcode
->tag
< OT_odd_infix_0
)
17125 inst
.cond
= COND_ALWAYS
;
17129 if (warn_on_deprecated
&& unified_syntax
)
17130 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17131 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17132 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17135 inst
.cond
= cond
->value
;
17139 /* Cannot have a conditional suffix on a mnemonic of less than two
17141 if (end
- base
< 3)
17144 /* Look for suffixed mnemonic. */
17146 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17147 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17149 if (opcode
&& cond
)
17152 switch (opcode
->tag
)
17154 case OT_cinfix3_legacy
:
17155 /* Ignore conditional suffixes matched on infix only mnemonics. */
17159 case OT_cinfix3_deprecated
:
17160 case OT_odd_infix_unc
:
17161 if (!unified_syntax
)
17163 /* else fall through */
17167 case OT_csuf_or_in3
:
17168 inst
.cond
= cond
->value
;
17171 case OT_unconditional
:
17172 case OT_unconditionalF
:
17174 inst
.cond
= cond
->value
;
17177 /* Delayed diagnostic. */
17178 inst
.error
= BAD_COND
;
17179 inst
.cond
= COND_ALWAYS
;
17188 /* Cannot have a usual-position infix on a mnemonic of less than
17189 six characters (five would be a suffix). */
17190 if (end
- base
< 6)
17193 /* Look for infixed mnemonic in the usual position. */
17195 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17199 memcpy (save
, affix
, 2);
17200 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17201 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17203 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17204 memcpy (affix
, save
, 2);
17207 && (opcode
->tag
== OT_cinfix3
17208 || opcode
->tag
== OT_cinfix3_deprecated
17209 || opcode
->tag
== OT_csuf_or_in3
17210 || opcode
->tag
== OT_cinfix3_legacy
))
17213 if (warn_on_deprecated
&& unified_syntax
17214 && (opcode
->tag
== OT_cinfix3
17215 || opcode
->tag
== OT_cinfix3_deprecated
))
17216 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17218 inst
.cond
= cond
->value
;
17225 /* This function generates an initial IT instruction, leaving its block
17226 virtually open for the new instructions. Eventually,
17227 the mask will be updated by now_it_add_mask () each time
17228 a new instruction needs to be included in the IT block.
17229 Finally, the block is closed with close_automatic_it_block ().
17230 The block closure can be requested either from md_assemble (),
17231 a tencode (), or due to a label hook. */
17234 new_automatic_it_block (int cond
)
17236 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17237 now_it
.mask
= 0x18;
17239 now_it
.block_length
= 1;
17240 mapping_state (MAP_THUMB
);
17241 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17242 now_it
.warn_deprecated
= FALSE
;
17243 now_it
.insn_cond
= TRUE
;
17246 /* Close an automatic IT block.
17247 See comments in new_automatic_it_block (). */
17250 close_automatic_it_block (void)
17252 now_it
.mask
= 0x10;
17253 now_it
.block_length
= 0;
17256 /* Update the mask of the current automatically-generated IT
17257 instruction. See comments in new_automatic_it_block (). */
17260 now_it_add_mask (int cond
)
17262 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17263 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17264 | ((bitvalue) << (nbit)))
17265 const int resulting_bit
= (cond
& 1);
17267 now_it
.mask
&= 0xf;
17268 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17270 (5 - now_it
.block_length
));
17271 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17273 ((5 - now_it
.block_length
) - 1) );
17274 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17277 #undef SET_BIT_VALUE
17280 /* The IT blocks handling machinery is accessed through the these functions:
17281 it_fsm_pre_encode () from md_assemble ()
17282 set_it_insn_type () optional, from the tencode functions
17283 set_it_insn_type_last () ditto
17284 in_it_block () ditto
17285 it_fsm_post_encode () from md_assemble ()
17286 force_automatic_it_block_close () from label habdling functions
17289 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17290 initializing the IT insn type with a generic initial value depending
17291 on the inst.condition.
17292 2) During the tencode function, two things may happen:
17293 a) The tencode function overrides the IT insn type by
17294 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17295 b) The tencode function queries the IT block state by
17296 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17298 Both set_it_insn_type and in_it_block run the internal FSM state
17299 handling function (handle_it_state), because: a) setting the IT insn
17300 type may incur in an invalid state (exiting the function),
17301 and b) querying the state requires the FSM to be updated.
17302 Specifically we want to avoid creating an IT block for conditional
17303 branches, so it_fsm_pre_encode is actually a guess and we can't
17304 determine whether an IT block is required until the tencode () routine
17305 has decided what type of instruction this actually it.
17306 Because of this, if set_it_insn_type and in_it_block have to be used,
17307 set_it_insn_type has to be called first.
17309 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17310 determines the insn IT type depending on the inst.cond code.
17311 When a tencode () routine encodes an instruction that can be
17312 either outside an IT block, or, in the case of being inside, has to be
17313 the last one, set_it_insn_type_last () will determine the proper
17314 IT instruction type based on the inst.cond code. Otherwise,
17315 set_it_insn_type can be called for overriding that logic or
17316 for covering other cases.
17318 Calling handle_it_state () may not transition the IT block state to
17319 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17320 still queried. Instead, if the FSM determines that the state should
17321 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17322 after the tencode () function: that's what it_fsm_post_encode () does.
17324 Since in_it_block () calls the state handling function to get an
17325 updated state, an error may occur (due to invalid insns combination).
17326 In that case, inst.error is set.
17327 Therefore, inst.error has to be checked after the execution of
17328 the tencode () routine.
17330 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17331 any pending state change (if any) that didn't take place in
17332 handle_it_state () as explained above. */
17335 it_fsm_pre_encode (void)
17337 if (inst
.cond
!= COND_ALWAYS
)
17338 inst
.it_insn_type
= INSIDE_IT_INSN
;
17340 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17342 now_it
.state_handled
= 0;
17345 /* IT state FSM handling function. */
17348 handle_it_state (void)
17350 now_it
.state_handled
= 1;
17351 now_it
.insn_cond
= FALSE
;
17353 switch (now_it
.state
)
17355 case OUTSIDE_IT_BLOCK
:
17356 switch (inst
.it_insn_type
)
17358 case OUTSIDE_IT_INSN
:
17361 case INSIDE_IT_INSN
:
17362 case INSIDE_IT_LAST_INSN
:
17363 if (thumb_mode
== 0)
17366 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17367 as_tsktsk (_("Warning: conditional outside an IT block"\
17372 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17373 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17375 /* Automatically generate the IT instruction. */
17376 new_automatic_it_block (inst
.cond
);
17377 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17378 close_automatic_it_block ();
17382 inst
.error
= BAD_OUT_IT
;
17388 case IF_INSIDE_IT_LAST_INSN
:
17389 case NEUTRAL_IT_INSN
:
17393 now_it
.state
= MANUAL_IT_BLOCK
;
17394 now_it
.block_length
= 0;
17399 case AUTOMATIC_IT_BLOCK
:
17400 /* Three things may happen now:
17401 a) We should increment current it block size;
17402 b) We should close current it block (closing insn or 4 insns);
17403 c) We should close current it block and start a new one (due
17404 to incompatible conditions or
17405 4 insns-length block reached). */
17407 switch (inst
.it_insn_type
)
17409 case OUTSIDE_IT_INSN
:
17410 /* The closure of the block shall happen immediatelly,
17411 so any in_it_block () call reports the block as closed. */
17412 force_automatic_it_block_close ();
17415 case INSIDE_IT_INSN
:
17416 case INSIDE_IT_LAST_INSN
:
17417 case IF_INSIDE_IT_LAST_INSN
:
17418 now_it
.block_length
++;
17420 if (now_it
.block_length
> 4
17421 || !now_it_compatible (inst
.cond
))
17423 force_automatic_it_block_close ();
17424 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17425 new_automatic_it_block (inst
.cond
);
17429 now_it
.insn_cond
= TRUE
;
17430 now_it_add_mask (inst
.cond
);
17433 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17434 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17435 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17436 close_automatic_it_block ();
17439 case NEUTRAL_IT_INSN
:
17440 now_it
.block_length
++;
17441 now_it
.insn_cond
= TRUE
;
17443 if (now_it
.block_length
> 4)
17444 force_automatic_it_block_close ();
17446 now_it_add_mask (now_it
.cc
& 1);
17450 close_automatic_it_block ();
17451 now_it
.state
= MANUAL_IT_BLOCK
;
17456 case MANUAL_IT_BLOCK
:
17458 /* Check conditional suffixes. */
17459 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17462 now_it
.mask
&= 0x1f;
17463 is_last
= (now_it
.mask
== 0x10);
17464 now_it
.insn_cond
= TRUE
;
17466 switch (inst
.it_insn_type
)
17468 case OUTSIDE_IT_INSN
:
17469 inst
.error
= BAD_NOT_IT
;
17472 case INSIDE_IT_INSN
:
17473 if (cond
!= inst
.cond
)
17475 inst
.error
= BAD_IT_COND
;
17480 case INSIDE_IT_LAST_INSN
:
17481 case IF_INSIDE_IT_LAST_INSN
:
17482 if (cond
!= inst
.cond
)
17484 inst
.error
= BAD_IT_COND
;
17489 inst
.error
= BAD_BRANCH
;
17494 case NEUTRAL_IT_INSN
:
17495 /* The BKPT instruction is unconditional even in an IT block. */
17499 inst
.error
= BAD_IT_IT
;
17509 struct depr_insn_mask
17511 unsigned long pattern
;
17512 unsigned long mask
;
17513 const char* description
;
17516 /* List of 16-bit instruction patterns deprecated in an IT block in
17518 static const struct depr_insn_mask depr_it_insns
[] = {
17519 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17520 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17521 { 0xa000, 0xb800, N_("ADR") },
17522 { 0x4800, 0xf800, N_("Literal loads") },
17523 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17524 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17525 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17526 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17527 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17532 it_fsm_post_encode (void)
17536 if (!now_it
.state_handled
)
17537 handle_it_state ();
17539 if (now_it
.insn_cond
17540 && !now_it
.warn_deprecated
17541 && warn_on_deprecated
17542 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17544 if (inst
.instruction
>= 0x10000)
17546 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17547 "deprecated in ARMv8"));
17548 now_it
.warn_deprecated
= TRUE
;
17552 const struct depr_insn_mask
*p
= depr_it_insns
;
17554 while (p
->mask
!= 0)
17556 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17558 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17559 "of the following class are deprecated in ARMv8: "
17560 "%s"), p
->description
);
17561 now_it
.warn_deprecated
= TRUE
;
17569 if (now_it
.block_length
> 1)
17571 as_tsktsk (_("IT blocks containing more than one conditional "
17572 "instruction are deprecated in ARMv8"));
17573 now_it
.warn_deprecated
= TRUE
;
17577 is_last
= (now_it
.mask
== 0x10);
17580 now_it
.state
= OUTSIDE_IT_BLOCK
;
17586 force_automatic_it_block_close (void)
17588 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17590 close_automatic_it_block ();
17591 now_it
.state
= OUTSIDE_IT_BLOCK
;
17599 if (!now_it
.state_handled
)
17600 handle_it_state ();
17602 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17606 md_assemble (char *str
)
17609 const struct asm_opcode
* opcode
;
17611 /* Align the previous label if needed. */
17612 if (last_label_seen
!= NULL
)
17614 symbol_set_frag (last_label_seen
, frag_now
);
17615 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17616 S_SET_SEGMENT (last_label_seen
, now_seg
);
17619 memset (&inst
, '\0', sizeof (inst
));
17620 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17622 opcode
= opcode_lookup (&p
);
17625 /* It wasn't an instruction, but it might be a register alias of
17626 the form alias .req reg, or a Neon .dn/.qn directive. */
17627 if (! create_register_alias (str
, p
)
17628 && ! create_neon_reg_alias (str
, p
))
17629 as_bad (_("bad instruction `%s'"), str
);
17634 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17635 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17637 /* The value which unconditional instructions should have in place of the
17638 condition field. */
17639 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17643 arm_feature_set variant
;
17645 variant
= cpu_variant
;
17646 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17647 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17648 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17649 /* Check that this instruction is supported for this CPU. */
17650 if (!opcode
->tvariant
17651 || (thumb_mode
== 1
17652 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17654 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17657 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17658 && opcode
->tencode
!= do_t_branch
)
17660 as_bad (_("Thumb does not support conditional execution"));
17664 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17666 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17667 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17668 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17670 /* Two things are addressed here.
17671 1) Implicit require narrow instructions on Thumb-1.
17672 This avoids relaxation accidentally introducing Thumb-2
17674 2) Reject wide instructions in non Thumb-2 cores. */
17675 if (inst
.size_req
== 0)
17677 else if (inst
.size_req
== 4)
17679 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17685 inst
.instruction
= opcode
->tvalue
;
17687 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17689 /* Prepare the it_insn_type for those encodings that don't set
17691 it_fsm_pre_encode ();
17693 opcode
->tencode ();
17695 it_fsm_post_encode ();
17698 if (!(inst
.error
|| inst
.relax
))
17700 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17701 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17702 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17704 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17709 /* Something has gone badly wrong if we try to relax a fixed size
17711 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17713 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17714 *opcode
->tvariant
);
17715 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17716 set those bits when Thumb-2 32-bit instructions are seen. ie.
17717 anything other than bl/blx and v6-M instructions.
17718 The impact of relaxable instructions will be considered later after we
17719 finish all relaxation. */
17720 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17721 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17722 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17723 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17726 check_neon_suffixes
;
17730 mapping_state (MAP_THUMB
);
17733 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17737 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17738 is_bx
= (opcode
->aencode
== do_bx
);
17740 /* Check that this instruction is supported for this CPU. */
17741 if (!(is_bx
&& fix_v4bx
)
17742 && !(opcode
->avariant
&&
17743 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17745 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17750 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17754 inst
.instruction
= opcode
->avalue
;
17755 if (opcode
->tag
== OT_unconditionalF
)
17756 inst
.instruction
|= 0xF << 28;
17758 inst
.instruction
|= inst
.cond
<< 28;
17759 inst
.size
= INSN_SIZE
;
17760 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17762 it_fsm_pre_encode ();
17763 opcode
->aencode ();
17764 it_fsm_post_encode ();
17766 /* Arm mode bx is marked as both v4T and v5 because it's still required
17767 on a hypothetical non-thumb v5 core. */
17769 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17771 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17772 *opcode
->avariant
);
17774 check_neon_suffixes
;
17778 mapping_state (MAP_ARM
);
17783 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17791 check_it_blocks_finished (void)
17796 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17797 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17798 == MANUAL_IT_BLOCK
)
17800 as_warn (_("section '%s' finished with an open IT block."),
17804 if (now_it
.state
== MANUAL_IT_BLOCK
)
17805 as_warn (_("file finished with an open IT block."));
17809 /* Various frobbings of labels and their addresses. */
17812 arm_start_line_hook (void)
17814 last_label_seen
= NULL
;
17818 arm_frob_label (symbolS
* sym
)
17820 last_label_seen
= sym
;
17822 ARM_SET_THUMB (sym
, thumb_mode
);
17824 #if defined OBJ_COFF || defined OBJ_ELF
17825 ARM_SET_INTERWORK (sym
, support_interwork
);
17828 force_automatic_it_block_close ();
17830 /* Note - do not allow local symbols (.Lxxx) to be labelled
17831 as Thumb functions. This is because these labels, whilst
17832 they exist inside Thumb code, are not the entry points for
17833 possible ARM->Thumb calls. Also, these labels can be used
17834 as part of a computed goto or switch statement. eg gcc
17835 can generate code that looks like this:
17837 ldr r2, [pc, .Laaa]
17847 The first instruction loads the address of the jump table.
17848 The second instruction converts a table index into a byte offset.
17849 The third instruction gets the jump address out of the table.
17850 The fourth instruction performs the jump.
17852 If the address stored at .Laaa is that of a symbol which has the
17853 Thumb_Func bit set, then the linker will arrange for this address
17854 to have the bottom bit set, which in turn would mean that the
17855 address computation performed by the third instruction would end
17856 up with the bottom bit set. Since the ARM is capable of unaligned
17857 word loads, the instruction would then load the incorrect address
17858 out of the jump table, and chaos would ensue. */
17859 if (label_is_thumb_function_name
17860 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17861 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17863 /* When the address of a Thumb function is taken the bottom
17864 bit of that address should be set. This will allow
17865 interworking between Arm and Thumb functions to work
17868 THUMB_SET_FUNC (sym
, 1);
17870 label_is_thumb_function_name
= FALSE
;
17873 dwarf2_emit_label (sym
);
17877 arm_data_in_code (void)
17879 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17881 *input_line_pointer
= '/';
17882 input_line_pointer
+= 5;
17883 *input_line_pointer
= 0;
17891 arm_canonicalize_symbol_name (char * name
)
17895 if (thumb_mode
&& (len
= strlen (name
)) > 5
17896 && streq (name
+ len
- 5, "/data"))
17897 *(name
+ len
- 5) = 0;
17902 /* Table of all register names defined by default. The user can
17903 define additional names with .req. Note that all register names
17904 should appear in both upper and lowercase variants. Some registers
17905 also have mixed-case names. */
17907 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17908 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17909 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17910 #define REGSET(p,t) \
17911 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17912 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17913 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17914 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17915 #define REGSETH(p,t) \
17916 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17917 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17918 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17919 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17920 #define REGSET2(p,t) \
17921 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17922 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17923 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17924 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17925 #define SPLRBANK(base,bank,t) \
17926 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17927 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17928 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17929 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17930 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17931 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17933 static const struct reg_entry reg_names
[] =
17935 /* ARM integer registers. */
17936 REGSET(r
, RN
), REGSET(R
, RN
),
17938 /* ATPCS synonyms. */
17939 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17940 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17941 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17943 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17944 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17945 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17947 /* Well-known aliases. */
17948 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17949 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17951 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17952 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17954 /* Coprocessor numbers. */
17955 REGSET(p
, CP
), REGSET(P
, CP
),
17957 /* Coprocessor register numbers. The "cr" variants are for backward
17959 REGSET(c
, CN
), REGSET(C
, CN
),
17960 REGSET(cr
, CN
), REGSET(CR
, CN
),
17962 /* ARM banked registers. */
17963 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17964 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17965 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17966 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17967 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17968 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17969 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17971 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17972 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17973 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17974 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17975 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17976 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
17977 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17978 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17980 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17981 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17982 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17983 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17984 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17985 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17986 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17987 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17988 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17990 /* FPA registers. */
17991 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17992 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17994 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17995 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17997 /* VFP SP registers. */
17998 REGSET(s
,VFS
), REGSET(S
,VFS
),
17999 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18001 /* VFP DP Registers. */
18002 REGSET(d
,VFD
), REGSET(D
,VFD
),
18003 /* Extra Neon DP registers. */
18004 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18006 /* Neon QP registers. */
18007 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18009 /* VFP control registers. */
18010 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18011 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18012 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18013 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18014 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18015 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18017 /* Maverick DSP coprocessor registers. */
18018 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18019 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18021 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18022 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18023 REGDEF(dspsc
,0,DSPSC
),
18025 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18026 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18027 REGDEF(DSPSC
,0,DSPSC
),
18029 /* iWMMXt data registers - p0, c0-15. */
18030 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18032 /* iWMMXt control registers - p1, c0-3. */
18033 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18034 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18035 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18036 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18038 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18039 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18040 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18041 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18042 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18044 /* XScale accumulator registers. */
18045 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18051 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18052 within psr_required_here. */
18053 static const struct asm_psr psrs
[] =
18055 /* Backward compatibility notation. Note that "all" is no longer
18056 truly all possible PSR bits. */
18057 {"all", PSR_c
| PSR_f
},
18061 /* Individual flags. */
18067 /* Combinations of flags. */
18068 {"fs", PSR_f
| PSR_s
},
18069 {"fx", PSR_f
| PSR_x
},
18070 {"fc", PSR_f
| PSR_c
},
18071 {"sf", PSR_s
| PSR_f
},
18072 {"sx", PSR_s
| PSR_x
},
18073 {"sc", PSR_s
| PSR_c
},
18074 {"xf", PSR_x
| PSR_f
},
18075 {"xs", PSR_x
| PSR_s
},
18076 {"xc", PSR_x
| PSR_c
},
18077 {"cf", PSR_c
| PSR_f
},
18078 {"cs", PSR_c
| PSR_s
},
18079 {"cx", PSR_c
| PSR_x
},
18080 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18081 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18082 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18083 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18084 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18085 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18086 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18087 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18088 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18089 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18090 {"scf", PSR_s
| PSR_c
| PSR_f
},
18091 {"scx", PSR_s
| PSR_c
| PSR_x
},
18092 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18093 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18094 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18095 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18096 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18097 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18098 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18099 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18100 {"csf", PSR_c
| PSR_s
| PSR_f
},
18101 {"csx", PSR_c
| PSR_s
| PSR_x
},
18102 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18103 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18104 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18105 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18106 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18107 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18108 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18109 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18110 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18111 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18112 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18113 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18114 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18115 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18116 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18117 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18118 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18119 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18120 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18121 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18122 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18123 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18124 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18125 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18126 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18127 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18130 /* Table of V7M psr names. */
18131 static const struct asm_psr v7m_psrs
[] =
18133 {"apsr", 0 }, {"APSR", 0 },
18134 {"iapsr", 1 }, {"IAPSR", 1 },
18135 {"eapsr", 2 }, {"EAPSR", 2 },
18136 {"psr", 3 }, {"PSR", 3 },
18137 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18138 {"ipsr", 5 }, {"IPSR", 5 },
18139 {"epsr", 6 }, {"EPSR", 6 },
18140 {"iepsr", 7 }, {"IEPSR", 7 },
18141 {"msp", 8 }, {"MSP", 8 },
18142 {"psp", 9 }, {"PSP", 9 },
18143 {"primask", 16}, {"PRIMASK", 16},
18144 {"basepri", 17}, {"BASEPRI", 17},
18145 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18146 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18147 {"faultmask", 19}, {"FAULTMASK", 19},
18148 {"control", 20}, {"CONTROL", 20}
18151 /* Table of all shift-in-operand names. */
18152 static const struct asm_shift_name shift_names
[] =
18154 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18155 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18156 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18157 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18158 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18159 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18162 /* Table of all explicit relocation names. */
18164 static struct reloc_entry reloc_names
[] =
18166 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18167 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18168 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18169 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18170 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18171 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18172 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18173 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18174 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18175 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18176 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18177 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18178 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18179 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18180 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18181 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18182 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18183 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18187 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18188 static const struct asm_cond conds
[] =
18192 {"cs", 0x2}, {"hs", 0x2},
18193 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18207 #define UL_BARRIER(L,U,CODE,FEAT) \
18208 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
18209 { U, CODE, ARM_FEATURE (FEAT, 0) }
18211 static struct asm_barrier_opt barrier_opt_names
[] =
18213 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18214 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18215 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18216 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18217 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18218 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18219 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18220 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18221 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18222 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18223 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18224 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18225 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18226 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18227 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18228 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18233 /* Table of ARM-format instructions. */
18235 /* Macros for gluing together operand strings. N.B. In all cases
18236 other than OPS0, the trailing OP_stop comes from default
18237 zero-initialization of the unspecified elements of the array. */
18238 #define OPS0() { OP_stop, }
18239 #define OPS1(a) { OP_##a, }
18240 #define OPS2(a,b) { OP_##a,OP_##b, }
18241 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18242 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18243 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18244 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18246 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18247 This is useful when mixing operands for ARM and THUMB, i.e. using the
18248 MIX_ARM_THUMB_OPERANDS macro.
18249 In order to use these macros, prefix the number of operands with _
18251 #define OPS_1(a) { a, }
18252 #define OPS_2(a,b) { a,b, }
18253 #define OPS_3(a,b,c) { a,b,c, }
18254 #define OPS_4(a,b,c,d) { a,b,c,d, }
18255 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18256 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18258 /* These macros abstract out the exact format of the mnemonic table and
18259 save some repeated characters. */
18261 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18262 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18263 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18264 THUMB_VARIANT, do_##ae, do_##te }
18266 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18267 a T_MNEM_xyz enumerator. */
18268 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18269 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18270 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18271 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18273 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18274 infix after the third character. */
18275 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18276 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18277 THUMB_VARIANT, do_##ae, do_##te }
18278 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18279 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18280 THUMB_VARIANT, do_##ae, do_##te }
18281 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18282 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18283 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18284 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18285 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18286 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18287 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18288 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18290 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18291 field is still 0xE. Many of the Thumb variants can be executed
18292 conditionally, so this is checked separately. */
18293 #define TUE(mnem, op, top, nops, ops, ae, te) \
18294 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18295 THUMB_VARIANT, do_##ae, do_##te }
18297 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18298 Used by mnemonics that have very minimal differences in the encoding for
18299 ARM and Thumb variants and can be handled in a common function. */
18300 #define TUEc(mnem, op, top, nops, ops, en) \
18301 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18302 THUMB_VARIANT, do_##en, do_##en }
18304 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18305 condition code field. */
18306 #define TUF(mnem, op, top, nops, ops, ae, te) \
18307 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18308 THUMB_VARIANT, do_##ae, do_##te }
18310 /* ARM-only variants of all the above. */
18311 #define CE(mnem, op, nops, ops, ae) \
18312 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18314 #define C3(mnem, op, nops, ops, ae) \
18315 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18317 /* Legacy mnemonics that always have conditional infix after the third
18319 #define CL(mnem, op, nops, ops, ae) \
18320 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18321 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18323 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18324 #define cCE(mnem, op, nops, ops, ae) \
18325 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18327 /* Legacy coprocessor instructions where conditional infix and conditional
18328 suffix are ambiguous. For consistency this includes all FPA instructions,
18329 not just the potentially ambiguous ones. */
18330 #define cCL(mnem, op, nops, ops, ae) \
18331 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18332 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18334 /* Coprocessor, takes either a suffix or a position-3 infix
18335 (for an FPA corner case). */
18336 #define C3E(mnem, op, nops, ops, ae) \
18337 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18338 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18340 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18341 { m1 #m2 m3, OPS##nops ops, \
18342 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18343 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18345 #define CM(m1, m2, op, nops, ops, ae) \
18346 xCM_ (m1, , m2, op, nops, ops, ae), \
18347 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18348 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18349 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18350 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18351 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18352 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18353 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18354 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18355 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18356 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18357 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18358 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18359 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18360 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18361 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18362 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18363 xCM_ (m1, le, m2, op, nops, ops, ae), \
18364 xCM_ (m1, al, m2, op, nops, ops, ae)
18366 #define UE(mnem, op, nops, ops, ae) \
18367 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18369 #define UF(mnem, op, nops, ops, ae) \
18370 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18372 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18373 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18374 use the same encoding function for each. */
18375 #define NUF(mnem, op, nops, ops, enc) \
18376 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18377 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18379 /* Neon data processing, version which indirects through neon_enc_tab for
18380 the various overloaded versions of opcodes. */
18381 #define nUF(mnem, op, nops, ops, enc) \
18382 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18383 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18385 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18387 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18388 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18389 THUMB_VARIANT, do_##enc, do_##enc }
18391 #define NCE(mnem, op, nops, ops, enc) \
18392 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18394 #define NCEF(mnem, op, nops, ops, enc) \
18395 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18397 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18398 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18399 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18400 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18402 #define nCE(mnem, op, nops, ops, enc) \
18403 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18405 #define nCEF(mnem, op, nops, ops, enc) \
18406 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18410 static const struct asm_opcode insns
[] =
18412 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18413 #define THUMB_VARIANT & arm_ext_v4t
18414 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18415 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18416 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18417 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18418 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18419 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18420 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18421 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18422 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18423 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18424 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18425 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18426 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18427 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18428 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18429 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18431 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18432 for setting PSR flag bits. They are obsolete in V6 and do not
18433 have Thumb equivalents. */
18434 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18435 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18436 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18437 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18438 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18439 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18440 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18441 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18442 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18444 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18445 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18446 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18447 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18449 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18450 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18451 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18453 OP_ADDRGLDR
),ldst
, t_ldst
),
18454 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18456 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18457 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18458 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18459 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18460 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18461 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18463 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18464 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18465 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18466 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18469 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18470 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18471 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18472 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18474 /* Thumb-compatibility pseudo ops. */
18475 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18476 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18477 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18478 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18479 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18480 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18481 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18482 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18483 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18484 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18485 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18486 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18488 /* These may simplify to neg. */
18489 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18490 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18492 #undef THUMB_VARIANT
18493 #define THUMB_VARIANT & arm_ext_v6
18495 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18497 /* V1 instructions with no Thumb analogue prior to V6T2. */
18498 #undef THUMB_VARIANT
18499 #define THUMB_VARIANT & arm_ext_v6t2
18501 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18502 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18503 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18505 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18506 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18507 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18508 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18510 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18511 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18513 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18514 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18516 /* V1 instructions with no Thumb analogue at all. */
18517 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18518 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18520 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18521 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18522 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18523 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18524 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18525 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18526 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18527 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18530 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18531 #undef THUMB_VARIANT
18532 #define THUMB_VARIANT & arm_ext_v4t
18534 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18535 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18537 #undef THUMB_VARIANT
18538 #define THUMB_VARIANT & arm_ext_v6t2
18540 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18541 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18543 /* Generic coprocessor instructions. */
18544 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18545 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18546 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18547 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18548 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18549 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18550 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18553 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18555 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18556 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18559 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18560 #undef THUMB_VARIANT
18561 #define THUMB_VARIANT & arm_ext_msr
18563 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18564 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18567 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18568 #undef THUMB_VARIANT
18569 #define THUMB_VARIANT & arm_ext_v6t2
18571 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18572 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18573 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18574 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18575 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18576 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18577 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18578 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18581 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18582 #undef THUMB_VARIANT
18583 #define THUMB_VARIANT & arm_ext_v4t
18585 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18586 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18587 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18588 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18589 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18590 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18593 #define ARM_VARIANT & arm_ext_v4t_5
18595 /* ARM Architecture 4T. */
18596 /* Note: bx (and blx) are required on V5, even if the processor does
18597 not support Thumb. */
18598 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18601 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18602 #undef THUMB_VARIANT
18603 #define THUMB_VARIANT & arm_ext_v5t
18605 /* Note: blx has 2 variants; the .value coded here is for
18606 BLX(2). Only this variant has conditional execution. */
18607 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18608 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18610 #undef THUMB_VARIANT
18611 #define THUMB_VARIANT & arm_ext_v6t2
18613 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18614 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18615 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18616 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18617 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18618 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18619 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18620 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18623 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18624 #undef THUMB_VARIANT
18625 #define THUMB_VARIANT & arm_ext_v5exp
18627 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18628 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18629 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18630 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18632 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18633 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18635 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18636 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18637 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18638 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18640 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18641 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18642 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18643 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18645 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18646 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18648 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18649 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18650 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18651 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18654 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18655 #undef THUMB_VARIANT
18656 #define THUMB_VARIANT & arm_ext_v6t2
18658 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18659 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18661 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18662 ADDRGLDRS
), ldrd
, t_ldstd
),
18664 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18665 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18668 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18670 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18673 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18674 #undef THUMB_VARIANT
18675 #define THUMB_VARIANT & arm_ext_v6
18677 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18678 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18679 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18680 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18681 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18682 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18683 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18684 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18685 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18686 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18688 #undef THUMB_VARIANT
18689 #define THUMB_VARIANT & arm_ext_v6t2
18691 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18692 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18694 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18695 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18697 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18698 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18700 /* ARM V6 not included in V7M. */
18701 #undef THUMB_VARIANT
18702 #define THUMB_VARIANT & arm_ext_v6_notm
18703 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18704 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18705 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18706 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18707 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18708 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18709 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18710 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18711 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18712 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18713 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18714 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18715 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18716 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18717 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18718 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18719 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18720 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18722 /* ARM V6 not included in V7M (eg. integer SIMD). */
18723 #undef THUMB_VARIANT
18724 #define THUMB_VARIANT & arm_ext_v6_dsp
18725 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18726 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18727 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18728 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18729 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18730 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18731 /* Old name for QASX. */
18732 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18733 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18734 /* Old name for QSAX. */
18735 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18736 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18737 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18738 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18739 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18740 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18741 /* Old name for SASX. */
18742 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18743 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18744 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18745 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18746 /* Old name for SHASX. */
18747 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18748 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18749 /* Old name for SHSAX. */
18750 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18751 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18752 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18753 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18754 /* Old name for SSAX. */
18755 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18756 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18757 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18758 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18759 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18760 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18761 /* Old name for UASX. */
18762 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18763 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18764 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18765 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18766 /* Old name for UHASX. */
18767 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18768 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18769 /* Old name for UHSAX. */
18770 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18771 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18772 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18773 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18774 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18775 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18776 /* Old name for UQASX. */
18777 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18778 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18779 /* Old name for UQSAX. */
18780 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18781 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18782 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18783 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18784 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18785 /* Old name for USAX. */
18786 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18787 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18788 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18789 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18790 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18791 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18792 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18793 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18794 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18795 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18796 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18797 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18798 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18799 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18800 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18801 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18802 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18803 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18804 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18805 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18806 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18807 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18808 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18809 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18810 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18811 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18812 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18813 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18814 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18815 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18816 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18817 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18818 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18819 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18822 #define ARM_VARIANT & arm_ext_v6k
18823 #undef THUMB_VARIANT
18824 #define THUMB_VARIANT & arm_ext_v6k
18826 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18827 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18828 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18829 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18831 #undef THUMB_VARIANT
18832 #define THUMB_VARIANT & arm_ext_v6_notm
18833 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18835 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18836 RRnpcb
), strexd
, t_strexd
),
18838 #undef THUMB_VARIANT
18839 #define THUMB_VARIANT & arm_ext_v6t2
18840 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18842 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18844 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18846 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18848 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18851 #define ARM_VARIANT & arm_ext_sec
18852 #undef THUMB_VARIANT
18853 #define THUMB_VARIANT & arm_ext_sec
18855 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18858 #define ARM_VARIANT & arm_ext_virt
18859 #undef THUMB_VARIANT
18860 #define THUMB_VARIANT & arm_ext_virt
18862 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18863 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18866 #define ARM_VARIANT & arm_ext_v6t2
18867 #undef THUMB_VARIANT
18868 #define THUMB_VARIANT & arm_ext_v6t2
18870 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18871 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18872 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18873 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18875 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18876 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18877 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18878 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18880 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18881 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18882 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18883 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18885 /* Thumb-only instructions. */
18887 #define ARM_VARIANT NULL
18888 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18889 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18891 /* ARM does not really have an IT instruction, so always allow it.
18892 The opcode is copied from Thumb in order to allow warnings in
18893 -mimplicit-it=[never | arm] modes. */
18895 #define ARM_VARIANT & arm_ext_v1
18897 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18898 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18899 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18900 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18901 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18902 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18903 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18904 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18905 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18906 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18907 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18908 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18909 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18910 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18911 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18912 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18913 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18914 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18916 /* Thumb2 only instructions. */
18918 #define ARM_VARIANT NULL
18920 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18921 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18922 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18923 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18924 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18925 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18927 /* Hardware division instructions. */
18929 #define ARM_VARIANT & arm_ext_adiv
18930 #undef THUMB_VARIANT
18931 #define THUMB_VARIANT & arm_ext_div
18933 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18934 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18936 /* ARM V6M/V7 instructions. */
18938 #define ARM_VARIANT & arm_ext_barrier
18939 #undef THUMB_VARIANT
18940 #define THUMB_VARIANT & arm_ext_barrier
18942 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18943 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18944 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18946 /* ARM V7 instructions. */
18948 #define ARM_VARIANT & arm_ext_v7
18949 #undef THUMB_VARIANT
18950 #define THUMB_VARIANT & arm_ext_v7
18952 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18953 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18956 #define ARM_VARIANT & arm_ext_mp
18957 #undef THUMB_VARIANT
18958 #define THUMB_VARIANT & arm_ext_mp
18960 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18962 /* AArchv8 instructions. */
18964 #define ARM_VARIANT & arm_ext_v8
18965 #undef THUMB_VARIANT
18966 #define THUMB_VARIANT & arm_ext_v8
18968 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18969 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18970 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18971 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18973 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18974 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18975 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18977 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18979 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18981 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18983 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18984 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18985 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18986 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18987 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18988 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18990 /* ARMv8 T32 only. */
18992 #define ARM_VARIANT NULL
18993 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18994 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18995 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18997 /* FP for ARMv8. */
18999 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19000 #undef THUMB_VARIANT
19001 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19003 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19004 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19005 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19006 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19007 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19008 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19009 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19010 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19011 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19012 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19013 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19014 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19015 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19016 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19017 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19018 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19019 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19021 /* Crypto v1 extensions. */
19023 #define ARM_VARIANT & fpu_crypto_ext_armv8
19024 #undef THUMB_VARIANT
19025 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19027 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19028 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19029 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19030 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19031 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19032 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19033 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19034 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19035 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19036 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19037 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19038 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19039 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19040 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19043 #define ARM_VARIANT & crc_ext_armv8
19044 #undef THUMB_VARIANT
19045 #define THUMB_VARIANT & crc_ext_armv8
19046 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19047 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19048 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19049 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19050 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19051 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19054 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19055 #undef THUMB_VARIANT
19056 #define THUMB_VARIANT NULL
19058 cCE("wfs", e200110
, 1, (RR
), rd
),
19059 cCE("rfs", e300110
, 1, (RR
), rd
),
19060 cCE("wfc", e400110
, 1, (RR
), rd
),
19061 cCE("rfc", e500110
, 1, (RR
), rd
),
19063 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19064 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19065 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19066 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19068 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19069 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19070 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19071 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19073 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19074 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19075 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19076 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19077 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19078 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19079 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19080 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19081 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19082 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19083 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19084 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19086 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19087 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19088 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19089 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19090 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19091 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19092 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19093 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19094 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19095 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19096 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19097 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19099 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19100 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19101 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19102 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19103 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19104 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19105 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19106 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19107 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19108 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19109 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19110 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19112 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19113 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19114 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19115 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19116 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19117 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19118 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19119 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19120 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19121 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19122 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19123 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19125 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19126 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19127 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19128 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19129 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19130 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19131 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19132 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19133 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19134 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19135 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19136 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19138 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19139 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19140 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19141 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19142 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19143 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19144 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19145 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19146 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19147 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19148 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19149 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19151 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19152 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19153 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19154 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19155 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19156 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19157 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19158 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19159 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19160 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19161 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19162 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19164 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19165 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19166 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19167 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19168 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19169 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19170 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19171 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19172 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19173 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19174 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19175 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19177 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19178 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19179 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19180 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19181 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19182 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19183 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19184 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19185 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19186 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19187 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19188 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19190 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19191 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19192 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19193 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19194 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19195 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19196 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19197 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19198 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19199 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19200 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19201 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19203 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19204 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19205 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19206 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19207 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19208 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19209 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19210 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19211 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19212 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19213 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19214 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19216 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19217 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19218 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19219 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19220 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19221 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19222 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19223 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19224 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19225 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19226 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19227 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19229 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19230 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19231 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19232 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19233 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19234 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19235 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19236 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19237 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19238 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19239 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19240 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19242 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19243 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19244 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19245 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19246 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19247 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19248 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19249 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19250 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19251 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19252 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19253 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19282 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19283 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19284 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19285 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19286 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19287 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19288 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19289 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19290 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19291 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19292 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19294 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19295 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19296 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19297 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19298 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19299 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19300 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19301 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19302 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19303 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19304 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19305 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19307 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19308 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19309 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19310 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19311 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19312 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19313 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19314 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19315 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19316 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19317 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19318 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19320 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19321 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19322 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19323 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19324 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19325 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19326 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19327 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19328 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19329 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19330 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19331 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19333 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19334 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19335 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19336 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19337 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19338 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19339 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19340 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19341 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19342 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19343 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19344 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19346 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19347 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19348 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19349 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19350 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19351 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19352 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19353 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19354 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19355 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19356 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19357 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19359 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19360 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19361 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19362 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19363 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19364 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19365 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19366 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19367 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19368 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19369 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19370 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19372 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19373 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19374 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19375 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19376 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19377 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19378 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19379 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19380 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19381 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19382 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19383 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19385 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19386 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19387 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19388 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19389 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19390 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19391 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19392 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19393 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19394 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19395 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19396 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19398 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19399 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19400 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19401 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19402 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19403 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19404 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19405 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19406 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19407 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19408 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19409 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19411 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19412 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19413 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19414 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19415 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19416 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19417 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19418 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19419 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19420 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19421 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19422 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19424 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19425 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19426 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19427 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19428 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19429 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19430 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19431 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19432 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19433 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19434 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19435 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19437 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19438 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19439 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19440 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19441 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19442 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19443 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19444 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19445 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19446 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19447 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19448 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19450 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19451 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19452 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19453 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19455 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19456 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19457 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19458 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19459 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19460 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19461 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19462 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19463 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19464 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19465 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19466 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19468 /* The implementation of the FIX instruction is broken on some
19469 assemblers, in that it accepts a precision specifier as well as a
19470 rounding specifier, despite the fact that this is meaningless.
19471 To be more compatible, we accept it as well, though of course it
19472 does not set any bits. */
19473 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19474 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19475 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19476 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19477 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19478 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19479 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19480 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19481 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19482 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19483 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19484 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19485 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19487 /* Instructions that were new with the real FPA, call them V2. */
19489 #define ARM_VARIANT & fpu_fpa_ext_v2
19491 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19492 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19493 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19494 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19495 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19496 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19499 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19501 /* Moves and type conversions. */
19502 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19503 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19504 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19505 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19506 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19507 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19508 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19509 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19510 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19511 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19512 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19513 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19514 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19515 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19517 /* Memory operations. */
19518 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19519 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19520 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19521 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19522 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19523 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19524 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19525 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19526 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19527 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19528 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19529 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19530 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19531 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19532 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19533 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19534 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19535 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19537 /* Monadic operations. */
19538 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19539 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19540 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19542 /* Dyadic operations. */
19543 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19544 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19545 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19546 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19547 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19548 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19549 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19550 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19551 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19554 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19555 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19556 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19557 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19559 /* Double precision load/store are still present on single precision
19560 implementations. */
19561 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19562 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19563 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19564 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19565 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19566 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19567 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19568 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19569 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19570 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19573 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19575 /* Moves and type conversions. */
19576 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19577 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19578 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19579 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19580 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19581 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19582 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19583 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19584 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19585 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19586 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19587 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19588 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19590 /* Monadic operations. */
19591 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19592 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19593 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19595 /* Dyadic operations. */
19596 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19597 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19598 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19599 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19600 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19601 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19602 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19603 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19604 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19607 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19608 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19609 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19610 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19613 #define ARM_VARIANT & fpu_vfp_ext_v2
19615 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19616 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19617 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19618 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19620 /* Instructions which may belong to either the Neon or VFP instruction sets.
19621 Individual encoder functions perform additional architecture checks. */
19623 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19624 #undef THUMB_VARIANT
19625 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19627 /* These mnemonics are unique to VFP. */
19628 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19629 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19630 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19631 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19632 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19633 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19634 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19635 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19636 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19637 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19639 /* Mnemonics shared by Neon and VFP. */
19640 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19641 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19642 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19644 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19645 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19647 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19648 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19650 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19651 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19652 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19653 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19654 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19655 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19656 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19657 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19659 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19660 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19661 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19662 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19665 /* NOTE: All VMOV encoding is special-cased! */
19666 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19667 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19669 #undef THUMB_VARIANT
19670 #define THUMB_VARIANT & fpu_neon_ext_v1
19672 #define ARM_VARIANT & fpu_neon_ext_v1
19674 /* Data processing with three registers of the same length. */
19675 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19676 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19677 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19678 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19679 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19680 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19681 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19682 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19683 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19684 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19685 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19686 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19687 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19688 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19689 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19690 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19691 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19692 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19693 /* If not immediate, fall back to neon_dyadic_i64_su.
19694 shl_imm should accept I8 I16 I32 I64,
19695 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19696 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19697 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19698 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19699 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19700 /* Logic ops, types optional & ignored. */
19701 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19702 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19703 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19704 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19705 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19706 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19707 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19708 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19709 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19710 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19711 /* Bitfield ops, untyped. */
19712 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19713 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19714 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19715 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19716 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19717 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19718 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19719 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19720 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19721 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19722 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19723 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19724 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19725 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19726 back to neon_dyadic_if_su. */
19727 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19728 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19729 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19730 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19731 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19732 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19733 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19734 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19735 /* Comparison. Type I8 I16 I32 F32. */
19736 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19737 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19738 /* As above, D registers only. */
19739 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19740 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19741 /* Int and float variants, signedness unimportant. */
19742 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19743 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19744 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19745 /* Add/sub take types I8 I16 I32 I64 F32. */
19746 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19747 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19748 /* vtst takes sizes 8, 16, 32. */
19749 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19750 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19751 /* VMUL takes I8 I16 I32 F32 P8. */
19752 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19753 /* VQD{R}MULH takes S16 S32. */
19754 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19755 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19756 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19757 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19758 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19759 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19760 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19761 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19762 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19763 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19764 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19765 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19766 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19767 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19768 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19769 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19771 /* Two address, int/float. Types S8 S16 S32 F32. */
19772 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19773 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19775 /* Data processing with two registers and a shift amount. */
19776 /* Right shifts, and variants with rounding.
19777 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19778 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19779 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19780 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19781 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19782 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19783 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19784 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19785 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19786 /* Shift and insert. Sizes accepted 8 16 32 64. */
19787 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19788 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19789 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19790 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19791 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19792 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19793 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19794 /* Right shift immediate, saturating & narrowing, with rounding variants.
19795 Types accepted S16 S32 S64 U16 U32 U64. */
19796 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19797 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19798 /* As above, unsigned. Types accepted S16 S32 S64. */
19799 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19800 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19801 /* Right shift narrowing. Types accepted I16 I32 I64. */
19802 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19803 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19804 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19805 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19806 /* CVT with optional immediate for fixed-point variant. */
19807 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19809 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19810 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19812 /* Data processing, three registers of different lengths. */
19813 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19814 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19815 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19816 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19817 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19818 /* If not scalar, fall back to neon_dyadic_long.
19819 Vector types as above, scalar types S16 S32 U16 U32. */
19820 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19821 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19822 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19823 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19824 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19825 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19826 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19827 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19828 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19829 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19830 /* Saturating doubling multiplies. Types S16 S32. */
19831 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19832 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19833 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19834 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19835 S16 S32 U16 U32. */
19836 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19838 /* Extract. Size 8. */
19839 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19840 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19842 /* Two registers, miscellaneous. */
19843 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19844 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19845 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19846 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19847 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19848 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19849 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19850 /* Vector replicate. Sizes 8 16 32. */
19851 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19852 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19853 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19854 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19855 /* VMOVN. Types I16 I32 I64. */
19856 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19857 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19858 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19859 /* VQMOVUN. Types S16 S32 S64. */
19860 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19861 /* VZIP / VUZP. Sizes 8 16 32. */
19862 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19863 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19864 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19865 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19866 /* VQABS / VQNEG. Types S8 S16 S32. */
19867 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19868 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19869 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19870 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19871 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19872 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19873 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19874 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19875 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19876 /* Reciprocal estimates. Types U32 F32. */
19877 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19878 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19879 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19880 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19881 /* VCLS. Types S8 S16 S32. */
19882 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19883 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19884 /* VCLZ. Types I8 I16 I32. */
19885 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19886 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19887 /* VCNT. Size 8. */
19888 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19889 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19890 /* Two address, untyped. */
19891 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19892 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19893 /* VTRN. Sizes 8 16 32. */
19894 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19895 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19897 /* Table lookup. Size 8. */
19898 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19899 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19901 #undef THUMB_VARIANT
19902 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19904 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19906 /* Neon element/structure load/store. */
19907 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19908 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19909 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19910 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19911 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19912 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19913 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19914 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19916 #undef THUMB_VARIANT
19917 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19919 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19920 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19921 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19922 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19923 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19924 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19925 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19926 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19927 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19928 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19930 #undef THUMB_VARIANT
19931 #define THUMB_VARIANT & fpu_vfp_ext_v3
19933 #define ARM_VARIANT & fpu_vfp_ext_v3
19935 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19936 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19937 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19938 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19939 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19940 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19941 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19942 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19943 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19946 #define ARM_VARIANT & fpu_vfp_ext_fma
19947 #undef THUMB_VARIANT
19948 #define THUMB_VARIANT & fpu_vfp_ext_fma
19949 /* Mnemonics shared by Neon and VFP. These are included in the
19950 VFP FMA variant; NEON and VFP FMA always includes the NEON
19951 FMA instructions. */
19952 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19953 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19954 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19955 the v form should always be used. */
19956 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19957 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19958 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19959 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19960 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19961 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19963 #undef THUMB_VARIANT
19965 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19967 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19968 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19969 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19970 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19971 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19972 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19973 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19974 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19977 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19979 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19980 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19981 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19982 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19983 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19984 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19985 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19986 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19987 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19988 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19989 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19990 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19991 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19992 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19993 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19994 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19995 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19996 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19997 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19998 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19999 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20000 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20001 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20002 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20003 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20004 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20005 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20006 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20007 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20008 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20009 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20010 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20011 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20012 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20013 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20014 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20015 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20016 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20017 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20018 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20019 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20020 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20021 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20022 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20023 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20024 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20025 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20026 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20027 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20028 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20029 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20030 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20031 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20032 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20033 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20034 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20035 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20036 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20037 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20038 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20039 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20040 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20041 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20042 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20043 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20044 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20045 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20046 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20047 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20048 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20049 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20050 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20051 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20052 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20053 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20054 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20055 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20056 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20057 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20058 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20059 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20060 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20061 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20062 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20063 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20064 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20065 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20066 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20067 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20068 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20069 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20070 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20071 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20072 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20073 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20074 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20075 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20076 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20077 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20078 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20079 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20080 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20081 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20082 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20083 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20084 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20085 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20086 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20087 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20088 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20089 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20090 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20091 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20092 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20093 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20094 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20095 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20096 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20097 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20098 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20099 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20100 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20101 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20102 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20103 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20104 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20105 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20106 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20107 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20108 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20109 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20110 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20111 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20112 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20113 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20114 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20115 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20116 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20117 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20118 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20119 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20120 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20121 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20122 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20123 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20124 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20125 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20126 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20127 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20128 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20129 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20130 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20131 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20132 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20133 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20134 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20135 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20136 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20137 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20138 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20139 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20140 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20143 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20145 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20146 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20147 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20148 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20149 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20150 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20151 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20152 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20153 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20154 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20155 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20156 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20157 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20158 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20159 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20160 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20161 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20162 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20163 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20164 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20165 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20166 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20167 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20168 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20169 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20170 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20171 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20172 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20173 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20174 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20175 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20176 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20177 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20178 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20179 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20180 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20181 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20182 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20183 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20184 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20185 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20186 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20187 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20188 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20189 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20190 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20191 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20192 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20193 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20194 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20195 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20196 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20197 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20198 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20199 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20200 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20201 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20204 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20206 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20207 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20208 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20209 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20210 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20211 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20212 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20213 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20214 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20215 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20216 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20217 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20218 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20219 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20220 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20221 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20222 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20223 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20224 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20225 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20226 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20227 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20228 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20229 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20230 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20231 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20232 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20233 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20234 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20235 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20236 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20237 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20238 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20239 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20240 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20241 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20242 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20243 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20244 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20245 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20246 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20247 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20248 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20249 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20250 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20251 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20252 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20253 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20254 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20255 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20256 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20257 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20258 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20259 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20260 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20261 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20262 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20263 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20264 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20265 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20266 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20267 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20268 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20269 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20270 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20271 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20272 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20273 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20274 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20275 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20276 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20277 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20278 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20279 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20280 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20281 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20284 #undef THUMB_VARIANT
20310 /* MD interface: bits in the object file. */
20312 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20313 for use in the a.out file, and stores them in the array pointed to by buf.
20314 This knows about the endian-ness of the target machine and does
20315 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20316 2 (short) and 4 (long) Floating numbers are put out as a series of
20317 LITTLENUMS (shorts, here at least). */
20320 md_number_to_chars (char * buf
, valueT val
, int n
)
20322 if (target_big_endian
)
20323 number_to_chars_bigendian (buf
, val
, n
);
20325 number_to_chars_littleendian (buf
, val
, n
);
20329 md_chars_to_number (char * buf
, int n
)
20332 unsigned char * where
= (unsigned char *) buf
;
20334 if (target_big_endian
)
20339 result
|= (*where
++ & 255);
20347 result
|= (where
[n
] & 255);
20354 /* MD interface: Sections. */
20356 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20357 that an rs_machine_dependent frag may reach. */
20360 arm_frag_max_var (fragS
*fragp
)
20362 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20363 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20365 Note that we generate relaxable instructions even for cases that don't
20366 really need it, like an immediate that's a trivial constant. So we're
20367 overestimating the instruction size for some of those cases. Rather
20368 than putting more intelligence here, it would probably be better to
20369 avoid generating a relaxation frag in the first place when it can be
20370 determined up front that a short instruction will suffice. */
20372 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20376 /* Estimate the size of a frag before relaxing. Assume everything fits in
20380 md_estimate_size_before_relax (fragS
* fragp
,
20381 segT segtype ATTRIBUTE_UNUSED
)
20387 /* Convert a machine dependent frag. */
20390 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20392 unsigned long insn
;
20393 unsigned long old_op
;
20401 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20403 old_op
= bfd_get_16(abfd
, buf
);
20404 if (fragp
->fr_symbol
)
20406 exp
.X_op
= O_symbol
;
20407 exp
.X_add_symbol
= fragp
->fr_symbol
;
20411 exp
.X_op
= O_constant
;
20413 exp
.X_add_number
= fragp
->fr_offset
;
20414 opcode
= fragp
->fr_subtype
;
20417 case T_MNEM_ldr_pc
:
20418 case T_MNEM_ldr_pc2
:
20419 case T_MNEM_ldr_sp
:
20420 case T_MNEM_str_sp
:
20427 if (fragp
->fr_var
== 4)
20429 insn
= THUMB_OP32 (opcode
);
20430 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20432 insn
|= (old_op
& 0x700) << 4;
20436 insn
|= (old_op
& 7) << 12;
20437 insn
|= (old_op
& 0x38) << 13;
20439 insn
|= 0x00000c00;
20440 put_thumb32_insn (buf
, insn
);
20441 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20445 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20447 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20450 if (fragp
->fr_var
== 4)
20452 insn
= THUMB_OP32 (opcode
);
20453 insn
|= (old_op
& 0xf0) << 4;
20454 put_thumb32_insn (buf
, insn
);
20455 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20459 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20460 exp
.X_add_number
-= 4;
20468 if (fragp
->fr_var
== 4)
20470 int r0off
= (opcode
== T_MNEM_mov
20471 || opcode
== T_MNEM_movs
) ? 0 : 8;
20472 insn
= THUMB_OP32 (opcode
);
20473 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20474 insn
|= (old_op
& 0x700) << r0off
;
20475 put_thumb32_insn (buf
, insn
);
20476 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20480 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20485 if (fragp
->fr_var
== 4)
20487 insn
= THUMB_OP32(opcode
);
20488 put_thumb32_insn (buf
, insn
);
20489 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20492 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20496 if (fragp
->fr_var
== 4)
20498 insn
= THUMB_OP32(opcode
);
20499 insn
|= (old_op
& 0xf00) << 14;
20500 put_thumb32_insn (buf
, insn
);
20501 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20504 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20507 case T_MNEM_add_sp
:
20508 case T_MNEM_add_pc
:
20509 case T_MNEM_inc_sp
:
20510 case T_MNEM_dec_sp
:
20511 if (fragp
->fr_var
== 4)
20513 /* ??? Choose between add and addw. */
20514 insn
= THUMB_OP32 (opcode
);
20515 insn
|= (old_op
& 0xf0) << 4;
20516 put_thumb32_insn (buf
, insn
);
20517 if (opcode
== T_MNEM_add_pc
)
20518 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20520 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20523 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20531 if (fragp
->fr_var
== 4)
20533 insn
= THUMB_OP32 (opcode
);
20534 insn
|= (old_op
& 0xf0) << 4;
20535 insn
|= (old_op
& 0xf) << 16;
20536 put_thumb32_insn (buf
, insn
);
20537 if (insn
& (1 << 20))
20538 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20540 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20543 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20549 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20550 (enum bfd_reloc_code_real
) reloc_type
);
20551 fixp
->fx_file
= fragp
->fr_file
;
20552 fixp
->fx_line
= fragp
->fr_line
;
20553 fragp
->fr_fix
+= fragp
->fr_var
;
20555 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20556 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20557 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20558 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20561 /* Return the size of a relaxable immediate operand instruction.
20562 SHIFT and SIZE specify the form of the allowable immediate. */
20564 relax_immediate (fragS
*fragp
, int size
, int shift
)
20570 /* ??? Should be able to do better than this. */
20571 if (fragp
->fr_symbol
)
20574 low
= (1 << shift
) - 1;
20575 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20576 offset
= fragp
->fr_offset
;
20577 /* Force misaligned offsets to 32-bit variant. */
20580 if (offset
& ~mask
)
20585 /* Get the address of a symbol during relaxation. */
20587 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20593 sym
= fragp
->fr_symbol
;
20594 sym_frag
= symbol_get_frag (sym
);
20595 know (S_GET_SEGMENT (sym
) != absolute_section
20596 || sym_frag
== &zero_address_frag
);
20597 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20599 /* If frag has yet to be reached on this pass, assume it will
20600 move by STRETCH just as we did. If this is not so, it will
20601 be because some frag between grows, and that will force
20605 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20609 /* Adjust stretch for any alignment frag. Note that if have
20610 been expanding the earlier code, the symbol may be
20611 defined in what appears to be an earlier frag. FIXME:
20612 This doesn't handle the fr_subtype field, which specifies
20613 a maximum number of bytes to skip when doing an
20615 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20617 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20620 stretch
= - ((- stretch
)
20621 & ~ ((1 << (int) f
->fr_offset
) - 1));
20623 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20635 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20638 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20643 /* Assume worst case for symbols not known to be in the same section. */
20644 if (fragp
->fr_symbol
== NULL
20645 || !S_IS_DEFINED (fragp
->fr_symbol
)
20646 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20647 || S_IS_WEAK (fragp
->fr_symbol
))
20650 val
= relaxed_symbol_addr (fragp
, stretch
);
20651 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20652 addr
= (addr
+ 4) & ~3;
20653 /* Force misaligned targets to 32-bit variant. */
20657 if (val
< 0 || val
> 1020)
20662 /* Return the size of a relaxable add/sub immediate instruction. */
20664 relax_addsub (fragS
*fragp
, asection
*sec
)
20669 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20670 op
= bfd_get_16(sec
->owner
, buf
);
20671 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20672 return relax_immediate (fragp
, 8, 0);
20674 return relax_immediate (fragp
, 3, 0);
20677 /* Return TRUE iff the definition of symbol S could be pre-empted
20678 (overridden) at link or load time. */
20680 symbol_preemptible (symbolS
*s
)
20682 /* Weak symbols can always be pre-empted. */
20686 /* Non-global symbols cannot be pre-empted. */
20687 if (! S_IS_EXTERNAL (s
))
20691 /* In ELF, a global symbol can be marked protected, or private. In that
20692 case it can't be pre-empted (other definitions in the same link unit
20693 would violate the ODR). */
20694 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20698 /* Other global symbols might be pre-empted. */
20702 /* Return the size of a relaxable branch instruction. BITS is the
20703 size of the offset field in the narrow instruction. */
20706 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20712 /* Assume worst case for symbols not known to be in the same section. */
20713 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20714 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20715 || S_IS_WEAK (fragp
->fr_symbol
))
20719 /* A branch to a function in ARM state will require interworking. */
20720 if (S_IS_DEFINED (fragp
->fr_symbol
)
20721 && ARM_IS_FUNC (fragp
->fr_symbol
))
20725 if (symbol_preemptible (fragp
->fr_symbol
))
20728 val
= relaxed_symbol_addr (fragp
, stretch
);
20729 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20732 /* Offset is a signed value *2 */
20734 if (val
>= limit
|| val
< -limit
)
20740 /* Relax a machine dependent frag. This returns the amount by which
20741 the current size of the frag should change. */
20744 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20749 oldsize
= fragp
->fr_var
;
20750 switch (fragp
->fr_subtype
)
20752 case T_MNEM_ldr_pc2
:
20753 newsize
= relax_adr (fragp
, sec
, stretch
);
20755 case T_MNEM_ldr_pc
:
20756 case T_MNEM_ldr_sp
:
20757 case T_MNEM_str_sp
:
20758 newsize
= relax_immediate (fragp
, 8, 2);
20762 newsize
= relax_immediate (fragp
, 5, 2);
20766 newsize
= relax_immediate (fragp
, 5, 1);
20770 newsize
= relax_immediate (fragp
, 5, 0);
20773 newsize
= relax_adr (fragp
, sec
, stretch
);
20779 newsize
= relax_immediate (fragp
, 8, 0);
20782 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20785 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20787 case T_MNEM_add_sp
:
20788 case T_MNEM_add_pc
:
20789 newsize
= relax_immediate (fragp
, 8, 2);
20791 case T_MNEM_inc_sp
:
20792 case T_MNEM_dec_sp
:
20793 newsize
= relax_immediate (fragp
, 7, 2);
20799 newsize
= relax_addsub (fragp
, sec
);
20805 fragp
->fr_var
= newsize
;
20806 /* Freeze wide instructions that are at or before the same location as
20807 in the previous pass. This avoids infinite loops.
20808 Don't freeze them unconditionally because targets may be artificially
20809 misaligned by the expansion of preceding frags. */
20810 if (stretch
<= 0 && newsize
> 2)
20812 md_convert_frag (sec
->owner
, sec
, fragp
);
20816 return newsize
- oldsize
;
20819 /* Round up a section size to the appropriate boundary. */
20822 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20825 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20826 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20828 /* For a.out, force the section size to be aligned. If we don't do
20829 this, BFD will align it for us, but it will not write out the
20830 final bytes of the section. This may be a bug in BFD, but it is
20831 easier to fix it here since that is how the other a.out targets
20835 align
= bfd_get_section_alignment (stdoutput
, segment
);
20836 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20843 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20844 of an rs_align_code fragment. */
20847 arm_handle_align (fragS
* fragP
)
20849 static char const arm_noop
[2][2][4] =
20852 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20853 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20856 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20857 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20860 static char const thumb_noop
[2][2][2] =
20863 {0xc0, 0x46}, /* LE */
20864 {0x46, 0xc0}, /* BE */
20867 {0x00, 0xbf}, /* LE */
20868 {0xbf, 0x00} /* BE */
20871 static char const wide_thumb_noop
[2][4] =
20872 { /* Wide Thumb-2 */
20873 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20874 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20877 unsigned bytes
, fix
, noop_size
;
20880 const char *narrow_noop
= NULL
;
20885 if (fragP
->fr_type
!= rs_align_code
)
20888 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20889 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20892 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20893 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20895 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20897 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20899 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20900 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
20902 narrow_noop
= thumb_noop
[1][target_big_endian
];
20903 noop
= wide_thumb_noop
[target_big_endian
];
20906 noop
= thumb_noop
[0][target_big_endian
];
20914 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20915 ? selected_cpu
: arm_arch_none
,
20917 [target_big_endian
];
20924 fragP
->fr_var
= noop_size
;
20926 if (bytes
& (noop_size
- 1))
20928 fix
= bytes
& (noop_size
- 1);
20930 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20932 memset (p
, 0, fix
);
20939 if (bytes
& noop_size
)
20941 /* Insert a narrow noop. */
20942 memcpy (p
, narrow_noop
, noop_size
);
20944 bytes
-= noop_size
;
20948 /* Use wide noops for the remainder */
20952 while (bytes
>= noop_size
)
20954 memcpy (p
, noop
, noop_size
);
20956 bytes
-= noop_size
;
20960 fragP
->fr_fix
+= fix
;
20963 /* Called from md_do_align. Used to create an alignment
20964 frag in a code section. */
20967 arm_frag_align_code (int n
, int max
)
20971 /* We assume that there will never be a requirement
20972 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20973 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20978 _("alignments greater than %d bytes not supported in .text sections."),
20979 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20980 as_fatal ("%s", err_msg
);
20983 p
= frag_var (rs_align_code
,
20984 MAX_MEM_FOR_RS_ALIGN_CODE
,
20986 (relax_substateT
) max
,
20993 /* Perform target specific initialisation of a frag.
20994 Note - despite the name this initialisation is not done when the frag
20995 is created, but only when its type is assigned. A frag can be created
20996 and used a long time before its type is set, so beware of assuming that
20997 this initialisationis performed first. */
21001 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21003 /* Record whether this frag is in an ARM or a THUMB area. */
21004 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21007 #else /* OBJ_ELF is defined. */
21009 arm_init_frag (fragS
* fragP
, int max_chars
)
21011 /* If the current ARM vs THUMB mode has not already
21012 been recorded into this frag then do so now. */
21013 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21015 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21017 /* Record a mapping symbol for alignment frags. We will delete this
21018 later if the alignment ends up empty. */
21019 switch (fragP
->fr_type
)
21022 case rs_align_test
:
21024 mapping_state_2 (MAP_DATA
, max_chars
);
21026 case rs_align_code
:
21027 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21035 /* When we change sections we need to issue a new mapping symbol. */
21038 arm_elf_change_section (void)
21040 /* Link an unlinked unwind index table section to the .text section. */
21041 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21042 && elf_linked_to_section (now_seg
) == NULL
)
21043 elf_linked_to_section (now_seg
) = text_section
;
21047 arm_elf_section_type (const char * str
, size_t len
)
21049 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21050 return SHT_ARM_EXIDX
;
21055 /* Code to deal with unwinding tables. */
21057 static void add_unwind_adjustsp (offsetT
);
21059 /* Generate any deferred unwind frame offset. */
21062 flush_pending_unwind (void)
21066 offset
= unwind
.pending_offset
;
21067 unwind
.pending_offset
= 0;
21069 add_unwind_adjustsp (offset
);
21072 /* Add an opcode to this list for this function. Two-byte opcodes should
21073 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21077 add_unwind_opcode (valueT op
, int length
)
21079 /* Add any deferred stack adjustment. */
21080 if (unwind
.pending_offset
)
21081 flush_pending_unwind ();
21083 unwind
.sp_restored
= 0;
21085 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21087 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21088 if (unwind
.opcodes
)
21089 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21090 unwind
.opcode_alloc
);
21092 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21097 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21099 unwind
.opcode_count
++;
21103 /* Add unwind opcodes to adjust the stack pointer. */
21106 add_unwind_adjustsp (offsetT offset
)
21110 if (offset
> 0x200)
21112 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21117 /* Long form: 0xb2, uleb128. */
21118 /* This might not fit in a word so add the individual bytes,
21119 remembering the list is built in reverse order. */
21120 o
= (valueT
) ((offset
- 0x204) >> 2);
21122 add_unwind_opcode (0, 1);
21124 /* Calculate the uleb128 encoding of the offset. */
21128 bytes
[n
] = o
& 0x7f;
21134 /* Add the insn. */
21136 add_unwind_opcode (bytes
[n
- 1], 1);
21137 add_unwind_opcode (0xb2, 1);
21139 else if (offset
> 0x100)
21141 /* Two short opcodes. */
21142 add_unwind_opcode (0x3f, 1);
21143 op
= (offset
- 0x104) >> 2;
21144 add_unwind_opcode (op
, 1);
21146 else if (offset
> 0)
21148 /* Short opcode. */
21149 op
= (offset
- 4) >> 2;
21150 add_unwind_opcode (op
, 1);
21152 else if (offset
< 0)
21155 while (offset
> 0x100)
21157 add_unwind_opcode (0x7f, 1);
21160 op
= ((offset
- 4) >> 2) | 0x40;
21161 add_unwind_opcode (op
, 1);
21165 /* Finish the list of unwind opcodes for this function. */
21167 finish_unwind_opcodes (void)
21171 if (unwind
.fp_used
)
21173 /* Adjust sp as necessary. */
21174 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21175 flush_pending_unwind ();
21177 /* After restoring sp from the frame pointer. */
21178 op
= 0x90 | unwind
.fp_reg
;
21179 add_unwind_opcode (op
, 1);
21182 flush_pending_unwind ();
21186 /* Start an exception table entry. If idx is nonzero this is an index table
21190 start_unwind_section (const segT text_seg
, int idx
)
21192 const char * text_name
;
21193 const char * prefix
;
21194 const char * prefix_once
;
21195 const char * group_name
;
21199 size_t sec_name_len
;
21206 prefix
= ELF_STRING_ARM_unwind
;
21207 prefix_once
= ELF_STRING_ARM_unwind_once
;
21208 type
= SHT_ARM_EXIDX
;
21212 prefix
= ELF_STRING_ARM_unwind_info
;
21213 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21214 type
= SHT_PROGBITS
;
21217 text_name
= segment_name (text_seg
);
21218 if (streq (text_name
, ".text"))
21221 if (strncmp (text_name
, ".gnu.linkonce.t.",
21222 strlen (".gnu.linkonce.t.")) == 0)
21224 prefix
= prefix_once
;
21225 text_name
+= strlen (".gnu.linkonce.t.");
21228 prefix_len
= strlen (prefix
);
21229 text_len
= strlen (text_name
);
21230 sec_name_len
= prefix_len
+ text_len
;
21231 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21232 memcpy (sec_name
, prefix
, prefix_len
);
21233 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21234 sec_name
[prefix_len
+ text_len
] = '\0';
21240 /* Handle COMDAT group. */
21241 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21243 group_name
= elf_group_name (text_seg
);
21244 if (group_name
== NULL
)
21246 as_bad (_("Group section `%s' has no group signature"),
21247 segment_name (text_seg
));
21248 ignore_rest_of_line ();
21251 flags
|= SHF_GROUP
;
21255 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21257 /* Set the section link for index tables. */
21259 elf_linked_to_section (now_seg
) = text_seg
;
21263 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21264 personality routine data. Returns zero, or the index table value for
21265 an inline entry. */
21268 create_unwind_entry (int have_data
)
21273 /* The current word of data. */
21275 /* The number of bytes left in this word. */
21278 finish_unwind_opcodes ();
21280 /* Remember the current text section. */
21281 unwind
.saved_seg
= now_seg
;
21282 unwind
.saved_subseg
= now_subseg
;
21284 start_unwind_section (now_seg
, 0);
21286 if (unwind
.personality_routine
== NULL
)
21288 if (unwind
.personality_index
== -2)
21291 as_bad (_("handlerdata in cantunwind frame"));
21292 return 1; /* EXIDX_CANTUNWIND. */
21295 /* Use a default personality routine if none is specified. */
21296 if (unwind
.personality_index
== -1)
21298 if (unwind
.opcode_count
> 3)
21299 unwind
.personality_index
= 1;
21301 unwind
.personality_index
= 0;
21304 /* Space for the personality routine entry. */
21305 if (unwind
.personality_index
== 0)
21307 if (unwind
.opcode_count
> 3)
21308 as_bad (_("too many unwind opcodes for personality routine 0"));
21312 /* All the data is inline in the index table. */
21315 while (unwind
.opcode_count
> 0)
21317 unwind
.opcode_count
--;
21318 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21322 /* Pad with "finish" opcodes. */
21324 data
= (data
<< 8) | 0xb0;
21331 /* We get two opcodes "free" in the first word. */
21332 size
= unwind
.opcode_count
- 2;
21336 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21337 if (unwind
.personality_index
!= -1)
21339 as_bad (_("attempt to recreate an unwind entry"));
21343 /* An extra byte is required for the opcode count. */
21344 size
= unwind
.opcode_count
+ 1;
21347 size
= (size
+ 3) >> 2;
21349 as_bad (_("too many unwind opcodes"));
21351 frag_align (2, 0, 0);
21352 record_alignment (now_seg
, 2);
21353 unwind
.table_entry
= expr_build_dot ();
21355 /* Allocate the table entry. */
21356 ptr
= frag_more ((size
<< 2) + 4);
21357 /* PR 13449: Zero the table entries in case some of them are not used. */
21358 memset (ptr
, 0, (size
<< 2) + 4);
21359 where
= frag_now_fix () - ((size
<< 2) + 4);
21361 switch (unwind
.personality_index
)
21364 /* ??? Should this be a PLT generating relocation? */
21365 /* Custom personality routine. */
21366 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21367 BFD_RELOC_ARM_PREL31
);
21372 /* Set the first byte to the number of additional words. */
21373 data
= size
> 0 ? size
- 1 : 0;
21377 /* ABI defined personality routines. */
21379 /* Three opcodes bytes are packed into the first word. */
21386 /* The size and first two opcode bytes go in the first word. */
21387 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21392 /* Should never happen. */
21396 /* Pack the opcodes into words (MSB first), reversing the list at the same
21398 while (unwind
.opcode_count
> 0)
21402 md_number_to_chars (ptr
, data
, 4);
21407 unwind
.opcode_count
--;
21409 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21412 /* Finish off the last word. */
21415 /* Pad with "finish" opcodes. */
21417 data
= (data
<< 8) | 0xb0;
21419 md_number_to_chars (ptr
, data
, 4);
21424 /* Add an empty descriptor if there is no user-specified data. */
21425 ptr
= frag_more (4);
21426 md_number_to_chars (ptr
, 0, 4);
21433 /* Initialize the DWARF-2 unwind information for this procedure. */
21436 tc_arm_frame_initial_instructions (void)
21438 cfi_add_CFA_def_cfa (REG_SP
, 0);
21440 #endif /* OBJ_ELF */
21442 /* Convert REGNAME to a DWARF-2 register number. */
21445 tc_arm_regname_to_dw2regnum (char *regname
)
21447 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21451 /* PR 16694: Allow VFP registers as well. */
21452 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21456 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21465 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21469 exp
.X_op
= O_secrel
;
21470 exp
.X_add_symbol
= symbol
;
21471 exp
.X_add_number
= 0;
21472 emit_expr (&exp
, size
);
21476 /* MD interface: Symbol and relocation handling. */
21478 /* Return the address within the segment that a PC-relative fixup is
21479 relative to. For ARM, PC-relative fixups applied to instructions
21480 are generally relative to the location of the fixup plus 8 bytes.
21481 Thumb branches are offset by 4, and Thumb loads relative to PC
21482 require special handling. */
21485 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21487 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21489 /* If this is pc-relative and we are going to emit a relocation
21490 then we just want to put out any pipeline compensation that the linker
21491 will need. Otherwise we want to use the calculated base.
21492 For WinCE we skip the bias for externals as well, since this
21493 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21495 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21496 || (arm_force_relocation (fixP
)
21498 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21504 switch (fixP
->fx_r_type
)
21506 /* PC relative addressing on the Thumb is slightly odd as the
21507 bottom two bits of the PC are forced to zero for the
21508 calculation. This happens *after* application of the
21509 pipeline offset. However, Thumb adrl already adjusts for
21510 this, so we need not do it again. */
21511 case BFD_RELOC_ARM_THUMB_ADD
:
21514 case BFD_RELOC_ARM_THUMB_OFFSET
:
21515 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21516 case BFD_RELOC_ARM_T32_ADD_PC12
:
21517 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21518 return (base
+ 4) & ~3;
21520 /* Thumb branches are simply offset by +4. */
21521 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21522 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21523 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21524 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21525 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21528 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21530 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21531 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21532 && ARM_IS_FUNC (fixP
->fx_addsy
)
21533 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21534 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21537 /* BLX is like branches above, but forces the low two bits of PC to
21539 case BFD_RELOC_THUMB_PCREL_BLX
:
21541 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21542 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21543 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21544 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21545 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21546 return (base
+ 4) & ~3;
21548 /* ARM mode branches are offset by +8. However, the Windows CE
21549 loader expects the relocation not to take this into account. */
21550 case BFD_RELOC_ARM_PCREL_BLX
:
21552 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21553 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21554 && ARM_IS_FUNC (fixP
->fx_addsy
)
21555 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21556 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21559 case BFD_RELOC_ARM_PCREL_CALL
:
21561 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21562 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21563 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21564 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21565 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21568 case BFD_RELOC_ARM_PCREL_BRANCH
:
21569 case BFD_RELOC_ARM_PCREL_JUMP
:
21570 case BFD_RELOC_ARM_PLT32
:
21572 /* When handling fixups immediately, because we have already
21573 discovered the value of a symbol, or the address of the frag involved
21574 we must account for the offset by +8, as the OS loader will never see the reloc.
21575 see fixup_segment() in write.c
21576 The S_IS_EXTERNAL test handles the case of global symbols.
21577 Those need the calculated base, not just the pipe compensation the linker will need. */
21579 && fixP
->fx_addsy
!= NULL
21580 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21581 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21589 /* ARM mode loads relative to PC are also offset by +8. Unlike
21590 branches, the Windows CE loader *does* expect the relocation
21591 to take this into account. */
21592 case BFD_RELOC_ARM_OFFSET_IMM
:
21593 case BFD_RELOC_ARM_OFFSET_IMM8
:
21594 case BFD_RELOC_ARM_HWLITERAL
:
21595 case BFD_RELOC_ARM_LITERAL
:
21596 case BFD_RELOC_ARM_CP_OFF_IMM
:
21600 /* Other PC-relative relocations are un-offset. */
21606 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21607 Otherwise we have no need to default values of symbols. */
21610 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21613 if (name
[0] == '_' && name
[1] == 'G'
21614 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21618 if (symbol_find (name
))
21619 as_bad (_("GOT already in the symbol table"));
21621 GOT_symbol
= symbol_new (name
, undefined_section
,
21622 (valueT
) 0, & zero_address_frag
);
21632 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21633 computed as two separate immediate values, added together. We
21634 already know that this value cannot be computed by just one ARM
21637 static unsigned int
21638 validate_immediate_twopart (unsigned int val
,
21639 unsigned int * highpart
)
21644 for (i
= 0; i
< 32; i
+= 2)
21645 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21651 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21653 else if (a
& 0xff0000)
21655 if (a
& 0xff000000)
21657 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21661 gas_assert (a
& 0xff000000);
21662 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21665 return (a
& 0xff) | (i
<< 7);
21672 validate_offset_imm (unsigned int val
, int hwse
)
21674 if ((hwse
&& val
> 255) || val
> 4095)
21679 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21680 negative immediate constant by altering the instruction. A bit of
21685 by inverting the second operand, and
21688 by negating the second operand. */
21691 negate_data_op (unsigned long * instruction
,
21692 unsigned long value
)
21695 unsigned long negated
, inverted
;
21697 negated
= encode_arm_immediate (-value
);
21698 inverted
= encode_arm_immediate (~value
);
21700 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21703 /* First negates. */
21704 case OPCODE_SUB
: /* ADD <-> SUB */
21705 new_inst
= OPCODE_ADD
;
21710 new_inst
= OPCODE_SUB
;
21714 case OPCODE_CMP
: /* CMP <-> CMN */
21715 new_inst
= OPCODE_CMN
;
21720 new_inst
= OPCODE_CMP
;
21724 /* Now Inverted ops. */
21725 case OPCODE_MOV
: /* MOV <-> MVN */
21726 new_inst
= OPCODE_MVN
;
21731 new_inst
= OPCODE_MOV
;
21735 case OPCODE_AND
: /* AND <-> BIC */
21736 new_inst
= OPCODE_BIC
;
21741 new_inst
= OPCODE_AND
;
21745 case OPCODE_ADC
: /* ADC <-> SBC */
21746 new_inst
= OPCODE_SBC
;
21751 new_inst
= OPCODE_ADC
;
21755 /* We cannot do anything. */
21760 if (value
== (unsigned) FAIL
)
21763 *instruction
&= OPCODE_MASK
;
21764 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21768 /* Like negate_data_op, but for Thumb-2. */
21770 static unsigned int
21771 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21775 unsigned int negated
, inverted
;
21777 negated
= encode_thumb32_immediate (-value
);
21778 inverted
= encode_thumb32_immediate (~value
);
21780 rd
= (*instruction
>> 8) & 0xf;
21781 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21784 /* ADD <-> SUB. Includes CMP <-> CMN. */
21785 case T2_OPCODE_SUB
:
21786 new_inst
= T2_OPCODE_ADD
;
21790 case T2_OPCODE_ADD
:
21791 new_inst
= T2_OPCODE_SUB
;
21795 /* ORR <-> ORN. Includes MOV <-> MVN. */
21796 case T2_OPCODE_ORR
:
21797 new_inst
= T2_OPCODE_ORN
;
21801 case T2_OPCODE_ORN
:
21802 new_inst
= T2_OPCODE_ORR
;
21806 /* AND <-> BIC. TST has no inverted equivalent. */
21807 case T2_OPCODE_AND
:
21808 new_inst
= T2_OPCODE_BIC
;
21815 case T2_OPCODE_BIC
:
21816 new_inst
= T2_OPCODE_AND
;
21821 case T2_OPCODE_ADC
:
21822 new_inst
= T2_OPCODE_SBC
;
21826 case T2_OPCODE_SBC
:
21827 new_inst
= T2_OPCODE_ADC
;
21831 /* We cannot do anything. */
21836 if (value
== (unsigned int)FAIL
)
21839 *instruction
&= T2_OPCODE_MASK
;
21840 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21844 /* Read a 32-bit thumb instruction from buf. */
21845 static unsigned long
21846 get_thumb32_insn (char * buf
)
21848 unsigned long insn
;
21849 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21850 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21856 /* We usually want to set the low bit on the address of thumb function
21857 symbols. In particular .word foo - . should have the low bit set.
21858 Generic code tries to fold the difference of two symbols to
21859 a constant. Prevent this and force a relocation when the first symbols
21860 is a thumb function. */
21863 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21865 if (op
== O_subtract
21866 && l
->X_op
== O_symbol
21867 && r
->X_op
== O_symbol
21868 && THUMB_IS_FUNC (l
->X_add_symbol
))
21870 l
->X_op
= O_subtract
;
21871 l
->X_op_symbol
= r
->X_add_symbol
;
21872 l
->X_add_number
-= r
->X_add_number
;
21876 /* Process as normal. */
21880 /* Encode Thumb2 unconditional branches and calls. The encoding
21881 for the 2 are identical for the immediate values. */
21884 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21886 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21889 addressT S
, I1
, I2
, lo
, hi
;
21891 S
= (value
>> 24) & 0x01;
21892 I1
= (value
>> 23) & 0x01;
21893 I2
= (value
>> 22) & 0x01;
21894 hi
= (value
>> 12) & 0x3ff;
21895 lo
= (value
>> 1) & 0x7ff;
21896 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21897 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21898 newval
|= (S
<< 10) | hi
;
21899 newval2
&= ~T2I1I2MASK
;
21900 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21901 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21902 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21906 md_apply_fix (fixS
* fixP
,
21910 offsetT value
= * valP
;
21912 unsigned int newimm
;
21913 unsigned long temp
;
21915 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21917 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21919 /* Note whether this will delete the relocation. */
21921 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21924 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21925 consistency with the behaviour on 32-bit hosts. Remember value
21927 value
&= 0xffffffff;
21928 value
^= 0x80000000;
21929 value
-= 0x80000000;
21932 fixP
->fx_addnumber
= value
;
21934 /* Same treatment for fixP->fx_offset. */
21935 fixP
->fx_offset
&= 0xffffffff;
21936 fixP
->fx_offset
^= 0x80000000;
21937 fixP
->fx_offset
-= 0x80000000;
21939 switch (fixP
->fx_r_type
)
21941 case BFD_RELOC_NONE
:
21942 /* This will need to go in the object file. */
21946 case BFD_RELOC_ARM_IMMEDIATE
:
21947 /* We claim that this fixup has been processed here,
21948 even if in fact we generate an error because we do
21949 not have a reloc for it, so tc_gen_reloc will reject it. */
21952 if (fixP
->fx_addsy
)
21954 const char *msg
= 0;
21956 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21957 msg
= _("undefined symbol %s used as an immediate value");
21958 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21959 msg
= _("symbol %s is in a different section");
21960 else if (S_IS_WEAK (fixP
->fx_addsy
))
21961 msg
= _("symbol %s is weak and may be overridden later");
21965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21966 msg
, S_GET_NAME (fixP
->fx_addsy
));
21971 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21973 /* If the offset is negative, we should use encoding A2 for ADR. */
21974 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21975 newimm
= negate_data_op (&temp
, value
);
21978 newimm
= encode_arm_immediate (value
);
21980 /* If the instruction will fail, see if we can fix things up by
21981 changing the opcode. */
21982 if (newimm
== (unsigned int) FAIL
)
21983 newimm
= negate_data_op (&temp
, value
);
21986 if (newimm
== (unsigned int) FAIL
)
21988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21989 _("invalid constant (%lx) after fixup"),
21990 (unsigned long) value
);
21994 newimm
|= (temp
& 0xfffff000);
21995 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21998 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22000 unsigned int highpart
= 0;
22001 unsigned int newinsn
= 0xe1a00000; /* nop. */
22003 if (fixP
->fx_addsy
)
22005 const char *msg
= 0;
22007 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22008 msg
= _("undefined symbol %s used as an immediate value");
22009 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22010 msg
= _("symbol %s is in a different section");
22011 else if (S_IS_WEAK (fixP
->fx_addsy
))
22012 msg
= _("symbol %s is weak and may be overridden later");
22016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22017 msg
, S_GET_NAME (fixP
->fx_addsy
));
22022 newimm
= encode_arm_immediate (value
);
22023 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22025 /* If the instruction will fail, see if we can fix things up by
22026 changing the opcode. */
22027 if (newimm
== (unsigned int) FAIL
22028 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22030 /* No ? OK - try using two ADD instructions to generate
22032 newimm
= validate_immediate_twopart (value
, & highpart
);
22034 /* Yes - then make sure that the second instruction is
22036 if (newimm
!= (unsigned int) FAIL
)
22038 /* Still No ? Try using a negated value. */
22039 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22040 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22041 /* Otherwise - give up. */
22044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22045 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22050 /* Replace the first operand in the 2nd instruction (which
22051 is the PC) with the destination register. We have
22052 already added in the PC in the first instruction and we
22053 do not want to do it again. */
22054 newinsn
&= ~ 0xf0000;
22055 newinsn
|= ((newinsn
& 0x0f000) << 4);
22058 newimm
|= (temp
& 0xfffff000);
22059 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22061 highpart
|= (newinsn
& 0xfffff000);
22062 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22066 case BFD_RELOC_ARM_OFFSET_IMM
:
22067 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22070 case BFD_RELOC_ARM_LITERAL
:
22076 if (validate_offset_imm (value
, 0) == FAIL
)
22078 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22080 _("invalid literal constant: pool needs to be closer"));
22082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22083 _("bad immediate value for offset (%ld)"),
22088 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22090 newval
&= 0xfffff000;
22093 newval
&= 0xff7ff000;
22094 newval
|= value
| (sign
? INDEX_UP
: 0);
22096 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22099 case BFD_RELOC_ARM_OFFSET_IMM8
:
22100 case BFD_RELOC_ARM_HWLITERAL
:
22106 if (validate_offset_imm (value
, 1) == FAIL
)
22108 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22110 _("invalid literal constant: pool needs to be closer"));
22112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22113 _("bad immediate value for 8-bit offset (%ld)"),
22118 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22120 newval
&= 0xfffff0f0;
22123 newval
&= 0xff7ff0f0;
22124 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22126 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22129 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22130 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22132 _("bad immediate value for offset (%ld)"), (long) value
);
22135 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22137 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22140 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22141 /* This is a complicated relocation used for all varieties of Thumb32
22142 load/store instruction with immediate offset:
22144 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22145 *4, optional writeback(W)
22146 (doubleword load/store)
22148 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22149 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22150 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22151 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22152 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22154 Uppercase letters indicate bits that are already encoded at
22155 this point. Lowercase letters are our problem. For the
22156 second block of instructions, the secondary opcode nybble
22157 (bits 8..11) is present, and bit 23 is zero, even if this is
22158 a PC-relative operation. */
22159 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22161 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22163 if ((newval
& 0xf0000000) == 0xe0000000)
22165 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22167 newval
|= (1 << 23);
22170 if (value
% 4 != 0)
22172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22173 _("offset not a multiple of 4"));
22179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22180 _("offset out of range"));
22185 else if ((newval
& 0x000f0000) == 0x000f0000)
22187 /* PC-relative, 12-bit offset. */
22189 newval
|= (1 << 23);
22194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22195 _("offset out of range"));
22200 else if ((newval
& 0x00000100) == 0x00000100)
22202 /* Writeback: 8-bit, +/- offset. */
22204 newval
|= (1 << 9);
22209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22210 _("offset out of range"));
22215 else if ((newval
& 0x00000f00) == 0x00000e00)
22217 /* T-instruction: positive 8-bit offset. */
22218 if (value
< 0 || value
> 0xff)
22220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22221 _("offset out of range"));
22229 /* Positive 12-bit or negative 8-bit offset. */
22233 newval
|= (1 << 23);
22243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22244 _("offset out of range"));
22251 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22252 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22255 case BFD_RELOC_ARM_SHIFT_IMM
:
22256 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22257 if (((unsigned long) value
) > 32
22259 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22262 _("shift expression is too large"));
22267 /* Shifts of zero must be done as lsl. */
22269 else if (value
== 32)
22271 newval
&= 0xfffff07f;
22272 newval
|= (value
& 0x1f) << 7;
22273 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22276 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22277 case BFD_RELOC_ARM_T32_ADD_IMM
:
22278 case BFD_RELOC_ARM_T32_IMM12
:
22279 case BFD_RELOC_ARM_T32_ADD_PC12
:
22280 /* We claim that this fixup has been processed here,
22281 even if in fact we generate an error because we do
22282 not have a reloc for it, so tc_gen_reloc will reject it. */
22286 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22289 _("undefined symbol %s used as an immediate value"),
22290 S_GET_NAME (fixP
->fx_addsy
));
22294 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22296 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22299 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22300 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22302 newimm
= encode_thumb32_immediate (value
);
22303 if (newimm
== (unsigned int) FAIL
)
22304 newimm
= thumb32_negate_data_op (&newval
, value
);
22306 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22307 && newimm
== (unsigned int) FAIL
)
22309 /* Turn add/sum into addw/subw. */
22310 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22311 newval
= (newval
& 0xfeffffff) | 0x02000000;
22312 /* No flat 12-bit imm encoding for addsw/subsw. */
22313 if ((newval
& 0x00100000) == 0)
22315 /* 12 bit immediate for addw/subw. */
22319 newval
^= 0x00a00000;
22322 newimm
= (unsigned int) FAIL
;
22328 if (newimm
== (unsigned int)FAIL
)
22330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22331 _("invalid constant (%lx) after fixup"),
22332 (unsigned long) value
);
22336 newval
|= (newimm
& 0x800) << 15;
22337 newval
|= (newimm
& 0x700) << 4;
22338 newval
|= (newimm
& 0x0ff);
22340 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22341 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22344 case BFD_RELOC_ARM_SMC
:
22345 if (((unsigned long) value
) > 0xffff)
22346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22347 _("invalid smc expression"));
22348 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22349 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22350 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22353 case BFD_RELOC_ARM_HVC
:
22354 if (((unsigned long) value
) > 0xffff)
22355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22356 _("invalid hvc expression"));
22357 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22358 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22359 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22362 case BFD_RELOC_ARM_SWI
:
22363 if (fixP
->tc_fix_data
!= 0)
22365 if (((unsigned long) value
) > 0xff)
22366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22367 _("invalid swi expression"));
22368 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22370 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22374 if (((unsigned long) value
) > 0x00ffffff)
22375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22376 _("invalid swi expression"));
22377 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22379 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22383 case BFD_RELOC_ARM_MULTI
:
22384 if (((unsigned long) value
) > 0xffff)
22385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22386 _("invalid expression in load/store multiple"));
22387 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22388 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22392 case BFD_RELOC_ARM_PCREL_CALL
:
22394 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22396 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22397 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22398 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22399 /* Flip the bl to blx. This is a simple flip
22400 bit here because we generate PCREL_CALL for
22401 unconditional bls. */
22403 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22404 newval
= newval
| 0x10000000;
22405 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22411 goto arm_branch_common
;
22413 case BFD_RELOC_ARM_PCREL_JUMP
:
22414 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22416 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22417 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22418 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22420 /* This would map to a bl<cond>, b<cond>,
22421 b<always> to a Thumb function. We
22422 need to force a relocation for this particular
22424 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22428 case BFD_RELOC_ARM_PLT32
:
22430 case BFD_RELOC_ARM_PCREL_BRANCH
:
22432 goto arm_branch_common
;
22434 case BFD_RELOC_ARM_PCREL_BLX
:
22437 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22439 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22440 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22441 && ARM_IS_FUNC (fixP
->fx_addsy
))
22443 /* Flip the blx to a bl and warn. */
22444 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22445 newval
= 0xeb000000;
22446 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22447 _("blx to '%s' an ARM ISA state function changed to bl"),
22449 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22455 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22456 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22460 /* We are going to store value (shifted right by two) in the
22461 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22462 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22463 also be be clear. */
22465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22466 _("misaligned branch destination"));
22467 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22468 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22471 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22473 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22474 newval
|= (value
>> 2) & 0x00ffffff;
22475 /* Set the H bit on BLX instructions. */
22479 newval
|= 0x01000000;
22481 newval
&= ~0x01000000;
22483 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22487 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22488 /* CBZ can only branch forward. */
22490 /* Attempts to use CBZ to branch to the next instruction
22491 (which, strictly speaking, are prohibited) will be turned into
22494 FIXME: It may be better to remove the instruction completely and
22495 perform relaxation. */
22498 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22499 newval
= 0xbf00; /* NOP encoding T1 */
22500 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22507 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22509 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22510 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22511 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22516 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22517 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22520 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22522 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22523 newval
|= (value
& 0x1ff) >> 1;
22524 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22528 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22529 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22532 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22534 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22535 newval
|= (value
& 0xfff) >> 1;
22536 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22540 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22542 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22543 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22544 && ARM_IS_FUNC (fixP
->fx_addsy
)
22545 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22547 /* Force a relocation for a branch 20 bits wide. */
22550 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22552 _("conditional branch out of range"));
22554 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22557 addressT S
, J1
, J2
, lo
, hi
;
22559 S
= (value
& 0x00100000) >> 20;
22560 J2
= (value
& 0x00080000) >> 19;
22561 J1
= (value
& 0x00040000) >> 18;
22562 hi
= (value
& 0x0003f000) >> 12;
22563 lo
= (value
& 0x00000ffe) >> 1;
22565 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22566 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22567 newval
|= (S
<< 10) | hi
;
22568 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22569 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22570 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22574 case BFD_RELOC_THUMB_PCREL_BLX
:
22575 /* If there is a blx from a thumb state function to
22576 another thumb function flip this to a bl and warn
22580 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22581 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22582 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22584 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22585 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22586 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22588 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22589 newval
= newval
| 0x1000;
22590 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22591 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22596 goto thumb_bl_common
;
22598 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22599 /* A bl from Thumb state ISA to an internal ARM state function
22600 is converted to a blx. */
22602 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22603 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22604 && ARM_IS_FUNC (fixP
->fx_addsy
)
22605 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22607 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22608 newval
= newval
& ~0x1000;
22609 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22610 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22616 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22617 /* For a BLX instruction, make sure that the relocation is rounded up
22618 to a word boundary. This follows the semantics of the instruction
22619 which specifies that bit 1 of the target address will come from bit
22620 1 of the base address. */
22621 value
= (value
+ 3) & ~ 3;
22624 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22625 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22626 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22629 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22631 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22633 else if ((value
& ~0x1ffffff)
22634 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22636 _("Thumb2 branch out of range"));
22639 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22640 encode_thumb2_b_bl_offset (buf
, value
);
22644 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22645 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22649 encode_thumb2_b_bl_offset (buf
, value
);
22654 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22659 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22660 md_number_to_chars (buf
, value
, 2);
22664 case BFD_RELOC_ARM_TLS_CALL
:
22665 case BFD_RELOC_ARM_THM_TLS_CALL
:
22666 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22667 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22668 case BFD_RELOC_ARM_TLS_GOTDESC
:
22669 case BFD_RELOC_ARM_TLS_GD32
:
22670 case BFD_RELOC_ARM_TLS_LE32
:
22671 case BFD_RELOC_ARM_TLS_IE32
:
22672 case BFD_RELOC_ARM_TLS_LDM32
:
22673 case BFD_RELOC_ARM_TLS_LDO32
:
22674 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22677 case BFD_RELOC_ARM_GOT32
:
22678 case BFD_RELOC_ARM_GOTOFF
:
22681 case BFD_RELOC_ARM_GOT_PREL
:
22682 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22683 md_number_to_chars (buf
, value
, 4);
22686 case BFD_RELOC_ARM_TARGET2
:
22687 /* TARGET2 is not partial-inplace, so we need to write the
22688 addend here for REL targets, because it won't be written out
22689 during reloc processing later. */
22690 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22691 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22695 case BFD_RELOC_RVA
:
22697 case BFD_RELOC_ARM_TARGET1
:
22698 case BFD_RELOC_ARM_ROSEGREL32
:
22699 case BFD_RELOC_ARM_SBREL32
:
22700 case BFD_RELOC_32_PCREL
:
22702 case BFD_RELOC_32_SECREL
:
22704 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22706 /* For WinCE we only do this for pcrel fixups. */
22707 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22709 md_number_to_chars (buf
, value
, 4);
22713 case BFD_RELOC_ARM_PREL31
:
22714 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22716 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22717 if ((value
^ (value
>> 1)) & 0x40000000)
22719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22720 _("rel31 relocation overflow"));
22722 newval
|= value
& 0x7fffffff;
22723 md_number_to_chars (buf
, newval
, 4);
22728 case BFD_RELOC_ARM_CP_OFF_IMM
:
22729 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22730 if (value
< -1023 || value
> 1023 || (value
& 3))
22731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22732 _("co-processor offset out of range"));
22737 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22738 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22739 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22741 newval
= get_thumb32_insn (buf
);
22743 newval
&= 0xffffff00;
22746 newval
&= 0xff7fff00;
22747 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22749 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22750 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22751 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22753 put_thumb32_insn (buf
, newval
);
22756 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22757 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22758 if (value
< -255 || value
> 255)
22759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22760 _("co-processor offset out of range"));
22762 goto cp_off_common
;
22764 case BFD_RELOC_ARM_THUMB_OFFSET
:
22765 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22766 /* Exactly what ranges, and where the offset is inserted depends
22767 on the type of instruction, we can establish this from the
22769 switch (newval
>> 12)
22771 case 4: /* PC load. */
22772 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22773 forced to zero for these loads; md_pcrel_from has already
22774 compensated for this. */
22776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22777 _("invalid offset, target not word aligned (0x%08lX)"),
22778 (((unsigned long) fixP
->fx_frag
->fr_address
22779 + (unsigned long) fixP
->fx_where
) & ~3)
22780 + (unsigned long) value
);
22782 if (value
& ~0x3fc)
22783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22784 _("invalid offset, value too big (0x%08lX)"),
22787 newval
|= value
>> 2;
22790 case 9: /* SP load/store. */
22791 if (value
& ~0x3fc)
22792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22793 _("invalid offset, value too big (0x%08lX)"),
22795 newval
|= value
>> 2;
22798 case 6: /* Word load/store. */
22800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22801 _("invalid offset, value too big (0x%08lX)"),
22803 newval
|= value
<< 4; /* 6 - 2. */
22806 case 7: /* Byte load/store. */
22808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22809 _("invalid offset, value too big (0x%08lX)"),
22811 newval
|= value
<< 6;
22814 case 8: /* Halfword load/store. */
22816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22817 _("invalid offset, value too big (0x%08lX)"),
22819 newval
|= value
<< 5; /* 6 - 1. */
22823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22824 "Unable to process relocation for thumb opcode: %lx",
22825 (unsigned long) newval
);
22828 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22831 case BFD_RELOC_ARM_THUMB_ADD
:
22832 /* This is a complicated relocation, since we use it for all of
22833 the following immediate relocations:
22837 9bit ADD/SUB SP word-aligned
22838 10bit ADD PC/SP word-aligned
22840 The type of instruction being processed is encoded in the
22847 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22849 int rd
= (newval
>> 4) & 0xf;
22850 int rs
= newval
& 0xf;
22851 int subtract
= !!(newval
& 0x8000);
22853 /* Check for HI regs, only very restricted cases allowed:
22854 Adjusting SP, and using PC or SP to get an address. */
22855 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22856 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22858 _("invalid Hi register with immediate"));
22860 /* If value is negative, choose the opposite instruction. */
22864 subtract
= !subtract
;
22866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22867 _("immediate value out of range"));
22872 if (value
& ~0x1fc)
22873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22874 _("invalid immediate for stack address calculation"));
22875 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22876 newval
|= value
>> 2;
22878 else if (rs
== REG_PC
|| rs
== REG_SP
)
22880 if (subtract
|| value
& ~0x3fc)
22881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22882 _("invalid immediate for address calculation (value = 0x%08lX)"),
22883 (unsigned long) value
);
22884 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22886 newval
|= value
>> 2;
22891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22892 _("immediate value out of range"));
22893 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22894 newval
|= (rd
<< 8) | value
;
22899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22900 _("immediate value out of range"));
22901 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22902 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22905 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22908 case BFD_RELOC_ARM_THUMB_IMM
:
22909 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22910 if (value
< 0 || value
> 255)
22911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22912 _("invalid immediate: %ld is out of range"),
22915 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22918 case BFD_RELOC_ARM_THUMB_SHIFT
:
22919 /* 5bit shift value (0..32). LSL cannot take 32. */
22920 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22921 temp
= newval
& 0xf800;
22922 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22924 _("invalid shift value: %ld"), (long) value
);
22925 /* Shifts of zero must be encoded as LSL. */
22927 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22928 /* Shifts of 32 are encoded as zero. */
22929 else if (value
== 32)
22931 newval
|= value
<< 6;
22932 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22935 case BFD_RELOC_VTABLE_INHERIT
:
22936 case BFD_RELOC_VTABLE_ENTRY
:
22940 case BFD_RELOC_ARM_MOVW
:
22941 case BFD_RELOC_ARM_MOVT
:
22942 case BFD_RELOC_ARM_THUMB_MOVW
:
22943 case BFD_RELOC_ARM_THUMB_MOVT
:
22944 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22946 /* REL format relocations are limited to a 16-bit addend. */
22947 if (!fixP
->fx_done
)
22949 if (value
< -0x8000 || value
> 0x7fff)
22950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22951 _("offset out of range"));
22953 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22954 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22959 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22960 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22962 newval
= get_thumb32_insn (buf
);
22963 newval
&= 0xfbf08f00;
22964 newval
|= (value
& 0xf000) << 4;
22965 newval
|= (value
& 0x0800) << 15;
22966 newval
|= (value
& 0x0700) << 4;
22967 newval
|= (value
& 0x00ff);
22968 put_thumb32_insn (buf
, newval
);
22972 newval
= md_chars_to_number (buf
, 4);
22973 newval
&= 0xfff0f000;
22974 newval
|= value
& 0x0fff;
22975 newval
|= (value
& 0xf000) << 4;
22976 md_number_to_chars (buf
, newval
, 4);
22981 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22982 case BFD_RELOC_ARM_ALU_PC_G0
:
22983 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22984 case BFD_RELOC_ARM_ALU_PC_G1
:
22985 case BFD_RELOC_ARM_ALU_PC_G2
:
22986 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22987 case BFD_RELOC_ARM_ALU_SB_G0
:
22988 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22989 case BFD_RELOC_ARM_ALU_SB_G1
:
22990 case BFD_RELOC_ARM_ALU_SB_G2
:
22991 gas_assert (!fixP
->fx_done
);
22992 if (!seg
->use_rela_p
)
22995 bfd_vma encoded_addend
;
22996 bfd_vma addend_abs
= abs (value
);
22998 /* Check that the absolute value of the addend can be
22999 expressed as an 8-bit constant plus a rotation. */
23000 encoded_addend
= encode_arm_immediate (addend_abs
);
23001 if (encoded_addend
== (unsigned int) FAIL
)
23002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23003 _("the offset 0x%08lX is not representable"),
23004 (unsigned long) addend_abs
);
23006 /* Extract the instruction. */
23007 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23009 /* If the addend is positive, use an ADD instruction.
23010 Otherwise use a SUB. Take care not to destroy the S bit. */
23011 insn
&= 0xff1fffff;
23017 /* Place the encoded addend into the first 12 bits of the
23019 insn
&= 0xfffff000;
23020 insn
|= encoded_addend
;
23022 /* Update the instruction. */
23023 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23027 case BFD_RELOC_ARM_LDR_PC_G0
:
23028 case BFD_RELOC_ARM_LDR_PC_G1
:
23029 case BFD_RELOC_ARM_LDR_PC_G2
:
23030 case BFD_RELOC_ARM_LDR_SB_G0
:
23031 case BFD_RELOC_ARM_LDR_SB_G1
:
23032 case BFD_RELOC_ARM_LDR_SB_G2
:
23033 gas_assert (!fixP
->fx_done
);
23034 if (!seg
->use_rela_p
)
23037 bfd_vma addend_abs
= abs (value
);
23039 /* Check that the absolute value of the addend can be
23040 encoded in 12 bits. */
23041 if (addend_abs
>= 0x1000)
23042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23043 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23044 (unsigned long) addend_abs
);
23046 /* Extract the instruction. */
23047 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23049 /* If the addend is negative, clear bit 23 of the instruction.
23050 Otherwise set it. */
23052 insn
&= ~(1 << 23);
23056 /* Place the absolute value of the addend into the first 12 bits
23057 of the instruction. */
23058 insn
&= 0xfffff000;
23059 insn
|= addend_abs
;
23061 /* Update the instruction. */
23062 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23066 case BFD_RELOC_ARM_LDRS_PC_G0
:
23067 case BFD_RELOC_ARM_LDRS_PC_G1
:
23068 case BFD_RELOC_ARM_LDRS_PC_G2
:
23069 case BFD_RELOC_ARM_LDRS_SB_G0
:
23070 case BFD_RELOC_ARM_LDRS_SB_G1
:
23071 case BFD_RELOC_ARM_LDRS_SB_G2
:
23072 gas_assert (!fixP
->fx_done
);
23073 if (!seg
->use_rela_p
)
23076 bfd_vma addend_abs
= abs (value
);
23078 /* Check that the absolute value of the addend can be
23079 encoded in 8 bits. */
23080 if (addend_abs
>= 0x100)
23081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23082 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23083 (unsigned long) addend_abs
);
23085 /* Extract the instruction. */
23086 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23088 /* If the addend is negative, clear bit 23 of the instruction.
23089 Otherwise set it. */
23091 insn
&= ~(1 << 23);
23095 /* Place the first four bits of the absolute value of the addend
23096 into the first 4 bits of the instruction, and the remaining
23097 four into bits 8 .. 11. */
23098 insn
&= 0xfffff0f0;
23099 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23101 /* Update the instruction. */
23102 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23106 case BFD_RELOC_ARM_LDC_PC_G0
:
23107 case BFD_RELOC_ARM_LDC_PC_G1
:
23108 case BFD_RELOC_ARM_LDC_PC_G2
:
23109 case BFD_RELOC_ARM_LDC_SB_G0
:
23110 case BFD_RELOC_ARM_LDC_SB_G1
:
23111 case BFD_RELOC_ARM_LDC_SB_G2
:
23112 gas_assert (!fixP
->fx_done
);
23113 if (!seg
->use_rela_p
)
23116 bfd_vma addend_abs
= abs (value
);
23118 /* Check that the absolute value of the addend is a multiple of
23119 four and, when divided by four, fits in 8 bits. */
23120 if (addend_abs
& 0x3)
23121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23122 _("bad offset 0x%08lX (must be word-aligned)"),
23123 (unsigned long) addend_abs
);
23125 if ((addend_abs
>> 2) > 0xff)
23126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23127 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23128 (unsigned long) addend_abs
);
23130 /* Extract the instruction. */
23131 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23133 /* If the addend is negative, clear bit 23 of the instruction.
23134 Otherwise set it. */
23136 insn
&= ~(1 << 23);
23140 /* Place the addend (divided by four) into the first eight
23141 bits of the instruction. */
23142 insn
&= 0xfffffff0;
23143 insn
|= addend_abs
>> 2;
23145 /* Update the instruction. */
23146 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23150 case BFD_RELOC_ARM_V4BX
:
23151 /* This will need to go in the object file. */
23155 case BFD_RELOC_UNUSED
:
23157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23158 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23162 /* Translate internal representation of relocation info to BFD target
23166 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23169 bfd_reloc_code_real_type code
;
23171 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23173 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23174 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23175 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23177 if (fixp
->fx_pcrel
)
23179 if (section
->use_rela_p
)
23180 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23182 fixp
->fx_offset
= reloc
->address
;
23184 reloc
->addend
= fixp
->fx_offset
;
23186 switch (fixp
->fx_r_type
)
23189 if (fixp
->fx_pcrel
)
23191 code
= BFD_RELOC_8_PCREL
;
23196 if (fixp
->fx_pcrel
)
23198 code
= BFD_RELOC_16_PCREL
;
23203 if (fixp
->fx_pcrel
)
23205 code
= BFD_RELOC_32_PCREL
;
23209 case BFD_RELOC_ARM_MOVW
:
23210 if (fixp
->fx_pcrel
)
23212 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23216 case BFD_RELOC_ARM_MOVT
:
23217 if (fixp
->fx_pcrel
)
23219 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23223 case BFD_RELOC_ARM_THUMB_MOVW
:
23224 if (fixp
->fx_pcrel
)
23226 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23230 case BFD_RELOC_ARM_THUMB_MOVT
:
23231 if (fixp
->fx_pcrel
)
23233 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23237 case BFD_RELOC_NONE
:
23238 case BFD_RELOC_ARM_PCREL_BRANCH
:
23239 case BFD_RELOC_ARM_PCREL_BLX
:
23240 case BFD_RELOC_RVA
:
23241 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23242 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23243 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23244 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23245 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23246 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23247 case BFD_RELOC_VTABLE_ENTRY
:
23248 case BFD_RELOC_VTABLE_INHERIT
:
23250 case BFD_RELOC_32_SECREL
:
23252 code
= fixp
->fx_r_type
;
23255 case BFD_RELOC_THUMB_PCREL_BLX
:
23257 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23258 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23261 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23264 case BFD_RELOC_ARM_LITERAL
:
23265 case BFD_RELOC_ARM_HWLITERAL
:
23266 /* If this is called then the a literal has
23267 been referenced across a section boundary. */
23268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23269 _("literal referenced across section boundary"));
23273 case BFD_RELOC_ARM_TLS_CALL
:
23274 case BFD_RELOC_ARM_THM_TLS_CALL
:
23275 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23276 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23277 case BFD_RELOC_ARM_GOT32
:
23278 case BFD_RELOC_ARM_GOTOFF
:
23279 case BFD_RELOC_ARM_GOT_PREL
:
23280 case BFD_RELOC_ARM_PLT32
:
23281 case BFD_RELOC_ARM_TARGET1
:
23282 case BFD_RELOC_ARM_ROSEGREL32
:
23283 case BFD_RELOC_ARM_SBREL32
:
23284 case BFD_RELOC_ARM_PREL31
:
23285 case BFD_RELOC_ARM_TARGET2
:
23286 case BFD_RELOC_ARM_TLS_LE32
:
23287 case BFD_RELOC_ARM_TLS_LDO32
:
23288 case BFD_RELOC_ARM_PCREL_CALL
:
23289 case BFD_RELOC_ARM_PCREL_JUMP
:
23290 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23291 case BFD_RELOC_ARM_ALU_PC_G0
:
23292 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23293 case BFD_RELOC_ARM_ALU_PC_G1
:
23294 case BFD_RELOC_ARM_ALU_PC_G2
:
23295 case BFD_RELOC_ARM_LDR_PC_G0
:
23296 case BFD_RELOC_ARM_LDR_PC_G1
:
23297 case BFD_RELOC_ARM_LDR_PC_G2
:
23298 case BFD_RELOC_ARM_LDRS_PC_G0
:
23299 case BFD_RELOC_ARM_LDRS_PC_G1
:
23300 case BFD_RELOC_ARM_LDRS_PC_G2
:
23301 case BFD_RELOC_ARM_LDC_PC_G0
:
23302 case BFD_RELOC_ARM_LDC_PC_G1
:
23303 case BFD_RELOC_ARM_LDC_PC_G2
:
23304 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23305 case BFD_RELOC_ARM_ALU_SB_G0
:
23306 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23307 case BFD_RELOC_ARM_ALU_SB_G1
:
23308 case BFD_RELOC_ARM_ALU_SB_G2
:
23309 case BFD_RELOC_ARM_LDR_SB_G0
:
23310 case BFD_RELOC_ARM_LDR_SB_G1
:
23311 case BFD_RELOC_ARM_LDR_SB_G2
:
23312 case BFD_RELOC_ARM_LDRS_SB_G0
:
23313 case BFD_RELOC_ARM_LDRS_SB_G1
:
23314 case BFD_RELOC_ARM_LDRS_SB_G2
:
23315 case BFD_RELOC_ARM_LDC_SB_G0
:
23316 case BFD_RELOC_ARM_LDC_SB_G1
:
23317 case BFD_RELOC_ARM_LDC_SB_G2
:
23318 case BFD_RELOC_ARM_V4BX
:
23319 code
= fixp
->fx_r_type
;
23322 case BFD_RELOC_ARM_TLS_GOTDESC
:
23323 case BFD_RELOC_ARM_TLS_GD32
:
23324 case BFD_RELOC_ARM_TLS_IE32
:
23325 case BFD_RELOC_ARM_TLS_LDM32
:
23326 /* BFD will include the symbol's address in the addend.
23327 But we don't want that, so subtract it out again here. */
23328 if (!S_IS_COMMON (fixp
->fx_addsy
))
23329 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23330 code
= fixp
->fx_r_type
;
23334 case BFD_RELOC_ARM_IMMEDIATE
:
23335 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23336 _("internal relocation (type: IMMEDIATE) not fixed up"));
23339 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23340 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23341 _("ADRL used for a symbol not defined in the same file"));
23344 case BFD_RELOC_ARM_OFFSET_IMM
:
23345 if (section
->use_rela_p
)
23347 code
= fixp
->fx_r_type
;
23351 if (fixp
->fx_addsy
!= NULL
23352 && !S_IS_DEFINED (fixp
->fx_addsy
)
23353 && S_IS_LOCAL (fixp
->fx_addsy
))
23355 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23356 _("undefined local label `%s'"),
23357 S_GET_NAME (fixp
->fx_addsy
));
23361 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23362 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23369 switch (fixp
->fx_r_type
)
23371 case BFD_RELOC_NONE
: type
= "NONE"; break;
23372 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23373 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23374 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23375 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23376 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23377 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23378 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23379 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23380 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23381 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23382 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23383 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23384 default: type
= _("<unknown>"); break;
23386 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23387 _("cannot represent %s relocation in this object file format"),
23394 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23396 && fixp
->fx_addsy
== GOT_symbol
)
23398 code
= BFD_RELOC_ARM_GOTPC
;
23399 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23403 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23405 if (reloc
->howto
== NULL
)
23407 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23408 _("cannot represent %s relocation in this object file format"),
23409 bfd_get_reloc_code_name (code
));
23413 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23414 vtable entry to be used in the relocation's section offset. */
23415 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23416 reloc
->address
= fixp
->fx_offset
;
23421 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23424 cons_fix_new_arm (fragS
* frag
,
23428 bfd_reloc_code_real_type reloc
)
23433 FIXME: @@ Should look at CPU word size. */
23437 reloc
= BFD_RELOC_8
;
23440 reloc
= BFD_RELOC_16
;
23444 reloc
= BFD_RELOC_32
;
23447 reloc
= BFD_RELOC_64
;
23452 if (exp
->X_op
== O_secrel
)
23454 exp
->X_op
= O_symbol
;
23455 reloc
= BFD_RELOC_32_SECREL
;
23459 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23462 #if defined (OBJ_COFF)
23464 arm_validate_fix (fixS
* fixP
)
23466 /* If the destination of the branch is a defined symbol which does not have
23467 the THUMB_FUNC attribute, then we must be calling a function which has
23468 the (interfacearm) attribute. We look for the Thumb entry point to that
23469 function and change the branch to refer to that function instead. */
23470 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23471 && fixP
->fx_addsy
!= NULL
23472 && S_IS_DEFINED (fixP
->fx_addsy
)
23473 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23475 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23482 arm_force_relocation (struct fix
* fixp
)
23484 #if defined (OBJ_COFF) && defined (TE_PE)
23485 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23489 /* In case we have a call or a branch to a function in ARM ISA mode from
23490 a thumb function or vice-versa force the relocation. These relocations
23491 are cleared off for some cores that might have blx and simple transformations
23495 switch (fixp
->fx_r_type
)
23497 case BFD_RELOC_ARM_PCREL_JUMP
:
23498 case BFD_RELOC_ARM_PCREL_CALL
:
23499 case BFD_RELOC_THUMB_PCREL_BLX
:
23500 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23504 case BFD_RELOC_ARM_PCREL_BLX
:
23505 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23506 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23507 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23508 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23517 /* Resolve these relocations even if the symbol is extern or weak.
23518 Technically this is probably wrong due to symbol preemption.
23519 In practice these relocations do not have enough range to be useful
23520 at dynamic link time, and some code (e.g. in the Linux kernel)
23521 expects these references to be resolved. */
23522 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23523 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23524 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23525 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23526 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23527 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23528 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23529 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23530 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23531 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23532 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23533 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23534 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23535 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23538 /* Always leave these relocations for the linker. */
23539 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23540 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23541 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23544 /* Always generate relocations against function symbols. */
23545 if (fixp
->fx_r_type
== BFD_RELOC_32
23547 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23550 return generic_force_reloc (fixp
);
23553 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23554 /* Relocations against function names must be left unadjusted,
23555 so that the linker can use this information to generate interworking
23556 stubs. The MIPS version of this function
23557 also prevents relocations that are mips-16 specific, but I do not
23558 know why it does this.
23561 There is one other problem that ought to be addressed here, but
23562 which currently is not: Taking the address of a label (rather
23563 than a function) and then later jumping to that address. Such
23564 addresses also ought to have their bottom bit set (assuming that
23565 they reside in Thumb code), but at the moment they will not. */
23568 arm_fix_adjustable (fixS
* fixP
)
23570 if (fixP
->fx_addsy
== NULL
)
23573 /* Preserve relocations against symbols with function type. */
23574 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23577 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23578 && fixP
->fx_subsy
== NULL
)
23581 /* We need the symbol name for the VTABLE entries. */
23582 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23583 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23586 /* Don't allow symbols to be discarded on GOT related relocs. */
23587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23588 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23589 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23590 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23591 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23592 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23593 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23594 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23595 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23596 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23597 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23598 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23599 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23600 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23603 /* Similarly for group relocations. */
23604 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23605 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23606 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23609 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23610 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23611 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23612 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23613 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23614 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23615 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23616 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23617 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23622 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23627 elf32_arm_target_format (void)
23630 return (target_big_endian
23631 ? "elf32-bigarm-symbian"
23632 : "elf32-littlearm-symbian");
23633 #elif defined (TE_VXWORKS)
23634 return (target_big_endian
23635 ? "elf32-bigarm-vxworks"
23636 : "elf32-littlearm-vxworks");
23637 #elif defined (TE_NACL)
23638 return (target_big_endian
23639 ? "elf32-bigarm-nacl"
23640 : "elf32-littlearm-nacl");
23642 if (target_big_endian
)
23643 return "elf32-bigarm";
23645 return "elf32-littlearm";
23650 armelf_frob_symbol (symbolS
* symp
,
23653 elf_frob_symbol (symp
, puntp
);
23657 /* MD interface: Finalization. */
23662 literal_pool
* pool
;
23664 /* Ensure that all the IT blocks are properly closed. */
23665 check_it_blocks_finished ();
23667 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23669 /* Put it at the end of the relevant section. */
23670 subseg_set (pool
->section
, pool
->sub_section
);
23672 arm_elf_change_section ();
23679 /* Remove any excess mapping symbols generated for alignment frags in
23680 SEC. We may have created a mapping symbol before a zero byte
23681 alignment; remove it if there's a mapping symbol after the
23684 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23685 void *dummy ATTRIBUTE_UNUSED
)
23687 segment_info_type
*seginfo
= seg_info (sec
);
23690 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23693 for (fragp
= seginfo
->frchainP
->frch_root
;
23695 fragp
= fragp
->fr_next
)
23697 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23698 fragS
*next
= fragp
->fr_next
;
23700 /* Variable-sized frags have been converted to fixed size by
23701 this point. But if this was variable-sized to start with,
23702 there will be a fixed-size frag after it. So don't handle
23704 if (sym
== NULL
|| next
== NULL
)
23707 if (S_GET_VALUE (sym
) < next
->fr_address
)
23708 /* Not at the end of this frag. */
23710 know (S_GET_VALUE (sym
) == next
->fr_address
);
23714 if (next
->tc_frag_data
.first_map
!= NULL
)
23716 /* Next frag starts with a mapping symbol. Discard this
23718 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23722 if (next
->fr_next
== NULL
)
23724 /* This mapping symbol is at the end of the section. Discard
23726 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23727 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23731 /* As long as we have empty frags without any mapping symbols,
23733 /* If the next frag is non-empty and does not start with a
23734 mapping symbol, then this mapping symbol is required. */
23735 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23738 next
= next
->fr_next
;
23740 while (next
!= NULL
);
23745 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23749 arm_adjust_symtab (void)
23754 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23756 if (ARM_IS_THUMB (sym
))
23758 if (THUMB_IS_FUNC (sym
))
23760 /* Mark the symbol as a Thumb function. */
23761 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23762 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23763 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23765 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23766 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23768 as_bad (_("%s: unexpected function type: %d"),
23769 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23771 else switch (S_GET_STORAGE_CLASS (sym
))
23774 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23777 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23780 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23788 if (ARM_IS_INTERWORK (sym
))
23789 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23796 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23798 if (ARM_IS_THUMB (sym
))
23800 elf_symbol_type
* elf_sym
;
23802 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23803 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23805 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23806 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23808 /* If it's a .thumb_func, declare it as so,
23809 otherwise tag label as .code 16. */
23810 if (THUMB_IS_FUNC (sym
))
23811 elf_sym
->internal_elf_sym
.st_target_internal
23812 = ST_BRANCH_TO_THUMB
;
23813 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23814 elf_sym
->internal_elf_sym
.st_info
=
23815 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23820 /* Remove any overlapping mapping symbols generated by alignment frags. */
23821 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23822 /* Now do generic ELF adjustments. */
23823 elf_adjust_symtab ();
23827 /* MD interface: Initialization. */
23830 set_constant_flonums (void)
23834 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23835 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23839 /* Auto-select Thumb mode if it's the only available instruction set for the
23840 given architecture. */
23843 autoselect_thumb_from_cpu_variant (void)
23845 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23846 opcode_select (16);
23855 if ( (arm_ops_hsh
= hash_new ()) == NULL
23856 || (arm_cond_hsh
= hash_new ()) == NULL
23857 || (arm_shift_hsh
= hash_new ()) == NULL
23858 || (arm_psr_hsh
= hash_new ()) == NULL
23859 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23860 || (arm_reg_hsh
= hash_new ()) == NULL
23861 || (arm_reloc_hsh
= hash_new ()) == NULL
23862 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23863 as_fatal (_("virtual memory exhausted"));
23865 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23866 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23867 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23868 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23869 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23870 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23871 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23872 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23873 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23874 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23875 (void *) (v7m_psrs
+ i
));
23876 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23877 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23879 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23881 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23882 (void *) (barrier_opt_names
+ i
));
23884 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23886 struct reloc_entry
* entry
= reloc_names
+ i
;
23888 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23889 /* This makes encode_branch() use the EABI versions of this relocation. */
23890 entry
->reloc
= BFD_RELOC_UNUSED
;
23892 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23896 set_constant_flonums ();
23898 /* Set the cpu variant based on the command-line options. We prefer
23899 -mcpu= over -march= if both are set (as for GCC); and we prefer
23900 -mfpu= over any other way of setting the floating point unit.
23901 Use of legacy options with new options are faulted. */
23904 if (mcpu_cpu_opt
|| march_cpu_opt
)
23905 as_bad (_("use of old and new-style options to set CPU type"));
23907 mcpu_cpu_opt
= legacy_cpu
;
23909 else if (!mcpu_cpu_opt
)
23910 mcpu_cpu_opt
= march_cpu_opt
;
23915 as_bad (_("use of old and new-style options to set FPU type"));
23917 mfpu_opt
= legacy_fpu
;
23919 else if (!mfpu_opt
)
23921 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23922 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23923 /* Some environments specify a default FPU. If they don't, infer it
23924 from the processor. */
23926 mfpu_opt
= mcpu_fpu_opt
;
23928 mfpu_opt
= march_fpu_opt
;
23930 mfpu_opt
= &fpu_default
;
23936 if (mcpu_cpu_opt
!= NULL
)
23937 mfpu_opt
= &fpu_default
;
23938 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23939 mfpu_opt
= &fpu_arch_vfp_v2
;
23941 mfpu_opt
= &fpu_arch_fpa
;
23947 mcpu_cpu_opt
= &cpu_default
;
23948 selected_cpu
= cpu_default
;
23950 else if (no_cpu_selected ())
23951 selected_cpu
= cpu_default
;
23954 selected_cpu
= *mcpu_cpu_opt
;
23956 mcpu_cpu_opt
= &arm_arch_any
;
23959 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23961 autoselect_thumb_from_cpu_variant ();
23963 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23965 #if defined OBJ_COFF || defined OBJ_ELF
23967 unsigned int flags
= 0;
23969 #if defined OBJ_ELF
23970 flags
= meabi_flags
;
23972 switch (meabi_flags
)
23974 case EF_ARM_EABI_UNKNOWN
:
23976 /* Set the flags in the private structure. */
23977 if (uses_apcs_26
) flags
|= F_APCS26
;
23978 if (support_interwork
) flags
|= F_INTERWORK
;
23979 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23980 if (pic_code
) flags
|= F_PIC
;
23981 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23982 flags
|= F_SOFT_FLOAT
;
23984 switch (mfloat_abi_opt
)
23986 case ARM_FLOAT_ABI_SOFT
:
23987 case ARM_FLOAT_ABI_SOFTFP
:
23988 flags
|= F_SOFT_FLOAT
;
23991 case ARM_FLOAT_ABI_HARD
:
23992 if (flags
& F_SOFT_FLOAT
)
23993 as_bad (_("hard-float conflicts with specified fpu"));
23997 /* Using pure-endian doubles (even if soft-float). */
23998 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23999 flags
|= F_VFP_FLOAT
;
24001 #if defined OBJ_ELF
24002 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24003 flags
|= EF_ARM_MAVERICK_FLOAT
;
24006 case EF_ARM_EABI_VER4
:
24007 case EF_ARM_EABI_VER5
:
24008 /* No additional flags to set. */
24015 bfd_set_private_flags (stdoutput
, flags
);
24017 /* We have run out flags in the COFF header to encode the
24018 status of ATPCS support, so instead we create a dummy,
24019 empty, debug section called .arm.atpcs. */
24024 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24028 bfd_set_section_flags
24029 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24030 bfd_set_section_size (stdoutput
, sec
, 0);
24031 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24037 /* Record the CPU type as well. */
24038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24039 mach
= bfd_mach_arm_iWMMXt2
;
24040 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24041 mach
= bfd_mach_arm_iWMMXt
;
24042 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24043 mach
= bfd_mach_arm_XScale
;
24044 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24045 mach
= bfd_mach_arm_ep9312
;
24046 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24047 mach
= bfd_mach_arm_5TE
;
24048 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24050 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24051 mach
= bfd_mach_arm_5T
;
24053 mach
= bfd_mach_arm_5
;
24055 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24057 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24058 mach
= bfd_mach_arm_4T
;
24060 mach
= bfd_mach_arm_4
;
24062 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24063 mach
= bfd_mach_arm_3M
;
24064 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24065 mach
= bfd_mach_arm_3
;
24066 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24067 mach
= bfd_mach_arm_2a
;
24068 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24069 mach
= bfd_mach_arm_2
;
24071 mach
= bfd_mach_arm_unknown
;
24073 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24076 /* Command line processing. */
24079 Invocation line includes a switch not recognized by the base assembler.
24080 See if it's a processor-specific option.
24082 This routine is somewhat complicated by the need for backwards
24083 compatibility (since older releases of gcc can't be changed).
24084 The new options try to make the interface as compatible as
24087 New options (supported) are:
24089 -mcpu=<cpu name> Assemble for selected processor
24090 -march=<architecture name> Assemble for selected architecture
24091 -mfpu=<fpu architecture> Assemble for selected FPU.
24092 -EB/-mbig-endian Big-endian
24093 -EL/-mlittle-endian Little-endian
24094 -k Generate PIC code
24095 -mthumb Start in Thumb mode
24096 -mthumb-interwork Code supports ARM/Thumb interworking
24098 -m[no-]warn-deprecated Warn about deprecated features
24100 For now we will also provide support for:
24102 -mapcs-32 32-bit Program counter
24103 -mapcs-26 26-bit Program counter
24104 -macps-float Floats passed in FP registers
24105 -mapcs-reentrant Reentrant code
24107 (sometime these will probably be replaced with -mapcs=<list of options>
24108 and -matpcs=<list of options>)
24110 The remaining options are only supported for back-wards compatibility.
24111 Cpu variants, the arm part is optional:
24112 -m[arm]1 Currently not supported.
24113 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24114 -m[arm]3 Arm 3 processor
24115 -m[arm]6[xx], Arm 6 processors
24116 -m[arm]7[xx][t][[d]m] Arm 7 processors
24117 -m[arm]8[10] Arm 8 processors
24118 -m[arm]9[20][tdmi] Arm 9 processors
24119 -mstrongarm[110[0]] StrongARM processors
24120 -mxscale XScale processors
24121 -m[arm]v[2345[t[e]]] Arm architectures
24122 -mall All (except the ARM1)
24124 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24125 -mfpe-old (No float load/store multiples)
24126 -mvfpxd VFP Single precision
24128 -mno-fpu Disable all floating point instructions
24130 The following CPU names are recognized:
24131 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24132 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24133 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24134 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24135 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24136 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24137 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24141 const char * md_shortopts
= "m:k";
24143 #ifdef ARM_BI_ENDIAN
24144 #define OPTION_EB (OPTION_MD_BASE + 0)
24145 #define OPTION_EL (OPTION_MD_BASE + 1)
24147 #if TARGET_BYTES_BIG_ENDIAN
24148 #define OPTION_EB (OPTION_MD_BASE + 0)
24150 #define OPTION_EL (OPTION_MD_BASE + 1)
24153 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24155 struct option md_longopts
[] =
24158 {"EB", no_argument
, NULL
, OPTION_EB
},
24161 {"EL", no_argument
, NULL
, OPTION_EL
},
24163 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24164 {NULL
, no_argument
, NULL
, 0}
24167 size_t md_longopts_size
= sizeof (md_longopts
);
24169 struct arm_option_table
24171 char *option
; /* Option name to match. */
24172 char *help
; /* Help information. */
24173 int *var
; /* Variable to change. */
24174 int value
; /* What to change it to. */
24175 char *deprecated
; /* If non-null, print this message. */
24178 struct arm_option_table arm_opts
[] =
24180 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24181 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24182 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24183 &support_interwork
, 1, NULL
},
24184 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24185 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24186 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24188 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24189 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24190 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24191 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24194 /* These are recognized by the assembler, but have no affect on code. */
24195 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24196 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24198 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24199 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24200 &warn_on_deprecated
, 0, NULL
},
24201 {NULL
, NULL
, NULL
, 0, NULL
}
24204 struct arm_legacy_option_table
24206 char *option
; /* Option name to match. */
24207 const arm_feature_set
**var
; /* Variable to change. */
24208 const arm_feature_set value
; /* What to change it to. */
24209 char *deprecated
; /* If non-null, print this message. */
24212 const struct arm_legacy_option_table arm_legacy_opts
[] =
24214 /* DON'T add any new processors to this list -- we want the whole list
24215 to go away... Add them to the processors table instead. */
24216 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24217 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24218 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24219 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24220 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24221 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24222 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24223 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24224 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24225 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24226 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24227 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24228 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24229 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24230 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24231 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24232 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24233 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24234 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24235 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24236 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24237 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24238 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24239 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24240 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24241 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24242 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24243 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24244 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24245 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24246 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24247 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24248 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24249 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24250 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24251 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24252 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24253 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24254 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24255 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24256 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24257 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24258 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24259 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24260 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24261 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24262 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24263 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24264 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24265 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24266 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24267 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24268 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24269 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24270 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24271 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24272 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24273 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24274 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24275 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24276 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24277 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24278 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24279 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24280 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24281 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24282 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24283 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24284 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24285 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24286 N_("use -mcpu=strongarm110")},
24287 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24288 N_("use -mcpu=strongarm1100")},
24289 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24290 N_("use -mcpu=strongarm1110")},
24291 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24292 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24293 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24295 /* Architecture variants -- don't add any more to this list either. */
24296 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24297 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24298 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24299 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24300 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24301 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24302 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24303 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24304 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24305 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24306 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24307 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24308 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24309 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24310 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24311 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24312 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24313 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24315 /* Floating point variants -- don't add any more to this list either. */
24316 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24317 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24318 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24319 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24320 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24322 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24325 struct arm_cpu_option_table
24329 const arm_feature_set value
;
24330 /* For some CPUs we assume an FPU unless the user explicitly sets
24332 const arm_feature_set default_fpu
;
24333 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24335 const char *canonical_name
;
24338 /* This list should, at a minimum, contain all the cpu names
24339 recognized by GCC. */
24340 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24341 static const struct arm_cpu_option_table arm_cpus
[] =
24343 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24344 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24345 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24346 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24347 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24348 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24349 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24350 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24351 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24352 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24353 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24354 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24355 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24356 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24357 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24358 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24359 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24360 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24361 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24362 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24363 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24364 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24365 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24366 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24367 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24368 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24369 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24370 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24371 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24372 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24373 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24374 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24375 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24376 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24377 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24378 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24379 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24380 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24381 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24382 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24383 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24384 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24385 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24386 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24387 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24388 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24389 /* For V5 or later processors we default to using VFP; but the user
24390 should really set the FPU type explicitly. */
24391 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24392 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24393 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24394 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24395 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24396 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24397 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24398 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24399 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24400 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24401 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24402 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24403 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24404 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24405 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24406 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24407 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24408 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24409 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24410 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24412 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24413 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24414 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24415 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24416 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24417 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24418 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24419 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24420 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24422 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24423 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24424 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24425 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24426 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24427 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24428 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24429 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24430 FPU_NONE
, "Cortex-A5"),
24431 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24433 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24434 ARM_FEATURE (0, FPU_VFP_V3
24435 | FPU_NEON_EXT_V1
),
24437 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24438 ARM_FEATURE (0, FPU_VFP_V3
24439 | FPU_NEON_EXT_V1
),
24441 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24443 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24445 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24447 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24449 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24451 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24453 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24454 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24456 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24457 FPU_NONE
, "Cortex-R5"),
24458 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24459 FPU_ARCH_VFP_V3D16
,
24461 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24462 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24463 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24464 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24465 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24466 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24467 /* ??? XSCALE is really an architecture. */
24468 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24469 /* ??? iwmmxt is not a processor. */
24470 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24471 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24472 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24474 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24475 FPU_ARCH_MAVERICK
, "ARM920T"),
24476 /* Marvell processors. */
24477 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
| ARM_EXT_SEC
, 0),
24478 FPU_ARCH_VFP_V3D16
, NULL
),
24479 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
24481 FPU_ARCH_NEON_VFP_V4
, NULL
),
24482 /* APM X-Gene family. */
24483 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24485 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24488 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24492 struct arm_arch_option_table
24496 const arm_feature_set value
;
24497 const arm_feature_set default_fpu
;
24500 /* This list should, at a minimum, contain all the architecture names
24501 recognized by GCC. */
24502 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24503 static const struct arm_arch_option_table arm_archs
[] =
24505 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24506 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24507 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24508 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24509 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24510 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24511 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24512 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24513 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24514 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24515 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24516 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24517 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24518 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24519 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24520 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24521 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24522 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24523 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24524 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24525 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24526 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24527 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24528 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24529 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24530 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24531 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24532 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24533 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24534 /* The official spelling of the ARMv7 profile variants is the dashed form.
24535 Accept the non-dashed form for compatibility with old toolchains. */
24536 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24537 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24538 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24539 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24540 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24541 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24542 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24543 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24544 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24545 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24546 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24547 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24548 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24550 #undef ARM_ARCH_OPT
24552 /* ISA extensions in the co-processor and main instruction set space. */
24553 struct arm_option_extension_value_table
24557 const arm_feature_set merge_value
;
24558 const arm_feature_set clear_value
;
24559 const arm_feature_set allowed_archs
;
24562 /* The following table must be in alphabetical order with a NULL last entry.
24564 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24565 static const struct arm_option_extension_value_table arm_extensions
[] =
24567 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE (0, CRC_EXT_ARMV8
),
24568 ARM_FEATURE (ARM_EXT_V8
, 0)),
24569 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24570 ARM_FEATURE (0, FPU_CRYPTO_ARMV8
),
24571 ARM_FEATURE (ARM_EXT_V8
, 0)),
24572 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE (0, FPU_VFP_ARMV8
),
24573 ARM_FEATURE (ARM_EXT_V8
, 0)),
24574 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24575 ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24576 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24577 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
),
24578 ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
24579 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
),
24580 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
24581 ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
),
24582 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
24583 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
24584 ARM_FEATURE (ARM_EXT_MP
, 0),
24585 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24586 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24587 ARM_FEATURE(0, FPU_NEON_ARMV8
),
24588 ARM_FEATURE (ARM_EXT_V8
, 0)),
24589 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24590 ARM_FEATURE (ARM_EXT_OS
, 0),
24591 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24592 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24593 ARM_FEATURE (ARM_EXT_SEC
, 0),
24594 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24595 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24597 ARM_FEATURE (ARM_EXT_VIRT
, 0),
24598 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24599 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
),
24600 ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24601 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24605 /* ISA floating-point and Advanced SIMD extensions. */
24606 struct arm_option_fpu_value_table
24609 const arm_feature_set value
;
24612 /* This list should, at a minimum, contain all the fpu names
24613 recognized by GCC. */
24614 static const struct arm_option_fpu_value_table arm_fpus
[] =
24616 {"softfpa", FPU_NONE
},
24617 {"fpe", FPU_ARCH_FPE
},
24618 {"fpe2", FPU_ARCH_FPE
},
24619 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24620 {"fpa", FPU_ARCH_FPA
},
24621 {"fpa10", FPU_ARCH_FPA
},
24622 {"fpa11", FPU_ARCH_FPA
},
24623 {"arm7500fe", FPU_ARCH_FPA
},
24624 {"softvfp", FPU_ARCH_VFP
},
24625 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24626 {"vfp", FPU_ARCH_VFP_V2
},
24627 {"vfp9", FPU_ARCH_VFP_V2
},
24628 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24629 {"vfp10", FPU_ARCH_VFP_V2
},
24630 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24631 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24632 {"vfpv2", FPU_ARCH_VFP_V2
},
24633 {"vfpv3", FPU_ARCH_VFP_V3
},
24634 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24635 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24636 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24637 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24638 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24639 {"arm1020t", FPU_ARCH_VFP_V1
},
24640 {"arm1020e", FPU_ARCH_VFP_V2
},
24641 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24642 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24643 {"maverick", FPU_ARCH_MAVERICK
},
24644 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24645 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24646 {"vfpv4", FPU_ARCH_VFP_V4
},
24647 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24648 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24649 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24650 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24651 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24652 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24653 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24654 {"crypto-neon-fp-armv8",
24655 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24656 {NULL
, ARM_ARCH_NONE
}
24659 struct arm_option_value_table
24665 static const struct arm_option_value_table arm_float_abis
[] =
24667 {"hard", ARM_FLOAT_ABI_HARD
},
24668 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24669 {"soft", ARM_FLOAT_ABI_SOFT
},
24674 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24675 static const struct arm_option_value_table arm_eabis
[] =
24677 {"gnu", EF_ARM_EABI_UNKNOWN
},
24678 {"4", EF_ARM_EABI_VER4
},
24679 {"5", EF_ARM_EABI_VER5
},
24684 struct arm_long_option_table
24686 char * option
; /* Substring to match. */
24687 char * help
; /* Help information. */
24688 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24689 char * deprecated
; /* If non-null, print this message. */
24693 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24695 arm_feature_set
*ext_set
= (arm_feature_set
*)
24696 xmalloc (sizeof (arm_feature_set
));
24698 /* We insist on extensions being specified in alphabetical order, and with
24699 extensions being added before being removed. We achieve this by having
24700 the global ARM_EXTENSIONS table in alphabetical order, and using the
24701 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24702 or removing it (0) and only allowing it to change in the order
24704 const struct arm_option_extension_value_table
* opt
= NULL
;
24705 int adding_value
= -1;
24707 /* Copy the feature set, so that we can modify it. */
24708 *ext_set
= **opt_p
;
24711 while (str
!= NULL
&& *str
!= 0)
24718 as_bad (_("invalid architectural extension"));
24723 ext
= strchr (str
, '+');
24728 len
= strlen (str
);
24730 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24732 if (adding_value
!= 0)
24735 opt
= arm_extensions
;
24743 if (adding_value
== -1)
24746 opt
= arm_extensions
;
24748 else if (adding_value
!= 1)
24750 as_bad (_("must specify extensions to add before specifying "
24751 "those to remove"));
24758 as_bad (_("missing architectural extension"));
24762 gas_assert (adding_value
!= -1);
24763 gas_assert (opt
!= NULL
);
24765 /* Scan over the options table trying to find an exact match. */
24766 for (; opt
->name
!= NULL
; opt
++)
24767 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24769 /* Check we can apply the extension to this architecture. */
24770 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24772 as_bad (_("extension does not apply to the base architecture"));
24776 /* Add or remove the extension. */
24778 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
24780 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
24785 if (opt
->name
== NULL
)
24787 /* Did we fail to find an extension because it wasn't specified in
24788 alphabetical order, or because it does not exist? */
24790 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24791 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24794 if (opt
->name
== NULL
)
24795 as_bad (_("unknown architectural extension `%s'"), str
);
24797 as_bad (_("architectural extensions must be specified in "
24798 "alphabetical order"));
24804 /* We should skip the extension we've just matched the next time
24816 arm_parse_cpu (char *str
)
24818 const struct arm_cpu_option_table
*opt
;
24819 char *ext
= strchr (str
, '+');
24825 len
= strlen (str
);
24829 as_bad (_("missing cpu name `%s'"), str
);
24833 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24834 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24836 mcpu_cpu_opt
= &opt
->value
;
24837 mcpu_fpu_opt
= &opt
->default_fpu
;
24838 if (opt
->canonical_name
)
24839 strcpy (selected_cpu_name
, opt
->canonical_name
);
24844 for (i
= 0; i
< len
; i
++)
24845 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24846 selected_cpu_name
[i
] = 0;
24850 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24855 as_bad (_("unknown cpu `%s'"), str
);
24860 arm_parse_arch (char *str
)
24862 const struct arm_arch_option_table
*opt
;
24863 char *ext
= strchr (str
, '+');
24869 len
= strlen (str
);
24873 as_bad (_("missing architecture name `%s'"), str
);
24877 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24878 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24880 march_cpu_opt
= &opt
->value
;
24881 march_fpu_opt
= &opt
->default_fpu
;
24882 strcpy (selected_cpu_name
, opt
->name
);
24885 return arm_parse_extension (ext
, &march_cpu_opt
);
24890 as_bad (_("unknown architecture `%s'\n"), str
);
24895 arm_parse_fpu (char * str
)
24897 const struct arm_option_fpu_value_table
* opt
;
24899 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24900 if (streq (opt
->name
, str
))
24902 mfpu_opt
= &opt
->value
;
24906 as_bad (_("unknown floating point format `%s'\n"), str
);
24911 arm_parse_float_abi (char * str
)
24913 const struct arm_option_value_table
* opt
;
24915 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24916 if (streq (opt
->name
, str
))
24918 mfloat_abi_opt
= opt
->value
;
24922 as_bad (_("unknown floating point abi `%s'\n"), str
);
24928 arm_parse_eabi (char * str
)
24930 const struct arm_option_value_table
*opt
;
24932 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24933 if (streq (opt
->name
, str
))
24935 meabi_flags
= opt
->value
;
24938 as_bad (_("unknown EABI `%s'\n"), str
);
24944 arm_parse_it_mode (char * str
)
24946 bfd_boolean ret
= TRUE
;
24948 if (streq ("arm", str
))
24949 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24950 else if (streq ("thumb", str
))
24951 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24952 else if (streq ("always", str
))
24953 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24954 else if (streq ("never", str
))
24955 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24958 as_bad (_("unknown implicit IT mode `%s', should be "\
24959 "arm, thumb, always, or never."), str
);
24967 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
24969 codecomposer_syntax
= TRUE
;
24970 arm_comment_chars
[0] = ';';
24971 arm_line_separator_chars
[0] = 0;
24975 struct arm_long_option_table arm_long_opts
[] =
24977 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24978 arm_parse_cpu
, NULL
},
24979 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24980 arm_parse_arch
, NULL
},
24981 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24982 arm_parse_fpu
, NULL
},
24983 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24984 arm_parse_float_abi
, NULL
},
24986 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24987 arm_parse_eabi
, NULL
},
24989 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24990 arm_parse_it_mode
, NULL
},
24991 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24992 arm_ccs_mode
, NULL
},
24993 {NULL
, NULL
, 0, NULL
}
24997 md_parse_option (int c
, char * arg
)
24999 struct arm_option_table
*opt
;
25000 const struct arm_legacy_option_table
*fopt
;
25001 struct arm_long_option_table
*lopt
;
25007 target_big_endian
= 1;
25013 target_big_endian
= 0;
25017 case OPTION_FIX_V4BX
:
25022 /* Listing option. Just ignore these, we don't support additional
25027 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25029 if (c
== opt
->option
[0]
25030 && ((arg
== NULL
&& opt
->option
[1] == 0)
25031 || streq (arg
, opt
->option
+ 1)))
25033 /* If the option is deprecated, tell the user. */
25034 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25035 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25036 arg
? arg
: "", _(opt
->deprecated
));
25038 if (opt
->var
!= NULL
)
25039 *opt
->var
= opt
->value
;
25045 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25047 if (c
== fopt
->option
[0]
25048 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25049 || streq (arg
, fopt
->option
+ 1)))
25051 /* If the option is deprecated, tell the user. */
25052 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25053 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25054 arg
? arg
: "", _(fopt
->deprecated
));
25056 if (fopt
->var
!= NULL
)
25057 *fopt
->var
= &fopt
->value
;
25063 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25065 /* These options are expected to have an argument. */
25066 if (c
== lopt
->option
[0]
25068 && strncmp (arg
, lopt
->option
+ 1,
25069 strlen (lopt
->option
+ 1)) == 0)
25071 /* If the option is deprecated, tell the user. */
25072 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25073 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25074 _(lopt
->deprecated
));
25076 /* Call the sup-option parser. */
25077 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25088 md_show_usage (FILE * fp
)
25090 struct arm_option_table
*opt
;
25091 struct arm_long_option_table
*lopt
;
25093 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25095 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25096 if (opt
->help
!= NULL
)
25097 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25099 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25100 if (lopt
->help
!= NULL
)
25101 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25105 -EB assemble code for a big-endian cpu\n"));
25110 -EL assemble code for a little-endian cpu\n"));
25114 --fix-v4bx Allow BX in ARMv4 code\n"));
25122 arm_feature_set flags
;
25123 } cpu_arch_ver_table
;
25125 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25126 least features first. */
25127 static const cpu_arch_ver_table cpu_arch_ver
[] =
25133 {4, ARM_ARCH_V5TE
},
25134 {5, ARM_ARCH_V5TEJ
},
25138 {11, ARM_ARCH_V6M
},
25139 {12, ARM_ARCH_V6SM
},
25140 {8, ARM_ARCH_V6T2
},
25141 {10, ARM_ARCH_V7VE
},
25142 {10, ARM_ARCH_V7R
},
25143 {10, ARM_ARCH_V7M
},
25144 {14, ARM_ARCH_V8A
},
25148 /* Set an attribute if it has not already been set by the user. */
25150 aeabi_set_attribute_int (int tag
, int value
)
25153 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25154 || !attributes_set_explicitly
[tag
])
25155 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25159 aeabi_set_attribute_string (int tag
, const char *value
)
25162 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25163 || !attributes_set_explicitly
[tag
])
25164 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25167 /* Set the public EABI object attributes. */
25169 aeabi_set_public_attributes (void)
25174 int fp16_optional
= 0;
25175 arm_feature_set flags
;
25176 arm_feature_set tmp
;
25177 const cpu_arch_ver_table
*p
;
25179 /* Choose the architecture based on the capabilities of the requested cpu
25180 (if any) and/or the instructions actually used. */
25181 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25182 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25183 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25185 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25186 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25188 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25189 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25191 selected_cpu
= flags
;
25193 /* Allow the user to override the reported architecture. */
25196 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25197 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25200 /* We need to make sure that the attributes do not identify us as v6S-M
25201 when the only v6S-M feature in use is the Operating System Extensions. */
25202 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25203 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25204 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25208 for (p
= cpu_arch_ver
; p
->val
; p
++)
25210 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25213 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25217 /* The table lookup above finds the last architecture to contribute
25218 a new feature. Unfortunately, Tag13 is a subset of the union of
25219 v6T2 and v7-M, so it is never seen as contributing a new feature.
25220 We can not search for the last entry which is entirely used,
25221 because if no CPU is specified we build up only those flags
25222 actually used. Perhaps we should separate out the specified
25223 and implicit cases. Avoid taking this path for -march=all by
25224 checking for contradictory v7-A / v7-M features. */
25226 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25227 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25228 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25231 /* Tag_CPU_name. */
25232 if (selected_cpu_name
[0])
25236 q
= selected_cpu_name
;
25237 if (strncmp (q
, "armv", 4) == 0)
25242 for (i
= 0; q
[i
]; i
++)
25243 q
[i
] = TOUPPER (q
[i
]);
25245 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25248 /* Tag_CPU_arch. */
25249 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25251 /* Tag_CPU_arch_profile. */
25252 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25254 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25256 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25261 if (profile
!= '\0')
25262 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25264 /* Tag_ARM_ISA_use. */
25265 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25267 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25269 /* Tag_THUMB_ISA_use. */
25270 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25272 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25273 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25275 /* Tag_VFP_arch. */
25276 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25277 aeabi_set_attribute_int (Tag_VFP_arch
,
25278 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25280 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25281 aeabi_set_attribute_int (Tag_VFP_arch
,
25282 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25284 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25287 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25289 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25291 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25294 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25295 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25296 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25297 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25298 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25300 /* Tag_ABI_HardFP_use. */
25301 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25302 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25303 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25305 /* Tag_WMMX_arch. */
25306 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25307 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25308 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25309 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25311 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25312 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25313 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25314 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25316 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25318 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25322 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25327 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25328 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25329 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25333 We set Tag_DIV_use to two when integer divide instructions have been used
25334 in ARM state, or when Thumb integer divide instructions have been used,
25335 but we have no architecture profile set, nor have we any ARM instructions.
25337 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25340 For new architectures we will have to check these tests. */
25341 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25342 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25343 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25344 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25345 || (profile
== '\0'
25346 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25347 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25348 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25350 /* Tag_MP_extension_use. */
25351 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25352 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25354 /* Tag Virtualization_use. */
25355 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25357 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25360 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25363 /* Add the default contents for the .ARM.attributes section. */
25367 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25370 aeabi_set_public_attributes ();
25372 #endif /* OBJ_ELF */
25375 /* Parse a .cpu directive. */
25378 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25380 const struct arm_cpu_option_table
*opt
;
25384 name
= input_line_pointer
;
25385 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25386 input_line_pointer
++;
25387 saved_char
= *input_line_pointer
;
25388 *input_line_pointer
= 0;
25390 /* Skip the first "all" entry. */
25391 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25392 if (streq (opt
->name
, name
))
25394 mcpu_cpu_opt
= &opt
->value
;
25395 selected_cpu
= opt
->value
;
25396 if (opt
->canonical_name
)
25397 strcpy (selected_cpu_name
, opt
->canonical_name
);
25401 for (i
= 0; opt
->name
[i
]; i
++)
25402 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25404 selected_cpu_name
[i
] = 0;
25406 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25407 *input_line_pointer
= saved_char
;
25408 demand_empty_rest_of_line ();
25411 as_bad (_("unknown cpu `%s'"), name
);
25412 *input_line_pointer
= saved_char
;
25413 ignore_rest_of_line ();
25417 /* Parse a .arch directive. */
25420 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25422 const struct arm_arch_option_table
*opt
;
25426 name
= input_line_pointer
;
25427 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25428 input_line_pointer
++;
25429 saved_char
= *input_line_pointer
;
25430 *input_line_pointer
= 0;
25432 /* Skip the first "all" entry. */
25433 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25434 if (streq (opt
->name
, name
))
25436 mcpu_cpu_opt
= &opt
->value
;
25437 selected_cpu
= opt
->value
;
25438 strcpy (selected_cpu_name
, opt
->name
);
25439 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25440 *input_line_pointer
= saved_char
;
25441 demand_empty_rest_of_line ();
25445 as_bad (_("unknown architecture `%s'\n"), name
);
25446 *input_line_pointer
= saved_char
;
25447 ignore_rest_of_line ();
25451 /* Parse a .object_arch directive. */
25454 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25456 const struct arm_arch_option_table
*opt
;
25460 name
= input_line_pointer
;
25461 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25462 input_line_pointer
++;
25463 saved_char
= *input_line_pointer
;
25464 *input_line_pointer
= 0;
25466 /* Skip the first "all" entry. */
25467 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25468 if (streq (opt
->name
, name
))
25470 object_arch
= &opt
->value
;
25471 *input_line_pointer
= saved_char
;
25472 demand_empty_rest_of_line ();
25476 as_bad (_("unknown architecture `%s'\n"), name
);
25477 *input_line_pointer
= saved_char
;
25478 ignore_rest_of_line ();
25481 /* Parse a .arch_extension directive. */
25484 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25486 const struct arm_option_extension_value_table
*opt
;
25489 int adding_value
= 1;
25491 name
= input_line_pointer
;
25492 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25493 input_line_pointer
++;
25494 saved_char
= *input_line_pointer
;
25495 *input_line_pointer
= 0;
25497 if (strlen (name
) >= 2
25498 && strncmp (name
, "no", 2) == 0)
25504 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25505 if (streq (opt
->name
, name
))
25507 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25509 as_bad (_("architectural extension `%s' is not allowed for the "
25510 "current base architecture"), name
);
25515 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25518 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25520 mcpu_cpu_opt
= &selected_cpu
;
25521 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25522 *input_line_pointer
= saved_char
;
25523 demand_empty_rest_of_line ();
25527 if (opt
->name
== NULL
)
25528 as_bad (_("unknown architecture extension `%s'\n"), name
);
25530 *input_line_pointer
= saved_char
;
25531 ignore_rest_of_line ();
25534 /* Parse a .fpu directive. */
25537 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25539 const struct arm_option_fpu_value_table
*opt
;
25543 name
= input_line_pointer
;
25544 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25545 input_line_pointer
++;
25546 saved_char
= *input_line_pointer
;
25547 *input_line_pointer
= 0;
25549 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25550 if (streq (opt
->name
, name
))
25552 mfpu_opt
= &opt
->value
;
25553 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25554 *input_line_pointer
= saved_char
;
25555 demand_empty_rest_of_line ();
25559 as_bad (_("unknown floating point format `%s'\n"), name
);
25560 *input_line_pointer
= saved_char
;
25561 ignore_rest_of_line ();
25564 /* Copy symbol information. */
25567 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25569 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25573 /* Given a symbolic attribute NAME, return the proper integer value.
25574 Returns -1 if the attribute is not known. */
25577 arm_convert_symbolic_attribute (const char *name
)
25579 static const struct
25584 attribute_table
[] =
25586 /* When you modify this table you should
25587 also modify the list in doc/c-arm.texi. */
25588 #define T(tag) {#tag, tag}
25589 T (Tag_CPU_raw_name
),
25592 T (Tag_CPU_arch_profile
),
25593 T (Tag_ARM_ISA_use
),
25594 T (Tag_THUMB_ISA_use
),
25598 T (Tag_Advanced_SIMD_arch
),
25599 T (Tag_PCS_config
),
25600 T (Tag_ABI_PCS_R9_use
),
25601 T (Tag_ABI_PCS_RW_data
),
25602 T (Tag_ABI_PCS_RO_data
),
25603 T (Tag_ABI_PCS_GOT_use
),
25604 T (Tag_ABI_PCS_wchar_t
),
25605 T (Tag_ABI_FP_rounding
),
25606 T (Tag_ABI_FP_denormal
),
25607 T (Tag_ABI_FP_exceptions
),
25608 T (Tag_ABI_FP_user_exceptions
),
25609 T (Tag_ABI_FP_number_model
),
25610 T (Tag_ABI_align_needed
),
25611 T (Tag_ABI_align8_needed
),
25612 T (Tag_ABI_align_preserved
),
25613 T (Tag_ABI_align8_preserved
),
25614 T (Tag_ABI_enum_size
),
25615 T (Tag_ABI_HardFP_use
),
25616 T (Tag_ABI_VFP_args
),
25617 T (Tag_ABI_WMMX_args
),
25618 T (Tag_ABI_optimization_goals
),
25619 T (Tag_ABI_FP_optimization_goals
),
25620 T (Tag_compatibility
),
25621 T (Tag_CPU_unaligned_access
),
25622 T (Tag_FP_HP_extension
),
25623 T (Tag_VFP_HP_extension
),
25624 T (Tag_ABI_FP_16bit_format
),
25625 T (Tag_MPextension_use
),
25627 T (Tag_nodefaults
),
25628 T (Tag_also_compatible_with
),
25629 T (Tag_conformance
),
25631 T (Tag_Virtualization_use
),
25632 /* We deliberately do not include Tag_MPextension_use_legacy. */
25640 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25641 if (streq (name
, attribute_table
[i
].name
))
25642 return attribute_table
[i
].tag
;
25648 /* Apply sym value for relocations only in the case that
25649 they are for local symbols and you have the respective
25650 architectural feature for blx and simple switches. */
25652 arm_apply_sym_value (struct fix
* fixP
)
25655 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25656 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25658 switch (fixP
->fx_r_type
)
25660 case BFD_RELOC_ARM_PCREL_BLX
:
25661 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25662 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25666 case BFD_RELOC_ARM_PCREL_CALL
:
25667 case BFD_RELOC_THUMB_PCREL_BLX
:
25668 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25679 #endif /* OBJ_ELF */