1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[20];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 delim
= get_symbol_name (& name
);
2872 end_name
= input_line_pointer
;
2873 (void) restore_line_pointer (delim
);
2875 if (*input_line_pointer
!= ',')
2878 as_bad (_("expected comma after name \"%s\""), name
);
2880 ignore_rest_of_line ();
2884 input_line_pointer
++;
2887 if (name
[0] == '.' && name
[1] == '\0')
2889 /* XXX - this should not happen to .thumb_set. */
2893 if ((symbolP
= symbol_find (name
)) == NULL
2894 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2897 /* When doing symbol listings, play games with dummy fragments living
2898 outside the normal fragment chain to record the file and line info
2900 if (listing
& LISTING_SYMBOLS
)
2902 extern struct list_info_struct
* listing_tail
;
2903 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2905 memset (dummy_frag
, 0, sizeof (fragS
));
2906 dummy_frag
->fr_type
= rs_fill
;
2907 dummy_frag
->line
= listing_tail
;
2908 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2909 dummy_frag
->fr_symbol
= symbolP
;
2913 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2916 /* "set" symbols are local unless otherwise specified. */
2917 SF_SET_LOCAL (symbolP
);
2918 #endif /* OBJ_COFF */
2919 } /* Make a new symbol. */
2921 symbol_table_insert (symbolP
);
2926 && S_IS_DEFINED (symbolP
)
2927 && S_GET_SEGMENT (symbolP
) != reg_section
)
2928 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2930 pseudo_set (symbolP
);
2932 demand_empty_rest_of_line ();
2934 /* XXX Now we come to the Thumb specific bit of code. */
2936 THUMB_SET_FUNC (symbolP
, 1);
2937 ARM_SET_THUMB (symbolP
, 1);
2938 #if defined OBJ_ELF || defined OBJ_COFF
2939 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2943 /* Directives: Mode selection. */
2945 /* .syntax [unified|divided] - choose the new unified syntax
2946 (same for Arm and Thumb encoding, modulo slight differences in what
2947 can be represented) or the old divergent syntax for each mode. */
2949 s_syntax (int unused ATTRIBUTE_UNUSED
)
2953 delim
= get_symbol_name (& name
);
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 (void) restore_line_pointer (delim
);
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2971 s_bss (int ignore ATTRIBUTE_UNUSED
)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section
, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED
)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg
, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: CodeComposer Studio. */
2997 /* .ref (for CodeComposer Studio syntax only). */
2999 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3001 if (codecomposer_syntax
)
3002 ignore_rest_of_line ();
3004 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3007 /* If name is not NULL, then it is used for marking the beginning of a
3008 function, wherease if it is NULL then it means the function end. */
3010 asmfunc_debug (const char * name
)
3012 static const char * last_name
= NULL
;
3016 gas_assert (last_name
== NULL
);
3019 if (debug_type
== DEBUG_STABS
)
3020 stabs_generate_asm_func (name
, name
);
3024 gas_assert (last_name
!= NULL
);
3026 if (debug_type
== DEBUG_STABS
)
3027 stabs_generate_asm_endfunc (last_name
, last_name
);
3034 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3036 if (codecomposer_syntax
)
3038 switch (asmfunc_state
)
3040 case OUTSIDE_ASMFUNC
:
3041 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3044 case WAITING_ASMFUNC_NAME
:
3045 as_bad (_(".asmfunc repeated."));
3048 case WAITING_ENDASMFUNC
:
3049 as_bad (_(".asmfunc without function."));
3052 demand_empty_rest_of_line ();
3055 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3059 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3063 switch (asmfunc_state
)
3065 case OUTSIDE_ASMFUNC
:
3066 as_bad (_(".endasmfunc without a .asmfunc."));
3069 case WAITING_ASMFUNC_NAME
:
3070 as_bad (_(".endasmfunc without function."));
3073 case WAITING_ENDASMFUNC
:
3074 asmfunc_state
= OUTSIDE_ASMFUNC
;
3075 asmfunc_debug (NULL
);
3078 demand_empty_rest_of_line ();
3081 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3085 s_ccs_def (int name
)
3087 if (codecomposer_syntax
)
3090 as_bad (_(".def pseudo-op only available with -mccs flag."));
3093 /* Directives: Literal pools. */
3095 static literal_pool
*
3096 find_literal_pool (void)
3098 literal_pool
* pool
;
3100 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3102 if (pool
->section
== now_seg
3103 && pool
->sub_section
== now_subseg
)
3110 static literal_pool
*
3111 find_or_make_literal_pool (void)
3113 /* Next literal pool ID number. */
3114 static unsigned int latest_pool_num
= 1;
3115 literal_pool
* pool
;
3117 pool
= find_literal_pool ();
3121 /* Create a new pool. */
3122 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3126 pool
->next_free_entry
= 0;
3127 pool
->section
= now_seg
;
3128 pool
->sub_section
= now_subseg
;
3129 pool
->next
= list_of_pools
;
3130 pool
->symbol
= NULL
;
3131 pool
->alignment
= 2;
3133 /* Add it to the list. */
3134 list_of_pools
= pool
;
3137 /* New pools, and emptied pools, will have a NULL symbol. */
3138 if (pool
->symbol
== NULL
)
3140 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3141 (valueT
) 0, &zero_address_frag
);
3142 pool
->id
= latest_pool_num
++;
3149 /* Add the literal in the global 'inst'
3150 structure to the relevant literal pool. */
3153 add_to_lit_pool (unsigned int nbytes
)
3155 #define PADDING_SLOT 0x1
3156 #define LIT_ENTRY_SIZE_MASK 0xFF
3157 literal_pool
* pool
;
3158 unsigned int entry
, pool_size
= 0;
3159 bfd_boolean padding_slot_p
= FALSE
;
3165 imm1
= inst
.operands
[1].imm
;
3166 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3167 : inst
.reloc
.exp
.X_unsigned
? 0
3168 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3169 if (target_big_endian
)
3172 imm2
= inst
.operands
[1].imm
;
3176 pool
= find_or_make_literal_pool ();
3178 /* Check if this literal value is already in the pool. */
3179 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3183 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3184 && (inst
.reloc
.exp
.X_op
== O_constant
)
3185 && (pool
->literals
[entry
].X_add_number
3186 == inst
.reloc
.exp
.X_add_number
)
3187 && (pool
->literals
[entry
].X_md
== nbytes
)
3188 && (pool
->literals
[entry
].X_unsigned
3189 == inst
.reloc
.exp
.X_unsigned
))
3192 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3193 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3194 && (pool
->literals
[entry
].X_add_number
3195 == inst
.reloc
.exp
.X_add_number
)
3196 && (pool
->literals
[entry
].X_add_symbol
3197 == inst
.reloc
.exp
.X_add_symbol
)
3198 && (pool
->literals
[entry
].X_op_symbol
3199 == inst
.reloc
.exp
.X_op_symbol
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
))
3203 else if ((nbytes
== 8)
3204 && !(pool_size
& 0x7)
3205 && ((entry
+ 1) != pool
->next_free_entry
)
3206 && (pool
->literals
[entry
].X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3208 && (pool
->literals
[entry
].X_unsigned
3209 == inst
.reloc
.exp
.X_unsigned
)
3210 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3211 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3212 && (pool
->literals
[entry
+ 1].X_unsigned
3213 == inst
.reloc
.exp
.X_unsigned
))
3216 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3217 if (padding_slot_p
&& (nbytes
== 4))
3223 /* Do we need to create a new entry? */
3224 if (entry
== pool
->next_free_entry
)
3226 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3228 inst
.error
= _("literal pool overflow");
3234 /* For 8-byte entries, we align to an 8-byte boundary,
3235 and split it into two 4-byte entries, because on 32-bit
3236 host, 8-byte constants are treated as big num, thus
3237 saved in "generic_bignum" which will be overwritten
3238 by later assignments.
3240 We also need to make sure there is enough space for
3243 We also check to make sure the literal operand is a
3245 if (!(inst
.reloc
.exp
.X_op
== O_constant
3246 || inst
.reloc
.exp
.X_op
== O_big
))
3248 inst
.error
= _("invalid type for literal pool");
3251 else if (pool_size
& 0x7)
3253 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3259 pool
->literals
[entry
] = inst
.reloc
.exp
;
3260 pool
->literals
[entry
].X_add_number
= 0;
3261 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3262 pool
->next_free_entry
+= 1;
3265 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_op
= O_constant
;
3273 pool
->literals
[entry
].X_add_number
= imm1
;
3274 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3275 pool
->literals
[entry
++].X_md
= 4;
3276 pool
->literals
[entry
] = inst
.reloc
.exp
;
3277 pool
->literals
[entry
].X_op
= O_constant
;
3278 pool
->literals
[entry
].X_add_number
= imm2
;
3279 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3280 pool
->literals
[entry
].X_md
= 4;
3281 pool
->alignment
= 3;
3282 pool
->next_free_entry
+= 1;
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_md
= 4;
3291 /* PR ld/12974: Record the location of the first source line to reference
3292 this entry in the literal pool. If it turns out during linking that the
3293 symbol does not exist we will be able to give an accurate line number for
3294 the (first use of the) missing reference. */
3295 if (debug_type
== DEBUG_DWARF2
)
3296 dwarf2_where (pool
->locs
+ entry
);
3298 pool
->next_free_entry
+= 1;
3300 else if (padding_slot_p
)
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_md
= nbytes
;
3306 inst
.reloc
.exp
.X_op
= O_symbol
;
3307 inst
.reloc
.exp
.X_add_number
= pool_size
;
3308 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3314 tc_start_label_without_colon (void)
3316 bfd_boolean ret
= TRUE
;
3318 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3320 const char *label
= input_line_pointer
;
3322 while (!is_end_of_line
[(int) label
[-1]])
3327 as_bad (_("Invalid label '%s'"), label
);
3331 asmfunc_debug (label
);
3333 asmfunc_state
= WAITING_ENDASMFUNC
;
3339 /* Can't use symbol_new here, so have to create a symbol and then at
3340 a later date assign it a value. Thats what these functions do. */
3343 symbol_locate (symbolS
* symbolP
,
3344 const char * name
, /* It is copied, the caller can modify. */
3345 segT segment
, /* Segment identifier (SEG_<something>). */
3346 valueT valu
, /* Symbol value. */
3347 fragS
* frag
) /* Associated fragment. */
3350 char * preserved_copy_of_name
;
3352 name_length
= strlen (name
) + 1; /* +1 for \0. */
3353 obstack_grow (¬es
, name
, name_length
);
3354 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3356 #ifdef tc_canonicalize_symbol_name
3357 preserved_copy_of_name
=
3358 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3361 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3363 S_SET_SEGMENT (symbolP
, segment
);
3364 S_SET_VALUE (symbolP
, valu
);
3365 symbol_clear_list_pointers (symbolP
);
3367 symbol_set_frag (symbolP
, frag
);
3369 /* Link to end of symbol chain. */
3371 extern int symbol_table_frozen
;
3373 if (symbol_table_frozen
)
3377 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3379 obj_symbol_new_hook (symbolP
);
3381 #ifdef tc_symbol_new_hook
3382 tc_symbol_new_hook (symbolP
);
3386 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3387 #endif /* DEBUG_SYMS */
3391 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3394 literal_pool
* pool
;
3397 pool
= find_literal_pool ();
3399 || pool
->symbol
== NULL
3400 || pool
->next_free_entry
== 0)
3403 /* Align pool as you have word accesses.
3404 Only make a frag if we have to. */
3406 frag_align (pool
->alignment
, 0, 0);
3408 record_alignment (now_seg
, 2);
3411 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3412 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3414 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3416 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3417 (valueT
) frag_now_fix (), frag_now
);
3418 symbol_table_insert (pool
->symbol
);
3420 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3422 #if defined OBJ_COFF || defined OBJ_ELF
3423 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3426 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3429 if (debug_type
== DEBUG_DWARF2
)
3430 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3432 /* First output the expression in the instruction to the pool. */
3433 emit_expr (&(pool
->literals
[entry
]),
3434 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3437 /* Mark the pool as empty. */
3438 pool
->next_free_entry
= 0;
3439 pool
->symbol
= NULL
;
3443 /* Forward declarations for functions below, in the MD interface
3445 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3446 static valueT
create_unwind_entry (int);
3447 static void start_unwind_section (const segT
, int);
3448 static void add_unwind_opcode (valueT
, int);
3449 static void flush_pending_unwind (void);
3451 /* Directives: Data. */
3454 s_arm_elf_cons (int nbytes
)
3458 #ifdef md_flush_pending_output
3459 md_flush_pending_output ();
3462 if (is_it_end_of_statement ())
3464 demand_empty_rest_of_line ();
3468 #ifdef md_cons_align
3469 md_cons_align (nbytes
);
3472 mapping_state (MAP_DATA
);
3476 char *base
= input_line_pointer
;
3480 if (exp
.X_op
!= O_symbol
)
3481 emit_expr (&exp
, (unsigned int) nbytes
);
3484 char *before_reloc
= input_line_pointer
;
3485 reloc
= parse_reloc (&input_line_pointer
);
3488 as_bad (_("unrecognized relocation suffix"));
3489 ignore_rest_of_line ();
3492 else if (reloc
== BFD_RELOC_UNUSED
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 reloc_howto_type
*howto
= (reloc_howto_type
*)
3497 bfd_reloc_type_lookup (stdoutput
,
3498 (bfd_reloc_code_real_type
) reloc
);
3499 int size
= bfd_get_reloc_size (howto
);
3501 if (reloc
== BFD_RELOC_ARM_PLT32
)
3503 as_bad (_("(plt) is only valid on branch targets"));
3504 reloc
= BFD_RELOC_UNUSED
;
3509 as_bad (_("%s relocations do not fit in %d bytes"),
3510 howto
->name
, nbytes
);
3513 /* We've parsed an expression stopping at O_symbol.
3514 But there may be more expression left now that we
3515 have parsed the relocation marker. Parse it again.
3516 XXX Surely there is a cleaner way to do this. */
3517 char *p
= input_line_pointer
;
3519 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3520 memcpy (save_buf
, base
, input_line_pointer
- base
);
3521 memmove (base
+ (input_line_pointer
- before_reloc
),
3522 base
, before_reloc
- base
);
3524 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3526 memcpy (base
, save_buf
, p
- base
);
3528 offset
= nbytes
- size
;
3529 p
= frag_more (nbytes
);
3530 memset (p
, 0, nbytes
);
3531 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3532 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3537 while (*input_line_pointer
++ == ',');
3539 /* Put terminator back into stream. */
3540 input_line_pointer
--;
3541 demand_empty_rest_of_line ();
3544 /* Emit an expression containing a 32-bit thumb instruction.
3545 Implementation based on put_thumb32_insn. */
3548 emit_thumb32_expr (expressionS
* exp
)
3550 expressionS exp_high
= *exp
;
3552 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3553 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3554 exp
->X_add_number
&= 0xffff;
3555 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3558 /* Guess the instruction size based on the opcode. */
3561 thumb_insn_size (int opcode
)
3563 if ((unsigned int) opcode
< 0xe800u
)
3565 else if ((unsigned int) opcode
>= 0xe8000000u
)
3572 emit_insn (expressionS
*exp
, int nbytes
)
3576 if (exp
->X_op
== O_constant
)
3581 size
= thumb_insn_size (exp
->X_add_number
);
3585 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3587 as_bad (_(".inst.n operand too big. "\
3588 "Use .inst.w instead"));
3593 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3594 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3596 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3598 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3599 emit_thumb32_expr (exp
);
3601 emit_expr (exp
, (unsigned int) size
);
3603 it_fsm_post_encode ();
3607 as_bad (_("cannot determine Thumb instruction size. " \
3608 "Use .inst.n/.inst.w instead"));
3611 as_bad (_("constant expression required"));
3616 /* Like s_arm_elf_cons but do not use md_cons_align and
3617 set the mapping state to MAP_ARM/MAP_THUMB. */
3620 s_arm_elf_inst (int nbytes
)
3622 if (is_it_end_of_statement ())
3624 demand_empty_rest_of_line ();
3628 /* Calling mapping_state () here will not change ARM/THUMB,
3629 but will ensure not to be in DATA state. */
3632 mapping_state (MAP_THUMB
);
3637 as_bad (_("width suffixes are invalid in ARM mode"));
3638 ignore_rest_of_line ();
3644 mapping_state (MAP_ARM
);
3653 if (! emit_insn (& exp
, nbytes
))
3655 ignore_rest_of_line ();
3659 while (*input_line_pointer
++ == ',');
3661 /* Put terminator back into stream. */
3662 input_line_pointer
--;
3663 demand_empty_rest_of_line ();
3666 /* Parse a .rel31 directive. */
3669 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3676 if (*input_line_pointer
== '1')
3677 highbit
= 0x80000000;
3678 else if (*input_line_pointer
!= '0')
3679 as_bad (_("expected 0 or 1"));
3681 input_line_pointer
++;
3682 if (*input_line_pointer
!= ',')
3683 as_bad (_("missing comma"));
3684 input_line_pointer
++;
3686 #ifdef md_flush_pending_output
3687 md_flush_pending_output ();
3690 #ifdef md_cons_align
3694 mapping_state (MAP_DATA
);
3699 md_number_to_chars (p
, highbit
, 4);
3700 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3701 BFD_RELOC_ARM_PREL31
);
3703 demand_empty_rest_of_line ();
3706 /* Directives: AEABI stack-unwind tables. */
3708 /* Parse an unwind_fnstart directive. Simply records the current location. */
3711 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3713 demand_empty_rest_of_line ();
3714 if (unwind
.proc_start
)
3716 as_bad (_("duplicate .fnstart directive"));
3720 /* Mark the start of the function. */
3721 unwind
.proc_start
= expr_build_dot ();
3723 /* Reset the rest of the unwind info. */
3724 unwind
.opcode_count
= 0;
3725 unwind
.table_entry
= NULL
;
3726 unwind
.personality_routine
= NULL
;
3727 unwind
.personality_index
= -1;
3728 unwind
.frame_size
= 0;
3729 unwind
.fp_offset
= 0;
3730 unwind
.fp_reg
= REG_SP
;
3732 unwind
.sp_restored
= 0;
3736 /* Parse a handlerdata directive. Creates the exception handling table entry
3737 for the function. */
3740 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3742 demand_empty_rest_of_line ();
3743 if (!unwind
.proc_start
)
3744 as_bad (MISSING_FNSTART
);
3746 if (unwind
.table_entry
)
3747 as_bad (_("duplicate .handlerdata directive"));
3749 create_unwind_entry (1);
3752 /* Parse an unwind_fnend directive. Generates the index table entry. */
3755 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3760 unsigned int marked_pr_dependency
;
3762 demand_empty_rest_of_line ();
3764 if (!unwind
.proc_start
)
3766 as_bad (_(".fnend directive without .fnstart"));
3770 /* Add eh table entry. */
3771 if (unwind
.table_entry
== NULL
)
3772 val
= create_unwind_entry (0);
3776 /* Add index table entry. This is two words. */
3777 start_unwind_section (unwind
.saved_seg
, 1);
3778 frag_align (2, 0, 0);
3779 record_alignment (now_seg
, 2);
3781 ptr
= frag_more (8);
3783 where
= frag_now_fix () - 8;
3785 /* Self relative offset of the function start. */
3786 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3787 BFD_RELOC_ARM_PREL31
);
3789 /* Indicate dependency on EHABI-defined personality routines to the
3790 linker, if it hasn't been done already. */
3791 marked_pr_dependency
3792 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3793 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3794 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3796 static const char *const name
[] =
3798 "__aeabi_unwind_cpp_pr0",
3799 "__aeabi_unwind_cpp_pr1",
3800 "__aeabi_unwind_cpp_pr2"
3802 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3803 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3804 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3805 |= 1 << unwind
.personality_index
;
3809 /* Inline exception table entry. */
3810 md_number_to_chars (ptr
+ 4, val
, 4);
3812 /* Self relative offset of the table entry. */
3813 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3814 BFD_RELOC_ARM_PREL31
);
3816 /* Restore the original section. */
3817 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3819 unwind
.proc_start
= NULL
;
3823 /* Parse an unwind_cantunwind directive. */
3826 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3828 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3830 as_bad (MISSING_FNSTART
);
3832 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3833 as_bad (_("personality routine specified for cantunwind frame"));
3835 unwind
.personality_index
= -2;
3839 /* Parse a personalityindex directive. */
3842 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3846 if (!unwind
.proc_start
)
3847 as_bad (MISSING_FNSTART
);
3849 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3850 as_bad (_("duplicate .personalityindex directive"));
3854 if (exp
.X_op
!= O_constant
3855 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3857 as_bad (_("bad personality routine number"));
3858 ignore_rest_of_line ();
3862 unwind
.personality_index
= exp
.X_add_number
;
3864 demand_empty_rest_of_line ();
3868 /* Parse a personality directive. */
3871 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("duplicate .personality directive"));
3881 c
= get_symbol_name (& name
);
3882 p
= input_line_pointer
;
3884 ++ input_line_pointer
;
3885 unwind
.personality_routine
= symbol_find_or_make (name
);
3887 demand_empty_rest_of_line ();
3891 /* Parse a directive saving core registers. */
3894 s_arm_unwind_save_core (void)
3900 range
= parse_reg_list (&input_line_pointer
);
3903 as_bad (_("expected register list"));
3904 ignore_rest_of_line ();
3908 demand_empty_rest_of_line ();
3910 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3911 into .unwind_save {..., sp...}. We aren't bothered about the value of
3912 ip because it is clobbered by calls. */
3913 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3914 && (range
& 0x3000) == 0x1000)
3916 unwind
.opcode_count
--;
3917 unwind
.sp_restored
= 0;
3918 range
= (range
| 0x2000) & ~0x1000;
3919 unwind
.pending_offset
= 0;
3925 /* See if we can use the short opcodes. These pop a block of up to 8
3926 registers starting with r4, plus maybe r14. */
3927 for (n
= 0; n
< 8; n
++)
3929 /* Break at the first non-saved register. */
3930 if ((range
& (1 << (n
+ 4))) == 0)
3933 /* See if there are any other bits set. */
3934 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3936 /* Use the long form. */
3937 op
= 0x8000 | ((range
>> 4) & 0xfff);
3938 add_unwind_opcode (op
, 2);
3942 /* Use the short form. */
3944 op
= 0xa8; /* Pop r14. */
3946 op
= 0xa0; /* Do not pop r14. */
3948 add_unwind_opcode (op
, 1);
3955 op
= 0xb100 | (range
& 0xf);
3956 add_unwind_opcode (op
, 2);
3959 /* Record the number of bytes pushed. */
3960 for (n
= 0; n
< 16; n
++)
3962 if (range
& (1 << n
))
3963 unwind
.frame_size
+= 4;
3968 /* Parse a directive saving FPA registers. */
3971 s_arm_unwind_save_fpa (int reg
)
3977 /* Get Number of registers to transfer. */
3978 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3981 exp
.X_op
= O_illegal
;
3983 if (exp
.X_op
!= O_constant
)
3985 as_bad (_("expected , <constant>"));
3986 ignore_rest_of_line ();
3990 num_regs
= exp
.X_add_number
;
3992 if (num_regs
< 1 || num_regs
> 4)
3994 as_bad (_("number of registers must be in the range [1:4]"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4004 op
= 0xb4 | (num_regs
- 1);
4005 add_unwind_opcode (op
, 1);
4010 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4011 add_unwind_opcode (op
, 2);
4013 unwind
.frame_size
+= num_regs
* 12;
4017 /* Parse a directive saving VFP registers for ARMv6 and above. */
4020 s_arm_unwind_save_vfp_armv6 (void)
4025 int num_vfpv3_regs
= 0;
4026 int num_regs_below_16
;
4028 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4031 as_bad (_("expected register list"));
4032 ignore_rest_of_line ();
4036 demand_empty_rest_of_line ();
4038 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4039 than FSTMX/FLDMX-style ones). */
4041 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4043 num_vfpv3_regs
= count
;
4044 else if (start
+ count
> 16)
4045 num_vfpv3_regs
= start
+ count
- 16;
4047 if (num_vfpv3_regs
> 0)
4049 int start_offset
= start
> 16 ? start
- 16 : 0;
4050 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4054 /* Generate opcode for registers numbered in the range 0 .. 15. */
4055 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4056 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4057 if (num_regs_below_16
> 0)
4059 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4060 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= count
* 8;
4067 /* Parse a directive saving VFP registers for pre-ARMv6. */
4070 s_arm_unwind_save_vfp (void)
4076 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4089 op
= 0xb8 | (count
- 1);
4090 add_unwind_opcode (op
, 1);
4095 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4096 add_unwind_opcode (op
, 2);
4098 unwind
.frame_size
+= count
* 8 + 4;
4102 /* Parse a directive saving iWMMXt data registers. */
4105 s_arm_unwind_save_mmxwr (void)
4113 if (*input_line_pointer
== '{')
4114 input_line_pointer
++;
4118 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4122 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4127 as_tsktsk (_("register list not in ascending order"));
4130 if (*input_line_pointer
== '-')
4132 input_line_pointer
++;
4133 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4136 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 else if (reg
>= hi_reg
)
4141 as_bad (_("bad register range"));
4144 for (; reg
< hi_reg
; reg
++)
4148 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4150 skip_past_char (&input_line_pointer
, '}');
4152 demand_empty_rest_of_line ();
4154 /* Generate any deferred opcodes because we're going to be looking at
4156 flush_pending_unwind ();
4158 for (i
= 0; i
< 16; i
++)
4160 if (mask
& (1 << i
))
4161 unwind
.frame_size
+= 8;
4164 /* Attempt to combine with a previous opcode. We do this because gcc
4165 likes to output separate unwind directives for a single block of
4167 if (unwind
.opcode_count
> 0)
4169 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4170 if ((i
& 0xf8) == 0xc0)
4173 /* Only merge if the blocks are contiguous. */
4176 if ((mask
& 0xfe00) == (1 << 9))
4178 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4179 unwind
.opcode_count
--;
4182 else if (i
== 6 && unwind
.opcode_count
>= 2)
4184 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4188 op
= 0xffff << (reg
- 1);
4190 && ((mask
& op
) == (1u << (reg
- 1))))
4192 op
= (1 << (reg
+ i
+ 1)) - 1;
4193 op
&= ~((1 << reg
) - 1);
4195 unwind
.opcode_count
-= 2;
4202 /* We want to generate opcodes in the order the registers have been
4203 saved, ie. descending order. */
4204 for (reg
= 15; reg
>= -1; reg
--)
4206 /* Save registers in blocks. */
4208 || !(mask
& (1 << reg
)))
4210 /* We found an unsaved reg. Generate opcodes to save the
4217 op
= 0xc0 | (hi_reg
- 10);
4218 add_unwind_opcode (op
, 1);
4223 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4224 add_unwind_opcode (op
, 2);
4233 ignore_rest_of_line ();
4237 s_arm_unwind_save_mmxwcg (void)
4244 if (*input_line_pointer
== '{')
4245 input_line_pointer
++;
4247 skip_whitespace (input_line_pointer
);
4251 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4255 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4261 as_tsktsk (_("register list not in ascending order"));
4264 if (*input_line_pointer
== '-')
4266 input_line_pointer
++;
4267 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4270 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 else if (reg
>= hi_reg
)
4275 as_bad (_("bad register range"));
4278 for (; reg
< hi_reg
; reg
++)
4282 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4284 skip_past_char (&input_line_pointer
, '}');
4286 demand_empty_rest_of_line ();
4288 /* Generate any deferred opcodes because we're going to be looking at
4290 flush_pending_unwind ();
4292 for (reg
= 0; reg
< 16; reg
++)
4294 if (mask
& (1 << reg
))
4295 unwind
.frame_size
+= 4;
4298 add_unwind_opcode (op
, 2);
4301 ignore_rest_of_line ();
4305 /* Parse an unwind_save directive.
4306 If the argument is non-zero, this is a .vsave directive. */
4309 s_arm_unwind_save (int arch_v6
)
4312 struct reg_entry
*reg
;
4313 bfd_boolean had_brace
= FALSE
;
4315 if (!unwind
.proc_start
)
4316 as_bad (MISSING_FNSTART
);
4318 /* Figure out what sort of save we have. */
4319 peek
= input_line_pointer
;
4327 reg
= arm_reg_parse_multi (&peek
);
4331 as_bad (_("register expected"));
4332 ignore_rest_of_line ();
4341 as_bad (_("FPA .unwind_save does not take a register list"));
4342 ignore_rest_of_line ();
4345 input_line_pointer
= peek
;
4346 s_arm_unwind_save_fpa (reg
->number
);
4350 s_arm_unwind_save_core ();
4355 s_arm_unwind_save_vfp_armv6 ();
4357 s_arm_unwind_save_vfp ();
4360 case REG_TYPE_MMXWR
:
4361 s_arm_unwind_save_mmxwr ();
4364 case REG_TYPE_MMXWCG
:
4365 s_arm_unwind_save_mmxwcg ();
4369 as_bad (_(".unwind_save does not support this kind of register"));
4370 ignore_rest_of_line ();
4375 /* Parse an unwind_movsp directive. */
4378 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4391 ignore_rest_of_line ();
4395 /* Optional constant. */
4396 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4398 if (immediate_for_directive (&offset
) == FAIL
)
4404 demand_empty_rest_of_line ();
4406 if (reg
== REG_SP
|| reg
== REG_PC
)
4408 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4412 if (unwind
.fp_reg
!= REG_SP
)
4413 as_bad (_("unexpected .unwind_movsp directive"));
4415 /* Generate opcode to restore the value. */
4417 add_unwind_opcode (op
, 1);
4419 /* Record the information for later. */
4420 unwind
.fp_reg
= reg
;
4421 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4422 unwind
.sp_restored
= 1;
4425 /* Parse an unwind_pad directive. */
4428 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 if (immediate_for_directive (&offset
) == FAIL
)
4440 as_bad (_("stack increment must be multiple of 4"));
4441 ignore_rest_of_line ();
4445 /* Don't generate any opcodes, just record the details for later. */
4446 unwind
.frame_size
+= offset
;
4447 unwind
.pending_offset
+= offset
;
4449 demand_empty_rest_of_line ();
4452 /* Parse an unwind_setfp directive. */
4455 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4461 if (!unwind
.proc_start
)
4462 as_bad (MISSING_FNSTART
);
4464 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4465 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4468 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4472 as_bad (_("expected <reg>, <reg>"));
4473 ignore_rest_of_line ();
4477 /* Optional constant. */
4478 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4480 if (immediate_for_directive (&offset
) == FAIL
)
4486 demand_empty_rest_of_line ();
4488 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4490 as_bad (_("register must be either sp or set by a previous"
4491 "unwind_movsp directive"));
4495 /* Don't generate any opcodes, just record the information for later. */
4496 unwind
.fp_reg
= fp_reg
;
4498 if (sp_reg
== REG_SP
)
4499 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4501 unwind
.fp_offset
-= offset
;
4504 /* Parse an unwind_raw directive. */
4507 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4510 /* This is an arbitrary limit. */
4511 unsigned char op
[16];
4514 if (!unwind
.proc_start
)
4515 as_bad (MISSING_FNSTART
);
4518 if (exp
.X_op
== O_constant
4519 && skip_past_comma (&input_line_pointer
) != FAIL
)
4521 unwind
.frame_size
+= exp
.X_add_number
;
4525 exp
.X_op
= O_illegal
;
4527 if (exp
.X_op
!= O_constant
)
4529 as_bad (_("expected <offset>, <opcode>"));
4530 ignore_rest_of_line ();
4536 /* Parse the opcode. */
4541 as_bad (_("unwind opcode too long"));
4542 ignore_rest_of_line ();
4544 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4546 as_bad (_("invalid unwind opcode"));
4547 ignore_rest_of_line ();
4550 op
[count
++] = exp
.X_add_number
;
4552 /* Parse the next byte. */
4553 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 /* Add the opcode bytes in reverse order. */
4561 add_unwind_opcode (op
[count
], 1);
4563 demand_empty_rest_of_line ();
4567 /* Parse a .eabi_attribute directive. */
4570 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4572 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4574 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4575 attributes_set_explicitly
[tag
] = 1;
4578 /* Emit a tls fix for the symbol. */
4581 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4585 #ifdef md_flush_pending_output
4586 md_flush_pending_output ();
4589 #ifdef md_cons_align
4593 /* Since we're just labelling the code, there's no need to define a
4596 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4597 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4598 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4599 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4601 #endif /* OBJ_ELF */
4603 static void s_arm_arch (int);
4604 static void s_arm_object_arch (int);
4605 static void s_arm_cpu (int);
4606 static void s_arm_fpu (int);
4607 static void s_arm_arch_extension (int);
4612 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4619 if (exp
.X_op
== O_symbol
)
4620 exp
.X_op
= O_secrel
;
4622 emit_expr (&exp
, 4);
4624 while (*input_line_pointer
++ == ',');
4626 input_line_pointer
--;
4627 demand_empty_rest_of_line ();
4631 /* This table describes all the machine specific pseudo-ops the assembler
4632 has to support. The fields are:
4633 pseudo-op name without dot
4634 function to call to execute this pseudo-op
4635 Integer arg to pass to the function. */
4637 const pseudo_typeS md_pseudo_table
[] =
4639 /* Never called because '.req' does not start a line. */
4640 { "req", s_req
, 0 },
4641 /* Following two are likewise never called. */
4644 { "unreq", s_unreq
, 0 },
4645 { "bss", s_bss
, 0 },
4646 { "align", s_align_ptwo
, 2 },
4647 { "arm", s_arm
, 0 },
4648 { "thumb", s_thumb
, 0 },
4649 { "code", s_code
, 0 },
4650 { "force_thumb", s_force_thumb
, 0 },
4651 { "thumb_func", s_thumb_func
, 0 },
4652 { "thumb_set", s_thumb_set
, 0 },
4653 { "even", s_even
, 0 },
4654 { "ltorg", s_ltorg
, 0 },
4655 { "pool", s_ltorg
, 0 },
4656 { "syntax", s_syntax
, 0 },
4657 { "cpu", s_arm_cpu
, 0 },
4658 { "arch", s_arm_arch
, 0 },
4659 { "object_arch", s_arm_object_arch
, 0 },
4660 { "fpu", s_arm_fpu
, 0 },
4661 { "arch_extension", s_arm_arch_extension
, 0 },
4663 { "word", s_arm_elf_cons
, 4 },
4664 { "long", s_arm_elf_cons
, 4 },
4665 { "inst.n", s_arm_elf_inst
, 2 },
4666 { "inst.w", s_arm_elf_inst
, 4 },
4667 { "inst", s_arm_elf_inst
, 0 },
4668 { "rel31", s_arm_rel31
, 0 },
4669 { "fnstart", s_arm_unwind_fnstart
, 0 },
4670 { "fnend", s_arm_unwind_fnend
, 0 },
4671 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4672 { "personality", s_arm_unwind_personality
, 0 },
4673 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4674 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4675 { "save", s_arm_unwind_save
, 0 },
4676 { "vsave", s_arm_unwind_save
, 1 },
4677 { "movsp", s_arm_unwind_movsp
, 0 },
4678 { "pad", s_arm_unwind_pad
, 0 },
4679 { "setfp", s_arm_unwind_setfp
, 0 },
4680 { "unwind_raw", s_arm_unwind_raw
, 0 },
4681 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4682 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4686 /* These are used for dwarf. */
4690 /* These are used for dwarf2. */
4691 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4692 { "loc", dwarf2_directive_loc
, 0 },
4693 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4695 { "extend", float_cons
, 'x' },
4696 { "ldouble", float_cons
, 'x' },
4697 { "packed", float_cons
, 'p' },
4699 {"secrel32", pe_directive_secrel
, 0},
4702 /* These are for compatibility with CodeComposer Studio. */
4703 {"ref", s_ccs_ref
, 0},
4704 {"def", s_ccs_def
, 0},
4705 {"asmfunc", s_ccs_asmfunc
, 0},
4706 {"endasmfunc", s_ccs_endasmfunc
, 0},
4711 /* Parser functions used exclusively in instruction operands. */
4713 /* Generic immediate-value read function for use in insn parsing.
4714 STR points to the beginning of the immediate (the leading #);
4715 VAL receives the value; if the value is outside [MIN, MAX]
4716 issue an error. PREFIX_OPT is true if the immediate prefix is
4720 parse_immediate (char **str
, int *val
, int min
, int max
,
4721 bfd_boolean prefix_opt
)
4724 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4725 if (exp
.X_op
!= O_constant
)
4727 inst
.error
= _("constant expression required");
4731 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4733 inst
.error
= _("immediate value out of range");
4737 *val
= exp
.X_add_number
;
4741 /* Less-generic immediate-value read function with the possibility of loading a
4742 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4743 instructions. Puts the result directly in inst.operands[i]. */
4746 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4747 bfd_boolean allow_symbol_p
)
4750 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4753 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4755 if (exp_p
->X_op
== O_constant
)
4757 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4758 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4759 O_constant. We have to be careful not to break compilation for
4760 32-bit X_add_number, though. */
4761 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4763 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4764 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4766 inst
.operands
[i
].regisimm
= 1;
4769 else if (exp_p
->X_op
== O_big
4770 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4772 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4774 /* Bignums have their least significant bits in
4775 generic_bignum[0]. Make sure we put 32 bits in imm and
4776 32 bits in reg, in a (hopefully) portable way. */
4777 gas_assert (parts
!= 0);
4779 /* Make sure that the number is not too big.
4780 PR 11972: Bignums can now be sign-extended to the
4781 size of a .octa so check that the out of range bits
4782 are all zero or all one. */
4783 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4785 LITTLENUM_TYPE m
= -1;
4787 if (generic_bignum
[parts
* 2] != 0
4788 && generic_bignum
[parts
* 2] != m
)
4791 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4792 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4796 inst
.operands
[i
].imm
= 0;
4797 for (j
= 0; j
< parts
; j
++, idx
++)
4798 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4799 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4800 inst
.operands
[i
].reg
= 0;
4801 for (j
= 0; j
< parts
; j
++, idx
++)
4802 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4803 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4804 inst
.operands
[i
].regisimm
= 1;
4806 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4814 /* Returns the pseudo-register number of an FPA immediate constant,
4815 or FAIL if there isn't a valid constant here. */
4818 parse_fpa_immediate (char ** str
)
4820 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4826 /* First try and match exact strings, this is to guarantee
4827 that some formats will work even for cross assembly. */
4829 for (i
= 0; fp_const
[i
]; i
++)
4831 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4835 *str
+= strlen (fp_const
[i
]);
4836 if (is_end_of_line
[(unsigned char) **str
])
4842 /* Just because we didn't get a match doesn't mean that the constant
4843 isn't valid, just that it is in a format that we don't
4844 automatically recognize. Try parsing it with the standard
4845 expression routines. */
4847 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4849 /* Look for a raw floating point number. */
4850 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4851 && is_end_of_line
[(unsigned char) *save_in
])
4853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4855 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4857 if (words
[j
] != fp_values
[i
][j
])
4861 if (j
== MAX_LITTLENUMS
)
4869 /* Try and parse a more complex expression, this will probably fail
4870 unless the code uses a floating point prefix (eg "0f"). */
4871 save_in
= input_line_pointer
;
4872 input_line_pointer
= *str
;
4873 if (expression (&exp
) == absolute_section
4874 && exp
.X_op
== O_big
4875 && exp
.X_add_number
< 0)
4877 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4879 #define X_PRECISION 5
4880 #define E_PRECISION 15L
4881 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4893 *str
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4901 *str
= input_line_pointer
;
4902 input_line_pointer
= save_in
;
4903 inst
.error
= _("invalid FPA immediate expression");
4907 /* Returns 1 if a number has "quarter-precision" float format
4908 0baBbbbbbc defgh000 00000000 00000000. */
4911 is_quarter_float (unsigned imm
)
4913 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4914 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4918 /* Detect the presence of a floating point or integer zero constant,
4922 parse_ifimm_zero (char **in
)
4926 if (!is_immediate_prefix (**in
))
4931 /* Accept #0x0 as a synonym for #0. */
4932 if (strncmp (*in
, "0x", 2) == 0)
4935 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4940 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4941 &generic_floating_point_number
);
4944 && generic_floating_point_number
.sign
== '+'
4945 && (generic_floating_point_number
.low
4946 > generic_floating_point_number
.leader
))
4952 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4953 0baBbbbbbc defgh000 00000000 00000000.
4954 The zero and minus-zero cases need special handling, since they can't be
4955 encoded in the "quarter-precision" float format, but can nonetheless be
4956 loaded as integer constants. */
4959 parse_qfloat_immediate (char **ccp
, int *immed
)
4963 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4964 int found_fpchar
= 0;
4966 skip_past_char (&str
, '#');
4968 /* We must not accidentally parse an integer as a floating-point number. Make
4969 sure that the value we parse is not an integer by checking for special
4970 characters '.' or 'e'.
4971 FIXME: This is a horrible hack, but doing better is tricky because type
4972 information isn't in a very usable state at parse time. */
4974 skip_whitespace (fpnum
);
4976 if (strncmp (fpnum
, "0x", 2) == 0)
4980 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4981 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4991 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4993 unsigned fpword
= 0;
4996 /* Our FP word must be 32 bits (single-precision FP). */
4997 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4999 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5003 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5016 /* Shift operands. */
5019 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5022 struct asm_shift_name
5025 enum shift_kind kind
;
5028 /* Third argument to parse_shift. */
5029 enum parse_shift_mode
5031 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5032 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5033 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5034 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5035 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5038 /* Parse a <shift> specifier on an ARM data processing instruction.
5039 This has three forms:
5041 (LSL|LSR|ASL|ASR|ROR) Rs
5042 (LSL|LSR|ASL|ASR|ROR) #imm
5045 Note that ASL is assimilated to LSL in the instruction encoding, and
5046 RRX to ROR #0 (which cannot be written as such). */
5049 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5051 const struct asm_shift_name
*shift_name
;
5052 enum shift_kind shift
;
5057 for (p
= *str
; ISALPHA (*p
); p
++)
5062 inst
.error
= _("shift expression expected");
5066 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5069 if (shift_name
== NULL
)
5071 inst
.error
= _("shift expression expected");
5075 shift
= shift_name
->kind
;
5079 case NO_SHIFT_RESTRICT
:
5080 case SHIFT_IMMEDIATE
: break;
5082 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5083 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5085 inst
.error
= _("'LSL' or 'ASR' required");
5090 case SHIFT_LSL_IMMEDIATE
:
5091 if (shift
!= SHIFT_LSL
)
5093 inst
.error
= _("'LSL' required");
5098 case SHIFT_ASR_IMMEDIATE
:
5099 if (shift
!= SHIFT_ASR
)
5101 inst
.error
= _("'ASR' required");
5109 if (shift
!= SHIFT_RRX
)
5111 /* Whitespace can appear here if the next thing is a bare digit. */
5112 skip_whitespace (p
);
5114 if (mode
== NO_SHIFT_RESTRICT
5115 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5117 inst
.operands
[i
].imm
= reg
;
5118 inst
.operands
[i
].immisreg
= 1;
5120 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5123 inst
.operands
[i
].shift_kind
= shift
;
5124 inst
.operands
[i
].shifted
= 1;
5129 /* Parse a <shifter_operand> for an ARM data processing instruction:
5132 #<immediate>, <rotate>
5136 where <shift> is defined by parse_shift above, and <rotate> is a
5137 multiple of 2 between 0 and 30. Validation of immediate operands
5138 is deferred to md_apply_fix. */
5141 parse_shifter_operand (char **str
, int i
)
5146 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5148 inst
.operands
[i
].reg
= value
;
5149 inst
.operands
[i
].isreg
= 1;
5151 /* parse_shift will override this if appropriate */
5152 inst
.reloc
.exp
.X_op
= O_constant
;
5153 inst
.reloc
.exp
.X_add_number
= 0;
5155 if (skip_past_comma (str
) == FAIL
)
5158 /* Shift operation on register. */
5159 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5162 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5165 if (skip_past_comma (str
) == SUCCESS
)
5167 /* #x, y -- ie explicit rotation by Y. */
5168 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5171 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression expected");
5177 value
= exp
.X_add_number
;
5178 if (value
< 0 || value
> 30 || value
% 2 != 0)
5180 inst
.error
= _("invalid rotation");
5183 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5185 inst
.error
= _("invalid constant");
5189 /* Encode as specified. */
5190 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5194 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5195 inst
.reloc
.pc_rel
= 0;
5199 /* Group relocation information. Each entry in the table contains the
5200 textual name of the relocation as may appear in assembler source
5201 and must end with a colon.
5202 Along with this textual name are the relocation codes to be used if
5203 the corresponding instruction is an ALU instruction (ADD or SUB only),
5204 an LDR, an LDRS, or an LDC. */
5206 struct group_reloc_table_entry
5217 /* Varieties of non-ALU group relocation. */
5224 static struct group_reloc_table_entry group_reloc_table
[] =
5225 { /* Program counter relative: */
5227 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5232 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5233 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5234 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5235 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5237 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5242 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5243 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5244 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5245 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5247 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5248 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5249 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5250 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5251 /* Section base relative */
5253 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5258 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5259 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5260 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5261 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5263 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5268 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5269 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5270 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5271 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5273 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5274 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5278 /* Given the address of a pointer pointing to the textual name of a group
5279 relocation as may appear in assembler source, attempt to find its details
5280 in group_reloc_table. The pointer will be updated to the character after
5281 the trailing colon. On failure, FAIL will be returned; SUCCESS
5282 otherwise. On success, *entry will be updated to point at the relevant
5283 group_reloc_table entry. */
5286 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5289 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5291 int length
= strlen (group_reloc_table
[i
].name
);
5293 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5294 && (*str
)[length
] == ':')
5296 *out
= &group_reloc_table
[i
];
5297 *str
+= (length
+ 1);
5305 /* Parse a <shifter_operand> for an ARM data processing instruction
5306 (as for parse_shifter_operand) where group relocations are allowed:
5309 #<immediate>, <rotate>
5310 #:<group_reloc>:<expression>
5314 where <group_reloc> is one of the strings defined in group_reloc_table.
5315 The hashes are optional.
5317 Everything else is as for parse_shifter_operand. */
5319 static parse_operand_result
5320 parse_shifter_operand_group_reloc (char **str
, int i
)
5322 /* Determine if we have the sequence of characters #: or just :
5323 coming next. If we do, then we check for a group relocation.
5324 If we don't, punt the whole lot to parse_shifter_operand. */
5326 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5327 || (*str
)[0] == ':')
5329 struct group_reloc_table_entry
*entry
;
5331 if ((*str
)[0] == '#')
5336 /* Try to parse a group relocation. Anything else is an error. */
5337 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5339 inst
.error
= _("unknown group relocation");
5340 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5343 /* We now have the group relocation table entry corresponding to
5344 the name in the assembler source. Next, we parse the expression. */
5345 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5346 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5348 /* Record the relocation type (always the ALU variant here). */
5349 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5350 gas_assert (inst
.reloc
.type
!= 0);
5352 return PARSE_OPERAND_SUCCESS
;
5355 return parse_shifter_operand (str
, i
) == SUCCESS
5356 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5358 /* Never reached. */
5361 /* Parse a Neon alignment expression. Information is written to
5362 inst.operands[i]. We assume the initial ':' has been skipped.
5364 align .imm = align << 8, .immisalign=1, .preind=0 */
5365 static parse_operand_result
5366 parse_neon_alignment (char **str
, int i
)
5371 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5373 if (exp
.X_op
!= O_constant
)
5375 inst
.error
= _("alignment must be constant");
5376 return PARSE_OPERAND_FAIL
;
5379 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5380 inst
.operands
[i
].immisalign
= 1;
5381 /* Alignments are not pre-indexes. */
5382 inst
.operands
[i
].preind
= 0;
5385 return PARSE_OPERAND_SUCCESS
;
5388 /* Parse all forms of an ARM address expression. Information is written
5389 to inst.operands[i] and/or inst.reloc.
5391 Preindexed addressing (.preind=1):
5393 [Rn, #offset] .reg=Rn .reloc.exp=offset
5394 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5395 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5396 .shift_kind=shift .reloc.exp=shift_imm
5398 These three may have a trailing ! which causes .writeback to be set also.
5400 Postindexed addressing (.postind=1, .writeback=1):
5402 [Rn], #offset .reg=Rn .reloc.exp=offset
5403 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5404 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5405 .shift_kind=shift .reloc.exp=shift_imm
5407 Unindexed addressing (.preind=0, .postind=0):
5409 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5413 [Rn]{!} shorthand for [Rn,#0]{!}
5414 =immediate .isreg=0 .reloc.exp=immediate
5415 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5417 It is the caller's responsibility to check for addressing modes not
5418 supported by the instruction, and to set inst.reloc.type. */
5420 static parse_operand_result
5421 parse_address_main (char **str
, int i
, int group_relocations
,
5422 group_reloc_type group_type
)
5427 if (skip_past_char (&p
, '[') == FAIL
)
5429 if (skip_past_char (&p
, '=') == FAIL
)
5431 /* Bare address - translate to PC-relative offset. */
5432 inst
.reloc
.pc_rel
= 1;
5433 inst
.operands
[i
].reg
= REG_PC
;
5434 inst
.operands
[i
].isreg
= 1;
5435 inst
.operands
[i
].preind
= 1;
5437 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5438 return PARSE_OPERAND_FAIL
;
5440 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5441 /*allow_symbol_p=*/TRUE
))
5442 return PARSE_OPERAND_FAIL
;
5445 return PARSE_OPERAND_SUCCESS
;
5448 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5449 skip_whitespace (p
);
5451 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5453 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5454 return PARSE_OPERAND_FAIL
;
5456 inst
.operands
[i
].reg
= reg
;
5457 inst
.operands
[i
].isreg
= 1;
5459 if (skip_past_comma (&p
) == SUCCESS
)
5461 inst
.operands
[i
].preind
= 1;
5464 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5466 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5468 inst
.operands
[i
].imm
= reg
;
5469 inst
.operands
[i
].immisreg
= 1;
5471 if (skip_past_comma (&p
) == SUCCESS
)
5472 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5473 return PARSE_OPERAND_FAIL
;
5475 else if (skip_past_char (&p
, ':') == SUCCESS
)
5477 /* FIXME: '@' should be used here, but it's filtered out by generic
5478 code before we get to see it here. This may be subject to
5480 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5482 if (result
!= PARSE_OPERAND_SUCCESS
)
5487 if (inst
.operands
[i
].negative
)
5489 inst
.operands
[i
].negative
= 0;
5493 if (group_relocations
5494 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5496 struct group_reloc_table_entry
*entry
;
5498 /* Skip over the #: or : sequence. */
5504 /* Try to parse a group relocation. Anything else is an
5506 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5508 inst
.error
= _("unknown group relocation");
5509 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5512 /* We now have the group relocation table entry corresponding to
5513 the name in the assembler source. Next, we parse the
5515 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5516 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5518 /* Record the relocation type. */
5522 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5526 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5530 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5537 if (inst
.reloc
.type
== 0)
5539 inst
.error
= _("this group relocation is not allowed on this instruction");
5540 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5546 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5547 return PARSE_OPERAND_FAIL
;
5548 /* If the offset is 0, find out if it's a +0 or -0. */
5549 if (inst
.reloc
.exp
.X_op
== O_constant
5550 && inst
.reloc
.exp
.X_add_number
== 0)
5552 skip_whitespace (q
);
5556 skip_whitespace (q
);
5559 inst
.operands
[i
].negative
= 1;
5564 else if (skip_past_char (&p
, ':') == SUCCESS
)
5566 /* FIXME: '@' should be used here, but it's filtered out by generic code
5567 before we get to see it here. This may be subject to change. */
5568 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5570 if (result
!= PARSE_OPERAND_SUCCESS
)
5574 if (skip_past_char (&p
, ']') == FAIL
)
5576 inst
.error
= _("']' expected");
5577 return PARSE_OPERAND_FAIL
;
5580 if (skip_past_char (&p
, '!') == SUCCESS
)
5581 inst
.operands
[i
].writeback
= 1;
5583 else if (skip_past_comma (&p
) == SUCCESS
)
5585 if (skip_past_char (&p
, '{') == SUCCESS
)
5587 /* [Rn], {expr} - unindexed, with option */
5588 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5589 0, 255, TRUE
) == FAIL
)
5590 return PARSE_OPERAND_FAIL
;
5592 if (skip_past_char (&p
, '}') == FAIL
)
5594 inst
.error
= _("'}' expected at end of 'option' field");
5595 return PARSE_OPERAND_FAIL
;
5597 if (inst
.operands
[i
].preind
)
5599 inst
.error
= _("cannot combine index with option");
5600 return PARSE_OPERAND_FAIL
;
5603 return PARSE_OPERAND_SUCCESS
;
5607 inst
.operands
[i
].postind
= 1;
5608 inst
.operands
[i
].writeback
= 1;
5610 if (inst
.operands
[i
].preind
)
5612 inst
.error
= _("cannot combine pre- and post-indexing");
5613 return PARSE_OPERAND_FAIL
;
5617 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5619 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5621 /* We might be using the immediate for alignment already. If we
5622 are, OR the register number into the low-order bits. */
5623 if (inst
.operands
[i
].immisalign
)
5624 inst
.operands
[i
].imm
|= reg
;
5626 inst
.operands
[i
].imm
= reg
;
5627 inst
.operands
[i
].immisreg
= 1;
5629 if (skip_past_comma (&p
) == SUCCESS
)
5630 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5631 return PARSE_OPERAND_FAIL
;
5636 if (inst
.operands
[i
].negative
)
5638 inst
.operands
[i
].negative
= 0;
5641 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5642 return PARSE_OPERAND_FAIL
;
5643 /* If the offset is 0, find out if it's a +0 or -0. */
5644 if (inst
.reloc
.exp
.X_op
== O_constant
5645 && inst
.reloc
.exp
.X_add_number
== 0)
5647 skip_whitespace (q
);
5651 skip_whitespace (q
);
5654 inst
.operands
[i
].negative
= 1;
5660 /* If at this point neither .preind nor .postind is set, we have a
5661 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5662 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5664 inst
.operands
[i
].preind
= 1;
5665 inst
.reloc
.exp
.X_op
= O_constant
;
5666 inst
.reloc
.exp
.X_add_number
= 0;
5669 return PARSE_OPERAND_SUCCESS
;
5673 parse_address (char **str
, int i
)
5675 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5679 static parse_operand_result
5680 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5682 return parse_address_main (str
, i
, 1, type
);
5685 /* Parse an operand for a MOVW or MOVT instruction. */
5687 parse_half (char **str
)
5692 skip_past_char (&p
, '#');
5693 if (strncasecmp (p
, ":lower16:", 9) == 0)
5694 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5695 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5696 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5698 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5701 skip_whitespace (p
);
5704 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5707 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5709 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5711 inst
.error
= _("constant expression expected");
5714 if (inst
.reloc
.exp
.X_add_number
< 0
5715 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5717 inst
.error
= _("immediate value out of range");
5725 /* Miscellaneous. */
5727 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5728 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5730 parse_psr (char **str
, bfd_boolean lhs
)
5733 unsigned long psr_field
;
5734 const struct asm_psr
*psr
;
5736 bfd_boolean is_apsr
= FALSE
;
5737 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5739 /* PR gas/12698: If the user has specified -march=all then m_profile will
5740 be TRUE, but we want to ignore it in this case as we are building for any
5741 CPU type, including non-m variants. */
5742 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5745 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5746 feature for ease of use and backwards compatibility. */
5748 if (strncasecmp (p
, "SPSR", 4) == 0)
5751 goto unsupported_psr
;
5753 psr_field
= SPSR_BIT
;
5755 else if (strncasecmp (p
, "CPSR", 4) == 0)
5758 goto unsupported_psr
;
5762 else if (strncasecmp (p
, "APSR", 4) == 0)
5764 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5765 and ARMv7-R architecture CPUs. */
5774 while (ISALNUM (*p
) || *p
== '_');
5776 if (strncasecmp (start
, "iapsr", 5) == 0
5777 || strncasecmp (start
, "eapsr", 5) == 0
5778 || strncasecmp (start
, "xpsr", 4) == 0
5779 || strncasecmp (start
, "psr", 3) == 0)
5780 p
= start
+ strcspn (start
, "rR") + 1;
5782 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5788 /* If APSR is being written, a bitfield may be specified. Note that
5789 APSR itself is handled above. */
5790 if (psr
->field
<= 3)
5792 psr_field
= psr
->field
;
5798 /* M-profile MSR instructions have the mask field set to "10", except
5799 *PSR variants which modify APSR, which may use a different mask (and
5800 have been handled already). Do that by setting the PSR_f field
5802 return psr
->field
| (lhs
? PSR_f
: 0);
5805 goto unsupported_psr
;
5811 /* A suffix follows. */
5817 while (ISALNUM (*p
) || *p
== '_');
5821 /* APSR uses a notation for bits, rather than fields. */
5822 unsigned int nzcvq_bits
= 0;
5823 unsigned int g_bit
= 0;
5826 for (bit
= start
; bit
!= p
; bit
++)
5828 switch (TOLOWER (*bit
))
5831 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5835 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5839 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5843 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5847 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5851 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5855 inst
.error
= _("unexpected bit specified after APSR");
5860 if (nzcvq_bits
== 0x1f)
5865 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5867 inst
.error
= _("selected processor does not "
5868 "support DSP extension");
5875 if ((nzcvq_bits
& 0x20) != 0
5876 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5877 || (g_bit
& 0x2) != 0)
5879 inst
.error
= _("bad bitmask specified after APSR");
5885 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5890 psr_field
|= psr
->field
;
5896 goto error
; /* Garbage after "[CS]PSR". */
5898 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5899 is deprecated, but allow it anyway. */
5903 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5906 else if (!m_profile
)
5907 /* These bits are never right for M-profile devices: don't set them
5908 (only code paths which read/write APSR reach here). */
5909 psr_field
|= (PSR_c
| PSR_f
);
5915 inst
.error
= _("selected processor does not support requested special "
5916 "purpose register");
5920 inst
.error
= _("flag for {c}psr instruction expected");
5924 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5925 value suitable for splatting into the AIF field of the instruction. */
5928 parse_cps_flags (char **str
)
5937 case '\0': case ',':
5940 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5941 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5942 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5945 inst
.error
= _("unrecognized CPS flag");
5950 if (saw_a_flag
== 0)
5952 inst
.error
= _("missing CPS flags");
5960 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5961 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5964 parse_endian_specifier (char **str
)
5969 if (strncasecmp (s
, "BE", 2))
5971 else if (strncasecmp (s
, "LE", 2))
5975 inst
.error
= _("valid endian specifiers are be or le");
5979 if (ISALNUM (s
[2]) || s
[2] == '_')
5981 inst
.error
= _("valid endian specifiers are be or le");
5986 return little_endian
;
5989 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5990 value suitable for poking into the rotate field of an sxt or sxta
5991 instruction, or FAIL on error. */
5994 parse_ror (char **str
)
5999 if (strncasecmp (s
, "ROR", 3) == 0)
6003 inst
.error
= _("missing rotation field after comma");
6007 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6012 case 0: *str
= s
; return 0x0;
6013 case 8: *str
= s
; return 0x1;
6014 case 16: *str
= s
; return 0x2;
6015 case 24: *str
= s
; return 0x3;
6018 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6023 /* Parse a conditional code (from conds[] below). The value returned is in the
6024 range 0 .. 14, or FAIL. */
6026 parse_cond (char **str
)
6029 const struct asm_cond
*c
;
6031 /* Condition codes are always 2 characters, so matching up to
6032 3 characters is sufficient. */
6037 while (ISALPHA (*q
) && n
< 3)
6039 cond
[n
] = TOLOWER (*q
);
6044 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6047 inst
.error
= _("condition required");
6055 /* If the given feature available in the selected CPU, mark it as used.
6056 Returns TRUE iff feature is available. */
6058 mark_feature_used (const arm_feature_set
*feature
)
6060 /* Ensure the option is valid on the current architecture. */
6061 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6064 /* Add the appropriate architecture feature for the barrier option used.
6067 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6069 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6074 /* Parse an option for a barrier instruction. Returns the encoding for the
6077 parse_barrier (char **str
)
6080 const struct asm_barrier_opt
*o
;
6083 while (ISALPHA (*q
))
6086 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6091 if (!mark_feature_used (&o
->arch
))
6098 /* Parse the operands of a table branch instruction. Similar to a memory
6101 parse_tb (char **str
)
6106 if (skip_past_char (&p
, '[') == FAIL
)
6108 inst
.error
= _("'[' expected");
6112 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6114 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6117 inst
.operands
[0].reg
= reg
;
6119 if (skip_past_comma (&p
) == FAIL
)
6121 inst
.error
= _("',' expected");
6125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6127 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6130 inst
.operands
[0].imm
= reg
;
6132 if (skip_past_comma (&p
) == SUCCESS
)
6134 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6136 if (inst
.reloc
.exp
.X_add_number
!= 1)
6138 inst
.error
= _("invalid shift");
6141 inst
.operands
[0].shifted
= 1;
6144 if (skip_past_char (&p
, ']') == FAIL
)
6146 inst
.error
= _("']' expected");
6153 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6154 information on the types the operands can take and how they are encoded.
6155 Up to four operands may be read; this function handles setting the
6156 ".present" field for each read operand itself.
6157 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6158 else returns FAIL. */
6161 parse_neon_mov (char **str
, int *which_operand
)
6163 int i
= *which_operand
, val
;
6164 enum arm_reg_type rtype
;
6166 struct neon_type_el optype
;
6168 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6170 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6171 inst
.operands
[i
].reg
= val
;
6172 inst
.operands
[i
].isscalar
= 1;
6173 inst
.operands
[i
].vectype
= optype
;
6174 inst
.operands
[i
++].present
= 1;
6176 if (skip_past_comma (&ptr
) == FAIL
)
6179 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6182 inst
.operands
[i
].reg
= val
;
6183 inst
.operands
[i
].isreg
= 1;
6184 inst
.operands
[i
].present
= 1;
6186 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6189 /* Cases 0, 1, 2, 3, 5 (D only). */
6190 if (skip_past_comma (&ptr
) == FAIL
)
6193 inst
.operands
[i
].reg
= val
;
6194 inst
.operands
[i
].isreg
= 1;
6195 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6196 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6197 inst
.operands
[i
].isvec
= 1;
6198 inst
.operands
[i
].vectype
= optype
;
6199 inst
.operands
[i
++].present
= 1;
6201 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6203 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6204 Case 13: VMOV <Sd>, <Rm> */
6205 inst
.operands
[i
].reg
= val
;
6206 inst
.operands
[i
].isreg
= 1;
6207 inst
.operands
[i
].present
= 1;
6209 if (rtype
== REG_TYPE_NQ
)
6211 first_error (_("can't use Neon quad register here"));
6214 else if (rtype
!= REG_TYPE_VFS
)
6217 if (skip_past_comma (&ptr
) == FAIL
)
6219 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6221 inst
.operands
[i
].reg
= val
;
6222 inst
.operands
[i
].isreg
= 1;
6223 inst
.operands
[i
].present
= 1;
6226 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6229 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6230 Case 1: VMOV<c><q> <Dd>, <Dm>
6231 Case 8: VMOV.F32 <Sd>, <Sm>
6232 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6237 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6238 inst
.operands
[i
].isvec
= 1;
6239 inst
.operands
[i
].vectype
= optype
;
6240 inst
.operands
[i
].present
= 1;
6242 if (skip_past_comma (&ptr
) == SUCCESS
)
6247 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6250 inst
.operands
[i
].reg
= val
;
6251 inst
.operands
[i
].isreg
= 1;
6252 inst
.operands
[i
++].present
= 1;
6254 if (skip_past_comma (&ptr
) == FAIL
)
6257 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6260 inst
.operands
[i
].reg
= val
;
6261 inst
.operands
[i
].isreg
= 1;
6262 inst
.operands
[i
].present
= 1;
6265 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6266 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6267 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6268 Case 10: VMOV.F32 <Sd>, #<imm>
6269 Case 11: VMOV.F64 <Dd>, #<imm> */
6270 inst
.operands
[i
].immisfloat
= 1;
6271 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6273 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6274 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6278 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6282 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isreg
= 1;
6287 inst
.operands
[i
++].present
= 1;
6289 if (skip_past_comma (&ptr
) == FAIL
)
6292 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6294 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6295 inst
.operands
[i
].reg
= val
;
6296 inst
.operands
[i
].isscalar
= 1;
6297 inst
.operands
[i
].present
= 1;
6298 inst
.operands
[i
].vectype
= optype
;
6300 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6302 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
++].present
= 1;
6307 if (skip_past_comma (&ptr
) == FAIL
)
6310 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6313 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6317 inst
.operands
[i
].reg
= val
;
6318 inst
.operands
[i
].isreg
= 1;
6319 inst
.operands
[i
].isvec
= 1;
6320 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6321 inst
.operands
[i
].vectype
= optype
;
6322 inst
.operands
[i
].present
= 1;
6324 if (rtype
== REG_TYPE_VFS
)
6328 if (skip_past_comma (&ptr
) == FAIL
)
6330 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6333 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isreg
= 1;
6338 inst
.operands
[i
].isvec
= 1;
6339 inst
.operands
[i
].issingle
= 1;
6340 inst
.operands
[i
].vectype
= optype
;
6341 inst
.operands
[i
].present
= 1;
6344 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6348 inst
.operands
[i
].reg
= val
;
6349 inst
.operands
[i
].isreg
= 1;
6350 inst
.operands
[i
].isvec
= 1;
6351 inst
.operands
[i
].issingle
= 1;
6352 inst
.operands
[i
].vectype
= optype
;
6353 inst
.operands
[i
].present
= 1;
6358 first_error (_("parse error"));
6362 /* Successfully parsed the operands. Update args. */
6368 first_error (_("expected comma"));
6372 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6376 /* Use this macro when the operand constraints are different
6377 for ARM and THUMB (e.g. ldrd). */
6378 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6379 ((arm_operand) | ((thumb_operand) << 16))
6381 /* Matcher codes for parse_operands. */
6382 enum operand_parse_code
6384 OP_stop
, /* end of line */
6386 OP_RR
, /* ARM register */
6387 OP_RRnpc
, /* ARM register, not r15 */
6388 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6389 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6390 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6391 optional trailing ! */
6392 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6393 OP_RCP
, /* Coprocessor number */
6394 OP_RCN
, /* Coprocessor register */
6395 OP_RF
, /* FPA register */
6396 OP_RVS
, /* VFP single precision register */
6397 OP_RVD
, /* VFP double precision register (0..15) */
6398 OP_RND
, /* Neon double precision register (0..31) */
6399 OP_RNQ
, /* Neon quad precision register */
6400 OP_RVSD
, /* VFP single or double precision register */
6401 OP_RNDQ
, /* Neon double or quad precision register */
6402 OP_RNSDQ
, /* Neon single, double or quad precision register */
6403 OP_RNSC
, /* Neon scalar D[X] */
6404 OP_RVC
, /* VFP control register */
6405 OP_RMF
, /* Maverick F register */
6406 OP_RMD
, /* Maverick D register */
6407 OP_RMFX
, /* Maverick FX register */
6408 OP_RMDX
, /* Maverick DX register */
6409 OP_RMAX
, /* Maverick AX register */
6410 OP_RMDS
, /* Maverick DSPSC register */
6411 OP_RIWR
, /* iWMMXt wR register */
6412 OP_RIWC
, /* iWMMXt wC register */
6413 OP_RIWG
, /* iWMMXt wCG register */
6414 OP_RXA
, /* XScale accumulator register */
6416 OP_REGLST
, /* ARM register list */
6417 OP_VRSLST
, /* VFP single-precision register list */
6418 OP_VRDLST
, /* VFP double-precision register list */
6419 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6420 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6421 OP_NSTRLST
, /* Neon element/structure list */
6423 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6424 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6425 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6426 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6427 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6428 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6429 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6430 OP_VMOV
, /* Neon VMOV operands. */
6431 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6432 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6433 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6435 OP_I0
, /* immediate zero */
6436 OP_I7
, /* immediate value 0 .. 7 */
6437 OP_I15
, /* 0 .. 15 */
6438 OP_I16
, /* 1 .. 16 */
6439 OP_I16z
, /* 0 .. 16 */
6440 OP_I31
, /* 0 .. 31 */
6441 OP_I31w
, /* 0 .. 31, optional trailing ! */
6442 OP_I32
, /* 1 .. 32 */
6443 OP_I32z
, /* 0 .. 32 */
6444 OP_I63
, /* 0 .. 63 */
6445 OP_I63s
, /* -64 .. 63 */
6446 OP_I64
, /* 1 .. 64 */
6447 OP_I64z
, /* 0 .. 64 */
6448 OP_I255
, /* 0 .. 255 */
6450 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6451 OP_I7b
, /* 0 .. 7 */
6452 OP_I15b
, /* 0 .. 15 */
6453 OP_I31b
, /* 0 .. 31 */
6455 OP_SH
, /* shifter operand */
6456 OP_SHG
, /* shifter operand with possible group relocation */
6457 OP_ADDR
, /* Memory address expression (any mode) */
6458 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6459 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6460 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6461 OP_EXP
, /* arbitrary expression */
6462 OP_EXPi
, /* same, with optional immediate prefix */
6463 OP_EXPr
, /* same, with optional relocation suffix */
6464 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6466 OP_CPSF
, /* CPS flags */
6467 OP_ENDI
, /* Endianness specifier */
6468 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6469 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6470 OP_COND
, /* conditional code */
6471 OP_TB
, /* Table branch. */
6473 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6475 OP_RRnpc_I0
, /* ARM register or literal 0 */
6476 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6477 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6478 OP_RF_IF
, /* FPA register or immediate */
6479 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6480 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6482 /* Optional operands. */
6483 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6484 OP_oI31b
, /* 0 .. 31 */
6485 OP_oI32b
, /* 1 .. 32 */
6486 OP_oI32z
, /* 0 .. 32 */
6487 OP_oIffffb
, /* 0 .. 65535 */
6488 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6490 OP_oRR
, /* ARM register */
6491 OP_oRRnpc
, /* ARM register, not the PC */
6492 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6493 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6494 OP_oRND
, /* Optional Neon double precision register */
6495 OP_oRNQ
, /* Optional Neon quad precision register */
6496 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6497 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6498 OP_oSHll
, /* LSL immediate */
6499 OP_oSHar
, /* ASR immediate */
6500 OP_oSHllar
, /* LSL or ASR immediate */
6501 OP_oROR
, /* ROR 0/8/16/24 */
6502 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6504 /* Some pre-defined mixed (ARM/THUMB) operands. */
6505 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6506 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6507 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6509 OP_FIRST_OPTIONAL
= OP_oI7b
6512 /* Generic instruction operand parser. This does no encoding and no
6513 semantic validation; it merely squirrels values away in the inst
6514 structure. Returns SUCCESS or FAIL depending on whether the
6515 specified grammar matched. */
6517 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6519 unsigned const int *upat
= pattern
;
6520 char *backtrack_pos
= 0;
6521 const char *backtrack_error
= 0;
6522 int i
, val
= 0, backtrack_index
= 0;
6523 enum arm_reg_type rtype
;
6524 parse_operand_result result
;
6525 unsigned int op_parse_code
;
6527 #define po_char_or_fail(chr) \
6530 if (skip_past_char (&str, chr) == FAIL) \
6535 #define po_reg_or_fail(regtype) \
6538 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6539 & inst.operands[i].vectype); \
6542 first_error (_(reg_expected_msgs[regtype])); \
6545 inst.operands[i].reg = val; \
6546 inst.operands[i].isreg = 1; \
6547 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6548 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6549 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6550 || rtype == REG_TYPE_VFD \
6551 || rtype == REG_TYPE_NQ); \
6555 #define po_reg_or_goto(regtype, label) \
6558 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6559 & inst.operands[i].vectype); \
6563 inst.operands[i].reg = val; \
6564 inst.operands[i].isreg = 1; \
6565 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6566 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6567 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6568 || rtype == REG_TYPE_VFD \
6569 || rtype == REG_TYPE_NQ); \
6573 #define po_imm_or_fail(min, max, popt) \
6576 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6578 inst.operands[i].imm = val; \
6582 #define po_scalar_or_goto(elsz, label) \
6585 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6588 inst.operands[i].reg = val; \
6589 inst.operands[i].isscalar = 1; \
6593 #define po_misc_or_fail(expr) \
6601 #define po_misc_or_fail_no_backtrack(expr) \
6605 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6606 backtrack_pos = 0; \
6607 if (result != PARSE_OPERAND_SUCCESS) \
6612 #define po_barrier_or_imm(str) \
6615 val = parse_barrier (&str); \
6616 if (val == FAIL && ! ISALPHA (*str)) \
6619 /* ISB can only take SY as an option. */ \
6620 || ((inst.instruction & 0xf0) == 0x60 \
6623 inst.error = _("invalid barrier type"); \
6624 backtrack_pos = 0; \
6630 skip_whitespace (str
);
6632 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6634 op_parse_code
= upat
[i
];
6635 if (op_parse_code
>= 1<<16)
6636 op_parse_code
= thumb
? (op_parse_code
>> 16)
6637 : (op_parse_code
& ((1<<16)-1));
6639 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6641 /* Remember where we are in case we need to backtrack. */
6642 gas_assert (!backtrack_pos
);
6643 backtrack_pos
= str
;
6644 backtrack_error
= inst
.error
;
6645 backtrack_index
= i
;
6648 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6649 po_char_or_fail (',');
6651 switch (op_parse_code
)
6659 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6660 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6661 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6662 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6663 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6664 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6666 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6668 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6670 /* Also accept generic coprocessor regs for unknown registers. */
6672 po_reg_or_fail (REG_TYPE_CN
);
6674 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6675 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6676 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6677 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6678 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6679 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6680 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6681 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6682 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6683 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6685 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6687 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6688 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6690 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6692 /* Neon scalar. Using an element size of 8 means that some invalid
6693 scalars are accepted here, so deal with those in later code. */
6694 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6698 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6701 po_imm_or_fail (0, 0, TRUE
);
6706 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6711 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6714 if (parse_ifimm_zero (&str
))
6715 inst
.operands
[i
].imm
= 0;
6719 = _("only floating point zero is allowed as immediate value");
6727 po_scalar_or_goto (8, try_rr
);
6730 po_reg_or_fail (REG_TYPE_RN
);
6736 po_scalar_or_goto (8, try_nsdq
);
6739 po_reg_or_fail (REG_TYPE_NSDQ
);
6745 po_scalar_or_goto (8, try_ndq
);
6748 po_reg_or_fail (REG_TYPE_NDQ
);
6754 po_scalar_or_goto (8, try_vfd
);
6757 po_reg_or_fail (REG_TYPE_VFD
);
6762 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6763 not careful then bad things might happen. */
6764 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6769 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6772 /* There's a possibility of getting a 64-bit immediate here, so
6773 we need special handling. */
6774 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6777 inst
.error
= _("immediate value is out of range");
6785 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6788 po_imm_or_fail (0, 63, TRUE
);
6793 po_char_or_fail ('[');
6794 po_reg_or_fail (REG_TYPE_RN
);
6795 po_char_or_fail (']');
6801 po_reg_or_fail (REG_TYPE_RN
);
6802 if (skip_past_char (&str
, '!') == SUCCESS
)
6803 inst
.operands
[i
].writeback
= 1;
6807 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6808 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6809 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6810 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6811 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6812 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6813 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6814 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6815 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6816 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6817 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6818 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6820 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6822 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6823 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6825 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6826 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6827 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6828 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6830 /* Immediate variants */
6832 po_char_or_fail ('{');
6833 po_imm_or_fail (0, 255, TRUE
);
6834 po_char_or_fail ('}');
6838 /* The expression parser chokes on a trailing !, so we have
6839 to find it first and zap it. */
6842 while (*s
&& *s
!= ',')
6847 inst
.operands
[i
].writeback
= 1;
6849 po_imm_or_fail (0, 31, TRUE
);
6857 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6862 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6867 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6869 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6871 val
= parse_reloc (&str
);
6874 inst
.error
= _("unrecognized relocation suffix");
6877 else if (val
!= BFD_RELOC_UNUSED
)
6879 inst
.operands
[i
].imm
= val
;
6880 inst
.operands
[i
].hasreloc
= 1;
6885 /* Operand for MOVW or MOVT. */
6887 po_misc_or_fail (parse_half (&str
));
6890 /* Register or expression. */
6891 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6892 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6894 /* Register or immediate. */
6895 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6896 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6898 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6900 if (!is_immediate_prefix (*str
))
6903 val
= parse_fpa_immediate (&str
);
6906 /* FPA immediates are encoded as registers 8-15.
6907 parse_fpa_immediate has already applied the offset. */
6908 inst
.operands
[i
].reg
= val
;
6909 inst
.operands
[i
].isreg
= 1;
6912 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6913 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6915 /* Two kinds of register. */
6918 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6920 || (rege
->type
!= REG_TYPE_MMXWR
6921 && rege
->type
!= REG_TYPE_MMXWC
6922 && rege
->type
!= REG_TYPE_MMXWCG
))
6924 inst
.error
= _("iWMMXt data or control register expected");
6927 inst
.operands
[i
].reg
= rege
->number
;
6928 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6934 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6936 || (rege
->type
!= REG_TYPE_MMXWC
6937 && rege
->type
!= REG_TYPE_MMXWCG
))
6939 inst
.error
= _("iWMMXt control register expected");
6942 inst
.operands
[i
].reg
= rege
->number
;
6943 inst
.operands
[i
].isreg
= 1;
6948 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6949 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6950 case OP_oROR
: val
= parse_ror (&str
); break;
6951 case OP_COND
: val
= parse_cond (&str
); break;
6952 case OP_oBARRIER_I15
:
6953 po_barrier_or_imm (str
); break;
6955 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6961 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6962 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6964 inst
.error
= _("Banked registers are not available with this "
6970 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6974 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6977 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6979 if (strncasecmp (str
, "APSR_", 5) == 0)
6986 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6987 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6988 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6989 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6990 default: found
= 16;
6994 inst
.operands
[i
].isvec
= 1;
6995 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6996 inst
.operands
[i
].reg
= REG_PC
;
7003 po_misc_or_fail (parse_tb (&str
));
7006 /* Register lists. */
7008 val
= parse_reg_list (&str
);
7011 inst
.operands
[i
].writeback
= 1;
7017 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7021 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7025 /* Allow Q registers too. */
7026 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7031 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7033 inst
.operands
[i
].issingle
= 1;
7038 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7043 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7044 &inst
.operands
[i
].vectype
);
7047 /* Addressing modes */
7049 po_misc_or_fail (parse_address (&str
, i
));
7053 po_misc_or_fail_no_backtrack (
7054 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7058 po_misc_or_fail_no_backtrack (
7059 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7063 po_misc_or_fail_no_backtrack (
7064 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7068 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7072 po_misc_or_fail_no_backtrack (
7073 parse_shifter_operand_group_reloc (&str
, i
));
7077 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7081 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7085 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7089 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7092 /* Various value-based sanity checks and shared operations. We
7093 do not signal immediate failures for the register constraints;
7094 this allows a syntax error to take precedence. */
7095 switch (op_parse_code
)
7103 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7104 inst
.error
= BAD_PC
;
7109 if (inst
.operands
[i
].isreg
)
7111 if (inst
.operands
[i
].reg
== REG_PC
)
7112 inst
.error
= BAD_PC
;
7113 else if (inst
.operands
[i
].reg
== REG_SP
)
7114 inst
.error
= BAD_SP
;
7119 if (inst
.operands
[i
].isreg
7120 && inst
.operands
[i
].reg
== REG_PC
7121 && (inst
.operands
[i
].writeback
|| thumb
))
7122 inst
.error
= BAD_PC
;
7131 case OP_oBARRIER_I15
:
7140 inst
.operands
[i
].imm
= val
;
7147 /* If we get here, this operand was successfully parsed. */
7148 inst
.operands
[i
].present
= 1;
7152 inst
.error
= BAD_ARGS
;
7157 /* The parse routine should already have set inst.error, but set a
7158 default here just in case. */
7160 inst
.error
= _("syntax error");
7164 /* Do not backtrack over a trailing optional argument that
7165 absorbed some text. We will only fail again, with the
7166 'garbage following instruction' error message, which is
7167 probably less helpful than the current one. */
7168 if (backtrack_index
== i
&& backtrack_pos
!= str
7169 && upat
[i
+1] == OP_stop
)
7172 inst
.error
= _("syntax error");
7176 /* Try again, skipping the optional argument at backtrack_pos. */
7177 str
= backtrack_pos
;
7178 inst
.error
= backtrack_error
;
7179 inst
.operands
[backtrack_index
].present
= 0;
7180 i
= backtrack_index
;
7184 /* Check that we have parsed all the arguments. */
7185 if (*str
!= '\0' && !inst
.error
)
7186 inst
.error
= _("garbage following instruction");
7188 return inst
.error
? FAIL
: SUCCESS
;
7191 #undef po_char_or_fail
7192 #undef po_reg_or_fail
7193 #undef po_reg_or_goto
7194 #undef po_imm_or_fail
7195 #undef po_scalar_or_fail
7196 #undef po_barrier_or_imm
7198 /* Shorthand macro for instruction encoding functions issuing errors. */
7199 #define constraint(expr, err) \
7210 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7211 instructions are unpredictable if these registers are used. This
7212 is the BadReg predicate in ARM's Thumb-2 documentation. */
7213 #define reject_bad_reg(reg) \
7215 if (reg == REG_SP || reg == REG_PC) \
7217 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7222 /* If REG is R13 (the stack pointer), warn that its use is
7224 #define warn_deprecated_sp(reg) \
7226 if (warn_on_deprecated && reg == REG_SP) \
7227 as_tsktsk (_("use of r13 is deprecated")); \
7230 /* Functions for operand encoding. ARM, then Thumb. */
7232 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7234 /* If VAL can be encoded in the immediate field of an ARM instruction,
7235 return the encoded form. Otherwise, return FAIL. */
7238 encode_arm_immediate (unsigned int val
)
7242 for (i
= 0; i
< 32; i
+= 2)
7243 if ((a
= rotate_left (val
, i
)) <= 0xff)
7244 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7249 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7250 return the encoded form. Otherwise, return FAIL. */
7252 encode_thumb32_immediate (unsigned int val
)
7259 for (i
= 1; i
<= 24; i
++)
7262 if ((val
& ~(0xff << i
)) == 0)
7263 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7267 if (val
== ((a
<< 16) | a
))
7269 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7273 if (val
== ((a
<< 16) | a
))
7274 return 0x200 | (a
>> 8);
7278 /* Encode a VFP SP or DP register number into inst.instruction. */
7281 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7283 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7286 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7289 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7292 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7297 first_error (_("D register out of range for selected VFP version"));
7305 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7309 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7313 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7317 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7321 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7325 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7333 /* Encode a <shift> in an ARM-format instruction. The immediate,
7334 if any, is handled by md_apply_fix. */
7336 encode_arm_shift (int i
)
7338 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7339 inst
.instruction
|= SHIFT_ROR
<< 5;
7342 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7343 if (inst
.operands
[i
].immisreg
)
7345 inst
.instruction
|= SHIFT_BY_REG
;
7346 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7354 encode_arm_shifter_operand (int i
)
7356 if (inst
.operands
[i
].isreg
)
7358 inst
.instruction
|= inst
.operands
[i
].reg
;
7359 encode_arm_shift (i
);
7363 inst
.instruction
|= INST_IMMEDIATE
;
7364 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7365 inst
.instruction
|= inst
.operands
[i
].imm
;
7369 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7371 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7374 Generate an error if the operand is not a register. */
7375 constraint (!inst
.operands
[i
].isreg
,
7376 _("Instruction does not support =N addresses"));
7378 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7380 if (inst
.operands
[i
].preind
)
7384 inst
.error
= _("instruction does not accept preindexed addressing");
7387 inst
.instruction
|= PRE_INDEX
;
7388 if (inst
.operands
[i
].writeback
)
7389 inst
.instruction
|= WRITE_BACK
;
7392 else if (inst
.operands
[i
].postind
)
7394 gas_assert (inst
.operands
[i
].writeback
);
7396 inst
.instruction
|= WRITE_BACK
;
7398 else /* unindexed - only for coprocessor */
7400 inst
.error
= _("instruction does not accept unindexed addressing");
7404 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7405 && (((inst
.instruction
& 0x000f0000) >> 16)
7406 == ((inst
.instruction
& 0x0000f000) >> 12)))
7407 as_warn ((inst
.instruction
& LOAD_BIT
)
7408 ? _("destination register same as write-back base")
7409 : _("source register same as write-back base"));
7412 /* inst.operands[i] was set up by parse_address. Encode it into an
7413 ARM-format mode 2 load or store instruction. If is_t is true,
7414 reject forms that cannot be used with a T instruction (i.e. not
7417 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7419 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7421 encode_arm_addr_mode_common (i
, is_t
);
7423 if (inst
.operands
[i
].immisreg
)
7425 constraint ((inst
.operands
[i
].imm
== REG_PC
7426 || (is_pc
&& inst
.operands
[i
].writeback
)),
7428 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7429 inst
.instruction
|= inst
.operands
[i
].imm
;
7430 if (!inst
.operands
[i
].negative
)
7431 inst
.instruction
|= INDEX_UP
;
7432 if (inst
.operands
[i
].shifted
)
7434 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7435 inst
.instruction
|= SHIFT_ROR
<< 5;
7438 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7439 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7443 else /* immediate offset in inst.reloc */
7445 if (is_pc
&& !inst
.reloc
.pc_rel
)
7447 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7449 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7450 cannot use PC in addressing.
7451 PC cannot be used in writeback addressing, either. */
7452 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7455 /* Use of PC in str is deprecated for ARMv7. */
7456 if (warn_on_deprecated
7458 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7459 as_tsktsk (_("use of PC in this instruction is deprecated"));
7462 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7464 /* Prefer + for zero encoded value. */
7465 if (!inst
.operands
[i
].negative
)
7466 inst
.instruction
|= INDEX_UP
;
7467 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7472 /* inst.operands[i] was set up by parse_address. Encode it into an
7473 ARM-format mode 3 load or store instruction. Reject forms that
7474 cannot be used with such instructions. If is_t is true, reject
7475 forms that cannot be used with a T instruction (i.e. not
7478 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7480 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7482 inst
.error
= _("instruction does not accept scaled register index");
7486 encode_arm_addr_mode_common (i
, is_t
);
7488 if (inst
.operands
[i
].immisreg
)
7490 constraint ((inst
.operands
[i
].imm
== REG_PC
7491 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7493 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7495 inst
.instruction
|= inst
.operands
[i
].imm
;
7496 if (!inst
.operands
[i
].negative
)
7497 inst
.instruction
|= INDEX_UP
;
7499 else /* immediate offset in inst.reloc */
7501 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7502 && inst
.operands
[i
].writeback
),
7504 inst
.instruction
|= HWOFFSET_IMM
;
7505 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7507 /* Prefer + for zero encoded value. */
7508 if (!inst
.operands
[i
].negative
)
7509 inst
.instruction
|= INDEX_UP
;
7511 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7516 /* Write immediate bits [7:0] to the following locations:
7518 |28/24|23 19|18 16|15 4|3 0|
7519 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7521 This function is used by VMOV/VMVN/VORR/VBIC. */
7524 neon_write_immbits (unsigned immbits
)
7526 inst
.instruction
|= immbits
& 0xf;
7527 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7528 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7531 /* Invert low-order SIZE bits of XHI:XLO. */
7534 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7536 unsigned immlo
= xlo
? *xlo
: 0;
7537 unsigned immhi
= xhi
? *xhi
: 0;
7542 immlo
= (~immlo
) & 0xff;
7546 immlo
= (~immlo
) & 0xffff;
7550 immhi
= (~immhi
) & 0xffffffff;
7554 immlo
= (~immlo
) & 0xffffffff;
7568 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7572 neon_bits_same_in_bytes (unsigned imm
)
7574 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7575 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7576 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7577 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7580 /* For immediate of above form, return 0bABCD. */
7583 neon_squash_bits (unsigned imm
)
7585 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7586 | ((imm
& 0x01000000) >> 21);
7589 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7592 neon_qfloat_bits (unsigned imm
)
7594 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7597 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7598 the instruction. *OP is passed as the initial value of the op field, and
7599 may be set to a different value depending on the constant (i.e.
7600 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7601 MVN). If the immediate looks like a repeated pattern then also
7602 try smaller element sizes. */
7605 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7606 unsigned *immbits
, int *op
, int size
,
7607 enum neon_el_type type
)
7609 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7611 if (type
== NT_float
&& !float_p
)
7614 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7616 if (size
!= 32 || *op
== 1)
7618 *immbits
= neon_qfloat_bits (immlo
);
7624 if (neon_bits_same_in_bytes (immhi
)
7625 && neon_bits_same_in_bytes (immlo
))
7629 *immbits
= (neon_squash_bits (immhi
) << 4)
7630 | neon_squash_bits (immlo
);
7641 if (immlo
== (immlo
& 0x000000ff))
7646 else if (immlo
== (immlo
& 0x0000ff00))
7648 *immbits
= immlo
>> 8;
7651 else if (immlo
== (immlo
& 0x00ff0000))
7653 *immbits
= immlo
>> 16;
7656 else if (immlo
== (immlo
& 0xff000000))
7658 *immbits
= immlo
>> 24;
7661 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7663 *immbits
= (immlo
>> 8) & 0xff;
7666 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7668 *immbits
= (immlo
>> 16) & 0xff;
7672 if ((immlo
& 0xffff) != (immlo
>> 16))
7679 if (immlo
== (immlo
& 0x000000ff))
7684 else if (immlo
== (immlo
& 0x0000ff00))
7686 *immbits
= immlo
>> 8;
7690 if ((immlo
& 0xff) != (immlo
>> 8))
7695 if (immlo
== (immlo
& 0x000000ff))
7697 /* Don't allow MVN with 8-bit immediate. */
7707 #if defined BFD_HOST_64_BIT
7708 /* Returns TRUE if double precision value V may be cast
7709 to single precision without loss of accuracy. */
7712 is_double_a_single (bfd_int64_t v
)
7714 int exp
= (int)((v
>> 52) & 0x7FF);
7715 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7717 return (exp
== 0 || exp
== 0x7FF
7718 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7719 && (mantissa
& 0x1FFFFFFFl
) == 0;
7722 /* Returns a double precision value casted to single precision
7723 (ignoring the least significant bits in exponent and mantissa). */
7726 double_to_single (bfd_int64_t v
)
7728 int sign
= (int) ((v
>> 63) & 1l);
7729 int exp
= (int) ((v
>> 52) & 0x7FF);
7730 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7736 exp
= exp
- 1023 + 127;
7745 /* No denormalized numbers. */
7751 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7753 #endif /* BFD_HOST_64_BIT */
7762 static void do_vfp_nsyn_opcode (const char *);
7764 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7765 Determine whether it can be performed with a move instruction; if
7766 it can, convert inst.instruction to that move instruction and
7767 return TRUE; if it can't, convert inst.instruction to a literal-pool
7768 load and return FALSE. If this is not a valid thing to do in the
7769 current context, set inst.error and return TRUE.
7771 inst.operands[i] describes the destination register. */
7774 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7777 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7778 bfd_boolean arm_p
= (t
== CONST_ARM
);
7781 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7785 if ((inst
.instruction
& tbit
) == 0)
7787 inst
.error
= _("invalid pseudo operation");
7791 if (inst
.reloc
.exp
.X_op
!= O_constant
7792 && inst
.reloc
.exp
.X_op
!= O_symbol
7793 && inst
.reloc
.exp
.X_op
!= O_big
)
7795 inst
.error
= _("constant expression expected");
7799 if (inst
.reloc
.exp
.X_op
== O_constant
7800 || inst
.reloc
.exp
.X_op
== O_big
)
7802 #if defined BFD_HOST_64_BIT
7807 if (inst
.reloc
.exp
.X_op
== O_big
)
7809 LITTLENUM_TYPE w
[X_PRECISION
];
7812 if (inst
.reloc
.exp
.X_add_number
== -1)
7814 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7816 /* FIXME: Should we check words w[2..5] ? */
7821 #if defined BFD_HOST_64_BIT
7823 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7824 << LITTLENUM_NUMBER_OF_BITS
)
7825 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7826 << LITTLENUM_NUMBER_OF_BITS
)
7827 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7828 << LITTLENUM_NUMBER_OF_BITS
)
7829 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7831 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7832 | (l
[0] & LITTLENUM_MASK
);
7836 v
= inst
.reloc
.exp
.X_add_number
;
7838 if (!inst
.operands
[i
].issingle
)
7842 if ((v
& ~0xFF) == 0)
7844 /* This can be done with a mov(1) instruction. */
7845 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7846 inst
.instruction
|= v
;
7850 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
7852 /* Check if on thumb2 it can be done with a mov.w or mvn.w
7854 unsigned int newimm
;
7855 bfd_boolean isNegated
;
7857 newimm
= encode_thumb32_immediate (v
);
7858 if (newimm
!= (unsigned int) FAIL
)
7862 newimm
= encode_thumb32_immediate (~v
);
7863 if (newimm
!= (unsigned int) FAIL
)
7867 if (newimm
!= (unsigned int) FAIL
)
7869 inst
.instruction
= (0xf04f0000
7870 | (inst
.operands
[i
].reg
<< 8));
7871 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7872 inst
.instruction
|= (newimm
& 0x800) << 15;
7873 inst
.instruction
|= (newimm
& 0x700) << 4;
7874 inst
.instruction
|= (newimm
& 0x0ff);
7877 else if ((v
& ~0xFFFF) == 0)
7879 /* The number can be loaded with a mov.w instruction. */
7880 int imm
= v
& 0xFFFF;
7882 inst
.instruction
= 0xf2400000; /* MOVW. */
7883 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7884 inst
.instruction
|= (imm
& 0xf000) << 4;
7885 inst
.instruction
|= (imm
& 0x0800) << 15;
7886 inst
.instruction
|= (imm
& 0x0700) << 4;
7887 inst
.instruction
|= (imm
& 0x00ff);
7894 int value
= encode_arm_immediate (v
);
7898 /* This can be done with a mov instruction. */
7899 inst
.instruction
&= LITERAL_MASK
;
7900 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7901 inst
.instruction
|= value
& 0xfff;
7905 value
= encode_arm_immediate (~ v
);
7908 /* This can be done with a mvn instruction. */
7909 inst
.instruction
&= LITERAL_MASK
;
7910 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7911 inst
.instruction
|= value
& 0xfff;
7915 else if (t
== CONST_VEC
)
7918 unsigned immbits
= 0;
7919 unsigned immlo
= inst
.operands
[1].imm
;
7920 unsigned immhi
= inst
.operands
[1].regisimm
7921 ? inst
.operands
[1].reg
7922 : inst
.reloc
.exp
.X_unsigned
7924 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7925 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7926 &op
, 64, NT_invtype
);
7930 neon_invert_size (&immlo
, &immhi
, 64);
7932 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7933 &op
, 64, NT_invtype
);
7938 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7944 /* Fill other bits in vmov encoding for both thumb and arm. */
7946 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7948 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7949 neon_write_immbits (immbits
);
7957 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7958 if (inst
.operands
[i
].issingle
7959 && is_quarter_float (inst
.operands
[1].imm
)
7960 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7962 inst
.operands
[1].imm
=
7963 neon_qfloat_bits (v
);
7964 do_vfp_nsyn_opcode ("fconsts");
7968 /* If our host does not support a 64-bit type then we cannot perform
7969 the following optimization. This mean that there will be a
7970 discrepancy between the output produced by an assembler built for
7971 a 32-bit-only host and the output produced from a 64-bit host, but
7972 this cannot be helped. */
7973 #if defined BFD_HOST_64_BIT
7974 else if (!inst
.operands
[1].issingle
7975 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
7977 if (is_double_a_single (v
)
7978 && is_quarter_float (double_to_single (v
)))
7980 inst
.operands
[1].imm
=
7981 neon_qfloat_bits (double_to_single (v
));
7982 do_vfp_nsyn_opcode ("fconstd");
7990 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
7991 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
7994 inst
.operands
[1].reg
= REG_PC
;
7995 inst
.operands
[1].isreg
= 1;
7996 inst
.operands
[1].preind
= 1;
7997 inst
.reloc
.pc_rel
= 1;
7998 inst
.reloc
.type
= (thumb_p
7999 ? BFD_RELOC_ARM_THUMB_OFFSET
8001 ? BFD_RELOC_ARM_HWLITERAL
8002 : BFD_RELOC_ARM_LITERAL
));
8006 /* inst.operands[i] was set up by parse_address. Encode it into an
8007 ARM-format instruction. Reject all forms which cannot be encoded
8008 into a coprocessor load/store instruction. If wb_ok is false,
8009 reject use of writeback; if unind_ok is false, reject use of
8010 unindexed addressing. If reloc_override is not 0, use it instead
8011 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8012 (in which case it is preserved). */
8015 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8017 if (!inst
.operands
[i
].isreg
)
8020 if (! inst
.operands
[0].isvec
)
8022 inst
.error
= _("invalid co-processor operand");
8025 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8029 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8031 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8033 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8035 gas_assert (!inst
.operands
[i
].writeback
);
8038 inst
.error
= _("instruction does not support unindexed addressing");
8041 inst
.instruction
|= inst
.operands
[i
].imm
;
8042 inst
.instruction
|= INDEX_UP
;
8046 if (inst
.operands
[i
].preind
)
8047 inst
.instruction
|= PRE_INDEX
;
8049 if (inst
.operands
[i
].writeback
)
8051 if (inst
.operands
[i
].reg
== REG_PC
)
8053 inst
.error
= _("pc may not be used with write-back");
8058 inst
.error
= _("instruction does not support writeback");
8061 inst
.instruction
|= WRITE_BACK
;
8065 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8066 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8067 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8068 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8071 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8073 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8076 /* Prefer + for zero encoded value. */
8077 if (!inst
.operands
[i
].negative
)
8078 inst
.instruction
|= INDEX_UP
;
8083 /* Functions for instruction encoding, sorted by sub-architecture.
8084 First some generics; their names are taken from the conventional
8085 bit positions for register arguments in ARM format instructions. */
8095 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8102 inst
.instruction
|= inst
.operands
[1].reg
;
8108 inst
.instruction
|= inst
.operands
[0].reg
;
8109 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8122 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8123 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8127 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8129 if (ARM_CPU_IS_ANY (cpu_variant
))
8131 as_tsktsk ("%s", msg
);
8134 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8146 unsigned Rn
= inst
.operands
[2].reg
;
8147 /* Enforce restrictions on SWP instruction. */
8148 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8150 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8151 _("Rn must not overlap other operands"));
8153 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8155 if (!check_obsolete (&arm_ext_v8
,
8156 _("swp{b} use is obsoleted for ARMv8 and later"))
8157 && warn_on_deprecated
8158 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8159 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8163 inst
.instruction
|= inst
.operands
[1].reg
;
8164 inst
.instruction
|= Rn
<< 16;
8170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8172 inst
.instruction
|= inst
.operands
[2].reg
;
8178 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8179 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8180 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8181 || inst
.reloc
.exp
.X_add_number
!= 0),
8183 inst
.instruction
|= inst
.operands
[0].reg
;
8184 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8191 inst
.instruction
|= inst
.operands
[0].imm
;
8197 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8198 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8201 /* ARM instructions, in alphabetical order by function name (except
8202 that wrapper functions appear immediately after the function they
8205 /* This is a pseudo-op of the form "adr rd, label" to be converted
8206 into a relative address of the form "add rd, pc, #label-.-8". */
8211 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8213 /* Frag hacking will turn this into a sub instruction if the offset turns
8214 out to be negative. */
8215 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8216 inst
.reloc
.pc_rel
= 1;
8217 inst
.reloc
.exp
.X_add_number
-= 8;
8220 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8221 into a relative address of the form:
8222 add rd, pc, #low(label-.-8)"
8223 add rd, rd, #high(label-.-8)" */
8228 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8230 /* Frag hacking will turn this into a sub instruction if the offset turns
8231 out to be negative. */
8232 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8233 inst
.reloc
.pc_rel
= 1;
8234 inst
.size
= INSN_SIZE
* 2;
8235 inst
.reloc
.exp
.X_add_number
-= 8;
8241 if (!inst
.operands
[1].present
)
8242 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8244 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8245 encode_arm_shifter_operand (2);
8251 if (inst
.operands
[0].present
)
8252 inst
.instruction
|= inst
.operands
[0].imm
;
8254 inst
.instruction
|= 0xf;
8260 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8261 constraint (msb
> 32, _("bit-field extends past end of register"));
8262 /* The instruction encoding stores the LSB and MSB,
8263 not the LSB and width. */
8264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8265 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8266 inst
.instruction
|= (msb
- 1) << 16;
8274 /* #0 in second position is alternative syntax for bfc, which is
8275 the same instruction but with REG_PC in the Rm field. */
8276 if (!inst
.operands
[1].isreg
)
8277 inst
.operands
[1].reg
= REG_PC
;
8279 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8280 constraint (msb
> 32, _("bit-field extends past end of register"));
8281 /* The instruction encoding stores the LSB and MSB,
8282 not the LSB and width. */
8283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8284 inst
.instruction
|= inst
.operands
[1].reg
;
8285 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8286 inst
.instruction
|= (msb
- 1) << 16;
8292 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8293 _("bit-field extends past end of register"));
8294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8295 inst
.instruction
|= inst
.operands
[1].reg
;
8296 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8297 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8300 /* ARM V5 breakpoint instruction (argument parse)
8301 BKPT <16 bit unsigned immediate>
8302 Instruction is not conditional.
8303 The bit pattern given in insns[] has the COND_ALWAYS condition,
8304 and it is an error if the caller tried to override that. */
8309 /* Top 12 of 16 bits to bits 19:8. */
8310 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8312 /* Bottom 4 of 16 bits to bits 3:0. */
8313 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8317 encode_branch (int default_reloc
)
8319 if (inst
.operands
[0].hasreloc
)
8321 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8322 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8323 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8324 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8325 ? BFD_RELOC_ARM_PLT32
8326 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8329 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8330 inst
.reloc
.pc_rel
= 1;
8337 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8338 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8341 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8348 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8350 if (inst
.cond
== COND_ALWAYS
)
8351 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8353 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8357 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8360 /* ARM V5 branch-link-exchange instruction (argument parse)
8361 BLX <target_addr> ie BLX(1)
8362 BLX{<condition>} <Rm> ie BLX(2)
8363 Unfortunately, there are two different opcodes for this mnemonic.
8364 So, the insns[].value is not used, and the code here zaps values
8365 into inst.instruction.
8366 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8371 if (inst
.operands
[0].isreg
)
8373 /* Arg is a register; the opcode provided by insns[] is correct.
8374 It is not illegal to do "blx pc", just useless. */
8375 if (inst
.operands
[0].reg
== REG_PC
)
8376 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8378 inst
.instruction
|= inst
.operands
[0].reg
;
8382 /* Arg is an address; this instruction cannot be executed
8383 conditionally, and the opcode must be adjusted.
8384 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8385 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8386 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8387 inst
.instruction
= 0xfa000000;
8388 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8395 bfd_boolean want_reloc
;
8397 if (inst
.operands
[0].reg
== REG_PC
)
8398 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8400 inst
.instruction
|= inst
.operands
[0].reg
;
8401 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8402 it is for ARMv4t or earlier. */
8403 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8404 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8408 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8413 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8417 /* ARM v5TEJ. Jump to Jazelle code. */
8422 if (inst
.operands
[0].reg
== REG_PC
)
8423 as_tsktsk (_("use of r15 in bxj is not really useful"));
8425 inst
.instruction
|= inst
.operands
[0].reg
;
8428 /* Co-processor data operation:
8429 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8430 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8434 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8435 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8436 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8437 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8438 inst
.instruction
|= inst
.operands
[4].reg
;
8439 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8445 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8446 encode_arm_shifter_operand (1);
8449 /* Transfer between coprocessor and ARM registers.
8450 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8455 No special properties. */
8457 struct deprecated_coproc_regs_s
8464 arm_feature_set deprecated
;
8465 arm_feature_set obsoleted
;
8466 const char *dep_msg
;
8467 const char *obs_msg
;
8470 #define DEPR_ACCESS_V8 \
8471 N_("This coprocessor register access is deprecated in ARMv8")
8473 /* Table of all deprecated coprocessor registers. */
8474 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8476 {15, 0, 7, 10, 5, /* CP15DMB. */
8477 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8478 DEPR_ACCESS_V8
, NULL
},
8479 {15, 0, 7, 10, 4, /* CP15DSB. */
8480 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8481 DEPR_ACCESS_V8
, NULL
},
8482 {15, 0, 7, 5, 4, /* CP15ISB. */
8483 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8484 DEPR_ACCESS_V8
, NULL
},
8485 {14, 6, 1, 0, 0, /* TEEHBR. */
8486 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8487 DEPR_ACCESS_V8
, NULL
},
8488 {14, 6, 0, 0, 0, /* TEECR. */
8489 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8490 DEPR_ACCESS_V8
, NULL
},
8493 #undef DEPR_ACCESS_V8
8495 static const size_t deprecated_coproc_reg_count
=
8496 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8504 Rd
= inst
.operands
[2].reg
;
8507 if (inst
.instruction
== 0xee000010
8508 || inst
.instruction
== 0xfe000010)
8510 reject_bad_reg (Rd
);
8513 constraint (Rd
== REG_SP
, BAD_SP
);
8518 if (inst
.instruction
== 0xe000010)
8519 constraint (Rd
== REG_PC
, BAD_PC
);
8522 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8524 const struct deprecated_coproc_regs_s
*r
=
8525 deprecated_coproc_regs
+ i
;
8527 if (inst
.operands
[0].reg
== r
->cp
8528 && inst
.operands
[1].imm
== r
->opc1
8529 && inst
.operands
[3].reg
== r
->crn
8530 && inst
.operands
[4].reg
== r
->crm
8531 && inst
.operands
[5].imm
== r
->opc2
)
8533 if (! ARM_CPU_IS_ANY (cpu_variant
)
8534 && warn_on_deprecated
8535 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8536 as_tsktsk ("%s", r
->dep_msg
);
8540 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8541 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8542 inst
.instruction
|= Rd
<< 12;
8543 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8544 inst
.instruction
|= inst
.operands
[4].reg
;
8545 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8548 /* Transfer between coprocessor register and pair of ARM registers.
8549 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8554 Two XScale instructions are special cases of these:
8556 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8557 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8559 Result unpredictable if Rd or Rn is R15. */
8566 Rd
= inst
.operands
[2].reg
;
8567 Rn
= inst
.operands
[3].reg
;
8571 reject_bad_reg (Rd
);
8572 reject_bad_reg (Rn
);
8576 constraint (Rd
== REG_PC
, BAD_PC
);
8577 constraint (Rn
== REG_PC
, BAD_PC
);
8580 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8581 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8582 inst
.instruction
|= Rd
<< 12;
8583 inst
.instruction
|= Rn
<< 16;
8584 inst
.instruction
|= inst
.operands
[4].reg
;
8590 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8591 if (inst
.operands
[1].present
)
8593 inst
.instruction
|= CPSI_MMOD
;
8594 inst
.instruction
|= inst
.operands
[1].imm
;
8601 inst
.instruction
|= inst
.operands
[0].imm
;
8607 unsigned Rd
, Rn
, Rm
;
8609 Rd
= inst
.operands
[0].reg
;
8610 Rn
= (inst
.operands
[1].present
8611 ? inst
.operands
[1].reg
: Rd
);
8612 Rm
= inst
.operands
[2].reg
;
8614 constraint ((Rd
== REG_PC
), BAD_PC
);
8615 constraint ((Rn
== REG_PC
), BAD_PC
);
8616 constraint ((Rm
== REG_PC
), BAD_PC
);
8618 inst
.instruction
|= Rd
<< 16;
8619 inst
.instruction
|= Rn
<< 0;
8620 inst
.instruction
|= Rm
<< 8;
8626 /* There is no IT instruction in ARM mode. We
8627 process it to do the validation as if in
8628 thumb mode, just in case the code gets
8629 assembled for thumb using the unified syntax. */
8634 set_it_insn_type (IT_INSN
);
8635 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8636 now_it
.cc
= inst
.operands
[0].imm
;
8640 /* If there is only one register in the register list,
8641 then return its register number. Otherwise return -1. */
8643 only_one_reg_in_list (int range
)
8645 int i
= ffs (range
) - 1;
8646 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8650 encode_ldmstm(int from_push_pop_mnem
)
8652 int base_reg
= inst
.operands
[0].reg
;
8653 int range
= inst
.operands
[1].imm
;
8656 inst
.instruction
|= base_reg
<< 16;
8657 inst
.instruction
|= range
;
8659 if (inst
.operands
[1].writeback
)
8660 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8662 if (inst
.operands
[0].writeback
)
8664 inst
.instruction
|= WRITE_BACK
;
8665 /* Check for unpredictable uses of writeback. */
8666 if (inst
.instruction
& LOAD_BIT
)
8668 /* Not allowed in LDM type 2. */
8669 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8670 && ((range
& (1 << REG_PC
)) == 0))
8671 as_warn (_("writeback of base register is UNPREDICTABLE"));
8672 /* Only allowed if base reg not in list for other types. */
8673 else if (range
& (1 << base_reg
))
8674 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8678 /* Not allowed for type 2. */
8679 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8680 as_warn (_("writeback of base register is UNPREDICTABLE"));
8681 /* Only allowed if base reg not in list, or first in list. */
8682 else if ((range
& (1 << base_reg
))
8683 && (range
& ((1 << base_reg
) - 1)))
8684 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8688 /* If PUSH/POP has only one register, then use the A2 encoding. */
8689 one_reg
= only_one_reg_in_list (range
);
8690 if (from_push_pop_mnem
&& one_reg
>= 0)
8692 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8694 inst
.instruction
&= A_COND_MASK
;
8695 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8696 inst
.instruction
|= one_reg
<< 12;
8703 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8706 /* ARMv5TE load-consecutive (argument parse)
8715 constraint (inst
.operands
[0].reg
% 2 != 0,
8716 _("first transfer register must be even"));
8717 constraint (inst
.operands
[1].present
8718 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8719 _("can only transfer two consecutive registers"));
8720 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8721 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8723 if (!inst
.operands
[1].present
)
8724 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8726 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8727 register and the first register written; we have to diagnose
8728 overlap between the base and the second register written here. */
8730 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8731 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8732 as_warn (_("base register written back, and overlaps "
8733 "second transfer register"));
8735 if (!(inst
.instruction
& V4_STR_BIT
))
8737 /* For an index-register load, the index register must not overlap the
8738 destination (even if not write-back). */
8739 if (inst
.operands
[2].immisreg
8740 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8741 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8742 as_warn (_("index register overlaps transfer register"));
8744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8745 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8751 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8752 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8753 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8754 || inst
.operands
[1].negative
8755 /* This can arise if the programmer has written
8757 or if they have mistakenly used a register name as the last
8760 It is very difficult to distinguish between these two cases
8761 because "rX" might actually be a label. ie the register
8762 name has been occluded by a symbol of the same name. So we
8763 just generate a general 'bad addressing mode' type error
8764 message and leave it up to the programmer to discover the
8765 true cause and fix their mistake. */
8766 || (inst
.operands
[1].reg
== REG_PC
),
8769 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8770 || inst
.reloc
.exp
.X_add_number
!= 0,
8771 _("offset must be zero in ARM encoding"));
8773 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8776 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8777 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8783 constraint (inst
.operands
[0].reg
% 2 != 0,
8784 _("even register required"));
8785 constraint (inst
.operands
[1].present
8786 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8787 _("can only load two consecutive registers"));
8788 /* If op 1 were present and equal to PC, this function wouldn't
8789 have been called in the first place. */
8790 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8792 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8793 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8796 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8797 which is not a multiple of four is UNPREDICTABLE. */
8799 check_ldr_r15_aligned (void)
8801 constraint (!(inst
.operands
[1].immisreg
)
8802 && (inst
.operands
[0].reg
== REG_PC
8803 && inst
.operands
[1].reg
== REG_PC
8804 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8805 _("ldr to register 15 must be 4-byte alligned"));
8811 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8812 if (!inst
.operands
[1].isreg
)
8813 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8815 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8816 check_ldr_r15_aligned ();
8822 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8824 if (inst
.operands
[1].preind
)
8826 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8827 || inst
.reloc
.exp
.X_add_number
!= 0,
8828 _("this instruction requires a post-indexed address"));
8830 inst
.operands
[1].preind
= 0;
8831 inst
.operands
[1].postind
= 1;
8832 inst
.operands
[1].writeback
= 1;
8834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8835 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8838 /* Halfword and signed-byte load/store operations. */
8843 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8845 if (!inst
.operands
[1].isreg
)
8846 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8848 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8854 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8856 if (inst
.operands
[1].preind
)
8858 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8859 || inst
.reloc
.exp
.X_add_number
!= 0,
8860 _("this instruction requires a post-indexed address"));
8862 inst
.operands
[1].preind
= 0;
8863 inst
.operands
[1].postind
= 1;
8864 inst
.operands
[1].writeback
= 1;
8866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8867 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8870 /* Co-processor register load/store.
8871 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8875 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8876 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8877 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8883 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8884 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8885 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8886 && !(inst
.instruction
& 0x00400000))
8887 as_tsktsk (_("Rd and Rm should be different in mla"));
8889 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8890 inst
.instruction
|= inst
.operands
[1].reg
;
8891 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8892 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8899 encode_arm_shifter_operand (1);
8902 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8909 top
= (inst
.instruction
& 0x00400000) != 0;
8910 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8911 _(":lower16: not allowed this instruction"));
8912 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8913 _(":upper16: not allowed instruction"));
8914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8915 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8917 imm
= inst
.reloc
.exp
.X_add_number
;
8918 /* The value is in two pieces: 0:11, 16:19. */
8919 inst
.instruction
|= (imm
& 0x00000fff);
8920 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8925 do_vfp_nsyn_mrs (void)
8927 if (inst
.operands
[0].isvec
)
8929 if (inst
.operands
[1].reg
!= 1)
8930 first_error (_("operand 1 must be FPSCR"));
8931 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8932 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8933 do_vfp_nsyn_opcode ("fmstat");
8935 else if (inst
.operands
[1].isvec
)
8936 do_vfp_nsyn_opcode ("fmrx");
8944 do_vfp_nsyn_msr (void)
8946 if (inst
.operands
[0].isvec
)
8947 do_vfp_nsyn_opcode ("fmxr");
8957 unsigned Rt
= inst
.operands
[0].reg
;
8959 if (thumb_mode
&& Rt
== REG_SP
)
8961 inst
.error
= BAD_SP
;
8965 /* APSR_ sets isvec. All other refs to PC are illegal. */
8966 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8968 inst
.error
= BAD_PC
;
8972 /* If we get through parsing the register name, we just insert the number
8973 generated into the instruction without further validation. */
8974 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8975 inst
.instruction
|= (Rt
<< 12);
8981 unsigned Rt
= inst
.operands
[1].reg
;
8984 reject_bad_reg (Rt
);
8985 else if (Rt
== REG_PC
)
8987 inst
.error
= BAD_PC
;
8991 /* If we get through parsing the register name, we just insert the number
8992 generated into the instruction without further validation. */
8993 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8994 inst
.instruction
|= (Rt
<< 12);
9002 if (do_vfp_nsyn_mrs () == SUCCESS
)
9005 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9008 if (inst
.operands
[1].isreg
)
9010 br
= inst
.operands
[1].reg
;
9011 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9012 as_bad (_("bad register for mrs"));
9016 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9017 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9019 _("'APSR', 'CPSR' or 'SPSR' expected"));
9020 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9023 inst
.instruction
|= br
;
9026 /* Two possible forms:
9027 "{C|S}PSR_<field>, Rm",
9028 "{C|S}PSR_f, #expression". */
9033 if (do_vfp_nsyn_msr () == SUCCESS
)
9036 inst
.instruction
|= inst
.operands
[0].imm
;
9037 if (inst
.operands
[1].isreg
)
9038 inst
.instruction
|= inst
.operands
[1].reg
;
9041 inst
.instruction
|= INST_IMMEDIATE
;
9042 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9043 inst
.reloc
.pc_rel
= 0;
9050 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9052 if (!inst
.operands
[2].present
)
9053 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9054 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9055 inst
.instruction
|= inst
.operands
[1].reg
;
9056 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9058 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9059 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9060 as_tsktsk (_("Rd and Rm should be different in mul"));
9063 /* Long Multiply Parser
9064 UMULL RdLo, RdHi, Rm, Rs
9065 SMULL RdLo, RdHi, Rm, Rs
9066 UMLAL RdLo, RdHi, Rm, Rs
9067 SMLAL RdLo, RdHi, Rm, Rs. */
9072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9073 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9074 inst
.instruction
|= inst
.operands
[2].reg
;
9075 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9077 /* rdhi and rdlo must be different. */
9078 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9079 as_tsktsk (_("rdhi and rdlo must be different"));
9081 /* rdhi, rdlo and rm must all be different before armv6. */
9082 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9083 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9084 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9085 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9091 if (inst
.operands
[0].present
9092 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9094 /* Architectural NOP hints are CPSR sets with no bits selected. */
9095 inst
.instruction
&= 0xf0000000;
9096 inst
.instruction
|= 0x0320f000;
9097 if (inst
.operands
[0].present
)
9098 inst
.instruction
|= inst
.operands
[0].imm
;
9102 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9103 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9104 Condition defaults to COND_ALWAYS.
9105 Error if Rd, Rn or Rm are R15. */
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9111 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9112 inst
.instruction
|= inst
.operands
[2].reg
;
9113 if (inst
.operands
[3].present
)
9114 encode_arm_shift (3);
9117 /* ARM V6 PKHTB (Argument Parse). */
9122 if (!inst
.operands
[3].present
)
9124 /* If the shift specifier is omitted, turn the instruction
9125 into pkhbt rd, rm, rn. */
9126 inst
.instruction
&= 0xfff00010;
9127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9128 inst
.instruction
|= inst
.operands
[1].reg
;
9129 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9135 inst
.instruction
|= inst
.operands
[2].reg
;
9136 encode_arm_shift (3);
9140 /* ARMv5TE: Preload-Cache
9141 MP Extensions: Preload for write
9145 Syntactically, like LDR with B=1, W=0, L=1. */
9150 constraint (!inst
.operands
[0].isreg
,
9151 _("'[' expected after PLD mnemonic"));
9152 constraint (inst
.operands
[0].postind
,
9153 _("post-indexed expression used in preload instruction"));
9154 constraint (inst
.operands
[0].writeback
,
9155 _("writeback used in preload instruction"));
9156 constraint (!inst
.operands
[0].preind
,
9157 _("unindexed addressing used in preload instruction"));
9158 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9161 /* ARMv7: PLI <addr_mode> */
9165 constraint (!inst
.operands
[0].isreg
,
9166 _("'[' expected after PLI mnemonic"));
9167 constraint (inst
.operands
[0].postind
,
9168 _("post-indexed expression used in preload instruction"));
9169 constraint (inst
.operands
[0].writeback
,
9170 _("writeback used in preload instruction"));
9171 constraint (!inst
.operands
[0].preind
,
9172 _("unindexed addressing used in preload instruction"));
9173 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9174 inst
.instruction
&= ~PRE_INDEX
;
9180 constraint (inst
.operands
[0].writeback
,
9181 _("push/pop do not support {reglist}^"));
9182 inst
.operands
[1] = inst
.operands
[0];
9183 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9184 inst
.operands
[0].isreg
= 1;
9185 inst
.operands
[0].writeback
= 1;
9186 inst
.operands
[0].reg
= REG_SP
;
9187 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9190 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9191 word at the specified address and the following word
9193 Unconditionally executed.
9194 Error if Rn is R15. */
9199 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9200 if (inst
.operands
[0].writeback
)
9201 inst
.instruction
|= WRITE_BACK
;
9204 /* ARM V6 ssat (argument parse). */
9209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9210 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9211 inst
.instruction
|= inst
.operands
[2].reg
;
9213 if (inst
.operands
[3].present
)
9214 encode_arm_shift (3);
9217 /* ARM V6 usat (argument parse). */
9222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9223 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9224 inst
.instruction
|= inst
.operands
[2].reg
;
9226 if (inst
.operands
[3].present
)
9227 encode_arm_shift (3);
9230 /* ARM V6 ssat16 (argument parse). */
9235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9236 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9237 inst
.instruction
|= inst
.operands
[2].reg
;
9243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9244 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9245 inst
.instruction
|= inst
.operands
[2].reg
;
9248 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9249 preserving the other bits.
9251 setend <endian_specifier>, where <endian_specifier> is either
9257 if (warn_on_deprecated
9258 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9259 as_tsktsk (_("setend use is deprecated for ARMv8"));
9261 if (inst
.operands
[0].imm
)
9262 inst
.instruction
|= 0x200;
9268 unsigned int Rm
= (inst
.operands
[1].present
9269 ? inst
.operands
[1].reg
9270 : inst
.operands
[0].reg
);
9272 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9273 inst
.instruction
|= Rm
;
9274 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9276 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9277 inst
.instruction
|= SHIFT_BY_REG
;
9278 /* PR 12854: Error on extraneous shifts. */
9279 constraint (inst
.operands
[2].shifted
,
9280 _("extraneous shift as part of operand to shift insn"));
9283 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9289 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9290 inst
.reloc
.pc_rel
= 0;
9296 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9297 inst
.reloc
.pc_rel
= 0;
9303 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9304 inst
.reloc
.pc_rel
= 0;
9310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9311 _("selected processor does not support SETPAN instruction"));
9313 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9320 _("selected processor does not support SETPAN instruction"));
9322 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9325 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9326 SMLAxy{cond} Rd,Rm,Rs,Rn
9327 SMLAWy{cond} Rd,Rm,Rs,Rn
9328 Error if any register is R15. */
9333 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9334 inst
.instruction
|= inst
.operands
[1].reg
;
9335 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9336 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9339 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9340 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9341 Error if any register is R15.
9342 Warning if Rdlo == Rdhi. */
9347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9348 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9349 inst
.instruction
|= inst
.operands
[2].reg
;
9350 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9352 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9353 as_tsktsk (_("rdhi and rdlo must be different"));
9356 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9357 SMULxy{cond} Rd,Rm,Rs
9358 Error if any register is R15. */
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9364 inst
.instruction
|= inst
.operands
[1].reg
;
9365 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9368 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9369 the same for both ARM and Thumb-2. */
9376 if (inst
.operands
[0].present
)
9378 reg
= inst
.operands
[0].reg
;
9379 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9384 inst
.instruction
|= reg
<< 16;
9385 inst
.instruction
|= inst
.operands
[1].imm
;
9386 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9387 inst
.instruction
|= WRITE_BACK
;
9390 /* ARM V6 strex (argument parse). */
9395 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9396 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9397 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9398 || inst
.operands
[2].negative
9399 /* See comment in do_ldrex(). */
9400 || (inst
.operands
[2].reg
== REG_PC
),
9403 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9404 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9406 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9407 || inst
.reloc
.exp
.X_add_number
!= 0,
9408 _("offset must be zero in ARM encoding"));
9410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9411 inst
.instruction
|= inst
.operands
[1].reg
;
9412 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9413 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9419 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9420 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9421 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9422 || inst
.operands
[2].negative
,
9425 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9426 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9434 constraint (inst
.operands
[1].reg
% 2 != 0,
9435 _("even register required"));
9436 constraint (inst
.operands
[2].present
9437 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9438 _("can only store two consecutive registers"));
9439 /* If op 2 were present and equal to PC, this function wouldn't
9440 have been called in the first place. */
9441 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9443 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9444 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9445 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9448 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9449 inst
.instruction
|= inst
.operands
[1].reg
;
9450 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9457 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9458 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9466 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9467 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9472 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9473 extends it to 32-bits, and adds the result to a value in another
9474 register. You can specify a rotation by 0, 8, 16, or 24 bits
9475 before extracting the 16-bit value.
9476 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9477 Condition defaults to COND_ALWAYS.
9478 Error if any register uses R15. */
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9484 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9485 inst
.instruction
|= inst
.operands
[2].reg
;
9486 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9491 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9492 Condition defaults to COND_ALWAYS.
9493 Error if any register uses R15. */
9498 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9499 inst
.instruction
|= inst
.operands
[1].reg
;
9500 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9503 /* VFP instructions. In a logical order: SP variant first, monad
9504 before dyad, arithmetic then move then load/store. */
9507 do_vfp_sp_monadic (void)
9509 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9510 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9514 do_vfp_sp_dyadic (void)
9516 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9517 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9518 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9522 do_vfp_sp_compare_z (void)
9524 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9528 do_vfp_dp_sp_cvt (void)
9530 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9531 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9535 do_vfp_sp_dp_cvt (void)
9537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9538 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9542 do_vfp_reg_from_sp (void)
9544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9549 do_vfp_reg2_from_sp2 (void)
9551 constraint (inst
.operands
[2].imm
!= 2,
9552 _("only two consecutive VFP SP registers allowed here"));
9553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9554 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9555 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9559 do_vfp_sp_from_reg (void)
9561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9562 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9566 do_vfp_sp2_from_reg2 (void)
9568 constraint (inst
.operands
[0].imm
!= 2,
9569 _("only two consecutive VFP SP registers allowed here"));
9570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9571 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9572 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9576 do_vfp_sp_ldst (void)
9578 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9579 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9583 do_vfp_dp_ldst (void)
9585 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9586 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9591 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9593 if (inst
.operands
[0].writeback
)
9594 inst
.instruction
|= WRITE_BACK
;
9596 constraint (ldstm_type
!= VFP_LDSTMIA
,
9597 _("this addressing mode requires base-register writeback"));
9598 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9599 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9600 inst
.instruction
|= inst
.operands
[1].imm
;
9604 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9608 if (inst
.operands
[0].writeback
)
9609 inst
.instruction
|= WRITE_BACK
;
9611 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9612 _("this addressing mode requires base-register writeback"));
9614 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9615 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9617 count
= inst
.operands
[1].imm
<< 1;
9618 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9621 inst
.instruction
|= count
;
9625 do_vfp_sp_ldstmia (void)
9627 vfp_sp_ldstm (VFP_LDSTMIA
);
9631 do_vfp_sp_ldstmdb (void)
9633 vfp_sp_ldstm (VFP_LDSTMDB
);
9637 do_vfp_dp_ldstmia (void)
9639 vfp_dp_ldstm (VFP_LDSTMIA
);
9643 do_vfp_dp_ldstmdb (void)
9645 vfp_dp_ldstm (VFP_LDSTMDB
);
9649 do_vfp_xp_ldstmia (void)
9651 vfp_dp_ldstm (VFP_LDSTMIAX
);
9655 do_vfp_xp_ldstmdb (void)
9657 vfp_dp_ldstm (VFP_LDSTMDBX
);
9661 do_vfp_dp_rd_rm (void)
9663 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9664 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9668 do_vfp_dp_rn_rd (void)
9670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9671 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9675 do_vfp_dp_rd_rn (void)
9677 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9678 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9682 do_vfp_dp_rd_rn_rm (void)
9684 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9685 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9686 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9696 do_vfp_dp_rm_rd_rn (void)
9698 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9700 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9703 /* VFPv3 instructions. */
9705 do_vfp_sp_const (void)
9707 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9708 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9709 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9713 do_vfp_dp_const (void)
9715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9716 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9717 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9721 vfp_conv (int srcsize
)
9723 int immbits
= srcsize
- inst
.operands
[1].imm
;
9725 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9727 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9728 i.e. immbits must be in range 0 - 16. */
9729 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9732 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9734 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9735 i.e. immbits must be in range 0 - 31. */
9736 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9740 inst
.instruction
|= (immbits
& 1) << 5;
9741 inst
.instruction
|= (immbits
>> 1);
9745 do_vfp_sp_conv_16 (void)
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9752 do_vfp_dp_conv_16 (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9759 do_vfp_sp_conv_32 (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9766 do_vfp_dp_conv_32 (void)
9768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9772 /* FPA instructions. Also in a logical order. */
9777 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9778 inst
.instruction
|= inst
.operands
[1].reg
;
9782 do_fpa_ldmstm (void)
9784 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9785 switch (inst
.operands
[1].imm
)
9787 case 1: inst
.instruction
|= CP_T_X
; break;
9788 case 2: inst
.instruction
|= CP_T_Y
; break;
9789 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9794 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9796 /* The instruction specified "ea" or "fd", so we can only accept
9797 [Rn]{!}. The instruction does not really support stacking or
9798 unstacking, so we have to emulate these by setting appropriate
9799 bits and offsets. */
9800 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9801 || inst
.reloc
.exp
.X_add_number
!= 0,
9802 _("this instruction does not support indexing"));
9804 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9805 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9807 if (!(inst
.instruction
& INDEX_UP
))
9808 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9810 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9812 inst
.operands
[2].preind
= 0;
9813 inst
.operands
[2].postind
= 1;
9817 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9820 /* iWMMXt instructions: strictly in alphabetical order. */
9823 do_iwmmxt_tandorc (void)
9825 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9829 do_iwmmxt_textrc (void)
9831 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9832 inst
.instruction
|= inst
.operands
[1].imm
;
9836 do_iwmmxt_textrm (void)
9838 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9839 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9840 inst
.instruction
|= inst
.operands
[2].imm
;
9844 do_iwmmxt_tinsr (void)
9846 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9847 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9848 inst
.instruction
|= inst
.operands
[2].imm
;
9852 do_iwmmxt_tmia (void)
9854 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9855 inst
.instruction
|= inst
.operands
[1].reg
;
9856 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9860 do_iwmmxt_waligni (void)
9862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9864 inst
.instruction
|= inst
.operands
[2].reg
;
9865 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9869 do_iwmmxt_wmerge (void)
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[2].reg
;
9874 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9878 do_iwmmxt_wmov (void)
9880 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9883 inst
.instruction
|= inst
.operands
[1].reg
;
9887 do_iwmmxt_wldstbh (void)
9890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9894 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9895 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9899 do_iwmmxt_wldstw (void)
9901 /* RIWR_RIWC clears .isreg for a control register. */
9902 if (!inst
.operands
[0].isreg
)
9904 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9905 inst
.instruction
|= 0xf0000000;
9908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9909 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9913 do_iwmmxt_wldstd (void)
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9916 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9917 && inst
.operands
[1].immisreg
)
9919 inst
.instruction
&= ~0x1a000ff;
9920 inst
.instruction
|= (0xfU
<< 28);
9921 if (inst
.operands
[1].preind
)
9922 inst
.instruction
|= PRE_INDEX
;
9923 if (!inst
.operands
[1].negative
)
9924 inst
.instruction
|= INDEX_UP
;
9925 if (inst
.operands
[1].writeback
)
9926 inst
.instruction
|= WRITE_BACK
;
9927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9928 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9929 inst
.instruction
|= inst
.operands
[1].imm
;
9932 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9936 do_iwmmxt_wshufh (void)
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9940 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9941 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9945 do_iwmmxt_wzero (void)
9947 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9948 inst
.instruction
|= inst
.operands
[0].reg
;
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9954 do_iwmmxt_wrwrwr_or_imm5 (void)
9956 if (inst
.operands
[2].isreg
)
9959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9960 _("immediate operand requires iWMMXt2"));
9962 if (inst
.operands
[2].imm
== 0)
9964 switch ((inst
.instruction
>> 20) & 0xf)
9970 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9971 inst
.operands
[2].imm
= 16;
9972 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9978 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9979 inst
.operands
[2].imm
= 32;
9980 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9987 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9989 wrn
= (inst
.instruction
>> 16) & 0xf;
9990 inst
.instruction
&= 0xff0fff0f;
9991 inst
.instruction
|= wrn
;
9992 /* Bail out here; the instruction is now assembled. */
9997 /* Map 32 -> 0, etc. */
9998 inst
.operands
[2].imm
&= 0x1f;
9999 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10003 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10004 operations first, then control, shift, and load/store. */
10006 /* Insns like "foo X,Y,Z". */
10009 do_mav_triple (void)
10011 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10012 inst
.instruction
|= inst
.operands
[1].reg
;
10013 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10016 /* Insns like "foo W,X,Y,Z".
10017 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10024 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10025 inst
.instruction
|= inst
.operands
[3].reg
;
10028 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10030 do_mav_dspsc (void)
10032 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10035 /* Maverick shift immediate instructions.
10036 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10037 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10040 do_mav_shift (void)
10042 int imm
= inst
.operands
[2].imm
;
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10045 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10047 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10048 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10049 Bit 4 should be 0. */
10050 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10052 inst
.instruction
|= imm
;
10055 /* XScale instructions. Also sorted arithmetic before move. */
10057 /* Xscale multiply-accumulate (argument parse)
10060 MIAxycc acc0,Rm,Rs. */
10065 inst
.instruction
|= inst
.operands
[1].reg
;
10066 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10069 /* Xscale move-accumulator-register (argument parse)
10071 MARcc acc0,RdLo,RdHi. */
10076 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10077 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10080 /* Xscale move-register-accumulator (argument parse)
10082 MRAcc RdLo,RdHi,acc0. */
10087 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10089 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10092 /* Encoding functions relevant only to Thumb. */
10094 /* inst.operands[i] is a shifted-register operand; encode
10095 it into inst.instruction in the format used by Thumb32. */
10098 encode_thumb32_shifted_operand (int i
)
10100 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10101 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10103 constraint (inst
.operands
[i
].immisreg
,
10104 _("shift by register not allowed in thumb mode"));
10105 inst
.instruction
|= inst
.operands
[i
].reg
;
10106 if (shift
== SHIFT_RRX
)
10107 inst
.instruction
|= SHIFT_ROR
<< 4;
10110 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10111 _("expression too complex"));
10113 constraint (value
> 32
10114 || (value
== 32 && (shift
== SHIFT_LSL
10115 || shift
== SHIFT_ROR
)),
10116 _("shift expression is too large"));
10120 else if (value
== 32)
10123 inst
.instruction
|= shift
<< 4;
10124 inst
.instruction
|= (value
& 0x1c) << 10;
10125 inst
.instruction
|= (value
& 0x03) << 6;
10130 /* inst.operands[i] was set up by parse_address. Encode it into a
10131 Thumb32 format load or store instruction. Reject forms that cannot
10132 be used with such instructions. If is_t is true, reject forms that
10133 cannot be used with a T instruction; if is_d is true, reject forms
10134 that cannot be used with a D instruction. If it is a store insn,
10135 reject PC in Rn. */
10138 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10140 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10142 constraint (!inst
.operands
[i
].isreg
,
10143 _("Instruction does not support =N addresses"));
10145 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10146 if (inst
.operands
[i
].immisreg
)
10148 constraint (is_pc
, BAD_PC_ADDRESSING
);
10149 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10150 constraint (inst
.operands
[i
].negative
,
10151 _("Thumb does not support negative register indexing"));
10152 constraint (inst
.operands
[i
].postind
,
10153 _("Thumb does not support register post-indexing"));
10154 constraint (inst
.operands
[i
].writeback
,
10155 _("Thumb does not support register indexing with writeback"));
10156 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10157 _("Thumb supports only LSL in shifted register indexing"));
10159 inst
.instruction
|= inst
.operands
[i
].imm
;
10160 if (inst
.operands
[i
].shifted
)
10162 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10163 _("expression too complex"));
10164 constraint (inst
.reloc
.exp
.X_add_number
< 0
10165 || inst
.reloc
.exp
.X_add_number
> 3,
10166 _("shift out of range"));
10167 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10169 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10171 else if (inst
.operands
[i
].preind
)
10173 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10174 constraint (is_t
&& inst
.operands
[i
].writeback
,
10175 _("cannot use writeback with this instruction"));
10176 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10177 BAD_PC_ADDRESSING
);
10181 inst
.instruction
|= 0x01000000;
10182 if (inst
.operands
[i
].writeback
)
10183 inst
.instruction
|= 0x00200000;
10187 inst
.instruction
|= 0x00000c00;
10188 if (inst
.operands
[i
].writeback
)
10189 inst
.instruction
|= 0x00000100;
10191 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10193 else if (inst
.operands
[i
].postind
)
10195 gas_assert (inst
.operands
[i
].writeback
);
10196 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10197 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10200 inst
.instruction
|= 0x00200000;
10202 inst
.instruction
|= 0x00000900;
10203 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10205 else /* unindexed - only for coprocessor */
10206 inst
.error
= _("instruction does not accept unindexed addressing");
10209 /* Table of Thumb instructions which exist in both 16- and 32-bit
10210 encodings (the latter only in post-V6T2 cores). The index is the
10211 value used in the insns table below. When there is more than one
10212 possible 16-bit encoding for the instruction, this table always
10214 Also contains several pseudo-instructions used during relaxation. */
10215 #define T16_32_TAB \
10216 X(_adc, 4140, eb400000), \
10217 X(_adcs, 4140, eb500000), \
10218 X(_add, 1c00, eb000000), \
10219 X(_adds, 1c00, eb100000), \
10220 X(_addi, 0000, f1000000), \
10221 X(_addis, 0000, f1100000), \
10222 X(_add_pc,000f, f20f0000), \
10223 X(_add_sp,000d, f10d0000), \
10224 X(_adr, 000f, f20f0000), \
10225 X(_and, 4000, ea000000), \
10226 X(_ands, 4000, ea100000), \
10227 X(_asr, 1000, fa40f000), \
10228 X(_asrs, 1000, fa50f000), \
10229 X(_b, e000, f000b000), \
10230 X(_bcond, d000, f0008000), \
10231 X(_bic, 4380, ea200000), \
10232 X(_bics, 4380, ea300000), \
10233 X(_cmn, 42c0, eb100f00), \
10234 X(_cmp, 2800, ebb00f00), \
10235 X(_cpsie, b660, f3af8400), \
10236 X(_cpsid, b670, f3af8600), \
10237 X(_cpy, 4600, ea4f0000), \
10238 X(_dec_sp,80dd, f1ad0d00), \
10239 X(_eor, 4040, ea800000), \
10240 X(_eors, 4040, ea900000), \
10241 X(_inc_sp,00dd, f10d0d00), \
10242 X(_ldmia, c800, e8900000), \
10243 X(_ldr, 6800, f8500000), \
10244 X(_ldrb, 7800, f8100000), \
10245 X(_ldrh, 8800, f8300000), \
10246 X(_ldrsb, 5600, f9100000), \
10247 X(_ldrsh, 5e00, f9300000), \
10248 X(_ldr_pc,4800, f85f0000), \
10249 X(_ldr_pc2,4800, f85f0000), \
10250 X(_ldr_sp,9800, f85d0000), \
10251 X(_lsl, 0000, fa00f000), \
10252 X(_lsls, 0000, fa10f000), \
10253 X(_lsr, 0800, fa20f000), \
10254 X(_lsrs, 0800, fa30f000), \
10255 X(_mov, 2000, ea4f0000), \
10256 X(_movs, 2000, ea5f0000), \
10257 X(_mul, 4340, fb00f000), \
10258 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10259 X(_mvn, 43c0, ea6f0000), \
10260 X(_mvns, 43c0, ea7f0000), \
10261 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10262 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10263 X(_orr, 4300, ea400000), \
10264 X(_orrs, 4300, ea500000), \
10265 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10266 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10267 X(_rev, ba00, fa90f080), \
10268 X(_rev16, ba40, fa90f090), \
10269 X(_revsh, bac0, fa90f0b0), \
10270 X(_ror, 41c0, fa60f000), \
10271 X(_rors, 41c0, fa70f000), \
10272 X(_sbc, 4180, eb600000), \
10273 X(_sbcs, 4180, eb700000), \
10274 X(_stmia, c000, e8800000), \
10275 X(_str, 6000, f8400000), \
10276 X(_strb, 7000, f8000000), \
10277 X(_strh, 8000, f8200000), \
10278 X(_str_sp,9000, f84d0000), \
10279 X(_sub, 1e00, eba00000), \
10280 X(_subs, 1e00, ebb00000), \
10281 X(_subi, 8000, f1a00000), \
10282 X(_subis, 8000, f1b00000), \
10283 X(_sxtb, b240, fa4ff080), \
10284 X(_sxth, b200, fa0ff080), \
10285 X(_tst, 4200, ea100f00), \
10286 X(_uxtb, b2c0, fa5ff080), \
10287 X(_uxth, b280, fa1ff080), \
10288 X(_nop, bf00, f3af8000), \
10289 X(_yield, bf10, f3af8001), \
10290 X(_wfe, bf20, f3af8002), \
10291 X(_wfi, bf30, f3af8003), \
10292 X(_sev, bf40, f3af8004), \
10293 X(_sevl, bf50, f3af8005), \
10294 X(_udf, de00, f7f0a000)
10296 /* To catch errors in encoding functions, the codes are all offset by
10297 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10298 as 16-bit instructions. */
10299 #define X(a,b,c) T_MNEM##a
10300 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10303 #define X(a,b,c) 0x##b
10304 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10305 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10308 #define X(a,b,c) 0x##c
10309 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10310 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10311 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10315 /* Thumb instruction encoders, in alphabetical order. */
10317 /* ADDW or SUBW. */
10320 do_t_add_sub_w (void)
10324 Rd
= inst
.operands
[0].reg
;
10325 Rn
= inst
.operands
[1].reg
;
10327 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10328 is the SP-{plus,minus}-immediate form of the instruction. */
10330 constraint (Rd
== REG_PC
, BAD_PC
);
10332 reject_bad_reg (Rd
);
10334 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10335 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10338 /* Parse an add or subtract instruction. We get here with inst.instruction
10339 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10342 do_t_add_sub (void)
10346 Rd
= inst
.operands
[0].reg
;
10347 Rs
= (inst
.operands
[1].present
10348 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10349 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10352 set_it_insn_type_last ();
10354 if (unified_syntax
)
10357 bfd_boolean narrow
;
10360 flags
= (inst
.instruction
== T_MNEM_adds
10361 || inst
.instruction
== T_MNEM_subs
);
10363 narrow
= !in_it_block ();
10365 narrow
= in_it_block ();
10366 if (!inst
.operands
[2].isreg
)
10370 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10372 add
= (inst
.instruction
== T_MNEM_add
10373 || inst
.instruction
== T_MNEM_adds
);
10375 if (inst
.size_req
!= 4)
10377 /* Attempt to use a narrow opcode, with relaxation if
10379 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10380 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10381 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10382 opcode
= T_MNEM_add_sp
;
10383 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10384 opcode
= T_MNEM_add_pc
;
10385 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10388 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10390 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10394 inst
.instruction
= THUMB_OP16(opcode
);
10395 inst
.instruction
|= (Rd
<< 4) | Rs
;
10396 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10397 if (inst
.size_req
!= 2)
10398 inst
.relax
= opcode
;
10401 constraint (inst
.size_req
== 2, BAD_HIREG
);
10403 if (inst
.size_req
== 4
10404 || (inst
.size_req
!= 2 && !opcode
))
10408 constraint (add
, BAD_PC
);
10409 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10410 _("only SUBS PC, LR, #const allowed"));
10411 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10412 _("expression too complex"));
10413 constraint (inst
.reloc
.exp
.X_add_number
< 0
10414 || inst
.reloc
.exp
.X_add_number
> 0xff,
10415 _("immediate value out of range"));
10416 inst
.instruction
= T2_SUBS_PC_LR
10417 | inst
.reloc
.exp
.X_add_number
;
10418 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10421 else if (Rs
== REG_PC
)
10423 /* Always use addw/subw. */
10424 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10425 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10429 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10430 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10433 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10435 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10437 inst
.instruction
|= Rd
<< 8;
10438 inst
.instruction
|= Rs
<< 16;
10443 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10444 unsigned int shift
= inst
.operands
[2].shift_kind
;
10446 Rn
= inst
.operands
[2].reg
;
10447 /* See if we can do this with a 16-bit instruction. */
10448 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10450 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10455 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10456 || inst
.instruction
== T_MNEM_add
)
10458 : T_OPCODE_SUB_R3
);
10459 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10463 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10465 /* Thumb-1 cores (except v6-M) require at least one high
10466 register in a narrow non flag setting add. */
10467 if (Rd
> 7 || Rn
> 7
10468 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10469 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10476 inst
.instruction
= T_OPCODE_ADD_HI
;
10477 inst
.instruction
|= (Rd
& 8) << 4;
10478 inst
.instruction
|= (Rd
& 7);
10479 inst
.instruction
|= Rn
<< 3;
10485 constraint (Rd
== REG_PC
, BAD_PC
);
10486 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10487 constraint (Rs
== REG_PC
, BAD_PC
);
10488 reject_bad_reg (Rn
);
10490 /* If we get here, it can't be done in 16 bits. */
10491 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10492 _("shift must be constant"));
10493 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10494 inst
.instruction
|= Rd
<< 8;
10495 inst
.instruction
|= Rs
<< 16;
10496 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10497 _("shift value over 3 not allowed in thumb mode"));
10498 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10499 _("only LSL shift allowed in thumb mode"));
10500 encode_thumb32_shifted_operand (2);
10505 constraint (inst
.instruction
== T_MNEM_adds
10506 || inst
.instruction
== T_MNEM_subs
,
10509 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10511 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10512 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10515 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10516 ? 0x0000 : 0x8000);
10517 inst
.instruction
|= (Rd
<< 4) | Rs
;
10518 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10522 Rn
= inst
.operands
[2].reg
;
10523 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10525 /* We now have Rd, Rs, and Rn set to registers. */
10526 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10528 /* Can't do this for SUB. */
10529 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10530 inst
.instruction
= T_OPCODE_ADD_HI
;
10531 inst
.instruction
|= (Rd
& 8) << 4;
10532 inst
.instruction
|= (Rd
& 7);
10534 inst
.instruction
|= Rn
<< 3;
10536 inst
.instruction
|= Rs
<< 3;
10538 constraint (1, _("dest must overlap one source register"));
10542 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10543 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10544 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10554 Rd
= inst
.operands
[0].reg
;
10555 reject_bad_reg (Rd
);
10557 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10559 /* Defer to section relaxation. */
10560 inst
.relax
= inst
.instruction
;
10561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10562 inst
.instruction
|= Rd
<< 4;
10564 else if (unified_syntax
&& inst
.size_req
!= 2)
10566 /* Generate a 32-bit opcode. */
10567 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10568 inst
.instruction
|= Rd
<< 8;
10569 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10570 inst
.reloc
.pc_rel
= 1;
10574 /* Generate a 16-bit opcode. */
10575 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10576 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10577 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10578 inst
.reloc
.pc_rel
= 1;
10580 inst
.instruction
|= Rd
<< 4;
10584 /* Arithmetic instructions for which there is just one 16-bit
10585 instruction encoding, and it allows only two low registers.
10586 For maximal compatibility with ARM syntax, we allow three register
10587 operands even when Thumb-32 instructions are not available, as long
10588 as the first two are identical. For instance, both "sbc r0,r1" and
10589 "sbc r0,r0,r1" are allowed. */
10595 Rd
= inst
.operands
[0].reg
;
10596 Rs
= (inst
.operands
[1].present
10597 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10598 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10599 Rn
= inst
.operands
[2].reg
;
10601 reject_bad_reg (Rd
);
10602 reject_bad_reg (Rs
);
10603 if (inst
.operands
[2].isreg
)
10604 reject_bad_reg (Rn
);
10606 if (unified_syntax
)
10608 if (!inst
.operands
[2].isreg
)
10610 /* For an immediate, we always generate a 32-bit opcode;
10611 section relaxation will shrink it later if possible. */
10612 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10613 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10614 inst
.instruction
|= Rd
<< 8;
10615 inst
.instruction
|= Rs
<< 16;
10616 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10620 bfd_boolean narrow
;
10622 /* See if we can do this with a 16-bit instruction. */
10623 if (THUMB_SETS_FLAGS (inst
.instruction
))
10624 narrow
= !in_it_block ();
10626 narrow
= in_it_block ();
10628 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10630 if (inst
.operands
[2].shifted
)
10632 if (inst
.size_req
== 4)
10638 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10639 inst
.instruction
|= Rd
;
10640 inst
.instruction
|= Rn
<< 3;
10644 /* If we get here, it can't be done in 16 bits. */
10645 constraint (inst
.operands
[2].shifted
10646 && inst
.operands
[2].immisreg
,
10647 _("shift must be constant"));
10648 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10649 inst
.instruction
|= Rd
<< 8;
10650 inst
.instruction
|= Rs
<< 16;
10651 encode_thumb32_shifted_operand (2);
10656 /* On its face this is a lie - the instruction does set the
10657 flags. However, the only supported mnemonic in this mode
10658 says it doesn't. */
10659 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10661 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10662 _("unshifted register required"));
10663 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10664 constraint (Rd
!= Rs
,
10665 _("dest and source1 must be the same register"));
10667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10668 inst
.instruction
|= Rd
;
10669 inst
.instruction
|= Rn
<< 3;
10673 /* Similarly, but for instructions where the arithmetic operation is
10674 commutative, so we can allow either of them to be different from
10675 the destination operand in a 16-bit instruction. For instance, all
10676 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10683 Rd
= inst
.operands
[0].reg
;
10684 Rs
= (inst
.operands
[1].present
10685 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10686 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10687 Rn
= inst
.operands
[2].reg
;
10689 reject_bad_reg (Rd
);
10690 reject_bad_reg (Rs
);
10691 if (inst
.operands
[2].isreg
)
10692 reject_bad_reg (Rn
);
10694 if (unified_syntax
)
10696 if (!inst
.operands
[2].isreg
)
10698 /* For an immediate, we always generate a 32-bit opcode;
10699 section relaxation will shrink it later if possible. */
10700 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10701 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10702 inst
.instruction
|= Rd
<< 8;
10703 inst
.instruction
|= Rs
<< 16;
10704 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10708 bfd_boolean narrow
;
10710 /* See if we can do this with a 16-bit instruction. */
10711 if (THUMB_SETS_FLAGS (inst
.instruction
))
10712 narrow
= !in_it_block ();
10714 narrow
= in_it_block ();
10716 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10718 if (inst
.operands
[2].shifted
)
10720 if (inst
.size_req
== 4)
10727 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10728 inst
.instruction
|= Rd
;
10729 inst
.instruction
|= Rn
<< 3;
10734 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10735 inst
.instruction
|= Rd
;
10736 inst
.instruction
|= Rs
<< 3;
10741 /* If we get here, it can't be done in 16 bits. */
10742 constraint (inst
.operands
[2].shifted
10743 && inst
.operands
[2].immisreg
,
10744 _("shift must be constant"));
10745 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10746 inst
.instruction
|= Rd
<< 8;
10747 inst
.instruction
|= Rs
<< 16;
10748 encode_thumb32_shifted_operand (2);
10753 /* On its face this is a lie - the instruction does set the
10754 flags. However, the only supported mnemonic in this mode
10755 says it doesn't. */
10756 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10758 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10759 _("unshifted register required"));
10760 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10763 inst
.instruction
|= Rd
;
10766 inst
.instruction
|= Rn
<< 3;
10768 inst
.instruction
|= Rs
<< 3;
10770 constraint (1, _("dest must overlap one source register"));
10778 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10779 constraint (msb
> 32, _("bit-field extends past end of register"));
10780 /* The instruction encoding stores the LSB and MSB,
10781 not the LSB and width. */
10782 Rd
= inst
.operands
[0].reg
;
10783 reject_bad_reg (Rd
);
10784 inst
.instruction
|= Rd
<< 8;
10785 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10786 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10787 inst
.instruction
|= msb
- 1;
10796 Rd
= inst
.operands
[0].reg
;
10797 reject_bad_reg (Rd
);
10799 /* #0 in second position is alternative syntax for bfc, which is
10800 the same instruction but with REG_PC in the Rm field. */
10801 if (!inst
.operands
[1].isreg
)
10805 Rn
= inst
.operands
[1].reg
;
10806 reject_bad_reg (Rn
);
10809 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10810 constraint (msb
> 32, _("bit-field extends past end of register"));
10811 /* The instruction encoding stores the LSB and MSB,
10812 not the LSB and width. */
10813 inst
.instruction
|= Rd
<< 8;
10814 inst
.instruction
|= Rn
<< 16;
10815 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10816 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10817 inst
.instruction
|= msb
- 1;
10825 Rd
= inst
.operands
[0].reg
;
10826 Rn
= inst
.operands
[1].reg
;
10828 reject_bad_reg (Rd
);
10829 reject_bad_reg (Rn
);
10831 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10832 _("bit-field extends past end of register"));
10833 inst
.instruction
|= Rd
<< 8;
10834 inst
.instruction
|= Rn
<< 16;
10835 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10836 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10837 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10840 /* ARM V5 Thumb BLX (argument parse)
10841 BLX <target_addr> which is BLX(1)
10842 BLX <Rm> which is BLX(2)
10843 Unfortunately, there are two different opcodes for this mnemonic.
10844 So, the insns[].value is not used, and the code here zaps values
10845 into inst.instruction.
10847 ??? How to take advantage of the additional two bits of displacement
10848 available in Thumb32 mode? Need new relocation? */
10853 set_it_insn_type_last ();
10855 if (inst
.operands
[0].isreg
)
10857 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10858 /* We have a register, so this is BLX(2). */
10859 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10863 /* No register. This must be BLX(1). */
10864 inst
.instruction
= 0xf000e800;
10865 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10877 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10879 if (in_it_block ())
10881 /* Conditional branches inside IT blocks are encoded as unconditional
10883 cond
= COND_ALWAYS
;
10888 if (cond
!= COND_ALWAYS
)
10889 opcode
= T_MNEM_bcond
;
10891 opcode
= inst
.instruction
;
10894 && (inst
.size_req
== 4
10895 || (inst
.size_req
!= 2
10896 && (inst
.operands
[0].hasreloc
10897 || inst
.reloc
.exp
.X_op
== O_constant
))))
10899 inst
.instruction
= THUMB_OP32(opcode
);
10900 if (cond
== COND_ALWAYS
)
10901 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10904 gas_assert (cond
!= 0xF);
10905 inst
.instruction
|= cond
<< 22;
10906 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10911 inst
.instruction
= THUMB_OP16(opcode
);
10912 if (cond
== COND_ALWAYS
)
10913 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10916 inst
.instruction
|= cond
<< 8;
10917 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10919 /* Allow section relaxation. */
10920 if (unified_syntax
&& inst
.size_req
!= 2)
10921 inst
.relax
= opcode
;
10923 inst
.reloc
.type
= reloc
;
10924 inst
.reloc
.pc_rel
= 1;
10927 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10928 between the two is the maximum immediate allowed - which is passed in
10931 do_t_bkpt_hlt1 (int range
)
10933 constraint (inst
.cond
!= COND_ALWAYS
,
10934 _("instruction is always unconditional"));
10935 if (inst
.operands
[0].present
)
10937 constraint (inst
.operands
[0].imm
> range
,
10938 _("immediate value out of range"));
10939 inst
.instruction
|= inst
.operands
[0].imm
;
10942 set_it_insn_type (NEUTRAL_IT_INSN
);
10948 do_t_bkpt_hlt1 (63);
10954 do_t_bkpt_hlt1 (255);
10958 do_t_branch23 (void)
10960 set_it_insn_type_last ();
10961 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10963 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10964 this file. We used to simply ignore the PLT reloc type here --
10965 the branch encoding is now needed to deal with TLSCALL relocs.
10966 So if we see a PLT reloc now, put it back to how it used to be to
10967 keep the preexisting behaviour. */
10968 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10969 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10971 #if defined(OBJ_COFF)
10972 /* If the destination of the branch is a defined symbol which does not have
10973 the THUMB_FUNC attribute, then we must be calling a function which has
10974 the (interfacearm) attribute. We look for the Thumb entry point to that
10975 function and change the branch to refer to that function instead. */
10976 if ( inst
.reloc
.exp
.X_op
== O_symbol
10977 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10978 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10979 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10980 inst
.reloc
.exp
.X_add_symbol
=
10981 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10988 set_it_insn_type_last ();
10989 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10990 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10991 should cause the alignment to be checked once it is known. This is
10992 because BX PC only works if the instruction is word aligned. */
11000 set_it_insn_type_last ();
11001 Rm
= inst
.operands
[0].reg
;
11002 reject_bad_reg (Rm
);
11003 inst
.instruction
|= Rm
<< 16;
11012 Rd
= inst
.operands
[0].reg
;
11013 Rm
= inst
.operands
[1].reg
;
11015 reject_bad_reg (Rd
);
11016 reject_bad_reg (Rm
);
11018 inst
.instruction
|= Rd
<< 8;
11019 inst
.instruction
|= Rm
<< 16;
11020 inst
.instruction
|= Rm
;
11026 set_it_insn_type (OUTSIDE_IT_INSN
);
11027 inst
.instruction
|= inst
.operands
[0].imm
;
11033 set_it_insn_type (OUTSIDE_IT_INSN
);
11035 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11036 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11038 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11039 inst
.instruction
= 0xf3af8000;
11040 inst
.instruction
|= imod
<< 9;
11041 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11042 if (inst
.operands
[1].present
)
11043 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11048 && (inst
.operands
[0].imm
& 4),
11049 _("selected processor does not support 'A' form "
11050 "of this instruction"));
11051 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11052 _("Thumb does not support the 2-argument "
11053 "form of this instruction"));
11054 inst
.instruction
|= inst
.operands
[0].imm
;
11058 /* THUMB CPY instruction (argument parse). */
11063 if (inst
.size_req
== 4)
11065 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11066 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11067 inst
.instruction
|= inst
.operands
[1].reg
;
11071 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11072 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11073 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11080 set_it_insn_type (OUTSIDE_IT_INSN
);
11081 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11082 inst
.instruction
|= inst
.operands
[0].reg
;
11083 inst
.reloc
.pc_rel
= 1;
11084 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11090 inst
.instruction
|= inst
.operands
[0].imm
;
11096 unsigned Rd
, Rn
, Rm
;
11098 Rd
= inst
.operands
[0].reg
;
11099 Rn
= (inst
.operands
[1].present
11100 ? inst
.operands
[1].reg
: Rd
);
11101 Rm
= inst
.operands
[2].reg
;
11103 reject_bad_reg (Rd
);
11104 reject_bad_reg (Rn
);
11105 reject_bad_reg (Rm
);
11107 inst
.instruction
|= Rd
<< 8;
11108 inst
.instruction
|= Rn
<< 16;
11109 inst
.instruction
|= Rm
;
11115 if (unified_syntax
&& inst
.size_req
== 4)
11116 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11118 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11124 unsigned int cond
= inst
.operands
[0].imm
;
11126 set_it_insn_type (IT_INSN
);
11127 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11129 now_it
.warn_deprecated
= FALSE
;
11131 /* If the condition is a negative condition, invert the mask. */
11132 if ((cond
& 0x1) == 0x0)
11134 unsigned int mask
= inst
.instruction
& 0x000f;
11136 if ((mask
& 0x7) == 0)
11138 /* No conversion needed. */
11139 now_it
.block_length
= 1;
11141 else if ((mask
& 0x3) == 0)
11144 now_it
.block_length
= 2;
11146 else if ((mask
& 0x1) == 0)
11149 now_it
.block_length
= 3;
11154 now_it
.block_length
= 4;
11157 inst
.instruction
&= 0xfff0;
11158 inst
.instruction
|= mask
;
11161 inst
.instruction
|= cond
<< 4;
11164 /* Helper function used for both push/pop and ldm/stm. */
11166 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11170 load
= (inst
.instruction
& (1 << 20)) != 0;
11172 if (mask
& (1 << 13))
11173 inst
.error
= _("SP not allowed in register list");
11175 if ((mask
& (1 << base
)) != 0
11177 inst
.error
= _("having the base register in the register list when "
11178 "using write back is UNPREDICTABLE");
11182 if (mask
& (1 << 15))
11184 if (mask
& (1 << 14))
11185 inst
.error
= _("LR and PC should not both be in register list");
11187 set_it_insn_type_last ();
11192 if (mask
& (1 << 15))
11193 inst
.error
= _("PC not allowed in register list");
11196 if ((mask
& (mask
- 1)) == 0)
11198 /* Single register transfers implemented as str/ldr. */
11201 if (inst
.instruction
& (1 << 23))
11202 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11204 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11208 if (inst
.instruction
& (1 << 23))
11209 inst
.instruction
= 0x00800000; /* ia -> [base] */
11211 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11214 inst
.instruction
|= 0xf8400000;
11216 inst
.instruction
|= 0x00100000;
11218 mask
= ffs (mask
) - 1;
11221 else if (writeback
)
11222 inst
.instruction
|= WRITE_BACK
;
11224 inst
.instruction
|= mask
;
11225 inst
.instruction
|= base
<< 16;
11231 /* This really doesn't seem worth it. */
11232 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11233 _("expression too complex"));
11234 constraint (inst
.operands
[1].writeback
,
11235 _("Thumb load/store multiple does not support {reglist}^"));
11237 if (unified_syntax
)
11239 bfd_boolean narrow
;
11243 /* See if we can use a 16-bit instruction. */
11244 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11245 && inst
.size_req
!= 4
11246 && !(inst
.operands
[1].imm
& ~0xff))
11248 mask
= 1 << inst
.operands
[0].reg
;
11250 if (inst
.operands
[0].reg
<= 7)
11252 if (inst
.instruction
== T_MNEM_stmia
11253 ? inst
.operands
[0].writeback
11254 : (inst
.operands
[0].writeback
11255 == !(inst
.operands
[1].imm
& mask
)))
11257 if (inst
.instruction
== T_MNEM_stmia
11258 && (inst
.operands
[1].imm
& mask
)
11259 && (inst
.operands
[1].imm
& (mask
- 1)))
11260 as_warn (_("value stored for r%d is UNKNOWN"),
11261 inst
.operands
[0].reg
);
11263 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11264 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11265 inst
.instruction
|= inst
.operands
[1].imm
;
11268 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11270 /* This means 1 register in reg list one of 3 situations:
11271 1. Instruction is stmia, but without writeback.
11272 2. lmdia without writeback, but with Rn not in
11274 3. ldmia with writeback, but with Rn in reglist.
11275 Case 3 is UNPREDICTABLE behaviour, so we handle
11276 case 1 and 2 which can be converted into a 16-bit
11277 str or ldr. The SP cases are handled below. */
11278 unsigned long opcode
;
11279 /* First, record an error for Case 3. */
11280 if (inst
.operands
[1].imm
& mask
11281 && inst
.operands
[0].writeback
)
11283 _("having the base register in the register list when "
11284 "using write back is UNPREDICTABLE");
11286 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11288 inst
.instruction
= THUMB_OP16 (opcode
);
11289 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11290 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11294 else if (inst
.operands
[0] .reg
== REG_SP
)
11296 if (inst
.operands
[0].writeback
)
11299 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11300 ? T_MNEM_push
: T_MNEM_pop
);
11301 inst
.instruction
|= inst
.operands
[1].imm
;
11304 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11307 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11308 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11309 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11317 if (inst
.instruction
< 0xffff)
11318 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11320 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11321 inst
.operands
[0].writeback
);
11326 constraint (inst
.operands
[0].reg
> 7
11327 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11328 constraint (inst
.instruction
!= T_MNEM_ldmia
11329 && inst
.instruction
!= T_MNEM_stmia
,
11330 _("Thumb-2 instruction only valid in unified syntax"));
11331 if (inst
.instruction
== T_MNEM_stmia
)
11333 if (!inst
.operands
[0].writeback
)
11334 as_warn (_("this instruction will write back the base register"));
11335 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11336 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11337 as_warn (_("value stored for r%d is UNKNOWN"),
11338 inst
.operands
[0].reg
);
11342 if (!inst
.operands
[0].writeback
11343 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11344 as_warn (_("this instruction will write back the base register"));
11345 else if (inst
.operands
[0].writeback
11346 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11347 as_warn (_("this instruction will not write back the base register"));
11350 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11351 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11352 inst
.instruction
|= inst
.operands
[1].imm
;
11359 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11360 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11361 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11362 || inst
.operands
[1].negative
,
11365 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11368 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11369 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11375 if (!inst
.operands
[1].present
)
11377 constraint (inst
.operands
[0].reg
== REG_LR
,
11378 _("r14 not allowed as first register "
11379 "when second register is omitted"));
11380 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11382 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11386 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11387 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11393 unsigned long opcode
;
11396 if (inst
.operands
[0].isreg
11397 && !inst
.operands
[0].preind
11398 && inst
.operands
[0].reg
== REG_PC
)
11399 set_it_insn_type_last ();
11401 opcode
= inst
.instruction
;
11402 if (unified_syntax
)
11404 if (!inst
.operands
[1].isreg
)
11406 if (opcode
<= 0xffff)
11407 inst
.instruction
= THUMB_OP32 (opcode
);
11408 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11411 if (inst
.operands
[1].isreg
11412 && !inst
.operands
[1].writeback
11413 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11414 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11415 && opcode
<= 0xffff
11416 && inst
.size_req
!= 4)
11418 /* Insn may have a 16-bit form. */
11419 Rn
= inst
.operands
[1].reg
;
11420 if (inst
.operands
[1].immisreg
)
11422 inst
.instruction
= THUMB_OP16 (opcode
);
11424 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11426 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11427 reject_bad_reg (inst
.operands
[1].imm
);
11429 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11430 && opcode
!= T_MNEM_ldrsb
)
11431 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11432 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11439 if (inst
.reloc
.pc_rel
)
11440 opcode
= T_MNEM_ldr_pc2
;
11442 opcode
= T_MNEM_ldr_pc
;
11446 if (opcode
== T_MNEM_ldr
)
11447 opcode
= T_MNEM_ldr_sp
;
11449 opcode
= T_MNEM_str_sp
;
11451 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11455 inst
.instruction
= inst
.operands
[0].reg
;
11456 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11458 inst
.instruction
|= THUMB_OP16 (opcode
);
11459 if (inst
.size_req
== 2)
11460 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11462 inst
.relax
= opcode
;
11466 /* Definitely a 32-bit variant. */
11468 /* Warning for Erratum 752419. */
11469 if (opcode
== T_MNEM_ldr
11470 && inst
.operands
[0].reg
== REG_SP
11471 && inst
.operands
[1].writeback
== 1
11472 && !inst
.operands
[1].immisreg
)
11474 if (no_cpu_selected ()
11475 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11476 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11477 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11478 as_warn (_("This instruction may be unpredictable "
11479 "if executed on M-profile cores "
11480 "with interrupts enabled."));
11483 /* Do some validations regarding addressing modes. */
11484 if (inst
.operands
[1].immisreg
)
11485 reject_bad_reg (inst
.operands
[1].imm
);
11487 constraint (inst
.operands
[1].writeback
== 1
11488 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11491 inst
.instruction
= THUMB_OP32 (opcode
);
11492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11493 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11494 check_ldr_r15_aligned ();
11498 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11500 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11502 /* Only [Rn,Rm] is acceptable. */
11503 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11504 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11505 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11506 || inst
.operands
[1].negative
,
11507 _("Thumb does not support this addressing mode"));
11508 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11513 if (!inst
.operands
[1].isreg
)
11514 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11517 constraint (!inst
.operands
[1].preind
11518 || inst
.operands
[1].shifted
11519 || inst
.operands
[1].writeback
,
11520 _("Thumb does not support this addressing mode"));
11521 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11523 constraint (inst
.instruction
& 0x0600,
11524 _("byte or halfword not valid for base register"));
11525 constraint (inst
.operands
[1].reg
== REG_PC
11526 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11527 _("r15 based store not allowed"));
11528 constraint (inst
.operands
[1].immisreg
,
11529 _("invalid base register for register offset"));
11531 if (inst
.operands
[1].reg
== REG_PC
)
11532 inst
.instruction
= T_OPCODE_LDR_PC
;
11533 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11534 inst
.instruction
= T_OPCODE_LDR_SP
;
11536 inst
.instruction
= T_OPCODE_STR_SP
;
11538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11539 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11543 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11544 if (!inst
.operands
[1].immisreg
)
11546 /* Immediate offset. */
11547 inst
.instruction
|= inst
.operands
[0].reg
;
11548 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11549 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11553 /* Register offset. */
11554 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11555 constraint (inst
.operands
[1].negative
,
11556 _("Thumb does not support this addressing mode"));
11559 switch (inst
.instruction
)
11561 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11562 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11563 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11564 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11565 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11566 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11567 case 0x5600 /* ldrsb */:
11568 case 0x5e00 /* ldrsh */: break;
11572 inst
.instruction
|= inst
.operands
[0].reg
;
11573 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11574 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11580 if (!inst
.operands
[1].present
)
11582 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11583 constraint (inst
.operands
[0].reg
== REG_LR
,
11584 _("r14 not allowed here"));
11585 constraint (inst
.operands
[0].reg
== REG_R12
,
11586 _("r12 not allowed here"));
11589 if (inst
.operands
[2].writeback
11590 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11591 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11592 as_warn (_("base register written back, and overlaps "
11593 "one of transfer registers"));
11595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11596 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11597 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11604 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11610 unsigned Rd
, Rn
, Rm
, Ra
;
11612 Rd
= inst
.operands
[0].reg
;
11613 Rn
= inst
.operands
[1].reg
;
11614 Rm
= inst
.operands
[2].reg
;
11615 Ra
= inst
.operands
[3].reg
;
11617 reject_bad_reg (Rd
);
11618 reject_bad_reg (Rn
);
11619 reject_bad_reg (Rm
);
11620 reject_bad_reg (Ra
);
11622 inst
.instruction
|= Rd
<< 8;
11623 inst
.instruction
|= Rn
<< 16;
11624 inst
.instruction
|= Rm
;
11625 inst
.instruction
|= Ra
<< 12;
11631 unsigned RdLo
, RdHi
, Rn
, Rm
;
11633 RdLo
= inst
.operands
[0].reg
;
11634 RdHi
= inst
.operands
[1].reg
;
11635 Rn
= inst
.operands
[2].reg
;
11636 Rm
= inst
.operands
[3].reg
;
11638 reject_bad_reg (RdLo
);
11639 reject_bad_reg (RdHi
);
11640 reject_bad_reg (Rn
);
11641 reject_bad_reg (Rm
);
11643 inst
.instruction
|= RdLo
<< 12;
11644 inst
.instruction
|= RdHi
<< 8;
11645 inst
.instruction
|= Rn
<< 16;
11646 inst
.instruction
|= Rm
;
11650 do_t_mov_cmp (void)
11654 Rn
= inst
.operands
[0].reg
;
11655 Rm
= inst
.operands
[1].reg
;
11658 set_it_insn_type_last ();
11660 if (unified_syntax
)
11662 int r0off
= (inst
.instruction
== T_MNEM_mov
11663 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11664 unsigned long opcode
;
11665 bfd_boolean narrow
;
11666 bfd_boolean low_regs
;
11668 low_regs
= (Rn
<= 7 && Rm
<= 7);
11669 opcode
= inst
.instruction
;
11670 if (in_it_block ())
11671 narrow
= opcode
!= T_MNEM_movs
;
11673 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11674 if (inst
.size_req
== 4
11675 || inst
.operands
[1].shifted
)
11678 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11679 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11680 && !inst
.operands
[1].shifted
11684 inst
.instruction
= T2_SUBS_PC_LR
;
11688 if (opcode
== T_MNEM_cmp
)
11690 constraint (Rn
== REG_PC
, BAD_PC
);
11693 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11695 warn_deprecated_sp (Rm
);
11696 /* R15 was documented as a valid choice for Rm in ARMv6,
11697 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11698 tools reject R15, so we do too. */
11699 constraint (Rm
== REG_PC
, BAD_PC
);
11702 reject_bad_reg (Rm
);
11704 else if (opcode
== T_MNEM_mov
11705 || opcode
== T_MNEM_movs
)
11707 if (inst
.operands
[1].isreg
)
11709 if (opcode
== T_MNEM_movs
)
11711 reject_bad_reg (Rn
);
11712 reject_bad_reg (Rm
);
11716 /* This is mov.n. */
11717 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11718 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11720 as_tsktsk (_("Use of r%u as a source register is "
11721 "deprecated when r%u is the destination "
11722 "register."), Rm
, Rn
);
11727 /* This is mov.w. */
11728 constraint (Rn
== REG_PC
, BAD_PC
);
11729 constraint (Rm
== REG_PC
, BAD_PC
);
11730 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11734 reject_bad_reg (Rn
);
11737 if (!inst
.operands
[1].isreg
)
11739 /* Immediate operand. */
11740 if (!in_it_block () && opcode
== T_MNEM_mov
)
11742 if (low_regs
&& narrow
)
11744 inst
.instruction
= THUMB_OP16 (opcode
);
11745 inst
.instruction
|= Rn
<< 8;
11746 if (inst
.size_req
== 2)
11747 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11749 inst
.relax
= opcode
;
11753 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11754 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11755 inst
.instruction
|= Rn
<< r0off
;
11756 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11759 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11760 && (inst
.instruction
== T_MNEM_mov
11761 || inst
.instruction
== T_MNEM_movs
))
11763 /* Register shifts are encoded as separate shift instructions. */
11764 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11766 if (in_it_block ())
11771 if (inst
.size_req
== 4)
11774 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11780 switch (inst
.operands
[1].shift_kind
)
11783 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11786 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11789 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11792 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11798 inst
.instruction
= opcode
;
11801 inst
.instruction
|= Rn
;
11802 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11807 inst
.instruction
|= CONDS_BIT
;
11809 inst
.instruction
|= Rn
<< 8;
11810 inst
.instruction
|= Rm
<< 16;
11811 inst
.instruction
|= inst
.operands
[1].imm
;
11816 /* Some mov with immediate shift have narrow variants.
11817 Register shifts are handled above. */
11818 if (low_regs
&& inst
.operands
[1].shifted
11819 && (inst
.instruction
== T_MNEM_mov
11820 || inst
.instruction
== T_MNEM_movs
))
11822 if (in_it_block ())
11823 narrow
= (inst
.instruction
== T_MNEM_mov
);
11825 narrow
= (inst
.instruction
== T_MNEM_movs
);
11830 switch (inst
.operands
[1].shift_kind
)
11832 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11833 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11834 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11835 default: narrow
= FALSE
; break;
11841 inst
.instruction
|= Rn
;
11842 inst
.instruction
|= Rm
<< 3;
11843 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11847 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11848 inst
.instruction
|= Rn
<< r0off
;
11849 encode_thumb32_shifted_operand (1);
11853 switch (inst
.instruction
)
11856 /* In v4t or v5t a move of two lowregs produces unpredictable
11857 results. Don't allow this. */
11860 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11861 "MOV Rd, Rs with two low registers is not "
11862 "permitted on this architecture");
11863 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11867 inst
.instruction
= T_OPCODE_MOV_HR
;
11868 inst
.instruction
|= (Rn
& 0x8) << 4;
11869 inst
.instruction
|= (Rn
& 0x7);
11870 inst
.instruction
|= Rm
<< 3;
11874 /* We know we have low registers at this point.
11875 Generate LSLS Rd, Rs, #0. */
11876 inst
.instruction
= T_OPCODE_LSL_I
;
11877 inst
.instruction
|= Rn
;
11878 inst
.instruction
|= Rm
<< 3;
11884 inst
.instruction
= T_OPCODE_CMP_LR
;
11885 inst
.instruction
|= Rn
;
11886 inst
.instruction
|= Rm
<< 3;
11890 inst
.instruction
= T_OPCODE_CMP_HR
;
11891 inst
.instruction
|= (Rn
& 0x8) << 4;
11892 inst
.instruction
|= (Rn
& 0x7);
11893 inst
.instruction
|= Rm
<< 3;
11900 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11902 /* PR 10443: Do not silently ignore shifted operands. */
11903 constraint (inst
.operands
[1].shifted
,
11904 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11906 if (inst
.operands
[1].isreg
)
11908 if (Rn
< 8 && Rm
< 8)
11910 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11911 since a MOV instruction produces unpredictable results. */
11912 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11913 inst
.instruction
= T_OPCODE_ADD_I3
;
11915 inst
.instruction
= T_OPCODE_CMP_LR
;
11917 inst
.instruction
|= Rn
;
11918 inst
.instruction
|= Rm
<< 3;
11922 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11923 inst
.instruction
= T_OPCODE_MOV_HR
;
11925 inst
.instruction
= T_OPCODE_CMP_HR
;
11931 constraint (Rn
> 7,
11932 _("only lo regs allowed with immediate"));
11933 inst
.instruction
|= Rn
<< 8;
11934 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11945 top
= (inst
.instruction
& 0x00800000) != 0;
11946 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11948 constraint (top
, _(":lower16: not allowed this instruction"));
11949 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11951 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11953 constraint (!top
, _(":upper16: not allowed this instruction"));
11954 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11957 Rd
= inst
.operands
[0].reg
;
11958 reject_bad_reg (Rd
);
11960 inst
.instruction
|= Rd
<< 8;
11961 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11963 imm
= inst
.reloc
.exp
.X_add_number
;
11964 inst
.instruction
|= (imm
& 0xf000) << 4;
11965 inst
.instruction
|= (imm
& 0x0800) << 15;
11966 inst
.instruction
|= (imm
& 0x0700) << 4;
11967 inst
.instruction
|= (imm
& 0x00ff);
11972 do_t_mvn_tst (void)
11976 Rn
= inst
.operands
[0].reg
;
11977 Rm
= inst
.operands
[1].reg
;
11979 if (inst
.instruction
== T_MNEM_cmp
11980 || inst
.instruction
== T_MNEM_cmn
)
11981 constraint (Rn
== REG_PC
, BAD_PC
);
11983 reject_bad_reg (Rn
);
11984 reject_bad_reg (Rm
);
11986 if (unified_syntax
)
11988 int r0off
= (inst
.instruction
== T_MNEM_mvn
11989 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11990 bfd_boolean narrow
;
11992 if (inst
.size_req
== 4
11993 || inst
.instruction
> 0xffff
11994 || inst
.operands
[1].shifted
11995 || Rn
> 7 || Rm
> 7)
11997 else if (inst
.instruction
== T_MNEM_cmn
11998 || inst
.instruction
== T_MNEM_tst
)
12000 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12001 narrow
= !in_it_block ();
12003 narrow
= in_it_block ();
12005 if (!inst
.operands
[1].isreg
)
12007 /* For an immediate, we always generate a 32-bit opcode;
12008 section relaxation will shrink it later if possible. */
12009 if (inst
.instruction
< 0xffff)
12010 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12011 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12012 inst
.instruction
|= Rn
<< r0off
;
12013 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12017 /* See if we can do this with a 16-bit instruction. */
12020 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12021 inst
.instruction
|= Rn
;
12022 inst
.instruction
|= Rm
<< 3;
12026 constraint (inst
.operands
[1].shifted
12027 && inst
.operands
[1].immisreg
,
12028 _("shift must be constant"));
12029 if (inst
.instruction
< 0xffff)
12030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12031 inst
.instruction
|= Rn
<< r0off
;
12032 encode_thumb32_shifted_operand (1);
12038 constraint (inst
.instruction
> 0xffff
12039 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12040 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12041 _("unshifted register required"));
12042 constraint (Rn
> 7 || Rm
> 7,
12045 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12046 inst
.instruction
|= Rn
;
12047 inst
.instruction
|= Rm
<< 3;
12056 if (do_vfp_nsyn_mrs () == SUCCESS
)
12059 Rd
= inst
.operands
[0].reg
;
12060 reject_bad_reg (Rd
);
12061 inst
.instruction
|= Rd
<< 8;
12063 if (inst
.operands
[1].isreg
)
12065 unsigned br
= inst
.operands
[1].reg
;
12066 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12067 as_bad (_("bad register for mrs"));
12069 inst
.instruction
|= br
& (0xf << 16);
12070 inst
.instruction
|= (br
& 0x300) >> 4;
12071 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12075 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12077 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12079 /* PR gas/12698: The constraint is only applied for m_profile.
12080 If the user has specified -march=all, we want to ignore it as
12081 we are building for any CPU type, including non-m variants. */
12082 bfd_boolean m_profile
=
12083 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12084 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12085 "not support requested special purpose register"));
12088 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12090 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12091 _("'APSR', 'CPSR' or 'SPSR' expected"));
12093 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12094 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12095 inst
.instruction
|= 0xf0000;
12105 if (do_vfp_nsyn_msr () == SUCCESS
)
12108 constraint (!inst
.operands
[1].isreg
,
12109 _("Thumb encoding does not support an immediate here"));
12111 if (inst
.operands
[0].isreg
)
12112 flags
= (int)(inst
.operands
[0].reg
);
12114 flags
= inst
.operands
[0].imm
;
12116 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12118 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12120 /* PR gas/12698: The constraint is only applied for m_profile.
12121 If the user has specified -march=all, we want to ignore it as
12122 we are building for any CPU type, including non-m variants. */
12123 bfd_boolean m_profile
=
12124 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12125 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12126 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12127 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12128 && bits
!= PSR_f
)) && m_profile
,
12129 _("selected processor does not support requested special "
12130 "purpose register"));
12133 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12134 "requested special purpose register"));
12136 Rn
= inst
.operands
[1].reg
;
12137 reject_bad_reg (Rn
);
12139 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12140 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12141 inst
.instruction
|= (flags
& 0x300) >> 4;
12142 inst
.instruction
|= (flags
& 0xff);
12143 inst
.instruction
|= Rn
<< 16;
12149 bfd_boolean narrow
;
12150 unsigned Rd
, Rn
, Rm
;
12152 if (!inst
.operands
[2].present
)
12153 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12155 Rd
= inst
.operands
[0].reg
;
12156 Rn
= inst
.operands
[1].reg
;
12157 Rm
= inst
.operands
[2].reg
;
12159 if (unified_syntax
)
12161 if (inst
.size_req
== 4
12167 else if (inst
.instruction
== T_MNEM_muls
)
12168 narrow
= !in_it_block ();
12170 narrow
= in_it_block ();
12174 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12175 constraint (Rn
> 7 || Rm
> 7,
12182 /* 16-bit MULS/Conditional MUL. */
12183 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12184 inst
.instruction
|= Rd
;
12187 inst
.instruction
|= Rm
<< 3;
12189 inst
.instruction
|= Rn
<< 3;
12191 constraint (1, _("dest must overlap one source register"));
12195 constraint (inst
.instruction
!= T_MNEM_mul
,
12196 _("Thumb-2 MUL must not set flags"));
12198 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12199 inst
.instruction
|= Rd
<< 8;
12200 inst
.instruction
|= Rn
<< 16;
12201 inst
.instruction
|= Rm
<< 0;
12203 reject_bad_reg (Rd
);
12204 reject_bad_reg (Rn
);
12205 reject_bad_reg (Rm
);
12212 unsigned RdLo
, RdHi
, Rn
, Rm
;
12214 RdLo
= inst
.operands
[0].reg
;
12215 RdHi
= inst
.operands
[1].reg
;
12216 Rn
= inst
.operands
[2].reg
;
12217 Rm
= inst
.operands
[3].reg
;
12219 reject_bad_reg (RdLo
);
12220 reject_bad_reg (RdHi
);
12221 reject_bad_reg (Rn
);
12222 reject_bad_reg (Rm
);
12224 inst
.instruction
|= RdLo
<< 12;
12225 inst
.instruction
|= RdHi
<< 8;
12226 inst
.instruction
|= Rn
<< 16;
12227 inst
.instruction
|= Rm
;
12230 as_tsktsk (_("rdhi and rdlo must be different"));
12236 set_it_insn_type (NEUTRAL_IT_INSN
);
12238 if (unified_syntax
)
12240 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12243 inst
.instruction
|= inst
.operands
[0].imm
;
12247 /* PR9722: Check for Thumb2 availability before
12248 generating a thumb2 nop instruction. */
12249 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12251 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12252 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12255 inst
.instruction
= 0x46c0;
12260 constraint (inst
.operands
[0].present
,
12261 _("Thumb does not support NOP with hints"));
12262 inst
.instruction
= 0x46c0;
12269 if (unified_syntax
)
12271 bfd_boolean narrow
;
12273 if (THUMB_SETS_FLAGS (inst
.instruction
))
12274 narrow
= !in_it_block ();
12276 narrow
= in_it_block ();
12277 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12279 if (inst
.size_req
== 4)
12284 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12286 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12290 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12291 inst
.instruction
|= inst
.operands
[0].reg
;
12292 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12297 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12299 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12301 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12302 inst
.instruction
|= inst
.operands
[0].reg
;
12303 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12312 Rd
= inst
.operands
[0].reg
;
12313 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12315 reject_bad_reg (Rd
);
12316 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12317 reject_bad_reg (Rn
);
12319 inst
.instruction
|= Rd
<< 8;
12320 inst
.instruction
|= Rn
<< 16;
12322 if (!inst
.operands
[2].isreg
)
12324 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12325 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12331 Rm
= inst
.operands
[2].reg
;
12332 reject_bad_reg (Rm
);
12334 constraint (inst
.operands
[2].shifted
12335 && inst
.operands
[2].immisreg
,
12336 _("shift must be constant"));
12337 encode_thumb32_shifted_operand (2);
12344 unsigned Rd
, Rn
, Rm
;
12346 Rd
= inst
.operands
[0].reg
;
12347 Rn
= inst
.operands
[1].reg
;
12348 Rm
= inst
.operands
[2].reg
;
12350 reject_bad_reg (Rd
);
12351 reject_bad_reg (Rn
);
12352 reject_bad_reg (Rm
);
12354 inst
.instruction
|= Rd
<< 8;
12355 inst
.instruction
|= Rn
<< 16;
12356 inst
.instruction
|= Rm
;
12357 if (inst
.operands
[3].present
)
12359 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12360 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12361 _("expression too complex"));
12362 inst
.instruction
|= (val
& 0x1c) << 10;
12363 inst
.instruction
|= (val
& 0x03) << 6;
12370 if (!inst
.operands
[3].present
)
12374 inst
.instruction
&= ~0x00000020;
12376 /* PR 10168. Swap the Rm and Rn registers. */
12377 Rtmp
= inst
.operands
[1].reg
;
12378 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12379 inst
.operands
[2].reg
= Rtmp
;
12387 if (inst
.operands
[0].immisreg
)
12388 reject_bad_reg (inst
.operands
[0].imm
);
12390 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12394 do_t_push_pop (void)
12398 constraint (inst
.operands
[0].writeback
,
12399 _("push/pop do not support {reglist}^"));
12400 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12401 _("expression too complex"));
12403 mask
= inst
.operands
[0].imm
;
12404 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12405 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12406 else if (inst
.size_req
!= 4
12407 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12408 ? REG_LR
: REG_PC
)))
12410 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12411 inst
.instruction
|= THUMB_PP_PC_LR
;
12412 inst
.instruction
|= mask
& 0xff;
12414 else if (unified_syntax
)
12416 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12417 encode_thumb2_ldmstm (13, mask
, TRUE
);
12421 inst
.error
= _("invalid register list to push/pop instruction");
12431 Rd
= inst
.operands
[0].reg
;
12432 Rm
= inst
.operands
[1].reg
;
12434 reject_bad_reg (Rd
);
12435 reject_bad_reg (Rm
);
12437 inst
.instruction
|= Rd
<< 8;
12438 inst
.instruction
|= Rm
<< 16;
12439 inst
.instruction
|= Rm
;
12447 Rd
= inst
.operands
[0].reg
;
12448 Rm
= inst
.operands
[1].reg
;
12450 reject_bad_reg (Rd
);
12451 reject_bad_reg (Rm
);
12453 if (Rd
<= 7 && Rm
<= 7
12454 && inst
.size_req
!= 4)
12456 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12457 inst
.instruction
|= Rd
;
12458 inst
.instruction
|= Rm
<< 3;
12460 else if (unified_syntax
)
12462 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12463 inst
.instruction
|= Rd
<< 8;
12464 inst
.instruction
|= Rm
<< 16;
12465 inst
.instruction
|= Rm
;
12468 inst
.error
= BAD_HIREG
;
12476 Rd
= inst
.operands
[0].reg
;
12477 Rm
= inst
.operands
[1].reg
;
12479 reject_bad_reg (Rd
);
12480 reject_bad_reg (Rm
);
12482 inst
.instruction
|= Rd
<< 8;
12483 inst
.instruction
|= Rm
;
12491 Rd
= inst
.operands
[0].reg
;
12492 Rs
= (inst
.operands
[1].present
12493 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12494 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12496 reject_bad_reg (Rd
);
12497 reject_bad_reg (Rs
);
12498 if (inst
.operands
[2].isreg
)
12499 reject_bad_reg (inst
.operands
[2].reg
);
12501 inst
.instruction
|= Rd
<< 8;
12502 inst
.instruction
|= Rs
<< 16;
12503 if (!inst
.operands
[2].isreg
)
12505 bfd_boolean narrow
;
12507 if ((inst
.instruction
& 0x00100000) != 0)
12508 narrow
= !in_it_block ();
12510 narrow
= in_it_block ();
12512 if (Rd
> 7 || Rs
> 7)
12515 if (inst
.size_req
== 4 || !unified_syntax
)
12518 if (inst
.reloc
.exp
.X_op
!= O_constant
12519 || inst
.reloc
.exp
.X_add_number
!= 0)
12522 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12523 relaxation, but it doesn't seem worth the hassle. */
12526 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12527 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12528 inst
.instruction
|= Rs
<< 3;
12529 inst
.instruction
|= Rd
;
12533 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12534 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12538 encode_thumb32_shifted_operand (2);
12544 if (warn_on_deprecated
12545 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12546 as_tsktsk (_("setend use is deprecated for ARMv8"));
12548 set_it_insn_type (OUTSIDE_IT_INSN
);
12549 if (inst
.operands
[0].imm
)
12550 inst
.instruction
|= 0x8;
12556 if (!inst
.operands
[1].present
)
12557 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12559 if (unified_syntax
)
12561 bfd_boolean narrow
;
12564 switch (inst
.instruction
)
12567 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12569 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12571 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12573 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12577 if (THUMB_SETS_FLAGS (inst
.instruction
))
12578 narrow
= !in_it_block ();
12580 narrow
= in_it_block ();
12581 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12583 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12585 if (inst
.operands
[2].isreg
12586 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12587 || inst
.operands
[2].reg
> 7))
12589 if (inst
.size_req
== 4)
12592 reject_bad_reg (inst
.operands
[0].reg
);
12593 reject_bad_reg (inst
.operands
[1].reg
);
12597 if (inst
.operands
[2].isreg
)
12599 reject_bad_reg (inst
.operands
[2].reg
);
12600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12601 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12603 inst
.instruction
|= inst
.operands
[2].reg
;
12605 /* PR 12854: Error on extraneous shifts. */
12606 constraint (inst
.operands
[2].shifted
,
12607 _("extraneous shift as part of operand to shift insn"));
12611 inst
.operands
[1].shifted
= 1;
12612 inst
.operands
[1].shift_kind
= shift_kind
;
12613 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12614 ? T_MNEM_movs
: T_MNEM_mov
);
12615 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12616 encode_thumb32_shifted_operand (1);
12617 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12618 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12623 if (inst
.operands
[2].isreg
)
12625 switch (shift_kind
)
12627 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12628 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12629 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12630 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12634 inst
.instruction
|= inst
.operands
[0].reg
;
12635 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12637 /* PR 12854: Error on extraneous shifts. */
12638 constraint (inst
.operands
[2].shifted
,
12639 _("extraneous shift as part of operand to shift insn"));
12643 switch (shift_kind
)
12645 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12646 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12647 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12650 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12651 inst
.instruction
|= inst
.operands
[0].reg
;
12652 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12658 constraint (inst
.operands
[0].reg
> 7
12659 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12660 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12662 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12664 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12665 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12666 _("source1 and dest must be same register"));
12668 switch (inst
.instruction
)
12670 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12671 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12672 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12673 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12677 inst
.instruction
|= inst
.operands
[0].reg
;
12678 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12680 /* PR 12854: Error on extraneous shifts. */
12681 constraint (inst
.operands
[2].shifted
,
12682 _("extraneous shift as part of operand to shift insn"));
12686 switch (inst
.instruction
)
12688 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12689 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12690 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12691 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12694 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12695 inst
.instruction
|= inst
.operands
[0].reg
;
12696 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12704 unsigned Rd
, Rn
, Rm
;
12706 Rd
= inst
.operands
[0].reg
;
12707 Rn
= inst
.operands
[1].reg
;
12708 Rm
= inst
.operands
[2].reg
;
12710 reject_bad_reg (Rd
);
12711 reject_bad_reg (Rn
);
12712 reject_bad_reg (Rm
);
12714 inst
.instruction
|= Rd
<< 8;
12715 inst
.instruction
|= Rn
<< 16;
12716 inst
.instruction
|= Rm
;
12722 unsigned Rd
, Rn
, Rm
;
12724 Rd
= inst
.operands
[0].reg
;
12725 Rm
= inst
.operands
[1].reg
;
12726 Rn
= inst
.operands
[2].reg
;
12728 reject_bad_reg (Rd
);
12729 reject_bad_reg (Rn
);
12730 reject_bad_reg (Rm
);
12732 inst
.instruction
|= Rd
<< 8;
12733 inst
.instruction
|= Rn
<< 16;
12734 inst
.instruction
|= Rm
;
12740 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12741 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12742 _("SMC is not permitted on this architecture"));
12743 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12744 _("expression too complex"));
12745 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12746 inst
.instruction
|= (value
& 0xf000) >> 12;
12747 inst
.instruction
|= (value
& 0x0ff0);
12748 inst
.instruction
|= (value
& 0x000f) << 16;
12749 /* PR gas/15623: SMC instructions must be last in an IT block. */
12750 set_it_insn_type_last ();
12756 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12758 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12759 inst
.instruction
|= (value
& 0x0fff);
12760 inst
.instruction
|= (value
& 0xf000) << 4;
12764 do_t_ssat_usat (int bias
)
12768 Rd
= inst
.operands
[0].reg
;
12769 Rn
= inst
.operands
[2].reg
;
12771 reject_bad_reg (Rd
);
12772 reject_bad_reg (Rn
);
12774 inst
.instruction
|= Rd
<< 8;
12775 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12776 inst
.instruction
|= Rn
<< 16;
12778 if (inst
.operands
[3].present
)
12780 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12782 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12784 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12785 _("expression too complex"));
12787 if (shift_amount
!= 0)
12789 constraint (shift_amount
> 31,
12790 _("shift expression is too large"));
12792 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12793 inst
.instruction
|= 0x00200000; /* sh bit. */
12795 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12796 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12804 do_t_ssat_usat (1);
12812 Rd
= inst
.operands
[0].reg
;
12813 Rn
= inst
.operands
[2].reg
;
12815 reject_bad_reg (Rd
);
12816 reject_bad_reg (Rn
);
12818 inst
.instruction
|= Rd
<< 8;
12819 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12820 inst
.instruction
|= Rn
<< 16;
12826 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12827 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12828 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12829 || inst
.operands
[2].negative
,
12832 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12834 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12835 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12836 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12837 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12843 if (!inst
.operands
[2].present
)
12844 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12846 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12847 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12848 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12851 inst
.instruction
|= inst
.operands
[0].reg
;
12852 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12853 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12854 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12860 unsigned Rd
, Rn
, Rm
;
12862 Rd
= inst
.operands
[0].reg
;
12863 Rn
= inst
.operands
[1].reg
;
12864 Rm
= inst
.operands
[2].reg
;
12866 reject_bad_reg (Rd
);
12867 reject_bad_reg (Rn
);
12868 reject_bad_reg (Rm
);
12870 inst
.instruction
|= Rd
<< 8;
12871 inst
.instruction
|= Rn
<< 16;
12872 inst
.instruction
|= Rm
;
12873 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12881 Rd
= inst
.operands
[0].reg
;
12882 Rm
= inst
.operands
[1].reg
;
12884 reject_bad_reg (Rd
);
12885 reject_bad_reg (Rm
);
12887 if (inst
.instruction
<= 0xffff
12888 && inst
.size_req
!= 4
12889 && Rd
<= 7 && Rm
<= 7
12890 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12892 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12893 inst
.instruction
|= Rd
;
12894 inst
.instruction
|= Rm
<< 3;
12896 else if (unified_syntax
)
12898 if (inst
.instruction
<= 0xffff)
12899 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12900 inst
.instruction
|= Rd
<< 8;
12901 inst
.instruction
|= Rm
;
12902 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12906 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12907 _("Thumb encoding does not support rotation"));
12908 constraint (1, BAD_HIREG
);
12915 /* We have to do the following check manually as ARM_EXT_OS only applies
12917 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12919 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12920 /* This only applies to the v6m howver, not later architectures. */
12921 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12922 as_bad (_("SVC is not permitted on this architecture"));
12923 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12926 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12935 half
= (inst
.instruction
& 0x10) != 0;
12936 set_it_insn_type_last ();
12937 constraint (inst
.operands
[0].immisreg
,
12938 _("instruction requires register index"));
12940 Rn
= inst
.operands
[0].reg
;
12941 Rm
= inst
.operands
[0].imm
;
12943 constraint (Rn
== REG_SP
, BAD_SP
);
12944 reject_bad_reg (Rm
);
12946 constraint (!half
&& inst
.operands
[0].shifted
,
12947 _("instruction does not allow shifted index"));
12948 inst
.instruction
|= (Rn
<< 16) | Rm
;
12954 if (!inst
.operands
[0].present
)
12955 inst
.operands
[0].imm
= 0;
12957 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12959 constraint (inst
.size_req
== 2,
12960 _("immediate value out of range"));
12961 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12962 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12963 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12967 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12968 inst
.instruction
|= inst
.operands
[0].imm
;
12971 set_it_insn_type (NEUTRAL_IT_INSN
);
12978 do_t_ssat_usat (0);
12986 Rd
= inst
.operands
[0].reg
;
12987 Rn
= inst
.operands
[2].reg
;
12989 reject_bad_reg (Rd
);
12990 reject_bad_reg (Rn
);
12992 inst
.instruction
|= Rd
<< 8;
12993 inst
.instruction
|= inst
.operands
[1].imm
;
12994 inst
.instruction
|= Rn
<< 16;
12997 /* Neon instruction encoder helpers. */
12999 /* Encodings for the different types for various Neon opcodes. */
13001 /* An "invalid" code for the following tables. */
13004 struct neon_tab_entry
13007 unsigned float_or_poly
;
13008 unsigned scalar_or_imm
;
13011 /* Map overloaded Neon opcodes to their respective encodings. */
13012 #define NEON_ENC_TAB \
13013 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13014 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13015 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13016 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13017 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13018 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13019 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13020 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13021 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13022 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13023 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13024 /* Register variants of the following two instructions are encoded as
13025 vcge / vcgt with the operands reversed. */ \
13026 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13027 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13028 X(vfma, N_INV, 0x0000c10, N_INV), \
13029 X(vfms, N_INV, 0x0200c10, N_INV), \
13030 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13031 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13032 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13033 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13034 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13035 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13036 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13037 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13038 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13039 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13040 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13041 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13042 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13043 X(vshl, 0x0000400, N_INV, 0x0800510), \
13044 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13045 X(vand, 0x0000110, N_INV, 0x0800030), \
13046 X(vbic, 0x0100110, N_INV, 0x0800030), \
13047 X(veor, 0x1000110, N_INV, N_INV), \
13048 X(vorn, 0x0300110, N_INV, 0x0800010), \
13049 X(vorr, 0x0200110, N_INV, 0x0800010), \
13050 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13051 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13052 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13053 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13054 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13055 X(vst1, 0x0000000, 0x0800000, N_INV), \
13056 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13057 X(vst2, 0x0000100, 0x0800100, N_INV), \
13058 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13059 X(vst3, 0x0000200, 0x0800200, N_INV), \
13060 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13061 X(vst4, 0x0000300, 0x0800300, N_INV), \
13062 X(vmovn, 0x1b20200, N_INV, N_INV), \
13063 X(vtrn, 0x1b20080, N_INV, N_INV), \
13064 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13065 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13066 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13067 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13068 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13069 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13070 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13071 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13072 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13073 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13074 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13075 X(vseleq, 0xe000a00, N_INV, N_INV), \
13076 X(vselvs, 0xe100a00, N_INV, N_INV), \
13077 X(vselge, 0xe200a00, N_INV, N_INV), \
13078 X(vselgt, 0xe300a00, N_INV, N_INV), \
13079 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13080 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13081 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13082 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13083 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13084 X(aes, 0x3b00300, N_INV, N_INV), \
13085 X(sha3op, 0x2000c00, N_INV, N_INV), \
13086 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13087 X(sha2op, 0x3ba0380, N_INV, N_INV)
13091 #define X(OPC,I,F,S) N_MNEM_##OPC
13096 static const struct neon_tab_entry neon_enc_tab
[] =
13098 #define X(OPC,I,F,S) { (I), (F), (S) }
13103 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13104 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13105 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13106 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13107 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13108 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13109 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13110 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13111 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13112 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13113 #define NEON_ENC_SINGLE_(X) \
13114 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13115 #define NEON_ENC_DOUBLE_(X) \
13116 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13117 #define NEON_ENC_FPV8_(X) \
13118 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13120 #define NEON_ENCODE(type, inst) \
13123 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13124 inst.is_neon = 1; \
13128 #define check_neon_suffixes \
13131 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13133 as_bad (_("invalid neon suffix for non neon instruction")); \
13139 /* Define shapes for instruction operands. The following mnemonic characters
13140 are used in this table:
13142 F - VFP S<n> register
13143 D - Neon D<n> register
13144 Q - Neon Q<n> register
13148 L - D<n> register list
13150 This table is used to generate various data:
13151 - enumerations of the form NS_DDR to be used as arguments to
13153 - a table classifying shapes into single, double, quad, mixed.
13154 - a table used to drive neon_select_shape. */
13156 #define NEON_SHAPE_DEF \
13157 X(3, (D, D, D), DOUBLE), \
13158 X(3, (Q, Q, Q), QUAD), \
13159 X(3, (D, D, I), DOUBLE), \
13160 X(3, (Q, Q, I), QUAD), \
13161 X(3, (D, D, S), DOUBLE), \
13162 X(3, (Q, Q, S), QUAD), \
13163 X(2, (D, D), DOUBLE), \
13164 X(2, (Q, Q), QUAD), \
13165 X(2, (D, S), DOUBLE), \
13166 X(2, (Q, S), QUAD), \
13167 X(2, (D, R), DOUBLE), \
13168 X(2, (Q, R), QUAD), \
13169 X(2, (D, I), DOUBLE), \
13170 X(2, (Q, I), QUAD), \
13171 X(3, (D, L, D), DOUBLE), \
13172 X(2, (D, Q), MIXED), \
13173 X(2, (Q, D), MIXED), \
13174 X(3, (D, Q, I), MIXED), \
13175 X(3, (Q, D, I), MIXED), \
13176 X(3, (Q, D, D), MIXED), \
13177 X(3, (D, Q, Q), MIXED), \
13178 X(3, (Q, Q, D), MIXED), \
13179 X(3, (Q, D, S), MIXED), \
13180 X(3, (D, Q, S), MIXED), \
13181 X(4, (D, D, D, I), DOUBLE), \
13182 X(4, (Q, Q, Q, I), QUAD), \
13183 X(2, (F, F), SINGLE), \
13184 X(3, (F, F, F), SINGLE), \
13185 X(2, (F, I), SINGLE), \
13186 X(2, (F, D), MIXED), \
13187 X(2, (D, F), MIXED), \
13188 X(3, (F, F, I), MIXED), \
13189 X(4, (R, R, F, F), SINGLE), \
13190 X(4, (F, F, R, R), SINGLE), \
13191 X(3, (D, R, R), DOUBLE), \
13192 X(3, (R, R, D), DOUBLE), \
13193 X(2, (S, R), SINGLE), \
13194 X(2, (R, S), SINGLE), \
13195 X(2, (F, R), SINGLE), \
13196 X(2, (R, F), SINGLE)
13198 #define S2(A,B) NS_##A##B
13199 #define S3(A,B,C) NS_##A##B##C
13200 #define S4(A,B,C,D) NS_##A##B##C##D
13202 #define X(N, L, C) S##N L
13215 enum neon_shape_class
13223 #define X(N, L, C) SC_##C
13225 static enum neon_shape_class neon_shape_class
[] =
13243 /* Register widths of above. */
13244 static unsigned neon_shape_el_size
[] =
13255 struct neon_shape_info
13258 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13261 #define S2(A,B) { SE_##A, SE_##B }
13262 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13263 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13265 #define X(N, L, C) { N, S##N L }
13267 static struct neon_shape_info neon_shape_tab
[] =
13277 /* Bit masks used in type checking given instructions.
13278 'N_EQK' means the type must be the same as (or based on in some way) the key
13279 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13280 set, various other bits can be set as well in order to modify the meaning of
13281 the type constraint. */
13283 enum neon_type_mask
13307 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13308 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13309 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13310 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13311 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13312 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13313 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13314 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13315 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13316 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13317 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13319 N_MAX_NONSPECIAL
= N_P64
13322 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13324 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13325 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13326 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13327 #define N_SUF_32 (N_SU_32 | N_F32)
13328 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13329 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13331 /* Pass this as the first type argument to neon_check_type to ignore types
13333 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13335 /* Select a "shape" for the current instruction (describing register types or
13336 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13337 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13338 function of operand parsing, so this function doesn't need to be called.
13339 Shapes should be listed in order of decreasing length. */
13341 static enum neon_shape
13342 neon_select_shape (enum neon_shape shape
, ...)
13345 enum neon_shape first_shape
= shape
;
13347 /* Fix missing optional operands. FIXME: we don't know at this point how
13348 many arguments we should have, so this makes the assumption that we have
13349 > 1. This is true of all current Neon opcodes, I think, but may not be
13350 true in the future. */
13351 if (!inst
.operands
[1].present
)
13352 inst
.operands
[1] = inst
.operands
[0];
13354 va_start (ap
, shape
);
13356 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13361 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13363 if (!inst
.operands
[j
].present
)
13369 switch (neon_shape_tab
[shape
].el
[j
])
13372 if (!(inst
.operands
[j
].isreg
13373 && inst
.operands
[j
].isvec
13374 && inst
.operands
[j
].issingle
13375 && !inst
.operands
[j
].isquad
))
13380 if (!(inst
.operands
[j
].isreg
13381 && inst
.operands
[j
].isvec
13382 && !inst
.operands
[j
].isquad
13383 && !inst
.operands
[j
].issingle
))
13388 if (!(inst
.operands
[j
].isreg
13389 && !inst
.operands
[j
].isvec
))
13394 if (!(inst
.operands
[j
].isreg
13395 && inst
.operands
[j
].isvec
13396 && inst
.operands
[j
].isquad
13397 && !inst
.operands
[j
].issingle
))
13402 if (!(!inst
.operands
[j
].isreg
13403 && !inst
.operands
[j
].isscalar
))
13408 if (!(!inst
.operands
[j
].isreg
13409 && inst
.operands
[j
].isscalar
))
13419 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13420 /* We've matched all the entries in the shape table, and we don't
13421 have any left over operands which have not been matched. */
13427 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13428 first_error (_("invalid instruction shape"));
13433 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13434 means the Q bit should be set). */
13437 neon_quad (enum neon_shape shape
)
13439 return neon_shape_class
[shape
] == SC_QUAD
;
13443 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13446 /* Allow modification to be made to types which are constrained to be
13447 based on the key element, based on bits set alongside N_EQK. */
13448 if ((typebits
& N_EQK
) != 0)
13450 if ((typebits
& N_HLF
) != 0)
13452 else if ((typebits
& N_DBL
) != 0)
13454 if ((typebits
& N_SGN
) != 0)
13455 *g_type
= NT_signed
;
13456 else if ((typebits
& N_UNS
) != 0)
13457 *g_type
= NT_unsigned
;
13458 else if ((typebits
& N_INT
) != 0)
13459 *g_type
= NT_integer
;
13460 else if ((typebits
& N_FLT
) != 0)
13461 *g_type
= NT_float
;
13462 else if ((typebits
& N_SIZ
) != 0)
13463 *g_type
= NT_untyped
;
13467 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13468 operand type, i.e. the single type specified in a Neon instruction when it
13469 is the only one given. */
13471 static struct neon_type_el
13472 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13474 struct neon_type_el dest
= *key
;
13476 gas_assert ((thisarg
& N_EQK
) != 0);
13478 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13483 /* Convert Neon type and size into compact bitmask representation. */
13485 static enum neon_type_mask
13486 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13493 case 8: return N_8
;
13494 case 16: return N_16
;
13495 case 32: return N_32
;
13496 case 64: return N_64
;
13504 case 8: return N_I8
;
13505 case 16: return N_I16
;
13506 case 32: return N_I32
;
13507 case 64: return N_I64
;
13515 case 16: return N_F16
;
13516 case 32: return N_F32
;
13517 case 64: return N_F64
;
13525 case 8: return N_P8
;
13526 case 16: return N_P16
;
13527 case 64: return N_P64
;
13535 case 8: return N_S8
;
13536 case 16: return N_S16
;
13537 case 32: return N_S32
;
13538 case 64: return N_S64
;
13546 case 8: return N_U8
;
13547 case 16: return N_U16
;
13548 case 32: return N_U32
;
13549 case 64: return N_U64
;
13560 /* Convert compact Neon bitmask type representation to a type and size. Only
13561 handles the case where a single bit is set in the mask. */
13564 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13565 enum neon_type_mask mask
)
13567 if ((mask
& N_EQK
) != 0)
13570 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13572 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13574 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13576 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13581 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13583 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13584 *type
= NT_unsigned
;
13585 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13586 *type
= NT_integer
;
13587 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13588 *type
= NT_untyped
;
13589 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13591 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13599 /* Modify a bitmask of allowed types. This is only needed for type
13603 modify_types_allowed (unsigned allowed
, unsigned mods
)
13606 enum neon_el_type type
;
13612 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13614 if (el_type_of_type_chk (&type
, &size
,
13615 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13617 neon_modify_type_size (mods
, &type
, &size
);
13618 destmask
|= type_chk_of_el_type (type
, size
);
13625 /* Check type and return type classification.
13626 The manual states (paraphrase): If one datatype is given, it indicates the
13628 - the second operand, if there is one
13629 - the operand, if there is no second operand
13630 - the result, if there are no operands.
13631 This isn't quite good enough though, so we use a concept of a "key" datatype
13632 which is set on a per-instruction basis, which is the one which matters when
13633 only one data type is written.
13634 Note: this function has side-effects (e.g. filling in missing operands). All
13635 Neon instructions should call it before performing bit encoding. */
13637 static struct neon_type_el
13638 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13641 unsigned i
, pass
, key_el
= 0;
13642 unsigned types
[NEON_MAX_TYPE_ELS
];
13643 enum neon_el_type k_type
= NT_invtype
;
13644 unsigned k_size
= -1u;
13645 struct neon_type_el badtype
= {NT_invtype
, -1};
13646 unsigned key_allowed
= 0;
13648 /* Optional registers in Neon instructions are always (not) in operand 1.
13649 Fill in the missing operand here, if it was omitted. */
13650 if (els
> 1 && !inst
.operands
[1].present
)
13651 inst
.operands
[1] = inst
.operands
[0];
13653 /* Suck up all the varargs. */
13655 for (i
= 0; i
< els
; i
++)
13657 unsigned thisarg
= va_arg (ap
, unsigned);
13658 if (thisarg
== N_IGNORE_TYPE
)
13663 types
[i
] = thisarg
;
13664 if ((thisarg
& N_KEY
) != 0)
13669 if (inst
.vectype
.elems
> 0)
13670 for (i
= 0; i
< els
; i
++)
13671 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13673 first_error (_("types specified in both the mnemonic and operands"));
13677 /* Duplicate inst.vectype elements here as necessary.
13678 FIXME: No idea if this is exactly the same as the ARM assembler,
13679 particularly when an insn takes one register and one non-register
13681 if (inst
.vectype
.elems
== 1 && els
> 1)
13684 inst
.vectype
.elems
= els
;
13685 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13686 for (j
= 0; j
< els
; j
++)
13688 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13691 else if (inst
.vectype
.elems
== 0 && els
> 0)
13694 /* No types were given after the mnemonic, so look for types specified
13695 after each operand. We allow some flexibility here; as long as the
13696 "key" operand has a type, we can infer the others. */
13697 for (j
= 0; j
< els
; j
++)
13698 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13699 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13701 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13703 for (j
= 0; j
< els
; j
++)
13704 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13705 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13710 first_error (_("operand types can't be inferred"));
13714 else if (inst
.vectype
.elems
!= els
)
13716 first_error (_("type specifier has the wrong number of parts"));
13720 for (pass
= 0; pass
< 2; pass
++)
13722 for (i
= 0; i
< els
; i
++)
13724 unsigned thisarg
= types
[i
];
13725 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13726 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13727 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13728 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13730 /* Decay more-specific signed & unsigned types to sign-insensitive
13731 integer types if sign-specific variants are unavailable. */
13732 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13733 && (types_allowed
& N_SU_ALL
) == 0)
13734 g_type
= NT_integer
;
13736 /* If only untyped args are allowed, decay any more specific types to
13737 them. Some instructions only care about signs for some element
13738 sizes, so handle that properly. */
13739 if (((types_allowed
& N_UNT
) == 0)
13740 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13741 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13742 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13743 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13744 g_type
= NT_untyped
;
13748 if ((thisarg
& N_KEY
) != 0)
13752 key_allowed
= thisarg
& ~N_KEY
;
13757 if ((thisarg
& N_VFP
) != 0)
13759 enum neon_shape_el regshape
;
13760 unsigned regwidth
, match
;
13762 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13765 first_error (_("invalid instruction shape"));
13768 regshape
= neon_shape_tab
[ns
].el
[i
];
13769 regwidth
= neon_shape_el_size
[regshape
];
13771 /* In VFP mode, operands must match register widths. If we
13772 have a key operand, use its width, else use the width of
13773 the current operand. */
13779 if (regwidth
!= match
)
13781 first_error (_("operand size must match register width"));
13786 if ((thisarg
& N_EQK
) == 0)
13788 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13790 if ((given_type
& types_allowed
) == 0)
13792 first_error (_("bad type in Neon instruction"));
13798 enum neon_el_type mod_k_type
= k_type
;
13799 unsigned mod_k_size
= k_size
;
13800 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13801 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13803 first_error (_("inconsistent types in Neon instruction"));
13811 return inst
.vectype
.el
[key_el
];
13814 /* Neon-style VFP instruction forwarding. */
13816 /* Thumb VFP instructions have 0xE in the condition field. */
13819 do_vfp_cond_or_thumb (void)
13824 inst
.instruction
|= 0xe0000000;
13826 inst
.instruction
|= inst
.cond
<< 28;
13829 /* Look up and encode a simple mnemonic, for use as a helper function for the
13830 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13831 etc. It is assumed that operand parsing has already been done, and that the
13832 operands are in the form expected by the given opcode (this isn't necessarily
13833 the same as the form in which they were parsed, hence some massaging must
13834 take place before this function is called).
13835 Checks current arch version against that in the looked-up opcode. */
13838 do_vfp_nsyn_opcode (const char *opname
)
13840 const struct asm_opcode
*opcode
;
13842 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13847 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13848 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13855 inst
.instruction
= opcode
->tvalue
;
13856 opcode
->tencode ();
13860 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13861 opcode
->aencode ();
13866 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13868 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13873 do_vfp_nsyn_opcode ("fadds");
13875 do_vfp_nsyn_opcode ("fsubs");
13880 do_vfp_nsyn_opcode ("faddd");
13882 do_vfp_nsyn_opcode ("fsubd");
13886 /* Check operand types to see if this is a VFP instruction, and if so call
13890 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13892 enum neon_shape rs
;
13893 struct neon_type_el et
;
13898 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13899 et
= neon_check_type (2, rs
,
13900 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13904 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13905 et
= neon_check_type (3, rs
,
13906 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13913 if (et
.type
!= NT_invtype
)
13924 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13926 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13931 do_vfp_nsyn_opcode ("fmacs");
13933 do_vfp_nsyn_opcode ("fnmacs");
13938 do_vfp_nsyn_opcode ("fmacd");
13940 do_vfp_nsyn_opcode ("fnmacd");
13945 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13947 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13952 do_vfp_nsyn_opcode ("ffmas");
13954 do_vfp_nsyn_opcode ("ffnmas");
13959 do_vfp_nsyn_opcode ("ffmad");
13961 do_vfp_nsyn_opcode ("ffnmad");
13966 do_vfp_nsyn_mul (enum neon_shape rs
)
13969 do_vfp_nsyn_opcode ("fmuls");
13971 do_vfp_nsyn_opcode ("fmuld");
13975 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13977 int is_neg
= (inst
.instruction
& 0x80) != 0;
13978 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13983 do_vfp_nsyn_opcode ("fnegs");
13985 do_vfp_nsyn_opcode ("fabss");
13990 do_vfp_nsyn_opcode ("fnegd");
13992 do_vfp_nsyn_opcode ("fabsd");
13996 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13997 insns belong to Neon, and are handled elsewhere. */
14000 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14002 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14006 do_vfp_nsyn_opcode ("fldmdbs");
14008 do_vfp_nsyn_opcode ("fldmias");
14013 do_vfp_nsyn_opcode ("fstmdbs");
14015 do_vfp_nsyn_opcode ("fstmias");
14020 do_vfp_nsyn_sqrt (void)
14022 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14023 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14026 do_vfp_nsyn_opcode ("fsqrts");
14028 do_vfp_nsyn_opcode ("fsqrtd");
14032 do_vfp_nsyn_div (void)
14034 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14035 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14036 N_F32
| N_F64
| N_KEY
| N_VFP
);
14039 do_vfp_nsyn_opcode ("fdivs");
14041 do_vfp_nsyn_opcode ("fdivd");
14045 do_vfp_nsyn_nmul (void)
14047 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14048 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14049 N_F32
| N_F64
| N_KEY
| N_VFP
);
14053 NEON_ENCODE (SINGLE
, inst
);
14054 do_vfp_sp_dyadic ();
14058 NEON_ENCODE (DOUBLE
, inst
);
14059 do_vfp_dp_rd_rn_rm ();
14061 do_vfp_cond_or_thumb ();
14065 do_vfp_nsyn_cmp (void)
14067 if (inst
.operands
[1].isreg
)
14069 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14070 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14074 NEON_ENCODE (SINGLE
, inst
);
14075 do_vfp_sp_monadic ();
14079 NEON_ENCODE (DOUBLE
, inst
);
14080 do_vfp_dp_rd_rm ();
14085 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14086 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14088 switch (inst
.instruction
& 0x0fffffff)
14091 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14094 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14102 NEON_ENCODE (SINGLE
, inst
);
14103 do_vfp_sp_compare_z ();
14107 NEON_ENCODE (DOUBLE
, inst
);
14111 do_vfp_cond_or_thumb ();
14115 nsyn_insert_sp (void)
14117 inst
.operands
[1] = inst
.operands
[0];
14118 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14119 inst
.operands
[0].reg
= REG_SP
;
14120 inst
.operands
[0].isreg
= 1;
14121 inst
.operands
[0].writeback
= 1;
14122 inst
.operands
[0].present
= 1;
14126 do_vfp_nsyn_push (void)
14129 if (inst
.operands
[1].issingle
)
14130 do_vfp_nsyn_opcode ("fstmdbs");
14132 do_vfp_nsyn_opcode ("fstmdbd");
14136 do_vfp_nsyn_pop (void)
14139 if (inst
.operands
[1].issingle
)
14140 do_vfp_nsyn_opcode ("fldmias");
14142 do_vfp_nsyn_opcode ("fldmiad");
14145 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14146 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14149 neon_dp_fixup (struct arm_it
* insn
)
14151 unsigned int i
= insn
->instruction
;
14156 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14167 insn
->instruction
= i
;
14170 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14174 neon_logbits (unsigned x
)
14176 return ffs (x
) - 4;
14179 #define LOW4(R) ((R) & 0xf)
14180 #define HI1(R) (((R) >> 4) & 1)
14182 /* Encode insns with bit pattern:
14184 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14185 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14187 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14188 different meaning for some instruction. */
14191 neon_three_same (int isquad
, int ubit
, int size
)
14193 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14194 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14195 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14196 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14197 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14198 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14199 inst
.instruction
|= (isquad
!= 0) << 6;
14200 inst
.instruction
|= (ubit
!= 0) << 24;
14202 inst
.instruction
|= neon_logbits (size
) << 20;
14204 neon_dp_fixup (&inst
);
14207 /* Encode instructions of the form:
14209 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14210 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14212 Don't write size if SIZE == -1. */
14215 neon_two_same (int qbit
, int ubit
, int size
)
14217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14219 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14220 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14221 inst
.instruction
|= (qbit
!= 0) << 6;
14222 inst
.instruction
|= (ubit
!= 0) << 24;
14225 inst
.instruction
|= neon_logbits (size
) << 18;
14227 neon_dp_fixup (&inst
);
14230 /* Neon instruction encoders, in approximate order of appearance. */
14233 do_neon_dyadic_i_su (void)
14235 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14236 struct neon_type_el et
= neon_check_type (3, rs
,
14237 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14238 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14242 do_neon_dyadic_i64_su (void)
14244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14245 struct neon_type_el et
= neon_check_type (3, rs
,
14246 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14247 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14251 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14254 unsigned size
= et
.size
>> 3;
14255 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14256 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14257 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14259 inst
.instruction
|= (isquad
!= 0) << 6;
14260 inst
.instruction
|= immbits
<< 16;
14261 inst
.instruction
|= (size
>> 3) << 7;
14262 inst
.instruction
|= (size
& 0x7) << 19;
14264 inst
.instruction
|= (uval
!= 0) << 24;
14266 neon_dp_fixup (&inst
);
14270 do_neon_shl_imm (void)
14272 if (!inst
.operands
[2].isreg
)
14274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14275 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14276 int imm
= inst
.operands
[2].imm
;
14278 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14279 _("immediate out of range for shift"));
14280 NEON_ENCODE (IMMED
, inst
);
14281 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14285 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14286 struct neon_type_el et
= neon_check_type (3, rs
,
14287 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14290 /* VSHL/VQSHL 3-register variants have syntax such as:
14292 whereas other 3-register operations encoded by neon_three_same have
14295 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14297 tmp
= inst
.operands
[2].reg
;
14298 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14299 inst
.operands
[1].reg
= tmp
;
14300 NEON_ENCODE (INTEGER
, inst
);
14301 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14306 do_neon_qshl_imm (void)
14308 if (!inst
.operands
[2].isreg
)
14310 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14311 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14312 int imm
= inst
.operands
[2].imm
;
14314 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14315 _("immediate out of range for shift"));
14316 NEON_ENCODE (IMMED
, inst
);
14317 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14321 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14322 struct neon_type_el et
= neon_check_type (3, rs
,
14323 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14326 /* See note in do_neon_shl_imm. */
14327 tmp
= inst
.operands
[2].reg
;
14328 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14329 inst
.operands
[1].reg
= tmp
;
14330 NEON_ENCODE (INTEGER
, inst
);
14331 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14336 do_neon_rshl (void)
14338 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14339 struct neon_type_el et
= neon_check_type (3, rs
,
14340 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14343 tmp
= inst
.operands
[2].reg
;
14344 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14345 inst
.operands
[1].reg
= tmp
;
14346 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14350 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14352 /* Handle .I8 pseudo-instructions. */
14355 /* Unfortunately, this will make everything apart from zero out-of-range.
14356 FIXME is this the intended semantics? There doesn't seem much point in
14357 accepting .I8 if so. */
14358 immediate
|= immediate
<< 8;
14364 if (immediate
== (immediate
& 0x000000ff))
14366 *immbits
= immediate
;
14369 else if (immediate
== (immediate
& 0x0000ff00))
14371 *immbits
= immediate
>> 8;
14374 else if (immediate
== (immediate
& 0x00ff0000))
14376 *immbits
= immediate
>> 16;
14379 else if (immediate
== (immediate
& 0xff000000))
14381 *immbits
= immediate
>> 24;
14384 if ((immediate
& 0xffff) != (immediate
>> 16))
14385 goto bad_immediate
;
14386 immediate
&= 0xffff;
14389 if (immediate
== (immediate
& 0x000000ff))
14391 *immbits
= immediate
;
14394 else if (immediate
== (immediate
& 0x0000ff00))
14396 *immbits
= immediate
>> 8;
14401 first_error (_("immediate value out of range"));
14406 do_neon_logic (void)
14408 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14410 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14411 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14412 /* U bit and size field were set as part of the bitmask. */
14413 NEON_ENCODE (INTEGER
, inst
);
14414 neon_three_same (neon_quad (rs
), 0, -1);
14418 const int three_ops_form
= (inst
.operands
[2].present
14419 && !inst
.operands
[2].isreg
);
14420 const int immoperand
= (three_ops_form
? 2 : 1);
14421 enum neon_shape rs
= (three_ops_form
14422 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14423 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14424 struct neon_type_el et
= neon_check_type (2, rs
,
14425 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14426 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14430 if (et
.type
== NT_invtype
)
14433 if (three_ops_form
)
14434 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14435 _("first and second operands shall be the same register"));
14437 NEON_ENCODE (IMMED
, inst
);
14439 immbits
= inst
.operands
[immoperand
].imm
;
14442 /* .i64 is a pseudo-op, so the immediate must be a repeating
14444 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14445 inst
.operands
[immoperand
].reg
: 0))
14447 /* Set immbits to an invalid constant. */
14448 immbits
= 0xdeadbeef;
14455 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14459 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14463 /* Pseudo-instruction for VBIC. */
14464 neon_invert_size (&immbits
, 0, et
.size
);
14465 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14469 /* Pseudo-instruction for VORR. */
14470 neon_invert_size (&immbits
, 0, et
.size
);
14471 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14481 inst
.instruction
|= neon_quad (rs
) << 6;
14482 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14483 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14484 inst
.instruction
|= cmode
<< 8;
14485 neon_write_immbits (immbits
);
14487 neon_dp_fixup (&inst
);
14492 do_neon_bitfield (void)
14494 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14495 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14496 neon_three_same (neon_quad (rs
), 0, -1);
14500 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14503 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14504 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14506 if (et
.type
== NT_float
)
14508 NEON_ENCODE (FLOAT
, inst
);
14509 neon_three_same (neon_quad (rs
), 0, -1);
14513 NEON_ENCODE (INTEGER
, inst
);
14514 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14519 do_neon_dyadic_if_su (void)
14521 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14525 do_neon_dyadic_if_su_d (void)
14527 /* This version only allow D registers, but that constraint is enforced during
14528 operand parsing so we don't need to do anything extra here. */
14529 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14533 do_neon_dyadic_if_i_d (void)
14535 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14536 affected if we specify unsigned args. */
14537 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14540 enum vfp_or_neon_is_neon_bits
14543 NEON_CHECK_ARCH
= 2,
14544 NEON_CHECK_ARCH8
= 4
14547 /* Call this function if an instruction which may have belonged to the VFP or
14548 Neon instruction sets, but turned out to be a Neon instruction (due to the
14549 operand types involved, etc.). We have to check and/or fix-up a couple of
14552 - Make sure the user hasn't attempted to make a Neon instruction
14554 - Alter the value in the condition code field if necessary.
14555 - Make sure that the arch supports Neon instructions.
14557 Which of these operations take place depends on bits from enum
14558 vfp_or_neon_is_neon_bits.
14560 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14561 current instruction's condition is COND_ALWAYS, the condition field is
14562 changed to inst.uncond_value. This is necessary because instructions shared
14563 between VFP and Neon may be conditional for the VFP variants only, and the
14564 unconditional Neon version must have, e.g., 0xF in the condition field. */
14567 vfp_or_neon_is_neon (unsigned check
)
14569 /* Conditions are always legal in Thumb mode (IT blocks). */
14570 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14572 if (inst
.cond
!= COND_ALWAYS
)
14574 first_error (_(BAD_COND
));
14577 if (inst
.uncond_value
!= -1)
14578 inst
.instruction
|= inst
.uncond_value
<< 28;
14581 if ((check
& NEON_CHECK_ARCH
)
14582 && !mark_feature_used (&fpu_neon_ext_v1
))
14584 first_error (_(BAD_FPU
));
14588 if ((check
& NEON_CHECK_ARCH8
)
14589 && !mark_feature_used (&fpu_neon_ext_armv8
))
14591 first_error (_(BAD_FPU
));
14599 do_neon_addsub_if_i (void)
14601 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14604 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14607 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14608 affected if we specify unsigned args. */
14609 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14612 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14614 V<op> A,B (A is operand 0, B is operand 2)
14619 so handle that case specially. */
14622 neon_exchange_operands (void)
14624 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14625 if (inst
.operands
[1].present
)
14627 /* Swap operands[1] and operands[2]. */
14628 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14629 inst
.operands
[1] = inst
.operands
[2];
14630 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14634 inst
.operands
[1] = inst
.operands
[2];
14635 inst
.operands
[2] = inst
.operands
[0];
14640 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14642 if (inst
.operands
[2].isreg
)
14645 neon_exchange_operands ();
14646 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14650 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14651 struct neon_type_el et
= neon_check_type (2, rs
,
14652 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14654 NEON_ENCODE (IMMED
, inst
);
14655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14659 inst
.instruction
|= neon_quad (rs
) << 6;
14660 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14661 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14663 neon_dp_fixup (&inst
);
14670 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14674 do_neon_cmp_inv (void)
14676 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14682 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14685 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14686 scalars, which are encoded in 5 bits, M : Rm.
14687 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14688 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14692 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14694 unsigned regno
= NEON_SCALAR_REG (scalar
);
14695 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14700 if (regno
> 7 || elno
> 3)
14702 return regno
| (elno
<< 3);
14705 if (regno
> 15 || elno
> 1)
14707 return regno
| (elno
<< 4);
14711 first_error (_("scalar out of range for multiply instruction"));
14717 /* Encode multiply / multiply-accumulate scalar instructions. */
14720 neon_mul_mac (struct neon_type_el et
, int ubit
)
14724 /* Give a more helpful error message if we have an invalid type. */
14725 if (et
.type
== NT_invtype
)
14728 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14731 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14732 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14733 inst
.instruction
|= LOW4 (scalar
);
14734 inst
.instruction
|= HI1 (scalar
) << 5;
14735 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14736 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14737 inst
.instruction
|= (ubit
!= 0) << 24;
14739 neon_dp_fixup (&inst
);
14743 do_neon_mac_maybe_scalar (void)
14745 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14748 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14751 if (inst
.operands
[2].isscalar
)
14753 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14754 struct neon_type_el et
= neon_check_type (3, rs
,
14755 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14756 NEON_ENCODE (SCALAR
, inst
);
14757 neon_mul_mac (et
, neon_quad (rs
));
14761 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14762 affected if we specify unsigned args. */
14763 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14768 do_neon_fmac (void)
14770 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14773 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14776 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14782 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14783 struct neon_type_el et
= neon_check_type (3, rs
,
14784 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14785 neon_three_same (neon_quad (rs
), 0, et
.size
);
14788 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14789 same types as the MAC equivalents. The polynomial type for this instruction
14790 is encoded the same as the integer type. */
14795 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14798 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14801 if (inst
.operands
[2].isscalar
)
14802 do_neon_mac_maybe_scalar ();
14804 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14808 do_neon_qdmulh (void)
14810 if (inst
.operands
[2].isscalar
)
14812 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14813 struct neon_type_el et
= neon_check_type (3, rs
,
14814 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14815 NEON_ENCODE (SCALAR
, inst
);
14816 neon_mul_mac (et
, neon_quad (rs
));
14820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14821 struct neon_type_el et
= neon_check_type (3, rs
,
14822 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14823 NEON_ENCODE (INTEGER
, inst
);
14824 /* The U bit (rounding) comes from bit mask. */
14825 neon_three_same (neon_quad (rs
), 0, et
.size
);
14830 do_neon_fcmp_absolute (void)
14832 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14833 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14834 /* Size field comes from bit mask. */
14835 neon_three_same (neon_quad (rs
), 1, -1);
14839 do_neon_fcmp_absolute_inv (void)
14841 neon_exchange_operands ();
14842 do_neon_fcmp_absolute ();
14846 do_neon_step (void)
14848 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14849 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14850 neon_three_same (neon_quad (rs
), 0, -1);
14854 do_neon_abs_neg (void)
14856 enum neon_shape rs
;
14857 struct neon_type_el et
;
14859 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14862 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14865 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14866 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14870 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14871 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14872 inst
.instruction
|= neon_quad (rs
) << 6;
14873 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14874 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14876 neon_dp_fixup (&inst
);
14882 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14883 struct neon_type_el et
= neon_check_type (2, rs
,
14884 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14885 int imm
= inst
.operands
[2].imm
;
14886 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14887 _("immediate out of range for insert"));
14888 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14894 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14895 struct neon_type_el et
= neon_check_type (2, rs
,
14896 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14897 int imm
= inst
.operands
[2].imm
;
14898 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14899 _("immediate out of range for insert"));
14900 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14904 do_neon_qshlu_imm (void)
14906 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14907 struct neon_type_el et
= neon_check_type (2, rs
,
14908 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14909 int imm
= inst
.operands
[2].imm
;
14910 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14911 _("immediate out of range for shift"));
14912 /* Only encodes the 'U present' variant of the instruction.
14913 In this case, signed types have OP (bit 8) set to 0.
14914 Unsigned types have OP set to 1. */
14915 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14916 /* The rest of the bits are the same as other immediate shifts. */
14917 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14921 do_neon_qmovn (void)
14923 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14924 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14925 /* Saturating move where operands can be signed or unsigned, and the
14926 destination has the same signedness. */
14927 NEON_ENCODE (INTEGER
, inst
);
14928 if (et
.type
== NT_unsigned
)
14929 inst
.instruction
|= 0xc0;
14931 inst
.instruction
|= 0x80;
14932 neon_two_same (0, 1, et
.size
/ 2);
14936 do_neon_qmovun (void)
14938 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14939 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14940 /* Saturating move with unsigned results. Operands must be signed. */
14941 NEON_ENCODE (INTEGER
, inst
);
14942 neon_two_same (0, 1, et
.size
/ 2);
14946 do_neon_rshift_sat_narrow (void)
14948 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14949 or unsigned. If operands are unsigned, results must also be unsigned. */
14950 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14951 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14952 int imm
= inst
.operands
[2].imm
;
14953 /* This gets the bounds check, size encoding and immediate bits calculation
14957 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14958 VQMOVN.I<size> <Dd>, <Qm>. */
14961 inst
.operands
[2].present
= 0;
14962 inst
.instruction
= N_MNEM_vqmovn
;
14967 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14968 _("immediate out of range"));
14969 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14973 do_neon_rshift_sat_narrow_u (void)
14975 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14976 or unsigned. If operands are unsigned, results must also be unsigned. */
14977 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14978 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14979 int imm
= inst
.operands
[2].imm
;
14980 /* This gets the bounds check, size encoding and immediate bits calculation
14984 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14985 VQMOVUN.I<size> <Dd>, <Qm>. */
14988 inst
.operands
[2].present
= 0;
14989 inst
.instruction
= N_MNEM_vqmovun
;
14994 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14995 _("immediate out of range"));
14996 /* FIXME: The manual is kind of unclear about what value U should have in
14997 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14999 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15003 do_neon_movn (void)
15005 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15006 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15007 NEON_ENCODE (INTEGER
, inst
);
15008 neon_two_same (0, 1, et
.size
/ 2);
15012 do_neon_rshift_narrow (void)
15014 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15015 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15016 int imm
= inst
.operands
[2].imm
;
15017 /* This gets the bounds check, size encoding and immediate bits calculation
15021 /* If immediate is zero then we are a pseudo-instruction for
15022 VMOVN.I<size> <Dd>, <Qm> */
15025 inst
.operands
[2].present
= 0;
15026 inst
.instruction
= N_MNEM_vmovn
;
15031 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15032 _("immediate out of range for narrowing operation"));
15033 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15037 do_neon_shll (void)
15039 /* FIXME: Type checking when lengthening. */
15040 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15041 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15042 unsigned imm
= inst
.operands
[2].imm
;
15044 if (imm
== et
.size
)
15046 /* Maximum shift variant. */
15047 NEON_ENCODE (INTEGER
, inst
);
15048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15049 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15050 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15051 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15052 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15054 neon_dp_fixup (&inst
);
15058 /* A more-specific type check for non-max versions. */
15059 et
= neon_check_type (2, NS_QDI
,
15060 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15061 NEON_ENCODE (IMMED
, inst
);
15062 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15066 /* Check the various types for the VCVT instruction, and return which version
15067 the current instruction is. */
15069 #define CVT_FLAVOUR_VAR \
15070 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15071 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15072 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15073 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15074 /* Half-precision conversions. */ \
15075 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15076 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15077 /* VFP instructions. */ \
15078 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15079 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15080 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15081 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15082 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15083 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15084 /* VFP instructions with bitshift. */ \
15085 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15086 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15087 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15088 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15089 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15090 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15091 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15092 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15094 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15095 neon_cvt_flavour_##C,
15097 /* The different types of conversions we can do. */
15098 enum neon_cvt_flavour
15101 neon_cvt_flavour_invalid
,
15102 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15107 static enum neon_cvt_flavour
15108 get_neon_cvt_flavour (enum neon_shape rs
)
15110 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15111 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15112 if (et.type != NT_invtype) \
15114 inst.error = NULL; \
15115 return (neon_cvt_flavour_##C); \
15118 struct neon_type_el et
;
15119 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15120 || rs
== NS_FF
) ? N_VFP
: 0;
15121 /* The instruction versions which take an immediate take one register
15122 argument, which is extended to the width of the full register. Thus the
15123 "source" and "destination" registers must have the same width. Hack that
15124 here by making the size equal to the key (wider, in this case) operand. */
15125 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15129 return neon_cvt_flavour_invalid
;
15144 /* Neon-syntax VFP conversions. */
15147 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15149 const char *opname
= 0;
15151 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15153 /* Conversions with immediate bitshift. */
15154 const char *enc
[] =
15156 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15162 if (flavour
< (int) ARRAY_SIZE (enc
))
15164 opname
= enc
[flavour
];
15165 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15166 _("operands 0 and 1 must be the same register"));
15167 inst
.operands
[1] = inst
.operands
[2];
15168 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15173 /* Conversions without bitshift. */
15174 const char *enc
[] =
15176 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15182 if (flavour
< (int) ARRAY_SIZE (enc
))
15183 opname
= enc
[flavour
];
15187 do_vfp_nsyn_opcode (opname
);
15191 do_vfp_nsyn_cvtz (void)
15193 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15194 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15195 const char *enc
[] =
15197 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15203 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15204 do_vfp_nsyn_opcode (enc
[flavour
]);
15208 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15209 enum neon_cvt_mode mode
)
15214 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15215 D register operands. */
15216 if (flavour
== neon_cvt_flavour_s32_f64
15217 || flavour
== neon_cvt_flavour_u32_f64
)
15218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15221 set_it_insn_type (OUTSIDE_IT_INSN
);
15225 case neon_cvt_flavour_s32_f64
:
15229 case neon_cvt_flavour_s32_f32
:
15233 case neon_cvt_flavour_u32_f64
:
15237 case neon_cvt_flavour_u32_f32
:
15242 first_error (_("invalid instruction shape"));
15248 case neon_cvt_mode_a
: rm
= 0; break;
15249 case neon_cvt_mode_n
: rm
= 1; break;
15250 case neon_cvt_mode_p
: rm
= 2; break;
15251 case neon_cvt_mode_m
: rm
= 3; break;
15252 default: first_error (_("invalid rounding mode")); return;
15255 NEON_ENCODE (FPV8
, inst
);
15256 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15257 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15258 inst
.instruction
|= sz
<< 8;
15259 inst
.instruction
|= op
<< 7;
15260 inst
.instruction
|= rm
<< 16;
15261 inst
.instruction
|= 0xf0000000;
15262 inst
.is_neon
= TRUE
;
15266 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15268 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15269 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15270 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15272 /* PR11109: Handle round-to-zero for VCVT conversions. */
15273 if (mode
== neon_cvt_mode_z
15274 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15275 && (flavour
== neon_cvt_flavour_s32_f32
15276 || flavour
== neon_cvt_flavour_u32_f32
15277 || flavour
== neon_cvt_flavour_s32_f64
15278 || flavour
== neon_cvt_flavour_u32_f64
)
15279 && (rs
== NS_FD
|| rs
== NS_FF
))
15281 do_vfp_nsyn_cvtz ();
15285 /* VFP rather than Neon conversions. */
15286 if (flavour
>= neon_cvt_flavour_first_fp
)
15288 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15289 do_vfp_nsyn_cvt (rs
, flavour
);
15291 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15302 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15304 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15307 /* Fixed-point conversion with #0 immediate is encoded as an
15308 integer conversion. */
15309 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15311 immbits
= 32 - inst
.operands
[2].imm
;
15312 NEON_ENCODE (IMMED
, inst
);
15313 if (flavour
!= neon_cvt_flavour_invalid
)
15314 inst
.instruction
|= enctab
[flavour
];
15315 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15316 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15317 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15318 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15319 inst
.instruction
|= neon_quad (rs
) << 6;
15320 inst
.instruction
|= 1 << 21;
15321 inst
.instruction
|= immbits
<< 16;
15323 neon_dp_fixup (&inst
);
15329 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15331 NEON_ENCODE (FLOAT
, inst
);
15332 set_it_insn_type (OUTSIDE_IT_INSN
);
15334 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15337 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15338 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15339 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15340 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15341 inst
.instruction
|= neon_quad (rs
) << 6;
15342 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15343 inst
.instruction
|= mode
<< 8;
15345 inst
.instruction
|= 0xfc000000;
15347 inst
.instruction
|= 0xf0000000;
15353 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15355 NEON_ENCODE (INTEGER
, inst
);
15357 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15360 if (flavour
!= neon_cvt_flavour_invalid
)
15361 inst
.instruction
|= enctab
[flavour
];
15363 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15364 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15365 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15366 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15367 inst
.instruction
|= neon_quad (rs
) << 6;
15368 inst
.instruction
|= 2 << 18;
15370 neon_dp_fixup (&inst
);
15375 /* Half-precision conversions for Advanced SIMD -- neon. */
15380 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15382 as_bad (_("operand size must match register width"));
15387 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15389 as_bad (_("operand size must match register width"));
15394 inst
.instruction
= 0x3b60600;
15396 inst
.instruction
= 0x3b60700;
15398 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15399 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15400 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15401 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15402 neon_dp_fixup (&inst
);
15406 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15407 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15408 do_vfp_nsyn_cvt (rs
, flavour
);
15410 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15415 do_neon_cvtr (void)
15417 do_neon_cvt_1 (neon_cvt_mode_x
);
15423 do_neon_cvt_1 (neon_cvt_mode_z
);
15427 do_neon_cvta (void)
15429 do_neon_cvt_1 (neon_cvt_mode_a
);
15433 do_neon_cvtn (void)
15435 do_neon_cvt_1 (neon_cvt_mode_n
);
15439 do_neon_cvtp (void)
15441 do_neon_cvt_1 (neon_cvt_mode_p
);
15445 do_neon_cvtm (void)
15447 do_neon_cvt_1 (neon_cvt_mode_m
);
15451 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15454 mark_feature_used (&fpu_vfp_ext_armv8
);
15456 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15457 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15458 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15459 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15460 inst
.instruction
|= to
? 0x10000 : 0;
15461 inst
.instruction
|= t
? 0x80 : 0;
15462 inst
.instruction
|= is_double
? 0x100 : 0;
15463 do_vfp_cond_or_thumb ();
15467 do_neon_cvttb_1 (bfd_boolean t
)
15469 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15473 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15476 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15478 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15481 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15483 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15485 /* The VCVTB and VCVTT instructions with D-register operands
15486 don't work for SP only targets. */
15487 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15491 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15493 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15495 /* The VCVTB and VCVTT instructions with D-register operands
15496 don't work for SP only targets. */
15497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15501 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15508 do_neon_cvtb (void)
15510 do_neon_cvttb_1 (FALSE
);
15515 do_neon_cvtt (void)
15517 do_neon_cvttb_1 (TRUE
);
15521 neon_move_immediate (void)
15523 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15524 struct neon_type_el et
= neon_check_type (2, rs
,
15525 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15526 unsigned immlo
, immhi
= 0, immbits
;
15527 int op
, cmode
, float_p
;
15529 constraint (et
.type
== NT_invtype
,
15530 _("operand size must be specified for immediate VMOV"));
15532 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15533 op
= (inst
.instruction
& (1 << 5)) != 0;
15535 immlo
= inst
.operands
[1].imm
;
15536 if (inst
.operands
[1].regisimm
)
15537 immhi
= inst
.operands
[1].reg
;
15539 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15540 _("immediate has bits set outside the operand size"));
15542 float_p
= inst
.operands
[1].immisfloat
;
15544 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15545 et
.size
, et
.type
)) == FAIL
)
15547 /* Invert relevant bits only. */
15548 neon_invert_size (&immlo
, &immhi
, et
.size
);
15549 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15550 with one or the other; those cases are caught by
15551 neon_cmode_for_move_imm. */
15553 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15554 &op
, et
.size
, et
.type
)) == FAIL
)
15556 first_error (_("immediate out of range"));
15561 inst
.instruction
&= ~(1 << 5);
15562 inst
.instruction
|= op
<< 5;
15564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15566 inst
.instruction
|= neon_quad (rs
) << 6;
15567 inst
.instruction
|= cmode
<< 8;
15569 neon_write_immbits (immbits
);
15575 if (inst
.operands
[1].isreg
)
15577 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15579 NEON_ENCODE (INTEGER
, inst
);
15580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15584 inst
.instruction
|= neon_quad (rs
) << 6;
15588 NEON_ENCODE (IMMED
, inst
);
15589 neon_move_immediate ();
15592 neon_dp_fixup (&inst
);
15595 /* Encode instructions of form:
15597 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15598 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15601 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15605 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15606 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15607 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15608 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15609 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15610 inst
.instruction
|= neon_logbits (size
) << 20;
15612 neon_dp_fixup (&inst
);
15616 do_neon_dyadic_long (void)
15618 /* FIXME: Type checking for lengthening op. */
15619 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15620 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15621 neon_mixed_length (et
, et
.size
);
15625 do_neon_abal (void)
15627 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15628 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15629 neon_mixed_length (et
, et
.size
);
15633 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15635 if (inst
.operands
[2].isscalar
)
15637 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15638 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15639 NEON_ENCODE (SCALAR
, inst
);
15640 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15644 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15645 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15646 NEON_ENCODE (INTEGER
, inst
);
15647 neon_mixed_length (et
, et
.size
);
15652 do_neon_mac_maybe_scalar_long (void)
15654 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15658 do_neon_dyadic_wide (void)
15660 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15661 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15662 neon_mixed_length (et
, et
.size
);
15666 do_neon_dyadic_narrow (void)
15668 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15669 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15670 /* Operand sign is unimportant, and the U bit is part of the opcode,
15671 so force the operand type to integer. */
15672 et
.type
= NT_integer
;
15673 neon_mixed_length (et
, et
.size
/ 2);
15677 do_neon_mul_sat_scalar_long (void)
15679 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15683 do_neon_vmull (void)
15685 if (inst
.operands
[2].isscalar
)
15686 do_neon_mac_maybe_scalar_long ();
15689 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15690 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15692 if (et
.type
== NT_poly
)
15693 NEON_ENCODE (POLY
, inst
);
15695 NEON_ENCODE (INTEGER
, inst
);
15697 /* For polynomial encoding the U bit must be zero, and the size must
15698 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15699 obviously, as 0b10). */
15702 /* Check we're on the correct architecture. */
15703 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15705 _("Instruction form not available on this architecture.");
15710 neon_mixed_length (et
, et
.size
);
15717 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15718 struct neon_type_el et
= neon_check_type (3, rs
,
15719 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15720 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15722 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15723 _("shift out of range"));
15724 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15725 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15726 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15727 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15728 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15729 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15730 inst
.instruction
|= neon_quad (rs
) << 6;
15731 inst
.instruction
|= imm
<< 8;
15733 neon_dp_fixup (&inst
);
15739 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15740 struct neon_type_el et
= neon_check_type (2, rs
,
15741 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15742 unsigned op
= (inst
.instruction
>> 7) & 3;
15743 /* N (width of reversed regions) is encoded as part of the bitmask. We
15744 extract it here to check the elements to be reversed are smaller.
15745 Otherwise we'd get a reserved instruction. */
15746 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15747 gas_assert (elsize
!= 0);
15748 constraint (et
.size
>= elsize
,
15749 _("elements must be smaller than reversal region"));
15750 neon_two_same (neon_quad (rs
), 1, et
.size
);
15756 if (inst
.operands
[1].isscalar
)
15758 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15759 struct neon_type_el et
= neon_check_type (2, rs
,
15760 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15761 unsigned sizebits
= et
.size
>> 3;
15762 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15763 int logsize
= neon_logbits (et
.size
);
15764 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15766 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15769 NEON_ENCODE (SCALAR
, inst
);
15770 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15771 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15772 inst
.instruction
|= LOW4 (dm
);
15773 inst
.instruction
|= HI1 (dm
) << 5;
15774 inst
.instruction
|= neon_quad (rs
) << 6;
15775 inst
.instruction
|= x
<< 17;
15776 inst
.instruction
|= sizebits
<< 16;
15778 neon_dp_fixup (&inst
);
15782 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15783 struct neon_type_el et
= neon_check_type (2, rs
,
15784 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15785 /* Duplicate ARM register to lanes of vector. */
15786 NEON_ENCODE (ARMREG
, inst
);
15789 case 8: inst
.instruction
|= 0x400000; break;
15790 case 16: inst
.instruction
|= 0x000020; break;
15791 case 32: inst
.instruction
|= 0x000000; break;
15794 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15797 inst
.instruction
|= neon_quad (rs
) << 21;
15798 /* The encoding for this instruction is identical for the ARM and Thumb
15799 variants, except for the condition field. */
15800 do_vfp_cond_or_thumb ();
15804 /* VMOV has particularly many variations. It can be one of:
15805 0. VMOV<c><q> <Qd>, <Qm>
15806 1. VMOV<c><q> <Dd>, <Dm>
15807 (Register operations, which are VORR with Rm = Rn.)
15808 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15809 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15811 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15812 (ARM register to scalar.)
15813 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15814 (Two ARM registers to vector.)
15815 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15816 (Scalar to ARM register.)
15817 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15818 (Vector to two ARM registers.)
15819 8. VMOV.F32 <Sd>, <Sm>
15820 9. VMOV.F64 <Dd>, <Dm>
15821 (VFP register moves.)
15822 10. VMOV.F32 <Sd>, #imm
15823 11. VMOV.F64 <Dd>, #imm
15824 (VFP float immediate load.)
15825 12. VMOV <Rd>, <Sm>
15826 (VFP single to ARM reg.)
15827 13. VMOV <Sd>, <Rm>
15828 (ARM reg to VFP single.)
15829 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15830 (Two ARM regs to two VFP singles.)
15831 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15832 (Two VFP singles to two ARM regs.)
15834 These cases can be disambiguated using neon_select_shape, except cases 1/9
15835 and 3/11 which depend on the operand type too.
15837 All the encoded bits are hardcoded by this function.
15839 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15840 Cases 5, 7 may be used with VFPv2 and above.
15842 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15843 can specify a type where it doesn't make sense to, and is ignored). */
15848 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15849 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15851 struct neon_type_el et
;
15852 const char *ldconst
= 0;
15856 case NS_DD
: /* case 1/9. */
15857 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15858 /* It is not an error here if no type is given. */
15860 if (et
.type
== NT_float
&& et
.size
== 64)
15862 do_vfp_nsyn_opcode ("fcpyd");
15865 /* fall through. */
15867 case NS_QQ
: /* case 0/1. */
15869 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15871 /* The architecture manual I have doesn't explicitly state which
15872 value the U bit should have for register->register moves, but
15873 the equivalent VORR instruction has U = 0, so do that. */
15874 inst
.instruction
= 0x0200110;
15875 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15876 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15877 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15878 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15879 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15880 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15881 inst
.instruction
|= neon_quad (rs
) << 6;
15883 neon_dp_fixup (&inst
);
15887 case NS_DI
: /* case 3/11. */
15888 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15890 if (et
.type
== NT_float
&& et
.size
== 64)
15892 /* case 11 (fconstd). */
15893 ldconst
= "fconstd";
15894 goto encode_fconstd
;
15896 /* fall through. */
15898 case NS_QI
: /* case 2/3. */
15899 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15901 inst
.instruction
= 0x0800010;
15902 neon_move_immediate ();
15903 neon_dp_fixup (&inst
);
15906 case NS_SR
: /* case 4. */
15908 unsigned bcdebits
= 0;
15910 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15911 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15913 /* .<size> is optional here, defaulting to .32. */
15914 if (inst
.vectype
.elems
== 0
15915 && inst
.operands
[0].vectype
.type
== NT_invtype
15916 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15918 inst
.vectype
.el
[0].type
= NT_untyped
;
15919 inst
.vectype
.el
[0].size
= 32;
15920 inst
.vectype
.elems
= 1;
15923 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15924 logsize
= neon_logbits (et
.size
);
15926 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15928 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15929 && et
.size
!= 32, _(BAD_FPU
));
15930 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15931 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15935 case 8: bcdebits
= 0x8; break;
15936 case 16: bcdebits
= 0x1; break;
15937 case 32: bcdebits
= 0x0; break;
15941 bcdebits
|= x
<< logsize
;
15943 inst
.instruction
= 0xe000b10;
15944 do_vfp_cond_or_thumb ();
15945 inst
.instruction
|= LOW4 (dn
) << 16;
15946 inst
.instruction
|= HI1 (dn
) << 7;
15947 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15948 inst
.instruction
|= (bcdebits
& 3) << 5;
15949 inst
.instruction
|= (bcdebits
>> 2) << 21;
15953 case NS_DRR
: /* case 5 (fmdrr). */
15954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15957 inst
.instruction
= 0xc400b10;
15958 do_vfp_cond_or_thumb ();
15959 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15960 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15961 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15962 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15965 case NS_RS
: /* case 6. */
15968 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15969 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15970 unsigned abcdebits
= 0;
15972 /* .<dt> is optional here, defaulting to .32. */
15973 if (inst
.vectype
.elems
== 0
15974 && inst
.operands
[0].vectype
.type
== NT_invtype
15975 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15977 inst
.vectype
.el
[0].type
= NT_untyped
;
15978 inst
.vectype
.el
[0].size
= 32;
15979 inst
.vectype
.elems
= 1;
15982 et
= neon_check_type (2, NS_NULL
,
15983 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15984 logsize
= neon_logbits (et
.size
);
15986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15989 && et
.size
!= 32, _(BAD_FPU
));
15990 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15991 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15995 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15996 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15997 case 32: abcdebits
= 0x00; break;
16001 abcdebits
|= x
<< logsize
;
16002 inst
.instruction
= 0xe100b10;
16003 do_vfp_cond_or_thumb ();
16004 inst
.instruction
|= LOW4 (dn
) << 16;
16005 inst
.instruction
|= HI1 (dn
) << 7;
16006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16007 inst
.instruction
|= (abcdebits
& 3) << 5;
16008 inst
.instruction
|= (abcdebits
>> 2) << 21;
16012 case NS_RRD
: /* case 7 (fmrrd). */
16013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16016 inst
.instruction
= 0xc500b10;
16017 do_vfp_cond_or_thumb ();
16018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16019 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16020 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16021 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16024 case NS_FF
: /* case 8 (fcpys). */
16025 do_vfp_nsyn_opcode ("fcpys");
16028 case NS_FI
: /* case 10 (fconsts). */
16029 ldconst
= "fconsts";
16031 if (is_quarter_float (inst
.operands
[1].imm
))
16033 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16034 do_vfp_nsyn_opcode (ldconst
);
16037 first_error (_("immediate out of range"));
16040 case NS_RF
: /* case 12 (fmrs). */
16041 do_vfp_nsyn_opcode ("fmrs");
16044 case NS_FR
: /* case 13 (fmsr). */
16045 do_vfp_nsyn_opcode ("fmsr");
16048 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16049 (one of which is a list), but we have parsed four. Do some fiddling to
16050 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16052 case NS_RRFF
: /* case 14 (fmrrs). */
16053 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16054 _("VFP registers must be adjacent"));
16055 inst
.operands
[2].imm
= 2;
16056 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16057 do_vfp_nsyn_opcode ("fmrrs");
16060 case NS_FFRR
: /* case 15 (fmsrr). */
16061 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16062 _("VFP registers must be adjacent"));
16063 inst
.operands
[1] = inst
.operands
[2];
16064 inst
.operands
[2] = inst
.operands
[3];
16065 inst
.operands
[0].imm
= 2;
16066 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16067 do_vfp_nsyn_opcode ("fmsrr");
16071 /* neon_select_shape has determined that the instruction
16072 shape is wrong and has already set the error message. */
16081 do_neon_rshift_round_imm (void)
16083 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16084 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16085 int imm
= inst
.operands
[2].imm
;
16087 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16090 inst
.operands
[2].present
= 0;
16095 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16096 _("immediate out of range for shift"));
16097 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16102 do_neon_movl (void)
16104 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16105 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16106 unsigned sizebits
= et
.size
>> 3;
16107 inst
.instruction
|= sizebits
<< 19;
16108 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16114 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16115 struct neon_type_el et
= neon_check_type (2, rs
,
16116 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16117 NEON_ENCODE (INTEGER
, inst
);
16118 neon_two_same (neon_quad (rs
), 1, et
.size
);
16122 do_neon_zip_uzp (void)
16124 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16125 struct neon_type_el et
= neon_check_type (2, rs
,
16126 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16127 if (rs
== NS_DD
&& et
.size
== 32)
16129 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16130 inst
.instruction
= N_MNEM_vtrn
;
16134 neon_two_same (neon_quad (rs
), 1, et
.size
);
16138 do_neon_sat_abs_neg (void)
16140 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16141 struct neon_type_el et
= neon_check_type (2, rs
,
16142 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16143 neon_two_same (neon_quad (rs
), 1, et
.size
);
16147 do_neon_pair_long (void)
16149 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16150 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16151 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16152 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16153 neon_two_same (neon_quad (rs
), 1, et
.size
);
16157 do_neon_recip_est (void)
16159 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16160 struct neon_type_el et
= neon_check_type (2, rs
,
16161 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16162 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16163 neon_two_same (neon_quad (rs
), 1, et
.size
);
16169 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16170 struct neon_type_el et
= neon_check_type (2, rs
,
16171 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16172 neon_two_same (neon_quad (rs
), 1, et
.size
);
16178 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16179 struct neon_type_el et
= neon_check_type (2, rs
,
16180 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16181 neon_two_same (neon_quad (rs
), 1, et
.size
);
16187 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16188 struct neon_type_el et
= neon_check_type (2, rs
,
16189 N_EQK
| N_INT
, N_8
| N_KEY
);
16190 neon_two_same (neon_quad (rs
), 1, et
.size
);
16196 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16197 neon_two_same (neon_quad (rs
), 1, -1);
16201 do_neon_tbl_tbx (void)
16203 unsigned listlenbits
;
16204 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16206 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16208 first_error (_("bad list length for table lookup"));
16212 listlenbits
= inst
.operands
[1].imm
- 1;
16213 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16214 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16215 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16216 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16217 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16218 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16219 inst
.instruction
|= listlenbits
<< 8;
16221 neon_dp_fixup (&inst
);
16225 do_neon_ldm_stm (void)
16227 /* P, U and L bits are part of bitmask. */
16228 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16229 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16231 if (inst
.operands
[1].issingle
)
16233 do_vfp_nsyn_ldm_stm (is_dbmode
);
16237 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16238 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16240 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16241 _("register list must contain at least 1 and at most 16 "
16244 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16245 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16247 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16249 inst
.instruction
|= offsetbits
;
16251 do_vfp_cond_or_thumb ();
16255 do_neon_ldr_str (void)
16257 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16259 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16260 And is UNPREDICTABLE in thumb mode. */
16262 && inst
.operands
[1].reg
== REG_PC
16263 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16266 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16267 else if (warn_on_deprecated
)
16268 as_tsktsk (_("Use of PC here is deprecated"));
16271 if (inst
.operands
[0].issingle
)
16274 do_vfp_nsyn_opcode ("flds");
16276 do_vfp_nsyn_opcode ("fsts");
16281 do_vfp_nsyn_opcode ("fldd");
16283 do_vfp_nsyn_opcode ("fstd");
16287 /* "interleave" version also handles non-interleaving register VLD1/VST1
16291 do_neon_ld_st_interleave (void)
16293 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16294 N_8
| N_16
| N_32
| N_64
);
16295 unsigned alignbits
= 0;
16297 /* The bits in this table go:
16298 0: register stride of one (0) or two (1)
16299 1,2: register list length, minus one (1, 2, 3, 4).
16300 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16301 We use -1 for invalid entries. */
16302 const int typetable
[] =
16304 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16305 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16306 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16307 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16311 if (et
.type
== NT_invtype
)
16314 if (inst
.operands
[1].immisalign
)
16315 switch (inst
.operands
[1].imm
>> 8)
16317 case 64: alignbits
= 1; break;
16319 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16320 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16321 goto bad_alignment
;
16325 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16326 goto bad_alignment
;
16331 first_error (_("bad alignment"));
16335 inst
.instruction
|= alignbits
<< 4;
16336 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16338 /* Bits [4:6] of the immediate in a list specifier encode register stride
16339 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16340 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16341 up the right value for "type" in a table based on this value and the given
16342 list style, then stick it back. */
16343 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16344 | (((inst
.instruction
>> 8) & 3) << 3);
16346 typebits
= typetable
[idx
];
16348 constraint (typebits
== -1, _("bad list type for instruction"));
16349 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16350 _("bad element type for instruction"));
16352 inst
.instruction
&= ~0xf00;
16353 inst
.instruction
|= typebits
<< 8;
16356 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16357 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16358 otherwise. The variable arguments are a list of pairs of legal (size, align)
16359 values, terminated with -1. */
16362 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16365 int result
= FAIL
, thissize
, thisalign
;
16367 if (!inst
.operands
[1].immisalign
)
16373 va_start (ap
, do_align
);
16377 thissize
= va_arg (ap
, int);
16378 if (thissize
== -1)
16380 thisalign
= va_arg (ap
, int);
16382 if (size
== thissize
&& align
== thisalign
)
16385 while (result
!= SUCCESS
);
16389 if (result
== SUCCESS
)
16392 first_error (_("unsupported alignment for instruction"));
16398 do_neon_ld_st_lane (void)
16400 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16401 int align_good
, do_align
= 0;
16402 int logsize
= neon_logbits (et
.size
);
16403 int align
= inst
.operands
[1].imm
>> 8;
16404 int n
= (inst
.instruction
>> 8) & 3;
16405 int max_el
= 64 / et
.size
;
16407 if (et
.type
== NT_invtype
)
16410 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16411 _("bad list length"));
16412 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16413 _("scalar index out of range"));
16414 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16416 _("stride of 2 unavailable when element size is 8"));
16420 case 0: /* VLD1 / VST1. */
16421 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16423 if (align_good
== FAIL
)
16427 unsigned alignbits
= 0;
16430 case 16: alignbits
= 0x1; break;
16431 case 32: alignbits
= 0x3; break;
16434 inst
.instruction
|= alignbits
<< 4;
16438 case 1: /* VLD2 / VST2. */
16439 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16441 if (align_good
== FAIL
)
16444 inst
.instruction
|= 1 << 4;
16447 case 2: /* VLD3 / VST3. */
16448 constraint (inst
.operands
[1].immisalign
,
16449 _("can't use alignment with this instruction"));
16452 case 3: /* VLD4 / VST4. */
16453 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16454 16, 64, 32, 64, 32, 128, -1);
16455 if (align_good
== FAIL
)
16459 unsigned alignbits
= 0;
16462 case 8: alignbits
= 0x1; break;
16463 case 16: alignbits
= 0x1; break;
16464 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16467 inst
.instruction
|= alignbits
<< 4;
16474 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16475 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16476 inst
.instruction
|= 1 << (4 + logsize
);
16478 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16479 inst
.instruction
|= logsize
<< 10;
16482 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16485 do_neon_ld_dup (void)
16487 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16488 int align_good
, do_align
= 0;
16490 if (et
.type
== NT_invtype
)
16493 switch ((inst
.instruction
>> 8) & 3)
16495 case 0: /* VLD1. */
16496 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16497 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16498 &do_align
, 16, 16, 32, 32, -1);
16499 if (align_good
== FAIL
)
16501 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16504 case 2: inst
.instruction
|= 1 << 5; break;
16505 default: first_error (_("bad list length")); return;
16507 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16510 case 1: /* VLD2. */
16511 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16512 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16513 if (align_good
== FAIL
)
16515 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16516 _("bad list length"));
16517 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16518 inst
.instruction
|= 1 << 5;
16519 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16522 case 2: /* VLD3. */
16523 constraint (inst
.operands
[1].immisalign
,
16524 _("can't use alignment with this instruction"));
16525 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16526 _("bad list length"));
16527 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16528 inst
.instruction
|= 1 << 5;
16529 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16532 case 3: /* VLD4. */
16534 int align
= inst
.operands
[1].imm
>> 8;
16535 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16536 16, 64, 32, 64, 32, 128, -1);
16537 if (align_good
== FAIL
)
16539 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16540 _("bad list length"));
16541 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16542 inst
.instruction
|= 1 << 5;
16543 if (et
.size
== 32 && align
== 128)
16544 inst
.instruction
|= 0x3 << 6;
16546 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16553 inst
.instruction
|= do_align
<< 4;
16556 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16557 apart from bits [11:4]. */
16560 do_neon_ldx_stx (void)
16562 if (inst
.operands
[1].isreg
)
16563 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16565 switch (NEON_LANE (inst
.operands
[0].imm
))
16567 case NEON_INTERLEAVE_LANES
:
16568 NEON_ENCODE (INTERLV
, inst
);
16569 do_neon_ld_st_interleave ();
16572 case NEON_ALL_LANES
:
16573 NEON_ENCODE (DUP
, inst
);
16574 if (inst
.instruction
== N_INV
)
16576 first_error ("only loads support such operands");
16583 NEON_ENCODE (LANE
, inst
);
16584 do_neon_ld_st_lane ();
16587 /* L bit comes from bit mask. */
16588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16592 if (inst
.operands
[1].postind
)
16594 int postreg
= inst
.operands
[1].imm
& 0xf;
16595 constraint (!inst
.operands
[1].immisreg
,
16596 _("post-index must be a register"));
16597 constraint (postreg
== 0xd || postreg
== 0xf,
16598 _("bad register for post-index"));
16599 inst
.instruction
|= postreg
;
16603 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16604 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16605 || inst
.reloc
.exp
.X_add_number
!= 0,
16608 if (inst
.operands
[1].writeback
)
16610 inst
.instruction
|= 0xd;
16613 inst
.instruction
|= 0xf;
16617 inst
.instruction
|= 0xf9000000;
16619 inst
.instruction
|= 0xf4000000;
16624 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16626 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16627 D register operands. */
16628 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16629 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16632 NEON_ENCODE (FPV8
, inst
);
16635 do_vfp_sp_dyadic ();
16637 do_vfp_dp_rd_rn_rm ();
16640 inst
.instruction
|= 0x100;
16642 inst
.instruction
|= 0xf0000000;
16648 set_it_insn_type (OUTSIDE_IT_INSN
);
16650 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16651 first_error (_("invalid instruction shape"));
16657 set_it_insn_type (OUTSIDE_IT_INSN
);
16659 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16662 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16665 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16669 do_vrint_1 (enum neon_cvt_mode mode
)
16671 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16672 struct neon_type_el et
;
16677 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16678 D register operands. */
16679 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16680 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16683 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16684 if (et
.type
!= NT_invtype
)
16686 /* VFP encodings. */
16687 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16688 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16689 set_it_insn_type (OUTSIDE_IT_INSN
);
16691 NEON_ENCODE (FPV8
, inst
);
16693 do_vfp_sp_monadic ();
16695 do_vfp_dp_rd_rm ();
16699 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16700 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16701 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16702 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16703 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16704 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16705 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16709 inst
.instruction
|= (rs
== NS_DD
) << 8;
16710 do_vfp_cond_or_thumb ();
16714 /* Neon encodings (or something broken...). */
16716 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16718 if (et
.type
== NT_invtype
)
16721 set_it_insn_type (OUTSIDE_IT_INSN
);
16722 NEON_ENCODE (FLOAT
, inst
);
16724 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16727 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16728 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16729 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16730 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16731 inst
.instruction
|= neon_quad (rs
) << 6;
16734 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16735 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16736 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16737 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16738 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16739 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16740 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16745 inst
.instruction
|= 0xfc000000;
16747 inst
.instruction
|= 0xf0000000;
16754 do_vrint_1 (neon_cvt_mode_x
);
16760 do_vrint_1 (neon_cvt_mode_z
);
16766 do_vrint_1 (neon_cvt_mode_r
);
16772 do_vrint_1 (neon_cvt_mode_a
);
16778 do_vrint_1 (neon_cvt_mode_n
);
16784 do_vrint_1 (neon_cvt_mode_p
);
16790 do_vrint_1 (neon_cvt_mode_m
);
16793 /* Crypto v1 instructions. */
16795 do_crypto_2op_1 (unsigned elttype
, int op
)
16797 set_it_insn_type (OUTSIDE_IT_INSN
);
16799 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16805 NEON_ENCODE (INTEGER
, inst
);
16806 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16807 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16808 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16809 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16811 inst
.instruction
|= op
<< 6;
16814 inst
.instruction
|= 0xfc000000;
16816 inst
.instruction
|= 0xf0000000;
16820 do_crypto_3op_1 (int u
, int op
)
16822 set_it_insn_type (OUTSIDE_IT_INSN
);
16824 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16825 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16830 NEON_ENCODE (INTEGER
, inst
);
16831 neon_three_same (1, u
, 8 << op
);
16837 do_crypto_2op_1 (N_8
, 0);
16843 do_crypto_2op_1 (N_8
, 1);
16849 do_crypto_2op_1 (N_8
, 2);
16855 do_crypto_2op_1 (N_8
, 3);
16861 do_crypto_3op_1 (0, 0);
16867 do_crypto_3op_1 (0, 1);
16873 do_crypto_3op_1 (0, 2);
16879 do_crypto_3op_1 (0, 3);
16885 do_crypto_3op_1 (1, 0);
16891 do_crypto_3op_1 (1, 1);
16895 do_sha256su1 (void)
16897 do_crypto_3op_1 (1, 2);
16903 do_crypto_2op_1 (N_32
, -1);
16909 do_crypto_2op_1 (N_32
, 0);
16913 do_sha256su0 (void)
16915 do_crypto_2op_1 (N_32
, 1);
16919 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16921 unsigned int Rd
= inst
.operands
[0].reg
;
16922 unsigned int Rn
= inst
.operands
[1].reg
;
16923 unsigned int Rm
= inst
.operands
[2].reg
;
16925 set_it_insn_type (OUTSIDE_IT_INSN
);
16926 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16927 inst
.instruction
|= LOW4 (Rn
) << 16;
16928 inst
.instruction
|= LOW4 (Rm
);
16929 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16930 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16932 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16933 as_warn (UNPRED_REG ("r15"));
16934 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16935 as_warn (UNPRED_REG ("r13"));
16975 /* Overall per-instruction processing. */
16977 /* We need to be able to fix up arbitrary expressions in some statements.
16978 This is so that we can handle symbols that are an arbitrary distance from
16979 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16980 which returns part of an address in a form which will be valid for
16981 a data instruction. We do this by pushing the expression into a symbol
16982 in the expr_section, and creating a fix for that. */
16985 fix_new_arm (fragS
* frag
,
16999 /* Create an absolute valued symbol, so we have something to
17000 refer to in the object file. Unfortunately for us, gas's
17001 generic expression parsing will already have folded out
17002 any use of .set foo/.type foo %function that may have
17003 been used to set type information of the target location,
17004 that's being specified symbolically. We have to presume
17005 the user knows what they are doing. */
17009 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17011 symbol
= symbol_find_or_make (name
);
17012 S_SET_SEGMENT (symbol
, absolute_section
);
17013 symbol_set_frag (symbol
, &zero_address_frag
);
17014 S_SET_VALUE (symbol
, exp
->X_add_number
);
17015 exp
->X_op
= O_symbol
;
17016 exp
->X_add_symbol
= symbol
;
17017 exp
->X_add_number
= 0;
17023 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17024 (enum bfd_reloc_code_real
) reloc
);
17028 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17029 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17033 /* Mark whether the fix is to a THUMB instruction, or an ARM
17035 new_fix
->tc_fix_data
= thumb_mode
;
17038 /* Create a frg for an instruction requiring relaxation. */
17040 output_relax_insn (void)
17046 /* The size of the instruction is unknown, so tie the debug info to the
17047 start of the instruction. */
17048 dwarf2_emit_insn (0);
17050 switch (inst
.reloc
.exp
.X_op
)
17053 sym
= inst
.reloc
.exp
.X_add_symbol
;
17054 offset
= inst
.reloc
.exp
.X_add_number
;
17058 offset
= inst
.reloc
.exp
.X_add_number
;
17061 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17065 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17066 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17067 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17070 /* Write a 32-bit thumb instruction to buf. */
17072 put_thumb32_insn (char * buf
, unsigned long insn
)
17074 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17075 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17079 output_inst (const char * str
)
17085 as_bad ("%s -- `%s'", inst
.error
, str
);
17090 output_relax_insn ();
17093 if (inst
.size
== 0)
17096 to
= frag_more (inst
.size
);
17097 /* PR 9814: Record the thumb mode into the current frag so that we know
17098 what type of NOP padding to use, if necessary. We override any previous
17099 setting so that if the mode has changed then the NOPS that we use will
17100 match the encoding of the last instruction in the frag. */
17101 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17103 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17105 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17106 put_thumb32_insn (to
, inst
.instruction
);
17108 else if (inst
.size
> INSN_SIZE
)
17110 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17111 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17112 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17115 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17117 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17118 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17119 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17122 dwarf2_emit_insn (inst
.size
);
17126 output_it_inst (int cond
, int mask
, char * to
)
17128 unsigned long instruction
= 0xbf00;
17131 instruction
|= mask
;
17132 instruction
|= cond
<< 4;
17136 to
= frag_more (2);
17138 dwarf2_emit_insn (2);
17142 md_number_to_chars (to
, instruction
, 2);
17147 /* Tag values used in struct asm_opcode's tag field. */
17150 OT_unconditional
, /* Instruction cannot be conditionalized.
17151 The ARM condition field is still 0xE. */
17152 OT_unconditionalF
, /* Instruction cannot be conditionalized
17153 and carries 0xF in its ARM condition field. */
17154 OT_csuffix
, /* Instruction takes a conditional suffix. */
17155 OT_csuffixF
, /* Some forms of the instruction take a conditional
17156 suffix, others place 0xF where the condition field
17158 OT_cinfix3
, /* Instruction takes a conditional infix,
17159 beginning at character index 3. (In
17160 unified mode, it becomes a suffix.) */
17161 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17162 tsts, cmps, cmns, and teqs. */
17163 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17164 character index 3, even in unified mode. Used for
17165 legacy instructions where suffix and infix forms
17166 may be ambiguous. */
17167 OT_csuf_or_in3
, /* Instruction takes either a conditional
17168 suffix or an infix at character index 3. */
17169 OT_odd_infix_unc
, /* This is the unconditional variant of an
17170 instruction that takes a conditional infix
17171 at an unusual position. In unified mode,
17172 this variant will accept a suffix. */
17173 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17174 are the conditional variants of instructions that
17175 take conditional infixes in unusual positions.
17176 The infix appears at character index
17177 (tag - OT_odd_infix_0). These are not accepted
17178 in unified mode. */
17181 /* Subroutine of md_assemble, responsible for looking up the primary
17182 opcode from the mnemonic the user wrote. STR points to the
17183 beginning of the mnemonic.
17185 This is not simply a hash table lookup, because of conditional
17186 variants. Most instructions have conditional variants, which are
17187 expressed with a _conditional affix_ to the mnemonic. If we were
17188 to encode each conditional variant as a literal string in the opcode
17189 table, it would have approximately 20,000 entries.
17191 Most mnemonics take this affix as a suffix, and in unified syntax,
17192 'most' is upgraded to 'all'. However, in the divided syntax, some
17193 instructions take the affix as an infix, notably the s-variants of
17194 the arithmetic instructions. Of those instructions, all but six
17195 have the infix appear after the third character of the mnemonic.
17197 Accordingly, the algorithm for looking up primary opcodes given
17200 1. Look up the identifier in the opcode table.
17201 If we find a match, go to step U.
17203 2. Look up the last two characters of the identifier in the
17204 conditions table. If we find a match, look up the first N-2
17205 characters of the identifier in the opcode table. If we
17206 find a match, go to step CE.
17208 3. Look up the fourth and fifth characters of the identifier in
17209 the conditions table. If we find a match, extract those
17210 characters from the identifier, and look up the remaining
17211 characters in the opcode table. If we find a match, go
17216 U. Examine the tag field of the opcode structure, in case this is
17217 one of the six instructions with its conditional infix in an
17218 unusual place. If it is, the tag tells us where to find the
17219 infix; look it up in the conditions table and set inst.cond
17220 accordingly. Otherwise, this is an unconditional instruction.
17221 Again set inst.cond accordingly. Return the opcode structure.
17223 CE. Examine the tag field to make sure this is an instruction that
17224 should receive a conditional suffix. If it is not, fail.
17225 Otherwise, set inst.cond from the suffix we already looked up,
17226 and return the opcode structure.
17228 CM. Examine the tag field to make sure this is an instruction that
17229 should receive a conditional infix after the third character.
17230 If it is not, fail. Otherwise, undo the edits to the current
17231 line of input and proceed as for case CE. */
17233 static const struct asm_opcode
*
17234 opcode_lookup (char **str
)
17238 const struct asm_opcode
*opcode
;
17239 const struct asm_cond
*cond
;
17242 /* Scan up to the end of the mnemonic, which must end in white space,
17243 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17244 for (base
= end
= *str
; *end
!= '\0'; end
++)
17245 if (*end
== ' ' || *end
== '.')
17251 /* Handle a possible width suffix and/or Neon type suffix. */
17256 /* The .w and .n suffixes are only valid if the unified syntax is in
17258 if (unified_syntax
&& end
[1] == 'w')
17260 else if (unified_syntax
&& end
[1] == 'n')
17265 inst
.vectype
.elems
= 0;
17267 *str
= end
+ offset
;
17269 if (end
[offset
] == '.')
17271 /* See if we have a Neon type suffix (possible in either unified or
17272 non-unified ARM syntax mode). */
17273 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17276 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17282 /* Look for unaffixed or special-case affixed mnemonic. */
17283 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17288 if (opcode
->tag
< OT_odd_infix_0
)
17290 inst
.cond
= COND_ALWAYS
;
17294 if (warn_on_deprecated
&& unified_syntax
)
17295 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17296 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17297 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17300 inst
.cond
= cond
->value
;
17304 /* Cannot have a conditional suffix on a mnemonic of less than two
17306 if (end
- base
< 3)
17309 /* Look for suffixed mnemonic. */
17311 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17312 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17314 if (opcode
&& cond
)
17317 switch (opcode
->tag
)
17319 case OT_cinfix3_legacy
:
17320 /* Ignore conditional suffixes matched on infix only mnemonics. */
17324 case OT_cinfix3_deprecated
:
17325 case OT_odd_infix_unc
:
17326 if (!unified_syntax
)
17328 /* else fall through */
17332 case OT_csuf_or_in3
:
17333 inst
.cond
= cond
->value
;
17336 case OT_unconditional
:
17337 case OT_unconditionalF
:
17339 inst
.cond
= cond
->value
;
17342 /* Delayed diagnostic. */
17343 inst
.error
= BAD_COND
;
17344 inst
.cond
= COND_ALWAYS
;
17353 /* Cannot have a usual-position infix on a mnemonic of less than
17354 six characters (five would be a suffix). */
17355 if (end
- base
< 6)
17358 /* Look for infixed mnemonic in the usual position. */
17360 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17364 memcpy (save
, affix
, 2);
17365 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17366 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17368 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17369 memcpy (affix
, save
, 2);
17372 && (opcode
->tag
== OT_cinfix3
17373 || opcode
->tag
== OT_cinfix3_deprecated
17374 || opcode
->tag
== OT_csuf_or_in3
17375 || opcode
->tag
== OT_cinfix3_legacy
))
17378 if (warn_on_deprecated
&& unified_syntax
17379 && (opcode
->tag
== OT_cinfix3
17380 || opcode
->tag
== OT_cinfix3_deprecated
))
17381 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17383 inst
.cond
= cond
->value
;
17390 /* This function generates an initial IT instruction, leaving its block
17391 virtually open for the new instructions. Eventually,
17392 the mask will be updated by now_it_add_mask () each time
17393 a new instruction needs to be included in the IT block.
17394 Finally, the block is closed with close_automatic_it_block ().
17395 The block closure can be requested either from md_assemble (),
17396 a tencode (), or due to a label hook. */
17399 new_automatic_it_block (int cond
)
17401 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17402 now_it
.mask
= 0x18;
17404 now_it
.block_length
= 1;
17405 mapping_state (MAP_THUMB
);
17406 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17407 now_it
.warn_deprecated
= FALSE
;
17408 now_it
.insn_cond
= TRUE
;
17411 /* Close an automatic IT block.
17412 See comments in new_automatic_it_block (). */
17415 close_automatic_it_block (void)
17417 now_it
.mask
= 0x10;
17418 now_it
.block_length
= 0;
17421 /* Update the mask of the current automatically-generated IT
17422 instruction. See comments in new_automatic_it_block (). */
17425 now_it_add_mask (int cond
)
17427 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17428 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17429 | ((bitvalue) << (nbit)))
17430 const int resulting_bit
= (cond
& 1);
17432 now_it
.mask
&= 0xf;
17433 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17435 (5 - now_it
.block_length
));
17436 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17438 ((5 - now_it
.block_length
) - 1) );
17439 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17442 #undef SET_BIT_VALUE
17445 /* The IT blocks handling machinery is accessed through the these functions:
17446 it_fsm_pre_encode () from md_assemble ()
17447 set_it_insn_type () optional, from the tencode functions
17448 set_it_insn_type_last () ditto
17449 in_it_block () ditto
17450 it_fsm_post_encode () from md_assemble ()
17451 force_automatic_it_block_close () from label habdling functions
17454 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17455 initializing the IT insn type with a generic initial value depending
17456 on the inst.condition.
17457 2) During the tencode function, two things may happen:
17458 a) The tencode function overrides the IT insn type by
17459 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17460 b) The tencode function queries the IT block state by
17461 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17463 Both set_it_insn_type and in_it_block run the internal FSM state
17464 handling function (handle_it_state), because: a) setting the IT insn
17465 type may incur in an invalid state (exiting the function),
17466 and b) querying the state requires the FSM to be updated.
17467 Specifically we want to avoid creating an IT block for conditional
17468 branches, so it_fsm_pre_encode is actually a guess and we can't
17469 determine whether an IT block is required until the tencode () routine
17470 has decided what type of instruction this actually it.
17471 Because of this, if set_it_insn_type and in_it_block have to be used,
17472 set_it_insn_type has to be called first.
17474 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17475 determines the insn IT type depending on the inst.cond code.
17476 When a tencode () routine encodes an instruction that can be
17477 either outside an IT block, or, in the case of being inside, has to be
17478 the last one, set_it_insn_type_last () will determine the proper
17479 IT instruction type based on the inst.cond code. Otherwise,
17480 set_it_insn_type can be called for overriding that logic or
17481 for covering other cases.
17483 Calling handle_it_state () may not transition the IT block state to
17484 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17485 still queried. Instead, if the FSM determines that the state should
17486 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17487 after the tencode () function: that's what it_fsm_post_encode () does.
17489 Since in_it_block () calls the state handling function to get an
17490 updated state, an error may occur (due to invalid insns combination).
17491 In that case, inst.error is set.
17492 Therefore, inst.error has to be checked after the execution of
17493 the tencode () routine.
17495 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17496 any pending state change (if any) that didn't take place in
17497 handle_it_state () as explained above. */
17500 it_fsm_pre_encode (void)
17502 if (inst
.cond
!= COND_ALWAYS
)
17503 inst
.it_insn_type
= INSIDE_IT_INSN
;
17505 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17507 now_it
.state_handled
= 0;
17510 /* IT state FSM handling function. */
17513 handle_it_state (void)
17515 now_it
.state_handled
= 1;
17516 now_it
.insn_cond
= FALSE
;
17518 switch (now_it
.state
)
17520 case OUTSIDE_IT_BLOCK
:
17521 switch (inst
.it_insn_type
)
17523 case OUTSIDE_IT_INSN
:
17526 case INSIDE_IT_INSN
:
17527 case INSIDE_IT_LAST_INSN
:
17528 if (thumb_mode
== 0)
17531 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17532 as_tsktsk (_("Warning: conditional outside an IT block"\
17537 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17538 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17540 /* Automatically generate the IT instruction. */
17541 new_automatic_it_block (inst
.cond
);
17542 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17543 close_automatic_it_block ();
17547 inst
.error
= BAD_OUT_IT
;
17553 case IF_INSIDE_IT_LAST_INSN
:
17554 case NEUTRAL_IT_INSN
:
17558 now_it
.state
= MANUAL_IT_BLOCK
;
17559 now_it
.block_length
= 0;
17564 case AUTOMATIC_IT_BLOCK
:
17565 /* Three things may happen now:
17566 a) We should increment current it block size;
17567 b) We should close current it block (closing insn or 4 insns);
17568 c) We should close current it block and start a new one (due
17569 to incompatible conditions or
17570 4 insns-length block reached). */
17572 switch (inst
.it_insn_type
)
17574 case OUTSIDE_IT_INSN
:
17575 /* The closure of the block shall happen immediatelly,
17576 so any in_it_block () call reports the block as closed. */
17577 force_automatic_it_block_close ();
17580 case INSIDE_IT_INSN
:
17581 case INSIDE_IT_LAST_INSN
:
17582 case IF_INSIDE_IT_LAST_INSN
:
17583 now_it
.block_length
++;
17585 if (now_it
.block_length
> 4
17586 || !now_it_compatible (inst
.cond
))
17588 force_automatic_it_block_close ();
17589 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17590 new_automatic_it_block (inst
.cond
);
17594 now_it
.insn_cond
= TRUE
;
17595 now_it_add_mask (inst
.cond
);
17598 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17599 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17600 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17601 close_automatic_it_block ();
17604 case NEUTRAL_IT_INSN
:
17605 now_it
.block_length
++;
17606 now_it
.insn_cond
= TRUE
;
17608 if (now_it
.block_length
> 4)
17609 force_automatic_it_block_close ();
17611 now_it_add_mask (now_it
.cc
& 1);
17615 close_automatic_it_block ();
17616 now_it
.state
= MANUAL_IT_BLOCK
;
17621 case MANUAL_IT_BLOCK
:
17623 /* Check conditional suffixes. */
17624 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17627 now_it
.mask
&= 0x1f;
17628 is_last
= (now_it
.mask
== 0x10);
17629 now_it
.insn_cond
= TRUE
;
17631 switch (inst
.it_insn_type
)
17633 case OUTSIDE_IT_INSN
:
17634 inst
.error
= BAD_NOT_IT
;
17637 case INSIDE_IT_INSN
:
17638 if (cond
!= inst
.cond
)
17640 inst
.error
= BAD_IT_COND
;
17645 case INSIDE_IT_LAST_INSN
:
17646 case IF_INSIDE_IT_LAST_INSN
:
17647 if (cond
!= inst
.cond
)
17649 inst
.error
= BAD_IT_COND
;
17654 inst
.error
= BAD_BRANCH
;
17659 case NEUTRAL_IT_INSN
:
17660 /* The BKPT instruction is unconditional even in an IT block. */
17664 inst
.error
= BAD_IT_IT
;
17674 struct depr_insn_mask
17676 unsigned long pattern
;
17677 unsigned long mask
;
17678 const char* description
;
17681 /* List of 16-bit instruction patterns deprecated in an IT block in
17683 static const struct depr_insn_mask depr_it_insns
[] = {
17684 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17685 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17686 { 0xa000, 0xb800, N_("ADR") },
17687 { 0x4800, 0xf800, N_("Literal loads") },
17688 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17689 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17690 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17691 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17692 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17697 it_fsm_post_encode (void)
17701 if (!now_it
.state_handled
)
17702 handle_it_state ();
17704 if (now_it
.insn_cond
17705 && !now_it
.warn_deprecated
17706 && warn_on_deprecated
17707 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17709 if (inst
.instruction
>= 0x10000)
17711 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17712 "deprecated in ARMv8"));
17713 now_it
.warn_deprecated
= TRUE
;
17717 const struct depr_insn_mask
*p
= depr_it_insns
;
17719 while (p
->mask
!= 0)
17721 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17723 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17724 "of the following class are deprecated in ARMv8: "
17725 "%s"), p
->description
);
17726 now_it
.warn_deprecated
= TRUE
;
17734 if (now_it
.block_length
> 1)
17736 as_tsktsk (_("IT blocks containing more than one conditional "
17737 "instruction are deprecated in ARMv8"));
17738 now_it
.warn_deprecated
= TRUE
;
17742 is_last
= (now_it
.mask
== 0x10);
17745 now_it
.state
= OUTSIDE_IT_BLOCK
;
17751 force_automatic_it_block_close (void)
17753 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17755 close_automatic_it_block ();
17756 now_it
.state
= OUTSIDE_IT_BLOCK
;
17764 if (!now_it
.state_handled
)
17765 handle_it_state ();
17767 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17771 md_assemble (char *str
)
17774 const struct asm_opcode
* opcode
;
17776 /* Align the previous label if needed. */
17777 if (last_label_seen
!= NULL
)
17779 symbol_set_frag (last_label_seen
, frag_now
);
17780 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17781 S_SET_SEGMENT (last_label_seen
, now_seg
);
17784 memset (&inst
, '\0', sizeof (inst
));
17785 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17787 opcode
= opcode_lookup (&p
);
17790 /* It wasn't an instruction, but it might be a register alias of
17791 the form alias .req reg, or a Neon .dn/.qn directive. */
17792 if (! create_register_alias (str
, p
)
17793 && ! create_neon_reg_alias (str
, p
))
17794 as_bad (_("bad instruction `%s'"), str
);
17799 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17800 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17802 /* The value which unconditional instructions should have in place of the
17803 condition field. */
17804 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17808 arm_feature_set variant
;
17810 variant
= cpu_variant
;
17811 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17812 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17813 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17814 /* Check that this instruction is supported for this CPU. */
17815 if (!opcode
->tvariant
17816 || (thumb_mode
== 1
17817 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17819 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17822 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17823 && opcode
->tencode
!= do_t_branch
)
17825 as_bad (_("Thumb does not support conditional execution"));
17829 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17831 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17832 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17833 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17835 /* Two things are addressed here.
17836 1) Implicit require narrow instructions on Thumb-1.
17837 This avoids relaxation accidentally introducing Thumb-2
17839 2) Reject wide instructions in non Thumb-2 cores. */
17840 if (inst
.size_req
== 0)
17842 else if (inst
.size_req
== 4)
17844 as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str
);
17850 inst
.instruction
= opcode
->tvalue
;
17852 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17854 /* Prepare the it_insn_type for those encodings that don't set
17856 it_fsm_pre_encode ();
17858 opcode
->tencode ();
17860 it_fsm_post_encode ();
17863 if (!(inst
.error
|| inst
.relax
))
17865 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17866 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17867 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17869 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17874 /* Something has gone badly wrong if we try to relax a fixed size
17876 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17878 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17879 *opcode
->tvariant
);
17880 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17881 set those bits when Thumb-2 32-bit instructions are seen. ie.
17882 anything other than bl/blx and v6-M instructions.
17883 The impact of relaxable instructions will be considered later after we
17884 finish all relaxation. */
17885 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17886 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17887 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17888 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17891 check_neon_suffixes
;
17895 mapping_state (MAP_THUMB
);
17898 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17902 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17903 is_bx
= (opcode
->aencode
== do_bx
);
17905 /* Check that this instruction is supported for this CPU. */
17906 if (!(is_bx
&& fix_v4bx
)
17907 && !(opcode
->avariant
&&
17908 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17910 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17915 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17919 inst
.instruction
= opcode
->avalue
;
17920 if (opcode
->tag
== OT_unconditionalF
)
17921 inst
.instruction
|= 0xFU
<< 28;
17923 inst
.instruction
|= inst
.cond
<< 28;
17924 inst
.size
= INSN_SIZE
;
17925 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17927 it_fsm_pre_encode ();
17928 opcode
->aencode ();
17929 it_fsm_post_encode ();
17931 /* Arm mode bx is marked as both v4T and v5 because it's still required
17932 on a hypothetical non-thumb v5 core. */
17934 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17936 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17937 *opcode
->avariant
);
17939 check_neon_suffixes
;
17943 mapping_state (MAP_ARM
);
17948 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17956 check_it_blocks_finished (void)
17961 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17962 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17963 == MANUAL_IT_BLOCK
)
17965 as_warn (_("section '%s' finished with an open IT block."),
17969 if (now_it
.state
== MANUAL_IT_BLOCK
)
17970 as_warn (_("file finished with an open IT block."));
17974 /* Various frobbings of labels and their addresses. */
17977 arm_start_line_hook (void)
17979 last_label_seen
= NULL
;
17983 arm_frob_label (symbolS
* sym
)
17985 last_label_seen
= sym
;
17987 ARM_SET_THUMB (sym
, thumb_mode
);
17989 #if defined OBJ_COFF || defined OBJ_ELF
17990 ARM_SET_INTERWORK (sym
, support_interwork
);
17993 force_automatic_it_block_close ();
17995 /* Note - do not allow local symbols (.Lxxx) to be labelled
17996 as Thumb functions. This is because these labels, whilst
17997 they exist inside Thumb code, are not the entry points for
17998 possible ARM->Thumb calls. Also, these labels can be used
17999 as part of a computed goto or switch statement. eg gcc
18000 can generate code that looks like this:
18002 ldr r2, [pc, .Laaa]
18012 The first instruction loads the address of the jump table.
18013 The second instruction converts a table index into a byte offset.
18014 The third instruction gets the jump address out of the table.
18015 The fourth instruction performs the jump.
18017 If the address stored at .Laaa is that of a symbol which has the
18018 Thumb_Func bit set, then the linker will arrange for this address
18019 to have the bottom bit set, which in turn would mean that the
18020 address computation performed by the third instruction would end
18021 up with the bottom bit set. Since the ARM is capable of unaligned
18022 word loads, the instruction would then load the incorrect address
18023 out of the jump table, and chaos would ensue. */
18024 if (label_is_thumb_function_name
18025 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18026 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18028 /* When the address of a Thumb function is taken the bottom
18029 bit of that address should be set. This will allow
18030 interworking between Arm and Thumb functions to work
18033 THUMB_SET_FUNC (sym
, 1);
18035 label_is_thumb_function_name
= FALSE
;
18038 dwarf2_emit_label (sym
);
18042 arm_data_in_code (void)
18044 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18046 *input_line_pointer
= '/';
18047 input_line_pointer
+= 5;
18048 *input_line_pointer
= 0;
18056 arm_canonicalize_symbol_name (char * name
)
18060 if (thumb_mode
&& (len
= strlen (name
)) > 5
18061 && streq (name
+ len
- 5, "/data"))
18062 *(name
+ len
- 5) = 0;
18067 /* Table of all register names defined by default. The user can
18068 define additional names with .req. Note that all register names
18069 should appear in both upper and lowercase variants. Some registers
18070 also have mixed-case names. */
18072 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18073 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18074 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18075 #define REGSET(p,t) \
18076 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18077 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18078 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18079 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18080 #define REGSETH(p,t) \
18081 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18082 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18083 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18084 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18085 #define REGSET2(p,t) \
18086 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18087 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18088 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18089 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18090 #define SPLRBANK(base,bank,t) \
18091 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18092 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18093 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18094 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18095 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18096 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18098 static const struct reg_entry reg_names
[] =
18100 /* ARM integer registers. */
18101 REGSET(r
, RN
), REGSET(R
, RN
),
18103 /* ATPCS synonyms. */
18104 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18105 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18106 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18108 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18109 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18110 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18112 /* Well-known aliases. */
18113 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18114 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18116 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18117 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18119 /* Coprocessor numbers. */
18120 REGSET(p
, CP
), REGSET(P
, CP
),
18122 /* Coprocessor register numbers. The "cr" variants are for backward
18124 REGSET(c
, CN
), REGSET(C
, CN
),
18125 REGSET(cr
, CN
), REGSET(CR
, CN
),
18127 /* ARM banked registers. */
18128 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18129 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18130 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18131 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18132 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18133 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18134 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18136 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18137 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18138 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18139 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18140 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18141 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18142 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18143 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18145 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18146 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18147 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18148 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18149 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18150 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18151 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18152 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18153 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18155 /* FPA registers. */
18156 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18157 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18159 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18160 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18162 /* VFP SP registers. */
18163 REGSET(s
,VFS
), REGSET(S
,VFS
),
18164 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18166 /* VFP DP Registers. */
18167 REGSET(d
,VFD
), REGSET(D
,VFD
),
18168 /* Extra Neon DP registers. */
18169 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18171 /* Neon QP registers. */
18172 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18174 /* VFP control registers. */
18175 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18176 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18177 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18178 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18179 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18180 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18182 /* Maverick DSP coprocessor registers. */
18183 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18184 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18186 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18187 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18188 REGDEF(dspsc
,0,DSPSC
),
18190 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18191 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18192 REGDEF(DSPSC
,0,DSPSC
),
18194 /* iWMMXt data registers - p0, c0-15. */
18195 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18197 /* iWMMXt control registers - p1, c0-3. */
18198 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18199 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18200 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18201 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18203 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18204 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18205 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18206 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18207 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18209 /* XScale accumulator registers. */
18210 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18216 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18217 within psr_required_here. */
18218 static const struct asm_psr psrs
[] =
18220 /* Backward compatibility notation. Note that "all" is no longer
18221 truly all possible PSR bits. */
18222 {"all", PSR_c
| PSR_f
},
18226 /* Individual flags. */
18232 /* Combinations of flags. */
18233 {"fs", PSR_f
| PSR_s
},
18234 {"fx", PSR_f
| PSR_x
},
18235 {"fc", PSR_f
| PSR_c
},
18236 {"sf", PSR_s
| PSR_f
},
18237 {"sx", PSR_s
| PSR_x
},
18238 {"sc", PSR_s
| PSR_c
},
18239 {"xf", PSR_x
| PSR_f
},
18240 {"xs", PSR_x
| PSR_s
},
18241 {"xc", PSR_x
| PSR_c
},
18242 {"cf", PSR_c
| PSR_f
},
18243 {"cs", PSR_c
| PSR_s
},
18244 {"cx", PSR_c
| PSR_x
},
18245 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18246 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18247 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18248 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18249 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18250 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18251 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18252 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18253 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18254 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18255 {"scf", PSR_s
| PSR_c
| PSR_f
},
18256 {"scx", PSR_s
| PSR_c
| PSR_x
},
18257 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18258 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18259 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18260 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18261 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18262 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18263 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18264 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18265 {"csf", PSR_c
| PSR_s
| PSR_f
},
18266 {"csx", PSR_c
| PSR_s
| PSR_x
},
18267 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18268 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18269 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18270 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18271 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18272 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18273 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18274 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18275 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18276 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18277 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18278 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18279 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18280 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18281 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18282 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18283 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18284 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18285 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18286 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18287 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18288 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18289 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18290 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18291 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18292 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18295 /* Table of V7M psr names. */
18296 static const struct asm_psr v7m_psrs
[] =
18298 {"apsr", 0 }, {"APSR", 0 },
18299 {"iapsr", 1 }, {"IAPSR", 1 },
18300 {"eapsr", 2 }, {"EAPSR", 2 },
18301 {"psr", 3 }, {"PSR", 3 },
18302 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18303 {"ipsr", 5 }, {"IPSR", 5 },
18304 {"epsr", 6 }, {"EPSR", 6 },
18305 {"iepsr", 7 }, {"IEPSR", 7 },
18306 {"msp", 8 }, {"MSP", 8 },
18307 {"psp", 9 }, {"PSP", 9 },
18308 {"primask", 16}, {"PRIMASK", 16},
18309 {"basepri", 17}, {"BASEPRI", 17},
18310 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18311 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18312 {"faultmask", 19}, {"FAULTMASK", 19},
18313 {"control", 20}, {"CONTROL", 20}
18316 /* Table of all shift-in-operand names. */
18317 static const struct asm_shift_name shift_names
[] =
18319 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18320 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18321 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18322 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18323 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18324 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18327 /* Table of all explicit relocation names. */
18329 static struct reloc_entry reloc_names
[] =
18331 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18332 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18333 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18334 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18335 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18336 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18337 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18338 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18339 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18340 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18341 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18342 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18343 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18344 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18345 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18346 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18347 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18348 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18352 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18353 static const struct asm_cond conds
[] =
18357 {"cs", 0x2}, {"hs", 0x2},
18358 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18372 #define UL_BARRIER(L,U,CODE,FEAT) \
18373 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18374 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18376 static struct asm_barrier_opt barrier_opt_names
[] =
18378 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18379 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18380 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18381 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18382 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18383 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18384 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18385 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18386 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18387 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18388 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18389 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18390 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18391 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18392 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18393 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18398 /* Table of ARM-format instructions. */
18400 /* Macros for gluing together operand strings. N.B. In all cases
18401 other than OPS0, the trailing OP_stop comes from default
18402 zero-initialization of the unspecified elements of the array. */
18403 #define OPS0() { OP_stop, }
18404 #define OPS1(a) { OP_##a, }
18405 #define OPS2(a,b) { OP_##a,OP_##b, }
18406 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18407 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18408 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18409 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18411 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18412 This is useful when mixing operands for ARM and THUMB, i.e. using the
18413 MIX_ARM_THUMB_OPERANDS macro.
18414 In order to use these macros, prefix the number of operands with _
18416 #define OPS_1(a) { a, }
18417 #define OPS_2(a,b) { a,b, }
18418 #define OPS_3(a,b,c) { a,b,c, }
18419 #define OPS_4(a,b,c,d) { a,b,c,d, }
18420 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18421 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18423 /* These macros abstract out the exact format of the mnemonic table and
18424 save some repeated characters. */
18426 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18427 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18428 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18429 THUMB_VARIANT, do_##ae, do_##te }
18431 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18432 a T_MNEM_xyz enumerator. */
18433 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18434 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18435 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18436 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18438 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18439 infix after the third character. */
18440 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18441 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18442 THUMB_VARIANT, do_##ae, do_##te }
18443 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18444 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18445 THUMB_VARIANT, do_##ae, do_##te }
18446 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18447 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18448 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18449 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18450 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18451 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18452 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18453 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18455 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18456 field is still 0xE. Many of the Thumb variants can be executed
18457 conditionally, so this is checked separately. */
18458 #define TUE(mnem, op, top, nops, ops, ae, te) \
18459 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18460 THUMB_VARIANT, do_##ae, do_##te }
18462 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18463 Used by mnemonics that have very minimal differences in the encoding for
18464 ARM and Thumb variants and can be handled in a common function. */
18465 #define TUEc(mnem, op, top, nops, ops, en) \
18466 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18467 THUMB_VARIANT, do_##en, do_##en }
18469 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18470 condition code field. */
18471 #define TUF(mnem, op, top, nops, ops, ae, te) \
18472 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18473 THUMB_VARIANT, do_##ae, do_##te }
18475 /* ARM-only variants of all the above. */
18476 #define CE(mnem, op, nops, ops, ae) \
18477 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18479 #define C3(mnem, op, nops, ops, ae) \
18480 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18482 /* Legacy mnemonics that always have conditional infix after the third
18484 #define CL(mnem, op, nops, ops, ae) \
18485 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18486 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18488 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18489 #define cCE(mnem, op, nops, ops, ae) \
18490 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18492 /* Legacy coprocessor instructions where conditional infix and conditional
18493 suffix are ambiguous. For consistency this includes all FPA instructions,
18494 not just the potentially ambiguous ones. */
18495 #define cCL(mnem, op, nops, ops, ae) \
18496 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18497 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18499 /* Coprocessor, takes either a suffix or a position-3 infix
18500 (for an FPA corner case). */
18501 #define C3E(mnem, op, nops, ops, ae) \
18502 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18503 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18505 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18506 { m1 #m2 m3, OPS##nops ops, \
18507 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18508 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18510 #define CM(m1, m2, op, nops, ops, ae) \
18511 xCM_ (m1, , m2, op, nops, ops, ae), \
18512 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18513 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18514 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18515 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18516 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18517 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18518 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18519 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18520 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18521 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18522 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18523 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18524 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18525 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18526 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18527 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18528 xCM_ (m1, le, m2, op, nops, ops, ae), \
18529 xCM_ (m1, al, m2, op, nops, ops, ae)
18531 #define UE(mnem, op, nops, ops, ae) \
18532 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18534 #define UF(mnem, op, nops, ops, ae) \
18535 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18537 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18538 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18539 use the same encoding function for each. */
18540 #define NUF(mnem, op, nops, ops, enc) \
18541 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18542 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18544 /* Neon data processing, version which indirects through neon_enc_tab for
18545 the various overloaded versions of opcodes. */
18546 #define nUF(mnem, op, nops, ops, enc) \
18547 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18548 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18550 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18552 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18553 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18554 THUMB_VARIANT, do_##enc, do_##enc }
18556 #define NCE(mnem, op, nops, ops, enc) \
18557 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18559 #define NCEF(mnem, op, nops, ops, enc) \
18560 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18562 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18563 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18564 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18565 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18567 #define nCE(mnem, op, nops, ops, enc) \
18568 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18570 #define nCEF(mnem, op, nops, ops, enc) \
18571 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18575 static const struct asm_opcode insns
[] =
18577 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18578 #define THUMB_VARIANT & arm_ext_v4t
18579 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18580 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18581 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18582 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18583 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18584 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18585 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18586 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18587 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18588 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18589 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18590 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18591 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18592 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18593 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18594 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18596 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18597 for setting PSR flag bits. They are obsolete in V6 and do not
18598 have Thumb equivalents. */
18599 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18600 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18601 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18602 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18603 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18604 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18605 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18606 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18607 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18609 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18610 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18611 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18612 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18614 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18615 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18616 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18618 OP_ADDRGLDR
),ldst
, t_ldst
),
18619 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18621 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18622 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18623 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18624 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18625 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18626 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18628 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18629 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18630 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18631 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18634 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18635 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18636 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18637 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18639 /* Thumb-compatibility pseudo ops. */
18640 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18641 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18642 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18643 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18644 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18645 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18646 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18647 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18648 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18649 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18650 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18651 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18653 /* These may simplify to neg. */
18654 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18655 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18657 #undef THUMB_VARIANT
18658 #define THUMB_VARIANT & arm_ext_v6
18660 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18662 /* V1 instructions with no Thumb analogue prior to V6T2. */
18663 #undef THUMB_VARIANT
18664 #define THUMB_VARIANT & arm_ext_v6t2
18666 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18667 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18668 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18670 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18671 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18672 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18673 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18675 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18676 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18678 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18679 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18681 /* V1 instructions with no Thumb analogue at all. */
18682 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18683 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18685 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18686 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18687 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18688 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18689 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18690 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18691 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18692 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18695 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18696 #undef THUMB_VARIANT
18697 #define THUMB_VARIANT & arm_ext_v4t
18699 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18700 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18702 #undef THUMB_VARIANT
18703 #define THUMB_VARIANT & arm_ext_v6t2
18705 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18706 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18708 /* Generic coprocessor instructions. */
18709 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18710 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18711 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18712 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18713 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18714 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18715 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18718 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18720 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18721 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18724 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18725 #undef THUMB_VARIANT
18726 #define THUMB_VARIANT & arm_ext_msr
18728 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18729 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18732 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18733 #undef THUMB_VARIANT
18734 #define THUMB_VARIANT & arm_ext_v6t2
18736 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18737 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18738 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18739 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18740 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18741 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18742 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18743 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18746 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18747 #undef THUMB_VARIANT
18748 #define THUMB_VARIANT & arm_ext_v4t
18750 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18751 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18752 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18753 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18754 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18755 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18758 #define ARM_VARIANT & arm_ext_v4t_5
18760 /* ARM Architecture 4T. */
18761 /* Note: bx (and blx) are required on V5, even if the processor does
18762 not support Thumb. */
18763 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18766 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18767 #undef THUMB_VARIANT
18768 #define THUMB_VARIANT & arm_ext_v5t
18770 /* Note: blx has 2 variants; the .value coded here is for
18771 BLX(2). Only this variant has conditional execution. */
18772 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18773 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18775 #undef THUMB_VARIANT
18776 #define THUMB_VARIANT & arm_ext_v6t2
18778 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18779 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18780 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18781 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18782 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18783 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18784 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18785 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18788 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18789 #undef THUMB_VARIANT
18790 #define THUMB_VARIANT & arm_ext_v5exp
18792 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18793 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18794 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18795 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18797 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18798 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18800 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18801 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18802 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18803 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18805 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18806 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18807 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18808 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18810 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18811 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18813 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18814 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18815 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18816 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18819 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18820 #undef THUMB_VARIANT
18821 #define THUMB_VARIANT & arm_ext_v6t2
18823 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18824 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18826 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18827 ADDRGLDRS
), ldrd
, t_ldstd
),
18829 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18830 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18833 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18835 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18838 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18839 #undef THUMB_VARIANT
18840 #define THUMB_VARIANT & arm_ext_v6
18842 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18843 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18844 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18845 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18846 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18847 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18848 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18849 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18850 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18851 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18853 #undef THUMB_VARIANT
18854 #define THUMB_VARIANT & arm_ext_v6t2
18856 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18857 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18859 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18860 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18862 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18863 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18865 /* ARM V6 not included in V7M. */
18866 #undef THUMB_VARIANT
18867 #define THUMB_VARIANT & arm_ext_v6_notm
18868 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18869 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18870 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18871 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18872 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18873 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18874 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18875 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18876 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18877 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18878 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18879 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18880 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18881 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18882 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18883 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18884 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18885 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18886 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18888 /* ARM V6 not included in V7M (eg. integer SIMD). */
18889 #undef THUMB_VARIANT
18890 #define THUMB_VARIANT & arm_ext_v6_dsp
18891 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18892 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18893 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18894 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18895 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18896 /* Old name for QASX. */
18897 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18898 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18899 /* Old name for QSAX. */
18900 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18901 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18902 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18903 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18904 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18905 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18906 /* Old name for SASX. */
18907 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18908 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18909 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18910 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18911 /* Old name for SHASX. */
18912 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18913 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18914 /* Old name for SHSAX. */
18915 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18916 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18917 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18918 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18919 /* Old name for SSAX. */
18920 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18921 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18922 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18923 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18924 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18925 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18926 /* Old name for UASX. */
18927 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18928 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18929 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18930 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 /* Old name for UHASX. */
18932 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18933 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 /* Old name for UHSAX. */
18935 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18936 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18937 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18940 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18941 /* Old name for UQASX. */
18942 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18943 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18944 /* Old name for UQSAX. */
18945 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18948 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 /* Old name for USAX. */
18951 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18954 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18955 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18956 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18957 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18958 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18959 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18960 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18961 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18963 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18964 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18965 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18966 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18967 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18968 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18969 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18970 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18971 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18972 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18973 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18974 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18975 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18976 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18977 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18978 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18979 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18980 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18981 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18982 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18983 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18984 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18987 #define ARM_VARIANT & arm_ext_v6k
18988 #undef THUMB_VARIANT
18989 #define THUMB_VARIANT & arm_ext_v6k
18991 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18992 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18993 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18994 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18996 #undef THUMB_VARIANT
18997 #define THUMB_VARIANT & arm_ext_v6_notm
18998 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19000 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19001 RRnpcb
), strexd
, t_strexd
),
19003 #undef THUMB_VARIANT
19004 #define THUMB_VARIANT & arm_ext_v6t2
19005 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19007 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19009 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19011 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19013 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19016 #define ARM_VARIANT & arm_ext_sec
19017 #undef THUMB_VARIANT
19018 #define THUMB_VARIANT & arm_ext_sec
19020 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19023 #define ARM_VARIANT & arm_ext_virt
19024 #undef THUMB_VARIANT
19025 #define THUMB_VARIANT & arm_ext_virt
19027 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19028 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19031 #define ARM_VARIANT & arm_ext_pan
19032 #undef THUMB_VARIANT
19033 #define THUMB_VARIANT & arm_ext_pan
19035 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19038 #define ARM_VARIANT & arm_ext_v6t2
19039 #undef THUMB_VARIANT
19040 #define THUMB_VARIANT & arm_ext_v6t2
19042 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19043 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19044 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19045 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19047 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19048 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19049 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19050 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19052 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19053 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19054 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19055 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19057 /* Thumb-only instructions. */
19059 #define ARM_VARIANT NULL
19060 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19061 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19063 /* ARM does not really have an IT instruction, so always allow it.
19064 The opcode is copied from Thumb in order to allow warnings in
19065 -mimplicit-it=[never | arm] modes. */
19067 #define ARM_VARIANT & arm_ext_v1
19069 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19070 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19071 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19072 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19073 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19074 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19075 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19076 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19077 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19078 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19079 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19080 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19081 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19082 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19083 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19084 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19085 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19086 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19088 /* Thumb2 only instructions. */
19090 #define ARM_VARIANT NULL
19092 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19093 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19094 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19095 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19096 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19097 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19099 /* Hardware division instructions. */
19101 #define ARM_VARIANT & arm_ext_adiv
19102 #undef THUMB_VARIANT
19103 #define THUMB_VARIANT & arm_ext_div
19105 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19106 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19108 /* ARM V6M/V7 instructions. */
19110 #define ARM_VARIANT & arm_ext_barrier
19111 #undef THUMB_VARIANT
19112 #define THUMB_VARIANT & arm_ext_barrier
19114 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19115 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19116 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19118 /* ARM V7 instructions. */
19120 #define ARM_VARIANT & arm_ext_v7
19121 #undef THUMB_VARIANT
19122 #define THUMB_VARIANT & arm_ext_v7
19124 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19125 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19128 #define ARM_VARIANT & arm_ext_mp
19129 #undef THUMB_VARIANT
19130 #define THUMB_VARIANT & arm_ext_mp
19132 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19134 /* AArchv8 instructions. */
19136 #define ARM_VARIANT & arm_ext_v8
19137 #undef THUMB_VARIANT
19138 #define THUMB_VARIANT & arm_ext_v8
19140 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19141 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19142 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19143 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19145 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19146 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19147 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19149 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19151 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19153 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19155 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19156 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19157 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19158 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19159 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19160 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19162 /* ARMv8 T32 only. */
19164 #define ARM_VARIANT NULL
19165 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19166 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19167 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19169 /* FP for ARMv8. */
19171 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19172 #undef THUMB_VARIANT
19173 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19175 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19176 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19177 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19178 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19179 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19180 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19181 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19182 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19183 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19184 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19185 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19186 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19187 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19188 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19189 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19190 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19191 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19193 /* Crypto v1 extensions. */
19195 #define ARM_VARIANT & fpu_crypto_ext_armv8
19196 #undef THUMB_VARIANT
19197 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19199 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19200 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19201 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19202 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19203 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19204 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19205 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19206 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19207 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19208 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19209 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19210 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19211 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19212 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19215 #define ARM_VARIANT & crc_ext_armv8
19216 #undef THUMB_VARIANT
19217 #define THUMB_VARIANT & crc_ext_armv8
19218 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19219 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19220 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19221 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19222 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19223 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19226 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19227 #undef THUMB_VARIANT
19228 #define THUMB_VARIANT NULL
19230 cCE("wfs", e200110
, 1, (RR
), rd
),
19231 cCE("rfs", e300110
, 1, (RR
), rd
),
19232 cCE("wfc", e400110
, 1, (RR
), rd
),
19233 cCE("rfc", e500110
, 1, (RR
), rd
),
19235 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19236 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19237 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19238 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19240 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19241 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19242 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19243 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19245 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19246 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19247 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19248 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19249 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19250 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19251 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19252 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19253 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19254 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19267 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19454 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19455 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19456 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19457 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19458 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19459 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19460 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19461 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19462 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19463 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19464 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19466 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19467 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19468 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19469 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19470 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19471 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19472 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19473 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19474 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19475 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19476 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19477 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19479 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19480 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19481 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19484 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19623 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19624 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19625 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19627 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19628 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19629 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19630 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19631 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19632 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19633 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19634 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19635 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19636 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19637 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19638 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19640 /* The implementation of the FIX instruction is broken on some
19641 assemblers, in that it accepts a precision specifier as well as a
19642 rounding specifier, despite the fact that this is meaningless.
19643 To be more compatible, we accept it as well, though of course it
19644 does not set any bits. */
19645 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19646 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19647 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19648 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19649 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19650 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19651 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19652 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19653 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19654 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19655 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19656 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19657 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19659 /* Instructions that were new with the real FPA, call them V2. */
19661 #define ARM_VARIANT & fpu_fpa_ext_v2
19663 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19664 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19665 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19666 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19667 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19668 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19671 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19673 /* Moves and type conversions. */
19674 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19675 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19676 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19677 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19678 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19679 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19680 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19681 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19682 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19683 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19684 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19685 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19686 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19687 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19689 /* Memory operations. */
19690 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19691 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19692 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19693 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19694 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19695 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19696 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19697 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19698 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19699 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19700 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19701 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19702 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19703 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19704 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19705 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19706 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19707 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19709 /* Monadic operations. */
19710 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19711 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19712 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19714 /* Dyadic operations. */
19715 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19716 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19717 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19718 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19719 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19720 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19721 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19722 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19723 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19726 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19727 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19728 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19729 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19731 /* Double precision load/store are still present on single precision
19732 implementations. */
19733 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19734 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19735 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19736 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19737 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19738 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19739 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19740 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19741 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19742 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19745 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19747 /* Moves and type conversions. */
19748 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19749 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19750 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19751 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19752 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19753 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19754 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19755 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19756 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19757 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19758 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19759 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19760 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19762 /* Monadic operations. */
19763 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19764 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19765 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19767 /* Dyadic operations. */
19768 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19769 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19770 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19771 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19772 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19773 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19774 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19775 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19776 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19779 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19780 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19781 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19782 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19785 #define ARM_VARIANT & fpu_vfp_ext_v2
19787 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19788 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19789 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19790 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19792 /* Instructions which may belong to either the Neon or VFP instruction sets.
19793 Individual encoder functions perform additional architecture checks. */
19795 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19796 #undef THUMB_VARIANT
19797 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19799 /* These mnemonics are unique to VFP. */
19800 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19801 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19802 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19803 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19804 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19805 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19806 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19807 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19808 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19809 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19811 /* Mnemonics shared by Neon and VFP. */
19812 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19813 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19814 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19816 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19817 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19819 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19820 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19822 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19823 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19824 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19825 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19826 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19827 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19828 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19829 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19831 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19832 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19833 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19834 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19837 /* NOTE: All VMOV encoding is special-cased! */
19838 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19839 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19841 #undef THUMB_VARIANT
19842 #define THUMB_VARIANT & fpu_neon_ext_v1
19844 #define ARM_VARIANT & fpu_neon_ext_v1
19846 /* Data processing with three registers of the same length. */
19847 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19848 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19849 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19850 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19851 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19852 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19853 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19854 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19855 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19856 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19857 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19858 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19859 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19860 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19861 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19862 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19863 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19864 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19865 /* If not immediate, fall back to neon_dyadic_i64_su.
19866 shl_imm should accept I8 I16 I32 I64,
19867 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19868 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19869 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19870 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19871 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19872 /* Logic ops, types optional & ignored. */
19873 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19874 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19875 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19876 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19877 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19878 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19879 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19880 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19881 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19882 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19883 /* Bitfield ops, untyped. */
19884 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19885 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19886 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19887 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19888 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19889 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19890 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19891 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19892 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19893 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19894 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19895 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19896 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19897 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19898 back to neon_dyadic_if_su. */
19899 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19900 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19901 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19902 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19903 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19904 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19905 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19906 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19907 /* Comparison. Type I8 I16 I32 F32. */
19908 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19909 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19910 /* As above, D registers only. */
19911 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19912 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19913 /* Int and float variants, signedness unimportant. */
19914 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19915 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19916 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19917 /* Add/sub take types I8 I16 I32 I64 F32. */
19918 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19919 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19920 /* vtst takes sizes 8, 16, 32. */
19921 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19922 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19923 /* VMUL takes I8 I16 I32 F32 P8. */
19924 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19925 /* VQD{R}MULH takes S16 S32. */
19926 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19927 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19928 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19929 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19930 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19931 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19932 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19933 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19934 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19935 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19936 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19937 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19938 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19939 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19940 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19941 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19942 /* ARM v8.1 extension. */
19943 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19944 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19945 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19946 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19948 /* Two address, int/float. Types S8 S16 S32 F32. */
19949 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19950 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19952 /* Data processing with two registers and a shift amount. */
19953 /* Right shifts, and variants with rounding.
19954 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19955 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19956 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19957 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19958 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19959 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19960 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19961 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19962 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19963 /* Shift and insert. Sizes accepted 8 16 32 64. */
19964 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19965 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19966 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19967 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19968 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19969 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19970 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19971 /* Right shift immediate, saturating & narrowing, with rounding variants.
19972 Types accepted S16 S32 S64 U16 U32 U64. */
19973 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19974 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19975 /* As above, unsigned. Types accepted S16 S32 S64. */
19976 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19977 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19978 /* Right shift narrowing. Types accepted I16 I32 I64. */
19979 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19980 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19981 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19982 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19983 /* CVT with optional immediate for fixed-point variant. */
19984 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19986 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19987 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19989 /* Data processing, three registers of different lengths. */
19990 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19991 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19992 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19993 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19994 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19995 /* If not scalar, fall back to neon_dyadic_long.
19996 Vector types as above, scalar types S16 S32 U16 U32. */
19997 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19998 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19999 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20000 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20001 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20002 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20003 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20004 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20005 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20006 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20007 /* Saturating doubling multiplies. Types S16 S32. */
20008 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20009 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20010 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20011 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20012 S16 S32 U16 U32. */
20013 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20015 /* Extract. Size 8. */
20016 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20017 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20019 /* Two registers, miscellaneous. */
20020 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20021 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20022 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20023 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20024 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20025 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20026 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20027 /* Vector replicate. Sizes 8 16 32. */
20028 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20029 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20030 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20031 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20032 /* VMOVN. Types I16 I32 I64. */
20033 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20034 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20035 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20036 /* VQMOVUN. Types S16 S32 S64. */
20037 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20038 /* VZIP / VUZP. Sizes 8 16 32. */
20039 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20040 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20041 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20042 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20043 /* VQABS / VQNEG. Types S8 S16 S32. */
20044 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20045 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20046 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20047 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20048 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20049 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20050 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20051 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20052 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20053 /* Reciprocal estimates. Types U32 F32. */
20054 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20055 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20056 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20057 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20058 /* VCLS. Types S8 S16 S32. */
20059 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20060 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20061 /* VCLZ. Types I8 I16 I32. */
20062 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20063 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20064 /* VCNT. Size 8. */
20065 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20066 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20067 /* Two address, untyped. */
20068 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20069 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20070 /* VTRN. Sizes 8 16 32. */
20071 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20072 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20074 /* Table lookup. Size 8. */
20075 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20076 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20078 #undef THUMB_VARIANT
20079 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20081 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20083 /* Neon element/structure load/store. */
20084 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20085 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20086 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20087 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20088 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20089 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20090 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20091 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20093 #undef THUMB_VARIANT
20094 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20096 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20097 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20098 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20099 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20100 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20101 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20102 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20103 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20104 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20105 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20107 #undef THUMB_VARIANT
20108 #define THUMB_VARIANT & fpu_vfp_ext_v3
20110 #define ARM_VARIANT & fpu_vfp_ext_v3
20112 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20113 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20114 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20115 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20116 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20117 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20118 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20119 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20120 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20123 #define ARM_VARIANT & fpu_vfp_ext_fma
20124 #undef THUMB_VARIANT
20125 #define THUMB_VARIANT & fpu_vfp_ext_fma
20126 /* Mnemonics shared by Neon and VFP. These are included in the
20127 VFP FMA variant; NEON and VFP FMA always includes the NEON
20128 FMA instructions. */
20129 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20130 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20131 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20132 the v form should always be used. */
20133 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20134 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20135 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20136 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20137 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20138 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20140 #undef THUMB_VARIANT
20142 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20144 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20145 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20146 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20147 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20148 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20149 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20150 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20151 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20154 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20156 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20157 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20158 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20159 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20160 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20161 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20162 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20163 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20164 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20165 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20166 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20167 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20168 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20169 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20170 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20171 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20172 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20173 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20174 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20175 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20176 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20177 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20178 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20179 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20180 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20181 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20182 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20183 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20184 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20185 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20186 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20187 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20188 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20189 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20190 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20191 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20192 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20193 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20194 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20195 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20196 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20197 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20198 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20199 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20200 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20201 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20202 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20203 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20204 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20205 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20206 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20207 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20208 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20209 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20210 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20211 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20212 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20213 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20214 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20215 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20216 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20217 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20218 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20219 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20220 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20221 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20223 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20224 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20225 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20226 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20233 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20234 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20235 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20236 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20245 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20257 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20258 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20259 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20260 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20261 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20262 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20267 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20268 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20269 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20270 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20271 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20272 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20273 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20274 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20275 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20276 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20277 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20278 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20279 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20280 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20281 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20282 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20283 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20284 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20285 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20286 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20287 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20288 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20289 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20290 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20291 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20292 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20293 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20294 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20295 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20296 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20297 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20298 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20299 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20300 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20301 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20302 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20303 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20304 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20305 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20306 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20308 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20309 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20310 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20311 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20312 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20313 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20314 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20315 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20316 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20317 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20320 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20322 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20323 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20324 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20325 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20326 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20327 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20328 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20329 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20330 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20331 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20332 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20333 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20334 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20335 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20336 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20337 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20338 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20341 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20343 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20344 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20345 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20346 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20352 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20353 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20354 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20355 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20356 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20357 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20383 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20384 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20385 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20386 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20387 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20388 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20389 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20390 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20391 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20392 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20393 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20394 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20395 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20396 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20397 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20398 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20399 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20400 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20401 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20402 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20403 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20404 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20405 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20406 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20407 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20408 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20409 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20410 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20411 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20412 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20413 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20414 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20415 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20416 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20417 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20418 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20419 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20420 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20421 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20422 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20423 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20424 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20425 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20426 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20427 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20428 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20429 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20430 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20431 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20432 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20433 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20434 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20435 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20436 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20437 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20438 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20439 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20440 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20441 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20442 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20443 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20444 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20445 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20446 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20447 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20448 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20449 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20450 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20451 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20452 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20453 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20454 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20455 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20456 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20457 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20458 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20461 #undef THUMB_VARIANT
20487 /* MD interface: bits in the object file. */
20489 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20490 for use in the a.out file, and stores them in the array pointed to by buf.
20491 This knows about the endian-ness of the target machine and does
20492 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20493 2 (short) and 4 (long) Floating numbers are put out as a series of
20494 LITTLENUMS (shorts, here at least). */
20497 md_number_to_chars (char * buf
, valueT val
, int n
)
20499 if (target_big_endian
)
20500 number_to_chars_bigendian (buf
, val
, n
);
20502 number_to_chars_littleendian (buf
, val
, n
);
20506 md_chars_to_number (char * buf
, int n
)
20509 unsigned char * where
= (unsigned char *) buf
;
20511 if (target_big_endian
)
20516 result
|= (*where
++ & 255);
20524 result
|= (where
[n
] & 255);
20531 /* MD interface: Sections. */
20533 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20534 that an rs_machine_dependent frag may reach. */
20537 arm_frag_max_var (fragS
*fragp
)
20539 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20540 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20542 Note that we generate relaxable instructions even for cases that don't
20543 really need it, like an immediate that's a trivial constant. So we're
20544 overestimating the instruction size for some of those cases. Rather
20545 than putting more intelligence here, it would probably be better to
20546 avoid generating a relaxation frag in the first place when it can be
20547 determined up front that a short instruction will suffice. */
20549 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20553 /* Estimate the size of a frag before relaxing. Assume everything fits in
20557 md_estimate_size_before_relax (fragS
* fragp
,
20558 segT segtype ATTRIBUTE_UNUSED
)
20564 /* Convert a machine dependent frag. */
20567 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20569 unsigned long insn
;
20570 unsigned long old_op
;
20578 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20580 old_op
= bfd_get_16(abfd
, buf
);
20581 if (fragp
->fr_symbol
)
20583 exp
.X_op
= O_symbol
;
20584 exp
.X_add_symbol
= fragp
->fr_symbol
;
20588 exp
.X_op
= O_constant
;
20590 exp
.X_add_number
= fragp
->fr_offset
;
20591 opcode
= fragp
->fr_subtype
;
20594 case T_MNEM_ldr_pc
:
20595 case T_MNEM_ldr_pc2
:
20596 case T_MNEM_ldr_sp
:
20597 case T_MNEM_str_sp
:
20604 if (fragp
->fr_var
== 4)
20606 insn
= THUMB_OP32 (opcode
);
20607 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20609 insn
|= (old_op
& 0x700) << 4;
20613 insn
|= (old_op
& 7) << 12;
20614 insn
|= (old_op
& 0x38) << 13;
20616 insn
|= 0x00000c00;
20617 put_thumb32_insn (buf
, insn
);
20618 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20622 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20624 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20627 if (fragp
->fr_var
== 4)
20629 insn
= THUMB_OP32 (opcode
);
20630 insn
|= (old_op
& 0xf0) << 4;
20631 put_thumb32_insn (buf
, insn
);
20632 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20636 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20637 exp
.X_add_number
-= 4;
20645 if (fragp
->fr_var
== 4)
20647 int r0off
= (opcode
== T_MNEM_mov
20648 || opcode
== T_MNEM_movs
) ? 0 : 8;
20649 insn
= THUMB_OP32 (opcode
);
20650 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20651 insn
|= (old_op
& 0x700) << r0off
;
20652 put_thumb32_insn (buf
, insn
);
20653 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20657 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20662 if (fragp
->fr_var
== 4)
20664 insn
= THUMB_OP32(opcode
);
20665 put_thumb32_insn (buf
, insn
);
20666 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20669 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20673 if (fragp
->fr_var
== 4)
20675 insn
= THUMB_OP32(opcode
);
20676 insn
|= (old_op
& 0xf00) << 14;
20677 put_thumb32_insn (buf
, insn
);
20678 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20681 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20684 case T_MNEM_add_sp
:
20685 case T_MNEM_add_pc
:
20686 case T_MNEM_inc_sp
:
20687 case T_MNEM_dec_sp
:
20688 if (fragp
->fr_var
== 4)
20690 /* ??? Choose between add and addw. */
20691 insn
= THUMB_OP32 (opcode
);
20692 insn
|= (old_op
& 0xf0) << 4;
20693 put_thumb32_insn (buf
, insn
);
20694 if (opcode
== T_MNEM_add_pc
)
20695 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20697 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20700 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20708 if (fragp
->fr_var
== 4)
20710 insn
= THUMB_OP32 (opcode
);
20711 insn
|= (old_op
& 0xf0) << 4;
20712 insn
|= (old_op
& 0xf) << 16;
20713 put_thumb32_insn (buf
, insn
);
20714 if (insn
& (1 << 20))
20715 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20717 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20720 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20726 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20727 (enum bfd_reloc_code_real
) reloc_type
);
20728 fixp
->fx_file
= fragp
->fr_file
;
20729 fixp
->fx_line
= fragp
->fr_line
;
20730 fragp
->fr_fix
+= fragp
->fr_var
;
20732 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20733 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20734 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20735 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20738 /* Return the size of a relaxable immediate operand instruction.
20739 SHIFT and SIZE specify the form of the allowable immediate. */
20741 relax_immediate (fragS
*fragp
, int size
, int shift
)
20747 /* ??? Should be able to do better than this. */
20748 if (fragp
->fr_symbol
)
20751 low
= (1 << shift
) - 1;
20752 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20753 offset
= fragp
->fr_offset
;
20754 /* Force misaligned offsets to 32-bit variant. */
20757 if (offset
& ~mask
)
20762 /* Get the address of a symbol during relaxation. */
20764 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20770 sym
= fragp
->fr_symbol
;
20771 sym_frag
= symbol_get_frag (sym
);
20772 know (S_GET_SEGMENT (sym
) != absolute_section
20773 || sym_frag
== &zero_address_frag
);
20774 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20776 /* If frag has yet to be reached on this pass, assume it will
20777 move by STRETCH just as we did. If this is not so, it will
20778 be because some frag between grows, and that will force
20782 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20786 /* Adjust stretch for any alignment frag. Note that if have
20787 been expanding the earlier code, the symbol may be
20788 defined in what appears to be an earlier frag. FIXME:
20789 This doesn't handle the fr_subtype field, which specifies
20790 a maximum number of bytes to skip when doing an
20792 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20794 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20797 stretch
= - ((- stretch
)
20798 & ~ ((1 << (int) f
->fr_offset
) - 1));
20800 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20812 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20815 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20820 /* Assume worst case for symbols not known to be in the same section. */
20821 if (fragp
->fr_symbol
== NULL
20822 || !S_IS_DEFINED (fragp
->fr_symbol
)
20823 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20824 || S_IS_WEAK (fragp
->fr_symbol
))
20827 val
= relaxed_symbol_addr (fragp
, stretch
);
20828 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20829 addr
= (addr
+ 4) & ~3;
20830 /* Force misaligned targets to 32-bit variant. */
20834 if (val
< 0 || val
> 1020)
20839 /* Return the size of a relaxable add/sub immediate instruction. */
20841 relax_addsub (fragS
*fragp
, asection
*sec
)
20846 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20847 op
= bfd_get_16(sec
->owner
, buf
);
20848 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20849 return relax_immediate (fragp
, 8, 0);
20851 return relax_immediate (fragp
, 3, 0);
20854 /* Return TRUE iff the definition of symbol S could be pre-empted
20855 (overridden) at link or load time. */
20857 symbol_preemptible (symbolS
*s
)
20859 /* Weak symbols can always be pre-empted. */
20863 /* Non-global symbols cannot be pre-empted. */
20864 if (! S_IS_EXTERNAL (s
))
20868 /* In ELF, a global symbol can be marked protected, or private. In that
20869 case it can't be pre-empted (other definitions in the same link unit
20870 would violate the ODR). */
20871 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20875 /* Other global symbols might be pre-empted. */
20879 /* Return the size of a relaxable branch instruction. BITS is the
20880 size of the offset field in the narrow instruction. */
20883 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20889 /* Assume worst case for symbols not known to be in the same section. */
20890 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20891 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20892 || S_IS_WEAK (fragp
->fr_symbol
))
20896 /* A branch to a function in ARM state will require interworking. */
20897 if (S_IS_DEFINED (fragp
->fr_symbol
)
20898 && ARM_IS_FUNC (fragp
->fr_symbol
))
20902 if (symbol_preemptible (fragp
->fr_symbol
))
20905 val
= relaxed_symbol_addr (fragp
, stretch
);
20906 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20909 /* Offset is a signed value *2 */
20911 if (val
>= limit
|| val
< -limit
)
20917 /* Relax a machine dependent frag. This returns the amount by which
20918 the current size of the frag should change. */
20921 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20926 oldsize
= fragp
->fr_var
;
20927 switch (fragp
->fr_subtype
)
20929 case T_MNEM_ldr_pc2
:
20930 newsize
= relax_adr (fragp
, sec
, stretch
);
20932 case T_MNEM_ldr_pc
:
20933 case T_MNEM_ldr_sp
:
20934 case T_MNEM_str_sp
:
20935 newsize
= relax_immediate (fragp
, 8, 2);
20939 newsize
= relax_immediate (fragp
, 5, 2);
20943 newsize
= relax_immediate (fragp
, 5, 1);
20947 newsize
= relax_immediate (fragp
, 5, 0);
20950 newsize
= relax_adr (fragp
, sec
, stretch
);
20956 newsize
= relax_immediate (fragp
, 8, 0);
20959 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20962 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20964 case T_MNEM_add_sp
:
20965 case T_MNEM_add_pc
:
20966 newsize
= relax_immediate (fragp
, 8, 2);
20968 case T_MNEM_inc_sp
:
20969 case T_MNEM_dec_sp
:
20970 newsize
= relax_immediate (fragp
, 7, 2);
20976 newsize
= relax_addsub (fragp
, sec
);
20982 fragp
->fr_var
= newsize
;
20983 /* Freeze wide instructions that are at or before the same location as
20984 in the previous pass. This avoids infinite loops.
20985 Don't freeze them unconditionally because targets may be artificially
20986 misaligned by the expansion of preceding frags. */
20987 if (stretch
<= 0 && newsize
> 2)
20989 md_convert_frag (sec
->owner
, sec
, fragp
);
20993 return newsize
- oldsize
;
20996 /* Round up a section size to the appropriate boundary. */
20999 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21002 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21003 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21005 /* For a.out, force the section size to be aligned. If we don't do
21006 this, BFD will align it for us, but it will not write out the
21007 final bytes of the section. This may be a bug in BFD, but it is
21008 easier to fix it here since that is how the other a.out targets
21012 align
= bfd_get_section_alignment (stdoutput
, segment
);
21013 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21020 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21021 of an rs_align_code fragment. */
21024 arm_handle_align (fragS
* fragP
)
21026 static char const arm_noop
[2][2][4] =
21029 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21030 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21033 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21034 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21037 static char const thumb_noop
[2][2][2] =
21040 {0xc0, 0x46}, /* LE */
21041 {0x46, 0xc0}, /* BE */
21044 {0x00, 0xbf}, /* LE */
21045 {0xbf, 0x00} /* BE */
21048 static char const wide_thumb_noop
[2][4] =
21049 { /* Wide Thumb-2 */
21050 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21051 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21054 unsigned bytes
, fix
, noop_size
;
21057 const char *narrow_noop
= NULL
;
21062 if (fragP
->fr_type
!= rs_align_code
)
21065 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21066 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21069 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21070 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21072 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21074 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21076 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21077 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21079 narrow_noop
= thumb_noop
[1][target_big_endian
];
21080 noop
= wide_thumb_noop
[target_big_endian
];
21083 noop
= thumb_noop
[0][target_big_endian
];
21091 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21092 ? selected_cpu
: arm_arch_none
,
21094 [target_big_endian
];
21101 fragP
->fr_var
= noop_size
;
21103 if (bytes
& (noop_size
- 1))
21105 fix
= bytes
& (noop_size
- 1);
21107 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21109 memset (p
, 0, fix
);
21116 if (bytes
& noop_size
)
21118 /* Insert a narrow noop. */
21119 memcpy (p
, narrow_noop
, noop_size
);
21121 bytes
-= noop_size
;
21125 /* Use wide noops for the remainder */
21129 while (bytes
>= noop_size
)
21131 memcpy (p
, noop
, noop_size
);
21133 bytes
-= noop_size
;
21137 fragP
->fr_fix
+= fix
;
21140 /* Called from md_do_align. Used to create an alignment
21141 frag in a code section. */
21144 arm_frag_align_code (int n
, int max
)
21148 /* We assume that there will never be a requirement
21149 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21150 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21155 _("alignments greater than %d bytes not supported in .text sections."),
21156 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21157 as_fatal ("%s", err_msg
);
21160 p
= frag_var (rs_align_code
,
21161 MAX_MEM_FOR_RS_ALIGN_CODE
,
21163 (relax_substateT
) max
,
21170 /* Perform target specific initialisation of a frag.
21171 Note - despite the name this initialisation is not done when the frag
21172 is created, but only when its type is assigned. A frag can be created
21173 and used a long time before its type is set, so beware of assuming that
21174 this initialisationis performed first. */
21178 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21180 /* Record whether this frag is in an ARM or a THUMB area. */
21181 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21184 #else /* OBJ_ELF is defined. */
21186 arm_init_frag (fragS
* fragP
, int max_chars
)
21188 int frag_thumb_mode
;
21190 /* If the current ARM vs THUMB mode has not already
21191 been recorded into this frag then do so now. */
21192 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21193 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21195 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21197 /* Record a mapping symbol for alignment frags. We will delete this
21198 later if the alignment ends up empty. */
21199 switch (fragP
->fr_type
)
21202 case rs_align_test
:
21204 mapping_state_2 (MAP_DATA
, max_chars
);
21206 case rs_align_code
:
21207 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21214 /* When we change sections we need to issue a new mapping symbol. */
21217 arm_elf_change_section (void)
21219 /* Link an unlinked unwind index table section to the .text section. */
21220 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21221 && elf_linked_to_section (now_seg
) == NULL
)
21222 elf_linked_to_section (now_seg
) = text_section
;
21226 arm_elf_section_type (const char * str
, size_t len
)
21228 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21229 return SHT_ARM_EXIDX
;
21234 /* Code to deal with unwinding tables. */
21236 static void add_unwind_adjustsp (offsetT
);
21238 /* Generate any deferred unwind frame offset. */
21241 flush_pending_unwind (void)
21245 offset
= unwind
.pending_offset
;
21246 unwind
.pending_offset
= 0;
21248 add_unwind_adjustsp (offset
);
21251 /* Add an opcode to this list for this function. Two-byte opcodes should
21252 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21256 add_unwind_opcode (valueT op
, int length
)
21258 /* Add any deferred stack adjustment. */
21259 if (unwind
.pending_offset
)
21260 flush_pending_unwind ();
21262 unwind
.sp_restored
= 0;
21264 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21266 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21267 if (unwind
.opcodes
)
21268 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21269 unwind
.opcode_alloc
);
21271 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21276 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21278 unwind
.opcode_count
++;
21282 /* Add unwind opcodes to adjust the stack pointer. */
21285 add_unwind_adjustsp (offsetT offset
)
21289 if (offset
> 0x200)
21291 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21296 /* Long form: 0xb2, uleb128. */
21297 /* This might not fit in a word so add the individual bytes,
21298 remembering the list is built in reverse order. */
21299 o
= (valueT
) ((offset
- 0x204) >> 2);
21301 add_unwind_opcode (0, 1);
21303 /* Calculate the uleb128 encoding of the offset. */
21307 bytes
[n
] = o
& 0x7f;
21313 /* Add the insn. */
21315 add_unwind_opcode (bytes
[n
- 1], 1);
21316 add_unwind_opcode (0xb2, 1);
21318 else if (offset
> 0x100)
21320 /* Two short opcodes. */
21321 add_unwind_opcode (0x3f, 1);
21322 op
= (offset
- 0x104) >> 2;
21323 add_unwind_opcode (op
, 1);
21325 else if (offset
> 0)
21327 /* Short opcode. */
21328 op
= (offset
- 4) >> 2;
21329 add_unwind_opcode (op
, 1);
21331 else if (offset
< 0)
21334 while (offset
> 0x100)
21336 add_unwind_opcode (0x7f, 1);
21339 op
= ((offset
- 4) >> 2) | 0x40;
21340 add_unwind_opcode (op
, 1);
21344 /* Finish the list of unwind opcodes for this function. */
21346 finish_unwind_opcodes (void)
21350 if (unwind
.fp_used
)
21352 /* Adjust sp as necessary. */
21353 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21354 flush_pending_unwind ();
21356 /* After restoring sp from the frame pointer. */
21357 op
= 0x90 | unwind
.fp_reg
;
21358 add_unwind_opcode (op
, 1);
21361 flush_pending_unwind ();
21365 /* Start an exception table entry. If idx is nonzero this is an index table
21369 start_unwind_section (const segT text_seg
, int idx
)
21371 const char * text_name
;
21372 const char * prefix
;
21373 const char * prefix_once
;
21374 const char * group_name
;
21378 size_t sec_name_len
;
21385 prefix
= ELF_STRING_ARM_unwind
;
21386 prefix_once
= ELF_STRING_ARM_unwind_once
;
21387 type
= SHT_ARM_EXIDX
;
21391 prefix
= ELF_STRING_ARM_unwind_info
;
21392 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21393 type
= SHT_PROGBITS
;
21396 text_name
= segment_name (text_seg
);
21397 if (streq (text_name
, ".text"))
21400 if (strncmp (text_name
, ".gnu.linkonce.t.",
21401 strlen (".gnu.linkonce.t.")) == 0)
21403 prefix
= prefix_once
;
21404 text_name
+= strlen (".gnu.linkonce.t.");
21407 prefix_len
= strlen (prefix
);
21408 text_len
= strlen (text_name
);
21409 sec_name_len
= prefix_len
+ text_len
;
21410 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21411 memcpy (sec_name
, prefix
, prefix_len
);
21412 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21413 sec_name
[prefix_len
+ text_len
] = '\0';
21419 /* Handle COMDAT group. */
21420 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21422 group_name
= elf_group_name (text_seg
);
21423 if (group_name
== NULL
)
21425 as_bad (_("Group section `%s' has no group signature"),
21426 segment_name (text_seg
));
21427 ignore_rest_of_line ();
21430 flags
|= SHF_GROUP
;
21434 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21436 /* Set the section link for index tables. */
21438 elf_linked_to_section (now_seg
) = text_seg
;
21442 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21443 personality routine data. Returns zero, or the index table value for
21444 an inline entry. */
21447 create_unwind_entry (int have_data
)
21452 /* The current word of data. */
21454 /* The number of bytes left in this word. */
21457 finish_unwind_opcodes ();
21459 /* Remember the current text section. */
21460 unwind
.saved_seg
= now_seg
;
21461 unwind
.saved_subseg
= now_subseg
;
21463 start_unwind_section (now_seg
, 0);
21465 if (unwind
.personality_routine
== NULL
)
21467 if (unwind
.personality_index
== -2)
21470 as_bad (_("handlerdata in cantunwind frame"));
21471 return 1; /* EXIDX_CANTUNWIND. */
21474 /* Use a default personality routine if none is specified. */
21475 if (unwind
.personality_index
== -1)
21477 if (unwind
.opcode_count
> 3)
21478 unwind
.personality_index
= 1;
21480 unwind
.personality_index
= 0;
21483 /* Space for the personality routine entry. */
21484 if (unwind
.personality_index
== 0)
21486 if (unwind
.opcode_count
> 3)
21487 as_bad (_("too many unwind opcodes for personality routine 0"));
21491 /* All the data is inline in the index table. */
21494 while (unwind
.opcode_count
> 0)
21496 unwind
.opcode_count
--;
21497 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21501 /* Pad with "finish" opcodes. */
21503 data
= (data
<< 8) | 0xb0;
21510 /* We get two opcodes "free" in the first word. */
21511 size
= unwind
.opcode_count
- 2;
21515 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21516 if (unwind
.personality_index
!= -1)
21518 as_bad (_("attempt to recreate an unwind entry"));
21522 /* An extra byte is required for the opcode count. */
21523 size
= unwind
.opcode_count
+ 1;
21526 size
= (size
+ 3) >> 2;
21528 as_bad (_("too many unwind opcodes"));
21530 frag_align (2, 0, 0);
21531 record_alignment (now_seg
, 2);
21532 unwind
.table_entry
= expr_build_dot ();
21534 /* Allocate the table entry. */
21535 ptr
= frag_more ((size
<< 2) + 4);
21536 /* PR 13449: Zero the table entries in case some of them are not used. */
21537 memset (ptr
, 0, (size
<< 2) + 4);
21538 where
= frag_now_fix () - ((size
<< 2) + 4);
21540 switch (unwind
.personality_index
)
21543 /* ??? Should this be a PLT generating relocation? */
21544 /* Custom personality routine. */
21545 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21546 BFD_RELOC_ARM_PREL31
);
21551 /* Set the first byte to the number of additional words. */
21552 data
= size
> 0 ? size
- 1 : 0;
21556 /* ABI defined personality routines. */
21558 /* Three opcodes bytes are packed into the first word. */
21565 /* The size and first two opcode bytes go in the first word. */
21566 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21571 /* Should never happen. */
21575 /* Pack the opcodes into words (MSB first), reversing the list at the same
21577 while (unwind
.opcode_count
> 0)
21581 md_number_to_chars (ptr
, data
, 4);
21586 unwind
.opcode_count
--;
21588 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21591 /* Finish off the last word. */
21594 /* Pad with "finish" opcodes. */
21596 data
= (data
<< 8) | 0xb0;
21598 md_number_to_chars (ptr
, data
, 4);
21603 /* Add an empty descriptor if there is no user-specified data. */
21604 ptr
= frag_more (4);
21605 md_number_to_chars (ptr
, 0, 4);
21612 /* Initialize the DWARF-2 unwind information for this procedure. */
21615 tc_arm_frame_initial_instructions (void)
21617 cfi_add_CFA_def_cfa (REG_SP
, 0);
21619 #endif /* OBJ_ELF */
21621 /* Convert REGNAME to a DWARF-2 register number. */
21624 tc_arm_regname_to_dw2regnum (char *regname
)
21626 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21630 /* PR 16694: Allow VFP registers as well. */
21631 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21635 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21644 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21648 exp
.X_op
= O_secrel
;
21649 exp
.X_add_symbol
= symbol
;
21650 exp
.X_add_number
= 0;
21651 emit_expr (&exp
, size
);
21655 /* MD interface: Symbol and relocation handling. */
21657 /* Return the address within the segment that a PC-relative fixup is
21658 relative to. For ARM, PC-relative fixups applied to instructions
21659 are generally relative to the location of the fixup plus 8 bytes.
21660 Thumb branches are offset by 4, and Thumb loads relative to PC
21661 require special handling. */
21664 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21666 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21668 /* If this is pc-relative and we are going to emit a relocation
21669 then we just want to put out any pipeline compensation that the linker
21670 will need. Otherwise we want to use the calculated base.
21671 For WinCE we skip the bias for externals as well, since this
21672 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21674 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21675 || (arm_force_relocation (fixP
)
21677 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21683 switch (fixP
->fx_r_type
)
21685 /* PC relative addressing on the Thumb is slightly odd as the
21686 bottom two bits of the PC are forced to zero for the
21687 calculation. This happens *after* application of the
21688 pipeline offset. However, Thumb adrl already adjusts for
21689 this, so we need not do it again. */
21690 case BFD_RELOC_ARM_THUMB_ADD
:
21693 case BFD_RELOC_ARM_THUMB_OFFSET
:
21694 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21695 case BFD_RELOC_ARM_T32_ADD_PC12
:
21696 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21697 return (base
+ 4) & ~3;
21699 /* Thumb branches are simply offset by +4. */
21700 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21701 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21702 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21703 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21704 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21707 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21709 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21710 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21711 && ARM_IS_FUNC (fixP
->fx_addsy
)
21712 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21713 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21716 /* BLX is like branches above, but forces the low two bits of PC to
21718 case BFD_RELOC_THUMB_PCREL_BLX
:
21720 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21721 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21722 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21723 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21724 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21725 return (base
+ 4) & ~3;
21727 /* ARM mode branches are offset by +8. However, the Windows CE
21728 loader expects the relocation not to take this into account. */
21729 case BFD_RELOC_ARM_PCREL_BLX
:
21731 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21732 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21733 && ARM_IS_FUNC (fixP
->fx_addsy
)
21734 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21735 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21738 case BFD_RELOC_ARM_PCREL_CALL
:
21740 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21741 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21742 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21743 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21744 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21747 case BFD_RELOC_ARM_PCREL_BRANCH
:
21748 case BFD_RELOC_ARM_PCREL_JUMP
:
21749 case BFD_RELOC_ARM_PLT32
:
21751 /* When handling fixups immediately, because we have already
21752 discovered the value of a symbol, or the address of the frag involved
21753 we must account for the offset by +8, as the OS loader will never see the reloc.
21754 see fixup_segment() in write.c
21755 The S_IS_EXTERNAL test handles the case of global symbols.
21756 Those need the calculated base, not just the pipe compensation the linker will need. */
21758 && fixP
->fx_addsy
!= NULL
21759 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21760 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21768 /* ARM mode loads relative to PC are also offset by +8. Unlike
21769 branches, the Windows CE loader *does* expect the relocation
21770 to take this into account. */
21771 case BFD_RELOC_ARM_OFFSET_IMM
:
21772 case BFD_RELOC_ARM_OFFSET_IMM8
:
21773 case BFD_RELOC_ARM_HWLITERAL
:
21774 case BFD_RELOC_ARM_LITERAL
:
21775 case BFD_RELOC_ARM_CP_OFF_IMM
:
21779 /* Other PC-relative relocations are un-offset. */
21785 static bfd_boolean flag_warn_syms
= TRUE
;
21788 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21790 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21791 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21792 does mean that the resulting code might be very confusing to the reader.
21793 Also this warning can be triggered if the user omits an operand before
21794 an immediate address, eg:
21798 GAS treats this as an assignment of the value of the symbol foo to a
21799 symbol LDR, and so (without this code) it will not issue any kind of
21800 warning or error message.
21802 Note - ARM instructions are case-insensitive but the strings in the hash
21803 table are all stored in lower case, so we must first ensure that name is
21805 if (flag_warn_syms
&& arm_ops_hsh
)
21807 char * nbuf
= strdup (name
);
21810 for (p
= nbuf
; *p
; p
++)
21812 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21814 static struct hash_control
* already_warned
= NULL
;
21816 if (already_warned
== NULL
)
21817 already_warned
= hash_new ();
21818 /* Only warn about the symbol once. To keep the code
21819 simple we let hash_insert do the lookup for us. */
21820 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21821 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21830 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21831 Otherwise we have no need to default values of symbols. */
21834 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21837 if (name
[0] == '_' && name
[1] == 'G'
21838 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21842 if (symbol_find (name
))
21843 as_bad (_("GOT already in the symbol table"));
21845 GOT_symbol
= symbol_new (name
, undefined_section
,
21846 (valueT
) 0, & zero_address_frag
);
21856 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21857 computed as two separate immediate values, added together. We
21858 already know that this value cannot be computed by just one ARM
21861 static unsigned int
21862 validate_immediate_twopart (unsigned int val
,
21863 unsigned int * highpart
)
21868 for (i
= 0; i
< 32; i
+= 2)
21869 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21875 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21877 else if (a
& 0xff0000)
21879 if (a
& 0xff000000)
21881 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21885 gas_assert (a
& 0xff000000);
21886 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21889 return (a
& 0xff) | (i
<< 7);
21896 validate_offset_imm (unsigned int val
, int hwse
)
21898 if ((hwse
&& val
> 255) || val
> 4095)
21903 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21904 negative immediate constant by altering the instruction. A bit of
21909 by inverting the second operand, and
21912 by negating the second operand. */
21915 negate_data_op (unsigned long * instruction
,
21916 unsigned long value
)
21919 unsigned long negated
, inverted
;
21921 negated
= encode_arm_immediate (-value
);
21922 inverted
= encode_arm_immediate (~value
);
21924 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21927 /* First negates. */
21928 case OPCODE_SUB
: /* ADD <-> SUB */
21929 new_inst
= OPCODE_ADD
;
21934 new_inst
= OPCODE_SUB
;
21938 case OPCODE_CMP
: /* CMP <-> CMN */
21939 new_inst
= OPCODE_CMN
;
21944 new_inst
= OPCODE_CMP
;
21948 /* Now Inverted ops. */
21949 case OPCODE_MOV
: /* MOV <-> MVN */
21950 new_inst
= OPCODE_MVN
;
21955 new_inst
= OPCODE_MOV
;
21959 case OPCODE_AND
: /* AND <-> BIC */
21960 new_inst
= OPCODE_BIC
;
21965 new_inst
= OPCODE_AND
;
21969 case OPCODE_ADC
: /* ADC <-> SBC */
21970 new_inst
= OPCODE_SBC
;
21975 new_inst
= OPCODE_ADC
;
21979 /* We cannot do anything. */
21984 if (value
== (unsigned) FAIL
)
21987 *instruction
&= OPCODE_MASK
;
21988 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21992 /* Like negate_data_op, but for Thumb-2. */
21994 static unsigned int
21995 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21999 unsigned int negated
, inverted
;
22001 negated
= encode_thumb32_immediate (-value
);
22002 inverted
= encode_thumb32_immediate (~value
);
22004 rd
= (*instruction
>> 8) & 0xf;
22005 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22008 /* ADD <-> SUB. Includes CMP <-> CMN. */
22009 case T2_OPCODE_SUB
:
22010 new_inst
= T2_OPCODE_ADD
;
22014 case T2_OPCODE_ADD
:
22015 new_inst
= T2_OPCODE_SUB
;
22019 /* ORR <-> ORN. Includes MOV <-> MVN. */
22020 case T2_OPCODE_ORR
:
22021 new_inst
= T2_OPCODE_ORN
;
22025 case T2_OPCODE_ORN
:
22026 new_inst
= T2_OPCODE_ORR
;
22030 /* AND <-> BIC. TST has no inverted equivalent. */
22031 case T2_OPCODE_AND
:
22032 new_inst
= T2_OPCODE_BIC
;
22039 case T2_OPCODE_BIC
:
22040 new_inst
= T2_OPCODE_AND
;
22045 case T2_OPCODE_ADC
:
22046 new_inst
= T2_OPCODE_SBC
;
22050 case T2_OPCODE_SBC
:
22051 new_inst
= T2_OPCODE_ADC
;
22055 /* We cannot do anything. */
22060 if (value
== (unsigned int)FAIL
)
22063 *instruction
&= T2_OPCODE_MASK
;
22064 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22068 /* Read a 32-bit thumb instruction from buf. */
22069 static unsigned long
22070 get_thumb32_insn (char * buf
)
22072 unsigned long insn
;
22073 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22074 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22080 /* We usually want to set the low bit on the address of thumb function
22081 symbols. In particular .word foo - . should have the low bit set.
22082 Generic code tries to fold the difference of two symbols to
22083 a constant. Prevent this and force a relocation when the first symbols
22084 is a thumb function. */
22087 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22089 if (op
== O_subtract
22090 && l
->X_op
== O_symbol
22091 && r
->X_op
== O_symbol
22092 && THUMB_IS_FUNC (l
->X_add_symbol
))
22094 l
->X_op
= O_subtract
;
22095 l
->X_op_symbol
= r
->X_add_symbol
;
22096 l
->X_add_number
-= r
->X_add_number
;
22100 /* Process as normal. */
22104 /* Encode Thumb2 unconditional branches and calls. The encoding
22105 for the 2 are identical for the immediate values. */
22108 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22110 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22113 addressT S
, I1
, I2
, lo
, hi
;
22115 S
= (value
>> 24) & 0x01;
22116 I1
= (value
>> 23) & 0x01;
22117 I2
= (value
>> 22) & 0x01;
22118 hi
= (value
>> 12) & 0x3ff;
22119 lo
= (value
>> 1) & 0x7ff;
22120 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22121 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22122 newval
|= (S
<< 10) | hi
;
22123 newval2
&= ~T2I1I2MASK
;
22124 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22125 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22126 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22130 md_apply_fix (fixS
* fixP
,
22134 offsetT value
= * valP
;
22136 unsigned int newimm
;
22137 unsigned long temp
;
22139 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22141 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22143 /* Note whether this will delete the relocation. */
22145 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22148 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22149 consistency with the behaviour on 32-bit hosts. Remember value
22151 value
&= 0xffffffff;
22152 value
^= 0x80000000;
22153 value
-= 0x80000000;
22156 fixP
->fx_addnumber
= value
;
22158 /* Same treatment for fixP->fx_offset. */
22159 fixP
->fx_offset
&= 0xffffffff;
22160 fixP
->fx_offset
^= 0x80000000;
22161 fixP
->fx_offset
-= 0x80000000;
22163 switch (fixP
->fx_r_type
)
22165 case BFD_RELOC_NONE
:
22166 /* This will need to go in the object file. */
22170 case BFD_RELOC_ARM_IMMEDIATE
:
22171 /* We claim that this fixup has been processed here,
22172 even if in fact we generate an error because we do
22173 not have a reloc for it, so tc_gen_reloc will reject it. */
22176 if (fixP
->fx_addsy
)
22178 const char *msg
= 0;
22180 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22181 msg
= _("undefined symbol %s used as an immediate value");
22182 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22183 msg
= _("symbol %s is in a different section");
22184 else if (S_IS_WEAK (fixP
->fx_addsy
))
22185 msg
= _("symbol %s is weak and may be overridden later");
22189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22190 msg
, S_GET_NAME (fixP
->fx_addsy
));
22195 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22197 /* If the offset is negative, we should use encoding A2 for ADR. */
22198 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22199 newimm
= negate_data_op (&temp
, value
);
22202 newimm
= encode_arm_immediate (value
);
22204 /* If the instruction will fail, see if we can fix things up by
22205 changing the opcode. */
22206 if (newimm
== (unsigned int) FAIL
)
22207 newimm
= negate_data_op (&temp
, value
);
22210 if (newimm
== (unsigned int) FAIL
)
22212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22213 _("invalid constant (%lx) after fixup"),
22214 (unsigned long) value
);
22218 newimm
|= (temp
& 0xfffff000);
22219 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22222 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22224 unsigned int highpart
= 0;
22225 unsigned int newinsn
= 0xe1a00000; /* nop. */
22227 if (fixP
->fx_addsy
)
22229 const char *msg
= 0;
22231 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22232 msg
= _("undefined symbol %s used as an immediate value");
22233 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22234 msg
= _("symbol %s is in a different section");
22235 else if (S_IS_WEAK (fixP
->fx_addsy
))
22236 msg
= _("symbol %s is weak and may be overridden later");
22240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22241 msg
, S_GET_NAME (fixP
->fx_addsy
));
22246 newimm
= encode_arm_immediate (value
);
22247 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22249 /* If the instruction will fail, see if we can fix things up by
22250 changing the opcode. */
22251 if (newimm
== (unsigned int) FAIL
22252 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22254 /* No ? OK - try using two ADD instructions to generate
22256 newimm
= validate_immediate_twopart (value
, & highpart
);
22258 /* Yes - then make sure that the second instruction is
22260 if (newimm
!= (unsigned int) FAIL
)
22262 /* Still No ? Try using a negated value. */
22263 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22264 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22265 /* Otherwise - give up. */
22268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22269 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22274 /* Replace the first operand in the 2nd instruction (which
22275 is the PC) with the destination register. We have
22276 already added in the PC in the first instruction and we
22277 do not want to do it again. */
22278 newinsn
&= ~ 0xf0000;
22279 newinsn
|= ((newinsn
& 0x0f000) << 4);
22282 newimm
|= (temp
& 0xfffff000);
22283 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22285 highpart
|= (newinsn
& 0xfffff000);
22286 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22290 case BFD_RELOC_ARM_OFFSET_IMM
:
22291 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22294 case BFD_RELOC_ARM_LITERAL
:
22300 if (validate_offset_imm (value
, 0) == FAIL
)
22302 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22304 _("invalid literal constant: pool needs to be closer"));
22306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22307 _("bad immediate value for offset (%ld)"),
22312 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22314 newval
&= 0xfffff000;
22317 newval
&= 0xff7ff000;
22318 newval
|= value
| (sign
? INDEX_UP
: 0);
22320 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22323 case BFD_RELOC_ARM_OFFSET_IMM8
:
22324 case BFD_RELOC_ARM_HWLITERAL
:
22330 if (validate_offset_imm (value
, 1) == FAIL
)
22332 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22334 _("invalid literal constant: pool needs to be closer"));
22336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22337 _("bad immediate value for 8-bit offset (%ld)"),
22342 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22344 newval
&= 0xfffff0f0;
22347 newval
&= 0xff7ff0f0;
22348 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22350 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22353 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22354 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22356 _("bad immediate value for offset (%ld)"), (long) value
);
22359 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22361 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22364 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22365 /* This is a complicated relocation used for all varieties of Thumb32
22366 load/store instruction with immediate offset:
22368 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22369 *4, optional writeback(W)
22370 (doubleword load/store)
22372 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22373 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22374 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22375 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22376 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22378 Uppercase letters indicate bits that are already encoded at
22379 this point. Lowercase letters are our problem. For the
22380 second block of instructions, the secondary opcode nybble
22381 (bits 8..11) is present, and bit 23 is zero, even if this is
22382 a PC-relative operation. */
22383 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22385 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22387 if ((newval
& 0xf0000000) == 0xe0000000)
22389 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22391 newval
|= (1 << 23);
22394 if (value
% 4 != 0)
22396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22397 _("offset not a multiple of 4"));
22403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22404 _("offset out of range"));
22409 else if ((newval
& 0x000f0000) == 0x000f0000)
22411 /* PC-relative, 12-bit offset. */
22413 newval
|= (1 << 23);
22418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22419 _("offset out of range"));
22424 else if ((newval
& 0x00000100) == 0x00000100)
22426 /* Writeback: 8-bit, +/- offset. */
22428 newval
|= (1 << 9);
22433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22434 _("offset out of range"));
22439 else if ((newval
& 0x00000f00) == 0x00000e00)
22441 /* T-instruction: positive 8-bit offset. */
22442 if (value
< 0 || value
> 0xff)
22444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22445 _("offset out of range"));
22453 /* Positive 12-bit or negative 8-bit offset. */
22457 newval
|= (1 << 23);
22467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22468 _("offset out of range"));
22475 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22476 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22479 case BFD_RELOC_ARM_SHIFT_IMM
:
22480 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22481 if (((unsigned long) value
) > 32
22483 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22486 _("shift expression is too large"));
22491 /* Shifts of zero must be done as lsl. */
22493 else if (value
== 32)
22495 newval
&= 0xfffff07f;
22496 newval
|= (value
& 0x1f) << 7;
22497 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22500 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22501 case BFD_RELOC_ARM_T32_ADD_IMM
:
22502 case BFD_RELOC_ARM_T32_IMM12
:
22503 case BFD_RELOC_ARM_T32_ADD_PC12
:
22504 /* We claim that this fixup has been processed here,
22505 even if in fact we generate an error because we do
22506 not have a reloc for it, so tc_gen_reloc will reject it. */
22510 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22513 _("undefined symbol %s used as an immediate value"),
22514 S_GET_NAME (fixP
->fx_addsy
));
22518 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22520 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22523 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22524 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22526 newimm
= encode_thumb32_immediate (value
);
22527 if (newimm
== (unsigned int) FAIL
)
22528 newimm
= thumb32_negate_data_op (&newval
, value
);
22530 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22531 && newimm
== (unsigned int) FAIL
)
22533 /* Turn add/sum into addw/subw. */
22534 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22535 newval
= (newval
& 0xfeffffff) | 0x02000000;
22536 /* No flat 12-bit imm encoding for addsw/subsw. */
22537 if ((newval
& 0x00100000) == 0)
22539 /* 12 bit immediate for addw/subw. */
22543 newval
^= 0x00a00000;
22546 newimm
= (unsigned int) FAIL
;
22552 if (newimm
== (unsigned int)FAIL
)
22554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22555 _("invalid constant (%lx) after fixup"),
22556 (unsigned long) value
);
22560 newval
|= (newimm
& 0x800) << 15;
22561 newval
|= (newimm
& 0x700) << 4;
22562 newval
|= (newimm
& 0x0ff);
22564 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22565 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22568 case BFD_RELOC_ARM_SMC
:
22569 if (((unsigned long) value
) > 0xffff)
22570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22571 _("invalid smc expression"));
22572 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22573 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22574 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22577 case BFD_RELOC_ARM_HVC
:
22578 if (((unsigned long) value
) > 0xffff)
22579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22580 _("invalid hvc expression"));
22581 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22582 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22586 case BFD_RELOC_ARM_SWI
:
22587 if (fixP
->tc_fix_data
!= 0)
22589 if (((unsigned long) value
) > 0xff)
22590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22591 _("invalid swi expression"));
22592 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22594 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22598 if (((unsigned long) value
) > 0x00ffffff)
22599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22600 _("invalid swi expression"));
22601 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22603 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22607 case BFD_RELOC_ARM_MULTI
:
22608 if (((unsigned long) value
) > 0xffff)
22609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22610 _("invalid expression in load/store multiple"));
22611 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22612 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22616 case BFD_RELOC_ARM_PCREL_CALL
:
22618 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22620 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22621 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22622 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22623 /* Flip the bl to blx. This is a simple flip
22624 bit here because we generate PCREL_CALL for
22625 unconditional bls. */
22627 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22628 newval
= newval
| 0x10000000;
22629 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22635 goto arm_branch_common
;
22637 case BFD_RELOC_ARM_PCREL_JUMP
:
22638 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22640 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22641 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22642 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22644 /* This would map to a bl<cond>, b<cond>,
22645 b<always> to a Thumb function. We
22646 need to force a relocation for this particular
22648 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22652 case BFD_RELOC_ARM_PLT32
:
22654 case BFD_RELOC_ARM_PCREL_BRANCH
:
22656 goto arm_branch_common
;
22658 case BFD_RELOC_ARM_PCREL_BLX
:
22661 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22663 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22664 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22665 && ARM_IS_FUNC (fixP
->fx_addsy
))
22667 /* Flip the blx to a bl and warn. */
22668 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22669 newval
= 0xeb000000;
22670 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22671 _("blx to '%s' an ARM ISA state function changed to bl"),
22673 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22679 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22680 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22684 /* We are going to store value (shifted right by two) in the
22685 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22686 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22687 also be be clear. */
22689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22690 _("misaligned branch destination"));
22691 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22692 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22695 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22697 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22698 newval
|= (value
>> 2) & 0x00ffffff;
22699 /* Set the H bit on BLX instructions. */
22703 newval
|= 0x01000000;
22705 newval
&= ~0x01000000;
22707 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22711 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22712 /* CBZ can only branch forward. */
22714 /* Attempts to use CBZ to branch to the next instruction
22715 (which, strictly speaking, are prohibited) will be turned into
22718 FIXME: It may be better to remove the instruction completely and
22719 perform relaxation. */
22722 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22723 newval
= 0xbf00; /* NOP encoding T1 */
22724 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22731 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22733 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22734 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22735 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22740 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22741 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22744 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22746 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22747 newval
|= (value
& 0x1ff) >> 1;
22748 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22752 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22753 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22756 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22758 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22759 newval
|= (value
& 0xfff) >> 1;
22760 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22764 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22766 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22767 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22768 && ARM_IS_FUNC (fixP
->fx_addsy
)
22769 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22771 /* Force a relocation for a branch 20 bits wide. */
22774 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22776 _("conditional branch out of range"));
22778 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22781 addressT S
, J1
, J2
, lo
, hi
;
22783 S
= (value
& 0x00100000) >> 20;
22784 J2
= (value
& 0x00080000) >> 19;
22785 J1
= (value
& 0x00040000) >> 18;
22786 hi
= (value
& 0x0003f000) >> 12;
22787 lo
= (value
& 0x00000ffe) >> 1;
22789 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22790 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22791 newval
|= (S
<< 10) | hi
;
22792 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22793 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22794 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22798 case BFD_RELOC_THUMB_PCREL_BLX
:
22799 /* If there is a blx from a thumb state function to
22800 another thumb function flip this to a bl and warn
22804 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22805 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22806 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22808 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22809 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22810 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22812 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22813 newval
= newval
| 0x1000;
22814 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22815 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22820 goto thumb_bl_common
;
22822 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22823 /* A bl from Thumb state ISA to an internal ARM state function
22824 is converted to a blx. */
22826 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22827 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22828 && ARM_IS_FUNC (fixP
->fx_addsy
)
22829 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22831 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22832 newval
= newval
& ~0x1000;
22833 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22834 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22840 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22841 /* For a BLX instruction, make sure that the relocation is rounded up
22842 to a word boundary. This follows the semantics of the instruction
22843 which specifies that bit 1 of the target address will come from bit
22844 1 of the base address. */
22845 value
= (value
+ 3) & ~ 3;
22848 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22849 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22850 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22853 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22855 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22857 else if ((value
& ~0x1ffffff)
22858 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22860 _("Thumb2 branch out of range"));
22863 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22864 encode_thumb2_b_bl_offset (buf
, value
);
22868 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22869 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22873 encode_thumb2_b_bl_offset (buf
, value
);
22878 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22883 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22884 md_number_to_chars (buf
, value
, 2);
22888 case BFD_RELOC_ARM_TLS_CALL
:
22889 case BFD_RELOC_ARM_THM_TLS_CALL
:
22890 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22891 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22892 case BFD_RELOC_ARM_TLS_GOTDESC
:
22893 case BFD_RELOC_ARM_TLS_GD32
:
22894 case BFD_RELOC_ARM_TLS_LE32
:
22895 case BFD_RELOC_ARM_TLS_IE32
:
22896 case BFD_RELOC_ARM_TLS_LDM32
:
22897 case BFD_RELOC_ARM_TLS_LDO32
:
22898 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22901 case BFD_RELOC_ARM_GOT32
:
22902 case BFD_RELOC_ARM_GOTOFF
:
22905 case BFD_RELOC_ARM_GOT_PREL
:
22906 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22907 md_number_to_chars (buf
, value
, 4);
22910 case BFD_RELOC_ARM_TARGET2
:
22911 /* TARGET2 is not partial-inplace, so we need to write the
22912 addend here for REL targets, because it won't be written out
22913 during reloc processing later. */
22914 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22915 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22919 case BFD_RELOC_RVA
:
22921 case BFD_RELOC_ARM_TARGET1
:
22922 case BFD_RELOC_ARM_ROSEGREL32
:
22923 case BFD_RELOC_ARM_SBREL32
:
22924 case BFD_RELOC_32_PCREL
:
22926 case BFD_RELOC_32_SECREL
:
22928 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22930 /* For WinCE we only do this for pcrel fixups. */
22931 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22933 md_number_to_chars (buf
, value
, 4);
22937 case BFD_RELOC_ARM_PREL31
:
22938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22940 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22941 if ((value
^ (value
>> 1)) & 0x40000000)
22943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22944 _("rel31 relocation overflow"));
22946 newval
|= value
& 0x7fffffff;
22947 md_number_to_chars (buf
, newval
, 4);
22952 case BFD_RELOC_ARM_CP_OFF_IMM
:
22953 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22954 if (value
< -1023 || value
> 1023 || (value
& 3))
22955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22956 _("co-processor offset out of range"));
22961 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22962 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22963 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22965 newval
= get_thumb32_insn (buf
);
22967 newval
&= 0xffffff00;
22970 newval
&= 0xff7fff00;
22971 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22973 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22974 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22975 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22977 put_thumb32_insn (buf
, newval
);
22980 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22981 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22982 if (value
< -255 || value
> 255)
22983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22984 _("co-processor offset out of range"));
22986 goto cp_off_common
;
22988 case BFD_RELOC_ARM_THUMB_OFFSET
:
22989 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22990 /* Exactly what ranges, and where the offset is inserted depends
22991 on the type of instruction, we can establish this from the
22993 switch (newval
>> 12)
22995 case 4: /* PC load. */
22996 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22997 forced to zero for these loads; md_pcrel_from has already
22998 compensated for this. */
23000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23001 _("invalid offset, target not word aligned (0x%08lX)"),
23002 (((unsigned long) fixP
->fx_frag
->fr_address
23003 + (unsigned long) fixP
->fx_where
) & ~3)
23004 + (unsigned long) value
);
23006 if (value
& ~0x3fc)
23007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23008 _("invalid offset, value too big (0x%08lX)"),
23011 newval
|= value
>> 2;
23014 case 9: /* SP load/store. */
23015 if (value
& ~0x3fc)
23016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23017 _("invalid offset, value too big (0x%08lX)"),
23019 newval
|= value
>> 2;
23022 case 6: /* Word load/store. */
23024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23025 _("invalid offset, value too big (0x%08lX)"),
23027 newval
|= value
<< 4; /* 6 - 2. */
23030 case 7: /* Byte load/store. */
23032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23033 _("invalid offset, value too big (0x%08lX)"),
23035 newval
|= value
<< 6;
23038 case 8: /* Halfword load/store. */
23040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23041 _("invalid offset, value too big (0x%08lX)"),
23043 newval
|= value
<< 5; /* 6 - 1. */
23047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23048 "Unable to process relocation for thumb opcode: %lx",
23049 (unsigned long) newval
);
23052 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23055 case BFD_RELOC_ARM_THUMB_ADD
:
23056 /* This is a complicated relocation, since we use it for all of
23057 the following immediate relocations:
23061 9bit ADD/SUB SP word-aligned
23062 10bit ADD PC/SP word-aligned
23064 The type of instruction being processed is encoded in the
23071 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23073 int rd
= (newval
>> 4) & 0xf;
23074 int rs
= newval
& 0xf;
23075 int subtract
= !!(newval
& 0x8000);
23077 /* Check for HI regs, only very restricted cases allowed:
23078 Adjusting SP, and using PC or SP to get an address. */
23079 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23080 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23082 _("invalid Hi register with immediate"));
23084 /* If value is negative, choose the opposite instruction. */
23088 subtract
= !subtract
;
23090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23091 _("immediate value out of range"));
23096 if (value
& ~0x1fc)
23097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23098 _("invalid immediate for stack address calculation"));
23099 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23100 newval
|= value
>> 2;
23102 else if (rs
== REG_PC
|| rs
== REG_SP
)
23104 /* PR gas/18541. If the addition is for a defined symbol
23105 within range of an ADR instruction then accept it. */
23108 && fixP
->fx_addsy
!= NULL
)
23112 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23113 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23114 || S_IS_WEAK (fixP
->fx_addsy
))
23116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23117 _("address calculation needs a strongly defined nearby symbol"));
23121 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23123 /* Round up to the next 4-byte boundary. */
23128 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23133 _("symbol too far away"));
23143 if (subtract
|| value
& ~0x3fc)
23144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23145 _("invalid immediate for address calculation (value = 0x%08lX)"),
23146 (unsigned long) (subtract
? - value
: value
));
23147 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23149 newval
|= value
>> 2;
23154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23155 _("immediate value out of range"));
23156 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23157 newval
|= (rd
<< 8) | value
;
23162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23163 _("immediate value out of range"));
23164 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23165 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23168 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23171 case BFD_RELOC_ARM_THUMB_IMM
:
23172 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23173 if (value
< 0 || value
> 255)
23174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23175 _("invalid immediate: %ld is out of range"),
23178 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23181 case BFD_RELOC_ARM_THUMB_SHIFT
:
23182 /* 5bit shift value (0..32). LSL cannot take 32. */
23183 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23184 temp
= newval
& 0xf800;
23185 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23187 _("invalid shift value: %ld"), (long) value
);
23188 /* Shifts of zero must be encoded as LSL. */
23190 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23191 /* Shifts of 32 are encoded as zero. */
23192 else if (value
== 32)
23194 newval
|= value
<< 6;
23195 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23198 case BFD_RELOC_VTABLE_INHERIT
:
23199 case BFD_RELOC_VTABLE_ENTRY
:
23203 case BFD_RELOC_ARM_MOVW
:
23204 case BFD_RELOC_ARM_MOVT
:
23205 case BFD_RELOC_ARM_THUMB_MOVW
:
23206 case BFD_RELOC_ARM_THUMB_MOVT
:
23207 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23209 /* REL format relocations are limited to a 16-bit addend. */
23210 if (!fixP
->fx_done
)
23212 if (value
< -0x8000 || value
> 0x7fff)
23213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23214 _("offset out of range"));
23216 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23217 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23222 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23223 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23225 newval
= get_thumb32_insn (buf
);
23226 newval
&= 0xfbf08f00;
23227 newval
|= (value
& 0xf000) << 4;
23228 newval
|= (value
& 0x0800) << 15;
23229 newval
|= (value
& 0x0700) << 4;
23230 newval
|= (value
& 0x00ff);
23231 put_thumb32_insn (buf
, newval
);
23235 newval
= md_chars_to_number (buf
, 4);
23236 newval
&= 0xfff0f000;
23237 newval
|= value
& 0x0fff;
23238 newval
|= (value
& 0xf000) << 4;
23239 md_number_to_chars (buf
, newval
, 4);
23244 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23245 case BFD_RELOC_ARM_ALU_PC_G0
:
23246 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23247 case BFD_RELOC_ARM_ALU_PC_G1
:
23248 case BFD_RELOC_ARM_ALU_PC_G2
:
23249 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23250 case BFD_RELOC_ARM_ALU_SB_G0
:
23251 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23252 case BFD_RELOC_ARM_ALU_SB_G1
:
23253 case BFD_RELOC_ARM_ALU_SB_G2
:
23254 gas_assert (!fixP
->fx_done
);
23255 if (!seg
->use_rela_p
)
23258 bfd_vma encoded_addend
;
23259 bfd_vma addend_abs
= abs (value
);
23261 /* Check that the absolute value of the addend can be
23262 expressed as an 8-bit constant plus a rotation. */
23263 encoded_addend
= encode_arm_immediate (addend_abs
);
23264 if (encoded_addend
== (unsigned int) FAIL
)
23265 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23266 _("the offset 0x%08lX is not representable"),
23267 (unsigned long) addend_abs
);
23269 /* Extract the instruction. */
23270 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23272 /* If the addend is positive, use an ADD instruction.
23273 Otherwise use a SUB. Take care not to destroy the S bit. */
23274 insn
&= 0xff1fffff;
23280 /* Place the encoded addend into the first 12 bits of the
23282 insn
&= 0xfffff000;
23283 insn
|= encoded_addend
;
23285 /* Update the instruction. */
23286 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23290 case BFD_RELOC_ARM_LDR_PC_G0
:
23291 case BFD_RELOC_ARM_LDR_PC_G1
:
23292 case BFD_RELOC_ARM_LDR_PC_G2
:
23293 case BFD_RELOC_ARM_LDR_SB_G0
:
23294 case BFD_RELOC_ARM_LDR_SB_G1
:
23295 case BFD_RELOC_ARM_LDR_SB_G2
:
23296 gas_assert (!fixP
->fx_done
);
23297 if (!seg
->use_rela_p
)
23300 bfd_vma addend_abs
= abs (value
);
23302 /* Check that the absolute value of the addend can be
23303 encoded in 12 bits. */
23304 if (addend_abs
>= 0x1000)
23305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23306 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23307 (unsigned long) addend_abs
);
23309 /* Extract the instruction. */
23310 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23312 /* If the addend is negative, clear bit 23 of the instruction.
23313 Otherwise set it. */
23315 insn
&= ~(1 << 23);
23319 /* Place the absolute value of the addend into the first 12 bits
23320 of the instruction. */
23321 insn
&= 0xfffff000;
23322 insn
|= addend_abs
;
23324 /* Update the instruction. */
23325 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23329 case BFD_RELOC_ARM_LDRS_PC_G0
:
23330 case BFD_RELOC_ARM_LDRS_PC_G1
:
23331 case BFD_RELOC_ARM_LDRS_PC_G2
:
23332 case BFD_RELOC_ARM_LDRS_SB_G0
:
23333 case BFD_RELOC_ARM_LDRS_SB_G1
:
23334 case BFD_RELOC_ARM_LDRS_SB_G2
:
23335 gas_assert (!fixP
->fx_done
);
23336 if (!seg
->use_rela_p
)
23339 bfd_vma addend_abs
= abs (value
);
23341 /* Check that the absolute value of the addend can be
23342 encoded in 8 bits. */
23343 if (addend_abs
>= 0x100)
23344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23345 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23346 (unsigned long) addend_abs
);
23348 /* Extract the instruction. */
23349 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23351 /* If the addend is negative, clear bit 23 of the instruction.
23352 Otherwise set it. */
23354 insn
&= ~(1 << 23);
23358 /* Place the first four bits of the absolute value of the addend
23359 into the first 4 bits of the instruction, and the remaining
23360 four into bits 8 .. 11. */
23361 insn
&= 0xfffff0f0;
23362 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23364 /* Update the instruction. */
23365 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23369 case BFD_RELOC_ARM_LDC_PC_G0
:
23370 case BFD_RELOC_ARM_LDC_PC_G1
:
23371 case BFD_RELOC_ARM_LDC_PC_G2
:
23372 case BFD_RELOC_ARM_LDC_SB_G0
:
23373 case BFD_RELOC_ARM_LDC_SB_G1
:
23374 case BFD_RELOC_ARM_LDC_SB_G2
:
23375 gas_assert (!fixP
->fx_done
);
23376 if (!seg
->use_rela_p
)
23379 bfd_vma addend_abs
= abs (value
);
23381 /* Check that the absolute value of the addend is a multiple of
23382 four and, when divided by four, fits in 8 bits. */
23383 if (addend_abs
& 0x3)
23384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23385 _("bad offset 0x%08lX (must be word-aligned)"),
23386 (unsigned long) addend_abs
);
23388 if ((addend_abs
>> 2) > 0xff)
23389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23390 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23391 (unsigned long) addend_abs
);
23393 /* Extract the instruction. */
23394 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23396 /* If the addend is negative, clear bit 23 of the instruction.
23397 Otherwise set it. */
23399 insn
&= ~(1 << 23);
23403 /* Place the addend (divided by four) into the first eight
23404 bits of the instruction. */
23405 insn
&= 0xfffffff0;
23406 insn
|= addend_abs
>> 2;
23408 /* Update the instruction. */
23409 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23413 case BFD_RELOC_ARM_V4BX
:
23414 /* This will need to go in the object file. */
23418 case BFD_RELOC_UNUSED
:
23420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23421 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23425 /* Translate internal representation of relocation info to BFD target
23429 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23432 bfd_reloc_code_real_type code
;
23434 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23436 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23437 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23438 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23440 if (fixp
->fx_pcrel
)
23442 if (section
->use_rela_p
)
23443 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23445 fixp
->fx_offset
= reloc
->address
;
23447 reloc
->addend
= fixp
->fx_offset
;
23449 switch (fixp
->fx_r_type
)
23452 if (fixp
->fx_pcrel
)
23454 code
= BFD_RELOC_8_PCREL
;
23459 if (fixp
->fx_pcrel
)
23461 code
= BFD_RELOC_16_PCREL
;
23466 if (fixp
->fx_pcrel
)
23468 code
= BFD_RELOC_32_PCREL
;
23472 case BFD_RELOC_ARM_MOVW
:
23473 if (fixp
->fx_pcrel
)
23475 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23479 case BFD_RELOC_ARM_MOVT
:
23480 if (fixp
->fx_pcrel
)
23482 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23486 case BFD_RELOC_ARM_THUMB_MOVW
:
23487 if (fixp
->fx_pcrel
)
23489 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23493 case BFD_RELOC_ARM_THUMB_MOVT
:
23494 if (fixp
->fx_pcrel
)
23496 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23500 case BFD_RELOC_NONE
:
23501 case BFD_RELOC_ARM_PCREL_BRANCH
:
23502 case BFD_RELOC_ARM_PCREL_BLX
:
23503 case BFD_RELOC_RVA
:
23504 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23505 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23506 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23507 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23508 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23509 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23510 case BFD_RELOC_VTABLE_ENTRY
:
23511 case BFD_RELOC_VTABLE_INHERIT
:
23513 case BFD_RELOC_32_SECREL
:
23515 code
= fixp
->fx_r_type
;
23518 case BFD_RELOC_THUMB_PCREL_BLX
:
23520 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23521 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23524 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23527 case BFD_RELOC_ARM_LITERAL
:
23528 case BFD_RELOC_ARM_HWLITERAL
:
23529 /* If this is called then the a literal has
23530 been referenced across a section boundary. */
23531 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23532 _("literal referenced across section boundary"));
23536 case BFD_RELOC_ARM_TLS_CALL
:
23537 case BFD_RELOC_ARM_THM_TLS_CALL
:
23538 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23539 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23540 case BFD_RELOC_ARM_GOT32
:
23541 case BFD_RELOC_ARM_GOTOFF
:
23542 case BFD_RELOC_ARM_GOT_PREL
:
23543 case BFD_RELOC_ARM_PLT32
:
23544 case BFD_RELOC_ARM_TARGET1
:
23545 case BFD_RELOC_ARM_ROSEGREL32
:
23546 case BFD_RELOC_ARM_SBREL32
:
23547 case BFD_RELOC_ARM_PREL31
:
23548 case BFD_RELOC_ARM_TARGET2
:
23549 case BFD_RELOC_ARM_TLS_LDO32
:
23550 case BFD_RELOC_ARM_PCREL_CALL
:
23551 case BFD_RELOC_ARM_PCREL_JUMP
:
23552 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23553 case BFD_RELOC_ARM_ALU_PC_G0
:
23554 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23555 case BFD_RELOC_ARM_ALU_PC_G1
:
23556 case BFD_RELOC_ARM_ALU_PC_G2
:
23557 case BFD_RELOC_ARM_LDR_PC_G0
:
23558 case BFD_RELOC_ARM_LDR_PC_G1
:
23559 case BFD_RELOC_ARM_LDR_PC_G2
:
23560 case BFD_RELOC_ARM_LDRS_PC_G0
:
23561 case BFD_RELOC_ARM_LDRS_PC_G1
:
23562 case BFD_RELOC_ARM_LDRS_PC_G2
:
23563 case BFD_RELOC_ARM_LDC_PC_G0
:
23564 case BFD_RELOC_ARM_LDC_PC_G1
:
23565 case BFD_RELOC_ARM_LDC_PC_G2
:
23566 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23567 case BFD_RELOC_ARM_ALU_SB_G0
:
23568 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23569 case BFD_RELOC_ARM_ALU_SB_G1
:
23570 case BFD_RELOC_ARM_ALU_SB_G2
:
23571 case BFD_RELOC_ARM_LDR_SB_G0
:
23572 case BFD_RELOC_ARM_LDR_SB_G1
:
23573 case BFD_RELOC_ARM_LDR_SB_G2
:
23574 case BFD_RELOC_ARM_LDRS_SB_G0
:
23575 case BFD_RELOC_ARM_LDRS_SB_G1
:
23576 case BFD_RELOC_ARM_LDRS_SB_G2
:
23577 case BFD_RELOC_ARM_LDC_SB_G0
:
23578 case BFD_RELOC_ARM_LDC_SB_G1
:
23579 case BFD_RELOC_ARM_LDC_SB_G2
:
23580 case BFD_RELOC_ARM_V4BX
:
23581 code
= fixp
->fx_r_type
;
23584 case BFD_RELOC_ARM_TLS_GOTDESC
:
23585 case BFD_RELOC_ARM_TLS_GD32
:
23586 case BFD_RELOC_ARM_TLS_LE32
:
23587 case BFD_RELOC_ARM_TLS_IE32
:
23588 case BFD_RELOC_ARM_TLS_LDM32
:
23589 /* BFD will include the symbol's address in the addend.
23590 But we don't want that, so subtract it out again here. */
23591 if (!S_IS_COMMON (fixp
->fx_addsy
))
23592 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23593 code
= fixp
->fx_r_type
;
23597 case BFD_RELOC_ARM_IMMEDIATE
:
23598 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23599 _("internal relocation (type: IMMEDIATE) not fixed up"));
23602 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23603 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23604 _("ADRL used for a symbol not defined in the same file"));
23607 case BFD_RELOC_ARM_OFFSET_IMM
:
23608 if (section
->use_rela_p
)
23610 code
= fixp
->fx_r_type
;
23614 if (fixp
->fx_addsy
!= NULL
23615 && !S_IS_DEFINED (fixp
->fx_addsy
)
23616 && S_IS_LOCAL (fixp
->fx_addsy
))
23618 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23619 _("undefined local label `%s'"),
23620 S_GET_NAME (fixp
->fx_addsy
));
23624 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23625 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23632 switch (fixp
->fx_r_type
)
23634 case BFD_RELOC_NONE
: type
= "NONE"; break;
23635 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23636 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23637 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23638 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23639 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23640 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23641 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23642 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23643 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23644 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23645 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23646 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23647 default: type
= _("<unknown>"); break;
23649 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23650 _("cannot represent %s relocation in this object file format"),
23657 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23659 && fixp
->fx_addsy
== GOT_symbol
)
23661 code
= BFD_RELOC_ARM_GOTPC
;
23662 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23666 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23668 if (reloc
->howto
== NULL
)
23670 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23671 _("cannot represent %s relocation in this object file format"),
23672 bfd_get_reloc_code_name (code
));
23676 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23677 vtable entry to be used in the relocation's section offset. */
23678 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23679 reloc
->address
= fixp
->fx_offset
;
23684 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23687 cons_fix_new_arm (fragS
* frag
,
23691 bfd_reloc_code_real_type reloc
)
23696 FIXME: @@ Should look at CPU word size. */
23700 reloc
= BFD_RELOC_8
;
23703 reloc
= BFD_RELOC_16
;
23707 reloc
= BFD_RELOC_32
;
23710 reloc
= BFD_RELOC_64
;
23715 if (exp
->X_op
== O_secrel
)
23717 exp
->X_op
= O_symbol
;
23718 reloc
= BFD_RELOC_32_SECREL
;
23722 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23725 #if defined (OBJ_COFF)
23727 arm_validate_fix (fixS
* fixP
)
23729 /* If the destination of the branch is a defined symbol which does not have
23730 the THUMB_FUNC attribute, then we must be calling a function which has
23731 the (interfacearm) attribute. We look for the Thumb entry point to that
23732 function and change the branch to refer to that function instead. */
23733 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23734 && fixP
->fx_addsy
!= NULL
23735 && S_IS_DEFINED (fixP
->fx_addsy
)
23736 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23738 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23745 arm_force_relocation (struct fix
* fixp
)
23747 #if defined (OBJ_COFF) && defined (TE_PE)
23748 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23752 /* In case we have a call or a branch to a function in ARM ISA mode from
23753 a thumb function or vice-versa force the relocation. These relocations
23754 are cleared off for some cores that might have blx and simple transformations
23758 switch (fixp
->fx_r_type
)
23760 case BFD_RELOC_ARM_PCREL_JUMP
:
23761 case BFD_RELOC_ARM_PCREL_CALL
:
23762 case BFD_RELOC_THUMB_PCREL_BLX
:
23763 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23767 case BFD_RELOC_ARM_PCREL_BLX
:
23768 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23769 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23770 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23771 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23780 /* Resolve these relocations even if the symbol is extern or weak.
23781 Technically this is probably wrong due to symbol preemption.
23782 In practice these relocations do not have enough range to be useful
23783 at dynamic link time, and some code (e.g. in the Linux kernel)
23784 expects these references to be resolved. */
23785 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23786 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23787 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23788 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23789 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23790 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23791 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23792 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23793 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23794 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23795 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23796 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23797 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23798 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23801 /* Always leave these relocations for the linker. */
23802 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23803 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23804 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23807 /* Always generate relocations against function symbols. */
23808 if (fixp
->fx_r_type
== BFD_RELOC_32
23810 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23813 return generic_force_reloc (fixp
);
23816 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23817 /* Relocations against function names must be left unadjusted,
23818 so that the linker can use this information to generate interworking
23819 stubs. The MIPS version of this function
23820 also prevents relocations that are mips-16 specific, but I do not
23821 know why it does this.
23824 There is one other problem that ought to be addressed here, but
23825 which currently is not: Taking the address of a label (rather
23826 than a function) and then later jumping to that address. Such
23827 addresses also ought to have their bottom bit set (assuming that
23828 they reside in Thumb code), but at the moment they will not. */
23831 arm_fix_adjustable (fixS
* fixP
)
23833 if (fixP
->fx_addsy
== NULL
)
23836 /* Preserve relocations against symbols with function type. */
23837 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23840 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23841 && fixP
->fx_subsy
== NULL
)
23844 /* We need the symbol name for the VTABLE entries. */
23845 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23846 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23849 /* Don't allow symbols to be discarded on GOT related relocs. */
23850 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23851 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23852 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23853 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23854 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23855 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23856 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23857 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23858 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23859 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23860 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23861 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23862 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23863 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23866 /* Similarly for group relocations. */
23867 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23868 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23869 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23872 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23873 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23874 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23875 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23876 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23877 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23878 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23879 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23880 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23885 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23890 elf32_arm_target_format (void)
23893 return (target_big_endian
23894 ? "elf32-bigarm-symbian"
23895 : "elf32-littlearm-symbian");
23896 #elif defined (TE_VXWORKS)
23897 return (target_big_endian
23898 ? "elf32-bigarm-vxworks"
23899 : "elf32-littlearm-vxworks");
23900 #elif defined (TE_NACL)
23901 return (target_big_endian
23902 ? "elf32-bigarm-nacl"
23903 : "elf32-littlearm-nacl");
23905 if (target_big_endian
)
23906 return "elf32-bigarm";
23908 return "elf32-littlearm";
23913 armelf_frob_symbol (symbolS
* symp
,
23916 elf_frob_symbol (symp
, puntp
);
23920 /* MD interface: Finalization. */
23925 literal_pool
* pool
;
23927 /* Ensure that all the IT blocks are properly closed. */
23928 check_it_blocks_finished ();
23930 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23932 /* Put it at the end of the relevant section. */
23933 subseg_set (pool
->section
, pool
->sub_section
);
23935 arm_elf_change_section ();
23942 /* Remove any excess mapping symbols generated for alignment frags in
23943 SEC. We may have created a mapping symbol before a zero byte
23944 alignment; remove it if there's a mapping symbol after the
23947 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23948 void *dummy ATTRIBUTE_UNUSED
)
23950 segment_info_type
*seginfo
= seg_info (sec
);
23953 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23956 for (fragp
= seginfo
->frchainP
->frch_root
;
23958 fragp
= fragp
->fr_next
)
23960 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23961 fragS
*next
= fragp
->fr_next
;
23963 /* Variable-sized frags have been converted to fixed size by
23964 this point. But if this was variable-sized to start with,
23965 there will be a fixed-size frag after it. So don't handle
23967 if (sym
== NULL
|| next
== NULL
)
23970 if (S_GET_VALUE (sym
) < next
->fr_address
)
23971 /* Not at the end of this frag. */
23973 know (S_GET_VALUE (sym
) == next
->fr_address
);
23977 if (next
->tc_frag_data
.first_map
!= NULL
)
23979 /* Next frag starts with a mapping symbol. Discard this
23981 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23985 if (next
->fr_next
== NULL
)
23987 /* This mapping symbol is at the end of the section. Discard
23989 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23990 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23994 /* As long as we have empty frags without any mapping symbols,
23996 /* If the next frag is non-empty and does not start with a
23997 mapping symbol, then this mapping symbol is required. */
23998 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24001 next
= next
->fr_next
;
24003 while (next
!= NULL
);
24008 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24012 arm_adjust_symtab (void)
24017 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24019 if (ARM_IS_THUMB (sym
))
24021 if (THUMB_IS_FUNC (sym
))
24023 /* Mark the symbol as a Thumb function. */
24024 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24025 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24026 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24028 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24029 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24031 as_bad (_("%s: unexpected function type: %d"),
24032 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24034 else switch (S_GET_STORAGE_CLASS (sym
))
24037 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24040 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24043 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24051 if (ARM_IS_INTERWORK (sym
))
24052 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24059 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24061 if (ARM_IS_THUMB (sym
))
24063 elf_symbol_type
* elf_sym
;
24065 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24066 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24068 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24069 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24071 /* If it's a .thumb_func, declare it as so,
24072 otherwise tag label as .code 16. */
24073 if (THUMB_IS_FUNC (sym
))
24074 elf_sym
->internal_elf_sym
.st_target_internal
24075 = ST_BRANCH_TO_THUMB
;
24076 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24077 elf_sym
->internal_elf_sym
.st_info
=
24078 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24083 /* Remove any overlapping mapping symbols generated by alignment frags. */
24084 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24085 /* Now do generic ELF adjustments. */
24086 elf_adjust_symtab ();
24090 /* MD interface: Initialization. */
24093 set_constant_flonums (void)
24097 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24098 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24102 /* Auto-select Thumb mode if it's the only available instruction set for the
24103 given architecture. */
24106 autoselect_thumb_from_cpu_variant (void)
24108 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24109 opcode_select (16);
24118 if ( (arm_ops_hsh
= hash_new ()) == NULL
24119 || (arm_cond_hsh
= hash_new ()) == NULL
24120 || (arm_shift_hsh
= hash_new ()) == NULL
24121 || (arm_psr_hsh
= hash_new ()) == NULL
24122 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24123 || (arm_reg_hsh
= hash_new ()) == NULL
24124 || (arm_reloc_hsh
= hash_new ()) == NULL
24125 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24126 as_fatal (_("virtual memory exhausted"));
24128 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24129 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24130 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24131 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24132 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24133 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24134 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24135 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24136 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24137 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24138 (void *) (v7m_psrs
+ i
));
24139 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24140 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24142 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24144 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24145 (void *) (barrier_opt_names
+ i
));
24147 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24149 struct reloc_entry
* entry
= reloc_names
+ i
;
24151 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24152 /* This makes encode_branch() use the EABI versions of this relocation. */
24153 entry
->reloc
= BFD_RELOC_UNUSED
;
24155 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24159 set_constant_flonums ();
24161 /* Set the cpu variant based on the command-line options. We prefer
24162 -mcpu= over -march= if both are set (as for GCC); and we prefer
24163 -mfpu= over any other way of setting the floating point unit.
24164 Use of legacy options with new options are faulted. */
24167 if (mcpu_cpu_opt
|| march_cpu_opt
)
24168 as_bad (_("use of old and new-style options to set CPU type"));
24170 mcpu_cpu_opt
= legacy_cpu
;
24172 else if (!mcpu_cpu_opt
)
24173 mcpu_cpu_opt
= march_cpu_opt
;
24178 as_bad (_("use of old and new-style options to set FPU type"));
24180 mfpu_opt
= legacy_fpu
;
24182 else if (!mfpu_opt
)
24184 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24185 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24186 /* Some environments specify a default FPU. If they don't, infer it
24187 from the processor. */
24189 mfpu_opt
= mcpu_fpu_opt
;
24191 mfpu_opt
= march_fpu_opt
;
24193 mfpu_opt
= &fpu_default
;
24199 if (mcpu_cpu_opt
!= NULL
)
24200 mfpu_opt
= &fpu_default
;
24201 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24202 mfpu_opt
= &fpu_arch_vfp_v2
;
24204 mfpu_opt
= &fpu_arch_fpa
;
24210 mcpu_cpu_opt
= &cpu_default
;
24211 selected_cpu
= cpu_default
;
24213 else if (no_cpu_selected ())
24214 selected_cpu
= cpu_default
;
24217 selected_cpu
= *mcpu_cpu_opt
;
24219 mcpu_cpu_opt
= &arm_arch_any
;
24222 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24224 autoselect_thumb_from_cpu_variant ();
24226 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24228 #if defined OBJ_COFF || defined OBJ_ELF
24230 unsigned int flags
= 0;
24232 #if defined OBJ_ELF
24233 flags
= meabi_flags
;
24235 switch (meabi_flags
)
24237 case EF_ARM_EABI_UNKNOWN
:
24239 /* Set the flags in the private structure. */
24240 if (uses_apcs_26
) flags
|= F_APCS26
;
24241 if (support_interwork
) flags
|= F_INTERWORK
;
24242 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24243 if (pic_code
) flags
|= F_PIC
;
24244 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24245 flags
|= F_SOFT_FLOAT
;
24247 switch (mfloat_abi_opt
)
24249 case ARM_FLOAT_ABI_SOFT
:
24250 case ARM_FLOAT_ABI_SOFTFP
:
24251 flags
|= F_SOFT_FLOAT
;
24254 case ARM_FLOAT_ABI_HARD
:
24255 if (flags
& F_SOFT_FLOAT
)
24256 as_bad (_("hard-float conflicts with specified fpu"));
24260 /* Using pure-endian doubles (even if soft-float). */
24261 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24262 flags
|= F_VFP_FLOAT
;
24264 #if defined OBJ_ELF
24265 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24266 flags
|= EF_ARM_MAVERICK_FLOAT
;
24269 case EF_ARM_EABI_VER4
:
24270 case EF_ARM_EABI_VER5
:
24271 /* No additional flags to set. */
24278 bfd_set_private_flags (stdoutput
, flags
);
24280 /* We have run out flags in the COFF header to encode the
24281 status of ATPCS support, so instead we create a dummy,
24282 empty, debug section called .arm.atpcs. */
24287 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24291 bfd_set_section_flags
24292 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24293 bfd_set_section_size (stdoutput
, sec
, 0);
24294 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24300 /* Record the CPU type as well. */
24301 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24302 mach
= bfd_mach_arm_iWMMXt2
;
24303 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24304 mach
= bfd_mach_arm_iWMMXt
;
24305 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24306 mach
= bfd_mach_arm_XScale
;
24307 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24308 mach
= bfd_mach_arm_ep9312
;
24309 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24310 mach
= bfd_mach_arm_5TE
;
24311 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24313 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24314 mach
= bfd_mach_arm_5T
;
24316 mach
= bfd_mach_arm_5
;
24318 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24320 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24321 mach
= bfd_mach_arm_4T
;
24323 mach
= bfd_mach_arm_4
;
24325 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24326 mach
= bfd_mach_arm_3M
;
24327 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24328 mach
= bfd_mach_arm_3
;
24329 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24330 mach
= bfd_mach_arm_2a
;
24331 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24332 mach
= bfd_mach_arm_2
;
24334 mach
= bfd_mach_arm_unknown
;
24336 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24339 /* Command line processing. */
24342 Invocation line includes a switch not recognized by the base assembler.
24343 See if it's a processor-specific option.
24345 This routine is somewhat complicated by the need for backwards
24346 compatibility (since older releases of gcc can't be changed).
24347 The new options try to make the interface as compatible as
24350 New options (supported) are:
24352 -mcpu=<cpu name> Assemble for selected processor
24353 -march=<architecture name> Assemble for selected architecture
24354 -mfpu=<fpu architecture> Assemble for selected FPU.
24355 -EB/-mbig-endian Big-endian
24356 -EL/-mlittle-endian Little-endian
24357 -k Generate PIC code
24358 -mthumb Start in Thumb mode
24359 -mthumb-interwork Code supports ARM/Thumb interworking
24361 -m[no-]warn-deprecated Warn about deprecated features
24362 -m[no-]warn-syms Warn when symbols match instructions
24364 For now we will also provide support for:
24366 -mapcs-32 32-bit Program counter
24367 -mapcs-26 26-bit Program counter
24368 -macps-float Floats passed in FP registers
24369 -mapcs-reentrant Reentrant code
24371 (sometime these will probably be replaced with -mapcs=<list of options>
24372 and -matpcs=<list of options>)
24374 The remaining options are only supported for back-wards compatibility.
24375 Cpu variants, the arm part is optional:
24376 -m[arm]1 Currently not supported.
24377 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24378 -m[arm]3 Arm 3 processor
24379 -m[arm]6[xx], Arm 6 processors
24380 -m[arm]7[xx][t][[d]m] Arm 7 processors
24381 -m[arm]8[10] Arm 8 processors
24382 -m[arm]9[20][tdmi] Arm 9 processors
24383 -mstrongarm[110[0]] StrongARM processors
24384 -mxscale XScale processors
24385 -m[arm]v[2345[t[e]]] Arm architectures
24386 -mall All (except the ARM1)
24388 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24389 -mfpe-old (No float load/store multiples)
24390 -mvfpxd VFP Single precision
24392 -mno-fpu Disable all floating point instructions
24394 The following CPU names are recognized:
24395 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24396 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24397 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24398 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24399 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24400 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24401 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24405 const char * md_shortopts
= "m:k";
24407 #ifdef ARM_BI_ENDIAN
24408 #define OPTION_EB (OPTION_MD_BASE + 0)
24409 #define OPTION_EL (OPTION_MD_BASE + 1)
24411 #if TARGET_BYTES_BIG_ENDIAN
24412 #define OPTION_EB (OPTION_MD_BASE + 0)
24414 #define OPTION_EL (OPTION_MD_BASE + 1)
24417 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24419 struct option md_longopts
[] =
24422 {"EB", no_argument
, NULL
, OPTION_EB
},
24425 {"EL", no_argument
, NULL
, OPTION_EL
},
24427 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24428 {NULL
, no_argument
, NULL
, 0}
24432 size_t md_longopts_size
= sizeof (md_longopts
);
24434 struct arm_option_table
24436 char *option
; /* Option name to match. */
24437 char *help
; /* Help information. */
24438 int *var
; /* Variable to change. */
24439 int value
; /* What to change it to. */
24440 char *deprecated
; /* If non-null, print this message. */
24443 struct arm_option_table arm_opts
[] =
24445 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24446 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24447 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24448 &support_interwork
, 1, NULL
},
24449 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24450 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24451 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24453 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24454 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24455 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24456 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24459 /* These are recognized by the assembler, but have no affect on code. */
24460 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24461 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24463 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24464 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24465 &warn_on_deprecated
, 0, NULL
},
24466 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24467 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24468 {NULL
, NULL
, NULL
, 0, NULL
}
24471 struct arm_legacy_option_table
24473 char *option
; /* Option name to match. */
24474 const arm_feature_set
**var
; /* Variable to change. */
24475 const arm_feature_set value
; /* What to change it to. */
24476 char *deprecated
; /* If non-null, print this message. */
24479 const struct arm_legacy_option_table arm_legacy_opts
[] =
24481 /* DON'T add any new processors to this list -- we want the whole list
24482 to go away... Add them to the processors table instead. */
24483 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24484 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24485 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24486 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24487 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24488 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24489 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24490 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24491 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24492 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24493 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24494 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24495 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24496 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24497 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24498 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24499 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24500 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24501 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24502 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24503 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24504 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24505 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24506 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24507 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24508 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24509 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24510 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24511 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24512 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24513 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24514 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24515 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24516 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24517 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24518 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24519 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24520 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24521 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24522 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24523 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24524 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24525 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24526 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24527 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24528 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24529 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24530 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24531 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24532 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24533 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24534 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24535 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24536 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24537 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24538 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24539 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24540 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24541 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24542 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24543 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24544 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24545 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24546 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24547 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24548 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24549 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24550 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24551 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24552 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24553 N_("use -mcpu=strongarm110")},
24554 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24555 N_("use -mcpu=strongarm1100")},
24556 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24557 N_("use -mcpu=strongarm1110")},
24558 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24559 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24560 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24562 /* Architecture variants -- don't add any more to this list either. */
24563 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24564 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24565 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24566 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24567 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24568 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24569 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24570 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24571 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24572 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24573 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24574 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24575 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24576 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24577 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24578 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24579 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24580 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24582 /* Floating point variants -- don't add any more to this list either. */
24583 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24584 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24585 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24586 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24587 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24589 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24592 struct arm_cpu_option_table
24596 const arm_feature_set value
;
24597 /* For some CPUs we assume an FPU unless the user explicitly sets
24599 const arm_feature_set default_fpu
;
24600 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24602 const char *canonical_name
;
24605 /* This list should, at a minimum, contain all the cpu names
24606 recognized by GCC. */
24607 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24608 static const struct arm_cpu_option_table arm_cpus
[] =
24610 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24611 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24612 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24613 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24614 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24615 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24616 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24617 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24618 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24619 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24620 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24621 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24622 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24623 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24624 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24625 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24626 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24627 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24628 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24629 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24630 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24631 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24632 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24633 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24634 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24635 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24636 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24637 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24638 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24639 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24640 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24641 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24642 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24643 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24644 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24645 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24646 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24647 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24648 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24649 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24650 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24651 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24652 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24653 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24654 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24655 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24656 /* For V5 or later processors we default to using VFP; but the user
24657 should really set the FPU type explicitly. */
24658 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24659 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24660 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24661 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24662 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24663 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24664 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24665 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24666 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24667 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24668 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24669 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24670 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24671 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24672 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24673 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24674 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24675 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24676 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24677 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24679 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24680 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24681 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24682 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24683 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24684 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24685 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24686 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24687 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24689 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24690 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24691 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24692 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24693 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24694 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24695 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24696 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24697 FPU_NONE
, "Cortex-A5"),
24698 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24700 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24701 ARM_FEATURE_COPROC (FPU_VFP_V3
24702 | FPU_NEON_EXT_V1
),
24704 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24705 ARM_FEATURE_COPROC (FPU_VFP_V3
24706 | FPU_NEON_EXT_V1
),
24708 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24710 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24712 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24714 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24716 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24718 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24720 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24722 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24723 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24725 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24726 FPU_NONE
, "Cortex-R5"),
24727 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24728 FPU_ARCH_VFP_V3D16
,
24730 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24731 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24732 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24733 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24734 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24735 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24736 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24739 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24743 /* ??? XSCALE is really an architecture. */
24744 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24745 /* ??? iwmmxt is not a processor. */
24746 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24747 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24748 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24750 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24751 FPU_ARCH_MAVERICK
, "ARM920T"),
24752 /* Marvell processors. */
24753 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24755 FPU_ARCH_VFP_V3D16
, NULL
),
24756 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24758 FPU_ARCH_NEON_VFP_V4
, NULL
),
24759 /* APM X-Gene family. */
24760 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24762 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24765 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24769 struct arm_arch_option_table
24773 const arm_feature_set value
;
24774 const arm_feature_set default_fpu
;
24777 /* This list should, at a minimum, contain all the architecture names
24778 recognized by GCC. */
24779 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24780 static const struct arm_arch_option_table arm_archs
[] =
24782 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24783 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24784 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24785 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24786 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24787 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24788 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24789 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24790 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24791 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24792 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24793 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24794 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24795 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24796 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24797 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24798 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24799 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24800 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24801 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24802 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24803 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24804 kept to preserve existing behaviour. */
24805 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24806 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24807 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24808 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24809 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24810 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24811 kept to preserve existing behaviour. */
24812 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24813 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24814 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24815 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24816 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24817 /* The official spelling of the ARMv7 profile variants is the dashed form.
24818 Accept the non-dashed form for compatibility with old toolchains. */
24819 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24820 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24821 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24822 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24823 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24824 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24825 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24826 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24827 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24828 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24829 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
24830 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24831 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24832 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24833 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24835 #undef ARM_ARCH_OPT
24837 /* ISA extensions in the co-processor and main instruction set space. */
24838 struct arm_option_extension_value_table
24842 const arm_feature_set merge_value
;
24843 const arm_feature_set clear_value
;
24844 const arm_feature_set allowed_archs
;
24847 /* The following table must be in alphabetical order with a NULL last entry.
24849 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24850 static const struct arm_option_extension_value_table arm_extensions
[] =
24852 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24853 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24854 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24855 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24856 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24857 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24858 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24859 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24860 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24861 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24862 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24863 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24864 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24865 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24866 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24867 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24868 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24869 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24870 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24871 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24872 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24873 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24874 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24875 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24876 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24877 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24878 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24879 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24880 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24881 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24882 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24883 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24885 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24886 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24887 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24888 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24889 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24890 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24891 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24892 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24896 /* ISA floating-point and Advanced SIMD extensions. */
24897 struct arm_option_fpu_value_table
24900 const arm_feature_set value
;
24903 /* This list should, at a minimum, contain all the fpu names
24904 recognized by GCC. */
24905 static const struct arm_option_fpu_value_table arm_fpus
[] =
24907 {"softfpa", FPU_NONE
},
24908 {"fpe", FPU_ARCH_FPE
},
24909 {"fpe2", FPU_ARCH_FPE
},
24910 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24911 {"fpa", FPU_ARCH_FPA
},
24912 {"fpa10", FPU_ARCH_FPA
},
24913 {"fpa11", FPU_ARCH_FPA
},
24914 {"arm7500fe", FPU_ARCH_FPA
},
24915 {"softvfp", FPU_ARCH_VFP
},
24916 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24917 {"vfp", FPU_ARCH_VFP_V2
},
24918 {"vfp9", FPU_ARCH_VFP_V2
},
24919 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24920 {"vfp10", FPU_ARCH_VFP_V2
},
24921 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24922 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24923 {"vfpv2", FPU_ARCH_VFP_V2
},
24924 {"vfpv3", FPU_ARCH_VFP_V3
},
24925 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24926 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24927 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24928 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24929 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24930 {"arm1020t", FPU_ARCH_VFP_V1
},
24931 {"arm1020e", FPU_ARCH_VFP_V2
},
24932 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24933 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24934 {"maverick", FPU_ARCH_MAVERICK
},
24935 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24936 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24937 {"vfpv4", FPU_ARCH_VFP_V4
},
24938 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24939 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24940 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24941 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24942 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24943 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24944 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24945 {"crypto-neon-fp-armv8",
24946 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24947 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24948 {"crypto-neon-fp-armv8.1",
24949 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
24950 {NULL
, ARM_ARCH_NONE
}
24953 struct arm_option_value_table
24959 static const struct arm_option_value_table arm_float_abis
[] =
24961 {"hard", ARM_FLOAT_ABI_HARD
},
24962 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24963 {"soft", ARM_FLOAT_ABI_SOFT
},
24968 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24969 static const struct arm_option_value_table arm_eabis
[] =
24971 {"gnu", EF_ARM_EABI_UNKNOWN
},
24972 {"4", EF_ARM_EABI_VER4
},
24973 {"5", EF_ARM_EABI_VER5
},
24978 struct arm_long_option_table
24980 char * option
; /* Substring to match. */
24981 char * help
; /* Help information. */
24982 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24983 char * deprecated
; /* If non-null, print this message. */
24987 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24989 arm_feature_set
*ext_set
= (arm_feature_set
*)
24990 xmalloc (sizeof (arm_feature_set
));
24992 /* We insist on extensions being specified in alphabetical order, and with
24993 extensions being added before being removed. We achieve this by having
24994 the global ARM_EXTENSIONS table in alphabetical order, and using the
24995 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24996 or removing it (0) and only allowing it to change in the order
24998 const struct arm_option_extension_value_table
* opt
= NULL
;
24999 int adding_value
= -1;
25001 /* Copy the feature set, so that we can modify it. */
25002 *ext_set
= **opt_p
;
25005 while (str
!= NULL
&& *str
!= 0)
25012 as_bad (_("invalid architectural extension"));
25017 ext
= strchr (str
, '+');
25022 len
= strlen (str
);
25024 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25026 if (adding_value
!= 0)
25029 opt
= arm_extensions
;
25037 if (adding_value
== -1)
25040 opt
= arm_extensions
;
25042 else if (adding_value
!= 1)
25044 as_bad (_("must specify extensions to add before specifying "
25045 "those to remove"));
25052 as_bad (_("missing architectural extension"));
25056 gas_assert (adding_value
!= -1);
25057 gas_assert (opt
!= NULL
);
25059 /* Scan over the options table trying to find an exact match. */
25060 for (; opt
->name
!= NULL
; opt
++)
25061 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25063 /* Check we can apply the extension to this architecture. */
25064 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25066 as_bad (_("extension does not apply to the base architecture"));
25070 /* Add or remove the extension. */
25072 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25074 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25079 if (opt
->name
== NULL
)
25081 /* Did we fail to find an extension because it wasn't specified in
25082 alphabetical order, or because it does not exist? */
25084 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25085 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25088 if (opt
->name
== NULL
)
25089 as_bad (_("unknown architectural extension `%s'"), str
);
25091 as_bad (_("architectural extensions must be specified in "
25092 "alphabetical order"));
25098 /* We should skip the extension we've just matched the next time
25110 arm_parse_cpu (char *str
)
25112 const struct arm_cpu_option_table
*opt
;
25113 char *ext
= strchr (str
, '+');
25119 len
= strlen (str
);
25123 as_bad (_("missing cpu name `%s'"), str
);
25127 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25128 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25130 mcpu_cpu_opt
= &opt
->value
;
25131 mcpu_fpu_opt
= &opt
->default_fpu
;
25132 if (opt
->canonical_name
)
25134 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25135 strcpy (selected_cpu_name
, opt
->canonical_name
);
25141 if (len
>= sizeof selected_cpu_name
)
25142 len
= (sizeof selected_cpu_name
) - 1;
25144 for (i
= 0; i
< len
; i
++)
25145 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25146 selected_cpu_name
[i
] = 0;
25150 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25155 as_bad (_("unknown cpu `%s'"), str
);
25160 arm_parse_arch (char *str
)
25162 const struct arm_arch_option_table
*opt
;
25163 char *ext
= strchr (str
, '+');
25169 len
= strlen (str
);
25173 as_bad (_("missing architecture name `%s'"), str
);
25177 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25178 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25180 march_cpu_opt
= &opt
->value
;
25181 march_fpu_opt
= &opt
->default_fpu
;
25182 strcpy (selected_cpu_name
, opt
->name
);
25185 return arm_parse_extension (ext
, &march_cpu_opt
);
25190 as_bad (_("unknown architecture `%s'\n"), str
);
25195 arm_parse_fpu (char * str
)
25197 const struct arm_option_fpu_value_table
* opt
;
25199 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25200 if (streq (opt
->name
, str
))
25202 mfpu_opt
= &opt
->value
;
25206 as_bad (_("unknown floating point format `%s'\n"), str
);
25211 arm_parse_float_abi (char * str
)
25213 const struct arm_option_value_table
* opt
;
25215 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25216 if (streq (opt
->name
, str
))
25218 mfloat_abi_opt
= opt
->value
;
25222 as_bad (_("unknown floating point abi `%s'\n"), str
);
25228 arm_parse_eabi (char * str
)
25230 const struct arm_option_value_table
*opt
;
25232 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25233 if (streq (opt
->name
, str
))
25235 meabi_flags
= opt
->value
;
25238 as_bad (_("unknown EABI `%s'\n"), str
);
25244 arm_parse_it_mode (char * str
)
25246 bfd_boolean ret
= TRUE
;
25248 if (streq ("arm", str
))
25249 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25250 else if (streq ("thumb", str
))
25251 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25252 else if (streq ("always", str
))
25253 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25254 else if (streq ("never", str
))
25255 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25258 as_bad (_("unknown implicit IT mode `%s', should be "\
25259 "arm, thumb, always, or never."), str
);
25267 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25269 codecomposer_syntax
= TRUE
;
25270 arm_comment_chars
[0] = ';';
25271 arm_line_separator_chars
[0] = 0;
25275 struct arm_long_option_table arm_long_opts
[] =
25277 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25278 arm_parse_cpu
, NULL
},
25279 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25280 arm_parse_arch
, NULL
},
25281 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25282 arm_parse_fpu
, NULL
},
25283 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25284 arm_parse_float_abi
, NULL
},
25286 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25287 arm_parse_eabi
, NULL
},
25289 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25290 arm_parse_it_mode
, NULL
},
25291 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25292 arm_ccs_mode
, NULL
},
25293 {NULL
, NULL
, 0, NULL
}
25297 md_parse_option (int c
, char * arg
)
25299 struct arm_option_table
*opt
;
25300 const struct arm_legacy_option_table
*fopt
;
25301 struct arm_long_option_table
*lopt
;
25307 target_big_endian
= 1;
25313 target_big_endian
= 0;
25317 case OPTION_FIX_V4BX
:
25322 /* Listing option. Just ignore these, we don't support additional
25327 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25329 if (c
== opt
->option
[0]
25330 && ((arg
== NULL
&& opt
->option
[1] == 0)
25331 || streq (arg
, opt
->option
+ 1)))
25333 /* If the option is deprecated, tell the user. */
25334 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25335 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25336 arg
? arg
: "", _(opt
->deprecated
));
25338 if (opt
->var
!= NULL
)
25339 *opt
->var
= opt
->value
;
25345 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25347 if (c
== fopt
->option
[0]
25348 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25349 || streq (arg
, fopt
->option
+ 1)))
25351 /* If the option is deprecated, tell the user. */
25352 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25353 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25354 arg
? arg
: "", _(fopt
->deprecated
));
25356 if (fopt
->var
!= NULL
)
25357 *fopt
->var
= &fopt
->value
;
25363 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25365 /* These options are expected to have an argument. */
25366 if (c
== lopt
->option
[0]
25368 && strncmp (arg
, lopt
->option
+ 1,
25369 strlen (lopt
->option
+ 1)) == 0)
25371 /* If the option is deprecated, tell the user. */
25372 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25373 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25374 _(lopt
->deprecated
));
25376 /* Call the sup-option parser. */
25377 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25388 md_show_usage (FILE * fp
)
25390 struct arm_option_table
*opt
;
25391 struct arm_long_option_table
*lopt
;
25393 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25395 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25396 if (opt
->help
!= NULL
)
25397 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25399 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25400 if (lopt
->help
!= NULL
)
25401 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25405 -EB assemble code for a big-endian cpu\n"));
25410 -EL assemble code for a little-endian cpu\n"));
25414 --fix-v4bx Allow BX in ARMv4 code\n"));
25422 arm_feature_set flags
;
25423 } cpu_arch_ver_table
;
25425 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25426 least features first. */
25427 static const cpu_arch_ver_table cpu_arch_ver
[] =
25433 {4, ARM_ARCH_V5TE
},
25434 {5, ARM_ARCH_V5TEJ
},
25438 {11, ARM_ARCH_V6M
},
25439 {12, ARM_ARCH_V6SM
},
25440 {8, ARM_ARCH_V6T2
},
25441 {10, ARM_ARCH_V7VE
},
25442 {10, ARM_ARCH_V7R
},
25443 {10, ARM_ARCH_V7M
},
25444 {14, ARM_ARCH_V8A
},
25448 /* Set an attribute if it has not already been set by the user. */
25450 aeabi_set_attribute_int (int tag
, int value
)
25453 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25454 || !attributes_set_explicitly
[tag
])
25455 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25459 aeabi_set_attribute_string (int tag
, const char *value
)
25462 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25463 || !attributes_set_explicitly
[tag
])
25464 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25467 /* Set the public EABI object attributes. */
25469 aeabi_set_public_attributes (void)
25474 int fp16_optional
= 0;
25475 arm_feature_set flags
;
25476 arm_feature_set tmp
;
25477 const cpu_arch_ver_table
*p
;
25479 /* Choose the architecture based on the capabilities of the requested cpu
25480 (if any) and/or the instructions actually used. */
25481 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25482 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25483 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25485 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25486 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25488 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25489 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25491 selected_cpu
= flags
;
25493 /* Allow the user to override the reported architecture. */
25496 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25497 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25500 /* We need to make sure that the attributes do not identify us as v6S-M
25501 when the only v6S-M feature in use is the Operating System Extensions. */
25502 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25503 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25504 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25508 for (p
= cpu_arch_ver
; p
->val
; p
++)
25510 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25513 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25517 /* The table lookup above finds the last architecture to contribute
25518 a new feature. Unfortunately, Tag13 is a subset of the union of
25519 v6T2 and v7-M, so it is never seen as contributing a new feature.
25520 We can not search for the last entry which is entirely used,
25521 because if no CPU is specified we build up only those flags
25522 actually used. Perhaps we should separate out the specified
25523 and implicit cases. Avoid taking this path for -march=all by
25524 checking for contradictory v7-A / v7-M features. */
25526 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25527 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25528 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25531 /* Tag_CPU_name. */
25532 if (selected_cpu_name
[0])
25536 q
= selected_cpu_name
;
25537 if (strncmp (q
, "armv", 4) == 0)
25542 for (i
= 0; q
[i
]; i
++)
25543 q
[i
] = TOUPPER (q
[i
]);
25545 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25548 /* Tag_CPU_arch. */
25549 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25551 /* Tag_CPU_arch_profile. */
25552 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25554 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25556 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25561 if (profile
!= '\0')
25562 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25564 /* Tag_ARM_ISA_use. */
25565 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25567 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25569 /* Tag_THUMB_ISA_use. */
25570 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25572 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25573 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25575 /* Tag_VFP_arch. */
25576 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25577 aeabi_set_attribute_int (Tag_VFP_arch
,
25578 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25580 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25581 aeabi_set_attribute_int (Tag_VFP_arch
,
25582 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25584 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25587 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25589 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25591 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25594 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25595 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25596 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25597 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25598 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25600 /* Tag_ABI_HardFP_use. */
25601 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25602 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25603 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25605 /* Tag_WMMX_arch. */
25606 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25607 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25608 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25609 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25611 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25612 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25613 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25614 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25616 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25618 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25622 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25627 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25628 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25629 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25633 We set Tag_DIV_use to two when integer divide instructions have been used
25634 in ARM state, or when Thumb integer divide instructions have been used,
25635 but we have no architecture profile set, nor have we any ARM instructions.
25637 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25640 For new architectures we will have to check these tests. */
25641 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25642 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25643 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25644 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25645 || (profile
== '\0'
25646 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25647 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25648 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25650 /* Tag_MP_extension_use. */
25651 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25652 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25654 /* Tag Virtualization_use. */
25655 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25657 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25660 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25663 /* Add the default contents for the .ARM.attributes section. */
25667 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25670 aeabi_set_public_attributes ();
25672 #endif /* OBJ_ELF */
25675 /* Parse a .cpu directive. */
25678 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25680 const struct arm_cpu_option_table
*opt
;
25684 name
= input_line_pointer
;
25685 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25686 input_line_pointer
++;
25687 saved_char
= *input_line_pointer
;
25688 *input_line_pointer
= 0;
25690 /* Skip the first "all" entry. */
25691 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25692 if (streq (opt
->name
, name
))
25694 mcpu_cpu_opt
= &opt
->value
;
25695 selected_cpu
= opt
->value
;
25696 if (opt
->canonical_name
)
25697 strcpy (selected_cpu_name
, opt
->canonical_name
);
25701 for (i
= 0; opt
->name
[i
]; i
++)
25702 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25704 selected_cpu_name
[i
] = 0;
25706 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25707 *input_line_pointer
= saved_char
;
25708 demand_empty_rest_of_line ();
25711 as_bad (_("unknown cpu `%s'"), name
);
25712 *input_line_pointer
= saved_char
;
25713 ignore_rest_of_line ();
25717 /* Parse a .arch directive. */
25720 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25722 const struct arm_arch_option_table
*opt
;
25726 name
= input_line_pointer
;
25727 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25728 input_line_pointer
++;
25729 saved_char
= *input_line_pointer
;
25730 *input_line_pointer
= 0;
25732 /* Skip the first "all" entry. */
25733 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25734 if (streq (opt
->name
, name
))
25736 mcpu_cpu_opt
= &opt
->value
;
25737 selected_cpu
= opt
->value
;
25738 strcpy (selected_cpu_name
, opt
->name
);
25739 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25740 *input_line_pointer
= saved_char
;
25741 demand_empty_rest_of_line ();
25745 as_bad (_("unknown architecture `%s'\n"), name
);
25746 *input_line_pointer
= saved_char
;
25747 ignore_rest_of_line ();
25751 /* Parse a .object_arch directive. */
25754 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25756 const struct arm_arch_option_table
*opt
;
25760 name
= input_line_pointer
;
25761 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25762 input_line_pointer
++;
25763 saved_char
= *input_line_pointer
;
25764 *input_line_pointer
= 0;
25766 /* Skip the first "all" entry. */
25767 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25768 if (streq (opt
->name
, name
))
25770 object_arch
= &opt
->value
;
25771 *input_line_pointer
= saved_char
;
25772 demand_empty_rest_of_line ();
25776 as_bad (_("unknown architecture `%s'\n"), name
);
25777 *input_line_pointer
= saved_char
;
25778 ignore_rest_of_line ();
25781 /* Parse a .arch_extension directive. */
25784 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25786 const struct arm_option_extension_value_table
*opt
;
25789 int adding_value
= 1;
25791 name
= input_line_pointer
;
25792 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25793 input_line_pointer
++;
25794 saved_char
= *input_line_pointer
;
25795 *input_line_pointer
= 0;
25797 if (strlen (name
) >= 2
25798 && strncmp (name
, "no", 2) == 0)
25804 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25805 if (streq (opt
->name
, name
))
25807 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25809 as_bad (_("architectural extension `%s' is not allowed for the "
25810 "current base architecture"), name
);
25815 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25818 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25820 mcpu_cpu_opt
= &selected_cpu
;
25821 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25822 *input_line_pointer
= saved_char
;
25823 demand_empty_rest_of_line ();
25827 if (opt
->name
== NULL
)
25828 as_bad (_("unknown architecture extension `%s'\n"), name
);
25830 *input_line_pointer
= saved_char
;
25831 ignore_rest_of_line ();
25834 /* Parse a .fpu directive. */
25837 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25839 const struct arm_option_fpu_value_table
*opt
;
25843 name
= input_line_pointer
;
25844 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25845 input_line_pointer
++;
25846 saved_char
= *input_line_pointer
;
25847 *input_line_pointer
= 0;
25849 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25850 if (streq (opt
->name
, name
))
25852 mfpu_opt
= &opt
->value
;
25853 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25854 *input_line_pointer
= saved_char
;
25855 demand_empty_rest_of_line ();
25859 as_bad (_("unknown floating point format `%s'\n"), name
);
25860 *input_line_pointer
= saved_char
;
25861 ignore_rest_of_line ();
25864 /* Copy symbol information. */
25867 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25869 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25873 /* Given a symbolic attribute NAME, return the proper integer value.
25874 Returns -1 if the attribute is not known. */
25877 arm_convert_symbolic_attribute (const char *name
)
25879 static const struct
25884 attribute_table
[] =
25886 /* When you modify this table you should
25887 also modify the list in doc/c-arm.texi. */
25888 #define T(tag) {#tag, tag}
25889 T (Tag_CPU_raw_name
),
25892 T (Tag_CPU_arch_profile
),
25893 T (Tag_ARM_ISA_use
),
25894 T (Tag_THUMB_ISA_use
),
25898 T (Tag_Advanced_SIMD_arch
),
25899 T (Tag_PCS_config
),
25900 T (Tag_ABI_PCS_R9_use
),
25901 T (Tag_ABI_PCS_RW_data
),
25902 T (Tag_ABI_PCS_RO_data
),
25903 T (Tag_ABI_PCS_GOT_use
),
25904 T (Tag_ABI_PCS_wchar_t
),
25905 T (Tag_ABI_FP_rounding
),
25906 T (Tag_ABI_FP_denormal
),
25907 T (Tag_ABI_FP_exceptions
),
25908 T (Tag_ABI_FP_user_exceptions
),
25909 T (Tag_ABI_FP_number_model
),
25910 T (Tag_ABI_align_needed
),
25911 T (Tag_ABI_align8_needed
),
25912 T (Tag_ABI_align_preserved
),
25913 T (Tag_ABI_align8_preserved
),
25914 T (Tag_ABI_enum_size
),
25915 T (Tag_ABI_HardFP_use
),
25916 T (Tag_ABI_VFP_args
),
25917 T (Tag_ABI_WMMX_args
),
25918 T (Tag_ABI_optimization_goals
),
25919 T (Tag_ABI_FP_optimization_goals
),
25920 T (Tag_compatibility
),
25921 T (Tag_CPU_unaligned_access
),
25922 T (Tag_FP_HP_extension
),
25923 T (Tag_VFP_HP_extension
),
25924 T (Tag_ABI_FP_16bit_format
),
25925 T (Tag_MPextension_use
),
25927 T (Tag_nodefaults
),
25928 T (Tag_also_compatible_with
),
25929 T (Tag_conformance
),
25931 T (Tag_Virtualization_use
),
25932 /* We deliberately do not include Tag_MPextension_use_legacy. */
25940 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25941 if (streq (name
, attribute_table
[i
].name
))
25942 return attribute_table
[i
].tag
;
25948 /* Apply sym value for relocations only in the case that they are for
25949 local symbols in the same segment as the fixup and you have the
25950 respective architectural feature for blx and simple switches. */
25952 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25955 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25956 /* PR 17444: If the local symbol is in a different section then a reloc
25957 will always be generated for it, so applying the symbol value now
25958 will result in a double offset being stored in the relocation. */
25959 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25960 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25962 switch (fixP
->fx_r_type
)
25964 case BFD_RELOC_ARM_PCREL_BLX
:
25965 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25966 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25970 case BFD_RELOC_ARM_PCREL_CALL
:
25971 case BFD_RELOC_THUMB_PCREL_BLX
:
25972 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25983 #endif /* OBJ_ELF */