1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
369 static int mfloat_abi_opt
= -1;
370 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
372 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
373 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
375 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
376 /* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
379 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
380 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
381 static arm_feature_set selected_fpu
= FPU_NONE
;
382 /* Feature bits selected by the last .object_arch directive. */
383 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
384 /* Must be long enough to hold any of the names in arm_cpus. */
385 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
386 static char selected_cpu_name
[20];
388 extern FLONUM_TYPE generic_floating_point_number
;
390 /* Return if no cpu was selected on command-line. */
392 no_cpu_selected (void)
394 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
399 static int meabi_flags
= EABI_DEFAULT
;
401 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
404 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
409 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
414 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415 symbolS
* GOT_symbol
;
418 /* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
422 static int thumb_mode
= 0;
423 /* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426 #define MODE_RECORDED (1 << 4)
428 /* Specifies the intrinsic IT insn behavior mode. */
429 enum implicit_it_mode
431 IMPLICIT_IT_MODE_NEVER
= 0x00,
432 IMPLICIT_IT_MODE_ARM
= 0x01,
433 IMPLICIT_IT_MODE_THUMB
= 0x02,
434 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
436 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
438 /* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
450 Important differences from the old Thumb mode:
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
461 static bfd_boolean unified_syntax
= FALSE
;
463 /* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467 const char arm_symbol_chars
[] = "#[]{}";
483 enum neon_el_type type
;
487 #define NEON_MAX_TYPE_ELS 5
491 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
495 enum pred_instruction_type
501 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN
, /* The IT insn has been parsed. */
506 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
512 /* The maximum number of operands we need. */
513 #define ARM_IT_MAX_OPERANDS 6
514 #define ARM_IT_MAX_RELOCS 3
519 unsigned long instruction
;
521 unsigned int size_req
;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1u if nothing is
526 unsigned int uncond_value
;
527 struct neon_type vectype
;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
536 bfd_reloc_code_real_type type
;
539 } relocs
[ARM_IT_MAX_RELOCS
];
541 enum pred_instruction_type pred_insn_type
;
547 struct neon_type_el vectype
;
548 unsigned present
: 1; /* Operand present. */
549 unsigned isreg
: 1; /* Operand was a register. */
550 unsigned immisreg
: 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
556 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad
: 1; /* Operand is SIMD quad register. */
563 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
564 unsigned iszr
: 1; /* Operand is ZR register. */
565 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
566 unsigned writeback
: 1; /* Operand has trailing ! */
567 unsigned preind
: 1; /* Preindexed address. */
568 unsigned postind
: 1; /* Postindexed address. */
569 unsigned negative
: 1; /* Index register was negated. */
570 unsigned shifted
: 1; /* Shift applied to operation. */
571 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
572 } operands
[ARM_IT_MAX_OPERANDS
];
575 static struct arm_it inst
;
577 #define NUM_FLOAT_VALS 8
579 const char * fp_const
[] =
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
594 #define CP_T_X 0x00008000
595 #define CP_T_Y 0x00400000
597 #define CONDS_BIT 0x00100000
598 #define LOAD_BIT 0x00100000
600 #define DOUBLE_LOAD_FLAG 0x00000001
604 const char * template_name
;
608 #define COND_ALWAYS 0xE
612 const char * template_name
;
616 struct asm_barrier_opt
618 const char * template_name
;
620 const arm_feature_set arch
;
623 /* The bit that distinguishes CPSR and SPSR. */
624 #define SPSR_BIT (1 << 22)
626 /* The individual PSR flag bits. */
627 #define PSR_c (1 << 16)
628 #define PSR_x (1 << 17)
629 #define PSR_s (1 << 18)
630 #define PSR_f (1 << 19)
635 bfd_reloc_code_real_type reloc
;
640 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
641 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
646 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
649 /* Bits for DEFINED field in neon_typed_alias. */
650 #define NTA_HASTYPE 1
651 #define NTA_HASINDEX 2
653 struct neon_typed_alias
655 unsigned char defined
;
657 struct neon_type_el eltype
;
660 /* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
692 /* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
701 unsigned char builtin
;
702 struct neon_typed_alias
* neon
;
705 /* Diagnostics used when we don't get a register of the expected type. */
706 const char * const reg_expected_msgs
[] =
708 [REG_TYPE_RN
] = N_("ARM register expected"),
709 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN
] = N_("co-processor register expected"),
711 [REG_TYPE_FN
] = N_("FPA register expected"),
712 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
720 [REG_TYPE_VFC
] = N_("VFP system register expected"),
721 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 /* Some well known registers that we refer to directly elsewhere. */
741 /* ARM instructions take 4bytes in the object file, Thumb instructions
747 /* Basic string to match. */
748 const char * template_name
;
750 /* Parameters to instruction. */
751 unsigned int operands
[8];
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag
: 4;
756 /* Basic instruction code. */
759 /* Thumb-format instruction code. */
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set
* avariant
;
764 const arm_feature_set
* tvariant
;
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode
) (void);
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode
) (void);
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred
: 1;
776 /* Defines for various bits that we will want to toggle. */
777 #define INST_IMMEDIATE 0x02000000
778 #define OFFSET_REG 0x02000000
779 #define HWOFFSET_IMM 0x00400000
780 #define SHIFT_BY_REG 0x00000010
781 #define PRE_INDEX 0x01000000
782 #define INDEX_UP 0x00800000
783 #define WRITE_BACK 0x00200000
784 #define LDM_TYPE_2_OR_3 0x00400000
785 #define CPSI_MMOD 0x00020000
787 #define LITERAL_MASK 0xf000f000
788 #define OPCODE_MASK 0xfe1fffff
789 #define V4_STR_BIT 0x00000020
790 #define VLDR_VMOV_SAME 0x0040f000
792 #define T2_SUBS_PC_LR 0xf3de8f00
794 #define DATA_OP_SHIFT 21
795 #define SBIT_SHIFT 20
797 #define T2_OPCODE_MASK 0xfe1fffff
798 #define T2_DATA_OP_SHIFT 21
799 #define T2_SBIT_SHIFT 20
801 #define A_COND_MASK 0xf0000000
802 #define A_PUSH_POP_OP_MASK 0x0fff0000
804 /* Opcodes for pushing/poping registers to/from the stack. */
805 #define A1_OPCODE_PUSH 0x092d0000
806 #define A2_OPCODE_PUSH 0x052d0004
807 #define A2_OPCODE_POP 0x049d0004
809 /* Codes to distinguish the arithmetic instructions. */
820 #define OPCODE_CMP 10
821 #define OPCODE_CMN 11
822 #define OPCODE_ORR 12
823 #define OPCODE_MOV 13
824 #define OPCODE_BIC 14
825 #define OPCODE_MVN 15
827 #define T2_OPCODE_AND 0
828 #define T2_OPCODE_BIC 1
829 #define T2_OPCODE_ORR 2
830 #define T2_OPCODE_ORN 3
831 #define T2_OPCODE_EOR 4
832 #define T2_OPCODE_ADD 8
833 #define T2_OPCODE_ADC 10
834 #define T2_OPCODE_SBC 11
835 #define T2_OPCODE_SUB 13
836 #define T2_OPCODE_RSB 14
838 #define T_OPCODE_MUL 0x4340
839 #define T_OPCODE_TST 0x4200
840 #define T_OPCODE_CMN 0x42c0
841 #define T_OPCODE_NEG 0x4240
842 #define T_OPCODE_MVN 0x43c0
844 #define T_OPCODE_ADD_R3 0x1800
845 #define T_OPCODE_SUB_R3 0x1a00
846 #define T_OPCODE_ADD_HI 0x4400
847 #define T_OPCODE_ADD_ST 0xb000
848 #define T_OPCODE_SUB_ST 0xb080
849 #define T_OPCODE_ADD_SP 0xa800
850 #define T_OPCODE_ADD_PC 0xa000
851 #define T_OPCODE_ADD_I8 0x3000
852 #define T_OPCODE_SUB_I8 0x3800
853 #define T_OPCODE_ADD_I3 0x1c00
854 #define T_OPCODE_SUB_I3 0x1e00
856 #define T_OPCODE_ASR_R 0x4100
857 #define T_OPCODE_LSL_R 0x4080
858 #define T_OPCODE_LSR_R 0x40c0
859 #define T_OPCODE_ROR_R 0x41c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe000
891 #define THUMB_SIZE 2 /* Size of thumb instruction. */
892 #define THUMB_PP_PC_LR 0x0100
893 #define THUMB_LOAD_BIT 0x0800
894 #define THUMB2_LOAD_BIT 0x00100000
896 #define BAD_SYNTAX _("syntax error")
897 #define BAD_ARGS _("bad arguments to instruction")
898 #define BAD_SP _("r13 not allowed here")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_ODD _("Odd register not allowed here")
901 #define BAD_EVEN _("Even register not allowed here")
902 #define BAD_COND _("instruction cannot be conditional")
903 #define BAD_OVERLAP _("registers may not be the same")
904 #define BAD_HIREG _("lo register required")
905 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907 #define BAD_BRANCH _("branch must be last instruction in IT block")
908 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909 #define BAD_NO_VPT _("instruction not allowed in VPT block")
910 #define BAD_NOT_IT _("instruction not allowed in IT block")
911 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912 #define BAD_FPU _("selected FPU does not support instruction")
913 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914 #define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916 #define BAD_IT_COND _("incorrect condition in IT block")
917 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
919 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920 #define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922 #define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924 #define BAD_RANGE _("branch out of range")
925 #define BAD_FP16 _("selected processor does not support fp16 instruction")
926 #define BAD_BF16 _("selected processor does not support bf16 instruction")
927 #define BAD_CDE _("selected processor does not support cde instruction")
928 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
933 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
935 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
937 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
939 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940 #define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945 #define BAD_EL_TYPE _("bad element type for instruction")
946 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
948 static htab_t arm_ops_hsh
;
949 static htab_t arm_cond_hsh
;
950 static htab_t arm_vcond_hsh
;
951 static htab_t arm_shift_hsh
;
952 static htab_t arm_psr_hsh
;
953 static htab_t arm_v7m_psr_hsh
;
954 static htab_t arm_reg_hsh
;
955 static htab_t arm_reloc_hsh
;
956 static htab_t arm_barrier_opt_hsh
;
958 /* Stuff needed to resolve the label ambiguity
967 symbolS
* last_label_seen
;
968 static int label_is_thumb_function_name
= FALSE
;
970 /* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
973 #define MAX_LITERAL_POOL_SIZE 1024
974 typedef struct literal_pool
976 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
977 unsigned int next_free_entry
;
983 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
985 struct literal_pool
* next
;
986 unsigned int alignment
;
989 /* Pointer to a linked list of literal pools. */
990 literal_pool
* list_of_pools
= NULL
;
992 typedef enum asmfunc_states
995 WAITING_ASMFUNC_NAME
,
999 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1002 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1004 static struct current_pred now_pred
;
1008 now_pred_compatible (int cond
)
1010 return (cond
& ~1) == (now_pred
.cc
& ~1);
1014 conditional_insn (void)
1016 return inst
.cond
!= COND_ALWAYS
;
1019 static int in_pred_block (void);
1021 static int handle_pred_state (void);
1023 static void force_automatic_it_block_close (void);
1025 static void it_fsm_post_encode (void);
1027 #define set_pred_insn_type(type) \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1036 #define set_pred_insn_type_nonvoid(type, failret) \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1045 #define set_pred_insn_type_last() \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1055 /* Toggle value[pos]. */
1056 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1060 /* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062 char arm_comment_chars
[] = "@";
1064 /* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067 /* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070 /* Also note that comments like this one will always work. */
1071 const char line_comment_chars
[] = "#";
1073 char arm_line_separator_chars
[] = ";";
1075 /* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077 const char EXP_CHARS
[] = "eE";
1079 /* Chars that mean this number is a floating point constant. */
1080 /* As in 0f12.456 */
1081 /* or 0d1.2345e12 */
1083 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1085 /* Prefix characters that indicate the start of an immediate
1087 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1089 /* Separator character handling. */
1091 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1093 enum fp_16bit_format
1095 ARM_FP16_FORMAT_IEEE
= 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1097 ARM_FP16_FORMAT_DEFAULT
= 0x3
1100 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1104 skip_past_char (char ** str
, char c
)
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str
);
1118 #define skip_past_comma(str) skip_past_char (str, ',')
1120 /* Arithmetic expressions (possibly involving symbols). */
1122 /* Return TRUE if anything in the expression is a bignum. */
1125 walk_no_bignums (symbolS
* sp
)
1127 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1130 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 || (symbol_get_value_expression (sp
)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1140 static bfd_boolean in_my_get_expression
= FALSE
;
1142 /* Third argument to my_get_expression. */
1143 #define GE_NO_PREFIX 0
1144 #define GE_IMM_PREFIX 1
1145 #define GE_OPT_PREFIX 2
1146 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148 #define GE_OPT_PREFIX_BIG 3
1151 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1155 /* In unified syntax, all prefixes are optional. */
1157 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1160 switch (prefix_mode
)
1162 case GE_NO_PREFIX
: break;
1164 if (!is_immediate_prefix (**str
))
1166 inst
.error
= _("immediate expression requires a # prefix");
1172 case GE_OPT_PREFIX_BIG
:
1173 if (is_immediate_prefix (**str
))
1180 memset (ep
, 0, sizeof (expressionS
));
1182 save_in
= input_line_pointer
;
1183 input_line_pointer
= *str
;
1184 in_my_get_expression
= TRUE
;
1186 in_my_get_expression
= FALSE
;
1188 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str
= input_line_pointer
;
1192 input_line_pointer
= save_in
;
1193 if (inst
.error
== NULL
)
1194 inst
.error
= (ep
->X_op
== O_absent
1195 ? _("missing expression") :_("bad expression"));
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1203 && (ep
->X_op
== O_big
1204 || (ep
->X_add_symbol
1205 && (walk_no_bignums (ep
->X_add_symbol
)
1207 && walk_no_bignums (ep
->X_op_symbol
))))))
1209 inst
.error
= _("invalid constant");
1210 *str
= input_line_pointer
;
1211 input_line_pointer
= save_in
;
1215 *str
= input_line_pointer
;
1216 input_line_pointer
= save_in
;
1220 /* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1235 md_atof (int type
, char * litP
, int * sizeP
)
1238 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1254 FLONUM_TYPE generic_float
;
1256 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1259 input_line_pointer
= t
;
1261 return _("invalid floating point number");
1263 switch (generic_float
.sign
)
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1291 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1321 return _("Unrecognized or unsupported floating point constant");
1324 t
= atof_ieee (input_line_pointer
, type
, words
);
1326 input_line_pointer
= t
;
1327 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1329 if (target_big_endian
|| prec
== 1)
1330 for (i
= 0; i
< prec
; i
++)
1332 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1333 litP
+= sizeof (LITTLENUM_TYPE
);
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1336 for (i
= prec
- 1; i
>= 0; i
--)
1338 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1339 litP
+= sizeof (LITTLENUM_TYPE
);
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i
= 0; i
< prec
; i
+= 2)
1346 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1347 sizeof (LITTLENUM_TYPE
));
1348 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1349 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1350 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1356 /* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1360 md_operand (expressionS
* exp
)
1362 if (in_my_get_expression
)
1363 exp
->X_op
= O_illegal
;
1366 /* Immediate values. */
1369 /* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1374 immediate_for_directive (int *val
)
1377 exp
.X_op
= O_illegal
;
1379 if (is_immediate_prefix (*input_line_pointer
))
1381 input_line_pointer
++;
1385 if (exp
.X_op
!= O_constant
)
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1391 *val
= exp
.X_add_number
;
1396 /* Register parsing. */
1398 /* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1403 static struct reg_entry
*
1404 arm_reg_parse_multi (char **ccp
)
1408 struct reg_entry
*reg
;
1410 skip_whitespace (start
);
1412 #ifdef REGISTER_PREFIX
1413 if (*start
!= REGISTER_PREFIX
)
1417 #ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1423 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1428 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1430 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1440 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1441 enum arm_reg_type type
)
1443 /* Alternative syntaxes are accepted for a few register classes. */
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg
&& reg
->type
== REG_TYPE_CN
)
1456 /* For backward compatibility, a bare number is valid here. */
1458 unsigned long processor
= strtoul (start
, ccp
, 10);
1459 if (*ccp
!= start
&& processor
<= 15)
1464 case REG_TYPE_MMXWC
:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1478 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1482 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1485 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1492 if (reg
&& reg
->type
== type
)
1495 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1502 /* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1510 Can all be legally parsed by this function.
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1517 parse_neon_type (struct neon_type
*type
, char **str
)
1524 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1526 enum neon_el_type thistype
= NT_untyped
;
1527 unsigned thissize
= -1u;
1534 /* Just a size without an explicit type. */
1538 switch (TOLOWER (*ptr
))
1540 case 'i': thistype
= NT_integer
; break;
1541 case 'f': thistype
= NT_float
; break;
1542 case 'p': thistype
= NT_poly
; break;
1543 case 's': thistype
= NT_signed
; break;
1544 case 'u': thistype
= NT_unsigned
; break;
1546 thistype
= NT_float
;
1551 thistype
= NT_bfloat
;
1552 switch (TOLOWER (*(++ptr
)))
1556 thissize
= strtoul (ptr
, &ptr
, 10);
1559 as_bad (_("bad size %d in type specifier"), thissize
);
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1585 thissize
= strtoul (ptr
, &ptr
, 10);
1587 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1590 as_bad (_("bad size %d in type specifier"), thissize
);
1598 type
->el
[type
->elems
].type
= thistype
;
1599 type
->el
[type
->elems
].size
= thissize
;
1604 /* Empty/missing type is not a successful parse. */
1605 if (type
->elems
== 0)
1613 /* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1619 first_error (const char *err
)
1625 /* Parse a single type, e.g. ".s32", leading period included. */
1627 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1630 struct neon_type optype
;
1634 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1636 if (optype
.elems
== 1)
1637 *vectype
= optype
.el
[0];
1640 first_error (_("only one type should be specified for operand"));
1646 first_error (_("vector type expected"));
1658 /* Special meanings for indices (which have a range of 0-7), which will fit into
1661 #define NEON_ALL_LANES 15
1662 #define NEON_INTERLEAVE_LANES 14
1664 /* Record a use of the given feature. */
1666 record_feature_use (const arm_feature_set
*feature
)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1674 /* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1677 mark_feature_used (const arm_feature_set
*feature
)
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1682 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1683 && ARM_CPU_IS_ANY (cpu_variant
))
1685 first_error (BAD_MVE_AUTO
);
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1692 /* Add the appropriate architecture feature for the barrier option used.
1694 record_feature_use (feature
);
1699 /* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1705 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1706 enum arm_reg_type
*rtype
,
1707 struct neon_typed_alias
*typeinfo
)
1710 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1711 struct neon_typed_alias atype
;
1712 struct neon_type_el parsetype
;
1716 atype
.eltype
.type
= NT_invtype
;
1717 atype
.eltype
.size
= -1;
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1723 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type
== REG_TYPE_NDQ
1733 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1734 || (type
== REG_TYPE_VFSD
1735 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1736 || (type
== REG_TYPE_NSDQ
1737 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1738 || reg
->type
== REG_TYPE_NQ
))
1739 || (type
== REG_TYPE_NSD
1740 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1741 || (type
== REG_TYPE_MMXWC
1742 && (reg
->type
== REG_TYPE_MMXWCG
)))
1743 type
= (enum arm_reg_type
) reg
->type
;
1745 if (type
== REG_TYPE_MQ
)
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1750 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1753 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1755 first_error (_("expected MVE register [q0..q7]"));
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1761 && (type
== REG_TYPE_NQ
))
1765 if (type
!= reg
->type
)
1771 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1773 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1775 first_error (_("can't redefine type for operand"));
1778 atype
.defined
|= NTA_HASTYPE
;
1779 atype
.eltype
= parsetype
;
1782 if (skip_past_char (&str
, '[') == SUCCESS
)
1784 if (type
!= REG_TYPE_VFD
1785 && !(type
== REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1787 && !(type
== REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1791 first_error (_("only D and Q registers may be indexed"));
1793 first_error (_("only D registers may be indexed"));
1797 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1799 first_error (_("can't change index for operand"));
1803 atype
.defined
|= NTA_HASINDEX
;
1805 if (skip_past_char (&str
, ']') == SUCCESS
)
1806 atype
.index
= NEON_ALL_LANES
;
1811 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1813 if (exp
.X_op
!= O_constant
)
1815 first_error (_("constant expression required"));
1819 if (skip_past_char (&str
, ']') == FAIL
)
1822 atype
.index
= exp
.X_add_number
;
1837 /* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1845 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1846 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1848 struct neon_typed_alias atype
;
1850 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1855 /* Do not allow regname(... to parse as a register. */
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1862 first_error (_("register operand expected, but got scalar"));
1867 *vectype
= atype
.eltype
;
1874 #define NEON_SCALAR_REG(X) ((X) >> 4)
1875 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1877 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1882 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1883 arm_reg_type reg_type
)
1887 struct neon_typed_alias atype
;
1890 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1908 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1911 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1913 first_error (_("scalar must have an index"));
1916 else if (atype
.index
>= reg_size
/ elsize
)
1918 first_error (_("scalar index out of range"));
1923 *type
= atype
.eltype
;
1927 return reg
* 16 + atype
.index
;
1930 /* Types of registers in a list. */
1943 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1946 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1952 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1957 skip_whitespace (str
);
1970 const char apsr_str
[] = "apsr";
1971 int apsr_str_len
= strlen (apsr_str
);
1973 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1974 if (etype
== REGLIST_CLRM
)
1976 if (reg
== REG_SP
|| reg
== REG_PC
)
1978 else if (reg
== FAIL
1979 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1980 && !ISALPHA (*(str
+ apsr_str_len
)))
1983 str
+= apsr_str_len
;
1988 first_error (_("r0-r12, lr or APSR expected"));
1992 else /* etype == REGLIST_RN. */
1996 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2007 first_error (_("bad range in register list"));
2011 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2013 if (range
& (1 << i
))
2015 (_("Warning: duplicated register (r%d) in register list"),
2023 if (range
& (1 << reg
))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2026 else if (reg
<= cur_reg
)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2032 while (skip_past_comma (&str
) != FAIL
2033 || (in_range
= 1, *str
++ == '-'));
2036 if (skip_past_char (&str
, '}') == FAIL
)
2038 first_error (_("missing `}'"));
2042 else if (etype
== REGLIST_RN
)
2046 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2049 if (exp
.X_op
== O_constant
)
2051 if (exp
.X_add_number
2052 != (exp
.X_add_number
& 0x0000ffff))
2054 inst
.error
= _("invalid register mask");
2058 if ((range
& exp
.X_add_number
) != 0)
2060 int regno
= range
& exp
.X_add_number
;
2063 regno
= (1 << regno
) - 1;
2065 (_("Warning: duplicated register (r%d) in register list"),
2069 range
|= exp
.X_add_number
;
2073 if (inst
.relocs
[0].type
!= 0)
2075 inst
.error
= _("expression too complex");
2079 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2080 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2081 inst
.relocs
[0].pc_rel
= 0;
2085 if (*str
== '|' || *str
== '+')
2091 while (another_range
);
2097 /* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2113 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2114 bfd_boolean
*partial_match
)
2119 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2123 unsigned long mask
= 0;
2125 bfd_boolean vpr_seen
= FALSE
;
2126 bfd_boolean expect_vpr
=
2127 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2129 if (skip_past_char (&str
, '{') == FAIL
)
2131 inst
.error
= _("expecting {");
2138 case REGLIST_VFP_S_VPR
:
2139 regtype
= REG_TYPE_VFS
;
2144 case REGLIST_VFP_D_VPR
:
2145 regtype
= REG_TYPE_VFD
;
2148 case REGLIST_NEON_D
:
2149 regtype
= REG_TYPE_NDQ
;
2156 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2173 base_reg
= max_regs
;
2174 *partial_match
= FALSE
;
2178 unsigned int setmask
= 1, addregs
= 1;
2179 const char vpr_str
[] = "vpr";
2180 size_t vpr_str_len
= strlen (vpr_str
);
2182 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2186 if (new_base
== FAIL
2187 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2188 && !ISALPHA (*(str
+ vpr_str_len
))
2194 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2198 first_error (_("VPR expected last"));
2201 else if (new_base
== FAIL
)
2203 if (regtype
== REG_TYPE_VFS
)
2204 first_error (_("VFP single precision register or VPR "
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2212 else if (new_base
== FAIL
)
2214 first_error (_(reg_expected_msgs
[regtype
]));
2218 *partial_match
= TRUE
;
2222 if (new_base
>= max_regs
)
2224 first_error (_("register out of range in list"));
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype
== REG_TYPE_NQ
)
2235 if (new_base
< base_reg
)
2236 base_reg
= new_base
;
2238 if (mask
& (setmask
<< new_base
))
2240 first_error (_("invalid register list"));
2244 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2246 as_tsktsk (_("register list not in ascending order"));
2250 mask
|= setmask
<< new_base
;
2253 if (*str
== '-') /* We have the start of a range expression */
2259 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2262 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2266 if (high_range
>= max_regs
)
2268 first_error (_("register out of range in list"));
2272 if (regtype
== REG_TYPE_NQ
)
2273 high_range
= high_range
+ 1;
2275 if (high_range
<= new_base
)
2277 inst
.error
= _("register range not in ascending order");
2281 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2283 if (mask
& (setmask
<< new_base
))
2285 inst
.error
= _("invalid register list");
2289 mask
|= setmask
<< new_base
;
2294 while (skip_past_comma (&str
) != FAIL
);
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2304 if (expect_vpr
&& !vpr_seen
)
2306 first_error (_("VPR expected last"));
2310 /* Final test -- the registers must be consecutive. */
2312 for (i
= 0; i
< count
; i
++)
2314 if ((mask
& (1u << i
)) == 0)
2316 inst
.error
= _("non-contiguous register range");
2326 /* True if two alias types are the same. */
2329 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2337 if (a
->defined
!= b
->defined
)
2340 if ((a
->defined
& NTA_HASTYPE
) != 0
2341 && (a
->eltype
.type
!= b
->eltype
.type
2342 || a
->eltype
.size
!= b
->eltype
.size
))
2345 if ((a
->defined
& NTA_HASINDEX
) != 0
2346 && (a
->index
!= b
->index
))
2352 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2360 #define NEON_LANE(X) ((X) & 0xf)
2361 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2365 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2367 struct neon_type_el
*eltype
)
2374 int leading_brace
= 0;
2375 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2376 const char *const incr_error
= mve
? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error
= _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype
;
2380 firsttype
.defined
= 0;
2381 firsttype
.eltype
.type
= NT_invtype
;
2382 firsttype
.eltype
.size
= -1;
2383 firsttype
.index
= -1;
2385 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2390 struct neon_typed_alias atype
;
2392 rtype
= REG_TYPE_MQ
;
2393 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2397 first_error (_(reg_expected_msgs
[rtype
]));
2404 if (rtype
== REG_TYPE_NQ
)
2410 else if (reg_incr
== -1)
2412 reg_incr
= getreg
- base_reg
;
2413 if (reg_incr
< 1 || reg_incr
> 2)
2415 first_error (_(incr_error
));
2419 else if (getreg
!= base_reg
+ reg_incr
* count
)
2421 first_error (_(incr_error
));
2425 if (! neon_alias_types_same (&atype
, &firsttype
))
2427 first_error (_(type_error
));
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2435 struct neon_typed_alias htype
;
2436 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2438 lane
= NEON_INTERLEAVE_LANES
;
2439 else if (lane
!= NEON_INTERLEAVE_LANES
)
2441 first_error (_(type_error
));
2446 else if (reg_incr
!= 1)
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2452 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2455 first_error (_(reg_expected_msgs
[rtype
]));
2458 if (! neon_alias_types_same (&htype
, &firsttype
))
2460 first_error (_(type_error
));
2463 count
+= hireg
+ dregs
- getreg
;
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype
== REG_TYPE_NQ
)
2474 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2478 else if (lane
!= atype
.index
)
2480 first_error (_(type_error
));
2484 else if (lane
== -1)
2485 lane
= NEON_INTERLEAVE_LANES
;
2486 else if (lane
!= NEON_INTERLEAVE_LANES
)
2488 first_error (_(type_error
));
2493 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2495 /* No lane set by [x]. We must be interleaving structures. */
2497 lane
= NEON_INTERLEAVE_LANES
;
2500 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2501 || (count
> 1 && reg_incr
== -1))
2503 first_error (_("error parsing element/structure list"));
2507 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2509 first_error (_("expected }"));
2517 *eltype
= firsttype
.eltype
;
2522 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2525 /* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2532 parse_reloc (char **str
)
2534 struct reloc_entry
*r
;
2538 return BFD_RELOC_UNUSED
;
2543 while (*q
&& *q
!= ')' && *q
!= ',')
2548 if ((r
= (struct reloc_entry
*)
2549 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2556 /* Directives: register aliases. */
2558 static struct reg_entry
*
2559 insert_reg_alias (char *str
, unsigned number
, int type
)
2561 struct reg_entry
*new_reg
;
2564 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2566 if (new_reg
->builtin
)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2569 /* Only warn about a redefinition if it's not defined as the
2571 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2577 name
= xstrdup (str
);
2578 new_reg
= XNEW (struct reg_entry
);
2580 new_reg
->name
= name
;
2581 new_reg
->number
= number
;
2582 new_reg
->type
= type
;
2583 new_reg
->builtin
= FALSE
;
2584 new_reg
->neon
= NULL
;
2586 str_hash_insert (arm_reg_hsh
, name
, new_reg
, 0);
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
2887 = (struct reg_entry
*) str_hash_find (arm_reg_hsh
, name
);
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 str_hash_delete (arm_reg_hsh
, name
);
2900 free ((char *) reg
->name
);
2904 /* Also locate the all upper case and all lower case versions.
2905 Do not complain if we cannot find one or the other as it
2906 was probably deleted above. */
2908 nbuf
= strdup (name
);
2909 for (p
= nbuf
; *p
; p
++)
2911 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2914 str_hash_delete (arm_reg_hsh
, nbuf
);
2915 free ((char *) reg
->name
);
2920 for (p
= nbuf
; *p
; p
++)
2922 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2925 str_hash_delete (arm_reg_hsh
, nbuf
);
2926 free ((char *) reg
->name
);
2935 *input_line_pointer
= saved_char
;
2936 demand_empty_rest_of_line ();
2939 /* Directives: Instruction set selection. */
2942 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2943 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2944 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2945 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947 /* Create a new mapping symbol for the transition to STATE. */
2950 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2953 const char * symname
;
2960 type
= BSF_NO_FLAGS
;
2964 type
= BSF_NO_FLAGS
;
2968 type
= BSF_NO_FLAGS
;
2974 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2975 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2980 THUMB_SET_FUNC (symbolP
, 0);
2981 ARM_SET_THUMB (symbolP
, 0);
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 THUMB_SET_FUNC (symbolP
, 1);
2987 ARM_SET_THUMB (symbolP
, 1);
2988 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2996 /* Save the mapping symbols for future reference. Also check that
2997 we do not place two mapping symbols at the same offset within a
2998 frag. We'll handle overlap between frags in
2999 check_mapping_symbols.
3001 If .fill or other data filling directive generates zero sized data,
3002 the mapping symbol for the following code will have the same value
3003 as the one generated for the data filling directive. In this case,
3004 we replace the old symbol with the new one at the same address. */
3007 if (frag
->tc_frag_data
.first_map
!= NULL
)
3009 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3010 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3012 frag
->tc_frag_data
.first_map
= symbolP
;
3014 if (frag
->tc_frag_data
.last_map
!= NULL
)
3016 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3017 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3018 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3020 frag
->tc_frag_data
.last_map
= symbolP
;
3023 /* We must sometimes convert a region marked as code to data during
3024 code alignment, if an odd number of bytes have to be padded. The
3025 code mapping symbol is pushed to an aligned address. */
3028 insert_data_mapping_symbol (enum mstate state
,
3029 valueT value
, fragS
*frag
, offsetT bytes
)
3031 /* If there was already a mapping symbol, remove it. */
3032 if (frag
->tc_frag_data
.last_map
!= NULL
3033 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3035 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3039 know (frag
->tc_frag_data
.first_map
== symp
);
3040 frag
->tc_frag_data
.first_map
= NULL
;
3042 frag
->tc_frag_data
.last_map
= NULL
;
3043 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3046 make_mapping_symbol (MAP_DATA
, value
, frag
);
3047 make_mapping_symbol (state
, value
+ bytes
, frag
);
3050 static void mapping_state_2 (enum mstate state
, int max_chars
);
3052 /* Set the mapping state to STATE. Only call this when about to
3053 emit some STATE bytes to the file. */
3055 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057 mapping_state (enum mstate state
)
3059 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3068 All ARM instructions require 4-byte alignment.
3069 (Almost) all Thumb instructions require 2-byte alignment.
3071 When emitting instructions into any section, mark the section
3074 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3075 but themselves require 2-byte alignment; this applies to some
3076 PC- relative forms. However, these cases will involve implicit
3077 literal pool generation or an explicit .align >=2, both of
3078 which will cause the section to me marked with sufficient
3079 alignment. Thus, we don't handle those cases here. */
3080 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3082 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3083 /* This case will be evaluated later. */
3086 mapping_state_2 (state
, 0);
3089 /* Same as mapping_state, but MAX_CHARS bytes have already been
3090 allocated. Put the mapping symbol that far back. */
3093 mapping_state_2 (enum mstate state
, int max_chars
)
3095 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3097 if (!SEG_NORMAL (now_seg
))
3100 if (mapstate
== state
)
3101 /* The mapping symbol has already been emitted.
3102 There is nothing else to do. */
3105 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3106 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3108 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3109 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3112 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3115 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3116 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3120 #define mapping_state(x) ((void)0)
3121 #define mapping_state_2(x, y) ((void)0)
3124 /* Find the real, Thumb encoded start of a Thumb function. */
3128 find_real_start (symbolS
* symbolP
)
3131 const char * name
= S_GET_NAME (symbolP
);
3132 symbolS
* new_target
;
3134 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3135 #define STUB_NAME ".real_start_of"
3140 /* The compiler may generate BL instructions to local labels because
3141 it needs to perform a branch to a far away location. These labels
3142 do not have a corresponding ".real_start_of" label. We check
3143 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3144 the ".real_start_of" convention for nonlocal branches. */
3145 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3148 real_start
= concat (STUB_NAME
, name
, NULL
);
3149 new_target
= symbol_find (real_start
);
3152 if (new_target
== NULL
)
3154 as_warn (_("Failed to find real start of function: %s\n"), name
);
3155 new_target
= symbolP
;
3163 opcode_select (int width
)
3170 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3171 as_bad (_("selected processor does not support THUMB opcodes"));
3174 /* No need to force the alignment, since we will have been
3175 coming from ARM mode, which is word-aligned. */
3176 record_alignment (now_seg
, 1);
3183 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3184 as_bad (_("selected processor does not support ARM opcodes"));
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 1);
3196 as_bad (_("invalid instruction size selected (%d)"), width
);
3201 s_arm (int ignore ATTRIBUTE_UNUSED
)
3204 demand_empty_rest_of_line ();
3208 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 demand_empty_rest_of_line ();
3215 s_code (int unused ATTRIBUTE_UNUSED
)
3219 temp
= get_absolute_expression ();
3224 opcode_select (temp
);
3228 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3233 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3235 /* If we are not already in thumb mode go into it, EVEN if
3236 the target processor does not support thumb instructions.
3237 This is used by gcc/config/arm/lib1funcs.asm for example
3238 to compile interworking support functions even if the
3239 target processor should not support interworking. */
3243 record_alignment (now_seg
, 1);
3246 demand_empty_rest_of_line ();
3250 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3254 /* The following label is the name/address of the start of a Thumb function.
3255 We need to know this for the interworking support. */
3256 label_is_thumb_function_name
= TRUE
;
3259 /* Perform a .set directive, but also mark the alias as
3260 being a thumb function. */
3263 s_thumb_set (int equiv
)
3265 /* XXX the following is a duplicate of the code for s_set() in read.c
3266 We cannot just call that code as we need to get at the symbol that
3273 /* Especial apologies for the random logic:
3274 This just grew, and could be parsed much more simply!
3276 delim
= get_symbol_name (& name
);
3277 end_name
= input_line_pointer
;
3278 (void) restore_line_pointer (delim
);
3280 if (*input_line_pointer
!= ',')
3283 as_bad (_("expected comma after name \"%s\""), name
);
3285 ignore_rest_of_line ();
3289 input_line_pointer
++;
3292 if (name
[0] == '.' && name
[1] == '\0')
3294 /* XXX - this should not happen to .thumb_set. */
3298 if ((symbolP
= symbol_find (name
)) == NULL
3299 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3302 /* When doing symbol listings, play games with dummy fragments living
3303 outside the normal fragment chain to record the file and line info
3305 if (listing
& LISTING_SYMBOLS
)
3307 extern struct list_info_struct
* listing_tail
;
3308 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3310 memset (dummy_frag
, 0, sizeof (fragS
));
3311 dummy_frag
->fr_type
= rs_fill
;
3312 dummy_frag
->line
= listing_tail
;
3313 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3314 dummy_frag
->fr_symbol
= symbolP
;
3318 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3321 /* "set" symbols are local unless otherwise specified. */
3322 SF_SET_LOCAL (symbolP
);
3323 #endif /* OBJ_COFF */
3324 } /* Make a new symbol. */
3326 symbol_table_insert (symbolP
);
3331 && S_IS_DEFINED (symbolP
)
3332 && S_GET_SEGMENT (symbolP
) != reg_section
)
3333 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3335 pseudo_set (symbolP
);
3337 demand_empty_rest_of_line ();
3339 /* XXX Now we come to the Thumb specific bit of code. */
3341 THUMB_SET_FUNC (symbolP
, 1);
3342 ARM_SET_THUMB (symbolP
, 1);
3343 #if defined OBJ_ELF || defined OBJ_COFF
3344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3348 /* Directives: Mode selection. */
3350 /* .syntax [unified|divided] - choose the new unified syntax
3351 (same for Arm and Thumb encoding, modulo slight differences in what
3352 can be represented) or the old divergent syntax for each mode. */
3354 s_syntax (int unused ATTRIBUTE_UNUSED
)
3358 delim
= get_symbol_name (& name
);
3360 if (!strcasecmp (name
, "unified"))
3361 unified_syntax
= TRUE
;
3362 else if (!strcasecmp (name
, "divided"))
3363 unified_syntax
= FALSE
;
3366 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3369 (void) restore_line_pointer (delim
);
3370 demand_empty_rest_of_line ();
3373 /* Directives: sectioning and alignment. */
3376 s_bss (int ignore ATTRIBUTE_UNUSED
)
3378 /* We don't support putting frags in the BSS segment, we fake it by
3379 marking in_bss, then looking at s_skip for clues. */
3380 subseg_set (bss_section
, 0);
3381 demand_empty_rest_of_line ();
3383 #ifdef md_elf_section_change_hook
3384 md_elf_section_change_hook ();
3389 s_even (int ignore ATTRIBUTE_UNUSED
)
3391 /* Never make frag if expect extra pass. */
3393 frag_align (1, 0, 0);
3395 record_alignment (now_seg
, 1);
3397 demand_empty_rest_of_line ();
3400 /* Directives: CodeComposer Studio. */
3402 /* .ref (for CodeComposer Studio syntax only). */
3404 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3406 if (codecomposer_syntax
)
3407 ignore_rest_of_line ();
3409 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3412 /* If name is not NULL, then it is used for marking the beginning of a
3413 function, whereas if it is NULL then it means the function end. */
3415 asmfunc_debug (const char * name
)
3417 static const char * last_name
= NULL
;
3421 gas_assert (last_name
== NULL
);
3424 if (debug_type
== DEBUG_STABS
)
3425 stabs_generate_asm_func (name
, name
);
3429 gas_assert (last_name
!= NULL
);
3431 if (debug_type
== DEBUG_STABS
)
3432 stabs_generate_asm_endfunc (last_name
, last_name
);
3439 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3441 if (codecomposer_syntax
)
3443 switch (asmfunc_state
)
3445 case OUTSIDE_ASMFUNC
:
3446 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3449 case WAITING_ASMFUNC_NAME
:
3450 as_bad (_(".asmfunc repeated."));
3453 case WAITING_ENDASMFUNC
:
3454 as_bad (_(".asmfunc without function."));
3457 demand_empty_rest_of_line ();
3460 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3464 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3466 if (codecomposer_syntax
)
3468 switch (asmfunc_state
)
3470 case OUTSIDE_ASMFUNC
:
3471 as_bad (_(".endasmfunc without a .asmfunc."));
3474 case WAITING_ASMFUNC_NAME
:
3475 as_bad (_(".endasmfunc without function."));
3478 case WAITING_ENDASMFUNC
:
3479 asmfunc_state
= OUTSIDE_ASMFUNC
;
3480 asmfunc_debug (NULL
);
3483 demand_empty_rest_of_line ();
3486 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3490 s_ccs_def (int name
)
3492 if (codecomposer_syntax
)
3495 as_bad (_(".def pseudo-op only available with -mccs flag."));
3498 /* Directives: Literal pools. */
3500 static literal_pool
*
3501 find_literal_pool (void)
3503 literal_pool
* pool
;
3505 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3507 if (pool
->section
== now_seg
3508 && pool
->sub_section
== now_subseg
)
3515 static literal_pool
*
3516 find_or_make_literal_pool (void)
3518 /* Next literal pool ID number. */
3519 static unsigned int latest_pool_num
= 1;
3520 literal_pool
* pool
;
3522 pool
= find_literal_pool ();
3526 /* Create a new pool. */
3527 pool
= XNEW (literal_pool
);
3531 pool
->next_free_entry
= 0;
3532 pool
->section
= now_seg
;
3533 pool
->sub_section
= now_subseg
;
3534 pool
->next
= list_of_pools
;
3535 pool
->symbol
= NULL
;
3536 pool
->alignment
= 2;
3538 /* Add it to the list. */
3539 list_of_pools
= pool
;
3542 /* New pools, and emptied pools, will have a NULL symbol. */
3543 if (pool
->symbol
== NULL
)
3545 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3546 &zero_address_frag
, 0);
3547 pool
->id
= latest_pool_num
++;
3554 /* Add the literal in the global 'inst'
3555 structure to the relevant literal pool. */
3558 add_to_lit_pool (unsigned int nbytes
)
3560 #define PADDING_SLOT 0x1
3561 #define LIT_ENTRY_SIZE_MASK 0xFF
3562 literal_pool
* pool
;
3563 unsigned int entry
, pool_size
= 0;
3564 bfd_boolean padding_slot_p
= FALSE
;
3570 imm1
= inst
.operands
[1].imm
;
3571 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3572 : inst
.relocs
[0].exp
.X_unsigned
? 0
3573 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3574 if (target_big_endian
)
3577 imm2
= inst
.operands
[1].imm
;
3581 pool
= find_or_make_literal_pool ();
3583 /* Check if this literal value is already in the pool. */
3584 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3588 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3589 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
3591 == inst
.relocs
[0].exp
.X_add_number
)
3592 && (pool
->literals
[entry
].X_md
== nbytes
)
3593 && (pool
->literals
[entry
].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3598 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3599 && (pool
->literals
[entry
].X_add_number
3600 == inst
.relocs
[0].exp
.X_add_number
)
3601 && (pool
->literals
[entry
].X_add_symbol
3602 == inst
.relocs
[0].exp
.X_add_symbol
)
3603 && (pool
->literals
[entry
].X_op_symbol
3604 == inst
.relocs
[0].exp
.X_op_symbol
)
3605 && (pool
->literals
[entry
].X_md
== nbytes
))
3608 else if ((nbytes
== 8)
3609 && !(pool_size
& 0x7)
3610 && ((entry
+ 1) != pool
->next_free_entry
)
3611 && (pool
->literals
[entry
].X_op
== O_constant
)
3612 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3613 && (pool
->literals
[entry
].X_unsigned
3614 == inst
.relocs
[0].exp
.X_unsigned
)
3615 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3616 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3617 && (pool
->literals
[entry
+ 1].X_unsigned
3618 == inst
.relocs
[0].exp
.X_unsigned
))
3621 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3622 if (padding_slot_p
&& (nbytes
== 4))
3628 /* Do we need to create a new entry? */
3629 if (entry
== pool
->next_free_entry
)
3631 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3633 inst
.error
= _("literal pool overflow");
3639 /* For 8-byte entries, we align to an 8-byte boundary,
3640 and split it into two 4-byte entries, because on 32-bit
3641 host, 8-byte constants are treated as big num, thus
3642 saved in "generic_bignum" which will be overwritten
3643 by later assignments.
3645 We also need to make sure there is enough space for
3648 We also check to make sure the literal operand is a
3650 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3651 || inst
.relocs
[0].exp
.X_op
== O_big
))
3653 inst
.error
= _("invalid type for literal pool");
3656 else if (pool_size
& 0x7)
3658 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3660 inst
.error
= _("literal pool overflow");
3664 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3665 pool
->literals
[entry
].X_op
= O_constant
;
3666 pool
->literals
[entry
].X_add_number
= 0;
3667 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3668 pool
->next_free_entry
+= 1;
3671 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3673 inst
.error
= _("literal pool overflow");
3677 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3678 pool
->literals
[entry
].X_op
= O_constant
;
3679 pool
->literals
[entry
].X_add_number
= imm1
;
3680 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3681 pool
->literals
[entry
++].X_md
= 4;
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm2
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
].X_md
= 4;
3687 pool
->alignment
= 3;
3688 pool
->next_free_entry
+= 1;
3692 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3693 pool
->literals
[entry
].X_md
= 4;
3697 /* PR ld/12974: Record the location of the first source line to reference
3698 this entry in the literal pool. If it turns out during linking that the
3699 symbol does not exist we will be able to give an accurate line number for
3700 the (first use of the) missing reference. */
3701 if (debug_type
== DEBUG_DWARF2
)
3702 dwarf2_where (pool
->locs
+ entry
);
3704 pool
->next_free_entry
+= 1;
3706 else if (padding_slot_p
)
3708 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3709 pool
->literals
[entry
].X_md
= nbytes
;
3712 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3713 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3714 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3720 tc_start_label_without_colon (void)
3722 bfd_boolean ret
= TRUE
;
3724 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3726 const char *label
= input_line_pointer
;
3728 while (!is_end_of_line
[(int) label
[-1]])
3733 as_bad (_("Invalid label '%s'"), label
);
3737 asmfunc_debug (label
);
3739 asmfunc_state
= WAITING_ENDASMFUNC
;
3745 /* Can't use symbol_new here, so have to create a symbol and then at
3746 a later date assign it a value. That's what these functions do. */
3749 symbol_locate (symbolS
* symbolP
,
3750 const char * name
, /* It is copied, the caller can modify. */
3751 segT segment
, /* Segment identifier (SEG_<something>). */
3752 valueT valu
, /* Symbol value. */
3753 fragS
* frag
) /* Associated fragment. */
3756 char * preserved_copy_of_name
;
3758 name_length
= strlen (name
) + 1; /* +1 for \0. */
3759 obstack_grow (¬es
, name
, name_length
);
3760 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3762 #ifdef tc_canonicalize_symbol_name
3763 preserved_copy_of_name
=
3764 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3767 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3769 S_SET_SEGMENT (symbolP
, segment
);
3770 S_SET_VALUE (symbolP
, valu
);
3771 symbol_clear_list_pointers (symbolP
);
3773 symbol_set_frag (symbolP
, frag
);
3775 /* Link to end of symbol chain. */
3777 extern int symbol_table_frozen
;
3779 if (symbol_table_frozen
)
3783 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3785 obj_symbol_new_hook (symbolP
);
3787 #ifdef tc_symbol_new_hook
3788 tc_symbol_new_hook (symbolP
);
3792 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3793 #endif /* DEBUG_SYMS */
3797 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3800 literal_pool
* pool
;
3803 pool
= find_literal_pool ();
3805 || pool
->symbol
== NULL
3806 || pool
->next_free_entry
== 0)
3809 /* Align pool as you have word accesses.
3810 Only make a frag if we have to. */
3812 frag_align (pool
->alignment
, 0, 0);
3814 record_alignment (now_seg
, 2);
3817 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3818 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3820 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3822 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3823 (valueT
) frag_now_fix (), frag_now
);
3824 symbol_table_insert (pool
->symbol
);
3826 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3828 #if defined OBJ_COFF || defined OBJ_ELF
3829 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3832 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3835 if (debug_type
== DEBUG_DWARF2
)
3836 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3838 /* First output the expression in the instruction to the pool. */
3839 emit_expr (&(pool
->literals
[entry
]),
3840 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3843 /* Mark the pool as empty. */
3844 pool
->next_free_entry
= 0;
3845 pool
->symbol
= NULL
;
3849 /* Forward declarations for functions below, in the MD interface
3851 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3852 static valueT
create_unwind_entry (int);
3853 static void start_unwind_section (const segT
, int);
3854 static void add_unwind_opcode (valueT
, int);
3855 static void flush_pending_unwind (void);
3857 /* Directives: Data. */
3860 s_arm_elf_cons (int nbytes
)
3864 #ifdef md_flush_pending_output
3865 md_flush_pending_output ();
3868 if (is_it_end_of_statement ())
3870 demand_empty_rest_of_line ();
3874 #ifdef md_cons_align
3875 md_cons_align (nbytes
);
3878 mapping_state (MAP_DATA
);
3882 char *base
= input_line_pointer
;
3886 if (exp
.X_op
!= O_symbol
)
3887 emit_expr (&exp
, (unsigned int) nbytes
);
3890 char *before_reloc
= input_line_pointer
;
3891 reloc
= parse_reloc (&input_line_pointer
);
3894 as_bad (_("unrecognized relocation suffix"));
3895 ignore_rest_of_line ();
3898 else if (reloc
== BFD_RELOC_UNUSED
)
3899 emit_expr (&exp
, (unsigned int) nbytes
);
3902 reloc_howto_type
*howto
= (reloc_howto_type
*)
3903 bfd_reloc_type_lookup (stdoutput
,
3904 (bfd_reloc_code_real_type
) reloc
);
3905 int size
= bfd_get_reloc_size (howto
);
3907 if (reloc
== BFD_RELOC_ARM_PLT32
)
3909 as_bad (_("(plt) is only valid on branch targets"));
3910 reloc
= BFD_RELOC_UNUSED
;
3915 as_bad (ngettext ("%s relocations do not fit in %d byte",
3916 "%s relocations do not fit in %d bytes",
3918 howto
->name
, nbytes
);
3921 /* We've parsed an expression stopping at O_symbol.
3922 But there may be more expression left now that we
3923 have parsed the relocation marker. Parse it again.
3924 XXX Surely there is a cleaner way to do this. */
3925 char *p
= input_line_pointer
;
3927 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3929 memcpy (save_buf
, base
, input_line_pointer
- base
);
3930 memmove (base
+ (input_line_pointer
- before_reloc
),
3931 base
, before_reloc
- base
);
3933 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3935 memcpy (base
, save_buf
, p
- base
);
3937 offset
= nbytes
- size
;
3938 p
= frag_more (nbytes
);
3939 memset (p
, 0, nbytes
);
3940 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3941 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3947 while (*input_line_pointer
++ == ',');
3949 /* Put terminator back into stream. */
3950 input_line_pointer
--;
3951 demand_empty_rest_of_line ();
3954 /* Emit an expression containing a 32-bit thumb instruction.
3955 Implementation based on put_thumb32_insn. */
3958 emit_thumb32_expr (expressionS
* exp
)
3960 expressionS exp_high
= *exp
;
3962 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3963 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3964 exp
->X_add_number
&= 0xffff;
3965 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3968 /* Guess the instruction size based on the opcode. */
3971 thumb_insn_size (int opcode
)
3973 if ((unsigned int) opcode
< 0xe800u
)
3975 else if ((unsigned int) opcode
>= 0xe8000000u
)
3982 emit_insn (expressionS
*exp
, int nbytes
)
3986 if (exp
->X_op
== O_constant
)
3991 size
= thumb_insn_size (exp
->X_add_number
);
3995 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3997 as_bad (_(".inst.n operand too big. "\
3998 "Use .inst.w instead"));
4003 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4004 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4006 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4008 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4009 emit_thumb32_expr (exp
);
4011 emit_expr (exp
, (unsigned int) size
);
4013 it_fsm_post_encode ();
4017 as_bad (_("cannot determine Thumb instruction size. " \
4018 "Use .inst.n/.inst.w instead"));
4021 as_bad (_("constant expression required"));
4026 /* Like s_arm_elf_cons but do not use md_cons_align and
4027 set the mapping state to MAP_ARM/MAP_THUMB. */
4030 s_arm_elf_inst (int nbytes
)
4032 if (is_it_end_of_statement ())
4034 demand_empty_rest_of_line ();
4038 /* Calling mapping_state () here will not change ARM/THUMB,
4039 but will ensure not to be in DATA state. */
4042 mapping_state (MAP_THUMB
);
4047 as_bad (_("width suffixes are invalid in ARM mode"));
4048 ignore_rest_of_line ();
4054 mapping_state (MAP_ARM
);
4063 if (! emit_insn (& exp
, nbytes
))
4065 ignore_rest_of_line ();
4069 while (*input_line_pointer
++ == ',');
4071 /* Put terminator back into stream. */
4072 input_line_pointer
--;
4073 demand_empty_rest_of_line ();
4076 /* Parse a .rel31 directive. */
4079 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4086 if (*input_line_pointer
== '1')
4087 highbit
= 0x80000000;
4088 else if (*input_line_pointer
!= '0')
4089 as_bad (_("expected 0 or 1"));
4091 input_line_pointer
++;
4092 if (*input_line_pointer
!= ',')
4093 as_bad (_("missing comma"));
4094 input_line_pointer
++;
4096 #ifdef md_flush_pending_output
4097 md_flush_pending_output ();
4100 #ifdef md_cons_align
4104 mapping_state (MAP_DATA
);
4109 md_number_to_chars (p
, highbit
, 4);
4110 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4111 BFD_RELOC_ARM_PREL31
);
4113 demand_empty_rest_of_line ();
4116 /* Directives: AEABI stack-unwind tables. */
4118 /* Parse an unwind_fnstart directive. Simply records the current location. */
4121 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4123 demand_empty_rest_of_line ();
4124 if (unwind
.proc_start
)
4126 as_bad (_("duplicate .fnstart directive"));
4130 /* Mark the start of the function. */
4131 unwind
.proc_start
= expr_build_dot ();
4133 /* Reset the rest of the unwind info. */
4134 unwind
.opcode_count
= 0;
4135 unwind
.table_entry
= NULL
;
4136 unwind
.personality_routine
= NULL
;
4137 unwind
.personality_index
= -1;
4138 unwind
.frame_size
= 0;
4139 unwind
.fp_offset
= 0;
4140 unwind
.fp_reg
= REG_SP
;
4142 unwind
.sp_restored
= 0;
4146 /* Parse a handlerdata directive. Creates the exception handling table entry
4147 for the function. */
4150 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4152 demand_empty_rest_of_line ();
4153 if (!unwind
.proc_start
)
4154 as_bad (MISSING_FNSTART
);
4156 if (unwind
.table_entry
)
4157 as_bad (_("duplicate .handlerdata directive"));
4159 create_unwind_entry (1);
4162 /* Parse an unwind_fnend directive. Generates the index table entry. */
4165 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4170 unsigned int marked_pr_dependency
;
4172 demand_empty_rest_of_line ();
4174 if (!unwind
.proc_start
)
4176 as_bad (_(".fnend directive without .fnstart"));
4180 /* Add eh table entry. */
4181 if (unwind
.table_entry
== NULL
)
4182 val
= create_unwind_entry (0);
4186 /* Add index table entry. This is two words. */
4187 start_unwind_section (unwind
.saved_seg
, 1);
4188 frag_align (2, 0, 0);
4189 record_alignment (now_seg
, 2);
4191 ptr
= frag_more (8);
4193 where
= frag_now_fix () - 8;
4195 /* Self relative offset of the function start. */
4196 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4197 BFD_RELOC_ARM_PREL31
);
4199 /* Indicate dependency on EHABI-defined personality routines to the
4200 linker, if it hasn't been done already. */
4201 marked_pr_dependency
4202 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4203 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4204 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4206 static const char *const name
[] =
4208 "__aeabi_unwind_cpp_pr0",
4209 "__aeabi_unwind_cpp_pr1",
4210 "__aeabi_unwind_cpp_pr2"
4212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4214 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4215 |= 1 << unwind
.personality_index
;
4219 /* Inline exception table entry. */
4220 md_number_to_chars (ptr
+ 4, val
, 4);
4222 /* Self relative offset of the table entry. */
4223 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4224 BFD_RELOC_ARM_PREL31
);
4226 /* Restore the original section. */
4227 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4229 unwind
.proc_start
= NULL
;
4233 /* Parse an unwind_cantunwind directive. */
4236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4238 demand_empty_rest_of_line ();
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4243 as_bad (_("personality routine specified for cantunwind frame"));
4245 unwind
.personality_index
= -2;
4249 /* Parse a personalityindex directive. */
4252 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4256 if (!unwind
.proc_start
)
4257 as_bad (MISSING_FNSTART
);
4259 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4260 as_bad (_("duplicate .personalityindex directive"));
4264 if (exp
.X_op
!= O_constant
4265 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4267 as_bad (_("bad personality routine number"));
4268 ignore_rest_of_line ();
4272 unwind
.personality_index
= exp
.X_add_number
;
4274 demand_empty_rest_of_line ();
4278 /* Parse a personality directive. */
4281 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4285 if (!unwind
.proc_start
)
4286 as_bad (MISSING_FNSTART
);
4288 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4289 as_bad (_("duplicate .personality directive"));
4291 c
= get_symbol_name (& name
);
4292 p
= input_line_pointer
;
4294 ++ input_line_pointer
;
4295 unwind
.personality_routine
= symbol_find_or_make (name
);
4297 demand_empty_rest_of_line ();
4301 /* Parse a directive saving core registers. */
4304 s_arm_unwind_save_core (void)
4310 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4313 as_bad (_("expected register list"));
4314 ignore_rest_of_line ();
4318 demand_empty_rest_of_line ();
4320 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4321 into .unwind_save {..., sp...}. We aren't bothered about the value of
4322 ip because it is clobbered by calls. */
4323 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4324 && (range
& 0x3000) == 0x1000)
4326 unwind
.opcode_count
--;
4327 unwind
.sp_restored
= 0;
4328 range
= (range
| 0x2000) & ~0x1000;
4329 unwind
.pending_offset
= 0;
4335 /* See if we can use the short opcodes. These pop a block of up to 8
4336 registers starting with r4, plus maybe r14. */
4337 for (n
= 0; n
< 8; n
++)
4339 /* Break at the first non-saved register. */
4340 if ((range
& (1 << (n
+ 4))) == 0)
4343 /* See if there are any other bits set. */
4344 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4346 /* Use the long form. */
4347 op
= 0x8000 | ((range
>> 4) & 0xfff);
4348 add_unwind_opcode (op
, 2);
4352 /* Use the short form. */
4354 op
= 0xa8; /* Pop r14. */
4356 op
= 0xa0; /* Do not pop r14. */
4358 add_unwind_opcode (op
, 1);
4365 op
= 0xb100 | (range
& 0xf);
4366 add_unwind_opcode (op
, 2);
4369 /* Record the number of bytes pushed. */
4370 for (n
= 0; n
< 16; n
++)
4372 if (range
& (1 << n
))
4373 unwind
.frame_size
+= 4;
4378 /* Parse a directive saving FPA registers. */
4381 s_arm_unwind_save_fpa (int reg
)
4387 /* Get Number of registers to transfer. */
4388 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4391 exp
.X_op
= O_illegal
;
4393 if (exp
.X_op
!= O_constant
)
4395 as_bad (_("expected , <constant>"));
4396 ignore_rest_of_line ();
4400 num_regs
= exp
.X_add_number
;
4402 if (num_regs
< 1 || num_regs
> 4)
4404 as_bad (_("number of registers must be in the range [1:4]"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4414 op
= 0xb4 | (num_regs
- 1);
4415 add_unwind_opcode (op
, 1);
4420 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4421 add_unwind_opcode (op
, 2);
4423 unwind
.frame_size
+= num_regs
* 12;
4427 /* Parse a directive saving VFP registers for ARMv6 and above. */
4430 s_arm_unwind_save_vfp_armv6 (void)
4435 int num_vfpv3_regs
= 0;
4436 int num_regs_below_16
;
4437 bfd_boolean partial_match
;
4439 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4443 as_bad (_("expected register list"));
4444 ignore_rest_of_line ();
4448 demand_empty_rest_of_line ();
4450 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4451 than FSTMX/FLDMX-style ones). */
4453 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 num_vfpv3_regs
= count
;
4456 else if (start
+ count
> 16)
4457 num_vfpv3_regs
= start
+ count
- 16;
4459 if (num_vfpv3_regs
> 0)
4461 int start_offset
= start
> 16 ? start
- 16 : 0;
4462 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4463 add_unwind_opcode (op
, 2);
4466 /* Generate opcode for registers numbered in the range 0 .. 15. */
4467 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4468 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4469 if (num_regs_below_16
> 0)
4471 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4472 add_unwind_opcode (op
, 2);
4475 unwind
.frame_size
+= count
* 8;
4479 /* Parse a directive saving VFP registers for pre-ARMv6. */
4482 s_arm_unwind_save_vfp (void)
4487 bfd_boolean partial_match
;
4489 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4493 as_bad (_("expected register list"));
4494 ignore_rest_of_line ();
4498 demand_empty_rest_of_line ();
4503 op
= 0xb8 | (count
- 1);
4504 add_unwind_opcode (op
, 1);
4509 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4510 add_unwind_opcode (op
, 2);
4512 unwind
.frame_size
+= count
* 8 + 4;
4516 /* Parse a directive saving iWMMXt data registers. */
4519 s_arm_unwind_save_mmxwr (void)
4527 if (*input_line_pointer
== '{')
4528 input_line_pointer
++;
4532 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4536 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4541 as_tsktsk (_("register list not in ascending order"));
4544 if (*input_line_pointer
== '-')
4546 input_line_pointer
++;
4547 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4550 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4553 else if (reg
>= hi_reg
)
4555 as_bad (_("bad register range"));
4558 for (; reg
< hi_reg
; reg
++)
4562 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4564 skip_past_char (&input_line_pointer
, '}');
4566 demand_empty_rest_of_line ();
4568 /* Generate any deferred opcodes because we're going to be looking at
4570 flush_pending_unwind ();
4572 for (i
= 0; i
< 16; i
++)
4574 if (mask
& (1 << i
))
4575 unwind
.frame_size
+= 8;
4578 /* Attempt to combine with a previous opcode. We do this because gcc
4579 likes to output separate unwind directives for a single block of
4581 if (unwind
.opcode_count
> 0)
4583 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4584 if ((i
& 0xf8) == 0xc0)
4587 /* Only merge if the blocks are contiguous. */
4590 if ((mask
& 0xfe00) == (1 << 9))
4592 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4593 unwind
.opcode_count
--;
4596 else if (i
== 6 && unwind
.opcode_count
>= 2)
4598 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4602 op
= 0xffff << (reg
- 1);
4604 && ((mask
& op
) == (1u << (reg
- 1))))
4606 op
= (1 << (reg
+ i
+ 1)) - 1;
4607 op
&= ~((1 << reg
) - 1);
4609 unwind
.opcode_count
-= 2;
4616 /* We want to generate opcodes in the order the registers have been
4617 saved, ie. descending order. */
4618 for (reg
= 15; reg
>= -1; reg
--)
4620 /* Save registers in blocks. */
4622 || !(mask
& (1 << reg
)))
4624 /* We found an unsaved reg. Generate opcodes to save the
4631 op
= 0xc0 | (hi_reg
- 10);
4632 add_unwind_opcode (op
, 1);
4637 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4638 add_unwind_opcode (op
, 2);
4647 ignore_rest_of_line ();
4651 s_arm_unwind_save_mmxwcg (void)
4658 if (*input_line_pointer
== '{')
4659 input_line_pointer
++;
4661 skip_whitespace (input_line_pointer
);
4665 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4669 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4675 as_tsktsk (_("register list not in ascending order"));
4678 if (*input_line_pointer
== '-')
4680 input_line_pointer
++;
4681 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4687 else if (reg
>= hi_reg
)
4689 as_bad (_("bad register range"));
4692 for (; reg
< hi_reg
; reg
++)
4696 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4698 skip_past_char (&input_line_pointer
, '}');
4700 demand_empty_rest_of_line ();
4702 /* Generate any deferred opcodes because we're going to be looking at
4704 flush_pending_unwind ();
4706 for (reg
= 0; reg
< 16; reg
++)
4708 if (mask
& (1 << reg
))
4709 unwind
.frame_size
+= 4;
4712 add_unwind_opcode (op
, 2);
4715 ignore_rest_of_line ();
4719 /* Parse an unwind_save directive.
4720 If the argument is non-zero, this is a .vsave directive. */
4723 s_arm_unwind_save (int arch_v6
)
4726 struct reg_entry
*reg
;
4727 bfd_boolean had_brace
= FALSE
;
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 /* Figure out what sort of save we have. */
4733 peek
= input_line_pointer
;
4741 reg
= arm_reg_parse_multi (&peek
);
4745 as_bad (_("register expected"));
4746 ignore_rest_of_line ();
4755 as_bad (_("FPA .unwind_save does not take a register list"));
4756 ignore_rest_of_line ();
4759 input_line_pointer
= peek
;
4760 s_arm_unwind_save_fpa (reg
->number
);
4764 s_arm_unwind_save_core ();
4769 s_arm_unwind_save_vfp_armv6 ();
4771 s_arm_unwind_save_vfp ();
4774 case REG_TYPE_MMXWR
:
4775 s_arm_unwind_save_mmxwr ();
4778 case REG_TYPE_MMXWCG
:
4779 s_arm_unwind_save_mmxwcg ();
4783 as_bad (_(".unwind_save does not support this kind of register"));
4784 ignore_rest_of_line ();
4789 /* Parse an unwind_movsp directive. */
4792 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4798 if (!unwind
.proc_start
)
4799 as_bad (MISSING_FNSTART
);
4801 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4804 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4805 ignore_rest_of_line ();
4809 /* Optional constant. */
4810 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4812 if (immediate_for_directive (&offset
) == FAIL
)
4818 demand_empty_rest_of_line ();
4820 if (reg
== REG_SP
|| reg
== REG_PC
)
4822 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4826 if (unwind
.fp_reg
!= REG_SP
)
4827 as_bad (_("unexpected .unwind_movsp directive"));
4829 /* Generate opcode to restore the value. */
4831 add_unwind_opcode (op
, 1);
4833 /* Record the information for later. */
4834 unwind
.fp_reg
= reg
;
4835 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4836 unwind
.sp_restored
= 1;
4839 /* Parse an unwind_pad directive. */
4842 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4846 if (!unwind
.proc_start
)
4847 as_bad (MISSING_FNSTART
);
4849 if (immediate_for_directive (&offset
) == FAIL
)
4854 as_bad (_("stack increment must be multiple of 4"));
4855 ignore_rest_of_line ();
4859 /* Don't generate any opcodes, just record the details for later. */
4860 unwind
.frame_size
+= offset
;
4861 unwind
.pending_offset
+= offset
;
4863 demand_empty_rest_of_line ();
4866 /* Parse an unwind_setfp directive. */
4869 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4875 if (!unwind
.proc_start
)
4876 as_bad (MISSING_FNSTART
);
4878 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4879 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4882 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4886 as_bad (_("expected <reg>, <reg>"));
4887 ignore_rest_of_line ();
4891 /* Optional constant. */
4892 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4894 if (immediate_for_directive (&offset
) == FAIL
)
4900 demand_empty_rest_of_line ();
4902 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4904 as_bad (_("register must be either sp or set by a previous"
4905 "unwind_movsp directive"));
4909 /* Don't generate any opcodes, just record the information for later. */
4910 unwind
.fp_reg
= fp_reg
;
4912 if (sp_reg
== REG_SP
)
4913 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4915 unwind
.fp_offset
-= offset
;
4918 /* Parse an unwind_raw directive. */
4921 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4924 /* This is an arbitrary limit. */
4925 unsigned char op
[16];
4928 if (!unwind
.proc_start
)
4929 as_bad (MISSING_FNSTART
);
4932 if (exp
.X_op
== O_constant
4933 && skip_past_comma (&input_line_pointer
) != FAIL
)
4935 unwind
.frame_size
+= exp
.X_add_number
;
4939 exp
.X_op
= O_illegal
;
4941 if (exp
.X_op
!= O_constant
)
4943 as_bad (_("expected <offset>, <opcode>"));
4944 ignore_rest_of_line ();
4950 /* Parse the opcode. */
4955 as_bad (_("unwind opcode too long"));
4956 ignore_rest_of_line ();
4958 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4960 as_bad (_("invalid unwind opcode"));
4961 ignore_rest_of_line ();
4964 op
[count
++] = exp
.X_add_number
;
4966 /* Parse the next byte. */
4967 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4973 /* Add the opcode bytes in reverse order. */
4975 add_unwind_opcode (op
[count
], 1);
4977 demand_empty_rest_of_line ();
4981 /* Parse a .eabi_attribute directive. */
4984 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4986 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4988 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4989 attributes_set_explicitly
[tag
] = 1;
4992 /* Emit a tls fix for the symbol. */
4995 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4999 #ifdef md_flush_pending_output
5000 md_flush_pending_output ();
5003 #ifdef md_cons_align
5007 /* Since we're just labelling the code, there's no need to define a
5010 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5011 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5012 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5013 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5015 #endif /* OBJ_ELF */
5017 static void s_arm_arch (int);
5018 static void s_arm_object_arch (int);
5019 static void s_arm_cpu (int);
5020 static void s_arm_fpu (int);
5021 static void s_arm_arch_extension (int);
5026 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5033 if (exp
.X_op
== O_symbol
)
5034 exp
.X_op
= O_secrel
;
5036 emit_expr (&exp
, 4);
5038 while (*input_line_pointer
++ == ',');
5040 input_line_pointer
--;
5041 demand_empty_rest_of_line ();
5046 arm_is_largest_exponent_ok (int precision
)
5048 /* precision == 1 ensures that this will only return
5049 true for 16 bit floats. */
5050 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5054 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5058 enum fp_16bit_format new_format
;
5060 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5062 name
= input_line_pointer
;
5063 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5064 input_line_pointer
++;
5066 saved_char
= *input_line_pointer
;
5067 *input_line_pointer
= 0;
5069 if (strcasecmp (name
, "ieee") == 0)
5070 new_format
= ARM_FP16_FORMAT_IEEE
;
5071 else if (strcasecmp (name
, "alternative") == 0)
5072 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5075 as_bad (_("unrecognised float16 format \"%s\""), name
);
5079 /* Only set fp16_format if it is still the default (aka not already
5081 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5082 fp16_format
= new_format
;
5085 if (new_format
!= fp16_format
)
5086 as_warn (_("float16 format cannot be set more than once, ignoring."));
5090 *input_line_pointer
= saved_char
;
5091 ignore_rest_of_line ();
5094 /* This table describes all the machine specific pseudo-ops the assembler
5095 has to support. The fields are:
5096 pseudo-op name without dot
5097 function to call to execute this pseudo-op
5098 Integer arg to pass to the function. */
5100 const pseudo_typeS md_pseudo_table
[] =
5102 /* Never called because '.req' does not start a line. */
5103 { "req", s_req
, 0 },
5104 /* Following two are likewise never called. */
5107 { "unreq", s_unreq
, 0 },
5108 { "bss", s_bss
, 0 },
5109 { "align", s_align_ptwo
, 2 },
5110 { "arm", s_arm
, 0 },
5111 { "thumb", s_thumb
, 0 },
5112 { "code", s_code
, 0 },
5113 { "force_thumb", s_force_thumb
, 0 },
5114 { "thumb_func", s_thumb_func
, 0 },
5115 { "thumb_set", s_thumb_set
, 0 },
5116 { "even", s_even
, 0 },
5117 { "ltorg", s_ltorg
, 0 },
5118 { "pool", s_ltorg
, 0 },
5119 { "syntax", s_syntax
, 0 },
5120 { "cpu", s_arm_cpu
, 0 },
5121 { "arch", s_arm_arch
, 0 },
5122 { "object_arch", s_arm_object_arch
, 0 },
5123 { "fpu", s_arm_fpu
, 0 },
5124 { "arch_extension", s_arm_arch_extension
, 0 },
5126 { "word", s_arm_elf_cons
, 4 },
5127 { "long", s_arm_elf_cons
, 4 },
5128 { "inst.n", s_arm_elf_inst
, 2 },
5129 { "inst.w", s_arm_elf_inst
, 4 },
5130 { "inst", s_arm_elf_inst
, 0 },
5131 { "rel31", s_arm_rel31
, 0 },
5132 { "fnstart", s_arm_unwind_fnstart
, 0 },
5133 { "fnend", s_arm_unwind_fnend
, 0 },
5134 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5135 { "personality", s_arm_unwind_personality
, 0 },
5136 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5137 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5138 { "save", s_arm_unwind_save
, 0 },
5139 { "vsave", s_arm_unwind_save
, 1 },
5140 { "movsp", s_arm_unwind_movsp
, 0 },
5141 { "pad", s_arm_unwind_pad
, 0 },
5142 { "setfp", s_arm_unwind_setfp
, 0 },
5143 { "unwind_raw", s_arm_unwind_raw
, 0 },
5144 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5145 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5149 /* These are used for dwarf. */
5153 /* These are used for dwarf2. */
5154 { "file", dwarf2_directive_file
, 0 },
5155 { "loc", dwarf2_directive_loc
, 0 },
5156 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5158 { "extend", float_cons
, 'x' },
5159 { "ldouble", float_cons
, 'x' },
5160 { "packed", float_cons
, 'p' },
5161 { "bfloat16", float_cons
, 'b' },
5163 {"secrel32", pe_directive_secrel
, 0},
5166 /* These are for compatibility with CodeComposer Studio. */
5167 {"ref", s_ccs_ref
, 0},
5168 {"def", s_ccs_def
, 0},
5169 {"asmfunc", s_ccs_asmfunc
, 0},
5170 {"endasmfunc", s_ccs_endasmfunc
, 0},
5172 {"float16", float_cons
, 'h' },
5173 {"float16_format", set_fp16_format
, 0 },
5178 /* Parser functions used exclusively in instruction operands. */
5180 /* Generic immediate-value read function for use in insn parsing.
5181 STR points to the beginning of the immediate (the leading #);
5182 VAL receives the value; if the value is outside [MIN, MAX]
5183 issue an error. PREFIX_OPT is true if the immediate prefix is
5187 parse_immediate (char **str
, int *val
, int min
, int max
,
5188 bfd_boolean prefix_opt
)
5192 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5193 if (exp
.X_op
!= O_constant
)
5195 inst
.error
= _("constant expression required");
5199 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5201 inst
.error
= _("immediate value out of range");
5205 *val
= exp
.X_add_number
;
5209 /* Less-generic immediate-value read function with the possibility of loading a
5210 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5211 instructions. Puts the result directly in inst.operands[i]. */
5214 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5215 bfd_boolean allow_symbol_p
)
5218 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5221 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5223 if (exp_p
->X_op
== O_constant
)
5225 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5226 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5227 O_constant. We have to be careful not to break compilation for
5228 32-bit X_add_number, though. */
5229 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5231 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5232 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5234 inst
.operands
[i
].regisimm
= 1;
5237 else if (exp_p
->X_op
== O_big
5238 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5240 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5242 /* Bignums have their least significant bits in
5243 generic_bignum[0]. Make sure we put 32 bits in imm and
5244 32 bits in reg, in a (hopefully) portable way. */
5245 gas_assert (parts
!= 0);
5247 /* Make sure that the number is not too big.
5248 PR 11972: Bignums can now be sign-extended to the
5249 size of a .octa so check that the out of range bits
5250 are all zero or all one. */
5251 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5253 LITTLENUM_TYPE m
= -1;
5255 if (generic_bignum
[parts
* 2] != 0
5256 && generic_bignum
[parts
* 2] != m
)
5259 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5260 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5264 inst
.operands
[i
].imm
= 0;
5265 for (j
= 0; j
< parts
; j
++, idx
++)
5266 inst
.operands
[i
].imm
|= ((unsigned) generic_bignum
[idx
]
5267 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5268 inst
.operands
[i
].reg
= 0;
5269 for (j
= 0; j
< parts
; j
++, idx
++)
5270 inst
.operands
[i
].reg
|= ((unsigned) generic_bignum
[idx
]
5271 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5272 inst
.operands
[i
].regisimm
= 1;
5274 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5282 /* Returns the pseudo-register number of an FPA immediate constant,
5283 or FAIL if there isn't a valid constant here. */
5286 parse_fpa_immediate (char ** str
)
5288 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5294 /* First try and match exact strings, this is to guarantee
5295 that some formats will work even for cross assembly. */
5297 for (i
= 0; fp_const
[i
]; i
++)
5299 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5303 *str
+= strlen (fp_const
[i
]);
5304 if (is_end_of_line
[(unsigned char) **str
])
5310 /* Just because we didn't get a match doesn't mean that the constant
5311 isn't valid, just that it is in a format that we don't
5312 automatically recognize. Try parsing it with the standard
5313 expression routines. */
5315 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5317 /* Look for a raw floating point number. */
5318 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5319 && is_end_of_line
[(unsigned char) *save_in
])
5321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5323 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5325 if (words
[j
] != fp_values
[i
][j
])
5329 if (j
== MAX_LITTLENUMS
)
5337 /* Try and parse a more complex expression, this will probably fail
5338 unless the code uses a floating point prefix (eg "0f"). */
5339 save_in
= input_line_pointer
;
5340 input_line_pointer
= *str
;
5341 if (expression (&exp
) == absolute_section
5342 && exp
.X_op
== O_big
5343 && exp
.X_add_number
< 0)
5345 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 #define X_PRECISION 5
5348 #define E_PRECISION 15L
5349 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5351 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5353 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5355 if (words
[j
] != fp_values
[i
][j
])
5359 if (j
== MAX_LITTLENUMS
)
5361 *str
= input_line_pointer
;
5362 input_line_pointer
= save_in
;
5369 *str
= input_line_pointer
;
5370 input_line_pointer
= save_in
;
5371 inst
.error
= _("invalid FPA immediate expression");
5375 /* Returns 1 if a number has "quarter-precision" float format
5376 0baBbbbbbc defgh000 00000000 00000000. */
5379 is_quarter_float (unsigned imm
)
5381 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5382 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5386 /* Detect the presence of a floating point or integer zero constant,
5390 parse_ifimm_zero (char **in
)
5394 if (!is_immediate_prefix (**in
))
5396 /* In unified syntax, all prefixes are optional. */
5397 if (!unified_syntax
)
5403 /* Accept #0x0 as a synonym for #0. */
5404 if (strncmp (*in
, "0x", 2) == 0)
5407 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5412 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5413 &generic_floating_point_number
);
5416 && generic_floating_point_number
.sign
== '+'
5417 && (generic_floating_point_number
.low
5418 > generic_floating_point_number
.leader
))
5424 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5425 0baBbbbbbc defgh000 00000000 00000000.
5426 The zero and minus-zero cases need special handling, since they can't be
5427 encoded in the "quarter-precision" float format, but can nonetheless be
5428 loaded as integer constants. */
5431 parse_qfloat_immediate (char **ccp
, int *immed
)
5435 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5436 int found_fpchar
= 0;
5438 skip_past_char (&str
, '#');
5440 /* We must not accidentally parse an integer as a floating-point number. Make
5441 sure that the value we parse is not an integer by checking for special
5442 characters '.' or 'e'.
5443 FIXME: This is a horrible hack, but doing better is tricky because type
5444 information isn't in a very usable state at parse time. */
5446 skip_whitespace (fpnum
);
5448 if (strncmp (fpnum
, "0x", 2) == 0)
5452 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5453 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5463 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5465 unsigned fpword
= 0;
5468 /* Our FP word must be 32 bits (single-precision FP). */
5469 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5471 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5475 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5488 /* Shift operands. */
5491 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5494 struct asm_shift_name
5497 enum shift_kind kind
;
5500 /* Third argument to parse_shift. */
5501 enum parse_shift_mode
5503 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5504 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5505 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5506 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5507 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5508 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5511 /* Parse a <shift> specifier on an ARM data processing instruction.
5512 This has three forms:
5514 (LSL|LSR|ASL|ASR|ROR) Rs
5515 (LSL|LSR|ASL|ASR|ROR) #imm
5518 Note that ASL is assimilated to LSL in the instruction encoding, and
5519 RRX to ROR #0 (which cannot be written as such). */
5522 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5524 const struct asm_shift_name
*shift_name
;
5525 enum shift_kind shift
;
5530 for (p
= *str
; ISALPHA (*p
); p
++)
5535 inst
.error
= _("shift expression expected");
5540 = (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5543 if (shift_name
== NULL
)
5545 inst
.error
= _("shift expression expected");
5549 shift
= shift_name
->kind
;
5553 case NO_SHIFT_RESTRICT
:
5554 case SHIFT_IMMEDIATE
:
5555 if (shift
== SHIFT_UXTW
)
5557 inst
.error
= _("'UXTW' not allowed here");
5562 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5563 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5565 inst
.error
= _("'LSL' or 'ASR' required");
5570 case SHIFT_LSL_IMMEDIATE
:
5571 if (shift
!= SHIFT_LSL
)
5573 inst
.error
= _("'LSL' required");
5578 case SHIFT_ASR_IMMEDIATE
:
5579 if (shift
!= SHIFT_ASR
)
5581 inst
.error
= _("'ASR' required");
5585 case SHIFT_UXTW_IMMEDIATE
:
5586 if (shift
!= SHIFT_UXTW
)
5588 inst
.error
= _("'UXTW' required");
5596 if (shift
!= SHIFT_RRX
)
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p
);
5601 if (mode
== NO_SHIFT_RESTRICT
5602 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5604 inst
.operands
[i
].imm
= reg
;
5605 inst
.operands
[i
].immisreg
= 1;
5607 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5610 inst
.operands
[i
].shift_kind
= shift
;
5611 inst
.operands
[i
].shifted
= 1;
5616 /* Parse a <shifter_operand> for an ARM data processing instruction:
5619 #<immediate>, <rotate>
5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
5625 is deferred to md_apply_fix. */
5628 parse_shifter_operand (char **str
, int i
)
5633 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5635 inst
.operands
[i
].reg
= value
;
5636 inst
.operands
[i
].isreg
= 1;
5638 /* parse_shift will override this if appropriate */
5639 inst
.relocs
[0].exp
.X_op
= O_constant
;
5640 inst
.relocs
[0].exp
.X_add_number
= 0;
5642 if (skip_past_comma (str
) == FAIL
)
5645 /* Shift operation on register. */
5646 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5649 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5652 if (skip_past_comma (str
) == SUCCESS
)
5654 /* #x, y -- ie explicit rotation by Y. */
5655 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5658 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5660 inst
.error
= _("constant expression expected");
5664 value
= exp
.X_add_number
;
5665 if (value
< 0 || value
> 30 || value
% 2 != 0)
5667 inst
.error
= _("invalid rotation");
5670 if (inst
.relocs
[0].exp
.X_add_number
< 0
5671 || inst
.relocs
[0].exp
.X_add_number
> 255)
5673 inst
.error
= _("invalid constant");
5677 /* Encode as specified. */
5678 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5682 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5683 inst
.relocs
[0].pc_rel
= 0;
5687 /* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5694 struct group_reloc_table_entry
5705 /* Varieties of non-ALU group relocation. */
5713 static struct group_reloc_table_entry group_reloc_table
[] =
5714 { /* Program counter relative: */
5716 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5721 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5726 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5731 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5736 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5740 /* Section base relative */
5742 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5747 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5752 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5757 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5762 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5765 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5766 /* Absolute thumb alu relocations. */
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5788 /* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5796 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5799 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5801 int length
= strlen (group_reloc_table
[i
].name
);
5803 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5804 && (*str
)[length
] == ':')
5806 *out
= &group_reloc_table
[i
];
5807 *str
+= (length
+ 1);
5815 /* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5827 Everything else is as for parse_shifter_operand. */
5829 static parse_operand_result
5830 parse_shifter_operand_group_reloc (char **str
, int i
)
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5836 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5837 || (*str
)[0] == ':')
5839 struct group_reloc_table_entry
*entry
;
5841 if ((*str
)[0] == '#')
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5849 inst
.error
= _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5853 /* We now have the group relocation table entry corresponding to
5854 the name in the assembler source. Next, we parse the expression. */
5855 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5858 /* Record the relocation type (always the ALU variant here). */
5859 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5860 gas_assert (inst
.relocs
[0].type
!= 0);
5862 return PARSE_OPERAND_SUCCESS
;
5865 return parse_shifter_operand (str
, i
) == SUCCESS
5866 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5868 /* Never reached. */
5871 /* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875 static parse_operand_result
5876 parse_neon_alignment (char **str
, int i
)
5881 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5883 if (exp
.X_op
!= O_constant
)
5885 inst
.error
= _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL
;
5889 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5890 inst
.operands
[i
].immisalign
= 1;
5891 /* Alignments are not pre-indexes. */
5892 inst
.operands
[i
].preind
= 0;
5895 return PARSE_OPERAND_SUCCESS
;
5898 /* Parse all forms of an ARM address expression. Information is written
5899 to inst.operands[i] and/or inst.relocs[0].
5901 Preindexed addressing (.preind=1):
5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5906 .shift_kind=shift .relocs[0].exp=shift_imm
5908 These three may have a trailing ! which causes .writeback to be set also.
5910 Postindexed addressing (.postind=1, .writeback=1):
5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5915 .shift_kind=shift .relocs[0].exp=shift_imm
5917 Unindexed addressing (.preind=0, .postind=0):
5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5923 [Rn]{!} shorthand for [Rn,#0]{!}
5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5927 It is the caller's responsibility to check for addressing modes not
5928 supported by the instruction, and to set inst.relocs[0].type. */
5930 static parse_operand_result
5931 parse_address_main (char **str
, int i
, int group_relocations
,
5932 group_reloc_type group_type
)
5937 if (skip_past_char (&p
, '[') == FAIL
)
5939 if (skip_past_char (&p
, '=') == FAIL
)
5941 /* Bare address - translate to PC-relative offset. */
5942 inst
.relocs
[0].pc_rel
= 1;
5943 inst
.operands
[i
].reg
= REG_PC
;
5944 inst
.operands
[i
].isreg
= 1;
5945 inst
.operands
[i
].preind
= 1;
5947 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5948 return PARSE_OPERAND_FAIL
;
5950 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5951 /*allow_symbol_p=*/TRUE
))
5952 return PARSE_OPERAND_FAIL
;
5955 return PARSE_OPERAND_SUCCESS
;
5958 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5959 skip_whitespace (p
);
5961 if (group_type
== GROUP_MVE
)
5963 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5964 struct neon_type_el et
;
5965 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5967 inst
.operands
[i
].isquad
= 1;
5969 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5971 inst
.error
= BAD_ADDR_MODE
;
5972 return PARSE_OPERAND_FAIL
;
5975 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5977 if (group_type
== GROUP_MVE
)
5978 inst
.error
= BAD_ADDR_MODE
;
5980 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5981 return PARSE_OPERAND_FAIL
;
5983 inst
.operands
[i
].reg
= reg
;
5984 inst
.operands
[i
].isreg
= 1;
5986 if (skip_past_comma (&p
) == SUCCESS
)
5988 inst
.operands
[i
].preind
= 1;
5991 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5993 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5994 struct neon_type_el et
;
5995 if (group_type
== GROUP_MVE
5996 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5998 inst
.operands
[i
].immisreg
= 2;
5999 inst
.operands
[i
].imm
= reg
;
6001 if (skip_past_comma (&p
) == SUCCESS
)
6003 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6005 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6006 inst
.relocs
[0].exp
.X_add_number
= 0;
6009 return PARSE_OPERAND_FAIL
;
6012 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6014 inst
.operands
[i
].imm
= reg
;
6015 inst
.operands
[i
].immisreg
= 1;
6017 if (skip_past_comma (&p
) == SUCCESS
)
6018 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6019 return PARSE_OPERAND_FAIL
;
6021 else if (skip_past_char (&p
, ':') == SUCCESS
)
6023 /* FIXME: '@' should be used here, but it's filtered out by generic
6024 code before we get to see it here. This may be subject to
6026 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6028 if (result
!= PARSE_OPERAND_SUCCESS
)
6033 if (inst
.operands
[i
].negative
)
6035 inst
.operands
[i
].negative
= 0;
6039 if (group_relocations
6040 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6042 struct group_reloc_table_entry
*entry
;
6044 /* Skip over the #: or : sequence. */
6050 /* Try to parse a group relocation. Anything else is an
6052 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6054 inst
.error
= _("unknown group relocation");
6055 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6058 /* We now have the group relocation table entry corresponding to
6059 the name in the assembler source. Next, we parse the
6061 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6062 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6064 /* Record the relocation type. */
6069 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6074 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6079 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6086 if (inst
.relocs
[0].type
== 0)
6088 inst
.error
= _("this group relocation is not allowed on this instruction");
6089 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6096 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6097 return PARSE_OPERAND_FAIL
;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
6099 if (inst
.relocs
[0].exp
.X_op
== O_constant
6100 && inst
.relocs
[0].exp
.X_add_number
== 0)
6102 skip_whitespace (q
);
6106 skip_whitespace (q
);
6109 inst
.operands
[i
].negative
= 1;
6114 else if (skip_past_char (&p
, ':') == SUCCESS
)
6116 /* FIXME: '@' should be used here, but it's filtered out by generic code
6117 before we get to see it here. This may be subject to change. */
6118 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6120 if (result
!= PARSE_OPERAND_SUCCESS
)
6124 if (skip_past_char (&p
, ']') == FAIL
)
6126 inst
.error
= _("']' expected");
6127 return PARSE_OPERAND_FAIL
;
6130 if (skip_past_char (&p
, '!') == SUCCESS
)
6131 inst
.operands
[i
].writeback
= 1;
6133 else if (skip_past_comma (&p
) == SUCCESS
)
6135 if (skip_past_char (&p
, '{') == SUCCESS
)
6137 /* [Rn], {expr} - unindexed, with option */
6138 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6139 0, 255, TRUE
) == FAIL
)
6140 return PARSE_OPERAND_FAIL
;
6142 if (skip_past_char (&p
, '}') == FAIL
)
6144 inst
.error
= _("'}' expected at end of 'option' field");
6145 return PARSE_OPERAND_FAIL
;
6147 if (inst
.operands
[i
].preind
)
6149 inst
.error
= _("cannot combine index with option");
6150 return PARSE_OPERAND_FAIL
;
6153 return PARSE_OPERAND_SUCCESS
;
6157 inst
.operands
[i
].postind
= 1;
6158 inst
.operands
[i
].writeback
= 1;
6160 if (inst
.operands
[i
].preind
)
6162 inst
.error
= _("cannot combine pre- and post-indexing");
6163 return PARSE_OPERAND_FAIL
;
6167 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6169 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6170 struct neon_type_el et
;
6171 if (group_type
== GROUP_MVE
6172 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6174 inst
.operands
[i
].immisreg
= 2;
6175 inst
.operands
[i
].imm
= reg
;
6177 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6179 /* We might be using the immediate for alignment already. If we
6180 are, OR the register number into the low-order bits. */
6181 if (inst
.operands
[i
].immisalign
)
6182 inst
.operands
[i
].imm
|= reg
;
6184 inst
.operands
[i
].imm
= reg
;
6185 inst
.operands
[i
].immisreg
= 1;
6187 if (skip_past_comma (&p
) == SUCCESS
)
6188 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6189 return PARSE_OPERAND_FAIL
;
6195 if (inst
.operands
[i
].negative
)
6197 inst
.operands
[i
].negative
= 0;
6200 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6201 return PARSE_OPERAND_FAIL
;
6202 /* If the offset is 0, find out if it's a +0 or -0. */
6203 if (inst
.relocs
[0].exp
.X_op
== O_constant
6204 && inst
.relocs
[0].exp
.X_add_number
== 0)
6206 skip_whitespace (q
);
6210 skip_whitespace (q
);
6213 inst
.operands
[i
].negative
= 1;
6219 /* If at this point neither .preind nor .postind is set, we have a
6220 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6221 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6223 inst
.operands
[i
].preind
= 1;
6224 inst
.relocs
[0].exp
.X_op
= O_constant
;
6225 inst
.relocs
[0].exp
.X_add_number
= 0;
6228 return PARSE_OPERAND_SUCCESS
;
6232 parse_address (char **str
, int i
)
6234 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6238 static parse_operand_result
6239 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6241 return parse_address_main (str
, i
, 1, type
);
6244 /* Parse an operand for a MOVW or MOVT instruction. */
6246 parse_half (char **str
)
6251 skip_past_char (&p
, '#');
6252 if (strncasecmp (p
, ":lower16:", 9) == 0)
6253 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6254 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6255 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6257 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6260 skip_whitespace (p
);
6263 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6266 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6268 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6270 inst
.error
= _("constant expression expected");
6273 if (inst
.relocs
[0].exp
.X_add_number
< 0
6274 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6276 inst
.error
= _("immediate value out of range");
6284 /* Miscellaneous. */
6286 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6287 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6289 parse_psr (char **str
, bfd_boolean lhs
)
6292 unsigned long psr_field
;
6293 const struct asm_psr
*psr
;
6295 bfd_boolean is_apsr
= FALSE
;
6296 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6298 /* PR gas/12698: If the user has specified -march=all then m_profile will
6299 be TRUE, but we want to ignore it in this case as we are building for any
6300 CPU type, including non-m variants. */
6301 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6304 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6305 feature for ease of use and backwards compatibility. */
6307 if (strncasecmp (p
, "SPSR", 4) == 0)
6310 goto unsupported_psr
;
6312 psr_field
= SPSR_BIT
;
6314 else if (strncasecmp (p
, "CPSR", 4) == 0)
6317 goto unsupported_psr
;
6321 else if (strncasecmp (p
, "APSR", 4) == 0)
6323 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6324 and ARMv7-R architecture CPUs. */
6333 while (ISALNUM (*p
) || *p
== '_');
6335 if (strncasecmp (start
, "iapsr", 5) == 0
6336 || strncasecmp (start
, "eapsr", 5) == 0
6337 || strncasecmp (start
, "xpsr", 4) == 0
6338 || strncasecmp (start
, "psr", 3) == 0)
6339 p
= start
+ strcspn (start
, "rR") + 1;
6341 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6347 /* If APSR is being written, a bitfield may be specified. Note that
6348 APSR itself is handled above. */
6349 if (psr
->field
<= 3)
6351 psr_field
= psr
->field
;
6357 /* M-profile MSR instructions have the mask field set to "10", except
6358 *PSR variants which modify APSR, which may use a different mask (and
6359 have been handled already). Do that by setting the PSR_f field
6361 return psr
->field
| (lhs
? PSR_f
: 0);
6364 goto unsupported_psr
;
6370 /* A suffix follows. */
6376 while (ISALNUM (*p
) || *p
== '_');
6380 /* APSR uses a notation for bits, rather than fields. */
6381 unsigned int nzcvq_bits
= 0;
6382 unsigned int g_bit
= 0;
6385 for (bit
= start
; bit
!= p
; bit
++)
6387 switch (TOLOWER (*bit
))
6390 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6394 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6398 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6402 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6406 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6410 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6414 inst
.error
= _("unexpected bit specified after APSR");
6419 if (nzcvq_bits
== 0x1f)
6424 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6426 inst
.error
= _("selected processor does not "
6427 "support DSP extension");
6434 if ((nzcvq_bits
& 0x20) != 0
6435 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6436 || (g_bit
& 0x2) != 0)
6438 inst
.error
= _("bad bitmask specified after APSR");
6444 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6449 psr_field
|= psr
->field
;
6455 goto error
; /* Garbage after "[CS]PSR". */
6457 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6458 is deprecated, but allow it anyway. */
6462 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6465 else if (!m_profile
)
6466 /* These bits are never right for M-profile devices: don't set them
6467 (only code paths which read/write APSR reach here). */
6468 psr_field
|= (PSR_c
| PSR_f
);
6474 inst
.error
= _("selected processor does not support requested special "
6475 "purpose register");
6479 inst
.error
= _("flag for {c}psr instruction expected");
6484 parse_sys_vldr_vstr (char **str
)
6493 {"FPSCR", 0x1, 0x0},
6494 {"FPSCR_nzcvqc", 0x2, 0x0},
6497 {"FPCXTNS", 0x6, 0x1},
6498 {"FPCXTS", 0x7, 0x1}
6500 char *op_end
= strchr (*str
, ',');
6501 size_t op_strlen
= op_end
- *str
;
6503 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6505 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6507 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6516 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6517 value suitable for splatting into the AIF field of the instruction. */
6520 parse_cps_flags (char **str
)
6529 case '\0': case ',':
6532 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6533 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6534 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6537 inst
.error
= _("unrecognized CPS flag");
6542 if (saw_a_flag
== 0)
6544 inst
.error
= _("missing CPS flags");
6552 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6553 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6556 parse_endian_specifier (char **str
)
6561 if (strncasecmp (s
, "BE", 2))
6563 else if (strncasecmp (s
, "LE", 2))
6567 inst
.error
= _("valid endian specifiers are be or le");
6571 if (ISALNUM (s
[2]) || s
[2] == '_')
6573 inst
.error
= _("valid endian specifiers are be or le");
6578 return little_endian
;
6581 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6582 value suitable for poking into the rotate field of an sxt or sxta
6583 instruction, or FAIL on error. */
6586 parse_ror (char **str
)
6591 if (strncasecmp (s
, "ROR", 3) == 0)
6595 inst
.error
= _("missing rotation field after comma");
6599 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6604 case 0: *str
= s
; return 0x0;
6605 case 8: *str
= s
; return 0x1;
6606 case 16: *str
= s
; return 0x2;
6607 case 24: *str
= s
; return 0x3;
6610 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6615 /* Parse a conditional code (from conds[] below). The value returned is in the
6616 range 0 .. 14, or FAIL. */
6618 parse_cond (char **str
)
6621 const struct asm_cond
*c
;
6623 /* Condition codes are always 2 characters, so matching up to
6624 3 characters is sufficient. */
6629 while (ISALPHA (*q
) && n
< 3)
6631 cond
[n
] = TOLOWER (*q
);
6636 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6639 inst
.error
= _("condition required");
6647 /* Parse an option for a barrier instruction. Returns the encoding for the
6650 parse_barrier (char **str
)
6653 const struct asm_barrier_opt
*o
;
6656 while (ISALPHA (*q
))
6659 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6664 if (!mark_feature_used (&o
->arch
))
6671 /* Parse the operands of a table branch instruction. Similar to a memory
6674 parse_tb (char **str
)
6679 if (skip_past_char (&p
, '[') == FAIL
)
6681 inst
.error
= _("'[' expected");
6685 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6687 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6690 inst
.operands
[0].reg
= reg
;
6692 if (skip_past_comma (&p
) == FAIL
)
6694 inst
.error
= _("',' expected");
6698 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6703 inst
.operands
[0].imm
= reg
;
6705 if (skip_past_comma (&p
) == SUCCESS
)
6707 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6709 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6711 inst
.error
= _("invalid shift");
6714 inst
.operands
[0].shifted
= 1;
6717 if (skip_past_char (&p
, ']') == FAIL
)
6719 inst
.error
= _("']' expected");
6726 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6727 information on the types the operands can take and how they are encoded.
6728 Up to four operands may be read; this function handles setting the
6729 ".present" field for each read operand itself.
6730 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6731 else returns FAIL. */
6734 parse_neon_mov (char **str
, int *which_operand
)
6736 int i
= *which_operand
, val
;
6737 enum arm_reg_type rtype
;
6739 struct neon_type_el optype
;
6741 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6743 /* Cases 17 or 19. */
6744 inst
.operands
[i
].reg
= val
;
6745 inst
.operands
[i
].isvec
= 1;
6746 inst
.operands
[i
].isscalar
= 2;
6747 inst
.operands
[i
].vectype
= optype
;
6748 inst
.operands
[i
++].present
= 1;
6750 if (skip_past_comma (&ptr
) == FAIL
)
6753 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6755 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6756 inst
.operands
[i
].reg
= val
;
6757 inst
.operands
[i
].isreg
= 1;
6758 inst
.operands
[i
].present
= 1;
6760 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6763 inst
.operands
[i
].reg
= val
;
6764 inst
.operands
[i
].isvec
= 1;
6765 inst
.operands
[i
].isscalar
= 2;
6766 inst
.operands
[i
].vectype
= optype
;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6775 inst
.operands
[i
].reg
= val
;
6776 inst
.operands
[i
].isreg
= 1;
6777 inst
.operands
[i
++].present
= 1;
6779 if (skip_past_comma (&ptr
) == FAIL
)
6782 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6785 inst
.operands
[i
].reg
= val
;
6786 inst
.operands
[i
].isreg
= 1;
6787 inst
.operands
[i
].present
= 1;
6791 first_error (_("expected ARM or MVE vector register"));
6795 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6797 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6798 inst
.operands
[i
].reg
= val
;
6799 inst
.operands
[i
].isscalar
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
++].present
= 1;
6803 if (skip_past_comma (&ptr
) == FAIL
)
6806 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6809 inst
.operands
[i
].reg
= val
;
6810 inst
.operands
[i
].isreg
= 1;
6811 inst
.operands
[i
].present
= 1;
6813 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6815 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6818 /* Cases 0, 1, 2, 3, 5 (D only). */
6819 if (skip_past_comma (&ptr
) == FAIL
)
6822 inst
.operands
[i
].reg
= val
;
6823 inst
.operands
[i
].isreg
= 1;
6824 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6825 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].vectype
= optype
;
6828 inst
.operands
[i
++].present
= 1;
6830 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6832 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6833 Case 13: VMOV <Sd>, <Rm> */
6834 inst
.operands
[i
].reg
= val
;
6835 inst
.operands
[i
].isreg
= 1;
6836 inst
.operands
[i
].present
= 1;
6838 if (rtype
== REG_TYPE_NQ
)
6840 first_error (_("can't use Neon quad register here"));
6843 else if (rtype
!= REG_TYPE_VFS
)
6846 if (skip_past_comma (&ptr
) == FAIL
)
6848 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6850 inst
.operands
[i
].reg
= val
;
6851 inst
.operands
[i
].isreg
= 1;
6852 inst
.operands
[i
].present
= 1;
6855 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6857 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6861 Case 1: VMOV<c><q> <Dd>, <Dm>
6862 Case 8: VMOV.F32 <Sd>, <Sm>
6863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6865 inst
.operands
[i
].reg
= val
;
6866 inst
.operands
[i
].isreg
= 1;
6867 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6868 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6869 inst
.operands
[i
].isvec
= 1;
6870 inst
.operands
[i
].vectype
= optype
;
6871 inst
.operands
[i
].present
= 1;
6873 if (skip_past_comma (&ptr
) == SUCCESS
)
6878 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6881 inst
.operands
[i
].reg
= val
;
6882 inst
.operands
[i
].isreg
= 1;
6883 inst
.operands
[i
++].present
= 1;
6885 if (skip_past_comma (&ptr
) == FAIL
)
6888 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6891 inst
.operands
[i
].reg
= val
;
6892 inst
.operands
[i
].isreg
= 1;
6893 inst
.operands
[i
].present
= 1;
6896 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6899 Case 10: VMOV.F32 <Sd>, #<imm>
6900 Case 11: VMOV.F64 <Dd>, #<imm> */
6901 inst
.operands
[i
].immisfloat
= 1;
6902 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6904 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6905 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6909 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6913 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6915 /* Cases 6, 7, 16, 18. */
6916 inst
.operands
[i
].reg
= val
;
6917 inst
.operands
[i
].isreg
= 1;
6918 inst
.operands
[i
++].present
= 1;
6920 if (skip_past_comma (&ptr
) == FAIL
)
6923 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6925 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6926 inst
.operands
[i
].reg
= val
;
6927 inst
.operands
[i
].isscalar
= 2;
6928 inst
.operands
[i
].present
= 1;
6929 inst
.operands
[i
].vectype
= optype
;
6931 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6933 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6934 inst
.operands
[i
].reg
= val
;
6935 inst
.operands
[i
].isscalar
= 1;
6936 inst
.operands
[i
].present
= 1;
6937 inst
.operands
[i
].vectype
= optype
;
6939 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6941 inst
.operands
[i
].reg
= val
;
6942 inst
.operands
[i
].isreg
= 1;
6943 inst
.operands
[i
++].present
= 1;
6945 if (skip_past_comma (&ptr
) == FAIL
)
6948 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6951 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6953 inst
.operands
[i
].reg
= val
;
6954 inst
.operands
[i
].isreg
= 1;
6955 inst
.operands
[i
].isvec
= 1;
6956 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6957 inst
.operands
[i
].vectype
= optype
;
6958 inst
.operands
[i
].present
= 1;
6960 if (rtype
== REG_TYPE_VFS
)
6964 if (skip_past_comma (&ptr
) == FAIL
)
6966 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6969 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6972 inst
.operands
[i
].reg
= val
;
6973 inst
.operands
[i
].isreg
= 1;
6974 inst
.operands
[i
].isvec
= 1;
6975 inst
.operands
[i
].issingle
= 1;
6976 inst
.operands
[i
].vectype
= optype
;
6977 inst
.operands
[i
].present
= 1;
6982 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6986 inst
.operands
[i
].reg
= val
;
6987 inst
.operands
[i
].isvec
= 1;
6988 inst
.operands
[i
].isscalar
= 2;
6989 inst
.operands
[i
].vectype
= optype
;
6990 inst
.operands
[i
++].present
= 1;
6992 if (skip_past_comma (&ptr
) == FAIL
)
6995 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6998 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7001 inst
.operands
[i
].reg
= val
;
7002 inst
.operands
[i
].isvec
= 1;
7003 inst
.operands
[i
].isscalar
= 2;
7004 inst
.operands
[i
].vectype
= optype
;
7005 inst
.operands
[i
].present
= 1;
7009 first_error (_("VFP single, double or MVE vector register"
7015 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7019 inst
.operands
[i
].reg
= val
;
7020 inst
.operands
[i
].isreg
= 1;
7021 inst
.operands
[i
].isvec
= 1;
7022 inst
.operands
[i
].issingle
= 1;
7023 inst
.operands
[i
].vectype
= optype
;
7024 inst
.operands
[i
].present
= 1;
7029 first_error (_("parse error"));
7033 /* Successfully parsed the operands. Update args. */
7039 first_error (_("expected comma"));
7043 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7047 /* Use this macro when the operand constraints are different
7048 for ARM and THUMB (e.g. ldrd). */
7049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7050 ((arm_operand) | ((thumb_operand) << 16))
7052 /* Matcher codes for parse_operands. */
7053 enum operand_parse_code
7055 OP_stop
, /* end of line */
7057 OP_RR
, /* ARM register */
7058 OP_RRnpc
, /* ARM register, not r15 */
7059 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7060 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7061 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7062 optional trailing ! */
7063 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7064 OP_RCP
, /* Coprocessor number */
7065 OP_RCN
, /* Coprocessor register */
7066 OP_RF
, /* FPA register */
7067 OP_RVS
, /* VFP single precision register */
7068 OP_RVD
, /* VFP double precision register (0..15) */
7069 OP_RND
, /* Neon double precision register (0..31) */
7070 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7071 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7073 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7075 OP_RNQ
, /* Neon quad precision register */
7076 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7077 OP_RVSD
, /* VFP single or double precision register */
7078 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7079 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7080 OP_RNSD
, /* Neon single or double precision register */
7081 OP_RNDQ
, /* Neon double or quad precision register */
7082 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7083 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7084 OP_RNSDQ
, /* Neon single, double or quad precision register */
7085 OP_RNSC
, /* Neon scalar D[X] */
7086 OP_RVC
, /* VFP control register */
7087 OP_RMF
, /* Maverick F register */
7088 OP_RMD
, /* Maverick D register */
7089 OP_RMFX
, /* Maverick FX register */
7090 OP_RMDX
, /* Maverick DX register */
7091 OP_RMAX
, /* Maverick AX register */
7092 OP_RMDS
, /* Maverick DSPSC register */
7093 OP_RIWR
, /* iWMMXt wR register */
7094 OP_RIWC
, /* iWMMXt wC register */
7095 OP_RIWG
, /* iWMMXt wCG register */
7096 OP_RXA
, /* XScale accumulator register */
7098 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7099 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7101 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7103 OP_RMQ
, /* MVE vector register. */
7104 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7105 OP_RMQRR
, /* MVE vector or ARM register. */
7107 /* New operands for Armv8.1-M Mainline. */
7108 OP_LR
, /* ARM LR register */
7109 OP_RRe
, /* ARM register, only even numbered. */
7110 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7111 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7112 OP_RR_ZR
, /* ARM register or ZR but no PC */
7114 OP_REGLST
, /* ARM register list */
7115 OP_CLRMLST
, /* CLRM register list */
7116 OP_VRSLST
, /* VFP single-precision register list */
7117 OP_VRDLST
, /* VFP double-precision register list */
7118 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7119 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7120 OP_NSTRLST
, /* Neon element/structure list */
7121 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7122 OP_MSTRLST2
, /* MVE vector list with two elements. */
7123 OP_MSTRLST4
, /* MVE vector list with four elements. */
7125 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7126 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7127 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7128 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7130 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7131 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7132 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7133 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7135 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7136 scalar, or ARM register. */
7137 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7138 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7139 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7141 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7142 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7143 OP_VMOV
, /* Neon VMOV operands. */
7144 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7145 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7147 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7148 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7150 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7151 OP_VLDR
, /* VLDR operand. */
7153 OP_I0
, /* immediate zero */
7154 OP_I7
, /* immediate value 0 .. 7 */
7155 OP_I15
, /* 0 .. 15 */
7156 OP_I16
, /* 1 .. 16 */
7157 OP_I16z
, /* 0 .. 16 */
7158 OP_I31
, /* 0 .. 31 */
7159 OP_I31w
, /* 0 .. 31, optional trailing ! */
7160 OP_I32
, /* 1 .. 32 */
7161 OP_I32z
, /* 0 .. 32 */
7162 OP_I48_I64
, /* 48 or 64 */
7163 OP_I63
, /* 0 .. 63 */
7164 OP_I63s
, /* -64 .. 63 */
7165 OP_I64
, /* 1 .. 64 */
7166 OP_I64z
, /* 0 .. 64 */
7167 OP_I127
, /* 0 .. 127 */
7168 OP_I255
, /* 0 .. 255 */
7169 OP_I511
, /* 0 .. 511 */
7170 OP_I4095
, /* 0 .. 4095 */
7171 OP_I8191
, /* 0 .. 8191 */
7172 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7173 OP_I7b
, /* 0 .. 7 */
7174 OP_I15b
, /* 0 .. 15 */
7175 OP_I31b
, /* 0 .. 31 */
7177 OP_SH
, /* shifter operand */
7178 OP_SHG
, /* shifter operand with possible group relocation */
7179 OP_ADDR
, /* Memory address expression (any mode) */
7180 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7181 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7182 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7183 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7184 OP_EXP
, /* arbitrary expression */
7185 OP_EXPi
, /* same, with optional immediate prefix */
7186 OP_EXPr
, /* same, with optional relocation suffix */
7187 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7188 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7189 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7190 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7192 OP_CPSF
, /* CPS flags */
7193 OP_ENDI
, /* Endianness specifier */
7194 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7195 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7196 OP_COND
, /* conditional code */
7197 OP_TB
, /* Table branch. */
7199 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7201 OP_RRnpc_I0
, /* ARM register or literal 0 */
7202 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7203 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7204 OP_RF_IF
, /* FPA register or immediate */
7205 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7206 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7208 /* Optional operands. */
7209 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7210 OP_oI31b
, /* 0 .. 31 */
7211 OP_oI32b
, /* 1 .. 32 */
7212 OP_oI32z
, /* 0 .. 32 */
7213 OP_oIffffb
, /* 0 .. 65535 */
7214 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7216 OP_oRR
, /* ARM register */
7217 OP_oLR
, /* ARM LR register */
7218 OP_oRRnpc
, /* ARM register, not the PC */
7219 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7220 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7221 OP_oRND
, /* Optional Neon double precision register */
7222 OP_oRNQ
, /* Optional Neon quad precision register */
7223 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7224 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7225 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7226 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7228 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7230 OP_oSHll
, /* LSL immediate */
7231 OP_oSHar
, /* ASR immediate */
7232 OP_oSHllar
, /* LSL or ASR immediate */
7233 OP_oROR
, /* ROR 0/8/16/24 */
7234 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7236 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7240 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7241 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7243 OP_FIRST_OPTIONAL
= OP_oI7b
7246 /* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7251 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7253 unsigned const int *upat
= pattern
;
7254 char *backtrack_pos
= 0;
7255 const char *backtrack_error
= 0;
7256 int i
, val
= 0, backtrack_index
= 0;
7257 enum arm_reg_type rtype
;
7258 parse_operand_result result
;
7259 unsigned int op_parse_code
;
7260 bfd_boolean partial_match
;
7262 #define po_char_or_fail(chr) \
7265 if (skip_past_char (&str, chr) == FAIL) \
7270 #define po_reg_or_fail(regtype) \
7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7274 & inst.operands[i].vectype); \
7277 first_error (_(reg_expected_msgs[regtype])); \
7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7291 #define po_reg_or_goto(regtype, label) \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7304 || rtype == REG_TYPE_VFD \
7305 || rtype == REG_TYPE_NQ); \
7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7310 #define po_imm_or_fail(min, max, popt) \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7315 inst.operands[i].imm = val; \
7319 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7326 inst.error = _("constant expression required"); \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7334 inst.operands[i].imm = exp.X_add_number; \
7338 #define po_scalar_or_goto(elsz, label, reg_type) \
7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7350 #define po_misc_or_fail(expr) \
7358 #define po_misc_or_fail_no_backtrack(expr) \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7369 #define po_barrier_or_imm(str) \
7372 val = parse_barrier (&str); \
7373 if (val == FAIL && ! ISALPHA (*str)) \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7387 skip_whitespace (str
);
7389 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7391 op_parse_code
= upat
[i
];
7392 if (op_parse_code
>= 1<<16)
7393 op_parse_code
= thumb
? (op_parse_code
>> 16)
7394 : (op_parse_code
& ((1<<16)-1));
7396 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7398 /* Remember where we are in case we need to backtrack. */
7399 backtrack_pos
= str
;
7400 backtrack_error
= inst
.error
;
7401 backtrack_index
= i
;
7404 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7405 po_char_or_fail (',');
7407 switch (op_parse_code
)
7419 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7420 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7421 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7422 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7423 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7424 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7427 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7431 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7435 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7438 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7440 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7442 /* Also accept generic coprocessor regs for unknown registers. */
7444 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7446 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7447 existing register with a value of 0, this seems like the
7448 best way to parse P0. */
7450 if (strncasecmp (str
, "P0", 2) == 0)
7453 inst
.operands
[i
].isreg
= 1;
7454 inst
.operands
[i
].reg
= 13;
7459 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7460 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7461 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7462 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7463 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7464 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7465 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7466 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7467 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7468 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7471 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7474 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7475 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7477 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7482 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7486 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7488 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7491 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7493 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7497 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7500 po_reg_or_fail (REG_TYPE_MQ
);
7503 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7505 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7510 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7513 po_reg_or_fail (REG_TYPE_NSDQ
);
7517 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7521 po_reg_or_fail (REG_TYPE_MQ
);
7523 /* Neon scalar. Using an element size of 8 means that some invalid
7524 scalars are accepted here, so deal with those in later code. */
7525 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7529 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7532 po_imm_or_fail (0, 0, TRUE
);
7537 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7541 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7546 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7549 if (parse_ifimm_zero (&str
))
7550 inst
.operands
[i
].imm
= 0;
7554 = _("only floating point zero is allowed as immediate value");
7562 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7565 po_reg_or_fail (REG_TYPE_RN
);
7569 case OP_RNSDQ_RNSC_MQ_RR
:
7570 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7573 case OP_RNSDQ_RNSC_MQ
:
7574 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7579 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7583 po_reg_or_fail (REG_TYPE_NSDQ
);
7590 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7593 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7596 po_reg_or_fail (REG_TYPE_NSD
);
7600 case OP_RNDQMQ_RNSC_RR
:
7601 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7604 case OP_RNDQ_RNSC_RR
:
7605 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7607 case OP_RNDQMQ_RNSC
:
7608 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7613 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7616 po_reg_or_fail (REG_TYPE_NDQ
);
7622 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7625 po_reg_or_fail (REG_TYPE_VFD
);
7630 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7631 not careful then bad things might happen. */
7632 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7635 case OP_RNDQMQ_Ibig
:
7636 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7641 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7644 /* There's a possibility of getting a 64-bit immediate here, so
7645 we need special handling. */
7646 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7649 inst
.error
= _("immediate value is out of range");
7655 case OP_RNDQMQ_I63b_RR
:
7656 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7659 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7664 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7667 po_imm_or_fail (0, 63, TRUE
);
7672 po_char_or_fail ('[');
7673 po_reg_or_fail (REG_TYPE_RN
);
7674 po_char_or_fail (']');
7680 po_reg_or_fail (REG_TYPE_RN
);
7681 if (skip_past_char (&str
, '!') == SUCCESS
)
7682 inst
.operands
[i
].writeback
= 1;
7686 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7687 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7688 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7689 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7690 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7691 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7692 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7693 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7694 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7695 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7696 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7697 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7698 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7699 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7700 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7701 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7702 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7703 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7705 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7706 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7708 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7709 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7710 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7711 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7713 /* Immediate variants */
7715 po_char_or_fail ('{');
7716 po_imm_or_fail (0, 255, TRUE
);
7717 po_char_or_fail ('}');
7721 /* The expression parser chokes on a trailing !, so we have
7722 to find it first and zap it. */
7725 while (*s
&& *s
!= ',')
7730 inst
.operands
[i
].writeback
= 1;
7732 po_imm_or_fail (0, 31, TRUE
);
7740 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7745 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7750 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7752 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7754 val
= parse_reloc (&str
);
7757 inst
.error
= _("unrecognized relocation suffix");
7760 else if (val
!= BFD_RELOC_UNUSED
)
7762 inst
.operands
[i
].imm
= val
;
7763 inst
.operands
[i
].hasreloc
= 1;
7769 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7771 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7773 inst
.operands
[i
].hasreloc
= 1;
7775 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7777 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7778 inst
.operands
[i
].hasreloc
= 0;
7782 /* Operand for MOVW or MOVT. */
7784 po_misc_or_fail (parse_half (&str
));
7787 /* Register or expression. */
7788 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7789 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7791 /* Register or immediate. */
7792 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7793 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7795 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7796 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7798 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7800 if (!is_immediate_prefix (*str
))
7803 val
= parse_fpa_immediate (&str
);
7806 /* FPA immediates are encoded as registers 8-15.
7807 parse_fpa_immediate has already applied the offset. */
7808 inst
.operands
[i
].reg
= val
;
7809 inst
.operands
[i
].isreg
= 1;
7812 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7813 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7815 /* Two kinds of register. */
7818 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7820 || (rege
->type
!= REG_TYPE_MMXWR
7821 && rege
->type
!= REG_TYPE_MMXWC
7822 && rege
->type
!= REG_TYPE_MMXWCG
))
7824 inst
.error
= _("iWMMXt data or control register expected");
7827 inst
.operands
[i
].reg
= rege
->number
;
7828 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7834 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7836 || (rege
->type
!= REG_TYPE_MMXWC
7837 && rege
->type
!= REG_TYPE_MMXWCG
))
7839 inst
.error
= _("iWMMXt control register expected");
7842 inst
.operands
[i
].reg
= rege
->number
;
7843 inst
.operands
[i
].isreg
= 1;
7848 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7849 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7850 case OP_oROR
: val
= parse_ror (&str
); break;
7852 case OP_COND
: val
= parse_cond (&str
); break;
7853 case OP_oBARRIER_I15
:
7854 po_barrier_or_imm (str
); break;
7856 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7862 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7863 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7865 inst
.error
= _("Banked registers are not available with this "
7871 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7875 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7878 val
= parse_sys_vldr_vstr (&str
);
7882 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7885 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7887 if (strncasecmp (str
, "APSR_", 5) == 0)
7894 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7895 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7896 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7897 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7898 default: found
= 16;
7902 inst
.operands
[i
].isvec
= 1;
7903 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7904 inst
.operands
[i
].reg
= REG_PC
;
7911 po_misc_or_fail (parse_tb (&str
));
7914 /* Register lists. */
7916 val
= parse_reg_list (&str
, REGLIST_RN
);
7919 inst
.operands
[i
].writeback
= 1;
7925 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7929 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7939 /* Allow Q registers too. */
7940 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7941 REGLIST_NEON_D
, &partial_match
);
7945 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7946 REGLIST_VFP_S
, &partial_match
);
7947 inst
.operands
[i
].issingle
= 1;
7952 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7953 REGLIST_VFP_D_VPR
, &partial_match
);
7954 if (val
== FAIL
&& !partial_match
)
7957 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7958 REGLIST_VFP_S_VPR
, &partial_match
);
7959 inst
.operands
[i
].issingle
= 1;
7964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7965 REGLIST_NEON_D
, &partial_match
);
7970 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7971 1, &inst
.operands
[i
].vectype
);
7972 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7976 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7977 0, &inst
.operands
[i
].vectype
);
7980 /* Addressing modes */
7982 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7986 po_misc_or_fail (parse_address (&str
, i
));
7990 po_misc_or_fail_no_backtrack (
7991 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7995 po_misc_or_fail_no_backtrack (
7996 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
8000 po_misc_or_fail_no_backtrack (
8001 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8005 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8009 po_misc_or_fail_no_backtrack (
8010 parse_shifter_operand_group_reloc (&str
, i
));
8014 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8018 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8027 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8032 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8035 po_reg_or_fail (REG_TYPE_ZR
);
8039 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8042 /* Various value-based sanity checks and shared operations. We
8043 do not signal immediate failures for the register constraints;
8044 this allows a syntax error to take precedence. */
8045 switch (op_parse_code
)
8053 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8054 inst
.error
= BAD_PC
;
8059 case OP_RRnpcsp_I32
:
8060 if (inst
.operands
[i
].isreg
)
8062 if (inst
.operands
[i
].reg
== REG_PC
)
8063 inst
.error
= BAD_PC
;
8064 else if (inst
.operands
[i
].reg
== REG_SP
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8066 relaxed since ARMv8-A. */
8067 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8070 inst
.error
= BAD_SP
;
8076 if (inst
.operands
[i
].isreg
8077 && inst
.operands
[i
].reg
== REG_PC
8078 && (inst
.operands
[i
].writeback
|| thumb
))
8079 inst
.error
= BAD_PC
;
8084 if (inst
.operands
[i
].isreg
)
8094 case OP_oBARRIER_I15
:
8107 inst
.operands
[i
].imm
= val
;
8112 if (inst
.operands
[i
].reg
!= REG_LR
)
8113 inst
.error
= _("operand must be LR register");
8119 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8120 inst
.error
= BAD_PC
;
8124 if (inst
.operands
[i
].isreg
8125 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8126 inst
.error
= BAD_ODD
;
8130 if (inst
.operands
[i
].isreg
)
8132 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8133 inst
.error
= BAD_EVEN
;
8134 else if (inst
.operands
[i
].reg
== REG_SP
)
8135 as_tsktsk (MVE_BAD_SP
);
8136 else if (inst
.operands
[i
].reg
== REG_PC
)
8137 inst
.error
= BAD_PC
;
8145 /* If we get here, this operand was successfully parsed. */
8146 inst
.operands
[i
].present
= 1;
8150 inst
.error
= BAD_ARGS
;
8155 /* The parse routine should already have set inst.error, but set a
8156 default here just in case. */
8158 inst
.error
= BAD_SYNTAX
;
8162 /* Do not backtrack over a trailing optional argument that
8163 absorbed some text. We will only fail again, with the
8164 'garbage following instruction' error message, which is
8165 probably less helpful than the current one. */
8166 if (backtrack_index
== i
&& backtrack_pos
!= str
8167 && upat
[i
+1] == OP_stop
)
8170 inst
.error
= BAD_SYNTAX
;
8174 /* Try again, skipping the optional argument at backtrack_pos. */
8175 str
= backtrack_pos
;
8176 inst
.error
= backtrack_error
;
8177 inst
.operands
[backtrack_index
].present
= 0;
8178 i
= backtrack_index
;
8182 /* Check that we have parsed all the arguments. */
8183 if (*str
!= '\0' && !inst
.error
)
8184 inst
.error
= _("garbage following instruction");
8186 return inst
.error
? FAIL
: SUCCESS
;
8189 #undef po_char_or_fail
8190 #undef po_reg_or_fail
8191 #undef po_reg_or_goto
8192 #undef po_imm_or_fail
8193 #undef po_scalar_or_fail
8194 #undef po_barrier_or_imm
8196 /* Shorthand macro for instruction encoding functions issuing errors. */
8197 #define constraint(expr, err) \
8208 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8209 instructions are unpredictable if these registers are used. This
8210 is the BadReg predicate in ARM's Thumb-2 documentation.
8212 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8213 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8214 #define reject_bad_reg(reg) \
8216 if (reg == REG_PC) \
8218 inst.error = BAD_PC; \
8221 else if (reg == REG_SP \
8222 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8224 inst.error = BAD_SP; \
8229 /* If REG is R13 (the stack pointer), warn that its use is
8231 #define warn_deprecated_sp(reg) \
8233 if (warn_on_deprecated && reg == REG_SP) \
8234 as_tsktsk (_("use of r13 is deprecated")); \
8237 /* Functions for operand encoding. ARM, then Thumb. */
8239 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8241 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8243 The only binary encoding difference is the Coprocessor number. Coprocessor
8244 9 is used for half-precision calculations or conversions. The format of the
8245 instruction is the same as the equivalent Coprocessor 10 instruction that
8246 exists for Single-Precision operation. */
8249 do_scalar_fp16_v82_encode (void)
8251 if (inst
.cond
< COND_ALWAYS
)
8252 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8253 " the behaviour is UNPREDICTABLE"));
8254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8257 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8258 mark_feature_used (&arm_ext_fp16
);
8261 /* If VAL can be encoded in the immediate field of an ARM instruction,
8262 return the encoded form. Otherwise, return FAIL. */
8265 encode_arm_immediate (unsigned int val
)
8272 for (i
= 2; i
< 32; i
+= 2)
8273 if ((a
= rotate_left (val
, i
)) <= 0xff)
8274 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8279 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8280 return the encoded form. Otherwise, return FAIL. */
8282 encode_thumb32_immediate (unsigned int val
)
8289 for (i
= 1; i
<= 24; i
++)
8292 if ((val
& ~(0xffU
<< i
)) == 0)
8293 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8297 if (val
== ((a
<< 16) | a
))
8299 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8303 if (val
== ((a
<< 16) | a
))
8304 return 0x200 | (a
>> 8);
8308 /* Encode a VFP SP or DP register number into inst.instruction. */
8311 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8313 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8316 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8319 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8327 first_error (_("D register out of range for selected VFP version"));
8335 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8339 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8343 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8347 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8351 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8355 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8363 /* Encode a <shift> in an ARM-format instruction. The immediate,
8364 if any, is handled by md_apply_fix. */
8366 encode_arm_shift (int i
)
8368 /* register-shifted register. */
8369 if (inst
.operands
[i
].immisreg
)
8372 for (op_index
= 0; op_index
<= i
; ++op_index
)
8374 /* Check the operand only when it's presented. In pre-UAL syntax,
8375 if the destination register is the same as the first operand, two
8376 register form of the instruction can be used. */
8377 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8378 && inst
.operands
[op_index
].reg
== REG_PC
)
8379 as_warn (UNPRED_REG ("r15"));
8382 if (inst
.operands
[i
].imm
== REG_PC
)
8383 as_warn (UNPRED_REG ("r15"));
8386 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8387 inst
.instruction
|= SHIFT_ROR
<< 5;
8390 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8391 if (inst
.operands
[i
].immisreg
)
8393 inst
.instruction
|= SHIFT_BY_REG
;
8394 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8397 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8402 encode_arm_shifter_operand (int i
)
8404 if (inst
.operands
[i
].isreg
)
8406 inst
.instruction
|= inst
.operands
[i
].reg
;
8407 encode_arm_shift (i
);
8411 inst
.instruction
|= INST_IMMEDIATE
;
8412 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8413 inst
.instruction
|= inst
.operands
[i
].imm
;
8417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8419 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8422 Generate an error if the operand is not a register. */
8423 constraint (!inst
.operands
[i
].isreg
,
8424 _("Instruction does not support =N addresses"));
8426 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8428 if (inst
.operands
[i
].preind
)
8432 inst
.error
= _("instruction does not accept preindexed addressing");
8435 inst
.instruction
|= PRE_INDEX
;
8436 if (inst
.operands
[i
].writeback
)
8437 inst
.instruction
|= WRITE_BACK
;
8440 else if (inst
.operands
[i
].postind
)
8442 gas_assert (inst
.operands
[i
].writeback
);
8444 inst
.instruction
|= WRITE_BACK
;
8446 else /* unindexed - only for coprocessor */
8448 inst
.error
= _("instruction does not accept unindexed addressing");
8452 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8453 && (((inst
.instruction
& 0x000f0000) >> 16)
8454 == ((inst
.instruction
& 0x0000f000) >> 12)))
8455 as_warn ((inst
.instruction
& LOAD_BIT
)
8456 ? _("destination register same as write-back base")
8457 : _("source register same as write-back base"));
8460 /* inst.operands[i] was set up by parse_address. Encode it into an
8461 ARM-format mode 2 load or store instruction. If is_t is true,
8462 reject forms that cannot be used with a T instruction (i.e. not
8465 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8467 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8469 encode_arm_addr_mode_common (i
, is_t
);
8471 if (inst
.operands
[i
].immisreg
)
8473 constraint ((inst
.operands
[i
].imm
== REG_PC
8474 || (is_pc
&& inst
.operands
[i
].writeback
)),
8476 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8477 inst
.instruction
|= inst
.operands
[i
].imm
;
8478 if (!inst
.operands
[i
].negative
)
8479 inst
.instruction
|= INDEX_UP
;
8480 if (inst
.operands
[i
].shifted
)
8482 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8483 inst
.instruction
|= SHIFT_ROR
<< 5;
8486 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8487 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8491 else /* immediate offset in inst.relocs[0] */
8493 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8495 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8498 cannot use PC in addressing.
8499 PC cannot be used in writeback addressing, either. */
8500 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8503 /* Use of PC in str is deprecated for ARMv7. */
8504 if (warn_on_deprecated
8506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8507 as_tsktsk (_("use of PC in this instruction is deprecated"));
8510 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8512 /* Prefer + for zero encoded value. */
8513 if (!inst
.operands
[i
].negative
)
8514 inst
.instruction
|= INDEX_UP
;
8515 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8520 /* inst.operands[i] was set up by parse_address. Encode it into an
8521 ARM-format mode 3 load or store instruction. Reject forms that
8522 cannot be used with such instructions. If is_t is true, reject
8523 forms that cannot be used with a T instruction (i.e. not
8526 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8528 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8530 inst
.error
= _("instruction does not accept scaled register index");
8534 encode_arm_addr_mode_common (i
, is_t
);
8536 if (inst
.operands
[i
].immisreg
)
8538 constraint ((inst
.operands
[i
].imm
== REG_PC
8539 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8541 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8543 inst
.instruction
|= inst
.operands
[i
].imm
;
8544 if (!inst
.operands
[i
].negative
)
8545 inst
.instruction
|= INDEX_UP
;
8547 else /* immediate offset in inst.relocs[0] */
8549 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8550 && inst
.operands
[i
].writeback
),
8552 inst
.instruction
|= HWOFFSET_IMM
;
8553 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8555 /* Prefer + for zero encoded value. */
8556 if (!inst
.operands
[i
].negative
)
8557 inst
.instruction
|= INDEX_UP
;
8559 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8564 /* Write immediate bits [7:0] to the following locations:
8566 |28/24|23 19|18 16|15 4|3 0|
8567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8569 This function is used by VMOV/VMVN/VORR/VBIC. */
8572 neon_write_immbits (unsigned immbits
)
8574 inst
.instruction
|= immbits
& 0xf;
8575 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8576 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8579 /* Invert low-order SIZE bits of XHI:XLO. */
8582 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8584 unsigned immlo
= xlo
? *xlo
: 0;
8585 unsigned immhi
= xhi
? *xhi
: 0;
8590 immlo
= (~immlo
) & 0xff;
8594 immlo
= (~immlo
) & 0xffff;
8598 immhi
= (~immhi
) & 0xffffffff;
8602 immlo
= (~immlo
) & 0xffffffff;
8616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8620 neon_bits_same_in_bytes (unsigned imm
)
8622 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8623 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8624 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8625 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8628 /* For immediate of above form, return 0bABCD. */
8631 neon_squash_bits (unsigned imm
)
8633 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8634 | ((imm
& 0x01000000) >> 21);
8637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8640 neon_qfloat_bits (unsigned imm
)
8642 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8646 the instruction. *OP is passed as the initial value of the op field, and
8647 may be set to a different value depending on the constant (i.e.
8648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8649 MVN). If the immediate looks like a repeated pattern then also
8650 try smaller element sizes. */
8653 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8654 unsigned *immbits
, int *op
, int size
,
8655 enum neon_el_type type
)
8657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8659 if (type
== NT_float
&& !float_p
)
8662 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8664 if (size
!= 32 || *op
== 1)
8666 *immbits
= neon_qfloat_bits (immlo
);
8672 if (neon_bits_same_in_bytes (immhi
)
8673 && neon_bits_same_in_bytes (immlo
))
8677 *immbits
= (neon_squash_bits (immhi
) << 4)
8678 | neon_squash_bits (immlo
);
8689 if (immlo
== (immlo
& 0x000000ff))
8694 else if (immlo
== (immlo
& 0x0000ff00))
8696 *immbits
= immlo
>> 8;
8699 else if (immlo
== (immlo
& 0x00ff0000))
8701 *immbits
= immlo
>> 16;
8704 else if (immlo
== (immlo
& 0xff000000))
8706 *immbits
= immlo
>> 24;
8709 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8711 *immbits
= (immlo
>> 8) & 0xff;
8714 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8716 *immbits
= (immlo
>> 16) & 0xff;
8720 if ((immlo
& 0xffff) != (immlo
>> 16))
8727 if (immlo
== (immlo
& 0x000000ff))
8732 else if (immlo
== (immlo
& 0x0000ff00))
8734 *immbits
= immlo
>> 8;
8738 if ((immlo
& 0xff) != (immlo
>> 8))
8743 if (immlo
== (immlo
& 0x000000ff))
8745 /* Don't allow MVN with 8-bit immediate. */
8755 #if defined BFD_HOST_64_BIT
8756 /* Returns TRUE if double precision value V may be cast
8757 to single precision without loss of accuracy. */
8760 is_double_a_single (bfd_int64_t v
)
8762 int exp
= (int)((v
>> 52) & 0x7FF);
8763 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8765 return (exp
== 0 || exp
== 0x7FF
8766 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8767 && (mantissa
& 0x1FFFFFFFl
) == 0;
8770 /* Returns a double precision value casted to single precision
8771 (ignoring the least significant bits in exponent and mantissa). */
8774 double_to_single (bfd_int64_t v
)
8776 unsigned int sign
= (v
>> 63) & 1;
8777 int exp
= (v
>> 52) & 0x7FF;
8778 bfd_int64_t mantissa
= (v
& (bfd_int64_t
) 0xFFFFFFFFFFFFFULL
);
8784 exp
= exp
- 1023 + 127;
8793 /* No denormalized numbers. */
8799 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8801 #endif /* BFD_HOST_64_BIT */
8810 static void do_vfp_nsyn_opcode (const char *);
8812 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8813 Determine whether it can be performed with a move instruction; if
8814 it can, convert inst.instruction to that move instruction and
8815 return TRUE; if it can't, convert inst.instruction to a literal-pool
8816 load and return FALSE. If this is not a valid thing to do in the
8817 current context, set inst.error and return TRUE.
8819 inst.operands[i] describes the destination register. */
8822 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8825 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8826 bfd_boolean arm_p
= (t
== CONST_ARM
);
8829 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8833 if ((inst
.instruction
& tbit
) == 0)
8835 inst
.error
= _("invalid pseudo operation");
8839 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8840 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8841 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8843 inst
.error
= _("constant expression expected");
8847 if (inst
.relocs
[0].exp
.X_op
== O_constant
8848 || inst
.relocs
[0].exp
.X_op
== O_big
)
8850 #if defined BFD_HOST_64_BIT
8855 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8857 LITTLENUM_TYPE w
[X_PRECISION
];
8860 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8862 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8864 /* FIXME: Should we check words w[2..5] ? */
8869 #if defined BFD_HOST_64_BIT
8870 v
= ((((bfd_uint64_t
) l
[3] & LITTLENUM_MASK
)
8871 << LITTLENUM_NUMBER_OF_BITS
)
8872 | (((bfd_int64_t
) l
[2] & LITTLENUM_MASK
)
8873 << LITTLENUM_NUMBER_OF_BITS
)
8874 | (((bfd_uint64_t
) l
[1] & LITTLENUM_MASK
)
8875 << LITTLENUM_NUMBER_OF_BITS
)
8876 | (l
[0] & LITTLENUM_MASK
));
8878 v
= ((((valueT
) l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8879 | (l
[0] & LITTLENUM_MASK
));
8883 v
= inst
.relocs
[0].exp
.X_add_number
;
8885 if (!inst
.operands
[i
].issingle
)
8889 /* LDR should not use lead in a flag-setting instruction being
8890 chosen so we do not check whether movs can be used. */
8892 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8893 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8894 && inst
.operands
[i
].reg
!= 13
8895 && inst
.operands
[i
].reg
!= 15)
8897 /* Check if on thumb2 it can be done with a mov.w, mvn or
8898 movw instruction. */
8899 unsigned int newimm
;
8900 bfd_boolean isNegated
= FALSE
;
8902 newimm
= encode_thumb32_immediate (v
);
8903 if (newimm
== (unsigned int) FAIL
)
8905 newimm
= encode_thumb32_immediate (~v
);
8909 /* The number can be loaded with a mov.w or mvn
8911 if (newimm
!= (unsigned int) FAIL
8912 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8914 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8915 | (inst
.operands
[i
].reg
<< 8));
8916 /* Change to MOVN. */
8917 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8918 inst
.instruction
|= (newimm
& 0x800) << 15;
8919 inst
.instruction
|= (newimm
& 0x700) << 4;
8920 inst
.instruction
|= (newimm
& 0x0ff);
8923 /* The number can be loaded with a movw instruction. */
8924 else if ((v
& ~0xFFFF) == 0
8925 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8927 int imm
= v
& 0xFFFF;
8929 inst
.instruction
= 0xf2400000; /* MOVW. */
8930 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8931 inst
.instruction
|= (imm
& 0xf000) << 4;
8932 inst
.instruction
|= (imm
& 0x0800) << 15;
8933 inst
.instruction
|= (imm
& 0x0700) << 4;
8934 inst
.instruction
|= (imm
& 0x00ff);
8935 /* In case this replacement is being done on Armv8-M
8936 Baseline we need to make sure to disable the
8937 instruction size check, as otherwise GAS will reject
8938 the use of this T32 instruction. */
8946 int value
= encode_arm_immediate (v
);
8950 /* This can be done with a mov instruction. */
8951 inst
.instruction
&= LITERAL_MASK
;
8952 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8953 inst
.instruction
|= value
& 0xfff;
8957 value
= encode_arm_immediate (~ v
);
8960 /* This can be done with a mvn instruction. */
8961 inst
.instruction
&= LITERAL_MASK
;
8962 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8963 inst
.instruction
|= value
& 0xfff;
8967 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8970 unsigned immbits
= 0;
8971 unsigned immlo
= inst
.operands
[1].imm
;
8972 unsigned immhi
= inst
.operands
[1].regisimm
8973 ? inst
.operands
[1].reg
8974 : inst
.relocs
[0].exp
.X_unsigned
8976 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8977 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8978 &op
, 64, NT_invtype
);
8982 neon_invert_size (&immlo
, &immhi
, 64);
8984 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8985 &op
, 64, NT_invtype
);
8990 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8996 /* Fill other bits in vmov encoding for both thumb and arm. */
8998 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9000 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9001 neon_write_immbits (immbits
);
9009 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9010 if (inst
.operands
[i
].issingle
9011 && is_quarter_float (inst
.operands
[1].imm
)
9012 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9014 inst
.operands
[1].imm
=
9015 neon_qfloat_bits (v
);
9016 do_vfp_nsyn_opcode ("fconsts");
9020 /* If our host does not support a 64-bit type then we cannot perform
9021 the following optimization. This mean that there will be a
9022 discrepancy between the output produced by an assembler built for
9023 a 32-bit-only host and the output produced from a 64-bit host, but
9024 this cannot be helped. */
9025 #if defined BFD_HOST_64_BIT
9026 else if (!inst
.operands
[1].issingle
9027 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9029 if (is_double_a_single (v
)
9030 && is_quarter_float (double_to_single (v
)))
9032 inst
.operands
[1].imm
=
9033 neon_qfloat_bits (double_to_single (v
));
9034 do_vfp_nsyn_opcode ("fconstd");
9042 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9043 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9046 inst
.operands
[1].reg
= REG_PC
;
9047 inst
.operands
[1].isreg
= 1;
9048 inst
.operands
[1].preind
= 1;
9049 inst
.relocs
[0].pc_rel
= 1;
9050 inst
.relocs
[0].type
= (thumb_p
9051 ? BFD_RELOC_ARM_THUMB_OFFSET
9053 ? BFD_RELOC_ARM_HWLITERAL
9054 : BFD_RELOC_ARM_LITERAL
));
9058 /* inst.operands[i] was set up by parse_address. Encode it into an
9059 ARM-format instruction. Reject all forms which cannot be encoded
9060 into a coprocessor load/store instruction. If wb_ok is false,
9061 reject use of writeback; if unind_ok is false, reject use of
9062 unindexed addressing. If reloc_override is not 0, use it instead
9063 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9064 (in which case it is preserved). */
9067 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9069 if (!inst
.operands
[i
].isreg
)
9072 if (! inst
.operands
[0].isvec
)
9074 inst
.error
= _("invalid co-processor operand");
9077 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9081 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9083 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9085 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9087 gas_assert (!inst
.operands
[i
].writeback
);
9090 inst
.error
= _("instruction does not support unindexed addressing");
9093 inst
.instruction
|= inst
.operands
[i
].imm
;
9094 inst
.instruction
|= INDEX_UP
;
9098 if (inst
.operands
[i
].preind
)
9099 inst
.instruction
|= PRE_INDEX
;
9101 if (inst
.operands
[i
].writeback
)
9103 if (inst
.operands
[i
].reg
== REG_PC
)
9105 inst
.error
= _("pc may not be used with write-back");
9110 inst
.error
= _("instruction does not support writeback");
9113 inst
.instruction
|= WRITE_BACK
;
9117 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9118 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9119 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9120 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9123 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9125 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9128 /* Prefer + for zero encoded value. */
9129 if (!inst
.operands
[i
].negative
)
9130 inst
.instruction
|= INDEX_UP
;
9135 /* Functions for instruction encoding, sorted by sub-architecture.
9136 First some generics; their names are taken from the conventional
9137 bit positions for register arguments in ARM format instructions. */
9147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9153 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9159 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9160 inst
.instruction
|= inst
.operands
[1].reg
;
9166 inst
.instruction
|= inst
.operands
[0].reg
;
9167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9173 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9174 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9180 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9181 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9187 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9188 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9192 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9194 if (ARM_CPU_IS_ANY (cpu_variant
))
9196 as_tsktsk ("%s", msg
);
9199 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9211 unsigned Rn
= inst
.operands
[2].reg
;
9212 /* Enforce restrictions on SWP instruction. */
9213 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9215 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9216 _("Rn must not overlap other operands"));
9218 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9220 if (!check_obsolete (&arm_ext_v8
,
9221 _("swp{b} use is obsoleted for ARMv8 and later"))
9222 && warn_on_deprecated
9223 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9224 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9228 inst
.instruction
|= inst
.operands
[1].reg
;
9229 inst
.instruction
|= Rn
<< 16;
9235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9237 inst
.instruction
|= inst
.operands
[2].reg
;
9243 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9244 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9245 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9246 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9248 inst
.instruction
|= inst
.operands
[0].reg
;
9249 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9250 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9256 inst
.instruction
|= inst
.operands
[0].imm
;
9262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9263 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9266 /* ARM instructions, in alphabetical order by function name (except
9267 that wrapper functions appear immediately after the function they
9270 /* This is a pseudo-op of the form "adr rd, label" to be converted
9271 into a relative address of the form "add rd, pc, #label-.-8". */
9276 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9278 /* Frag hacking will turn this into a sub instruction if the offset turns
9279 out to be negative. */
9280 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9281 inst
.relocs
[0].pc_rel
= 1;
9282 inst
.relocs
[0].exp
.X_add_number
-= 8;
9284 if (support_interwork
9285 && inst
.relocs
[0].exp
.X_op
== O_symbol
9286 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9287 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9288 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9289 inst
.relocs
[0].exp
.X_add_number
|= 1;
9292 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9293 into a relative address of the form:
9294 add rd, pc, #low(label-.-8)"
9295 add rd, rd, #high(label-.-8)" */
9300 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9302 /* Frag hacking will turn this into a sub instruction if the offset turns
9303 out to be negative. */
9304 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9305 inst
.relocs
[0].pc_rel
= 1;
9306 inst
.size
= INSN_SIZE
* 2;
9307 inst
.relocs
[0].exp
.X_add_number
-= 8;
9309 if (support_interwork
9310 && inst
.relocs
[0].exp
.X_op
== O_symbol
9311 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9312 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9313 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9314 inst
.relocs
[0].exp
.X_add_number
|= 1;
9320 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9321 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9323 if (!inst
.operands
[1].present
)
9324 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9327 encode_arm_shifter_operand (2);
9333 if (inst
.operands
[0].present
)
9334 inst
.instruction
|= inst
.operands
[0].imm
;
9336 inst
.instruction
|= 0xf;
9342 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9343 constraint (msb
> 32, _("bit-field extends past end of register"));
9344 /* The instruction encoding stores the LSB and MSB,
9345 not the LSB and width. */
9346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9347 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9348 inst
.instruction
|= (msb
- 1) << 16;
9356 /* #0 in second position is alternative syntax for bfc, which is
9357 the same instruction but with REG_PC in the Rm field. */
9358 if (!inst
.operands
[1].isreg
)
9359 inst
.operands
[1].reg
= REG_PC
;
9361 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9362 constraint (msb
> 32, _("bit-field extends past end of register"));
9363 /* The instruction encoding stores the LSB and MSB,
9364 not the LSB and width. */
9365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9366 inst
.instruction
|= inst
.operands
[1].reg
;
9367 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9368 inst
.instruction
|= (msb
- 1) << 16;
9374 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9375 _("bit-field extends past end of register"));
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9377 inst
.instruction
|= inst
.operands
[1].reg
;
9378 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9379 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9382 /* ARM V5 breakpoint instruction (argument parse)
9383 BKPT <16 bit unsigned immediate>
9384 Instruction is not conditional.
9385 The bit pattern given in insns[] has the COND_ALWAYS condition,
9386 and it is an error if the caller tried to override that. */
9391 /* Top 12 of 16 bits to bits 19:8. */
9392 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9394 /* Bottom 4 of 16 bits to bits 3:0. */
9395 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9399 encode_branch (int default_reloc
)
9401 if (inst
.operands
[0].hasreloc
)
9403 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9404 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9405 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9406 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9407 ? BFD_RELOC_ARM_PLT32
9408 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9411 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9412 inst
.relocs
[0].pc_rel
= 1;
9419 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9420 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9423 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9430 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9432 if (inst
.cond
== COND_ALWAYS
)
9433 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9435 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9439 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9442 /* ARM V5 branch-link-exchange instruction (argument parse)
9443 BLX <target_addr> ie BLX(1)
9444 BLX{<condition>} <Rm> ie BLX(2)
9445 Unfortunately, there are two different opcodes for this mnemonic.
9446 So, the insns[].value is not used, and the code here zaps values
9447 into inst.instruction.
9448 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9453 if (inst
.operands
[0].isreg
)
9455 /* Arg is a register; the opcode provided by insns[] is correct.
9456 It is not illegal to do "blx pc", just useless. */
9457 if (inst
.operands
[0].reg
== REG_PC
)
9458 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9460 inst
.instruction
|= inst
.operands
[0].reg
;
9464 /* Arg is an address; this instruction cannot be executed
9465 conditionally, and the opcode must be adjusted.
9466 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9467 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9468 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9469 inst
.instruction
= 0xfa000000;
9470 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9477 bfd_boolean want_reloc
;
9479 if (inst
.operands
[0].reg
== REG_PC
)
9480 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9482 inst
.instruction
|= inst
.operands
[0].reg
;
9483 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9484 it is for ARMv4t or earlier. */
9485 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9486 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9487 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9491 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9496 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9500 /* ARM v5TEJ. Jump to Jazelle code. */
9505 if (inst
.operands
[0].reg
== REG_PC
)
9506 as_tsktsk (_("use of r15 in bxj is not really useful"));
9508 inst
.instruction
|= inst
.operands
[0].reg
;
9511 /* Co-processor data operation:
9512 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9513 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9518 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9519 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9520 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9521 inst
.instruction
|= inst
.operands
[4].reg
;
9522 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9528 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9529 encode_arm_shifter_operand (1);
9532 /* Transfer between coprocessor and ARM registers.
9533 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9538 No special properties. */
9540 struct deprecated_coproc_regs_s
9547 arm_feature_set deprecated
;
9548 arm_feature_set obsoleted
;
9549 const char *dep_msg
;
9550 const char *obs_msg
;
9553 #define DEPR_ACCESS_V8 \
9554 N_("This coprocessor register access is deprecated in ARMv8")
9556 /* Table of all deprecated coprocessor registers. */
9557 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9559 {15, 0, 7, 10, 5, /* CP15DMB. */
9560 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9561 DEPR_ACCESS_V8
, NULL
},
9562 {15, 0, 7, 10, 4, /* CP15DSB. */
9563 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9564 DEPR_ACCESS_V8
, NULL
},
9565 {15, 0, 7, 5, 4, /* CP15ISB. */
9566 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9567 DEPR_ACCESS_V8
, NULL
},
9568 {14, 6, 1, 0, 0, /* TEEHBR. */
9569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9570 DEPR_ACCESS_V8
, NULL
},
9571 {14, 6, 0, 0, 0, /* TEECR. */
9572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9573 DEPR_ACCESS_V8
, NULL
},
9576 #undef DEPR_ACCESS_V8
9578 static const size_t deprecated_coproc_reg_count
=
9579 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9587 Rd
= inst
.operands
[2].reg
;
9590 if (inst
.instruction
== 0xee000010
9591 || inst
.instruction
== 0xfe000010)
9593 reject_bad_reg (Rd
);
9594 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9596 constraint (Rd
== REG_SP
, BAD_SP
);
9601 if (inst
.instruction
== 0xe000010)
9602 constraint (Rd
== REG_PC
, BAD_PC
);
9605 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9607 const struct deprecated_coproc_regs_s
*r
=
9608 deprecated_coproc_regs
+ i
;
9610 if (inst
.operands
[0].reg
== r
->cp
9611 && inst
.operands
[1].imm
== r
->opc1
9612 && inst
.operands
[3].reg
== r
->crn
9613 && inst
.operands
[4].reg
== r
->crm
9614 && inst
.operands
[5].imm
== r
->opc2
)
9616 if (! ARM_CPU_IS_ANY (cpu_variant
)
9617 && warn_on_deprecated
9618 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9619 as_tsktsk ("%s", r
->dep_msg
);
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9624 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9625 inst
.instruction
|= Rd
<< 12;
9626 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9627 inst
.instruction
|= inst
.operands
[4].reg
;
9628 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9631 /* Transfer between coprocessor register and pair of ARM registers.
9632 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9637 Two XScale instructions are special cases of these:
9639 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9640 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9642 Result unpredictable if Rd or Rn is R15. */
9649 Rd
= inst
.operands
[2].reg
;
9650 Rn
= inst
.operands
[3].reg
;
9654 reject_bad_reg (Rd
);
9655 reject_bad_reg (Rn
);
9659 constraint (Rd
== REG_PC
, BAD_PC
);
9660 constraint (Rn
== REG_PC
, BAD_PC
);
9663 /* Only check the MRRC{2} variants. */
9664 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9666 /* If Rd == Rn, error that the operation is
9667 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9668 constraint (Rd
== Rn
, BAD_OVERLAP
);
9671 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9672 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9673 inst
.instruction
|= Rd
<< 12;
9674 inst
.instruction
|= Rn
<< 16;
9675 inst
.instruction
|= inst
.operands
[4].reg
;
9681 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9682 if (inst
.operands
[1].present
)
9684 inst
.instruction
|= CPSI_MMOD
;
9685 inst
.instruction
|= inst
.operands
[1].imm
;
9692 inst
.instruction
|= inst
.operands
[0].imm
;
9698 unsigned Rd
, Rn
, Rm
;
9700 Rd
= inst
.operands
[0].reg
;
9701 Rn
= (inst
.operands
[1].present
9702 ? inst
.operands
[1].reg
: Rd
);
9703 Rm
= inst
.operands
[2].reg
;
9705 constraint ((Rd
== REG_PC
), BAD_PC
);
9706 constraint ((Rn
== REG_PC
), BAD_PC
);
9707 constraint ((Rm
== REG_PC
), BAD_PC
);
9709 inst
.instruction
|= Rd
<< 16;
9710 inst
.instruction
|= Rn
<< 0;
9711 inst
.instruction
|= Rm
<< 8;
9717 /* There is no IT instruction in ARM mode. We
9718 process it to do the validation as if in
9719 thumb mode, just in case the code gets
9720 assembled for thumb using the unified syntax. */
9725 set_pred_insn_type (IT_INSN
);
9726 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9727 now_pred
.cc
= inst
.operands
[0].imm
;
9731 /* If there is only one register in the register list,
9732 then return its register number. Otherwise return -1. */
9734 only_one_reg_in_list (int range
)
9736 int i
= ffs (range
) - 1;
9737 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9741 encode_ldmstm(int from_push_pop_mnem
)
9743 int base_reg
= inst
.operands
[0].reg
;
9744 int range
= inst
.operands
[1].imm
;
9747 inst
.instruction
|= base_reg
<< 16;
9748 inst
.instruction
|= range
;
9750 if (inst
.operands
[1].writeback
)
9751 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9753 if (inst
.operands
[0].writeback
)
9755 inst
.instruction
|= WRITE_BACK
;
9756 /* Check for unpredictable uses of writeback. */
9757 if (inst
.instruction
& LOAD_BIT
)
9759 /* Not allowed in LDM type 2. */
9760 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9761 && ((range
& (1 << REG_PC
)) == 0))
9762 as_warn (_("writeback of base register is UNPREDICTABLE"));
9763 /* Only allowed if base reg not in list for other types. */
9764 else if (range
& (1 << base_reg
))
9765 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9769 /* Not allowed for type 2. */
9770 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9771 as_warn (_("writeback of base register is UNPREDICTABLE"));
9772 /* Only allowed if base reg not in list, or first in list. */
9773 else if ((range
& (1 << base_reg
))
9774 && (range
& ((1 << base_reg
) - 1)))
9775 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9779 /* If PUSH/POP has only one register, then use the A2 encoding. */
9780 one_reg
= only_one_reg_in_list (range
);
9781 if (from_push_pop_mnem
&& one_reg
>= 0)
9783 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9785 if (is_push
&& one_reg
== 13 /* SP */)
9786 /* PR 22483: The A2 encoding cannot be used when
9787 pushing the stack pointer as this is UNPREDICTABLE. */
9790 inst
.instruction
&= A_COND_MASK
;
9791 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9792 inst
.instruction
|= one_reg
<< 12;
9799 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9802 /* ARMv5TE load-consecutive (argument parse)
9811 constraint (inst
.operands
[0].reg
% 2 != 0,
9812 _("first transfer register must be even"));
9813 constraint (inst
.operands
[1].present
9814 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9815 _("can only transfer two consecutive registers"));
9816 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9817 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9819 if (!inst
.operands
[1].present
)
9820 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9822 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9823 register and the first register written; we have to diagnose
9824 overlap between the base and the second register written here. */
9826 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9827 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9828 as_warn (_("base register written back, and overlaps "
9829 "second transfer register"));
9831 if (!(inst
.instruction
& V4_STR_BIT
))
9833 /* For an index-register load, the index register must not overlap the
9834 destination (even if not write-back). */
9835 if (inst
.operands
[2].immisreg
9836 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9837 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9838 as_warn (_("index register overlaps transfer register"));
9840 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9841 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9847 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9848 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9849 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9850 || inst
.operands
[1].negative
9851 /* This can arise if the programmer has written
9853 or if they have mistakenly used a register name as the last
9856 It is very difficult to distinguish between these two cases
9857 because "rX" might actually be a label. ie the register
9858 name has been occluded by a symbol of the same name. So we
9859 just generate a general 'bad addressing mode' type error
9860 message and leave it up to the programmer to discover the
9861 true cause and fix their mistake. */
9862 || (inst
.operands
[1].reg
== REG_PC
),
9865 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9866 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9867 _("offset must be zero in ARM encoding"));
9869 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9879 constraint (inst
.operands
[0].reg
% 2 != 0,
9880 _("even register required"));
9881 constraint (inst
.operands
[1].present
9882 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9883 _("can only load two consecutive registers"));
9884 /* If op 1 were present and equal to PC, this function wouldn't
9885 have been called in the first place. */
9886 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9889 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9892 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9893 which is not a multiple of four is UNPREDICTABLE. */
9895 check_ldr_r15_aligned (void)
9897 constraint (!(inst
.operands
[1].immisreg
)
9898 && (inst
.operands
[0].reg
== REG_PC
9899 && inst
.operands
[1].reg
== REG_PC
9900 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9901 _("ldr to register 15 must be 4-byte aligned"));
9907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9908 if (!inst
.operands
[1].isreg
)
9909 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9911 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9912 check_ldr_r15_aligned ();
9918 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9920 if (inst
.operands
[1].preind
)
9922 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9923 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9924 _("this instruction requires a post-indexed address"));
9926 inst
.operands
[1].preind
= 0;
9927 inst
.operands
[1].postind
= 1;
9928 inst
.operands
[1].writeback
= 1;
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9931 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9934 /* Halfword and signed-byte load/store operations. */
9939 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9941 if (!inst
.operands
[1].isreg
)
9942 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9944 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9950 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9952 if (inst
.operands
[1].preind
)
9954 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9955 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9956 _("this instruction requires a post-indexed address"));
9958 inst
.operands
[1].preind
= 0;
9959 inst
.operands
[1].postind
= 1;
9960 inst
.operands
[1].writeback
= 1;
9962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9963 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9966 /* Co-processor register load/store.
9967 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9972 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9973 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9979 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9980 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9981 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9982 && !(inst
.instruction
& 0x00400000))
9983 as_tsktsk (_("Rd and Rm should be different in mla"));
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9986 inst
.instruction
|= inst
.operands
[1].reg
;
9987 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9988 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9994 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9995 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9998 encode_arm_shifter_operand (1);
10001 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10008 top
= (inst
.instruction
& 0x00400000) != 0;
10009 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10010 _(":lower16: not allowed in this instruction"));
10011 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10012 _(":upper16: not allowed in this instruction"));
10013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10014 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10016 imm
= inst
.relocs
[0].exp
.X_add_number
;
10017 /* The value is in two pieces: 0:11, 16:19. */
10018 inst
.instruction
|= (imm
& 0x00000fff);
10019 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10024 do_vfp_nsyn_mrs (void)
10026 if (inst
.operands
[0].isvec
)
10028 if (inst
.operands
[1].reg
!= 1)
10029 first_error (_("operand 1 must be FPSCR"));
10030 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10031 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10032 do_vfp_nsyn_opcode ("fmstat");
10034 else if (inst
.operands
[1].isvec
)
10035 do_vfp_nsyn_opcode ("fmrx");
10043 do_vfp_nsyn_msr (void)
10045 if (inst
.operands
[0].isvec
)
10046 do_vfp_nsyn_opcode ("fmxr");
10056 unsigned Rt
= inst
.operands
[0].reg
;
10058 if (thumb_mode
&& Rt
== REG_SP
)
10060 inst
.error
= BAD_SP
;
10064 switch (inst
.operands
[1].reg
)
10066 /* MVFR2 is only valid for Armv8-A. */
10068 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10072 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10073 case 1: /* fpscr. */
10074 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10075 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10079 case 14: /* fpcxt_ns. */
10080 case 15: /* fpcxt_s. */
10081 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10082 _("selected processor does not support instruction"));
10085 case 2: /* fpscr_nzcvqc. */
10086 case 12: /* vpr. */
10088 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10089 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10090 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10091 _("selected processor does not support instruction"));
10092 if (inst
.operands
[0].reg
!= 2
10093 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10094 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10101 /* APSR_ sets isvec. All other refs to PC are illegal. */
10102 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10104 inst
.error
= BAD_PC
;
10108 /* If we get through parsing the register name, we just insert the number
10109 generated into the instruction without further validation. */
10110 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10111 inst
.instruction
|= (Rt
<< 12);
10117 unsigned Rt
= inst
.operands
[1].reg
;
10120 reject_bad_reg (Rt
);
10121 else if (Rt
== REG_PC
)
10123 inst
.error
= BAD_PC
;
10127 switch (inst
.operands
[0].reg
)
10129 /* MVFR2 is only valid for Armv8-A. */
10131 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10135 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10136 case 1: /* fpcr. */
10137 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10138 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10142 case 14: /* fpcxt_ns. */
10143 case 15: /* fpcxt_s. */
10144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10145 _("selected processor does not support instruction"));
10148 case 2: /* fpscr_nzcvqc. */
10149 case 12: /* vpr. */
10151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10152 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10153 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10154 _("selected processor does not support instruction"));
10155 if (inst
.operands
[0].reg
!= 2
10156 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10157 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10164 /* If we get through parsing the register name, we just insert the number
10165 generated into the instruction without further validation. */
10166 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10167 inst
.instruction
|= (Rt
<< 12);
10175 if (do_vfp_nsyn_mrs () == SUCCESS
)
10178 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10181 if (inst
.operands
[1].isreg
)
10183 br
= inst
.operands
[1].reg
;
10184 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10185 as_bad (_("bad register for mrs"));
10189 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10190 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10192 _("'APSR', 'CPSR' or 'SPSR' expected"));
10193 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10196 inst
.instruction
|= br
;
10199 /* Two possible forms:
10200 "{C|S}PSR_<field>, Rm",
10201 "{C|S}PSR_f, #expression". */
10206 if (do_vfp_nsyn_msr () == SUCCESS
)
10209 inst
.instruction
|= inst
.operands
[0].imm
;
10210 if (inst
.operands
[1].isreg
)
10211 inst
.instruction
|= inst
.operands
[1].reg
;
10214 inst
.instruction
|= INST_IMMEDIATE
;
10215 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10216 inst
.relocs
[0].pc_rel
= 0;
10223 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10225 if (!inst
.operands
[2].present
)
10226 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10227 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10228 inst
.instruction
|= inst
.operands
[1].reg
;
10229 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10231 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10232 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10233 as_tsktsk (_("Rd and Rm should be different in mul"));
10236 /* Long Multiply Parser
10237 UMULL RdLo, RdHi, Rm, Rs
10238 SMULL RdLo, RdHi, Rm, Rs
10239 UMLAL RdLo, RdHi, Rm, Rs
10240 SMLAL RdLo, RdHi, Rm, Rs. */
10245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10246 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10247 inst
.instruction
|= inst
.operands
[2].reg
;
10248 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10250 /* rdhi and rdlo must be different. */
10251 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10252 as_tsktsk (_("rdhi and rdlo must be different"));
10254 /* rdhi, rdlo and rm must all be different before armv6. */
10255 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10256 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10257 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10258 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10264 if (inst
.operands
[0].present
10265 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10267 /* Architectural NOP hints are CPSR sets with no bits selected. */
10268 inst
.instruction
&= 0xf0000000;
10269 inst
.instruction
|= 0x0320f000;
10270 if (inst
.operands
[0].present
)
10271 inst
.instruction
|= inst
.operands
[0].imm
;
10275 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10276 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10277 Condition defaults to COND_ALWAYS.
10278 Error if Rd, Rn or Rm are R15. */
10283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10284 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10285 inst
.instruction
|= inst
.operands
[2].reg
;
10286 if (inst
.operands
[3].present
)
10287 encode_arm_shift (3);
10290 /* ARM V6 PKHTB (Argument Parse). */
10295 if (!inst
.operands
[3].present
)
10297 /* If the shift specifier is omitted, turn the instruction
10298 into pkhbt rd, rm, rn. */
10299 inst
.instruction
&= 0xfff00010;
10300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10301 inst
.instruction
|= inst
.operands
[1].reg
;
10302 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10308 inst
.instruction
|= inst
.operands
[2].reg
;
10309 encode_arm_shift (3);
10313 /* ARMv5TE: Preload-Cache
10314 MP Extensions: Preload for write
10318 Syntactically, like LDR with B=1, W=0, L=1. */
10323 constraint (!inst
.operands
[0].isreg
,
10324 _("'[' expected after PLD mnemonic"));
10325 constraint (inst
.operands
[0].postind
,
10326 _("post-indexed expression used in preload instruction"));
10327 constraint (inst
.operands
[0].writeback
,
10328 _("writeback used in preload instruction"));
10329 constraint (!inst
.operands
[0].preind
,
10330 _("unindexed addressing used in preload instruction"));
10331 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10334 /* ARMv7: PLI <addr_mode> */
10338 constraint (!inst
.operands
[0].isreg
,
10339 _("'[' expected after PLI mnemonic"));
10340 constraint (inst
.operands
[0].postind
,
10341 _("post-indexed expression used in preload instruction"));
10342 constraint (inst
.operands
[0].writeback
,
10343 _("writeback used in preload instruction"));
10344 constraint (!inst
.operands
[0].preind
,
10345 _("unindexed addressing used in preload instruction"));
10346 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10347 inst
.instruction
&= ~PRE_INDEX
;
10353 constraint (inst
.operands
[0].writeback
,
10354 _("push/pop do not support {reglist}^"));
10355 inst
.operands
[1] = inst
.operands
[0];
10356 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10357 inst
.operands
[0].isreg
= 1;
10358 inst
.operands
[0].writeback
= 1;
10359 inst
.operands
[0].reg
= REG_SP
;
10360 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10363 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10364 word at the specified address and the following word
10366 Unconditionally executed.
10367 Error if Rn is R15. */
10372 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10373 if (inst
.operands
[0].writeback
)
10374 inst
.instruction
|= WRITE_BACK
;
10377 /* ARM V6 ssat (argument parse). */
10382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10383 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10384 inst
.instruction
|= inst
.operands
[2].reg
;
10386 if (inst
.operands
[3].present
)
10387 encode_arm_shift (3);
10390 /* ARM V6 usat (argument parse). */
10395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10396 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10397 inst
.instruction
|= inst
.operands
[2].reg
;
10399 if (inst
.operands
[3].present
)
10400 encode_arm_shift (3);
10403 /* ARM V6 ssat16 (argument parse). */
10408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10409 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10410 inst
.instruction
|= inst
.operands
[2].reg
;
10416 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10417 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10418 inst
.instruction
|= inst
.operands
[2].reg
;
10421 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10422 preserving the other bits.
10424 setend <endian_specifier>, where <endian_specifier> is either
10430 if (warn_on_deprecated
10431 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10432 as_tsktsk (_("setend use is deprecated for ARMv8"));
10434 if (inst
.operands
[0].imm
)
10435 inst
.instruction
|= 0x200;
10441 unsigned int Rm
= (inst
.operands
[1].present
10442 ? inst
.operands
[1].reg
10443 : inst
.operands
[0].reg
);
10445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10446 inst
.instruction
|= Rm
;
10447 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10449 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10450 inst
.instruction
|= SHIFT_BY_REG
;
10451 /* PR 12854: Error on extraneous shifts. */
10452 constraint (inst
.operands
[2].shifted
,
10453 _("extraneous shift as part of operand to shift insn"));
10456 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10462 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10463 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10465 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10466 inst
.relocs
[0].pc_rel
= 0;
10472 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10473 inst
.relocs
[0].pc_rel
= 0;
10479 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10480 inst
.relocs
[0].pc_rel
= 0;
10486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10487 _("selected processor does not support SETPAN instruction"));
10489 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10496 _("selected processor does not support SETPAN instruction"));
10498 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10501 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10502 SMLAxy{cond} Rd,Rm,Rs,Rn
10503 SMLAWy{cond} Rd,Rm,Rs,Rn
10504 Error if any register is R15. */
10509 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10510 inst
.instruction
|= inst
.operands
[1].reg
;
10511 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10512 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10515 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10516 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10517 Error if any register is R15.
10518 Warning if Rdlo == Rdhi. */
10523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10525 inst
.instruction
|= inst
.operands
[2].reg
;
10526 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10528 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10529 as_tsktsk (_("rdhi and rdlo must be different"));
10532 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10533 SMULxy{cond} Rd,Rm,Rs
10534 Error if any register is R15. */
10539 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10540 inst
.instruction
|= inst
.operands
[1].reg
;
10541 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10544 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10545 the same for both ARM and Thumb-2. */
10552 if (inst
.operands
[0].present
)
10554 reg
= inst
.operands
[0].reg
;
10555 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10560 inst
.instruction
|= reg
<< 16;
10561 inst
.instruction
|= inst
.operands
[1].imm
;
10562 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10563 inst
.instruction
|= WRITE_BACK
;
10566 /* ARM V6 strex (argument parse). */
10571 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10572 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10573 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10574 || inst
.operands
[2].negative
10575 /* See comment in do_ldrex(). */
10576 || (inst
.operands
[2].reg
== REG_PC
),
10579 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10580 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10582 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10583 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10584 _("offset must be zero in ARM encoding"));
10586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10587 inst
.instruction
|= inst
.operands
[1].reg
;
10588 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10589 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10593 do_t_strexbh (void)
10595 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10596 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10597 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10598 || inst
.operands
[2].negative
,
10601 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10602 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10610 constraint (inst
.operands
[1].reg
% 2 != 0,
10611 _("even register required"));
10612 constraint (inst
.operands
[2].present
10613 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10614 _("can only store two consecutive registers"));
10615 /* If op 2 were present and equal to PC, this function wouldn't
10616 have been called in the first place. */
10617 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10619 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10620 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10621 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10625 inst
.instruction
|= inst
.operands
[1].reg
;
10626 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10633 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10634 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10642 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10643 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10648 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10649 extends it to 32-bits, and adds the result to a value in another
10650 register. You can specify a rotation by 0, 8, 16, or 24 bits
10651 before extracting the 16-bit value.
10652 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10653 Condition defaults to COND_ALWAYS.
10654 Error if any register uses R15. */
10659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10661 inst
.instruction
|= inst
.operands
[2].reg
;
10662 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10667 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10668 Condition defaults to COND_ALWAYS.
10669 Error if any register uses R15. */
10674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10675 inst
.instruction
|= inst
.operands
[1].reg
;
10676 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10679 /* VFP instructions. In a logical order: SP variant first, monad
10680 before dyad, arithmetic then move then load/store. */
10683 do_vfp_sp_monadic (void)
10685 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10686 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10689 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10690 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10694 do_vfp_sp_dyadic (void)
10696 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10697 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10698 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10702 do_vfp_sp_compare_z (void)
10704 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10708 do_vfp_dp_sp_cvt (void)
10710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10711 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10715 do_vfp_sp_dp_cvt (void)
10717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10718 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10722 do_vfp_reg_from_sp (void)
10724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10725 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10729 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10733 do_vfp_reg2_from_sp2 (void)
10735 constraint (inst
.operands
[2].imm
!= 2,
10736 _("only two consecutive VFP SP registers allowed here"));
10737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10738 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10739 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10743 do_vfp_sp_from_reg (void)
10745 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10746 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10749 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10750 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10754 do_vfp_sp2_from_reg2 (void)
10756 constraint (inst
.operands
[0].imm
!= 2,
10757 _("only two consecutive VFP SP registers allowed here"));
10758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10759 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10760 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10764 do_vfp_sp_ldst (void)
10766 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10767 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10771 do_vfp_dp_ldst (void)
10773 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10774 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10779 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10781 if (inst
.operands
[0].writeback
)
10782 inst
.instruction
|= WRITE_BACK
;
10784 constraint (ldstm_type
!= VFP_LDSTMIA
,
10785 _("this addressing mode requires base-register writeback"));
10786 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10788 inst
.instruction
|= inst
.operands
[1].imm
;
10792 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10796 if (inst
.operands
[0].writeback
)
10797 inst
.instruction
|= WRITE_BACK
;
10799 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10800 _("this addressing mode requires base-register writeback"));
10802 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10803 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10805 count
= inst
.operands
[1].imm
<< 1;
10806 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10809 inst
.instruction
|= count
;
10813 do_vfp_sp_ldstmia (void)
10815 vfp_sp_ldstm (VFP_LDSTMIA
);
10819 do_vfp_sp_ldstmdb (void)
10821 vfp_sp_ldstm (VFP_LDSTMDB
);
10825 do_vfp_dp_ldstmia (void)
10827 vfp_dp_ldstm (VFP_LDSTMIA
);
10831 do_vfp_dp_ldstmdb (void)
10833 vfp_dp_ldstm (VFP_LDSTMDB
);
10837 do_vfp_xp_ldstmia (void)
10839 vfp_dp_ldstm (VFP_LDSTMIAX
);
10843 do_vfp_xp_ldstmdb (void)
10845 vfp_dp_ldstm (VFP_LDSTMDBX
);
10849 do_vfp_dp_rd_rm (void)
10851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10852 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10856 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10860 do_vfp_dp_rn_rd (void)
10862 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10863 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10867 do_vfp_dp_rd_rn (void)
10869 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10870 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10874 do_vfp_dp_rd_rn_rm (void)
10876 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10877 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10880 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10881 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10882 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10886 do_vfp_dp_rd (void)
10888 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10892 do_vfp_dp_rm_rd_rn (void)
10894 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10895 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10898 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10899 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10900 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10903 /* VFPv3 instructions. */
10905 do_vfp_sp_const (void)
10907 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10908 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10909 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10913 do_vfp_dp_const (void)
10915 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10916 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10917 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10921 vfp_conv (int srcsize
)
10923 int immbits
= srcsize
- inst
.operands
[1].imm
;
10925 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10927 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10928 i.e. immbits must be in range 0 - 16. */
10929 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10932 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10934 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10935 i.e. immbits must be in range 0 - 31. */
10936 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10940 inst
.instruction
|= (immbits
& 1) << 5;
10941 inst
.instruction
|= (immbits
>> 1);
10945 do_vfp_sp_conv_16 (void)
10947 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10952 do_vfp_dp_conv_16 (void)
10954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10959 do_vfp_sp_conv_32 (void)
10961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10966 do_vfp_dp_conv_32 (void)
10968 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10972 /* FPA instructions. Also in a logical order. */
10977 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10978 inst
.instruction
|= inst
.operands
[1].reg
;
10982 do_fpa_ldmstm (void)
10984 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10985 switch (inst
.operands
[1].imm
)
10987 case 1: inst
.instruction
|= CP_T_X
; break;
10988 case 2: inst
.instruction
|= CP_T_Y
; break;
10989 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10994 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10996 /* The instruction specified "ea" or "fd", so we can only accept
10997 [Rn]{!}. The instruction does not really support stacking or
10998 unstacking, so we have to emulate these by setting appropriate
10999 bits and offsets. */
11000 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11001 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11002 _("this instruction does not support indexing"));
11004 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11005 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11007 if (!(inst
.instruction
& INDEX_UP
))
11008 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11010 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11012 inst
.operands
[2].preind
= 0;
11013 inst
.operands
[2].postind
= 1;
11017 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11020 /* iWMMXt instructions: strictly in alphabetical order. */
11023 do_iwmmxt_tandorc (void)
11025 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11029 do_iwmmxt_textrc (void)
11031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11032 inst
.instruction
|= inst
.operands
[1].imm
;
11036 do_iwmmxt_textrm (void)
11038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11040 inst
.instruction
|= inst
.operands
[2].imm
;
11044 do_iwmmxt_tinsr (void)
11046 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11047 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11048 inst
.instruction
|= inst
.operands
[2].imm
;
11052 do_iwmmxt_tmia (void)
11054 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11055 inst
.instruction
|= inst
.operands
[1].reg
;
11056 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11060 do_iwmmxt_waligni (void)
11062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11063 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11064 inst
.instruction
|= inst
.operands
[2].reg
;
11065 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11069 do_iwmmxt_wmerge (void)
11071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11072 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11073 inst
.instruction
|= inst
.operands
[2].reg
;
11074 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11078 do_iwmmxt_wmov (void)
11080 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11082 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11083 inst
.instruction
|= inst
.operands
[1].reg
;
11087 do_iwmmxt_wldstbh (void)
11090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11092 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11094 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11095 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11099 do_iwmmxt_wldstw (void)
11101 /* RIWR_RIWC clears .isreg for a control register. */
11102 if (!inst
.operands
[0].isreg
)
11104 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11105 inst
.instruction
|= 0xf0000000;
11108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11109 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11113 do_iwmmxt_wldstd (void)
11115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11116 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11117 && inst
.operands
[1].immisreg
)
11119 inst
.instruction
&= ~0x1a000ff;
11120 inst
.instruction
|= (0xfU
<< 28);
11121 if (inst
.operands
[1].preind
)
11122 inst
.instruction
|= PRE_INDEX
;
11123 if (!inst
.operands
[1].negative
)
11124 inst
.instruction
|= INDEX_UP
;
11125 if (inst
.operands
[1].writeback
)
11126 inst
.instruction
|= WRITE_BACK
;
11127 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11128 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11129 inst
.instruction
|= inst
.operands
[1].imm
;
11132 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11136 do_iwmmxt_wshufh (void)
11138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11140 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11141 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11145 do_iwmmxt_wzero (void)
11147 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11148 inst
.instruction
|= inst
.operands
[0].reg
;
11149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11150 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11154 do_iwmmxt_wrwrwr_or_imm5 (void)
11156 if (inst
.operands
[2].isreg
)
11159 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11160 _("immediate operand requires iWMMXt2"));
11162 if (inst
.operands
[2].imm
== 0)
11164 switch ((inst
.instruction
>> 20) & 0xf)
11170 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11171 inst
.operands
[2].imm
= 16;
11172 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11178 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11179 inst
.operands
[2].imm
= 32;
11180 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11187 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11189 wrn
= (inst
.instruction
>> 16) & 0xf;
11190 inst
.instruction
&= 0xff0fff0f;
11191 inst
.instruction
|= wrn
;
11192 /* Bail out here; the instruction is now assembled. */
11197 /* Map 32 -> 0, etc. */
11198 inst
.operands
[2].imm
&= 0x1f;
11199 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11203 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11204 operations first, then control, shift, and load/store. */
11206 /* Insns like "foo X,Y,Z". */
11209 do_mav_triple (void)
11211 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11212 inst
.instruction
|= inst
.operands
[1].reg
;
11213 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11216 /* Insns like "foo W,X,Y,Z".
11217 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11222 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11223 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11224 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11225 inst
.instruction
|= inst
.operands
[3].reg
;
11228 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11230 do_mav_dspsc (void)
11232 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11235 /* Maverick shift immediate instructions.
11236 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11237 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11240 do_mav_shift (void)
11242 int imm
= inst
.operands
[2].imm
;
11244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11247 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11248 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11249 Bit 4 should be 0. */
11250 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11252 inst
.instruction
|= imm
;
11255 /* XScale instructions. Also sorted arithmetic before move. */
11257 /* Xscale multiply-accumulate (argument parse)
11260 MIAxycc acc0,Rm,Rs. */
11265 inst
.instruction
|= inst
.operands
[1].reg
;
11266 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11269 /* Xscale move-accumulator-register (argument parse)
11271 MARcc acc0,RdLo,RdHi. */
11276 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11277 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11280 /* Xscale move-register-accumulator (argument parse)
11282 MRAcc RdLo,RdHi,acc0. */
11287 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11289 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11292 /* Encoding functions relevant only to Thumb. */
11294 /* inst.operands[i] is a shifted-register operand; encode
11295 it into inst.instruction in the format used by Thumb32. */
11298 encode_thumb32_shifted_operand (int i
)
11300 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11301 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11303 constraint (inst
.operands
[i
].immisreg
,
11304 _("shift by register not allowed in thumb mode"));
11305 inst
.instruction
|= inst
.operands
[i
].reg
;
11306 if (shift
== SHIFT_RRX
)
11307 inst
.instruction
|= SHIFT_ROR
<< 4;
11310 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11311 _("expression too complex"));
11313 constraint (value
> 32
11314 || (value
== 32 && (shift
== SHIFT_LSL
11315 || shift
== SHIFT_ROR
)),
11316 _("shift expression is too large"));
11320 else if (value
== 32)
11323 inst
.instruction
|= shift
<< 4;
11324 inst
.instruction
|= (value
& 0x1c) << 10;
11325 inst
.instruction
|= (value
& 0x03) << 6;
11330 /* inst.operands[i] was set up by parse_address. Encode it into a
11331 Thumb32 format load or store instruction. Reject forms that cannot
11332 be used with such instructions. If is_t is true, reject forms that
11333 cannot be used with a T instruction; if is_d is true, reject forms
11334 that cannot be used with a D instruction. If it is a store insn,
11335 reject PC in Rn. */
11338 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11340 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11342 constraint (!inst
.operands
[i
].isreg
,
11343 _("Instruction does not support =N addresses"));
11345 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11346 if (inst
.operands
[i
].immisreg
)
11348 constraint (is_pc
, BAD_PC_ADDRESSING
);
11349 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11350 constraint (inst
.operands
[i
].negative
,
11351 _("Thumb does not support negative register indexing"));
11352 constraint (inst
.operands
[i
].postind
,
11353 _("Thumb does not support register post-indexing"));
11354 constraint (inst
.operands
[i
].writeback
,
11355 _("Thumb does not support register indexing with writeback"));
11356 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11357 _("Thumb supports only LSL in shifted register indexing"));
11359 inst
.instruction
|= inst
.operands
[i
].imm
;
11360 if (inst
.operands
[i
].shifted
)
11362 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11363 _("expression too complex"));
11364 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11365 || inst
.relocs
[0].exp
.X_add_number
> 3,
11366 _("shift out of range"));
11367 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11369 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11371 else if (inst
.operands
[i
].preind
)
11373 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11374 constraint (is_t
&& inst
.operands
[i
].writeback
,
11375 _("cannot use writeback with this instruction"));
11376 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11377 BAD_PC_ADDRESSING
);
11381 inst
.instruction
|= 0x01000000;
11382 if (inst
.operands
[i
].writeback
)
11383 inst
.instruction
|= 0x00200000;
11387 inst
.instruction
|= 0x00000c00;
11388 if (inst
.operands
[i
].writeback
)
11389 inst
.instruction
|= 0x00000100;
11391 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11393 else if (inst
.operands
[i
].postind
)
11395 gas_assert (inst
.operands
[i
].writeback
);
11396 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11397 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11400 inst
.instruction
|= 0x00200000;
11402 inst
.instruction
|= 0x00000900;
11403 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11405 else /* unindexed - only for coprocessor */
11406 inst
.error
= _("instruction does not accept unindexed addressing");
11409 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11410 encodings (the latter only in post-V6T2 cores). The index is the
11411 value used in the insns table below. When there is more than one
11412 possible 16-bit encoding for the instruction, this table always
11414 Also contains several pseudo-instructions used during relaxation. */
11415 #define T16_32_TAB \
11416 X(_adc, 4140, eb400000), \
11417 X(_adcs, 4140, eb500000), \
11418 X(_add, 1c00, eb000000), \
11419 X(_adds, 1c00, eb100000), \
11420 X(_addi, 0000, f1000000), \
11421 X(_addis, 0000, f1100000), \
11422 X(_add_pc,000f, f20f0000), \
11423 X(_add_sp,000d, f10d0000), \
11424 X(_adr, 000f, f20f0000), \
11425 X(_and, 4000, ea000000), \
11426 X(_ands, 4000, ea100000), \
11427 X(_asr, 1000, fa40f000), \
11428 X(_asrs, 1000, fa50f000), \
11429 X(_b, e000, f000b000), \
11430 X(_bcond, d000, f0008000), \
11431 X(_bf, 0000, f040e001), \
11432 X(_bfcsel,0000, f000e001), \
11433 X(_bfx, 0000, f060e001), \
11434 X(_bfl, 0000, f000c001), \
11435 X(_bflx, 0000, f070e001), \
11436 X(_bic, 4380, ea200000), \
11437 X(_bics, 4380, ea300000), \
11438 X(_cinc, 0000, ea509000), \
11439 X(_cinv, 0000, ea50a000), \
11440 X(_cmn, 42c0, eb100f00), \
11441 X(_cmp, 2800, ebb00f00), \
11442 X(_cneg, 0000, ea50b000), \
11443 X(_cpsie, b660, f3af8400), \
11444 X(_cpsid, b670, f3af8600), \
11445 X(_cpy, 4600, ea4f0000), \
11446 X(_csel, 0000, ea508000), \
11447 X(_cset, 0000, ea5f900f), \
11448 X(_csetm, 0000, ea5fa00f), \
11449 X(_csinc, 0000, ea509000), \
11450 X(_csinv, 0000, ea50a000), \
11451 X(_csneg, 0000, ea50b000), \
11452 X(_dec_sp,80dd, f1ad0d00), \
11453 X(_dls, 0000, f040e001), \
11454 X(_dlstp, 0000, f000e001), \
11455 X(_eor, 4040, ea800000), \
11456 X(_eors, 4040, ea900000), \
11457 X(_inc_sp,00dd, f10d0d00), \
11458 X(_lctp, 0000, f00fe001), \
11459 X(_ldmia, c800, e8900000), \
11460 X(_ldr, 6800, f8500000), \
11461 X(_ldrb, 7800, f8100000), \
11462 X(_ldrh, 8800, f8300000), \
11463 X(_ldrsb, 5600, f9100000), \
11464 X(_ldrsh, 5e00, f9300000), \
11465 X(_ldr_pc,4800, f85f0000), \
11466 X(_ldr_pc2,4800, f85f0000), \
11467 X(_ldr_sp,9800, f85d0000), \
11468 X(_le, 0000, f00fc001), \
11469 X(_letp, 0000, f01fc001), \
11470 X(_lsl, 0000, fa00f000), \
11471 X(_lsls, 0000, fa10f000), \
11472 X(_lsr, 0800, fa20f000), \
11473 X(_lsrs, 0800, fa30f000), \
11474 X(_mov, 2000, ea4f0000), \
11475 X(_movs, 2000, ea5f0000), \
11476 X(_mul, 4340, fb00f000), \
11477 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11478 X(_mvn, 43c0, ea6f0000), \
11479 X(_mvns, 43c0, ea7f0000), \
11480 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11481 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11482 X(_orr, 4300, ea400000), \
11483 X(_orrs, 4300, ea500000), \
11484 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11485 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11486 X(_rev, ba00, fa90f080), \
11487 X(_rev16, ba40, fa90f090), \
11488 X(_revsh, bac0, fa90f0b0), \
11489 X(_ror, 41c0, fa60f000), \
11490 X(_rors, 41c0, fa70f000), \
11491 X(_sbc, 4180, eb600000), \
11492 X(_sbcs, 4180, eb700000), \
11493 X(_stmia, c000, e8800000), \
11494 X(_str, 6000, f8400000), \
11495 X(_strb, 7000, f8000000), \
11496 X(_strh, 8000, f8200000), \
11497 X(_str_sp,9000, f84d0000), \
11498 X(_sub, 1e00, eba00000), \
11499 X(_subs, 1e00, ebb00000), \
11500 X(_subi, 8000, f1a00000), \
11501 X(_subis, 8000, f1b00000), \
11502 X(_sxtb, b240, fa4ff080), \
11503 X(_sxth, b200, fa0ff080), \
11504 X(_tst, 4200, ea100f00), \
11505 X(_uxtb, b2c0, fa5ff080), \
11506 X(_uxth, b280, fa1ff080), \
11507 X(_nop, bf00, f3af8000), \
11508 X(_yield, bf10, f3af8001), \
11509 X(_wfe, bf20, f3af8002), \
11510 X(_wfi, bf30, f3af8003), \
11511 X(_wls, 0000, f040c001), \
11512 X(_wlstp, 0000, f000c001), \
11513 X(_sev, bf40, f3af8004), \
11514 X(_sevl, bf50, f3af8005), \
11515 X(_udf, de00, f7f0a000)
11517 /* To catch errors in encoding functions, the codes are all offset by
11518 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11519 as 16-bit instructions. */
11520 #define X(a,b,c) T_MNEM##a
11521 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11524 #define X(a,b,c) 0x##b
11525 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11526 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11529 #define X(a,b,c) 0x##c
11530 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11531 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11532 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11536 /* Thumb instruction encoders, in alphabetical order. */
11538 /* ADDW or SUBW. */
11541 do_t_add_sub_w (void)
11545 Rd
= inst
.operands
[0].reg
;
11546 Rn
= inst
.operands
[1].reg
;
11548 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11549 is the SP-{plus,minus}-immediate form of the instruction. */
11551 constraint (Rd
== REG_PC
, BAD_PC
);
11553 reject_bad_reg (Rd
);
11555 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11556 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11559 /* Parse an add or subtract instruction. We get here with inst.instruction
11560 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11563 do_t_add_sub (void)
11567 Rd
= inst
.operands
[0].reg
;
11568 Rs
= (inst
.operands
[1].present
11569 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11570 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11573 set_pred_insn_type_last ();
11575 if (unified_syntax
)
11578 bfd_boolean narrow
;
11581 flags
= (inst
.instruction
== T_MNEM_adds
11582 || inst
.instruction
== T_MNEM_subs
);
11584 narrow
= !in_pred_block ();
11586 narrow
= in_pred_block ();
11587 if (!inst
.operands
[2].isreg
)
11591 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11592 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11594 add
= (inst
.instruction
== T_MNEM_add
11595 || inst
.instruction
== T_MNEM_adds
);
11597 if (inst
.size_req
!= 4)
11599 /* Attempt to use a narrow opcode, with relaxation if
11601 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11602 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11603 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11604 opcode
= T_MNEM_add_sp
;
11605 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11606 opcode
= T_MNEM_add_pc
;
11607 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11610 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11612 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11616 inst
.instruction
= THUMB_OP16(opcode
);
11617 inst
.instruction
|= (Rd
<< 4) | Rs
;
11618 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11619 || (inst
.relocs
[0].type
11620 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11622 if (inst
.size_req
== 2)
11623 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11625 inst
.relax
= opcode
;
11629 constraint (inst
.size_req
== 2, BAD_HIREG
);
11631 if (inst
.size_req
== 4
11632 || (inst
.size_req
!= 2 && !opcode
))
11634 constraint ((inst
.relocs
[0].type
11635 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11636 && (inst
.relocs
[0].type
11637 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11638 THUMB1_RELOC_ONLY
);
11641 constraint (add
, BAD_PC
);
11642 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11643 _("only SUBS PC, LR, #const allowed"));
11644 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11645 _("expression too complex"));
11646 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11647 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11648 _("immediate value out of range"));
11649 inst
.instruction
= T2_SUBS_PC_LR
11650 | inst
.relocs
[0].exp
.X_add_number
;
11651 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11654 else if (Rs
== REG_PC
)
11656 /* Always use addw/subw. */
11657 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11658 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11662 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11663 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11666 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11668 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11670 inst
.instruction
|= Rd
<< 8;
11671 inst
.instruction
|= Rs
<< 16;
11676 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11677 unsigned int shift
= inst
.operands
[2].shift_kind
;
11679 Rn
= inst
.operands
[2].reg
;
11680 /* See if we can do this with a 16-bit instruction. */
11681 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11683 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11688 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11689 || inst
.instruction
== T_MNEM_add
)
11691 : T_OPCODE_SUB_R3
);
11692 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11696 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11698 /* Thumb-1 cores (except v6-M) require at least one high
11699 register in a narrow non flag setting add. */
11700 if (Rd
> 7 || Rn
> 7
11701 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11702 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11709 inst
.instruction
= T_OPCODE_ADD_HI
;
11710 inst
.instruction
|= (Rd
& 8) << 4;
11711 inst
.instruction
|= (Rd
& 7);
11712 inst
.instruction
|= Rn
<< 3;
11718 constraint (Rd
== REG_PC
, BAD_PC
);
11719 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11720 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11721 constraint (Rs
== REG_PC
, BAD_PC
);
11722 reject_bad_reg (Rn
);
11724 /* If we get here, it can't be done in 16 bits. */
11725 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11726 _("shift must be constant"));
11727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11728 inst
.instruction
|= Rd
<< 8;
11729 inst
.instruction
|= Rs
<< 16;
11730 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11731 _("shift value over 3 not allowed in thumb mode"));
11732 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11733 _("only LSL shift allowed in thumb mode"));
11734 encode_thumb32_shifted_operand (2);
11739 constraint (inst
.instruction
== T_MNEM_adds
11740 || inst
.instruction
== T_MNEM_subs
,
11743 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11745 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11746 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11749 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11750 ? 0x0000 : 0x8000);
11751 inst
.instruction
|= (Rd
<< 4) | Rs
;
11752 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11756 Rn
= inst
.operands
[2].reg
;
11757 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11759 /* We now have Rd, Rs, and Rn set to registers. */
11760 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11762 /* Can't do this for SUB. */
11763 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11764 inst
.instruction
= T_OPCODE_ADD_HI
;
11765 inst
.instruction
|= (Rd
& 8) << 4;
11766 inst
.instruction
|= (Rd
& 7);
11768 inst
.instruction
|= Rn
<< 3;
11770 inst
.instruction
|= Rs
<< 3;
11772 constraint (1, _("dest must overlap one source register"));
11776 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11777 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11778 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11788 Rd
= inst
.operands
[0].reg
;
11789 reject_bad_reg (Rd
);
11791 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11793 /* Defer to section relaxation. */
11794 inst
.relax
= inst
.instruction
;
11795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11796 inst
.instruction
|= Rd
<< 4;
11798 else if (unified_syntax
&& inst
.size_req
!= 2)
11800 /* Generate a 32-bit opcode. */
11801 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11802 inst
.instruction
|= Rd
<< 8;
11803 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11804 inst
.relocs
[0].pc_rel
= 1;
11808 /* Generate a 16-bit opcode. */
11809 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11810 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11811 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11812 inst
.relocs
[0].pc_rel
= 1;
11813 inst
.instruction
|= Rd
<< 4;
11816 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11817 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11818 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11819 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11820 inst
.relocs
[0].exp
.X_add_number
+= 1;
11823 /* Arithmetic instructions for which there is just one 16-bit
11824 instruction encoding, and it allows only two low registers.
11825 For maximal compatibility with ARM syntax, we allow three register
11826 operands even when Thumb-32 instructions are not available, as long
11827 as the first two are identical. For instance, both "sbc r0,r1" and
11828 "sbc r0,r0,r1" are allowed. */
11834 Rd
= inst
.operands
[0].reg
;
11835 Rs
= (inst
.operands
[1].present
11836 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11837 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11838 Rn
= inst
.operands
[2].reg
;
11840 reject_bad_reg (Rd
);
11841 reject_bad_reg (Rs
);
11842 if (inst
.operands
[2].isreg
)
11843 reject_bad_reg (Rn
);
11845 if (unified_syntax
)
11847 if (!inst
.operands
[2].isreg
)
11849 /* For an immediate, we always generate a 32-bit opcode;
11850 section relaxation will shrink it later if possible. */
11851 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11852 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11853 inst
.instruction
|= Rd
<< 8;
11854 inst
.instruction
|= Rs
<< 16;
11855 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11859 bfd_boolean narrow
;
11861 /* See if we can do this with a 16-bit instruction. */
11862 if (THUMB_SETS_FLAGS (inst
.instruction
))
11863 narrow
= !in_pred_block ();
11865 narrow
= in_pred_block ();
11867 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11869 if (inst
.operands
[2].shifted
)
11871 if (inst
.size_req
== 4)
11877 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11878 inst
.instruction
|= Rd
;
11879 inst
.instruction
|= Rn
<< 3;
11883 /* If we get here, it can't be done in 16 bits. */
11884 constraint (inst
.operands
[2].shifted
11885 && inst
.operands
[2].immisreg
,
11886 _("shift must be constant"));
11887 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11888 inst
.instruction
|= Rd
<< 8;
11889 inst
.instruction
|= Rs
<< 16;
11890 encode_thumb32_shifted_operand (2);
11895 /* On its face this is a lie - the instruction does set the
11896 flags. However, the only supported mnemonic in this mode
11897 says it doesn't. */
11898 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11900 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11901 _("unshifted register required"));
11902 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11903 constraint (Rd
!= Rs
,
11904 _("dest and source1 must be the same register"));
11906 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11907 inst
.instruction
|= Rd
;
11908 inst
.instruction
|= Rn
<< 3;
11912 /* Similarly, but for instructions where the arithmetic operation is
11913 commutative, so we can allow either of them to be different from
11914 the destination operand in a 16-bit instruction. For instance, all
11915 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11922 Rd
= inst
.operands
[0].reg
;
11923 Rs
= (inst
.operands
[1].present
11924 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11925 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11926 Rn
= inst
.operands
[2].reg
;
11928 reject_bad_reg (Rd
);
11929 reject_bad_reg (Rs
);
11930 if (inst
.operands
[2].isreg
)
11931 reject_bad_reg (Rn
);
11933 if (unified_syntax
)
11935 if (!inst
.operands
[2].isreg
)
11937 /* For an immediate, we always generate a 32-bit opcode;
11938 section relaxation will shrink it later if possible. */
11939 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11940 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11941 inst
.instruction
|= Rd
<< 8;
11942 inst
.instruction
|= Rs
<< 16;
11943 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11947 bfd_boolean narrow
;
11949 /* See if we can do this with a 16-bit instruction. */
11950 if (THUMB_SETS_FLAGS (inst
.instruction
))
11951 narrow
= !in_pred_block ();
11953 narrow
= in_pred_block ();
11955 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11957 if (inst
.operands
[2].shifted
)
11959 if (inst
.size_req
== 4)
11966 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11967 inst
.instruction
|= Rd
;
11968 inst
.instruction
|= Rn
<< 3;
11973 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11974 inst
.instruction
|= Rd
;
11975 inst
.instruction
|= Rs
<< 3;
11980 /* If we get here, it can't be done in 16 bits. */
11981 constraint (inst
.operands
[2].shifted
11982 && inst
.operands
[2].immisreg
,
11983 _("shift must be constant"));
11984 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11985 inst
.instruction
|= Rd
<< 8;
11986 inst
.instruction
|= Rs
<< 16;
11987 encode_thumb32_shifted_operand (2);
11992 /* On its face this is a lie - the instruction does set the
11993 flags. However, the only supported mnemonic in this mode
11994 says it doesn't. */
11995 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11997 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11998 _("unshifted register required"));
11999 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12001 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12002 inst
.instruction
|= Rd
;
12005 inst
.instruction
|= Rn
<< 3;
12007 inst
.instruction
|= Rs
<< 3;
12009 constraint (1, _("dest must overlap one source register"));
12017 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12018 constraint (msb
> 32, _("bit-field extends past end of register"));
12019 /* The instruction encoding stores the LSB and MSB,
12020 not the LSB and width. */
12021 Rd
= inst
.operands
[0].reg
;
12022 reject_bad_reg (Rd
);
12023 inst
.instruction
|= Rd
<< 8;
12024 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12025 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12026 inst
.instruction
|= msb
- 1;
12035 Rd
= inst
.operands
[0].reg
;
12036 reject_bad_reg (Rd
);
12038 /* #0 in second position is alternative syntax for bfc, which is
12039 the same instruction but with REG_PC in the Rm field. */
12040 if (!inst
.operands
[1].isreg
)
12044 Rn
= inst
.operands
[1].reg
;
12045 reject_bad_reg (Rn
);
12048 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12049 constraint (msb
> 32, _("bit-field extends past end of register"));
12050 /* The instruction encoding stores the LSB and MSB,
12051 not the LSB and width. */
12052 inst
.instruction
|= Rd
<< 8;
12053 inst
.instruction
|= Rn
<< 16;
12054 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12055 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12056 inst
.instruction
|= msb
- 1;
12064 Rd
= inst
.operands
[0].reg
;
12065 Rn
= inst
.operands
[1].reg
;
12067 reject_bad_reg (Rd
);
12068 reject_bad_reg (Rn
);
12070 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12071 _("bit-field extends past end of register"));
12072 inst
.instruction
|= Rd
<< 8;
12073 inst
.instruction
|= Rn
<< 16;
12074 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12075 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12076 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12079 /* ARM V5 Thumb BLX (argument parse)
12080 BLX <target_addr> which is BLX(1)
12081 BLX <Rm> which is BLX(2)
12082 Unfortunately, there are two different opcodes for this mnemonic.
12083 So, the insns[].value is not used, and the code here zaps values
12084 into inst.instruction.
12086 ??? How to take advantage of the additional two bits of displacement
12087 available in Thumb32 mode? Need new relocation? */
12092 set_pred_insn_type_last ();
12094 if (inst
.operands
[0].isreg
)
12096 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12097 /* We have a register, so this is BLX(2). */
12098 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12102 /* No register. This must be BLX(1). */
12103 inst
.instruction
= 0xf000e800;
12104 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12113 bfd_reloc_code_real_type reloc
;
12116 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12118 if (in_pred_block ())
12120 /* Conditional branches inside IT blocks are encoded as unconditional
12122 cond
= COND_ALWAYS
;
12127 if (cond
!= COND_ALWAYS
)
12128 opcode
= T_MNEM_bcond
;
12130 opcode
= inst
.instruction
;
12133 && (inst
.size_req
== 4
12134 || (inst
.size_req
!= 2
12135 && (inst
.operands
[0].hasreloc
12136 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12138 inst
.instruction
= THUMB_OP32(opcode
);
12139 if (cond
== COND_ALWAYS
)
12140 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12144 _("selected architecture does not support "
12145 "wide conditional branch instruction"));
12147 gas_assert (cond
!= 0xF);
12148 inst
.instruction
|= cond
<< 22;
12149 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12154 inst
.instruction
= THUMB_OP16(opcode
);
12155 if (cond
== COND_ALWAYS
)
12156 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12159 inst
.instruction
|= cond
<< 8;
12160 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12162 /* Allow section relaxation. */
12163 if (unified_syntax
&& inst
.size_req
!= 2)
12164 inst
.relax
= opcode
;
12166 inst
.relocs
[0].type
= reloc
;
12167 inst
.relocs
[0].pc_rel
= 1;
12170 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12171 between the two is the maximum immediate allowed - which is passed in
12174 do_t_bkpt_hlt1 (int range
)
12176 constraint (inst
.cond
!= COND_ALWAYS
,
12177 _("instruction is always unconditional"));
12178 if (inst
.operands
[0].present
)
12180 constraint (inst
.operands
[0].imm
> range
,
12181 _("immediate value out of range"));
12182 inst
.instruction
|= inst
.operands
[0].imm
;
12185 set_pred_insn_type (NEUTRAL_IT_INSN
);
12191 do_t_bkpt_hlt1 (63);
12197 do_t_bkpt_hlt1 (255);
12201 do_t_branch23 (void)
12203 set_pred_insn_type_last ();
12204 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12206 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12207 this file. We used to simply ignore the PLT reloc type here --
12208 the branch encoding is now needed to deal with TLSCALL relocs.
12209 So if we see a PLT reloc now, put it back to how it used to be to
12210 keep the preexisting behaviour. */
12211 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12212 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12214 #if defined(OBJ_COFF)
12215 /* If the destination of the branch is a defined symbol which does not have
12216 the THUMB_FUNC attribute, then we must be calling a function which has
12217 the (interfacearm) attribute. We look for the Thumb entry point to that
12218 function and change the branch to refer to that function instead. */
12219 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12220 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12221 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12222 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12223 inst
.relocs
[0].exp
.X_add_symbol
12224 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12231 set_pred_insn_type_last ();
12232 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12233 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12234 should cause the alignment to be checked once it is known. This is
12235 because BX PC only works if the instruction is word aligned. */
12243 set_pred_insn_type_last ();
12244 Rm
= inst
.operands
[0].reg
;
12245 reject_bad_reg (Rm
);
12246 inst
.instruction
|= Rm
<< 16;
12255 Rd
= inst
.operands
[0].reg
;
12256 Rm
= inst
.operands
[1].reg
;
12258 reject_bad_reg (Rd
);
12259 reject_bad_reg (Rm
);
12261 inst
.instruction
|= Rd
<< 8;
12262 inst
.instruction
|= Rm
<< 16;
12263 inst
.instruction
|= Rm
;
12266 /* For the Armv8.1-M conditional instructions. */
12270 unsigned Rd
, Rn
, Rm
;
12273 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12275 Rd
= inst
.operands
[0].reg
;
12276 switch (inst
.instruction
)
12282 Rn
= inst
.operands
[1].reg
;
12283 Rm
= inst
.operands
[2].reg
;
12284 cond
= inst
.operands
[3].imm
;
12285 constraint (Rn
== REG_SP
, BAD_SP
);
12286 constraint (Rm
== REG_SP
, BAD_SP
);
12292 Rn
= inst
.operands
[1].reg
;
12293 cond
= inst
.operands
[2].imm
;
12294 /* Invert the last bit to invert the cond. */
12295 cond
= TOGGLE_BIT (cond
, 0);
12296 constraint (Rn
== REG_SP
, BAD_SP
);
12302 cond
= inst
.operands
[1].imm
;
12303 /* Invert the last bit to invert the cond. */
12304 cond
= TOGGLE_BIT (cond
, 0);
12312 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12314 inst
.instruction
|= Rd
<< 8;
12315 inst
.instruction
|= Rn
<< 16;
12316 inst
.instruction
|= Rm
;
12317 inst
.instruction
|= cond
<< 4;
12323 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12329 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12330 inst
.instruction
|= inst
.operands
[0].imm
;
12336 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12338 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12339 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12341 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12342 inst
.instruction
= 0xf3af8000;
12343 inst
.instruction
|= imod
<< 9;
12344 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12345 if (inst
.operands
[1].present
)
12346 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12350 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12351 && (inst
.operands
[0].imm
& 4),
12352 _("selected processor does not support 'A' form "
12353 "of this instruction"));
12354 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12355 _("Thumb does not support the 2-argument "
12356 "form of this instruction"));
12357 inst
.instruction
|= inst
.operands
[0].imm
;
12361 /* THUMB CPY instruction (argument parse). */
12366 if (inst
.size_req
== 4)
12368 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12369 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12370 inst
.instruction
|= inst
.operands
[1].reg
;
12374 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12375 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12376 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12383 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12384 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12385 inst
.instruction
|= inst
.operands
[0].reg
;
12386 inst
.relocs
[0].pc_rel
= 1;
12387 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12393 inst
.instruction
|= inst
.operands
[0].imm
;
12399 unsigned Rd
, Rn
, Rm
;
12401 Rd
= inst
.operands
[0].reg
;
12402 Rn
= (inst
.operands
[1].present
12403 ? inst
.operands
[1].reg
: Rd
);
12404 Rm
= inst
.operands
[2].reg
;
12406 reject_bad_reg (Rd
);
12407 reject_bad_reg (Rn
);
12408 reject_bad_reg (Rm
);
12410 inst
.instruction
|= Rd
<< 8;
12411 inst
.instruction
|= Rn
<< 16;
12412 inst
.instruction
|= Rm
;
12418 if (unified_syntax
&& inst
.size_req
== 4)
12419 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12421 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12427 unsigned int cond
= inst
.operands
[0].imm
;
12429 set_pred_insn_type (IT_INSN
);
12430 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12431 now_pred
.cc
= cond
;
12432 now_pred
.warn_deprecated
= FALSE
;
12433 now_pred
.type
= SCALAR_PRED
;
12435 /* If the condition is a negative condition, invert the mask. */
12436 if ((cond
& 0x1) == 0x0)
12438 unsigned int mask
= inst
.instruction
& 0x000f;
12440 if ((mask
& 0x7) == 0)
12442 /* No conversion needed. */
12443 now_pred
.block_length
= 1;
12445 else if ((mask
& 0x3) == 0)
12448 now_pred
.block_length
= 2;
12450 else if ((mask
& 0x1) == 0)
12453 now_pred
.block_length
= 3;
12458 now_pred
.block_length
= 4;
12461 inst
.instruction
&= 0xfff0;
12462 inst
.instruction
|= mask
;
12465 inst
.instruction
|= cond
<< 4;
12468 /* Helper function used for both push/pop and ldm/stm. */
12470 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12471 bfd_boolean writeback
)
12473 bfd_boolean load
, store
;
12475 gas_assert (base
!= -1 || !do_io
);
12476 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12477 store
= do_io
&& !load
;
12479 if (mask
& (1 << 13))
12480 inst
.error
= _("SP not allowed in register list");
12482 if (do_io
&& (mask
& (1 << base
)) != 0
12484 inst
.error
= _("having the base register in the register list when "
12485 "using write back is UNPREDICTABLE");
12489 if (mask
& (1 << 15))
12491 if (mask
& (1 << 14))
12492 inst
.error
= _("LR and PC should not both be in register list");
12494 set_pred_insn_type_last ();
12499 if (mask
& (1 << 15))
12500 inst
.error
= _("PC not allowed in register list");
12503 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12505 /* Single register transfers implemented as str/ldr. */
12508 if (inst
.instruction
& (1 << 23))
12509 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12511 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12515 if (inst
.instruction
& (1 << 23))
12516 inst
.instruction
= 0x00800000; /* ia -> [base] */
12518 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12521 inst
.instruction
|= 0xf8400000;
12523 inst
.instruction
|= 0x00100000;
12525 mask
= ffs (mask
) - 1;
12528 else if (writeback
)
12529 inst
.instruction
|= WRITE_BACK
;
12531 inst
.instruction
|= mask
;
12533 inst
.instruction
|= base
<< 16;
12539 /* This really doesn't seem worth it. */
12540 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12541 _("expression too complex"));
12542 constraint (inst
.operands
[1].writeback
,
12543 _("Thumb load/store multiple does not support {reglist}^"));
12545 if (unified_syntax
)
12547 bfd_boolean narrow
;
12551 /* See if we can use a 16-bit instruction. */
12552 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12553 && inst
.size_req
!= 4
12554 && !(inst
.operands
[1].imm
& ~0xff))
12556 mask
= 1 << inst
.operands
[0].reg
;
12558 if (inst
.operands
[0].reg
<= 7)
12560 if (inst
.instruction
== T_MNEM_stmia
12561 ? inst
.operands
[0].writeback
12562 : (inst
.operands
[0].writeback
12563 == !(inst
.operands
[1].imm
& mask
)))
12565 if (inst
.instruction
== T_MNEM_stmia
12566 && (inst
.operands
[1].imm
& mask
)
12567 && (inst
.operands
[1].imm
& (mask
- 1)))
12568 as_warn (_("value stored for r%d is UNKNOWN"),
12569 inst
.operands
[0].reg
);
12571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12572 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12573 inst
.instruction
|= inst
.operands
[1].imm
;
12576 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12578 /* This means 1 register in reg list one of 3 situations:
12579 1. Instruction is stmia, but without writeback.
12580 2. lmdia without writeback, but with Rn not in
12582 3. ldmia with writeback, but with Rn in reglist.
12583 Case 3 is UNPREDICTABLE behaviour, so we handle
12584 case 1 and 2 which can be converted into a 16-bit
12585 str or ldr. The SP cases are handled below. */
12586 unsigned long opcode
;
12587 /* First, record an error for Case 3. */
12588 if (inst
.operands
[1].imm
& mask
12589 && inst
.operands
[0].writeback
)
12591 _("having the base register in the register list when "
12592 "using write back is UNPREDICTABLE");
12594 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12596 inst
.instruction
= THUMB_OP16 (opcode
);
12597 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12598 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12602 else if (inst
.operands
[0] .reg
== REG_SP
)
12604 if (inst
.operands
[0].writeback
)
12607 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12608 ? T_MNEM_push
: T_MNEM_pop
);
12609 inst
.instruction
|= inst
.operands
[1].imm
;
12612 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12615 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12616 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12617 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12625 if (inst
.instruction
< 0xffff)
12626 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12628 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12629 inst
.operands
[1].imm
,
12630 inst
.operands
[0].writeback
);
12635 constraint (inst
.operands
[0].reg
> 7
12636 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12637 constraint (inst
.instruction
!= T_MNEM_ldmia
12638 && inst
.instruction
!= T_MNEM_stmia
,
12639 _("Thumb-2 instruction only valid in unified syntax"));
12640 if (inst
.instruction
== T_MNEM_stmia
)
12642 if (!inst
.operands
[0].writeback
)
12643 as_warn (_("this instruction will write back the base register"));
12644 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12645 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12646 as_warn (_("value stored for r%d is UNKNOWN"),
12647 inst
.operands
[0].reg
);
12651 if (!inst
.operands
[0].writeback
12652 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12653 as_warn (_("this instruction will write back the base register"));
12654 else if (inst
.operands
[0].writeback
12655 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12656 as_warn (_("this instruction will not write back the base register"));
12659 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12660 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12661 inst
.instruction
|= inst
.operands
[1].imm
;
12668 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12669 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12670 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12671 || inst
.operands
[1].negative
,
12674 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12677 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12678 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12684 if (!inst
.operands
[1].present
)
12686 constraint (inst
.operands
[0].reg
== REG_LR
,
12687 _("r14 not allowed as first register "
12688 "when second register is omitted"));
12689 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12691 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12695 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12696 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12702 unsigned long opcode
;
12705 if (inst
.operands
[0].isreg
12706 && !inst
.operands
[0].preind
12707 && inst
.operands
[0].reg
== REG_PC
)
12708 set_pred_insn_type_last ();
12710 opcode
= inst
.instruction
;
12711 if (unified_syntax
)
12713 if (!inst
.operands
[1].isreg
)
12715 if (opcode
<= 0xffff)
12716 inst
.instruction
= THUMB_OP32 (opcode
);
12717 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12720 if (inst
.operands
[1].isreg
12721 && !inst
.operands
[1].writeback
12722 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12723 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12724 && opcode
<= 0xffff
12725 && inst
.size_req
!= 4)
12727 /* Insn may have a 16-bit form. */
12728 Rn
= inst
.operands
[1].reg
;
12729 if (inst
.operands
[1].immisreg
)
12731 inst
.instruction
= THUMB_OP16 (opcode
);
12733 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12735 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12736 reject_bad_reg (inst
.operands
[1].imm
);
12738 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12739 && opcode
!= T_MNEM_ldrsb
)
12740 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12741 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12748 if (inst
.relocs
[0].pc_rel
)
12749 opcode
= T_MNEM_ldr_pc2
;
12751 opcode
= T_MNEM_ldr_pc
;
12755 if (opcode
== T_MNEM_ldr
)
12756 opcode
= T_MNEM_ldr_sp
;
12758 opcode
= T_MNEM_str_sp
;
12760 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12764 inst
.instruction
= inst
.operands
[0].reg
;
12765 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12767 inst
.instruction
|= THUMB_OP16 (opcode
);
12768 if (inst
.size_req
== 2)
12769 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12771 inst
.relax
= opcode
;
12775 /* Definitely a 32-bit variant. */
12777 /* Warning for Erratum 752419. */
12778 if (opcode
== T_MNEM_ldr
12779 && inst
.operands
[0].reg
== REG_SP
12780 && inst
.operands
[1].writeback
== 1
12781 && !inst
.operands
[1].immisreg
)
12783 if (no_cpu_selected ()
12784 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12785 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12786 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12787 as_warn (_("This instruction may be unpredictable "
12788 "if executed on M-profile cores "
12789 "with interrupts enabled."));
12792 /* Do some validations regarding addressing modes. */
12793 if (inst
.operands
[1].immisreg
)
12794 reject_bad_reg (inst
.operands
[1].imm
);
12796 constraint (inst
.operands
[1].writeback
== 1
12797 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12800 inst
.instruction
= THUMB_OP32 (opcode
);
12801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12802 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12803 check_ldr_r15_aligned ();
12807 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12809 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12811 /* Only [Rn,Rm] is acceptable. */
12812 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12813 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12814 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12815 || inst
.operands
[1].negative
,
12816 _("Thumb does not support this addressing mode"));
12817 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12822 if (!inst
.operands
[1].isreg
)
12823 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12826 constraint (!inst
.operands
[1].preind
12827 || inst
.operands
[1].shifted
12828 || inst
.operands
[1].writeback
,
12829 _("Thumb does not support this addressing mode"));
12830 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12832 constraint (inst
.instruction
& 0x0600,
12833 _("byte or halfword not valid for base register"));
12834 constraint (inst
.operands
[1].reg
== REG_PC
12835 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12836 _("r15 based store not allowed"));
12837 constraint (inst
.operands
[1].immisreg
,
12838 _("invalid base register for register offset"));
12840 if (inst
.operands
[1].reg
== REG_PC
)
12841 inst
.instruction
= T_OPCODE_LDR_PC
;
12842 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12843 inst
.instruction
= T_OPCODE_LDR_SP
;
12845 inst
.instruction
= T_OPCODE_STR_SP
;
12847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12852 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12853 if (!inst
.operands
[1].immisreg
)
12855 /* Immediate offset. */
12856 inst
.instruction
|= inst
.operands
[0].reg
;
12857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12858 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12862 /* Register offset. */
12863 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12864 constraint (inst
.operands
[1].negative
,
12865 _("Thumb does not support this addressing mode"));
12868 switch (inst
.instruction
)
12870 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12871 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12872 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12873 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12874 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12875 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12876 case 0x5600 /* ldrsb */:
12877 case 0x5e00 /* ldrsh */: break;
12881 inst
.instruction
|= inst
.operands
[0].reg
;
12882 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12883 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12889 if (!inst
.operands
[1].present
)
12891 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12892 constraint (inst
.operands
[0].reg
== REG_LR
,
12893 _("r14 not allowed here"));
12894 constraint (inst
.operands
[0].reg
== REG_R12
,
12895 _("r12 not allowed here"));
12898 if (inst
.operands
[2].writeback
12899 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12900 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12901 as_warn (_("base register written back, and overlaps "
12902 "one of transfer registers"));
12904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12905 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12906 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12913 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12919 unsigned Rd
, Rn
, Rm
, Ra
;
12921 Rd
= inst
.operands
[0].reg
;
12922 Rn
= inst
.operands
[1].reg
;
12923 Rm
= inst
.operands
[2].reg
;
12924 Ra
= inst
.operands
[3].reg
;
12926 reject_bad_reg (Rd
);
12927 reject_bad_reg (Rn
);
12928 reject_bad_reg (Rm
);
12929 reject_bad_reg (Ra
);
12931 inst
.instruction
|= Rd
<< 8;
12932 inst
.instruction
|= Rn
<< 16;
12933 inst
.instruction
|= Rm
;
12934 inst
.instruction
|= Ra
<< 12;
12940 unsigned RdLo
, RdHi
, Rn
, Rm
;
12942 RdLo
= inst
.operands
[0].reg
;
12943 RdHi
= inst
.operands
[1].reg
;
12944 Rn
= inst
.operands
[2].reg
;
12945 Rm
= inst
.operands
[3].reg
;
12947 reject_bad_reg (RdLo
);
12948 reject_bad_reg (RdHi
);
12949 reject_bad_reg (Rn
);
12950 reject_bad_reg (Rm
);
12952 inst
.instruction
|= RdLo
<< 12;
12953 inst
.instruction
|= RdHi
<< 8;
12954 inst
.instruction
|= Rn
<< 16;
12955 inst
.instruction
|= Rm
;
12959 do_t_mov_cmp (void)
12963 Rn
= inst
.operands
[0].reg
;
12964 Rm
= inst
.operands
[1].reg
;
12967 set_pred_insn_type_last ();
12969 if (unified_syntax
)
12971 int r0off
= (inst
.instruction
== T_MNEM_mov
12972 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12973 unsigned long opcode
;
12974 bfd_boolean narrow
;
12975 bfd_boolean low_regs
;
12977 low_regs
= (Rn
<= 7 && Rm
<= 7);
12978 opcode
= inst
.instruction
;
12979 if (in_pred_block ())
12980 narrow
= opcode
!= T_MNEM_movs
;
12982 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12983 if (inst
.size_req
== 4
12984 || inst
.operands
[1].shifted
)
12987 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12988 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12989 && !inst
.operands
[1].shifted
12993 inst
.instruction
= T2_SUBS_PC_LR
;
12997 if (opcode
== T_MNEM_cmp
)
12999 constraint (Rn
== REG_PC
, BAD_PC
);
13002 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13004 warn_deprecated_sp (Rm
);
13005 /* R15 was documented as a valid choice for Rm in ARMv6,
13006 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13007 tools reject R15, so we do too. */
13008 constraint (Rm
== REG_PC
, BAD_PC
);
13011 reject_bad_reg (Rm
);
13013 else if (opcode
== T_MNEM_mov
13014 || opcode
== T_MNEM_movs
)
13016 if (inst
.operands
[1].isreg
)
13018 if (opcode
== T_MNEM_movs
)
13020 reject_bad_reg (Rn
);
13021 reject_bad_reg (Rm
);
13025 /* This is mov.n. */
13026 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13027 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13029 as_tsktsk (_("Use of r%u as a source register is "
13030 "deprecated when r%u is the destination "
13031 "register."), Rm
, Rn
);
13036 /* This is mov.w. */
13037 constraint (Rn
== REG_PC
, BAD_PC
);
13038 constraint (Rm
== REG_PC
, BAD_PC
);
13039 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13040 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13044 reject_bad_reg (Rn
);
13047 if (!inst
.operands
[1].isreg
)
13049 /* Immediate operand. */
13050 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13052 if (low_regs
&& narrow
)
13054 inst
.instruction
= THUMB_OP16 (opcode
);
13055 inst
.instruction
|= Rn
<< 8;
13056 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13057 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13059 if (inst
.size_req
== 2)
13060 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13062 inst
.relax
= opcode
;
13067 constraint ((inst
.relocs
[0].type
13068 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13069 && (inst
.relocs
[0].type
13070 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13071 THUMB1_RELOC_ONLY
);
13073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13074 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13075 inst
.instruction
|= Rn
<< r0off
;
13076 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13079 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13080 && (inst
.instruction
== T_MNEM_mov
13081 || inst
.instruction
== T_MNEM_movs
))
13083 /* Register shifts are encoded as separate shift instructions. */
13084 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13086 if (in_pred_block ())
13091 if (inst
.size_req
== 4)
13094 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13100 switch (inst
.operands
[1].shift_kind
)
13103 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13106 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13109 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13112 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13118 inst
.instruction
= opcode
;
13121 inst
.instruction
|= Rn
;
13122 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13127 inst
.instruction
|= CONDS_BIT
;
13129 inst
.instruction
|= Rn
<< 8;
13130 inst
.instruction
|= Rm
<< 16;
13131 inst
.instruction
|= inst
.operands
[1].imm
;
13136 /* Some mov with immediate shift have narrow variants.
13137 Register shifts are handled above. */
13138 if (low_regs
&& inst
.operands
[1].shifted
13139 && (inst
.instruction
== T_MNEM_mov
13140 || inst
.instruction
== T_MNEM_movs
))
13142 if (in_pred_block ())
13143 narrow
= (inst
.instruction
== T_MNEM_mov
);
13145 narrow
= (inst
.instruction
== T_MNEM_movs
);
13150 switch (inst
.operands
[1].shift_kind
)
13152 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13153 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13154 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13155 default: narrow
= FALSE
; break;
13161 inst
.instruction
|= Rn
;
13162 inst
.instruction
|= Rm
<< 3;
13163 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13167 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13168 inst
.instruction
|= Rn
<< r0off
;
13169 encode_thumb32_shifted_operand (1);
13173 switch (inst
.instruction
)
13176 /* In v4t or v5t a move of two lowregs produces unpredictable
13177 results. Don't allow this. */
13180 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13181 "MOV Rd, Rs with two low registers is not "
13182 "permitted on this architecture");
13183 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13187 inst
.instruction
= T_OPCODE_MOV_HR
;
13188 inst
.instruction
|= (Rn
& 0x8) << 4;
13189 inst
.instruction
|= (Rn
& 0x7);
13190 inst
.instruction
|= Rm
<< 3;
13194 /* We know we have low registers at this point.
13195 Generate LSLS Rd, Rs, #0. */
13196 inst
.instruction
= T_OPCODE_LSL_I
;
13197 inst
.instruction
|= Rn
;
13198 inst
.instruction
|= Rm
<< 3;
13204 inst
.instruction
= T_OPCODE_CMP_LR
;
13205 inst
.instruction
|= Rn
;
13206 inst
.instruction
|= Rm
<< 3;
13210 inst
.instruction
= T_OPCODE_CMP_HR
;
13211 inst
.instruction
|= (Rn
& 0x8) << 4;
13212 inst
.instruction
|= (Rn
& 0x7);
13213 inst
.instruction
|= Rm
<< 3;
13220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13222 /* PR 10443: Do not silently ignore shifted operands. */
13223 constraint (inst
.operands
[1].shifted
,
13224 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13226 if (inst
.operands
[1].isreg
)
13228 if (Rn
< 8 && Rm
< 8)
13230 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13231 since a MOV instruction produces unpredictable results. */
13232 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13233 inst
.instruction
= T_OPCODE_ADD_I3
;
13235 inst
.instruction
= T_OPCODE_CMP_LR
;
13237 inst
.instruction
|= Rn
;
13238 inst
.instruction
|= Rm
<< 3;
13242 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13243 inst
.instruction
= T_OPCODE_MOV_HR
;
13245 inst
.instruction
= T_OPCODE_CMP_HR
;
13251 constraint (Rn
> 7,
13252 _("only lo regs allowed with immediate"));
13253 inst
.instruction
|= Rn
<< 8;
13254 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13265 top
= (inst
.instruction
& 0x00800000) != 0;
13266 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13268 constraint (top
, _(":lower16: not allowed in this instruction"));
13269 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13271 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13273 constraint (!top
, _(":upper16: not allowed in this instruction"));
13274 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13277 Rd
= inst
.operands
[0].reg
;
13278 reject_bad_reg (Rd
);
13280 inst
.instruction
|= Rd
<< 8;
13281 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13283 imm
= inst
.relocs
[0].exp
.X_add_number
;
13284 inst
.instruction
|= (imm
& 0xf000) << 4;
13285 inst
.instruction
|= (imm
& 0x0800) << 15;
13286 inst
.instruction
|= (imm
& 0x0700) << 4;
13287 inst
.instruction
|= (imm
& 0x00ff);
13292 do_t_mvn_tst (void)
13296 Rn
= inst
.operands
[0].reg
;
13297 Rm
= inst
.operands
[1].reg
;
13299 if (inst
.instruction
== T_MNEM_cmp
13300 || inst
.instruction
== T_MNEM_cmn
)
13301 constraint (Rn
== REG_PC
, BAD_PC
);
13303 reject_bad_reg (Rn
);
13304 reject_bad_reg (Rm
);
13306 if (unified_syntax
)
13308 int r0off
= (inst
.instruction
== T_MNEM_mvn
13309 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13310 bfd_boolean narrow
;
13312 if (inst
.size_req
== 4
13313 || inst
.instruction
> 0xffff
13314 || inst
.operands
[1].shifted
13315 || Rn
> 7 || Rm
> 7)
13317 else if (inst
.instruction
== T_MNEM_cmn
13318 || inst
.instruction
== T_MNEM_tst
)
13320 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13321 narrow
= !in_pred_block ();
13323 narrow
= in_pred_block ();
13325 if (!inst
.operands
[1].isreg
)
13327 /* For an immediate, we always generate a 32-bit opcode;
13328 section relaxation will shrink it later if possible. */
13329 if (inst
.instruction
< 0xffff)
13330 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13331 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13332 inst
.instruction
|= Rn
<< r0off
;
13333 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13337 /* See if we can do this with a 16-bit instruction. */
13340 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13341 inst
.instruction
|= Rn
;
13342 inst
.instruction
|= Rm
<< 3;
13346 constraint (inst
.operands
[1].shifted
13347 && inst
.operands
[1].immisreg
,
13348 _("shift must be constant"));
13349 if (inst
.instruction
< 0xffff)
13350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13351 inst
.instruction
|= Rn
<< r0off
;
13352 encode_thumb32_shifted_operand (1);
13358 constraint (inst
.instruction
> 0xffff
13359 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13360 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13361 _("unshifted register required"));
13362 constraint (Rn
> 7 || Rm
> 7,
13365 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13366 inst
.instruction
|= Rn
;
13367 inst
.instruction
|= Rm
<< 3;
13376 if (do_vfp_nsyn_mrs () == SUCCESS
)
13379 Rd
= inst
.operands
[0].reg
;
13380 reject_bad_reg (Rd
);
13381 inst
.instruction
|= Rd
<< 8;
13383 if (inst
.operands
[1].isreg
)
13385 unsigned br
= inst
.operands
[1].reg
;
13386 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13387 as_bad (_("bad register for mrs"));
13389 inst
.instruction
|= br
& (0xf << 16);
13390 inst
.instruction
|= (br
& 0x300) >> 4;
13391 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13395 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13397 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13399 /* PR gas/12698: The constraint is only applied for m_profile.
13400 If the user has specified -march=all, we want to ignore it as
13401 we are building for any CPU type, including non-m variants. */
13402 bfd_boolean m_profile
=
13403 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13404 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13405 "not support requested special purpose register"));
13408 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13410 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13411 _("'APSR', 'CPSR' or 'SPSR' expected"));
13413 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13414 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13415 inst
.instruction
|= 0xf0000;
13425 if (do_vfp_nsyn_msr () == SUCCESS
)
13428 constraint (!inst
.operands
[1].isreg
,
13429 _("Thumb encoding does not support an immediate here"));
13431 if (inst
.operands
[0].isreg
)
13432 flags
= (int)(inst
.operands
[0].reg
);
13434 flags
= inst
.operands
[0].imm
;
13436 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13438 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13440 /* PR gas/12698: The constraint is only applied for m_profile.
13441 If the user has specified -march=all, we want to ignore it as
13442 we are building for any CPU type, including non-m variants. */
13443 bfd_boolean m_profile
=
13444 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13445 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13446 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13447 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13448 && bits
!= PSR_f
)) && m_profile
,
13449 _("selected processor does not support requested special "
13450 "purpose register"));
13453 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13454 "requested special purpose register"));
13456 Rn
= inst
.operands
[1].reg
;
13457 reject_bad_reg (Rn
);
13459 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13460 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13461 inst
.instruction
|= (flags
& 0x300) >> 4;
13462 inst
.instruction
|= (flags
& 0xff);
13463 inst
.instruction
|= Rn
<< 16;
13469 bfd_boolean narrow
;
13470 unsigned Rd
, Rn
, Rm
;
13472 if (!inst
.operands
[2].present
)
13473 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13475 Rd
= inst
.operands
[0].reg
;
13476 Rn
= inst
.operands
[1].reg
;
13477 Rm
= inst
.operands
[2].reg
;
13479 if (unified_syntax
)
13481 if (inst
.size_req
== 4
13487 else if (inst
.instruction
== T_MNEM_muls
)
13488 narrow
= !in_pred_block ();
13490 narrow
= in_pred_block ();
13494 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13495 constraint (Rn
> 7 || Rm
> 7,
13502 /* 16-bit MULS/Conditional MUL. */
13503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13504 inst
.instruction
|= Rd
;
13507 inst
.instruction
|= Rm
<< 3;
13509 inst
.instruction
|= Rn
<< 3;
13511 constraint (1, _("dest must overlap one source register"));
13515 constraint (inst
.instruction
!= T_MNEM_mul
,
13516 _("Thumb-2 MUL must not set flags"));
13518 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13519 inst
.instruction
|= Rd
<< 8;
13520 inst
.instruction
|= Rn
<< 16;
13521 inst
.instruction
|= Rm
<< 0;
13523 reject_bad_reg (Rd
);
13524 reject_bad_reg (Rn
);
13525 reject_bad_reg (Rm
);
13532 unsigned RdLo
, RdHi
, Rn
, Rm
;
13534 RdLo
= inst
.operands
[0].reg
;
13535 RdHi
= inst
.operands
[1].reg
;
13536 Rn
= inst
.operands
[2].reg
;
13537 Rm
= inst
.operands
[3].reg
;
13539 reject_bad_reg (RdLo
);
13540 reject_bad_reg (RdHi
);
13541 reject_bad_reg (Rn
);
13542 reject_bad_reg (Rm
);
13544 inst
.instruction
|= RdLo
<< 12;
13545 inst
.instruction
|= RdHi
<< 8;
13546 inst
.instruction
|= Rn
<< 16;
13547 inst
.instruction
|= Rm
;
13550 as_tsktsk (_("rdhi and rdlo must be different"));
13556 set_pred_insn_type (NEUTRAL_IT_INSN
);
13558 if (unified_syntax
)
13560 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13562 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13563 inst
.instruction
|= inst
.operands
[0].imm
;
13567 /* PR9722: Check for Thumb2 availability before
13568 generating a thumb2 nop instruction. */
13569 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13572 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13575 inst
.instruction
= 0x46c0;
13580 constraint (inst
.operands
[0].present
,
13581 _("Thumb does not support NOP with hints"));
13582 inst
.instruction
= 0x46c0;
13589 if (unified_syntax
)
13591 bfd_boolean narrow
;
13593 if (THUMB_SETS_FLAGS (inst
.instruction
))
13594 narrow
= !in_pred_block ();
13596 narrow
= in_pred_block ();
13597 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13599 if (inst
.size_req
== 4)
13604 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13610 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13611 inst
.instruction
|= inst
.operands
[0].reg
;
13612 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13617 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13619 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13621 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13622 inst
.instruction
|= inst
.operands
[0].reg
;
13623 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13632 Rd
= inst
.operands
[0].reg
;
13633 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13635 reject_bad_reg (Rd
);
13636 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13637 reject_bad_reg (Rn
);
13639 inst
.instruction
|= Rd
<< 8;
13640 inst
.instruction
|= Rn
<< 16;
13642 if (!inst
.operands
[2].isreg
)
13644 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13645 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13651 Rm
= inst
.operands
[2].reg
;
13652 reject_bad_reg (Rm
);
13654 constraint (inst
.operands
[2].shifted
13655 && inst
.operands
[2].immisreg
,
13656 _("shift must be constant"));
13657 encode_thumb32_shifted_operand (2);
13664 unsigned Rd
, Rn
, Rm
;
13666 Rd
= inst
.operands
[0].reg
;
13667 Rn
= inst
.operands
[1].reg
;
13668 Rm
= inst
.operands
[2].reg
;
13670 reject_bad_reg (Rd
);
13671 reject_bad_reg (Rn
);
13672 reject_bad_reg (Rm
);
13674 inst
.instruction
|= Rd
<< 8;
13675 inst
.instruction
|= Rn
<< 16;
13676 inst
.instruction
|= Rm
;
13677 if (inst
.operands
[3].present
)
13679 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13680 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13681 _("expression too complex"));
13682 inst
.instruction
|= (val
& 0x1c) << 10;
13683 inst
.instruction
|= (val
& 0x03) << 6;
13690 if (!inst
.operands
[3].present
)
13694 inst
.instruction
&= ~0x00000020;
13696 /* PR 10168. Swap the Rm and Rn registers. */
13697 Rtmp
= inst
.operands
[1].reg
;
13698 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13699 inst
.operands
[2].reg
= Rtmp
;
13707 if (inst
.operands
[0].immisreg
)
13708 reject_bad_reg (inst
.operands
[0].imm
);
13710 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13714 do_t_push_pop (void)
13718 constraint (inst
.operands
[0].writeback
,
13719 _("push/pop do not support {reglist}^"));
13720 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13721 _("expression too complex"));
13723 mask
= inst
.operands
[0].imm
;
13724 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13725 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13726 else if (inst
.size_req
!= 4
13727 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13728 ? REG_LR
: REG_PC
)))
13730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13731 inst
.instruction
|= THUMB_PP_PC_LR
;
13732 inst
.instruction
|= mask
& 0xff;
13734 else if (unified_syntax
)
13736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13737 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13741 inst
.error
= _("invalid register list to push/pop instruction");
13749 if (unified_syntax
)
13750 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13753 inst
.error
= _("invalid register list to push/pop instruction");
13759 do_t_vscclrm (void)
13761 if (inst
.operands
[0].issingle
)
13763 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13764 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13765 inst
.instruction
|= inst
.operands
[0].imm
;
13769 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13770 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13771 inst
.instruction
|= 1 << 8;
13772 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13781 Rd
= inst
.operands
[0].reg
;
13782 Rm
= inst
.operands
[1].reg
;
13784 reject_bad_reg (Rd
);
13785 reject_bad_reg (Rm
);
13787 inst
.instruction
|= Rd
<< 8;
13788 inst
.instruction
|= Rm
<< 16;
13789 inst
.instruction
|= Rm
;
13797 Rd
= inst
.operands
[0].reg
;
13798 Rm
= inst
.operands
[1].reg
;
13800 reject_bad_reg (Rd
);
13801 reject_bad_reg (Rm
);
13803 if (Rd
<= 7 && Rm
<= 7
13804 && inst
.size_req
!= 4)
13806 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13807 inst
.instruction
|= Rd
;
13808 inst
.instruction
|= Rm
<< 3;
13810 else if (unified_syntax
)
13812 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13813 inst
.instruction
|= Rd
<< 8;
13814 inst
.instruction
|= Rm
<< 16;
13815 inst
.instruction
|= Rm
;
13818 inst
.error
= BAD_HIREG
;
13826 Rd
= inst
.operands
[0].reg
;
13827 Rm
= inst
.operands
[1].reg
;
13829 reject_bad_reg (Rd
);
13830 reject_bad_reg (Rm
);
13832 inst
.instruction
|= Rd
<< 8;
13833 inst
.instruction
|= Rm
;
13841 Rd
= inst
.operands
[0].reg
;
13842 Rs
= (inst
.operands
[1].present
13843 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13844 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13846 reject_bad_reg (Rd
);
13847 reject_bad_reg (Rs
);
13848 if (inst
.operands
[2].isreg
)
13849 reject_bad_reg (inst
.operands
[2].reg
);
13851 inst
.instruction
|= Rd
<< 8;
13852 inst
.instruction
|= Rs
<< 16;
13853 if (!inst
.operands
[2].isreg
)
13855 bfd_boolean narrow
;
13857 if ((inst
.instruction
& 0x00100000) != 0)
13858 narrow
= !in_pred_block ();
13860 narrow
= in_pred_block ();
13862 if (Rd
> 7 || Rs
> 7)
13865 if (inst
.size_req
== 4 || !unified_syntax
)
13868 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13869 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13872 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13873 relaxation, but it doesn't seem worth the hassle. */
13876 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13877 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13878 inst
.instruction
|= Rs
<< 3;
13879 inst
.instruction
|= Rd
;
13883 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13884 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13888 encode_thumb32_shifted_operand (2);
13894 if (warn_on_deprecated
13895 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13896 as_tsktsk (_("setend use is deprecated for ARMv8"));
13898 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13899 if (inst
.operands
[0].imm
)
13900 inst
.instruction
|= 0x8;
13906 if (!inst
.operands
[1].present
)
13907 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13909 if (unified_syntax
)
13911 bfd_boolean narrow
;
13914 switch (inst
.instruction
)
13917 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13919 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13921 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13923 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13927 if (THUMB_SETS_FLAGS (inst
.instruction
))
13928 narrow
= !in_pred_block ();
13930 narrow
= in_pred_block ();
13931 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13933 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13935 if (inst
.operands
[2].isreg
13936 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13937 || inst
.operands
[2].reg
> 7))
13939 if (inst
.size_req
== 4)
13942 reject_bad_reg (inst
.operands
[0].reg
);
13943 reject_bad_reg (inst
.operands
[1].reg
);
13947 if (inst
.operands
[2].isreg
)
13949 reject_bad_reg (inst
.operands
[2].reg
);
13950 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13951 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13952 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13953 inst
.instruction
|= inst
.operands
[2].reg
;
13955 /* PR 12854: Error on extraneous shifts. */
13956 constraint (inst
.operands
[2].shifted
,
13957 _("extraneous shift as part of operand to shift insn"));
13961 inst
.operands
[1].shifted
= 1;
13962 inst
.operands
[1].shift_kind
= shift_kind
;
13963 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13964 ? T_MNEM_movs
: T_MNEM_mov
);
13965 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13966 encode_thumb32_shifted_operand (1);
13967 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13968 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13973 if (inst
.operands
[2].isreg
)
13975 switch (shift_kind
)
13977 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13978 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13979 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13980 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13984 inst
.instruction
|= inst
.operands
[0].reg
;
13985 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13987 /* PR 12854: Error on extraneous shifts. */
13988 constraint (inst
.operands
[2].shifted
,
13989 _("extraneous shift as part of operand to shift insn"));
13993 switch (shift_kind
)
13995 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13996 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13997 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14000 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14001 inst
.instruction
|= inst
.operands
[0].reg
;
14002 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14008 constraint (inst
.operands
[0].reg
> 7
14009 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14010 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14012 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14014 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14015 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14016 _("source1 and dest must be same register"));
14018 switch (inst
.instruction
)
14020 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14021 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14022 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14023 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14027 inst
.instruction
|= inst
.operands
[0].reg
;
14028 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14030 /* PR 12854: Error on extraneous shifts. */
14031 constraint (inst
.operands
[2].shifted
,
14032 _("extraneous shift as part of operand to shift insn"));
14036 switch (inst
.instruction
)
14038 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14039 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14040 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14041 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14044 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14045 inst
.instruction
|= inst
.operands
[0].reg
;
14046 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14054 unsigned Rd
, Rn
, Rm
;
14056 Rd
= inst
.operands
[0].reg
;
14057 Rn
= inst
.operands
[1].reg
;
14058 Rm
= inst
.operands
[2].reg
;
14060 reject_bad_reg (Rd
);
14061 reject_bad_reg (Rn
);
14062 reject_bad_reg (Rm
);
14064 inst
.instruction
|= Rd
<< 8;
14065 inst
.instruction
|= Rn
<< 16;
14066 inst
.instruction
|= Rm
;
14072 unsigned Rd
, Rn
, Rm
;
14074 Rd
= inst
.operands
[0].reg
;
14075 Rm
= inst
.operands
[1].reg
;
14076 Rn
= inst
.operands
[2].reg
;
14078 reject_bad_reg (Rd
);
14079 reject_bad_reg (Rn
);
14080 reject_bad_reg (Rm
);
14082 inst
.instruction
|= Rd
<< 8;
14083 inst
.instruction
|= Rn
<< 16;
14084 inst
.instruction
|= Rm
;
14090 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14092 _("SMC is not permitted on this architecture"));
14093 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14094 _("expression too complex"));
14095 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14097 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14098 inst
.instruction
|= (value
& 0x000f) << 16;
14100 /* PR gas/15623: SMC instructions must be last in an IT block. */
14101 set_pred_insn_type_last ();
14107 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14109 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14110 inst
.instruction
|= (value
& 0x0fff);
14111 inst
.instruction
|= (value
& 0xf000) << 4;
14115 do_t_ssat_usat (int bias
)
14119 Rd
= inst
.operands
[0].reg
;
14120 Rn
= inst
.operands
[2].reg
;
14122 reject_bad_reg (Rd
);
14123 reject_bad_reg (Rn
);
14125 inst
.instruction
|= Rd
<< 8;
14126 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14127 inst
.instruction
|= Rn
<< 16;
14129 if (inst
.operands
[3].present
)
14131 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14133 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14135 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14136 _("expression too complex"));
14138 if (shift_amount
!= 0)
14140 constraint (shift_amount
> 31,
14141 _("shift expression is too large"));
14143 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14144 inst
.instruction
|= 0x00200000; /* sh bit. */
14146 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14147 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14155 do_t_ssat_usat (1);
14163 Rd
= inst
.operands
[0].reg
;
14164 Rn
= inst
.operands
[2].reg
;
14166 reject_bad_reg (Rd
);
14167 reject_bad_reg (Rn
);
14169 inst
.instruction
|= Rd
<< 8;
14170 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14171 inst
.instruction
|= Rn
<< 16;
14177 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14178 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14179 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14180 || inst
.operands
[2].negative
,
14183 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14185 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14186 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14187 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14188 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14194 if (!inst
.operands
[2].present
)
14195 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14197 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14198 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14199 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14202 inst
.instruction
|= inst
.operands
[0].reg
;
14203 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14204 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14205 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14211 unsigned Rd
, Rn
, Rm
;
14213 Rd
= inst
.operands
[0].reg
;
14214 Rn
= inst
.operands
[1].reg
;
14215 Rm
= inst
.operands
[2].reg
;
14217 reject_bad_reg (Rd
);
14218 reject_bad_reg (Rn
);
14219 reject_bad_reg (Rm
);
14221 inst
.instruction
|= Rd
<< 8;
14222 inst
.instruction
|= Rn
<< 16;
14223 inst
.instruction
|= Rm
;
14224 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14232 Rd
= inst
.operands
[0].reg
;
14233 Rm
= inst
.operands
[1].reg
;
14235 reject_bad_reg (Rd
);
14236 reject_bad_reg (Rm
);
14238 if (inst
.instruction
<= 0xffff
14239 && inst
.size_req
!= 4
14240 && Rd
<= 7 && Rm
<= 7
14241 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14243 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14244 inst
.instruction
|= Rd
;
14245 inst
.instruction
|= Rm
<< 3;
14247 else if (unified_syntax
)
14249 if (inst
.instruction
<= 0xffff)
14250 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14251 inst
.instruction
|= Rd
<< 8;
14252 inst
.instruction
|= Rm
;
14253 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14257 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14258 _("Thumb encoding does not support rotation"));
14259 constraint (1, BAD_HIREG
);
14266 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14275 half
= (inst
.instruction
& 0x10) != 0;
14276 set_pred_insn_type_last ();
14277 constraint (inst
.operands
[0].immisreg
,
14278 _("instruction requires register index"));
14280 Rn
= inst
.operands
[0].reg
;
14281 Rm
= inst
.operands
[0].imm
;
14283 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14284 constraint (Rn
== REG_SP
, BAD_SP
);
14285 reject_bad_reg (Rm
);
14287 constraint (!half
&& inst
.operands
[0].shifted
,
14288 _("instruction does not allow shifted index"));
14289 inst
.instruction
|= (Rn
<< 16) | Rm
;
14295 if (!inst
.operands
[0].present
)
14296 inst
.operands
[0].imm
= 0;
14298 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14300 constraint (inst
.size_req
== 2,
14301 _("immediate value out of range"));
14302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14303 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14304 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14308 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14309 inst
.instruction
|= inst
.operands
[0].imm
;
14312 set_pred_insn_type (NEUTRAL_IT_INSN
);
14319 do_t_ssat_usat (0);
14327 Rd
= inst
.operands
[0].reg
;
14328 Rn
= inst
.operands
[2].reg
;
14330 reject_bad_reg (Rd
);
14331 reject_bad_reg (Rn
);
14333 inst
.instruction
|= Rd
<< 8;
14334 inst
.instruction
|= inst
.operands
[1].imm
;
14335 inst
.instruction
|= Rn
<< 16;
14338 /* Checking the range of the branch offset (VAL) with NBITS bits
14339 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14341 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14343 gas_assert (nbits
> 0 && nbits
<= 32);
14346 int cmp
= (1 << (nbits
- 1));
14347 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14352 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14358 /* For branches in Armv8.1-M Mainline. */
14360 do_t_branch_future (void)
14362 unsigned long insn
= inst
.instruction
;
14364 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14365 if (inst
.operands
[0].hasreloc
== 0)
14367 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14368 as_bad (BAD_BRANCH_OFF
);
14370 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14374 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14375 inst
.relocs
[0].pc_rel
= 1;
14381 if (inst
.operands
[1].hasreloc
== 0)
14383 int val
= inst
.operands
[1].imm
;
14384 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14385 as_bad (BAD_BRANCH_OFF
);
14387 int immA
= (val
& 0x0001f000) >> 12;
14388 int immB
= (val
& 0x00000ffc) >> 2;
14389 int immC
= (val
& 0x00000002) >> 1;
14390 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14394 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14395 inst
.relocs
[1].pc_rel
= 1;
14400 if (inst
.operands
[1].hasreloc
== 0)
14402 int val
= inst
.operands
[1].imm
;
14403 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14404 as_bad (BAD_BRANCH_OFF
);
14406 int immA
= (val
& 0x0007f000) >> 12;
14407 int immB
= (val
& 0x00000ffc) >> 2;
14408 int immC
= (val
& 0x00000002) >> 1;
14409 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14413 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14414 inst
.relocs
[1].pc_rel
= 1;
14418 case T_MNEM_bfcsel
:
14420 if (inst
.operands
[1].hasreloc
== 0)
14422 int val
= inst
.operands
[1].imm
;
14423 int immA
= (val
& 0x00001000) >> 12;
14424 int immB
= (val
& 0x00000ffc) >> 2;
14425 int immC
= (val
& 0x00000002) >> 1;
14426 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14430 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14431 inst
.relocs
[1].pc_rel
= 1;
14435 if (inst
.operands
[2].hasreloc
== 0)
14437 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14438 int val2
= inst
.operands
[2].imm
;
14439 int val0
= inst
.operands
[0].imm
& 0x1f;
14440 int diff
= val2
- val0
;
14442 inst
.instruction
|= 1 << 17; /* T bit. */
14443 else if (diff
!= 2)
14444 as_bad (_("out of range label-relative fixup value"));
14448 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14449 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14450 inst
.relocs
[2].pc_rel
= 1;
14454 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14455 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14467 /* Helper function for do_t_loloop to handle relocations. */
14469 v8_1_loop_reloc (int is_le
)
14471 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14473 int value
= inst
.relocs
[0].exp
.X_add_number
;
14474 value
= (is_le
) ? -value
: value
;
14476 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14477 as_bad (BAD_BRANCH_OFF
);
14481 immh
= (value
& 0x00000ffc) >> 2;
14482 imml
= (value
& 0x00000002) >> 1;
14484 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14488 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14489 inst
.relocs
[0].pc_rel
= 1;
14493 /* For shifts with four operands in MVE. */
14495 do_mve_scalar_shift1 (void)
14497 unsigned int value
= inst
.operands
[2].imm
;
14499 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14500 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14502 /* Setting the bit for saturation. */
14503 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14505 /* Assuming Rm is already checked not to be 11x1. */
14506 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14507 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14508 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14511 /* For shifts in MVE. */
14513 do_mve_scalar_shift (void)
14515 if (!inst
.operands
[2].present
)
14517 inst
.operands
[2] = inst
.operands
[1];
14518 inst
.operands
[1].reg
= 0xf;
14521 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14522 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14524 if (inst
.operands
[2].isreg
)
14526 /* Assuming Rm is already checked not to be 11x1. */
14527 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14528 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14529 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14533 /* Assuming imm is already checked as [1,32]. */
14534 unsigned int value
= inst
.operands
[2].imm
;
14535 inst
.instruction
|= (value
& 0x1c) << 10;
14536 inst
.instruction
|= (value
& 0x03) << 6;
14537 /* Change last 4 bits from 0xd to 0xf. */
14538 inst
.instruction
|= 0x2;
14542 /* MVE instruction encoder helpers. */
14543 #define M_MNEM_vabav 0xee800f01
14544 #define M_MNEM_vmladav 0xeef00e00
14545 #define M_MNEM_vmladava 0xeef00e20
14546 #define M_MNEM_vmladavx 0xeef01e00
14547 #define M_MNEM_vmladavax 0xeef01e20
14548 #define M_MNEM_vmlsdav 0xeef00e01
14549 #define M_MNEM_vmlsdava 0xeef00e21
14550 #define M_MNEM_vmlsdavx 0xeef01e01
14551 #define M_MNEM_vmlsdavax 0xeef01e21
14552 #define M_MNEM_vmullt 0xee011e00
14553 #define M_MNEM_vmullb 0xee010e00
14554 #define M_MNEM_vctp 0xf000e801
14555 #define M_MNEM_vst20 0xfc801e00
14556 #define M_MNEM_vst21 0xfc801e20
14557 #define M_MNEM_vst40 0xfc801e01
14558 #define M_MNEM_vst41 0xfc801e21
14559 #define M_MNEM_vst42 0xfc801e41
14560 #define M_MNEM_vst43 0xfc801e61
14561 #define M_MNEM_vld20 0xfc901e00
14562 #define M_MNEM_vld21 0xfc901e20
14563 #define M_MNEM_vld40 0xfc901e01
14564 #define M_MNEM_vld41 0xfc901e21
14565 #define M_MNEM_vld42 0xfc901e41
14566 #define M_MNEM_vld43 0xfc901e61
14567 #define M_MNEM_vstrb 0xec000e00
14568 #define M_MNEM_vstrh 0xec000e10
14569 #define M_MNEM_vstrw 0xec000e40
14570 #define M_MNEM_vstrd 0xec000e50
14571 #define M_MNEM_vldrb 0xec100e00
14572 #define M_MNEM_vldrh 0xec100e10
14573 #define M_MNEM_vldrw 0xec100e40
14574 #define M_MNEM_vldrd 0xec100e50
14575 #define M_MNEM_vmovlt 0xeea01f40
14576 #define M_MNEM_vmovlb 0xeea00f40
14577 #define M_MNEM_vmovnt 0xfe311e81
14578 #define M_MNEM_vmovnb 0xfe310e81
14579 #define M_MNEM_vadc 0xee300f00
14580 #define M_MNEM_vadci 0xee301f00
14581 #define M_MNEM_vbrsr 0xfe011e60
14582 #define M_MNEM_vaddlv 0xee890f00
14583 #define M_MNEM_vaddlva 0xee890f20
14584 #define M_MNEM_vaddv 0xeef10f00
14585 #define M_MNEM_vaddva 0xeef10f20
14586 #define M_MNEM_vddup 0xee011f6e
14587 #define M_MNEM_vdwdup 0xee011f60
14588 #define M_MNEM_vidup 0xee010f6e
14589 #define M_MNEM_viwdup 0xee010f60
14590 #define M_MNEM_vmaxv 0xeee20f00
14591 #define M_MNEM_vmaxav 0xeee00f00
14592 #define M_MNEM_vminv 0xeee20f80
14593 #define M_MNEM_vminav 0xeee00f80
14594 #define M_MNEM_vmlaldav 0xee800e00
14595 #define M_MNEM_vmlaldava 0xee800e20
14596 #define M_MNEM_vmlaldavx 0xee801e00
14597 #define M_MNEM_vmlaldavax 0xee801e20
14598 #define M_MNEM_vmlsldav 0xee800e01
14599 #define M_MNEM_vmlsldava 0xee800e21
14600 #define M_MNEM_vmlsldavx 0xee801e01
14601 #define M_MNEM_vmlsldavax 0xee801e21
14602 #define M_MNEM_vrmlaldavhx 0xee801f00
14603 #define M_MNEM_vrmlaldavhax 0xee801f20
14604 #define M_MNEM_vrmlsldavh 0xfe800e01
14605 #define M_MNEM_vrmlsldavha 0xfe800e21
14606 #define M_MNEM_vrmlsldavhx 0xfe801e01
14607 #define M_MNEM_vrmlsldavhax 0xfe801e21
14608 #define M_MNEM_vqmovnt 0xee331e01
14609 #define M_MNEM_vqmovnb 0xee330e01
14610 #define M_MNEM_vqmovunt 0xee311e81
14611 #define M_MNEM_vqmovunb 0xee310e81
14612 #define M_MNEM_vshrnt 0xee801fc1
14613 #define M_MNEM_vshrnb 0xee800fc1
14614 #define M_MNEM_vrshrnt 0xfe801fc1
14615 #define M_MNEM_vqshrnt 0xee801f40
14616 #define M_MNEM_vqshrnb 0xee800f40
14617 #define M_MNEM_vqshrunt 0xee801fc0
14618 #define M_MNEM_vqshrunb 0xee800fc0
14619 #define M_MNEM_vrshrnb 0xfe800fc1
14620 #define M_MNEM_vqrshrnt 0xee801f41
14621 #define M_MNEM_vqrshrnb 0xee800f41
14622 #define M_MNEM_vqrshrunt 0xfe801fc0
14623 #define M_MNEM_vqrshrunb 0xfe800fc0
14625 /* Bfloat16 instruction encoder helpers. */
14626 #define B_MNEM_vfmat 0xfc300850
14627 #define B_MNEM_vfmab 0xfc300810
14629 /* Neon instruction encoder helpers. */
14631 /* Encodings for the different types for various Neon opcodes. */
14633 /* An "invalid" code for the following tables. */
14636 struct neon_tab_entry
14639 unsigned float_or_poly
;
14640 unsigned scalar_or_imm
;
14643 /* Map overloaded Neon opcodes to their respective encodings. */
14644 #define NEON_ENC_TAB \
14645 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14646 X(vabdl, 0x0800700, N_INV, N_INV), \
14647 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14648 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14649 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14650 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14651 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14652 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14653 X(vaddl, 0x0800000, N_INV, N_INV), \
14654 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14655 X(vsubl, 0x0800200, N_INV, N_INV), \
14656 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14657 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14658 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14659 /* Register variants of the following two instructions are encoded as
14660 vcge / vcgt with the operands reversed. */ \
14661 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14662 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14663 X(vfma, N_INV, 0x0000c10, N_INV), \
14664 X(vfms, N_INV, 0x0200c10, N_INV), \
14665 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14666 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14667 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14668 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14669 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14670 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14671 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14672 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14673 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14674 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14675 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14676 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14677 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14678 X(vshl, 0x0000400, N_INV, 0x0800510), \
14679 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14680 X(vand, 0x0000110, N_INV, 0x0800030), \
14681 X(vbic, 0x0100110, N_INV, 0x0800030), \
14682 X(veor, 0x1000110, N_INV, N_INV), \
14683 X(vorn, 0x0300110, N_INV, 0x0800010), \
14684 X(vorr, 0x0200110, N_INV, 0x0800010), \
14685 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14686 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14687 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14688 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14689 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14690 X(vst1, 0x0000000, 0x0800000, N_INV), \
14691 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14692 X(vst2, 0x0000100, 0x0800100, N_INV), \
14693 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14694 X(vst3, 0x0000200, 0x0800200, N_INV), \
14695 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14696 X(vst4, 0x0000300, 0x0800300, N_INV), \
14697 X(vmovn, 0x1b20200, N_INV, N_INV), \
14698 X(vtrn, 0x1b20080, N_INV, N_INV), \
14699 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14700 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14701 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14702 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14703 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14704 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14705 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14706 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14707 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14708 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14709 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14710 X(vseleq, 0xe000a00, N_INV, N_INV), \
14711 X(vselvs, 0xe100a00, N_INV, N_INV), \
14712 X(vselge, 0xe200a00, N_INV, N_INV), \
14713 X(vselgt, 0xe300a00, N_INV, N_INV), \
14714 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14715 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14716 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14717 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14718 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14719 X(aes, 0x3b00300, N_INV, N_INV), \
14720 X(sha3op, 0x2000c00, N_INV, N_INV), \
14721 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14722 X(sha2op, 0x3ba0380, N_INV, N_INV)
14726 #define X(OPC,I,F,S) N_MNEM_##OPC
14731 static const struct neon_tab_entry neon_enc_tab
[] =
14733 #define X(OPC,I,F,S) { (I), (F), (S) }
14738 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14739 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14740 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14741 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14742 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14743 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14744 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14745 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14746 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14747 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14748 #define NEON_ENC_SINGLE_(X) \
14749 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14750 #define NEON_ENC_DOUBLE_(X) \
14751 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14752 #define NEON_ENC_FPV8_(X) \
14753 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14755 #define NEON_ENCODE(type, inst) \
14758 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14759 inst.is_neon = 1; \
14763 #define check_neon_suffixes \
14766 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14768 as_bad (_("invalid neon suffix for non neon instruction")); \
14774 /* Define shapes for instruction operands. The following mnemonic characters
14775 are used in this table:
14777 F - VFP S<n> register
14778 D - Neon D<n> register
14779 Q - Neon Q<n> register
14783 L - D<n> register list
14785 This table is used to generate various data:
14786 - enumerations of the form NS_DDR to be used as arguments to
14788 - a table classifying shapes into single, double, quad, mixed.
14789 - a table used to drive neon_select_shape. */
14791 #define NEON_SHAPE_DEF \
14792 X(4, (R, R, Q, Q), QUAD), \
14793 X(4, (Q, R, R, I), QUAD), \
14794 X(4, (R, R, S, S), QUAD), \
14795 X(4, (S, S, R, R), QUAD), \
14796 X(3, (Q, R, I), QUAD), \
14797 X(3, (I, Q, Q), QUAD), \
14798 X(3, (I, Q, R), QUAD), \
14799 X(3, (R, Q, Q), QUAD), \
14800 X(3, (D, D, D), DOUBLE), \
14801 X(3, (Q, Q, Q), QUAD), \
14802 X(3, (D, D, I), DOUBLE), \
14803 X(3, (Q, Q, I), QUAD), \
14804 X(3, (D, D, S), DOUBLE), \
14805 X(3, (Q, Q, S), QUAD), \
14806 X(3, (Q, Q, R), QUAD), \
14807 X(3, (R, R, Q), QUAD), \
14808 X(2, (R, Q), QUAD), \
14809 X(2, (D, D), DOUBLE), \
14810 X(2, (Q, Q), QUAD), \
14811 X(2, (D, S), DOUBLE), \
14812 X(2, (Q, S), QUAD), \
14813 X(2, (D, R), DOUBLE), \
14814 X(2, (Q, R), QUAD), \
14815 X(2, (D, I), DOUBLE), \
14816 X(2, (Q, I), QUAD), \
14817 X(3, (P, F, I), SINGLE), \
14818 X(3, (P, D, I), DOUBLE), \
14819 X(3, (P, Q, I), QUAD), \
14820 X(4, (P, F, F, I), SINGLE), \
14821 X(4, (P, D, D, I), DOUBLE), \
14822 X(4, (P, Q, Q, I), QUAD), \
14823 X(5, (P, F, F, F, I), SINGLE), \
14824 X(5, (P, D, D, D, I), DOUBLE), \
14825 X(5, (P, Q, Q, Q, I), QUAD), \
14826 X(3, (D, L, D), DOUBLE), \
14827 X(2, (D, Q), MIXED), \
14828 X(2, (Q, D), MIXED), \
14829 X(3, (D, Q, I), MIXED), \
14830 X(3, (Q, D, I), MIXED), \
14831 X(3, (Q, D, D), MIXED), \
14832 X(3, (D, Q, Q), MIXED), \
14833 X(3, (Q, Q, D), MIXED), \
14834 X(3, (Q, D, S), MIXED), \
14835 X(3, (D, Q, S), MIXED), \
14836 X(4, (D, D, D, I), DOUBLE), \
14837 X(4, (Q, Q, Q, I), QUAD), \
14838 X(4, (D, D, S, I), DOUBLE), \
14839 X(4, (Q, Q, S, I), QUAD), \
14840 X(2, (F, F), SINGLE), \
14841 X(3, (F, F, F), SINGLE), \
14842 X(2, (F, I), SINGLE), \
14843 X(2, (F, D), MIXED), \
14844 X(2, (D, F), MIXED), \
14845 X(3, (F, F, I), MIXED), \
14846 X(4, (R, R, F, F), SINGLE), \
14847 X(4, (F, F, R, R), SINGLE), \
14848 X(3, (D, R, R), DOUBLE), \
14849 X(3, (R, R, D), DOUBLE), \
14850 X(2, (S, R), SINGLE), \
14851 X(2, (R, S), SINGLE), \
14852 X(2, (F, R), SINGLE), \
14853 X(2, (R, F), SINGLE), \
14854 /* Used for MVE tail predicated loop instructions. */\
14855 X(2, (R, R), QUAD), \
14856 /* Half float shape supported so far. */\
14857 X (2, (H, D), MIXED), \
14858 X (2, (D, H), MIXED), \
14859 X (2, (H, F), MIXED), \
14860 X (2, (F, H), MIXED), \
14861 X (2, (H, H), HALF), \
14862 X (2, (H, R), HALF), \
14863 X (2, (R, H), HALF), \
14864 X (2, (H, I), HALF), \
14865 X (3, (H, H, H), HALF), \
14866 X (3, (H, F, I), MIXED), \
14867 X (3, (F, H, I), MIXED), \
14868 X (3, (D, H, H), MIXED), \
14869 X (3, (D, H, S), MIXED)
14871 #define S2(A,B) NS_##A##B
14872 #define S3(A,B,C) NS_##A##B##C
14873 #define S4(A,B,C,D) NS_##A##B##C##D
14874 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14876 #define X(N, L, C) S##N L
14890 enum neon_shape_class
14899 #define X(N, L, C) SC_##C
14901 static enum neon_shape_class neon_shape_class
[] =
14921 /* Register widths of above. */
14922 static unsigned neon_shape_el_size
[] =
14935 struct neon_shape_info
14938 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14941 #define S2(A,B) { SE_##A, SE_##B }
14942 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14943 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14944 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14946 #define X(N, L, C) { N, S##N L }
14948 static struct neon_shape_info neon_shape_tab
[] =
14959 /* Bit masks used in type checking given instructions.
14960 'N_EQK' means the type must be the same as (or based on in some way) the key
14961 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14962 set, various other bits can be set as well in order to modify the meaning of
14963 the type constraint. */
14965 enum neon_type_mask
14989 N_BF16
= 0x0400000,
14990 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14991 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14992 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14993 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14994 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14995 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14996 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14997 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14998 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14999 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15000 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15002 N_MAX_NONSPECIAL
= N_P64
15005 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15007 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15008 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15009 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15010 #define N_S_32 (N_S8 | N_S16 | N_S32)
15011 #define N_F_16_32 (N_F16 | N_F32)
15012 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15013 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15014 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15015 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15016 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15017 #define N_F_MVE (N_F16 | N_F32)
15018 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15020 /* Pass this as the first type argument to neon_check_type to ignore types
15022 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15024 /* Select a "shape" for the current instruction (describing register types or
15025 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15026 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15027 function of operand parsing, so this function doesn't need to be called.
15028 Shapes should be listed in order of decreasing length. */
15030 static enum neon_shape
15031 neon_select_shape (enum neon_shape shape
, ...)
15034 enum neon_shape first_shape
= shape
;
15036 /* Fix missing optional operands. FIXME: we don't know at this point how
15037 many arguments we should have, so this makes the assumption that we have
15038 > 1. This is true of all current Neon opcodes, I think, but may not be
15039 true in the future. */
15040 if (!inst
.operands
[1].present
)
15041 inst
.operands
[1] = inst
.operands
[0];
15043 va_start (ap
, shape
);
15045 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15050 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15052 if (!inst
.operands
[j
].present
)
15058 switch (neon_shape_tab
[shape
].el
[j
])
15060 /* If a .f16, .16, .u16, .s16 type specifier is given over
15061 a VFP single precision register operand, it's essentially
15062 means only half of the register is used.
15064 If the type specifier is given after the mnemonics, the
15065 information is stored in inst.vectype. If the type specifier
15066 is given after register operand, the information is stored
15067 in inst.operands[].vectype.
15069 When there is only one type specifier, and all the register
15070 operands are the same type of hardware register, the type
15071 specifier applies to all register operands.
15073 If no type specifier is given, the shape is inferred from
15074 operand information.
15077 vadd.f16 s0, s1, s2: NS_HHH
15078 vabs.f16 s0, s1: NS_HH
15079 vmov.f16 s0, r1: NS_HR
15080 vmov.f16 r0, s1: NS_RH
15081 vcvt.f16 r0, s1: NS_RH
15082 vcvt.f16.s32 s2, s2, #29: NS_HFI
15083 vcvt.f16.s32 s2, s2: NS_HF
15086 if (!(inst
.operands
[j
].isreg
15087 && inst
.operands
[j
].isvec
15088 && inst
.operands
[j
].issingle
15089 && !inst
.operands
[j
].isquad
15090 && ((inst
.vectype
.elems
== 1
15091 && inst
.vectype
.el
[0].size
== 16)
15092 || (inst
.vectype
.elems
> 1
15093 && inst
.vectype
.el
[j
].size
== 16)
15094 || (inst
.vectype
.elems
== 0
15095 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15096 && inst
.operands
[j
].vectype
.size
== 16))))
15101 if (!(inst
.operands
[j
].isreg
15102 && inst
.operands
[j
].isvec
15103 && inst
.operands
[j
].issingle
15104 && !inst
.operands
[j
].isquad
15105 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15106 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15107 || (inst
.vectype
.elems
== 0
15108 && (inst
.operands
[j
].vectype
.size
== 32
15109 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15114 if (!(inst
.operands
[j
].isreg
15115 && inst
.operands
[j
].isvec
15116 && !inst
.operands
[j
].isquad
15117 && !inst
.operands
[j
].issingle
))
15122 if (!(inst
.operands
[j
].isreg
15123 && !inst
.operands
[j
].isvec
))
15128 if (!(inst
.operands
[j
].isreg
15129 && inst
.operands
[j
].isvec
15130 && inst
.operands
[j
].isquad
15131 && !inst
.operands
[j
].issingle
))
15136 if (!(!inst
.operands
[j
].isreg
15137 && !inst
.operands
[j
].isscalar
))
15142 if (!(!inst
.operands
[j
].isreg
15143 && inst
.operands
[j
].isscalar
))
15154 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15155 /* We've matched all the entries in the shape table, and we don't
15156 have any left over operands which have not been matched. */
15162 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15163 first_error (_("invalid instruction shape"));
15168 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15169 means the Q bit should be set). */
15172 neon_quad (enum neon_shape shape
)
15174 return neon_shape_class
[shape
] == SC_QUAD
;
15178 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15181 /* Allow modification to be made to types which are constrained to be
15182 based on the key element, based on bits set alongside N_EQK. */
15183 if ((typebits
& N_EQK
) != 0)
15185 if ((typebits
& N_HLF
) != 0)
15187 else if ((typebits
& N_DBL
) != 0)
15189 if ((typebits
& N_SGN
) != 0)
15190 *g_type
= NT_signed
;
15191 else if ((typebits
& N_UNS
) != 0)
15192 *g_type
= NT_unsigned
;
15193 else if ((typebits
& N_INT
) != 0)
15194 *g_type
= NT_integer
;
15195 else if ((typebits
& N_FLT
) != 0)
15196 *g_type
= NT_float
;
15197 else if ((typebits
& N_SIZ
) != 0)
15198 *g_type
= NT_untyped
;
15202 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15203 operand type, i.e. the single type specified in a Neon instruction when it
15204 is the only one given. */
15206 static struct neon_type_el
15207 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15209 struct neon_type_el dest
= *key
;
15211 gas_assert ((thisarg
& N_EQK
) != 0);
15213 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15218 /* Convert Neon type and size into compact bitmask representation. */
15220 static enum neon_type_mask
15221 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15228 case 8: return N_8
;
15229 case 16: return N_16
;
15230 case 32: return N_32
;
15231 case 64: return N_64
;
15239 case 8: return N_I8
;
15240 case 16: return N_I16
;
15241 case 32: return N_I32
;
15242 case 64: return N_I64
;
15250 case 16: return N_F16
;
15251 case 32: return N_F32
;
15252 case 64: return N_F64
;
15260 case 8: return N_P8
;
15261 case 16: return N_P16
;
15262 case 64: return N_P64
;
15270 case 8: return N_S8
;
15271 case 16: return N_S16
;
15272 case 32: return N_S32
;
15273 case 64: return N_S64
;
15281 case 8: return N_U8
;
15282 case 16: return N_U16
;
15283 case 32: return N_U32
;
15284 case 64: return N_U64
;
15290 if (size
== 16) return N_BF16
;
15299 /* Convert compact Neon bitmask type representation to a type and size. Only
15300 handles the case where a single bit is set in the mask. */
15303 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15304 enum neon_type_mask mask
)
15306 if ((mask
& N_EQK
) != 0)
15309 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15311 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15314 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15316 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15321 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15323 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15324 *type
= NT_unsigned
;
15325 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15326 *type
= NT_integer
;
15327 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15328 *type
= NT_untyped
;
15329 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15331 else if ((mask
& (N_F_ALL
)) != 0)
15333 else if ((mask
& (N_BF16
)) != 0)
15341 /* Modify a bitmask of allowed types. This is only needed for type
15345 modify_types_allowed (unsigned allowed
, unsigned mods
)
15348 enum neon_el_type type
;
15354 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15356 if (el_type_of_type_chk (&type
, &size
,
15357 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15359 neon_modify_type_size (mods
, &type
, &size
);
15360 destmask
|= type_chk_of_el_type (type
, size
);
15367 /* Check type and return type classification.
15368 The manual states (paraphrase): If one datatype is given, it indicates the
15370 - the second operand, if there is one
15371 - the operand, if there is no second operand
15372 - the result, if there are no operands.
15373 This isn't quite good enough though, so we use a concept of a "key" datatype
15374 which is set on a per-instruction basis, which is the one which matters when
15375 only one data type is written.
15376 Note: this function has side-effects (e.g. filling in missing operands). All
15377 Neon instructions should call it before performing bit encoding. */
15379 static struct neon_type_el
15380 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15383 unsigned i
, pass
, key_el
= 0;
15384 unsigned types
[NEON_MAX_TYPE_ELS
];
15385 enum neon_el_type k_type
= NT_invtype
;
15386 unsigned k_size
= -1u;
15387 struct neon_type_el badtype
= {NT_invtype
, -1};
15388 unsigned key_allowed
= 0;
15390 /* Optional registers in Neon instructions are always (not) in operand 1.
15391 Fill in the missing operand here, if it was omitted. */
15392 if (els
> 1 && !inst
.operands
[1].present
)
15393 inst
.operands
[1] = inst
.operands
[0];
15395 /* Suck up all the varargs. */
15397 for (i
= 0; i
< els
; i
++)
15399 unsigned thisarg
= va_arg (ap
, unsigned);
15400 if (thisarg
== N_IGNORE_TYPE
)
15405 types
[i
] = thisarg
;
15406 if ((thisarg
& N_KEY
) != 0)
15411 if (inst
.vectype
.elems
> 0)
15412 for (i
= 0; i
< els
; i
++)
15413 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15415 first_error (_("types specified in both the mnemonic and operands"));
15419 /* Duplicate inst.vectype elements here as necessary.
15420 FIXME: No idea if this is exactly the same as the ARM assembler,
15421 particularly when an insn takes one register and one non-register
15423 if (inst
.vectype
.elems
== 1 && els
> 1)
15426 inst
.vectype
.elems
= els
;
15427 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15428 for (j
= 0; j
< els
; j
++)
15430 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15433 else if (inst
.vectype
.elems
== 0 && els
> 0)
15436 /* No types were given after the mnemonic, so look for types specified
15437 after each operand. We allow some flexibility here; as long as the
15438 "key" operand has a type, we can infer the others. */
15439 for (j
= 0; j
< els
; j
++)
15440 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15441 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15443 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15445 for (j
= 0; j
< els
; j
++)
15446 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15447 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15452 first_error (_("operand types can't be inferred"));
15456 else if (inst
.vectype
.elems
!= els
)
15458 first_error (_("type specifier has the wrong number of parts"));
15462 for (pass
= 0; pass
< 2; pass
++)
15464 for (i
= 0; i
< els
; i
++)
15466 unsigned thisarg
= types
[i
];
15467 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15468 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15469 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15470 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15472 /* Decay more-specific signed & unsigned types to sign-insensitive
15473 integer types if sign-specific variants are unavailable. */
15474 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15475 && (types_allowed
& N_SU_ALL
) == 0)
15476 g_type
= NT_integer
;
15478 /* If only untyped args are allowed, decay any more specific types to
15479 them. Some instructions only care about signs for some element
15480 sizes, so handle that properly. */
15481 if (((types_allowed
& N_UNT
) == 0)
15482 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15483 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15484 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15485 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15486 g_type
= NT_untyped
;
15490 if ((thisarg
& N_KEY
) != 0)
15494 key_allowed
= thisarg
& ~N_KEY
;
15496 /* Check architecture constraint on FP16 extension. */
15498 && k_type
== NT_float
15499 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15501 inst
.error
= _(BAD_FP16
);
15508 if ((thisarg
& N_VFP
) != 0)
15510 enum neon_shape_el regshape
;
15511 unsigned regwidth
, match
;
15513 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15516 first_error (_("invalid instruction shape"));
15519 regshape
= neon_shape_tab
[ns
].el
[i
];
15520 regwidth
= neon_shape_el_size
[regshape
];
15522 /* In VFP mode, operands must match register widths. If we
15523 have a key operand, use its width, else use the width of
15524 the current operand. */
15530 /* FP16 will use a single precision register. */
15531 if (regwidth
== 32 && match
== 16)
15533 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15537 inst
.error
= _(BAD_FP16
);
15542 if (regwidth
!= match
)
15544 first_error (_("operand size must match register width"));
15549 if ((thisarg
& N_EQK
) == 0)
15551 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15553 if ((given_type
& types_allowed
) == 0)
15555 first_error (BAD_SIMD_TYPE
);
15561 enum neon_el_type mod_k_type
= k_type
;
15562 unsigned mod_k_size
= k_size
;
15563 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15564 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15566 first_error (_("inconsistent types in Neon instruction"));
15574 return inst
.vectype
.el
[key_el
];
15577 /* Neon-style VFP instruction forwarding. */
15579 /* Thumb VFP instructions have 0xE in the condition field. */
15582 do_vfp_cond_or_thumb (void)
15587 inst
.instruction
|= 0xe0000000;
15589 inst
.instruction
|= inst
.cond
<< 28;
15592 /* Look up and encode a simple mnemonic, for use as a helper function for the
15593 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15594 etc. It is assumed that operand parsing has already been done, and that the
15595 operands are in the form expected by the given opcode (this isn't necessarily
15596 the same as the form in which they were parsed, hence some massaging must
15597 take place before this function is called).
15598 Checks current arch version against that in the looked-up opcode. */
15601 do_vfp_nsyn_opcode (const char *opname
)
15603 const struct asm_opcode
*opcode
;
15605 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15610 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15611 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15618 inst
.instruction
= opcode
->tvalue
;
15619 opcode
->tencode ();
15623 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15624 opcode
->aencode ();
15629 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15631 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15633 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15636 do_vfp_nsyn_opcode ("fadds");
15638 do_vfp_nsyn_opcode ("fsubs");
15640 /* ARMv8.2 fp16 instruction. */
15642 do_scalar_fp16_v82_encode ();
15647 do_vfp_nsyn_opcode ("faddd");
15649 do_vfp_nsyn_opcode ("fsubd");
15653 /* Check operand types to see if this is a VFP instruction, and if so call
15657 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15659 enum neon_shape rs
;
15660 struct neon_type_el et
;
15665 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15666 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15670 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15671 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15672 N_F_ALL
| N_KEY
| N_VFP
);
15679 if (et
.type
!= NT_invtype
)
15690 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15692 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15694 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15697 do_vfp_nsyn_opcode ("fmacs");
15699 do_vfp_nsyn_opcode ("fnmacs");
15701 /* ARMv8.2 fp16 instruction. */
15703 do_scalar_fp16_v82_encode ();
15708 do_vfp_nsyn_opcode ("fmacd");
15710 do_vfp_nsyn_opcode ("fnmacd");
15715 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15717 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15719 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15722 do_vfp_nsyn_opcode ("ffmas");
15724 do_vfp_nsyn_opcode ("ffnmas");
15726 /* ARMv8.2 fp16 instruction. */
15728 do_scalar_fp16_v82_encode ();
15733 do_vfp_nsyn_opcode ("ffmad");
15735 do_vfp_nsyn_opcode ("ffnmad");
15740 do_vfp_nsyn_mul (enum neon_shape rs
)
15742 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15744 do_vfp_nsyn_opcode ("fmuls");
15746 /* ARMv8.2 fp16 instruction. */
15748 do_scalar_fp16_v82_encode ();
15751 do_vfp_nsyn_opcode ("fmuld");
15755 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15757 int is_neg
= (inst
.instruction
& 0x80) != 0;
15758 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15760 if (rs
== NS_FF
|| rs
== NS_HH
)
15763 do_vfp_nsyn_opcode ("fnegs");
15765 do_vfp_nsyn_opcode ("fabss");
15767 /* ARMv8.2 fp16 instruction. */
15769 do_scalar_fp16_v82_encode ();
15774 do_vfp_nsyn_opcode ("fnegd");
15776 do_vfp_nsyn_opcode ("fabsd");
15780 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15781 insns belong to Neon, and are handled elsewhere. */
15784 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15786 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15790 do_vfp_nsyn_opcode ("fldmdbs");
15792 do_vfp_nsyn_opcode ("fldmias");
15797 do_vfp_nsyn_opcode ("fstmdbs");
15799 do_vfp_nsyn_opcode ("fstmias");
15804 do_vfp_nsyn_sqrt (void)
15806 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15807 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15809 if (rs
== NS_FF
|| rs
== NS_HH
)
15811 do_vfp_nsyn_opcode ("fsqrts");
15813 /* ARMv8.2 fp16 instruction. */
15815 do_scalar_fp16_v82_encode ();
15818 do_vfp_nsyn_opcode ("fsqrtd");
15822 do_vfp_nsyn_div (void)
15824 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15825 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15826 N_F_ALL
| N_KEY
| N_VFP
);
15828 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15830 do_vfp_nsyn_opcode ("fdivs");
15832 /* ARMv8.2 fp16 instruction. */
15834 do_scalar_fp16_v82_encode ();
15837 do_vfp_nsyn_opcode ("fdivd");
15841 do_vfp_nsyn_nmul (void)
15843 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15844 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15845 N_F_ALL
| N_KEY
| N_VFP
);
15847 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15849 NEON_ENCODE (SINGLE
, inst
);
15850 do_vfp_sp_dyadic ();
15852 /* ARMv8.2 fp16 instruction. */
15854 do_scalar_fp16_v82_encode ();
15858 NEON_ENCODE (DOUBLE
, inst
);
15859 do_vfp_dp_rd_rn_rm ();
15861 do_vfp_cond_or_thumb ();
15865 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15869 neon_logbits (unsigned x
)
15871 return ffs (x
) - 4;
15874 #define LOW4(R) ((R) & 0xf)
15875 #define HI1(R) (((R) >> 4) & 1)
15876 #define LOW1(R) ((R) & 0x1)
15877 #define HI4(R) (((R) >> 1) & 0xf)
15880 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15885 first_error (BAD_EL_TYPE
);
15888 switch (inst
.operands
[0].imm
)
15891 first_error (_("invalid condition"));
15913 /* only accept eq and ne. */
15914 if (inst
.operands
[0].imm
> 1)
15916 first_error (_("invalid condition"));
15919 return inst
.operands
[0].imm
;
15921 if (inst
.operands
[0].imm
== 0x2)
15923 else if (inst
.operands
[0].imm
== 0x8)
15927 first_error (_("invalid condition"));
15931 switch (inst
.operands
[0].imm
)
15934 first_error (_("invalid condition"));
15950 /* Should be unreachable. */
15954 /* For VCTP (create vector tail predicate) in MVE. */
15959 unsigned size
= 0x0;
15961 if (inst
.cond
> COND_ALWAYS
)
15962 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15964 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15966 /* This is a typical MVE instruction which has no type but have size 8, 16,
15967 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15968 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15969 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15970 dt
= inst
.vectype
.el
[0].size
;
15972 /* Setting this does not indicate an actual NEON instruction, but only
15973 indicates that the mnemonic accepts neon-style type suffixes. */
15987 first_error (_("Type is not allowed for this instruction"));
15989 inst
.instruction
|= size
<< 20;
15990 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15996 /* We are dealing with a vector predicated block. */
15997 if (inst
.operands
[0].present
)
15999 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16000 struct neon_type_el et
16001 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16004 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16006 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16008 if (et
.type
== NT_invtype
)
16011 if (et
.type
== NT_float
)
16013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16015 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16016 inst
.instruction
|= (et
.size
== 16) << 28;
16017 inst
.instruction
|= 0x3 << 20;
16021 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16023 inst
.instruction
|= 1 << 28;
16024 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16027 if (inst
.operands
[2].isquad
)
16029 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16030 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16031 inst
.instruction
|= (fcond
& 0x2) >> 1;
16035 if (inst
.operands
[2].reg
== REG_SP
)
16036 as_tsktsk (MVE_BAD_SP
);
16037 inst
.instruction
|= 1 << 6;
16038 inst
.instruction
|= (fcond
& 0x2) << 4;
16039 inst
.instruction
|= inst
.operands
[2].reg
;
16041 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16042 inst
.instruction
|= (fcond
& 0x4) << 10;
16043 inst
.instruction
|= (fcond
& 0x1) << 7;
16046 set_pred_insn_type (VPT_INSN
);
16048 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16049 | ((inst
.instruction
& 0xe000) >> 13);
16050 now_pred
.warn_deprecated
= FALSE
;
16051 now_pred
.type
= VECTOR_PRED
;
16058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16059 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16060 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16061 if (!inst
.operands
[2].present
)
16062 first_error (_("MVE vector or ARM register expected"));
16063 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16065 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16066 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16067 && inst
.operands
[1].isquad
)
16069 inst
.instruction
= N_MNEM_vcmp
;
16073 if (inst
.cond
> COND_ALWAYS
)
16074 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16076 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16078 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16079 struct neon_type_el et
16080 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16083 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16084 && !inst
.operands
[2].iszr
, BAD_PC
);
16086 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16088 inst
.instruction
= 0xee010f00;
16089 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16090 inst
.instruction
|= (fcond
& 0x4) << 10;
16091 inst
.instruction
|= (fcond
& 0x1) << 7;
16092 if (et
.type
== NT_float
)
16094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16096 inst
.instruction
|= (et
.size
== 16) << 28;
16097 inst
.instruction
|= 0x3 << 20;
16101 inst
.instruction
|= 1 << 28;
16102 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16104 if (inst
.operands
[2].isquad
)
16106 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16107 inst
.instruction
|= (fcond
& 0x2) >> 1;
16108 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16112 if (inst
.operands
[2].reg
== REG_SP
)
16113 as_tsktsk (MVE_BAD_SP
);
16114 inst
.instruction
|= 1 << 6;
16115 inst
.instruction
|= (fcond
& 0x2) << 4;
16116 inst
.instruction
|= inst
.operands
[2].reg
;
16124 do_mve_vmaxa_vmina (void)
16126 if (inst
.cond
> COND_ALWAYS
)
16127 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16129 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16131 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16132 struct neon_type_el et
16133 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16135 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16136 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16137 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16138 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16139 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16144 do_mve_vfmas (void)
16146 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16147 struct neon_type_el et
16148 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16150 if (inst
.cond
> COND_ALWAYS
)
16151 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16153 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16155 if (inst
.operands
[2].reg
== REG_SP
)
16156 as_tsktsk (MVE_BAD_SP
);
16157 else if (inst
.operands
[2].reg
== REG_PC
)
16158 as_tsktsk (MVE_BAD_PC
);
16160 inst
.instruction
|= (et
.size
== 16) << 28;
16161 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16162 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16163 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16164 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16165 inst
.instruction
|= inst
.operands
[2].reg
;
16170 do_mve_viddup (void)
16172 if (inst
.cond
> COND_ALWAYS
)
16173 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16175 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16177 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16178 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16179 _("immediate must be either 1, 2, 4 or 8"));
16181 enum neon_shape rs
;
16182 struct neon_type_el et
;
16184 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16186 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16187 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16192 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16193 if (inst
.operands
[2].reg
== REG_SP
)
16194 as_tsktsk (MVE_BAD_SP
);
16195 else if (inst
.operands
[2].reg
== REG_PC
)
16196 first_error (BAD_PC
);
16198 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16199 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16200 Rm
= inst
.operands
[2].reg
>> 1;
16202 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16203 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16205 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16206 inst
.instruction
|= (imm
> 2) << 7;
16207 inst
.instruction
|= Rm
<< 1;
16208 inst
.instruction
|= (imm
== 2 || imm
== 8);
16213 do_mve_vmlas (void)
16215 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16216 struct neon_type_el et
16217 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16219 if (inst
.operands
[2].reg
== REG_PC
)
16220 as_tsktsk (MVE_BAD_PC
);
16221 else if (inst
.operands
[2].reg
== REG_SP
)
16222 as_tsktsk (MVE_BAD_SP
);
16224 if (inst
.cond
> COND_ALWAYS
)
16225 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16227 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16229 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16230 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16231 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16232 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16233 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16235 inst
.instruction
|= inst
.operands
[2].reg
;
16240 do_mve_vshll (void)
16242 struct neon_type_el et
16243 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16245 if (inst
.cond
> COND_ALWAYS
)
16246 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16248 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16250 int imm
= inst
.operands
[2].imm
;
16251 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16252 _("immediate value out of range"));
16254 if ((unsigned)imm
== et
.size
)
16256 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16257 inst
.instruction
|= 0x110001;
16261 inst
.instruction
|= (et
.size
+ imm
) << 16;
16262 inst
.instruction
|= 0x800140;
16265 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16266 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16268 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16269 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16274 do_mve_vshlc (void)
16276 if (inst
.cond
> COND_ALWAYS
)
16277 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16279 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16281 if (inst
.operands
[1].reg
== REG_PC
)
16282 as_tsktsk (MVE_BAD_PC
);
16283 else if (inst
.operands
[1].reg
== REG_SP
)
16284 as_tsktsk (MVE_BAD_SP
);
16286 int imm
= inst
.operands
[2].imm
;
16287 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16289 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16290 inst
.instruction
|= (imm
& 0x1f) << 16;
16291 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16292 inst
.instruction
|= inst
.operands
[1].reg
;
16297 do_mve_vshrn (void)
16300 switch (inst
.instruction
)
16302 case M_MNEM_vshrnt
:
16303 case M_MNEM_vshrnb
:
16304 case M_MNEM_vrshrnt
:
16305 case M_MNEM_vrshrnb
:
16306 types
= N_I16
| N_I32
;
16308 case M_MNEM_vqshrnt
:
16309 case M_MNEM_vqshrnb
:
16310 case M_MNEM_vqrshrnt
:
16311 case M_MNEM_vqrshrnb
:
16312 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16314 case M_MNEM_vqshrunt
:
16315 case M_MNEM_vqshrunb
:
16316 case M_MNEM_vqrshrunt
:
16317 case M_MNEM_vqrshrunb
:
16318 types
= N_S16
| N_S32
;
16324 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16326 if (inst
.cond
> COND_ALWAYS
)
16327 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16329 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16331 unsigned Qd
= inst
.operands
[0].reg
;
16332 unsigned Qm
= inst
.operands
[1].reg
;
16333 unsigned imm
= inst
.operands
[2].imm
;
16334 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16336 ? _("immediate operand expected in the range [1,8]")
16337 : _("immediate operand expected in the range [1,16]"));
16339 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16340 inst
.instruction
|= HI1 (Qd
) << 22;
16341 inst
.instruction
|= (et
.size
- imm
) << 16;
16342 inst
.instruction
|= LOW4 (Qd
) << 12;
16343 inst
.instruction
|= HI1 (Qm
) << 5;
16344 inst
.instruction
|= LOW4 (Qm
);
16349 do_mve_vqmovn (void)
16351 struct neon_type_el et
;
16352 if (inst
.instruction
== M_MNEM_vqmovnt
16353 || inst
.instruction
== M_MNEM_vqmovnb
)
16354 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16355 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16357 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16359 if (inst
.cond
> COND_ALWAYS
)
16360 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16362 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16364 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16365 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16366 inst
.instruction
|= (et
.size
== 32) << 18;
16367 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16369 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16374 do_mve_vpsel (void)
16376 neon_select_shape (NS_QQQ
, NS_NULL
);
16378 if (inst
.cond
> COND_ALWAYS
)
16379 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16381 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16386 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16387 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16388 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16393 do_mve_vpnot (void)
16395 if (inst
.cond
> COND_ALWAYS
)
16396 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16398 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16402 do_mve_vmaxnma_vminnma (void)
16404 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16405 struct neon_type_el et
16406 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16408 if (inst
.cond
> COND_ALWAYS
)
16409 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16411 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16413 inst
.instruction
|= (et
.size
== 16) << 28;
16414 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16415 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16416 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16417 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16422 do_mve_vcmul (void)
16424 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16425 struct neon_type_el et
16426 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16428 if (inst
.cond
> COND_ALWAYS
)
16429 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16431 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16433 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16434 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16435 _("immediate out of range"));
16437 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16438 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16439 as_tsktsk (BAD_MVE_SRCDEST
);
16441 inst
.instruction
|= (et
.size
== 32) << 28;
16442 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16443 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16444 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16445 inst
.instruction
|= (rot
> 90) << 12;
16446 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16447 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16448 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16449 inst
.instruction
|= (rot
== 90 || rot
== 270);
16453 /* To handle the Low Overhead Loop instructions
16454 in Armv8.1-M Mainline and MVE. */
16458 unsigned long insn
= inst
.instruction
;
16460 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16462 if (insn
== T_MNEM_lctp
)
16465 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16467 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16469 struct neon_type_el et
16470 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16471 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16478 constraint (!inst
.operands
[0].present
,
16480 /* fall through. */
16483 if (!inst
.operands
[0].present
)
16484 inst
.instruction
|= 1 << 21;
16486 v8_1_loop_reloc (TRUE
);
16491 v8_1_loop_reloc (FALSE
);
16492 /* fall through. */
16495 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16497 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16498 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16499 else if (inst
.operands
[1].reg
== REG_PC
)
16500 as_tsktsk (MVE_BAD_PC
);
16501 if (inst
.operands
[1].reg
== REG_SP
)
16502 as_tsktsk (MVE_BAD_SP
);
16504 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16514 do_vfp_nsyn_cmp (void)
16516 enum neon_shape rs
;
16517 if (!inst
.operands
[0].isreg
)
16524 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16525 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16529 if (inst
.operands
[1].isreg
)
16531 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16532 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16534 if (rs
== NS_FF
|| rs
== NS_HH
)
16536 NEON_ENCODE (SINGLE
, inst
);
16537 do_vfp_sp_monadic ();
16541 NEON_ENCODE (DOUBLE
, inst
);
16542 do_vfp_dp_rd_rm ();
16547 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16548 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16550 switch (inst
.instruction
& 0x0fffffff)
16553 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16556 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16562 if (rs
== NS_FI
|| rs
== NS_HI
)
16564 NEON_ENCODE (SINGLE
, inst
);
16565 do_vfp_sp_compare_z ();
16569 NEON_ENCODE (DOUBLE
, inst
);
16573 do_vfp_cond_or_thumb ();
16575 /* ARMv8.2 fp16 instruction. */
16576 if (rs
== NS_HI
|| rs
== NS_HH
)
16577 do_scalar_fp16_v82_encode ();
16581 nsyn_insert_sp (void)
16583 inst
.operands
[1] = inst
.operands
[0];
16584 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16585 inst
.operands
[0].reg
= REG_SP
;
16586 inst
.operands
[0].isreg
= 1;
16587 inst
.operands
[0].writeback
= 1;
16588 inst
.operands
[0].present
= 1;
16591 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16592 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16595 neon_dp_fixup (struct arm_it
* insn
)
16597 unsigned int i
= insn
->instruction
;
16602 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16613 insn
->instruction
= i
;
16617 mve_encode_qqr (int size
, int U
, int fp
)
16619 if (inst
.operands
[2].reg
== REG_SP
)
16620 as_tsktsk (MVE_BAD_SP
);
16621 else if (inst
.operands
[2].reg
== REG_PC
)
16622 as_tsktsk (MVE_BAD_PC
);
16627 if (((unsigned)inst
.instruction
) == 0xd00)
16628 inst
.instruction
= 0xee300f40;
16630 else if (((unsigned)inst
.instruction
) == 0x200d00)
16631 inst
.instruction
= 0xee301f40;
16633 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16634 inst
.instruction
= 0xee310e60;
16636 /* Setting size which is 1 for F16 and 0 for F32. */
16637 inst
.instruction
|= (size
== 16) << 28;
16642 if (((unsigned)inst
.instruction
) == 0x800)
16643 inst
.instruction
= 0xee010f40;
16645 else if (((unsigned)inst
.instruction
) == 0x1000800)
16646 inst
.instruction
= 0xee011f40;
16648 else if (((unsigned)inst
.instruction
) == 0)
16649 inst
.instruction
= 0xee000f40;
16651 else if (((unsigned)inst
.instruction
) == 0x200)
16652 inst
.instruction
= 0xee001f40;
16654 else if (((unsigned)inst
.instruction
) == 0x900)
16655 inst
.instruction
= 0xee010e40;
16657 else if (((unsigned)inst
.instruction
) == 0x910)
16658 inst
.instruction
= 0xee011e60;
16660 else if (((unsigned)inst
.instruction
) == 0x10)
16661 inst
.instruction
= 0xee000f60;
16663 else if (((unsigned)inst
.instruction
) == 0x210)
16664 inst
.instruction
= 0xee001f60;
16666 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16667 inst
.instruction
= 0xee000e40;
16669 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16670 inst
.instruction
= 0xee010e60;
16672 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16673 inst
.instruction
= 0xfe010e60;
16676 inst
.instruction
|= U
<< 28;
16678 /* Setting bits for size. */
16679 inst
.instruction
|= neon_logbits (size
) << 20;
16681 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16682 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16683 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16684 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16685 inst
.instruction
|= inst
.operands
[2].reg
;
16690 mve_encode_rqq (unsigned bit28
, unsigned size
)
16692 inst
.instruction
|= bit28
<< 28;
16693 inst
.instruction
|= neon_logbits (size
) << 20;
16694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16696 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16697 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16698 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16703 mve_encode_qqq (int ubit
, int size
)
16706 inst
.instruction
|= (ubit
!= 0) << 28;
16707 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16708 inst
.instruction
|= neon_logbits (size
) << 20;
16709 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16711 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16712 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16713 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16719 mve_encode_rq (unsigned bit28
, unsigned size
)
16721 inst
.instruction
|= bit28
<< 28;
16722 inst
.instruction
|= neon_logbits (size
) << 18;
16723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16724 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16729 mve_encode_rrqq (unsigned U
, unsigned size
)
16731 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16733 inst
.instruction
|= U
<< 28;
16734 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16735 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16736 inst
.instruction
|= (size
== 32) << 16;
16737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16738 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16739 inst
.instruction
|= inst
.operands
[3].reg
;
16743 /* Helper function for neon_three_same handling the operands. */
16745 neon_three_args (int isquad
)
16747 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16748 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16749 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16750 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16751 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16752 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16753 inst
.instruction
|= (isquad
!= 0) << 6;
16757 /* Encode insns with bit pattern:
16759 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16760 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16762 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16763 different meaning for some instruction. */
16766 neon_three_same (int isquad
, int ubit
, int size
)
16768 neon_three_args (isquad
);
16769 inst
.instruction
|= (ubit
!= 0) << 24;
16771 inst
.instruction
|= neon_logbits (size
) << 20;
16773 neon_dp_fixup (&inst
);
16776 /* Encode instructions of the form:
16778 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16779 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16781 Don't write size if SIZE == -1. */
16784 neon_two_same (int qbit
, int ubit
, int size
)
16786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16790 inst
.instruction
|= (qbit
!= 0) << 6;
16791 inst
.instruction
|= (ubit
!= 0) << 24;
16794 inst
.instruction
|= neon_logbits (size
) << 18;
16796 neon_dp_fixup (&inst
);
16799 enum vfp_or_neon_is_neon_bits
16802 NEON_CHECK_ARCH
= 2,
16803 NEON_CHECK_ARCH8
= 4
16806 /* Call this function if an instruction which may have belonged to the VFP or
16807 Neon instruction sets, but turned out to be a Neon instruction (due to the
16808 operand types involved, etc.). We have to check and/or fix-up a couple of
16811 - Make sure the user hasn't attempted to make a Neon instruction
16813 - Alter the value in the condition code field if necessary.
16814 - Make sure that the arch supports Neon instructions.
16816 Which of these operations take place depends on bits from enum
16817 vfp_or_neon_is_neon_bits.
16819 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16820 current instruction's condition is COND_ALWAYS, the condition field is
16821 changed to inst.uncond_value. This is necessary because instructions shared
16822 between VFP and Neon may be conditional for the VFP variants only, and the
16823 unconditional Neon version must have, e.g., 0xF in the condition field. */
16826 vfp_or_neon_is_neon (unsigned check
)
16828 /* Conditions are always legal in Thumb mode (IT blocks). */
16829 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16831 if (inst
.cond
!= COND_ALWAYS
)
16833 first_error (_(BAD_COND
));
16836 if (inst
.uncond_value
!= -1u)
16837 inst
.instruction
|= inst
.uncond_value
<< 28;
16841 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16842 || ((check
& NEON_CHECK_ARCH8
)
16843 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16845 first_error (_(BAD_FPU
));
16853 /* Return TRUE if the SIMD instruction is available for the current
16854 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16855 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16856 vfp_or_neon_is_neon for the NEON specific checks. */
16859 check_simd_pred_availability (int fp
, unsigned check
)
16861 if (inst
.cond
> COND_ALWAYS
)
16863 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16865 inst
.error
= BAD_FPU
;
16868 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16870 else if (inst
.cond
< COND_ALWAYS
)
16872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16873 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16874 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16879 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16880 && vfp_or_neon_is_neon (check
) == FAIL
)
16883 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16884 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16889 /* Neon instruction encoders, in approximate order of appearance. */
16892 do_neon_dyadic_i_su (void)
16894 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16897 enum neon_shape rs
;
16898 struct neon_type_el et
;
16899 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16900 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16902 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16904 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16908 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16910 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16914 do_neon_dyadic_i64_su (void)
16916 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16918 enum neon_shape rs
;
16919 struct neon_type_el et
;
16920 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16922 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16923 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16927 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16928 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16931 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16933 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16937 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16940 unsigned size
= et
.size
>> 3;
16941 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16942 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16943 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16944 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16945 inst
.instruction
|= (isquad
!= 0) << 6;
16946 inst
.instruction
|= immbits
<< 16;
16947 inst
.instruction
|= (size
>> 3) << 7;
16948 inst
.instruction
|= (size
& 0x7) << 19;
16950 inst
.instruction
|= (uval
!= 0) << 24;
16952 neon_dp_fixup (&inst
);
16958 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16961 if (!inst
.operands
[2].isreg
)
16963 enum neon_shape rs
;
16964 struct neon_type_el et
;
16965 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16967 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16968 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16972 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16973 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16975 int imm
= inst
.operands
[2].imm
;
16977 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16978 _("immediate out of range for shift"));
16979 NEON_ENCODE (IMMED
, inst
);
16980 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16984 enum neon_shape rs
;
16985 struct neon_type_el et
;
16986 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16988 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16989 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16993 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16994 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17000 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17001 _("invalid instruction shape"));
17002 if (inst
.operands
[2].reg
== REG_SP
)
17003 as_tsktsk (MVE_BAD_SP
);
17004 else if (inst
.operands
[2].reg
== REG_PC
)
17005 as_tsktsk (MVE_BAD_PC
);
17007 inst
.instruction
= 0xee311e60;
17008 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17009 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17010 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17011 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17012 inst
.instruction
|= inst
.operands
[2].reg
;
17019 /* VSHL/VQSHL 3-register variants have syntax such as:
17021 whereas other 3-register operations encoded by neon_three_same have
17024 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17025 operands[2].reg here. */
17026 tmp
= inst
.operands
[2].reg
;
17027 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17028 inst
.operands
[1].reg
= tmp
;
17029 NEON_ENCODE (INTEGER
, inst
);
17030 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17036 do_neon_qshl (void)
17038 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17041 if (!inst
.operands
[2].isreg
)
17043 enum neon_shape rs
;
17044 struct neon_type_el et
;
17045 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17047 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17048 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17052 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17053 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17055 int imm
= inst
.operands
[2].imm
;
17057 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17058 _("immediate out of range for shift"));
17059 NEON_ENCODE (IMMED
, inst
);
17060 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17064 enum neon_shape rs
;
17065 struct neon_type_el et
;
17067 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17069 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17070 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17074 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17075 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17080 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17081 _("invalid instruction shape"));
17082 if (inst
.operands
[2].reg
== REG_SP
)
17083 as_tsktsk (MVE_BAD_SP
);
17084 else if (inst
.operands
[2].reg
== REG_PC
)
17085 as_tsktsk (MVE_BAD_PC
);
17087 inst
.instruction
= 0xee311ee0;
17088 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17089 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17090 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17091 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17092 inst
.instruction
|= inst
.operands
[2].reg
;
17099 /* See note in do_neon_shl. */
17100 tmp
= inst
.operands
[2].reg
;
17101 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17102 inst
.operands
[1].reg
= tmp
;
17103 NEON_ENCODE (INTEGER
, inst
);
17104 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17110 do_neon_rshl (void)
17112 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17115 enum neon_shape rs
;
17116 struct neon_type_el et
;
17117 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17119 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17120 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17124 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17125 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17132 if (inst
.operands
[2].reg
== REG_PC
)
17133 as_tsktsk (MVE_BAD_PC
);
17134 else if (inst
.operands
[2].reg
== REG_SP
)
17135 as_tsktsk (MVE_BAD_SP
);
17137 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17138 _("invalid instruction shape"));
17140 if (inst
.instruction
== 0x0000510)
17141 /* We are dealing with vqrshl. */
17142 inst
.instruction
= 0xee331ee0;
17144 /* We are dealing with vrshl. */
17145 inst
.instruction
= 0xee331e60;
17147 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17148 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17149 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17151 inst
.instruction
|= inst
.operands
[2].reg
;
17156 tmp
= inst
.operands
[2].reg
;
17157 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17158 inst
.operands
[1].reg
= tmp
;
17159 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17164 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17166 /* Handle .I8 pseudo-instructions. */
17169 /* Unfortunately, this will make everything apart from zero out-of-range.
17170 FIXME is this the intended semantics? There doesn't seem much point in
17171 accepting .I8 if so. */
17172 immediate
|= immediate
<< 8;
17178 if (immediate
== (immediate
& 0x000000ff))
17180 *immbits
= immediate
;
17183 else if (immediate
== (immediate
& 0x0000ff00))
17185 *immbits
= immediate
>> 8;
17188 else if (immediate
== (immediate
& 0x00ff0000))
17190 *immbits
= immediate
>> 16;
17193 else if (immediate
== (immediate
& 0xff000000))
17195 *immbits
= immediate
>> 24;
17198 if ((immediate
& 0xffff) != (immediate
>> 16))
17199 goto bad_immediate
;
17200 immediate
&= 0xffff;
17203 if (immediate
== (immediate
& 0x000000ff))
17205 *immbits
= immediate
;
17208 else if (immediate
== (immediate
& 0x0000ff00))
17210 *immbits
= immediate
>> 8;
17215 first_error (_("immediate value out of range"));
17220 do_neon_logic (void)
17222 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17224 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17226 && !check_simd_pred_availability (FALSE
,
17227 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17229 else if (rs
!= NS_QQQ
17230 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17231 first_error (BAD_FPU
);
17233 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17234 /* U bit and size field were set as part of the bitmask. */
17235 NEON_ENCODE (INTEGER
, inst
);
17236 neon_three_same (neon_quad (rs
), 0, -1);
17240 const int three_ops_form
= (inst
.operands
[2].present
17241 && !inst
.operands
[2].isreg
);
17242 const int immoperand
= (three_ops_form
? 2 : 1);
17243 enum neon_shape rs
= (three_ops_form
17244 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17245 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17246 /* Because neon_select_shape makes the second operand a copy of the first
17247 if the second operand is not present. */
17249 && !check_simd_pred_availability (FALSE
,
17250 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17252 else if (rs
!= NS_QQI
17253 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17254 first_error (BAD_FPU
);
17256 struct neon_type_el et
;
17257 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17258 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17260 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17263 if (et
.type
== NT_invtype
)
17265 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17270 if (three_ops_form
)
17271 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17272 _("first and second operands shall be the same register"));
17274 NEON_ENCODE (IMMED
, inst
);
17276 immbits
= inst
.operands
[immoperand
].imm
;
17279 /* .i64 is a pseudo-op, so the immediate must be a repeating
17281 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17282 inst
.operands
[immoperand
].reg
: 0))
17284 /* Set immbits to an invalid constant. */
17285 immbits
= 0xdeadbeef;
17292 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17296 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17300 /* Pseudo-instruction for VBIC. */
17301 neon_invert_size (&immbits
, 0, et
.size
);
17302 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17306 /* Pseudo-instruction for VORR. */
17307 neon_invert_size (&immbits
, 0, et
.size
);
17308 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17318 inst
.instruction
|= neon_quad (rs
) << 6;
17319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17321 inst
.instruction
|= cmode
<< 8;
17322 neon_write_immbits (immbits
);
17324 neon_dp_fixup (&inst
);
17329 do_neon_bitfield (void)
17331 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17332 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17333 neon_three_same (neon_quad (rs
), 0, -1);
17337 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17340 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17341 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17343 if (et
.type
== NT_float
)
17345 NEON_ENCODE (FLOAT
, inst
);
17347 mve_encode_qqr (et
.size
, 0, 1);
17349 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17353 NEON_ENCODE (INTEGER
, inst
);
17355 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17357 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17363 do_neon_dyadic_if_su_d (void)
17365 /* This version only allow D registers, but that constraint is enforced during
17366 operand parsing so we don't need to do anything extra here. */
17367 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17371 do_neon_dyadic_if_i_d (void)
17373 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17374 affected if we specify unsigned args. */
17375 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17379 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17381 constraint (size
< 32, BAD_ADDR_MODE
);
17382 constraint (size
!= elsize
, BAD_EL_TYPE
);
17383 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17384 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17385 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17386 _("destination register and offset register may not be the"
17389 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17396 constraint ((imm
% (size
/ 8) != 0)
17397 || imm
> (0x7f << neon_logbits (size
)),
17398 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17399 " range of +/-[0,508]")
17400 : _("immediate must be a multiple of 8 in the"
17401 " range of +/-[0,1016]"));
17402 inst
.instruction
|= 0x11 << 24;
17403 inst
.instruction
|= add
<< 23;
17404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17405 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17406 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17407 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17408 inst
.instruction
|= 1 << 12;
17409 inst
.instruction
|= (size
== 64) << 8;
17410 inst
.instruction
&= 0xffffff00;
17411 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17412 inst
.instruction
|= imm
>> neon_logbits (size
);
17416 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17418 unsigned os
= inst
.operands
[1].imm
>> 5;
17419 unsigned type
= inst
.vectype
.el
[0].type
;
17420 constraint (os
!= 0 && size
== 8,
17421 _("can not shift offsets when accessing less than half-word"));
17422 constraint (os
&& os
!= neon_logbits (size
),
17423 _("shift immediate must be 1, 2 or 3 for half-word, word"
17424 " or double-word accesses respectively"));
17425 if (inst
.operands
[1].reg
== REG_PC
)
17426 as_tsktsk (MVE_BAD_PC
);
17431 constraint (elsize
>= 64, BAD_EL_TYPE
);
17434 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17438 constraint (elsize
!= size
, BAD_EL_TYPE
);
17443 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17447 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17448 _("destination register and offset register may not be"
17450 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17451 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17453 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17457 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17460 inst
.instruction
|= 1 << 23;
17461 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17462 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17463 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17464 inst
.instruction
|= neon_logbits (elsize
) << 7;
17465 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17466 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17467 inst
.instruction
|= !!os
;
17471 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17473 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17475 constraint (size
>= 64, BAD_ADDR_MODE
);
17479 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17482 constraint (elsize
!= size
, BAD_EL_TYPE
);
17489 constraint (elsize
!= size
&& type
!= NT_unsigned
17490 && type
!= NT_signed
, BAD_EL_TYPE
);
17494 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17497 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17505 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17510 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17513 constraint (1, _("immediate must be a multiple of 2 in the"
17514 " range of +/-[0,254]"));
17517 constraint (1, _("immediate must be a multiple of 4 in the"
17518 " range of +/-[0,508]"));
17523 if (size
!= elsize
)
17525 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17526 constraint (inst
.operands
[0].reg
> 14,
17527 _("MVE vector register in the range [Q0..Q7] expected"));
17528 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17529 inst
.instruction
|= (size
== 16) << 19;
17530 inst
.instruction
|= neon_logbits (elsize
) << 7;
17534 if (inst
.operands
[1].reg
== REG_PC
)
17535 as_tsktsk (MVE_BAD_PC
);
17536 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17537 as_tsktsk (MVE_BAD_SP
);
17538 inst
.instruction
|= 1 << 12;
17539 inst
.instruction
|= neon_logbits (size
) << 7;
17541 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17542 inst
.instruction
|= add
<< 23;
17543 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17544 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17545 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17546 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17547 inst
.instruction
&= 0xffffff80;
17548 inst
.instruction
|= imm
>> neon_logbits (size
);
17553 do_mve_vstr_vldr (void)
17558 if (inst
.cond
> COND_ALWAYS
)
17559 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17561 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17563 switch (inst
.instruction
)
17570 /* fall through. */
17576 /* fall through. */
17582 /* fall through. */
17588 /* fall through. */
17593 unsigned elsize
= inst
.vectype
.el
[0].size
;
17595 if (inst
.operands
[1].isquad
)
17597 /* We are dealing with [Q, imm]{!} cases. */
17598 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17602 if (inst
.operands
[1].immisreg
== 2)
17604 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17605 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17607 else if (!inst
.operands
[1].immisreg
)
17609 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17610 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17613 constraint (1, BAD_ADDR_MODE
);
17620 do_mve_vst_vld (void)
17622 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17625 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17626 || inst
.relocs
[0].exp
.X_add_number
!= 0
17627 || inst
.operands
[1].immisreg
!= 0,
17629 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17630 if (inst
.operands
[1].reg
== REG_PC
)
17631 as_tsktsk (MVE_BAD_PC
);
17632 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17633 as_tsktsk (MVE_BAD_SP
);
17636 /* These instructions are one of the "exceptions" mentioned in
17637 handle_pred_state. They are MVE instructions that are not VPT compatible
17638 and do not accept a VPT code, thus appending such a code is a syntax
17640 if (inst
.cond
> COND_ALWAYS
)
17641 first_error (BAD_SYNTAX
);
17642 /* If we append a scalar condition code we can set this to
17643 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17644 else if (inst
.cond
< COND_ALWAYS
)
17645 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17647 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17649 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17650 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17651 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17652 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17653 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17658 do_mve_vaddlv (void)
17660 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17661 struct neon_type_el et
17662 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17664 if (et
.type
== NT_invtype
)
17665 first_error (BAD_EL_TYPE
);
17667 if (inst
.cond
> COND_ALWAYS
)
17668 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17670 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17672 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17674 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17675 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17677 inst
.instruction
|= inst
.operands
[2].reg
;
17682 do_neon_dyadic_if_su (void)
17684 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17685 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17688 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17689 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17690 && et
.type
== NT_float
17691 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17693 if (!check_simd_pred_availability (et
.type
== NT_float
,
17694 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17697 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17701 do_neon_addsub_if_i (void)
17703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17704 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17707 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17708 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17709 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17711 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17712 /* If we are parsing Q registers and the element types match MVE, which NEON
17713 also supports, then we must check whether this is an instruction that can
17714 be used by both MVE/NEON. This distinction can be made based on whether
17715 they are predicated or not. */
17716 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17718 if (!check_simd_pred_availability (et
.type
== NT_float
,
17719 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17724 /* If they are either in a D register or are using an unsupported. */
17726 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17730 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17731 affected if we specify unsigned args. */
17732 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17735 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17737 V<op> A,B (A is operand 0, B is operand 2)
17742 so handle that case specially. */
17745 neon_exchange_operands (void)
17747 if (inst
.operands
[1].present
)
17749 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17751 /* Swap operands[1] and operands[2]. */
17752 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17753 inst
.operands
[1] = inst
.operands
[2];
17754 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17759 inst
.operands
[1] = inst
.operands
[2];
17760 inst
.operands
[2] = inst
.operands
[0];
17765 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17767 if (inst
.operands
[2].isreg
)
17770 neon_exchange_operands ();
17771 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17775 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17776 struct neon_type_el et
= neon_check_type (2, rs
,
17777 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17779 NEON_ENCODE (IMMED
, inst
);
17780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17782 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17784 inst
.instruction
|= neon_quad (rs
) << 6;
17785 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17786 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17788 neon_dp_fixup (&inst
);
17795 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17799 do_neon_cmp_inv (void)
17801 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17807 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17810 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17811 scalars, which are encoded in 5 bits, M : Rm.
17812 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17813 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17816 Dot Product instructions are similar to multiply instructions except elsize
17817 should always be 32.
17819 This function translates SCALAR, which is GAS's internal encoding of indexed
17820 scalar register, to raw encoding. There is also register and index range
17821 check based on ELSIZE. */
17824 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17826 unsigned regno
= NEON_SCALAR_REG (scalar
);
17827 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17832 if (regno
> 7 || elno
> 3)
17834 return regno
| (elno
<< 3);
17837 if (regno
> 15 || elno
> 1)
17839 return regno
| (elno
<< 4);
17843 first_error (_("scalar out of range for multiply instruction"));
17849 /* Encode multiply / multiply-accumulate scalar instructions. */
17852 neon_mul_mac (struct neon_type_el et
, int ubit
)
17856 /* Give a more helpful error message if we have an invalid type. */
17857 if (et
.type
== NT_invtype
)
17860 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17861 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17862 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17863 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17864 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17865 inst
.instruction
|= LOW4 (scalar
);
17866 inst
.instruction
|= HI1 (scalar
) << 5;
17867 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17868 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17869 inst
.instruction
|= (ubit
!= 0) << 24;
17871 neon_dp_fixup (&inst
);
17875 do_neon_mac_maybe_scalar (void)
17877 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17880 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17883 if (inst
.operands
[2].isscalar
)
17885 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17886 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17887 struct neon_type_el et
= neon_check_type (3, rs
,
17888 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17889 NEON_ENCODE (SCALAR
, inst
);
17890 neon_mul_mac (et
, neon_quad (rs
));
17892 else if (!inst
.operands
[2].isvec
)
17894 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17896 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17897 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17899 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17903 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17904 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17905 affected if we specify unsigned args. */
17906 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17911 do_bfloat_vfma (void)
17913 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17914 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17915 enum neon_shape rs
;
17918 if (inst
.instruction
!= B_MNEM_vfmab
)
17921 inst
.instruction
= B_MNEM_vfmat
;
17924 if (inst
.operands
[2].isscalar
)
17926 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17927 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17929 inst
.instruction
|= (1 << 25);
17930 int index
= inst
.operands
[2].reg
& 0xf;
17931 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17932 inst
.operands
[2].reg
>>= 4;
17933 constraint (!(inst
.operands
[2].reg
< 8),
17934 _("indexed register must be less than 8"));
17935 neon_three_args (t_bit
);
17936 inst
.instruction
|= ((index
& 1) << 3);
17937 inst
.instruction
|= ((index
& 2) << 4);
17941 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17942 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17943 neon_three_args (t_bit
);
17949 do_neon_fmac (void)
17951 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17952 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17955 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17958 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17960 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17961 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17967 if (inst
.operands
[2].reg
== REG_SP
)
17968 as_tsktsk (MVE_BAD_SP
);
17969 else if (inst
.operands
[2].reg
== REG_PC
)
17970 as_tsktsk (MVE_BAD_PC
);
17972 inst
.instruction
= 0xee310e40;
17973 inst
.instruction
|= (et
.size
== 16) << 28;
17974 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17975 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17976 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17977 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17978 inst
.instruction
|= inst
.operands
[2].reg
;
17985 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17988 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17994 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17995 inst
.cond
== COND_ALWAYS
)
17997 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17998 inst
.instruction
= N_MNEM_vfma
;
17999 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18001 return do_neon_fmac();
18012 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18013 struct neon_type_el et
= neon_check_type (3, rs
,
18014 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18015 neon_three_same (neon_quad (rs
), 0, et
.size
);
18018 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18019 same types as the MAC equivalents. The polynomial type for this instruction
18020 is encoded the same as the integer type. */
18025 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18028 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18031 if (inst
.operands
[2].isscalar
)
18033 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18034 do_neon_mac_maybe_scalar ();
18038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18040 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18041 struct neon_type_el et
18042 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18043 if (et
.type
== NT_float
)
18044 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18047 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18051 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18052 neon_dyadic_misc (NT_poly
,
18053 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18059 do_neon_qdmulh (void)
18061 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18064 if (inst
.operands
[2].isscalar
)
18066 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18067 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18068 struct neon_type_el et
= neon_check_type (3, rs
,
18069 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18070 NEON_ENCODE (SCALAR
, inst
);
18071 neon_mul_mac (et
, neon_quad (rs
));
18075 enum neon_shape rs
;
18076 struct neon_type_el et
;
18077 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18079 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18080 et
= neon_check_type (3, rs
,
18081 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18085 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18086 et
= neon_check_type (3, rs
,
18087 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18090 NEON_ENCODE (INTEGER
, inst
);
18092 mve_encode_qqr (et
.size
, 0, 0);
18094 /* The U bit (rounding) comes from bit mask. */
18095 neon_three_same (neon_quad (rs
), 0, et
.size
);
18100 do_mve_vaddv (void)
18102 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18103 struct neon_type_el et
18104 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18106 if (et
.type
== NT_invtype
)
18107 first_error (BAD_EL_TYPE
);
18109 if (inst
.cond
> COND_ALWAYS
)
18110 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18112 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18114 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18116 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18120 do_mve_vhcadd (void)
18122 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18123 struct neon_type_el et
18124 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18126 if (inst
.cond
> COND_ALWAYS
)
18127 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18129 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18131 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18132 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18134 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18135 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18136 "operand makes instruction UNPREDICTABLE"));
18138 mve_encode_qqq (0, et
.size
);
18139 inst
.instruction
|= (rot
== 270) << 12;
18144 do_mve_vqdmull (void)
18146 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18147 struct neon_type_el et
18148 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18151 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18152 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18153 as_tsktsk (BAD_MVE_SRCDEST
);
18155 if (inst
.cond
> COND_ALWAYS
)
18156 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18158 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18162 mve_encode_qqq (et
.size
== 32, 64);
18163 inst
.instruction
|= 1;
18167 mve_encode_qqr (64, et
.size
== 32, 0);
18168 inst
.instruction
|= 0x3 << 5;
18175 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18176 struct neon_type_el et
18177 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18179 if (et
.type
== NT_invtype
)
18180 first_error (BAD_EL_TYPE
);
18182 if (inst
.cond
> COND_ALWAYS
)
18183 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18185 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18187 mve_encode_qqq (0, 64);
18191 do_mve_vbrsr (void)
18193 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18194 struct neon_type_el et
18195 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18197 if (inst
.cond
> COND_ALWAYS
)
18198 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18200 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18202 mve_encode_qqr (et
.size
, 0, 0);
18208 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18210 if (inst
.cond
> COND_ALWAYS
)
18211 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18213 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18215 mve_encode_qqq (1, 64);
18219 do_mve_vmulh (void)
18221 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18222 struct neon_type_el et
18223 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18225 if (inst
.cond
> COND_ALWAYS
)
18226 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18228 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18230 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18234 do_mve_vqdmlah (void)
18236 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18237 struct neon_type_el et
18238 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18240 if (inst
.cond
> COND_ALWAYS
)
18241 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18243 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18245 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18249 do_mve_vqdmladh (void)
18251 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18252 struct neon_type_el et
18253 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18255 if (inst
.cond
> COND_ALWAYS
)
18256 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18258 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18260 mve_encode_qqq (0, et
.size
);
18265 do_mve_vmull (void)
18268 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18269 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18270 if (inst
.cond
== COND_ALWAYS
18271 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18276 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18283 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18284 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18285 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18287 /* We are dealing with MVE's vmullt. */
18289 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18290 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18291 as_tsktsk (BAD_MVE_SRCDEST
);
18293 if (inst
.cond
> COND_ALWAYS
)
18294 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18296 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18298 if (et
.type
== NT_poly
)
18299 mve_encode_qqq (neon_logbits (et
.size
), 64);
18301 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18306 inst
.instruction
= N_MNEM_vmul
;
18309 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18314 do_mve_vabav (void)
18316 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18321 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18324 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18325 | N_S16
| N_S32
| N_U8
| N_U16
18328 if (inst
.cond
> COND_ALWAYS
)
18329 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18331 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18333 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18337 do_mve_vmladav (void)
18339 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18340 struct neon_type_el et
= neon_check_type (3, rs
,
18341 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18343 if (et
.type
== NT_unsigned
18344 && (inst
.instruction
== M_MNEM_vmladavx
18345 || inst
.instruction
== M_MNEM_vmladavax
18346 || inst
.instruction
== M_MNEM_vmlsdav
18347 || inst
.instruction
== M_MNEM_vmlsdava
18348 || inst
.instruction
== M_MNEM_vmlsdavx
18349 || inst
.instruction
== M_MNEM_vmlsdavax
))
18350 first_error (BAD_SIMD_TYPE
);
18352 constraint (inst
.operands
[2].reg
> 14,
18353 _("MVE vector register in the range [Q0..Q7] expected"));
18355 if (inst
.cond
> COND_ALWAYS
)
18356 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18358 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18360 if (inst
.instruction
== M_MNEM_vmlsdav
18361 || inst
.instruction
== M_MNEM_vmlsdava
18362 || inst
.instruction
== M_MNEM_vmlsdavx
18363 || inst
.instruction
== M_MNEM_vmlsdavax
)
18364 inst
.instruction
|= (et
.size
== 8) << 28;
18366 inst
.instruction
|= (et
.size
== 8) << 8;
18368 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18369 inst
.instruction
|= (et
.size
== 32) << 16;
18373 do_mve_vmlaldav (void)
18375 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18376 struct neon_type_el et
18377 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18378 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18380 if (et
.type
== NT_unsigned
18381 && (inst
.instruction
== M_MNEM_vmlsldav
18382 || inst
.instruction
== M_MNEM_vmlsldava
18383 || inst
.instruction
== M_MNEM_vmlsldavx
18384 || inst
.instruction
== M_MNEM_vmlsldavax
))
18385 first_error (BAD_SIMD_TYPE
);
18387 if (inst
.cond
> COND_ALWAYS
)
18388 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18390 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18392 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18396 do_mve_vrmlaldavh (void)
18398 struct neon_type_el et
;
18399 if (inst
.instruction
== M_MNEM_vrmlsldavh
18400 || inst
.instruction
== M_MNEM_vrmlsldavha
18401 || inst
.instruction
== M_MNEM_vrmlsldavhx
18402 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18404 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18405 if (inst
.operands
[1].reg
== REG_SP
)
18406 as_tsktsk (MVE_BAD_SP
);
18410 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18411 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18412 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18414 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18415 N_U32
| N_S32
| N_KEY
);
18416 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18417 with vmax/min instructions, making the use of SP in assembly really
18418 nonsensical, so instead of issuing a warning like we do for other uses
18419 of SP for the odd register operand we error out. */
18420 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18423 /* Make sure we still check the second operand is an odd one and that PC is
18424 disallowed. This because we are parsing for any GPR operand, to be able
18425 to distinguish between giving a warning or an error for SP as described
18427 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18428 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18430 if (inst
.cond
> COND_ALWAYS
)
18431 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18433 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18435 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18440 do_mve_vmaxnmv (void)
18442 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18443 struct neon_type_el et
18444 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18446 if (inst
.cond
> COND_ALWAYS
)
18447 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18449 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18451 if (inst
.operands
[0].reg
== REG_SP
)
18452 as_tsktsk (MVE_BAD_SP
);
18453 else if (inst
.operands
[0].reg
== REG_PC
)
18454 as_tsktsk (MVE_BAD_PC
);
18456 mve_encode_rq (et
.size
== 16, 64);
18460 do_mve_vmaxv (void)
18462 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18463 struct neon_type_el et
;
18465 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18466 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18468 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18470 if (inst
.cond
> COND_ALWAYS
)
18471 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18473 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18475 if (inst
.operands
[0].reg
== REG_SP
)
18476 as_tsktsk (MVE_BAD_SP
);
18477 else if (inst
.operands
[0].reg
== REG_PC
)
18478 as_tsktsk (MVE_BAD_PC
);
18480 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18485 do_neon_qrdmlah (void)
18487 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18489 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18491 /* Check we're on the correct architecture. */
18492 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18494 = _("instruction form not available on this architecture.");
18495 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18497 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18498 record_feature_use (&fpu_neon_ext_v8_1
);
18500 if (inst
.operands
[2].isscalar
)
18502 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18503 struct neon_type_el et
= neon_check_type (3, rs
,
18504 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18505 NEON_ENCODE (SCALAR
, inst
);
18506 neon_mul_mac (et
, neon_quad (rs
));
18510 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18511 struct neon_type_el et
= neon_check_type (3, rs
,
18512 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18513 NEON_ENCODE (INTEGER
, inst
);
18514 /* The U bit (rounding) comes from bit mask. */
18515 neon_three_same (neon_quad (rs
), 0, et
.size
);
18520 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18521 struct neon_type_el et
18522 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18524 NEON_ENCODE (INTEGER
, inst
);
18525 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18530 do_neon_fcmp_absolute (void)
18532 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18533 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18534 N_F_16_32
| N_KEY
);
18535 /* Size field comes from bit mask. */
18536 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18540 do_neon_fcmp_absolute_inv (void)
18542 neon_exchange_operands ();
18543 do_neon_fcmp_absolute ();
18547 do_neon_step (void)
18549 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18550 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18551 N_F_16_32
| N_KEY
);
18552 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18556 do_neon_abs_neg (void)
18558 enum neon_shape rs
;
18559 struct neon_type_el et
;
18561 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18564 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18565 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18567 if (!check_simd_pred_availability (et
.type
== NT_float
,
18568 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18571 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18572 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18573 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18574 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18575 inst
.instruction
|= neon_quad (rs
) << 6;
18576 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18577 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18579 neon_dp_fixup (&inst
);
18585 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18588 enum neon_shape rs
;
18589 struct neon_type_el et
;
18590 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18592 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18593 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18597 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18598 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18602 int imm
= inst
.operands
[2].imm
;
18603 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18604 _("immediate out of range for insert"));
18605 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18611 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18614 enum neon_shape rs
;
18615 struct neon_type_el et
;
18616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18618 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18619 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18623 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18624 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18627 int imm
= inst
.operands
[2].imm
;
18628 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18629 _("immediate out of range for insert"));
18630 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18634 do_neon_qshlu_imm (void)
18636 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18639 enum neon_shape rs
;
18640 struct neon_type_el et
;
18641 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18643 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18644 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18648 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18649 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18650 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18653 int imm
= inst
.operands
[2].imm
;
18654 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18655 _("immediate out of range for shift"));
18656 /* Only encodes the 'U present' variant of the instruction.
18657 In this case, signed types have OP (bit 8) set to 0.
18658 Unsigned types have OP set to 1. */
18659 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18660 /* The rest of the bits are the same as other immediate shifts. */
18661 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18665 do_neon_qmovn (void)
18667 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18668 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18669 /* Saturating move where operands can be signed or unsigned, and the
18670 destination has the same signedness. */
18671 NEON_ENCODE (INTEGER
, inst
);
18672 if (et
.type
== NT_unsigned
)
18673 inst
.instruction
|= 0xc0;
18675 inst
.instruction
|= 0x80;
18676 neon_two_same (0, 1, et
.size
/ 2);
18680 do_neon_qmovun (void)
18682 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18683 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18684 /* Saturating move with unsigned results. Operands must be signed. */
18685 NEON_ENCODE (INTEGER
, inst
);
18686 neon_two_same (0, 1, et
.size
/ 2);
18690 do_neon_rshift_sat_narrow (void)
18692 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18693 or unsigned. If operands are unsigned, results must also be unsigned. */
18694 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18695 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18696 int imm
= inst
.operands
[2].imm
;
18697 /* This gets the bounds check, size encoding and immediate bits calculation
18701 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18702 VQMOVN.I<size> <Dd>, <Qm>. */
18705 inst
.operands
[2].present
= 0;
18706 inst
.instruction
= N_MNEM_vqmovn
;
18711 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18712 _("immediate out of range"));
18713 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18717 do_neon_rshift_sat_narrow_u (void)
18719 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18720 or unsigned. If operands are unsigned, results must also be unsigned. */
18721 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18722 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18723 int imm
= inst
.operands
[2].imm
;
18724 /* This gets the bounds check, size encoding and immediate bits calculation
18728 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18729 VQMOVUN.I<size> <Dd>, <Qm>. */
18732 inst
.operands
[2].present
= 0;
18733 inst
.instruction
= N_MNEM_vqmovun
;
18738 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18739 _("immediate out of range"));
18740 /* FIXME: The manual is kind of unclear about what value U should have in
18741 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18743 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18747 do_neon_movn (void)
18749 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18750 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18751 NEON_ENCODE (INTEGER
, inst
);
18752 neon_two_same (0, 1, et
.size
/ 2);
18756 do_neon_rshift_narrow (void)
18758 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18759 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18760 int imm
= inst
.operands
[2].imm
;
18761 /* This gets the bounds check, size encoding and immediate bits calculation
18765 /* If immediate is zero then we are a pseudo-instruction for
18766 VMOVN.I<size> <Dd>, <Qm> */
18769 inst
.operands
[2].present
= 0;
18770 inst
.instruction
= N_MNEM_vmovn
;
18775 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18776 _("immediate out of range for narrowing operation"));
18777 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18781 do_neon_shll (void)
18783 /* FIXME: Type checking when lengthening. */
18784 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18785 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18786 unsigned imm
= inst
.operands
[2].imm
;
18788 if (imm
== et
.size
)
18790 /* Maximum shift variant. */
18791 NEON_ENCODE (INTEGER
, inst
);
18792 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18793 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18794 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18795 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18796 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18798 neon_dp_fixup (&inst
);
18802 /* A more-specific type check for non-max versions. */
18803 et
= neon_check_type (2, NS_QDI
,
18804 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18805 NEON_ENCODE (IMMED
, inst
);
18806 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18810 /* Check the various types for the VCVT instruction, and return which version
18811 the current instruction is. */
18813 #define CVT_FLAVOUR_VAR \
18814 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18815 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18816 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18817 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18818 /* Half-precision conversions. */ \
18819 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18820 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18821 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18822 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18823 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18825 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18826 Compared with single/double precision variants, only the co-processor \
18827 field is different, so the encoding flow is reused here. */ \
18828 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18829 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18830 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18831 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18832 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18833 /* VFP instructions. */ \
18834 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18835 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18836 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18837 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18838 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18839 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18840 /* VFP instructions with bitshift. */ \
18841 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18842 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18843 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18844 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18845 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18846 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18847 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18848 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18850 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18851 neon_cvt_flavour_##C,
18853 /* The different types of conversions we can do. */
18854 enum neon_cvt_flavour
18857 neon_cvt_flavour_invalid
,
18858 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18863 static enum neon_cvt_flavour
18864 get_neon_cvt_flavour (enum neon_shape rs
)
18866 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18867 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18868 if (et.type != NT_invtype) \
18870 inst.error = NULL; \
18871 return (neon_cvt_flavour_##C); \
18874 struct neon_type_el et
;
18875 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18876 || rs
== NS_FF
) ? N_VFP
: 0;
18877 /* The instruction versions which take an immediate take one register
18878 argument, which is extended to the width of the full register. Thus the
18879 "source" and "destination" registers must have the same width. Hack that
18880 here by making the size equal to the key (wider, in this case) operand. */
18881 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18885 return neon_cvt_flavour_invalid
;
18900 /* Neon-syntax VFP conversions. */
18903 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18905 const char *opname
= 0;
18907 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18908 || rs
== NS_FHI
|| rs
== NS_HFI
)
18910 /* Conversions with immediate bitshift. */
18911 const char *enc
[] =
18913 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18919 if (flavour
< (int) ARRAY_SIZE (enc
))
18921 opname
= enc
[flavour
];
18922 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18923 _("operands 0 and 1 must be the same register"));
18924 inst
.operands
[1] = inst
.operands
[2];
18925 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18930 /* Conversions without bitshift. */
18931 const char *enc
[] =
18933 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18939 if (flavour
< (int) ARRAY_SIZE (enc
))
18940 opname
= enc
[flavour
];
18944 do_vfp_nsyn_opcode (opname
);
18946 /* ARMv8.2 fp16 VCVT instruction. */
18947 if (flavour
== neon_cvt_flavour_s32_f16
18948 || flavour
== neon_cvt_flavour_u32_f16
18949 || flavour
== neon_cvt_flavour_f16_u32
18950 || flavour
== neon_cvt_flavour_f16_s32
)
18951 do_scalar_fp16_v82_encode ();
18955 do_vfp_nsyn_cvtz (void)
18957 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18958 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18959 const char *enc
[] =
18961 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18967 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18968 do_vfp_nsyn_opcode (enc
[flavour
]);
18972 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18973 enum neon_cvt_mode mode
)
18978 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18979 D register operands. */
18980 if (flavour
== neon_cvt_flavour_s32_f64
18981 || flavour
== neon_cvt_flavour_u32_f64
)
18982 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18985 if (flavour
== neon_cvt_flavour_s32_f16
18986 || flavour
== neon_cvt_flavour_u32_f16
)
18987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18990 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18994 case neon_cvt_flavour_s32_f64
:
18998 case neon_cvt_flavour_s32_f32
:
19002 case neon_cvt_flavour_s32_f16
:
19006 case neon_cvt_flavour_u32_f64
:
19010 case neon_cvt_flavour_u32_f32
:
19014 case neon_cvt_flavour_u32_f16
:
19019 first_error (_("invalid instruction shape"));
19025 case neon_cvt_mode_a
: rm
= 0; break;
19026 case neon_cvt_mode_n
: rm
= 1; break;
19027 case neon_cvt_mode_p
: rm
= 2; break;
19028 case neon_cvt_mode_m
: rm
= 3; break;
19029 default: first_error (_("invalid rounding mode")); return;
19032 NEON_ENCODE (FPV8
, inst
);
19033 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19034 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19035 inst
.instruction
|= sz
<< 8;
19037 /* ARMv8.2 fp16 VCVT instruction. */
19038 if (flavour
== neon_cvt_flavour_s32_f16
19039 ||flavour
== neon_cvt_flavour_u32_f16
)
19040 do_scalar_fp16_v82_encode ();
19041 inst
.instruction
|= op
<< 7;
19042 inst
.instruction
|= rm
<< 16;
19043 inst
.instruction
|= 0xf0000000;
19044 inst
.is_neon
= TRUE
;
19048 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19050 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19051 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19052 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19054 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19056 if (flavour
== neon_cvt_flavour_invalid
)
19059 /* PR11109: Handle round-to-zero for VCVT conversions. */
19060 if (mode
== neon_cvt_mode_z
19061 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19062 && (flavour
== neon_cvt_flavour_s16_f16
19063 || flavour
== neon_cvt_flavour_u16_f16
19064 || flavour
== neon_cvt_flavour_s32_f32
19065 || flavour
== neon_cvt_flavour_u32_f32
19066 || flavour
== neon_cvt_flavour_s32_f64
19067 || flavour
== neon_cvt_flavour_u32_f64
)
19068 && (rs
== NS_FD
|| rs
== NS_FF
))
19070 do_vfp_nsyn_cvtz ();
19074 /* ARMv8.2 fp16 VCVT conversions. */
19075 if (mode
== neon_cvt_mode_z
19076 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19077 && (flavour
== neon_cvt_flavour_s32_f16
19078 || flavour
== neon_cvt_flavour_u32_f16
)
19081 do_vfp_nsyn_cvtz ();
19082 do_scalar_fp16_v82_encode ();
19086 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19087 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19089 /* We are dealing with vcvt with the 'ne' condition. */
19091 inst
.instruction
= N_MNEM_vcvt
;
19092 do_neon_cvt_1 (neon_cvt_mode_z
);
19096 /* VFP rather than Neon conversions. */
19097 if (flavour
>= neon_cvt_flavour_first_fp
)
19099 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19100 do_vfp_nsyn_cvt (rs
, flavour
);
19102 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19110 if (mode
== neon_cvt_mode_z
19111 && (flavour
== neon_cvt_flavour_f16_s16
19112 || flavour
== neon_cvt_flavour_f16_u16
19113 || flavour
== neon_cvt_flavour_s16_f16
19114 || flavour
== neon_cvt_flavour_u16_f16
19115 || flavour
== neon_cvt_flavour_f32_u32
19116 || flavour
== neon_cvt_flavour_f32_s32
19117 || flavour
== neon_cvt_flavour_s32_f32
19118 || flavour
== neon_cvt_flavour_u32_f32
))
19120 if (!check_simd_pred_availability (TRUE
,
19121 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19124 /* fall through. */
19128 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19129 0x0000100, 0x1000100, 0x0, 0x1000000};
19131 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19132 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19135 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19137 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19138 _("immediate value out of range"));
19141 case neon_cvt_flavour_f16_s16
:
19142 case neon_cvt_flavour_f16_u16
:
19143 case neon_cvt_flavour_s16_f16
:
19144 case neon_cvt_flavour_u16_f16
:
19145 constraint (inst
.operands
[2].imm
> 16,
19146 _("immediate value out of range"));
19148 case neon_cvt_flavour_f32_u32
:
19149 case neon_cvt_flavour_f32_s32
:
19150 case neon_cvt_flavour_s32_f32
:
19151 case neon_cvt_flavour_u32_f32
:
19152 constraint (inst
.operands
[2].imm
> 32,
19153 _("immediate value out of range"));
19156 inst
.error
= BAD_FPU
;
19161 /* Fixed-point conversion with #0 immediate is encoded as an
19162 integer conversion. */
19163 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19165 NEON_ENCODE (IMMED
, inst
);
19166 if (flavour
!= neon_cvt_flavour_invalid
)
19167 inst
.instruction
|= enctab
[flavour
];
19168 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19169 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19170 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19171 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19172 inst
.instruction
|= neon_quad (rs
) << 6;
19173 inst
.instruction
|= 1 << 21;
19174 if (flavour
< neon_cvt_flavour_s16_f16
)
19176 inst
.instruction
|= 1 << 21;
19177 immbits
= 32 - inst
.operands
[2].imm
;
19178 inst
.instruction
|= immbits
<< 16;
19182 inst
.instruction
|= 3 << 20;
19183 immbits
= 16 - inst
.operands
[2].imm
;
19184 inst
.instruction
|= immbits
<< 16;
19185 inst
.instruction
&= ~(1 << 9);
19188 neon_dp_fixup (&inst
);
19193 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19194 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19195 && (flavour
== neon_cvt_flavour_s16_f16
19196 || flavour
== neon_cvt_flavour_u16_f16
19197 || flavour
== neon_cvt_flavour_s32_f32
19198 || flavour
== neon_cvt_flavour_u32_f32
))
19200 if (!check_simd_pred_availability (TRUE
,
19201 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19204 else if (mode
== neon_cvt_mode_z
19205 && (flavour
== neon_cvt_flavour_f16_s16
19206 || flavour
== neon_cvt_flavour_f16_u16
19207 || flavour
== neon_cvt_flavour_s16_f16
19208 || flavour
== neon_cvt_flavour_u16_f16
19209 || flavour
== neon_cvt_flavour_f32_u32
19210 || flavour
== neon_cvt_flavour_f32_s32
19211 || flavour
== neon_cvt_flavour_s32_f32
19212 || flavour
== neon_cvt_flavour_u32_f32
))
19214 if (!check_simd_pred_availability (TRUE
,
19215 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19218 /* fall through. */
19220 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19223 NEON_ENCODE (FLOAT
, inst
);
19224 if (!check_simd_pred_availability (TRUE
,
19225 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19228 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19230 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19231 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19232 inst
.instruction
|= neon_quad (rs
) << 6;
19233 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19234 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19235 inst
.instruction
|= mode
<< 8;
19236 if (flavour
== neon_cvt_flavour_u16_f16
19237 || flavour
== neon_cvt_flavour_s16_f16
)
19238 /* Mask off the original size bits and reencode them. */
19239 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19242 inst
.instruction
|= 0xfc000000;
19244 inst
.instruction
|= 0xf0000000;
19250 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19251 0x100, 0x180, 0x0, 0x080};
19253 NEON_ENCODE (INTEGER
, inst
);
19255 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19257 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19261 if (flavour
!= neon_cvt_flavour_invalid
)
19262 inst
.instruction
|= enctab
[flavour
];
19264 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19265 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19266 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19267 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19268 inst
.instruction
|= neon_quad (rs
) << 6;
19269 if (flavour
>= neon_cvt_flavour_s16_f16
19270 && flavour
<= neon_cvt_flavour_f16_u16
)
19271 /* Half precision. */
19272 inst
.instruction
|= 1 << 18;
19274 inst
.instruction
|= 2 << 18;
19276 neon_dp_fixup (&inst
);
19281 /* Half-precision conversions for Advanced SIMD -- neon. */
19284 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19288 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19290 as_bad (_("operand size must match register width"));
19295 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19297 as_bad (_("operand size must match register width"));
19303 if (flavour
== neon_cvt_flavour_bf16_f32
)
19305 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19307 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19308 /* VCVT.bf16.f32. */
19309 inst
.instruction
= 0x11b60640;
19312 /* VCVT.f16.f32. */
19313 inst
.instruction
= 0x3b60600;
19316 /* VCVT.f32.f16. */
19317 inst
.instruction
= 0x3b60700;
19319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19321 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19322 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19323 neon_dp_fixup (&inst
);
19327 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19328 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19329 do_vfp_nsyn_cvt (rs
, flavour
);
19331 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19336 do_neon_cvtr (void)
19338 do_neon_cvt_1 (neon_cvt_mode_x
);
19344 do_neon_cvt_1 (neon_cvt_mode_z
);
19348 do_neon_cvta (void)
19350 do_neon_cvt_1 (neon_cvt_mode_a
);
19354 do_neon_cvtn (void)
19356 do_neon_cvt_1 (neon_cvt_mode_n
);
19360 do_neon_cvtp (void)
19362 do_neon_cvt_1 (neon_cvt_mode_p
);
19366 do_neon_cvtm (void)
19368 do_neon_cvt_1 (neon_cvt_mode_m
);
19372 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19375 mark_feature_used (&fpu_vfp_ext_armv8
);
19377 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19378 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19379 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19380 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19381 inst
.instruction
|= to
? 0x10000 : 0;
19382 inst
.instruction
|= t
? 0x80 : 0;
19383 inst
.instruction
|= is_double
? 0x100 : 0;
19384 do_vfp_cond_or_thumb ();
19388 do_neon_cvttb_1 (bfd_boolean t
)
19390 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19391 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19395 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19397 int single_to_half
= 0;
19398 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19401 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19403 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19404 && (flavour
== neon_cvt_flavour_u16_f16
19405 || flavour
== neon_cvt_flavour_s16_f16
19406 || flavour
== neon_cvt_flavour_f16_s16
19407 || flavour
== neon_cvt_flavour_f16_u16
19408 || flavour
== neon_cvt_flavour_u32_f32
19409 || flavour
== neon_cvt_flavour_s32_f32
19410 || flavour
== neon_cvt_flavour_f32_s32
19411 || flavour
== neon_cvt_flavour_f32_u32
))
19414 inst
.instruction
= N_MNEM_vcvt
;
19415 set_pred_insn_type (INSIDE_VPT_INSN
);
19416 do_neon_cvt_1 (neon_cvt_mode_z
);
19419 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19420 single_to_half
= 1;
19421 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19423 first_error (BAD_FPU
);
19427 inst
.instruction
= 0xee3f0e01;
19428 inst
.instruction
|= single_to_half
<< 28;
19429 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19430 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19431 inst
.instruction
|= t
<< 12;
19432 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19436 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19439 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19441 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19444 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19446 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19448 /* The VCVTB and VCVTT instructions with D-register operands
19449 don't work for SP only targets. */
19450 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19454 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19456 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19458 /* The VCVTB and VCVTT instructions with D-register operands
19459 don't work for SP only targets. */
19460 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19464 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19466 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19468 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19470 inst
.instruction
|= (1 << 8);
19471 inst
.instruction
&= ~(1 << 9);
19472 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19479 do_neon_cvtb (void)
19481 do_neon_cvttb_1 (FALSE
);
19486 do_neon_cvtt (void)
19488 do_neon_cvttb_1 (TRUE
);
19492 neon_move_immediate (void)
19494 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19495 struct neon_type_el et
= neon_check_type (2, rs
,
19496 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19497 unsigned immlo
, immhi
= 0, immbits
;
19498 int op
, cmode
, float_p
;
19500 constraint (et
.type
== NT_invtype
,
19501 _("operand size must be specified for immediate VMOV"));
19503 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19504 op
= (inst
.instruction
& (1 << 5)) != 0;
19506 immlo
= inst
.operands
[1].imm
;
19507 if (inst
.operands
[1].regisimm
)
19508 immhi
= inst
.operands
[1].reg
;
19510 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19511 _("immediate has bits set outside the operand size"));
19513 float_p
= inst
.operands
[1].immisfloat
;
19515 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19516 et
.size
, et
.type
)) == FAIL
)
19518 /* Invert relevant bits only. */
19519 neon_invert_size (&immlo
, &immhi
, et
.size
);
19520 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19521 with one or the other; those cases are caught by
19522 neon_cmode_for_move_imm. */
19524 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19525 &op
, et
.size
, et
.type
)) == FAIL
)
19527 first_error (_("immediate out of range"));
19532 inst
.instruction
&= ~(1 << 5);
19533 inst
.instruction
|= op
<< 5;
19535 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19536 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19537 inst
.instruction
|= neon_quad (rs
) << 6;
19538 inst
.instruction
|= cmode
<< 8;
19540 neon_write_immbits (immbits
);
19546 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19549 if (inst
.operands
[1].isreg
)
19551 enum neon_shape rs
;
19552 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19553 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19555 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19560 NEON_ENCODE (INTEGER
, inst
);
19561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19564 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19565 inst
.instruction
|= neon_quad (rs
) << 6;
19569 NEON_ENCODE (IMMED
, inst
);
19570 neon_move_immediate ();
19573 neon_dp_fixup (&inst
);
19575 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19577 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19581 /* Encode instructions of form:
19583 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19584 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19587 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19593 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19594 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19595 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19596 inst
.instruction
|= neon_logbits (size
) << 20;
19598 neon_dp_fixup (&inst
);
19602 do_neon_dyadic_long (void)
19604 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19607 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19610 NEON_ENCODE (INTEGER
, inst
);
19611 /* FIXME: Type checking for lengthening op. */
19612 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19613 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19614 neon_mixed_length (et
, et
.size
);
19616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19617 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19619 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19620 in an IT block with le/lt conditions. */
19622 if (inst
.cond
== 0xf)
19624 else if (inst
.cond
== 0x10)
19627 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19629 if (inst
.instruction
== N_MNEM_vaddl
)
19631 inst
.instruction
= N_MNEM_vadd
;
19632 do_neon_addsub_if_i ();
19634 else if (inst
.instruction
== N_MNEM_vsubl
)
19636 inst
.instruction
= N_MNEM_vsub
;
19637 do_neon_addsub_if_i ();
19639 else if (inst
.instruction
== N_MNEM_vabdl
)
19641 inst
.instruction
= N_MNEM_vabd
;
19642 do_neon_dyadic_if_su ();
19646 first_error (BAD_FPU
);
19650 do_neon_abal (void)
19652 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19653 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19654 neon_mixed_length (et
, et
.size
);
19658 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19660 if (inst
.operands
[2].isscalar
)
19662 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19663 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19664 NEON_ENCODE (SCALAR
, inst
);
19665 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19669 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19670 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19671 NEON_ENCODE (INTEGER
, inst
);
19672 neon_mixed_length (et
, et
.size
);
19677 do_neon_mac_maybe_scalar_long (void)
19679 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19682 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19683 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19686 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19688 unsigned regno
= NEON_SCALAR_REG (scalar
);
19689 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19693 if (regno
> 7 || elno
> 3)
19696 return ((regno
& 0x7)
19697 | ((elno
& 0x1) << 3)
19698 | (((elno
>> 1) & 0x1) << 5));
19702 if (regno
> 15 || elno
> 1)
19705 return (((regno
& 0x1) << 5)
19706 | ((regno
>> 1) & 0x7)
19707 | ((elno
& 0x1) << 3));
19711 first_error (_("scalar out of range for multiply instruction"));
19716 do_neon_fmac_maybe_scalar_long (int subtype
)
19718 enum neon_shape rs
;
19720 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19721 field (bits[21:20]) has different meaning. For scalar index variant, it's
19722 used to differentiate add and subtract, otherwise it's with fixed value
19726 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19727 be a scalar index register. */
19728 if (inst
.operands
[2].isscalar
)
19730 high8
= 0xfe000000;
19733 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19737 high8
= 0xfc000000;
19740 inst
.instruction
|= (0x1 << 23);
19741 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19745 if (inst
.cond
!= COND_ALWAYS
)
19746 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19747 "behaviour is UNPREDICTABLE"));
19749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19755 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19756 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19757 so we simply pass -1 as size. */
19758 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19759 neon_three_same (quad_p
, 0, size
);
19761 /* Undo neon_dp_fixup. Redo the high eight bits. */
19762 inst
.instruction
&= 0x00ffffff;
19763 inst
.instruction
|= high8
;
19765 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19766 whether the instruction is in Q form and whether Vm is a scalar indexed
19768 if (inst
.operands
[2].isscalar
)
19771 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19772 inst
.instruction
&= 0xffffffd0;
19773 inst
.instruction
|= rm
;
19777 /* Redo Rn as well. */
19778 inst
.instruction
&= 0xfff0ff7f;
19779 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19780 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19785 /* Redo Rn and Rm. */
19786 inst
.instruction
&= 0xfff0ff50;
19787 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19788 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19789 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19790 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19795 do_neon_vfmal (void)
19797 return do_neon_fmac_maybe_scalar_long (0);
19801 do_neon_vfmsl (void)
19803 return do_neon_fmac_maybe_scalar_long (1);
19807 do_neon_dyadic_wide (void)
19809 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19810 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19811 neon_mixed_length (et
, et
.size
);
19815 do_neon_dyadic_narrow (void)
19817 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19818 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19819 /* Operand sign is unimportant, and the U bit is part of the opcode,
19820 so force the operand type to integer. */
19821 et
.type
= NT_integer
;
19822 neon_mixed_length (et
, et
.size
/ 2);
19826 do_neon_mul_sat_scalar_long (void)
19828 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19832 do_neon_vmull (void)
19834 if (inst
.operands
[2].isscalar
)
19835 do_neon_mac_maybe_scalar_long ();
19838 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19839 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19841 if (et
.type
== NT_poly
)
19842 NEON_ENCODE (POLY
, inst
);
19844 NEON_ENCODE (INTEGER
, inst
);
19846 /* For polynomial encoding the U bit must be zero, and the size must
19847 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19848 obviously, as 0b10). */
19851 /* Check we're on the correct architecture. */
19852 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19854 _("Instruction form not available on this architecture.");
19859 neon_mixed_length (et
, et
.size
);
19866 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19867 struct neon_type_el et
= neon_check_type (3, rs
,
19868 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19869 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19871 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19872 _("shift out of range"));
19873 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19875 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19876 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19877 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19878 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19879 inst
.instruction
|= neon_quad (rs
) << 6;
19880 inst
.instruction
|= imm
<< 8;
19882 neon_dp_fixup (&inst
);
19888 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19891 enum neon_shape rs
;
19892 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19893 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19895 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19897 struct neon_type_el et
= neon_check_type (2, rs
,
19898 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19900 unsigned op
= (inst
.instruction
>> 7) & 3;
19901 /* N (width of reversed regions) is encoded as part of the bitmask. We
19902 extract it here to check the elements to be reversed are smaller.
19903 Otherwise we'd get a reserved instruction. */
19904 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19907 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19908 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19909 " operands makes instruction UNPREDICTABLE"));
19911 gas_assert (elsize
!= 0);
19912 constraint (et
.size
>= elsize
,
19913 _("elements must be smaller than reversal region"));
19914 neon_two_same (neon_quad (rs
), 1, et
.size
);
19920 if (inst
.operands
[1].isscalar
)
19922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19924 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19925 struct neon_type_el et
= neon_check_type (2, rs
,
19926 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19927 unsigned sizebits
= et
.size
>> 3;
19928 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19929 int logsize
= neon_logbits (et
.size
);
19930 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19932 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19935 NEON_ENCODE (SCALAR
, inst
);
19936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19938 inst
.instruction
|= LOW4 (dm
);
19939 inst
.instruction
|= HI1 (dm
) << 5;
19940 inst
.instruction
|= neon_quad (rs
) << 6;
19941 inst
.instruction
|= x
<< 17;
19942 inst
.instruction
|= sizebits
<< 16;
19944 neon_dp_fixup (&inst
);
19948 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19949 struct neon_type_el et
= neon_check_type (2, rs
,
19950 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19953 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19962 if (inst
.operands
[1].reg
== REG_SP
)
19963 as_tsktsk (MVE_BAD_SP
);
19964 else if (inst
.operands
[1].reg
== REG_PC
)
19965 as_tsktsk (MVE_BAD_PC
);
19968 /* Duplicate ARM register to lanes of vector. */
19969 NEON_ENCODE (ARMREG
, inst
);
19972 case 8: inst
.instruction
|= 0x400000; break;
19973 case 16: inst
.instruction
|= 0x000020; break;
19974 case 32: inst
.instruction
|= 0x000000; break;
19977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19980 inst
.instruction
|= neon_quad (rs
) << 21;
19981 /* The encoding for this instruction is identical for the ARM and Thumb
19982 variants, except for the condition field. */
19983 do_vfp_cond_or_thumb ();
19988 do_mve_mov (int toQ
)
19990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19992 if (inst
.cond
> COND_ALWAYS
)
19993 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19995 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20004 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20005 _("Index one must be [2,3] and index two must be two less than"
20007 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20008 _("General purpose registers may not be the same"));
20009 constraint (inst
.operands
[Rt
].reg
== REG_SP
20010 || inst
.operands
[Rt2
].reg
== REG_SP
,
20012 constraint (inst
.operands
[Rt
].reg
== REG_PC
20013 || inst
.operands
[Rt2
].reg
== REG_PC
,
20016 inst
.instruction
= 0xec000f00;
20017 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20018 inst
.instruction
|= !!toQ
<< 20;
20019 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20020 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20021 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20022 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20028 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20031 if (inst
.cond
> COND_ALWAYS
)
20032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20036 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20039 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20040 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20042 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20048 /* VMOV has particularly many variations. It can be one of:
20049 0. VMOV<c><q> <Qd>, <Qm>
20050 1. VMOV<c><q> <Dd>, <Dm>
20051 (Register operations, which are VORR with Rm = Rn.)
20052 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20053 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20055 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20056 (ARM register to scalar.)
20057 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20058 (Two ARM registers to vector.)
20059 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20060 (Scalar to ARM register.)
20061 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20062 (Vector to two ARM registers.)
20063 8. VMOV.F32 <Sd>, <Sm>
20064 9. VMOV.F64 <Dd>, <Dm>
20065 (VFP register moves.)
20066 10. VMOV.F32 <Sd>, #imm
20067 11. VMOV.F64 <Dd>, #imm
20068 (VFP float immediate load.)
20069 12. VMOV <Rd>, <Sm>
20070 (VFP single to ARM reg.)
20071 13. VMOV <Sd>, <Rm>
20072 (ARM reg to VFP single.)
20073 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20074 (Two ARM regs to two VFP singles.)
20075 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20076 (Two VFP singles to two ARM regs.)
20077 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20078 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20079 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20080 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20082 These cases can be disambiguated using neon_select_shape, except cases 1/9
20083 and 3/11 which depend on the operand type too.
20085 All the encoded bits are hardcoded by this function.
20087 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20088 Cases 5, 7 may be used with VFPv2 and above.
20090 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20091 can specify a type where it doesn't make sense to, and is ignored). */
20096 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20097 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20098 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20099 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20101 struct neon_type_el et
;
20102 const char *ldconst
= 0;
20106 case NS_DD
: /* case 1/9. */
20107 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20108 /* It is not an error here if no type is given. */
20111 /* In MVE we interpret the following instructions as same, so ignoring
20112 the following type (float) and size (64) checks.
20113 a: VMOV<c><q> <Dd>, <Dm>
20114 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20115 if ((et
.type
== NT_float
&& et
.size
== 64)
20116 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20118 do_vfp_nsyn_opcode ("fcpyd");
20121 /* fall through. */
20123 case NS_QQ
: /* case 0/1. */
20125 if (!check_simd_pred_availability (FALSE
,
20126 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20128 /* The architecture manual I have doesn't explicitly state which
20129 value the U bit should have for register->register moves, but
20130 the equivalent VORR instruction has U = 0, so do that. */
20131 inst
.instruction
= 0x0200110;
20132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20136 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20137 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20138 inst
.instruction
|= neon_quad (rs
) << 6;
20140 neon_dp_fixup (&inst
);
20144 case NS_DI
: /* case 3/11. */
20145 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20147 if (et
.type
== NT_float
&& et
.size
== 64)
20149 /* case 11 (fconstd). */
20150 ldconst
= "fconstd";
20151 goto encode_fconstd
;
20153 /* fall through. */
20155 case NS_QI
: /* case 2/3. */
20156 if (!check_simd_pred_availability (FALSE
,
20157 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20159 inst
.instruction
= 0x0800010;
20160 neon_move_immediate ();
20161 neon_dp_fixup (&inst
);
20164 case NS_SR
: /* case 4. */
20166 unsigned bcdebits
= 0;
20168 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20169 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20171 /* .<size> is optional here, defaulting to .32. */
20172 if (inst
.vectype
.elems
== 0
20173 && inst
.operands
[0].vectype
.type
== NT_invtype
20174 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20176 inst
.vectype
.el
[0].type
= NT_untyped
;
20177 inst
.vectype
.el
[0].size
= 32;
20178 inst
.vectype
.elems
= 1;
20181 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20182 logsize
= neon_logbits (et
.size
);
20186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20187 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20193 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20197 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20199 if (inst
.operands
[1].reg
== REG_SP
)
20200 as_tsktsk (MVE_BAD_SP
);
20201 else if (inst
.operands
[1].reg
== REG_PC
)
20202 as_tsktsk (MVE_BAD_PC
);
20204 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20206 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20207 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20212 case 8: bcdebits
= 0x8; break;
20213 case 16: bcdebits
= 0x1; break;
20214 case 32: bcdebits
= 0x0; break;
20218 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20220 inst
.instruction
= 0xe000b10;
20221 do_vfp_cond_or_thumb ();
20222 inst
.instruction
|= LOW4 (dn
) << 16;
20223 inst
.instruction
|= HI1 (dn
) << 7;
20224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20225 inst
.instruction
|= (bcdebits
& 3) << 5;
20226 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20227 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20231 case NS_DRR
: /* case 5 (fmdrr). */
20232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20233 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20236 inst
.instruction
= 0xc400b10;
20237 do_vfp_cond_or_thumb ();
20238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20240 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20241 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20244 case NS_RS
: /* case 6. */
20247 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20248 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20249 unsigned abcdebits
= 0;
20251 /* .<dt> is optional here, defaulting to .32. */
20252 if (inst
.vectype
.elems
== 0
20253 && inst
.operands
[0].vectype
.type
== NT_invtype
20254 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20256 inst
.vectype
.el
[0].type
= NT_untyped
;
20257 inst
.vectype
.el
[0].size
= 32;
20258 inst
.vectype
.elems
= 1;
20261 et
= neon_check_type (2, NS_NULL
,
20262 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20263 logsize
= neon_logbits (et
.size
);
20267 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20268 && vfp_or_neon_is_neon (NEON_CHECK_CC
20269 | NEON_CHECK_ARCH
) == FAIL
)
20274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20275 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20279 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20281 if (inst
.operands
[0].reg
== REG_SP
)
20282 as_tsktsk (MVE_BAD_SP
);
20283 else if (inst
.operands
[0].reg
== REG_PC
)
20284 as_tsktsk (MVE_BAD_PC
);
20287 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20289 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20290 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20294 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20295 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20296 case 32: abcdebits
= 0x00; break;
20300 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20301 inst
.instruction
= 0xe100b10;
20302 do_vfp_cond_or_thumb ();
20303 inst
.instruction
|= LOW4 (dn
) << 16;
20304 inst
.instruction
|= HI1 (dn
) << 7;
20305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20306 inst
.instruction
|= (abcdebits
& 3) << 5;
20307 inst
.instruction
|= (abcdebits
>> 2) << 21;
20308 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20312 case NS_RRD
: /* case 7 (fmrrd). */
20313 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20314 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20317 inst
.instruction
= 0xc500b10;
20318 do_vfp_cond_or_thumb ();
20319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20321 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20322 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20325 case NS_FF
: /* case 8 (fcpys). */
20326 do_vfp_nsyn_opcode ("fcpys");
20330 case NS_FI
: /* case 10 (fconsts). */
20331 ldconst
= "fconsts";
20333 if (!inst
.operands
[1].immisfloat
)
20336 /* Immediate has to fit in 8 bits so float is enough. */
20337 float imm
= (float) inst
.operands
[1].imm
;
20338 memcpy (&new_imm
, &imm
, sizeof (float));
20339 /* But the assembly may have been written to provide an integer
20340 bit pattern that equates to a float, so check that the
20341 conversion has worked. */
20342 if (is_quarter_float (new_imm
))
20344 if (is_quarter_float (inst
.operands
[1].imm
))
20345 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20347 inst
.operands
[1].imm
= new_imm
;
20348 inst
.operands
[1].immisfloat
= 1;
20352 if (is_quarter_float (inst
.operands
[1].imm
))
20354 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20355 do_vfp_nsyn_opcode (ldconst
);
20357 /* ARMv8.2 fp16 vmov.f16 instruction. */
20359 do_scalar_fp16_v82_encode ();
20362 first_error (_("immediate out of range"));
20366 case NS_RF
: /* case 12 (fmrs). */
20367 do_vfp_nsyn_opcode ("fmrs");
20368 /* ARMv8.2 fp16 vmov.f16 instruction. */
20370 do_scalar_fp16_v82_encode ();
20374 case NS_FR
: /* case 13 (fmsr). */
20375 do_vfp_nsyn_opcode ("fmsr");
20376 /* ARMv8.2 fp16 vmov.f16 instruction. */
20378 do_scalar_fp16_v82_encode ();
20388 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20389 (one of which is a list), but we have parsed four. Do some fiddling to
20390 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20392 case NS_RRFF
: /* case 14 (fmrrs). */
20393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20394 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20396 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20397 _("VFP registers must be adjacent"));
20398 inst
.operands
[2].imm
= 2;
20399 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20400 do_vfp_nsyn_opcode ("fmrrs");
20403 case NS_FFRR
: /* case 15 (fmsrr). */
20404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20405 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20407 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20408 _("VFP registers must be adjacent"));
20409 inst
.operands
[1] = inst
.operands
[2];
20410 inst
.operands
[2] = inst
.operands
[3];
20411 inst
.operands
[0].imm
= 2;
20412 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20413 do_vfp_nsyn_opcode ("fmsrr");
20417 /* neon_select_shape has determined that the instruction
20418 shape is wrong and has already set the error message. */
20429 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20430 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20431 && !inst
.operands
[2].present
))
20433 inst
.instruction
= 0;
20436 set_pred_insn_type (INSIDE_IT_INSN
);
20441 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20444 if (inst
.cond
!= COND_ALWAYS
)
20445 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20447 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20448 | N_S16
| N_U16
| N_KEY
);
20450 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20452 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20453 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20455 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20460 do_neon_rshift_round_imm (void)
20462 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20465 enum neon_shape rs
;
20466 struct neon_type_el et
;
20468 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20470 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20471 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20475 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20476 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20478 int imm
= inst
.operands
[2].imm
;
20480 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20483 inst
.operands
[2].present
= 0;
20488 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20489 _("immediate out of range for shift"));
20490 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20495 do_neon_movhf (void)
20497 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20498 constraint (rs
!= NS_HH
, _("invalid suffix"));
20500 if (inst
.cond
!= COND_ALWAYS
)
20504 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20505 " the behaviour is UNPREDICTABLE"));
20509 inst
.error
= BAD_COND
;
20514 do_vfp_sp_monadic ();
20517 inst
.instruction
|= 0xf0000000;
20521 do_neon_movl (void)
20523 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20524 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20525 unsigned sizebits
= et
.size
>> 3;
20526 inst
.instruction
|= sizebits
<< 19;
20527 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20534 struct neon_type_el et
= neon_check_type (2, rs
,
20535 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20536 NEON_ENCODE (INTEGER
, inst
);
20537 neon_two_same (neon_quad (rs
), 1, et
.size
);
20541 do_neon_zip_uzp (void)
20543 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20544 struct neon_type_el et
= neon_check_type (2, rs
,
20545 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20546 if (rs
== NS_DD
&& et
.size
== 32)
20548 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20549 inst
.instruction
= N_MNEM_vtrn
;
20553 neon_two_same (neon_quad (rs
), 1, et
.size
);
20557 do_neon_sat_abs_neg (void)
20559 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20562 enum neon_shape rs
;
20563 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20564 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20566 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20567 struct neon_type_el et
= neon_check_type (2, rs
,
20568 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20569 neon_two_same (neon_quad (rs
), 1, et
.size
);
20573 do_neon_pair_long (void)
20575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20577 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20578 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20579 neon_two_same (neon_quad (rs
), 1, et
.size
);
20583 do_neon_recip_est (void)
20585 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20586 struct neon_type_el et
= neon_check_type (2, rs
,
20587 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20588 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20589 neon_two_same (neon_quad (rs
), 1, et
.size
);
20595 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20598 enum neon_shape rs
;
20599 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20600 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20602 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20604 struct neon_type_el et
= neon_check_type (2, rs
,
20605 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20606 neon_two_same (neon_quad (rs
), 1, et
.size
);
20612 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20615 enum neon_shape rs
;
20616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20617 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20619 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20621 struct neon_type_el et
= neon_check_type (2, rs
,
20622 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20623 neon_two_same (neon_quad (rs
), 1, et
.size
);
20629 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20630 struct neon_type_el et
= neon_check_type (2, rs
,
20631 N_EQK
| N_INT
, N_8
| N_KEY
);
20632 neon_two_same (neon_quad (rs
), 1, et
.size
);
20638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20641 neon_two_same (neon_quad (rs
), 1, -1);
20645 do_neon_tbl_tbx (void)
20647 unsigned listlenbits
;
20648 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20650 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20652 first_error (_("bad list length for table lookup"));
20656 listlenbits
= inst
.operands
[1].imm
- 1;
20657 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20658 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20659 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20660 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20661 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20662 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20663 inst
.instruction
|= listlenbits
<< 8;
20665 neon_dp_fixup (&inst
);
20669 do_neon_ldm_stm (void)
20671 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20672 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20674 /* P, U and L bits are part of bitmask. */
20675 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20676 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20678 if (inst
.operands
[1].issingle
)
20680 do_vfp_nsyn_ldm_stm (is_dbmode
);
20684 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20685 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20687 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20688 _("register list must contain at least 1 and at most 16 "
20691 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20692 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20694 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20696 inst
.instruction
|= offsetbits
;
20698 do_vfp_cond_or_thumb ();
20702 do_vfp_nsyn_pop (void)
20705 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20706 return do_vfp_nsyn_opcode ("vldm");
20709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20712 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20713 _("register list must contain at least 1 and at most 16 "
20716 if (inst
.operands
[1].issingle
)
20717 do_vfp_nsyn_opcode ("fldmias");
20719 do_vfp_nsyn_opcode ("fldmiad");
20723 do_vfp_nsyn_push (void)
20726 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20727 return do_vfp_nsyn_opcode ("vstmdb");
20730 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20733 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20734 _("register list must contain at least 1 and at most 16 "
20737 if (inst
.operands
[1].issingle
)
20738 do_vfp_nsyn_opcode ("fstmdbs");
20740 do_vfp_nsyn_opcode ("fstmdbd");
20745 do_neon_ldr_str (void)
20747 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20749 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20750 And is UNPREDICTABLE in thumb mode. */
20752 && inst
.operands
[1].reg
== REG_PC
20753 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20756 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20757 else if (warn_on_deprecated
)
20758 as_tsktsk (_("Use of PC here is deprecated"));
20761 if (inst
.operands
[0].issingle
)
20764 do_vfp_nsyn_opcode ("flds");
20766 do_vfp_nsyn_opcode ("fsts");
20768 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20769 if (inst
.vectype
.el
[0].size
== 16)
20770 do_scalar_fp16_v82_encode ();
20775 do_vfp_nsyn_opcode ("fldd");
20777 do_vfp_nsyn_opcode ("fstd");
20782 do_t_vldr_vstr_sysreg (void)
20784 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20785 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20787 /* Use of PC is UNPREDICTABLE. */
20788 if (inst
.operands
[1].reg
== REG_PC
)
20789 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20791 if (inst
.operands
[1].immisreg
)
20792 inst
.error
= _("instruction does not accept register index");
20794 if (!inst
.operands
[1].isreg
)
20795 inst
.error
= _("instruction does not accept PC-relative addressing");
20797 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20798 inst
.error
= _("immediate value out of range");
20800 inst
.instruction
= 0xec000f80;
20802 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20803 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20804 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20805 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20809 do_vldr_vstr (void)
20811 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20813 /* VLDR/VSTR (System Register). */
20816 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20817 as_bad (_("Instruction not permitted on this architecture"));
20819 do_t_vldr_vstr_sysreg ();
20824 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20825 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20826 as_bad (_("Instruction not permitted on this architecture"));
20827 do_neon_ldr_str ();
20831 /* "interleave" version also handles non-interleaving register VLD1/VST1
20835 do_neon_ld_st_interleave (void)
20837 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20838 N_8
| N_16
| N_32
| N_64
);
20839 unsigned alignbits
= 0;
20841 /* The bits in this table go:
20842 0: register stride of one (0) or two (1)
20843 1,2: register list length, minus one (1, 2, 3, 4).
20844 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20845 We use -1 for invalid entries. */
20846 const int typetable
[] =
20848 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20849 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20850 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20851 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20855 if (et
.type
== NT_invtype
)
20858 if (inst
.operands
[1].immisalign
)
20859 switch (inst
.operands
[1].imm
>> 8)
20861 case 64: alignbits
= 1; break;
20863 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20864 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20865 goto bad_alignment
;
20869 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20870 goto bad_alignment
;
20875 first_error (_("bad alignment"));
20879 inst
.instruction
|= alignbits
<< 4;
20880 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20882 /* Bits [4:6] of the immediate in a list specifier encode register stride
20883 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20884 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20885 up the right value for "type" in a table based on this value and the given
20886 list style, then stick it back. */
20887 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20888 | (((inst
.instruction
>> 8) & 3) << 3);
20890 typebits
= typetable
[idx
];
20892 constraint (typebits
== -1, _("bad list type for instruction"));
20893 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20896 inst
.instruction
&= ~0xf00;
20897 inst
.instruction
|= typebits
<< 8;
20900 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20901 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20902 otherwise. The variable arguments are a list of pairs of legal (size, align)
20903 values, terminated with -1. */
20906 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20909 int result
= FAIL
, thissize
, thisalign
;
20911 if (!inst
.operands
[1].immisalign
)
20917 va_start (ap
, do_alignment
);
20921 thissize
= va_arg (ap
, int);
20922 if (thissize
== -1)
20924 thisalign
= va_arg (ap
, int);
20926 if (size
== thissize
&& align
== thisalign
)
20929 while (result
!= SUCCESS
);
20933 if (result
== SUCCESS
)
20936 first_error (_("unsupported alignment for instruction"));
20942 do_neon_ld_st_lane (void)
20944 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20945 int align_good
, do_alignment
= 0;
20946 int logsize
= neon_logbits (et
.size
);
20947 int align
= inst
.operands
[1].imm
>> 8;
20948 int n
= (inst
.instruction
>> 8) & 3;
20949 int max_el
= 64 / et
.size
;
20951 if (et
.type
== NT_invtype
)
20954 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20955 _("bad list length"));
20956 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20957 _("scalar index out of range"));
20958 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20960 _("stride of 2 unavailable when element size is 8"));
20964 case 0: /* VLD1 / VST1. */
20965 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20967 if (align_good
== FAIL
)
20971 unsigned alignbits
= 0;
20974 case 16: alignbits
= 0x1; break;
20975 case 32: alignbits
= 0x3; break;
20978 inst
.instruction
|= alignbits
<< 4;
20982 case 1: /* VLD2 / VST2. */
20983 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20984 16, 32, 32, 64, -1);
20985 if (align_good
== FAIL
)
20988 inst
.instruction
|= 1 << 4;
20991 case 2: /* VLD3 / VST3. */
20992 constraint (inst
.operands
[1].immisalign
,
20993 _("can't use alignment with this instruction"));
20996 case 3: /* VLD4 / VST4. */
20997 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20998 16, 64, 32, 64, 32, 128, -1);
20999 if (align_good
== FAIL
)
21003 unsigned alignbits
= 0;
21006 case 8: alignbits
= 0x1; break;
21007 case 16: alignbits
= 0x1; break;
21008 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21011 inst
.instruction
|= alignbits
<< 4;
21018 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21019 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21020 inst
.instruction
|= 1 << (4 + logsize
);
21022 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21023 inst
.instruction
|= logsize
<< 10;
21026 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21029 do_neon_ld_dup (void)
21031 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21032 int align_good
, do_alignment
= 0;
21034 if (et
.type
== NT_invtype
)
21037 switch ((inst
.instruction
>> 8) & 3)
21039 case 0: /* VLD1. */
21040 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21041 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21042 &do_alignment
, 16, 16, 32, 32, -1);
21043 if (align_good
== FAIL
)
21045 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21048 case 2: inst
.instruction
|= 1 << 5; break;
21049 default: first_error (_("bad list length")); return;
21051 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21054 case 1: /* VLD2. */
21055 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21056 &do_alignment
, 8, 16, 16, 32, 32, 64,
21058 if (align_good
== FAIL
)
21060 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21061 _("bad list length"));
21062 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21063 inst
.instruction
|= 1 << 5;
21064 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21067 case 2: /* VLD3. */
21068 constraint (inst
.operands
[1].immisalign
,
21069 _("can't use alignment with this instruction"));
21070 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21071 _("bad list length"));
21072 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21073 inst
.instruction
|= 1 << 5;
21074 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21077 case 3: /* VLD4. */
21079 int align
= inst
.operands
[1].imm
>> 8;
21080 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21081 16, 64, 32, 64, 32, 128, -1);
21082 if (align_good
== FAIL
)
21084 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21085 _("bad list length"));
21086 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21087 inst
.instruction
|= 1 << 5;
21088 if (et
.size
== 32 && align
== 128)
21089 inst
.instruction
|= 0x3 << 6;
21091 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21098 inst
.instruction
|= do_alignment
<< 4;
21101 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21102 apart from bits [11:4]. */
21105 do_neon_ldx_stx (void)
21107 if (inst
.operands
[1].isreg
)
21108 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21110 switch (NEON_LANE (inst
.operands
[0].imm
))
21112 case NEON_INTERLEAVE_LANES
:
21113 NEON_ENCODE (INTERLV
, inst
);
21114 do_neon_ld_st_interleave ();
21117 case NEON_ALL_LANES
:
21118 NEON_ENCODE (DUP
, inst
);
21119 if (inst
.instruction
== N_INV
)
21121 first_error ("only loads support such operands");
21128 NEON_ENCODE (LANE
, inst
);
21129 do_neon_ld_st_lane ();
21132 /* L bit comes from bit mask. */
21133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21135 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21137 if (inst
.operands
[1].postind
)
21139 int postreg
= inst
.operands
[1].imm
& 0xf;
21140 constraint (!inst
.operands
[1].immisreg
,
21141 _("post-index must be a register"));
21142 constraint (postreg
== 0xd || postreg
== 0xf,
21143 _("bad register for post-index"));
21144 inst
.instruction
|= postreg
;
21148 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21149 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21150 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21153 if (inst
.operands
[1].writeback
)
21155 inst
.instruction
|= 0xd;
21158 inst
.instruction
|= 0xf;
21162 inst
.instruction
|= 0xf9000000;
21164 inst
.instruction
|= 0xf4000000;
21169 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21171 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21172 D register operands. */
21173 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21174 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21177 NEON_ENCODE (FPV8
, inst
);
21179 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21181 do_vfp_sp_dyadic ();
21183 /* ARMv8.2 fp16 instruction. */
21185 do_scalar_fp16_v82_encode ();
21188 do_vfp_dp_rd_rn_rm ();
21191 inst
.instruction
|= 0x100;
21193 inst
.instruction
|= 0xf0000000;
21199 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21201 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21202 first_error (_("invalid instruction shape"));
21208 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21209 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21211 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21214 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21217 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21221 do_vrint_1 (enum neon_cvt_mode mode
)
21223 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21224 struct neon_type_el et
;
21229 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21230 D register operands. */
21231 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21235 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21237 if (et
.type
!= NT_invtype
)
21239 /* VFP encodings. */
21240 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21241 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21242 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21244 NEON_ENCODE (FPV8
, inst
);
21245 if (rs
== NS_FF
|| rs
== NS_HH
)
21246 do_vfp_sp_monadic ();
21248 do_vfp_dp_rd_rm ();
21252 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21253 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21254 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21255 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21256 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21257 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21258 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21262 inst
.instruction
|= (rs
== NS_DD
) << 8;
21263 do_vfp_cond_or_thumb ();
21265 /* ARMv8.2 fp16 vrint instruction. */
21267 do_scalar_fp16_v82_encode ();
21271 /* Neon encodings (or something broken...). */
21273 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21275 if (et
.type
== NT_invtype
)
21278 if (!check_simd_pred_availability (TRUE
,
21279 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21282 NEON_ENCODE (FLOAT
, inst
);
21284 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21285 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21286 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21287 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21288 inst
.instruction
|= neon_quad (rs
) << 6;
21289 /* Mask off the original size bits and reencode them. */
21290 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21291 | neon_logbits (et
.size
) << 18);
21295 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21296 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21297 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21298 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21299 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21300 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21301 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21306 inst
.instruction
|= 0xfc000000;
21308 inst
.instruction
|= 0xf0000000;
21315 do_vrint_1 (neon_cvt_mode_x
);
21321 do_vrint_1 (neon_cvt_mode_z
);
21327 do_vrint_1 (neon_cvt_mode_r
);
21333 do_vrint_1 (neon_cvt_mode_a
);
21339 do_vrint_1 (neon_cvt_mode_n
);
21345 do_vrint_1 (neon_cvt_mode_p
);
21351 do_vrint_1 (neon_cvt_mode_m
);
21355 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21357 unsigned regno
= NEON_SCALAR_REG (opnd
);
21358 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21360 if (elsize
== 16 && elno
< 2 && regno
< 16)
21361 return regno
| (elno
<< 4);
21362 else if (elsize
== 32 && elno
== 0)
21365 first_error (_("scalar out of range"));
21372 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21373 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21374 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21375 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21376 _("expression too complex"));
21377 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21378 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21379 _("immediate out of range"));
21382 if (!check_simd_pred_availability (TRUE
,
21383 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21386 if (inst
.operands
[2].isscalar
)
21388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21389 first_error (_("invalid instruction shape"));
21390 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21391 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21392 N_KEY
| N_F16
| N_F32
).size
;
21393 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21395 inst
.instruction
= 0xfe000800;
21396 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21397 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21398 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21399 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21400 inst
.instruction
|= LOW4 (m
);
21401 inst
.instruction
|= HI1 (m
) << 5;
21402 inst
.instruction
|= neon_quad (rs
) << 6;
21403 inst
.instruction
|= rot
<< 20;
21404 inst
.instruction
|= (size
== 32) << 23;
21408 enum neon_shape rs
;
21409 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21410 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21412 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21414 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21415 N_KEY
| N_F16
| N_F32
).size
;
21416 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21417 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21418 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21419 as_tsktsk (BAD_MVE_SRCDEST
);
21421 neon_three_same (neon_quad (rs
), 0, -1);
21422 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21423 inst
.instruction
|= 0xfc200800;
21424 inst
.instruction
|= rot
<< 23;
21425 inst
.instruction
|= (size
== 32) << 20;
21432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21433 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21434 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21435 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21436 _("expression too complex"));
21438 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21439 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21440 enum neon_shape rs
;
21441 struct neon_type_el et
;
21442 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21444 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21445 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21449 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21450 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21452 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21453 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21454 "operand makes instruction UNPREDICTABLE"));
21457 if (et
.type
== NT_invtype
)
21460 if (!check_simd_pred_availability (et
.type
== NT_float
,
21461 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21464 if (et
.type
== NT_float
)
21466 neon_three_same (neon_quad (rs
), 0, -1);
21467 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21468 inst
.instruction
|= 0xfc800800;
21469 inst
.instruction
|= (rot
== 270) << 24;
21470 inst
.instruction
|= (et
.size
== 32) << 20;
21474 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21475 inst
.instruction
= 0xfe000f00;
21476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21477 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21478 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21479 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21480 inst
.instruction
|= (rot
== 270) << 12;
21481 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21482 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21483 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21488 /* Dot Product instructions encoding support. */
21491 do_neon_dotproduct (int unsigned_p
)
21493 enum neon_shape rs
;
21494 unsigned scalar_oprd2
= 0;
21497 if (inst
.cond
!= COND_ALWAYS
)
21498 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21499 "is UNPREDICTABLE"));
21501 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21504 /* Dot Product instructions are in three-same D/Q register format or the third
21505 operand can be a scalar index register. */
21506 if (inst
.operands
[2].isscalar
)
21508 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21509 high8
= 0xfe000000;
21510 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21514 high8
= 0xfc000000;
21515 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21519 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21521 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21523 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21524 Product instruction, so we pass 0 as the "ubit" parameter. And the
21525 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21526 neon_three_same (neon_quad (rs
), 0, 32);
21528 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21529 different NEON three-same encoding. */
21530 inst
.instruction
&= 0x00ffffff;
21531 inst
.instruction
|= high8
;
21532 /* Encode 'U' bit which indicates signedness. */
21533 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21534 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21535 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21536 the instruction encoding. */
21537 if (inst
.operands
[2].isscalar
)
21539 inst
.instruction
&= 0xffffffd0;
21540 inst
.instruction
|= LOW4 (scalar_oprd2
);
21541 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21545 /* Dot Product instructions for signed integer. */
21548 do_neon_dotproduct_s (void)
21550 return do_neon_dotproduct (0);
21553 /* Dot Product instructions for unsigned integer. */
21556 do_neon_dotproduct_u (void)
21558 return do_neon_dotproduct (1);
21564 enum neon_shape rs
;
21565 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21566 if (inst
.operands
[2].isscalar
)
21568 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21569 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21571 inst
.instruction
|= (1 << 25);
21572 int index
= inst
.operands
[2].reg
& 0xf;
21573 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21574 inst
.operands
[2].reg
>>= 4;
21575 constraint (!(inst
.operands
[2].reg
< 16),
21576 _("indexed register must be less than 16"));
21577 neon_three_args (rs
== NS_QQS
);
21578 inst
.instruction
|= (index
<< 5);
21582 inst
.instruction
|= (1 << 21);
21583 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21584 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21585 neon_three_args (rs
== NS_QQQ
);
21592 enum neon_shape rs
;
21593 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21594 if (inst
.operands
[2].isscalar
)
21596 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21597 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21599 inst
.instruction
|= (1 << 25);
21600 int index
= inst
.operands
[2].reg
& 0xf;
21601 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21602 inst
.operands
[2].reg
>>= 4;
21603 constraint (!(inst
.operands
[2].reg
< 16),
21604 _("indexed register must be less than 16"));
21605 neon_three_args (rs
== NS_QQS
);
21606 inst
.instruction
|= (index
<< 5);
21613 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21614 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21616 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21618 neon_three_args (1);
21625 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21626 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21628 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21630 neon_three_args (1);
21635 check_cde_operand (size_t index
, int is_dual
)
21637 unsigned Rx
= inst
.operands
[index
].reg
;
21638 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21639 if (is_dual
== 0 && thumb_mode
)
21641 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21642 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21644 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21645 _("Register must be an even register between r0-r10."));
21649 cde_coproc_enabled (unsigned coproc
)
21653 case 0: return mark_feature_used (&arm_ext_cde0
);
21654 case 1: return mark_feature_used (&arm_ext_cde1
);
21655 case 2: return mark_feature_used (&arm_ext_cde2
);
21656 case 3: return mark_feature_used (&arm_ext_cde3
);
21657 case 4: return mark_feature_used (&arm_ext_cde4
);
21658 case 5: return mark_feature_used (&arm_ext_cde5
);
21659 case 6: return mark_feature_used (&arm_ext_cde6
);
21660 case 7: return mark_feature_used (&arm_ext_cde7
);
21661 default: return FALSE
;
21665 #define cde_coproc_pos 8
21667 cde_handle_coproc (void)
21669 unsigned coproc
= inst
.operands
[0].reg
;
21670 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21671 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21672 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21674 #undef cde_coproc_pos
21677 cxn_handle_predication (bfd_boolean is_accum
)
21679 if (is_accum
&& conditional_insn ())
21680 set_pred_insn_type (INSIDE_IT_INSN
);
21681 else if (conditional_insn ())
21682 /* conditional_insn essentially checks for a suffix, not whether the
21683 instruction is inside an IT block or not.
21684 The non-accumulator versions should not have suffixes. */
21685 inst
.error
= BAD_SYNTAX
;
21687 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21691 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21694 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21698 Rd
= inst
.operands
[1].reg
;
21699 check_cde_operand (1, is_dual
);
21703 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21704 _("cx1d requires consecutive destination registers."));
21705 imm
= inst
.operands
[3].imm
;
21707 else if (is_dual
== 0)
21708 imm
= inst
.operands
[2].imm
;
21712 inst
.instruction
|= Rd
<< 12;
21713 inst
.instruction
|= (imm
& 0x1F80) << 9;
21714 inst
.instruction
|= (imm
& 0x0040) << 1;
21715 inst
.instruction
|= (imm
& 0x003f);
21717 cde_handle_coproc ();
21718 cxn_handle_predication (is_accum
);
21722 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21725 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21727 unsigned imm
, Rd
, Rn
;
21729 Rd
= inst
.operands
[1].reg
;
21733 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21734 _("cx2d requires consecutive destination registers."));
21735 imm
= inst
.operands
[4].imm
;
21736 Rn
= inst
.operands
[3].reg
;
21738 else if (is_dual
== 0)
21740 imm
= inst
.operands
[3].imm
;
21741 Rn
= inst
.operands
[2].reg
;
21746 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21747 check_cde_operand (1, is_dual
);
21749 inst
.instruction
|= Rd
<< 12;
21750 inst
.instruction
|= Rn
<< 16;
21752 inst
.instruction
|= (imm
& 0x0380) << 13;
21753 inst
.instruction
|= (imm
& 0x0040) << 1;
21754 inst
.instruction
|= (imm
& 0x003f);
21756 cde_handle_coproc ();
21757 cxn_handle_predication (is_accum
);
21761 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21764 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21766 unsigned imm
, Rd
, Rn
, Rm
;
21768 Rd
= inst
.operands
[1].reg
;
21772 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21773 _("cx3d requires consecutive destination registers."));
21774 imm
= inst
.operands
[5].imm
;
21775 Rn
= inst
.operands
[3].reg
;
21776 Rm
= inst
.operands
[4].reg
;
21778 else if (is_dual
== 0)
21780 imm
= inst
.operands
[4].imm
;
21781 Rn
= inst
.operands
[2].reg
;
21782 Rm
= inst
.operands
[3].reg
;
21787 check_cde_operand (1, is_dual
);
21788 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21789 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21791 inst
.instruction
|= Rd
;
21792 inst
.instruction
|= Rn
<< 16;
21793 inst
.instruction
|= Rm
<< 12;
21795 inst
.instruction
|= (imm
& 0x0038) << 17;
21796 inst
.instruction
|= (imm
& 0x0004) << 5;
21797 inst
.instruction
|= (imm
& 0x0003) << 4;
21799 cde_handle_coproc ();
21800 cxn_handle_predication (is_accum
);
21806 return do_custom_instruction_1 (0, 0);
21812 return do_custom_instruction_1 (0, 1);
21818 return do_custom_instruction_1 (1, 0);
21824 return do_custom_instruction_1 (1, 1);
21830 return do_custom_instruction_2 (0, 0);
21836 return do_custom_instruction_2 (0, 1);
21842 return do_custom_instruction_2 (1, 0);
21848 return do_custom_instruction_2 (1, 1);
21854 return do_custom_instruction_3 (0, 0);
21860 return do_custom_instruction_3 (0, 1);
21866 return do_custom_instruction_3 (1, 0);
21872 return do_custom_instruction_3 (1, 1);
21876 vcx_assign_vec_d (unsigned regnum
)
21878 inst
.instruction
|= HI4 (regnum
) << 12;
21879 inst
.instruction
|= LOW1 (regnum
) << 22;
21883 vcx_assign_vec_m (unsigned regnum
)
21885 inst
.instruction
|= HI4 (regnum
);
21886 inst
.instruction
|= LOW1 (regnum
) << 5;
21890 vcx_assign_vec_n (unsigned regnum
)
21892 inst
.instruction
|= HI4 (regnum
) << 16;
21893 inst
.instruction
|= LOW1 (regnum
) << 7;
21896 enum vcx_reg_type
{
21902 static enum vcx_reg_type
21903 vcx_get_reg_type (enum neon_shape ns
)
21905 gas_assert (ns
== NS_PQI
21913 || ns
== NS_PFFFI
);
21914 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21916 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21921 #define vcx_size_pos 24
21922 #define vcx_vec_pos 6
21924 vcx_handle_shape (enum vcx_reg_type reg_type
)
21927 if (reg_type
== q_reg
)
21928 inst
.instruction
|= 1 << vcx_vec_pos
;
21929 else if (reg_type
== d_reg
)
21930 inst
.instruction
|= 1 << vcx_size_pos
;
21934 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21935 bits (or equivalent for N and M registers).
21936 Similarly the D registers are encoded as N in D:Vd bits.
21937 While the S registers are encoded as N in the Vd:D bits.
21939 Taking into account the maximum values of these registers we can see a
21940 nicer pattern for calculation:
21941 Q -> 7, D -> 15, S -> 31
21943 If we say that everything is encoded in the Vd:D bits, then we can say
21944 that Q is encoded as 4*N, and D is encoded as 2*N.
21945 This way the bits will end up the same, and calculation is simpler.
21946 (calculation is now:
21947 1. Multiply by a number determined by the register letter.
21948 2. Encode resulting number in Vd:D bits.)
21950 This is made a little more complicated by automatic handling of 'Q'
21951 registers elsewhere, which means the register number is already 2*N where
21952 N is the number the user wrote after the register letter.
21957 #undef vcx_size_pos
21960 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21962 if (reg_type
== q_reg
)
21964 gas_assert (R
% 2 == 0);
21965 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21967 else if (reg_type
== d_reg
)
21968 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21970 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21973 static void (*vcx_assign_vec
[3]) (unsigned) = {
21980 vcx_handle_register_arguments (unsigned num_registers
,
21981 enum vcx_reg_type reg_type
)
21984 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21985 for (i
= 0; i
< num_registers
; i
++)
21987 R
= inst
.operands
[i
+1].reg
;
21988 vcx_ensure_register_in_range (R
, reg_type
);
21989 if (num_registers
== 3 && i
> 0)
21992 vcx_assign_vec
[1] (R
* reg_mult
);
21994 vcx_assign_vec
[2] (R
* reg_mult
);
21997 vcx_assign_vec
[i
](R
* reg_mult
);
22002 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22004 if (reg_type
== q_reg
)
22005 if (inst
.cond
> COND_ALWAYS
)
22006 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22008 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22009 else if (inst
.cond
== COND_ALWAYS
)
22010 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22012 inst
.error
= BAD_NOT_IT
;
22016 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22018 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22019 cde_handle_coproc ();
22020 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22021 vcx_handle_register_arguments (num_args
, reg_type
);
22022 vcx_handle_insn_block (reg_type
);
22023 if (reg_type
== q_reg
)
22024 constraint (!mark_feature_used (&mve_ext
),
22025 _("vcx instructions with Q registers require MVE"));
22027 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22028 && mark_feature_used (&armv8m_fp
))
22029 && !mark_feature_used (&mve_ext
),
22030 _("vcx instructions with S or D registers require either MVE"
22031 " or Armv8-M floating point extension."));
22037 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22038 vcx_handle_common_checks (1, rs
);
22040 unsigned imm
= inst
.operands
[2].imm
;
22041 inst
.instruction
|= (imm
& 0x03f);
22042 inst
.instruction
|= (imm
& 0x040) << 1;
22043 inst
.instruction
|= (imm
& 0x780) << 9;
22045 constraint (imm
>= 2048,
22046 _("vcx1 with S or D registers takes immediate within 0-2047"));
22047 inst
.instruction
|= (imm
& 0x800) << 13;
22053 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22054 vcx_handle_common_checks (2, rs
);
22056 unsigned imm
= inst
.operands
[3].imm
;
22057 inst
.instruction
|= (imm
& 0x01) << 4;
22058 inst
.instruction
|= (imm
& 0x02) << 6;
22059 inst
.instruction
|= (imm
& 0x3c) << 14;
22061 constraint (imm
>= 64,
22062 _("vcx2 with S or D registers takes immediate within 0-63"));
22063 inst
.instruction
|= (imm
& 0x40) << 18;
22069 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22070 vcx_handle_common_checks (3, rs
);
22072 unsigned imm
= inst
.operands
[4].imm
;
22073 inst
.instruction
|= (imm
& 0x1) << 4;
22074 inst
.instruction
|= (imm
& 0x6) << 19;
22075 if (rs
!= NS_PQQQI
)
22076 constraint (imm
>= 8,
22077 _("vcx2 with S or D registers takes immediate within 0-7"));
22078 inst
.instruction
|= (imm
& 0x8) << 21;
22081 /* Crypto v1 instructions. */
22083 do_crypto_2op_1 (unsigned elttype
, int op
)
22085 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22087 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22093 NEON_ENCODE (INTEGER
, inst
);
22094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22095 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22096 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22097 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22099 inst
.instruction
|= op
<< 6;
22102 inst
.instruction
|= 0xfc000000;
22104 inst
.instruction
|= 0xf0000000;
22108 do_crypto_3op_1 (int u
, int op
)
22110 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22112 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22113 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22118 NEON_ENCODE (INTEGER
, inst
);
22119 neon_three_same (1, u
, 8 << op
);
22125 do_crypto_2op_1 (N_8
, 0);
22131 do_crypto_2op_1 (N_8
, 1);
22137 do_crypto_2op_1 (N_8
, 2);
22143 do_crypto_2op_1 (N_8
, 3);
22149 do_crypto_3op_1 (0, 0);
22155 do_crypto_3op_1 (0, 1);
22161 do_crypto_3op_1 (0, 2);
22167 do_crypto_3op_1 (0, 3);
22173 do_crypto_3op_1 (1, 0);
22179 do_crypto_3op_1 (1, 1);
22183 do_sha256su1 (void)
22185 do_crypto_3op_1 (1, 2);
22191 do_crypto_2op_1 (N_32
, -1);
22197 do_crypto_2op_1 (N_32
, 0);
22201 do_sha256su0 (void)
22203 do_crypto_2op_1 (N_32
, 1);
22207 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22209 unsigned int Rd
= inst
.operands
[0].reg
;
22210 unsigned int Rn
= inst
.operands
[1].reg
;
22211 unsigned int Rm
= inst
.operands
[2].reg
;
22213 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22214 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22215 inst
.instruction
|= LOW4 (Rn
) << 16;
22216 inst
.instruction
|= LOW4 (Rm
);
22217 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22218 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22220 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22221 as_warn (UNPRED_REG ("r15"));
22263 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22265 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22266 do_vfp_sp_dp_cvt ();
22267 do_vfp_cond_or_thumb ();
22273 enum neon_shape rs
;
22274 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22275 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22276 if (inst
.operands
[2].isscalar
)
22278 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22279 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22281 inst
.instruction
|= (1 << 25);
22282 int index
= inst
.operands
[2].reg
& 0xf;
22283 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22284 inst
.operands
[2].reg
>>= 4;
22285 constraint (!(inst
.operands
[2].reg
< 16),
22286 _("indexed register must be less than 16"));
22287 neon_three_args (rs
== NS_QQS
);
22288 inst
.instruction
|= (index
<< 5);
22292 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22293 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22294 neon_three_args (rs
== NS_QQQ
);
22301 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22302 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22304 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22305 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22307 neon_three_args (1);
22311 /* Overall per-instruction processing. */
22313 /* We need to be able to fix up arbitrary expressions in some statements.
22314 This is so that we can handle symbols that are an arbitrary distance from
22315 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22316 which returns part of an address in a form which will be valid for
22317 a data instruction. We do this by pushing the expression into a symbol
22318 in the expr_section, and creating a fix for that. */
22321 fix_new_arm (fragS
* frag
,
22335 /* Create an absolute valued symbol, so we have something to
22336 refer to in the object file. Unfortunately for us, gas's
22337 generic expression parsing will already have folded out
22338 any use of .set foo/.type foo %function that may have
22339 been used to set type information of the target location,
22340 that's being specified symbolically. We have to presume
22341 the user knows what they are doing. */
22345 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22347 symbol
= symbol_find_or_make (name
);
22348 S_SET_SEGMENT (symbol
, absolute_section
);
22349 symbol_set_frag (symbol
, &zero_address_frag
);
22350 S_SET_VALUE (symbol
, exp
->X_add_number
);
22351 exp
->X_op
= O_symbol
;
22352 exp
->X_add_symbol
= symbol
;
22353 exp
->X_add_number
= 0;
22359 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22360 (enum bfd_reloc_code_real
) reloc
);
22364 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22365 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22369 /* Mark whether the fix is to a THUMB instruction, or an ARM
22371 new_fix
->tc_fix_data
= thumb_mode
;
22374 /* Create a frg for an instruction requiring relaxation. */
22376 output_relax_insn (void)
22382 /* The size of the instruction is unknown, so tie the debug info to the
22383 start of the instruction. */
22384 dwarf2_emit_insn (0);
22386 switch (inst
.relocs
[0].exp
.X_op
)
22389 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22390 offset
= inst
.relocs
[0].exp
.X_add_number
;
22394 offset
= inst
.relocs
[0].exp
.X_add_number
;
22397 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22401 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22402 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22403 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22406 /* Write a 32-bit thumb instruction to buf. */
22408 put_thumb32_insn (char * buf
, unsigned long insn
)
22410 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22411 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22415 output_inst (const char * str
)
22421 as_bad ("%s -- `%s'", inst
.error
, str
);
22426 output_relax_insn ();
22429 if (inst
.size
== 0)
22432 to
= frag_more (inst
.size
);
22433 /* PR 9814: Record the thumb mode into the current frag so that we know
22434 what type of NOP padding to use, if necessary. We override any previous
22435 setting so that if the mode has changed then the NOPS that we use will
22436 match the encoding of the last instruction in the frag. */
22437 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22439 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22441 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22442 put_thumb32_insn (to
, inst
.instruction
);
22444 else if (inst
.size
> INSN_SIZE
)
22446 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22447 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22448 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22451 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22454 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22456 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22457 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22458 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22459 inst
.relocs
[r
].type
);
22462 dwarf2_emit_insn (inst
.size
);
22466 output_it_inst (int cond
, int mask
, char * to
)
22468 unsigned long instruction
= 0xbf00;
22471 instruction
|= mask
;
22472 instruction
|= cond
<< 4;
22476 to
= frag_more (2);
22478 dwarf2_emit_insn (2);
22482 md_number_to_chars (to
, instruction
, 2);
22487 /* Tag values used in struct asm_opcode's tag field. */
22490 OT_unconditional
, /* Instruction cannot be conditionalized.
22491 The ARM condition field is still 0xE. */
22492 OT_unconditionalF
, /* Instruction cannot be conditionalized
22493 and carries 0xF in its ARM condition field. */
22494 OT_csuffix
, /* Instruction takes a conditional suffix. */
22495 OT_csuffixF
, /* Some forms of the instruction take a scalar
22496 conditional suffix, others place 0xF where the
22497 condition field would be, others take a vector
22498 conditional suffix. */
22499 OT_cinfix3
, /* Instruction takes a conditional infix,
22500 beginning at character index 3. (In
22501 unified mode, it becomes a suffix.) */
22502 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22503 tsts, cmps, cmns, and teqs. */
22504 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22505 character index 3, even in unified mode. Used for
22506 legacy instructions where suffix and infix forms
22507 may be ambiguous. */
22508 OT_csuf_or_in3
, /* Instruction takes either a conditional
22509 suffix or an infix at character index 3. */
22510 OT_odd_infix_unc
, /* This is the unconditional variant of an
22511 instruction that takes a conditional infix
22512 at an unusual position. In unified mode,
22513 this variant will accept a suffix. */
22514 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22515 are the conditional variants of instructions that
22516 take conditional infixes in unusual positions.
22517 The infix appears at character index
22518 (tag - OT_odd_infix_0). These are not accepted
22519 in unified mode. */
22522 /* Subroutine of md_assemble, responsible for looking up the primary
22523 opcode from the mnemonic the user wrote. STR points to the
22524 beginning of the mnemonic.
22526 This is not simply a hash table lookup, because of conditional
22527 variants. Most instructions have conditional variants, which are
22528 expressed with a _conditional affix_ to the mnemonic. If we were
22529 to encode each conditional variant as a literal string in the opcode
22530 table, it would have approximately 20,000 entries.
22532 Most mnemonics take this affix as a suffix, and in unified syntax,
22533 'most' is upgraded to 'all'. However, in the divided syntax, some
22534 instructions take the affix as an infix, notably the s-variants of
22535 the arithmetic instructions. Of those instructions, all but six
22536 have the infix appear after the third character of the mnemonic.
22538 Accordingly, the algorithm for looking up primary opcodes given
22541 1. Look up the identifier in the opcode table.
22542 If we find a match, go to step U.
22544 2. Look up the last two characters of the identifier in the
22545 conditions table. If we find a match, look up the first N-2
22546 characters of the identifier in the opcode table. If we
22547 find a match, go to step CE.
22549 3. Look up the fourth and fifth characters of the identifier in
22550 the conditions table. If we find a match, extract those
22551 characters from the identifier, and look up the remaining
22552 characters in the opcode table. If we find a match, go
22557 U. Examine the tag field of the opcode structure, in case this is
22558 one of the six instructions with its conditional infix in an
22559 unusual place. If it is, the tag tells us where to find the
22560 infix; look it up in the conditions table and set inst.cond
22561 accordingly. Otherwise, this is an unconditional instruction.
22562 Again set inst.cond accordingly. Return the opcode structure.
22564 CE. Examine the tag field to make sure this is an instruction that
22565 should receive a conditional suffix. If it is not, fail.
22566 Otherwise, set inst.cond from the suffix we already looked up,
22567 and return the opcode structure.
22569 CM. Examine the tag field to make sure this is an instruction that
22570 should receive a conditional infix after the third character.
22571 If it is not, fail. Otherwise, undo the edits to the current
22572 line of input and proceed as for case CE. */
22574 static const struct asm_opcode
*
22575 opcode_lookup (char **str
)
22579 const struct asm_opcode
*opcode
;
22580 const struct asm_cond
*cond
;
22583 /* Scan up to the end of the mnemonic, which must end in white space,
22584 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22585 for (base
= end
= *str
; *end
!= '\0'; end
++)
22586 if (*end
== ' ' || *end
== '.')
22592 /* Handle a possible width suffix and/or Neon type suffix. */
22597 /* The .w and .n suffixes are only valid if the unified syntax is in
22599 if (unified_syntax
&& end
[1] == 'w')
22601 else if (unified_syntax
&& end
[1] == 'n')
22606 inst
.vectype
.elems
= 0;
22608 *str
= end
+ offset
;
22610 if (end
[offset
] == '.')
22612 /* See if we have a Neon type suffix (possible in either unified or
22613 non-unified ARM syntax mode). */
22614 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22617 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22623 /* Look for unaffixed or special-case affixed mnemonic. */
22624 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22630 if (opcode
->tag
< OT_odd_infix_0
)
22632 inst
.cond
= COND_ALWAYS
;
22636 if (warn_on_deprecated
&& unified_syntax
)
22637 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22638 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22639 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22642 inst
.cond
= cond
->value
;
22645 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22647 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22649 if (end
- base
< 2)
22652 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22653 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22655 /* If this opcode can not be vector predicated then don't accept it with a
22656 vector predication code. */
22657 if (opcode
&& !opcode
->mayBeVecPred
)
22660 if (!opcode
|| !cond
)
22662 /* Cannot have a conditional suffix on a mnemonic of less than two
22664 if (end
- base
< 3)
22667 /* Look for suffixed mnemonic. */
22669 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22670 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22674 if (opcode
&& cond
)
22677 switch (opcode
->tag
)
22679 case OT_cinfix3_legacy
:
22680 /* Ignore conditional suffixes matched on infix only mnemonics. */
22684 case OT_cinfix3_deprecated
:
22685 case OT_odd_infix_unc
:
22686 if (!unified_syntax
)
22688 /* Fall through. */
22692 case OT_csuf_or_in3
:
22693 inst
.cond
= cond
->value
;
22696 case OT_unconditional
:
22697 case OT_unconditionalF
:
22699 inst
.cond
= cond
->value
;
22702 /* Delayed diagnostic. */
22703 inst
.error
= BAD_COND
;
22704 inst
.cond
= COND_ALWAYS
;
22713 /* Cannot have a usual-position infix on a mnemonic of less than
22714 six characters (five would be a suffix). */
22715 if (end
- base
< 6)
22718 /* Look for infixed mnemonic in the usual position. */
22720 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22724 memcpy (save
, affix
, 2);
22725 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22726 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22728 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22729 memcpy (affix
, save
, 2);
22732 && (opcode
->tag
== OT_cinfix3
22733 || opcode
->tag
== OT_cinfix3_deprecated
22734 || opcode
->tag
== OT_csuf_or_in3
22735 || opcode
->tag
== OT_cinfix3_legacy
))
22738 if (warn_on_deprecated
&& unified_syntax
22739 && (opcode
->tag
== OT_cinfix3
22740 || opcode
->tag
== OT_cinfix3_deprecated
))
22741 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22743 inst
.cond
= cond
->value
;
22750 /* This function generates an initial IT instruction, leaving its block
22751 virtually open for the new instructions. Eventually,
22752 the mask will be updated by now_pred_add_mask () each time
22753 a new instruction needs to be included in the IT block.
22754 Finally, the block is closed with close_automatic_it_block ().
22755 The block closure can be requested either from md_assemble (),
22756 a tencode (), or due to a label hook. */
22759 new_automatic_it_block (int cond
)
22761 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22762 now_pred
.mask
= 0x18;
22763 now_pred
.cc
= cond
;
22764 now_pred
.block_length
= 1;
22765 mapping_state (MAP_THUMB
);
22766 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22767 now_pred
.warn_deprecated
= FALSE
;
22768 now_pred
.insn_cond
= TRUE
;
22771 /* Close an automatic IT block.
22772 See comments in new_automatic_it_block (). */
22775 close_automatic_it_block (void)
22777 now_pred
.mask
= 0x10;
22778 now_pred
.block_length
= 0;
22781 /* Update the mask of the current automatically-generated IT
22782 instruction. See comments in new_automatic_it_block (). */
22785 now_pred_add_mask (int cond
)
22787 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22788 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22789 | ((bitvalue) << (nbit)))
22790 const int resulting_bit
= (cond
& 1);
22792 now_pred
.mask
&= 0xf;
22793 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22795 (5 - now_pred
.block_length
));
22796 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22798 ((5 - now_pred
.block_length
) - 1));
22799 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22802 #undef SET_BIT_VALUE
22805 /* The IT blocks handling machinery is accessed through the these functions:
22806 it_fsm_pre_encode () from md_assemble ()
22807 set_pred_insn_type () optional, from the tencode functions
22808 set_pred_insn_type_last () ditto
22809 in_pred_block () ditto
22810 it_fsm_post_encode () from md_assemble ()
22811 force_automatic_it_block_close () from label handling functions
22814 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22815 initializing the IT insn type with a generic initial value depending
22816 on the inst.condition.
22817 2) During the tencode function, two things may happen:
22818 a) The tencode function overrides the IT insn type by
22819 calling either set_pred_insn_type (type) or
22820 set_pred_insn_type_last ().
22821 b) The tencode function queries the IT block state by
22822 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22824 Both set_pred_insn_type and in_pred_block run the internal FSM state
22825 handling function (handle_pred_state), because: a) setting the IT insn
22826 type may incur in an invalid state (exiting the function),
22827 and b) querying the state requires the FSM to be updated.
22828 Specifically we want to avoid creating an IT block for conditional
22829 branches, so it_fsm_pre_encode is actually a guess and we can't
22830 determine whether an IT block is required until the tencode () routine
22831 has decided what type of instruction this actually it.
22832 Because of this, if set_pred_insn_type and in_pred_block have to be
22833 used, set_pred_insn_type has to be called first.
22835 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22836 that determines the insn IT type depending on the inst.cond code.
22837 When a tencode () routine encodes an instruction that can be
22838 either outside an IT block, or, in the case of being inside, has to be
22839 the last one, set_pred_insn_type_last () will determine the proper
22840 IT instruction type based on the inst.cond code. Otherwise,
22841 set_pred_insn_type can be called for overriding that logic or
22842 for covering other cases.
22844 Calling handle_pred_state () may not transition the IT block state to
22845 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22846 still queried. Instead, if the FSM determines that the state should
22847 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22848 after the tencode () function: that's what it_fsm_post_encode () does.
22850 Since in_pred_block () calls the state handling function to get an
22851 updated state, an error may occur (due to invalid insns combination).
22852 In that case, inst.error is set.
22853 Therefore, inst.error has to be checked after the execution of
22854 the tencode () routine.
22856 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22857 any pending state change (if any) that didn't take place in
22858 handle_pred_state () as explained above. */
22861 it_fsm_pre_encode (void)
22863 if (inst
.cond
!= COND_ALWAYS
)
22864 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22866 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22868 now_pred
.state_handled
= 0;
22871 /* IT state FSM handling function. */
22872 /* MVE instructions and non-MVE instructions are handled differently because of
22873 the introduction of VPT blocks.
22874 Specifications say that any non-MVE instruction inside a VPT block is
22875 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22876 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22877 few exceptions we have MVE_UNPREDICABLE_INSN.
22878 The error messages provided depending on the different combinations possible
22879 are described in the cases below:
22880 For 'most' MVE instructions:
22881 1) In an IT block, with an IT code: syntax error
22882 2) In an IT block, with a VPT code: error: must be in a VPT block
22883 3) In an IT block, with no code: warning: UNPREDICTABLE
22884 4) In a VPT block, with an IT code: syntax error
22885 5) In a VPT block, with a VPT code: OK!
22886 6) In a VPT block, with no code: error: missing code
22887 7) Outside a pred block, with an IT code: error: syntax error
22888 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22889 9) Outside a pred block, with no code: OK!
22890 For non-MVE instructions:
22891 10) In an IT block, with an IT code: OK!
22892 11) In an IT block, with a VPT code: syntax error
22893 12) In an IT block, with no code: error: missing code
22894 13) In a VPT block, with an IT code: error: should be in an IT block
22895 14) In a VPT block, with a VPT code: syntax error
22896 15) In a VPT block, with no code: UNPREDICTABLE
22897 16) Outside a pred block, with an IT code: error: should be in an IT block
22898 17) Outside a pred block, with a VPT code: syntax error
22899 18) Outside a pred block, with no code: OK!
22904 handle_pred_state (void)
22906 now_pred
.state_handled
= 1;
22907 now_pred
.insn_cond
= FALSE
;
22909 switch (now_pred
.state
)
22911 case OUTSIDE_PRED_BLOCK
:
22912 switch (inst
.pred_insn_type
)
22914 case MVE_UNPREDICABLE_INSN
:
22915 case MVE_OUTSIDE_PRED_INSN
:
22916 if (inst
.cond
< COND_ALWAYS
)
22918 /* Case 7: Outside a pred block, with an IT code: error: syntax
22920 inst
.error
= BAD_SYNTAX
;
22923 /* Case 9: Outside a pred block, with no code: OK! */
22925 case OUTSIDE_PRED_INSN
:
22926 if (inst
.cond
> COND_ALWAYS
)
22928 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22930 inst
.error
= BAD_SYNTAX
;
22933 /* Case 18: Outside a pred block, with no code: OK! */
22936 case INSIDE_VPT_INSN
:
22937 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22939 inst
.error
= BAD_OUT_VPT
;
22942 case INSIDE_IT_INSN
:
22943 case INSIDE_IT_LAST_INSN
:
22944 if (inst
.cond
< COND_ALWAYS
)
22946 /* Case 16: Outside a pred block, with an IT code: error: should
22947 be in an IT block. */
22948 if (thumb_mode
== 0)
22951 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22952 as_tsktsk (_("Warning: conditional outside an IT block"\
22957 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22958 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22960 /* Automatically generate the IT instruction. */
22961 new_automatic_it_block (inst
.cond
);
22962 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22963 close_automatic_it_block ();
22967 inst
.error
= BAD_OUT_IT
;
22973 else if (inst
.cond
> COND_ALWAYS
)
22975 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22977 inst
.error
= BAD_SYNTAX
;
22982 case IF_INSIDE_IT_LAST_INSN
:
22983 case NEUTRAL_IT_INSN
:
22987 if (inst
.cond
!= COND_ALWAYS
)
22988 first_error (BAD_SYNTAX
);
22989 now_pred
.state
= MANUAL_PRED_BLOCK
;
22990 now_pred
.block_length
= 0;
22991 now_pred
.type
= VECTOR_PRED
;
22995 now_pred
.state
= MANUAL_PRED_BLOCK
;
22996 now_pred
.block_length
= 0;
22997 now_pred
.type
= SCALAR_PRED
;
23002 case AUTOMATIC_PRED_BLOCK
:
23003 /* Three things may happen now:
23004 a) We should increment current it block size;
23005 b) We should close current it block (closing insn or 4 insns);
23006 c) We should close current it block and start a new one (due
23007 to incompatible conditions or
23008 4 insns-length block reached). */
23010 switch (inst
.pred_insn_type
)
23012 case INSIDE_VPT_INSN
:
23014 case MVE_UNPREDICABLE_INSN
:
23015 case MVE_OUTSIDE_PRED_INSN
:
23017 case OUTSIDE_PRED_INSN
:
23018 /* The closure of the block shall happen immediately,
23019 so any in_pred_block () call reports the block as closed. */
23020 force_automatic_it_block_close ();
23023 case INSIDE_IT_INSN
:
23024 case INSIDE_IT_LAST_INSN
:
23025 case IF_INSIDE_IT_LAST_INSN
:
23026 now_pred
.block_length
++;
23028 if (now_pred
.block_length
> 4
23029 || !now_pred_compatible (inst
.cond
))
23031 force_automatic_it_block_close ();
23032 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23033 new_automatic_it_block (inst
.cond
);
23037 now_pred
.insn_cond
= TRUE
;
23038 now_pred_add_mask (inst
.cond
);
23041 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23042 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23043 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23044 close_automatic_it_block ();
23048 case NEUTRAL_IT_INSN
:
23049 now_pred
.block_length
++;
23050 now_pred
.insn_cond
= TRUE
;
23052 if (now_pred
.block_length
> 4)
23053 force_automatic_it_block_close ();
23055 now_pred_add_mask (now_pred
.cc
& 1);
23059 close_automatic_it_block ();
23060 now_pred
.state
= MANUAL_PRED_BLOCK
;
23065 case MANUAL_PRED_BLOCK
:
23069 if (now_pred
.type
== SCALAR_PRED
)
23071 /* Check conditional suffixes. */
23072 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23073 now_pred
.mask
<<= 1;
23074 now_pred
.mask
&= 0x1f;
23075 is_last
= (now_pred
.mask
== 0x10);
23079 now_pred
.cc
^= (now_pred
.mask
>> 4);
23080 cond
= now_pred
.cc
+ 0xf;
23081 now_pred
.mask
<<= 1;
23082 now_pred
.mask
&= 0x1f;
23083 is_last
= now_pred
.mask
== 0x10;
23085 now_pred
.insn_cond
= TRUE
;
23087 switch (inst
.pred_insn_type
)
23089 case OUTSIDE_PRED_INSN
:
23090 if (now_pred
.type
== SCALAR_PRED
)
23092 if (inst
.cond
== COND_ALWAYS
)
23094 /* Case 12: In an IT block, with no code: error: missing
23096 inst
.error
= BAD_NOT_IT
;
23099 else if (inst
.cond
> COND_ALWAYS
)
23101 /* Case 11: In an IT block, with a VPT code: syntax error.
23103 inst
.error
= BAD_SYNTAX
;
23106 else if (thumb_mode
)
23108 /* This is for some special cases where a non-MVE
23109 instruction is not allowed in an IT block, such as cbz,
23110 but are put into one with a condition code.
23111 You could argue this should be a syntax error, but we
23112 gave the 'not allowed in IT block' diagnostic in the
23113 past so we will keep doing so. */
23114 inst
.error
= BAD_NOT_IT
;
23121 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23122 as_tsktsk (MVE_NOT_VPT
);
23125 case MVE_OUTSIDE_PRED_INSN
:
23126 if (now_pred
.type
== SCALAR_PRED
)
23128 if (inst
.cond
== COND_ALWAYS
)
23130 /* Case 3: In an IT block, with no code: warning:
23132 as_tsktsk (MVE_NOT_IT
);
23135 else if (inst
.cond
< COND_ALWAYS
)
23137 /* Case 1: In an IT block, with an IT code: syntax error.
23139 inst
.error
= BAD_SYNTAX
;
23147 if (inst
.cond
< COND_ALWAYS
)
23149 /* Case 4: In a VPT block, with an IT code: syntax error.
23151 inst
.error
= BAD_SYNTAX
;
23154 else if (inst
.cond
== COND_ALWAYS
)
23156 /* Case 6: In a VPT block, with no code: error: missing
23158 inst
.error
= BAD_NOT_VPT
;
23166 case MVE_UNPREDICABLE_INSN
:
23167 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23169 case INSIDE_IT_INSN
:
23170 if (inst
.cond
> COND_ALWAYS
)
23172 /* Case 11: In an IT block, with a VPT code: syntax error. */
23173 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23174 inst
.error
= BAD_SYNTAX
;
23177 else if (now_pred
.type
== SCALAR_PRED
)
23179 /* Case 10: In an IT block, with an IT code: OK! */
23180 if (cond
!= inst
.cond
)
23182 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23189 /* Case 13: In a VPT block, with an IT code: error: should be
23191 inst
.error
= BAD_OUT_IT
;
23196 case INSIDE_VPT_INSN
:
23197 if (now_pred
.type
== SCALAR_PRED
)
23199 /* Case 2: In an IT block, with a VPT code: error: must be in a
23201 inst
.error
= BAD_OUT_VPT
;
23204 /* Case 5: In a VPT block, with a VPT code: OK! */
23205 else if (cond
!= inst
.cond
)
23207 inst
.error
= BAD_VPT_COND
;
23211 case INSIDE_IT_LAST_INSN
:
23212 case IF_INSIDE_IT_LAST_INSN
:
23213 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23215 /* Case 4: In a VPT block, with an IT code: syntax error. */
23216 /* Case 11: In an IT block, with a VPT code: syntax error. */
23217 inst
.error
= BAD_SYNTAX
;
23220 else if (cond
!= inst
.cond
)
23222 inst
.error
= BAD_IT_COND
;
23227 inst
.error
= BAD_BRANCH
;
23232 case NEUTRAL_IT_INSN
:
23233 /* The BKPT instruction is unconditional even in a IT or VPT
23238 if (now_pred
.type
== SCALAR_PRED
)
23240 inst
.error
= BAD_IT_IT
;
23243 /* fall through. */
23245 if (inst
.cond
== COND_ALWAYS
)
23247 /* Executing a VPT/VPST instruction inside an IT block or a
23248 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23250 if (now_pred
.type
== SCALAR_PRED
)
23251 as_tsktsk (MVE_NOT_IT
);
23253 as_tsktsk (MVE_NOT_VPT
);
23258 /* VPT/VPST do not accept condition codes. */
23259 inst
.error
= BAD_SYNTAX
;
23270 struct depr_insn_mask
23272 unsigned long pattern
;
23273 unsigned long mask
;
23274 const char* description
;
23277 /* List of 16-bit instruction patterns deprecated in an IT block in
23279 static const struct depr_insn_mask depr_it_insns
[] = {
23280 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23281 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23282 { 0xa000, 0xb800, N_("ADR") },
23283 { 0x4800, 0xf800, N_("Literal loads") },
23284 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23285 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23286 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23287 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23288 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23293 it_fsm_post_encode (void)
23297 if (!now_pred
.state_handled
)
23298 handle_pred_state ();
23300 if (now_pred
.insn_cond
23301 && warn_on_restrict_it
23302 && !now_pred
.warn_deprecated
23303 && warn_on_deprecated
23304 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23305 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23306 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23308 if (inst
.instruction
>= 0x10000)
23310 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23311 "performance deprecated in ARMv8-A and ARMv8-R"));
23312 now_pred
.warn_deprecated
= TRUE
;
23316 const struct depr_insn_mask
*p
= depr_it_insns
;
23318 while (p
->mask
!= 0)
23320 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23322 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23323 "instructions of the following class are "
23324 "performance deprecated in ARMv8-A and "
23325 "ARMv8-R: %s"), p
->description
);
23326 now_pred
.warn_deprecated
= TRUE
;
23334 if (now_pred
.block_length
> 1)
23336 as_tsktsk (_("IT blocks containing more than one conditional "
23337 "instruction are performance deprecated in ARMv8-A and "
23339 now_pred
.warn_deprecated
= TRUE
;
23343 is_last
= (now_pred
.mask
== 0x10);
23346 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23352 force_automatic_it_block_close (void)
23354 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23356 close_automatic_it_block ();
23357 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23363 in_pred_block (void)
23365 if (!now_pred
.state_handled
)
23366 handle_pred_state ();
23368 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23371 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23372 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23373 here, hence the "known" in the function name. */
23376 known_t32_only_insn (const struct asm_opcode
*opcode
)
23378 /* Original Thumb-1 wide instruction. */
23379 if (opcode
->tencode
== do_t_blx
23380 || opcode
->tencode
== do_t_branch23
23381 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23382 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23385 /* Wide-only instruction added to ARMv8-M Baseline. */
23386 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23387 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23388 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23389 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23395 /* Whether wide instruction variant can be used if available for a valid OPCODE
23399 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23401 if (known_t32_only_insn (opcode
))
23404 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23405 of variant T3 of B.W is checked in do_t_branch. */
23406 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23407 && opcode
->tencode
== do_t_branch
)
23410 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23411 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23412 && opcode
->tencode
== do_t_mov_cmp
23413 /* Make sure CMP instruction is not affected. */
23414 && opcode
->aencode
== do_mov
)
23417 /* Wide instruction variants of all instructions with narrow *and* wide
23418 variants become available with ARMv6t2. Other opcodes are either
23419 narrow-only or wide-only and are thus available if OPCODE is valid. */
23420 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23423 /* OPCODE with narrow only instruction variant or wide variant not
23429 md_assemble (char *str
)
23432 const struct asm_opcode
* opcode
;
23434 /* Align the previous label if needed. */
23435 if (last_label_seen
!= NULL
)
23437 symbol_set_frag (last_label_seen
, frag_now
);
23438 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23439 S_SET_SEGMENT (last_label_seen
, now_seg
);
23442 memset (&inst
, '\0', sizeof (inst
));
23444 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23445 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23447 opcode
= opcode_lookup (&p
);
23450 /* It wasn't an instruction, but it might be a register alias of
23451 the form alias .req reg, or a Neon .dn/.qn directive. */
23452 if (! create_register_alias (str
, p
)
23453 && ! create_neon_reg_alias (str
, p
))
23454 as_bad (_("bad instruction `%s'"), str
);
23459 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23460 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23462 /* The value which unconditional instructions should have in place of the
23463 condition field. */
23464 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1u;
23468 arm_feature_set variant
;
23470 variant
= cpu_variant
;
23471 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23472 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23473 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23474 /* Check that this instruction is supported for this CPU. */
23475 if (!opcode
->tvariant
23476 || (thumb_mode
== 1
23477 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23479 if (opcode
->tencode
== do_t_swi
)
23480 as_bad (_("SVC is not permitted on this architecture"));
23482 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23485 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23486 && opcode
->tencode
!= do_t_branch
)
23488 as_bad (_("Thumb does not support conditional execution"));
23492 /* Two things are addressed here:
23493 1) Implicit require narrow instructions on Thumb-1.
23494 This avoids relaxation accidentally introducing Thumb-2
23496 2) Reject wide instructions in non Thumb-2 cores.
23498 Only instructions with narrow and wide variants need to be handled
23499 but selecting all non wide-only instructions is easier. */
23500 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23501 && !t32_insn_ok (variant
, opcode
))
23503 if (inst
.size_req
== 0)
23505 else if (inst
.size_req
== 4)
23507 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23508 as_bad (_("selected processor does not support 32bit wide "
23509 "variant of instruction `%s'"), str
);
23511 as_bad (_("selected processor does not support `%s' in "
23512 "Thumb-2 mode"), str
);
23517 inst
.instruction
= opcode
->tvalue
;
23519 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23521 /* Prepare the pred_insn_type for those encodings that don't set
23523 it_fsm_pre_encode ();
23525 opcode
->tencode ();
23527 it_fsm_post_encode ();
23530 if (!(inst
.error
|| inst
.relax
))
23532 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23533 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23534 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23536 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23541 /* Something has gone badly wrong if we try to relax a fixed size
23543 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23546 *opcode
->tvariant
);
23547 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23548 set those bits when Thumb-2 32-bit instructions are seen. The impact
23549 of relaxable instructions will be considered later after we finish all
23551 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23552 variant
= arm_arch_none
;
23554 variant
= cpu_variant
;
23555 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23556 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23559 check_neon_suffixes
;
23563 mapping_state (MAP_THUMB
);
23566 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23570 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23571 is_bx
= (opcode
->aencode
== do_bx
);
23573 /* Check that this instruction is supported for this CPU. */
23574 if (!(is_bx
&& fix_v4bx
)
23575 && !(opcode
->avariant
&&
23576 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23578 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23583 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23587 inst
.instruction
= opcode
->avalue
;
23588 if (opcode
->tag
== OT_unconditionalF
)
23589 inst
.instruction
|= 0xFU
<< 28;
23591 inst
.instruction
|= inst
.cond
<< 28;
23592 inst
.size
= INSN_SIZE
;
23593 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23595 it_fsm_pre_encode ();
23596 opcode
->aencode ();
23597 it_fsm_post_encode ();
23599 /* Arm mode bx is marked as both v4T and v5 because it's still required
23600 on a hypothetical non-thumb v5 core. */
23602 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23604 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23605 *opcode
->avariant
);
23607 check_neon_suffixes
;
23611 mapping_state (MAP_ARM
);
23616 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23624 check_pred_blocks_finished (void)
23629 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23630 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23631 == MANUAL_PRED_BLOCK
)
23633 if (now_pred
.type
== SCALAR_PRED
)
23634 as_warn (_("section '%s' finished with an open IT block."),
23637 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23641 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23643 if (now_pred
.type
== SCALAR_PRED
)
23644 as_warn (_("file finished with an open IT block."));
23646 as_warn (_("file finished with an open VPT/VPST block."));
23651 /* Various frobbings of labels and their addresses. */
23654 arm_start_line_hook (void)
23656 last_label_seen
= NULL
;
23660 arm_frob_label (symbolS
* sym
)
23662 last_label_seen
= sym
;
23664 ARM_SET_THUMB (sym
, thumb_mode
);
23666 #if defined OBJ_COFF || defined OBJ_ELF
23667 ARM_SET_INTERWORK (sym
, support_interwork
);
23670 force_automatic_it_block_close ();
23672 /* Note - do not allow local symbols (.Lxxx) to be labelled
23673 as Thumb functions. This is because these labels, whilst
23674 they exist inside Thumb code, are not the entry points for
23675 possible ARM->Thumb calls. Also, these labels can be used
23676 as part of a computed goto or switch statement. eg gcc
23677 can generate code that looks like this:
23679 ldr r2, [pc, .Laaa]
23689 The first instruction loads the address of the jump table.
23690 The second instruction converts a table index into a byte offset.
23691 The third instruction gets the jump address out of the table.
23692 The fourth instruction performs the jump.
23694 If the address stored at .Laaa is that of a symbol which has the
23695 Thumb_Func bit set, then the linker will arrange for this address
23696 to have the bottom bit set, which in turn would mean that the
23697 address computation performed by the third instruction would end
23698 up with the bottom bit set. Since the ARM is capable of unaligned
23699 word loads, the instruction would then load the incorrect address
23700 out of the jump table, and chaos would ensue. */
23701 if (label_is_thumb_function_name
23702 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23703 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23705 /* When the address of a Thumb function is taken the bottom
23706 bit of that address should be set. This will allow
23707 interworking between Arm and Thumb functions to work
23710 THUMB_SET_FUNC (sym
, 1);
23712 label_is_thumb_function_name
= FALSE
;
23715 dwarf2_emit_label (sym
);
23719 arm_data_in_code (void)
23721 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23723 *input_line_pointer
= '/';
23724 input_line_pointer
+= 5;
23725 *input_line_pointer
= 0;
23733 arm_canonicalize_symbol_name (char * name
)
23737 if (thumb_mode
&& (len
= strlen (name
)) > 5
23738 && streq (name
+ len
- 5, "/data"))
23739 *(name
+ len
- 5) = 0;
23744 /* Table of all register names defined by default. The user can
23745 define additional names with .req. Note that all register names
23746 should appear in both upper and lowercase variants. Some registers
23747 also have mixed-case names. */
23749 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23750 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23751 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23752 #define REGSET(p,t) \
23753 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23754 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23755 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23756 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23757 #define REGSETH(p,t) \
23758 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23759 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23760 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23761 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23762 #define REGSET2(p,t) \
23763 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23764 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23765 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23766 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23767 #define SPLRBANK(base,bank,t) \
23768 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23769 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23770 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23771 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23772 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23773 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23775 static const struct reg_entry reg_names
[] =
23777 /* ARM integer registers. */
23778 REGSET(r
, RN
), REGSET(R
, RN
),
23780 /* ATPCS synonyms. */
23781 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23782 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23783 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23785 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23786 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23787 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23789 /* Well-known aliases. */
23790 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23791 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23793 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23794 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23796 /* Defining the new Zero register from ARMv8.1-M. */
23800 /* Coprocessor numbers. */
23801 REGSET(p
, CP
), REGSET(P
, CP
),
23803 /* Coprocessor register numbers. The "cr" variants are for backward
23805 REGSET(c
, CN
), REGSET(C
, CN
),
23806 REGSET(cr
, CN
), REGSET(CR
, CN
),
23808 /* ARM banked registers. */
23809 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23810 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23811 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23812 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23813 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23814 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23815 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23817 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23818 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23819 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23820 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23821 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23822 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23823 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23824 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23826 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23827 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23828 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23829 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23830 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23831 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23832 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23833 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23834 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23836 /* FPA registers. */
23837 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23838 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23840 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23841 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23843 /* VFP SP registers. */
23844 REGSET(s
,VFS
), REGSET(S
,VFS
),
23845 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23847 /* VFP DP Registers. */
23848 REGSET(d
,VFD
), REGSET(D
,VFD
),
23849 /* Extra Neon DP registers. */
23850 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23852 /* Neon QP registers. */
23853 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23855 /* VFP control registers. */
23856 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23857 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23858 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23859 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23860 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23861 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23862 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23863 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23864 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23865 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23866 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23868 /* Maverick DSP coprocessor registers. */
23869 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23870 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23872 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23873 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23874 REGDEF(dspsc
,0,DSPSC
),
23876 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23877 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23878 REGDEF(DSPSC
,0,DSPSC
),
23880 /* iWMMXt data registers - p0, c0-15. */
23881 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23883 /* iWMMXt control registers - p1, c0-3. */
23884 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23885 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23886 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23887 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23889 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23890 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23891 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23892 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23893 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23895 /* XScale accumulator registers. */
23896 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23902 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23903 within psr_required_here. */
23904 static const struct asm_psr psrs
[] =
23906 /* Backward compatibility notation. Note that "all" is no longer
23907 truly all possible PSR bits. */
23908 {"all", PSR_c
| PSR_f
},
23912 /* Individual flags. */
23918 /* Combinations of flags. */
23919 {"fs", PSR_f
| PSR_s
},
23920 {"fx", PSR_f
| PSR_x
},
23921 {"fc", PSR_f
| PSR_c
},
23922 {"sf", PSR_s
| PSR_f
},
23923 {"sx", PSR_s
| PSR_x
},
23924 {"sc", PSR_s
| PSR_c
},
23925 {"xf", PSR_x
| PSR_f
},
23926 {"xs", PSR_x
| PSR_s
},
23927 {"xc", PSR_x
| PSR_c
},
23928 {"cf", PSR_c
| PSR_f
},
23929 {"cs", PSR_c
| PSR_s
},
23930 {"cx", PSR_c
| PSR_x
},
23931 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23932 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23933 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23934 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23935 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23936 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23937 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23938 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23939 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23940 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23941 {"scf", PSR_s
| PSR_c
| PSR_f
},
23942 {"scx", PSR_s
| PSR_c
| PSR_x
},
23943 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23944 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23945 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23946 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23947 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23948 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23949 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23950 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23951 {"csf", PSR_c
| PSR_s
| PSR_f
},
23952 {"csx", PSR_c
| PSR_s
| PSR_x
},
23953 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23954 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23955 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23956 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23957 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23958 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23959 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23960 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23961 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23962 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23963 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23964 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23965 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23966 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23967 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23968 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23969 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23970 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23971 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23972 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23973 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23974 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23975 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23976 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23977 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23978 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23981 /* Table of V7M psr names. */
23982 static const struct asm_psr v7m_psrs
[] =
23984 {"apsr", 0x0 }, {"APSR", 0x0 },
23985 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23986 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23987 {"psr", 0x3 }, {"PSR", 0x3 },
23988 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23989 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23990 {"epsr", 0x6 }, {"EPSR", 0x6 },
23991 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23992 {"msp", 0x8 }, {"MSP", 0x8 },
23993 {"psp", 0x9 }, {"PSP", 0x9 },
23994 {"msplim", 0xa }, {"MSPLIM", 0xa },
23995 {"psplim", 0xb }, {"PSPLIM", 0xb },
23996 {"primask", 0x10}, {"PRIMASK", 0x10},
23997 {"basepri", 0x11}, {"BASEPRI", 0x11},
23998 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23999 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
24000 {"control", 0x14}, {"CONTROL", 0x14},
24001 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
24002 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24003 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24004 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24005 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24006 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24007 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24008 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24009 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24012 /* Table of all shift-in-operand names. */
24013 static const struct asm_shift_name shift_names
[] =
24015 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24016 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24017 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24018 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24019 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24020 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24021 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24024 /* Table of all explicit relocation names. */
24026 static struct reloc_entry reloc_names
[] =
24028 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24029 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24030 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24031 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24032 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24033 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24034 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24035 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24036 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24037 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24038 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24039 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24040 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24041 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24042 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24043 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24044 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24045 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24046 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24047 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24048 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24049 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24050 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24051 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24052 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24053 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24054 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24058 /* Table of all conditional affixes. */
24059 static const struct asm_cond conds
[] =
24063 {"cs", 0x2}, {"hs", 0x2},
24064 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24077 static const struct asm_cond vconds
[] =
24083 #define UL_BARRIER(L,U,CODE,FEAT) \
24084 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24085 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24087 static struct asm_barrier_opt barrier_opt_names
[] =
24089 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24090 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24091 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24092 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24093 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24094 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24095 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24096 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24097 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24098 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24099 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24101 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24102 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24103 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24104 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24109 /* Table of ARM-format instructions. */
24111 /* Macros for gluing together operand strings. N.B. In all cases
24112 other than OPS0, the trailing OP_stop comes from default
24113 zero-initialization of the unspecified elements of the array. */
24114 #define OPS0() { OP_stop, }
24115 #define OPS1(a) { OP_##a, }
24116 #define OPS2(a,b) { OP_##a,OP_##b, }
24117 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24118 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24119 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24120 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24122 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24123 This is useful when mixing operands for ARM and THUMB, i.e. using the
24124 MIX_ARM_THUMB_OPERANDS macro.
24125 In order to use these macros, prefix the number of operands with _
24127 #define OPS_1(a) { a, }
24128 #define OPS_2(a,b) { a,b, }
24129 #define OPS_3(a,b,c) { a,b,c, }
24130 #define OPS_4(a,b,c,d) { a,b,c,d, }
24131 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24132 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24134 /* These macros abstract out the exact format of the mnemonic table and
24135 save some repeated characters. */
24137 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24138 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24139 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24140 THUMB_VARIANT, do_##ae, do_##te, 0 }
24142 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24143 a T_MNEM_xyz enumerator. */
24144 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24145 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24146 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24147 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24149 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24150 infix after the third character. */
24151 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24152 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24153 THUMB_VARIANT, do_##ae, do_##te, 0 }
24154 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24155 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24156 THUMB_VARIANT, do_##ae, do_##te, 0 }
24157 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24158 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24159 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24160 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24161 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24162 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24163 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24164 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24166 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24167 field is still 0xE. Many of the Thumb variants can be executed
24168 conditionally, so this is checked separately. */
24169 #define TUE(mnem, op, top, nops, ops, ae, te) \
24170 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24171 THUMB_VARIANT, do_##ae, do_##te, 0 }
24173 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24174 Used by mnemonics that have very minimal differences in the encoding for
24175 ARM and Thumb variants and can be handled in a common function. */
24176 #define TUEc(mnem, op, top, nops, ops, en) \
24177 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24178 THUMB_VARIANT, do_##en, do_##en, 0 }
24180 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24181 condition code field. */
24182 #define TUF(mnem, op, top, nops, ops, ae, te) \
24183 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24184 THUMB_VARIANT, do_##ae, do_##te, 0 }
24186 /* ARM-only variants of all the above. */
24187 #define CE(mnem, op, nops, ops, ae) \
24188 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24190 #define C3(mnem, op, nops, ops, ae) \
24191 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24193 /* Thumb-only variants of TCE and TUE. */
24194 #define ToC(mnem, top, nops, ops, te) \
24195 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24198 #define ToU(mnem, top, nops, ops, te) \
24199 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24202 /* T_MNEM_xyz enumerator variants of ToC. */
24203 #define toC(mnem, top, nops, ops, te) \
24204 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24207 /* T_MNEM_xyz enumerator variants of ToU. */
24208 #define toU(mnem, top, nops, ops, te) \
24209 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24212 /* Legacy mnemonics that always have conditional infix after the third
24214 #define CL(mnem, op, nops, ops, ae) \
24215 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24216 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24218 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24219 #define cCE(mnem, op, nops, ops, ae) \
24220 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24222 /* mov instructions that are shared between coprocessor and MVE. */
24223 #define mcCE(mnem, op, nops, ops, ae) \
24224 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24226 /* Legacy coprocessor instructions where conditional infix and conditional
24227 suffix are ambiguous. For consistency this includes all FPA instructions,
24228 not just the potentially ambiguous ones. */
24229 #define cCL(mnem, op, nops, ops, ae) \
24230 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24231 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24233 /* Coprocessor, takes either a suffix or a position-3 infix
24234 (for an FPA corner case). */
24235 #define C3E(mnem, op, nops, ops, ae) \
24236 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24237 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24239 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24240 { m1 #m2 m3, OPS##nops ops, \
24241 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24242 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24244 #define CM(m1, m2, op, nops, ops, ae) \
24245 xCM_ (m1, , m2, op, nops, ops, ae), \
24246 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24247 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24248 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24249 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24250 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24251 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24252 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24253 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24254 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24255 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24256 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24257 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24258 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24259 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24260 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24261 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24262 xCM_ (m1, le, m2, op, nops, ops, ae), \
24263 xCM_ (m1, al, m2, op, nops, ops, ae)
24265 #define UE(mnem, op, nops, ops, ae) \
24266 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24268 #define UF(mnem, op, nops, ops, ae) \
24269 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24271 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24272 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24273 use the same encoding function for each. */
24274 #define NUF(mnem, op, nops, ops, enc) \
24275 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24276 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24278 /* Neon data processing, version which indirects through neon_enc_tab for
24279 the various overloaded versions of opcodes. */
24280 #define nUF(mnem, op, nops, ops, enc) \
24281 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24282 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24284 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24286 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24287 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24288 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24290 #define NCE(mnem, op, nops, ops, enc) \
24291 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24293 #define NCEF(mnem, op, nops, ops, enc) \
24294 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24296 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24297 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24298 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24299 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24301 #define nCE(mnem, op, nops, ops, enc) \
24302 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24304 #define nCEF(mnem, op, nops, ops, enc) \
24305 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24308 #define mCEF(mnem, op, nops, ops, enc) \
24309 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24310 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24313 /* nCEF but for MVE predicated instructions. */
24314 #define mnCEF(mnem, op, nops, ops, enc) \
24315 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24317 /* nCE but for MVE predicated instructions. */
24318 #define mnCE(mnem, op, nops, ops, enc) \
24319 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24321 /* NUF but for potentially MVE predicated instructions. */
24322 #define MNUF(mnem, op, nops, ops, enc) \
24323 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24324 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24326 /* nUF but for potentially MVE predicated instructions. */
24327 #define mnUF(mnem, op, nops, ops, enc) \
24328 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24329 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24331 /* ToC but for potentially MVE predicated instructions. */
24332 #define mToC(mnem, top, nops, ops, te) \
24333 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24336 /* NCE but for MVE predicated instructions. */
24337 #define MNCE(mnem, op, nops, ops, enc) \
24338 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24340 /* NCEF but for MVE predicated instructions. */
24341 #define MNCEF(mnem, op, nops, ops, enc) \
24342 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24345 static const struct asm_opcode insns
[] =
24347 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24348 #define THUMB_VARIANT & arm_ext_v4t
24349 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24350 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24351 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24352 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24353 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24354 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24355 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24356 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24357 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24358 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24360 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24361 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24362 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24363 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24364 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24366 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24367 for setting PSR flag bits. They are obsolete in V6 and do not
24368 have Thumb equivalents. */
24369 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24370 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24371 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24372 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24373 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24374 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24375 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24376 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24377 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24379 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24380 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24381 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24382 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24384 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24385 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24386 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24388 OP_ADDRGLDR
),ldst
, t_ldst
),
24389 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24391 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24392 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24393 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24394 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24395 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24396 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24398 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24399 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24402 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24403 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24404 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24405 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24407 /* Thumb-compatibility pseudo ops. */
24408 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24409 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24410 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24411 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24412 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24413 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24414 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24415 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24416 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24417 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24418 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24419 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24421 /* These may simplify to neg. */
24422 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24423 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24425 #undef THUMB_VARIANT
24426 #define THUMB_VARIANT & arm_ext_os
24428 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24429 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24431 #undef THUMB_VARIANT
24432 #define THUMB_VARIANT & arm_ext_v6
24434 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24436 /* V1 instructions with no Thumb analogue prior to V6T2. */
24437 #undef THUMB_VARIANT
24438 #define THUMB_VARIANT & arm_ext_v6t2
24440 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24441 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24442 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24444 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24445 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24446 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24447 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24449 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24450 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24452 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24453 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24455 /* V1 instructions with no Thumb analogue at all. */
24456 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24457 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24459 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24460 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24461 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24462 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24463 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24464 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24465 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24466 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24469 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24470 #undef THUMB_VARIANT
24471 #define THUMB_VARIANT & arm_ext_v4t
24473 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24474 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24476 #undef THUMB_VARIANT
24477 #define THUMB_VARIANT & arm_ext_v6t2
24479 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24480 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24482 /* Generic coprocessor instructions. */
24483 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24484 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24485 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24486 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24487 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24488 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24489 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24492 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24494 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24495 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24498 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24499 #undef THUMB_VARIANT
24500 #define THUMB_VARIANT & arm_ext_msr
24502 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24503 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24506 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24507 #undef THUMB_VARIANT
24508 #define THUMB_VARIANT & arm_ext_v6t2
24510 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24511 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24512 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24513 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24514 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24515 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24516 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24517 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24520 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24521 #undef THUMB_VARIANT
24522 #define THUMB_VARIANT & arm_ext_v4t
24524 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24525 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24526 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24527 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24528 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24529 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24532 #define ARM_VARIANT & arm_ext_v4t_5
24534 /* ARM Architecture 4T. */
24535 /* Note: bx (and blx) are required on V5, even if the processor does
24536 not support Thumb. */
24537 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24540 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24541 #undef THUMB_VARIANT
24542 #define THUMB_VARIANT & arm_ext_v5t
24544 /* Note: blx has 2 variants; the .value coded here is for
24545 BLX(2). Only this variant has conditional execution. */
24546 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24547 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24549 #undef THUMB_VARIANT
24550 #define THUMB_VARIANT & arm_ext_v6t2
24552 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24553 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24554 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24555 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24556 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24557 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24558 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24559 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24562 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24563 #undef THUMB_VARIANT
24564 #define THUMB_VARIANT & arm_ext_v5exp
24566 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24567 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24568 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24569 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24571 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24572 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24574 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24575 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24576 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24577 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24579 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24580 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24581 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24582 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24584 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24585 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24587 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24588 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24589 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24590 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24593 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24594 #undef THUMB_VARIANT
24595 #define THUMB_VARIANT & arm_ext_v6t2
24597 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24598 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24600 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24601 ADDRGLDRS
), ldrd
, t_ldstd
),
24603 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24604 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24607 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24609 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24612 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24613 #undef THUMB_VARIANT
24614 #define THUMB_VARIANT & arm_ext_v6
24616 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24617 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24618 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24619 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24620 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24621 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24622 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24623 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24624 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24625 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24627 #undef THUMB_VARIANT
24628 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24630 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24631 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24633 #undef THUMB_VARIANT
24634 #define THUMB_VARIANT & arm_ext_v6t2
24636 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24637 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24639 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24640 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24642 /* ARM V6 not included in V7M. */
24643 #undef THUMB_VARIANT
24644 #define THUMB_VARIANT & arm_ext_v6_notm
24645 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24646 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24647 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24648 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24649 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24650 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24651 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24652 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24653 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24654 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24655 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24656 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24657 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24658 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24659 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24660 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24661 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24662 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24663 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24665 /* ARM V6 not included in V7M (eg. integer SIMD). */
24666 #undef THUMB_VARIANT
24667 #define THUMB_VARIANT & arm_ext_v6_dsp
24668 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24669 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24670 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24671 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24672 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24673 /* Old name for QASX. */
24674 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24675 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24676 /* Old name for QSAX. */
24677 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24678 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24679 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24680 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24681 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 /* Old name for SASX. */
24684 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24685 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24686 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24688 /* Old name for SHASX. */
24689 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 /* Old name for SHSAX. */
24692 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24693 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 /* Old name for SSAX. */
24697 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24700 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 /* Old name for UASX. */
24704 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24705 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24708 /* Old name for UHASX. */
24709 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 /* Old name for UHSAX. */
24712 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24715 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24718 /* Old name for UQASX. */
24719 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24720 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 /* Old name for UQSAX. */
24722 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24727 /* Old name for USAX. */
24728 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24729 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24730 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24731 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24732 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24733 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24734 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24735 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24736 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24737 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24738 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24739 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24740 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24741 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24742 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24743 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24744 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24745 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24746 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24747 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24748 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24749 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24750 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24751 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24752 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24753 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24754 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24755 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24756 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24757 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24758 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24759 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24760 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24761 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24764 #define ARM_VARIANT & arm_ext_v6k_v6t2
24765 #undef THUMB_VARIANT
24766 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24768 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24769 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24770 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24771 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24773 #undef THUMB_VARIANT
24774 #define THUMB_VARIANT & arm_ext_v6_notm
24775 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24777 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24778 RRnpcb
), strexd
, t_strexd
),
24780 #undef THUMB_VARIANT
24781 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24782 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24784 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24786 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24788 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24790 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24793 #define ARM_VARIANT & arm_ext_sec
24794 #undef THUMB_VARIANT
24795 #define THUMB_VARIANT & arm_ext_sec
24797 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24800 #define ARM_VARIANT & arm_ext_virt
24801 #undef THUMB_VARIANT
24802 #define THUMB_VARIANT & arm_ext_virt
24804 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24805 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24808 #define ARM_VARIANT & arm_ext_pan
24809 #undef THUMB_VARIANT
24810 #define THUMB_VARIANT & arm_ext_pan
24812 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24815 #define ARM_VARIANT & arm_ext_v6t2
24816 #undef THUMB_VARIANT
24817 #define THUMB_VARIANT & arm_ext_v6t2
24819 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24820 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24821 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24822 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24824 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24825 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24827 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24828 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24829 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24830 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24833 #define ARM_VARIANT & arm_ext_v3
24834 #undef THUMB_VARIANT
24835 #define THUMB_VARIANT & arm_ext_v6t2
24837 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24838 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24839 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24842 #define ARM_VARIANT & arm_ext_v6t2
24843 #undef THUMB_VARIANT
24844 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24845 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24846 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24848 /* Thumb-only instructions. */
24850 #define ARM_VARIANT NULL
24851 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24852 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24854 /* ARM does not really have an IT instruction, so always allow it.
24855 The opcode is copied from Thumb in order to allow warnings in
24856 -mimplicit-it=[never | arm] modes. */
24858 #define ARM_VARIANT & arm_ext_v1
24859 #undef THUMB_VARIANT
24860 #define THUMB_VARIANT & arm_ext_v6t2
24862 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24863 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24864 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24865 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24866 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24867 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24868 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24869 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24870 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24871 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24872 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24873 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24874 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24875 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24876 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24877 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24878 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24879 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24881 /* Thumb2 only instructions. */
24883 #define ARM_VARIANT NULL
24885 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24886 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24887 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24888 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24889 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24890 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24892 /* Hardware division instructions. */
24894 #define ARM_VARIANT & arm_ext_adiv
24895 #undef THUMB_VARIANT
24896 #define THUMB_VARIANT & arm_ext_div
24898 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24899 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24901 /* ARM V6M/V7 instructions. */
24903 #define ARM_VARIANT & arm_ext_barrier
24904 #undef THUMB_VARIANT
24905 #define THUMB_VARIANT & arm_ext_barrier
24907 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24908 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24909 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24911 /* ARM V7 instructions. */
24913 #define ARM_VARIANT & arm_ext_v7
24914 #undef THUMB_VARIANT
24915 #define THUMB_VARIANT & arm_ext_v7
24917 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24918 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24921 #define ARM_VARIANT & arm_ext_mp
24922 #undef THUMB_VARIANT
24923 #define THUMB_VARIANT & arm_ext_mp
24925 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24927 /* AArchv8 instructions. */
24929 #define ARM_VARIANT & arm_ext_v8
24931 /* Instructions shared between armv8-a and armv8-m. */
24932 #undef THUMB_VARIANT
24933 #define THUMB_VARIANT & arm_ext_atomics
24935 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24936 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24937 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24938 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24939 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24940 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24941 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24942 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24943 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24944 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24946 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24948 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24950 #undef THUMB_VARIANT
24951 #define THUMB_VARIANT & arm_ext_v8
24953 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24954 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24956 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24958 #undef THUMB_VARIANT
24959 #define THUMB_VARIANT & arm_ext_v8r
24961 #define ARM_VARIANT & arm_ext_v8r
24963 /* ARMv8-R instructions. */
24964 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24966 /* Defined in V8 but is in undefined encoding space for earlier
24967 architectures. However earlier architectures are required to treat
24968 this instuction as a semihosting trap as well. Hence while not explicitly
24969 defined as such, it is in fact correct to define the instruction for all
24971 #undef THUMB_VARIANT
24972 #define THUMB_VARIANT & arm_ext_v1
24974 #define ARM_VARIANT & arm_ext_v1
24975 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24977 /* ARMv8 T32 only. */
24979 #define ARM_VARIANT NULL
24980 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24981 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24982 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24984 /* FP for ARMv8. */
24986 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24987 #undef THUMB_VARIANT
24988 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24990 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24991 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24992 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24993 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24994 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24995 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24996 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24997 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24998 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24999 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
25000 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
25002 /* Crypto v1 extensions. */
25004 #define ARM_VARIANT & fpu_crypto_ext_armv8
25005 #undef THUMB_VARIANT
25006 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25008 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25009 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25010 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25011 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25012 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25013 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25014 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25015 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25016 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25017 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25018 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25019 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25020 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25021 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25024 #define ARM_VARIANT & arm_ext_crc
25025 #undef THUMB_VARIANT
25026 #define THUMB_VARIANT & arm_ext_crc
25027 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25028 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25029 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25030 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25031 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25032 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25034 /* ARMv8.2 RAS extension. */
25036 #define ARM_VARIANT & arm_ext_ras
25037 #undef THUMB_VARIANT
25038 #define THUMB_VARIANT & arm_ext_ras
25039 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25042 #define ARM_VARIANT & arm_ext_v8_3
25043 #undef THUMB_VARIANT
25044 #define THUMB_VARIANT & arm_ext_v8_3
25045 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25048 #define ARM_VARIANT & fpu_neon_ext_dotprod
25049 #undef THUMB_VARIANT
25050 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25051 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25052 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25055 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25056 #undef THUMB_VARIANT
25057 #define THUMB_VARIANT NULL
25059 cCE("wfs", e200110
, 1, (RR
), rd
),
25060 cCE("rfs", e300110
, 1, (RR
), rd
),
25061 cCE("wfc", e400110
, 1, (RR
), rd
),
25062 cCE("rfc", e500110
, 1, (RR
), rd
),
25064 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25065 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25066 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25067 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25069 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25070 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25071 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25072 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25074 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25075 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25076 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25077 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25078 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25082 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25083 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25095 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25277 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25278 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25280 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25282 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25283 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25284 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25285 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25286 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25290 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25291 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25303 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25446 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25447 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25449 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25451 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25452 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25453 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25454 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25456 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25457 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25458 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25459 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25460 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25461 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25462 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25463 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25464 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25465 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25466 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25467 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25469 /* The implementation of the FIX instruction is broken on some
25470 assemblers, in that it accepts a precision specifier as well as a
25471 rounding specifier, despite the fact that this is meaningless.
25472 To be more compatible, we accept it as well, though of course it
25473 does not set any bits. */
25474 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25475 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25476 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25477 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25478 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25479 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25480 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25481 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25482 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25483 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25484 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25485 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25486 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25488 /* Instructions that were new with the real FPA, call them V2. */
25490 #define ARM_VARIANT & fpu_fpa_ext_v2
25492 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25493 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25494 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25495 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25496 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25497 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25500 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25501 #undef THUMB_VARIANT
25502 #define THUMB_VARIANT & arm_ext_v6t2
25503 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25504 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25505 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25506 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25507 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25508 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25510 /* Memory operations. */
25511 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25512 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25513 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25514 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25515 #undef THUMB_VARIANT
25517 /* Moves and type conversions. */
25518 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25519 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25520 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25521 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25522 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25523 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25524 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25525 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25526 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25528 /* Memory operations. */
25529 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25530 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25531 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25532 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25533 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25534 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25535 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25536 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25537 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25538 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25539 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25540 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25542 /* Monadic operations. */
25543 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25544 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25545 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25547 /* Dyadic operations. */
25548 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25549 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25550 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25551 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25552 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25553 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25554 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25555 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25556 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25559 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25560 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25561 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25562 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25564 /* Double precision load/store are still present on single precision
25565 implementations. */
25566 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25567 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25568 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25569 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25570 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25571 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25572 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25573 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25576 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25578 /* Moves and type conversions. */
25579 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25580 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25581 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25582 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25583 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25584 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25585 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25586 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25587 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25588 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25589 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25590 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25592 /* Monadic operations. */
25593 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25594 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25595 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25597 /* Dyadic operations. */
25598 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25599 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25600 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25601 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25602 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25603 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25604 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25605 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25606 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25609 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25610 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25611 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25612 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25614 /* Instructions which may belong to either the Neon or VFP instruction sets.
25615 Individual encoder functions perform additional architecture checks. */
25617 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25618 #undef THUMB_VARIANT
25619 #define THUMB_VARIANT & arm_ext_v6t2
25621 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25622 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25623 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25624 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25625 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25626 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25628 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25629 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25631 #undef THUMB_VARIANT
25632 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25634 /* These mnemonics are unique to VFP. */
25635 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25636 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25637 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25638 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25639 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25640 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25642 /* Mnemonics shared by Neon and VFP. */
25643 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25645 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25646 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25647 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25648 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25651 /* NOTE: All VMOV encoding is special-cased! */
25652 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25654 #undef THUMB_VARIANT
25655 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25656 by different feature bits. Since we are setting the Thumb guard, we can
25657 require Thumb-1 which makes it a nop guard and set the right feature bit in
25658 do_vldr_vstr (). */
25659 #define THUMB_VARIANT & arm_ext_v4t
25660 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25661 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25664 #define ARM_VARIANT & arm_ext_fp16
25665 #undef THUMB_VARIANT
25666 #define THUMB_VARIANT & arm_ext_fp16
25667 /* New instructions added from v8.2, allowing the extraction and insertion of
25668 the upper 16 bits of a 32-bit vector register. */
25669 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25670 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25672 /* New backported fma/fms instructions optional in v8.2. */
25673 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25674 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25676 #undef THUMB_VARIANT
25677 #define THUMB_VARIANT & fpu_neon_ext_v1
25679 #define ARM_VARIANT & fpu_neon_ext_v1
25681 /* Data processing with three registers of the same length. */
25682 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25683 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25684 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25685 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25686 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25687 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25688 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25689 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25690 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25691 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25692 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25693 /* If not immediate, fall back to neon_dyadic_i64_su.
25694 shl should accept I8 I16 I32 I64,
25695 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25696 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25697 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25698 /* Logic ops, types optional & ignored. */
25699 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25700 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25701 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25702 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25703 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25704 /* Bitfield ops, untyped. */
25705 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25706 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25707 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25708 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25709 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25710 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25711 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25712 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25713 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25714 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25715 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25716 back to neon_dyadic_if_su. */
25717 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25718 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25719 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25720 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25721 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25722 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25723 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25724 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25725 /* Comparison. Type I8 I16 I32 F32. */
25726 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25727 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25728 /* As above, D registers only. */
25729 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25730 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25731 /* Int and float variants, signedness unimportant. */
25732 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25733 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25734 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25735 /* Add/sub take types I8 I16 I32 I64 F32. */
25736 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25737 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25738 /* vtst takes sizes 8, 16, 32. */
25739 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25740 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25741 /* VMUL takes I8 I16 I32 F32 P8. */
25742 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25743 /* VQD{R}MULH takes S16 S32. */
25744 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25745 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25746 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25747 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25748 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25749 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25750 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25751 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25752 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25753 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25754 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25755 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25756 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25757 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25758 /* ARM v8.1 extension. */
25759 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25760 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25761 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25763 /* Two address, int/float. Types S8 S16 S32 F32. */
25764 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25765 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25767 /* Data processing with two registers and a shift amount. */
25768 /* Right shifts, and variants with rounding.
25769 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25770 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25771 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25772 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25773 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25774 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25775 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25776 /* Shift and insert. Sizes accepted 8 16 32 64. */
25777 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25778 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25779 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25780 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25781 /* Right shift immediate, saturating & narrowing, with rounding variants.
25782 Types accepted S16 S32 S64 U16 U32 U64. */
25783 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25784 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25785 /* As above, unsigned. Types accepted S16 S32 S64. */
25786 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25787 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25788 /* Right shift narrowing. Types accepted I16 I32 I64. */
25789 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25790 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25791 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25792 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25793 /* CVT with optional immediate for fixed-point variant. */
25794 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25796 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25798 /* Data processing, three registers of different lengths. */
25799 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25800 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25801 /* If not scalar, fall back to neon_dyadic_long.
25802 Vector types as above, scalar types S16 S32 U16 U32. */
25803 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25804 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25805 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25806 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25807 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25808 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25809 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25810 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25811 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25812 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25813 /* Saturating doubling multiplies. Types S16 S32. */
25814 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25815 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25816 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25817 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25818 S16 S32 U16 U32. */
25819 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25821 /* Extract. Size 8. */
25822 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25823 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25825 /* Two registers, miscellaneous. */
25826 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25827 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25828 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25829 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25830 /* Vector replicate. Sizes 8 16 32. */
25831 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25832 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25833 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25834 /* VMOVN. Types I16 I32 I64. */
25835 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25836 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25837 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25838 /* VQMOVUN. Types S16 S32 S64. */
25839 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25840 /* VZIP / VUZP. Sizes 8 16 32. */
25841 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25842 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25843 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25844 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25845 /* VQABS / VQNEG. Types S8 S16 S32. */
25846 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25847 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25848 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25849 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25850 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25851 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25852 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25853 /* Reciprocal estimates. Types U32 F16 F32. */
25854 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25855 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25856 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25857 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25858 /* VCLS. Types S8 S16 S32. */
25859 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25860 /* VCLZ. Types I8 I16 I32. */
25861 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25862 /* VCNT. Size 8. */
25863 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25864 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25865 /* Two address, untyped. */
25866 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25867 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25868 /* VTRN. Sizes 8 16 32. */
25869 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25870 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25872 /* Table lookup. Size 8. */
25873 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25874 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25876 #undef THUMB_VARIANT
25877 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25879 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25881 /* Neon element/structure load/store. */
25882 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25883 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25884 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25885 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25886 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25887 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25888 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25889 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25891 #undef THUMB_VARIANT
25892 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25894 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25895 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25896 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25897 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25898 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25899 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25900 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25901 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25902 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25903 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25905 #undef THUMB_VARIANT
25906 #define THUMB_VARIANT & fpu_vfp_ext_v3
25908 #define ARM_VARIANT & fpu_vfp_ext_v3
25910 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25911 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25912 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25913 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25914 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25915 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25916 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25917 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25918 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25921 #define ARM_VARIANT & fpu_vfp_ext_fma
25922 #undef THUMB_VARIANT
25923 #define THUMB_VARIANT & fpu_vfp_ext_fma
25924 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25925 VFP FMA variant; NEON and VFP FMA always includes the NEON
25926 FMA instructions. */
25927 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25928 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25929 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25931 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25932 the v form should always be used. */
25933 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25934 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25935 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25936 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25937 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25938 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25940 #undef THUMB_VARIANT
25942 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25944 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25945 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25946 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25947 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25948 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25949 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25950 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25951 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25954 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25956 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25957 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25958 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25959 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25960 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25961 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25962 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25963 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25964 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25965 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25966 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25967 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25968 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25969 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25970 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25971 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25972 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25973 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25974 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25975 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25976 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25977 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25978 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25979 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25980 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25981 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25982 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25983 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25984 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25985 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25986 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25987 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25988 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25989 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25990 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25991 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25992 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25993 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25994 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25995 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25996 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25997 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25999 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26000 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26003 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26012 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26023 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26024 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26025 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26026 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26045 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26046 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26049 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26054 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26056 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26057 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26058 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26059 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26060 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26061 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26062 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26063 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26064 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26065 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26066 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26067 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26068 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26069 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26070 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26071 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26072 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26073 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26074 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26075 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26076 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26077 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26078 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26079 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26080 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26081 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26082 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26083 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26084 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26085 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26086 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26087 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26088 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26089 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26090 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26091 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26092 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26093 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26095 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26096 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26097 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26098 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26099 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26100 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26101 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26102 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26103 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26104 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26105 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26106 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26107 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26108 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26109 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26110 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26111 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26112 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26113 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26114 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26115 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26116 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26117 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26120 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26122 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26123 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26124 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26125 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26126 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26127 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26128 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26129 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26131 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26132 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26143 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26176 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26181 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26183 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26184 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26185 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26186 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26187 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26188 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26189 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26190 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26191 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26192 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26193 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26194 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26195 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26196 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26197 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26198 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26199 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26200 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26201 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26202 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26203 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26204 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26205 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26206 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26207 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26208 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26209 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26210 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26211 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26212 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26213 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26214 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26215 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26216 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26217 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26218 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26219 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26220 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26221 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26222 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26223 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26224 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26225 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26226 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26227 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26228 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26229 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26230 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26231 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26232 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26233 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26234 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26235 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26236 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26237 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26238 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26239 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26240 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26241 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26242 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26243 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26244 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26245 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26246 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26247 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26248 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26249 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26250 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26251 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26252 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26253 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26254 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26255 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26256 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26257 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26258 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26260 /* ARMv8.5-A instructions. */
26262 #define ARM_VARIANT & arm_ext_sb
26263 #undef THUMB_VARIANT
26264 #define THUMB_VARIANT & arm_ext_sb
26265 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26268 #define ARM_VARIANT & arm_ext_predres
26269 #undef THUMB_VARIANT
26270 #define THUMB_VARIANT & arm_ext_predres
26271 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26272 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26273 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26275 /* ARMv8-M instructions. */
26277 #define ARM_VARIANT NULL
26278 #undef THUMB_VARIANT
26279 #define THUMB_VARIANT & arm_ext_v8m
26280 ToU("sg", e97fe97f
, 0, (), noargs
),
26281 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26282 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26283 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26284 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26285 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26286 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26288 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26289 instructions behave as nop if no VFP is present. */
26290 #undef THUMB_VARIANT
26291 #define THUMB_VARIANT & arm_ext_v8m_main
26292 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26293 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26295 /* Armv8.1-M Mainline instructions. */
26296 #undef THUMB_VARIANT
26297 #define THUMB_VARIANT & arm_ext_v8_1m_main
26298 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26299 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26300 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26301 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26302 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26303 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26304 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26305 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26306 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26308 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26309 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26310 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26311 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26312 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26314 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26315 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26316 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26318 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26319 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26321 #undef THUMB_VARIANT
26322 #define THUMB_VARIANT & mve_ext
26323 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26324 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26325 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26326 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26327 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26328 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26329 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26330 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26331 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26332 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26333 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26334 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26335 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26336 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26337 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26339 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26340 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26341 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26342 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26343 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26345 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26346 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26347 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26348 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26350 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26351 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26352 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26353 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26355 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26356 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26357 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26358 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26359 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26360 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26361 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26362 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26363 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26364 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26365 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26366 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26367 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26368 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26369 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26371 /* MVE and MVE FP only. */
26372 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26373 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26374 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26375 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26376 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26377 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26378 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26379 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26380 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26381 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26382 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26383 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26384 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26385 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26386 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26387 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26388 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26389 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26391 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26392 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26393 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26394 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26395 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26396 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26397 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26398 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26399 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26400 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26401 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26402 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26403 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26404 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26405 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26406 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26407 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26408 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26409 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26410 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26412 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26413 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26414 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26415 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26416 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26417 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26418 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26419 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26420 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26421 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26422 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26423 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26424 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26425 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26426 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26427 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26428 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26430 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26431 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26432 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26433 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26434 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26435 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26436 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26437 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26438 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26439 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26440 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26441 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26442 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26443 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26444 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26445 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26446 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26447 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26448 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26449 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26451 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26452 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26453 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26454 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26455 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26457 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26458 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26459 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26460 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26461 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26462 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26463 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26464 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26465 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26466 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26467 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26468 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26469 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26470 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26471 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26472 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26473 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26475 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26476 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26477 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26478 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26479 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26480 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26481 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26482 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26483 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26484 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26485 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26486 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26488 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26489 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26490 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26492 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26493 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26494 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26495 toU("lctp", _lctp
, 0, (), t_loloop
),
26497 #undef THUMB_VARIANT
26498 #define THUMB_VARIANT & mve_fp_ext
26499 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26500 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26501 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26502 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26503 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26504 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26505 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26506 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26509 #define ARM_VARIANT & fpu_vfp_ext_v1
26510 #undef THUMB_VARIANT
26511 #define THUMB_VARIANT & arm_ext_v6t2
26512 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26513 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26515 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26518 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26520 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26521 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26522 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26523 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26525 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26526 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26527 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26529 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26530 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26532 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26533 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26535 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26536 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26539 #define ARM_VARIANT & fpu_vfp_ext_v2
26541 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26542 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26543 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26544 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26547 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26548 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26549 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26550 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26551 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26552 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26553 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26556 #define ARM_VARIANT & fpu_neon_ext_v1
26557 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26558 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26559 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26560 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26561 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26562 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26563 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26564 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26565 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26566 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26567 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26568 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26569 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26570 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26571 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26572 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26573 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26574 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26575 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26576 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26577 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26578 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26579 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26580 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26581 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26582 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26583 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26584 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26585 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26586 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26587 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26588 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26589 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26590 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26591 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26592 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26593 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26596 #define ARM_VARIANT & arm_ext_v8_3
26597 #undef THUMB_VARIANT
26598 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26599 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26600 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26603 #define ARM_VARIANT &arm_ext_bf16
26604 #undef THUMB_VARIANT
26605 #define THUMB_VARIANT &arm_ext_bf16
26606 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26607 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26608 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26611 #define ARM_VARIANT &arm_ext_i8mm
26612 #undef THUMB_VARIANT
26613 #define THUMB_VARIANT &arm_ext_i8mm
26614 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26615 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26616 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26617 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26618 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26621 #undef THUMB_VARIANT
26622 #define THUMB_VARIANT &arm_ext_cde
26623 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26624 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26625 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26626 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26628 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26629 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26630 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26631 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26633 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26634 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26635 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26636 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26638 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26639 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26641 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26642 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26644 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26645 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26649 #undef THUMB_VARIANT
26681 /* MD interface: bits in the object file. */
26683 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26684 for use in the a.out file, and stores them in the array pointed to by buf.
26685 This knows about the endian-ness of the target machine and does
26686 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26687 2 (short) and 4 (long) Floating numbers are put out as a series of
26688 LITTLENUMS (shorts, here at least). */
26691 md_number_to_chars (char * buf
, valueT val
, int n
)
26693 if (target_big_endian
)
26694 number_to_chars_bigendian (buf
, val
, n
);
26696 number_to_chars_littleendian (buf
, val
, n
);
26700 md_chars_to_number (char * buf
, int n
)
26703 unsigned char * where
= (unsigned char *) buf
;
26705 if (target_big_endian
)
26710 result
|= (*where
++ & 255);
26718 result
|= (where
[n
] & 255);
26725 /* MD interface: Sections. */
26727 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26728 that an rs_machine_dependent frag may reach. */
26731 arm_frag_max_var (fragS
*fragp
)
26733 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26734 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26736 Note that we generate relaxable instructions even for cases that don't
26737 really need it, like an immediate that's a trivial constant. So we're
26738 overestimating the instruction size for some of those cases. Rather
26739 than putting more intelligence here, it would probably be better to
26740 avoid generating a relaxation frag in the first place when it can be
26741 determined up front that a short instruction will suffice. */
26743 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26747 /* Estimate the size of a frag before relaxing. Assume everything fits in
26751 md_estimate_size_before_relax (fragS
* fragp
,
26752 segT segtype ATTRIBUTE_UNUSED
)
26758 /* Convert a machine dependent frag. */
26761 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26763 unsigned long insn
;
26764 unsigned long old_op
;
26772 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26774 old_op
= bfd_get_16(abfd
, buf
);
26775 if (fragp
->fr_symbol
)
26777 exp
.X_op
= O_symbol
;
26778 exp
.X_add_symbol
= fragp
->fr_symbol
;
26782 exp
.X_op
= O_constant
;
26784 exp
.X_add_number
= fragp
->fr_offset
;
26785 opcode
= fragp
->fr_subtype
;
26788 case T_MNEM_ldr_pc
:
26789 case T_MNEM_ldr_pc2
:
26790 case T_MNEM_ldr_sp
:
26791 case T_MNEM_str_sp
:
26798 if (fragp
->fr_var
== 4)
26800 insn
= THUMB_OP32 (opcode
);
26801 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26803 insn
|= (old_op
& 0x700) << 4;
26807 insn
|= (old_op
& 7) << 12;
26808 insn
|= (old_op
& 0x38) << 13;
26810 insn
|= 0x00000c00;
26811 put_thumb32_insn (buf
, insn
);
26812 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26816 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26818 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26821 if (fragp
->fr_var
== 4)
26823 insn
= THUMB_OP32 (opcode
);
26824 insn
|= (old_op
& 0xf0) << 4;
26825 put_thumb32_insn (buf
, insn
);
26826 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26830 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26831 exp
.X_add_number
-= 4;
26839 if (fragp
->fr_var
== 4)
26841 int r0off
= (opcode
== T_MNEM_mov
26842 || opcode
== T_MNEM_movs
) ? 0 : 8;
26843 insn
= THUMB_OP32 (opcode
);
26844 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26845 insn
|= (old_op
& 0x700) << r0off
;
26846 put_thumb32_insn (buf
, insn
);
26847 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26851 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26856 if (fragp
->fr_var
== 4)
26858 insn
= THUMB_OP32(opcode
);
26859 put_thumb32_insn (buf
, insn
);
26860 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26863 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26867 if (fragp
->fr_var
== 4)
26869 insn
= THUMB_OP32(opcode
);
26870 insn
|= (old_op
& 0xf00) << 14;
26871 put_thumb32_insn (buf
, insn
);
26872 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26875 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26878 case T_MNEM_add_sp
:
26879 case T_MNEM_add_pc
:
26880 case T_MNEM_inc_sp
:
26881 case T_MNEM_dec_sp
:
26882 if (fragp
->fr_var
== 4)
26884 /* ??? Choose between add and addw. */
26885 insn
= THUMB_OP32 (opcode
);
26886 insn
|= (old_op
& 0xf0) << 4;
26887 put_thumb32_insn (buf
, insn
);
26888 if (opcode
== T_MNEM_add_pc
)
26889 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26891 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26894 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26902 if (fragp
->fr_var
== 4)
26904 insn
= THUMB_OP32 (opcode
);
26905 insn
|= (old_op
& 0xf0) << 4;
26906 insn
|= (old_op
& 0xf) << 16;
26907 put_thumb32_insn (buf
, insn
);
26908 if (insn
& (1 << 20))
26909 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26911 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26914 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26920 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26921 (enum bfd_reloc_code_real
) reloc_type
);
26922 fixp
->fx_file
= fragp
->fr_file
;
26923 fixp
->fx_line
= fragp
->fr_line
;
26924 fragp
->fr_fix
+= fragp
->fr_var
;
26926 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26927 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26928 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26929 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26932 /* Return the size of a relaxable immediate operand instruction.
26933 SHIFT and SIZE specify the form of the allowable immediate. */
26935 relax_immediate (fragS
*fragp
, int size
, int shift
)
26941 /* ??? Should be able to do better than this. */
26942 if (fragp
->fr_symbol
)
26945 low
= (1 << shift
) - 1;
26946 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26947 offset
= fragp
->fr_offset
;
26948 /* Force misaligned offsets to 32-bit variant. */
26951 if (offset
& ~mask
)
26956 /* Get the address of a symbol during relaxation. */
26958 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26964 sym
= fragp
->fr_symbol
;
26965 sym_frag
= symbol_get_frag (sym
);
26966 know (S_GET_SEGMENT (sym
) != absolute_section
26967 || sym_frag
== &zero_address_frag
);
26968 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26970 /* If frag has yet to be reached on this pass, assume it will
26971 move by STRETCH just as we did. If this is not so, it will
26972 be because some frag between grows, and that will force
26976 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26980 /* Adjust stretch for any alignment frag. Note that if have
26981 been expanding the earlier code, the symbol may be
26982 defined in what appears to be an earlier frag. FIXME:
26983 This doesn't handle the fr_subtype field, which specifies
26984 a maximum number of bytes to skip when doing an
26986 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26988 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26991 stretch
= - ((- stretch
)
26992 & ~ ((1 << (int) f
->fr_offset
) - 1));
26994 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27006 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27009 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27014 /* Assume worst case for symbols not known to be in the same section. */
27015 if (fragp
->fr_symbol
== NULL
27016 || !S_IS_DEFINED (fragp
->fr_symbol
)
27017 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27018 || S_IS_WEAK (fragp
->fr_symbol
))
27021 val
= relaxed_symbol_addr (fragp
, stretch
);
27022 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27023 addr
= (addr
+ 4) & ~3;
27024 /* Force misaligned targets to 32-bit variant. */
27028 if (val
< 0 || val
> 1020)
27033 /* Return the size of a relaxable add/sub immediate instruction. */
27035 relax_addsub (fragS
*fragp
, asection
*sec
)
27040 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27041 op
= bfd_get_16(sec
->owner
, buf
);
27042 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27043 return relax_immediate (fragp
, 8, 0);
27045 return relax_immediate (fragp
, 3, 0);
27048 /* Return TRUE iff the definition of symbol S could be pre-empted
27049 (overridden) at link or load time. */
27051 symbol_preemptible (symbolS
*s
)
27053 /* Weak symbols can always be pre-empted. */
27057 /* Non-global symbols cannot be pre-empted. */
27058 if (! S_IS_EXTERNAL (s
))
27062 /* In ELF, a global symbol can be marked protected, or private. In that
27063 case it can't be pre-empted (other definitions in the same link unit
27064 would violate the ODR). */
27065 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27069 /* Other global symbols might be pre-empted. */
27073 /* Return the size of a relaxable branch instruction. BITS is the
27074 size of the offset field in the narrow instruction. */
27077 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27083 /* Assume worst case for symbols not known to be in the same section. */
27084 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27085 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27086 || S_IS_WEAK (fragp
->fr_symbol
))
27090 /* A branch to a function in ARM state will require interworking. */
27091 if (S_IS_DEFINED (fragp
->fr_symbol
)
27092 && ARM_IS_FUNC (fragp
->fr_symbol
))
27096 if (symbol_preemptible (fragp
->fr_symbol
))
27099 val
= relaxed_symbol_addr (fragp
, stretch
);
27100 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27103 /* Offset is a signed value *2 */
27105 if (val
>= limit
|| val
< -limit
)
27111 /* Relax a machine dependent frag. This returns the amount by which
27112 the current size of the frag should change. */
27115 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27120 oldsize
= fragp
->fr_var
;
27121 switch (fragp
->fr_subtype
)
27123 case T_MNEM_ldr_pc2
:
27124 newsize
= relax_adr (fragp
, sec
, stretch
);
27126 case T_MNEM_ldr_pc
:
27127 case T_MNEM_ldr_sp
:
27128 case T_MNEM_str_sp
:
27129 newsize
= relax_immediate (fragp
, 8, 2);
27133 newsize
= relax_immediate (fragp
, 5, 2);
27137 newsize
= relax_immediate (fragp
, 5, 1);
27141 newsize
= relax_immediate (fragp
, 5, 0);
27144 newsize
= relax_adr (fragp
, sec
, stretch
);
27150 newsize
= relax_immediate (fragp
, 8, 0);
27153 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27156 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27158 case T_MNEM_add_sp
:
27159 case T_MNEM_add_pc
:
27160 newsize
= relax_immediate (fragp
, 8, 2);
27162 case T_MNEM_inc_sp
:
27163 case T_MNEM_dec_sp
:
27164 newsize
= relax_immediate (fragp
, 7, 2);
27170 newsize
= relax_addsub (fragp
, sec
);
27176 fragp
->fr_var
= newsize
;
27177 /* Freeze wide instructions that are at or before the same location as
27178 in the previous pass. This avoids infinite loops.
27179 Don't freeze them unconditionally because targets may be artificially
27180 misaligned by the expansion of preceding frags. */
27181 if (stretch
<= 0 && newsize
> 2)
27183 md_convert_frag (sec
->owner
, sec
, fragp
);
27187 return newsize
- oldsize
;
27190 /* Round up a section size to the appropriate boundary. */
27193 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27199 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27200 of an rs_align_code fragment. */
27203 arm_handle_align (fragS
* fragP
)
27205 static unsigned char const arm_noop
[2][2][4] =
27208 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27209 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27212 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27213 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27216 static unsigned char const thumb_noop
[2][2][2] =
27219 {0xc0, 0x46}, /* LE */
27220 {0x46, 0xc0}, /* BE */
27223 {0x00, 0xbf}, /* LE */
27224 {0xbf, 0x00} /* BE */
27227 static unsigned char const wide_thumb_noop
[2][4] =
27228 { /* Wide Thumb-2 */
27229 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27230 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27233 unsigned bytes
, fix
, noop_size
;
27235 const unsigned char * noop
;
27236 const unsigned char *narrow_noop
= NULL
;
27241 if (fragP
->fr_type
!= rs_align_code
)
27244 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27245 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27248 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27249 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27251 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27253 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27255 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27256 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27258 narrow_noop
= thumb_noop
[1][target_big_endian
];
27259 noop
= wide_thumb_noop
[target_big_endian
];
27262 noop
= thumb_noop
[0][target_big_endian
];
27270 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27271 ? selected_cpu
: arm_arch_none
,
27273 [target_big_endian
];
27280 fragP
->fr_var
= noop_size
;
27282 if (bytes
& (noop_size
- 1))
27284 fix
= bytes
& (noop_size
- 1);
27286 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27288 memset (p
, 0, fix
);
27295 if (bytes
& noop_size
)
27297 /* Insert a narrow noop. */
27298 memcpy (p
, narrow_noop
, noop_size
);
27300 bytes
-= noop_size
;
27304 /* Use wide noops for the remainder */
27308 while (bytes
>= noop_size
)
27310 memcpy (p
, noop
, noop_size
);
27312 bytes
-= noop_size
;
27316 fragP
->fr_fix
+= fix
;
27319 /* Called from md_do_align. Used to create an alignment
27320 frag in a code section. */
27323 arm_frag_align_code (int n
, int max
)
27327 /* We assume that there will never be a requirement
27328 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27329 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27334 _("alignments greater than %d bytes not supported in .text sections."),
27335 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27336 as_fatal ("%s", err_msg
);
27339 p
= frag_var (rs_align_code
,
27340 MAX_MEM_FOR_RS_ALIGN_CODE
,
27342 (relax_substateT
) max
,
27349 /* Perform target specific initialisation of a frag.
27350 Note - despite the name this initialisation is not done when the frag
27351 is created, but only when its type is assigned. A frag can be created
27352 and used a long time before its type is set, so beware of assuming that
27353 this initialisation is performed first. */
27357 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27359 /* Record whether this frag is in an ARM or a THUMB area. */
27360 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27363 #else /* OBJ_ELF is defined. */
27365 arm_init_frag (fragS
* fragP
, int max_chars
)
27367 bfd_boolean frag_thumb_mode
;
27369 /* If the current ARM vs THUMB mode has not already
27370 been recorded into this frag then do so now. */
27371 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27372 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27374 /* PR 21809: Do not set a mapping state for debug sections
27375 - it just confuses other tools. */
27376 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27379 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27381 /* Record a mapping symbol for alignment frags. We will delete this
27382 later if the alignment ends up empty. */
27383 switch (fragP
->fr_type
)
27386 case rs_align_test
:
27388 mapping_state_2 (MAP_DATA
, max_chars
);
27390 case rs_align_code
:
27391 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27398 /* When we change sections we need to issue a new mapping symbol. */
27401 arm_elf_change_section (void)
27403 /* Link an unlinked unwind index table section to the .text section. */
27404 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27405 && elf_linked_to_section (now_seg
) == NULL
)
27406 elf_linked_to_section (now_seg
) = text_section
;
27410 arm_elf_section_type (const char * str
, size_t len
)
27412 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27413 return SHT_ARM_EXIDX
;
27418 /* Code to deal with unwinding tables. */
27420 static void add_unwind_adjustsp (offsetT
);
27422 /* Generate any deferred unwind frame offset. */
27425 flush_pending_unwind (void)
27429 offset
= unwind
.pending_offset
;
27430 unwind
.pending_offset
= 0;
27432 add_unwind_adjustsp (offset
);
27435 /* Add an opcode to this list for this function. Two-byte opcodes should
27436 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27440 add_unwind_opcode (valueT op
, int length
)
27442 /* Add any deferred stack adjustment. */
27443 if (unwind
.pending_offset
)
27444 flush_pending_unwind ();
27446 unwind
.sp_restored
= 0;
27448 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27450 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27451 if (unwind
.opcodes
)
27452 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27453 unwind
.opcode_alloc
);
27455 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27460 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27462 unwind
.opcode_count
++;
27466 /* Add unwind opcodes to adjust the stack pointer. */
27469 add_unwind_adjustsp (offsetT offset
)
27473 if (offset
> 0x200)
27475 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27480 /* Long form: 0xb2, uleb128. */
27481 /* This might not fit in a word so add the individual bytes,
27482 remembering the list is built in reverse order. */
27483 o
= (valueT
) ((offset
- 0x204) >> 2);
27485 add_unwind_opcode (0, 1);
27487 /* Calculate the uleb128 encoding of the offset. */
27491 bytes
[n
] = o
& 0x7f;
27497 /* Add the insn. */
27499 add_unwind_opcode (bytes
[n
- 1], 1);
27500 add_unwind_opcode (0xb2, 1);
27502 else if (offset
> 0x100)
27504 /* Two short opcodes. */
27505 add_unwind_opcode (0x3f, 1);
27506 op
= (offset
- 0x104) >> 2;
27507 add_unwind_opcode (op
, 1);
27509 else if (offset
> 0)
27511 /* Short opcode. */
27512 op
= (offset
- 4) >> 2;
27513 add_unwind_opcode (op
, 1);
27515 else if (offset
< 0)
27518 while (offset
> 0x100)
27520 add_unwind_opcode (0x7f, 1);
27523 op
= ((offset
- 4) >> 2) | 0x40;
27524 add_unwind_opcode (op
, 1);
27528 /* Finish the list of unwind opcodes for this function. */
27531 finish_unwind_opcodes (void)
27535 if (unwind
.fp_used
)
27537 /* Adjust sp as necessary. */
27538 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27539 flush_pending_unwind ();
27541 /* After restoring sp from the frame pointer. */
27542 op
= 0x90 | unwind
.fp_reg
;
27543 add_unwind_opcode (op
, 1);
27546 flush_pending_unwind ();
27550 /* Start an exception table entry. If idx is nonzero this is an index table
27554 start_unwind_section (const segT text_seg
, int idx
)
27556 const char * text_name
;
27557 const char * prefix
;
27558 const char * prefix_once
;
27559 struct elf_section_match match
;
27567 prefix
= ELF_STRING_ARM_unwind
;
27568 prefix_once
= ELF_STRING_ARM_unwind_once
;
27569 type
= SHT_ARM_EXIDX
;
27573 prefix
= ELF_STRING_ARM_unwind_info
;
27574 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27575 type
= SHT_PROGBITS
;
27578 text_name
= segment_name (text_seg
);
27579 if (streq (text_name
, ".text"))
27582 if (strncmp (text_name
, ".gnu.linkonce.t.",
27583 strlen (".gnu.linkonce.t.")) == 0)
27585 prefix
= prefix_once
;
27586 text_name
+= strlen (".gnu.linkonce.t.");
27589 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27593 memset (&match
, 0, sizeof (match
));
27595 /* Handle COMDAT group. */
27596 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27598 match
.group_name
= elf_group_name (text_seg
);
27599 if (match
.group_name
== NULL
)
27601 as_bad (_("Group section `%s' has no group signature"),
27602 segment_name (text_seg
));
27603 ignore_rest_of_line ();
27606 flags
|= SHF_GROUP
;
27610 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27613 /* Set the section link for index tables. */
27615 elf_linked_to_section (now_seg
) = text_seg
;
27619 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27620 personality routine data. Returns zero, or the index table value for
27621 an inline entry. */
27624 create_unwind_entry (int have_data
)
27629 /* The current word of data. */
27631 /* The number of bytes left in this word. */
27634 finish_unwind_opcodes ();
27636 /* Remember the current text section. */
27637 unwind
.saved_seg
= now_seg
;
27638 unwind
.saved_subseg
= now_subseg
;
27640 start_unwind_section (now_seg
, 0);
27642 if (unwind
.personality_routine
== NULL
)
27644 if (unwind
.personality_index
== -2)
27647 as_bad (_("handlerdata in cantunwind frame"));
27648 return 1; /* EXIDX_CANTUNWIND. */
27651 /* Use a default personality routine if none is specified. */
27652 if (unwind
.personality_index
== -1)
27654 if (unwind
.opcode_count
> 3)
27655 unwind
.personality_index
= 1;
27657 unwind
.personality_index
= 0;
27660 /* Space for the personality routine entry. */
27661 if (unwind
.personality_index
== 0)
27663 if (unwind
.opcode_count
> 3)
27664 as_bad (_("too many unwind opcodes for personality routine 0"));
27668 /* All the data is inline in the index table. */
27671 while (unwind
.opcode_count
> 0)
27673 unwind
.opcode_count
--;
27674 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27678 /* Pad with "finish" opcodes. */
27680 data
= (data
<< 8) | 0xb0;
27687 /* We get two opcodes "free" in the first word. */
27688 size
= unwind
.opcode_count
- 2;
27692 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27693 if (unwind
.personality_index
!= -1)
27695 as_bad (_("attempt to recreate an unwind entry"));
27699 /* An extra byte is required for the opcode count. */
27700 size
= unwind
.opcode_count
+ 1;
27703 size
= (size
+ 3) >> 2;
27705 as_bad (_("too many unwind opcodes"));
27707 frag_align (2, 0, 0);
27708 record_alignment (now_seg
, 2);
27709 unwind
.table_entry
= expr_build_dot ();
27711 /* Allocate the table entry. */
27712 ptr
= frag_more ((size
<< 2) + 4);
27713 /* PR 13449: Zero the table entries in case some of them are not used. */
27714 memset (ptr
, 0, (size
<< 2) + 4);
27715 where
= frag_now_fix () - ((size
<< 2) + 4);
27717 switch (unwind
.personality_index
)
27720 /* ??? Should this be a PLT generating relocation? */
27721 /* Custom personality routine. */
27722 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27723 BFD_RELOC_ARM_PREL31
);
27728 /* Set the first byte to the number of additional words. */
27729 data
= size
> 0 ? size
- 1 : 0;
27733 /* ABI defined personality routines. */
27735 /* Three opcodes bytes are packed into the first word. */
27742 /* The size and first two opcode bytes go in the first word. */
27743 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27748 /* Should never happen. */
27752 /* Pack the opcodes into words (MSB first), reversing the list at the same
27754 while (unwind
.opcode_count
> 0)
27758 md_number_to_chars (ptr
, data
, 4);
27763 unwind
.opcode_count
--;
27765 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27768 /* Finish off the last word. */
27771 /* Pad with "finish" opcodes. */
27773 data
= (data
<< 8) | 0xb0;
27775 md_number_to_chars (ptr
, data
, 4);
27780 /* Add an empty descriptor if there is no user-specified data. */
27781 ptr
= frag_more (4);
27782 md_number_to_chars (ptr
, 0, 4);
27789 /* Initialize the DWARF-2 unwind information for this procedure. */
27792 tc_arm_frame_initial_instructions (void)
27794 cfi_add_CFA_def_cfa (REG_SP
, 0);
27796 #endif /* OBJ_ELF */
27798 /* Convert REGNAME to a DWARF-2 register number. */
27801 tc_arm_regname_to_dw2regnum (char *regname
)
27803 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27807 /* PR 16694: Allow VFP registers as well. */
27808 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27812 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27821 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27825 exp
.X_op
= O_secrel
;
27826 exp
.X_add_symbol
= symbol
;
27827 exp
.X_add_number
= 0;
27828 emit_expr (&exp
, size
);
27832 /* MD interface: Symbol and relocation handling. */
27834 /* Return the address within the segment that a PC-relative fixup is
27835 relative to. For ARM, PC-relative fixups applied to instructions
27836 are generally relative to the location of the fixup plus 8 bytes.
27837 Thumb branches are offset by 4, and Thumb loads relative to PC
27838 require special handling. */
27841 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27843 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27845 /* If this is pc-relative and we are going to emit a relocation
27846 then we just want to put out any pipeline compensation that the linker
27847 will need. Otherwise we want to use the calculated base.
27848 For WinCE we skip the bias for externals as well, since this
27849 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27851 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27852 || (arm_force_relocation (fixP
)
27854 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27860 switch (fixP
->fx_r_type
)
27862 /* PC relative addressing on the Thumb is slightly odd as the
27863 bottom two bits of the PC are forced to zero for the
27864 calculation. This happens *after* application of the
27865 pipeline offset. However, Thumb adrl already adjusts for
27866 this, so we need not do it again. */
27867 case BFD_RELOC_ARM_THUMB_ADD
:
27870 case BFD_RELOC_ARM_THUMB_OFFSET
:
27871 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27872 case BFD_RELOC_ARM_T32_ADD_PC12
:
27873 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27874 return (base
+ 4) & ~3;
27876 /* Thumb branches are simply offset by +4. */
27877 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27878 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27879 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27880 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27881 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27882 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27883 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27884 case BFD_RELOC_ARM_THUMB_BF17
:
27885 case BFD_RELOC_ARM_THUMB_BF19
:
27886 case BFD_RELOC_ARM_THUMB_BF13
:
27887 case BFD_RELOC_ARM_THUMB_LOOP12
:
27890 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27892 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27893 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27894 && ARM_IS_FUNC (fixP
->fx_addsy
)
27895 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27896 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27899 /* BLX is like branches above, but forces the low two bits of PC to
27901 case BFD_RELOC_THUMB_PCREL_BLX
:
27903 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27904 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27905 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27906 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27907 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27908 return (base
+ 4) & ~3;
27910 /* ARM mode branches are offset by +8. However, the Windows CE
27911 loader expects the relocation not to take this into account. */
27912 case BFD_RELOC_ARM_PCREL_BLX
:
27914 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27915 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27916 && ARM_IS_FUNC (fixP
->fx_addsy
)
27917 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27918 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27921 case BFD_RELOC_ARM_PCREL_CALL
:
27923 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27924 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27925 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27926 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27927 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27930 case BFD_RELOC_ARM_PCREL_BRANCH
:
27931 case BFD_RELOC_ARM_PCREL_JUMP
:
27932 case BFD_RELOC_ARM_PLT32
:
27934 /* When handling fixups immediately, because we have already
27935 discovered the value of a symbol, or the address of the frag involved
27936 we must account for the offset by +8, as the OS loader will never see the reloc.
27937 see fixup_segment() in write.c
27938 The S_IS_EXTERNAL test handles the case of global symbols.
27939 Those need the calculated base, not just the pipe compensation the linker will need. */
27941 && fixP
->fx_addsy
!= NULL
27942 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27943 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27951 /* ARM mode loads relative to PC are also offset by +8. Unlike
27952 branches, the Windows CE loader *does* expect the relocation
27953 to take this into account. */
27954 case BFD_RELOC_ARM_OFFSET_IMM
:
27955 case BFD_RELOC_ARM_OFFSET_IMM8
:
27956 case BFD_RELOC_ARM_HWLITERAL
:
27957 case BFD_RELOC_ARM_LITERAL
:
27958 case BFD_RELOC_ARM_CP_OFF_IMM
:
27962 /* Other PC-relative relocations are un-offset. */
27968 static bfd_boolean flag_warn_syms
= TRUE
;
27971 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27973 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27974 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27975 does mean that the resulting code might be very confusing to the reader.
27976 Also this warning can be triggered if the user omits an operand before
27977 an immediate address, eg:
27981 GAS treats this as an assignment of the value of the symbol foo to a
27982 symbol LDR, and so (without this code) it will not issue any kind of
27983 warning or error message.
27985 Note - ARM instructions are case-insensitive but the strings in the hash
27986 table are all stored in lower case, so we must first ensure that name is
27988 if (flag_warn_syms
&& arm_ops_hsh
)
27990 char * nbuf
= strdup (name
);
27993 for (p
= nbuf
; *p
; p
++)
27995 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27997 static htab_t already_warned
= NULL
;
27999 if (already_warned
== NULL
)
28000 already_warned
= str_htab_create ();
28001 /* Only warn about the symbol once. To keep the code
28002 simple we let str_hash_insert do the lookup for us. */
28003 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28005 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28006 str_hash_insert (already_warned
, nbuf
, NULL
, 0);
28016 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28017 Otherwise we have no need to default values of symbols. */
28020 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28023 if (name
[0] == '_' && name
[1] == 'G'
28024 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28028 if (symbol_find (name
))
28029 as_bad (_("GOT already in the symbol table"));
28031 GOT_symbol
= symbol_new (name
, undefined_section
,
28032 &zero_address_frag
, 0);
28042 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28043 computed as two separate immediate values, added together. We
28044 already know that this value cannot be computed by just one ARM
28047 static unsigned int
28048 validate_immediate_twopart (unsigned int val
,
28049 unsigned int * highpart
)
28054 for (i
= 0; i
< 32; i
+= 2)
28055 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28061 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28063 else if (a
& 0xff0000)
28065 if (a
& 0xff000000)
28067 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28071 gas_assert (a
& 0xff000000);
28072 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28075 return (a
& 0xff) | (i
<< 7);
28082 validate_offset_imm (unsigned int val
, int hwse
)
28084 if ((hwse
&& val
> 255) || val
> 4095)
28089 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28090 negative immediate constant by altering the instruction. A bit of
28095 by inverting the second operand, and
28098 by negating the second operand. */
28101 negate_data_op (unsigned long * instruction
,
28102 unsigned long value
)
28105 unsigned long negated
, inverted
;
28107 negated
= encode_arm_immediate (-value
);
28108 inverted
= encode_arm_immediate (~value
);
28110 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28113 /* First negates. */
28114 case OPCODE_SUB
: /* ADD <-> SUB */
28115 new_inst
= OPCODE_ADD
;
28120 new_inst
= OPCODE_SUB
;
28124 case OPCODE_CMP
: /* CMP <-> CMN */
28125 new_inst
= OPCODE_CMN
;
28130 new_inst
= OPCODE_CMP
;
28134 /* Now Inverted ops. */
28135 case OPCODE_MOV
: /* MOV <-> MVN */
28136 new_inst
= OPCODE_MVN
;
28141 new_inst
= OPCODE_MOV
;
28145 case OPCODE_AND
: /* AND <-> BIC */
28146 new_inst
= OPCODE_BIC
;
28151 new_inst
= OPCODE_AND
;
28155 case OPCODE_ADC
: /* ADC <-> SBC */
28156 new_inst
= OPCODE_SBC
;
28161 new_inst
= OPCODE_ADC
;
28165 /* We cannot do anything. */
28170 if (value
== (unsigned) FAIL
)
28173 *instruction
&= OPCODE_MASK
;
28174 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28178 /* Like negate_data_op, but for Thumb-2. */
28180 static unsigned int
28181 thumb32_negate_data_op (valueT
*instruction
, unsigned int value
)
28183 unsigned int op
, new_inst
;
28185 unsigned int negated
, inverted
;
28187 negated
= encode_thumb32_immediate (-value
);
28188 inverted
= encode_thumb32_immediate (~value
);
28190 rd
= (*instruction
>> 8) & 0xf;
28191 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28194 /* ADD <-> SUB. Includes CMP <-> CMN. */
28195 case T2_OPCODE_SUB
:
28196 new_inst
= T2_OPCODE_ADD
;
28200 case T2_OPCODE_ADD
:
28201 new_inst
= T2_OPCODE_SUB
;
28205 /* ORR <-> ORN. Includes MOV <-> MVN. */
28206 case T2_OPCODE_ORR
:
28207 new_inst
= T2_OPCODE_ORN
;
28211 case T2_OPCODE_ORN
:
28212 new_inst
= T2_OPCODE_ORR
;
28216 /* AND <-> BIC. TST has no inverted equivalent. */
28217 case T2_OPCODE_AND
:
28218 new_inst
= T2_OPCODE_BIC
;
28225 case T2_OPCODE_BIC
:
28226 new_inst
= T2_OPCODE_AND
;
28231 case T2_OPCODE_ADC
:
28232 new_inst
= T2_OPCODE_SBC
;
28236 case T2_OPCODE_SBC
:
28237 new_inst
= T2_OPCODE_ADC
;
28241 /* We cannot do anything. */
28246 if (value
== (unsigned int)FAIL
)
28249 *instruction
&= T2_OPCODE_MASK
;
28250 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28254 /* Read a 32-bit thumb instruction from buf. */
28256 static unsigned long
28257 get_thumb32_insn (char * buf
)
28259 unsigned long insn
;
28260 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28261 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28266 /* We usually want to set the low bit on the address of thumb function
28267 symbols. In particular .word foo - . should have the low bit set.
28268 Generic code tries to fold the difference of two symbols to
28269 a constant. Prevent this and force a relocation when the first symbols
28270 is a thumb function. */
28273 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28275 if (op
== O_subtract
28276 && l
->X_op
== O_symbol
28277 && r
->X_op
== O_symbol
28278 && THUMB_IS_FUNC (l
->X_add_symbol
))
28280 l
->X_op
= O_subtract
;
28281 l
->X_op_symbol
= r
->X_add_symbol
;
28282 l
->X_add_number
-= r
->X_add_number
;
28286 /* Process as normal. */
28290 /* Encode Thumb2 unconditional branches and calls. The encoding
28291 for the 2 are identical for the immediate values. */
28294 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28296 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28299 addressT S
, I1
, I2
, lo
, hi
;
28301 S
= (value
>> 24) & 0x01;
28302 I1
= (value
>> 23) & 0x01;
28303 I2
= (value
>> 22) & 0x01;
28304 hi
= (value
>> 12) & 0x3ff;
28305 lo
= (value
>> 1) & 0x7ff;
28306 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28307 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28308 newval
|= (S
<< 10) | hi
;
28309 newval2
&= ~T2I1I2MASK
;
28310 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28311 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28312 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28316 md_apply_fix (fixS
* fixP
,
28320 valueT value
= * valP
;
28322 unsigned int newimm
;
28323 unsigned long temp
;
28325 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28327 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28329 /* Note whether this will delete the relocation. */
28331 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28334 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28335 consistency with the behaviour on 32-bit hosts. Remember value
28337 value
&= 0xffffffff;
28338 value
^= 0x80000000;
28339 value
-= 0x80000000;
28342 fixP
->fx_addnumber
= value
;
28344 /* Same treatment for fixP->fx_offset. */
28345 fixP
->fx_offset
&= 0xffffffff;
28346 fixP
->fx_offset
^= 0x80000000;
28347 fixP
->fx_offset
-= 0x80000000;
28349 switch (fixP
->fx_r_type
)
28351 case BFD_RELOC_NONE
:
28352 /* This will need to go in the object file. */
28356 case BFD_RELOC_ARM_IMMEDIATE
:
28357 /* We claim that this fixup has been processed here,
28358 even if in fact we generate an error because we do
28359 not have a reloc for it, so tc_gen_reloc will reject it. */
28362 if (fixP
->fx_addsy
)
28364 const char *msg
= 0;
28366 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28367 msg
= _("undefined symbol %s used as an immediate value");
28368 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28369 msg
= _("symbol %s is in a different section");
28370 else if (S_IS_WEAK (fixP
->fx_addsy
))
28371 msg
= _("symbol %s is weak and may be overridden later");
28375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28376 msg
, S_GET_NAME (fixP
->fx_addsy
));
28381 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28383 /* If the offset is negative, we should use encoding A2 for ADR. */
28384 if ((temp
& 0xfff0000) == 0x28f0000 && (offsetT
) value
< 0)
28385 newimm
= negate_data_op (&temp
, value
);
28388 newimm
= encode_arm_immediate (value
);
28390 /* If the instruction will fail, see if we can fix things up by
28391 changing the opcode. */
28392 if (newimm
== (unsigned int) FAIL
)
28393 newimm
= negate_data_op (&temp
, value
);
28394 /* MOV accepts both ARM modified immediate (A1 encoding) and
28395 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28396 When disassembling, MOV is preferred when there is no encoding
28398 if (newimm
== (unsigned int) FAIL
28399 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28400 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28401 && !((temp
>> SBIT_SHIFT
) & 0x1)
28402 && value
<= 0xffff)
28404 /* Clear bits[23:20] to change encoding from A1 to A2. */
28405 temp
&= 0xff0fffff;
28406 /* Encoding high 4bits imm. Code below will encode the remaining
28408 temp
|= (value
& 0x0000f000) << 4;
28409 newimm
= value
& 0x00000fff;
28413 if (newimm
== (unsigned int) FAIL
)
28415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28416 _("invalid constant (%lx) after fixup"),
28417 (unsigned long) value
);
28421 newimm
|= (temp
& 0xfffff000);
28422 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28425 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28427 unsigned int highpart
= 0;
28428 unsigned int newinsn
= 0xe1a00000; /* nop. */
28430 if (fixP
->fx_addsy
)
28432 const char *msg
= 0;
28434 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28435 msg
= _("undefined symbol %s used as an immediate value");
28436 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28437 msg
= _("symbol %s is in a different section");
28438 else if (S_IS_WEAK (fixP
->fx_addsy
))
28439 msg
= _("symbol %s is weak and may be overridden later");
28443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28444 msg
, S_GET_NAME (fixP
->fx_addsy
));
28449 newimm
= encode_arm_immediate (value
);
28450 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28452 /* If the instruction will fail, see if we can fix things up by
28453 changing the opcode. */
28454 if (newimm
== (unsigned int) FAIL
28455 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28457 /* No ? OK - try using two ADD instructions to generate
28459 newimm
= validate_immediate_twopart (value
, & highpart
);
28461 /* Yes - then make sure that the second instruction is
28463 if (newimm
!= (unsigned int) FAIL
)
28465 /* Still No ? Try using a negated value. */
28466 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28467 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28468 /* Otherwise - give up. */
28471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28472 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28477 /* Replace the first operand in the 2nd instruction (which
28478 is the PC) with the destination register. We have
28479 already added in the PC in the first instruction and we
28480 do not want to do it again. */
28481 newinsn
&= ~ 0xf0000;
28482 newinsn
|= ((newinsn
& 0x0f000) << 4);
28485 newimm
|= (temp
& 0xfffff000);
28486 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28488 highpart
|= (newinsn
& 0xfffff000);
28489 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28493 case BFD_RELOC_ARM_OFFSET_IMM
:
28494 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28496 /* Fall through. */
28498 case BFD_RELOC_ARM_LITERAL
:
28499 sign
= (offsetT
) value
> 0;
28501 if ((offsetT
) value
< 0)
28504 if (validate_offset_imm (value
, 0) == FAIL
)
28506 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28508 _("invalid literal constant: pool needs to be closer"));
28510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28511 _("bad immediate value for offset (%ld)"),
28516 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28518 newval
&= 0xfffff000;
28521 newval
&= 0xff7ff000;
28522 newval
|= value
| (sign
? INDEX_UP
: 0);
28524 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28527 case BFD_RELOC_ARM_OFFSET_IMM8
:
28528 case BFD_RELOC_ARM_HWLITERAL
:
28529 sign
= (offsetT
) value
> 0;
28531 if ((offsetT
) value
< 0)
28534 if (validate_offset_imm (value
, 1) == FAIL
)
28536 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28538 _("invalid literal constant: pool needs to be closer"));
28540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28541 _("bad immediate value for 8-bit offset (%ld)"),
28546 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28548 newval
&= 0xfffff0f0;
28551 newval
&= 0xff7ff0f0;
28552 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28554 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28557 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28558 if (value
> 1020 || value
% 4 != 0)
28559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28560 _("bad immediate value for offset (%ld)"), (long) value
);
28563 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28565 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28568 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28569 /* This is a complicated relocation used for all varieties of Thumb32
28570 load/store instruction with immediate offset:
28572 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28573 *4, optional writeback(W)
28574 (doubleword load/store)
28576 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28577 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28578 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28579 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28580 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28582 Uppercase letters indicate bits that are already encoded at
28583 this point. Lowercase letters are our problem. For the
28584 second block of instructions, the secondary opcode nybble
28585 (bits 8..11) is present, and bit 23 is zero, even if this is
28586 a PC-relative operation. */
28587 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28589 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28591 if ((newval
& 0xf0000000) == 0xe0000000)
28593 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28594 if ((offsetT
) value
>= 0)
28595 newval
|= (1 << 23);
28598 if (value
% 4 != 0)
28600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28601 _("offset not a multiple of 4"));
28607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28608 _("offset out of range"));
28613 else if ((newval
& 0x000f0000) == 0x000f0000)
28615 /* PC-relative, 12-bit offset. */
28616 if ((offsetT
) value
>= 0)
28617 newval
|= (1 << 23);
28622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28623 _("offset out of range"));
28628 else if ((newval
& 0x00000100) == 0x00000100)
28630 /* Writeback: 8-bit, +/- offset. */
28631 if ((offsetT
) value
>= 0)
28632 newval
|= (1 << 9);
28637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28638 _("offset out of range"));
28643 else if ((newval
& 0x00000f00) == 0x00000e00)
28645 /* T-instruction: positive 8-bit offset. */
28648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28649 _("offset out of range"));
28657 /* Positive 12-bit or negative 8-bit offset. */
28658 unsigned int limit
;
28659 if ((offsetT
) value
>= 0)
28661 newval
|= (1 << 23);
28671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28672 _("offset out of range"));
28679 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28680 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28683 case BFD_RELOC_ARM_SHIFT_IMM
:
28684 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28687 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28690 _("shift expression is too large"));
28695 /* Shifts of zero must be done as lsl. */
28697 else if (value
== 32)
28699 newval
&= 0xfffff07f;
28700 newval
|= (value
& 0x1f) << 7;
28701 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28704 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28705 case BFD_RELOC_ARM_T32_ADD_IMM
:
28706 case BFD_RELOC_ARM_T32_IMM12
:
28707 case BFD_RELOC_ARM_T32_ADD_PC12
:
28708 /* We claim that this fixup has been processed here,
28709 even if in fact we generate an error because we do
28710 not have a reloc for it, so tc_gen_reloc will reject it. */
28714 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28717 _("undefined symbol %s used as an immediate value"),
28718 S_GET_NAME (fixP
->fx_addsy
));
28722 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28724 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28727 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28728 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28729 Thumb2 modified immediate encoding (T2). */
28730 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28731 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28733 newimm
= encode_thumb32_immediate (value
);
28734 if (newimm
== (unsigned int) FAIL
)
28735 newimm
= thumb32_negate_data_op (&newval
, value
);
28737 if (newimm
== (unsigned int) FAIL
)
28739 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28741 /* Turn add/sum into addw/subw. */
28742 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28743 newval
= (newval
& 0xfeffffff) | 0x02000000;
28744 /* No flat 12-bit imm encoding for addsw/subsw. */
28745 if ((newval
& 0x00100000) == 0)
28747 /* 12 bit immediate for addw/subw. */
28748 if ((offsetT
) value
< 0)
28751 newval
^= 0x00a00000;
28754 newimm
= (unsigned int) FAIL
;
28761 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28762 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28763 disassembling, MOV is preferred when there is no encoding
28765 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28766 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28767 but with the Rn field [19:16] set to 1111. */
28768 && (((newval
>> 16) & 0xf) == 0xf)
28769 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28770 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28771 && value
<= 0xffff)
28773 /* Toggle bit[25] to change encoding from T2 to T3. */
28775 /* Clear bits[19:16]. */
28776 newval
&= 0xfff0ffff;
28777 /* Encoding high 4bits imm. Code below will encode the
28778 remaining low 12bits. */
28779 newval
|= (value
& 0x0000f000) << 4;
28780 newimm
= value
& 0x00000fff;
28785 if (newimm
== (unsigned int)FAIL
)
28787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28788 _("invalid constant (%lx) after fixup"),
28789 (unsigned long) value
);
28793 newval
|= (newimm
& 0x800) << 15;
28794 newval
|= (newimm
& 0x700) << 4;
28795 newval
|= (newimm
& 0x0ff);
28797 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28798 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28801 case BFD_RELOC_ARM_SMC
:
28803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28804 _("invalid smc expression"));
28806 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28807 newval
|= (value
& 0xf);
28808 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28811 case BFD_RELOC_ARM_HVC
:
28812 if (value
> 0xffff)
28813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28814 _("invalid hvc expression"));
28815 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28816 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28820 case BFD_RELOC_ARM_SWI
:
28821 if (fixP
->tc_fix_data
!= 0)
28824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28825 _("invalid swi expression"));
28826 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28828 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28832 if (value
> 0x00ffffff)
28833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28834 _("invalid swi expression"));
28835 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28837 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28841 case BFD_RELOC_ARM_MULTI
:
28842 if (value
> 0xffff)
28843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28844 _("invalid expression in load/store multiple"));
28845 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28846 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28850 case BFD_RELOC_ARM_PCREL_CALL
:
28852 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28854 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28855 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28856 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28857 /* Flip the bl to blx. This is a simple flip
28858 bit here because we generate PCREL_CALL for
28859 unconditional bls. */
28861 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28862 newval
= newval
| 0x10000000;
28863 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28869 goto arm_branch_common
;
28871 case BFD_RELOC_ARM_PCREL_JUMP
:
28872 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28874 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28875 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28876 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28878 /* This would map to a bl<cond>, b<cond>,
28879 b<always> to a Thumb function. We
28880 need to force a relocation for this particular
28882 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28885 /* Fall through. */
28887 case BFD_RELOC_ARM_PLT32
:
28889 case BFD_RELOC_ARM_PCREL_BRANCH
:
28891 goto arm_branch_common
;
28893 case BFD_RELOC_ARM_PCREL_BLX
:
28896 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28898 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28899 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28900 && ARM_IS_FUNC (fixP
->fx_addsy
))
28902 /* Flip the blx to a bl and warn. */
28903 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28904 newval
= 0xeb000000;
28905 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28906 _("blx to '%s' an ARM ISA state function changed to bl"),
28908 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28914 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28915 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28919 /* We are going to store value (shifted right by two) in the
28920 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28921 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28925 _("misaligned branch destination"));
28926 if ((value
& 0xfe000000) != 0
28927 && (value
& 0xfe000000) != 0xfe000000)
28928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28930 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28932 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28933 newval
|= (value
>> 2) & 0x00ffffff;
28934 /* Set the H bit on BLX instructions. */
28938 newval
|= 0x01000000;
28940 newval
&= ~0x01000000;
28942 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28946 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28947 /* CBZ can only branch forward. */
28949 /* Attempts to use CBZ to branch to the next instruction
28950 (which, strictly speaking, are prohibited) will be turned into
28953 FIXME: It may be better to remove the instruction completely and
28954 perform relaxation. */
28955 if ((offsetT
) value
== -2)
28957 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28958 newval
= 0xbf00; /* NOP encoding T1 */
28959 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28966 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28968 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28969 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28970 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28975 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28976 if (out_of_range_p (value
, 8))
28977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28979 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28981 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28982 newval
|= (value
& 0x1ff) >> 1;
28983 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28987 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28988 if (out_of_range_p (value
, 11))
28989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28991 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28993 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28994 newval
|= (value
& 0xfff) >> 1;
28995 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28999 /* This relocation is misnamed, it should be BRANCH21. */
29000 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29002 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29003 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29004 && ARM_IS_FUNC (fixP
->fx_addsy
)
29005 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29007 /* Force a relocation for a branch 20 bits wide. */
29010 if (out_of_range_p (value
, 20))
29011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29012 _("conditional branch out of range"));
29014 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29017 addressT S
, J1
, J2
, lo
, hi
;
29019 S
= (value
& 0x00100000) >> 20;
29020 J2
= (value
& 0x00080000) >> 19;
29021 J1
= (value
& 0x00040000) >> 18;
29022 hi
= (value
& 0x0003f000) >> 12;
29023 lo
= (value
& 0x00000ffe) >> 1;
29025 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29026 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29027 newval
|= (S
<< 10) | hi
;
29028 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29029 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29030 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29034 case BFD_RELOC_THUMB_PCREL_BLX
:
29035 /* If there is a blx from a thumb state function to
29036 another thumb function flip this to a bl and warn
29040 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29041 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29042 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29044 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29045 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29046 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29048 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29049 newval
= newval
| 0x1000;
29050 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29051 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29056 goto thumb_bl_common
;
29058 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29059 /* A bl from Thumb state ISA to an internal ARM state function
29060 is converted to a blx. */
29062 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29063 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29064 && ARM_IS_FUNC (fixP
->fx_addsy
)
29065 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29067 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29068 newval
= newval
& ~0x1000;
29069 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29070 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29076 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29077 /* For a BLX instruction, make sure that the relocation is rounded up
29078 to a word boundary. This follows the semantics of the instruction
29079 which specifies that bit 1 of the target address will come from bit
29080 1 of the base address. */
29081 value
= (value
+ 3) & ~ 3;
29084 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29085 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29086 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29089 if (out_of_range_p (value
, 22))
29091 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29093 else if (out_of_range_p (value
, 24))
29094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29095 _("Thumb2 branch out of range"));
29098 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29099 encode_thumb2_b_bl_offset (buf
, value
);
29103 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29104 if (out_of_range_p (value
, 24))
29105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29107 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29108 encode_thumb2_b_bl_offset (buf
, value
);
29113 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29118 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29119 md_number_to_chars (buf
, value
, 2);
29123 case BFD_RELOC_ARM_TLS_CALL
:
29124 case BFD_RELOC_ARM_THM_TLS_CALL
:
29125 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29126 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29127 case BFD_RELOC_ARM_TLS_GOTDESC
:
29128 case BFD_RELOC_ARM_TLS_GD32
:
29129 case BFD_RELOC_ARM_TLS_LE32
:
29130 case BFD_RELOC_ARM_TLS_IE32
:
29131 case BFD_RELOC_ARM_TLS_LDM32
:
29132 case BFD_RELOC_ARM_TLS_LDO32
:
29133 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29136 /* Same handling as above, but with the arm_fdpic guard. */
29137 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29138 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29139 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29142 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29147 _("Relocation supported only in FDPIC mode"));
29151 case BFD_RELOC_ARM_GOT32
:
29152 case BFD_RELOC_ARM_GOTOFF
:
29155 case BFD_RELOC_ARM_GOT_PREL
:
29156 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29157 md_number_to_chars (buf
, value
, 4);
29160 case BFD_RELOC_ARM_TARGET2
:
29161 /* TARGET2 is not partial-inplace, so we need to write the
29162 addend here for REL targets, because it won't be written out
29163 during reloc processing later. */
29164 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29165 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29168 /* Relocations for FDPIC. */
29169 case BFD_RELOC_ARM_GOTFUNCDESC
:
29170 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29171 case BFD_RELOC_ARM_FUNCDESC
:
29174 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29175 md_number_to_chars (buf
, 0, 4);
29179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29180 _("Relocation supported only in FDPIC mode"));
29185 case BFD_RELOC_RVA
:
29187 case BFD_RELOC_ARM_TARGET1
:
29188 case BFD_RELOC_ARM_ROSEGREL32
:
29189 case BFD_RELOC_ARM_SBREL32
:
29190 case BFD_RELOC_32_PCREL
:
29192 case BFD_RELOC_32_SECREL
:
29194 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29196 /* For WinCE we only do this for pcrel fixups. */
29197 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29199 md_number_to_chars (buf
, value
, 4);
29203 case BFD_RELOC_ARM_PREL31
:
29204 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29206 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29207 if ((value
^ (value
>> 1)) & 0x40000000)
29209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29210 _("rel31 relocation overflow"));
29212 newval
|= value
& 0x7fffffff;
29213 md_number_to_chars (buf
, newval
, 4);
29218 case BFD_RELOC_ARM_CP_OFF_IMM
:
29219 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29220 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29221 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29222 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29224 newval
= get_thumb32_insn (buf
);
29225 if ((newval
& 0x0f200f00) == 0x0d000900)
29227 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29228 has permitted values that are multiples of 2, in the range -510
29230 if (value
+ 510 > 510 + 510 || (value
& 1))
29231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29232 _("co-processor offset out of range"));
29234 else if ((newval
& 0xfe001f80) == 0xec000f80)
29236 if (value
+ 511 > 512 + 511 || (value
& 3))
29237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29238 _("co-processor offset out of range"));
29240 else if (value
+ 1023 > 1023 + 1023 || (value
& 3))
29241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29242 _("co-processor offset out of range"));
29244 sign
= (offsetT
) value
> 0;
29245 if ((offsetT
) value
< 0)
29247 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29248 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29249 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29251 newval
= get_thumb32_insn (buf
);
29254 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29255 newval
&= 0xffffff80;
29257 newval
&= 0xffffff00;
29261 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29262 newval
&= 0xff7fff80;
29264 newval
&= 0xff7fff00;
29265 if ((newval
& 0x0f200f00) == 0x0d000900)
29267 /* This is a fp16 vstr/vldr.
29269 It requires the immediate offset in the instruction is shifted
29270 left by 1 to be a half-word offset.
29272 Here, left shift by 1 first, and later right shift by 2
29273 should get the right offset. */
29276 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29278 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29279 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29280 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29282 put_thumb32_insn (buf
, newval
);
29285 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29286 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29287 if (value
+ 255 > 255 + 255)
29288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29289 _("co-processor offset out of range"));
29291 goto cp_off_common
;
29293 case BFD_RELOC_ARM_THUMB_OFFSET
:
29294 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29295 /* Exactly what ranges, and where the offset is inserted depends
29296 on the type of instruction, we can establish this from the
29298 switch (newval
>> 12)
29300 case 4: /* PC load. */
29301 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29302 forced to zero for these loads; md_pcrel_from has already
29303 compensated for this. */
29305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29306 _("invalid offset, target not word aligned (0x%08lX)"),
29307 (((unsigned long) fixP
->fx_frag
->fr_address
29308 + (unsigned long) fixP
->fx_where
) & ~3)
29309 + (unsigned long) value
);
29310 else if (get_recorded_alignment (seg
) < 2)
29311 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29312 _("section does not have enough alignment to ensure safe PC-relative loads"));
29314 if (value
& ~0x3fc)
29315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29316 _("invalid offset, value too big (0x%08lX)"),
29319 newval
|= value
>> 2;
29322 case 9: /* SP load/store. */
29323 if (value
& ~0x3fc)
29324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29325 _("invalid offset, value too big (0x%08lX)"),
29327 newval
|= value
>> 2;
29330 case 6: /* Word load/store. */
29332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29333 _("invalid offset, value too big (0x%08lX)"),
29335 newval
|= value
<< 4; /* 6 - 2. */
29338 case 7: /* Byte load/store. */
29340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29341 _("invalid offset, value too big (0x%08lX)"),
29343 newval
|= value
<< 6;
29346 case 8: /* Halfword load/store. */
29348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29349 _("invalid offset, value too big (0x%08lX)"),
29351 newval
|= value
<< 5; /* 6 - 1. */
29355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29356 "Unable to process relocation for thumb opcode: %lx",
29357 (unsigned long) newval
);
29360 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29363 case BFD_RELOC_ARM_THUMB_ADD
:
29364 /* This is a complicated relocation, since we use it for all of
29365 the following immediate relocations:
29369 9bit ADD/SUB SP word-aligned
29370 10bit ADD PC/SP word-aligned
29372 The type of instruction being processed is encoded in the
29379 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29381 int rd
= (newval
>> 4) & 0xf;
29382 int rs
= newval
& 0xf;
29383 int subtract
= !!(newval
& 0x8000);
29385 /* Check for HI regs, only very restricted cases allowed:
29386 Adjusting SP, and using PC or SP to get an address. */
29387 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29388 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29390 _("invalid Hi register with immediate"));
29392 /* If value is negative, choose the opposite instruction. */
29393 if ((offsetT
) value
< 0)
29396 subtract
= !subtract
;
29397 if ((offsetT
) value
< 0)
29398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29399 _("immediate value out of range"));
29404 if (value
& ~0x1fc)
29405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29406 _("invalid immediate for stack address calculation"));
29407 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29408 newval
|= value
>> 2;
29410 else if (rs
== REG_PC
|| rs
== REG_SP
)
29412 /* PR gas/18541. If the addition is for a defined symbol
29413 within range of an ADR instruction then accept it. */
29416 && fixP
->fx_addsy
!= NULL
)
29420 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29421 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29422 || S_IS_WEAK (fixP
->fx_addsy
))
29424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29425 _("address calculation needs a strongly defined nearby symbol"));
29429 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29431 /* Round up to the next 4-byte boundary. */
29436 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29441 _("symbol too far away"));
29451 if (subtract
|| value
& ~0x3fc)
29452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29453 _("invalid immediate for address calculation (value = 0x%08lX)"),
29454 (unsigned long) (subtract
? - value
: value
));
29455 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29457 newval
|= value
>> 2;
29462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29463 _("immediate value out of range"));
29464 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29465 newval
|= (rd
<< 8) | value
;
29470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29471 _("immediate value out of range"));
29472 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29473 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29476 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29479 case BFD_RELOC_ARM_THUMB_IMM
:
29480 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29483 _("invalid immediate: %ld is out of range"),
29486 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29489 case BFD_RELOC_ARM_THUMB_SHIFT
:
29490 /* 5bit shift value (0..32). LSL cannot take 32. */
29491 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29492 temp
= newval
& 0xf800;
29493 if (value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29495 _("invalid shift value: %ld"), (long) value
);
29496 /* Shifts of zero must be encoded as LSL. */
29498 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29499 /* Shifts of 32 are encoded as zero. */
29500 else if (value
== 32)
29502 newval
|= value
<< 6;
29503 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29506 case BFD_RELOC_VTABLE_INHERIT
:
29507 case BFD_RELOC_VTABLE_ENTRY
:
29511 case BFD_RELOC_ARM_MOVW
:
29512 case BFD_RELOC_ARM_MOVT
:
29513 case BFD_RELOC_ARM_THUMB_MOVW
:
29514 case BFD_RELOC_ARM_THUMB_MOVT
:
29515 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29517 /* REL format relocations are limited to a 16-bit addend. */
29518 if (!fixP
->fx_done
)
29520 if (value
+ 0x8000 > 0x7fff + 0x8000)
29521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29522 _("offset out of range"));
29524 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29525 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29530 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29531 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29533 newval
= get_thumb32_insn (buf
);
29534 newval
&= 0xfbf08f00;
29535 newval
|= (value
& 0xf000) << 4;
29536 newval
|= (value
& 0x0800) << 15;
29537 newval
|= (value
& 0x0700) << 4;
29538 newval
|= (value
& 0x00ff);
29539 put_thumb32_insn (buf
, newval
);
29543 newval
= md_chars_to_number (buf
, 4);
29544 newval
&= 0xfff0f000;
29545 newval
|= value
& 0x0fff;
29546 newval
|= (value
& 0xf000) << 4;
29547 md_number_to_chars (buf
, newval
, 4);
29552 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29553 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29554 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29555 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29556 gas_assert (!fixP
->fx_done
);
29559 bfd_boolean is_mov
;
29560 bfd_vma encoded_addend
= value
;
29562 /* Check that addend can be encoded in instruction. */
29563 if (!seg
->use_rela_p
&& value
> 255)
29564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29565 _("the offset 0x%08lX is not representable"),
29566 (unsigned long) encoded_addend
);
29568 /* Extract the instruction. */
29569 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29570 is_mov
= (insn
& 0xf800) == 0x2000;
29575 if (!seg
->use_rela_p
)
29576 insn
|= encoded_addend
;
29582 /* Extract the instruction. */
29583 /* Encoding is the following
29588 /* The following conditions must be true :
29593 rd
= (insn
>> 4) & 0xf;
29595 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29597 _("Unable to process relocation for thumb opcode: %lx"),
29598 (unsigned long) insn
);
29600 /* Encode as ADD immediate8 thumb 1 code. */
29601 insn
= 0x3000 | (rd
<< 8);
29603 /* Place the encoded addend into the first 8 bits of the
29605 if (!seg
->use_rela_p
)
29606 insn
|= encoded_addend
;
29609 /* Update the instruction. */
29610 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29614 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29615 case BFD_RELOC_ARM_ALU_PC_G0
:
29616 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29617 case BFD_RELOC_ARM_ALU_PC_G1
:
29618 case BFD_RELOC_ARM_ALU_PC_G2
:
29619 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29620 case BFD_RELOC_ARM_ALU_SB_G0
:
29621 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29622 case BFD_RELOC_ARM_ALU_SB_G1
:
29623 case BFD_RELOC_ARM_ALU_SB_G2
:
29624 gas_assert (!fixP
->fx_done
);
29625 if (!seg
->use_rela_p
)
29628 bfd_vma encoded_addend
;
29629 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29631 /* Check that the absolute value of the addend can be
29632 expressed as an 8-bit constant plus a rotation. */
29633 encoded_addend
= encode_arm_immediate (addend_abs
);
29634 if (encoded_addend
== (unsigned int) FAIL
)
29635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29636 _("the offset 0x%08lX is not representable"),
29637 (unsigned long) addend_abs
);
29639 /* Extract the instruction. */
29640 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29642 /* If the addend is positive, use an ADD instruction.
29643 Otherwise use a SUB. Take care not to destroy the S bit. */
29644 insn
&= 0xff1fffff;
29645 if ((offsetT
) value
< 0)
29650 /* Place the encoded addend into the first 12 bits of the
29652 insn
&= 0xfffff000;
29653 insn
|= encoded_addend
;
29655 /* Update the instruction. */
29656 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29660 case BFD_RELOC_ARM_LDR_PC_G0
:
29661 case BFD_RELOC_ARM_LDR_PC_G1
:
29662 case BFD_RELOC_ARM_LDR_PC_G2
:
29663 case BFD_RELOC_ARM_LDR_SB_G0
:
29664 case BFD_RELOC_ARM_LDR_SB_G1
:
29665 case BFD_RELOC_ARM_LDR_SB_G2
:
29666 gas_assert (!fixP
->fx_done
);
29667 if (!seg
->use_rela_p
)
29670 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29672 /* Check that the absolute value of the addend can be
29673 encoded in 12 bits. */
29674 if (addend_abs
>= 0x1000)
29675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29676 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29677 (unsigned long) addend_abs
);
29679 /* Extract the instruction. */
29680 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29682 /* If the addend is negative, clear bit 23 of the instruction.
29683 Otherwise set it. */
29684 if ((offsetT
) value
< 0)
29685 insn
&= ~(1 << 23);
29689 /* Place the absolute value of the addend into the first 12 bits
29690 of the instruction. */
29691 insn
&= 0xfffff000;
29692 insn
|= addend_abs
;
29694 /* Update the instruction. */
29695 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29699 case BFD_RELOC_ARM_LDRS_PC_G0
:
29700 case BFD_RELOC_ARM_LDRS_PC_G1
:
29701 case BFD_RELOC_ARM_LDRS_PC_G2
:
29702 case BFD_RELOC_ARM_LDRS_SB_G0
:
29703 case BFD_RELOC_ARM_LDRS_SB_G1
:
29704 case BFD_RELOC_ARM_LDRS_SB_G2
:
29705 gas_assert (!fixP
->fx_done
);
29706 if (!seg
->use_rela_p
)
29709 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29711 /* Check that the absolute value of the addend can be
29712 encoded in 8 bits. */
29713 if (addend_abs
>= 0x100)
29714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29715 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29716 (unsigned long) addend_abs
);
29718 /* Extract the instruction. */
29719 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29721 /* If the addend is negative, clear bit 23 of the instruction.
29722 Otherwise set it. */
29723 if ((offsetT
) value
< 0)
29724 insn
&= ~(1 << 23);
29728 /* Place the first four bits of the absolute value of the addend
29729 into the first 4 bits of the instruction, and the remaining
29730 four into bits 8 .. 11. */
29731 insn
&= 0xfffff0f0;
29732 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29734 /* Update the instruction. */
29735 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29739 case BFD_RELOC_ARM_LDC_PC_G0
:
29740 case BFD_RELOC_ARM_LDC_PC_G1
:
29741 case BFD_RELOC_ARM_LDC_PC_G2
:
29742 case BFD_RELOC_ARM_LDC_SB_G0
:
29743 case BFD_RELOC_ARM_LDC_SB_G1
:
29744 case BFD_RELOC_ARM_LDC_SB_G2
:
29745 gas_assert (!fixP
->fx_done
);
29746 if (!seg
->use_rela_p
)
29749 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29751 /* Check that the absolute value of the addend is a multiple of
29752 four and, when divided by four, fits in 8 bits. */
29753 if (addend_abs
& 0x3)
29754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29755 _("bad offset 0x%08lX (must be word-aligned)"),
29756 (unsigned long) addend_abs
);
29758 if ((addend_abs
>> 2) > 0xff)
29759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29760 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29761 (unsigned long) addend_abs
);
29763 /* Extract the instruction. */
29764 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29766 /* If the addend is negative, clear bit 23 of the instruction.
29767 Otherwise set it. */
29768 if ((offsetT
) value
< 0)
29769 insn
&= ~(1 << 23);
29773 /* Place the addend (divided by four) into the first eight
29774 bits of the instruction. */
29775 insn
&= 0xfffffff0;
29776 insn
|= addend_abs
>> 2;
29778 /* Update the instruction. */
29779 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29783 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29785 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29786 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29787 && ARM_IS_FUNC (fixP
->fx_addsy
)
29788 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29790 /* Force a relocation for a branch 5 bits wide. */
29793 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29797 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29799 addressT boff
= value
>> 1;
29801 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29802 newval
|= (boff
<< 7);
29803 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29807 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29809 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29810 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29811 && ARM_IS_FUNC (fixP
->fx_addsy
)
29812 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29816 if ((value
& ~0x7f) && ((value
& ~0x3f) != (valueT
) ~0x3f))
29817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29818 _("branch out of range"));
29820 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29822 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29824 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29825 addressT diff
= value
- boff
;
29829 newval
|= 1 << 1; /* T bit. */
29831 else if (diff
!= 2)
29833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29834 _("out of range label-relative fixup value"));
29836 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29840 case BFD_RELOC_ARM_THUMB_BF17
:
29842 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29843 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29844 && ARM_IS_FUNC (fixP
->fx_addsy
)
29845 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29847 /* Force a relocation for a branch 17 bits wide. */
29851 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29855 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29858 addressT immA
, immB
, immC
;
29860 immA
= (value
& 0x0001f000) >> 12;
29861 immB
= (value
& 0x00000ffc) >> 2;
29862 immC
= (value
& 0x00000002) >> 1;
29864 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29865 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29867 newval2
|= (immC
<< 11) | (immB
<< 1);
29868 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29869 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29873 case BFD_RELOC_ARM_THUMB_BF19
:
29875 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29876 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29877 && ARM_IS_FUNC (fixP
->fx_addsy
)
29878 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29880 /* Force a relocation for a branch 19 bits wide. */
29884 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29891 addressT immA
, immB
, immC
;
29893 immA
= (value
& 0x0007f000) >> 12;
29894 immB
= (value
& 0x00000ffc) >> 2;
29895 immC
= (value
& 0x00000002) >> 1;
29897 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29898 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29900 newval2
|= (immC
<< 11) | (immB
<< 1);
29901 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29902 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29906 case BFD_RELOC_ARM_THUMB_BF13
:
29908 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29909 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29910 && ARM_IS_FUNC (fixP
->fx_addsy
)
29911 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29913 /* Force a relocation for a branch 13 bits wide. */
29917 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29921 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29924 addressT immA
, immB
, immC
;
29926 immA
= (value
& 0x00001000) >> 12;
29927 immB
= (value
& 0x00000ffc) >> 2;
29928 immC
= (value
& 0x00000002) >> 1;
29930 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29931 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29933 newval2
|= (immC
<< 11) | (immB
<< 1);
29934 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29935 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29939 case BFD_RELOC_ARM_THUMB_LOOP12
:
29941 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29942 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29943 && ARM_IS_FUNC (fixP
->fx_addsy
)
29944 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29946 /* Force a relocation for a branch 12 bits wide. */
29950 bfd_vma insn
= get_thumb32_insn (buf
);
29951 /* le lr, <label>, le <label> or letp lr, <label> */
29952 if (((insn
& 0xffffffff) == 0xf00fc001)
29953 || ((insn
& 0xffffffff) == 0xf02fc001)
29954 || ((insn
& 0xffffffff) == 0xf01fc001))
29957 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29960 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29962 addressT imml
, immh
;
29964 immh
= (value
& 0x00000ffc) >> 2;
29965 imml
= (value
& 0x00000002) >> 1;
29967 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29968 newval
|= (imml
<< 11) | (immh
<< 1);
29969 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29973 case BFD_RELOC_ARM_V4BX
:
29974 /* This will need to go in the object file. */
29978 case BFD_RELOC_UNUSED
:
29980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29981 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29985 /* Translate internal representation of relocation info to BFD target
29989 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29992 bfd_reloc_code_real_type code
;
29994 reloc
= XNEW (arelent
);
29996 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29997 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29998 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
30000 if (fixp
->fx_pcrel
)
30002 if (section
->use_rela_p
)
30003 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30005 fixp
->fx_offset
= reloc
->address
;
30007 reloc
->addend
= fixp
->fx_offset
;
30009 switch (fixp
->fx_r_type
)
30012 if (fixp
->fx_pcrel
)
30014 code
= BFD_RELOC_8_PCREL
;
30017 /* Fall through. */
30020 if (fixp
->fx_pcrel
)
30022 code
= BFD_RELOC_16_PCREL
;
30025 /* Fall through. */
30028 if (fixp
->fx_pcrel
)
30030 code
= BFD_RELOC_32_PCREL
;
30033 /* Fall through. */
30035 case BFD_RELOC_ARM_MOVW
:
30036 if (fixp
->fx_pcrel
)
30038 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30041 /* Fall through. */
30043 case BFD_RELOC_ARM_MOVT
:
30044 if (fixp
->fx_pcrel
)
30046 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30049 /* Fall through. */
30051 case BFD_RELOC_ARM_THUMB_MOVW
:
30052 if (fixp
->fx_pcrel
)
30054 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30057 /* Fall through. */
30059 case BFD_RELOC_ARM_THUMB_MOVT
:
30060 if (fixp
->fx_pcrel
)
30062 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30065 /* Fall through. */
30067 case BFD_RELOC_NONE
:
30068 case BFD_RELOC_ARM_PCREL_BRANCH
:
30069 case BFD_RELOC_ARM_PCREL_BLX
:
30070 case BFD_RELOC_RVA
:
30071 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30072 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30073 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30074 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30075 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30076 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30077 case BFD_RELOC_VTABLE_ENTRY
:
30078 case BFD_RELOC_VTABLE_INHERIT
:
30080 case BFD_RELOC_32_SECREL
:
30082 code
= fixp
->fx_r_type
;
30085 case BFD_RELOC_THUMB_PCREL_BLX
:
30087 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30088 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30091 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30094 case BFD_RELOC_ARM_LITERAL
:
30095 case BFD_RELOC_ARM_HWLITERAL
:
30096 /* If this is called then the a literal has
30097 been referenced across a section boundary. */
30098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30099 _("literal referenced across section boundary"));
30103 case BFD_RELOC_ARM_TLS_CALL
:
30104 case BFD_RELOC_ARM_THM_TLS_CALL
:
30105 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30106 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30107 case BFD_RELOC_ARM_GOT32
:
30108 case BFD_RELOC_ARM_GOTOFF
:
30109 case BFD_RELOC_ARM_GOT_PREL
:
30110 case BFD_RELOC_ARM_PLT32
:
30111 case BFD_RELOC_ARM_TARGET1
:
30112 case BFD_RELOC_ARM_ROSEGREL32
:
30113 case BFD_RELOC_ARM_SBREL32
:
30114 case BFD_RELOC_ARM_PREL31
:
30115 case BFD_RELOC_ARM_TARGET2
:
30116 case BFD_RELOC_ARM_TLS_LDO32
:
30117 case BFD_RELOC_ARM_PCREL_CALL
:
30118 case BFD_RELOC_ARM_PCREL_JUMP
:
30119 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30120 case BFD_RELOC_ARM_ALU_PC_G0
:
30121 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30122 case BFD_RELOC_ARM_ALU_PC_G1
:
30123 case BFD_RELOC_ARM_ALU_PC_G2
:
30124 case BFD_RELOC_ARM_LDR_PC_G0
:
30125 case BFD_RELOC_ARM_LDR_PC_G1
:
30126 case BFD_RELOC_ARM_LDR_PC_G2
:
30127 case BFD_RELOC_ARM_LDRS_PC_G0
:
30128 case BFD_RELOC_ARM_LDRS_PC_G1
:
30129 case BFD_RELOC_ARM_LDRS_PC_G2
:
30130 case BFD_RELOC_ARM_LDC_PC_G0
:
30131 case BFD_RELOC_ARM_LDC_PC_G1
:
30132 case BFD_RELOC_ARM_LDC_PC_G2
:
30133 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30134 case BFD_RELOC_ARM_ALU_SB_G0
:
30135 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30136 case BFD_RELOC_ARM_ALU_SB_G1
:
30137 case BFD_RELOC_ARM_ALU_SB_G2
:
30138 case BFD_RELOC_ARM_LDR_SB_G0
:
30139 case BFD_RELOC_ARM_LDR_SB_G1
:
30140 case BFD_RELOC_ARM_LDR_SB_G2
:
30141 case BFD_RELOC_ARM_LDRS_SB_G0
:
30142 case BFD_RELOC_ARM_LDRS_SB_G1
:
30143 case BFD_RELOC_ARM_LDRS_SB_G2
:
30144 case BFD_RELOC_ARM_LDC_SB_G0
:
30145 case BFD_RELOC_ARM_LDC_SB_G1
:
30146 case BFD_RELOC_ARM_LDC_SB_G2
:
30147 case BFD_RELOC_ARM_V4BX
:
30148 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30149 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30150 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30151 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30152 case BFD_RELOC_ARM_GOTFUNCDESC
:
30153 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30154 case BFD_RELOC_ARM_FUNCDESC
:
30155 case BFD_RELOC_ARM_THUMB_BF17
:
30156 case BFD_RELOC_ARM_THUMB_BF19
:
30157 case BFD_RELOC_ARM_THUMB_BF13
:
30158 code
= fixp
->fx_r_type
;
30161 case BFD_RELOC_ARM_TLS_GOTDESC
:
30162 case BFD_RELOC_ARM_TLS_GD32
:
30163 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30164 case BFD_RELOC_ARM_TLS_LE32
:
30165 case BFD_RELOC_ARM_TLS_IE32
:
30166 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30167 case BFD_RELOC_ARM_TLS_LDM32
:
30168 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30169 /* BFD will include the symbol's address in the addend.
30170 But we don't want that, so subtract it out again here. */
30171 if (!S_IS_COMMON (fixp
->fx_addsy
))
30172 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30173 code
= fixp
->fx_r_type
;
30177 case BFD_RELOC_ARM_IMMEDIATE
:
30178 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30179 _("internal relocation (type: IMMEDIATE) not fixed up"));
30182 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30183 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30184 _("ADRL used for a symbol not defined in the same file"));
30187 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30188 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30189 case BFD_RELOC_ARM_THUMB_LOOP12
:
30190 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30191 _("%s used for a symbol not defined in the same file"),
30192 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30195 case BFD_RELOC_ARM_OFFSET_IMM
:
30196 if (section
->use_rela_p
)
30198 code
= fixp
->fx_r_type
;
30202 if (fixp
->fx_addsy
!= NULL
30203 && !S_IS_DEFINED (fixp
->fx_addsy
)
30204 && S_IS_LOCAL (fixp
->fx_addsy
))
30206 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30207 _("undefined local label `%s'"),
30208 S_GET_NAME (fixp
->fx_addsy
));
30212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30213 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30220 switch (fixp
->fx_r_type
)
30222 case BFD_RELOC_NONE
: type
= "NONE"; break;
30223 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30224 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30225 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30226 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30227 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30228 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30229 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30230 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30231 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30232 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30233 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30234 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30235 default: type
= _("<unknown>"); break;
30237 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30238 _("cannot represent %s relocation in this object file format"),
30245 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30247 && fixp
->fx_addsy
== GOT_symbol
)
30249 code
= BFD_RELOC_ARM_GOTPC
;
30250 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30254 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30256 if (reloc
->howto
== NULL
)
30258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30259 _("cannot represent %s relocation in this object file format"),
30260 bfd_get_reloc_code_name (code
));
30264 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30265 vtable entry to be used in the relocation's section offset. */
30266 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30267 reloc
->address
= fixp
->fx_offset
;
30272 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30275 cons_fix_new_arm (fragS
* frag
,
30279 bfd_reloc_code_real_type reloc
)
30284 FIXME: @@ Should look at CPU word size. */
30288 reloc
= BFD_RELOC_8
;
30291 reloc
= BFD_RELOC_16
;
30295 reloc
= BFD_RELOC_32
;
30298 reloc
= BFD_RELOC_64
;
30303 if (exp
->X_op
== O_secrel
)
30305 exp
->X_op
= O_symbol
;
30306 reloc
= BFD_RELOC_32_SECREL
;
30310 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30313 #if defined (OBJ_COFF)
30315 arm_validate_fix (fixS
* fixP
)
30317 /* If the destination of the branch is a defined symbol which does not have
30318 the THUMB_FUNC attribute, then we must be calling a function which has
30319 the (interfacearm) attribute. We look for the Thumb entry point to that
30320 function and change the branch to refer to that function instead. */
30321 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30322 && fixP
->fx_addsy
!= NULL
30323 && S_IS_DEFINED (fixP
->fx_addsy
)
30324 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30326 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30333 arm_force_relocation (struct fix
* fixp
)
30335 #if defined (OBJ_COFF) && defined (TE_PE)
30336 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30340 /* In case we have a call or a branch to a function in ARM ISA mode from
30341 a thumb function or vice-versa force the relocation. These relocations
30342 are cleared off for some cores that might have blx and simple transformations
30346 switch (fixp
->fx_r_type
)
30348 case BFD_RELOC_ARM_PCREL_JUMP
:
30349 case BFD_RELOC_ARM_PCREL_CALL
:
30350 case BFD_RELOC_THUMB_PCREL_BLX
:
30351 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30355 case BFD_RELOC_ARM_PCREL_BLX
:
30356 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30357 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30358 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30359 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30368 /* Resolve these relocations even if the symbol is extern or weak.
30369 Technically this is probably wrong due to symbol preemption.
30370 In practice these relocations do not have enough range to be useful
30371 at dynamic link time, and some code (e.g. in the Linux kernel)
30372 expects these references to be resolved. */
30373 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30374 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30375 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30376 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30377 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30379 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30380 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30385 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30386 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30387 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30390 /* Always leave these relocations for the linker. */
30391 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30392 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30393 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30396 /* Always generate relocations against function symbols. */
30397 if (fixp
->fx_r_type
== BFD_RELOC_32
30399 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30402 return generic_force_reloc (fixp
);
30405 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30406 /* Relocations against function names must be left unadjusted,
30407 so that the linker can use this information to generate interworking
30408 stubs. The MIPS version of this function
30409 also prevents relocations that are mips-16 specific, but I do not
30410 know why it does this.
30413 There is one other problem that ought to be addressed here, but
30414 which currently is not: Taking the address of a label (rather
30415 than a function) and then later jumping to that address. Such
30416 addresses also ought to have their bottom bit set (assuming that
30417 they reside in Thumb code), but at the moment they will not. */
30420 arm_fix_adjustable (fixS
* fixP
)
30422 if (fixP
->fx_addsy
== NULL
)
30425 /* Preserve relocations against symbols with function type. */
30426 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30429 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30430 && fixP
->fx_subsy
== NULL
)
30433 /* We need the symbol name for the VTABLE entries. */
30434 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30435 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30438 /* Don't allow symbols to be discarded on GOT related relocs. */
30439 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30440 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30441 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30448 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30453 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30454 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30455 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30458 /* Similarly for group relocations. */
30459 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30460 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30461 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30464 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30465 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30466 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30467 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30468 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30469 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30470 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30471 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30472 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30475 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30476 offsets, so keep these symbols. */
30477 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30478 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30483 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30487 elf32_arm_target_format (void)
30490 return (target_big_endian
30491 ? "elf32-bigarm-symbian"
30492 : "elf32-littlearm-symbian");
30493 #elif defined (TE_VXWORKS)
30494 return (target_big_endian
30495 ? "elf32-bigarm-vxworks"
30496 : "elf32-littlearm-vxworks");
30497 #elif defined (TE_NACL)
30498 return (target_big_endian
30499 ? "elf32-bigarm-nacl"
30500 : "elf32-littlearm-nacl");
30504 if (target_big_endian
)
30505 return "elf32-bigarm-fdpic";
30507 return "elf32-littlearm-fdpic";
30511 if (target_big_endian
)
30512 return "elf32-bigarm";
30514 return "elf32-littlearm";
30520 armelf_frob_symbol (symbolS
* symp
,
30523 elf_frob_symbol (symp
, puntp
);
30527 /* MD interface: Finalization. */
30532 literal_pool
* pool
;
30534 /* Ensure that all the predication blocks are properly closed. */
30535 check_pred_blocks_finished ();
30537 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30539 /* Put it at the end of the relevant section. */
30540 subseg_set (pool
->section
, pool
->sub_section
);
30542 arm_elf_change_section ();
30549 /* Remove any excess mapping symbols generated for alignment frags in
30550 SEC. We may have created a mapping symbol before a zero byte
30551 alignment; remove it if there's a mapping symbol after the
30554 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30555 void *dummy ATTRIBUTE_UNUSED
)
30557 segment_info_type
*seginfo
= seg_info (sec
);
30560 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30563 for (fragp
= seginfo
->frchainP
->frch_root
;
30565 fragp
= fragp
->fr_next
)
30567 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30568 fragS
*next
= fragp
->fr_next
;
30570 /* Variable-sized frags have been converted to fixed size by
30571 this point. But if this was variable-sized to start with,
30572 there will be a fixed-size frag after it. So don't handle
30574 if (sym
== NULL
|| next
== NULL
)
30577 if (S_GET_VALUE (sym
) < next
->fr_address
)
30578 /* Not at the end of this frag. */
30580 know (S_GET_VALUE (sym
) == next
->fr_address
);
30584 if (next
->tc_frag_data
.first_map
!= NULL
)
30586 /* Next frag starts with a mapping symbol. Discard this
30588 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30592 if (next
->fr_next
== NULL
)
30594 /* This mapping symbol is at the end of the section. Discard
30596 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30597 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30601 /* As long as we have empty frags without any mapping symbols,
30603 /* If the next frag is non-empty and does not start with a
30604 mapping symbol, then this mapping symbol is required. */
30605 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30608 next
= next
->fr_next
;
30610 while (next
!= NULL
);
30615 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30619 arm_adjust_symtab (void)
30624 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30626 if (ARM_IS_THUMB (sym
))
30628 if (THUMB_IS_FUNC (sym
))
30630 /* Mark the symbol as a Thumb function. */
30631 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30632 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30633 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30635 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30636 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30638 as_bad (_("%s: unexpected function type: %d"),
30639 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30641 else switch (S_GET_STORAGE_CLASS (sym
))
30644 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30647 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30650 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30658 if (ARM_IS_INTERWORK (sym
))
30659 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30666 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30668 if (ARM_IS_THUMB (sym
))
30670 elf_symbol_type
* elf_sym
;
30672 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30673 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30675 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30676 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30678 /* If it's a .thumb_func, declare it as so,
30679 otherwise tag label as .code 16. */
30680 if (THUMB_IS_FUNC (sym
))
30681 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30682 ST_BRANCH_TO_THUMB
);
30683 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30684 elf_sym
->internal_elf_sym
.st_info
=
30685 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30690 /* Remove any overlapping mapping symbols generated by alignment frags. */
30691 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30692 /* Now do generic ELF adjustments. */
30693 elf_adjust_symtab ();
30697 /* MD interface: Initialization. */
30700 set_constant_flonums (void)
30704 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30705 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30709 /* Auto-select Thumb mode if it's the only available instruction set for the
30710 given architecture. */
30713 autoselect_thumb_from_cpu_variant (void)
30715 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30716 opcode_select (16);
30725 arm_ops_hsh
= str_htab_create ();
30726 arm_cond_hsh
= str_htab_create ();
30727 arm_vcond_hsh
= str_htab_create ();
30728 arm_shift_hsh
= str_htab_create ();
30729 arm_psr_hsh
= str_htab_create ();
30730 arm_v7m_psr_hsh
= str_htab_create ();
30731 arm_reg_hsh
= str_htab_create ();
30732 arm_reloc_hsh
= str_htab_create ();
30733 arm_barrier_opt_hsh
= str_htab_create ();
30735 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30736 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30737 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, insns
+ i
, 0);
30738 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30739 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, conds
+ i
, 0);
30740 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30741 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, vconds
+ i
, 0);
30742 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30743 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, shift_names
+ i
, 0);
30744 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30745 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, psrs
+ i
, 0);
30746 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30747 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30749 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30750 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, reg_names
+ i
, 0);
30752 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30754 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30755 barrier_opt_names
+ i
, 0);
30757 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30759 struct reloc_entry
* entry
= reloc_names
+ i
;
30761 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30762 /* This makes encode_branch() use the EABI versions of this relocation. */
30763 entry
->reloc
= BFD_RELOC_UNUSED
;
30765 str_hash_insert (arm_reloc_hsh
, entry
->name
, entry
, 0);
30769 set_constant_flonums ();
30771 /* Set the cpu variant based on the command-line options. We prefer
30772 -mcpu= over -march= if both are set (as for GCC); and we prefer
30773 -mfpu= over any other way of setting the floating point unit.
30774 Use of legacy options with new options are faulted. */
30777 if (mcpu_cpu_opt
|| march_cpu_opt
)
30778 as_bad (_("use of old and new-style options to set CPU type"));
30780 selected_arch
= *legacy_cpu
;
30782 else if (mcpu_cpu_opt
)
30784 selected_arch
= *mcpu_cpu_opt
;
30785 selected_ext
= *mcpu_ext_opt
;
30787 else if (march_cpu_opt
)
30789 selected_arch
= *march_cpu_opt
;
30790 selected_ext
= *march_ext_opt
;
30792 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30797 as_bad (_("use of old and new-style options to set FPU type"));
30799 selected_fpu
= *legacy_fpu
;
30802 selected_fpu
= *mfpu_opt
;
30805 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30806 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30807 /* Some environments specify a default FPU. If they don't, infer it
30808 from the processor. */
30810 selected_fpu
= *mcpu_fpu_opt
;
30811 else if (march_fpu_opt
)
30812 selected_fpu
= *march_fpu_opt
;
30814 selected_fpu
= fpu_default
;
30818 if (ARM_FEATURE_ZERO (selected_fpu
))
30820 if (!no_cpu_selected ())
30821 selected_fpu
= fpu_default
;
30823 selected_fpu
= fpu_arch_fpa
;
30827 if (ARM_FEATURE_ZERO (selected_arch
))
30829 selected_arch
= cpu_default
;
30830 selected_cpu
= selected_arch
;
30832 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30834 /* Autodection of feature mode: allow all features in cpu_variant but leave
30835 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30836 after all instruction have been processed and we can decide what CPU
30837 should be selected. */
30838 if (ARM_FEATURE_ZERO (selected_arch
))
30839 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30841 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30844 autoselect_thumb_from_cpu_variant ();
30846 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30848 #if defined OBJ_COFF || defined OBJ_ELF
30850 unsigned int flags
= 0;
30852 #if defined OBJ_ELF
30853 flags
= meabi_flags
;
30855 switch (meabi_flags
)
30857 case EF_ARM_EABI_UNKNOWN
:
30859 /* Set the flags in the private structure. */
30860 if (uses_apcs_26
) flags
|= F_APCS26
;
30861 if (support_interwork
) flags
|= F_INTERWORK
;
30862 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30863 if (pic_code
) flags
|= F_PIC
;
30864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30865 flags
|= F_SOFT_FLOAT
;
30867 switch (mfloat_abi_opt
)
30869 case ARM_FLOAT_ABI_SOFT
:
30870 case ARM_FLOAT_ABI_SOFTFP
:
30871 flags
|= F_SOFT_FLOAT
;
30874 case ARM_FLOAT_ABI_HARD
:
30875 if (flags
& F_SOFT_FLOAT
)
30876 as_bad (_("hard-float conflicts with specified fpu"));
30880 /* Using pure-endian doubles (even if soft-float). */
30881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30882 flags
|= F_VFP_FLOAT
;
30884 #if defined OBJ_ELF
30885 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30886 flags
|= EF_ARM_MAVERICK_FLOAT
;
30889 case EF_ARM_EABI_VER4
:
30890 case EF_ARM_EABI_VER5
:
30891 /* No additional flags to set. */
30898 bfd_set_private_flags (stdoutput
, flags
);
30900 /* We have run out flags in the COFF header to encode the
30901 status of ATPCS support, so instead we create a dummy,
30902 empty, debug section called .arm.atpcs. */
30907 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30911 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30912 bfd_set_section_size (sec
, 0);
30913 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30919 /* Record the CPU type as well. */
30920 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30921 mach
= bfd_mach_arm_iWMMXt2
;
30922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30923 mach
= bfd_mach_arm_iWMMXt
;
30924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30925 mach
= bfd_mach_arm_XScale
;
30926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30927 mach
= bfd_mach_arm_ep9312
;
30928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30929 mach
= bfd_mach_arm_5TE
;
30930 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30933 mach
= bfd_mach_arm_5T
;
30935 mach
= bfd_mach_arm_5
;
30937 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30939 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30940 mach
= bfd_mach_arm_4T
;
30942 mach
= bfd_mach_arm_4
;
30944 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30945 mach
= bfd_mach_arm_3M
;
30946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30947 mach
= bfd_mach_arm_3
;
30948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30949 mach
= bfd_mach_arm_2a
;
30950 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30951 mach
= bfd_mach_arm_2
;
30953 mach
= bfd_mach_arm_unknown
;
30955 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30958 /* Command line processing. */
30961 Invocation line includes a switch not recognized by the base assembler.
30962 See if it's a processor-specific option.
30964 This routine is somewhat complicated by the need for backwards
30965 compatibility (since older releases of gcc can't be changed).
30966 The new options try to make the interface as compatible as
30969 New options (supported) are:
30971 -mcpu=<cpu name> Assemble for selected processor
30972 -march=<architecture name> Assemble for selected architecture
30973 -mfpu=<fpu architecture> Assemble for selected FPU.
30974 -EB/-mbig-endian Big-endian
30975 -EL/-mlittle-endian Little-endian
30976 -k Generate PIC code
30977 -mthumb Start in Thumb mode
30978 -mthumb-interwork Code supports ARM/Thumb interworking
30980 -m[no-]warn-deprecated Warn about deprecated features
30981 -m[no-]warn-syms Warn when symbols match instructions
30983 For now we will also provide support for:
30985 -mapcs-32 32-bit Program counter
30986 -mapcs-26 26-bit Program counter
30987 -macps-float Floats passed in FP registers
30988 -mapcs-reentrant Reentrant code
30990 (sometime these will probably be replaced with -mapcs=<list of options>
30991 and -matpcs=<list of options>)
30993 The remaining options are only supported for back-wards compatibility.
30994 Cpu variants, the arm part is optional:
30995 -m[arm]1 Currently not supported.
30996 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30997 -m[arm]3 Arm 3 processor
30998 -m[arm]6[xx], Arm 6 processors
30999 -m[arm]7[xx][t][[d]m] Arm 7 processors
31000 -m[arm]8[10] Arm 8 processors
31001 -m[arm]9[20][tdmi] Arm 9 processors
31002 -mstrongarm[110[0]] StrongARM processors
31003 -mxscale XScale processors
31004 -m[arm]v[2345[t[e]]] Arm architectures
31005 -mall All (except the ARM1)
31007 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31008 -mfpe-old (No float load/store multiples)
31009 -mvfpxd VFP Single precision
31011 -mno-fpu Disable all floating point instructions
31013 The following CPU names are recognized:
31014 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31015 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31016 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31017 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31018 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31019 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31020 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31024 const char * md_shortopts
= "m:k";
31026 #ifdef ARM_BI_ENDIAN
31027 #define OPTION_EB (OPTION_MD_BASE + 0)
31028 #define OPTION_EL (OPTION_MD_BASE + 1)
31030 #if TARGET_BYTES_BIG_ENDIAN
31031 #define OPTION_EB (OPTION_MD_BASE + 0)
31033 #define OPTION_EL (OPTION_MD_BASE + 1)
31036 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31037 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31039 struct option md_longopts
[] =
31042 {"EB", no_argument
, NULL
, OPTION_EB
},
31045 {"EL", no_argument
, NULL
, OPTION_EL
},
31047 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31049 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31051 {NULL
, no_argument
, NULL
, 0}
31054 size_t md_longopts_size
= sizeof (md_longopts
);
31056 struct arm_option_table
31058 const char * option
; /* Option name to match. */
31059 const char * help
; /* Help information. */
31060 int * var
; /* Variable to change. */
31061 int value
; /* What to change it to. */
31062 const char * deprecated
; /* If non-null, print this message. */
31065 struct arm_option_table arm_opts
[] =
31067 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31068 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31069 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31070 &support_interwork
, 1, NULL
},
31071 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31072 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31073 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31075 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31076 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31077 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31078 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31081 /* These are recognized by the assembler, but have no affect on code. */
31082 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31083 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31085 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31086 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31087 &warn_on_deprecated
, 0, NULL
},
31089 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31090 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31091 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31093 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31094 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31095 {NULL
, NULL
, NULL
, 0, NULL
}
31098 struct arm_legacy_option_table
31100 const char * option
; /* Option name to match. */
31101 const arm_feature_set
** var
; /* Variable to change. */
31102 const arm_feature_set value
; /* What to change it to. */
31103 const char * deprecated
; /* If non-null, print this message. */
31106 const struct arm_legacy_option_table arm_legacy_opts
[] =
31108 /* DON'T add any new processors to this list -- we want the whole list
31109 to go away... Add them to the processors table instead. */
31110 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31111 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31112 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31113 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31114 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31115 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31116 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31117 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31118 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31119 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31120 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31121 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31122 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31123 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31124 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31125 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31126 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31127 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31128 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31129 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31130 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31131 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31132 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31133 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31134 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31135 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31136 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31137 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31138 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31139 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31140 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31141 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31142 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31143 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31144 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31145 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31146 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31147 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31148 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31149 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31150 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31151 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31152 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31153 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31154 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31155 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31156 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31157 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31158 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31159 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31160 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31161 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31162 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31163 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31164 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31165 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31166 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31167 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31168 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31169 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31170 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31171 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31172 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31173 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31174 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31175 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31176 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31177 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31178 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31179 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31180 N_("use -mcpu=strongarm110")},
31181 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31182 N_("use -mcpu=strongarm1100")},
31183 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31184 N_("use -mcpu=strongarm1110")},
31185 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31186 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31187 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31189 /* Architecture variants -- don't add any more to this list either. */
31190 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31191 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31192 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31193 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31194 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31195 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31196 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31197 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31198 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31199 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31200 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31201 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31202 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31203 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31204 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31205 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31206 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31207 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31209 /* Floating point variants -- don't add any more to this list either. */
31210 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31211 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31212 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31213 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31214 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31216 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31219 struct arm_cpu_option_table
31223 const arm_feature_set value
;
31224 const arm_feature_set ext
;
31225 /* For some CPUs we assume an FPU unless the user explicitly sets
31227 const arm_feature_set default_fpu
;
31228 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31230 const char * canonical_name
;
31233 /* This list should, at a minimum, contain all the cpu names
31234 recognized by GCC. */
31235 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31237 static const struct arm_cpu_option_table arm_cpus
[] =
31239 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31242 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31245 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31248 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31251 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31254 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31257 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31260 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31263 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31266 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31269 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31272 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31275 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31278 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31281 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31284 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31287 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31290 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31293 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31296 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31299 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31302 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31305 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31308 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31311 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31314 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31317 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31320 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31323 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31326 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31329 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31332 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31335 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31338 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31341 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31344 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31347 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31350 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31353 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31356 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31359 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31362 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31365 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31368 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31371 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31374 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31378 /* For V5 or later processors we default to using VFP; but the user
31379 should really set the FPU type explicitly. */
31380 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31383 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31386 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31389 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31392 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31395 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31398 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31401 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31404 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31407 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31410 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31413 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31416 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31419 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31422 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31425 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31428 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31431 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31434 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31437 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31440 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31443 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31446 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31449 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31452 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31455 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31458 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31461 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31464 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31467 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31470 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31473 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31476 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31479 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31482 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31485 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31488 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31489 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31491 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31493 FPU_ARCH_NEON_VFP_V4
),
31494 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31495 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31496 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31497 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31498 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31499 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31500 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31502 FPU_ARCH_NEON_VFP_V4
),
31503 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31505 FPU_ARCH_NEON_VFP_V4
),
31506 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31508 FPU_ARCH_NEON_VFP_V4
),
31509 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31510 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31511 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31512 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31514 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31515 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31516 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31518 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31519 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31521 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31523 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31524 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31525 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31526 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31527 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31528 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31529 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31530 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31531 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31532 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31533 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31534 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31536 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31537 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31539 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31540 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31541 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31542 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31543 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31544 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31545 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31548 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31550 FPU_ARCH_VFP_V3D16
),
31551 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31552 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31554 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31555 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31556 FPU_ARCH_VFP_V3D16
),
31557 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31558 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31559 FPU_ARCH_VFP_V3D16
),
31560 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31561 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31562 FPU_ARCH_NEON_VFP_ARMV8
),
31563 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31564 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31566 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31567 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31569 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31572 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31575 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31578 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31581 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31584 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31587 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31590 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31591 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31593 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31594 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31596 /* ??? XSCALE is really an architecture. */
31597 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31601 /* ??? iwmmxt is not a processor. */
31602 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31605 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31608 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31613 ARM_CPU_OPT ("ep9312", "ARM920T",
31614 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31615 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31617 /* Marvell processors. */
31618 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31619 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31620 FPU_ARCH_VFP_V3D16
),
31621 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31622 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31623 FPU_ARCH_NEON_VFP_V4
),
31625 /* APM X-Gene family. */
31626 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31628 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31629 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31630 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31631 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31633 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31637 struct arm_ext_table
31641 const arm_feature_set merge
;
31642 const arm_feature_set clear
;
31645 struct arm_arch_option_table
31649 const arm_feature_set value
;
31650 const arm_feature_set default_fpu
;
31651 const struct arm_ext_table
* ext_table
;
31654 /* Used to add support for +E and +noE extension. */
31655 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31656 /* Used to add support for a +E extension. */
31657 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31658 /* Used to add support for a +noE extension. */
31659 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31661 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31662 ~0 & ~FPU_ENDIAN_PURE)
31664 static const struct arm_ext_table armv5te_ext_table
[] =
31666 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31667 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31670 static const struct arm_ext_table armv7_ext_table
[] =
31672 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31673 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31676 static const struct arm_ext_table armv7ve_ext_table
[] =
31678 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31679 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31680 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31681 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31682 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31683 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31684 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31686 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31687 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31689 /* Aliases for +simd. */
31690 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31692 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31693 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31694 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31696 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31699 static const struct arm_ext_table armv7a_ext_table
[] =
31701 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31702 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31703 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31704 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31705 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31706 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31707 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31709 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31710 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31712 /* Aliases for +simd. */
31713 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31714 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31716 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31717 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31719 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31720 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31721 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31724 static const struct arm_ext_table armv7r_ext_table
[] =
31726 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31727 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31728 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31729 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31730 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31731 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31732 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31733 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31734 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31737 static const struct arm_ext_table armv7em_ext_table
[] =
31739 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31740 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31741 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31742 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31743 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31744 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31745 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31748 static const struct arm_ext_table armv8a_ext_table
[] =
31750 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31751 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31752 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31753 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31755 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31756 should use the +simd option to turn on FP. */
31757 ARM_REMOVE ("fp", ALL_FP
),
31758 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31759 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31760 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31764 static const struct arm_ext_table armv81a_ext_table
[] =
31766 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31767 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31768 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31770 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31771 should use the +simd option to turn on FP. */
31772 ARM_REMOVE ("fp", ALL_FP
),
31773 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31774 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31775 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31778 static const struct arm_ext_table armv82a_ext_table
[] =
31780 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31781 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31782 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31783 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31784 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31785 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31786 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31787 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31789 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31790 should use the +simd option to turn on FP. */
31791 ARM_REMOVE ("fp", ALL_FP
),
31792 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31793 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31794 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31797 static const struct arm_ext_table armv84a_ext_table
[] =
31799 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31800 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31801 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31802 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31803 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31804 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31806 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31807 should use the +simd option to turn on FP. */
31808 ARM_REMOVE ("fp", ALL_FP
),
31809 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31810 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31811 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31814 static const struct arm_ext_table armv85a_ext_table
[] =
31816 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31817 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31818 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31819 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31820 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31821 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31823 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31824 should use the +simd option to turn on FP. */
31825 ARM_REMOVE ("fp", ALL_FP
),
31826 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31829 static const struct arm_ext_table armv86a_ext_table
[] =
31831 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31832 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31835 #define CDE_EXTENSIONS \
31836 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31837 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31838 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31839 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31840 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31841 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31842 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31843 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31845 static const struct arm_ext_table armv8m_main_ext_table
[] =
31847 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31848 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31849 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31850 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31852 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31856 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31858 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31859 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31861 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31862 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31865 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31866 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31867 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31868 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31870 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31871 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31872 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31874 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31877 #undef CDE_EXTENSIONS
31879 static const struct arm_ext_table armv8r_ext_table
[] =
31881 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31882 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31883 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31884 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31885 ARM_REMOVE ("fp", ALL_FP
),
31886 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31887 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31890 /* This list should, at a minimum, contain all the architecture names
31891 recognized by GCC. */
31892 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31893 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31894 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31896 static const struct arm_arch_option_table arm_archs
[] =
31898 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31899 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31900 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31901 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31902 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31903 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31904 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31905 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31906 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31907 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31908 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31909 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31910 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31911 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31912 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31913 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31914 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31915 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31916 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31917 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31918 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31919 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31920 kept to preserve existing behaviour. */
31921 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31922 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31923 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31924 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31925 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31926 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31927 kept to preserve existing behaviour. */
31928 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31929 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31930 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31931 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31932 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31933 /* The official spelling of the ARMv7 profile variants is the dashed form.
31934 Accept the non-dashed form for compatibility with old toolchains. */
31935 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31936 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31937 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31938 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31939 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31940 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31941 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31942 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31943 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31944 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31946 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31948 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31949 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31950 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31951 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31952 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31953 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31954 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31955 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31956 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31957 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31958 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31959 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31961 #undef ARM_ARCH_OPT
31963 /* ISA extensions in the co-processor and main instruction set space. */
31965 struct arm_option_extension_value_table
31969 const arm_feature_set merge_value
;
31970 const arm_feature_set clear_value
;
31971 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31972 indicates that an extension is available for all architectures while
31973 ARM_ANY marks an empty entry. */
31974 const arm_feature_set allowed_archs
[2];
31977 /* The following table must be in alphabetical order with a NULL last entry. */
31979 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31980 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31982 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31983 use the context sensitive approach using arm_ext_table's. */
31984 static const struct arm_option_extension_value_table arm_extensions
[] =
31986 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31987 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31988 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31989 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31990 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31991 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31992 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31993 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31995 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31996 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31997 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31998 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31999 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32000 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32001 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32003 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32004 | ARM_EXT2_FP16_FML
),
32005 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32006 | ARM_EXT2_FP16_FML
),
32008 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32009 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32010 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32011 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32012 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32013 Thumb divide instruction. Due to this having the same name as the
32014 previous entry, this will be ignored when doing command-line parsing and
32015 only considered by build attribute selection code. */
32016 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32017 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32018 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32019 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32020 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32021 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32022 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32023 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32024 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32025 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32026 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32027 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32028 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32029 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32030 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32031 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32032 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32033 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32035 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32036 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32038 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32039 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32040 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32041 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32042 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32043 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32044 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32045 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32047 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32048 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32049 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32050 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32051 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32052 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32053 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32054 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32056 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32057 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32058 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32059 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32060 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32064 /* ISA floating-point and Advanced SIMD extensions. */
32065 struct arm_option_fpu_value_table
32068 const arm_feature_set value
;
32071 /* This list should, at a minimum, contain all the fpu names
32072 recognized by GCC. */
32073 static const struct arm_option_fpu_value_table arm_fpus
[] =
32075 {"softfpa", FPU_NONE
},
32076 {"fpe", FPU_ARCH_FPE
},
32077 {"fpe2", FPU_ARCH_FPE
},
32078 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32079 {"fpa", FPU_ARCH_FPA
},
32080 {"fpa10", FPU_ARCH_FPA
},
32081 {"fpa11", FPU_ARCH_FPA
},
32082 {"arm7500fe", FPU_ARCH_FPA
},
32083 {"softvfp", FPU_ARCH_VFP
},
32084 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32085 {"vfp", FPU_ARCH_VFP_V2
},
32086 {"vfp9", FPU_ARCH_VFP_V2
},
32087 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32088 {"vfp10", FPU_ARCH_VFP_V2
},
32089 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32090 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32091 {"vfpv2", FPU_ARCH_VFP_V2
},
32092 {"vfpv3", FPU_ARCH_VFP_V3
},
32093 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32094 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32095 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32096 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32097 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32098 {"arm1020t", FPU_ARCH_VFP_V1
},
32099 {"arm1020e", FPU_ARCH_VFP_V2
},
32100 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32101 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32102 {"maverick", FPU_ARCH_MAVERICK
},
32103 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32104 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32105 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32106 {"vfpv4", FPU_ARCH_VFP_V4
},
32107 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32108 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32109 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32110 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32111 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32112 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32113 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32114 {"crypto-neon-fp-armv8",
32115 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32116 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32117 {"crypto-neon-fp-armv8.1",
32118 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32119 {NULL
, ARM_ARCH_NONE
}
32122 struct arm_option_value_table
32128 static const struct arm_option_value_table arm_float_abis
[] =
32130 {"hard", ARM_FLOAT_ABI_HARD
},
32131 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32132 {"soft", ARM_FLOAT_ABI_SOFT
},
32137 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32138 static const struct arm_option_value_table arm_eabis
[] =
32140 {"gnu", EF_ARM_EABI_UNKNOWN
},
32141 {"4", EF_ARM_EABI_VER4
},
32142 {"5", EF_ARM_EABI_VER5
},
32147 struct arm_long_option_table
32149 const char * option
; /* Substring to match. */
32150 const char * help
; /* Help information. */
32151 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32152 const char * deprecated
; /* If non-null, print this message. */
32156 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32157 arm_feature_set
*ext_set
,
32158 const struct arm_ext_table
*ext_table
)
32160 /* We insist on extensions being specified in alphabetical order, and with
32161 extensions being added before being removed. We achieve this by having
32162 the global ARM_EXTENSIONS table in alphabetical order, and using the
32163 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32164 or removing it (0) and only allowing it to change in the order
32166 const struct arm_option_extension_value_table
* opt
= NULL
;
32167 const arm_feature_set arm_any
= ARM_ANY
;
32168 int adding_value
= -1;
32170 while (str
!= NULL
&& *str
!= 0)
32177 as_bad (_("invalid architectural extension"));
32182 ext
= strchr (str
, '+');
32187 len
= strlen (str
);
32189 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32191 if (adding_value
!= 0)
32194 opt
= arm_extensions
;
32202 if (adding_value
== -1)
32205 opt
= arm_extensions
;
32207 else if (adding_value
!= 1)
32209 as_bad (_("must specify extensions to add before specifying "
32210 "those to remove"));
32217 as_bad (_("missing architectural extension"));
32221 gas_assert (adding_value
!= -1);
32222 gas_assert (opt
!= NULL
);
32224 if (ext_table
!= NULL
)
32226 const struct arm_ext_table
* ext_opt
= ext_table
;
32227 bfd_boolean found
= FALSE
;
32228 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32229 if (ext_opt
->name_len
== len
32230 && strncmp (ext_opt
->name
, str
, len
) == 0)
32234 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32235 /* TODO: Option not supported. When we remove the
32236 legacy table this case should error out. */
32239 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32243 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32244 /* TODO: Option not supported. When we remove the
32245 legacy table this case should error out. */
32247 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32259 /* Scan over the options table trying to find an exact match. */
32260 for (; opt
->name
!= NULL
; opt
++)
32261 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32263 int i
, nb_allowed_archs
=
32264 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32265 /* Check we can apply the extension to this architecture. */
32266 for (i
= 0; i
< nb_allowed_archs
; i
++)
32269 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32271 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32274 if (i
== nb_allowed_archs
)
32276 as_bad (_("extension does not apply to the base architecture"));
32280 /* Add or remove the extension. */
32282 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32284 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32286 /* Allowing Thumb division instructions for ARMv7 in autodetection
32287 rely on this break so that duplicate extensions (extensions
32288 with the same name as a previous extension in the list) are not
32289 considered for command-line parsing. */
32293 if (opt
->name
== NULL
)
32295 /* Did we fail to find an extension because it wasn't specified in
32296 alphabetical order, or because it does not exist? */
32298 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32299 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32302 if (opt
->name
== NULL
)
32303 as_bad (_("unknown architectural extension `%s'"), str
);
32305 as_bad (_("architectural extensions must be specified in "
32306 "alphabetical order"));
32312 /* We should skip the extension we've just matched the next time
32324 arm_parse_fp16_opt (const char *str
)
32326 if (strcasecmp (str
, "ieee") == 0)
32327 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32328 else if (strcasecmp (str
, "alternative") == 0)
32329 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32332 as_bad (_("unrecognised float16 format \"%s\""), str
);
32340 arm_parse_cpu (const char *str
)
32342 const struct arm_cpu_option_table
*opt
;
32343 const char *ext
= strchr (str
, '+');
32349 len
= strlen (str
);
32353 as_bad (_("missing cpu name `%s'"), str
);
32357 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32358 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32360 mcpu_cpu_opt
= &opt
->value
;
32361 if (mcpu_ext_opt
== NULL
)
32362 mcpu_ext_opt
= XNEW (arm_feature_set
);
32363 *mcpu_ext_opt
= opt
->ext
;
32364 mcpu_fpu_opt
= &opt
->default_fpu
;
32365 if (opt
->canonical_name
)
32367 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32368 strcpy (selected_cpu_name
, opt
->canonical_name
);
32374 if (len
>= sizeof selected_cpu_name
)
32375 len
= (sizeof selected_cpu_name
) - 1;
32377 for (i
= 0; i
< len
; i
++)
32378 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32379 selected_cpu_name
[i
] = 0;
32383 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32388 as_bad (_("unknown cpu `%s'"), str
);
32393 arm_parse_arch (const char *str
)
32395 const struct arm_arch_option_table
*opt
;
32396 const char *ext
= strchr (str
, '+');
32402 len
= strlen (str
);
32406 as_bad (_("missing architecture name `%s'"), str
);
32410 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32411 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32413 march_cpu_opt
= &opt
->value
;
32414 if (march_ext_opt
== NULL
)
32415 march_ext_opt
= XNEW (arm_feature_set
);
32416 *march_ext_opt
= arm_arch_none
;
32417 march_fpu_opt
= &opt
->default_fpu
;
32418 selected_ctx_ext_table
= opt
->ext_table
;
32419 strcpy (selected_cpu_name
, opt
->name
);
32422 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32428 as_bad (_("unknown architecture `%s'\n"), str
);
32433 arm_parse_fpu (const char * str
)
32435 const struct arm_option_fpu_value_table
* opt
;
32437 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32438 if (streq (opt
->name
, str
))
32440 mfpu_opt
= &opt
->value
;
32444 as_bad (_("unknown floating point format `%s'\n"), str
);
32449 arm_parse_float_abi (const char * str
)
32451 const struct arm_option_value_table
* opt
;
32453 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32454 if (streq (opt
->name
, str
))
32456 mfloat_abi_opt
= opt
->value
;
32460 as_bad (_("unknown floating point abi `%s'\n"), str
);
32466 arm_parse_eabi (const char * str
)
32468 const struct arm_option_value_table
*opt
;
32470 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32471 if (streq (opt
->name
, str
))
32473 meabi_flags
= opt
->value
;
32476 as_bad (_("unknown EABI `%s'\n"), str
);
32482 arm_parse_it_mode (const char * str
)
32484 bfd_boolean ret
= TRUE
;
32486 if (streq ("arm", str
))
32487 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32488 else if (streq ("thumb", str
))
32489 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32490 else if (streq ("always", str
))
32491 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32492 else if (streq ("never", str
))
32493 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32496 as_bad (_("unknown implicit IT mode `%s', should be "\
32497 "arm, thumb, always, or never."), str
);
32505 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32507 codecomposer_syntax
= TRUE
;
32508 arm_comment_chars
[0] = ';';
32509 arm_line_separator_chars
[0] = 0;
32513 struct arm_long_option_table arm_long_opts
[] =
32515 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32516 arm_parse_cpu
, NULL
},
32517 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32518 arm_parse_arch
, NULL
},
32519 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32520 arm_parse_fpu
, NULL
},
32521 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32522 arm_parse_float_abi
, NULL
},
32524 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32525 arm_parse_eabi
, NULL
},
32527 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32528 arm_parse_it_mode
, NULL
},
32529 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32530 arm_ccs_mode
, NULL
},
32532 N_("[ieee|alternative]\n\
32533 set the encoding for half precision floating point "
32534 "numbers to IEEE\n\
32535 or Arm alternative format."),
32536 arm_parse_fp16_opt
, NULL
},
32537 {NULL
, NULL
, 0, NULL
}
32541 md_parse_option (int c
, const char * arg
)
32543 struct arm_option_table
*opt
;
32544 const struct arm_legacy_option_table
*fopt
;
32545 struct arm_long_option_table
*lopt
;
32551 target_big_endian
= 1;
32557 target_big_endian
= 0;
32561 case OPTION_FIX_V4BX
:
32569 #endif /* OBJ_ELF */
32572 /* Listing option. Just ignore these, we don't support additional
32577 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32579 if (c
== opt
->option
[0]
32580 && ((arg
== NULL
&& opt
->option
[1] == 0)
32581 || streq (arg
, opt
->option
+ 1)))
32583 /* If the option is deprecated, tell the user. */
32584 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32585 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32586 arg
? arg
: "", _(opt
->deprecated
));
32588 if (opt
->var
!= NULL
)
32589 *opt
->var
= opt
->value
;
32595 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32597 if (c
== fopt
->option
[0]
32598 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32599 || streq (arg
, fopt
->option
+ 1)))
32601 /* If the option is deprecated, tell the user. */
32602 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32603 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32604 arg
? arg
: "", _(fopt
->deprecated
));
32606 if (fopt
->var
!= NULL
)
32607 *fopt
->var
= &fopt
->value
;
32613 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32615 /* These options are expected to have an argument. */
32616 if (c
== lopt
->option
[0]
32618 && strncmp (arg
, lopt
->option
+ 1,
32619 strlen (lopt
->option
+ 1)) == 0)
32621 /* If the option is deprecated, tell the user. */
32622 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32623 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32624 _(lopt
->deprecated
));
32626 /* Call the sup-option parser. */
32627 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32638 md_show_usage (FILE * fp
)
32640 struct arm_option_table
*opt
;
32641 struct arm_long_option_table
*lopt
;
32643 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32645 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32646 if (opt
->help
!= NULL
)
32647 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32649 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32650 if (lopt
->help
!= NULL
)
32651 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32655 -EB assemble code for a big-endian cpu\n"));
32660 -EL assemble code for a little-endian cpu\n"));
32664 --fix-v4bx Allow BX in ARMv4 code\n"));
32668 --fdpic generate an FDPIC object file\n"));
32669 #endif /* OBJ_ELF */
32677 arm_feature_set flags
;
32678 } cpu_arch_ver_table
;
32680 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32681 chronologically for architectures, with an exception for ARMv6-M and
32682 ARMv6S-M due to legacy reasons. No new architecture should have a
32683 special case. This allows for build attribute selection results to be
32684 stable when new architectures are added. */
32685 static const cpu_arch_ver_table cpu_arch_ver
[] =
32687 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32688 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32689 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32690 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32691 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32692 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32693 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32694 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32695 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32696 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32697 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32698 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32699 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32700 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32701 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32702 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32703 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32704 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32705 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32706 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32707 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32708 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32709 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32710 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32712 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32713 always selected build attributes to match those of ARMv6-M
32714 (resp. ARMv6S-M). However, due to these architectures being a strict
32715 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32716 would be selected when fully respecting chronology of architectures.
32717 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32718 move them before ARMv7 architectures. */
32719 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32720 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32722 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32723 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32724 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32725 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32726 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32727 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32728 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32729 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32730 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32731 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32732 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32733 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32734 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32735 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32736 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32737 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32738 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32739 {-1, ARM_ARCH_NONE
}
32742 /* Set an attribute if it has not already been set by the user. */
32745 aeabi_set_attribute_int (int tag
, int value
)
32748 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32749 || !attributes_set_explicitly
[tag
])
32750 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32754 aeabi_set_attribute_string (int tag
, const char *value
)
32757 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32758 || !attributes_set_explicitly
[tag
])
32759 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32762 /* Return whether features in the *NEEDED feature set are available via
32763 extensions for the architecture whose feature set is *ARCH_FSET. */
32766 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32767 const arm_feature_set
*needed
)
32769 int i
, nb_allowed_archs
;
32770 arm_feature_set ext_fset
;
32771 const struct arm_option_extension_value_table
*opt
;
32773 ext_fset
= arm_arch_none
;
32774 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32776 /* Extension does not provide any feature we need. */
32777 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32781 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32782 for (i
= 0; i
< nb_allowed_archs
; i
++)
32785 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32788 /* Extension is available, add it. */
32789 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32790 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32794 /* Can we enable all features in *needed? */
32795 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32798 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32799 a given architecture feature set *ARCH_EXT_FSET including extension feature
32800 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32801 - if true, check for an exact match of the architecture modulo extensions;
32802 - otherwise, select build attribute value of the first superset
32803 architecture released so that results remains stable when new architectures
32805 For -march/-mcpu=all the build attribute value of the most featureful
32806 architecture is returned. Tag_CPU_arch_profile result is returned in
32810 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32811 const arm_feature_set
*ext_fset
,
32812 char *profile
, int exact_match
)
32814 arm_feature_set arch_fset
;
32815 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32817 /* Select most featureful architecture with all its extensions if building
32818 for -march=all as the feature sets used to set build attributes. */
32819 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32821 /* Force revisiting of decision for each new architecture. */
32822 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32824 return TAG_CPU_ARCH_V8
;
32827 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32829 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32831 arm_feature_set known_arch_fset
;
32833 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32836 /* Base architecture match user-specified architecture and
32837 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32838 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32843 /* Base architecture match user-specified architecture only
32844 (eg. ARMv6-M in the same case as above). Record it in case we
32845 find a match with above condition. */
32846 else if (p_ver_ret
== NULL
32847 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32853 /* Architecture has all features wanted. */
32854 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32856 arm_feature_set added_fset
;
32858 /* Compute features added by this architecture over the one
32859 recorded in p_ver_ret. */
32860 if (p_ver_ret
!= NULL
)
32861 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32863 /* First architecture that match incl. with extensions, or the
32864 only difference in features over the recorded match is
32865 features that were optional and are now mandatory. */
32866 if (p_ver_ret
== NULL
32867 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32873 else if (p_ver_ret
== NULL
)
32875 arm_feature_set needed_ext_fset
;
32877 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32879 /* Architecture has all features needed when using some
32880 extensions. Record it and continue searching in case there
32881 exist an architecture providing all needed features without
32882 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32884 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32891 if (p_ver_ret
== NULL
)
32895 /* Tag_CPU_arch_profile. */
32896 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32897 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32898 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32899 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32900 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32902 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32903 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32905 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32909 return p_ver_ret
->val
;
32912 /* Set the public EABI object attributes. */
32915 aeabi_set_public_attributes (void)
32917 char profile
= '\0';
32920 int fp16_optional
= 0;
32921 int skip_exact_match
= 0;
32922 arm_feature_set flags
, flags_arch
, flags_ext
;
32924 /* Autodetection mode, choose the architecture based the instructions
32926 if (no_cpu_selected ())
32928 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32930 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32931 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32933 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32934 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32936 /* Code run during relaxation relies on selected_cpu being set. */
32937 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32938 flags_ext
= arm_arch_none
;
32939 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32940 selected_ext
= flags_ext
;
32941 selected_cpu
= flags
;
32943 /* Otherwise, choose the architecture based on the capabilities of the
32947 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32948 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32949 flags_ext
= selected_ext
;
32950 flags
= selected_cpu
;
32952 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32954 /* Allow the user to override the reported architecture. */
32955 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32957 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32958 flags_ext
= arm_arch_none
;
32961 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32963 /* When this function is run again after relaxation has happened there is no
32964 way to determine whether an architecture or CPU was specified by the user:
32965 - selected_cpu is set above for relaxation to work;
32966 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32967 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32968 Therefore, if not in -march=all case we first try an exact match and fall
32969 back to autodetection. */
32970 if (!skip_exact_match
)
32971 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32973 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32975 as_bad (_("no architecture contains all the instructions used\n"));
32977 /* Tag_CPU_name. */
32978 if (selected_cpu_name
[0])
32982 q
= selected_cpu_name
;
32983 if (strncmp (q
, "armv", 4) == 0)
32988 for (i
= 0; q
[i
]; i
++)
32989 q
[i
] = TOUPPER (q
[i
]);
32991 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32994 /* Tag_CPU_arch. */
32995 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32997 /* Tag_CPU_arch_profile. */
32998 if (profile
!= '\0')
32999 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
33001 /* Tag_DSP_extension. */
33002 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33003 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33005 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33006 /* Tag_ARM_ISA_use. */
33007 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33008 || ARM_FEATURE_ZERO (flags_arch
))
33009 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33011 /* Tag_THUMB_ISA_use. */
33012 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33013 || ARM_FEATURE_ZERO (flags_arch
))
33017 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33018 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33020 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33024 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33027 /* Tag_VFP_arch. */
33028 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33029 aeabi_set_attribute_int (Tag_VFP_arch
,
33030 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33032 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33033 aeabi_set_attribute_int (Tag_VFP_arch
,
33034 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33036 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33039 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33041 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33043 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33046 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33047 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33048 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33049 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33050 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33052 /* Tag_ABI_HardFP_use. */
33053 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33054 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33055 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33057 /* Tag_WMMX_arch. */
33058 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33059 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33060 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33061 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33063 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33064 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33065 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33066 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33067 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33068 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33070 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33072 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33076 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33081 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33082 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33083 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33084 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33086 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33087 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33088 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33092 We set Tag_DIV_use to two when integer divide instructions have been used
33093 in ARM state, or when Thumb integer divide instructions have been used,
33094 but we have no architecture profile set, nor have we any ARM instructions.
33096 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33097 by the base architecture.
33099 For new architectures we will have to check these tests. */
33100 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33101 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33102 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33103 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33104 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33105 || (profile
== '\0'
33106 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33107 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33108 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33110 /* Tag_MP_extension_use. */
33111 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33112 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33114 /* Tag Virtualization_use. */
33115 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33117 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33120 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33122 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33123 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33126 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33127 finished and free extension feature bits which will not be used anymore. */
33130 arm_md_post_relax (void)
33132 aeabi_set_public_attributes ();
33133 XDELETE (mcpu_ext_opt
);
33134 mcpu_ext_opt
= NULL
;
33135 XDELETE (march_ext_opt
);
33136 march_ext_opt
= NULL
;
33139 /* Add the default contents for the .ARM.attributes section. */
33144 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33147 aeabi_set_public_attributes ();
33149 #endif /* OBJ_ELF */
33151 /* Parse a .cpu directive. */
33154 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33156 const struct arm_cpu_option_table
*opt
;
33160 name
= input_line_pointer
;
33161 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33162 input_line_pointer
++;
33163 saved_char
= *input_line_pointer
;
33164 *input_line_pointer
= 0;
33166 /* Skip the first "all" entry. */
33167 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33168 if (streq (opt
->name
, name
))
33170 selected_arch
= opt
->value
;
33171 selected_ext
= opt
->ext
;
33172 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33173 if (opt
->canonical_name
)
33174 strcpy (selected_cpu_name
, opt
->canonical_name
);
33178 for (i
= 0; opt
->name
[i
]; i
++)
33179 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33181 selected_cpu_name
[i
] = 0;
33183 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33185 *input_line_pointer
= saved_char
;
33186 demand_empty_rest_of_line ();
33189 as_bad (_("unknown cpu `%s'"), name
);
33190 *input_line_pointer
= saved_char
;
33191 ignore_rest_of_line ();
33194 /* Parse a .arch directive. */
33197 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33199 const struct arm_arch_option_table
*opt
;
33203 name
= input_line_pointer
;
33204 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33205 input_line_pointer
++;
33206 saved_char
= *input_line_pointer
;
33207 *input_line_pointer
= 0;
33209 /* Skip the first "all" entry. */
33210 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33211 if (streq (opt
->name
, name
))
33213 selected_arch
= opt
->value
;
33214 selected_ctx_ext_table
= opt
->ext_table
;
33215 selected_ext
= arm_arch_none
;
33216 selected_cpu
= selected_arch
;
33217 strcpy (selected_cpu_name
, opt
->name
);
33218 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33219 *input_line_pointer
= saved_char
;
33220 demand_empty_rest_of_line ();
33224 as_bad (_("unknown architecture `%s'\n"), name
);
33225 *input_line_pointer
= saved_char
;
33226 ignore_rest_of_line ();
33229 /* Parse a .object_arch directive. */
33232 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33234 const struct arm_arch_option_table
*opt
;
33238 name
= input_line_pointer
;
33239 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33240 input_line_pointer
++;
33241 saved_char
= *input_line_pointer
;
33242 *input_line_pointer
= 0;
33244 /* Skip the first "all" entry. */
33245 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33246 if (streq (opt
->name
, name
))
33248 selected_object_arch
= opt
->value
;
33249 *input_line_pointer
= saved_char
;
33250 demand_empty_rest_of_line ();
33254 as_bad (_("unknown architecture `%s'\n"), name
);
33255 *input_line_pointer
= saved_char
;
33256 ignore_rest_of_line ();
33259 /* Parse a .arch_extension directive. */
33262 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33264 const struct arm_option_extension_value_table
*opt
;
33267 int adding_value
= 1;
33269 name
= input_line_pointer
;
33270 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33271 input_line_pointer
++;
33272 saved_char
= *input_line_pointer
;
33273 *input_line_pointer
= 0;
33275 if (strlen (name
) >= 2
33276 && strncmp (name
, "no", 2) == 0)
33282 /* Check the context specific extension table */
33283 if (selected_ctx_ext_table
)
33285 const struct arm_ext_table
* ext_opt
;
33286 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33288 if (streq (ext_opt
->name
, name
))
33292 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33293 /* TODO: Option not supported. When we remove the
33294 legacy table this case should error out. */
33296 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33300 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33302 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33303 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33304 *input_line_pointer
= saved_char
;
33305 demand_empty_rest_of_line ();
33311 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33312 if (streq (opt
->name
, name
))
33314 int i
, nb_allowed_archs
=
33315 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33316 for (i
= 0; i
< nb_allowed_archs
; i
++)
33319 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33321 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33325 if (i
== nb_allowed_archs
)
33327 as_bad (_("architectural extension `%s' is not allowed for the "
33328 "current base architecture"), name
);
33333 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33336 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33338 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33339 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33340 *input_line_pointer
= saved_char
;
33341 demand_empty_rest_of_line ();
33342 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33343 on this return so that duplicate extensions (extensions with the
33344 same name as a previous extension in the list) are not considered
33345 for command-line parsing. */
33349 if (opt
->name
== NULL
)
33350 as_bad (_("unknown architecture extension `%s'\n"), name
);
33352 *input_line_pointer
= saved_char
;
33353 ignore_rest_of_line ();
33356 /* Parse a .fpu directive. */
33359 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33361 const struct arm_option_fpu_value_table
*opt
;
33365 name
= input_line_pointer
;
33366 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33367 input_line_pointer
++;
33368 saved_char
= *input_line_pointer
;
33369 *input_line_pointer
= 0;
33371 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33372 if (streq (opt
->name
, name
))
33374 selected_fpu
= opt
->value
;
33375 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33376 #ifndef CPU_DEFAULT
33377 if (no_cpu_selected ())
33378 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33381 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33382 *input_line_pointer
= saved_char
;
33383 demand_empty_rest_of_line ();
33387 as_bad (_("unknown floating point format `%s'\n"), name
);
33388 *input_line_pointer
= saved_char
;
33389 ignore_rest_of_line ();
33392 /* Copy symbol information. */
33395 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33397 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33401 /* Given a symbolic attribute NAME, return the proper integer value.
33402 Returns -1 if the attribute is not known. */
33405 arm_convert_symbolic_attribute (const char *name
)
33407 static const struct
33412 attribute_table
[] =
33414 /* When you modify this table you should
33415 also modify the list in doc/c-arm.texi. */
33416 #define T(tag) {#tag, tag}
33417 T (Tag_CPU_raw_name
),
33420 T (Tag_CPU_arch_profile
),
33421 T (Tag_ARM_ISA_use
),
33422 T (Tag_THUMB_ISA_use
),
33426 T (Tag_Advanced_SIMD_arch
),
33427 T (Tag_PCS_config
),
33428 T (Tag_ABI_PCS_R9_use
),
33429 T (Tag_ABI_PCS_RW_data
),
33430 T (Tag_ABI_PCS_RO_data
),
33431 T (Tag_ABI_PCS_GOT_use
),
33432 T (Tag_ABI_PCS_wchar_t
),
33433 T (Tag_ABI_FP_rounding
),
33434 T (Tag_ABI_FP_denormal
),
33435 T (Tag_ABI_FP_exceptions
),
33436 T (Tag_ABI_FP_user_exceptions
),
33437 T (Tag_ABI_FP_number_model
),
33438 T (Tag_ABI_align_needed
),
33439 T (Tag_ABI_align8_needed
),
33440 T (Tag_ABI_align_preserved
),
33441 T (Tag_ABI_align8_preserved
),
33442 T (Tag_ABI_enum_size
),
33443 T (Tag_ABI_HardFP_use
),
33444 T (Tag_ABI_VFP_args
),
33445 T (Tag_ABI_WMMX_args
),
33446 T (Tag_ABI_optimization_goals
),
33447 T (Tag_ABI_FP_optimization_goals
),
33448 T (Tag_compatibility
),
33449 T (Tag_CPU_unaligned_access
),
33450 T (Tag_FP_HP_extension
),
33451 T (Tag_VFP_HP_extension
),
33452 T (Tag_ABI_FP_16bit_format
),
33453 T (Tag_MPextension_use
),
33455 T (Tag_nodefaults
),
33456 T (Tag_also_compatible_with
),
33457 T (Tag_conformance
),
33459 T (Tag_Virtualization_use
),
33460 T (Tag_DSP_extension
),
33462 /* We deliberately do not include Tag_MPextension_use_legacy. */
33470 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33471 if (streq (name
, attribute_table
[i
].name
))
33472 return attribute_table
[i
].tag
;
33477 /* Apply sym value for relocations only in the case that they are for
33478 local symbols in the same segment as the fixup and you have the
33479 respective architectural feature for blx and simple switches. */
33482 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33485 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33486 /* PR 17444: If the local symbol is in a different section then a reloc
33487 will always be generated for it, so applying the symbol value now
33488 will result in a double offset being stored in the relocation. */
33489 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33490 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33492 switch (fixP
->fx_r_type
)
33494 case BFD_RELOC_ARM_PCREL_BLX
:
33495 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33496 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33500 case BFD_RELOC_ARM_PCREL_CALL
:
33501 case BFD_RELOC_THUMB_PCREL_BLX
:
33502 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33513 #endif /* OBJ_ELF */