1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR
, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR
, /* ARM LR register */
6930 OP_RRe
, /* ARM register, only even numbered. */
6931 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST
, /* ARM register list */
6935 OP_CLRMLST
, /* CLRM register list */
6936 OP_VRSLST
, /* VFP single-precision register list */
6937 OP_VRDLST
, /* VFP double-precision register list */
6938 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST
, /* Neon element/structure list */
6941 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2
, /* MVE vector list with two elements. */
6943 OP_MSTRLST4
, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV
, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6970 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6971 OP_VLDR
, /* VLDR operand. */
6973 OP_I0
, /* immediate zero */
6974 OP_I7
, /* immediate value 0 .. 7 */
6975 OP_I15
, /* 0 .. 15 */
6976 OP_I16
, /* 1 .. 16 */
6977 OP_I16z
, /* 0 .. 16 */
6978 OP_I31
, /* 0 .. 31 */
6979 OP_I31w
, /* 0 .. 31, optional trailing ! */
6980 OP_I32
, /* 1 .. 32 */
6981 OP_I32z
, /* 0 .. 32 */
6982 OP_I63
, /* 0 .. 63 */
6983 OP_I63s
, /* -64 .. 63 */
6984 OP_I64
, /* 1 .. 64 */
6985 OP_I64z
, /* 0 .. 64 */
6986 OP_I255
, /* 0 .. 255 */
6988 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6989 OP_I7b
, /* 0 .. 7 */
6990 OP_I15b
, /* 0 .. 15 */
6991 OP_I31b
, /* 0 .. 31 */
6993 OP_SH
, /* shifter operand */
6994 OP_SHG
, /* shifter operand with possible group relocation */
6995 OP_ADDR
, /* Memory address expression (any mode) */
6996 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6997 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6998 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6999 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7000 OP_EXP
, /* arbitrary expression */
7001 OP_EXPi
, /* same, with optional immediate prefix */
7002 OP_EXPr
, /* same, with optional relocation suffix */
7003 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7004 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7005 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7006 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7008 OP_CPSF
, /* CPS flags */
7009 OP_ENDI
, /* Endianness specifier */
7010 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7011 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7012 OP_COND
, /* conditional code */
7013 OP_TB
, /* Table branch. */
7015 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7017 OP_RRnpc_I0
, /* ARM register or literal 0 */
7018 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7019 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7020 OP_RF_IF
, /* FPA register or immediate */
7021 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7022 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7024 /* Optional operands. */
7025 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7026 OP_oI31b
, /* 0 .. 31 */
7027 OP_oI32b
, /* 1 .. 32 */
7028 OP_oI32z
, /* 0 .. 32 */
7029 OP_oIffffb
, /* 0 .. 65535 */
7030 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7032 OP_oRR
, /* ARM register */
7033 OP_oLR
, /* ARM LR register */
7034 OP_oRRnpc
, /* ARM register, not the PC */
7035 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7036 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7037 OP_oRND
, /* Optional Neon double precision register */
7038 OP_oRNQ
, /* Optional Neon quad precision register */
7039 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7040 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7041 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7042 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7044 OP_oSHll
, /* LSL immediate */
7045 OP_oSHar
, /* ASR immediate */
7046 OP_oSHllar
, /* LSL or ASR immediate */
7047 OP_oROR
, /* ROR 0/8/16/24 */
7048 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7050 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7052 /* Some pre-defined mixed (ARM/THUMB) operands. */
7053 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7054 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7055 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7057 OP_FIRST_OPTIONAL
= OP_oI7b
7060 /* Generic instruction operand parser. This does no encoding and no
7061 semantic validation; it merely squirrels values away in the inst
7062 structure. Returns SUCCESS or FAIL depending on whether the
7063 specified grammar matched. */
7065 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7067 unsigned const int *upat
= pattern
;
7068 char *backtrack_pos
= 0;
7069 const char *backtrack_error
= 0;
7070 int i
, val
= 0, backtrack_index
= 0;
7071 enum arm_reg_type rtype
;
7072 parse_operand_result result
;
7073 unsigned int op_parse_code
;
7074 bfd_boolean partial_match
;
7076 #define po_char_or_fail(chr) \
7079 if (skip_past_char (&str, chr) == FAIL) \
7084 #define po_reg_or_fail(regtype) \
7087 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7088 & inst.operands[i].vectype); \
7091 first_error (_(reg_expected_msgs[regtype])); \
7094 inst.operands[i].reg = val; \
7095 inst.operands[i].isreg = 1; \
7096 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7097 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7098 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7099 || rtype == REG_TYPE_VFD \
7100 || rtype == REG_TYPE_NQ); \
7101 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7105 #define po_reg_or_goto(regtype, label) \
7108 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7109 & inst.operands[i].vectype); \
7113 inst.operands[i].reg = val; \
7114 inst.operands[i].isreg = 1; \
7115 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7116 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7117 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7118 || rtype == REG_TYPE_VFD \
7119 || rtype == REG_TYPE_NQ); \
7120 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7124 #define po_imm_or_fail(min, max, popt) \
7127 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7129 inst.operands[i].imm = val; \
7133 #define po_scalar_or_goto(elsz, label, reg_type) \
7136 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7140 inst.operands[i].reg = val; \
7141 inst.operands[i].isscalar = 1; \
7145 #define po_misc_or_fail(expr) \
7153 #define po_misc_or_fail_no_backtrack(expr) \
7157 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7158 backtrack_pos = 0; \
7159 if (result != PARSE_OPERAND_SUCCESS) \
7164 #define po_barrier_or_imm(str) \
7167 val = parse_barrier (&str); \
7168 if (val == FAIL && ! ISALPHA (*str)) \
7171 /* ISB can only take SY as an option. */ \
7172 || ((inst.instruction & 0xf0) == 0x60 \
7175 inst.error = _("invalid barrier type"); \
7176 backtrack_pos = 0; \
7182 skip_whitespace (str
);
7184 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7186 op_parse_code
= upat
[i
];
7187 if (op_parse_code
>= 1<<16)
7188 op_parse_code
= thumb
? (op_parse_code
>> 16)
7189 : (op_parse_code
& ((1<<16)-1));
7191 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7193 /* Remember where we are in case we need to backtrack. */
7194 backtrack_pos
= str
;
7195 backtrack_error
= inst
.error
;
7196 backtrack_index
= i
;
7199 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7200 po_char_or_fail (',');
7202 switch (op_parse_code
)
7214 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7215 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7216 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7217 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7218 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7219 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7222 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7226 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7229 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7231 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7233 /* Also accept generic coprocessor regs for unknown registers. */
7235 po_reg_or_fail (REG_TYPE_CN
);
7237 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7238 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7239 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7240 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7241 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7242 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7243 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7244 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7245 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7246 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7249 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7252 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7253 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7255 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7260 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7264 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7266 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7269 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7271 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7274 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7276 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7281 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7284 po_reg_or_fail (REG_TYPE_NSDQ
);
7288 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7292 po_reg_or_fail (REG_TYPE_MQ
);
7294 /* Neon scalar. Using an element size of 8 means that some invalid
7295 scalars are accepted here, so deal with those in later code. */
7296 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7300 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7303 po_imm_or_fail (0, 0, TRUE
);
7308 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7312 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7317 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7320 if (parse_ifimm_zero (&str
))
7321 inst
.operands
[i
].imm
= 0;
7325 = _("only floating point zero is allowed as immediate value");
7333 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7336 po_reg_or_fail (REG_TYPE_RN
);
7340 case OP_RNSDQ_RNSC_MQ_RR
:
7341 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7344 case OP_RNSDQ_RNSC_MQ
:
7345 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7350 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7354 po_reg_or_fail (REG_TYPE_NSDQ
);
7361 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7364 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7367 po_reg_or_fail (REG_TYPE_NSD
);
7371 case OP_RNDQMQ_RNSC_RR
:
7372 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7375 case OP_RNDQ_RNSC_RR
:
7376 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7378 case OP_RNDQMQ_RNSC
:
7379 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7384 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7387 po_reg_or_fail (REG_TYPE_NDQ
);
7393 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7396 po_reg_or_fail (REG_TYPE_VFD
);
7401 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7402 not careful then bad things might happen. */
7403 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7406 case OP_RNDQMQ_Ibig
:
7407 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7412 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7415 /* There's a possibility of getting a 64-bit immediate here, so
7416 we need special handling. */
7417 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7420 inst
.error
= _("immediate value is out of range");
7426 case OP_RNDQMQ_I63b_RR
:
7427 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7430 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7435 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7438 po_imm_or_fail (0, 63, TRUE
);
7443 po_char_or_fail ('[');
7444 po_reg_or_fail (REG_TYPE_RN
);
7445 po_char_or_fail (']');
7451 po_reg_or_fail (REG_TYPE_RN
);
7452 if (skip_past_char (&str
, '!') == SUCCESS
)
7453 inst
.operands
[i
].writeback
= 1;
7457 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7458 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7459 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7460 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7461 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7462 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7463 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7464 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7465 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7466 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7467 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7468 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7470 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7472 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7473 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7475 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7476 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7477 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7478 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7480 /* Immediate variants */
7482 po_char_or_fail ('{');
7483 po_imm_or_fail (0, 255, TRUE
);
7484 po_char_or_fail ('}');
7488 /* The expression parser chokes on a trailing !, so we have
7489 to find it first and zap it. */
7492 while (*s
&& *s
!= ',')
7497 inst
.operands
[i
].writeback
= 1;
7499 po_imm_or_fail (0, 31, TRUE
);
7507 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7512 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7517 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7519 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7521 val
= parse_reloc (&str
);
7524 inst
.error
= _("unrecognized relocation suffix");
7527 else if (val
!= BFD_RELOC_UNUSED
)
7529 inst
.operands
[i
].imm
= val
;
7530 inst
.operands
[i
].hasreloc
= 1;
7536 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7538 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7540 inst
.operands
[i
].hasreloc
= 1;
7542 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7544 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7545 inst
.operands
[i
].hasreloc
= 0;
7549 /* Operand for MOVW or MOVT. */
7551 po_misc_or_fail (parse_half (&str
));
7554 /* Register or expression. */
7555 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7556 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7558 /* Register or immediate. */
7559 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7560 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7562 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7564 if (!is_immediate_prefix (*str
))
7567 val
= parse_fpa_immediate (&str
);
7570 /* FPA immediates are encoded as registers 8-15.
7571 parse_fpa_immediate has already applied the offset. */
7572 inst
.operands
[i
].reg
= val
;
7573 inst
.operands
[i
].isreg
= 1;
7576 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7577 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7579 /* Two kinds of register. */
7582 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7584 || (rege
->type
!= REG_TYPE_MMXWR
7585 && rege
->type
!= REG_TYPE_MMXWC
7586 && rege
->type
!= REG_TYPE_MMXWCG
))
7588 inst
.error
= _("iWMMXt data or control register expected");
7591 inst
.operands
[i
].reg
= rege
->number
;
7592 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7598 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7600 || (rege
->type
!= REG_TYPE_MMXWC
7601 && rege
->type
!= REG_TYPE_MMXWCG
))
7603 inst
.error
= _("iWMMXt control register expected");
7606 inst
.operands
[i
].reg
= rege
->number
;
7607 inst
.operands
[i
].isreg
= 1;
7612 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7613 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7614 case OP_oROR
: val
= parse_ror (&str
); break;
7616 case OP_COND
: val
= parse_cond (&str
); break;
7617 case OP_oBARRIER_I15
:
7618 po_barrier_or_imm (str
); break;
7620 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7626 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7627 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7629 inst
.error
= _("Banked registers are not available with this "
7635 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7639 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7642 val
= parse_sys_vldr_vstr (&str
);
7646 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7651 if (strncasecmp (str
, "APSR_", 5) == 0)
7658 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7659 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7660 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7661 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7662 default: found
= 16;
7666 inst
.operands
[i
].isvec
= 1;
7667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7668 inst
.operands
[i
].reg
= REG_PC
;
7675 po_misc_or_fail (parse_tb (&str
));
7678 /* Register lists. */
7680 val
= parse_reg_list (&str
, REGLIST_RN
);
7683 inst
.operands
[i
].writeback
= 1;
7689 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7693 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7698 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7703 /* Allow Q registers too. */
7704 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7705 REGLIST_NEON_D
, &partial_match
);
7709 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7710 REGLIST_VFP_S
, &partial_match
);
7711 inst
.operands
[i
].issingle
= 1;
7716 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7717 REGLIST_VFP_D_VPR
, &partial_match
);
7718 if (val
== FAIL
&& !partial_match
)
7721 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7722 REGLIST_VFP_S_VPR
, &partial_match
);
7723 inst
.operands
[i
].issingle
= 1;
7728 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7729 REGLIST_NEON_D
, &partial_match
);
7734 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7735 1, &inst
.operands
[i
].vectype
);
7736 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7740 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7741 0, &inst
.operands
[i
].vectype
);
7744 /* Addressing modes */
7746 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7750 po_misc_or_fail (parse_address (&str
, i
));
7754 po_misc_or_fail_no_backtrack (
7755 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7759 po_misc_or_fail_no_backtrack (
7760 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7764 po_misc_or_fail_no_backtrack (
7765 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7769 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7773 po_misc_or_fail_no_backtrack (
7774 parse_shifter_operand_group_reloc (&str
, i
));
7778 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7782 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7786 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7791 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7794 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7797 po_reg_or_fail (REG_TYPE_ZR
);
7801 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7804 /* Various value-based sanity checks and shared operations. We
7805 do not signal immediate failures for the register constraints;
7806 this allows a syntax error to take precedence. */
7807 switch (op_parse_code
)
7815 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7816 inst
.error
= BAD_PC
;
7821 if (inst
.operands
[i
].isreg
)
7823 if (inst
.operands
[i
].reg
== REG_PC
)
7824 inst
.error
= BAD_PC
;
7825 else if (inst
.operands
[i
].reg
== REG_SP
7826 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7827 relaxed since ARMv8-A. */
7828 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7831 inst
.error
= BAD_SP
;
7837 if (inst
.operands
[i
].isreg
7838 && inst
.operands
[i
].reg
== REG_PC
7839 && (inst
.operands
[i
].writeback
|| thumb
))
7840 inst
.error
= BAD_PC
;
7845 if (inst
.operands
[i
].isreg
)
7855 case OP_oBARRIER_I15
:
7868 inst
.operands
[i
].imm
= val
;
7873 if (inst
.operands
[i
].reg
!= REG_LR
)
7874 inst
.error
= _("operand must be LR register");
7879 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7880 inst
.error
= BAD_PC
;
7884 if (inst
.operands
[i
].isreg
7885 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7886 inst
.error
= BAD_ODD
;
7890 if (inst
.operands
[i
].isreg
)
7892 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7893 inst
.error
= BAD_EVEN
;
7894 else if (inst
.operands
[i
].reg
== REG_SP
)
7895 as_tsktsk (MVE_BAD_SP
);
7896 else if (inst
.operands
[i
].reg
== REG_PC
)
7897 inst
.error
= BAD_PC
;
7905 /* If we get here, this operand was successfully parsed. */
7906 inst
.operands
[i
].present
= 1;
7910 inst
.error
= BAD_ARGS
;
7915 /* The parse routine should already have set inst.error, but set a
7916 default here just in case. */
7918 inst
.error
= BAD_SYNTAX
;
7922 /* Do not backtrack over a trailing optional argument that
7923 absorbed some text. We will only fail again, with the
7924 'garbage following instruction' error message, which is
7925 probably less helpful than the current one. */
7926 if (backtrack_index
== i
&& backtrack_pos
!= str
7927 && upat
[i
+1] == OP_stop
)
7930 inst
.error
= BAD_SYNTAX
;
7934 /* Try again, skipping the optional argument at backtrack_pos. */
7935 str
= backtrack_pos
;
7936 inst
.error
= backtrack_error
;
7937 inst
.operands
[backtrack_index
].present
= 0;
7938 i
= backtrack_index
;
7942 /* Check that we have parsed all the arguments. */
7943 if (*str
!= '\0' && !inst
.error
)
7944 inst
.error
= _("garbage following instruction");
7946 return inst
.error
? FAIL
: SUCCESS
;
7949 #undef po_char_or_fail
7950 #undef po_reg_or_fail
7951 #undef po_reg_or_goto
7952 #undef po_imm_or_fail
7953 #undef po_scalar_or_fail
7954 #undef po_barrier_or_imm
7956 /* Shorthand macro for instruction encoding functions issuing errors. */
7957 #define constraint(expr, err) \
7968 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7969 instructions are unpredictable if these registers are used. This
7970 is the BadReg predicate in ARM's Thumb-2 documentation.
7972 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7973 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7974 #define reject_bad_reg(reg) \
7976 if (reg == REG_PC) \
7978 inst.error = BAD_PC; \
7981 else if (reg == REG_SP \
7982 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7984 inst.error = BAD_SP; \
7989 /* If REG is R13 (the stack pointer), warn that its use is
7991 #define warn_deprecated_sp(reg) \
7993 if (warn_on_deprecated && reg == REG_SP) \
7994 as_tsktsk (_("use of r13 is deprecated")); \
7997 /* Functions for operand encoding. ARM, then Thumb. */
7999 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8001 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8003 The only binary encoding difference is the Coprocessor number. Coprocessor
8004 9 is used for half-precision calculations or conversions. The format of the
8005 instruction is the same as the equivalent Coprocessor 10 instruction that
8006 exists for Single-Precision operation. */
8009 do_scalar_fp16_v82_encode (void)
8011 if (inst
.cond
< COND_ALWAYS
)
8012 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8013 " the behaviour is UNPREDICTABLE"));
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8017 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8018 mark_feature_used (&arm_ext_fp16
);
8021 /* If VAL can be encoded in the immediate field of an ARM instruction,
8022 return the encoded form. Otherwise, return FAIL. */
8025 encode_arm_immediate (unsigned int val
)
8032 for (i
= 2; i
< 32; i
+= 2)
8033 if ((a
= rotate_left (val
, i
)) <= 0xff)
8034 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8039 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8040 return the encoded form. Otherwise, return FAIL. */
8042 encode_thumb32_immediate (unsigned int val
)
8049 for (i
= 1; i
<= 24; i
++)
8052 if ((val
& ~(0xff << i
)) == 0)
8053 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8057 if (val
== ((a
<< 16) | a
))
8059 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8063 if (val
== ((a
<< 16) | a
))
8064 return 0x200 | (a
>> 8);
8068 /* Encode a VFP SP or DP register number into inst.instruction. */
8071 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8073 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8076 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8079 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8082 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8087 first_error (_("D register out of range for selected VFP version"));
8095 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8099 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8103 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8107 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8111 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8115 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8123 /* Encode a <shift> in an ARM-format instruction. The immediate,
8124 if any, is handled by md_apply_fix. */
8126 encode_arm_shift (int i
)
8128 /* register-shifted register. */
8129 if (inst
.operands
[i
].immisreg
)
8132 for (op_index
= 0; op_index
<= i
; ++op_index
)
8134 /* Check the operand only when it's presented. In pre-UAL syntax,
8135 if the destination register is the same as the first operand, two
8136 register form of the instruction can be used. */
8137 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8138 && inst
.operands
[op_index
].reg
== REG_PC
)
8139 as_warn (UNPRED_REG ("r15"));
8142 if (inst
.operands
[i
].imm
== REG_PC
)
8143 as_warn (UNPRED_REG ("r15"));
8146 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8147 inst
.instruction
|= SHIFT_ROR
<< 5;
8150 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8151 if (inst
.operands
[i
].immisreg
)
8153 inst
.instruction
|= SHIFT_BY_REG
;
8154 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8157 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8162 encode_arm_shifter_operand (int i
)
8164 if (inst
.operands
[i
].isreg
)
8166 inst
.instruction
|= inst
.operands
[i
].reg
;
8167 encode_arm_shift (i
);
8171 inst
.instruction
|= INST_IMMEDIATE
;
8172 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8173 inst
.instruction
|= inst
.operands
[i
].imm
;
8177 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8179 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8182 Generate an error if the operand is not a register. */
8183 constraint (!inst
.operands
[i
].isreg
,
8184 _("Instruction does not support =N addresses"));
8186 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8188 if (inst
.operands
[i
].preind
)
8192 inst
.error
= _("instruction does not accept preindexed addressing");
8195 inst
.instruction
|= PRE_INDEX
;
8196 if (inst
.operands
[i
].writeback
)
8197 inst
.instruction
|= WRITE_BACK
;
8200 else if (inst
.operands
[i
].postind
)
8202 gas_assert (inst
.operands
[i
].writeback
);
8204 inst
.instruction
|= WRITE_BACK
;
8206 else /* unindexed - only for coprocessor */
8208 inst
.error
= _("instruction does not accept unindexed addressing");
8212 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8213 && (((inst
.instruction
& 0x000f0000) >> 16)
8214 == ((inst
.instruction
& 0x0000f000) >> 12)))
8215 as_warn ((inst
.instruction
& LOAD_BIT
)
8216 ? _("destination register same as write-back base")
8217 : _("source register same as write-back base"));
8220 /* inst.operands[i] was set up by parse_address. Encode it into an
8221 ARM-format mode 2 load or store instruction. If is_t is true,
8222 reject forms that cannot be used with a T instruction (i.e. not
8225 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8227 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8229 encode_arm_addr_mode_common (i
, is_t
);
8231 if (inst
.operands
[i
].immisreg
)
8233 constraint ((inst
.operands
[i
].imm
== REG_PC
8234 || (is_pc
&& inst
.operands
[i
].writeback
)),
8236 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8237 inst
.instruction
|= inst
.operands
[i
].imm
;
8238 if (!inst
.operands
[i
].negative
)
8239 inst
.instruction
|= INDEX_UP
;
8240 if (inst
.operands
[i
].shifted
)
8242 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8243 inst
.instruction
|= SHIFT_ROR
<< 5;
8246 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8247 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8251 else /* immediate offset in inst.relocs[0] */
8253 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8255 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8257 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8258 cannot use PC in addressing.
8259 PC cannot be used in writeback addressing, either. */
8260 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8263 /* Use of PC in str is deprecated for ARMv7. */
8264 if (warn_on_deprecated
8266 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8267 as_tsktsk (_("use of PC in this instruction is deprecated"));
8270 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8272 /* Prefer + for zero encoded value. */
8273 if (!inst
.operands
[i
].negative
)
8274 inst
.instruction
|= INDEX_UP
;
8275 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8280 /* inst.operands[i] was set up by parse_address. Encode it into an
8281 ARM-format mode 3 load or store instruction. Reject forms that
8282 cannot be used with such instructions. If is_t is true, reject
8283 forms that cannot be used with a T instruction (i.e. not
8286 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8288 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8290 inst
.error
= _("instruction does not accept scaled register index");
8294 encode_arm_addr_mode_common (i
, is_t
);
8296 if (inst
.operands
[i
].immisreg
)
8298 constraint ((inst
.operands
[i
].imm
== REG_PC
8299 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8301 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8303 inst
.instruction
|= inst
.operands
[i
].imm
;
8304 if (!inst
.operands
[i
].negative
)
8305 inst
.instruction
|= INDEX_UP
;
8307 else /* immediate offset in inst.relocs[0] */
8309 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8310 && inst
.operands
[i
].writeback
),
8312 inst
.instruction
|= HWOFFSET_IMM
;
8313 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8315 /* Prefer + for zero encoded value. */
8316 if (!inst
.operands
[i
].negative
)
8317 inst
.instruction
|= INDEX_UP
;
8319 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8324 /* Write immediate bits [7:0] to the following locations:
8326 |28/24|23 19|18 16|15 4|3 0|
8327 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8329 This function is used by VMOV/VMVN/VORR/VBIC. */
8332 neon_write_immbits (unsigned immbits
)
8334 inst
.instruction
|= immbits
& 0xf;
8335 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8336 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8339 /* Invert low-order SIZE bits of XHI:XLO. */
8342 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8344 unsigned immlo
= xlo
? *xlo
: 0;
8345 unsigned immhi
= xhi
? *xhi
: 0;
8350 immlo
= (~immlo
) & 0xff;
8354 immlo
= (~immlo
) & 0xffff;
8358 immhi
= (~immhi
) & 0xffffffff;
8362 immlo
= (~immlo
) & 0xffffffff;
8376 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8380 neon_bits_same_in_bytes (unsigned imm
)
8382 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8383 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8384 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8385 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8388 /* For immediate of above form, return 0bABCD. */
8391 neon_squash_bits (unsigned imm
)
8393 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8394 | ((imm
& 0x01000000) >> 21);
8397 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8400 neon_qfloat_bits (unsigned imm
)
8402 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8405 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8406 the instruction. *OP is passed as the initial value of the op field, and
8407 may be set to a different value depending on the constant (i.e.
8408 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8409 MVN). If the immediate looks like a repeated pattern then also
8410 try smaller element sizes. */
8413 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8414 unsigned *immbits
, int *op
, int size
,
8415 enum neon_el_type type
)
8417 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8419 if (type
== NT_float
&& !float_p
)
8422 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8424 if (size
!= 32 || *op
== 1)
8426 *immbits
= neon_qfloat_bits (immlo
);
8432 if (neon_bits_same_in_bytes (immhi
)
8433 && neon_bits_same_in_bytes (immlo
))
8437 *immbits
= (neon_squash_bits (immhi
) << 4)
8438 | neon_squash_bits (immlo
);
8449 if (immlo
== (immlo
& 0x000000ff))
8454 else if (immlo
== (immlo
& 0x0000ff00))
8456 *immbits
= immlo
>> 8;
8459 else if (immlo
== (immlo
& 0x00ff0000))
8461 *immbits
= immlo
>> 16;
8464 else if (immlo
== (immlo
& 0xff000000))
8466 *immbits
= immlo
>> 24;
8469 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8471 *immbits
= (immlo
>> 8) & 0xff;
8474 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8476 *immbits
= (immlo
>> 16) & 0xff;
8480 if ((immlo
& 0xffff) != (immlo
>> 16))
8487 if (immlo
== (immlo
& 0x000000ff))
8492 else if (immlo
== (immlo
& 0x0000ff00))
8494 *immbits
= immlo
>> 8;
8498 if ((immlo
& 0xff) != (immlo
>> 8))
8503 if (immlo
== (immlo
& 0x000000ff))
8505 /* Don't allow MVN with 8-bit immediate. */
8515 #if defined BFD_HOST_64_BIT
8516 /* Returns TRUE if double precision value V may be cast
8517 to single precision without loss of accuracy. */
8520 is_double_a_single (bfd_int64_t v
)
8522 int exp
= (int)((v
>> 52) & 0x7FF);
8523 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8525 return (exp
== 0 || exp
== 0x7FF
8526 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8527 && (mantissa
& 0x1FFFFFFFl
) == 0;
8530 /* Returns a double precision value casted to single precision
8531 (ignoring the least significant bits in exponent and mantissa). */
8534 double_to_single (bfd_int64_t v
)
8536 int sign
= (int) ((v
>> 63) & 1l);
8537 int exp
= (int) ((v
>> 52) & 0x7FF);
8538 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8544 exp
= exp
- 1023 + 127;
8553 /* No denormalized numbers. */
8559 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8561 #endif /* BFD_HOST_64_BIT */
8570 static void do_vfp_nsyn_opcode (const char *);
8572 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8573 Determine whether it can be performed with a move instruction; if
8574 it can, convert inst.instruction to that move instruction and
8575 return TRUE; if it can't, convert inst.instruction to a literal-pool
8576 load and return FALSE. If this is not a valid thing to do in the
8577 current context, set inst.error and return TRUE.
8579 inst.operands[i] describes the destination register. */
8582 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8585 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8586 bfd_boolean arm_p
= (t
== CONST_ARM
);
8589 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8593 if ((inst
.instruction
& tbit
) == 0)
8595 inst
.error
= _("invalid pseudo operation");
8599 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8600 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8601 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8603 inst
.error
= _("constant expression expected");
8607 if (inst
.relocs
[0].exp
.X_op
== O_constant
8608 || inst
.relocs
[0].exp
.X_op
== O_big
)
8610 #if defined BFD_HOST_64_BIT
8615 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8617 LITTLENUM_TYPE w
[X_PRECISION
];
8620 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8622 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8624 /* FIXME: Should we check words w[2..5] ? */
8629 #if defined BFD_HOST_64_BIT
8631 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8632 << LITTLENUM_NUMBER_OF_BITS
)
8633 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8634 << LITTLENUM_NUMBER_OF_BITS
)
8635 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8636 << LITTLENUM_NUMBER_OF_BITS
)
8637 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8639 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8640 | (l
[0] & LITTLENUM_MASK
);
8644 v
= inst
.relocs
[0].exp
.X_add_number
;
8646 if (!inst
.operands
[i
].issingle
)
8650 /* LDR should not use lead in a flag-setting instruction being
8651 chosen so we do not check whether movs can be used. */
8653 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8654 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8655 && inst
.operands
[i
].reg
!= 13
8656 && inst
.operands
[i
].reg
!= 15)
8658 /* Check if on thumb2 it can be done with a mov.w, mvn or
8659 movw instruction. */
8660 unsigned int newimm
;
8661 bfd_boolean isNegated
;
8663 newimm
= encode_thumb32_immediate (v
);
8664 if (newimm
!= (unsigned int) FAIL
)
8668 newimm
= encode_thumb32_immediate (~v
);
8669 if (newimm
!= (unsigned int) FAIL
)
8673 /* The number can be loaded with a mov.w or mvn
8675 if (newimm
!= (unsigned int) FAIL
8676 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8678 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8679 | (inst
.operands
[i
].reg
<< 8));
8680 /* Change to MOVN. */
8681 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8682 inst
.instruction
|= (newimm
& 0x800) << 15;
8683 inst
.instruction
|= (newimm
& 0x700) << 4;
8684 inst
.instruction
|= (newimm
& 0x0ff);
8687 /* The number can be loaded with a movw instruction. */
8688 else if ((v
& ~0xFFFF) == 0
8689 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8691 int imm
= v
& 0xFFFF;
8693 inst
.instruction
= 0xf2400000; /* MOVW. */
8694 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8695 inst
.instruction
|= (imm
& 0xf000) << 4;
8696 inst
.instruction
|= (imm
& 0x0800) << 15;
8697 inst
.instruction
|= (imm
& 0x0700) << 4;
8698 inst
.instruction
|= (imm
& 0x00ff);
8705 int value
= encode_arm_immediate (v
);
8709 /* This can be done with a mov instruction. */
8710 inst
.instruction
&= LITERAL_MASK
;
8711 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8712 inst
.instruction
|= value
& 0xfff;
8716 value
= encode_arm_immediate (~ v
);
8719 /* This can be done with a mvn instruction. */
8720 inst
.instruction
&= LITERAL_MASK
;
8721 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8722 inst
.instruction
|= value
& 0xfff;
8726 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8729 unsigned immbits
= 0;
8730 unsigned immlo
= inst
.operands
[1].imm
;
8731 unsigned immhi
= inst
.operands
[1].regisimm
8732 ? inst
.operands
[1].reg
8733 : inst
.relocs
[0].exp
.X_unsigned
8735 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8736 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8737 &op
, 64, NT_invtype
);
8741 neon_invert_size (&immlo
, &immhi
, 64);
8743 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8744 &op
, 64, NT_invtype
);
8749 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8755 /* Fill other bits in vmov encoding for both thumb and arm. */
8757 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8759 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8760 neon_write_immbits (immbits
);
8768 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8769 if (inst
.operands
[i
].issingle
8770 && is_quarter_float (inst
.operands
[1].imm
)
8771 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8773 inst
.operands
[1].imm
=
8774 neon_qfloat_bits (v
);
8775 do_vfp_nsyn_opcode ("fconsts");
8779 /* If our host does not support a 64-bit type then we cannot perform
8780 the following optimization. This mean that there will be a
8781 discrepancy between the output produced by an assembler built for
8782 a 32-bit-only host and the output produced from a 64-bit host, but
8783 this cannot be helped. */
8784 #if defined BFD_HOST_64_BIT
8785 else if (!inst
.operands
[1].issingle
8786 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8788 if (is_double_a_single (v
)
8789 && is_quarter_float (double_to_single (v
)))
8791 inst
.operands
[1].imm
=
8792 neon_qfloat_bits (double_to_single (v
));
8793 do_vfp_nsyn_opcode ("fconstd");
8801 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8802 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8805 inst
.operands
[1].reg
= REG_PC
;
8806 inst
.operands
[1].isreg
= 1;
8807 inst
.operands
[1].preind
= 1;
8808 inst
.relocs
[0].pc_rel
= 1;
8809 inst
.relocs
[0].type
= (thumb_p
8810 ? BFD_RELOC_ARM_THUMB_OFFSET
8812 ? BFD_RELOC_ARM_HWLITERAL
8813 : BFD_RELOC_ARM_LITERAL
));
8817 /* inst.operands[i] was set up by parse_address. Encode it into an
8818 ARM-format instruction. Reject all forms which cannot be encoded
8819 into a coprocessor load/store instruction. If wb_ok is false,
8820 reject use of writeback; if unind_ok is false, reject use of
8821 unindexed addressing. If reloc_override is not 0, use it instead
8822 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8823 (in which case it is preserved). */
8826 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8828 if (!inst
.operands
[i
].isreg
)
8831 if (! inst
.operands
[0].isvec
)
8833 inst
.error
= _("invalid co-processor operand");
8836 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8840 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8842 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8844 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8846 gas_assert (!inst
.operands
[i
].writeback
);
8849 inst
.error
= _("instruction does not support unindexed addressing");
8852 inst
.instruction
|= inst
.operands
[i
].imm
;
8853 inst
.instruction
|= INDEX_UP
;
8857 if (inst
.operands
[i
].preind
)
8858 inst
.instruction
|= PRE_INDEX
;
8860 if (inst
.operands
[i
].writeback
)
8862 if (inst
.operands
[i
].reg
== REG_PC
)
8864 inst
.error
= _("pc may not be used with write-back");
8869 inst
.error
= _("instruction does not support writeback");
8872 inst
.instruction
|= WRITE_BACK
;
8876 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8877 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8878 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8879 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8882 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8884 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8887 /* Prefer + for zero encoded value. */
8888 if (!inst
.operands
[i
].negative
)
8889 inst
.instruction
|= INDEX_UP
;
8894 /* Functions for instruction encoding, sorted by sub-architecture.
8895 First some generics; their names are taken from the conventional
8896 bit positions for register arguments in ARM format instructions. */
8906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8912 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8919 inst
.instruction
|= inst
.operands
[1].reg
;
8925 inst
.instruction
|= inst
.operands
[0].reg
;
8926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8933 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8939 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8940 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8946 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8951 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8953 if (ARM_CPU_IS_ANY (cpu_variant
))
8955 as_tsktsk ("%s", msg
);
8958 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8970 unsigned Rn
= inst
.operands
[2].reg
;
8971 /* Enforce restrictions on SWP instruction. */
8972 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8974 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8975 _("Rn must not overlap other operands"));
8977 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8979 if (!check_obsolete (&arm_ext_v8
,
8980 _("swp{b} use is obsoleted for ARMv8 and later"))
8981 && warn_on_deprecated
8982 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8983 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 inst
.instruction
|= inst
.operands
[1].reg
;
8988 inst
.instruction
|= Rn
<< 16;
8994 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8996 inst
.instruction
|= inst
.operands
[2].reg
;
9002 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9003 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9004 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9005 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9007 inst
.instruction
|= inst
.operands
[0].reg
;
9008 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9009 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9015 inst
.instruction
|= inst
.operands
[0].imm
;
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9025 /* ARM instructions, in alphabetical order by function name (except
9026 that wrapper functions appear immediately after the function they
9029 /* This is a pseudo-op of the form "adr rd, label" to be converted
9030 into a relative address of the form "add rd, pc, #label-.-8". */
9035 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9037 /* Frag hacking will turn this into a sub instruction if the offset turns
9038 out to be negative. */
9039 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9040 inst
.relocs
[0].pc_rel
= 1;
9041 inst
.relocs
[0].exp
.X_add_number
-= 8;
9043 if (support_interwork
9044 && inst
.relocs
[0].exp
.X_op
== O_symbol
9045 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9046 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9047 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9048 inst
.relocs
[0].exp
.X_add_number
|= 1;
9051 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9052 into a relative address of the form:
9053 add rd, pc, #low(label-.-8)"
9054 add rd, rd, #high(label-.-8)" */
9059 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9061 /* Frag hacking will turn this into a sub instruction if the offset turns
9062 out to be negative. */
9063 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9064 inst
.relocs
[0].pc_rel
= 1;
9065 inst
.size
= INSN_SIZE
* 2;
9066 inst
.relocs
[0].exp
.X_add_number
-= 8;
9068 if (support_interwork
9069 && inst
.relocs
[0].exp
.X_op
== O_symbol
9070 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9071 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9072 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9073 inst
.relocs
[0].exp
.X_add_number
|= 1;
9079 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9080 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9082 if (!inst
.operands
[1].present
)
9083 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9086 encode_arm_shifter_operand (2);
9092 if (inst
.operands
[0].present
)
9093 inst
.instruction
|= inst
.operands
[0].imm
;
9095 inst
.instruction
|= 0xf;
9101 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9102 constraint (msb
> 32, _("bit-field extends past end of register"));
9103 /* The instruction encoding stores the LSB and MSB,
9104 not the LSB and width. */
9105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9106 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9107 inst
.instruction
|= (msb
- 1) << 16;
9115 /* #0 in second position is alternative syntax for bfc, which is
9116 the same instruction but with REG_PC in the Rm field. */
9117 if (!inst
.operands
[1].isreg
)
9118 inst
.operands
[1].reg
= REG_PC
;
9120 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9121 constraint (msb
> 32, _("bit-field extends past end of register"));
9122 /* The instruction encoding stores the LSB and MSB,
9123 not the LSB and width. */
9124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9125 inst
.instruction
|= inst
.operands
[1].reg
;
9126 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9127 inst
.instruction
|= (msb
- 1) << 16;
9133 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9134 _("bit-field extends past end of register"));
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 inst
.instruction
|= inst
.operands
[1].reg
;
9137 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9138 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9141 /* ARM V5 breakpoint instruction (argument parse)
9142 BKPT <16 bit unsigned immediate>
9143 Instruction is not conditional.
9144 The bit pattern given in insns[] has the COND_ALWAYS condition,
9145 and it is an error if the caller tried to override that. */
9150 /* Top 12 of 16 bits to bits 19:8. */
9151 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9153 /* Bottom 4 of 16 bits to bits 3:0. */
9154 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9158 encode_branch (int default_reloc
)
9160 if (inst
.operands
[0].hasreloc
)
9162 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9163 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9164 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9165 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9166 ? BFD_RELOC_ARM_PLT32
9167 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9170 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9171 inst
.relocs
[0].pc_rel
= 1;
9178 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9179 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9182 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9189 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9191 if (inst
.cond
== COND_ALWAYS
)
9192 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9194 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9201 /* ARM V5 branch-link-exchange instruction (argument parse)
9202 BLX <target_addr> ie BLX(1)
9203 BLX{<condition>} <Rm> ie BLX(2)
9204 Unfortunately, there are two different opcodes for this mnemonic.
9205 So, the insns[].value is not used, and the code here zaps values
9206 into inst.instruction.
9207 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9212 if (inst
.operands
[0].isreg
)
9214 /* Arg is a register; the opcode provided by insns[] is correct.
9215 It is not illegal to do "blx pc", just useless. */
9216 if (inst
.operands
[0].reg
== REG_PC
)
9217 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9219 inst
.instruction
|= inst
.operands
[0].reg
;
9223 /* Arg is an address; this instruction cannot be executed
9224 conditionally, and the opcode must be adjusted.
9225 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9226 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9227 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9228 inst
.instruction
= 0xfa000000;
9229 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9236 bfd_boolean want_reloc
;
9238 if (inst
.operands
[0].reg
== REG_PC
)
9239 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9241 inst
.instruction
|= inst
.operands
[0].reg
;
9242 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9243 it is for ARMv4t or earlier. */
9244 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9245 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9246 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9250 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9255 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9259 /* ARM v5TEJ. Jump to Jazelle code. */
9264 if (inst
.operands
[0].reg
== REG_PC
)
9265 as_tsktsk (_("use of r15 in bxj is not really useful"));
9267 inst
.instruction
|= inst
.operands
[0].reg
;
9270 /* Co-processor data operation:
9271 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9272 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9277 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9278 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9279 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9280 inst
.instruction
|= inst
.operands
[4].reg
;
9281 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9288 encode_arm_shifter_operand (1);
9291 /* Transfer between coprocessor and ARM registers.
9292 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9297 No special properties. */
9299 struct deprecated_coproc_regs_s
9306 arm_feature_set deprecated
;
9307 arm_feature_set obsoleted
;
9308 const char *dep_msg
;
9309 const char *obs_msg
;
9312 #define DEPR_ACCESS_V8 \
9313 N_("This coprocessor register access is deprecated in ARMv8")
9315 /* Table of all deprecated coprocessor registers. */
9316 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9318 {15, 0, 7, 10, 5, /* CP15DMB. */
9319 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9320 DEPR_ACCESS_V8
, NULL
},
9321 {15, 0, 7, 10, 4, /* CP15DSB. */
9322 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9323 DEPR_ACCESS_V8
, NULL
},
9324 {15, 0, 7, 5, 4, /* CP15ISB. */
9325 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9326 DEPR_ACCESS_V8
, NULL
},
9327 {14, 6, 1, 0, 0, /* TEEHBR. */
9328 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9329 DEPR_ACCESS_V8
, NULL
},
9330 {14, 6, 0, 0, 0, /* TEECR. */
9331 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9332 DEPR_ACCESS_V8
, NULL
},
9335 #undef DEPR_ACCESS_V8
9337 static const size_t deprecated_coproc_reg_count
=
9338 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9346 Rd
= inst
.operands
[2].reg
;
9349 if (inst
.instruction
== 0xee000010
9350 || inst
.instruction
== 0xfe000010)
9352 reject_bad_reg (Rd
);
9353 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9355 constraint (Rd
== REG_SP
, BAD_SP
);
9360 if (inst
.instruction
== 0xe000010)
9361 constraint (Rd
== REG_PC
, BAD_PC
);
9364 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9366 const struct deprecated_coproc_regs_s
*r
=
9367 deprecated_coproc_regs
+ i
;
9369 if (inst
.operands
[0].reg
== r
->cp
9370 && inst
.operands
[1].imm
== r
->opc1
9371 && inst
.operands
[3].reg
== r
->crn
9372 && inst
.operands
[4].reg
== r
->crm
9373 && inst
.operands
[5].imm
== r
->opc2
)
9375 if (! ARM_CPU_IS_ANY (cpu_variant
)
9376 && warn_on_deprecated
9377 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9378 as_tsktsk ("%s", r
->dep_msg
);
9382 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9383 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9384 inst
.instruction
|= Rd
<< 12;
9385 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9386 inst
.instruction
|= inst
.operands
[4].reg
;
9387 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9390 /* Transfer between coprocessor register and pair of ARM registers.
9391 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9396 Two XScale instructions are special cases of these:
9398 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9399 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9401 Result unpredictable if Rd or Rn is R15. */
9408 Rd
= inst
.operands
[2].reg
;
9409 Rn
= inst
.operands
[3].reg
;
9413 reject_bad_reg (Rd
);
9414 reject_bad_reg (Rn
);
9418 constraint (Rd
== REG_PC
, BAD_PC
);
9419 constraint (Rn
== REG_PC
, BAD_PC
);
9422 /* Only check the MRRC{2} variants. */
9423 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9425 /* If Rd == Rn, error that the operation is
9426 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9427 constraint (Rd
== Rn
, BAD_OVERLAP
);
9430 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9431 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9432 inst
.instruction
|= Rd
<< 12;
9433 inst
.instruction
|= Rn
<< 16;
9434 inst
.instruction
|= inst
.operands
[4].reg
;
9440 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9441 if (inst
.operands
[1].present
)
9443 inst
.instruction
|= CPSI_MMOD
;
9444 inst
.instruction
|= inst
.operands
[1].imm
;
9451 inst
.instruction
|= inst
.operands
[0].imm
;
9457 unsigned Rd
, Rn
, Rm
;
9459 Rd
= inst
.operands
[0].reg
;
9460 Rn
= (inst
.operands
[1].present
9461 ? inst
.operands
[1].reg
: Rd
);
9462 Rm
= inst
.operands
[2].reg
;
9464 constraint ((Rd
== REG_PC
), BAD_PC
);
9465 constraint ((Rn
== REG_PC
), BAD_PC
);
9466 constraint ((Rm
== REG_PC
), BAD_PC
);
9468 inst
.instruction
|= Rd
<< 16;
9469 inst
.instruction
|= Rn
<< 0;
9470 inst
.instruction
|= Rm
<< 8;
9476 /* There is no IT instruction in ARM mode. We
9477 process it to do the validation as if in
9478 thumb mode, just in case the code gets
9479 assembled for thumb using the unified syntax. */
9484 set_pred_insn_type (IT_INSN
);
9485 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9486 now_pred
.cc
= inst
.operands
[0].imm
;
9490 /* If there is only one register in the register list,
9491 then return its register number. Otherwise return -1. */
9493 only_one_reg_in_list (int range
)
9495 int i
= ffs (range
) - 1;
9496 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9500 encode_ldmstm(int from_push_pop_mnem
)
9502 int base_reg
= inst
.operands
[0].reg
;
9503 int range
= inst
.operands
[1].imm
;
9506 inst
.instruction
|= base_reg
<< 16;
9507 inst
.instruction
|= range
;
9509 if (inst
.operands
[1].writeback
)
9510 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9512 if (inst
.operands
[0].writeback
)
9514 inst
.instruction
|= WRITE_BACK
;
9515 /* Check for unpredictable uses of writeback. */
9516 if (inst
.instruction
& LOAD_BIT
)
9518 /* Not allowed in LDM type 2. */
9519 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9520 && ((range
& (1 << REG_PC
)) == 0))
9521 as_warn (_("writeback of base register is UNPREDICTABLE"));
9522 /* Only allowed if base reg not in list for other types. */
9523 else if (range
& (1 << base_reg
))
9524 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9528 /* Not allowed for type 2. */
9529 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9530 as_warn (_("writeback of base register is UNPREDICTABLE"));
9531 /* Only allowed if base reg not in list, or first in list. */
9532 else if ((range
& (1 << base_reg
))
9533 && (range
& ((1 << base_reg
) - 1)))
9534 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9538 /* If PUSH/POP has only one register, then use the A2 encoding. */
9539 one_reg
= only_one_reg_in_list (range
);
9540 if (from_push_pop_mnem
&& one_reg
>= 0)
9542 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9544 if (is_push
&& one_reg
== 13 /* SP */)
9545 /* PR 22483: The A2 encoding cannot be used when
9546 pushing the stack pointer as this is UNPREDICTABLE. */
9549 inst
.instruction
&= A_COND_MASK
;
9550 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9551 inst
.instruction
|= one_reg
<< 12;
9558 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9561 /* ARMv5TE load-consecutive (argument parse)
9570 constraint (inst
.operands
[0].reg
% 2 != 0,
9571 _("first transfer register must be even"));
9572 constraint (inst
.operands
[1].present
9573 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9574 _("can only transfer two consecutive registers"));
9575 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9576 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9578 if (!inst
.operands
[1].present
)
9579 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9581 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9582 register and the first register written; we have to diagnose
9583 overlap between the base and the second register written here. */
9585 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9586 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9587 as_warn (_("base register written back, and overlaps "
9588 "second transfer register"));
9590 if (!(inst
.instruction
& V4_STR_BIT
))
9592 /* For an index-register load, the index register must not overlap the
9593 destination (even if not write-back). */
9594 if (inst
.operands
[2].immisreg
9595 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9596 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9597 as_warn (_("index register overlaps transfer register"));
9599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9600 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9606 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9607 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9608 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9609 || inst
.operands
[1].negative
9610 /* This can arise if the programmer has written
9612 or if they have mistakenly used a register name as the last
9615 It is very difficult to distinguish between these two cases
9616 because "rX" might actually be a label. ie the register
9617 name has been occluded by a symbol of the same name. So we
9618 just generate a general 'bad addressing mode' type error
9619 message and leave it up to the programmer to discover the
9620 true cause and fix their mistake. */
9621 || (inst
.operands
[1].reg
== REG_PC
),
9624 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9625 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9626 _("offset must be zero in ARM encoding"));
9628 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9631 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9632 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9638 constraint (inst
.operands
[0].reg
% 2 != 0,
9639 _("even register required"));
9640 constraint (inst
.operands
[1].present
9641 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9642 _("can only load two consecutive registers"));
9643 /* If op 1 were present and equal to PC, this function wouldn't
9644 have been called in the first place. */
9645 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9648 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9651 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9652 which is not a multiple of four is UNPREDICTABLE. */
9654 check_ldr_r15_aligned (void)
9656 constraint (!(inst
.operands
[1].immisreg
)
9657 && (inst
.operands
[0].reg
== REG_PC
9658 && inst
.operands
[1].reg
== REG_PC
9659 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9660 _("ldr to register 15 must be 4-byte aligned"));
9666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9667 if (!inst
.operands
[1].isreg
)
9668 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9670 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9671 check_ldr_r15_aligned ();
9677 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9679 if (inst
.operands
[1].preind
)
9681 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9682 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9683 _("this instruction requires a post-indexed address"));
9685 inst
.operands
[1].preind
= 0;
9686 inst
.operands
[1].postind
= 1;
9687 inst
.operands
[1].writeback
= 1;
9689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9690 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9693 /* Halfword and signed-byte load/store operations. */
9698 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9700 if (!inst
.operands
[1].isreg
)
9701 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9703 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9709 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9711 if (inst
.operands
[1].preind
)
9713 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9714 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9715 _("this instruction requires a post-indexed address"));
9717 inst
.operands
[1].preind
= 0;
9718 inst
.operands
[1].postind
= 1;
9719 inst
.operands
[1].writeback
= 1;
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9722 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9725 /* Co-processor register load/store.
9726 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9731 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9732 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9738 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9739 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9740 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9741 && !(inst
.instruction
& 0x00400000))
9742 as_tsktsk (_("Rd and Rm should be different in mla"));
9744 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9745 inst
.instruction
|= inst
.operands
[1].reg
;
9746 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9747 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9753 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9754 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9756 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9757 encode_arm_shifter_operand (1);
9760 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9767 top
= (inst
.instruction
& 0x00400000) != 0;
9768 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9769 _(":lower16: not allowed in this instruction"));
9770 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9771 _(":upper16: not allowed in this instruction"));
9772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9773 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9775 imm
= inst
.relocs
[0].exp
.X_add_number
;
9776 /* The value is in two pieces: 0:11, 16:19. */
9777 inst
.instruction
|= (imm
& 0x00000fff);
9778 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9783 do_vfp_nsyn_mrs (void)
9785 if (inst
.operands
[0].isvec
)
9787 if (inst
.operands
[1].reg
!= 1)
9788 first_error (_("operand 1 must be FPSCR"));
9789 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9790 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9791 do_vfp_nsyn_opcode ("fmstat");
9793 else if (inst
.operands
[1].isvec
)
9794 do_vfp_nsyn_opcode ("fmrx");
9802 do_vfp_nsyn_msr (void)
9804 if (inst
.operands
[0].isvec
)
9805 do_vfp_nsyn_opcode ("fmxr");
9815 unsigned Rt
= inst
.operands
[0].reg
;
9817 if (thumb_mode
&& Rt
== REG_SP
)
9819 inst
.error
= BAD_SP
;
9823 /* MVFR2 is only valid at ARMv8-A. */
9824 if (inst
.operands
[1].reg
== 5)
9825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9828 /* APSR_ sets isvec. All other refs to PC are illegal. */
9829 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9831 inst
.error
= BAD_PC
;
9835 /* If we get through parsing the register name, we just insert the number
9836 generated into the instruction without further validation. */
9837 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9838 inst
.instruction
|= (Rt
<< 12);
9844 unsigned Rt
= inst
.operands
[1].reg
;
9847 reject_bad_reg (Rt
);
9848 else if (Rt
== REG_PC
)
9850 inst
.error
= BAD_PC
;
9854 /* MVFR2 is only valid for ARMv8-A. */
9855 if (inst
.operands
[0].reg
== 5)
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9859 /* If we get through parsing the register name, we just insert the number
9860 generated into the instruction without further validation. */
9861 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9862 inst
.instruction
|= (Rt
<< 12);
9870 if (do_vfp_nsyn_mrs () == SUCCESS
)
9873 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9876 if (inst
.operands
[1].isreg
)
9878 br
= inst
.operands
[1].reg
;
9879 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9880 as_bad (_("bad register for mrs"));
9884 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9885 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9887 _("'APSR', 'CPSR' or 'SPSR' expected"));
9888 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9891 inst
.instruction
|= br
;
9894 /* Two possible forms:
9895 "{C|S}PSR_<field>, Rm",
9896 "{C|S}PSR_f, #expression". */
9901 if (do_vfp_nsyn_msr () == SUCCESS
)
9904 inst
.instruction
|= inst
.operands
[0].imm
;
9905 if (inst
.operands
[1].isreg
)
9906 inst
.instruction
|= inst
.operands
[1].reg
;
9909 inst
.instruction
|= INST_IMMEDIATE
;
9910 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9911 inst
.relocs
[0].pc_rel
= 0;
9918 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9920 if (!inst
.operands
[2].present
)
9921 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9923 inst
.instruction
|= inst
.operands
[1].reg
;
9924 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9926 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9927 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9928 as_tsktsk (_("Rd and Rm should be different in mul"));
9931 /* Long Multiply Parser
9932 UMULL RdLo, RdHi, Rm, Rs
9933 SMULL RdLo, RdHi, Rm, Rs
9934 UMLAL RdLo, RdHi, Rm, Rs
9935 SMLAL RdLo, RdHi, Rm, Rs. */
9940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9941 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9942 inst
.instruction
|= inst
.operands
[2].reg
;
9943 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9945 /* rdhi and rdlo must be different. */
9946 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9947 as_tsktsk (_("rdhi and rdlo must be different"));
9949 /* rdhi, rdlo and rm must all be different before armv6. */
9950 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9951 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9952 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9953 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9959 if (inst
.operands
[0].present
9960 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9962 /* Architectural NOP hints are CPSR sets with no bits selected. */
9963 inst
.instruction
&= 0xf0000000;
9964 inst
.instruction
|= 0x0320f000;
9965 if (inst
.operands
[0].present
)
9966 inst
.instruction
|= inst
.operands
[0].imm
;
9970 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9971 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9972 Condition defaults to COND_ALWAYS.
9973 Error if Rd, Rn or Rm are R15. */
9978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9980 inst
.instruction
|= inst
.operands
[2].reg
;
9981 if (inst
.operands
[3].present
)
9982 encode_arm_shift (3);
9985 /* ARM V6 PKHTB (Argument Parse). */
9990 if (!inst
.operands
[3].present
)
9992 /* If the shift specifier is omitted, turn the instruction
9993 into pkhbt rd, rm, rn. */
9994 inst
.instruction
&= 0xfff00010;
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9996 inst
.instruction
|= inst
.operands
[1].reg
;
9997 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10002 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10003 inst
.instruction
|= inst
.operands
[2].reg
;
10004 encode_arm_shift (3);
10008 /* ARMv5TE: Preload-Cache
10009 MP Extensions: Preload for write
10013 Syntactically, like LDR with B=1, W=0, L=1. */
10018 constraint (!inst
.operands
[0].isreg
,
10019 _("'[' expected after PLD mnemonic"));
10020 constraint (inst
.operands
[0].postind
,
10021 _("post-indexed expression used in preload instruction"));
10022 constraint (inst
.operands
[0].writeback
,
10023 _("writeback used in preload instruction"));
10024 constraint (!inst
.operands
[0].preind
,
10025 _("unindexed addressing used in preload instruction"));
10026 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10029 /* ARMv7: PLI <addr_mode> */
10033 constraint (!inst
.operands
[0].isreg
,
10034 _("'[' expected after PLI mnemonic"));
10035 constraint (inst
.operands
[0].postind
,
10036 _("post-indexed expression used in preload instruction"));
10037 constraint (inst
.operands
[0].writeback
,
10038 _("writeback used in preload instruction"));
10039 constraint (!inst
.operands
[0].preind
,
10040 _("unindexed addressing used in preload instruction"));
10041 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10042 inst
.instruction
&= ~PRE_INDEX
;
10048 constraint (inst
.operands
[0].writeback
,
10049 _("push/pop do not support {reglist}^"));
10050 inst
.operands
[1] = inst
.operands
[0];
10051 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10052 inst
.operands
[0].isreg
= 1;
10053 inst
.operands
[0].writeback
= 1;
10054 inst
.operands
[0].reg
= REG_SP
;
10055 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10058 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10059 word at the specified address and the following word
10061 Unconditionally executed.
10062 Error if Rn is R15. */
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10068 if (inst
.operands
[0].writeback
)
10069 inst
.instruction
|= WRITE_BACK
;
10072 /* ARM V6 ssat (argument parse). */
10077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10078 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10079 inst
.instruction
|= inst
.operands
[2].reg
;
10081 if (inst
.operands
[3].present
)
10082 encode_arm_shift (3);
10085 /* ARM V6 usat (argument parse). */
10090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10091 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10092 inst
.instruction
|= inst
.operands
[2].reg
;
10094 if (inst
.operands
[3].present
)
10095 encode_arm_shift (3);
10098 /* ARM V6 ssat16 (argument parse). */
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10104 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10105 inst
.instruction
|= inst
.operands
[2].reg
;
10111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10112 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10113 inst
.instruction
|= inst
.operands
[2].reg
;
10116 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10117 preserving the other bits.
10119 setend <endian_specifier>, where <endian_specifier> is either
10125 if (warn_on_deprecated
10126 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10127 as_tsktsk (_("setend use is deprecated for ARMv8"));
10129 if (inst
.operands
[0].imm
)
10130 inst
.instruction
|= 0x200;
10136 unsigned int Rm
= (inst
.operands
[1].present
10137 ? inst
.operands
[1].reg
10138 : inst
.operands
[0].reg
);
10140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10141 inst
.instruction
|= Rm
;
10142 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10144 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10145 inst
.instruction
|= SHIFT_BY_REG
;
10146 /* PR 12854: Error on extraneous shifts. */
10147 constraint (inst
.operands
[2].shifted
,
10148 _("extraneous shift as part of operand to shift insn"));
10151 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10157 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10158 inst
.relocs
[0].pc_rel
= 0;
10164 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10165 inst
.relocs
[0].pc_rel
= 0;
10171 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10172 inst
.relocs
[0].pc_rel
= 0;
10178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10179 _("selected processor does not support SETPAN instruction"));
10181 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10188 _("selected processor does not support SETPAN instruction"));
10190 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10193 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10194 SMLAxy{cond} Rd,Rm,Rs,Rn
10195 SMLAWy{cond} Rd,Rm,Rs,Rn
10196 Error if any register is R15. */
10201 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10202 inst
.instruction
|= inst
.operands
[1].reg
;
10203 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10204 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10207 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10208 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10209 Error if any register is R15.
10210 Warning if Rdlo == Rdhi. */
10215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10216 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10217 inst
.instruction
|= inst
.operands
[2].reg
;
10218 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10220 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10221 as_tsktsk (_("rdhi and rdlo must be different"));
10224 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10225 SMULxy{cond} Rd,Rm,Rs
10226 Error if any register is R15. */
10231 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10232 inst
.instruction
|= inst
.operands
[1].reg
;
10233 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10236 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10237 the same for both ARM and Thumb-2. */
10244 if (inst
.operands
[0].present
)
10246 reg
= inst
.operands
[0].reg
;
10247 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10252 inst
.instruction
|= reg
<< 16;
10253 inst
.instruction
|= inst
.operands
[1].imm
;
10254 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10255 inst
.instruction
|= WRITE_BACK
;
10258 /* ARM V6 strex (argument parse). */
10263 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10264 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10265 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10266 || inst
.operands
[2].negative
10267 /* See comment in do_ldrex(). */
10268 || (inst
.operands
[2].reg
== REG_PC
),
10271 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10272 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10274 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10275 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10276 _("offset must be zero in ARM encoding"));
10278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10279 inst
.instruction
|= inst
.operands
[1].reg
;
10280 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10281 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10285 do_t_strexbh (void)
10287 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10288 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10289 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10290 || inst
.operands
[2].negative
,
10293 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10294 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10302 constraint (inst
.operands
[1].reg
% 2 != 0,
10303 _("even register required"));
10304 constraint (inst
.operands
[2].present
10305 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10306 _("can only store two consecutive registers"));
10307 /* If op 2 were present and equal to PC, this function wouldn't
10308 have been called in the first place. */
10309 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10311 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10312 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10313 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10317 inst
.instruction
|= inst
.operands
[1].reg
;
10318 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10326 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10334 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10335 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10340 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10341 extends it to 32-bits, and adds the result to a value in another
10342 register. You can specify a rotation by 0, 8, 16, or 24 bits
10343 before extracting the 16-bit value.
10344 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10345 Condition defaults to COND_ALWAYS.
10346 Error if any register uses R15. */
10351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10353 inst
.instruction
|= inst
.operands
[2].reg
;
10354 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10359 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10360 Condition defaults to COND_ALWAYS.
10361 Error if any register uses R15. */
10366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10367 inst
.instruction
|= inst
.operands
[1].reg
;
10368 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10371 /* VFP instructions. In a logical order: SP variant first, monad
10372 before dyad, arithmetic then move then load/store. */
10375 do_vfp_sp_monadic (void)
10377 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10378 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10381 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10382 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10386 do_vfp_sp_dyadic (void)
10388 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10389 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10390 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10394 do_vfp_sp_compare_z (void)
10396 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10400 do_vfp_dp_sp_cvt (void)
10402 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10403 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10407 do_vfp_sp_dp_cvt (void)
10409 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10410 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10414 do_vfp_reg_from_sp (void)
10416 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10417 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10421 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10425 do_vfp_reg2_from_sp2 (void)
10427 constraint (inst
.operands
[2].imm
!= 2,
10428 _("only two consecutive VFP SP registers allowed here"));
10429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10430 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10431 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10435 do_vfp_sp_from_reg (void)
10437 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10438 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10441 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10442 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10446 do_vfp_sp2_from_reg2 (void)
10448 constraint (inst
.operands
[0].imm
!= 2,
10449 _("only two consecutive VFP SP registers allowed here"));
10450 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10451 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10452 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10456 do_vfp_sp_ldst (void)
10458 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10459 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10463 do_vfp_dp_ldst (void)
10465 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10466 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10471 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10473 if (inst
.operands
[0].writeback
)
10474 inst
.instruction
|= WRITE_BACK
;
10476 constraint (ldstm_type
!= VFP_LDSTMIA
,
10477 _("this addressing mode requires base-register writeback"));
10478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10479 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10480 inst
.instruction
|= inst
.operands
[1].imm
;
10484 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10488 if (inst
.operands
[0].writeback
)
10489 inst
.instruction
|= WRITE_BACK
;
10491 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10492 _("this addressing mode requires base-register writeback"));
10494 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10495 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10497 count
= inst
.operands
[1].imm
<< 1;
10498 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10501 inst
.instruction
|= count
;
10505 do_vfp_sp_ldstmia (void)
10507 vfp_sp_ldstm (VFP_LDSTMIA
);
10511 do_vfp_sp_ldstmdb (void)
10513 vfp_sp_ldstm (VFP_LDSTMDB
);
10517 do_vfp_dp_ldstmia (void)
10519 vfp_dp_ldstm (VFP_LDSTMIA
);
10523 do_vfp_dp_ldstmdb (void)
10525 vfp_dp_ldstm (VFP_LDSTMDB
);
10529 do_vfp_xp_ldstmia (void)
10531 vfp_dp_ldstm (VFP_LDSTMIAX
);
10535 do_vfp_xp_ldstmdb (void)
10537 vfp_dp_ldstm (VFP_LDSTMDBX
);
10541 do_vfp_dp_rd_rm (void)
10543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10544 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10547 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10548 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10552 do_vfp_dp_rn_rd (void)
10554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10555 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10559 do_vfp_dp_rd_rn (void)
10561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10562 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10566 do_vfp_dp_rd_rn_rm (void)
10568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10569 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10574 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10578 do_vfp_dp_rd (void)
10580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10584 do_vfp_dp_rm_rd_rn (void)
10586 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10587 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10592 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10595 /* VFPv3 instructions. */
10597 do_vfp_sp_const (void)
10599 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10600 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10601 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10605 do_vfp_dp_const (void)
10607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10608 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10609 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10613 vfp_conv (int srcsize
)
10615 int immbits
= srcsize
- inst
.operands
[1].imm
;
10617 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10619 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10620 i.e. immbits must be in range 0 - 16. */
10621 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10624 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10626 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10627 i.e. immbits must be in range 0 - 31. */
10628 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10632 inst
.instruction
|= (immbits
& 1) << 5;
10633 inst
.instruction
|= (immbits
>> 1);
10637 do_vfp_sp_conv_16 (void)
10639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10644 do_vfp_dp_conv_16 (void)
10646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10651 do_vfp_sp_conv_32 (void)
10653 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10658 do_vfp_dp_conv_32 (void)
10660 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10664 /* FPA instructions. Also in a logical order. */
10669 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10670 inst
.instruction
|= inst
.operands
[1].reg
;
10674 do_fpa_ldmstm (void)
10676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10677 switch (inst
.operands
[1].imm
)
10679 case 1: inst
.instruction
|= CP_T_X
; break;
10680 case 2: inst
.instruction
|= CP_T_Y
; break;
10681 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10686 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10688 /* The instruction specified "ea" or "fd", so we can only accept
10689 [Rn]{!}. The instruction does not really support stacking or
10690 unstacking, so we have to emulate these by setting appropriate
10691 bits and offsets. */
10692 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10693 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10694 _("this instruction does not support indexing"));
10696 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10697 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10699 if (!(inst
.instruction
& INDEX_UP
))
10700 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10702 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10704 inst
.operands
[2].preind
= 0;
10705 inst
.operands
[2].postind
= 1;
10709 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10712 /* iWMMXt instructions: strictly in alphabetical order. */
10715 do_iwmmxt_tandorc (void)
10717 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10721 do_iwmmxt_textrc (void)
10723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10724 inst
.instruction
|= inst
.operands
[1].imm
;
10728 do_iwmmxt_textrm (void)
10730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10732 inst
.instruction
|= inst
.operands
[2].imm
;
10736 do_iwmmxt_tinsr (void)
10738 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10739 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10740 inst
.instruction
|= inst
.operands
[2].imm
;
10744 do_iwmmxt_tmia (void)
10746 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10747 inst
.instruction
|= inst
.operands
[1].reg
;
10748 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10752 do_iwmmxt_waligni (void)
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10755 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10756 inst
.instruction
|= inst
.operands
[2].reg
;
10757 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10761 do_iwmmxt_wmerge (void)
10763 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10764 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10765 inst
.instruction
|= inst
.operands
[2].reg
;
10766 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10770 do_iwmmxt_wmov (void)
10772 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10774 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10775 inst
.instruction
|= inst
.operands
[1].reg
;
10779 do_iwmmxt_wldstbh (void)
10782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10784 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10786 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10787 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10791 do_iwmmxt_wldstw (void)
10793 /* RIWR_RIWC clears .isreg for a control register. */
10794 if (!inst
.operands
[0].isreg
)
10796 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10797 inst
.instruction
|= 0xf0000000;
10800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10801 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10805 do_iwmmxt_wldstd (void)
10807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10808 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10809 && inst
.operands
[1].immisreg
)
10811 inst
.instruction
&= ~0x1a000ff;
10812 inst
.instruction
|= (0xfU
<< 28);
10813 if (inst
.operands
[1].preind
)
10814 inst
.instruction
|= PRE_INDEX
;
10815 if (!inst
.operands
[1].negative
)
10816 inst
.instruction
|= INDEX_UP
;
10817 if (inst
.operands
[1].writeback
)
10818 inst
.instruction
|= WRITE_BACK
;
10819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10820 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10821 inst
.instruction
|= inst
.operands
[1].imm
;
10824 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10828 do_iwmmxt_wshufh (void)
10830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10832 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10833 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10837 do_iwmmxt_wzero (void)
10839 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10840 inst
.instruction
|= inst
.operands
[0].reg
;
10841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10842 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10846 do_iwmmxt_wrwrwr_or_imm5 (void)
10848 if (inst
.operands
[2].isreg
)
10851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10852 _("immediate operand requires iWMMXt2"));
10854 if (inst
.operands
[2].imm
== 0)
10856 switch ((inst
.instruction
>> 20) & 0xf)
10862 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10863 inst
.operands
[2].imm
= 16;
10864 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10870 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10871 inst
.operands
[2].imm
= 32;
10872 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10879 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10881 wrn
= (inst
.instruction
>> 16) & 0xf;
10882 inst
.instruction
&= 0xff0fff0f;
10883 inst
.instruction
|= wrn
;
10884 /* Bail out here; the instruction is now assembled. */
10889 /* Map 32 -> 0, etc. */
10890 inst
.operands
[2].imm
&= 0x1f;
10891 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10895 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10896 operations first, then control, shift, and load/store. */
10898 /* Insns like "foo X,Y,Z". */
10901 do_mav_triple (void)
10903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10904 inst
.instruction
|= inst
.operands
[1].reg
;
10905 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10908 /* Insns like "foo W,X,Y,Z".
10909 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10914 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10915 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10916 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10917 inst
.instruction
|= inst
.operands
[3].reg
;
10920 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10922 do_mav_dspsc (void)
10924 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10927 /* Maverick shift immediate instructions.
10928 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10929 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10932 do_mav_shift (void)
10934 int imm
= inst
.operands
[2].imm
;
10936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10939 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10940 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10941 Bit 4 should be 0. */
10942 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10944 inst
.instruction
|= imm
;
10947 /* XScale instructions. Also sorted arithmetic before move. */
10949 /* Xscale multiply-accumulate (argument parse)
10952 MIAxycc acc0,Rm,Rs. */
10957 inst
.instruction
|= inst
.operands
[1].reg
;
10958 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10961 /* Xscale move-accumulator-register (argument parse)
10963 MARcc acc0,RdLo,RdHi. */
10968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10969 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10972 /* Xscale move-register-accumulator (argument parse)
10974 MRAcc RdLo,RdHi,acc0. */
10979 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10981 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10984 /* Encoding functions relevant only to Thumb. */
10986 /* inst.operands[i] is a shifted-register operand; encode
10987 it into inst.instruction in the format used by Thumb32. */
10990 encode_thumb32_shifted_operand (int i
)
10992 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10993 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10995 constraint (inst
.operands
[i
].immisreg
,
10996 _("shift by register not allowed in thumb mode"));
10997 inst
.instruction
|= inst
.operands
[i
].reg
;
10998 if (shift
== SHIFT_RRX
)
10999 inst
.instruction
|= SHIFT_ROR
<< 4;
11002 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11003 _("expression too complex"));
11005 constraint (value
> 32
11006 || (value
== 32 && (shift
== SHIFT_LSL
11007 || shift
== SHIFT_ROR
)),
11008 _("shift expression is too large"));
11012 else if (value
== 32)
11015 inst
.instruction
|= shift
<< 4;
11016 inst
.instruction
|= (value
& 0x1c) << 10;
11017 inst
.instruction
|= (value
& 0x03) << 6;
11022 /* inst.operands[i] was set up by parse_address. Encode it into a
11023 Thumb32 format load or store instruction. Reject forms that cannot
11024 be used with such instructions. If is_t is true, reject forms that
11025 cannot be used with a T instruction; if is_d is true, reject forms
11026 that cannot be used with a D instruction. If it is a store insn,
11027 reject PC in Rn. */
11030 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11032 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11034 constraint (!inst
.operands
[i
].isreg
,
11035 _("Instruction does not support =N addresses"));
11037 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11038 if (inst
.operands
[i
].immisreg
)
11040 constraint (is_pc
, BAD_PC_ADDRESSING
);
11041 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11042 constraint (inst
.operands
[i
].negative
,
11043 _("Thumb does not support negative register indexing"));
11044 constraint (inst
.operands
[i
].postind
,
11045 _("Thumb does not support register post-indexing"));
11046 constraint (inst
.operands
[i
].writeback
,
11047 _("Thumb does not support register indexing with writeback"));
11048 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11049 _("Thumb supports only LSL in shifted register indexing"));
11051 inst
.instruction
|= inst
.operands
[i
].imm
;
11052 if (inst
.operands
[i
].shifted
)
11054 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11055 _("expression too complex"));
11056 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11057 || inst
.relocs
[0].exp
.X_add_number
> 3,
11058 _("shift out of range"));
11059 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11061 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11063 else if (inst
.operands
[i
].preind
)
11065 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11066 constraint (is_t
&& inst
.operands
[i
].writeback
,
11067 _("cannot use writeback with this instruction"));
11068 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11069 BAD_PC_ADDRESSING
);
11073 inst
.instruction
|= 0x01000000;
11074 if (inst
.operands
[i
].writeback
)
11075 inst
.instruction
|= 0x00200000;
11079 inst
.instruction
|= 0x00000c00;
11080 if (inst
.operands
[i
].writeback
)
11081 inst
.instruction
|= 0x00000100;
11083 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11085 else if (inst
.operands
[i
].postind
)
11087 gas_assert (inst
.operands
[i
].writeback
);
11088 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11089 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11092 inst
.instruction
|= 0x00200000;
11094 inst
.instruction
|= 0x00000900;
11095 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11097 else /* unindexed - only for coprocessor */
11098 inst
.error
= _("instruction does not accept unindexed addressing");
11101 /* Table of Thumb instructions which exist in both 16- and 32-bit
11102 encodings (the latter only in post-V6T2 cores). The index is the
11103 value used in the insns table below. When there is more than one
11104 possible 16-bit encoding for the instruction, this table always
11106 Also contains several pseudo-instructions used during relaxation. */
11107 #define T16_32_TAB \
11108 X(_adc, 4140, eb400000), \
11109 X(_adcs, 4140, eb500000), \
11110 X(_add, 1c00, eb000000), \
11111 X(_adds, 1c00, eb100000), \
11112 X(_addi, 0000, f1000000), \
11113 X(_addis, 0000, f1100000), \
11114 X(_add_pc,000f, f20f0000), \
11115 X(_add_sp,000d, f10d0000), \
11116 X(_adr, 000f, f20f0000), \
11117 X(_and, 4000, ea000000), \
11118 X(_ands, 4000, ea100000), \
11119 X(_asr, 1000, fa40f000), \
11120 X(_asrs, 1000, fa50f000), \
11121 X(_b, e000, f000b000), \
11122 X(_bcond, d000, f0008000), \
11123 X(_bf, 0000, f040e001), \
11124 X(_bfcsel,0000, f000e001), \
11125 X(_bfx, 0000, f060e001), \
11126 X(_bfl, 0000, f000c001), \
11127 X(_bflx, 0000, f070e001), \
11128 X(_bic, 4380, ea200000), \
11129 X(_bics, 4380, ea300000), \
11130 X(_cmn, 42c0, eb100f00), \
11131 X(_cmp, 2800, ebb00f00), \
11132 X(_cpsie, b660, f3af8400), \
11133 X(_cpsid, b670, f3af8600), \
11134 X(_cpy, 4600, ea4f0000), \
11135 X(_dec_sp,80dd, f1ad0d00), \
11136 X(_dls, 0000, f040e001), \
11137 X(_eor, 4040, ea800000), \
11138 X(_eors, 4040, ea900000), \
11139 X(_inc_sp,00dd, f10d0d00), \
11140 X(_ldmia, c800, e8900000), \
11141 X(_ldr, 6800, f8500000), \
11142 X(_ldrb, 7800, f8100000), \
11143 X(_ldrh, 8800, f8300000), \
11144 X(_ldrsb, 5600, f9100000), \
11145 X(_ldrsh, 5e00, f9300000), \
11146 X(_ldr_pc,4800, f85f0000), \
11147 X(_ldr_pc2,4800, f85f0000), \
11148 X(_ldr_sp,9800, f85d0000), \
11149 X(_le, 0000, f00fc001), \
11150 X(_lsl, 0000, fa00f000), \
11151 X(_lsls, 0000, fa10f000), \
11152 X(_lsr, 0800, fa20f000), \
11153 X(_lsrs, 0800, fa30f000), \
11154 X(_mov, 2000, ea4f0000), \
11155 X(_movs, 2000, ea5f0000), \
11156 X(_mul, 4340, fb00f000), \
11157 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11158 X(_mvn, 43c0, ea6f0000), \
11159 X(_mvns, 43c0, ea7f0000), \
11160 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11161 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11162 X(_orr, 4300, ea400000), \
11163 X(_orrs, 4300, ea500000), \
11164 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11165 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11166 X(_rev, ba00, fa90f080), \
11167 X(_rev16, ba40, fa90f090), \
11168 X(_revsh, bac0, fa90f0b0), \
11169 X(_ror, 41c0, fa60f000), \
11170 X(_rors, 41c0, fa70f000), \
11171 X(_sbc, 4180, eb600000), \
11172 X(_sbcs, 4180, eb700000), \
11173 X(_stmia, c000, e8800000), \
11174 X(_str, 6000, f8400000), \
11175 X(_strb, 7000, f8000000), \
11176 X(_strh, 8000, f8200000), \
11177 X(_str_sp,9000, f84d0000), \
11178 X(_sub, 1e00, eba00000), \
11179 X(_subs, 1e00, ebb00000), \
11180 X(_subi, 8000, f1a00000), \
11181 X(_subis, 8000, f1b00000), \
11182 X(_sxtb, b240, fa4ff080), \
11183 X(_sxth, b200, fa0ff080), \
11184 X(_tst, 4200, ea100f00), \
11185 X(_uxtb, b2c0, fa5ff080), \
11186 X(_uxth, b280, fa1ff080), \
11187 X(_nop, bf00, f3af8000), \
11188 X(_yield, bf10, f3af8001), \
11189 X(_wfe, bf20, f3af8002), \
11190 X(_wfi, bf30, f3af8003), \
11191 X(_wls, 0000, f040c001), \
11192 X(_sev, bf40, f3af8004), \
11193 X(_sevl, bf50, f3af8005), \
11194 X(_udf, de00, f7f0a000)
11196 /* To catch errors in encoding functions, the codes are all offset by
11197 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11198 as 16-bit instructions. */
11199 #define X(a,b,c) T_MNEM##a
11200 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11203 #define X(a,b,c) 0x##b
11204 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11205 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11208 #define X(a,b,c) 0x##c
11209 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11210 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11211 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11215 /* Thumb instruction encoders, in alphabetical order. */
11217 /* ADDW or SUBW. */
11220 do_t_add_sub_w (void)
11224 Rd
= inst
.operands
[0].reg
;
11225 Rn
= inst
.operands
[1].reg
;
11227 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11228 is the SP-{plus,minus}-immediate form of the instruction. */
11230 constraint (Rd
== REG_PC
, BAD_PC
);
11232 reject_bad_reg (Rd
);
11234 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11235 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11238 /* Parse an add or subtract instruction. We get here with inst.instruction
11239 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11242 do_t_add_sub (void)
11246 Rd
= inst
.operands
[0].reg
;
11247 Rs
= (inst
.operands
[1].present
11248 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11249 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11252 set_pred_insn_type_last ();
11254 if (unified_syntax
)
11257 bfd_boolean narrow
;
11260 flags
= (inst
.instruction
== T_MNEM_adds
11261 || inst
.instruction
== T_MNEM_subs
);
11263 narrow
= !in_pred_block ();
11265 narrow
= in_pred_block ();
11266 if (!inst
.operands
[2].isreg
)
11270 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11271 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11273 add
= (inst
.instruction
== T_MNEM_add
11274 || inst
.instruction
== T_MNEM_adds
);
11276 if (inst
.size_req
!= 4)
11278 /* Attempt to use a narrow opcode, with relaxation if
11280 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11281 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11282 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11283 opcode
= T_MNEM_add_sp
;
11284 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11285 opcode
= T_MNEM_add_pc
;
11286 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11289 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11291 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11295 inst
.instruction
= THUMB_OP16(opcode
);
11296 inst
.instruction
|= (Rd
<< 4) | Rs
;
11297 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11298 || (inst
.relocs
[0].type
11299 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11301 if (inst
.size_req
== 2)
11302 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11304 inst
.relax
= opcode
;
11308 constraint (inst
.size_req
== 2, BAD_HIREG
);
11310 if (inst
.size_req
== 4
11311 || (inst
.size_req
!= 2 && !opcode
))
11313 constraint ((inst
.relocs
[0].type
11314 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11315 && (inst
.relocs
[0].type
11316 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11317 THUMB1_RELOC_ONLY
);
11320 constraint (add
, BAD_PC
);
11321 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11322 _("only SUBS PC, LR, #const allowed"));
11323 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11324 _("expression too complex"));
11325 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11326 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11327 _("immediate value out of range"));
11328 inst
.instruction
= T2_SUBS_PC_LR
11329 | inst
.relocs
[0].exp
.X_add_number
;
11330 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11333 else if (Rs
== REG_PC
)
11335 /* Always use addw/subw. */
11336 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11337 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11341 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11342 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11345 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11347 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11349 inst
.instruction
|= Rd
<< 8;
11350 inst
.instruction
|= Rs
<< 16;
11355 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11356 unsigned int shift
= inst
.operands
[2].shift_kind
;
11358 Rn
= inst
.operands
[2].reg
;
11359 /* See if we can do this with a 16-bit instruction. */
11360 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11362 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11367 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11368 || inst
.instruction
== T_MNEM_add
)
11370 : T_OPCODE_SUB_R3
);
11371 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11375 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11377 /* Thumb-1 cores (except v6-M) require at least one high
11378 register in a narrow non flag setting add. */
11379 if (Rd
> 7 || Rn
> 7
11380 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11381 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11388 inst
.instruction
= T_OPCODE_ADD_HI
;
11389 inst
.instruction
|= (Rd
& 8) << 4;
11390 inst
.instruction
|= (Rd
& 7);
11391 inst
.instruction
|= Rn
<< 3;
11397 constraint (Rd
== REG_PC
, BAD_PC
);
11398 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11399 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11400 constraint (Rs
== REG_PC
, BAD_PC
);
11401 reject_bad_reg (Rn
);
11403 /* If we get here, it can't be done in 16 bits. */
11404 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11405 _("shift must be constant"));
11406 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11407 inst
.instruction
|= Rd
<< 8;
11408 inst
.instruction
|= Rs
<< 16;
11409 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11410 _("shift value over 3 not allowed in thumb mode"));
11411 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11412 _("only LSL shift allowed in thumb mode"));
11413 encode_thumb32_shifted_operand (2);
11418 constraint (inst
.instruction
== T_MNEM_adds
11419 || inst
.instruction
== T_MNEM_subs
,
11422 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11424 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11425 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11428 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11429 ? 0x0000 : 0x8000);
11430 inst
.instruction
|= (Rd
<< 4) | Rs
;
11431 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11435 Rn
= inst
.operands
[2].reg
;
11436 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11438 /* We now have Rd, Rs, and Rn set to registers. */
11439 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11441 /* Can't do this for SUB. */
11442 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11443 inst
.instruction
= T_OPCODE_ADD_HI
;
11444 inst
.instruction
|= (Rd
& 8) << 4;
11445 inst
.instruction
|= (Rd
& 7);
11447 inst
.instruction
|= Rn
<< 3;
11449 inst
.instruction
|= Rs
<< 3;
11451 constraint (1, _("dest must overlap one source register"));
11455 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11456 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11457 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11467 Rd
= inst
.operands
[0].reg
;
11468 reject_bad_reg (Rd
);
11470 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11472 /* Defer to section relaxation. */
11473 inst
.relax
= inst
.instruction
;
11474 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11475 inst
.instruction
|= Rd
<< 4;
11477 else if (unified_syntax
&& inst
.size_req
!= 2)
11479 /* Generate a 32-bit opcode. */
11480 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11481 inst
.instruction
|= Rd
<< 8;
11482 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11483 inst
.relocs
[0].pc_rel
= 1;
11487 /* Generate a 16-bit opcode. */
11488 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11489 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11490 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11491 inst
.relocs
[0].pc_rel
= 1;
11492 inst
.instruction
|= Rd
<< 4;
11495 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11496 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11497 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11498 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11499 inst
.relocs
[0].exp
.X_add_number
+= 1;
11502 /* Arithmetic instructions for which there is just one 16-bit
11503 instruction encoding, and it allows only two low registers.
11504 For maximal compatibility with ARM syntax, we allow three register
11505 operands even when Thumb-32 instructions are not available, as long
11506 as the first two are identical. For instance, both "sbc r0,r1" and
11507 "sbc r0,r0,r1" are allowed. */
11513 Rd
= inst
.operands
[0].reg
;
11514 Rs
= (inst
.operands
[1].present
11515 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11516 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11517 Rn
= inst
.operands
[2].reg
;
11519 reject_bad_reg (Rd
);
11520 reject_bad_reg (Rs
);
11521 if (inst
.operands
[2].isreg
)
11522 reject_bad_reg (Rn
);
11524 if (unified_syntax
)
11526 if (!inst
.operands
[2].isreg
)
11528 /* For an immediate, we always generate a 32-bit opcode;
11529 section relaxation will shrink it later if possible. */
11530 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11531 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11532 inst
.instruction
|= Rd
<< 8;
11533 inst
.instruction
|= Rs
<< 16;
11534 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11538 bfd_boolean narrow
;
11540 /* See if we can do this with a 16-bit instruction. */
11541 if (THUMB_SETS_FLAGS (inst
.instruction
))
11542 narrow
= !in_pred_block ();
11544 narrow
= in_pred_block ();
11546 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11548 if (inst
.operands
[2].shifted
)
11550 if (inst
.size_req
== 4)
11556 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11557 inst
.instruction
|= Rd
;
11558 inst
.instruction
|= Rn
<< 3;
11562 /* If we get here, it can't be done in 16 bits. */
11563 constraint (inst
.operands
[2].shifted
11564 && inst
.operands
[2].immisreg
,
11565 _("shift must be constant"));
11566 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11567 inst
.instruction
|= Rd
<< 8;
11568 inst
.instruction
|= Rs
<< 16;
11569 encode_thumb32_shifted_operand (2);
11574 /* On its face this is a lie - the instruction does set the
11575 flags. However, the only supported mnemonic in this mode
11576 says it doesn't. */
11577 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11579 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11580 _("unshifted register required"));
11581 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11582 constraint (Rd
!= Rs
,
11583 _("dest and source1 must be the same register"));
11585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11586 inst
.instruction
|= Rd
;
11587 inst
.instruction
|= Rn
<< 3;
11591 /* Similarly, but for instructions where the arithmetic operation is
11592 commutative, so we can allow either of them to be different from
11593 the destination operand in a 16-bit instruction. For instance, all
11594 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11601 Rd
= inst
.operands
[0].reg
;
11602 Rs
= (inst
.operands
[1].present
11603 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11604 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11605 Rn
= inst
.operands
[2].reg
;
11607 reject_bad_reg (Rd
);
11608 reject_bad_reg (Rs
);
11609 if (inst
.operands
[2].isreg
)
11610 reject_bad_reg (Rn
);
11612 if (unified_syntax
)
11614 if (!inst
.operands
[2].isreg
)
11616 /* For an immediate, we always generate a 32-bit opcode;
11617 section relaxation will shrink it later if possible. */
11618 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11619 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11620 inst
.instruction
|= Rd
<< 8;
11621 inst
.instruction
|= Rs
<< 16;
11622 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11626 bfd_boolean narrow
;
11628 /* See if we can do this with a 16-bit instruction. */
11629 if (THUMB_SETS_FLAGS (inst
.instruction
))
11630 narrow
= !in_pred_block ();
11632 narrow
= in_pred_block ();
11634 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11636 if (inst
.operands
[2].shifted
)
11638 if (inst
.size_req
== 4)
11645 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11646 inst
.instruction
|= Rd
;
11647 inst
.instruction
|= Rn
<< 3;
11652 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11653 inst
.instruction
|= Rd
;
11654 inst
.instruction
|= Rs
<< 3;
11659 /* If we get here, it can't be done in 16 bits. */
11660 constraint (inst
.operands
[2].shifted
11661 && inst
.operands
[2].immisreg
,
11662 _("shift must be constant"));
11663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11664 inst
.instruction
|= Rd
<< 8;
11665 inst
.instruction
|= Rs
<< 16;
11666 encode_thumb32_shifted_operand (2);
11671 /* On its face this is a lie - the instruction does set the
11672 flags. However, the only supported mnemonic in this mode
11673 says it doesn't. */
11674 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11676 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11677 _("unshifted register required"));
11678 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11680 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11681 inst
.instruction
|= Rd
;
11684 inst
.instruction
|= Rn
<< 3;
11686 inst
.instruction
|= Rs
<< 3;
11688 constraint (1, _("dest must overlap one source register"));
11696 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11697 constraint (msb
> 32, _("bit-field extends past end of register"));
11698 /* The instruction encoding stores the LSB and MSB,
11699 not the LSB and width. */
11700 Rd
= inst
.operands
[0].reg
;
11701 reject_bad_reg (Rd
);
11702 inst
.instruction
|= Rd
<< 8;
11703 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11704 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11705 inst
.instruction
|= msb
- 1;
11714 Rd
= inst
.operands
[0].reg
;
11715 reject_bad_reg (Rd
);
11717 /* #0 in second position is alternative syntax for bfc, which is
11718 the same instruction but with REG_PC in the Rm field. */
11719 if (!inst
.operands
[1].isreg
)
11723 Rn
= inst
.operands
[1].reg
;
11724 reject_bad_reg (Rn
);
11727 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11728 constraint (msb
> 32, _("bit-field extends past end of register"));
11729 /* The instruction encoding stores the LSB and MSB,
11730 not the LSB and width. */
11731 inst
.instruction
|= Rd
<< 8;
11732 inst
.instruction
|= Rn
<< 16;
11733 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11734 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11735 inst
.instruction
|= msb
- 1;
11743 Rd
= inst
.operands
[0].reg
;
11744 Rn
= inst
.operands
[1].reg
;
11746 reject_bad_reg (Rd
);
11747 reject_bad_reg (Rn
);
11749 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11750 _("bit-field extends past end of register"));
11751 inst
.instruction
|= Rd
<< 8;
11752 inst
.instruction
|= Rn
<< 16;
11753 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11754 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11755 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11758 /* ARM V5 Thumb BLX (argument parse)
11759 BLX <target_addr> which is BLX(1)
11760 BLX <Rm> which is BLX(2)
11761 Unfortunately, there are two different opcodes for this mnemonic.
11762 So, the insns[].value is not used, and the code here zaps values
11763 into inst.instruction.
11765 ??? How to take advantage of the additional two bits of displacement
11766 available in Thumb32 mode? Need new relocation? */
11771 set_pred_insn_type_last ();
11773 if (inst
.operands
[0].isreg
)
11775 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11776 /* We have a register, so this is BLX(2). */
11777 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11781 /* No register. This must be BLX(1). */
11782 inst
.instruction
= 0xf000e800;
11783 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11792 bfd_reloc_code_real_type reloc
;
11795 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11797 if (in_pred_block ())
11799 /* Conditional branches inside IT blocks are encoded as unconditional
11801 cond
= COND_ALWAYS
;
11806 if (cond
!= COND_ALWAYS
)
11807 opcode
= T_MNEM_bcond
;
11809 opcode
= inst
.instruction
;
11812 && (inst
.size_req
== 4
11813 || (inst
.size_req
!= 2
11814 && (inst
.operands
[0].hasreloc
11815 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11817 inst
.instruction
= THUMB_OP32(opcode
);
11818 if (cond
== COND_ALWAYS
)
11819 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11822 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11823 _("selected architecture does not support "
11824 "wide conditional branch instruction"));
11826 gas_assert (cond
!= 0xF);
11827 inst
.instruction
|= cond
<< 22;
11828 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11833 inst
.instruction
= THUMB_OP16(opcode
);
11834 if (cond
== COND_ALWAYS
)
11835 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11838 inst
.instruction
|= cond
<< 8;
11839 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11841 /* Allow section relaxation. */
11842 if (unified_syntax
&& inst
.size_req
!= 2)
11843 inst
.relax
= opcode
;
11845 inst
.relocs
[0].type
= reloc
;
11846 inst
.relocs
[0].pc_rel
= 1;
11849 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11850 between the two is the maximum immediate allowed - which is passed in
11853 do_t_bkpt_hlt1 (int range
)
11855 constraint (inst
.cond
!= COND_ALWAYS
,
11856 _("instruction is always unconditional"));
11857 if (inst
.operands
[0].present
)
11859 constraint (inst
.operands
[0].imm
> range
,
11860 _("immediate value out of range"));
11861 inst
.instruction
|= inst
.operands
[0].imm
;
11864 set_pred_insn_type (NEUTRAL_IT_INSN
);
11870 do_t_bkpt_hlt1 (63);
11876 do_t_bkpt_hlt1 (255);
11880 do_t_branch23 (void)
11882 set_pred_insn_type_last ();
11883 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11885 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11886 this file. We used to simply ignore the PLT reloc type here --
11887 the branch encoding is now needed to deal with TLSCALL relocs.
11888 So if we see a PLT reloc now, put it back to how it used to be to
11889 keep the preexisting behaviour. */
11890 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11891 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11893 #if defined(OBJ_COFF)
11894 /* If the destination of the branch is a defined symbol which does not have
11895 the THUMB_FUNC attribute, then we must be calling a function which has
11896 the (interfacearm) attribute. We look for the Thumb entry point to that
11897 function and change the branch to refer to that function instead. */
11898 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11899 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11900 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11901 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11902 inst
.relocs
[0].exp
.X_add_symbol
11903 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11910 set_pred_insn_type_last ();
11911 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11912 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11913 should cause the alignment to be checked once it is known. This is
11914 because BX PC only works if the instruction is word aligned. */
11922 set_pred_insn_type_last ();
11923 Rm
= inst
.operands
[0].reg
;
11924 reject_bad_reg (Rm
);
11925 inst
.instruction
|= Rm
<< 16;
11934 Rd
= inst
.operands
[0].reg
;
11935 Rm
= inst
.operands
[1].reg
;
11937 reject_bad_reg (Rd
);
11938 reject_bad_reg (Rm
);
11940 inst
.instruction
|= Rd
<< 8;
11941 inst
.instruction
|= Rm
<< 16;
11942 inst
.instruction
|= Rm
;
11948 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11954 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11955 inst
.instruction
|= inst
.operands
[0].imm
;
11961 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11963 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11964 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11966 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11967 inst
.instruction
= 0xf3af8000;
11968 inst
.instruction
|= imod
<< 9;
11969 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11970 if (inst
.operands
[1].present
)
11971 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11976 && (inst
.operands
[0].imm
& 4),
11977 _("selected processor does not support 'A' form "
11978 "of this instruction"));
11979 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11980 _("Thumb does not support the 2-argument "
11981 "form of this instruction"));
11982 inst
.instruction
|= inst
.operands
[0].imm
;
11986 /* THUMB CPY instruction (argument parse). */
11991 if (inst
.size_req
== 4)
11993 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11994 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11995 inst
.instruction
|= inst
.operands
[1].reg
;
11999 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12000 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12001 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12008 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12009 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12010 inst
.instruction
|= inst
.operands
[0].reg
;
12011 inst
.relocs
[0].pc_rel
= 1;
12012 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12018 inst
.instruction
|= inst
.operands
[0].imm
;
12024 unsigned Rd
, Rn
, Rm
;
12026 Rd
= inst
.operands
[0].reg
;
12027 Rn
= (inst
.operands
[1].present
12028 ? inst
.operands
[1].reg
: Rd
);
12029 Rm
= inst
.operands
[2].reg
;
12031 reject_bad_reg (Rd
);
12032 reject_bad_reg (Rn
);
12033 reject_bad_reg (Rm
);
12035 inst
.instruction
|= Rd
<< 8;
12036 inst
.instruction
|= Rn
<< 16;
12037 inst
.instruction
|= Rm
;
12043 if (unified_syntax
&& inst
.size_req
== 4)
12044 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12046 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12052 unsigned int cond
= inst
.operands
[0].imm
;
12054 set_pred_insn_type (IT_INSN
);
12055 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12056 now_pred
.cc
= cond
;
12057 now_pred
.warn_deprecated
= FALSE
;
12058 now_pred
.type
= SCALAR_PRED
;
12060 /* If the condition is a negative condition, invert the mask. */
12061 if ((cond
& 0x1) == 0x0)
12063 unsigned int mask
= inst
.instruction
& 0x000f;
12065 if ((mask
& 0x7) == 0)
12067 /* No conversion needed. */
12068 now_pred
.block_length
= 1;
12070 else if ((mask
& 0x3) == 0)
12073 now_pred
.block_length
= 2;
12075 else if ((mask
& 0x1) == 0)
12078 now_pred
.block_length
= 3;
12083 now_pred
.block_length
= 4;
12086 inst
.instruction
&= 0xfff0;
12087 inst
.instruction
|= mask
;
12090 inst
.instruction
|= cond
<< 4;
12093 /* Helper function used for both push/pop and ldm/stm. */
12095 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12096 bfd_boolean writeback
)
12098 bfd_boolean load
, store
;
12100 gas_assert (base
!= -1 || !do_io
);
12101 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12102 store
= do_io
&& !load
;
12104 if (mask
& (1 << 13))
12105 inst
.error
= _("SP not allowed in register list");
12107 if (do_io
&& (mask
& (1 << base
)) != 0
12109 inst
.error
= _("having the base register in the register list when "
12110 "using write back is UNPREDICTABLE");
12114 if (mask
& (1 << 15))
12116 if (mask
& (1 << 14))
12117 inst
.error
= _("LR and PC should not both be in register list");
12119 set_pred_insn_type_last ();
12124 if (mask
& (1 << 15))
12125 inst
.error
= _("PC not allowed in register list");
12128 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12130 /* Single register transfers implemented as str/ldr. */
12133 if (inst
.instruction
& (1 << 23))
12134 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12136 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12140 if (inst
.instruction
& (1 << 23))
12141 inst
.instruction
= 0x00800000; /* ia -> [base] */
12143 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12146 inst
.instruction
|= 0xf8400000;
12148 inst
.instruction
|= 0x00100000;
12150 mask
= ffs (mask
) - 1;
12153 else if (writeback
)
12154 inst
.instruction
|= WRITE_BACK
;
12156 inst
.instruction
|= mask
;
12158 inst
.instruction
|= base
<< 16;
12164 /* This really doesn't seem worth it. */
12165 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12166 _("expression too complex"));
12167 constraint (inst
.operands
[1].writeback
,
12168 _("Thumb load/store multiple does not support {reglist}^"));
12170 if (unified_syntax
)
12172 bfd_boolean narrow
;
12176 /* See if we can use a 16-bit instruction. */
12177 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12178 && inst
.size_req
!= 4
12179 && !(inst
.operands
[1].imm
& ~0xff))
12181 mask
= 1 << inst
.operands
[0].reg
;
12183 if (inst
.operands
[0].reg
<= 7)
12185 if (inst
.instruction
== T_MNEM_stmia
12186 ? inst
.operands
[0].writeback
12187 : (inst
.operands
[0].writeback
12188 == !(inst
.operands
[1].imm
& mask
)))
12190 if (inst
.instruction
== T_MNEM_stmia
12191 && (inst
.operands
[1].imm
& mask
)
12192 && (inst
.operands
[1].imm
& (mask
- 1)))
12193 as_warn (_("value stored for r%d is UNKNOWN"),
12194 inst
.operands
[0].reg
);
12196 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12197 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12198 inst
.instruction
|= inst
.operands
[1].imm
;
12201 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12203 /* This means 1 register in reg list one of 3 situations:
12204 1. Instruction is stmia, but without writeback.
12205 2. lmdia without writeback, but with Rn not in
12207 3. ldmia with writeback, but with Rn in reglist.
12208 Case 3 is UNPREDICTABLE behaviour, so we handle
12209 case 1 and 2 which can be converted into a 16-bit
12210 str or ldr. The SP cases are handled below. */
12211 unsigned long opcode
;
12212 /* First, record an error for Case 3. */
12213 if (inst
.operands
[1].imm
& mask
12214 && inst
.operands
[0].writeback
)
12216 _("having the base register in the register list when "
12217 "using write back is UNPREDICTABLE");
12219 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12221 inst
.instruction
= THUMB_OP16 (opcode
);
12222 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12223 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12227 else if (inst
.operands
[0] .reg
== REG_SP
)
12229 if (inst
.operands
[0].writeback
)
12232 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12233 ? T_MNEM_push
: T_MNEM_pop
);
12234 inst
.instruction
|= inst
.operands
[1].imm
;
12237 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12240 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12241 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12242 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12250 if (inst
.instruction
< 0xffff)
12251 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12253 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12254 inst
.operands
[1].imm
,
12255 inst
.operands
[0].writeback
);
12260 constraint (inst
.operands
[0].reg
> 7
12261 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12262 constraint (inst
.instruction
!= T_MNEM_ldmia
12263 && inst
.instruction
!= T_MNEM_stmia
,
12264 _("Thumb-2 instruction only valid in unified syntax"));
12265 if (inst
.instruction
== T_MNEM_stmia
)
12267 if (!inst
.operands
[0].writeback
)
12268 as_warn (_("this instruction will write back the base register"));
12269 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12270 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12271 as_warn (_("value stored for r%d is UNKNOWN"),
12272 inst
.operands
[0].reg
);
12276 if (!inst
.operands
[0].writeback
12277 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12278 as_warn (_("this instruction will write back the base register"));
12279 else if (inst
.operands
[0].writeback
12280 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12281 as_warn (_("this instruction will not write back the base register"));
12284 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12286 inst
.instruction
|= inst
.operands
[1].imm
;
12293 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12294 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12295 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12296 || inst
.operands
[1].negative
,
12299 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12302 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12303 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12309 if (!inst
.operands
[1].present
)
12311 constraint (inst
.operands
[0].reg
== REG_LR
,
12312 _("r14 not allowed as first register "
12313 "when second register is omitted"));
12314 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12316 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12320 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12327 unsigned long opcode
;
12330 if (inst
.operands
[0].isreg
12331 && !inst
.operands
[0].preind
12332 && inst
.operands
[0].reg
== REG_PC
)
12333 set_pred_insn_type_last ();
12335 opcode
= inst
.instruction
;
12336 if (unified_syntax
)
12338 if (!inst
.operands
[1].isreg
)
12340 if (opcode
<= 0xffff)
12341 inst
.instruction
= THUMB_OP32 (opcode
);
12342 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12345 if (inst
.operands
[1].isreg
12346 && !inst
.operands
[1].writeback
12347 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12348 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12349 && opcode
<= 0xffff
12350 && inst
.size_req
!= 4)
12352 /* Insn may have a 16-bit form. */
12353 Rn
= inst
.operands
[1].reg
;
12354 if (inst
.operands
[1].immisreg
)
12356 inst
.instruction
= THUMB_OP16 (opcode
);
12358 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12360 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12361 reject_bad_reg (inst
.operands
[1].imm
);
12363 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12364 && opcode
!= T_MNEM_ldrsb
)
12365 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12366 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12373 if (inst
.relocs
[0].pc_rel
)
12374 opcode
= T_MNEM_ldr_pc2
;
12376 opcode
= T_MNEM_ldr_pc
;
12380 if (opcode
== T_MNEM_ldr
)
12381 opcode
= T_MNEM_ldr_sp
;
12383 opcode
= T_MNEM_str_sp
;
12385 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12389 inst
.instruction
= inst
.operands
[0].reg
;
12390 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12392 inst
.instruction
|= THUMB_OP16 (opcode
);
12393 if (inst
.size_req
== 2)
12394 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12396 inst
.relax
= opcode
;
12400 /* Definitely a 32-bit variant. */
12402 /* Warning for Erratum 752419. */
12403 if (opcode
== T_MNEM_ldr
12404 && inst
.operands
[0].reg
== REG_SP
12405 && inst
.operands
[1].writeback
== 1
12406 && !inst
.operands
[1].immisreg
)
12408 if (no_cpu_selected ()
12409 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12410 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12411 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12412 as_warn (_("This instruction may be unpredictable "
12413 "if executed on M-profile cores "
12414 "with interrupts enabled."));
12417 /* Do some validations regarding addressing modes. */
12418 if (inst
.operands
[1].immisreg
)
12419 reject_bad_reg (inst
.operands
[1].imm
);
12421 constraint (inst
.operands
[1].writeback
== 1
12422 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12425 inst
.instruction
= THUMB_OP32 (opcode
);
12426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12427 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12428 check_ldr_r15_aligned ();
12432 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12434 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12436 /* Only [Rn,Rm] is acceptable. */
12437 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12438 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12439 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12440 || inst
.operands
[1].negative
,
12441 _("Thumb does not support this addressing mode"));
12442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12447 if (!inst
.operands
[1].isreg
)
12448 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12451 constraint (!inst
.operands
[1].preind
12452 || inst
.operands
[1].shifted
12453 || inst
.operands
[1].writeback
,
12454 _("Thumb does not support this addressing mode"));
12455 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12457 constraint (inst
.instruction
& 0x0600,
12458 _("byte or halfword not valid for base register"));
12459 constraint (inst
.operands
[1].reg
== REG_PC
12460 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12461 _("r15 based store not allowed"));
12462 constraint (inst
.operands
[1].immisreg
,
12463 _("invalid base register for register offset"));
12465 if (inst
.operands
[1].reg
== REG_PC
)
12466 inst
.instruction
= T_OPCODE_LDR_PC
;
12467 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12468 inst
.instruction
= T_OPCODE_LDR_SP
;
12470 inst
.instruction
= T_OPCODE_STR_SP
;
12472 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12473 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12477 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12478 if (!inst
.operands
[1].immisreg
)
12480 /* Immediate offset. */
12481 inst
.instruction
|= inst
.operands
[0].reg
;
12482 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12483 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12487 /* Register offset. */
12488 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12489 constraint (inst
.operands
[1].negative
,
12490 _("Thumb does not support this addressing mode"));
12493 switch (inst
.instruction
)
12495 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12496 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12497 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12498 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12499 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12500 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12501 case 0x5600 /* ldrsb */:
12502 case 0x5e00 /* ldrsh */: break;
12506 inst
.instruction
|= inst
.operands
[0].reg
;
12507 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12508 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12514 if (!inst
.operands
[1].present
)
12516 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12517 constraint (inst
.operands
[0].reg
== REG_LR
,
12518 _("r14 not allowed here"));
12519 constraint (inst
.operands
[0].reg
== REG_R12
,
12520 _("r12 not allowed here"));
12523 if (inst
.operands
[2].writeback
12524 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12525 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12526 as_warn (_("base register written back, and overlaps "
12527 "one of transfer registers"));
12529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12530 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12531 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12538 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12544 unsigned Rd
, Rn
, Rm
, Ra
;
12546 Rd
= inst
.operands
[0].reg
;
12547 Rn
= inst
.operands
[1].reg
;
12548 Rm
= inst
.operands
[2].reg
;
12549 Ra
= inst
.operands
[3].reg
;
12551 reject_bad_reg (Rd
);
12552 reject_bad_reg (Rn
);
12553 reject_bad_reg (Rm
);
12554 reject_bad_reg (Ra
);
12556 inst
.instruction
|= Rd
<< 8;
12557 inst
.instruction
|= Rn
<< 16;
12558 inst
.instruction
|= Rm
;
12559 inst
.instruction
|= Ra
<< 12;
12565 unsigned RdLo
, RdHi
, Rn
, Rm
;
12567 RdLo
= inst
.operands
[0].reg
;
12568 RdHi
= inst
.operands
[1].reg
;
12569 Rn
= inst
.operands
[2].reg
;
12570 Rm
= inst
.operands
[3].reg
;
12572 reject_bad_reg (RdLo
);
12573 reject_bad_reg (RdHi
);
12574 reject_bad_reg (Rn
);
12575 reject_bad_reg (Rm
);
12577 inst
.instruction
|= RdLo
<< 12;
12578 inst
.instruction
|= RdHi
<< 8;
12579 inst
.instruction
|= Rn
<< 16;
12580 inst
.instruction
|= Rm
;
12584 do_t_mov_cmp (void)
12588 Rn
= inst
.operands
[0].reg
;
12589 Rm
= inst
.operands
[1].reg
;
12592 set_pred_insn_type_last ();
12594 if (unified_syntax
)
12596 int r0off
= (inst
.instruction
== T_MNEM_mov
12597 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12598 unsigned long opcode
;
12599 bfd_boolean narrow
;
12600 bfd_boolean low_regs
;
12602 low_regs
= (Rn
<= 7 && Rm
<= 7);
12603 opcode
= inst
.instruction
;
12604 if (in_pred_block ())
12605 narrow
= opcode
!= T_MNEM_movs
;
12607 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12608 if (inst
.size_req
== 4
12609 || inst
.operands
[1].shifted
)
12612 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12613 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12614 && !inst
.operands
[1].shifted
12618 inst
.instruction
= T2_SUBS_PC_LR
;
12622 if (opcode
== T_MNEM_cmp
)
12624 constraint (Rn
== REG_PC
, BAD_PC
);
12627 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12629 warn_deprecated_sp (Rm
);
12630 /* R15 was documented as a valid choice for Rm in ARMv6,
12631 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12632 tools reject R15, so we do too. */
12633 constraint (Rm
== REG_PC
, BAD_PC
);
12636 reject_bad_reg (Rm
);
12638 else if (opcode
== T_MNEM_mov
12639 || opcode
== T_MNEM_movs
)
12641 if (inst
.operands
[1].isreg
)
12643 if (opcode
== T_MNEM_movs
)
12645 reject_bad_reg (Rn
);
12646 reject_bad_reg (Rm
);
12650 /* This is mov.n. */
12651 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12652 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12654 as_tsktsk (_("Use of r%u as a source register is "
12655 "deprecated when r%u is the destination "
12656 "register."), Rm
, Rn
);
12661 /* This is mov.w. */
12662 constraint (Rn
== REG_PC
, BAD_PC
);
12663 constraint (Rm
== REG_PC
, BAD_PC
);
12664 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12665 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12669 reject_bad_reg (Rn
);
12672 if (!inst
.operands
[1].isreg
)
12674 /* Immediate operand. */
12675 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12677 if (low_regs
&& narrow
)
12679 inst
.instruction
= THUMB_OP16 (opcode
);
12680 inst
.instruction
|= Rn
<< 8;
12681 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12682 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12684 if (inst
.size_req
== 2)
12685 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12687 inst
.relax
= opcode
;
12692 constraint ((inst
.relocs
[0].type
12693 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12694 && (inst
.relocs
[0].type
12695 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12696 THUMB1_RELOC_ONLY
);
12698 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12699 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12700 inst
.instruction
|= Rn
<< r0off
;
12701 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12704 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12705 && (inst
.instruction
== T_MNEM_mov
12706 || inst
.instruction
== T_MNEM_movs
))
12708 /* Register shifts are encoded as separate shift instructions. */
12709 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12711 if (in_pred_block ())
12716 if (inst
.size_req
== 4)
12719 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12725 switch (inst
.operands
[1].shift_kind
)
12728 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12731 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12734 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12737 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12743 inst
.instruction
= opcode
;
12746 inst
.instruction
|= Rn
;
12747 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12752 inst
.instruction
|= CONDS_BIT
;
12754 inst
.instruction
|= Rn
<< 8;
12755 inst
.instruction
|= Rm
<< 16;
12756 inst
.instruction
|= inst
.operands
[1].imm
;
12761 /* Some mov with immediate shift have narrow variants.
12762 Register shifts are handled above. */
12763 if (low_regs
&& inst
.operands
[1].shifted
12764 && (inst
.instruction
== T_MNEM_mov
12765 || inst
.instruction
== T_MNEM_movs
))
12767 if (in_pred_block ())
12768 narrow
= (inst
.instruction
== T_MNEM_mov
);
12770 narrow
= (inst
.instruction
== T_MNEM_movs
);
12775 switch (inst
.operands
[1].shift_kind
)
12777 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12778 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12779 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12780 default: narrow
= FALSE
; break;
12786 inst
.instruction
|= Rn
;
12787 inst
.instruction
|= Rm
<< 3;
12788 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12792 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12793 inst
.instruction
|= Rn
<< r0off
;
12794 encode_thumb32_shifted_operand (1);
12798 switch (inst
.instruction
)
12801 /* In v4t or v5t a move of two lowregs produces unpredictable
12802 results. Don't allow this. */
12805 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12806 "MOV Rd, Rs with two low registers is not "
12807 "permitted on this architecture");
12808 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12812 inst
.instruction
= T_OPCODE_MOV_HR
;
12813 inst
.instruction
|= (Rn
& 0x8) << 4;
12814 inst
.instruction
|= (Rn
& 0x7);
12815 inst
.instruction
|= Rm
<< 3;
12819 /* We know we have low registers at this point.
12820 Generate LSLS Rd, Rs, #0. */
12821 inst
.instruction
= T_OPCODE_LSL_I
;
12822 inst
.instruction
|= Rn
;
12823 inst
.instruction
|= Rm
<< 3;
12829 inst
.instruction
= T_OPCODE_CMP_LR
;
12830 inst
.instruction
|= Rn
;
12831 inst
.instruction
|= Rm
<< 3;
12835 inst
.instruction
= T_OPCODE_CMP_HR
;
12836 inst
.instruction
|= (Rn
& 0x8) << 4;
12837 inst
.instruction
|= (Rn
& 0x7);
12838 inst
.instruction
|= Rm
<< 3;
12845 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12847 /* PR 10443: Do not silently ignore shifted operands. */
12848 constraint (inst
.operands
[1].shifted
,
12849 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12851 if (inst
.operands
[1].isreg
)
12853 if (Rn
< 8 && Rm
< 8)
12855 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12856 since a MOV instruction produces unpredictable results. */
12857 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12858 inst
.instruction
= T_OPCODE_ADD_I3
;
12860 inst
.instruction
= T_OPCODE_CMP_LR
;
12862 inst
.instruction
|= Rn
;
12863 inst
.instruction
|= Rm
<< 3;
12867 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12868 inst
.instruction
= T_OPCODE_MOV_HR
;
12870 inst
.instruction
= T_OPCODE_CMP_HR
;
12876 constraint (Rn
> 7,
12877 _("only lo regs allowed with immediate"));
12878 inst
.instruction
|= Rn
<< 8;
12879 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12890 top
= (inst
.instruction
& 0x00800000) != 0;
12891 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12893 constraint (top
, _(":lower16: not allowed in this instruction"));
12894 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12896 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12898 constraint (!top
, _(":upper16: not allowed in this instruction"));
12899 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12902 Rd
= inst
.operands
[0].reg
;
12903 reject_bad_reg (Rd
);
12905 inst
.instruction
|= Rd
<< 8;
12906 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12908 imm
= inst
.relocs
[0].exp
.X_add_number
;
12909 inst
.instruction
|= (imm
& 0xf000) << 4;
12910 inst
.instruction
|= (imm
& 0x0800) << 15;
12911 inst
.instruction
|= (imm
& 0x0700) << 4;
12912 inst
.instruction
|= (imm
& 0x00ff);
12917 do_t_mvn_tst (void)
12921 Rn
= inst
.operands
[0].reg
;
12922 Rm
= inst
.operands
[1].reg
;
12924 if (inst
.instruction
== T_MNEM_cmp
12925 || inst
.instruction
== T_MNEM_cmn
)
12926 constraint (Rn
== REG_PC
, BAD_PC
);
12928 reject_bad_reg (Rn
);
12929 reject_bad_reg (Rm
);
12931 if (unified_syntax
)
12933 int r0off
= (inst
.instruction
== T_MNEM_mvn
12934 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12935 bfd_boolean narrow
;
12937 if (inst
.size_req
== 4
12938 || inst
.instruction
> 0xffff
12939 || inst
.operands
[1].shifted
12940 || Rn
> 7 || Rm
> 7)
12942 else if (inst
.instruction
== T_MNEM_cmn
12943 || inst
.instruction
== T_MNEM_tst
)
12945 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12946 narrow
= !in_pred_block ();
12948 narrow
= in_pred_block ();
12950 if (!inst
.operands
[1].isreg
)
12952 /* For an immediate, we always generate a 32-bit opcode;
12953 section relaxation will shrink it later if possible. */
12954 if (inst
.instruction
< 0xffff)
12955 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12956 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12957 inst
.instruction
|= Rn
<< r0off
;
12958 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12962 /* See if we can do this with a 16-bit instruction. */
12965 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12966 inst
.instruction
|= Rn
;
12967 inst
.instruction
|= Rm
<< 3;
12971 constraint (inst
.operands
[1].shifted
12972 && inst
.operands
[1].immisreg
,
12973 _("shift must be constant"));
12974 if (inst
.instruction
< 0xffff)
12975 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12976 inst
.instruction
|= Rn
<< r0off
;
12977 encode_thumb32_shifted_operand (1);
12983 constraint (inst
.instruction
> 0xffff
12984 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12985 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12986 _("unshifted register required"));
12987 constraint (Rn
> 7 || Rm
> 7,
12990 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12991 inst
.instruction
|= Rn
;
12992 inst
.instruction
|= Rm
<< 3;
13001 if (do_vfp_nsyn_mrs () == SUCCESS
)
13004 Rd
= inst
.operands
[0].reg
;
13005 reject_bad_reg (Rd
);
13006 inst
.instruction
|= Rd
<< 8;
13008 if (inst
.operands
[1].isreg
)
13010 unsigned br
= inst
.operands
[1].reg
;
13011 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13012 as_bad (_("bad register for mrs"));
13014 inst
.instruction
|= br
& (0xf << 16);
13015 inst
.instruction
|= (br
& 0x300) >> 4;
13016 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13020 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13022 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13024 /* PR gas/12698: The constraint is only applied for m_profile.
13025 If the user has specified -march=all, we want to ignore it as
13026 we are building for any CPU type, including non-m variants. */
13027 bfd_boolean m_profile
=
13028 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13029 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13030 "not support requested special purpose register"));
13033 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13035 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13036 _("'APSR', 'CPSR' or 'SPSR' expected"));
13038 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13039 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13040 inst
.instruction
|= 0xf0000;
13050 if (do_vfp_nsyn_msr () == SUCCESS
)
13053 constraint (!inst
.operands
[1].isreg
,
13054 _("Thumb encoding does not support an immediate here"));
13056 if (inst
.operands
[0].isreg
)
13057 flags
= (int)(inst
.operands
[0].reg
);
13059 flags
= inst
.operands
[0].imm
;
13061 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13063 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13065 /* PR gas/12698: The constraint is only applied for m_profile.
13066 If the user has specified -march=all, we want to ignore it as
13067 we are building for any CPU type, including non-m variants. */
13068 bfd_boolean m_profile
=
13069 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13070 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13071 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13072 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13073 && bits
!= PSR_f
)) && m_profile
,
13074 _("selected processor does not support requested special "
13075 "purpose register"));
13078 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13079 "requested special purpose register"));
13081 Rn
= inst
.operands
[1].reg
;
13082 reject_bad_reg (Rn
);
13084 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13085 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13086 inst
.instruction
|= (flags
& 0x300) >> 4;
13087 inst
.instruction
|= (flags
& 0xff);
13088 inst
.instruction
|= Rn
<< 16;
13094 bfd_boolean narrow
;
13095 unsigned Rd
, Rn
, Rm
;
13097 if (!inst
.operands
[2].present
)
13098 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13100 Rd
= inst
.operands
[0].reg
;
13101 Rn
= inst
.operands
[1].reg
;
13102 Rm
= inst
.operands
[2].reg
;
13104 if (unified_syntax
)
13106 if (inst
.size_req
== 4
13112 else if (inst
.instruction
== T_MNEM_muls
)
13113 narrow
= !in_pred_block ();
13115 narrow
= in_pred_block ();
13119 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13120 constraint (Rn
> 7 || Rm
> 7,
13127 /* 16-bit MULS/Conditional MUL. */
13128 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13129 inst
.instruction
|= Rd
;
13132 inst
.instruction
|= Rm
<< 3;
13134 inst
.instruction
|= Rn
<< 3;
13136 constraint (1, _("dest must overlap one source register"));
13140 constraint (inst
.instruction
!= T_MNEM_mul
,
13141 _("Thumb-2 MUL must not set flags"));
13143 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13144 inst
.instruction
|= Rd
<< 8;
13145 inst
.instruction
|= Rn
<< 16;
13146 inst
.instruction
|= Rm
<< 0;
13148 reject_bad_reg (Rd
);
13149 reject_bad_reg (Rn
);
13150 reject_bad_reg (Rm
);
13157 unsigned RdLo
, RdHi
, Rn
, Rm
;
13159 RdLo
= inst
.operands
[0].reg
;
13160 RdHi
= inst
.operands
[1].reg
;
13161 Rn
= inst
.operands
[2].reg
;
13162 Rm
= inst
.operands
[3].reg
;
13164 reject_bad_reg (RdLo
);
13165 reject_bad_reg (RdHi
);
13166 reject_bad_reg (Rn
);
13167 reject_bad_reg (Rm
);
13169 inst
.instruction
|= RdLo
<< 12;
13170 inst
.instruction
|= RdHi
<< 8;
13171 inst
.instruction
|= Rn
<< 16;
13172 inst
.instruction
|= Rm
;
13175 as_tsktsk (_("rdhi and rdlo must be different"));
13181 set_pred_insn_type (NEUTRAL_IT_INSN
);
13183 if (unified_syntax
)
13185 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13187 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13188 inst
.instruction
|= inst
.operands
[0].imm
;
13192 /* PR9722: Check for Thumb2 availability before
13193 generating a thumb2 nop instruction. */
13194 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13196 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13197 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13200 inst
.instruction
= 0x46c0;
13205 constraint (inst
.operands
[0].present
,
13206 _("Thumb does not support NOP with hints"));
13207 inst
.instruction
= 0x46c0;
13214 if (unified_syntax
)
13216 bfd_boolean narrow
;
13218 if (THUMB_SETS_FLAGS (inst
.instruction
))
13219 narrow
= !in_pred_block ();
13221 narrow
= in_pred_block ();
13222 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13224 if (inst
.size_req
== 4)
13229 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13230 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13231 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13235 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13236 inst
.instruction
|= inst
.operands
[0].reg
;
13237 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13242 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13244 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13246 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13247 inst
.instruction
|= inst
.operands
[0].reg
;
13248 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13257 Rd
= inst
.operands
[0].reg
;
13258 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13260 reject_bad_reg (Rd
);
13261 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13262 reject_bad_reg (Rn
);
13264 inst
.instruction
|= Rd
<< 8;
13265 inst
.instruction
|= Rn
<< 16;
13267 if (!inst
.operands
[2].isreg
)
13269 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13270 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13276 Rm
= inst
.operands
[2].reg
;
13277 reject_bad_reg (Rm
);
13279 constraint (inst
.operands
[2].shifted
13280 && inst
.operands
[2].immisreg
,
13281 _("shift must be constant"));
13282 encode_thumb32_shifted_operand (2);
13289 unsigned Rd
, Rn
, Rm
;
13291 Rd
= inst
.operands
[0].reg
;
13292 Rn
= inst
.operands
[1].reg
;
13293 Rm
= inst
.operands
[2].reg
;
13295 reject_bad_reg (Rd
);
13296 reject_bad_reg (Rn
);
13297 reject_bad_reg (Rm
);
13299 inst
.instruction
|= Rd
<< 8;
13300 inst
.instruction
|= Rn
<< 16;
13301 inst
.instruction
|= Rm
;
13302 if (inst
.operands
[3].present
)
13304 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13305 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13306 _("expression too complex"));
13307 inst
.instruction
|= (val
& 0x1c) << 10;
13308 inst
.instruction
|= (val
& 0x03) << 6;
13315 if (!inst
.operands
[3].present
)
13319 inst
.instruction
&= ~0x00000020;
13321 /* PR 10168. Swap the Rm and Rn registers. */
13322 Rtmp
= inst
.operands
[1].reg
;
13323 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13324 inst
.operands
[2].reg
= Rtmp
;
13332 if (inst
.operands
[0].immisreg
)
13333 reject_bad_reg (inst
.operands
[0].imm
);
13335 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13339 do_t_push_pop (void)
13343 constraint (inst
.operands
[0].writeback
,
13344 _("push/pop do not support {reglist}^"));
13345 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13346 _("expression too complex"));
13348 mask
= inst
.operands
[0].imm
;
13349 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13350 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13351 else if (inst
.size_req
!= 4
13352 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13353 ? REG_LR
: REG_PC
)))
13355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13356 inst
.instruction
|= THUMB_PP_PC_LR
;
13357 inst
.instruction
|= mask
& 0xff;
13359 else if (unified_syntax
)
13361 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13362 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13366 inst
.error
= _("invalid register list to push/pop instruction");
13374 if (unified_syntax
)
13375 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13378 inst
.error
= _("invalid register list to push/pop instruction");
13384 do_t_vscclrm (void)
13386 if (inst
.operands
[0].issingle
)
13388 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13389 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13390 inst
.instruction
|= inst
.operands
[0].imm
;
13394 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13395 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13396 inst
.instruction
|= 1 << 8;
13397 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13406 Rd
= inst
.operands
[0].reg
;
13407 Rm
= inst
.operands
[1].reg
;
13409 reject_bad_reg (Rd
);
13410 reject_bad_reg (Rm
);
13412 inst
.instruction
|= Rd
<< 8;
13413 inst
.instruction
|= Rm
<< 16;
13414 inst
.instruction
|= Rm
;
13422 Rd
= inst
.operands
[0].reg
;
13423 Rm
= inst
.operands
[1].reg
;
13425 reject_bad_reg (Rd
);
13426 reject_bad_reg (Rm
);
13428 if (Rd
<= 7 && Rm
<= 7
13429 && inst
.size_req
!= 4)
13431 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13432 inst
.instruction
|= Rd
;
13433 inst
.instruction
|= Rm
<< 3;
13435 else if (unified_syntax
)
13437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13438 inst
.instruction
|= Rd
<< 8;
13439 inst
.instruction
|= Rm
<< 16;
13440 inst
.instruction
|= Rm
;
13443 inst
.error
= BAD_HIREG
;
13451 Rd
= inst
.operands
[0].reg
;
13452 Rm
= inst
.operands
[1].reg
;
13454 reject_bad_reg (Rd
);
13455 reject_bad_reg (Rm
);
13457 inst
.instruction
|= Rd
<< 8;
13458 inst
.instruction
|= Rm
;
13466 Rd
= inst
.operands
[0].reg
;
13467 Rs
= (inst
.operands
[1].present
13468 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13469 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13471 reject_bad_reg (Rd
);
13472 reject_bad_reg (Rs
);
13473 if (inst
.operands
[2].isreg
)
13474 reject_bad_reg (inst
.operands
[2].reg
);
13476 inst
.instruction
|= Rd
<< 8;
13477 inst
.instruction
|= Rs
<< 16;
13478 if (!inst
.operands
[2].isreg
)
13480 bfd_boolean narrow
;
13482 if ((inst
.instruction
& 0x00100000) != 0)
13483 narrow
= !in_pred_block ();
13485 narrow
= in_pred_block ();
13487 if (Rd
> 7 || Rs
> 7)
13490 if (inst
.size_req
== 4 || !unified_syntax
)
13493 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13494 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13497 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13498 relaxation, but it doesn't seem worth the hassle. */
13501 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13502 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13503 inst
.instruction
|= Rs
<< 3;
13504 inst
.instruction
|= Rd
;
13508 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13509 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13513 encode_thumb32_shifted_operand (2);
13519 if (warn_on_deprecated
13520 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13521 as_tsktsk (_("setend use is deprecated for ARMv8"));
13523 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13524 if (inst
.operands
[0].imm
)
13525 inst
.instruction
|= 0x8;
13531 if (!inst
.operands
[1].present
)
13532 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13534 if (unified_syntax
)
13536 bfd_boolean narrow
;
13539 switch (inst
.instruction
)
13542 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13544 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13546 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13548 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13552 if (THUMB_SETS_FLAGS (inst
.instruction
))
13553 narrow
= !in_pred_block ();
13555 narrow
= in_pred_block ();
13556 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13558 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13560 if (inst
.operands
[2].isreg
13561 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13562 || inst
.operands
[2].reg
> 7))
13564 if (inst
.size_req
== 4)
13567 reject_bad_reg (inst
.operands
[0].reg
);
13568 reject_bad_reg (inst
.operands
[1].reg
);
13572 if (inst
.operands
[2].isreg
)
13574 reject_bad_reg (inst
.operands
[2].reg
);
13575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13576 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13577 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13578 inst
.instruction
|= inst
.operands
[2].reg
;
13580 /* PR 12854: Error on extraneous shifts. */
13581 constraint (inst
.operands
[2].shifted
,
13582 _("extraneous shift as part of operand to shift insn"));
13586 inst
.operands
[1].shifted
= 1;
13587 inst
.operands
[1].shift_kind
= shift_kind
;
13588 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13589 ? T_MNEM_movs
: T_MNEM_mov
);
13590 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13591 encode_thumb32_shifted_operand (1);
13592 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13593 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13598 if (inst
.operands
[2].isreg
)
13600 switch (shift_kind
)
13602 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13603 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13604 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13605 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13609 inst
.instruction
|= inst
.operands
[0].reg
;
13610 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13612 /* PR 12854: Error on extraneous shifts. */
13613 constraint (inst
.operands
[2].shifted
,
13614 _("extraneous shift as part of operand to shift insn"));
13618 switch (shift_kind
)
13620 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13621 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13622 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13625 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13626 inst
.instruction
|= inst
.operands
[0].reg
;
13627 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13633 constraint (inst
.operands
[0].reg
> 7
13634 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13635 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13637 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13639 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13640 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13641 _("source1 and dest must be same register"));
13643 switch (inst
.instruction
)
13645 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13646 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13647 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13648 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13652 inst
.instruction
|= inst
.operands
[0].reg
;
13653 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13655 /* PR 12854: Error on extraneous shifts. */
13656 constraint (inst
.operands
[2].shifted
,
13657 _("extraneous shift as part of operand to shift insn"));
13661 switch (inst
.instruction
)
13663 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13664 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13665 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13666 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13669 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13670 inst
.instruction
|= inst
.operands
[0].reg
;
13671 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13679 unsigned Rd
, Rn
, Rm
;
13681 Rd
= inst
.operands
[0].reg
;
13682 Rn
= inst
.operands
[1].reg
;
13683 Rm
= inst
.operands
[2].reg
;
13685 reject_bad_reg (Rd
);
13686 reject_bad_reg (Rn
);
13687 reject_bad_reg (Rm
);
13689 inst
.instruction
|= Rd
<< 8;
13690 inst
.instruction
|= Rn
<< 16;
13691 inst
.instruction
|= Rm
;
13697 unsigned Rd
, Rn
, Rm
;
13699 Rd
= inst
.operands
[0].reg
;
13700 Rm
= inst
.operands
[1].reg
;
13701 Rn
= inst
.operands
[2].reg
;
13703 reject_bad_reg (Rd
);
13704 reject_bad_reg (Rn
);
13705 reject_bad_reg (Rm
);
13707 inst
.instruction
|= Rd
<< 8;
13708 inst
.instruction
|= Rn
<< 16;
13709 inst
.instruction
|= Rm
;
13715 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13716 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13717 _("SMC is not permitted on this architecture"));
13718 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13719 _("expression too complex"));
13720 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13721 inst
.instruction
|= (value
& 0xf000) >> 12;
13722 inst
.instruction
|= (value
& 0x0ff0);
13723 inst
.instruction
|= (value
& 0x000f) << 16;
13724 /* PR gas/15623: SMC instructions must be last in an IT block. */
13725 set_pred_insn_type_last ();
13731 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13733 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13734 inst
.instruction
|= (value
& 0x0fff);
13735 inst
.instruction
|= (value
& 0xf000) << 4;
13739 do_t_ssat_usat (int bias
)
13743 Rd
= inst
.operands
[0].reg
;
13744 Rn
= inst
.operands
[2].reg
;
13746 reject_bad_reg (Rd
);
13747 reject_bad_reg (Rn
);
13749 inst
.instruction
|= Rd
<< 8;
13750 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13751 inst
.instruction
|= Rn
<< 16;
13753 if (inst
.operands
[3].present
)
13755 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13757 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13759 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13760 _("expression too complex"));
13762 if (shift_amount
!= 0)
13764 constraint (shift_amount
> 31,
13765 _("shift expression is too large"));
13767 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13768 inst
.instruction
|= 0x00200000; /* sh bit. */
13770 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13771 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13779 do_t_ssat_usat (1);
13787 Rd
= inst
.operands
[0].reg
;
13788 Rn
= inst
.operands
[2].reg
;
13790 reject_bad_reg (Rd
);
13791 reject_bad_reg (Rn
);
13793 inst
.instruction
|= Rd
<< 8;
13794 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13795 inst
.instruction
|= Rn
<< 16;
13801 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13802 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13803 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13804 || inst
.operands
[2].negative
,
13807 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13809 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13810 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13811 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13812 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13818 if (!inst
.operands
[2].present
)
13819 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13821 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13822 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13823 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13826 inst
.instruction
|= inst
.operands
[0].reg
;
13827 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13828 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13829 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13835 unsigned Rd
, Rn
, Rm
;
13837 Rd
= inst
.operands
[0].reg
;
13838 Rn
= inst
.operands
[1].reg
;
13839 Rm
= inst
.operands
[2].reg
;
13841 reject_bad_reg (Rd
);
13842 reject_bad_reg (Rn
);
13843 reject_bad_reg (Rm
);
13845 inst
.instruction
|= Rd
<< 8;
13846 inst
.instruction
|= Rn
<< 16;
13847 inst
.instruction
|= Rm
;
13848 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13856 Rd
= inst
.operands
[0].reg
;
13857 Rm
= inst
.operands
[1].reg
;
13859 reject_bad_reg (Rd
);
13860 reject_bad_reg (Rm
);
13862 if (inst
.instruction
<= 0xffff
13863 && inst
.size_req
!= 4
13864 && Rd
<= 7 && Rm
<= 7
13865 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13867 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13868 inst
.instruction
|= Rd
;
13869 inst
.instruction
|= Rm
<< 3;
13871 else if (unified_syntax
)
13873 if (inst
.instruction
<= 0xffff)
13874 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13875 inst
.instruction
|= Rd
<< 8;
13876 inst
.instruction
|= Rm
;
13877 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13881 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13882 _("Thumb encoding does not support rotation"));
13883 constraint (1, BAD_HIREG
);
13890 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13899 half
= (inst
.instruction
& 0x10) != 0;
13900 set_pred_insn_type_last ();
13901 constraint (inst
.operands
[0].immisreg
,
13902 _("instruction requires register index"));
13904 Rn
= inst
.operands
[0].reg
;
13905 Rm
= inst
.operands
[0].imm
;
13907 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13908 constraint (Rn
== REG_SP
, BAD_SP
);
13909 reject_bad_reg (Rm
);
13911 constraint (!half
&& inst
.operands
[0].shifted
,
13912 _("instruction does not allow shifted index"));
13913 inst
.instruction
|= (Rn
<< 16) | Rm
;
13919 if (!inst
.operands
[0].present
)
13920 inst
.operands
[0].imm
= 0;
13922 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13924 constraint (inst
.size_req
== 2,
13925 _("immediate value out of range"));
13926 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13927 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13928 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13932 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13933 inst
.instruction
|= inst
.operands
[0].imm
;
13936 set_pred_insn_type (NEUTRAL_IT_INSN
);
13943 do_t_ssat_usat (0);
13951 Rd
= inst
.operands
[0].reg
;
13952 Rn
= inst
.operands
[2].reg
;
13954 reject_bad_reg (Rd
);
13955 reject_bad_reg (Rn
);
13957 inst
.instruction
|= Rd
<< 8;
13958 inst
.instruction
|= inst
.operands
[1].imm
;
13959 inst
.instruction
|= Rn
<< 16;
13962 /* Checking the range of the branch offset (VAL) with NBITS bits
13963 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13965 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13967 gas_assert (nbits
> 0 && nbits
<= 32);
13970 int cmp
= (1 << (nbits
- 1));
13971 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13976 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13982 /* For branches in Armv8.1-M Mainline. */
13984 do_t_branch_future (void)
13986 unsigned long insn
= inst
.instruction
;
13988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13989 if (inst
.operands
[0].hasreloc
== 0)
13991 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13992 as_bad (BAD_BRANCH_OFF
);
13994 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13998 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13999 inst
.relocs
[0].pc_rel
= 1;
14005 if (inst
.operands
[1].hasreloc
== 0)
14007 int val
= inst
.operands
[1].imm
;
14008 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14009 as_bad (BAD_BRANCH_OFF
);
14011 int immA
= (val
& 0x0001f000) >> 12;
14012 int immB
= (val
& 0x00000ffc) >> 2;
14013 int immC
= (val
& 0x00000002) >> 1;
14014 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14018 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14019 inst
.relocs
[1].pc_rel
= 1;
14024 if (inst
.operands
[1].hasreloc
== 0)
14026 int val
= inst
.operands
[1].imm
;
14027 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14028 as_bad (BAD_BRANCH_OFF
);
14030 int immA
= (val
& 0x0007f000) >> 12;
14031 int immB
= (val
& 0x00000ffc) >> 2;
14032 int immC
= (val
& 0x00000002) >> 1;
14033 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14037 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14038 inst
.relocs
[1].pc_rel
= 1;
14042 case T_MNEM_bfcsel
:
14044 if (inst
.operands
[1].hasreloc
== 0)
14046 int val
= inst
.operands
[1].imm
;
14047 int immA
= (val
& 0x00001000) >> 12;
14048 int immB
= (val
& 0x00000ffc) >> 2;
14049 int immC
= (val
& 0x00000002) >> 1;
14050 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14054 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14055 inst
.relocs
[1].pc_rel
= 1;
14059 if (inst
.operands
[2].hasreloc
== 0)
14061 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14062 int val2
= inst
.operands
[2].imm
;
14063 int val0
= inst
.operands
[0].imm
& 0x1f;
14064 int diff
= val2
- val0
;
14066 inst
.instruction
|= 1 << 17; /* T bit. */
14067 else if (diff
!= 2)
14068 as_bad (_("out of range label-relative fixup value"));
14072 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14073 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14074 inst
.relocs
[2].pc_rel
= 1;
14078 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14079 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14084 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14091 /* Helper function for do_t_loloop to handle relocations. */
14093 v8_1_loop_reloc (int is_le
)
14095 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14097 int value
= inst
.relocs
[0].exp
.X_add_number
;
14098 value
= (is_le
) ? -value
: value
;
14100 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14101 as_bad (BAD_BRANCH_OFF
);
14105 immh
= (value
& 0x00000ffc) >> 2;
14106 imml
= (value
& 0x00000002) >> 1;
14108 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14112 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14113 inst
.relocs
[0].pc_rel
= 1;
14117 /* To handle the Scalar Low Overhead Loop instructions
14118 in Armv8.1-M Mainline. */
14122 unsigned long insn
= inst
.instruction
;
14124 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14125 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14131 if (!inst
.operands
[0].present
)
14132 inst
.instruction
|= 1 << 21;
14134 v8_1_loop_reloc (TRUE
);
14138 v8_1_loop_reloc (FALSE
);
14139 /* Fall through. */
14141 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14142 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14149 /* MVE instruction encoder helpers. */
14150 #define M_MNEM_vabav 0xee800f01
14151 #define M_MNEM_vmladav 0xeef00e00
14152 #define M_MNEM_vmladava 0xeef00e20
14153 #define M_MNEM_vmladavx 0xeef01e00
14154 #define M_MNEM_vmladavax 0xeef01e20
14155 #define M_MNEM_vmlsdav 0xeef00e01
14156 #define M_MNEM_vmlsdava 0xeef00e21
14157 #define M_MNEM_vmlsdavx 0xeef01e01
14158 #define M_MNEM_vmlsdavax 0xeef01e21
14159 #define M_MNEM_vmullt 0xee011e00
14160 #define M_MNEM_vmullb 0xee010e00
14161 #define M_MNEM_vst20 0xfc801e00
14162 #define M_MNEM_vst21 0xfc801e20
14163 #define M_MNEM_vst40 0xfc801e01
14164 #define M_MNEM_vst41 0xfc801e21
14165 #define M_MNEM_vst42 0xfc801e41
14166 #define M_MNEM_vst43 0xfc801e61
14167 #define M_MNEM_vld20 0xfc901e00
14168 #define M_MNEM_vld21 0xfc901e20
14169 #define M_MNEM_vld40 0xfc901e01
14170 #define M_MNEM_vld41 0xfc901e21
14171 #define M_MNEM_vld42 0xfc901e41
14172 #define M_MNEM_vld43 0xfc901e61
14173 #define M_MNEM_vstrb 0xec000e00
14174 #define M_MNEM_vstrh 0xec000e10
14175 #define M_MNEM_vstrw 0xec000e40
14176 #define M_MNEM_vstrd 0xec000e50
14177 #define M_MNEM_vldrb 0xec100e00
14178 #define M_MNEM_vldrh 0xec100e10
14179 #define M_MNEM_vldrw 0xec100e40
14180 #define M_MNEM_vldrd 0xec100e50
14181 #define M_MNEM_vmovlt 0xeea01f40
14182 #define M_MNEM_vmovlb 0xeea00f40
14183 #define M_MNEM_vmovnt 0xfe311e81
14184 #define M_MNEM_vmovnb 0xfe310e81
14185 #define M_MNEM_vadc 0xee300f00
14186 #define M_MNEM_vadci 0xee301f00
14187 #define M_MNEM_vbrsr 0xfe011e60
14188 #define M_MNEM_vaddlv 0xee890f00
14189 #define M_MNEM_vaddlva 0xee890f20
14190 #define M_MNEM_vaddv 0xeef10f00
14191 #define M_MNEM_vaddva 0xeef10f20
14192 #define M_MNEM_vddup 0xee011f6e
14193 #define M_MNEM_vdwdup 0xee011f60
14194 #define M_MNEM_vidup 0xee010f6e
14195 #define M_MNEM_viwdup 0xee010f60
14196 #define M_MNEM_vmaxv 0xeee20f00
14197 #define M_MNEM_vmaxav 0xeee00f00
14198 #define M_MNEM_vminv 0xeee20f80
14199 #define M_MNEM_vminav 0xeee00f80
14200 #define M_MNEM_vmlaldav 0xee800e00
14201 #define M_MNEM_vmlaldava 0xee800e20
14202 #define M_MNEM_vmlaldavx 0xee801e00
14203 #define M_MNEM_vmlaldavax 0xee801e20
14204 #define M_MNEM_vmlsldav 0xee800e01
14205 #define M_MNEM_vmlsldava 0xee800e21
14206 #define M_MNEM_vmlsldavx 0xee801e01
14207 #define M_MNEM_vmlsldavax 0xee801e21
14208 #define M_MNEM_vrmlaldavhx 0xee801f00
14209 #define M_MNEM_vrmlaldavhax 0xee801f20
14210 #define M_MNEM_vrmlsldavh 0xfe800e01
14211 #define M_MNEM_vrmlsldavha 0xfe800e21
14212 #define M_MNEM_vrmlsldavhx 0xfe801e01
14213 #define M_MNEM_vrmlsldavhax 0xfe801e21
14214 #define M_MNEM_vqmovnt 0xee331e01
14215 #define M_MNEM_vqmovnb 0xee330e01
14216 #define M_MNEM_vqmovunt 0xee311e81
14217 #define M_MNEM_vqmovunb 0xee310e81
14218 #define M_MNEM_vshrnt 0xee801fc1
14219 #define M_MNEM_vshrnb 0xee800fc1
14220 #define M_MNEM_vrshrnt 0xfe801fc1
14221 #define M_MNEM_vqshrnt 0xee801f40
14222 #define M_MNEM_vqshrnb 0xee800f40
14223 #define M_MNEM_vqshrunt 0xee801fc0
14224 #define M_MNEM_vqshrunb 0xee800fc0
14225 #define M_MNEM_vrshrnb 0xfe800fc1
14226 #define M_MNEM_vqrshrnt 0xee801f41
14227 #define M_MNEM_vqrshrnb 0xee800f41
14228 #define M_MNEM_vqrshrunt 0xfe801fc0
14229 #define M_MNEM_vqrshrunb 0xfe800fc0
14231 /* Neon instruction encoder helpers. */
14233 /* Encodings for the different types for various Neon opcodes. */
14235 /* An "invalid" code for the following tables. */
14238 struct neon_tab_entry
14241 unsigned float_or_poly
;
14242 unsigned scalar_or_imm
;
14245 /* Map overloaded Neon opcodes to their respective encodings. */
14246 #define NEON_ENC_TAB \
14247 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14248 X(vabdl, 0x0800700, N_INV, N_INV), \
14249 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14250 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14251 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14252 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14253 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14254 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14255 X(vaddl, 0x0800000, N_INV, N_INV), \
14256 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14257 X(vsubl, 0x0800200, N_INV, N_INV), \
14258 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14259 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14260 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14261 /* Register variants of the following two instructions are encoded as
14262 vcge / vcgt with the operands reversed. */ \
14263 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14264 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14265 X(vfma, N_INV, 0x0000c10, N_INV), \
14266 X(vfms, N_INV, 0x0200c10, N_INV), \
14267 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14268 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14269 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14270 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14271 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14272 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14273 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14274 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14275 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14276 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14277 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14278 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14279 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14280 X(vshl, 0x0000400, N_INV, 0x0800510), \
14281 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14282 X(vand, 0x0000110, N_INV, 0x0800030), \
14283 X(vbic, 0x0100110, N_INV, 0x0800030), \
14284 X(veor, 0x1000110, N_INV, N_INV), \
14285 X(vorn, 0x0300110, N_INV, 0x0800010), \
14286 X(vorr, 0x0200110, N_INV, 0x0800010), \
14287 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14288 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14289 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14290 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14291 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14292 X(vst1, 0x0000000, 0x0800000, N_INV), \
14293 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14294 X(vst2, 0x0000100, 0x0800100, N_INV), \
14295 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14296 X(vst3, 0x0000200, 0x0800200, N_INV), \
14297 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14298 X(vst4, 0x0000300, 0x0800300, N_INV), \
14299 X(vmovn, 0x1b20200, N_INV, N_INV), \
14300 X(vtrn, 0x1b20080, N_INV, N_INV), \
14301 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14302 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14303 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14304 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14305 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14306 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14307 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14308 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14309 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14310 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14311 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14312 X(vseleq, 0xe000a00, N_INV, N_INV), \
14313 X(vselvs, 0xe100a00, N_INV, N_INV), \
14314 X(vselge, 0xe200a00, N_INV, N_INV), \
14315 X(vselgt, 0xe300a00, N_INV, N_INV), \
14316 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14317 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14318 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14319 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14320 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14321 X(aes, 0x3b00300, N_INV, N_INV), \
14322 X(sha3op, 0x2000c00, N_INV, N_INV), \
14323 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14324 X(sha2op, 0x3ba0380, N_INV, N_INV)
14328 #define X(OPC,I,F,S) N_MNEM_##OPC
14333 static const struct neon_tab_entry neon_enc_tab
[] =
14335 #define X(OPC,I,F,S) { (I), (F), (S) }
14340 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14341 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14342 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14343 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14344 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14345 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14346 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14347 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14348 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14349 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14350 #define NEON_ENC_SINGLE_(X) \
14351 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14352 #define NEON_ENC_DOUBLE_(X) \
14353 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14354 #define NEON_ENC_FPV8_(X) \
14355 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14357 #define NEON_ENCODE(type, inst) \
14360 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14361 inst.is_neon = 1; \
14365 #define check_neon_suffixes \
14368 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14370 as_bad (_("invalid neon suffix for non neon instruction")); \
14376 /* Define shapes for instruction operands. The following mnemonic characters
14377 are used in this table:
14379 F - VFP S<n> register
14380 D - Neon D<n> register
14381 Q - Neon Q<n> register
14385 L - D<n> register list
14387 This table is used to generate various data:
14388 - enumerations of the form NS_DDR to be used as arguments to
14390 - a table classifying shapes into single, double, quad, mixed.
14391 - a table used to drive neon_select_shape. */
14393 #define NEON_SHAPE_DEF \
14394 X(4, (R, R, Q, Q), QUAD), \
14395 X(4, (Q, R, R, I), QUAD), \
14396 X(4, (R, R, S, S), QUAD), \
14397 X(4, (S, S, R, R), QUAD), \
14398 X(3, (Q, R, I), QUAD), \
14399 X(3, (I, Q, Q), QUAD), \
14400 X(3, (I, Q, R), QUAD), \
14401 X(3, (R, Q, Q), QUAD), \
14402 X(3, (D, D, D), DOUBLE), \
14403 X(3, (Q, Q, Q), QUAD), \
14404 X(3, (D, D, I), DOUBLE), \
14405 X(3, (Q, Q, I), QUAD), \
14406 X(3, (D, D, S), DOUBLE), \
14407 X(3, (Q, Q, S), QUAD), \
14408 X(3, (Q, Q, R), QUAD), \
14409 X(3, (R, R, Q), QUAD), \
14410 X(2, (R, Q), QUAD), \
14411 X(2, (D, D), DOUBLE), \
14412 X(2, (Q, Q), QUAD), \
14413 X(2, (D, S), DOUBLE), \
14414 X(2, (Q, S), QUAD), \
14415 X(2, (D, R), DOUBLE), \
14416 X(2, (Q, R), QUAD), \
14417 X(2, (D, I), DOUBLE), \
14418 X(2, (Q, I), QUAD), \
14419 X(3, (D, L, D), DOUBLE), \
14420 X(2, (D, Q), MIXED), \
14421 X(2, (Q, D), MIXED), \
14422 X(3, (D, Q, I), MIXED), \
14423 X(3, (Q, D, I), MIXED), \
14424 X(3, (Q, D, D), MIXED), \
14425 X(3, (D, Q, Q), MIXED), \
14426 X(3, (Q, Q, D), MIXED), \
14427 X(3, (Q, D, S), MIXED), \
14428 X(3, (D, Q, S), MIXED), \
14429 X(4, (D, D, D, I), DOUBLE), \
14430 X(4, (Q, Q, Q, I), QUAD), \
14431 X(4, (D, D, S, I), DOUBLE), \
14432 X(4, (Q, Q, S, I), QUAD), \
14433 X(2, (F, F), SINGLE), \
14434 X(3, (F, F, F), SINGLE), \
14435 X(2, (F, I), SINGLE), \
14436 X(2, (F, D), MIXED), \
14437 X(2, (D, F), MIXED), \
14438 X(3, (F, F, I), MIXED), \
14439 X(4, (R, R, F, F), SINGLE), \
14440 X(4, (F, F, R, R), SINGLE), \
14441 X(3, (D, R, R), DOUBLE), \
14442 X(3, (R, R, D), DOUBLE), \
14443 X(2, (S, R), SINGLE), \
14444 X(2, (R, S), SINGLE), \
14445 X(2, (F, R), SINGLE), \
14446 X(2, (R, F), SINGLE), \
14447 /* Half float shape supported so far. */\
14448 X (2, (H, D), MIXED), \
14449 X (2, (D, H), MIXED), \
14450 X (2, (H, F), MIXED), \
14451 X (2, (F, H), MIXED), \
14452 X (2, (H, H), HALF), \
14453 X (2, (H, R), HALF), \
14454 X (2, (R, H), HALF), \
14455 X (2, (H, I), HALF), \
14456 X (3, (H, H, H), HALF), \
14457 X (3, (H, F, I), MIXED), \
14458 X (3, (F, H, I), MIXED), \
14459 X (3, (D, H, H), MIXED), \
14460 X (3, (D, H, S), MIXED)
14462 #define S2(A,B) NS_##A##B
14463 #define S3(A,B,C) NS_##A##B##C
14464 #define S4(A,B,C,D) NS_##A##B##C##D
14466 #define X(N, L, C) S##N L
14479 enum neon_shape_class
14488 #define X(N, L, C) SC_##C
14490 static enum neon_shape_class neon_shape_class
[] =
14509 /* Register widths of above. */
14510 static unsigned neon_shape_el_size
[] =
14522 struct neon_shape_info
14525 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14528 #define S2(A,B) { SE_##A, SE_##B }
14529 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14530 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14532 #define X(N, L, C) { N, S##N L }
14534 static struct neon_shape_info neon_shape_tab
[] =
14544 /* Bit masks used in type checking given instructions.
14545 'N_EQK' means the type must be the same as (or based on in some way) the key
14546 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14547 set, various other bits can be set as well in order to modify the meaning of
14548 the type constraint. */
14550 enum neon_type_mask
14574 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14575 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14576 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14577 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14578 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14579 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14580 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14581 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14582 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14583 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14584 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14586 N_MAX_NONSPECIAL
= N_P64
14589 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14591 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14592 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14593 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14594 #define N_S_32 (N_S8 | N_S16 | N_S32)
14595 #define N_F_16_32 (N_F16 | N_F32)
14596 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14597 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14598 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14599 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14600 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14601 #define N_F_MVE (N_F16 | N_F32)
14602 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14604 /* Pass this as the first type argument to neon_check_type to ignore types
14606 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14608 /* Select a "shape" for the current instruction (describing register types or
14609 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14610 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14611 function of operand parsing, so this function doesn't need to be called.
14612 Shapes should be listed in order of decreasing length. */
14614 static enum neon_shape
14615 neon_select_shape (enum neon_shape shape
, ...)
14618 enum neon_shape first_shape
= shape
;
14620 /* Fix missing optional operands. FIXME: we don't know at this point how
14621 many arguments we should have, so this makes the assumption that we have
14622 > 1. This is true of all current Neon opcodes, I think, but may not be
14623 true in the future. */
14624 if (!inst
.operands
[1].present
)
14625 inst
.operands
[1] = inst
.operands
[0];
14627 va_start (ap
, shape
);
14629 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14634 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14636 if (!inst
.operands
[j
].present
)
14642 switch (neon_shape_tab
[shape
].el
[j
])
14644 /* If a .f16, .16, .u16, .s16 type specifier is given over
14645 a VFP single precision register operand, it's essentially
14646 means only half of the register is used.
14648 If the type specifier is given after the mnemonics, the
14649 information is stored in inst.vectype. If the type specifier
14650 is given after register operand, the information is stored
14651 in inst.operands[].vectype.
14653 When there is only one type specifier, and all the register
14654 operands are the same type of hardware register, the type
14655 specifier applies to all register operands.
14657 If no type specifier is given, the shape is inferred from
14658 operand information.
14661 vadd.f16 s0, s1, s2: NS_HHH
14662 vabs.f16 s0, s1: NS_HH
14663 vmov.f16 s0, r1: NS_HR
14664 vmov.f16 r0, s1: NS_RH
14665 vcvt.f16 r0, s1: NS_RH
14666 vcvt.f16.s32 s2, s2, #29: NS_HFI
14667 vcvt.f16.s32 s2, s2: NS_HF
14670 if (!(inst
.operands
[j
].isreg
14671 && inst
.operands
[j
].isvec
14672 && inst
.operands
[j
].issingle
14673 && !inst
.operands
[j
].isquad
14674 && ((inst
.vectype
.elems
== 1
14675 && inst
.vectype
.el
[0].size
== 16)
14676 || (inst
.vectype
.elems
> 1
14677 && inst
.vectype
.el
[j
].size
== 16)
14678 || (inst
.vectype
.elems
== 0
14679 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14680 && inst
.operands
[j
].vectype
.size
== 16))))
14685 if (!(inst
.operands
[j
].isreg
14686 && inst
.operands
[j
].isvec
14687 && inst
.operands
[j
].issingle
14688 && !inst
.operands
[j
].isquad
14689 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14690 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14691 || (inst
.vectype
.elems
== 0
14692 && (inst
.operands
[j
].vectype
.size
== 32
14693 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14698 if (!(inst
.operands
[j
].isreg
14699 && inst
.operands
[j
].isvec
14700 && !inst
.operands
[j
].isquad
14701 && !inst
.operands
[j
].issingle
))
14706 if (!(inst
.operands
[j
].isreg
14707 && !inst
.operands
[j
].isvec
))
14712 if (!(inst
.operands
[j
].isreg
14713 && inst
.operands
[j
].isvec
14714 && inst
.operands
[j
].isquad
14715 && !inst
.operands
[j
].issingle
))
14720 if (!(!inst
.operands
[j
].isreg
14721 && !inst
.operands
[j
].isscalar
))
14726 if (!(!inst
.operands
[j
].isreg
14727 && inst
.operands
[j
].isscalar
))
14737 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14738 /* We've matched all the entries in the shape table, and we don't
14739 have any left over operands which have not been matched. */
14745 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14746 first_error (_("invalid instruction shape"));
14751 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14752 means the Q bit should be set). */
14755 neon_quad (enum neon_shape shape
)
14757 return neon_shape_class
[shape
] == SC_QUAD
;
14761 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14764 /* Allow modification to be made to types which are constrained to be
14765 based on the key element, based on bits set alongside N_EQK. */
14766 if ((typebits
& N_EQK
) != 0)
14768 if ((typebits
& N_HLF
) != 0)
14770 else if ((typebits
& N_DBL
) != 0)
14772 if ((typebits
& N_SGN
) != 0)
14773 *g_type
= NT_signed
;
14774 else if ((typebits
& N_UNS
) != 0)
14775 *g_type
= NT_unsigned
;
14776 else if ((typebits
& N_INT
) != 0)
14777 *g_type
= NT_integer
;
14778 else if ((typebits
& N_FLT
) != 0)
14779 *g_type
= NT_float
;
14780 else if ((typebits
& N_SIZ
) != 0)
14781 *g_type
= NT_untyped
;
14785 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14786 operand type, i.e. the single type specified in a Neon instruction when it
14787 is the only one given. */
14789 static struct neon_type_el
14790 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14792 struct neon_type_el dest
= *key
;
14794 gas_assert ((thisarg
& N_EQK
) != 0);
14796 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14801 /* Convert Neon type and size into compact bitmask representation. */
14803 static enum neon_type_mask
14804 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14811 case 8: return N_8
;
14812 case 16: return N_16
;
14813 case 32: return N_32
;
14814 case 64: return N_64
;
14822 case 8: return N_I8
;
14823 case 16: return N_I16
;
14824 case 32: return N_I32
;
14825 case 64: return N_I64
;
14833 case 16: return N_F16
;
14834 case 32: return N_F32
;
14835 case 64: return N_F64
;
14843 case 8: return N_P8
;
14844 case 16: return N_P16
;
14845 case 64: return N_P64
;
14853 case 8: return N_S8
;
14854 case 16: return N_S16
;
14855 case 32: return N_S32
;
14856 case 64: return N_S64
;
14864 case 8: return N_U8
;
14865 case 16: return N_U16
;
14866 case 32: return N_U32
;
14867 case 64: return N_U64
;
14878 /* Convert compact Neon bitmask type representation to a type and size. Only
14879 handles the case where a single bit is set in the mask. */
14882 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14883 enum neon_type_mask mask
)
14885 if ((mask
& N_EQK
) != 0)
14888 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14890 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14892 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14894 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14899 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14901 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14902 *type
= NT_unsigned
;
14903 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14904 *type
= NT_integer
;
14905 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14906 *type
= NT_untyped
;
14907 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14909 else if ((mask
& (N_F_ALL
)) != 0)
14917 /* Modify a bitmask of allowed types. This is only needed for type
14921 modify_types_allowed (unsigned allowed
, unsigned mods
)
14924 enum neon_el_type type
;
14930 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14932 if (el_type_of_type_chk (&type
, &size
,
14933 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14935 neon_modify_type_size (mods
, &type
, &size
);
14936 destmask
|= type_chk_of_el_type (type
, size
);
14943 /* Check type and return type classification.
14944 The manual states (paraphrase): If one datatype is given, it indicates the
14946 - the second operand, if there is one
14947 - the operand, if there is no second operand
14948 - the result, if there are no operands.
14949 This isn't quite good enough though, so we use a concept of a "key" datatype
14950 which is set on a per-instruction basis, which is the one which matters when
14951 only one data type is written.
14952 Note: this function has side-effects (e.g. filling in missing operands). All
14953 Neon instructions should call it before performing bit encoding. */
14955 static struct neon_type_el
14956 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14959 unsigned i
, pass
, key_el
= 0;
14960 unsigned types
[NEON_MAX_TYPE_ELS
];
14961 enum neon_el_type k_type
= NT_invtype
;
14962 unsigned k_size
= -1u;
14963 struct neon_type_el badtype
= {NT_invtype
, -1};
14964 unsigned key_allowed
= 0;
14966 /* Optional registers in Neon instructions are always (not) in operand 1.
14967 Fill in the missing operand here, if it was omitted. */
14968 if (els
> 1 && !inst
.operands
[1].present
)
14969 inst
.operands
[1] = inst
.operands
[0];
14971 /* Suck up all the varargs. */
14973 for (i
= 0; i
< els
; i
++)
14975 unsigned thisarg
= va_arg (ap
, unsigned);
14976 if (thisarg
== N_IGNORE_TYPE
)
14981 types
[i
] = thisarg
;
14982 if ((thisarg
& N_KEY
) != 0)
14987 if (inst
.vectype
.elems
> 0)
14988 for (i
= 0; i
< els
; i
++)
14989 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14991 first_error (_("types specified in both the mnemonic and operands"));
14995 /* Duplicate inst.vectype elements here as necessary.
14996 FIXME: No idea if this is exactly the same as the ARM assembler,
14997 particularly when an insn takes one register and one non-register
14999 if (inst
.vectype
.elems
== 1 && els
> 1)
15002 inst
.vectype
.elems
= els
;
15003 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15004 for (j
= 0; j
< els
; j
++)
15006 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15009 else if (inst
.vectype
.elems
== 0 && els
> 0)
15012 /* No types were given after the mnemonic, so look for types specified
15013 after each operand. We allow some flexibility here; as long as the
15014 "key" operand has a type, we can infer the others. */
15015 for (j
= 0; j
< els
; j
++)
15016 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15017 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15019 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15021 for (j
= 0; j
< els
; j
++)
15022 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15023 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15028 first_error (_("operand types can't be inferred"));
15032 else if (inst
.vectype
.elems
!= els
)
15034 first_error (_("type specifier has the wrong number of parts"));
15038 for (pass
= 0; pass
< 2; pass
++)
15040 for (i
= 0; i
< els
; i
++)
15042 unsigned thisarg
= types
[i
];
15043 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15044 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15045 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15046 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15048 /* Decay more-specific signed & unsigned types to sign-insensitive
15049 integer types if sign-specific variants are unavailable. */
15050 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15051 && (types_allowed
& N_SU_ALL
) == 0)
15052 g_type
= NT_integer
;
15054 /* If only untyped args are allowed, decay any more specific types to
15055 them. Some instructions only care about signs for some element
15056 sizes, so handle that properly. */
15057 if (((types_allowed
& N_UNT
) == 0)
15058 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15059 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15060 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15061 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15062 g_type
= NT_untyped
;
15066 if ((thisarg
& N_KEY
) != 0)
15070 key_allowed
= thisarg
& ~N_KEY
;
15072 /* Check architecture constraint on FP16 extension. */
15074 && k_type
== NT_float
15075 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15077 inst
.error
= _(BAD_FP16
);
15084 if ((thisarg
& N_VFP
) != 0)
15086 enum neon_shape_el regshape
;
15087 unsigned regwidth
, match
;
15089 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15092 first_error (_("invalid instruction shape"));
15095 regshape
= neon_shape_tab
[ns
].el
[i
];
15096 regwidth
= neon_shape_el_size
[regshape
];
15098 /* In VFP mode, operands must match register widths. If we
15099 have a key operand, use its width, else use the width of
15100 the current operand. */
15106 /* FP16 will use a single precision register. */
15107 if (regwidth
== 32 && match
== 16)
15109 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15113 inst
.error
= _(BAD_FP16
);
15118 if (regwidth
!= match
)
15120 first_error (_("operand size must match register width"));
15125 if ((thisarg
& N_EQK
) == 0)
15127 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15129 if ((given_type
& types_allowed
) == 0)
15131 first_error (BAD_SIMD_TYPE
);
15137 enum neon_el_type mod_k_type
= k_type
;
15138 unsigned mod_k_size
= k_size
;
15139 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15140 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15142 first_error (_("inconsistent types in Neon instruction"));
15150 return inst
.vectype
.el
[key_el
];
15153 /* Neon-style VFP instruction forwarding. */
15155 /* Thumb VFP instructions have 0xE in the condition field. */
15158 do_vfp_cond_or_thumb (void)
15163 inst
.instruction
|= 0xe0000000;
15165 inst
.instruction
|= inst
.cond
<< 28;
15168 /* Look up and encode a simple mnemonic, for use as a helper function for the
15169 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15170 etc. It is assumed that operand parsing has already been done, and that the
15171 operands are in the form expected by the given opcode (this isn't necessarily
15172 the same as the form in which they were parsed, hence some massaging must
15173 take place before this function is called).
15174 Checks current arch version against that in the looked-up opcode. */
15177 do_vfp_nsyn_opcode (const char *opname
)
15179 const struct asm_opcode
*opcode
;
15181 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15186 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15187 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15194 inst
.instruction
= opcode
->tvalue
;
15195 opcode
->tencode ();
15199 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15200 opcode
->aencode ();
15205 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15207 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15209 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15212 do_vfp_nsyn_opcode ("fadds");
15214 do_vfp_nsyn_opcode ("fsubs");
15216 /* ARMv8.2 fp16 instruction. */
15218 do_scalar_fp16_v82_encode ();
15223 do_vfp_nsyn_opcode ("faddd");
15225 do_vfp_nsyn_opcode ("fsubd");
15229 /* Check operand types to see if this is a VFP instruction, and if so call
15233 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15235 enum neon_shape rs
;
15236 struct neon_type_el et
;
15241 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15242 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15246 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15247 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15248 N_F_ALL
| N_KEY
| N_VFP
);
15255 if (et
.type
!= NT_invtype
)
15266 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15268 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15270 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15273 do_vfp_nsyn_opcode ("fmacs");
15275 do_vfp_nsyn_opcode ("fnmacs");
15277 /* ARMv8.2 fp16 instruction. */
15279 do_scalar_fp16_v82_encode ();
15284 do_vfp_nsyn_opcode ("fmacd");
15286 do_vfp_nsyn_opcode ("fnmacd");
15291 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15293 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15295 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15298 do_vfp_nsyn_opcode ("ffmas");
15300 do_vfp_nsyn_opcode ("ffnmas");
15302 /* ARMv8.2 fp16 instruction. */
15304 do_scalar_fp16_v82_encode ();
15309 do_vfp_nsyn_opcode ("ffmad");
15311 do_vfp_nsyn_opcode ("ffnmad");
15316 do_vfp_nsyn_mul (enum neon_shape rs
)
15318 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15320 do_vfp_nsyn_opcode ("fmuls");
15322 /* ARMv8.2 fp16 instruction. */
15324 do_scalar_fp16_v82_encode ();
15327 do_vfp_nsyn_opcode ("fmuld");
15331 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15333 int is_neg
= (inst
.instruction
& 0x80) != 0;
15334 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15336 if (rs
== NS_FF
|| rs
== NS_HH
)
15339 do_vfp_nsyn_opcode ("fnegs");
15341 do_vfp_nsyn_opcode ("fabss");
15343 /* ARMv8.2 fp16 instruction. */
15345 do_scalar_fp16_v82_encode ();
15350 do_vfp_nsyn_opcode ("fnegd");
15352 do_vfp_nsyn_opcode ("fabsd");
15356 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15357 insns belong to Neon, and are handled elsewhere. */
15360 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15362 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15366 do_vfp_nsyn_opcode ("fldmdbs");
15368 do_vfp_nsyn_opcode ("fldmias");
15373 do_vfp_nsyn_opcode ("fstmdbs");
15375 do_vfp_nsyn_opcode ("fstmias");
15380 do_vfp_nsyn_sqrt (void)
15382 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15383 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15385 if (rs
== NS_FF
|| rs
== NS_HH
)
15387 do_vfp_nsyn_opcode ("fsqrts");
15389 /* ARMv8.2 fp16 instruction. */
15391 do_scalar_fp16_v82_encode ();
15394 do_vfp_nsyn_opcode ("fsqrtd");
15398 do_vfp_nsyn_div (void)
15400 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15401 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15402 N_F_ALL
| N_KEY
| N_VFP
);
15404 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15406 do_vfp_nsyn_opcode ("fdivs");
15408 /* ARMv8.2 fp16 instruction. */
15410 do_scalar_fp16_v82_encode ();
15413 do_vfp_nsyn_opcode ("fdivd");
15417 do_vfp_nsyn_nmul (void)
15419 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15420 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15421 N_F_ALL
| N_KEY
| N_VFP
);
15423 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15425 NEON_ENCODE (SINGLE
, inst
);
15426 do_vfp_sp_dyadic ();
15428 /* ARMv8.2 fp16 instruction. */
15430 do_scalar_fp16_v82_encode ();
15434 NEON_ENCODE (DOUBLE
, inst
);
15435 do_vfp_dp_rd_rn_rm ();
15437 do_vfp_cond_or_thumb ();
15441 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15445 neon_logbits (unsigned x
)
15447 return ffs (x
) - 4;
15450 #define LOW4(R) ((R) & 0xf)
15451 #define HI1(R) (((R) >> 4) & 1)
15454 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15459 first_error (BAD_EL_TYPE
);
15462 switch (inst
.operands
[0].imm
)
15465 first_error (_("invalid condition"));
15487 /* only accept eq and ne. */
15488 if (inst
.operands
[0].imm
> 1)
15490 first_error (_("invalid condition"));
15493 return inst
.operands
[0].imm
;
15495 if (inst
.operands
[0].imm
== 0x2)
15497 else if (inst
.operands
[0].imm
== 0x8)
15501 first_error (_("invalid condition"));
15505 switch (inst
.operands
[0].imm
)
15508 first_error (_("invalid condition"));
15524 /* Should be unreachable. */
15531 /* We are dealing with a vector predicated block. */
15532 if (inst
.operands
[0].present
)
15534 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15535 struct neon_type_el et
15536 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15539 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15541 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15543 if (et
.type
== NT_invtype
)
15546 if (et
.type
== NT_float
)
15548 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15550 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15551 inst
.instruction
|= (et
.size
== 16) << 28;
15552 inst
.instruction
|= 0x3 << 20;
15556 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15558 inst
.instruction
|= 1 << 28;
15559 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15562 if (inst
.operands
[2].isquad
)
15564 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15565 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15566 inst
.instruction
|= (fcond
& 0x2) >> 1;
15570 if (inst
.operands
[2].reg
== REG_SP
)
15571 as_tsktsk (MVE_BAD_SP
);
15572 inst
.instruction
|= 1 << 6;
15573 inst
.instruction
|= (fcond
& 0x2) << 4;
15574 inst
.instruction
|= inst
.operands
[2].reg
;
15576 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15577 inst
.instruction
|= (fcond
& 0x4) << 10;
15578 inst
.instruction
|= (fcond
& 0x1) << 7;
15581 set_pred_insn_type (VPT_INSN
);
15583 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15584 | ((inst
.instruction
& 0xe000) >> 13);
15585 now_pred
.warn_deprecated
= FALSE
;
15586 now_pred
.type
= VECTOR_PRED
;
15593 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15594 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15595 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15596 if (!inst
.operands
[2].present
)
15597 first_error (_("MVE vector or ARM register expected"));
15598 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15600 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15601 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15602 && inst
.operands
[1].isquad
)
15604 inst
.instruction
= N_MNEM_vcmp
;
15608 if (inst
.cond
> COND_ALWAYS
)
15609 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15611 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15613 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15614 struct neon_type_el et
15615 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15618 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15619 && !inst
.operands
[2].iszr
, BAD_PC
);
15621 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15623 inst
.instruction
= 0xee010f00;
15624 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15625 inst
.instruction
|= (fcond
& 0x4) << 10;
15626 inst
.instruction
|= (fcond
& 0x1) << 7;
15627 if (et
.type
== NT_float
)
15629 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15631 inst
.instruction
|= (et
.size
== 16) << 28;
15632 inst
.instruction
|= 0x3 << 20;
15636 inst
.instruction
|= 1 << 28;
15637 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15639 if (inst
.operands
[2].isquad
)
15641 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15642 inst
.instruction
|= (fcond
& 0x2) >> 1;
15643 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15647 if (inst
.operands
[2].reg
== REG_SP
)
15648 as_tsktsk (MVE_BAD_SP
);
15649 inst
.instruction
|= 1 << 6;
15650 inst
.instruction
|= (fcond
& 0x2) << 4;
15651 inst
.instruction
|= inst
.operands
[2].reg
;
15659 do_mve_vmaxa_vmina (void)
15661 if (inst
.cond
> COND_ALWAYS
)
15662 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15664 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15666 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15667 struct neon_type_el et
15668 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15671 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15672 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15673 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15674 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15679 do_mve_vfmas (void)
15681 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15682 struct neon_type_el et
15683 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15685 if (inst
.cond
> COND_ALWAYS
)
15686 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15688 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15690 if (inst
.operands
[2].reg
== REG_SP
)
15691 as_tsktsk (MVE_BAD_SP
);
15692 else if (inst
.operands
[2].reg
== REG_PC
)
15693 as_tsktsk (MVE_BAD_PC
);
15695 inst
.instruction
|= (et
.size
== 16) << 28;
15696 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15698 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15699 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15700 inst
.instruction
|= inst
.operands
[2].reg
;
15705 do_mve_viddup (void)
15707 if (inst
.cond
> COND_ALWAYS
)
15708 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15710 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15712 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15713 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15714 _("immediate must be either 1, 2, 4 or 8"));
15716 enum neon_shape rs
;
15717 struct neon_type_el et
;
15719 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15721 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15722 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15727 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15728 if (inst
.operands
[2].reg
== REG_SP
)
15729 as_tsktsk (MVE_BAD_SP
);
15730 else if (inst
.operands
[2].reg
== REG_PC
)
15731 first_error (BAD_PC
);
15733 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15734 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15735 Rm
= inst
.operands
[2].reg
>> 1;
15737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15738 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15739 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15741 inst
.instruction
|= (imm
> 2) << 7;
15742 inst
.instruction
|= Rm
<< 1;
15743 inst
.instruction
|= (imm
== 2 || imm
== 8);
15748 do_mve_vmlas (void)
15750 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15751 struct neon_type_el et
15752 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15754 if (inst
.operands
[2].reg
== REG_PC
)
15755 as_tsktsk (MVE_BAD_PC
);
15756 else if (inst
.operands
[2].reg
== REG_SP
)
15757 as_tsktsk (MVE_BAD_SP
);
15759 if (inst
.cond
> COND_ALWAYS
)
15760 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15762 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15764 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15765 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15766 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15767 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15768 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15769 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15770 inst
.instruction
|= inst
.operands
[2].reg
;
15775 do_mve_vshll (void)
15777 struct neon_type_el et
15778 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15780 if (inst
.cond
> COND_ALWAYS
)
15781 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15783 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15785 int imm
= inst
.operands
[2].imm
;
15786 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15787 _("immediate value out of range"));
15789 if ((unsigned)imm
== et
.size
)
15791 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15792 inst
.instruction
|= 0x110001;
15796 inst
.instruction
|= (et
.size
+ imm
) << 16;
15797 inst
.instruction
|= 0x800140;
15800 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15801 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15802 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15803 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15804 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15809 do_mve_vshlc (void)
15811 if (inst
.cond
> COND_ALWAYS
)
15812 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15814 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15816 if (inst
.operands
[1].reg
== REG_PC
)
15817 as_tsktsk (MVE_BAD_PC
);
15818 else if (inst
.operands
[1].reg
== REG_SP
)
15819 as_tsktsk (MVE_BAD_SP
);
15821 int imm
= inst
.operands
[2].imm
;
15822 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15824 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15825 inst
.instruction
|= (imm
& 0x1f) << 16;
15826 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15827 inst
.instruction
|= inst
.operands
[1].reg
;
15832 do_mve_vshrn (void)
15835 switch (inst
.instruction
)
15837 case M_MNEM_vshrnt
:
15838 case M_MNEM_vshrnb
:
15839 case M_MNEM_vrshrnt
:
15840 case M_MNEM_vrshrnb
:
15841 types
= N_I16
| N_I32
;
15843 case M_MNEM_vqshrnt
:
15844 case M_MNEM_vqshrnb
:
15845 case M_MNEM_vqrshrnt
:
15846 case M_MNEM_vqrshrnb
:
15847 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15849 case M_MNEM_vqshrunt
:
15850 case M_MNEM_vqshrunb
:
15851 case M_MNEM_vqrshrunt
:
15852 case M_MNEM_vqrshrunb
:
15853 types
= N_S16
| N_S32
;
15859 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15861 if (inst
.cond
> COND_ALWAYS
)
15862 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15864 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15866 unsigned Qd
= inst
.operands
[0].reg
;
15867 unsigned Qm
= inst
.operands
[1].reg
;
15868 unsigned imm
= inst
.operands
[2].imm
;
15869 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15871 ? _("immediate operand expected in the range [1,8]")
15872 : _("immediate operand expected in the range [1,16]"));
15874 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15875 inst
.instruction
|= HI1 (Qd
) << 22;
15876 inst
.instruction
|= (et
.size
- imm
) << 16;
15877 inst
.instruction
|= LOW4 (Qd
) << 12;
15878 inst
.instruction
|= HI1 (Qm
) << 5;
15879 inst
.instruction
|= LOW4 (Qm
);
15884 do_mve_vqmovn (void)
15886 struct neon_type_el et
;
15887 if (inst
.instruction
== M_MNEM_vqmovnt
15888 || inst
.instruction
== M_MNEM_vqmovnb
)
15889 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15890 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15892 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15894 if (inst
.cond
> COND_ALWAYS
)
15895 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15897 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15899 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15900 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15901 inst
.instruction
|= (et
.size
== 32) << 18;
15902 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15903 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15904 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15909 do_mve_vpsel (void)
15911 neon_select_shape (NS_QQQ
, NS_NULL
);
15913 if (inst
.cond
> COND_ALWAYS
)
15914 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15916 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15918 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15919 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15920 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15921 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15922 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15923 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15928 do_mve_vpnot (void)
15930 if (inst
.cond
> COND_ALWAYS
)
15931 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15933 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15937 do_mve_vmaxnma_vminnma (void)
15939 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15940 struct neon_type_el et
15941 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15943 if (inst
.cond
> COND_ALWAYS
)
15944 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15946 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15948 inst
.instruction
|= (et
.size
== 16) << 28;
15949 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15950 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15951 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15952 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15957 do_mve_vcmul (void)
15959 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15960 struct neon_type_el et
15961 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15963 if (inst
.cond
> COND_ALWAYS
)
15964 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15966 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15968 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15969 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15970 _("immediate out of range"));
15972 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15973 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15974 as_tsktsk (BAD_MVE_SRCDEST
);
15976 inst
.instruction
|= (et
.size
== 32) << 28;
15977 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15980 inst
.instruction
|= (rot
> 90) << 12;
15981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15982 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15983 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15984 inst
.instruction
|= (rot
== 90 || rot
== 270);
15989 do_vfp_nsyn_cmp (void)
15991 enum neon_shape rs
;
15992 if (!inst
.operands
[0].isreg
)
15999 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16000 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16004 if (inst
.operands
[1].isreg
)
16006 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16007 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16009 if (rs
== NS_FF
|| rs
== NS_HH
)
16011 NEON_ENCODE (SINGLE
, inst
);
16012 do_vfp_sp_monadic ();
16016 NEON_ENCODE (DOUBLE
, inst
);
16017 do_vfp_dp_rd_rm ();
16022 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16023 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16025 switch (inst
.instruction
& 0x0fffffff)
16028 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16031 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16037 if (rs
== NS_FI
|| rs
== NS_HI
)
16039 NEON_ENCODE (SINGLE
, inst
);
16040 do_vfp_sp_compare_z ();
16044 NEON_ENCODE (DOUBLE
, inst
);
16048 do_vfp_cond_or_thumb ();
16050 /* ARMv8.2 fp16 instruction. */
16051 if (rs
== NS_HI
|| rs
== NS_HH
)
16052 do_scalar_fp16_v82_encode ();
16056 nsyn_insert_sp (void)
16058 inst
.operands
[1] = inst
.operands
[0];
16059 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16060 inst
.operands
[0].reg
= REG_SP
;
16061 inst
.operands
[0].isreg
= 1;
16062 inst
.operands
[0].writeback
= 1;
16063 inst
.operands
[0].present
= 1;
16067 do_vfp_nsyn_push (void)
16071 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16072 _("register list must contain at least 1 and at most 16 "
16075 if (inst
.operands
[1].issingle
)
16076 do_vfp_nsyn_opcode ("fstmdbs");
16078 do_vfp_nsyn_opcode ("fstmdbd");
16082 do_vfp_nsyn_pop (void)
16086 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16087 _("register list must contain at least 1 and at most 16 "
16090 if (inst
.operands
[1].issingle
)
16091 do_vfp_nsyn_opcode ("fldmias");
16093 do_vfp_nsyn_opcode ("fldmiad");
16096 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16097 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16100 neon_dp_fixup (struct arm_it
* insn
)
16102 unsigned int i
= insn
->instruction
;
16107 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16118 insn
->instruction
= i
;
16122 mve_encode_qqr (int size
, int U
, int fp
)
16124 if (inst
.operands
[2].reg
== REG_SP
)
16125 as_tsktsk (MVE_BAD_SP
);
16126 else if (inst
.operands
[2].reg
== REG_PC
)
16127 as_tsktsk (MVE_BAD_PC
);
16132 if (((unsigned)inst
.instruction
) == 0xd00)
16133 inst
.instruction
= 0xee300f40;
16135 else if (((unsigned)inst
.instruction
) == 0x200d00)
16136 inst
.instruction
= 0xee301f40;
16138 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16139 inst
.instruction
= 0xee310e60;
16141 /* Setting size which is 1 for F16 and 0 for F32. */
16142 inst
.instruction
|= (size
== 16) << 28;
16147 if (((unsigned)inst
.instruction
) == 0x800)
16148 inst
.instruction
= 0xee010f40;
16150 else if (((unsigned)inst
.instruction
) == 0x1000800)
16151 inst
.instruction
= 0xee011f40;
16153 else if (((unsigned)inst
.instruction
) == 0)
16154 inst
.instruction
= 0xee000f40;
16156 else if (((unsigned)inst
.instruction
) == 0x200)
16157 inst
.instruction
= 0xee001f40;
16159 else if (((unsigned)inst
.instruction
) == 0x900)
16160 inst
.instruction
= 0xee010e40;
16162 else if (((unsigned)inst
.instruction
) == 0x910)
16163 inst
.instruction
= 0xee011e60;
16165 else if (((unsigned)inst
.instruction
) == 0x10)
16166 inst
.instruction
= 0xee000f60;
16168 else if (((unsigned)inst
.instruction
) == 0x210)
16169 inst
.instruction
= 0xee001f60;
16171 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16172 inst
.instruction
= 0xee000e40;
16174 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16175 inst
.instruction
= 0xee010e60;
16177 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16178 inst
.instruction
= 0xfe010e60;
16181 inst
.instruction
|= U
<< 28;
16183 /* Setting bits for size. */
16184 inst
.instruction
|= neon_logbits (size
) << 20;
16186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16190 inst
.instruction
|= inst
.operands
[2].reg
;
16195 mve_encode_rqq (unsigned bit28
, unsigned size
)
16197 inst
.instruction
|= bit28
<< 28;
16198 inst
.instruction
|= neon_logbits (size
) << 20;
16199 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16201 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16202 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16203 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16208 mve_encode_qqq (int ubit
, int size
)
16211 inst
.instruction
|= (ubit
!= 0) << 28;
16212 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16213 inst
.instruction
|= neon_logbits (size
) << 20;
16214 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16215 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16216 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16217 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16218 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16224 mve_encode_rq (unsigned bit28
, unsigned size
)
16226 inst
.instruction
|= bit28
<< 28;
16227 inst
.instruction
|= neon_logbits (size
) << 18;
16228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16229 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16234 mve_encode_rrqq (unsigned U
, unsigned size
)
16236 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16238 inst
.instruction
|= U
<< 28;
16239 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16240 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16241 inst
.instruction
|= (size
== 32) << 16;
16242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16243 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16244 inst
.instruction
|= inst
.operands
[3].reg
;
16248 /* Encode insns with bit pattern:
16250 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16251 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16253 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16254 different meaning for some instruction. */
16257 neon_three_same (int isquad
, int ubit
, int size
)
16259 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16260 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16261 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16262 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16263 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16264 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16265 inst
.instruction
|= (isquad
!= 0) << 6;
16266 inst
.instruction
|= (ubit
!= 0) << 24;
16268 inst
.instruction
|= neon_logbits (size
) << 20;
16270 neon_dp_fixup (&inst
);
16273 /* Encode instructions of the form:
16275 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16276 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16278 Don't write size if SIZE == -1. */
16281 neon_two_same (int qbit
, int ubit
, int size
)
16283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16287 inst
.instruction
|= (qbit
!= 0) << 6;
16288 inst
.instruction
|= (ubit
!= 0) << 24;
16291 inst
.instruction
|= neon_logbits (size
) << 18;
16293 neon_dp_fixup (&inst
);
16296 enum vfp_or_neon_is_neon_bits
16299 NEON_CHECK_ARCH
= 2,
16300 NEON_CHECK_ARCH8
= 4
16303 /* Call this function if an instruction which may have belonged to the VFP or
16304 Neon instruction sets, but turned out to be a Neon instruction (due to the
16305 operand types involved, etc.). We have to check and/or fix-up a couple of
16308 - Make sure the user hasn't attempted to make a Neon instruction
16310 - Alter the value in the condition code field if necessary.
16311 - Make sure that the arch supports Neon instructions.
16313 Which of these operations take place depends on bits from enum
16314 vfp_or_neon_is_neon_bits.
16316 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16317 current instruction's condition is COND_ALWAYS, the condition field is
16318 changed to inst.uncond_value. This is necessary because instructions shared
16319 between VFP and Neon may be conditional for the VFP variants only, and the
16320 unconditional Neon version must have, e.g., 0xF in the condition field. */
16323 vfp_or_neon_is_neon (unsigned check
)
16325 /* Conditions are always legal in Thumb mode (IT blocks). */
16326 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16328 if (inst
.cond
!= COND_ALWAYS
)
16330 first_error (_(BAD_COND
));
16333 if (inst
.uncond_value
!= -1)
16334 inst
.instruction
|= inst
.uncond_value
<< 28;
16338 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16339 || ((check
& NEON_CHECK_ARCH8
)
16340 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16342 first_error (_(BAD_FPU
));
16350 check_simd_pred_availability (int fp
, unsigned check
)
16352 if (inst
.cond
> COND_ALWAYS
)
16354 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16356 inst
.error
= BAD_FPU
;
16359 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16361 else if (inst
.cond
< COND_ALWAYS
)
16363 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16364 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16365 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16370 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16371 && vfp_or_neon_is_neon (check
) == FAIL
)
16374 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16375 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16380 /* Neon instruction encoders, in approximate order of appearance. */
16383 do_neon_dyadic_i_su (void)
16385 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16388 enum neon_shape rs
;
16389 struct neon_type_el et
;
16390 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16391 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16393 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16395 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16399 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16401 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16405 do_neon_dyadic_i64_su (void)
16407 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16409 enum neon_shape rs
;
16410 struct neon_type_el et
;
16411 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16413 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16414 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16418 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16419 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16422 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16424 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16428 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16431 unsigned size
= et
.size
>> 3;
16432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16436 inst
.instruction
|= (isquad
!= 0) << 6;
16437 inst
.instruction
|= immbits
<< 16;
16438 inst
.instruction
|= (size
>> 3) << 7;
16439 inst
.instruction
|= (size
& 0x7) << 19;
16441 inst
.instruction
|= (uval
!= 0) << 24;
16443 neon_dp_fixup (&inst
);
16449 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16452 if (!inst
.operands
[2].isreg
)
16454 enum neon_shape rs
;
16455 struct neon_type_el et
;
16456 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16458 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16459 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16463 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16464 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16466 int imm
= inst
.operands
[2].imm
;
16468 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16469 _("immediate out of range for shift"));
16470 NEON_ENCODE (IMMED
, inst
);
16471 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16475 enum neon_shape rs
;
16476 struct neon_type_el et
;
16477 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16479 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16480 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16484 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16485 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16491 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16492 _("invalid instruction shape"));
16493 if (inst
.operands
[2].reg
== REG_SP
)
16494 as_tsktsk (MVE_BAD_SP
);
16495 else if (inst
.operands
[2].reg
== REG_PC
)
16496 as_tsktsk (MVE_BAD_PC
);
16498 inst
.instruction
= 0xee311e60;
16499 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16500 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16501 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16502 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16503 inst
.instruction
|= inst
.operands
[2].reg
;
16510 /* VSHL/VQSHL 3-register variants have syntax such as:
16512 whereas other 3-register operations encoded by neon_three_same have
16515 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16516 operands[2].reg here. */
16517 tmp
= inst
.operands
[2].reg
;
16518 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16519 inst
.operands
[1].reg
= tmp
;
16520 NEON_ENCODE (INTEGER
, inst
);
16521 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16527 do_neon_qshl (void)
16529 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16532 if (!inst
.operands
[2].isreg
)
16534 enum neon_shape rs
;
16535 struct neon_type_el et
;
16536 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16538 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16539 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16543 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16544 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16546 int imm
= inst
.operands
[2].imm
;
16548 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16549 _("immediate out of range for shift"));
16550 NEON_ENCODE (IMMED
, inst
);
16551 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16555 enum neon_shape rs
;
16556 struct neon_type_el et
;
16558 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16560 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16561 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16565 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16566 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16571 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16572 _("invalid instruction shape"));
16573 if (inst
.operands
[2].reg
== REG_SP
)
16574 as_tsktsk (MVE_BAD_SP
);
16575 else if (inst
.operands
[2].reg
== REG_PC
)
16576 as_tsktsk (MVE_BAD_PC
);
16578 inst
.instruction
= 0xee311ee0;
16579 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16580 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16581 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16583 inst
.instruction
|= inst
.operands
[2].reg
;
16590 /* See note in do_neon_shl. */
16591 tmp
= inst
.operands
[2].reg
;
16592 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16593 inst
.operands
[1].reg
= tmp
;
16594 NEON_ENCODE (INTEGER
, inst
);
16595 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16601 do_neon_rshl (void)
16603 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16606 enum neon_shape rs
;
16607 struct neon_type_el et
;
16608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16610 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16611 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16615 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16616 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16623 if (inst
.operands
[2].reg
== REG_PC
)
16624 as_tsktsk (MVE_BAD_PC
);
16625 else if (inst
.operands
[2].reg
== REG_SP
)
16626 as_tsktsk (MVE_BAD_SP
);
16628 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16629 _("invalid instruction shape"));
16631 if (inst
.instruction
== 0x0000510)
16632 /* We are dealing with vqrshl. */
16633 inst
.instruction
= 0xee331ee0;
16635 /* We are dealing with vrshl. */
16636 inst
.instruction
= 0xee331e60;
16638 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16639 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16640 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16641 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16642 inst
.instruction
|= inst
.operands
[2].reg
;
16647 tmp
= inst
.operands
[2].reg
;
16648 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16649 inst
.operands
[1].reg
= tmp
;
16650 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16655 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16657 /* Handle .I8 pseudo-instructions. */
16660 /* Unfortunately, this will make everything apart from zero out-of-range.
16661 FIXME is this the intended semantics? There doesn't seem much point in
16662 accepting .I8 if so. */
16663 immediate
|= immediate
<< 8;
16669 if (immediate
== (immediate
& 0x000000ff))
16671 *immbits
= immediate
;
16674 else if (immediate
== (immediate
& 0x0000ff00))
16676 *immbits
= immediate
>> 8;
16679 else if (immediate
== (immediate
& 0x00ff0000))
16681 *immbits
= immediate
>> 16;
16684 else if (immediate
== (immediate
& 0xff000000))
16686 *immbits
= immediate
>> 24;
16689 if ((immediate
& 0xffff) != (immediate
>> 16))
16690 goto bad_immediate
;
16691 immediate
&= 0xffff;
16694 if (immediate
== (immediate
& 0x000000ff))
16696 *immbits
= immediate
;
16699 else if (immediate
== (immediate
& 0x0000ff00))
16701 *immbits
= immediate
>> 8;
16706 first_error (_("immediate value out of range"));
16711 do_neon_logic (void)
16713 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16715 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16717 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16720 else if (rs
!= NS_QQQ
16721 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16722 first_error (BAD_FPU
);
16724 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16725 /* U bit and size field were set as part of the bitmask. */
16726 NEON_ENCODE (INTEGER
, inst
);
16727 neon_three_same (neon_quad (rs
), 0, -1);
16731 const int three_ops_form
= (inst
.operands
[2].present
16732 && !inst
.operands
[2].isreg
);
16733 const int immoperand
= (three_ops_form
? 2 : 1);
16734 enum neon_shape rs
= (three_ops_form
16735 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16736 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16737 /* Because neon_select_shape makes the second operand a copy of the first
16738 if the second operand is not present. */
16740 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16743 else if (rs
!= NS_QQI
16744 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16745 first_error (BAD_FPU
);
16747 struct neon_type_el et
;
16748 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16749 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16751 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16754 if (et
.type
== NT_invtype
)
16756 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16761 if (three_ops_form
)
16762 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16763 _("first and second operands shall be the same register"));
16765 NEON_ENCODE (IMMED
, inst
);
16767 immbits
= inst
.operands
[immoperand
].imm
;
16770 /* .i64 is a pseudo-op, so the immediate must be a repeating
16772 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16773 inst
.operands
[immoperand
].reg
: 0))
16775 /* Set immbits to an invalid constant. */
16776 immbits
= 0xdeadbeef;
16783 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16787 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16791 /* Pseudo-instruction for VBIC. */
16792 neon_invert_size (&immbits
, 0, et
.size
);
16793 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16797 /* Pseudo-instruction for VORR. */
16798 neon_invert_size (&immbits
, 0, et
.size
);
16799 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16809 inst
.instruction
|= neon_quad (rs
) << 6;
16810 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16812 inst
.instruction
|= cmode
<< 8;
16813 neon_write_immbits (immbits
);
16815 neon_dp_fixup (&inst
);
16820 do_neon_bitfield (void)
16822 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16823 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16824 neon_three_same (neon_quad (rs
), 0, -1);
16828 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16831 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16832 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16834 if (et
.type
== NT_float
)
16836 NEON_ENCODE (FLOAT
, inst
);
16838 mve_encode_qqr (et
.size
, 0, 1);
16840 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16844 NEON_ENCODE (INTEGER
, inst
);
16846 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16848 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16854 do_neon_dyadic_if_su_d (void)
16856 /* This version only allow D registers, but that constraint is enforced during
16857 operand parsing so we don't need to do anything extra here. */
16858 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16862 do_neon_dyadic_if_i_d (void)
16864 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16865 affected if we specify unsigned args. */
16866 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16870 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16872 constraint (size
< 32, BAD_ADDR_MODE
);
16873 constraint (size
!= elsize
, BAD_EL_TYPE
);
16874 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16875 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16876 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16877 _("destination register and offset register may not be the"
16880 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16887 constraint ((imm
% (size
/ 8) != 0)
16888 || imm
> (0x7f << neon_logbits (size
)),
16889 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16890 " range of +/-[0,508]")
16891 : _("immediate must be a multiple of 8 in the"
16892 " range of +/-[0,1016]"));
16893 inst
.instruction
|= 0x11 << 24;
16894 inst
.instruction
|= add
<< 23;
16895 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16896 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16897 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16898 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16899 inst
.instruction
|= 1 << 12;
16900 inst
.instruction
|= (size
== 64) << 8;
16901 inst
.instruction
&= 0xffffff00;
16902 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16903 inst
.instruction
|= imm
>> neon_logbits (size
);
16907 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16909 unsigned os
= inst
.operands
[1].imm
>> 5;
16910 constraint (os
!= 0 && size
== 8,
16911 _("can not shift offsets when accessing less than half-word"));
16912 constraint (os
&& os
!= neon_logbits (size
),
16913 _("shift immediate must be 1, 2 or 3 for half-word, word"
16914 " or double-word accesses respectively"));
16915 if (inst
.operands
[1].reg
== REG_PC
)
16916 as_tsktsk (MVE_BAD_PC
);
16921 constraint (elsize
>= 64, BAD_EL_TYPE
);
16924 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16928 constraint (elsize
!= size
, BAD_EL_TYPE
);
16933 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16937 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16938 _("destination register and offset register may not be"
16940 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16942 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16943 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16944 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16948 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16951 inst
.instruction
|= 1 << 23;
16952 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16954 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16955 inst
.instruction
|= neon_logbits (elsize
) << 7;
16956 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16957 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16958 inst
.instruction
|= !!os
;
16962 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16964 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16966 constraint (size
>= 64, BAD_ADDR_MODE
);
16970 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16973 constraint (elsize
!= size
, BAD_EL_TYPE
);
16980 constraint (elsize
!= size
&& type
!= NT_unsigned
16981 && type
!= NT_signed
, BAD_EL_TYPE
);
16985 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16988 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16996 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17001 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17004 constraint (1, _("immediate must be a multiple of 2 in the"
17005 " range of +/-[0,254]"));
17008 constraint (1, _("immediate must be a multiple of 4 in the"
17009 " range of +/-[0,508]"));
17014 if (size
!= elsize
)
17016 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17017 constraint (inst
.operands
[0].reg
> 14,
17018 _("MVE vector register in the range [Q0..Q7] expected"));
17019 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17020 inst
.instruction
|= (size
== 16) << 19;
17021 inst
.instruction
|= neon_logbits (elsize
) << 7;
17025 if (inst
.operands
[1].reg
== REG_PC
)
17026 as_tsktsk (MVE_BAD_PC
);
17027 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17028 as_tsktsk (MVE_BAD_SP
);
17029 inst
.instruction
|= 1 << 12;
17030 inst
.instruction
|= neon_logbits (size
) << 7;
17032 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17033 inst
.instruction
|= add
<< 23;
17034 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17035 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17038 inst
.instruction
&= 0xffffff80;
17039 inst
.instruction
|= imm
>> neon_logbits (size
);
17044 do_mve_vstr_vldr (void)
17049 if (inst
.cond
> COND_ALWAYS
)
17050 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17052 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17054 switch (inst
.instruction
)
17061 /* fall through. */
17067 /* fall through. */
17073 /* fall through. */
17079 /* fall through. */
17084 unsigned elsize
= inst
.vectype
.el
[0].size
;
17086 if (inst
.operands
[1].isquad
)
17088 /* We are dealing with [Q, imm]{!} cases. */
17089 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17093 if (inst
.operands
[1].immisreg
== 2)
17095 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17096 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17098 else if (!inst
.operands
[1].immisreg
)
17100 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17101 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17104 constraint (1, BAD_ADDR_MODE
);
17111 do_mve_vst_vld (void)
17113 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17116 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17117 || inst
.relocs
[0].exp
.X_add_number
!= 0
17118 || inst
.operands
[1].immisreg
!= 0,
17120 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17121 if (inst
.operands
[1].reg
== REG_PC
)
17122 as_tsktsk (MVE_BAD_PC
);
17123 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17124 as_tsktsk (MVE_BAD_SP
);
17127 /* These instructions are one of the "exceptions" mentioned in
17128 handle_pred_state. They are MVE instructions that are not VPT compatible
17129 and do not accept a VPT code, thus appending such a code is a syntax
17131 if (inst
.cond
> COND_ALWAYS
)
17132 first_error (BAD_SYNTAX
);
17133 /* If we append a scalar condition code we can set this to
17134 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17135 else if (inst
.cond
< COND_ALWAYS
)
17136 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17138 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17140 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17141 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17142 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17144 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17149 do_mve_vaddlv (void)
17151 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17152 struct neon_type_el et
17153 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17155 if (et
.type
== NT_invtype
)
17156 first_error (BAD_EL_TYPE
);
17158 if (inst
.cond
> COND_ALWAYS
)
17159 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17161 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17163 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17165 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17166 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17168 inst
.instruction
|= inst
.operands
[2].reg
;
17173 do_neon_dyadic_if_su (void)
17175 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17176 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17179 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17180 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17181 && et
.type
== NT_float
17182 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17184 if (check_simd_pred_availability (et
.type
== NT_float
,
17185 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17188 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17192 do_neon_addsub_if_i (void)
17194 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17195 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17198 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17199 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17200 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17202 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17203 /* If we are parsing Q registers and the element types match MVE, which NEON
17204 also supports, then we must check whether this is an instruction that can
17205 be used by both MVE/NEON. This distinction can be made based on whether
17206 they are predicated or not. */
17207 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17209 if (check_simd_pred_availability (et
.type
== NT_float
,
17210 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17215 /* If they are either in a D register or are using an unsupported. */
17217 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17221 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17222 affected if we specify unsigned args. */
17223 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17226 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17228 V<op> A,B (A is operand 0, B is operand 2)
17233 so handle that case specially. */
17236 neon_exchange_operands (void)
17238 if (inst
.operands
[1].present
)
17240 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17242 /* Swap operands[1] and operands[2]. */
17243 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17244 inst
.operands
[1] = inst
.operands
[2];
17245 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17250 inst
.operands
[1] = inst
.operands
[2];
17251 inst
.operands
[2] = inst
.operands
[0];
17256 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17258 if (inst
.operands
[2].isreg
)
17261 neon_exchange_operands ();
17262 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17266 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17267 struct neon_type_el et
= neon_check_type (2, rs
,
17268 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17270 NEON_ENCODE (IMMED
, inst
);
17271 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17274 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17275 inst
.instruction
|= neon_quad (rs
) << 6;
17276 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17277 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17279 neon_dp_fixup (&inst
);
17286 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17290 do_neon_cmp_inv (void)
17292 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17298 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17301 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17302 scalars, which are encoded in 5 bits, M : Rm.
17303 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17304 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17307 Dot Product instructions are similar to multiply instructions except elsize
17308 should always be 32.
17310 This function translates SCALAR, which is GAS's internal encoding of indexed
17311 scalar register, to raw encoding. There is also register and index range
17312 check based on ELSIZE. */
17315 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17317 unsigned regno
= NEON_SCALAR_REG (scalar
);
17318 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17323 if (regno
> 7 || elno
> 3)
17325 return regno
| (elno
<< 3);
17328 if (regno
> 15 || elno
> 1)
17330 return regno
| (elno
<< 4);
17334 first_error (_("scalar out of range for multiply instruction"));
17340 /* Encode multiply / multiply-accumulate scalar instructions. */
17343 neon_mul_mac (struct neon_type_el et
, int ubit
)
17347 /* Give a more helpful error message if we have an invalid type. */
17348 if (et
.type
== NT_invtype
)
17351 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17352 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17354 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17355 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17356 inst
.instruction
|= LOW4 (scalar
);
17357 inst
.instruction
|= HI1 (scalar
) << 5;
17358 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17359 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17360 inst
.instruction
|= (ubit
!= 0) << 24;
17362 neon_dp_fixup (&inst
);
17366 do_neon_mac_maybe_scalar (void)
17368 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17371 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17374 if (inst
.operands
[2].isscalar
)
17376 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17377 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17378 struct neon_type_el et
= neon_check_type (3, rs
,
17379 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17380 NEON_ENCODE (SCALAR
, inst
);
17381 neon_mul_mac (et
, neon_quad (rs
));
17383 else if (!inst
.operands
[2].isvec
)
17385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17387 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17388 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17390 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17394 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17395 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17396 affected if we specify unsigned args. */
17397 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17402 do_neon_fmac (void)
17404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17405 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17408 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17411 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17413 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17414 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17419 if (inst
.operands
[2].reg
== REG_SP
)
17420 as_tsktsk (MVE_BAD_SP
);
17421 else if (inst
.operands
[2].reg
== REG_PC
)
17422 as_tsktsk (MVE_BAD_PC
);
17424 inst
.instruction
= 0xee310e40;
17425 inst
.instruction
|= (et
.size
== 16) << 28;
17426 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17427 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17428 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17429 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17430 inst
.instruction
|= inst
.operands
[2].reg
;
17437 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17440 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17446 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17447 struct neon_type_el et
= neon_check_type (3, rs
,
17448 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17449 neon_three_same (neon_quad (rs
), 0, et
.size
);
17452 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17453 same types as the MAC equivalents. The polynomial type for this instruction
17454 is encoded the same as the integer type. */
17459 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17462 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17465 if (inst
.operands
[2].isscalar
)
17467 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17468 do_neon_mac_maybe_scalar ();
17472 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17474 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17475 struct neon_type_el et
17476 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17477 if (et
.type
== NT_float
)
17478 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17481 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17485 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17486 neon_dyadic_misc (NT_poly
,
17487 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17493 do_neon_qdmulh (void)
17495 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17498 if (inst
.operands
[2].isscalar
)
17500 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17501 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17502 struct neon_type_el et
= neon_check_type (3, rs
,
17503 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17504 NEON_ENCODE (SCALAR
, inst
);
17505 neon_mul_mac (et
, neon_quad (rs
));
17509 enum neon_shape rs
;
17510 struct neon_type_el et
;
17511 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17513 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17514 et
= neon_check_type (3, rs
,
17515 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17519 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17520 et
= neon_check_type (3, rs
,
17521 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17524 NEON_ENCODE (INTEGER
, inst
);
17526 mve_encode_qqr (et
.size
, 0, 0);
17528 /* The U bit (rounding) comes from bit mask. */
17529 neon_three_same (neon_quad (rs
), 0, et
.size
);
17534 do_mve_vaddv (void)
17536 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17537 struct neon_type_el et
17538 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17540 if (et
.type
== NT_invtype
)
17541 first_error (BAD_EL_TYPE
);
17543 if (inst
.cond
> COND_ALWAYS
)
17544 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17546 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17548 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17550 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17554 do_mve_vhcadd (void)
17556 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17557 struct neon_type_el et
17558 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17560 if (inst
.cond
> COND_ALWAYS
)
17561 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17563 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17565 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17566 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17568 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17569 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17570 "operand makes instruction UNPREDICTABLE"));
17572 mve_encode_qqq (0, et
.size
);
17573 inst
.instruction
|= (rot
== 270) << 12;
17578 do_mve_vqdmull (void)
17580 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17581 struct neon_type_el et
17582 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17585 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17586 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17587 as_tsktsk (BAD_MVE_SRCDEST
);
17589 if (inst
.cond
> COND_ALWAYS
)
17590 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17592 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17596 mve_encode_qqq (et
.size
== 32, 64);
17597 inst
.instruction
|= 1;
17601 mve_encode_qqr (64, et
.size
== 32, 0);
17602 inst
.instruction
|= 0x3 << 5;
17609 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17610 struct neon_type_el et
17611 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17613 if (et
.type
== NT_invtype
)
17614 first_error (BAD_EL_TYPE
);
17616 if (inst
.cond
> COND_ALWAYS
)
17617 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17619 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17621 mve_encode_qqq (0, 64);
17625 do_mve_vbrsr (void)
17627 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17628 struct neon_type_el et
17629 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17631 if (inst
.cond
> COND_ALWAYS
)
17632 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17634 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17636 mve_encode_qqr (et
.size
, 0, 0);
17642 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17644 if (inst
.cond
> COND_ALWAYS
)
17645 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17647 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17649 mve_encode_qqq (1, 64);
17653 do_mve_vmulh (void)
17655 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17656 struct neon_type_el et
17657 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17659 if (inst
.cond
> COND_ALWAYS
)
17660 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17662 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17664 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17668 do_mve_vqdmlah (void)
17670 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17671 struct neon_type_el et
17672 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17674 if (inst
.cond
> COND_ALWAYS
)
17675 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17677 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17679 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17683 do_mve_vqdmladh (void)
17685 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17686 struct neon_type_el et
17687 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17689 if (inst
.cond
> COND_ALWAYS
)
17690 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17692 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17695 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17696 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17697 as_tsktsk (BAD_MVE_SRCDEST
);
17699 mve_encode_qqq (0, et
.size
);
17704 do_mve_vmull (void)
17707 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17708 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17709 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17710 && inst
.cond
== COND_ALWAYS
17711 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17716 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17717 N_SUF_32
| N_F64
| N_P8
17718 | N_P16
| N_I_MVE
| N_KEY
);
17719 if (((et
.type
== NT_poly
) && et
.size
== 8
17720 && ARM_CPU_IS_ANY (cpu_variant
))
17721 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17728 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17729 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17730 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17732 /* We are dealing with MVE's vmullt. */
17734 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17735 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17736 as_tsktsk (BAD_MVE_SRCDEST
);
17738 if (inst
.cond
> COND_ALWAYS
)
17739 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17741 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17743 if (et
.type
== NT_poly
)
17744 mve_encode_qqq (neon_logbits (et
.size
), 64);
17746 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17751 inst
.instruction
= N_MNEM_vmul
;
17754 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17759 do_mve_vabav (void)
17761 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17766 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17769 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17770 | N_S16
| N_S32
| N_U8
| N_U16
17773 if (inst
.cond
> COND_ALWAYS
)
17774 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17776 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17778 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17782 do_mve_vmladav (void)
17784 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17785 struct neon_type_el et
= neon_check_type (3, rs
,
17786 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17788 if (et
.type
== NT_unsigned
17789 && (inst
.instruction
== M_MNEM_vmladavx
17790 || inst
.instruction
== M_MNEM_vmladavax
17791 || inst
.instruction
== M_MNEM_vmlsdav
17792 || inst
.instruction
== M_MNEM_vmlsdava
17793 || inst
.instruction
== M_MNEM_vmlsdavx
17794 || inst
.instruction
== M_MNEM_vmlsdavax
))
17795 first_error (BAD_SIMD_TYPE
);
17797 constraint (inst
.operands
[2].reg
> 14,
17798 _("MVE vector register in the range [Q0..Q7] expected"));
17800 if (inst
.cond
> COND_ALWAYS
)
17801 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17803 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17805 if (inst
.instruction
== M_MNEM_vmlsdav
17806 || inst
.instruction
== M_MNEM_vmlsdava
17807 || inst
.instruction
== M_MNEM_vmlsdavx
17808 || inst
.instruction
== M_MNEM_vmlsdavax
)
17809 inst
.instruction
|= (et
.size
== 8) << 28;
17811 inst
.instruction
|= (et
.size
== 8) << 8;
17813 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17814 inst
.instruction
|= (et
.size
== 32) << 16;
17818 do_mve_vmlaldav (void)
17820 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17821 struct neon_type_el et
17822 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17823 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17825 if (et
.type
== NT_unsigned
17826 && (inst
.instruction
== M_MNEM_vmlsldav
17827 || inst
.instruction
== M_MNEM_vmlsldava
17828 || inst
.instruction
== M_MNEM_vmlsldavx
17829 || inst
.instruction
== M_MNEM_vmlsldavax
))
17830 first_error (BAD_SIMD_TYPE
);
17832 if (inst
.cond
> COND_ALWAYS
)
17833 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17835 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17837 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17841 do_mve_vrmlaldavh (void)
17843 struct neon_type_el et
;
17844 if (inst
.instruction
== M_MNEM_vrmlsldavh
17845 || inst
.instruction
== M_MNEM_vrmlsldavha
17846 || inst
.instruction
== M_MNEM_vrmlsldavhx
17847 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17849 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17850 if (inst
.operands
[1].reg
== REG_SP
)
17851 as_tsktsk (MVE_BAD_SP
);
17855 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17856 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17857 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17859 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17860 N_U32
| N_S32
| N_KEY
);
17861 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17862 with vmax/min instructions, making the use of SP in assembly really
17863 nonsensical, so instead of issuing a warning like we do for other uses
17864 of SP for the odd register operand we error out. */
17865 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17868 /* Make sure we still check the second operand is an odd one and that PC is
17869 disallowed. This because we are parsing for any GPR operand, to be able
17870 to distinguish between giving a warning or an error for SP as described
17872 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17873 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17875 if (inst
.cond
> COND_ALWAYS
)
17876 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17878 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17880 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17885 do_mve_vmaxnmv (void)
17887 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17888 struct neon_type_el et
17889 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17891 if (inst
.cond
> COND_ALWAYS
)
17892 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17894 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17896 if (inst
.operands
[0].reg
== REG_SP
)
17897 as_tsktsk (MVE_BAD_SP
);
17898 else if (inst
.operands
[0].reg
== REG_PC
)
17899 as_tsktsk (MVE_BAD_PC
);
17901 mve_encode_rq (et
.size
== 16, 64);
17905 do_mve_vmaxv (void)
17907 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17908 struct neon_type_el et
;
17910 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17911 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17913 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17915 if (inst
.cond
> COND_ALWAYS
)
17916 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17918 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17920 if (inst
.operands
[0].reg
== REG_SP
)
17921 as_tsktsk (MVE_BAD_SP
);
17922 else if (inst
.operands
[0].reg
== REG_PC
)
17923 as_tsktsk (MVE_BAD_PC
);
17925 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17930 do_neon_qrdmlah (void)
17932 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17934 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17936 /* Check we're on the correct architecture. */
17937 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17939 = _("instruction form not available on this architecture.");
17940 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17942 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17943 record_feature_use (&fpu_neon_ext_v8_1
);
17945 if (inst
.operands
[2].isscalar
)
17947 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17948 struct neon_type_el et
= neon_check_type (3, rs
,
17949 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17950 NEON_ENCODE (SCALAR
, inst
);
17951 neon_mul_mac (et
, neon_quad (rs
));
17955 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17956 struct neon_type_el et
= neon_check_type (3, rs
,
17957 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17958 NEON_ENCODE (INTEGER
, inst
);
17959 /* The U bit (rounding) comes from bit mask. */
17960 neon_three_same (neon_quad (rs
), 0, et
.size
);
17965 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17966 struct neon_type_el et
17967 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17969 NEON_ENCODE (INTEGER
, inst
);
17970 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17975 do_neon_fcmp_absolute (void)
17977 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17978 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17979 N_F_16_32
| N_KEY
);
17980 /* Size field comes from bit mask. */
17981 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17985 do_neon_fcmp_absolute_inv (void)
17987 neon_exchange_operands ();
17988 do_neon_fcmp_absolute ();
17992 do_neon_step (void)
17994 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17995 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17996 N_F_16_32
| N_KEY
);
17997 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18001 do_neon_abs_neg (void)
18003 enum neon_shape rs
;
18004 struct neon_type_el et
;
18006 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18009 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18010 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18012 if (check_simd_pred_availability (et
.type
== NT_float
,
18013 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18018 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18019 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18020 inst
.instruction
|= neon_quad (rs
) << 6;
18021 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18022 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18024 neon_dp_fixup (&inst
);
18030 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18033 enum neon_shape rs
;
18034 struct neon_type_el et
;
18035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18037 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18038 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18042 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18043 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18047 int imm
= inst
.operands
[2].imm
;
18048 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18049 _("immediate out of range for insert"));
18050 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18056 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18059 enum neon_shape rs
;
18060 struct neon_type_el et
;
18061 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18063 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18064 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18068 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18069 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18072 int imm
= inst
.operands
[2].imm
;
18073 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18074 _("immediate out of range for insert"));
18075 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18079 do_neon_qshlu_imm (void)
18081 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18084 enum neon_shape rs
;
18085 struct neon_type_el et
;
18086 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18088 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18089 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18093 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18094 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18095 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18098 int imm
= inst
.operands
[2].imm
;
18099 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18100 _("immediate out of range for shift"));
18101 /* Only encodes the 'U present' variant of the instruction.
18102 In this case, signed types have OP (bit 8) set to 0.
18103 Unsigned types have OP set to 1. */
18104 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18105 /* The rest of the bits are the same as other immediate shifts. */
18106 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18110 do_neon_qmovn (void)
18112 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18113 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18114 /* Saturating move where operands can be signed or unsigned, and the
18115 destination has the same signedness. */
18116 NEON_ENCODE (INTEGER
, inst
);
18117 if (et
.type
== NT_unsigned
)
18118 inst
.instruction
|= 0xc0;
18120 inst
.instruction
|= 0x80;
18121 neon_two_same (0, 1, et
.size
/ 2);
18125 do_neon_qmovun (void)
18127 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18128 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18129 /* Saturating move with unsigned results. Operands must be signed. */
18130 NEON_ENCODE (INTEGER
, inst
);
18131 neon_two_same (0, 1, et
.size
/ 2);
18135 do_neon_rshift_sat_narrow (void)
18137 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18138 or unsigned. If operands are unsigned, results must also be unsigned. */
18139 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18140 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18141 int imm
= inst
.operands
[2].imm
;
18142 /* This gets the bounds check, size encoding and immediate bits calculation
18146 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18147 VQMOVN.I<size> <Dd>, <Qm>. */
18150 inst
.operands
[2].present
= 0;
18151 inst
.instruction
= N_MNEM_vqmovn
;
18156 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18157 _("immediate out of range"));
18158 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18162 do_neon_rshift_sat_narrow_u (void)
18164 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18165 or unsigned. If operands are unsigned, results must also be unsigned. */
18166 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18167 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18168 int imm
= inst
.operands
[2].imm
;
18169 /* This gets the bounds check, size encoding and immediate bits calculation
18173 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18174 VQMOVUN.I<size> <Dd>, <Qm>. */
18177 inst
.operands
[2].present
= 0;
18178 inst
.instruction
= N_MNEM_vqmovun
;
18183 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18184 _("immediate out of range"));
18185 /* FIXME: The manual is kind of unclear about what value U should have in
18186 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18188 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18192 do_neon_movn (void)
18194 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18195 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18196 NEON_ENCODE (INTEGER
, inst
);
18197 neon_two_same (0, 1, et
.size
/ 2);
18201 do_neon_rshift_narrow (void)
18203 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18204 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18205 int imm
= inst
.operands
[2].imm
;
18206 /* This gets the bounds check, size encoding and immediate bits calculation
18210 /* If immediate is zero then we are a pseudo-instruction for
18211 VMOVN.I<size> <Dd>, <Qm> */
18214 inst
.operands
[2].present
= 0;
18215 inst
.instruction
= N_MNEM_vmovn
;
18220 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18221 _("immediate out of range for narrowing operation"));
18222 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18226 do_neon_shll (void)
18228 /* FIXME: Type checking when lengthening. */
18229 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18230 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18231 unsigned imm
= inst
.operands
[2].imm
;
18233 if (imm
== et
.size
)
18235 /* Maximum shift variant. */
18236 NEON_ENCODE (INTEGER
, inst
);
18237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18238 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18241 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18243 neon_dp_fixup (&inst
);
18247 /* A more-specific type check for non-max versions. */
18248 et
= neon_check_type (2, NS_QDI
,
18249 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18250 NEON_ENCODE (IMMED
, inst
);
18251 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18255 /* Check the various types for the VCVT instruction, and return which version
18256 the current instruction is. */
18258 #define CVT_FLAVOUR_VAR \
18259 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18260 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18261 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18262 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18263 /* Half-precision conversions. */ \
18264 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18265 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18266 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18267 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18268 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18269 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18270 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18271 Compared with single/double precision variants, only the co-processor \
18272 field is different, so the encoding flow is reused here. */ \
18273 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18274 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18275 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18276 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18277 /* VFP instructions. */ \
18278 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18279 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18280 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18281 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18282 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18283 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18284 /* VFP instructions with bitshift. */ \
18285 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18286 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18287 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18288 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18289 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18290 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18291 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18292 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18294 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18295 neon_cvt_flavour_##C,
18297 /* The different types of conversions we can do. */
18298 enum neon_cvt_flavour
18301 neon_cvt_flavour_invalid
,
18302 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18307 static enum neon_cvt_flavour
18308 get_neon_cvt_flavour (enum neon_shape rs
)
18310 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18311 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18312 if (et.type != NT_invtype) \
18314 inst.error = NULL; \
18315 return (neon_cvt_flavour_##C); \
18318 struct neon_type_el et
;
18319 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18320 || rs
== NS_FF
) ? N_VFP
: 0;
18321 /* The instruction versions which take an immediate take one register
18322 argument, which is extended to the width of the full register. Thus the
18323 "source" and "destination" registers must have the same width. Hack that
18324 here by making the size equal to the key (wider, in this case) operand. */
18325 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18329 return neon_cvt_flavour_invalid
;
18344 /* Neon-syntax VFP conversions. */
18347 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18349 const char *opname
= 0;
18351 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18352 || rs
== NS_FHI
|| rs
== NS_HFI
)
18354 /* Conversions with immediate bitshift. */
18355 const char *enc
[] =
18357 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18363 if (flavour
< (int) ARRAY_SIZE (enc
))
18365 opname
= enc
[flavour
];
18366 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18367 _("operands 0 and 1 must be the same register"));
18368 inst
.operands
[1] = inst
.operands
[2];
18369 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18374 /* Conversions without bitshift. */
18375 const char *enc
[] =
18377 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18383 if (flavour
< (int) ARRAY_SIZE (enc
))
18384 opname
= enc
[flavour
];
18388 do_vfp_nsyn_opcode (opname
);
18390 /* ARMv8.2 fp16 VCVT instruction. */
18391 if (flavour
== neon_cvt_flavour_s32_f16
18392 || flavour
== neon_cvt_flavour_u32_f16
18393 || flavour
== neon_cvt_flavour_f16_u32
18394 || flavour
== neon_cvt_flavour_f16_s32
)
18395 do_scalar_fp16_v82_encode ();
18399 do_vfp_nsyn_cvtz (void)
18401 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18402 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18403 const char *enc
[] =
18405 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18411 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18412 do_vfp_nsyn_opcode (enc
[flavour
]);
18416 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18417 enum neon_cvt_mode mode
)
18422 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18423 D register operands. */
18424 if (flavour
== neon_cvt_flavour_s32_f64
18425 || flavour
== neon_cvt_flavour_u32_f64
)
18426 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18429 if (flavour
== neon_cvt_flavour_s32_f16
18430 || flavour
== neon_cvt_flavour_u32_f16
)
18431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18434 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18438 case neon_cvt_flavour_s32_f64
:
18442 case neon_cvt_flavour_s32_f32
:
18446 case neon_cvt_flavour_s32_f16
:
18450 case neon_cvt_flavour_u32_f64
:
18454 case neon_cvt_flavour_u32_f32
:
18458 case neon_cvt_flavour_u32_f16
:
18463 first_error (_("invalid instruction shape"));
18469 case neon_cvt_mode_a
: rm
= 0; break;
18470 case neon_cvt_mode_n
: rm
= 1; break;
18471 case neon_cvt_mode_p
: rm
= 2; break;
18472 case neon_cvt_mode_m
: rm
= 3; break;
18473 default: first_error (_("invalid rounding mode")); return;
18476 NEON_ENCODE (FPV8
, inst
);
18477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18478 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18479 inst
.instruction
|= sz
<< 8;
18481 /* ARMv8.2 fp16 VCVT instruction. */
18482 if (flavour
== neon_cvt_flavour_s32_f16
18483 ||flavour
== neon_cvt_flavour_u32_f16
)
18484 do_scalar_fp16_v82_encode ();
18485 inst
.instruction
|= op
<< 7;
18486 inst
.instruction
|= rm
<< 16;
18487 inst
.instruction
|= 0xf0000000;
18488 inst
.is_neon
= TRUE
;
18492 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18494 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18495 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18496 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18498 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18500 if (flavour
== neon_cvt_flavour_invalid
)
18503 /* PR11109: Handle round-to-zero for VCVT conversions. */
18504 if (mode
== neon_cvt_mode_z
18505 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18506 && (flavour
== neon_cvt_flavour_s16_f16
18507 || flavour
== neon_cvt_flavour_u16_f16
18508 || flavour
== neon_cvt_flavour_s32_f32
18509 || flavour
== neon_cvt_flavour_u32_f32
18510 || flavour
== neon_cvt_flavour_s32_f64
18511 || flavour
== neon_cvt_flavour_u32_f64
)
18512 && (rs
== NS_FD
|| rs
== NS_FF
))
18514 do_vfp_nsyn_cvtz ();
18518 /* ARMv8.2 fp16 VCVT conversions. */
18519 if (mode
== neon_cvt_mode_z
18520 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18521 && (flavour
== neon_cvt_flavour_s32_f16
18522 || flavour
== neon_cvt_flavour_u32_f16
)
18525 do_vfp_nsyn_cvtz ();
18526 do_scalar_fp16_v82_encode ();
18530 /* VFP rather than Neon conversions. */
18531 if (flavour
>= neon_cvt_flavour_first_fp
)
18533 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18534 do_vfp_nsyn_cvt (rs
, flavour
);
18536 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18544 if (mode
== neon_cvt_mode_z
18545 && (flavour
== neon_cvt_flavour_f16_s16
18546 || flavour
== neon_cvt_flavour_f16_u16
18547 || flavour
== neon_cvt_flavour_s16_f16
18548 || flavour
== neon_cvt_flavour_u16_f16
18549 || flavour
== neon_cvt_flavour_f32_u32
18550 || flavour
== neon_cvt_flavour_f32_s32
18551 || flavour
== neon_cvt_flavour_s32_f32
18552 || flavour
== neon_cvt_flavour_u32_f32
))
18554 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18557 else if (mode
== neon_cvt_mode_n
)
18559 /* We are dealing with vcvt with the 'ne' condition. */
18561 inst
.instruction
= N_MNEM_vcvt
;
18562 do_neon_cvt_1 (neon_cvt_mode_z
);
18565 /* fall through. */
18569 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18570 0x0000100, 0x1000100, 0x0, 0x1000000};
18572 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18573 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18578 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18579 _("immediate value out of range"));
18582 case neon_cvt_flavour_f16_s16
:
18583 case neon_cvt_flavour_f16_u16
:
18584 case neon_cvt_flavour_s16_f16
:
18585 case neon_cvt_flavour_u16_f16
:
18586 constraint (inst
.operands
[2].imm
> 16,
18587 _("immediate value out of range"));
18589 case neon_cvt_flavour_f32_u32
:
18590 case neon_cvt_flavour_f32_s32
:
18591 case neon_cvt_flavour_s32_f32
:
18592 case neon_cvt_flavour_u32_f32
:
18593 constraint (inst
.operands
[2].imm
> 32,
18594 _("immediate value out of range"));
18597 inst
.error
= BAD_FPU
;
18602 /* Fixed-point conversion with #0 immediate is encoded as an
18603 integer conversion. */
18604 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18606 NEON_ENCODE (IMMED
, inst
);
18607 if (flavour
!= neon_cvt_flavour_invalid
)
18608 inst
.instruction
|= enctab
[flavour
];
18609 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18610 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18611 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18612 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18613 inst
.instruction
|= neon_quad (rs
) << 6;
18614 inst
.instruction
|= 1 << 21;
18615 if (flavour
< neon_cvt_flavour_s16_f16
)
18617 inst
.instruction
|= 1 << 21;
18618 immbits
= 32 - inst
.operands
[2].imm
;
18619 inst
.instruction
|= immbits
<< 16;
18623 inst
.instruction
|= 3 << 20;
18624 immbits
= 16 - inst
.operands
[2].imm
;
18625 inst
.instruction
|= immbits
<< 16;
18626 inst
.instruction
&= ~(1 << 9);
18629 neon_dp_fixup (&inst
);
18634 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18635 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18636 && (flavour
== neon_cvt_flavour_s16_f16
18637 || flavour
== neon_cvt_flavour_u16_f16
18638 || flavour
== neon_cvt_flavour_s32_f32
18639 || flavour
== neon_cvt_flavour_u32_f32
))
18641 if (check_simd_pred_availability (1,
18642 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18645 else if (mode
== neon_cvt_mode_z
18646 && (flavour
== neon_cvt_flavour_f16_s16
18647 || flavour
== neon_cvt_flavour_f16_u16
18648 || flavour
== neon_cvt_flavour_s16_f16
18649 || flavour
== neon_cvt_flavour_u16_f16
18650 || flavour
== neon_cvt_flavour_f32_u32
18651 || flavour
== neon_cvt_flavour_f32_s32
18652 || flavour
== neon_cvt_flavour_s32_f32
18653 || flavour
== neon_cvt_flavour_u32_f32
))
18655 if (check_simd_pred_availability (1,
18656 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18659 /* fall through. */
18661 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18664 NEON_ENCODE (FLOAT
, inst
);
18665 if (check_simd_pred_availability (1,
18666 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18673 inst
.instruction
|= neon_quad (rs
) << 6;
18674 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18675 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18676 inst
.instruction
|= mode
<< 8;
18677 if (flavour
== neon_cvt_flavour_u16_f16
18678 || flavour
== neon_cvt_flavour_s16_f16
)
18679 /* Mask off the original size bits and reencode them. */
18680 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18683 inst
.instruction
|= 0xfc000000;
18685 inst
.instruction
|= 0xf0000000;
18691 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18692 0x100, 0x180, 0x0, 0x080};
18694 NEON_ENCODE (INTEGER
, inst
);
18696 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18698 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18702 if (flavour
!= neon_cvt_flavour_invalid
)
18703 inst
.instruction
|= enctab
[flavour
];
18705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18707 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18708 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18709 inst
.instruction
|= neon_quad (rs
) << 6;
18710 if (flavour
>= neon_cvt_flavour_s16_f16
18711 && flavour
<= neon_cvt_flavour_f16_u16
)
18712 /* Half precision. */
18713 inst
.instruction
|= 1 << 18;
18715 inst
.instruction
|= 2 << 18;
18717 neon_dp_fixup (&inst
);
18722 /* Half-precision conversions for Advanced SIMD -- neon. */
18725 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18729 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18731 as_bad (_("operand size must match register width"));
18736 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18738 as_bad (_("operand size must match register width"));
18743 inst
.instruction
= 0x3b60600;
18745 inst
.instruction
= 0x3b60700;
18747 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18748 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18749 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18750 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18751 neon_dp_fixup (&inst
);
18755 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18756 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18757 do_vfp_nsyn_cvt (rs
, flavour
);
18759 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18764 do_neon_cvtr (void)
18766 do_neon_cvt_1 (neon_cvt_mode_x
);
18772 do_neon_cvt_1 (neon_cvt_mode_z
);
18776 do_neon_cvta (void)
18778 do_neon_cvt_1 (neon_cvt_mode_a
);
18782 do_neon_cvtn (void)
18784 do_neon_cvt_1 (neon_cvt_mode_n
);
18788 do_neon_cvtp (void)
18790 do_neon_cvt_1 (neon_cvt_mode_p
);
18794 do_neon_cvtm (void)
18796 do_neon_cvt_1 (neon_cvt_mode_m
);
18800 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18803 mark_feature_used (&fpu_vfp_ext_armv8
);
18805 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18806 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18807 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18808 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18809 inst
.instruction
|= to
? 0x10000 : 0;
18810 inst
.instruction
|= t
? 0x80 : 0;
18811 inst
.instruction
|= is_double
? 0x100 : 0;
18812 do_vfp_cond_or_thumb ();
18816 do_neon_cvttb_1 (bfd_boolean t
)
18818 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18819 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18823 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18825 int single_to_half
= 0;
18826 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
18829 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18831 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18832 && (flavour
== neon_cvt_flavour_u16_f16
18833 || flavour
== neon_cvt_flavour_s16_f16
18834 || flavour
== neon_cvt_flavour_f16_s16
18835 || flavour
== neon_cvt_flavour_f16_u16
18836 || flavour
== neon_cvt_flavour_u32_f32
18837 || flavour
== neon_cvt_flavour_s32_f32
18838 || flavour
== neon_cvt_flavour_f32_s32
18839 || flavour
== neon_cvt_flavour_f32_u32
))
18842 inst
.instruction
= N_MNEM_vcvt
;
18843 set_pred_insn_type (INSIDE_VPT_INSN
);
18844 do_neon_cvt_1 (neon_cvt_mode_z
);
18847 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18848 single_to_half
= 1;
18849 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18851 first_error (BAD_FPU
);
18855 inst
.instruction
= 0xee3f0e01;
18856 inst
.instruction
|= single_to_half
<< 28;
18857 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18859 inst
.instruction
|= t
<< 12;
18860 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18861 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18864 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18867 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18869 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18872 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18874 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18876 /* The VCVTB and VCVTT instructions with D-register operands
18877 don't work for SP only targets. */
18878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18882 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18884 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18886 /* The VCVTB and VCVTT instructions with D-register operands
18887 don't work for SP only targets. */
18888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18892 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18899 do_neon_cvtb (void)
18901 do_neon_cvttb_1 (FALSE
);
18906 do_neon_cvtt (void)
18908 do_neon_cvttb_1 (TRUE
);
18912 neon_move_immediate (void)
18914 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18915 struct neon_type_el et
= neon_check_type (2, rs
,
18916 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18917 unsigned immlo
, immhi
= 0, immbits
;
18918 int op
, cmode
, float_p
;
18920 constraint (et
.type
== NT_invtype
,
18921 _("operand size must be specified for immediate VMOV"));
18923 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18924 op
= (inst
.instruction
& (1 << 5)) != 0;
18926 immlo
= inst
.operands
[1].imm
;
18927 if (inst
.operands
[1].regisimm
)
18928 immhi
= inst
.operands
[1].reg
;
18930 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18931 _("immediate has bits set outside the operand size"));
18933 float_p
= inst
.operands
[1].immisfloat
;
18935 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18936 et
.size
, et
.type
)) == FAIL
)
18938 /* Invert relevant bits only. */
18939 neon_invert_size (&immlo
, &immhi
, et
.size
);
18940 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18941 with one or the other; those cases are caught by
18942 neon_cmode_for_move_imm. */
18944 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18945 &op
, et
.size
, et
.type
)) == FAIL
)
18947 first_error (_("immediate out of range"));
18952 inst
.instruction
&= ~(1 << 5);
18953 inst
.instruction
|= op
<< 5;
18955 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18956 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18957 inst
.instruction
|= neon_quad (rs
) << 6;
18958 inst
.instruction
|= cmode
<< 8;
18960 neon_write_immbits (immbits
);
18966 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18969 if (inst
.operands
[1].isreg
)
18971 enum neon_shape rs
;
18972 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18973 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
18975 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18977 NEON_ENCODE (INTEGER
, inst
);
18978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18980 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18982 inst
.instruction
|= neon_quad (rs
) << 6;
18986 NEON_ENCODE (IMMED
, inst
);
18987 neon_move_immediate ();
18990 neon_dp_fixup (&inst
);
18992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18994 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
18995 constraint ((inst
.instruction
& 0xd00) == 0xd00,
18996 _("immediate value out of range"));
19000 /* Encode instructions of form:
19002 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19003 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19006 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19008 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19009 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19010 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19011 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19012 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19013 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19014 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19015 inst
.instruction
|= neon_logbits (size
) << 20;
19017 neon_dp_fixup (&inst
);
19021 do_neon_dyadic_long (void)
19023 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19026 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19029 NEON_ENCODE (INTEGER
, inst
);
19030 /* FIXME: Type checking for lengthening op. */
19031 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19032 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19033 neon_mixed_length (et
, et
.size
);
19035 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19036 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19038 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19039 in an IT block with le/lt conditions. */
19041 if (inst
.cond
== 0xf)
19043 else if (inst
.cond
== 0x10)
19046 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19048 if (inst
.instruction
== N_MNEM_vaddl
)
19050 inst
.instruction
= N_MNEM_vadd
;
19051 do_neon_addsub_if_i ();
19053 else if (inst
.instruction
== N_MNEM_vsubl
)
19055 inst
.instruction
= N_MNEM_vsub
;
19056 do_neon_addsub_if_i ();
19058 else if (inst
.instruction
== N_MNEM_vabdl
)
19060 inst
.instruction
= N_MNEM_vabd
;
19061 do_neon_dyadic_if_su ();
19065 first_error (BAD_FPU
);
19069 do_neon_abal (void)
19071 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19072 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19073 neon_mixed_length (et
, et
.size
);
19077 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19079 if (inst
.operands
[2].isscalar
)
19081 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19082 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19083 NEON_ENCODE (SCALAR
, inst
);
19084 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19088 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19089 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19090 NEON_ENCODE (INTEGER
, inst
);
19091 neon_mixed_length (et
, et
.size
);
19096 do_neon_mac_maybe_scalar_long (void)
19098 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19101 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19102 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19105 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19107 unsigned regno
= NEON_SCALAR_REG (scalar
);
19108 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19112 if (regno
> 7 || elno
> 3)
19115 return ((regno
& 0x7)
19116 | ((elno
& 0x1) << 3)
19117 | (((elno
>> 1) & 0x1) << 5));
19121 if (regno
> 15 || elno
> 1)
19124 return (((regno
& 0x1) << 5)
19125 | ((regno
>> 1) & 0x7)
19126 | ((elno
& 0x1) << 3));
19130 first_error (_("scalar out of range for multiply instruction"));
19135 do_neon_fmac_maybe_scalar_long (int subtype
)
19137 enum neon_shape rs
;
19139 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19140 field (bits[21:20]) has different meaning. For scalar index variant, it's
19141 used to differentiate add and subtract, otherwise it's with fixed value
19145 if (inst
.cond
!= COND_ALWAYS
)
19146 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19147 "behaviour is UNPREDICTABLE"));
19149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19152 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19155 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19156 be a scalar index register. */
19157 if (inst
.operands
[2].isscalar
)
19159 high8
= 0xfe000000;
19162 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19166 high8
= 0xfc000000;
19169 inst
.instruction
|= (0x1 << 23);
19170 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19173 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19175 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19176 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19177 so we simply pass -1 as size. */
19178 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19179 neon_three_same (quad_p
, 0, size
);
19181 /* Undo neon_dp_fixup. Redo the high eight bits. */
19182 inst
.instruction
&= 0x00ffffff;
19183 inst
.instruction
|= high8
;
19185 #define LOW1(R) ((R) & 0x1)
19186 #define HI4(R) (((R) >> 1) & 0xf)
19187 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19188 whether the instruction is in Q form and whether Vm is a scalar indexed
19190 if (inst
.operands
[2].isscalar
)
19193 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19194 inst
.instruction
&= 0xffffffd0;
19195 inst
.instruction
|= rm
;
19199 /* Redo Rn as well. */
19200 inst
.instruction
&= 0xfff0ff7f;
19201 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19202 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19207 /* Redo Rn and Rm. */
19208 inst
.instruction
&= 0xfff0ff50;
19209 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19210 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19211 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19212 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19217 do_neon_vfmal (void)
19219 return do_neon_fmac_maybe_scalar_long (0);
19223 do_neon_vfmsl (void)
19225 return do_neon_fmac_maybe_scalar_long (1);
19229 do_neon_dyadic_wide (void)
19231 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19232 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19233 neon_mixed_length (et
, et
.size
);
19237 do_neon_dyadic_narrow (void)
19239 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19240 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19241 /* Operand sign is unimportant, and the U bit is part of the opcode,
19242 so force the operand type to integer. */
19243 et
.type
= NT_integer
;
19244 neon_mixed_length (et
, et
.size
/ 2);
19248 do_neon_mul_sat_scalar_long (void)
19250 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19254 do_neon_vmull (void)
19256 if (inst
.operands
[2].isscalar
)
19257 do_neon_mac_maybe_scalar_long ();
19260 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19261 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19263 if (et
.type
== NT_poly
)
19264 NEON_ENCODE (POLY
, inst
);
19266 NEON_ENCODE (INTEGER
, inst
);
19268 /* For polynomial encoding the U bit must be zero, and the size must
19269 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19270 obviously, as 0b10). */
19273 /* Check we're on the correct architecture. */
19274 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19276 _("Instruction form not available on this architecture.");
19281 neon_mixed_length (et
, et
.size
);
19288 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19289 struct neon_type_el et
= neon_check_type (3, rs
,
19290 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19291 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19293 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19294 _("shift out of range"));
19295 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19296 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19297 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19298 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19299 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19300 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19301 inst
.instruction
|= neon_quad (rs
) << 6;
19302 inst
.instruction
|= imm
<< 8;
19304 neon_dp_fixup (&inst
);
19310 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19313 enum neon_shape rs
;
19314 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19315 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19317 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19319 struct neon_type_el et
= neon_check_type (2, rs
,
19320 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19322 unsigned op
= (inst
.instruction
>> 7) & 3;
19323 /* N (width of reversed regions) is encoded as part of the bitmask. We
19324 extract it here to check the elements to be reversed are smaller.
19325 Otherwise we'd get a reserved instruction. */
19326 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19328 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19329 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19330 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19331 " operands makes instruction UNPREDICTABLE"));
19333 gas_assert (elsize
!= 0);
19334 constraint (et
.size
>= elsize
,
19335 _("elements must be smaller than reversal region"));
19336 neon_two_same (neon_quad (rs
), 1, et
.size
);
19342 if (inst
.operands
[1].isscalar
)
19344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19346 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19347 struct neon_type_el et
= neon_check_type (2, rs
,
19348 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19349 unsigned sizebits
= et
.size
>> 3;
19350 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19351 int logsize
= neon_logbits (et
.size
);
19352 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19354 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19357 NEON_ENCODE (SCALAR
, inst
);
19358 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19359 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19360 inst
.instruction
|= LOW4 (dm
);
19361 inst
.instruction
|= HI1 (dm
) << 5;
19362 inst
.instruction
|= neon_quad (rs
) << 6;
19363 inst
.instruction
|= x
<< 17;
19364 inst
.instruction
|= sizebits
<< 16;
19366 neon_dp_fixup (&inst
);
19370 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19371 struct neon_type_el et
= neon_check_type (2, rs
,
19372 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19375 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
))
19379 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19382 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19384 if (inst
.operands
[1].reg
== REG_SP
)
19385 as_tsktsk (MVE_BAD_SP
);
19386 else if (inst
.operands
[1].reg
== REG_PC
)
19387 as_tsktsk (MVE_BAD_PC
);
19390 /* Duplicate ARM register to lanes of vector. */
19391 NEON_ENCODE (ARMREG
, inst
);
19394 case 8: inst
.instruction
|= 0x400000; break;
19395 case 16: inst
.instruction
|= 0x000020; break;
19396 case 32: inst
.instruction
|= 0x000000; break;
19399 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19400 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19401 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19402 inst
.instruction
|= neon_quad (rs
) << 21;
19403 /* The encoding for this instruction is identical for the ARM and Thumb
19404 variants, except for the condition field. */
19405 do_vfp_cond_or_thumb ();
19410 do_mve_mov (int toQ
)
19412 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19414 if (inst
.cond
> COND_ALWAYS
)
19415 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19417 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19426 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19427 _("Index one must be [2,3] and index two must be two less than"
19429 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19430 _("General purpose registers may not be the same"));
19431 constraint (inst
.operands
[Rt
].reg
== REG_SP
19432 || inst
.operands
[Rt2
].reg
== REG_SP
,
19434 constraint (inst
.operands
[Rt
].reg
== REG_PC
19435 || inst
.operands
[Rt2
].reg
== REG_PC
,
19438 inst
.instruction
= 0xec000f00;
19439 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19440 inst
.instruction
|= !!toQ
<< 20;
19441 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19442 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19443 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19444 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19450 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19453 if (inst
.cond
> COND_ALWAYS
)
19454 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19456 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19458 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19461 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19462 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19463 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19464 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19465 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19470 /* VMOV has particularly many variations. It can be one of:
19471 0. VMOV<c><q> <Qd>, <Qm>
19472 1. VMOV<c><q> <Dd>, <Dm>
19473 (Register operations, which are VORR with Rm = Rn.)
19474 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19475 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19477 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19478 (ARM register to scalar.)
19479 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19480 (Two ARM registers to vector.)
19481 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19482 (Scalar to ARM register.)
19483 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19484 (Vector to two ARM registers.)
19485 8. VMOV.F32 <Sd>, <Sm>
19486 9. VMOV.F64 <Dd>, <Dm>
19487 (VFP register moves.)
19488 10. VMOV.F32 <Sd>, #imm
19489 11. VMOV.F64 <Dd>, #imm
19490 (VFP float immediate load.)
19491 12. VMOV <Rd>, <Sm>
19492 (VFP single to ARM reg.)
19493 13. VMOV <Sd>, <Rm>
19494 (ARM reg to VFP single.)
19495 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19496 (Two ARM regs to two VFP singles.)
19497 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19498 (Two VFP singles to two ARM regs.)
19499 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19500 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19501 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19502 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19504 These cases can be disambiguated using neon_select_shape, except cases 1/9
19505 and 3/11 which depend on the operand type too.
19507 All the encoded bits are hardcoded by this function.
19509 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19510 Cases 5, 7 may be used with VFPv2 and above.
19512 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19513 can specify a type where it doesn't make sense to, and is ignored). */
19518 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19519 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19520 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19521 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19523 struct neon_type_el et
;
19524 const char *ldconst
= 0;
19528 case NS_DD
: /* case 1/9. */
19529 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19530 /* It is not an error here if no type is given. */
19532 if (et
.type
== NT_float
&& et
.size
== 64)
19534 do_vfp_nsyn_opcode ("fcpyd");
19537 /* fall through. */
19539 case NS_QQ
: /* case 0/1. */
19541 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19543 /* The architecture manual I have doesn't explicitly state which
19544 value the U bit should have for register->register moves, but
19545 the equivalent VORR instruction has U = 0, so do that. */
19546 inst
.instruction
= 0x0200110;
19547 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19548 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19549 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19550 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19551 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19552 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19553 inst
.instruction
|= neon_quad (rs
) << 6;
19555 neon_dp_fixup (&inst
);
19559 case NS_DI
: /* case 3/11. */
19560 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19562 if (et
.type
== NT_float
&& et
.size
== 64)
19564 /* case 11 (fconstd). */
19565 ldconst
= "fconstd";
19566 goto encode_fconstd
;
19568 /* fall through. */
19570 case NS_QI
: /* case 2/3. */
19571 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19573 inst
.instruction
= 0x0800010;
19574 neon_move_immediate ();
19575 neon_dp_fixup (&inst
);
19578 case NS_SR
: /* case 4. */
19580 unsigned bcdebits
= 0;
19582 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19583 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19585 /* .<size> is optional here, defaulting to .32. */
19586 if (inst
.vectype
.elems
== 0
19587 && inst
.operands
[0].vectype
.type
== NT_invtype
19588 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19590 inst
.vectype
.el
[0].type
= NT_untyped
;
19591 inst
.vectype
.el
[0].size
= 32;
19592 inst
.vectype
.elems
= 1;
19595 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19596 logsize
= neon_logbits (et
.size
);
19600 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19601 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19606 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19607 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19613 if (inst
.operands
[1].reg
== REG_SP
)
19614 as_tsktsk (MVE_BAD_SP
);
19615 else if (inst
.operands
[1].reg
== REG_PC
)
19616 as_tsktsk (MVE_BAD_PC
);
19618 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19620 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19621 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19626 case 8: bcdebits
= 0x8; break;
19627 case 16: bcdebits
= 0x1; break;
19628 case 32: bcdebits
= 0x0; break;
19632 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19634 inst
.instruction
= 0xe000b10;
19635 do_vfp_cond_or_thumb ();
19636 inst
.instruction
|= LOW4 (dn
) << 16;
19637 inst
.instruction
|= HI1 (dn
) << 7;
19638 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19639 inst
.instruction
|= (bcdebits
& 3) << 5;
19640 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19641 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19645 case NS_DRR
: /* case 5 (fmdrr). */
19646 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19647 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19650 inst
.instruction
= 0xc400b10;
19651 do_vfp_cond_or_thumb ();
19652 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19653 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19654 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19655 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19658 case NS_RS
: /* case 6. */
19661 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19662 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19663 unsigned abcdebits
= 0;
19665 /* .<dt> is optional here, defaulting to .32. */
19666 if (inst
.vectype
.elems
== 0
19667 && inst
.operands
[0].vectype
.type
== NT_invtype
19668 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19670 inst
.vectype
.el
[0].type
= NT_untyped
;
19671 inst
.vectype
.el
[0].size
= 32;
19672 inst
.vectype
.elems
= 1;
19675 et
= neon_check_type (2, NS_NULL
,
19676 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19677 logsize
= neon_logbits (et
.size
);
19681 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19682 && vfp_or_neon_is_neon (NEON_CHECK_CC
19683 | NEON_CHECK_ARCH
) == FAIL
)
19688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19689 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19693 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19695 if (inst
.operands
[0].reg
== REG_SP
)
19696 as_tsktsk (MVE_BAD_SP
);
19697 else if (inst
.operands
[0].reg
== REG_PC
)
19698 as_tsktsk (MVE_BAD_PC
);
19701 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19703 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19704 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19708 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19709 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19710 case 32: abcdebits
= 0x00; break;
19714 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19715 inst
.instruction
= 0xe100b10;
19716 do_vfp_cond_or_thumb ();
19717 inst
.instruction
|= LOW4 (dn
) << 16;
19718 inst
.instruction
|= HI1 (dn
) << 7;
19719 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19720 inst
.instruction
|= (abcdebits
& 3) << 5;
19721 inst
.instruction
|= (abcdebits
>> 2) << 21;
19722 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19726 case NS_RRD
: /* case 7 (fmrrd). */
19727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19728 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19731 inst
.instruction
= 0xc500b10;
19732 do_vfp_cond_or_thumb ();
19733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19734 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19735 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19736 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19739 case NS_FF
: /* case 8 (fcpys). */
19740 do_vfp_nsyn_opcode ("fcpys");
19744 case NS_FI
: /* case 10 (fconsts). */
19745 ldconst
= "fconsts";
19747 if (!inst
.operands
[1].immisfloat
)
19750 /* Immediate has to fit in 8 bits so float is enough. */
19751 float imm
= (float) inst
.operands
[1].imm
;
19752 memcpy (&new_imm
, &imm
, sizeof (float));
19753 /* But the assembly may have been written to provide an integer
19754 bit pattern that equates to a float, so check that the
19755 conversion has worked. */
19756 if (is_quarter_float (new_imm
))
19758 if (is_quarter_float (inst
.operands
[1].imm
))
19759 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19761 inst
.operands
[1].imm
= new_imm
;
19762 inst
.operands
[1].immisfloat
= 1;
19766 if (is_quarter_float (inst
.operands
[1].imm
))
19768 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19769 do_vfp_nsyn_opcode (ldconst
);
19771 /* ARMv8.2 fp16 vmov.f16 instruction. */
19773 do_scalar_fp16_v82_encode ();
19776 first_error (_("immediate out of range"));
19780 case NS_RF
: /* case 12 (fmrs). */
19781 do_vfp_nsyn_opcode ("fmrs");
19782 /* ARMv8.2 fp16 vmov.f16 instruction. */
19784 do_scalar_fp16_v82_encode ();
19788 case NS_FR
: /* case 13 (fmsr). */
19789 do_vfp_nsyn_opcode ("fmsr");
19790 /* ARMv8.2 fp16 vmov.f16 instruction. */
19792 do_scalar_fp16_v82_encode ();
19802 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19803 (one of which is a list), but we have parsed four. Do some fiddling to
19804 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19806 case NS_RRFF
: /* case 14 (fmrrs). */
19807 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19808 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19810 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19811 _("VFP registers must be adjacent"));
19812 inst
.operands
[2].imm
= 2;
19813 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19814 do_vfp_nsyn_opcode ("fmrrs");
19817 case NS_FFRR
: /* case 15 (fmsrr). */
19818 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19819 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19821 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19822 _("VFP registers must be adjacent"));
19823 inst
.operands
[1] = inst
.operands
[2];
19824 inst
.operands
[2] = inst
.operands
[3];
19825 inst
.operands
[0].imm
= 2;
19826 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19827 do_vfp_nsyn_opcode ("fmsrr");
19831 /* neon_select_shape has determined that the instruction
19832 shape is wrong and has already set the error message. */
19843 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19844 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19845 && !inst
.operands
[2].present
))
19847 inst
.instruction
= 0;
19850 set_pred_insn_type (INSIDE_IT_INSN
);
19855 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19858 if (inst
.cond
!= COND_ALWAYS
)
19859 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19861 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19862 | N_S16
| N_U16
| N_KEY
);
19864 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19865 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19866 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19867 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19868 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19869 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19874 do_neon_rshift_round_imm (void)
19876 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19879 enum neon_shape rs
;
19880 struct neon_type_el et
;
19882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19884 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
19885 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
19889 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19890 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19892 int imm
= inst
.operands
[2].imm
;
19894 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19897 inst
.operands
[2].present
= 0;
19902 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19903 _("immediate out of range for shift"));
19904 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19909 do_neon_movhf (void)
19911 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19912 constraint (rs
!= NS_HH
, _("invalid suffix"));
19914 if (inst
.cond
!= COND_ALWAYS
)
19918 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19919 " the behaviour is UNPREDICTABLE"));
19923 inst
.error
= BAD_COND
;
19928 do_vfp_sp_monadic ();
19931 inst
.instruction
|= 0xf0000000;
19935 do_neon_movl (void)
19937 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19938 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19939 unsigned sizebits
= et
.size
>> 3;
19940 inst
.instruction
|= sizebits
<< 19;
19941 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19947 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19948 struct neon_type_el et
= neon_check_type (2, rs
,
19949 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19950 NEON_ENCODE (INTEGER
, inst
);
19951 neon_two_same (neon_quad (rs
), 1, et
.size
);
19955 do_neon_zip_uzp (void)
19957 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19958 struct neon_type_el et
= neon_check_type (2, rs
,
19959 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19960 if (rs
== NS_DD
&& et
.size
== 32)
19962 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19963 inst
.instruction
= N_MNEM_vtrn
;
19967 neon_two_same (neon_quad (rs
), 1, et
.size
);
19971 do_neon_sat_abs_neg (void)
19973 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19976 enum neon_shape rs
;
19977 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19978 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19980 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19981 struct neon_type_el et
= neon_check_type (2, rs
,
19982 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19983 neon_two_same (neon_quad (rs
), 1, et
.size
);
19987 do_neon_pair_long (void)
19989 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19990 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
19991 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19992 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
19993 neon_two_same (neon_quad (rs
), 1, et
.size
);
19997 do_neon_recip_est (void)
19999 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20000 struct neon_type_el et
= neon_check_type (2, rs
,
20001 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20002 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20003 neon_two_same (neon_quad (rs
), 1, et
.size
);
20009 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20012 enum neon_shape rs
;
20013 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20014 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20016 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20018 struct neon_type_el et
= neon_check_type (2, rs
,
20019 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20020 neon_two_same (neon_quad (rs
), 1, et
.size
);
20026 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20029 enum neon_shape rs
;
20030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20031 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20033 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20035 struct neon_type_el et
= neon_check_type (2, rs
,
20036 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20037 neon_two_same (neon_quad (rs
), 1, et
.size
);
20043 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20044 struct neon_type_el et
= neon_check_type (2, rs
,
20045 N_EQK
| N_INT
, N_8
| N_KEY
);
20046 neon_two_same (neon_quad (rs
), 1, et
.size
);
20052 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20053 neon_two_same (neon_quad (rs
), 1, -1);
20057 do_neon_tbl_tbx (void)
20059 unsigned listlenbits
;
20060 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20062 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20064 first_error (_("bad list length for table lookup"));
20068 listlenbits
= inst
.operands
[1].imm
- 1;
20069 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20073 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20074 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20075 inst
.instruction
|= listlenbits
<< 8;
20077 neon_dp_fixup (&inst
);
20081 do_neon_ldm_stm (void)
20083 /* P, U and L bits are part of bitmask. */
20084 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20085 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20087 if (inst
.operands
[1].issingle
)
20089 do_vfp_nsyn_ldm_stm (is_dbmode
);
20093 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20094 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20096 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20097 _("register list must contain at least 1 and at most 16 "
20100 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20101 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20102 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20103 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20105 inst
.instruction
|= offsetbits
;
20107 do_vfp_cond_or_thumb ();
20111 do_neon_ldr_str (void)
20113 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20115 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20116 And is UNPREDICTABLE in thumb mode. */
20118 && inst
.operands
[1].reg
== REG_PC
20119 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20122 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20123 else if (warn_on_deprecated
)
20124 as_tsktsk (_("Use of PC here is deprecated"));
20127 if (inst
.operands
[0].issingle
)
20130 do_vfp_nsyn_opcode ("flds");
20132 do_vfp_nsyn_opcode ("fsts");
20134 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20135 if (inst
.vectype
.el
[0].size
== 16)
20136 do_scalar_fp16_v82_encode ();
20141 do_vfp_nsyn_opcode ("fldd");
20143 do_vfp_nsyn_opcode ("fstd");
20148 do_t_vldr_vstr_sysreg (void)
20150 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20151 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20153 /* Use of PC is UNPREDICTABLE. */
20154 if (inst
.operands
[1].reg
== REG_PC
)
20155 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20157 if (inst
.operands
[1].immisreg
)
20158 inst
.error
= _("instruction does not accept register index");
20160 if (!inst
.operands
[1].isreg
)
20161 inst
.error
= _("instruction does not accept PC-relative addressing");
20163 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20164 inst
.error
= _("immediate value out of range");
20166 inst
.instruction
= 0xec000f80;
20168 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20169 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20170 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20171 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20175 do_vldr_vstr (void)
20177 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20179 /* VLDR/VSTR (System Register). */
20182 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20183 as_bad (_("Instruction not permitted on this architecture"));
20185 do_t_vldr_vstr_sysreg ();
20190 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20191 as_bad (_("Instruction not permitted on this architecture"));
20192 do_neon_ldr_str ();
20196 /* "interleave" version also handles non-interleaving register VLD1/VST1
20200 do_neon_ld_st_interleave (void)
20202 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20203 N_8
| N_16
| N_32
| N_64
);
20204 unsigned alignbits
= 0;
20206 /* The bits in this table go:
20207 0: register stride of one (0) or two (1)
20208 1,2: register list length, minus one (1, 2, 3, 4).
20209 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20210 We use -1 for invalid entries. */
20211 const int typetable
[] =
20213 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20214 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20215 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20216 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20220 if (et
.type
== NT_invtype
)
20223 if (inst
.operands
[1].immisalign
)
20224 switch (inst
.operands
[1].imm
>> 8)
20226 case 64: alignbits
= 1; break;
20228 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20229 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20230 goto bad_alignment
;
20234 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20235 goto bad_alignment
;
20240 first_error (_("bad alignment"));
20244 inst
.instruction
|= alignbits
<< 4;
20245 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20247 /* Bits [4:6] of the immediate in a list specifier encode register stride
20248 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20249 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20250 up the right value for "type" in a table based on this value and the given
20251 list style, then stick it back. */
20252 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20253 | (((inst
.instruction
>> 8) & 3) << 3);
20255 typebits
= typetable
[idx
];
20257 constraint (typebits
== -1, _("bad list type for instruction"));
20258 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20261 inst
.instruction
&= ~0xf00;
20262 inst
.instruction
|= typebits
<< 8;
20265 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20266 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20267 otherwise. The variable arguments are a list of pairs of legal (size, align)
20268 values, terminated with -1. */
20271 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20274 int result
= FAIL
, thissize
, thisalign
;
20276 if (!inst
.operands
[1].immisalign
)
20282 va_start (ap
, do_alignment
);
20286 thissize
= va_arg (ap
, int);
20287 if (thissize
== -1)
20289 thisalign
= va_arg (ap
, int);
20291 if (size
== thissize
&& align
== thisalign
)
20294 while (result
!= SUCCESS
);
20298 if (result
== SUCCESS
)
20301 first_error (_("unsupported alignment for instruction"));
20307 do_neon_ld_st_lane (void)
20309 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20310 int align_good
, do_alignment
= 0;
20311 int logsize
= neon_logbits (et
.size
);
20312 int align
= inst
.operands
[1].imm
>> 8;
20313 int n
= (inst
.instruction
>> 8) & 3;
20314 int max_el
= 64 / et
.size
;
20316 if (et
.type
== NT_invtype
)
20319 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20320 _("bad list length"));
20321 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20322 _("scalar index out of range"));
20323 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20325 _("stride of 2 unavailable when element size is 8"));
20329 case 0: /* VLD1 / VST1. */
20330 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20332 if (align_good
== FAIL
)
20336 unsigned alignbits
= 0;
20339 case 16: alignbits
= 0x1; break;
20340 case 32: alignbits
= 0x3; break;
20343 inst
.instruction
|= alignbits
<< 4;
20347 case 1: /* VLD2 / VST2. */
20348 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20349 16, 32, 32, 64, -1);
20350 if (align_good
== FAIL
)
20353 inst
.instruction
|= 1 << 4;
20356 case 2: /* VLD3 / VST3. */
20357 constraint (inst
.operands
[1].immisalign
,
20358 _("can't use alignment with this instruction"));
20361 case 3: /* VLD4 / VST4. */
20362 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20363 16, 64, 32, 64, 32, 128, -1);
20364 if (align_good
== FAIL
)
20368 unsigned alignbits
= 0;
20371 case 8: alignbits
= 0x1; break;
20372 case 16: alignbits
= 0x1; break;
20373 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20376 inst
.instruction
|= alignbits
<< 4;
20383 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20384 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20385 inst
.instruction
|= 1 << (4 + logsize
);
20387 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20388 inst
.instruction
|= logsize
<< 10;
20391 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20394 do_neon_ld_dup (void)
20396 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20397 int align_good
, do_alignment
= 0;
20399 if (et
.type
== NT_invtype
)
20402 switch ((inst
.instruction
>> 8) & 3)
20404 case 0: /* VLD1. */
20405 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20406 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20407 &do_alignment
, 16, 16, 32, 32, -1);
20408 if (align_good
== FAIL
)
20410 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20413 case 2: inst
.instruction
|= 1 << 5; break;
20414 default: first_error (_("bad list length")); return;
20416 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20419 case 1: /* VLD2. */
20420 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20421 &do_alignment
, 8, 16, 16, 32, 32, 64,
20423 if (align_good
== FAIL
)
20425 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20426 _("bad list length"));
20427 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20428 inst
.instruction
|= 1 << 5;
20429 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20432 case 2: /* VLD3. */
20433 constraint (inst
.operands
[1].immisalign
,
20434 _("can't use alignment with this instruction"));
20435 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20436 _("bad list length"));
20437 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20438 inst
.instruction
|= 1 << 5;
20439 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20442 case 3: /* VLD4. */
20444 int align
= inst
.operands
[1].imm
>> 8;
20445 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20446 16, 64, 32, 64, 32, 128, -1);
20447 if (align_good
== FAIL
)
20449 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20450 _("bad list length"));
20451 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20452 inst
.instruction
|= 1 << 5;
20453 if (et
.size
== 32 && align
== 128)
20454 inst
.instruction
|= 0x3 << 6;
20456 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20463 inst
.instruction
|= do_alignment
<< 4;
20466 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20467 apart from bits [11:4]. */
20470 do_neon_ldx_stx (void)
20472 if (inst
.operands
[1].isreg
)
20473 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20475 switch (NEON_LANE (inst
.operands
[0].imm
))
20477 case NEON_INTERLEAVE_LANES
:
20478 NEON_ENCODE (INTERLV
, inst
);
20479 do_neon_ld_st_interleave ();
20482 case NEON_ALL_LANES
:
20483 NEON_ENCODE (DUP
, inst
);
20484 if (inst
.instruction
== N_INV
)
20486 first_error ("only loads support such operands");
20493 NEON_ENCODE (LANE
, inst
);
20494 do_neon_ld_st_lane ();
20497 /* L bit comes from bit mask. */
20498 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20499 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20500 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20502 if (inst
.operands
[1].postind
)
20504 int postreg
= inst
.operands
[1].imm
& 0xf;
20505 constraint (!inst
.operands
[1].immisreg
,
20506 _("post-index must be a register"));
20507 constraint (postreg
== 0xd || postreg
== 0xf,
20508 _("bad register for post-index"));
20509 inst
.instruction
|= postreg
;
20513 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20514 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20515 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20518 if (inst
.operands
[1].writeback
)
20520 inst
.instruction
|= 0xd;
20523 inst
.instruction
|= 0xf;
20527 inst
.instruction
|= 0xf9000000;
20529 inst
.instruction
|= 0xf4000000;
20534 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20536 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20537 D register operands. */
20538 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20539 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20542 NEON_ENCODE (FPV8
, inst
);
20544 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20546 do_vfp_sp_dyadic ();
20548 /* ARMv8.2 fp16 instruction. */
20550 do_scalar_fp16_v82_encode ();
20553 do_vfp_dp_rd_rn_rm ();
20556 inst
.instruction
|= 0x100;
20558 inst
.instruction
|= 0xf0000000;
20564 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20566 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20567 first_error (_("invalid instruction shape"));
20573 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20574 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20576 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20579 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20582 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20586 do_vrint_1 (enum neon_cvt_mode mode
)
20588 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20589 struct neon_type_el et
;
20594 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20595 D register operands. */
20596 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20600 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20602 if (et
.type
!= NT_invtype
)
20604 /* VFP encodings. */
20605 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20606 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20607 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20609 NEON_ENCODE (FPV8
, inst
);
20610 if (rs
== NS_FF
|| rs
== NS_HH
)
20611 do_vfp_sp_monadic ();
20613 do_vfp_dp_rd_rm ();
20617 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20618 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20619 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20620 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20621 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20622 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20623 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20627 inst
.instruction
|= (rs
== NS_DD
) << 8;
20628 do_vfp_cond_or_thumb ();
20630 /* ARMv8.2 fp16 vrint instruction. */
20632 do_scalar_fp16_v82_encode ();
20636 /* Neon encodings (or something broken...). */
20638 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20640 if (et
.type
== NT_invtype
)
20643 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20646 NEON_ENCODE (FLOAT
, inst
);
20648 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20649 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20650 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20651 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20652 inst
.instruction
|= neon_quad (rs
) << 6;
20653 /* Mask off the original size bits and reencode them. */
20654 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20655 | neon_logbits (et
.size
) << 18);
20659 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20660 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20661 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20662 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20663 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20664 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20665 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20670 inst
.instruction
|= 0xfc000000;
20672 inst
.instruction
|= 0xf0000000;
20679 do_vrint_1 (neon_cvt_mode_x
);
20685 do_vrint_1 (neon_cvt_mode_z
);
20691 do_vrint_1 (neon_cvt_mode_r
);
20697 do_vrint_1 (neon_cvt_mode_a
);
20703 do_vrint_1 (neon_cvt_mode_n
);
20709 do_vrint_1 (neon_cvt_mode_p
);
20715 do_vrint_1 (neon_cvt_mode_m
);
20719 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20721 unsigned regno
= NEON_SCALAR_REG (opnd
);
20722 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20724 if (elsize
== 16 && elno
< 2 && regno
< 16)
20725 return regno
| (elno
<< 4);
20726 else if (elsize
== 32 && elno
== 0)
20729 first_error (_("scalar out of range"));
20736 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20737 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20738 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20739 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20740 _("expression too complex"));
20741 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20742 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20743 _("immediate out of range"));
20746 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20749 if (inst
.operands
[2].isscalar
)
20751 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20752 first_error (_("invalid instruction shape"));
20753 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20754 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20755 N_KEY
| N_F16
| N_F32
).size
;
20756 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20758 inst
.instruction
= 0xfe000800;
20759 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20760 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20761 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20762 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20763 inst
.instruction
|= LOW4 (m
);
20764 inst
.instruction
|= HI1 (m
) << 5;
20765 inst
.instruction
|= neon_quad (rs
) << 6;
20766 inst
.instruction
|= rot
<< 20;
20767 inst
.instruction
|= (size
== 32) << 23;
20771 enum neon_shape rs
;
20772 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20773 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20775 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20777 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20778 N_KEY
| N_F16
| N_F32
).size
;
20779 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20780 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20781 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20782 as_tsktsk (BAD_MVE_SRCDEST
);
20784 neon_three_same (neon_quad (rs
), 0, -1);
20785 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20786 inst
.instruction
|= 0xfc200800;
20787 inst
.instruction
|= rot
<< 23;
20788 inst
.instruction
|= (size
== 32) << 20;
20795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20796 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20797 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20798 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20799 _("expression too complex"));
20801 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20802 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20803 enum neon_shape rs
;
20804 struct neon_type_el et
;
20805 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20807 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20808 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20812 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20813 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20815 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20816 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20817 "operand makes instruction UNPREDICTABLE"));
20820 if (et
.type
== NT_invtype
)
20823 if (check_simd_pred_availability (et
.type
== NT_float
, NEON_CHECK_ARCH8
20827 if (et
.type
== NT_float
)
20829 neon_three_same (neon_quad (rs
), 0, -1);
20830 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20831 inst
.instruction
|= 0xfc800800;
20832 inst
.instruction
|= (rot
== 270) << 24;
20833 inst
.instruction
|= (et
.size
== 32) << 20;
20837 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20838 inst
.instruction
= 0xfe000f00;
20839 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20840 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20841 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20842 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20843 inst
.instruction
|= (rot
== 270) << 12;
20844 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20845 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20846 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20851 /* Dot Product instructions encoding support. */
20854 do_neon_dotproduct (int unsigned_p
)
20856 enum neon_shape rs
;
20857 unsigned scalar_oprd2
= 0;
20860 if (inst
.cond
!= COND_ALWAYS
)
20861 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20862 "is UNPREDICTABLE"));
20864 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20867 /* Dot Product instructions are in three-same D/Q register format or the third
20868 operand can be a scalar index register. */
20869 if (inst
.operands
[2].isscalar
)
20871 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20872 high8
= 0xfe000000;
20873 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20877 high8
= 0xfc000000;
20878 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20882 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20884 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20886 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20887 Product instruction, so we pass 0 as the "ubit" parameter. And the
20888 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20889 neon_three_same (neon_quad (rs
), 0, 32);
20891 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20892 different NEON three-same encoding. */
20893 inst
.instruction
&= 0x00ffffff;
20894 inst
.instruction
|= high8
;
20895 /* Encode 'U' bit which indicates signedness. */
20896 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20897 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20898 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20899 the instruction encoding. */
20900 if (inst
.operands
[2].isscalar
)
20902 inst
.instruction
&= 0xffffffd0;
20903 inst
.instruction
|= LOW4 (scalar_oprd2
);
20904 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20908 /* Dot Product instructions for signed integer. */
20911 do_neon_dotproduct_s (void)
20913 return do_neon_dotproduct (0);
20916 /* Dot Product instructions for unsigned integer. */
20919 do_neon_dotproduct_u (void)
20921 return do_neon_dotproduct (1);
20924 /* Crypto v1 instructions. */
20926 do_crypto_2op_1 (unsigned elttype
, int op
)
20928 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20930 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20936 NEON_ENCODE (INTEGER
, inst
);
20937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20942 inst
.instruction
|= op
<< 6;
20945 inst
.instruction
|= 0xfc000000;
20947 inst
.instruction
|= 0xf0000000;
20951 do_crypto_3op_1 (int u
, int op
)
20953 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20955 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
20956 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
20961 NEON_ENCODE (INTEGER
, inst
);
20962 neon_three_same (1, u
, 8 << op
);
20968 do_crypto_2op_1 (N_8
, 0);
20974 do_crypto_2op_1 (N_8
, 1);
20980 do_crypto_2op_1 (N_8
, 2);
20986 do_crypto_2op_1 (N_8
, 3);
20992 do_crypto_3op_1 (0, 0);
20998 do_crypto_3op_1 (0, 1);
21004 do_crypto_3op_1 (0, 2);
21010 do_crypto_3op_1 (0, 3);
21016 do_crypto_3op_1 (1, 0);
21022 do_crypto_3op_1 (1, 1);
21026 do_sha256su1 (void)
21028 do_crypto_3op_1 (1, 2);
21034 do_crypto_2op_1 (N_32
, -1);
21040 do_crypto_2op_1 (N_32
, 0);
21044 do_sha256su0 (void)
21046 do_crypto_2op_1 (N_32
, 1);
21050 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21052 unsigned int Rd
= inst
.operands
[0].reg
;
21053 unsigned int Rn
= inst
.operands
[1].reg
;
21054 unsigned int Rm
= inst
.operands
[2].reg
;
21056 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21057 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21058 inst
.instruction
|= LOW4 (Rn
) << 16;
21059 inst
.instruction
|= LOW4 (Rm
);
21060 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21061 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21063 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21064 as_warn (UNPRED_REG ("r15"));
21106 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21108 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21109 do_vfp_sp_dp_cvt ();
21110 do_vfp_cond_or_thumb ();
21114 /* Overall per-instruction processing. */
21116 /* We need to be able to fix up arbitrary expressions in some statements.
21117 This is so that we can handle symbols that are an arbitrary distance from
21118 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21119 which returns part of an address in a form which will be valid for
21120 a data instruction. We do this by pushing the expression into a symbol
21121 in the expr_section, and creating a fix for that. */
21124 fix_new_arm (fragS
* frag
,
21138 /* Create an absolute valued symbol, so we have something to
21139 refer to in the object file. Unfortunately for us, gas's
21140 generic expression parsing will already have folded out
21141 any use of .set foo/.type foo %function that may have
21142 been used to set type information of the target location,
21143 that's being specified symbolically. We have to presume
21144 the user knows what they are doing. */
21148 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21150 symbol
= symbol_find_or_make (name
);
21151 S_SET_SEGMENT (symbol
, absolute_section
);
21152 symbol_set_frag (symbol
, &zero_address_frag
);
21153 S_SET_VALUE (symbol
, exp
->X_add_number
);
21154 exp
->X_op
= O_symbol
;
21155 exp
->X_add_symbol
= symbol
;
21156 exp
->X_add_number
= 0;
21162 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21163 (enum bfd_reloc_code_real
) reloc
);
21167 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21168 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21172 /* Mark whether the fix is to a THUMB instruction, or an ARM
21174 new_fix
->tc_fix_data
= thumb_mode
;
21177 /* Create a frg for an instruction requiring relaxation. */
21179 output_relax_insn (void)
21185 /* The size of the instruction is unknown, so tie the debug info to the
21186 start of the instruction. */
21187 dwarf2_emit_insn (0);
21189 switch (inst
.relocs
[0].exp
.X_op
)
21192 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21193 offset
= inst
.relocs
[0].exp
.X_add_number
;
21197 offset
= inst
.relocs
[0].exp
.X_add_number
;
21200 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21204 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21205 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21206 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21209 /* Write a 32-bit thumb instruction to buf. */
21211 put_thumb32_insn (char * buf
, unsigned long insn
)
21213 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21214 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21218 output_inst (const char * str
)
21224 as_bad ("%s -- `%s'", inst
.error
, str
);
21229 output_relax_insn ();
21232 if (inst
.size
== 0)
21235 to
= frag_more (inst
.size
);
21236 /* PR 9814: Record the thumb mode into the current frag so that we know
21237 what type of NOP padding to use, if necessary. We override any previous
21238 setting so that if the mode has changed then the NOPS that we use will
21239 match the encoding of the last instruction in the frag. */
21240 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21242 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21244 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21245 put_thumb32_insn (to
, inst
.instruction
);
21247 else if (inst
.size
> INSN_SIZE
)
21249 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21250 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21251 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21254 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21257 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21259 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21260 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21261 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21262 inst
.relocs
[r
].type
);
21265 dwarf2_emit_insn (inst
.size
);
21269 output_it_inst (int cond
, int mask
, char * to
)
21271 unsigned long instruction
= 0xbf00;
21274 instruction
|= mask
;
21275 instruction
|= cond
<< 4;
21279 to
= frag_more (2);
21281 dwarf2_emit_insn (2);
21285 md_number_to_chars (to
, instruction
, 2);
21290 /* Tag values used in struct asm_opcode's tag field. */
21293 OT_unconditional
, /* Instruction cannot be conditionalized.
21294 The ARM condition field is still 0xE. */
21295 OT_unconditionalF
, /* Instruction cannot be conditionalized
21296 and carries 0xF in its ARM condition field. */
21297 OT_csuffix
, /* Instruction takes a conditional suffix. */
21298 OT_csuffixF
, /* Some forms of the instruction take a scalar
21299 conditional suffix, others place 0xF where the
21300 condition field would be, others take a vector
21301 conditional suffix. */
21302 OT_cinfix3
, /* Instruction takes a conditional infix,
21303 beginning at character index 3. (In
21304 unified mode, it becomes a suffix.) */
21305 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21306 tsts, cmps, cmns, and teqs. */
21307 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21308 character index 3, even in unified mode. Used for
21309 legacy instructions where suffix and infix forms
21310 may be ambiguous. */
21311 OT_csuf_or_in3
, /* Instruction takes either a conditional
21312 suffix or an infix at character index 3. */
21313 OT_odd_infix_unc
, /* This is the unconditional variant of an
21314 instruction that takes a conditional infix
21315 at an unusual position. In unified mode,
21316 this variant will accept a suffix. */
21317 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21318 are the conditional variants of instructions that
21319 take conditional infixes in unusual positions.
21320 The infix appears at character index
21321 (tag - OT_odd_infix_0). These are not accepted
21322 in unified mode. */
21325 /* Subroutine of md_assemble, responsible for looking up the primary
21326 opcode from the mnemonic the user wrote. STR points to the
21327 beginning of the mnemonic.
21329 This is not simply a hash table lookup, because of conditional
21330 variants. Most instructions have conditional variants, which are
21331 expressed with a _conditional affix_ to the mnemonic. If we were
21332 to encode each conditional variant as a literal string in the opcode
21333 table, it would have approximately 20,000 entries.
21335 Most mnemonics take this affix as a suffix, and in unified syntax,
21336 'most' is upgraded to 'all'. However, in the divided syntax, some
21337 instructions take the affix as an infix, notably the s-variants of
21338 the arithmetic instructions. Of those instructions, all but six
21339 have the infix appear after the third character of the mnemonic.
21341 Accordingly, the algorithm for looking up primary opcodes given
21344 1. Look up the identifier in the opcode table.
21345 If we find a match, go to step U.
21347 2. Look up the last two characters of the identifier in the
21348 conditions table. If we find a match, look up the first N-2
21349 characters of the identifier in the opcode table. If we
21350 find a match, go to step CE.
21352 3. Look up the fourth and fifth characters of the identifier in
21353 the conditions table. If we find a match, extract those
21354 characters from the identifier, and look up the remaining
21355 characters in the opcode table. If we find a match, go
21360 U. Examine the tag field of the opcode structure, in case this is
21361 one of the six instructions with its conditional infix in an
21362 unusual place. If it is, the tag tells us where to find the
21363 infix; look it up in the conditions table and set inst.cond
21364 accordingly. Otherwise, this is an unconditional instruction.
21365 Again set inst.cond accordingly. Return the opcode structure.
21367 CE. Examine the tag field to make sure this is an instruction that
21368 should receive a conditional suffix. If it is not, fail.
21369 Otherwise, set inst.cond from the suffix we already looked up,
21370 and return the opcode structure.
21372 CM. Examine the tag field to make sure this is an instruction that
21373 should receive a conditional infix after the third character.
21374 If it is not, fail. Otherwise, undo the edits to the current
21375 line of input and proceed as for case CE. */
21377 static const struct asm_opcode
*
21378 opcode_lookup (char **str
)
21382 const struct asm_opcode
*opcode
;
21383 const struct asm_cond
*cond
;
21386 /* Scan up to the end of the mnemonic, which must end in white space,
21387 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21388 for (base
= end
= *str
; *end
!= '\0'; end
++)
21389 if (*end
== ' ' || *end
== '.')
21395 /* Handle a possible width suffix and/or Neon type suffix. */
21400 /* The .w and .n suffixes are only valid if the unified syntax is in
21402 if (unified_syntax
&& end
[1] == 'w')
21404 else if (unified_syntax
&& end
[1] == 'n')
21409 inst
.vectype
.elems
= 0;
21411 *str
= end
+ offset
;
21413 if (end
[offset
] == '.')
21415 /* See if we have a Neon type suffix (possible in either unified or
21416 non-unified ARM syntax mode). */
21417 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21420 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21426 /* Look for unaffixed or special-case affixed mnemonic. */
21427 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21432 if (opcode
->tag
< OT_odd_infix_0
)
21434 inst
.cond
= COND_ALWAYS
;
21438 if (warn_on_deprecated
&& unified_syntax
)
21439 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21440 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21441 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21444 inst
.cond
= cond
->value
;
21447 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21449 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21451 if (end
- base
< 2)
21454 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21455 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21457 /* If this opcode can not be vector predicated then don't accept it with a
21458 vector predication code. */
21459 if (opcode
&& !opcode
->mayBeVecPred
)
21462 if (!opcode
|| !cond
)
21464 /* Cannot have a conditional suffix on a mnemonic of less than two
21466 if (end
- base
< 3)
21469 /* Look for suffixed mnemonic. */
21471 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21472 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21476 if (opcode
&& cond
)
21479 switch (opcode
->tag
)
21481 case OT_cinfix3_legacy
:
21482 /* Ignore conditional suffixes matched on infix only mnemonics. */
21486 case OT_cinfix3_deprecated
:
21487 case OT_odd_infix_unc
:
21488 if (!unified_syntax
)
21490 /* Fall through. */
21494 case OT_csuf_or_in3
:
21495 inst
.cond
= cond
->value
;
21498 case OT_unconditional
:
21499 case OT_unconditionalF
:
21501 inst
.cond
= cond
->value
;
21504 /* Delayed diagnostic. */
21505 inst
.error
= BAD_COND
;
21506 inst
.cond
= COND_ALWAYS
;
21515 /* Cannot have a usual-position infix on a mnemonic of less than
21516 six characters (five would be a suffix). */
21517 if (end
- base
< 6)
21520 /* Look for infixed mnemonic in the usual position. */
21522 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21526 memcpy (save
, affix
, 2);
21527 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21528 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21530 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21531 memcpy (affix
, save
, 2);
21534 && (opcode
->tag
== OT_cinfix3
21535 || opcode
->tag
== OT_cinfix3_deprecated
21536 || opcode
->tag
== OT_csuf_or_in3
21537 || opcode
->tag
== OT_cinfix3_legacy
))
21540 if (warn_on_deprecated
&& unified_syntax
21541 && (opcode
->tag
== OT_cinfix3
21542 || opcode
->tag
== OT_cinfix3_deprecated
))
21543 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21545 inst
.cond
= cond
->value
;
21552 /* This function generates an initial IT instruction, leaving its block
21553 virtually open for the new instructions. Eventually,
21554 the mask will be updated by now_pred_add_mask () each time
21555 a new instruction needs to be included in the IT block.
21556 Finally, the block is closed with close_automatic_it_block ().
21557 The block closure can be requested either from md_assemble (),
21558 a tencode (), or due to a label hook. */
21561 new_automatic_it_block (int cond
)
21563 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21564 now_pred
.mask
= 0x18;
21565 now_pred
.cc
= cond
;
21566 now_pred
.block_length
= 1;
21567 mapping_state (MAP_THUMB
);
21568 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21569 now_pred
.warn_deprecated
= FALSE
;
21570 now_pred
.insn_cond
= TRUE
;
21573 /* Close an automatic IT block.
21574 See comments in new_automatic_it_block (). */
21577 close_automatic_it_block (void)
21579 now_pred
.mask
= 0x10;
21580 now_pred
.block_length
= 0;
21583 /* Update the mask of the current automatically-generated IT
21584 instruction. See comments in new_automatic_it_block (). */
21587 now_pred_add_mask (int cond
)
21589 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21590 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21591 | ((bitvalue) << (nbit)))
21592 const int resulting_bit
= (cond
& 1);
21594 now_pred
.mask
&= 0xf;
21595 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21597 (5 - now_pred
.block_length
));
21598 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21600 ((5 - now_pred
.block_length
) - 1));
21601 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21604 #undef SET_BIT_VALUE
21607 /* The IT blocks handling machinery is accessed through the these functions:
21608 it_fsm_pre_encode () from md_assemble ()
21609 set_pred_insn_type () optional, from the tencode functions
21610 set_pred_insn_type_last () ditto
21611 in_pred_block () ditto
21612 it_fsm_post_encode () from md_assemble ()
21613 force_automatic_it_block_close () from label handling functions
21616 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21617 initializing the IT insn type with a generic initial value depending
21618 on the inst.condition.
21619 2) During the tencode function, two things may happen:
21620 a) The tencode function overrides the IT insn type by
21621 calling either set_pred_insn_type (type) or
21622 set_pred_insn_type_last ().
21623 b) The tencode function queries the IT block state by
21624 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21626 Both set_pred_insn_type and in_pred_block run the internal FSM state
21627 handling function (handle_pred_state), because: a) setting the IT insn
21628 type may incur in an invalid state (exiting the function),
21629 and b) querying the state requires the FSM to be updated.
21630 Specifically we want to avoid creating an IT block for conditional
21631 branches, so it_fsm_pre_encode is actually a guess and we can't
21632 determine whether an IT block is required until the tencode () routine
21633 has decided what type of instruction this actually it.
21634 Because of this, if set_pred_insn_type and in_pred_block have to be
21635 used, set_pred_insn_type has to be called first.
21637 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21638 that determines the insn IT type depending on the inst.cond code.
21639 When a tencode () routine encodes an instruction that can be
21640 either outside an IT block, or, in the case of being inside, has to be
21641 the last one, set_pred_insn_type_last () will determine the proper
21642 IT instruction type based on the inst.cond code. Otherwise,
21643 set_pred_insn_type can be called for overriding that logic or
21644 for covering other cases.
21646 Calling handle_pred_state () may not transition the IT block state to
21647 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21648 still queried. Instead, if the FSM determines that the state should
21649 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21650 after the tencode () function: that's what it_fsm_post_encode () does.
21652 Since in_pred_block () calls the state handling function to get an
21653 updated state, an error may occur (due to invalid insns combination).
21654 In that case, inst.error is set.
21655 Therefore, inst.error has to be checked after the execution of
21656 the tencode () routine.
21658 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21659 any pending state change (if any) that didn't take place in
21660 handle_pred_state () as explained above. */
21663 it_fsm_pre_encode (void)
21665 if (inst
.cond
!= COND_ALWAYS
)
21666 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21668 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21670 now_pred
.state_handled
= 0;
21673 /* IT state FSM handling function. */
21674 /* MVE instructions and non-MVE instructions are handled differently because of
21675 the introduction of VPT blocks.
21676 Specifications say that any non-MVE instruction inside a VPT block is
21677 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21678 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21679 few exceptions we have MVE_UNPREDICABLE_INSN.
21680 The error messages provided depending on the different combinations possible
21681 are described in the cases below:
21682 For 'most' MVE instructions:
21683 1) In an IT block, with an IT code: syntax error
21684 2) In an IT block, with a VPT code: error: must be in a VPT block
21685 3) In an IT block, with no code: warning: UNPREDICTABLE
21686 4) In a VPT block, with an IT code: syntax error
21687 5) In a VPT block, with a VPT code: OK!
21688 6) In a VPT block, with no code: error: missing code
21689 7) Outside a pred block, with an IT code: error: syntax error
21690 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21691 9) Outside a pred block, with no code: OK!
21692 For non-MVE instructions:
21693 10) In an IT block, with an IT code: OK!
21694 11) In an IT block, with a VPT code: syntax error
21695 12) In an IT block, with no code: error: missing code
21696 13) In a VPT block, with an IT code: error: should be in an IT block
21697 14) In a VPT block, with a VPT code: syntax error
21698 15) In a VPT block, with no code: UNPREDICTABLE
21699 16) Outside a pred block, with an IT code: error: should be in an IT block
21700 17) Outside a pred block, with a VPT code: syntax error
21701 18) Outside a pred block, with no code: OK!
21706 handle_pred_state (void)
21708 now_pred
.state_handled
= 1;
21709 now_pred
.insn_cond
= FALSE
;
21711 switch (now_pred
.state
)
21713 case OUTSIDE_PRED_BLOCK
:
21714 switch (inst
.pred_insn_type
)
21716 case MVE_UNPREDICABLE_INSN
:
21717 case MVE_OUTSIDE_PRED_INSN
:
21718 if (inst
.cond
< COND_ALWAYS
)
21720 /* Case 7: Outside a pred block, with an IT code: error: syntax
21722 inst
.error
= BAD_SYNTAX
;
21725 /* Case 9: Outside a pred block, with no code: OK! */
21727 case OUTSIDE_PRED_INSN
:
21728 if (inst
.cond
> COND_ALWAYS
)
21730 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21732 inst
.error
= BAD_SYNTAX
;
21735 /* Case 18: Outside a pred block, with no code: OK! */
21738 case INSIDE_VPT_INSN
:
21739 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21741 inst
.error
= BAD_OUT_VPT
;
21744 case INSIDE_IT_INSN
:
21745 case INSIDE_IT_LAST_INSN
:
21746 if (inst
.cond
< COND_ALWAYS
)
21748 /* Case 16: Outside a pred block, with an IT code: error: should
21749 be in an IT block. */
21750 if (thumb_mode
== 0)
21753 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21754 as_tsktsk (_("Warning: conditional outside an IT block"\
21759 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21760 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21762 /* Automatically generate the IT instruction. */
21763 new_automatic_it_block (inst
.cond
);
21764 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21765 close_automatic_it_block ();
21769 inst
.error
= BAD_OUT_IT
;
21775 else if (inst
.cond
> COND_ALWAYS
)
21777 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21779 inst
.error
= BAD_SYNTAX
;
21784 case IF_INSIDE_IT_LAST_INSN
:
21785 case NEUTRAL_IT_INSN
:
21789 if (inst
.cond
!= COND_ALWAYS
)
21790 first_error (BAD_SYNTAX
);
21791 now_pred
.state
= MANUAL_PRED_BLOCK
;
21792 now_pred
.block_length
= 0;
21793 now_pred
.type
= VECTOR_PRED
;
21797 now_pred
.state
= MANUAL_PRED_BLOCK
;
21798 now_pred
.block_length
= 0;
21799 now_pred
.type
= SCALAR_PRED
;
21804 case AUTOMATIC_PRED_BLOCK
:
21805 /* Three things may happen now:
21806 a) We should increment current it block size;
21807 b) We should close current it block (closing insn or 4 insns);
21808 c) We should close current it block and start a new one (due
21809 to incompatible conditions or
21810 4 insns-length block reached). */
21812 switch (inst
.pred_insn_type
)
21814 case INSIDE_VPT_INSN
:
21816 case MVE_UNPREDICABLE_INSN
:
21817 case MVE_OUTSIDE_PRED_INSN
:
21819 case OUTSIDE_PRED_INSN
:
21820 /* The closure of the block shall happen immediately,
21821 so any in_pred_block () call reports the block as closed. */
21822 force_automatic_it_block_close ();
21825 case INSIDE_IT_INSN
:
21826 case INSIDE_IT_LAST_INSN
:
21827 case IF_INSIDE_IT_LAST_INSN
:
21828 now_pred
.block_length
++;
21830 if (now_pred
.block_length
> 4
21831 || !now_pred_compatible (inst
.cond
))
21833 force_automatic_it_block_close ();
21834 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21835 new_automatic_it_block (inst
.cond
);
21839 now_pred
.insn_cond
= TRUE
;
21840 now_pred_add_mask (inst
.cond
);
21843 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21844 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21845 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21846 close_automatic_it_block ();
21849 case NEUTRAL_IT_INSN
:
21850 now_pred
.block_length
++;
21851 now_pred
.insn_cond
= TRUE
;
21853 if (now_pred
.block_length
> 4)
21854 force_automatic_it_block_close ();
21856 now_pred_add_mask (now_pred
.cc
& 1);
21860 close_automatic_it_block ();
21861 now_pred
.state
= MANUAL_PRED_BLOCK
;
21866 case MANUAL_PRED_BLOCK
:
21869 if (now_pred
.type
== SCALAR_PRED
)
21871 /* Check conditional suffixes. */
21872 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21873 now_pred
.mask
<<= 1;
21874 now_pred
.mask
&= 0x1f;
21875 is_last
= (now_pred
.mask
== 0x10);
21879 now_pred
.cc
^= (now_pred
.mask
>> 4);
21880 cond
= now_pred
.cc
+ 0xf;
21881 now_pred
.mask
<<= 1;
21882 now_pred
.mask
&= 0x1f;
21883 is_last
= now_pred
.mask
== 0x10;
21885 now_pred
.insn_cond
= TRUE
;
21887 switch (inst
.pred_insn_type
)
21889 case OUTSIDE_PRED_INSN
:
21890 if (now_pred
.type
== SCALAR_PRED
)
21892 if (inst
.cond
== COND_ALWAYS
)
21894 /* Case 12: In an IT block, with no code: error: missing
21896 inst
.error
= BAD_NOT_IT
;
21899 else if (inst
.cond
> COND_ALWAYS
)
21901 /* Case 11: In an IT block, with a VPT code: syntax error.
21903 inst
.error
= BAD_SYNTAX
;
21906 else if (thumb_mode
)
21908 /* This is for some special cases where a non-MVE
21909 instruction is not allowed in an IT block, such as cbz,
21910 but are put into one with a condition code.
21911 You could argue this should be a syntax error, but we
21912 gave the 'not allowed in IT block' diagnostic in the
21913 past so we will keep doing so. */
21914 inst
.error
= BAD_NOT_IT
;
21921 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21922 as_tsktsk (MVE_NOT_VPT
);
21925 case MVE_OUTSIDE_PRED_INSN
:
21926 if (now_pred
.type
== SCALAR_PRED
)
21928 if (inst
.cond
== COND_ALWAYS
)
21930 /* Case 3: In an IT block, with no code: warning:
21932 as_tsktsk (MVE_NOT_IT
);
21935 else if (inst
.cond
< COND_ALWAYS
)
21937 /* Case 1: In an IT block, with an IT code: syntax error.
21939 inst
.error
= BAD_SYNTAX
;
21947 if (inst
.cond
< COND_ALWAYS
)
21949 /* Case 4: In a VPT block, with an IT code: syntax error.
21951 inst
.error
= BAD_SYNTAX
;
21954 else if (inst
.cond
== COND_ALWAYS
)
21956 /* Case 6: In a VPT block, with no code: error: missing
21958 inst
.error
= BAD_NOT_VPT
;
21966 case MVE_UNPREDICABLE_INSN
:
21967 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
21969 case INSIDE_IT_INSN
:
21970 if (inst
.cond
> COND_ALWAYS
)
21972 /* Case 11: In an IT block, with a VPT code: syntax error. */
21973 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21974 inst
.error
= BAD_SYNTAX
;
21977 else if (now_pred
.type
== SCALAR_PRED
)
21979 /* Case 10: In an IT block, with an IT code: OK! */
21980 if (cond
!= inst
.cond
)
21982 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
21989 /* Case 13: In a VPT block, with an IT code: error: should be
21991 inst
.error
= BAD_OUT_IT
;
21996 case INSIDE_VPT_INSN
:
21997 if (now_pred
.type
== SCALAR_PRED
)
21999 /* Case 2: In an IT block, with a VPT code: error: must be in a
22001 inst
.error
= BAD_OUT_VPT
;
22004 /* Case 5: In a VPT block, with a VPT code: OK! */
22005 else if (cond
!= inst
.cond
)
22007 inst
.error
= BAD_VPT_COND
;
22011 case INSIDE_IT_LAST_INSN
:
22012 case IF_INSIDE_IT_LAST_INSN
:
22013 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22015 /* Case 4: In a VPT block, with an IT code: syntax error. */
22016 /* Case 11: In an IT block, with a VPT code: syntax error. */
22017 inst
.error
= BAD_SYNTAX
;
22020 else if (cond
!= inst
.cond
)
22022 inst
.error
= BAD_IT_COND
;
22027 inst
.error
= BAD_BRANCH
;
22032 case NEUTRAL_IT_INSN
:
22033 /* The BKPT instruction is unconditional even in a IT or VPT
22038 if (now_pred
.type
== SCALAR_PRED
)
22040 inst
.error
= BAD_IT_IT
;
22043 /* fall through. */
22045 if (inst
.cond
== COND_ALWAYS
)
22047 /* Executing a VPT/VPST instruction inside an IT block or a
22048 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22050 if (now_pred
.type
== SCALAR_PRED
)
22051 as_tsktsk (MVE_NOT_IT
);
22053 as_tsktsk (MVE_NOT_VPT
);
22058 /* VPT/VPST do not accept condition codes. */
22059 inst
.error
= BAD_SYNTAX
;
22070 struct depr_insn_mask
22072 unsigned long pattern
;
22073 unsigned long mask
;
22074 const char* description
;
22077 /* List of 16-bit instruction patterns deprecated in an IT block in
22079 static const struct depr_insn_mask depr_it_insns
[] = {
22080 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22081 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22082 { 0xa000, 0xb800, N_("ADR") },
22083 { 0x4800, 0xf800, N_("Literal loads") },
22084 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22085 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22086 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22087 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22088 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22093 it_fsm_post_encode (void)
22097 if (!now_pred
.state_handled
)
22098 handle_pred_state ();
22100 if (now_pred
.insn_cond
22101 && !now_pred
.warn_deprecated
22102 && warn_on_deprecated
22103 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22104 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22106 if (inst
.instruction
>= 0x10000)
22108 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22109 "performance deprecated in ARMv8-A and ARMv8-R"));
22110 now_pred
.warn_deprecated
= TRUE
;
22114 const struct depr_insn_mask
*p
= depr_it_insns
;
22116 while (p
->mask
!= 0)
22118 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22120 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22121 "instructions of the following class are "
22122 "performance deprecated in ARMv8-A and "
22123 "ARMv8-R: %s"), p
->description
);
22124 now_pred
.warn_deprecated
= TRUE
;
22132 if (now_pred
.block_length
> 1)
22134 as_tsktsk (_("IT blocks containing more than one conditional "
22135 "instruction are performance deprecated in ARMv8-A and "
22137 now_pred
.warn_deprecated
= TRUE
;
22141 is_last
= (now_pred
.mask
== 0x10);
22144 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22150 force_automatic_it_block_close (void)
22152 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22154 close_automatic_it_block ();
22155 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22161 in_pred_block (void)
22163 if (!now_pred
.state_handled
)
22164 handle_pred_state ();
22166 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22169 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22170 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22171 here, hence the "known" in the function name. */
22174 known_t32_only_insn (const struct asm_opcode
*opcode
)
22176 /* Original Thumb-1 wide instruction. */
22177 if (opcode
->tencode
== do_t_blx
22178 || opcode
->tencode
== do_t_branch23
22179 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22180 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22183 /* Wide-only instruction added to ARMv8-M Baseline. */
22184 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22185 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22186 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22187 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22193 /* Whether wide instruction variant can be used if available for a valid OPCODE
22197 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22199 if (known_t32_only_insn (opcode
))
22202 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22203 of variant T3 of B.W is checked in do_t_branch. */
22204 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22205 && opcode
->tencode
== do_t_branch
)
22208 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22209 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22210 && opcode
->tencode
== do_t_mov_cmp
22211 /* Make sure CMP instruction is not affected. */
22212 && opcode
->aencode
== do_mov
)
22215 /* Wide instruction variants of all instructions with narrow *and* wide
22216 variants become available with ARMv6t2. Other opcodes are either
22217 narrow-only or wide-only and are thus available if OPCODE is valid. */
22218 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22221 /* OPCODE with narrow only instruction variant or wide variant not
22227 md_assemble (char *str
)
22230 const struct asm_opcode
* opcode
;
22232 /* Align the previous label if needed. */
22233 if (last_label_seen
!= NULL
)
22235 symbol_set_frag (last_label_seen
, frag_now
);
22236 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22237 S_SET_SEGMENT (last_label_seen
, now_seg
);
22240 memset (&inst
, '\0', sizeof (inst
));
22242 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22243 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22245 opcode
= opcode_lookup (&p
);
22248 /* It wasn't an instruction, but it might be a register alias of
22249 the form alias .req reg, or a Neon .dn/.qn directive. */
22250 if (! create_register_alias (str
, p
)
22251 && ! create_neon_reg_alias (str
, p
))
22252 as_bad (_("bad instruction `%s'"), str
);
22257 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22258 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22260 /* The value which unconditional instructions should have in place of the
22261 condition field. */
22262 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22266 arm_feature_set variant
;
22268 variant
= cpu_variant
;
22269 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22270 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22271 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22272 /* Check that this instruction is supported for this CPU. */
22273 if (!opcode
->tvariant
22274 || (thumb_mode
== 1
22275 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22277 if (opcode
->tencode
== do_t_swi
)
22278 as_bad (_("SVC is not permitted on this architecture"));
22280 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22283 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22284 && opcode
->tencode
!= do_t_branch
)
22286 as_bad (_("Thumb does not support conditional execution"));
22290 /* Two things are addressed here:
22291 1) Implicit require narrow instructions on Thumb-1.
22292 This avoids relaxation accidentally introducing Thumb-2
22294 2) Reject wide instructions in non Thumb-2 cores.
22296 Only instructions with narrow and wide variants need to be handled
22297 but selecting all non wide-only instructions is easier. */
22298 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22299 && !t32_insn_ok (variant
, opcode
))
22301 if (inst
.size_req
== 0)
22303 else if (inst
.size_req
== 4)
22305 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22306 as_bad (_("selected processor does not support 32bit wide "
22307 "variant of instruction `%s'"), str
);
22309 as_bad (_("selected processor does not support `%s' in "
22310 "Thumb-2 mode"), str
);
22315 inst
.instruction
= opcode
->tvalue
;
22317 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22319 /* Prepare the pred_insn_type for those encodings that don't set
22321 it_fsm_pre_encode ();
22323 opcode
->tencode ();
22325 it_fsm_post_encode ();
22328 if (!(inst
.error
|| inst
.relax
))
22330 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22331 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22332 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22334 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22339 /* Something has gone badly wrong if we try to relax a fixed size
22341 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22343 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22344 *opcode
->tvariant
);
22345 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22346 set those bits when Thumb-2 32-bit instructions are seen. The impact
22347 of relaxable instructions will be considered later after we finish all
22349 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22350 variant
= arm_arch_none
;
22352 variant
= cpu_variant
;
22353 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22354 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22357 check_neon_suffixes
;
22361 mapping_state (MAP_THUMB
);
22364 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22368 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22369 is_bx
= (opcode
->aencode
== do_bx
);
22371 /* Check that this instruction is supported for this CPU. */
22372 if (!(is_bx
&& fix_v4bx
)
22373 && !(opcode
->avariant
&&
22374 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22376 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22381 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22385 inst
.instruction
= opcode
->avalue
;
22386 if (opcode
->tag
== OT_unconditionalF
)
22387 inst
.instruction
|= 0xFU
<< 28;
22389 inst
.instruction
|= inst
.cond
<< 28;
22390 inst
.size
= INSN_SIZE
;
22391 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22393 it_fsm_pre_encode ();
22394 opcode
->aencode ();
22395 it_fsm_post_encode ();
22397 /* Arm mode bx is marked as both v4T and v5 because it's still required
22398 on a hypothetical non-thumb v5 core. */
22400 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22402 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22403 *opcode
->avariant
);
22405 check_neon_suffixes
;
22409 mapping_state (MAP_ARM
);
22414 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22422 check_pred_blocks_finished (void)
22427 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22428 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22429 == MANUAL_PRED_BLOCK
)
22431 if (now_pred
.type
== SCALAR_PRED
)
22432 as_warn (_("section '%s' finished with an open IT block."),
22435 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22439 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22441 if (now_pred
.type
== SCALAR_PRED
)
22442 as_warn (_("file finished with an open IT block."));
22444 as_warn (_("file finished with an open VPT/VPST block."));
22449 /* Various frobbings of labels and their addresses. */
22452 arm_start_line_hook (void)
22454 last_label_seen
= NULL
;
22458 arm_frob_label (symbolS
* sym
)
22460 last_label_seen
= sym
;
22462 ARM_SET_THUMB (sym
, thumb_mode
);
22464 #if defined OBJ_COFF || defined OBJ_ELF
22465 ARM_SET_INTERWORK (sym
, support_interwork
);
22468 force_automatic_it_block_close ();
22470 /* Note - do not allow local symbols (.Lxxx) to be labelled
22471 as Thumb functions. This is because these labels, whilst
22472 they exist inside Thumb code, are not the entry points for
22473 possible ARM->Thumb calls. Also, these labels can be used
22474 as part of a computed goto or switch statement. eg gcc
22475 can generate code that looks like this:
22477 ldr r2, [pc, .Laaa]
22487 The first instruction loads the address of the jump table.
22488 The second instruction converts a table index into a byte offset.
22489 The third instruction gets the jump address out of the table.
22490 The fourth instruction performs the jump.
22492 If the address stored at .Laaa is that of a symbol which has the
22493 Thumb_Func bit set, then the linker will arrange for this address
22494 to have the bottom bit set, which in turn would mean that the
22495 address computation performed by the third instruction would end
22496 up with the bottom bit set. Since the ARM is capable of unaligned
22497 word loads, the instruction would then load the incorrect address
22498 out of the jump table, and chaos would ensue. */
22499 if (label_is_thumb_function_name
22500 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22501 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22503 /* When the address of a Thumb function is taken the bottom
22504 bit of that address should be set. This will allow
22505 interworking between Arm and Thumb functions to work
22508 THUMB_SET_FUNC (sym
, 1);
22510 label_is_thumb_function_name
= FALSE
;
22513 dwarf2_emit_label (sym
);
22517 arm_data_in_code (void)
22519 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22521 *input_line_pointer
= '/';
22522 input_line_pointer
+= 5;
22523 *input_line_pointer
= 0;
22531 arm_canonicalize_symbol_name (char * name
)
22535 if (thumb_mode
&& (len
= strlen (name
)) > 5
22536 && streq (name
+ len
- 5, "/data"))
22537 *(name
+ len
- 5) = 0;
22542 /* Table of all register names defined by default. The user can
22543 define additional names with .req. Note that all register names
22544 should appear in both upper and lowercase variants. Some registers
22545 also have mixed-case names. */
22547 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22548 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22549 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22550 #define REGSET(p,t) \
22551 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22552 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22553 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22554 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22555 #define REGSETH(p,t) \
22556 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22557 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22558 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22559 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22560 #define REGSET2(p,t) \
22561 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22562 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22563 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22564 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22565 #define SPLRBANK(base,bank,t) \
22566 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22567 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22568 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22569 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22570 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22571 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22573 static const struct reg_entry reg_names
[] =
22575 /* ARM integer registers. */
22576 REGSET(r
, RN
), REGSET(R
, RN
),
22578 /* ATPCS synonyms. */
22579 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22580 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22581 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22583 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22584 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22585 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22587 /* Well-known aliases. */
22588 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22589 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22591 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22592 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22594 /* Defining the new Zero register from ARMv8.1-M. */
22598 /* Coprocessor numbers. */
22599 REGSET(p
, CP
), REGSET(P
, CP
),
22601 /* Coprocessor register numbers. The "cr" variants are for backward
22603 REGSET(c
, CN
), REGSET(C
, CN
),
22604 REGSET(cr
, CN
), REGSET(CR
, CN
),
22606 /* ARM banked registers. */
22607 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22608 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22609 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22610 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22611 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22612 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22613 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22615 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22616 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22617 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22618 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22619 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22620 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22621 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22622 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22624 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22625 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22626 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22627 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22628 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22629 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22630 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22631 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22632 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22634 /* FPA registers. */
22635 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22636 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22638 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22639 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22641 /* VFP SP registers. */
22642 REGSET(s
,VFS
), REGSET(S
,VFS
),
22643 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22645 /* VFP DP Registers. */
22646 REGSET(d
,VFD
), REGSET(D
,VFD
),
22647 /* Extra Neon DP registers. */
22648 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22650 /* Neon QP registers. */
22651 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22653 /* VFP control registers. */
22654 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22655 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22656 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22657 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22658 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22659 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22660 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22662 /* Maverick DSP coprocessor registers. */
22663 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22664 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22666 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22667 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22668 REGDEF(dspsc
,0,DSPSC
),
22670 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22671 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22672 REGDEF(DSPSC
,0,DSPSC
),
22674 /* iWMMXt data registers - p0, c0-15. */
22675 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22677 /* iWMMXt control registers - p1, c0-3. */
22678 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22679 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22680 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22681 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22683 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22684 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22685 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22686 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22687 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22689 /* XScale accumulator registers. */
22690 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22696 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22697 within psr_required_here. */
22698 static const struct asm_psr psrs
[] =
22700 /* Backward compatibility notation. Note that "all" is no longer
22701 truly all possible PSR bits. */
22702 {"all", PSR_c
| PSR_f
},
22706 /* Individual flags. */
22712 /* Combinations of flags. */
22713 {"fs", PSR_f
| PSR_s
},
22714 {"fx", PSR_f
| PSR_x
},
22715 {"fc", PSR_f
| PSR_c
},
22716 {"sf", PSR_s
| PSR_f
},
22717 {"sx", PSR_s
| PSR_x
},
22718 {"sc", PSR_s
| PSR_c
},
22719 {"xf", PSR_x
| PSR_f
},
22720 {"xs", PSR_x
| PSR_s
},
22721 {"xc", PSR_x
| PSR_c
},
22722 {"cf", PSR_c
| PSR_f
},
22723 {"cs", PSR_c
| PSR_s
},
22724 {"cx", PSR_c
| PSR_x
},
22725 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22726 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22727 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22728 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22729 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22730 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22731 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22732 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22733 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22734 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22735 {"scf", PSR_s
| PSR_c
| PSR_f
},
22736 {"scx", PSR_s
| PSR_c
| PSR_x
},
22737 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22738 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22739 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22740 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22741 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22742 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22743 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22744 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22745 {"csf", PSR_c
| PSR_s
| PSR_f
},
22746 {"csx", PSR_c
| PSR_s
| PSR_x
},
22747 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22748 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22749 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22750 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22751 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22752 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22753 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22754 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22755 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22756 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22757 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22758 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22759 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22760 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22761 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22762 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22763 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22764 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22765 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22766 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22767 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22768 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22769 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22770 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22771 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22772 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22775 /* Table of V7M psr names. */
22776 static const struct asm_psr v7m_psrs
[] =
22778 {"apsr", 0x0 }, {"APSR", 0x0 },
22779 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22780 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22781 {"psr", 0x3 }, {"PSR", 0x3 },
22782 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22783 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22784 {"epsr", 0x6 }, {"EPSR", 0x6 },
22785 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22786 {"msp", 0x8 }, {"MSP", 0x8 },
22787 {"psp", 0x9 }, {"PSP", 0x9 },
22788 {"msplim", 0xa }, {"MSPLIM", 0xa },
22789 {"psplim", 0xb }, {"PSPLIM", 0xb },
22790 {"primask", 0x10}, {"PRIMASK", 0x10},
22791 {"basepri", 0x11}, {"BASEPRI", 0x11},
22792 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22793 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22794 {"control", 0x14}, {"CONTROL", 0x14},
22795 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22796 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22797 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22798 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22799 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22800 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22801 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22802 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22803 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22806 /* Table of all shift-in-operand names. */
22807 static const struct asm_shift_name shift_names
[] =
22809 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22810 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22811 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22812 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22813 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22814 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22815 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22818 /* Table of all explicit relocation names. */
22820 static struct reloc_entry reloc_names
[] =
22822 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22823 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22824 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22825 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22826 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22827 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22828 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22829 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22830 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22831 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22832 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22833 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22834 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22835 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22836 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22837 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22838 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22839 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22840 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22841 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22842 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22843 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22844 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22845 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22846 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22847 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22848 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22852 /* Table of all conditional affixes. */
22853 static const struct asm_cond conds
[] =
22857 {"cs", 0x2}, {"hs", 0x2},
22858 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22871 static const struct asm_cond vconds
[] =
22877 #define UL_BARRIER(L,U,CODE,FEAT) \
22878 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22879 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22881 static struct asm_barrier_opt barrier_opt_names
[] =
22883 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22884 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22885 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22886 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22887 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22888 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22889 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22890 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22891 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22892 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22893 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22894 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22895 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22896 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22897 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22898 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22903 /* Table of ARM-format instructions. */
22905 /* Macros for gluing together operand strings. N.B. In all cases
22906 other than OPS0, the trailing OP_stop comes from default
22907 zero-initialization of the unspecified elements of the array. */
22908 #define OPS0() { OP_stop, }
22909 #define OPS1(a) { OP_##a, }
22910 #define OPS2(a,b) { OP_##a,OP_##b, }
22911 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22912 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22913 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22914 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22916 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22917 This is useful when mixing operands for ARM and THUMB, i.e. using the
22918 MIX_ARM_THUMB_OPERANDS macro.
22919 In order to use these macros, prefix the number of operands with _
22921 #define OPS_1(a) { a, }
22922 #define OPS_2(a,b) { a,b, }
22923 #define OPS_3(a,b,c) { a,b,c, }
22924 #define OPS_4(a,b,c,d) { a,b,c,d, }
22925 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22926 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22928 /* These macros abstract out the exact format of the mnemonic table and
22929 save some repeated characters. */
22931 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22932 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22933 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22934 THUMB_VARIANT, do_##ae, do_##te, 0 }
22936 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22937 a T_MNEM_xyz enumerator. */
22938 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22939 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22940 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22941 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22943 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22944 infix after the third character. */
22945 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22946 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22947 THUMB_VARIANT, do_##ae, do_##te, 0 }
22948 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22949 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22950 THUMB_VARIANT, do_##ae, do_##te, 0 }
22951 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22952 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22953 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22954 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22955 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22956 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22957 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22958 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22960 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22961 field is still 0xE. Many of the Thumb variants can be executed
22962 conditionally, so this is checked separately. */
22963 #define TUE(mnem, op, top, nops, ops, ae, te) \
22964 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22965 THUMB_VARIANT, do_##ae, do_##te, 0 }
22967 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22968 Used by mnemonics that have very minimal differences in the encoding for
22969 ARM and Thumb variants and can be handled in a common function. */
22970 #define TUEc(mnem, op, top, nops, ops, en) \
22971 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22972 THUMB_VARIANT, do_##en, do_##en, 0 }
22974 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22975 condition code field. */
22976 #define TUF(mnem, op, top, nops, ops, ae, te) \
22977 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22978 THUMB_VARIANT, do_##ae, do_##te, 0 }
22980 /* ARM-only variants of all the above. */
22981 #define CE(mnem, op, nops, ops, ae) \
22982 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22984 #define C3(mnem, op, nops, ops, ae) \
22985 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22987 /* Thumb-only variants of TCE and TUE. */
22988 #define ToC(mnem, top, nops, ops, te) \
22989 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22992 #define ToU(mnem, top, nops, ops, te) \
22993 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22996 /* T_MNEM_xyz enumerator variants of ToC. */
22997 #define toC(mnem, top, nops, ops, te) \
22998 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23001 /* T_MNEM_xyz enumerator variants of ToU. */
23002 #define toU(mnem, top, nops, ops, te) \
23003 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23006 /* Legacy mnemonics that always have conditional infix after the third
23008 #define CL(mnem, op, nops, ops, ae) \
23009 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23010 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23012 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23013 #define cCE(mnem, op, nops, ops, ae) \
23014 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23016 /* mov instructions that are shared between coprocessor and MVE. */
23017 #define mcCE(mnem, op, nops, ops, ae) \
23018 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23020 /* Legacy coprocessor instructions where conditional infix and conditional
23021 suffix are ambiguous. For consistency this includes all FPA instructions,
23022 not just the potentially ambiguous ones. */
23023 #define cCL(mnem, op, nops, ops, ae) \
23024 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23025 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23027 /* Coprocessor, takes either a suffix or a position-3 infix
23028 (for an FPA corner case). */
23029 #define C3E(mnem, op, nops, ops, ae) \
23030 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23031 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23033 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23034 { m1 #m2 m3, OPS##nops ops, \
23035 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23036 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23038 #define CM(m1, m2, op, nops, ops, ae) \
23039 xCM_ (m1, , m2, op, nops, ops, ae), \
23040 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23041 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23042 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23043 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23044 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23045 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23046 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23047 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23048 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23049 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23050 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23051 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23052 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23053 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23054 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23055 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23056 xCM_ (m1, le, m2, op, nops, ops, ae), \
23057 xCM_ (m1, al, m2, op, nops, ops, ae)
23059 #define UE(mnem, op, nops, ops, ae) \
23060 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23062 #define UF(mnem, op, nops, ops, ae) \
23063 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23065 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23066 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23067 use the same encoding function for each. */
23068 #define NUF(mnem, op, nops, ops, enc) \
23069 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23070 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23072 /* Neon data processing, version which indirects through neon_enc_tab for
23073 the various overloaded versions of opcodes. */
23074 #define nUF(mnem, op, nops, ops, enc) \
23075 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23076 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23078 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23080 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23081 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23082 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23084 #define NCE(mnem, op, nops, ops, enc) \
23085 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23087 #define NCEF(mnem, op, nops, ops, enc) \
23088 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23090 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23091 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23092 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23093 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23095 #define nCE(mnem, op, nops, ops, enc) \
23096 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23098 #define nCEF(mnem, op, nops, ops, enc) \
23099 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23102 #define mCEF(mnem, op, nops, ops, enc) \
23103 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23104 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23107 /* nCEF but for MVE predicated instructions. */
23108 #define mnCEF(mnem, op, nops, ops, enc) \
23109 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23111 /* nCE but for MVE predicated instructions. */
23112 #define mnCE(mnem, op, nops, ops, enc) \
23113 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23115 /* NUF but for potentially MVE predicated instructions. */
23116 #define MNUF(mnem, op, nops, ops, enc) \
23117 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23118 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23120 /* nUF but for potentially MVE predicated instructions. */
23121 #define mnUF(mnem, op, nops, ops, enc) \
23122 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23123 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23125 /* ToC but for potentially MVE predicated instructions. */
23126 #define mToC(mnem, top, nops, ops, te) \
23127 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23130 /* NCE but for MVE predicated instructions. */
23131 #define MNCE(mnem, op, nops, ops, enc) \
23132 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23134 /* NCEF but for MVE predicated instructions. */
23135 #define MNCEF(mnem, op, nops, ops, enc) \
23136 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23139 static const struct asm_opcode insns
[] =
23141 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23142 #define THUMB_VARIANT & arm_ext_v4t
23143 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23144 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23145 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23146 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23147 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23148 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23149 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23150 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23151 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23152 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23153 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23154 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23155 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23156 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23157 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23158 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23160 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23161 for setting PSR flag bits. They are obsolete in V6 and do not
23162 have Thumb equivalents. */
23163 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23164 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23165 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23166 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23167 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23168 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23169 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23170 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23171 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23173 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23174 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23175 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23176 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23178 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23179 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23180 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23182 OP_ADDRGLDR
),ldst
, t_ldst
),
23183 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23185 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23186 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23187 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23188 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23189 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23190 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23192 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23193 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23196 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23197 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23198 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23199 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23201 /* Thumb-compatibility pseudo ops. */
23202 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23203 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23204 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23205 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23206 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23207 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23208 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23209 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23210 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23211 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23212 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23213 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23215 /* These may simplify to neg. */
23216 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23217 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23219 #undef THUMB_VARIANT
23220 #define THUMB_VARIANT & arm_ext_os
23222 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23223 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23225 #undef THUMB_VARIANT
23226 #define THUMB_VARIANT & arm_ext_v6
23228 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23230 /* V1 instructions with no Thumb analogue prior to V6T2. */
23231 #undef THUMB_VARIANT
23232 #define THUMB_VARIANT & arm_ext_v6t2
23234 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23235 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23236 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23238 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23239 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23240 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23241 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23243 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23244 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23246 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23247 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23249 /* V1 instructions with no Thumb analogue at all. */
23250 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23251 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23253 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23254 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23255 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23256 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23257 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23258 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23259 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23260 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23263 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23264 #undef THUMB_VARIANT
23265 #define THUMB_VARIANT & arm_ext_v4t
23267 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23268 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23270 #undef THUMB_VARIANT
23271 #define THUMB_VARIANT & arm_ext_v6t2
23273 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23274 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23276 /* Generic coprocessor instructions. */
23277 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23278 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23279 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23280 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23281 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23282 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23283 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23286 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23288 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23289 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23292 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23293 #undef THUMB_VARIANT
23294 #define THUMB_VARIANT & arm_ext_msr
23296 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23297 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23300 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23301 #undef THUMB_VARIANT
23302 #define THUMB_VARIANT & arm_ext_v6t2
23304 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23305 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23306 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23307 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23308 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23309 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23310 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23311 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23314 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23315 #undef THUMB_VARIANT
23316 #define THUMB_VARIANT & arm_ext_v4t
23318 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23319 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23320 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23321 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23322 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23323 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23326 #define ARM_VARIANT & arm_ext_v4t_5
23328 /* ARM Architecture 4T. */
23329 /* Note: bx (and blx) are required on V5, even if the processor does
23330 not support Thumb. */
23331 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23334 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23335 #undef THUMB_VARIANT
23336 #define THUMB_VARIANT & arm_ext_v5t
23338 /* Note: blx has 2 variants; the .value coded here is for
23339 BLX(2). Only this variant has conditional execution. */
23340 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23341 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23343 #undef THUMB_VARIANT
23344 #define THUMB_VARIANT & arm_ext_v6t2
23346 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23347 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23348 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23349 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23350 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23351 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23352 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23353 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23356 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23357 #undef THUMB_VARIANT
23358 #define THUMB_VARIANT & arm_ext_v5exp
23360 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23361 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23362 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23363 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23365 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23366 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23368 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23369 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23370 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23371 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23373 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23374 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23375 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23376 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23378 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23379 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23381 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23382 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23383 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23384 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23387 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23388 #undef THUMB_VARIANT
23389 #define THUMB_VARIANT & arm_ext_v6t2
23391 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23392 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23394 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23395 ADDRGLDRS
), ldrd
, t_ldstd
),
23397 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23398 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23401 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23403 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23406 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23407 #undef THUMB_VARIANT
23408 #define THUMB_VARIANT & arm_ext_v6
23410 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23411 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23412 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23413 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23414 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23415 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23416 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23417 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23418 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23419 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23421 #undef THUMB_VARIANT
23422 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23424 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23425 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23427 #undef THUMB_VARIANT
23428 #define THUMB_VARIANT & arm_ext_v6t2
23430 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23431 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23433 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23434 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23436 /* ARM V6 not included in V7M. */
23437 #undef THUMB_VARIANT
23438 #define THUMB_VARIANT & arm_ext_v6_notm
23439 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23440 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23441 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23442 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23443 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23444 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23445 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23446 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23447 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23448 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23449 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23450 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23451 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23452 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23453 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23454 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23455 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23456 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23457 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23459 /* ARM V6 not included in V7M (eg. integer SIMD). */
23460 #undef THUMB_VARIANT
23461 #define THUMB_VARIANT & arm_ext_v6_dsp
23462 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23463 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23464 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23465 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23466 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23467 /* Old name for QASX. */
23468 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23469 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23470 /* Old name for QSAX. */
23471 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23472 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23473 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23474 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23475 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23476 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23477 /* Old name for SASX. */
23478 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23479 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23480 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23481 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23482 /* Old name for SHASX. */
23483 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23484 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23485 /* Old name for SHSAX. */
23486 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23487 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23488 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23489 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23490 /* Old name for SSAX. */
23491 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23492 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23493 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23494 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23495 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23496 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23497 /* Old name for UASX. */
23498 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23499 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23500 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23501 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23502 /* Old name for UHASX. */
23503 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23504 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23505 /* Old name for UHSAX. */
23506 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23507 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23508 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23509 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23510 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23511 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23512 /* Old name for UQASX. */
23513 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23514 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23515 /* Old name for UQSAX. */
23516 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23517 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23518 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23519 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23520 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23521 /* Old name for USAX. */
23522 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23523 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23524 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23525 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23526 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23527 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23528 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23529 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23530 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23531 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23532 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23533 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23534 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23535 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23536 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23537 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23538 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23539 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23540 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23541 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23542 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23543 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23544 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23545 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23546 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23547 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23548 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23549 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23550 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23551 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23552 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23553 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23554 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23555 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23558 #define ARM_VARIANT & arm_ext_v6k_v6t2
23559 #undef THUMB_VARIANT
23560 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23562 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23563 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23564 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23565 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23567 #undef THUMB_VARIANT
23568 #define THUMB_VARIANT & arm_ext_v6_notm
23569 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23571 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23572 RRnpcb
), strexd
, t_strexd
),
23574 #undef THUMB_VARIANT
23575 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23576 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23578 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23580 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23582 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23584 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23587 #define ARM_VARIANT & arm_ext_sec
23588 #undef THUMB_VARIANT
23589 #define THUMB_VARIANT & arm_ext_sec
23591 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23594 #define ARM_VARIANT & arm_ext_virt
23595 #undef THUMB_VARIANT
23596 #define THUMB_VARIANT & arm_ext_virt
23598 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23599 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23602 #define ARM_VARIANT & arm_ext_pan
23603 #undef THUMB_VARIANT
23604 #define THUMB_VARIANT & arm_ext_pan
23606 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23609 #define ARM_VARIANT & arm_ext_v6t2
23610 #undef THUMB_VARIANT
23611 #define THUMB_VARIANT & arm_ext_v6t2
23613 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23614 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23615 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23616 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23618 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23619 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23621 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23622 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23623 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23624 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23627 #define ARM_VARIANT & arm_ext_v3
23628 #undef THUMB_VARIANT
23629 #define THUMB_VARIANT & arm_ext_v6t2
23631 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23632 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23633 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23636 #define ARM_VARIANT & arm_ext_v6t2
23637 #undef THUMB_VARIANT
23638 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23639 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23640 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23642 /* Thumb-only instructions. */
23644 #define ARM_VARIANT NULL
23645 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23646 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23648 /* ARM does not really have an IT instruction, so always allow it.
23649 The opcode is copied from Thumb in order to allow warnings in
23650 -mimplicit-it=[never | arm] modes. */
23652 #define ARM_VARIANT & arm_ext_v1
23653 #undef THUMB_VARIANT
23654 #define THUMB_VARIANT & arm_ext_v6t2
23656 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23657 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23658 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23659 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23660 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23661 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23662 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23663 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23664 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23665 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23666 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23667 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23668 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23669 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23670 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23671 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23672 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23673 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23675 /* Thumb2 only instructions. */
23677 #define ARM_VARIANT NULL
23679 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23680 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23681 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23682 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23683 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23684 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23686 /* Hardware division instructions. */
23688 #define ARM_VARIANT & arm_ext_adiv
23689 #undef THUMB_VARIANT
23690 #define THUMB_VARIANT & arm_ext_div
23692 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23693 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23695 /* ARM V6M/V7 instructions. */
23697 #define ARM_VARIANT & arm_ext_barrier
23698 #undef THUMB_VARIANT
23699 #define THUMB_VARIANT & arm_ext_barrier
23701 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23702 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23703 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23705 /* ARM V7 instructions. */
23707 #define ARM_VARIANT & arm_ext_v7
23708 #undef THUMB_VARIANT
23709 #define THUMB_VARIANT & arm_ext_v7
23711 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23712 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23715 #define ARM_VARIANT & arm_ext_mp
23716 #undef THUMB_VARIANT
23717 #define THUMB_VARIANT & arm_ext_mp
23719 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23721 /* AArchv8 instructions. */
23723 #define ARM_VARIANT & arm_ext_v8
23725 /* Instructions shared between armv8-a and armv8-m. */
23726 #undef THUMB_VARIANT
23727 #define THUMB_VARIANT & arm_ext_atomics
23729 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23730 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23731 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23732 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23733 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23734 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23735 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23736 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23737 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23738 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23740 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23742 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23744 #undef THUMB_VARIANT
23745 #define THUMB_VARIANT & arm_ext_v8
23747 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23748 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23750 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23753 /* Defined in V8 but is in undefined encoding space for earlier
23754 architectures. However earlier architectures are required to treat
23755 this instuction as a semihosting trap as well. Hence while not explicitly
23756 defined as such, it is in fact correct to define the instruction for all
23758 #undef THUMB_VARIANT
23759 #define THUMB_VARIANT & arm_ext_v1
23761 #define ARM_VARIANT & arm_ext_v1
23762 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23764 /* ARMv8 T32 only. */
23766 #define ARM_VARIANT NULL
23767 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23768 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23769 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23771 /* FP for ARMv8. */
23773 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23774 #undef THUMB_VARIANT
23775 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23777 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23778 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23779 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23780 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23781 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23782 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23783 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23784 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23785 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23786 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23787 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23789 /* Crypto v1 extensions. */
23791 #define ARM_VARIANT & fpu_crypto_ext_armv8
23792 #undef THUMB_VARIANT
23793 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23795 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23796 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23797 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23798 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23799 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23800 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23801 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23802 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23803 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23804 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23805 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23806 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23807 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23808 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23811 #define ARM_VARIANT & crc_ext_armv8
23812 #undef THUMB_VARIANT
23813 #define THUMB_VARIANT & crc_ext_armv8
23814 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23815 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23816 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23817 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23818 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23819 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23821 /* ARMv8.2 RAS extension. */
23823 #define ARM_VARIANT & arm_ext_ras
23824 #undef THUMB_VARIANT
23825 #define THUMB_VARIANT & arm_ext_ras
23826 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23829 #define ARM_VARIANT & arm_ext_v8_3
23830 #undef THUMB_VARIANT
23831 #define THUMB_VARIANT & arm_ext_v8_3
23832 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23835 #define ARM_VARIANT & fpu_neon_ext_dotprod
23836 #undef THUMB_VARIANT
23837 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23838 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23839 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23842 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23843 #undef THUMB_VARIANT
23844 #define THUMB_VARIANT NULL
23846 cCE("wfs", e200110
, 1, (RR
), rd
),
23847 cCE("rfs", e300110
, 1, (RR
), rd
),
23848 cCE("wfc", e400110
, 1, (RR
), rd
),
23849 cCE("rfc", e500110
, 1, (RR
), rd
),
23851 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23852 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23853 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23854 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23856 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23857 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23858 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23859 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23861 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23862 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23863 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23864 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23865 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23866 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23867 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23868 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23869 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23870 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23871 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23872 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23874 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23875 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23876 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23877 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23878 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23879 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23880 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23881 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23882 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23883 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23884 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23885 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23887 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23888 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23889 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23890 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23891 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23892 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23893 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23894 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23895 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23896 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23897 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23898 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23900 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23901 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23902 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23903 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23904 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23905 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23906 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23907 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23908 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23909 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23910 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23911 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23913 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23914 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23915 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23916 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23917 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23918 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23919 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23920 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23921 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23922 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23923 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23924 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23926 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23927 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23928 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23929 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23930 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23931 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23932 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23933 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23934 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23935 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23936 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23937 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23939 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23940 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23941 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23942 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23943 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23944 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23945 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23946 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23947 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23948 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23949 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
23950 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
23952 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
23953 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
23954 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
23955 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
23956 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
23957 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
23958 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
23959 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
23960 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
23961 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
23962 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
23963 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
23965 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
23966 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
23967 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
23968 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
23969 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
23970 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
23971 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
23972 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
23973 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
23974 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
23975 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
23976 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
23978 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
23979 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
23980 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
23981 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
23982 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
23983 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
23984 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
23985 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
23986 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
23987 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
23988 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
23989 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
23991 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
23992 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
23993 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
23994 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
23995 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
23996 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
23997 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
23998 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
23999 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24000 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24001 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24002 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24004 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24005 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24006 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24007 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24008 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24009 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24010 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24011 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24012 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24013 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24014 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24015 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24017 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24018 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24019 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24020 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24021 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24022 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24023 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24024 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24025 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24026 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24027 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24028 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24030 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24031 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24032 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24033 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24034 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24035 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24036 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24037 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24038 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24039 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24040 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24041 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24043 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24044 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24045 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24046 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24047 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24048 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24049 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24050 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24051 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24052 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24053 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24054 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24056 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24057 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24058 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24059 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24060 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24061 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24062 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24063 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24064 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24065 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24066 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24067 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24069 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24070 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24071 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24072 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24073 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24074 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24075 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24076 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24077 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24078 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24079 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24080 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24082 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24083 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24084 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24085 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24086 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24087 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24088 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24089 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24090 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24091 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24092 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24093 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24095 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24096 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24097 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24098 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24099 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24100 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24101 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24102 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24103 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24104 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24105 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24106 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24108 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24109 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24110 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24111 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24112 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24113 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24114 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24115 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24116 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24117 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24118 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24119 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24121 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24122 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24123 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24124 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24125 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24126 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24127 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24128 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24129 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24130 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24131 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24132 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24134 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24135 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24136 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24137 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24138 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24139 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24140 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24141 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24142 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24143 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24144 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24145 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24147 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24148 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24149 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24150 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24151 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24152 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24153 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24154 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24155 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24156 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24157 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24158 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24160 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24161 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24162 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24163 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24164 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24165 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24166 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24167 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24168 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24169 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24170 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24171 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24173 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24174 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24175 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24176 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24177 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24178 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24179 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24180 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24181 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24182 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24183 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24184 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24186 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24187 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24188 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24189 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24190 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24191 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24192 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24193 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24194 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24195 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24196 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24197 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24199 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24200 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24201 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24202 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24203 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24204 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24205 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24206 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24207 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24208 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24209 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24210 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24212 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24213 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24214 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24215 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24216 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24217 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24218 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24219 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24220 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24221 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24222 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24223 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24225 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24226 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24227 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24228 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24229 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24230 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24231 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24232 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24233 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24234 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24235 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24236 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24238 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24239 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24240 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24241 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24243 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24244 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24245 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24246 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24247 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24248 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24249 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24250 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24251 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24252 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24253 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24254 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24256 /* The implementation of the FIX instruction is broken on some
24257 assemblers, in that it accepts a precision specifier as well as a
24258 rounding specifier, despite the fact that this is meaningless.
24259 To be more compatible, we accept it as well, though of course it
24260 does not set any bits. */
24261 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24262 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24263 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24264 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24265 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24266 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24267 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24268 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24269 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24270 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24271 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24272 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24273 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24275 /* Instructions that were new with the real FPA, call them V2. */
24277 #define ARM_VARIANT & fpu_fpa_ext_v2
24279 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24280 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24281 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24282 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24283 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24284 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24287 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24289 /* Moves and type conversions. */
24290 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24291 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24292 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24293 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24294 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24295 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24296 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24297 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24298 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24299 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24300 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24302 /* Memory operations. */
24303 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24304 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24305 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24306 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24307 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24308 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24309 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24310 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24311 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24312 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24313 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24314 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24315 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24316 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24317 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24318 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24319 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24320 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24322 /* Monadic operations. */
24323 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24324 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24325 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24327 /* Dyadic operations. */
24328 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24329 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24330 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24331 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24332 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24333 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24334 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24335 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24336 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24339 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24340 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24341 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24342 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24344 /* Double precision load/store are still present on single precision
24345 implementations. */
24346 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24347 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24348 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24349 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24350 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24351 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24352 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24353 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24354 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24355 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24358 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24360 /* Moves and type conversions. */
24361 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24362 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24363 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24364 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24365 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24366 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24367 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24368 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24369 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24370 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24371 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24372 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24374 /* Monadic operations. */
24375 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24376 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24377 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24379 /* Dyadic operations. */
24380 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24381 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24382 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24383 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24384 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24385 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24386 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24387 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24388 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24391 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24392 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24393 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24394 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24396 /* Instructions which may belong to either the Neon or VFP instruction sets.
24397 Individual encoder functions perform additional architecture checks. */
24399 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24400 #undef THUMB_VARIANT
24401 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24403 /* These mnemonics are unique to VFP. */
24404 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24405 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24406 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24407 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24408 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24409 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24410 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24411 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24413 /* Mnemonics shared by Neon and VFP. */
24414 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24416 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24417 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24418 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24419 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24420 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24421 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24423 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24424 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24425 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24426 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24429 /* NOTE: All VMOV encoding is special-cased! */
24430 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24432 #undef THUMB_VARIANT
24433 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24434 by different feature bits. Since we are setting the Thumb guard, we can
24435 require Thumb-1 which makes it a nop guard and set the right feature bit in
24436 do_vldr_vstr (). */
24437 #define THUMB_VARIANT & arm_ext_v4t
24438 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24439 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24442 #define ARM_VARIANT & arm_ext_fp16
24443 #undef THUMB_VARIANT
24444 #define THUMB_VARIANT & arm_ext_fp16
24445 /* New instructions added from v8.2, allowing the extraction and insertion of
24446 the upper 16 bits of a 32-bit vector register. */
24447 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24448 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24450 /* New backported fma/fms instructions optional in v8.2. */
24451 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24452 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24454 #undef THUMB_VARIANT
24455 #define THUMB_VARIANT & fpu_neon_ext_v1
24457 #define ARM_VARIANT & fpu_neon_ext_v1
24459 /* Data processing with three registers of the same length. */
24460 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24461 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24462 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24463 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24464 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24465 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24466 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24467 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24468 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24469 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24470 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24471 /* If not immediate, fall back to neon_dyadic_i64_su.
24472 shl should accept I8 I16 I32 I64,
24473 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24474 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24475 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24476 /* Logic ops, types optional & ignored. */
24477 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24478 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24479 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24480 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24481 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24482 /* Bitfield ops, untyped. */
24483 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24484 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24485 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24486 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24487 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24488 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24489 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24490 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24491 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24492 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24493 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24494 back to neon_dyadic_if_su. */
24495 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24496 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24497 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24498 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24499 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24500 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24501 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24502 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24503 /* Comparison. Type I8 I16 I32 F32. */
24504 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24505 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24506 /* As above, D registers only. */
24507 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24508 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24509 /* Int and float variants, signedness unimportant. */
24510 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24511 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24512 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24513 /* Add/sub take types I8 I16 I32 I64 F32. */
24514 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24515 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24516 /* vtst takes sizes 8, 16, 32. */
24517 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24518 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24519 /* VMUL takes I8 I16 I32 F32 P8. */
24520 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24521 /* VQD{R}MULH takes S16 S32. */
24522 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24523 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24524 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24525 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24526 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24527 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24528 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24529 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24530 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24531 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24532 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24533 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24534 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24535 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24536 /* ARM v8.1 extension. */
24537 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24538 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24539 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24541 /* Two address, int/float. Types S8 S16 S32 F32. */
24542 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24543 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24545 /* Data processing with two registers and a shift amount. */
24546 /* Right shifts, and variants with rounding.
24547 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24548 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24549 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24550 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24551 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24552 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24553 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24554 /* Shift and insert. Sizes accepted 8 16 32 64. */
24555 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24556 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24557 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24558 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24559 /* Right shift immediate, saturating & narrowing, with rounding variants.
24560 Types accepted S16 S32 S64 U16 U32 U64. */
24561 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24562 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24563 /* As above, unsigned. Types accepted S16 S32 S64. */
24564 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24565 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24566 /* Right shift narrowing. Types accepted I16 I32 I64. */
24567 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24568 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24569 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24570 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24571 /* CVT with optional immediate for fixed-point variant. */
24572 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24574 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24576 /* Data processing, three registers of different lengths. */
24577 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24578 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24579 /* If not scalar, fall back to neon_dyadic_long.
24580 Vector types as above, scalar types S16 S32 U16 U32. */
24581 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24582 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24583 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24584 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24585 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24586 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24587 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24588 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24589 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24590 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24591 /* Saturating doubling multiplies. Types S16 S32. */
24592 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24593 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24594 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24595 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24596 S16 S32 U16 U32. */
24597 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24599 /* Extract. Size 8. */
24600 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24601 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24603 /* Two registers, miscellaneous. */
24604 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24605 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24606 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24607 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24608 /* Vector replicate. Sizes 8 16 32. */
24609 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24610 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24611 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24612 /* VMOVN. Types I16 I32 I64. */
24613 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24614 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24615 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24616 /* VQMOVUN. Types S16 S32 S64. */
24617 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24618 /* VZIP / VUZP. Sizes 8 16 32. */
24619 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24620 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24621 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24622 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24623 /* VQABS / VQNEG. Types S8 S16 S32. */
24624 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24625 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24626 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24627 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24628 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24629 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24630 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24631 /* Reciprocal estimates. Types U32 F16 F32. */
24632 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24633 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24634 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24635 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24636 /* VCLS. Types S8 S16 S32. */
24637 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24638 /* VCLZ. Types I8 I16 I32. */
24639 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24640 /* VCNT. Size 8. */
24641 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24642 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24643 /* Two address, untyped. */
24644 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24645 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24646 /* VTRN. Sizes 8 16 32. */
24647 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24648 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24650 /* Table lookup. Size 8. */
24651 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24652 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24654 #undef THUMB_VARIANT
24655 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24657 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24659 /* Neon element/structure load/store. */
24660 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24661 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24662 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24663 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24664 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24665 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24666 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24667 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24669 #undef THUMB_VARIANT
24670 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24672 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24673 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24674 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24675 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24676 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24677 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24678 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24679 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24680 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24681 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24683 #undef THUMB_VARIANT
24684 #define THUMB_VARIANT & fpu_vfp_ext_v3
24686 #define ARM_VARIANT & fpu_vfp_ext_v3
24688 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24689 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24690 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24691 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24692 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24693 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24694 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24695 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24696 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24699 #define ARM_VARIANT & fpu_vfp_ext_fma
24700 #undef THUMB_VARIANT
24701 #define THUMB_VARIANT & fpu_vfp_ext_fma
24702 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24703 VFP FMA variant; NEON and VFP FMA always includes the NEON
24704 FMA instructions. */
24705 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24706 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24708 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24709 the v form should always be used. */
24710 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24711 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24712 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24713 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24714 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24715 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24717 #undef THUMB_VARIANT
24719 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24721 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24722 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24723 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24724 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24725 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24726 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24727 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24728 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24731 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24733 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24734 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24735 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24736 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24737 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24738 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24739 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24740 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24741 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24742 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24743 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24744 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24745 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24746 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24747 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24748 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24749 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24750 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24751 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24752 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24753 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24754 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24755 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24756 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24757 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24758 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24759 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24760 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24761 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24762 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24763 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24764 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24765 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24766 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24767 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24768 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24769 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24770 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24771 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24772 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24773 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24774 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24775 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24776 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24777 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24778 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24779 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24780 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24781 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24782 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24783 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24784 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24785 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24786 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24787 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24788 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24789 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24790 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24791 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24792 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24793 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24794 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24795 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24796 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24797 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24798 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24799 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24800 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24801 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24802 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24803 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24804 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24805 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24806 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24807 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24808 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24809 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24810 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24811 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24812 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24813 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24814 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24815 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24816 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24817 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24818 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24819 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24820 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24821 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24822 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24823 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24824 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24825 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24826 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24827 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24828 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24829 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24830 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24831 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24832 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24833 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24834 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24835 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24836 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24837 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24838 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24839 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24840 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24841 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24842 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24843 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24844 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24845 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24846 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24847 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24848 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24849 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24850 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24851 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24852 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24853 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24854 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24855 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24856 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24857 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24858 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24859 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24860 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24861 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24862 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24863 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24864 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24865 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24866 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24867 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24868 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24869 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24870 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24871 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24872 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24873 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24874 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24875 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24876 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24877 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24878 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24879 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24880 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24881 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24882 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24883 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24884 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24885 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24886 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24887 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24888 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24889 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24890 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24891 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24892 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24893 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24894 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24897 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24899 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24900 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24901 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24902 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24903 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24904 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24905 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24906 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24907 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24908 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24909 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24910 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24911 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24912 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24913 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24914 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24915 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24916 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24917 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24918 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24919 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24920 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24921 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24922 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24923 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24924 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24925 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24926 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24927 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24928 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24929 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24930 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24931 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24932 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24933 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24934 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24935 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24936 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24937 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24938 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24939 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24940 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24941 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24942 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24943 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24944 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24945 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24946 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24947 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24948 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24949 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24950 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24951 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24952 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24953 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24954 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24955 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24958 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24960 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24961 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24962 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24963 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24964 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24965 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24966 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24967 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24968 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
24969 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
24970 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
24971 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
24972 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
24973 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
24974 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
24975 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
24976 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
24977 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
24978 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
24979 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
24980 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
24981 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
24982 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
24983 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
24984 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
24985 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
24986 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
24987 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
24988 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
24989 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
24990 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
24991 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
24992 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
24993 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
24994 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
24995 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
24996 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
24997 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
24998 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
24999 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25000 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25001 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25002 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25003 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25004 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25005 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25006 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25007 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25008 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25009 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25010 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25011 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25012 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25013 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25014 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25015 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25016 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25017 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25018 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25019 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25020 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25021 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25022 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25023 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25024 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25025 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25026 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25027 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25028 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25029 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25030 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25031 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25032 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25033 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25034 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25035 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25037 /* ARMv8.5-A instructions. */
25039 #define ARM_VARIANT & arm_ext_sb
25040 #undef THUMB_VARIANT
25041 #define THUMB_VARIANT & arm_ext_sb
25042 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25045 #define ARM_VARIANT & arm_ext_predres
25046 #undef THUMB_VARIANT
25047 #define THUMB_VARIANT & arm_ext_predres
25048 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25049 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25050 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25052 /* ARMv8-M instructions. */
25054 #define ARM_VARIANT NULL
25055 #undef THUMB_VARIANT
25056 #define THUMB_VARIANT & arm_ext_v8m
25057 ToU("sg", e97fe97f
, 0, (), noargs
),
25058 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25059 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25060 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25061 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25062 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25063 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25065 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25066 instructions behave as nop if no VFP is present. */
25067 #undef THUMB_VARIANT
25068 #define THUMB_VARIANT & arm_ext_v8m_main
25069 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25070 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25072 /* Armv8.1-M Mainline instructions. */
25073 #undef THUMB_VARIANT
25074 #define THUMB_VARIANT & arm_ext_v8_1m_main
25075 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25076 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25077 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25078 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25079 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25081 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25082 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25083 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25085 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25086 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25088 #undef THUMB_VARIANT
25089 #define THUMB_VARIANT & mve_ext
25091 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25092 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25093 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25094 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25095 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25096 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25097 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25098 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25099 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25100 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25101 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25102 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25103 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25104 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25105 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25107 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25108 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25109 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25110 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25111 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25112 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25113 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25114 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25115 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25116 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25117 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25118 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25119 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25120 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25121 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25123 /* MVE and MVE FP only. */
25124 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25125 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25126 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25127 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25128 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25129 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25130 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25131 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25132 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25133 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25134 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25135 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25136 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25137 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25138 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25139 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25140 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25142 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25143 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25144 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25145 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25146 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25147 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25148 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25149 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25150 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25151 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25152 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25153 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25154 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25155 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25156 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25157 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25158 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25159 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25160 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25161 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25163 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25164 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25165 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25166 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25167 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25168 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25169 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25170 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25171 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25172 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25173 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25174 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25175 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25176 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25177 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25178 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25179 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25181 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25182 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25183 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25184 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25185 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25186 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25187 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25188 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25189 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25190 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25191 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25192 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25193 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25194 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25195 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25196 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25197 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25198 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25199 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25200 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25202 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25203 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25204 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25205 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25206 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25208 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25209 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25210 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25211 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25212 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25213 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25214 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25215 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25216 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25217 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25218 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25219 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25220 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25221 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25222 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25223 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25224 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25226 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25227 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25228 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25229 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25230 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25231 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25232 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25233 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25234 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25235 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25236 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25237 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25239 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25240 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25241 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25243 #undef THUMB_VARIANT
25244 #define THUMB_VARIANT & mve_fp_ext
25245 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25246 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25247 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25248 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25249 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25250 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25251 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25252 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25255 #define ARM_VARIANT & fpu_vfp_ext_v1
25256 #undef THUMB_VARIANT
25257 #define THUMB_VARIANT & arm_ext_v6t2
25258 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25259 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25261 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25264 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25266 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25267 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25268 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25269 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25271 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25272 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25273 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25275 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25276 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25278 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25279 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25281 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25282 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25285 #define ARM_VARIANT & fpu_vfp_ext_v2
25287 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25288 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25289 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25290 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25293 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25294 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25295 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25296 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25297 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25298 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25299 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25302 #define ARM_VARIANT & fpu_neon_ext_v1
25303 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25304 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25305 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25306 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25307 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25308 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25309 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25310 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25311 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25312 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25313 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25314 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25315 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25316 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25317 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25318 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25319 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25320 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25321 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25322 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25323 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25324 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25325 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25326 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25327 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25328 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25329 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25330 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25331 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25332 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25333 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25334 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25335 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25336 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25337 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25338 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25339 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25342 #define ARM_VARIANT & arm_ext_v8_3
25343 #undef THUMB_VARIANT
25344 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25345 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25346 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25349 #undef THUMB_VARIANT
25381 /* MD interface: bits in the object file. */
25383 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25384 for use in the a.out file, and stores them in the array pointed to by buf.
25385 This knows about the endian-ness of the target machine and does
25386 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25387 2 (short) and 4 (long) Floating numbers are put out as a series of
25388 LITTLENUMS (shorts, here at least). */
25391 md_number_to_chars (char * buf
, valueT val
, int n
)
25393 if (target_big_endian
)
25394 number_to_chars_bigendian (buf
, val
, n
);
25396 number_to_chars_littleendian (buf
, val
, n
);
25400 md_chars_to_number (char * buf
, int n
)
25403 unsigned char * where
= (unsigned char *) buf
;
25405 if (target_big_endian
)
25410 result
|= (*where
++ & 255);
25418 result
|= (where
[n
] & 255);
25425 /* MD interface: Sections. */
25427 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25428 that an rs_machine_dependent frag may reach. */
25431 arm_frag_max_var (fragS
*fragp
)
25433 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25434 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25436 Note that we generate relaxable instructions even for cases that don't
25437 really need it, like an immediate that's a trivial constant. So we're
25438 overestimating the instruction size for some of those cases. Rather
25439 than putting more intelligence here, it would probably be better to
25440 avoid generating a relaxation frag in the first place when it can be
25441 determined up front that a short instruction will suffice. */
25443 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25447 /* Estimate the size of a frag before relaxing. Assume everything fits in
25451 md_estimate_size_before_relax (fragS
* fragp
,
25452 segT segtype ATTRIBUTE_UNUSED
)
25458 /* Convert a machine dependent frag. */
25461 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25463 unsigned long insn
;
25464 unsigned long old_op
;
25472 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25474 old_op
= bfd_get_16(abfd
, buf
);
25475 if (fragp
->fr_symbol
)
25477 exp
.X_op
= O_symbol
;
25478 exp
.X_add_symbol
= fragp
->fr_symbol
;
25482 exp
.X_op
= O_constant
;
25484 exp
.X_add_number
= fragp
->fr_offset
;
25485 opcode
= fragp
->fr_subtype
;
25488 case T_MNEM_ldr_pc
:
25489 case T_MNEM_ldr_pc2
:
25490 case T_MNEM_ldr_sp
:
25491 case T_MNEM_str_sp
:
25498 if (fragp
->fr_var
== 4)
25500 insn
= THUMB_OP32 (opcode
);
25501 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25503 insn
|= (old_op
& 0x700) << 4;
25507 insn
|= (old_op
& 7) << 12;
25508 insn
|= (old_op
& 0x38) << 13;
25510 insn
|= 0x00000c00;
25511 put_thumb32_insn (buf
, insn
);
25512 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25516 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25518 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25521 if (fragp
->fr_var
== 4)
25523 insn
= THUMB_OP32 (opcode
);
25524 insn
|= (old_op
& 0xf0) << 4;
25525 put_thumb32_insn (buf
, insn
);
25526 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25530 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25531 exp
.X_add_number
-= 4;
25539 if (fragp
->fr_var
== 4)
25541 int r0off
= (opcode
== T_MNEM_mov
25542 || opcode
== T_MNEM_movs
) ? 0 : 8;
25543 insn
= THUMB_OP32 (opcode
);
25544 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25545 insn
|= (old_op
& 0x700) << r0off
;
25546 put_thumb32_insn (buf
, insn
);
25547 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25551 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25556 if (fragp
->fr_var
== 4)
25558 insn
= THUMB_OP32(opcode
);
25559 put_thumb32_insn (buf
, insn
);
25560 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25563 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25567 if (fragp
->fr_var
== 4)
25569 insn
= THUMB_OP32(opcode
);
25570 insn
|= (old_op
& 0xf00) << 14;
25571 put_thumb32_insn (buf
, insn
);
25572 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25575 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25578 case T_MNEM_add_sp
:
25579 case T_MNEM_add_pc
:
25580 case T_MNEM_inc_sp
:
25581 case T_MNEM_dec_sp
:
25582 if (fragp
->fr_var
== 4)
25584 /* ??? Choose between add and addw. */
25585 insn
= THUMB_OP32 (opcode
);
25586 insn
|= (old_op
& 0xf0) << 4;
25587 put_thumb32_insn (buf
, insn
);
25588 if (opcode
== T_MNEM_add_pc
)
25589 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25591 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25594 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25602 if (fragp
->fr_var
== 4)
25604 insn
= THUMB_OP32 (opcode
);
25605 insn
|= (old_op
& 0xf0) << 4;
25606 insn
|= (old_op
& 0xf) << 16;
25607 put_thumb32_insn (buf
, insn
);
25608 if (insn
& (1 << 20))
25609 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25611 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25614 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25620 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25621 (enum bfd_reloc_code_real
) reloc_type
);
25622 fixp
->fx_file
= fragp
->fr_file
;
25623 fixp
->fx_line
= fragp
->fr_line
;
25624 fragp
->fr_fix
+= fragp
->fr_var
;
25626 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25627 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25628 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25629 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25632 /* Return the size of a relaxable immediate operand instruction.
25633 SHIFT and SIZE specify the form of the allowable immediate. */
25635 relax_immediate (fragS
*fragp
, int size
, int shift
)
25641 /* ??? Should be able to do better than this. */
25642 if (fragp
->fr_symbol
)
25645 low
= (1 << shift
) - 1;
25646 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25647 offset
= fragp
->fr_offset
;
25648 /* Force misaligned offsets to 32-bit variant. */
25651 if (offset
& ~mask
)
25656 /* Get the address of a symbol during relaxation. */
25658 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25664 sym
= fragp
->fr_symbol
;
25665 sym_frag
= symbol_get_frag (sym
);
25666 know (S_GET_SEGMENT (sym
) != absolute_section
25667 || sym_frag
== &zero_address_frag
);
25668 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25670 /* If frag has yet to be reached on this pass, assume it will
25671 move by STRETCH just as we did. If this is not so, it will
25672 be because some frag between grows, and that will force
25676 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25680 /* Adjust stretch for any alignment frag. Note that if have
25681 been expanding the earlier code, the symbol may be
25682 defined in what appears to be an earlier frag. FIXME:
25683 This doesn't handle the fr_subtype field, which specifies
25684 a maximum number of bytes to skip when doing an
25686 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25688 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25691 stretch
= - ((- stretch
)
25692 & ~ ((1 << (int) f
->fr_offset
) - 1));
25694 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25706 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25709 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25714 /* Assume worst case for symbols not known to be in the same section. */
25715 if (fragp
->fr_symbol
== NULL
25716 || !S_IS_DEFINED (fragp
->fr_symbol
)
25717 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25718 || S_IS_WEAK (fragp
->fr_symbol
))
25721 val
= relaxed_symbol_addr (fragp
, stretch
);
25722 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25723 addr
= (addr
+ 4) & ~3;
25724 /* Force misaligned targets to 32-bit variant. */
25728 if (val
< 0 || val
> 1020)
25733 /* Return the size of a relaxable add/sub immediate instruction. */
25735 relax_addsub (fragS
*fragp
, asection
*sec
)
25740 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25741 op
= bfd_get_16(sec
->owner
, buf
);
25742 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25743 return relax_immediate (fragp
, 8, 0);
25745 return relax_immediate (fragp
, 3, 0);
25748 /* Return TRUE iff the definition of symbol S could be pre-empted
25749 (overridden) at link or load time. */
25751 symbol_preemptible (symbolS
*s
)
25753 /* Weak symbols can always be pre-empted. */
25757 /* Non-global symbols cannot be pre-empted. */
25758 if (! S_IS_EXTERNAL (s
))
25762 /* In ELF, a global symbol can be marked protected, or private. In that
25763 case it can't be pre-empted (other definitions in the same link unit
25764 would violate the ODR). */
25765 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25769 /* Other global symbols might be pre-empted. */
25773 /* Return the size of a relaxable branch instruction. BITS is the
25774 size of the offset field in the narrow instruction. */
25777 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25783 /* Assume worst case for symbols not known to be in the same section. */
25784 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25785 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25786 || S_IS_WEAK (fragp
->fr_symbol
))
25790 /* A branch to a function in ARM state will require interworking. */
25791 if (S_IS_DEFINED (fragp
->fr_symbol
)
25792 && ARM_IS_FUNC (fragp
->fr_symbol
))
25796 if (symbol_preemptible (fragp
->fr_symbol
))
25799 val
= relaxed_symbol_addr (fragp
, stretch
);
25800 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25803 /* Offset is a signed value *2 */
25805 if (val
>= limit
|| val
< -limit
)
25811 /* Relax a machine dependent frag. This returns the amount by which
25812 the current size of the frag should change. */
25815 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25820 oldsize
= fragp
->fr_var
;
25821 switch (fragp
->fr_subtype
)
25823 case T_MNEM_ldr_pc2
:
25824 newsize
= relax_adr (fragp
, sec
, stretch
);
25826 case T_MNEM_ldr_pc
:
25827 case T_MNEM_ldr_sp
:
25828 case T_MNEM_str_sp
:
25829 newsize
= relax_immediate (fragp
, 8, 2);
25833 newsize
= relax_immediate (fragp
, 5, 2);
25837 newsize
= relax_immediate (fragp
, 5, 1);
25841 newsize
= relax_immediate (fragp
, 5, 0);
25844 newsize
= relax_adr (fragp
, sec
, stretch
);
25850 newsize
= relax_immediate (fragp
, 8, 0);
25853 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25856 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25858 case T_MNEM_add_sp
:
25859 case T_MNEM_add_pc
:
25860 newsize
= relax_immediate (fragp
, 8, 2);
25862 case T_MNEM_inc_sp
:
25863 case T_MNEM_dec_sp
:
25864 newsize
= relax_immediate (fragp
, 7, 2);
25870 newsize
= relax_addsub (fragp
, sec
);
25876 fragp
->fr_var
= newsize
;
25877 /* Freeze wide instructions that are at or before the same location as
25878 in the previous pass. This avoids infinite loops.
25879 Don't freeze them unconditionally because targets may be artificially
25880 misaligned by the expansion of preceding frags. */
25881 if (stretch
<= 0 && newsize
> 2)
25883 md_convert_frag (sec
->owner
, sec
, fragp
);
25887 return newsize
- oldsize
;
25890 /* Round up a section size to the appropriate boundary. */
25893 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25899 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25900 of an rs_align_code fragment. */
25903 arm_handle_align (fragS
* fragP
)
25905 static unsigned char const arm_noop
[2][2][4] =
25908 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25909 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25912 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25913 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25916 static unsigned char const thumb_noop
[2][2][2] =
25919 {0xc0, 0x46}, /* LE */
25920 {0x46, 0xc0}, /* BE */
25923 {0x00, 0xbf}, /* LE */
25924 {0xbf, 0x00} /* BE */
25927 static unsigned char const wide_thumb_noop
[2][4] =
25928 { /* Wide Thumb-2 */
25929 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25930 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25933 unsigned bytes
, fix
, noop_size
;
25935 const unsigned char * noop
;
25936 const unsigned char *narrow_noop
= NULL
;
25941 if (fragP
->fr_type
!= rs_align_code
)
25944 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
25945 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
25948 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25949 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
25951 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
25953 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
25955 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25956 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
25958 narrow_noop
= thumb_noop
[1][target_big_endian
];
25959 noop
= wide_thumb_noop
[target_big_endian
];
25962 noop
= thumb_noop
[0][target_big_endian
];
25970 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25971 ? selected_cpu
: arm_arch_none
,
25973 [target_big_endian
];
25980 fragP
->fr_var
= noop_size
;
25982 if (bytes
& (noop_size
- 1))
25984 fix
= bytes
& (noop_size
- 1);
25986 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
25988 memset (p
, 0, fix
);
25995 if (bytes
& noop_size
)
25997 /* Insert a narrow noop. */
25998 memcpy (p
, narrow_noop
, noop_size
);
26000 bytes
-= noop_size
;
26004 /* Use wide noops for the remainder */
26008 while (bytes
>= noop_size
)
26010 memcpy (p
, noop
, noop_size
);
26012 bytes
-= noop_size
;
26016 fragP
->fr_fix
+= fix
;
26019 /* Called from md_do_align. Used to create an alignment
26020 frag in a code section. */
26023 arm_frag_align_code (int n
, int max
)
26027 /* We assume that there will never be a requirement
26028 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26029 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26034 _("alignments greater than %d bytes not supported in .text sections."),
26035 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26036 as_fatal ("%s", err_msg
);
26039 p
= frag_var (rs_align_code
,
26040 MAX_MEM_FOR_RS_ALIGN_CODE
,
26042 (relax_substateT
) max
,
26049 /* Perform target specific initialisation of a frag.
26050 Note - despite the name this initialisation is not done when the frag
26051 is created, but only when its type is assigned. A frag can be created
26052 and used a long time before its type is set, so beware of assuming that
26053 this initialisation is performed first. */
26057 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26059 /* Record whether this frag is in an ARM or a THUMB area. */
26060 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26063 #else /* OBJ_ELF is defined. */
26065 arm_init_frag (fragS
* fragP
, int max_chars
)
26067 bfd_boolean frag_thumb_mode
;
26069 /* If the current ARM vs THUMB mode has not already
26070 been recorded into this frag then do so now. */
26071 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26072 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26074 /* PR 21809: Do not set a mapping state for debug sections
26075 - it just confuses other tools. */
26076 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26079 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26081 /* Record a mapping symbol for alignment frags. We will delete this
26082 later if the alignment ends up empty. */
26083 switch (fragP
->fr_type
)
26086 case rs_align_test
:
26088 mapping_state_2 (MAP_DATA
, max_chars
);
26090 case rs_align_code
:
26091 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26098 /* When we change sections we need to issue a new mapping symbol. */
26101 arm_elf_change_section (void)
26103 /* Link an unlinked unwind index table section to the .text section. */
26104 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26105 && elf_linked_to_section (now_seg
) == NULL
)
26106 elf_linked_to_section (now_seg
) = text_section
;
26110 arm_elf_section_type (const char * str
, size_t len
)
26112 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26113 return SHT_ARM_EXIDX
;
26118 /* Code to deal with unwinding tables. */
26120 static void add_unwind_adjustsp (offsetT
);
26122 /* Generate any deferred unwind frame offset. */
26125 flush_pending_unwind (void)
26129 offset
= unwind
.pending_offset
;
26130 unwind
.pending_offset
= 0;
26132 add_unwind_adjustsp (offset
);
26135 /* Add an opcode to this list for this function. Two-byte opcodes should
26136 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26140 add_unwind_opcode (valueT op
, int length
)
26142 /* Add any deferred stack adjustment. */
26143 if (unwind
.pending_offset
)
26144 flush_pending_unwind ();
26146 unwind
.sp_restored
= 0;
26148 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26150 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26151 if (unwind
.opcodes
)
26152 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26153 unwind
.opcode_alloc
);
26155 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26160 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26162 unwind
.opcode_count
++;
26166 /* Add unwind opcodes to adjust the stack pointer. */
26169 add_unwind_adjustsp (offsetT offset
)
26173 if (offset
> 0x200)
26175 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26180 /* Long form: 0xb2, uleb128. */
26181 /* This might not fit in a word so add the individual bytes,
26182 remembering the list is built in reverse order. */
26183 o
= (valueT
) ((offset
- 0x204) >> 2);
26185 add_unwind_opcode (0, 1);
26187 /* Calculate the uleb128 encoding of the offset. */
26191 bytes
[n
] = o
& 0x7f;
26197 /* Add the insn. */
26199 add_unwind_opcode (bytes
[n
- 1], 1);
26200 add_unwind_opcode (0xb2, 1);
26202 else if (offset
> 0x100)
26204 /* Two short opcodes. */
26205 add_unwind_opcode (0x3f, 1);
26206 op
= (offset
- 0x104) >> 2;
26207 add_unwind_opcode (op
, 1);
26209 else if (offset
> 0)
26211 /* Short opcode. */
26212 op
= (offset
- 4) >> 2;
26213 add_unwind_opcode (op
, 1);
26215 else if (offset
< 0)
26218 while (offset
> 0x100)
26220 add_unwind_opcode (0x7f, 1);
26223 op
= ((offset
- 4) >> 2) | 0x40;
26224 add_unwind_opcode (op
, 1);
26228 /* Finish the list of unwind opcodes for this function. */
26231 finish_unwind_opcodes (void)
26235 if (unwind
.fp_used
)
26237 /* Adjust sp as necessary. */
26238 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26239 flush_pending_unwind ();
26241 /* After restoring sp from the frame pointer. */
26242 op
= 0x90 | unwind
.fp_reg
;
26243 add_unwind_opcode (op
, 1);
26246 flush_pending_unwind ();
26250 /* Start an exception table entry. If idx is nonzero this is an index table
26254 start_unwind_section (const segT text_seg
, int idx
)
26256 const char * text_name
;
26257 const char * prefix
;
26258 const char * prefix_once
;
26259 const char * group_name
;
26267 prefix
= ELF_STRING_ARM_unwind
;
26268 prefix_once
= ELF_STRING_ARM_unwind_once
;
26269 type
= SHT_ARM_EXIDX
;
26273 prefix
= ELF_STRING_ARM_unwind_info
;
26274 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26275 type
= SHT_PROGBITS
;
26278 text_name
= segment_name (text_seg
);
26279 if (streq (text_name
, ".text"))
26282 if (strncmp (text_name
, ".gnu.linkonce.t.",
26283 strlen (".gnu.linkonce.t.")) == 0)
26285 prefix
= prefix_once
;
26286 text_name
+= strlen (".gnu.linkonce.t.");
26289 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26295 /* Handle COMDAT group. */
26296 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26298 group_name
= elf_group_name (text_seg
);
26299 if (group_name
== NULL
)
26301 as_bad (_("Group section `%s' has no group signature"),
26302 segment_name (text_seg
));
26303 ignore_rest_of_line ();
26306 flags
|= SHF_GROUP
;
26310 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26313 /* Set the section link for index tables. */
26315 elf_linked_to_section (now_seg
) = text_seg
;
26319 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26320 personality routine data. Returns zero, or the index table value for
26321 an inline entry. */
26324 create_unwind_entry (int have_data
)
26329 /* The current word of data. */
26331 /* The number of bytes left in this word. */
26334 finish_unwind_opcodes ();
26336 /* Remember the current text section. */
26337 unwind
.saved_seg
= now_seg
;
26338 unwind
.saved_subseg
= now_subseg
;
26340 start_unwind_section (now_seg
, 0);
26342 if (unwind
.personality_routine
== NULL
)
26344 if (unwind
.personality_index
== -2)
26347 as_bad (_("handlerdata in cantunwind frame"));
26348 return 1; /* EXIDX_CANTUNWIND. */
26351 /* Use a default personality routine if none is specified. */
26352 if (unwind
.personality_index
== -1)
26354 if (unwind
.opcode_count
> 3)
26355 unwind
.personality_index
= 1;
26357 unwind
.personality_index
= 0;
26360 /* Space for the personality routine entry. */
26361 if (unwind
.personality_index
== 0)
26363 if (unwind
.opcode_count
> 3)
26364 as_bad (_("too many unwind opcodes for personality routine 0"));
26368 /* All the data is inline in the index table. */
26371 while (unwind
.opcode_count
> 0)
26373 unwind
.opcode_count
--;
26374 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26378 /* Pad with "finish" opcodes. */
26380 data
= (data
<< 8) | 0xb0;
26387 /* We get two opcodes "free" in the first word. */
26388 size
= unwind
.opcode_count
- 2;
26392 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26393 if (unwind
.personality_index
!= -1)
26395 as_bad (_("attempt to recreate an unwind entry"));
26399 /* An extra byte is required for the opcode count. */
26400 size
= unwind
.opcode_count
+ 1;
26403 size
= (size
+ 3) >> 2;
26405 as_bad (_("too many unwind opcodes"));
26407 frag_align (2, 0, 0);
26408 record_alignment (now_seg
, 2);
26409 unwind
.table_entry
= expr_build_dot ();
26411 /* Allocate the table entry. */
26412 ptr
= frag_more ((size
<< 2) + 4);
26413 /* PR 13449: Zero the table entries in case some of them are not used. */
26414 memset (ptr
, 0, (size
<< 2) + 4);
26415 where
= frag_now_fix () - ((size
<< 2) + 4);
26417 switch (unwind
.personality_index
)
26420 /* ??? Should this be a PLT generating relocation? */
26421 /* Custom personality routine. */
26422 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26423 BFD_RELOC_ARM_PREL31
);
26428 /* Set the first byte to the number of additional words. */
26429 data
= size
> 0 ? size
- 1 : 0;
26433 /* ABI defined personality routines. */
26435 /* Three opcodes bytes are packed into the first word. */
26442 /* The size and first two opcode bytes go in the first word. */
26443 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26448 /* Should never happen. */
26452 /* Pack the opcodes into words (MSB first), reversing the list at the same
26454 while (unwind
.opcode_count
> 0)
26458 md_number_to_chars (ptr
, data
, 4);
26463 unwind
.opcode_count
--;
26465 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26468 /* Finish off the last word. */
26471 /* Pad with "finish" opcodes. */
26473 data
= (data
<< 8) | 0xb0;
26475 md_number_to_chars (ptr
, data
, 4);
26480 /* Add an empty descriptor if there is no user-specified data. */
26481 ptr
= frag_more (4);
26482 md_number_to_chars (ptr
, 0, 4);
26489 /* Initialize the DWARF-2 unwind information for this procedure. */
26492 tc_arm_frame_initial_instructions (void)
26494 cfi_add_CFA_def_cfa (REG_SP
, 0);
26496 #endif /* OBJ_ELF */
26498 /* Convert REGNAME to a DWARF-2 register number. */
26501 tc_arm_regname_to_dw2regnum (char *regname
)
26503 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26507 /* PR 16694: Allow VFP registers as well. */
26508 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26512 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26521 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26525 exp
.X_op
= O_secrel
;
26526 exp
.X_add_symbol
= symbol
;
26527 exp
.X_add_number
= 0;
26528 emit_expr (&exp
, size
);
26532 /* MD interface: Symbol and relocation handling. */
26534 /* Return the address within the segment that a PC-relative fixup is
26535 relative to. For ARM, PC-relative fixups applied to instructions
26536 are generally relative to the location of the fixup plus 8 bytes.
26537 Thumb branches are offset by 4, and Thumb loads relative to PC
26538 require special handling. */
26541 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26543 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26545 /* If this is pc-relative and we are going to emit a relocation
26546 then we just want to put out any pipeline compensation that the linker
26547 will need. Otherwise we want to use the calculated base.
26548 For WinCE we skip the bias for externals as well, since this
26549 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26551 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26552 || (arm_force_relocation (fixP
)
26554 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26560 switch (fixP
->fx_r_type
)
26562 /* PC relative addressing on the Thumb is slightly odd as the
26563 bottom two bits of the PC are forced to zero for the
26564 calculation. This happens *after* application of the
26565 pipeline offset. However, Thumb adrl already adjusts for
26566 this, so we need not do it again. */
26567 case BFD_RELOC_ARM_THUMB_ADD
:
26570 case BFD_RELOC_ARM_THUMB_OFFSET
:
26571 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26572 case BFD_RELOC_ARM_T32_ADD_PC12
:
26573 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26574 return (base
+ 4) & ~3;
26576 /* Thumb branches are simply offset by +4. */
26577 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26578 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26579 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26580 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26581 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26582 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26583 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26584 case BFD_RELOC_ARM_THUMB_BF17
:
26585 case BFD_RELOC_ARM_THUMB_BF19
:
26586 case BFD_RELOC_ARM_THUMB_BF13
:
26587 case BFD_RELOC_ARM_THUMB_LOOP12
:
26590 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26592 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26593 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26594 && ARM_IS_FUNC (fixP
->fx_addsy
)
26595 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26596 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26599 /* BLX is like branches above, but forces the low two bits of PC to
26601 case BFD_RELOC_THUMB_PCREL_BLX
:
26603 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26604 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26605 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26606 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26607 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26608 return (base
+ 4) & ~3;
26610 /* ARM mode branches are offset by +8. However, the Windows CE
26611 loader expects the relocation not to take this into account. */
26612 case BFD_RELOC_ARM_PCREL_BLX
:
26614 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26615 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26616 && ARM_IS_FUNC (fixP
->fx_addsy
)
26617 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26618 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26621 case BFD_RELOC_ARM_PCREL_CALL
:
26623 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26624 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26625 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26626 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26627 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26630 case BFD_RELOC_ARM_PCREL_BRANCH
:
26631 case BFD_RELOC_ARM_PCREL_JUMP
:
26632 case BFD_RELOC_ARM_PLT32
:
26634 /* When handling fixups immediately, because we have already
26635 discovered the value of a symbol, or the address of the frag involved
26636 we must account for the offset by +8, as the OS loader will never see the reloc.
26637 see fixup_segment() in write.c
26638 The S_IS_EXTERNAL test handles the case of global symbols.
26639 Those need the calculated base, not just the pipe compensation the linker will need. */
26641 && fixP
->fx_addsy
!= NULL
26642 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26643 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26651 /* ARM mode loads relative to PC are also offset by +8. Unlike
26652 branches, the Windows CE loader *does* expect the relocation
26653 to take this into account. */
26654 case BFD_RELOC_ARM_OFFSET_IMM
:
26655 case BFD_RELOC_ARM_OFFSET_IMM8
:
26656 case BFD_RELOC_ARM_HWLITERAL
:
26657 case BFD_RELOC_ARM_LITERAL
:
26658 case BFD_RELOC_ARM_CP_OFF_IMM
:
26662 /* Other PC-relative relocations are un-offset. */
26668 static bfd_boolean flag_warn_syms
= TRUE
;
26671 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26673 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26674 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26675 does mean that the resulting code might be very confusing to the reader.
26676 Also this warning can be triggered if the user omits an operand before
26677 an immediate address, eg:
26681 GAS treats this as an assignment of the value of the symbol foo to a
26682 symbol LDR, and so (without this code) it will not issue any kind of
26683 warning or error message.
26685 Note - ARM instructions are case-insensitive but the strings in the hash
26686 table are all stored in lower case, so we must first ensure that name is
26688 if (flag_warn_syms
&& arm_ops_hsh
)
26690 char * nbuf
= strdup (name
);
26693 for (p
= nbuf
; *p
; p
++)
26695 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26697 static struct hash_control
* already_warned
= NULL
;
26699 if (already_warned
== NULL
)
26700 already_warned
= hash_new ();
26701 /* Only warn about the symbol once. To keep the code
26702 simple we let hash_insert do the lookup for us. */
26703 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26704 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26713 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26714 Otherwise we have no need to default values of symbols. */
26717 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26720 if (name
[0] == '_' && name
[1] == 'G'
26721 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26725 if (symbol_find (name
))
26726 as_bad (_("GOT already in the symbol table"));
26728 GOT_symbol
= symbol_new (name
, undefined_section
,
26729 (valueT
) 0, & zero_address_frag
);
26739 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26740 computed as two separate immediate values, added together. We
26741 already know that this value cannot be computed by just one ARM
26744 static unsigned int
26745 validate_immediate_twopart (unsigned int val
,
26746 unsigned int * highpart
)
26751 for (i
= 0; i
< 32; i
+= 2)
26752 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26758 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26760 else if (a
& 0xff0000)
26762 if (a
& 0xff000000)
26764 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26768 gas_assert (a
& 0xff000000);
26769 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26772 return (a
& 0xff) | (i
<< 7);
26779 validate_offset_imm (unsigned int val
, int hwse
)
26781 if ((hwse
&& val
> 255) || val
> 4095)
26786 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26787 negative immediate constant by altering the instruction. A bit of
26792 by inverting the second operand, and
26795 by negating the second operand. */
26798 negate_data_op (unsigned long * instruction
,
26799 unsigned long value
)
26802 unsigned long negated
, inverted
;
26804 negated
= encode_arm_immediate (-value
);
26805 inverted
= encode_arm_immediate (~value
);
26807 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26810 /* First negates. */
26811 case OPCODE_SUB
: /* ADD <-> SUB */
26812 new_inst
= OPCODE_ADD
;
26817 new_inst
= OPCODE_SUB
;
26821 case OPCODE_CMP
: /* CMP <-> CMN */
26822 new_inst
= OPCODE_CMN
;
26827 new_inst
= OPCODE_CMP
;
26831 /* Now Inverted ops. */
26832 case OPCODE_MOV
: /* MOV <-> MVN */
26833 new_inst
= OPCODE_MVN
;
26838 new_inst
= OPCODE_MOV
;
26842 case OPCODE_AND
: /* AND <-> BIC */
26843 new_inst
= OPCODE_BIC
;
26848 new_inst
= OPCODE_AND
;
26852 case OPCODE_ADC
: /* ADC <-> SBC */
26853 new_inst
= OPCODE_SBC
;
26858 new_inst
= OPCODE_ADC
;
26862 /* We cannot do anything. */
26867 if (value
== (unsigned) FAIL
)
26870 *instruction
&= OPCODE_MASK
;
26871 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26875 /* Like negate_data_op, but for Thumb-2. */
26877 static unsigned int
26878 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26882 unsigned int negated
, inverted
;
26884 negated
= encode_thumb32_immediate (-value
);
26885 inverted
= encode_thumb32_immediate (~value
);
26887 rd
= (*instruction
>> 8) & 0xf;
26888 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26891 /* ADD <-> SUB. Includes CMP <-> CMN. */
26892 case T2_OPCODE_SUB
:
26893 new_inst
= T2_OPCODE_ADD
;
26897 case T2_OPCODE_ADD
:
26898 new_inst
= T2_OPCODE_SUB
;
26902 /* ORR <-> ORN. Includes MOV <-> MVN. */
26903 case T2_OPCODE_ORR
:
26904 new_inst
= T2_OPCODE_ORN
;
26908 case T2_OPCODE_ORN
:
26909 new_inst
= T2_OPCODE_ORR
;
26913 /* AND <-> BIC. TST has no inverted equivalent. */
26914 case T2_OPCODE_AND
:
26915 new_inst
= T2_OPCODE_BIC
;
26922 case T2_OPCODE_BIC
:
26923 new_inst
= T2_OPCODE_AND
;
26928 case T2_OPCODE_ADC
:
26929 new_inst
= T2_OPCODE_SBC
;
26933 case T2_OPCODE_SBC
:
26934 new_inst
= T2_OPCODE_ADC
;
26938 /* We cannot do anything. */
26943 if (value
== (unsigned int)FAIL
)
26946 *instruction
&= T2_OPCODE_MASK
;
26947 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
26951 /* Read a 32-bit thumb instruction from buf. */
26953 static unsigned long
26954 get_thumb32_insn (char * buf
)
26956 unsigned long insn
;
26957 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
26958 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26963 /* We usually want to set the low bit on the address of thumb function
26964 symbols. In particular .word foo - . should have the low bit set.
26965 Generic code tries to fold the difference of two symbols to
26966 a constant. Prevent this and force a relocation when the first symbols
26967 is a thumb function. */
26970 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
26972 if (op
== O_subtract
26973 && l
->X_op
== O_symbol
26974 && r
->X_op
== O_symbol
26975 && THUMB_IS_FUNC (l
->X_add_symbol
))
26977 l
->X_op
= O_subtract
;
26978 l
->X_op_symbol
= r
->X_add_symbol
;
26979 l
->X_add_number
-= r
->X_add_number
;
26983 /* Process as normal. */
26987 /* Encode Thumb2 unconditional branches and calls. The encoding
26988 for the 2 are identical for the immediate values. */
26991 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
26993 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26996 addressT S
, I1
, I2
, lo
, hi
;
26998 S
= (value
>> 24) & 0x01;
26999 I1
= (value
>> 23) & 0x01;
27000 I2
= (value
>> 22) & 0x01;
27001 hi
= (value
>> 12) & 0x3ff;
27002 lo
= (value
>> 1) & 0x7ff;
27003 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27004 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27005 newval
|= (S
<< 10) | hi
;
27006 newval2
&= ~T2I1I2MASK
;
27007 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27008 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27009 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27013 md_apply_fix (fixS
* fixP
,
27017 offsetT value
= * valP
;
27019 unsigned int newimm
;
27020 unsigned long temp
;
27022 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27024 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27026 /* Note whether this will delete the relocation. */
27028 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27031 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27032 consistency with the behaviour on 32-bit hosts. Remember value
27034 value
&= 0xffffffff;
27035 value
^= 0x80000000;
27036 value
-= 0x80000000;
27039 fixP
->fx_addnumber
= value
;
27041 /* Same treatment for fixP->fx_offset. */
27042 fixP
->fx_offset
&= 0xffffffff;
27043 fixP
->fx_offset
^= 0x80000000;
27044 fixP
->fx_offset
-= 0x80000000;
27046 switch (fixP
->fx_r_type
)
27048 case BFD_RELOC_NONE
:
27049 /* This will need to go in the object file. */
27053 case BFD_RELOC_ARM_IMMEDIATE
:
27054 /* We claim that this fixup has been processed here,
27055 even if in fact we generate an error because we do
27056 not have a reloc for it, so tc_gen_reloc will reject it. */
27059 if (fixP
->fx_addsy
)
27061 const char *msg
= 0;
27063 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27064 msg
= _("undefined symbol %s used as an immediate value");
27065 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27066 msg
= _("symbol %s is in a different section");
27067 else if (S_IS_WEAK (fixP
->fx_addsy
))
27068 msg
= _("symbol %s is weak and may be overridden later");
27072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27073 msg
, S_GET_NAME (fixP
->fx_addsy
));
27078 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27080 /* If the offset is negative, we should use encoding A2 for ADR. */
27081 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27082 newimm
= negate_data_op (&temp
, value
);
27085 newimm
= encode_arm_immediate (value
);
27087 /* If the instruction will fail, see if we can fix things up by
27088 changing the opcode. */
27089 if (newimm
== (unsigned int) FAIL
)
27090 newimm
= negate_data_op (&temp
, value
);
27091 /* MOV accepts both ARM modified immediate (A1 encoding) and
27092 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27093 When disassembling, MOV is preferred when there is no encoding
27095 if (newimm
== (unsigned int) FAIL
27096 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27097 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27098 && !((temp
>> SBIT_SHIFT
) & 0x1)
27099 && value
>= 0 && value
<= 0xffff)
27101 /* Clear bits[23:20] to change encoding from A1 to A2. */
27102 temp
&= 0xff0fffff;
27103 /* Encoding high 4bits imm. Code below will encode the remaining
27105 temp
|= (value
& 0x0000f000) << 4;
27106 newimm
= value
& 0x00000fff;
27110 if (newimm
== (unsigned int) FAIL
)
27112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27113 _("invalid constant (%lx) after fixup"),
27114 (unsigned long) value
);
27118 newimm
|= (temp
& 0xfffff000);
27119 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27122 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27124 unsigned int highpart
= 0;
27125 unsigned int newinsn
= 0xe1a00000; /* nop. */
27127 if (fixP
->fx_addsy
)
27129 const char *msg
= 0;
27131 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27132 msg
= _("undefined symbol %s used as an immediate value");
27133 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27134 msg
= _("symbol %s is in a different section");
27135 else if (S_IS_WEAK (fixP
->fx_addsy
))
27136 msg
= _("symbol %s is weak and may be overridden later");
27140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27141 msg
, S_GET_NAME (fixP
->fx_addsy
));
27146 newimm
= encode_arm_immediate (value
);
27147 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27149 /* If the instruction will fail, see if we can fix things up by
27150 changing the opcode. */
27151 if (newimm
== (unsigned int) FAIL
27152 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27154 /* No ? OK - try using two ADD instructions to generate
27156 newimm
= validate_immediate_twopart (value
, & highpart
);
27158 /* Yes - then make sure that the second instruction is
27160 if (newimm
!= (unsigned int) FAIL
)
27162 /* Still No ? Try using a negated value. */
27163 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27164 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27165 /* Otherwise - give up. */
27168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27169 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27174 /* Replace the first operand in the 2nd instruction (which
27175 is the PC) with the destination register. We have
27176 already added in the PC in the first instruction and we
27177 do not want to do it again. */
27178 newinsn
&= ~ 0xf0000;
27179 newinsn
|= ((newinsn
& 0x0f000) << 4);
27182 newimm
|= (temp
& 0xfffff000);
27183 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27185 highpart
|= (newinsn
& 0xfffff000);
27186 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27190 case BFD_RELOC_ARM_OFFSET_IMM
:
27191 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27193 /* Fall through. */
27195 case BFD_RELOC_ARM_LITERAL
:
27201 if (validate_offset_imm (value
, 0) == FAIL
)
27203 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27205 _("invalid literal constant: pool needs to be closer"));
27207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27208 _("bad immediate value for offset (%ld)"),
27213 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27215 newval
&= 0xfffff000;
27218 newval
&= 0xff7ff000;
27219 newval
|= value
| (sign
? INDEX_UP
: 0);
27221 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27224 case BFD_RELOC_ARM_OFFSET_IMM8
:
27225 case BFD_RELOC_ARM_HWLITERAL
:
27231 if (validate_offset_imm (value
, 1) == FAIL
)
27233 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27235 _("invalid literal constant: pool needs to be closer"));
27237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27238 _("bad immediate value for 8-bit offset (%ld)"),
27243 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27245 newval
&= 0xfffff0f0;
27248 newval
&= 0xff7ff0f0;
27249 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27251 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27254 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27255 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27257 _("bad immediate value for offset (%ld)"), (long) value
);
27260 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27262 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27265 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27266 /* This is a complicated relocation used for all varieties of Thumb32
27267 load/store instruction with immediate offset:
27269 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27270 *4, optional writeback(W)
27271 (doubleword load/store)
27273 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27274 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27275 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27276 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27277 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27279 Uppercase letters indicate bits that are already encoded at
27280 this point. Lowercase letters are our problem. For the
27281 second block of instructions, the secondary opcode nybble
27282 (bits 8..11) is present, and bit 23 is zero, even if this is
27283 a PC-relative operation. */
27284 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27286 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27288 if ((newval
& 0xf0000000) == 0xe0000000)
27290 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27292 newval
|= (1 << 23);
27295 if (value
% 4 != 0)
27297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27298 _("offset not a multiple of 4"));
27304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27305 _("offset out of range"));
27310 else if ((newval
& 0x000f0000) == 0x000f0000)
27312 /* PC-relative, 12-bit offset. */
27314 newval
|= (1 << 23);
27319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27320 _("offset out of range"));
27325 else if ((newval
& 0x00000100) == 0x00000100)
27327 /* Writeback: 8-bit, +/- offset. */
27329 newval
|= (1 << 9);
27334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27335 _("offset out of range"));
27340 else if ((newval
& 0x00000f00) == 0x00000e00)
27342 /* T-instruction: positive 8-bit offset. */
27343 if (value
< 0 || value
> 0xff)
27345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27346 _("offset out of range"));
27354 /* Positive 12-bit or negative 8-bit offset. */
27358 newval
|= (1 << 23);
27368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27369 _("offset out of range"));
27376 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27377 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27380 case BFD_RELOC_ARM_SHIFT_IMM
:
27381 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27382 if (((unsigned long) value
) > 32
27384 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27387 _("shift expression is too large"));
27392 /* Shifts of zero must be done as lsl. */
27394 else if (value
== 32)
27396 newval
&= 0xfffff07f;
27397 newval
|= (value
& 0x1f) << 7;
27398 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27401 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27402 case BFD_RELOC_ARM_T32_ADD_IMM
:
27403 case BFD_RELOC_ARM_T32_IMM12
:
27404 case BFD_RELOC_ARM_T32_ADD_PC12
:
27405 /* We claim that this fixup has been processed here,
27406 even if in fact we generate an error because we do
27407 not have a reloc for it, so tc_gen_reloc will reject it. */
27411 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27414 _("undefined symbol %s used as an immediate value"),
27415 S_GET_NAME (fixP
->fx_addsy
));
27419 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27421 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27424 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27425 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27426 Thumb2 modified immediate encoding (T2). */
27427 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27428 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27430 newimm
= encode_thumb32_immediate (value
);
27431 if (newimm
== (unsigned int) FAIL
)
27432 newimm
= thumb32_negate_data_op (&newval
, value
);
27434 if (newimm
== (unsigned int) FAIL
)
27436 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27438 /* Turn add/sum into addw/subw. */
27439 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27440 newval
= (newval
& 0xfeffffff) | 0x02000000;
27441 /* No flat 12-bit imm encoding for addsw/subsw. */
27442 if ((newval
& 0x00100000) == 0)
27444 /* 12 bit immediate for addw/subw. */
27448 newval
^= 0x00a00000;
27451 newimm
= (unsigned int) FAIL
;
27458 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27459 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27460 disassembling, MOV is preferred when there is no encoding
27462 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27463 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27464 but with the Rn field [19:16] set to 1111. */
27465 && (((newval
>> 16) & 0xf) == 0xf)
27466 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27467 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27468 && value
>= 0 && value
<= 0xffff)
27470 /* Toggle bit[25] to change encoding from T2 to T3. */
27472 /* Clear bits[19:16]. */
27473 newval
&= 0xfff0ffff;
27474 /* Encoding high 4bits imm. Code below will encode the
27475 remaining low 12bits. */
27476 newval
|= (value
& 0x0000f000) << 4;
27477 newimm
= value
& 0x00000fff;
27482 if (newimm
== (unsigned int)FAIL
)
27484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27485 _("invalid constant (%lx) after fixup"),
27486 (unsigned long) value
);
27490 newval
|= (newimm
& 0x800) << 15;
27491 newval
|= (newimm
& 0x700) << 4;
27492 newval
|= (newimm
& 0x0ff);
27494 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27495 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27498 case BFD_RELOC_ARM_SMC
:
27499 if (((unsigned long) value
) > 0xffff)
27500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27501 _("invalid smc expression"));
27502 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27503 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27504 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27507 case BFD_RELOC_ARM_HVC
:
27508 if (((unsigned long) value
) > 0xffff)
27509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27510 _("invalid hvc expression"));
27511 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27512 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27513 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27516 case BFD_RELOC_ARM_SWI
:
27517 if (fixP
->tc_fix_data
!= 0)
27519 if (((unsigned long) value
) > 0xff)
27520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27521 _("invalid swi expression"));
27522 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27524 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27528 if (((unsigned long) value
) > 0x00ffffff)
27529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27530 _("invalid swi expression"));
27531 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27533 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27537 case BFD_RELOC_ARM_MULTI
:
27538 if (((unsigned long) value
) > 0xffff)
27539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27540 _("invalid expression in load/store multiple"));
27541 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27542 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27546 case BFD_RELOC_ARM_PCREL_CALL
:
27548 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27550 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27551 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27552 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27553 /* Flip the bl to blx. This is a simple flip
27554 bit here because we generate PCREL_CALL for
27555 unconditional bls. */
27557 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27558 newval
= newval
| 0x10000000;
27559 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27565 goto arm_branch_common
;
27567 case BFD_RELOC_ARM_PCREL_JUMP
:
27568 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27570 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27571 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27572 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27574 /* This would map to a bl<cond>, b<cond>,
27575 b<always> to a Thumb function. We
27576 need to force a relocation for this particular
27578 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27581 /* Fall through. */
27583 case BFD_RELOC_ARM_PLT32
:
27585 case BFD_RELOC_ARM_PCREL_BRANCH
:
27587 goto arm_branch_common
;
27589 case BFD_RELOC_ARM_PCREL_BLX
:
27592 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27594 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27595 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27596 && ARM_IS_FUNC (fixP
->fx_addsy
))
27598 /* Flip the blx to a bl and warn. */
27599 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27600 newval
= 0xeb000000;
27601 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27602 _("blx to '%s' an ARM ISA state function changed to bl"),
27604 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27610 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27611 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27615 /* We are going to store value (shifted right by two) in the
27616 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27617 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27621 _("misaligned branch destination"));
27622 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27623 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27626 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27628 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27629 newval
|= (value
>> 2) & 0x00ffffff;
27630 /* Set the H bit on BLX instructions. */
27634 newval
|= 0x01000000;
27636 newval
&= ~0x01000000;
27638 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27642 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27643 /* CBZ can only branch forward. */
27645 /* Attempts to use CBZ to branch to the next instruction
27646 (which, strictly speaking, are prohibited) will be turned into
27649 FIXME: It may be better to remove the instruction completely and
27650 perform relaxation. */
27653 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27654 newval
= 0xbf00; /* NOP encoding T1 */
27655 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27664 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27665 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27666 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27671 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27672 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27675 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27677 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27678 newval
|= (value
& 0x1ff) >> 1;
27679 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27683 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27684 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27687 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27689 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27690 newval
|= (value
& 0xfff) >> 1;
27691 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27695 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27697 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27698 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27699 && ARM_IS_FUNC (fixP
->fx_addsy
)
27700 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27702 /* Force a relocation for a branch 20 bits wide. */
27705 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27707 _("conditional branch out of range"));
27709 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27712 addressT S
, J1
, J2
, lo
, hi
;
27714 S
= (value
& 0x00100000) >> 20;
27715 J2
= (value
& 0x00080000) >> 19;
27716 J1
= (value
& 0x00040000) >> 18;
27717 hi
= (value
& 0x0003f000) >> 12;
27718 lo
= (value
& 0x00000ffe) >> 1;
27720 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27721 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27722 newval
|= (S
<< 10) | hi
;
27723 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27724 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27725 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27729 case BFD_RELOC_THUMB_PCREL_BLX
:
27730 /* If there is a blx from a thumb state function to
27731 another thumb function flip this to a bl and warn
27735 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27736 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27737 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27739 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27740 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27741 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27743 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27744 newval
= newval
| 0x1000;
27745 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27746 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27751 goto thumb_bl_common
;
27753 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27754 /* A bl from Thumb state ISA to an internal ARM state function
27755 is converted to a blx. */
27757 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27758 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27759 && ARM_IS_FUNC (fixP
->fx_addsy
)
27760 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27762 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27763 newval
= newval
& ~0x1000;
27764 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27765 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27771 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27772 /* For a BLX instruction, make sure that the relocation is rounded up
27773 to a word boundary. This follows the semantics of the instruction
27774 which specifies that bit 1 of the target address will come from bit
27775 1 of the base address. */
27776 value
= (value
+ 3) & ~ 3;
27779 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27780 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27781 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27784 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27786 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27788 else if ((value
& ~0x1ffffff)
27789 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27791 _("Thumb2 branch out of range"));
27794 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27795 encode_thumb2_b_bl_offset (buf
, value
);
27799 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27800 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27803 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27804 encode_thumb2_b_bl_offset (buf
, value
);
27809 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27814 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27815 md_number_to_chars (buf
, value
, 2);
27819 case BFD_RELOC_ARM_TLS_CALL
:
27820 case BFD_RELOC_ARM_THM_TLS_CALL
:
27821 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27822 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27823 case BFD_RELOC_ARM_TLS_GOTDESC
:
27824 case BFD_RELOC_ARM_TLS_GD32
:
27825 case BFD_RELOC_ARM_TLS_LE32
:
27826 case BFD_RELOC_ARM_TLS_IE32
:
27827 case BFD_RELOC_ARM_TLS_LDM32
:
27828 case BFD_RELOC_ARM_TLS_LDO32
:
27829 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27832 /* Same handling as above, but with the arm_fdpic guard. */
27833 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27834 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27835 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27838 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27843 _("Relocation supported only in FDPIC mode"));
27847 case BFD_RELOC_ARM_GOT32
:
27848 case BFD_RELOC_ARM_GOTOFF
:
27851 case BFD_RELOC_ARM_GOT_PREL
:
27852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27853 md_number_to_chars (buf
, value
, 4);
27856 case BFD_RELOC_ARM_TARGET2
:
27857 /* TARGET2 is not partial-inplace, so we need to write the
27858 addend here for REL targets, because it won't be written out
27859 during reloc processing later. */
27860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27861 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27864 /* Relocations for FDPIC. */
27865 case BFD_RELOC_ARM_GOTFUNCDESC
:
27866 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27867 case BFD_RELOC_ARM_FUNCDESC
:
27870 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27871 md_number_to_chars (buf
, 0, 4);
27875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27876 _("Relocation supported only in FDPIC mode"));
27881 case BFD_RELOC_RVA
:
27883 case BFD_RELOC_ARM_TARGET1
:
27884 case BFD_RELOC_ARM_ROSEGREL32
:
27885 case BFD_RELOC_ARM_SBREL32
:
27886 case BFD_RELOC_32_PCREL
:
27888 case BFD_RELOC_32_SECREL
:
27890 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27892 /* For WinCE we only do this for pcrel fixups. */
27893 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27895 md_number_to_chars (buf
, value
, 4);
27899 case BFD_RELOC_ARM_PREL31
:
27900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27902 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27903 if ((value
^ (value
>> 1)) & 0x40000000)
27905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27906 _("rel31 relocation overflow"));
27908 newval
|= value
& 0x7fffffff;
27909 md_number_to_chars (buf
, newval
, 4);
27914 case BFD_RELOC_ARM_CP_OFF_IMM
:
27915 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27916 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27917 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27918 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27920 newval
= get_thumb32_insn (buf
);
27921 if ((newval
& 0x0f200f00) == 0x0d000900)
27923 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27924 has permitted values that are multiples of 2, in the range 0
27926 if (value
< -510 || value
> 510 || (value
& 1))
27927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27928 _("co-processor offset out of range"));
27930 else if ((newval
& 0xfe001f80) == 0xec000f80)
27932 if (value
< -511 || value
> 512 || (value
& 3))
27933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27934 _("co-processor offset out of range"));
27936 else if (value
< -1023 || value
> 1023 || (value
& 3))
27937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27938 _("co-processor offset out of range"));
27943 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27944 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27945 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27947 newval
= get_thumb32_insn (buf
);
27950 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27951 newval
&= 0xffffff80;
27953 newval
&= 0xffffff00;
27957 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27958 newval
&= 0xff7fff80;
27960 newval
&= 0xff7fff00;
27961 if ((newval
& 0x0f200f00) == 0x0d000900)
27963 /* This is a fp16 vstr/vldr.
27965 It requires the immediate offset in the instruction is shifted
27966 left by 1 to be a half-word offset.
27968 Here, left shift by 1 first, and later right shift by 2
27969 should get the right offset. */
27972 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
27974 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27975 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27976 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27978 put_thumb32_insn (buf
, newval
);
27981 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
27982 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
27983 if (value
< -255 || value
> 255)
27984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27985 _("co-processor offset out of range"));
27987 goto cp_off_common
;
27989 case BFD_RELOC_ARM_THUMB_OFFSET
:
27990 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27991 /* Exactly what ranges, and where the offset is inserted depends
27992 on the type of instruction, we can establish this from the
27994 switch (newval
>> 12)
27996 case 4: /* PC load. */
27997 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27998 forced to zero for these loads; md_pcrel_from has already
27999 compensated for this. */
28001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28002 _("invalid offset, target not word aligned (0x%08lX)"),
28003 (((unsigned long) fixP
->fx_frag
->fr_address
28004 + (unsigned long) fixP
->fx_where
) & ~3)
28005 + (unsigned long) value
);
28007 if (value
& ~0x3fc)
28008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28009 _("invalid offset, value too big (0x%08lX)"),
28012 newval
|= value
>> 2;
28015 case 9: /* SP load/store. */
28016 if (value
& ~0x3fc)
28017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28018 _("invalid offset, value too big (0x%08lX)"),
28020 newval
|= value
>> 2;
28023 case 6: /* Word load/store. */
28025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28026 _("invalid offset, value too big (0x%08lX)"),
28028 newval
|= value
<< 4; /* 6 - 2. */
28031 case 7: /* Byte load/store. */
28033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28034 _("invalid offset, value too big (0x%08lX)"),
28036 newval
|= value
<< 6;
28039 case 8: /* Halfword load/store. */
28041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28042 _("invalid offset, value too big (0x%08lX)"),
28044 newval
|= value
<< 5; /* 6 - 1. */
28048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28049 "Unable to process relocation for thumb opcode: %lx",
28050 (unsigned long) newval
);
28053 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28056 case BFD_RELOC_ARM_THUMB_ADD
:
28057 /* This is a complicated relocation, since we use it for all of
28058 the following immediate relocations:
28062 9bit ADD/SUB SP word-aligned
28063 10bit ADD PC/SP word-aligned
28065 The type of instruction being processed is encoded in the
28072 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28074 int rd
= (newval
>> 4) & 0xf;
28075 int rs
= newval
& 0xf;
28076 int subtract
= !!(newval
& 0x8000);
28078 /* Check for HI regs, only very restricted cases allowed:
28079 Adjusting SP, and using PC or SP to get an address. */
28080 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28081 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28083 _("invalid Hi register with immediate"));
28085 /* If value is negative, choose the opposite instruction. */
28089 subtract
= !subtract
;
28091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28092 _("immediate value out of range"));
28097 if (value
& ~0x1fc)
28098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28099 _("invalid immediate for stack address calculation"));
28100 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28101 newval
|= value
>> 2;
28103 else if (rs
== REG_PC
|| rs
== REG_SP
)
28105 /* PR gas/18541. If the addition is for a defined symbol
28106 within range of an ADR instruction then accept it. */
28109 && fixP
->fx_addsy
!= NULL
)
28113 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28114 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28115 || S_IS_WEAK (fixP
->fx_addsy
))
28117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28118 _("address calculation needs a strongly defined nearby symbol"));
28122 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28124 /* Round up to the next 4-byte boundary. */
28129 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28134 _("symbol too far away"));
28144 if (subtract
|| value
& ~0x3fc)
28145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28146 _("invalid immediate for address calculation (value = 0x%08lX)"),
28147 (unsigned long) (subtract
? - value
: value
));
28148 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28150 newval
|= value
>> 2;
28155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28156 _("immediate value out of range"));
28157 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28158 newval
|= (rd
<< 8) | value
;
28163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28164 _("immediate value out of range"));
28165 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28166 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28172 case BFD_RELOC_ARM_THUMB_IMM
:
28173 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28174 if (value
< 0 || value
> 255)
28175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28176 _("invalid immediate: %ld is out of range"),
28179 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28182 case BFD_RELOC_ARM_THUMB_SHIFT
:
28183 /* 5bit shift value (0..32). LSL cannot take 32. */
28184 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28185 temp
= newval
& 0xf800;
28186 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28188 _("invalid shift value: %ld"), (long) value
);
28189 /* Shifts of zero must be encoded as LSL. */
28191 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28192 /* Shifts of 32 are encoded as zero. */
28193 else if (value
== 32)
28195 newval
|= value
<< 6;
28196 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28199 case BFD_RELOC_VTABLE_INHERIT
:
28200 case BFD_RELOC_VTABLE_ENTRY
:
28204 case BFD_RELOC_ARM_MOVW
:
28205 case BFD_RELOC_ARM_MOVT
:
28206 case BFD_RELOC_ARM_THUMB_MOVW
:
28207 case BFD_RELOC_ARM_THUMB_MOVT
:
28208 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28210 /* REL format relocations are limited to a 16-bit addend. */
28211 if (!fixP
->fx_done
)
28213 if (value
< -0x8000 || value
> 0x7fff)
28214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28215 _("offset out of range"));
28217 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28218 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28223 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28224 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28226 newval
= get_thumb32_insn (buf
);
28227 newval
&= 0xfbf08f00;
28228 newval
|= (value
& 0xf000) << 4;
28229 newval
|= (value
& 0x0800) << 15;
28230 newval
|= (value
& 0x0700) << 4;
28231 newval
|= (value
& 0x00ff);
28232 put_thumb32_insn (buf
, newval
);
28236 newval
= md_chars_to_number (buf
, 4);
28237 newval
&= 0xfff0f000;
28238 newval
|= value
& 0x0fff;
28239 newval
|= (value
& 0xf000) << 4;
28240 md_number_to_chars (buf
, newval
, 4);
28245 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28246 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28247 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28248 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28249 gas_assert (!fixP
->fx_done
);
28252 bfd_boolean is_mov
;
28253 bfd_vma encoded_addend
= value
;
28255 /* Check that addend can be encoded in instruction. */
28256 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28258 _("the offset 0x%08lX is not representable"),
28259 (unsigned long) encoded_addend
);
28261 /* Extract the instruction. */
28262 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28263 is_mov
= (insn
& 0xf800) == 0x2000;
28268 if (!seg
->use_rela_p
)
28269 insn
|= encoded_addend
;
28275 /* Extract the instruction. */
28276 /* Encoding is the following
28281 /* The following conditions must be true :
28286 rd
= (insn
>> 4) & 0xf;
28288 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28290 _("Unable to process relocation for thumb opcode: %lx"),
28291 (unsigned long) insn
);
28293 /* Encode as ADD immediate8 thumb 1 code. */
28294 insn
= 0x3000 | (rd
<< 8);
28296 /* Place the encoded addend into the first 8 bits of the
28298 if (!seg
->use_rela_p
)
28299 insn
|= encoded_addend
;
28302 /* Update the instruction. */
28303 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28307 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28308 case BFD_RELOC_ARM_ALU_PC_G0
:
28309 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28310 case BFD_RELOC_ARM_ALU_PC_G1
:
28311 case BFD_RELOC_ARM_ALU_PC_G2
:
28312 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28313 case BFD_RELOC_ARM_ALU_SB_G0
:
28314 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28315 case BFD_RELOC_ARM_ALU_SB_G1
:
28316 case BFD_RELOC_ARM_ALU_SB_G2
:
28317 gas_assert (!fixP
->fx_done
);
28318 if (!seg
->use_rela_p
)
28321 bfd_vma encoded_addend
;
28322 bfd_vma addend_abs
= llabs (value
);
28324 /* Check that the absolute value of the addend can be
28325 expressed as an 8-bit constant plus a rotation. */
28326 encoded_addend
= encode_arm_immediate (addend_abs
);
28327 if (encoded_addend
== (unsigned int) FAIL
)
28328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28329 _("the offset 0x%08lX is not representable"),
28330 (unsigned long) addend_abs
);
28332 /* Extract the instruction. */
28333 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28335 /* If the addend is positive, use an ADD instruction.
28336 Otherwise use a SUB. Take care not to destroy the S bit. */
28337 insn
&= 0xff1fffff;
28343 /* Place the encoded addend into the first 12 bits of the
28345 insn
&= 0xfffff000;
28346 insn
|= encoded_addend
;
28348 /* Update the instruction. */
28349 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28353 case BFD_RELOC_ARM_LDR_PC_G0
:
28354 case BFD_RELOC_ARM_LDR_PC_G1
:
28355 case BFD_RELOC_ARM_LDR_PC_G2
:
28356 case BFD_RELOC_ARM_LDR_SB_G0
:
28357 case BFD_RELOC_ARM_LDR_SB_G1
:
28358 case BFD_RELOC_ARM_LDR_SB_G2
:
28359 gas_assert (!fixP
->fx_done
);
28360 if (!seg
->use_rela_p
)
28363 bfd_vma addend_abs
= llabs (value
);
28365 /* Check that the absolute value of the addend can be
28366 encoded in 12 bits. */
28367 if (addend_abs
>= 0x1000)
28368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28369 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28370 (unsigned long) addend_abs
);
28372 /* Extract the instruction. */
28373 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28375 /* If the addend is negative, clear bit 23 of the instruction.
28376 Otherwise set it. */
28378 insn
&= ~(1 << 23);
28382 /* Place the absolute value of the addend into the first 12 bits
28383 of the instruction. */
28384 insn
&= 0xfffff000;
28385 insn
|= addend_abs
;
28387 /* Update the instruction. */
28388 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28392 case BFD_RELOC_ARM_LDRS_PC_G0
:
28393 case BFD_RELOC_ARM_LDRS_PC_G1
:
28394 case BFD_RELOC_ARM_LDRS_PC_G2
:
28395 case BFD_RELOC_ARM_LDRS_SB_G0
:
28396 case BFD_RELOC_ARM_LDRS_SB_G1
:
28397 case BFD_RELOC_ARM_LDRS_SB_G2
:
28398 gas_assert (!fixP
->fx_done
);
28399 if (!seg
->use_rela_p
)
28402 bfd_vma addend_abs
= llabs (value
);
28404 /* Check that the absolute value of the addend can be
28405 encoded in 8 bits. */
28406 if (addend_abs
>= 0x100)
28407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28408 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28409 (unsigned long) addend_abs
);
28411 /* Extract the instruction. */
28412 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28414 /* If the addend is negative, clear bit 23 of the instruction.
28415 Otherwise set it. */
28417 insn
&= ~(1 << 23);
28421 /* Place the first four bits of the absolute value of the addend
28422 into the first 4 bits of the instruction, and the remaining
28423 four into bits 8 .. 11. */
28424 insn
&= 0xfffff0f0;
28425 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28427 /* Update the instruction. */
28428 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28432 case BFD_RELOC_ARM_LDC_PC_G0
:
28433 case BFD_RELOC_ARM_LDC_PC_G1
:
28434 case BFD_RELOC_ARM_LDC_PC_G2
:
28435 case BFD_RELOC_ARM_LDC_SB_G0
:
28436 case BFD_RELOC_ARM_LDC_SB_G1
:
28437 case BFD_RELOC_ARM_LDC_SB_G2
:
28438 gas_assert (!fixP
->fx_done
);
28439 if (!seg
->use_rela_p
)
28442 bfd_vma addend_abs
= llabs (value
);
28444 /* Check that the absolute value of the addend is a multiple of
28445 four and, when divided by four, fits in 8 bits. */
28446 if (addend_abs
& 0x3)
28447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28448 _("bad offset 0x%08lX (must be word-aligned)"),
28449 (unsigned long) addend_abs
);
28451 if ((addend_abs
>> 2) > 0xff)
28452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28453 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28454 (unsigned long) addend_abs
);
28456 /* Extract the instruction. */
28457 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28459 /* If the addend is negative, clear bit 23 of the instruction.
28460 Otherwise set it. */
28462 insn
&= ~(1 << 23);
28466 /* Place the addend (divided by four) into the first eight
28467 bits of the instruction. */
28468 insn
&= 0xfffffff0;
28469 insn
|= addend_abs
>> 2;
28471 /* Update the instruction. */
28472 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28476 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28478 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28479 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28480 && ARM_IS_FUNC (fixP
->fx_addsy
)
28481 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28483 /* Force a relocation for a branch 5 bits wide. */
28486 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28490 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28492 addressT boff
= value
>> 1;
28494 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28495 newval
|= (boff
<< 7);
28496 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28500 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28502 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28503 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28504 && ARM_IS_FUNC (fixP
->fx_addsy
)
28505 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28509 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28511 _("branch out of range"));
28513 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28515 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28517 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28518 addressT diff
= value
- boff
;
28522 newval
|= 1 << 1; /* T bit. */
28524 else if (diff
!= 2)
28526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28527 _("out of range label-relative fixup value"));
28529 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28533 case BFD_RELOC_ARM_THUMB_BF17
:
28535 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28536 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28537 && ARM_IS_FUNC (fixP
->fx_addsy
)
28538 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28540 /* Force a relocation for a branch 17 bits wide. */
28544 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28548 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28551 addressT immA
, immB
, immC
;
28553 immA
= (value
& 0x0001f000) >> 12;
28554 immB
= (value
& 0x00000ffc) >> 2;
28555 immC
= (value
& 0x00000002) >> 1;
28557 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28558 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28560 newval2
|= (immC
<< 11) | (immB
<< 1);
28561 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28562 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28566 case BFD_RELOC_ARM_THUMB_BF19
:
28568 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28569 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28570 && ARM_IS_FUNC (fixP
->fx_addsy
)
28571 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28573 /* Force a relocation for a branch 19 bits wide. */
28577 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28581 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28584 addressT immA
, immB
, immC
;
28586 immA
= (value
& 0x0007f000) >> 12;
28587 immB
= (value
& 0x00000ffc) >> 2;
28588 immC
= (value
& 0x00000002) >> 1;
28590 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28591 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28593 newval2
|= (immC
<< 11) | (immB
<< 1);
28594 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28595 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28599 case BFD_RELOC_ARM_THUMB_BF13
:
28601 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28602 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28603 && ARM_IS_FUNC (fixP
->fx_addsy
)
28604 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28606 /* Force a relocation for a branch 13 bits wide. */
28610 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28614 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28617 addressT immA
, immB
, immC
;
28619 immA
= (value
& 0x00001000) >> 12;
28620 immB
= (value
& 0x00000ffc) >> 2;
28621 immC
= (value
& 0x00000002) >> 1;
28623 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28624 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28626 newval2
|= (immC
<< 11) | (immB
<< 1);
28627 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28628 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28632 case BFD_RELOC_ARM_THUMB_LOOP12
:
28634 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28635 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28636 && ARM_IS_FUNC (fixP
->fx_addsy
)
28637 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28639 /* Force a relocation for a branch 12 bits wide. */
28643 bfd_vma insn
= get_thumb32_insn (buf
);
28644 /* le lr, <label> or le <label> */
28645 if (((insn
& 0xffffffff) == 0xf00fc001)
28646 || ((insn
& 0xffffffff) == 0xf02fc001))
28649 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28652 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28654 addressT imml
, immh
;
28656 immh
= (value
& 0x00000ffc) >> 2;
28657 imml
= (value
& 0x00000002) >> 1;
28659 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28660 newval
|= (imml
<< 11) | (immh
<< 1);
28661 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28665 case BFD_RELOC_ARM_V4BX
:
28666 /* This will need to go in the object file. */
28670 case BFD_RELOC_UNUSED
:
28672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28673 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28677 /* Translate internal representation of relocation info to BFD target
28681 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28684 bfd_reloc_code_real_type code
;
28686 reloc
= XNEW (arelent
);
28688 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28689 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28690 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28692 if (fixp
->fx_pcrel
)
28694 if (section
->use_rela_p
)
28695 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28697 fixp
->fx_offset
= reloc
->address
;
28699 reloc
->addend
= fixp
->fx_offset
;
28701 switch (fixp
->fx_r_type
)
28704 if (fixp
->fx_pcrel
)
28706 code
= BFD_RELOC_8_PCREL
;
28709 /* Fall through. */
28712 if (fixp
->fx_pcrel
)
28714 code
= BFD_RELOC_16_PCREL
;
28717 /* Fall through. */
28720 if (fixp
->fx_pcrel
)
28722 code
= BFD_RELOC_32_PCREL
;
28725 /* Fall through. */
28727 case BFD_RELOC_ARM_MOVW
:
28728 if (fixp
->fx_pcrel
)
28730 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28733 /* Fall through. */
28735 case BFD_RELOC_ARM_MOVT
:
28736 if (fixp
->fx_pcrel
)
28738 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28741 /* Fall through. */
28743 case BFD_RELOC_ARM_THUMB_MOVW
:
28744 if (fixp
->fx_pcrel
)
28746 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28749 /* Fall through. */
28751 case BFD_RELOC_ARM_THUMB_MOVT
:
28752 if (fixp
->fx_pcrel
)
28754 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28757 /* Fall through. */
28759 case BFD_RELOC_NONE
:
28760 case BFD_RELOC_ARM_PCREL_BRANCH
:
28761 case BFD_RELOC_ARM_PCREL_BLX
:
28762 case BFD_RELOC_RVA
:
28763 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28764 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28765 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28766 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28767 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28768 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28769 case BFD_RELOC_VTABLE_ENTRY
:
28770 case BFD_RELOC_VTABLE_INHERIT
:
28772 case BFD_RELOC_32_SECREL
:
28774 code
= fixp
->fx_r_type
;
28777 case BFD_RELOC_THUMB_PCREL_BLX
:
28779 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28780 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28783 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28786 case BFD_RELOC_ARM_LITERAL
:
28787 case BFD_RELOC_ARM_HWLITERAL
:
28788 /* If this is called then the a literal has
28789 been referenced across a section boundary. */
28790 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28791 _("literal referenced across section boundary"));
28795 case BFD_RELOC_ARM_TLS_CALL
:
28796 case BFD_RELOC_ARM_THM_TLS_CALL
:
28797 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28798 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28799 case BFD_RELOC_ARM_GOT32
:
28800 case BFD_RELOC_ARM_GOTOFF
:
28801 case BFD_RELOC_ARM_GOT_PREL
:
28802 case BFD_RELOC_ARM_PLT32
:
28803 case BFD_RELOC_ARM_TARGET1
:
28804 case BFD_RELOC_ARM_ROSEGREL32
:
28805 case BFD_RELOC_ARM_SBREL32
:
28806 case BFD_RELOC_ARM_PREL31
:
28807 case BFD_RELOC_ARM_TARGET2
:
28808 case BFD_RELOC_ARM_TLS_LDO32
:
28809 case BFD_RELOC_ARM_PCREL_CALL
:
28810 case BFD_RELOC_ARM_PCREL_JUMP
:
28811 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28812 case BFD_RELOC_ARM_ALU_PC_G0
:
28813 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28814 case BFD_RELOC_ARM_ALU_PC_G1
:
28815 case BFD_RELOC_ARM_ALU_PC_G2
:
28816 case BFD_RELOC_ARM_LDR_PC_G0
:
28817 case BFD_RELOC_ARM_LDR_PC_G1
:
28818 case BFD_RELOC_ARM_LDR_PC_G2
:
28819 case BFD_RELOC_ARM_LDRS_PC_G0
:
28820 case BFD_RELOC_ARM_LDRS_PC_G1
:
28821 case BFD_RELOC_ARM_LDRS_PC_G2
:
28822 case BFD_RELOC_ARM_LDC_PC_G0
:
28823 case BFD_RELOC_ARM_LDC_PC_G1
:
28824 case BFD_RELOC_ARM_LDC_PC_G2
:
28825 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28826 case BFD_RELOC_ARM_ALU_SB_G0
:
28827 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28828 case BFD_RELOC_ARM_ALU_SB_G1
:
28829 case BFD_RELOC_ARM_ALU_SB_G2
:
28830 case BFD_RELOC_ARM_LDR_SB_G0
:
28831 case BFD_RELOC_ARM_LDR_SB_G1
:
28832 case BFD_RELOC_ARM_LDR_SB_G2
:
28833 case BFD_RELOC_ARM_LDRS_SB_G0
:
28834 case BFD_RELOC_ARM_LDRS_SB_G1
:
28835 case BFD_RELOC_ARM_LDRS_SB_G2
:
28836 case BFD_RELOC_ARM_LDC_SB_G0
:
28837 case BFD_RELOC_ARM_LDC_SB_G1
:
28838 case BFD_RELOC_ARM_LDC_SB_G2
:
28839 case BFD_RELOC_ARM_V4BX
:
28840 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28841 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28842 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28843 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28844 case BFD_RELOC_ARM_GOTFUNCDESC
:
28845 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28846 case BFD_RELOC_ARM_FUNCDESC
:
28847 case BFD_RELOC_ARM_THUMB_BF17
:
28848 case BFD_RELOC_ARM_THUMB_BF19
:
28849 case BFD_RELOC_ARM_THUMB_BF13
:
28850 code
= fixp
->fx_r_type
;
28853 case BFD_RELOC_ARM_TLS_GOTDESC
:
28854 case BFD_RELOC_ARM_TLS_GD32
:
28855 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28856 case BFD_RELOC_ARM_TLS_LE32
:
28857 case BFD_RELOC_ARM_TLS_IE32
:
28858 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28859 case BFD_RELOC_ARM_TLS_LDM32
:
28860 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28861 /* BFD will include the symbol's address in the addend.
28862 But we don't want that, so subtract it out again here. */
28863 if (!S_IS_COMMON (fixp
->fx_addsy
))
28864 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28865 code
= fixp
->fx_r_type
;
28869 case BFD_RELOC_ARM_IMMEDIATE
:
28870 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28871 _("internal relocation (type: IMMEDIATE) not fixed up"));
28874 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28875 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28876 _("ADRL used for a symbol not defined in the same file"));
28879 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28880 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28881 case BFD_RELOC_ARM_THUMB_LOOP12
:
28882 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28883 _("%s used for a symbol not defined in the same file"),
28884 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28887 case BFD_RELOC_ARM_OFFSET_IMM
:
28888 if (section
->use_rela_p
)
28890 code
= fixp
->fx_r_type
;
28894 if (fixp
->fx_addsy
!= NULL
28895 && !S_IS_DEFINED (fixp
->fx_addsy
)
28896 && S_IS_LOCAL (fixp
->fx_addsy
))
28898 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28899 _("undefined local label `%s'"),
28900 S_GET_NAME (fixp
->fx_addsy
));
28904 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28905 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28912 switch (fixp
->fx_r_type
)
28914 case BFD_RELOC_NONE
: type
= "NONE"; break;
28915 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28916 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28917 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28918 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28919 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28920 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28921 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28922 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28923 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28924 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28925 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28926 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28927 default: type
= _("<unknown>"); break;
28929 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28930 _("cannot represent %s relocation in this object file format"),
28937 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28939 && fixp
->fx_addsy
== GOT_symbol
)
28941 code
= BFD_RELOC_ARM_GOTPC
;
28942 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
28946 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
28948 if (reloc
->howto
== NULL
)
28950 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28951 _("cannot represent %s relocation in this object file format"),
28952 bfd_get_reloc_code_name (code
));
28956 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28957 vtable entry to be used in the relocation's section offset. */
28958 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28959 reloc
->address
= fixp
->fx_offset
;
28964 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28967 cons_fix_new_arm (fragS
* frag
,
28971 bfd_reloc_code_real_type reloc
)
28976 FIXME: @@ Should look at CPU word size. */
28980 reloc
= BFD_RELOC_8
;
28983 reloc
= BFD_RELOC_16
;
28987 reloc
= BFD_RELOC_32
;
28990 reloc
= BFD_RELOC_64
;
28995 if (exp
->X_op
== O_secrel
)
28997 exp
->X_op
= O_symbol
;
28998 reloc
= BFD_RELOC_32_SECREL
;
29002 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29005 #if defined (OBJ_COFF)
29007 arm_validate_fix (fixS
* fixP
)
29009 /* If the destination of the branch is a defined symbol which does not have
29010 the THUMB_FUNC attribute, then we must be calling a function which has
29011 the (interfacearm) attribute. We look for the Thumb entry point to that
29012 function and change the branch to refer to that function instead. */
29013 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29014 && fixP
->fx_addsy
!= NULL
29015 && S_IS_DEFINED (fixP
->fx_addsy
)
29016 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29018 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29025 arm_force_relocation (struct fix
* fixp
)
29027 #if defined (OBJ_COFF) && defined (TE_PE)
29028 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29032 /* In case we have a call or a branch to a function in ARM ISA mode from
29033 a thumb function or vice-versa force the relocation. These relocations
29034 are cleared off for some cores that might have blx and simple transformations
29038 switch (fixp
->fx_r_type
)
29040 case BFD_RELOC_ARM_PCREL_JUMP
:
29041 case BFD_RELOC_ARM_PCREL_CALL
:
29042 case BFD_RELOC_THUMB_PCREL_BLX
:
29043 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29047 case BFD_RELOC_ARM_PCREL_BLX
:
29048 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29049 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29050 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29051 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29060 /* Resolve these relocations even if the symbol is extern or weak.
29061 Technically this is probably wrong due to symbol preemption.
29062 In practice these relocations do not have enough range to be useful
29063 at dynamic link time, and some code (e.g. in the Linux kernel)
29064 expects these references to be resolved. */
29065 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29066 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29067 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29068 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29069 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29070 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29071 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29072 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29073 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29074 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29075 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29076 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29077 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29078 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29081 /* Always leave these relocations for the linker. */
29082 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29083 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29084 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29087 /* Always generate relocations against function symbols. */
29088 if (fixp
->fx_r_type
== BFD_RELOC_32
29090 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29093 return generic_force_reloc (fixp
);
29096 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29097 /* Relocations against function names must be left unadjusted,
29098 so that the linker can use this information to generate interworking
29099 stubs. The MIPS version of this function
29100 also prevents relocations that are mips-16 specific, but I do not
29101 know why it does this.
29104 There is one other problem that ought to be addressed here, but
29105 which currently is not: Taking the address of a label (rather
29106 than a function) and then later jumping to that address. Such
29107 addresses also ought to have their bottom bit set (assuming that
29108 they reside in Thumb code), but at the moment they will not. */
29111 arm_fix_adjustable (fixS
* fixP
)
29113 if (fixP
->fx_addsy
== NULL
)
29116 /* Preserve relocations against symbols with function type. */
29117 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29120 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29121 && fixP
->fx_subsy
== NULL
)
29124 /* We need the symbol name for the VTABLE entries. */
29125 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29126 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29129 /* Don't allow symbols to be discarded on GOT related relocs. */
29130 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29131 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29132 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29133 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29134 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29135 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29136 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29137 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29138 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29139 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29140 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29141 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29142 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29143 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29144 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29145 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29146 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29149 /* Similarly for group relocations. */
29150 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29151 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29152 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29155 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29156 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29157 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29158 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29159 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29160 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29161 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29162 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29163 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29166 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29167 offsets, so keep these symbols. */
29168 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29169 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29174 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29178 elf32_arm_target_format (void)
29181 return (target_big_endian
29182 ? "elf32-bigarm-symbian"
29183 : "elf32-littlearm-symbian");
29184 #elif defined (TE_VXWORKS)
29185 return (target_big_endian
29186 ? "elf32-bigarm-vxworks"
29187 : "elf32-littlearm-vxworks");
29188 #elif defined (TE_NACL)
29189 return (target_big_endian
29190 ? "elf32-bigarm-nacl"
29191 : "elf32-littlearm-nacl");
29195 if (target_big_endian
)
29196 return "elf32-bigarm-fdpic";
29198 return "elf32-littlearm-fdpic";
29202 if (target_big_endian
)
29203 return "elf32-bigarm";
29205 return "elf32-littlearm";
29211 armelf_frob_symbol (symbolS
* symp
,
29214 elf_frob_symbol (symp
, puntp
);
29218 /* MD interface: Finalization. */
29223 literal_pool
* pool
;
29225 /* Ensure that all the predication blocks are properly closed. */
29226 check_pred_blocks_finished ();
29228 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29230 /* Put it at the end of the relevant section. */
29231 subseg_set (pool
->section
, pool
->sub_section
);
29233 arm_elf_change_section ();
29240 /* Remove any excess mapping symbols generated for alignment frags in
29241 SEC. We may have created a mapping symbol before a zero byte
29242 alignment; remove it if there's a mapping symbol after the
29245 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29246 void *dummy ATTRIBUTE_UNUSED
)
29248 segment_info_type
*seginfo
= seg_info (sec
);
29251 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29254 for (fragp
= seginfo
->frchainP
->frch_root
;
29256 fragp
= fragp
->fr_next
)
29258 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29259 fragS
*next
= fragp
->fr_next
;
29261 /* Variable-sized frags have been converted to fixed size by
29262 this point. But if this was variable-sized to start with,
29263 there will be a fixed-size frag after it. So don't handle
29265 if (sym
== NULL
|| next
== NULL
)
29268 if (S_GET_VALUE (sym
) < next
->fr_address
)
29269 /* Not at the end of this frag. */
29271 know (S_GET_VALUE (sym
) == next
->fr_address
);
29275 if (next
->tc_frag_data
.first_map
!= NULL
)
29277 /* Next frag starts with a mapping symbol. Discard this
29279 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29283 if (next
->fr_next
== NULL
)
29285 /* This mapping symbol is at the end of the section. Discard
29287 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29288 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29292 /* As long as we have empty frags without any mapping symbols,
29294 /* If the next frag is non-empty and does not start with a
29295 mapping symbol, then this mapping symbol is required. */
29296 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29299 next
= next
->fr_next
;
29301 while (next
!= NULL
);
29306 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29310 arm_adjust_symtab (void)
29315 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29317 if (ARM_IS_THUMB (sym
))
29319 if (THUMB_IS_FUNC (sym
))
29321 /* Mark the symbol as a Thumb function. */
29322 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29323 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29324 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29326 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29327 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29329 as_bad (_("%s: unexpected function type: %d"),
29330 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29332 else switch (S_GET_STORAGE_CLASS (sym
))
29335 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29338 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29341 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29349 if (ARM_IS_INTERWORK (sym
))
29350 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29357 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29359 if (ARM_IS_THUMB (sym
))
29361 elf_symbol_type
* elf_sym
;
29363 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29364 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29366 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29367 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29369 /* If it's a .thumb_func, declare it as so,
29370 otherwise tag label as .code 16. */
29371 if (THUMB_IS_FUNC (sym
))
29372 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29373 ST_BRANCH_TO_THUMB
);
29374 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29375 elf_sym
->internal_elf_sym
.st_info
=
29376 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29381 /* Remove any overlapping mapping symbols generated by alignment frags. */
29382 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29383 /* Now do generic ELF adjustments. */
29384 elf_adjust_symtab ();
29388 /* MD interface: Initialization. */
29391 set_constant_flonums (void)
29395 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29396 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29400 /* Auto-select Thumb mode if it's the only available instruction set for the
29401 given architecture. */
29404 autoselect_thumb_from_cpu_variant (void)
29406 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29407 opcode_select (16);
29416 if ( (arm_ops_hsh
= hash_new ()) == NULL
29417 || (arm_cond_hsh
= hash_new ()) == NULL
29418 || (arm_vcond_hsh
= hash_new ()) == NULL
29419 || (arm_shift_hsh
= hash_new ()) == NULL
29420 || (arm_psr_hsh
= hash_new ()) == NULL
29421 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29422 || (arm_reg_hsh
= hash_new ()) == NULL
29423 || (arm_reloc_hsh
= hash_new ()) == NULL
29424 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29425 as_fatal (_("virtual memory exhausted"));
29427 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29428 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29429 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29430 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29431 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29432 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29433 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29434 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29435 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29436 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29437 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29438 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29439 (void *) (v7m_psrs
+ i
));
29440 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29441 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29443 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29445 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29446 (void *) (barrier_opt_names
+ i
));
29448 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29450 struct reloc_entry
* entry
= reloc_names
+ i
;
29452 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29453 /* This makes encode_branch() use the EABI versions of this relocation. */
29454 entry
->reloc
= BFD_RELOC_UNUSED
;
29456 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29460 set_constant_flonums ();
29462 /* Set the cpu variant based on the command-line options. We prefer
29463 -mcpu= over -march= if both are set (as for GCC); and we prefer
29464 -mfpu= over any other way of setting the floating point unit.
29465 Use of legacy options with new options are faulted. */
29468 if (mcpu_cpu_opt
|| march_cpu_opt
)
29469 as_bad (_("use of old and new-style options to set CPU type"));
29471 selected_arch
= *legacy_cpu
;
29473 else if (mcpu_cpu_opt
)
29475 selected_arch
= *mcpu_cpu_opt
;
29476 selected_ext
= *mcpu_ext_opt
;
29478 else if (march_cpu_opt
)
29480 selected_arch
= *march_cpu_opt
;
29481 selected_ext
= *march_ext_opt
;
29483 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29488 as_bad (_("use of old and new-style options to set FPU type"));
29490 selected_fpu
= *legacy_fpu
;
29493 selected_fpu
= *mfpu_opt
;
29496 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29497 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29498 /* Some environments specify a default FPU. If they don't, infer it
29499 from the processor. */
29501 selected_fpu
= *mcpu_fpu_opt
;
29502 else if (march_fpu_opt
)
29503 selected_fpu
= *march_fpu_opt
;
29505 selected_fpu
= fpu_default
;
29509 if (ARM_FEATURE_ZERO (selected_fpu
))
29511 if (!no_cpu_selected ())
29512 selected_fpu
= fpu_default
;
29514 selected_fpu
= fpu_arch_fpa
;
29518 if (ARM_FEATURE_ZERO (selected_arch
))
29520 selected_arch
= cpu_default
;
29521 selected_cpu
= selected_arch
;
29523 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29525 /* Autodection of feature mode: allow all features in cpu_variant but leave
29526 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29527 after all instruction have been processed and we can decide what CPU
29528 should be selected. */
29529 if (ARM_FEATURE_ZERO (selected_arch
))
29530 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29532 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29535 autoselect_thumb_from_cpu_variant ();
29537 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29539 #if defined OBJ_COFF || defined OBJ_ELF
29541 unsigned int flags
= 0;
29543 #if defined OBJ_ELF
29544 flags
= meabi_flags
;
29546 switch (meabi_flags
)
29548 case EF_ARM_EABI_UNKNOWN
:
29550 /* Set the flags in the private structure. */
29551 if (uses_apcs_26
) flags
|= F_APCS26
;
29552 if (support_interwork
) flags
|= F_INTERWORK
;
29553 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29554 if (pic_code
) flags
|= F_PIC
;
29555 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29556 flags
|= F_SOFT_FLOAT
;
29558 switch (mfloat_abi_opt
)
29560 case ARM_FLOAT_ABI_SOFT
:
29561 case ARM_FLOAT_ABI_SOFTFP
:
29562 flags
|= F_SOFT_FLOAT
;
29565 case ARM_FLOAT_ABI_HARD
:
29566 if (flags
& F_SOFT_FLOAT
)
29567 as_bad (_("hard-float conflicts with specified fpu"));
29571 /* Using pure-endian doubles (even if soft-float). */
29572 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29573 flags
|= F_VFP_FLOAT
;
29575 #if defined OBJ_ELF
29576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29577 flags
|= EF_ARM_MAVERICK_FLOAT
;
29580 case EF_ARM_EABI_VER4
:
29581 case EF_ARM_EABI_VER5
:
29582 /* No additional flags to set. */
29589 bfd_set_private_flags (stdoutput
, flags
);
29591 /* We have run out flags in the COFF header to encode the
29592 status of ATPCS support, so instead we create a dummy,
29593 empty, debug section called .arm.atpcs. */
29598 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29602 bfd_set_section_flags
29603 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29604 bfd_set_section_size (stdoutput
, sec
, 0);
29605 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29611 /* Record the CPU type as well. */
29612 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29613 mach
= bfd_mach_arm_iWMMXt2
;
29614 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29615 mach
= bfd_mach_arm_iWMMXt
;
29616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29617 mach
= bfd_mach_arm_XScale
;
29618 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29619 mach
= bfd_mach_arm_ep9312
;
29620 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29621 mach
= bfd_mach_arm_5TE
;
29622 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29624 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29625 mach
= bfd_mach_arm_5T
;
29627 mach
= bfd_mach_arm_5
;
29629 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29631 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29632 mach
= bfd_mach_arm_4T
;
29634 mach
= bfd_mach_arm_4
;
29636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29637 mach
= bfd_mach_arm_3M
;
29638 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29639 mach
= bfd_mach_arm_3
;
29640 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29641 mach
= bfd_mach_arm_2a
;
29642 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29643 mach
= bfd_mach_arm_2
;
29645 mach
= bfd_mach_arm_unknown
;
29647 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29650 /* Command line processing. */
29653 Invocation line includes a switch not recognized by the base assembler.
29654 See if it's a processor-specific option.
29656 This routine is somewhat complicated by the need for backwards
29657 compatibility (since older releases of gcc can't be changed).
29658 The new options try to make the interface as compatible as
29661 New options (supported) are:
29663 -mcpu=<cpu name> Assemble for selected processor
29664 -march=<architecture name> Assemble for selected architecture
29665 -mfpu=<fpu architecture> Assemble for selected FPU.
29666 -EB/-mbig-endian Big-endian
29667 -EL/-mlittle-endian Little-endian
29668 -k Generate PIC code
29669 -mthumb Start in Thumb mode
29670 -mthumb-interwork Code supports ARM/Thumb interworking
29672 -m[no-]warn-deprecated Warn about deprecated features
29673 -m[no-]warn-syms Warn when symbols match instructions
29675 For now we will also provide support for:
29677 -mapcs-32 32-bit Program counter
29678 -mapcs-26 26-bit Program counter
29679 -macps-float Floats passed in FP registers
29680 -mapcs-reentrant Reentrant code
29682 (sometime these will probably be replaced with -mapcs=<list of options>
29683 and -matpcs=<list of options>)
29685 The remaining options are only supported for back-wards compatibility.
29686 Cpu variants, the arm part is optional:
29687 -m[arm]1 Currently not supported.
29688 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29689 -m[arm]3 Arm 3 processor
29690 -m[arm]6[xx], Arm 6 processors
29691 -m[arm]7[xx][t][[d]m] Arm 7 processors
29692 -m[arm]8[10] Arm 8 processors
29693 -m[arm]9[20][tdmi] Arm 9 processors
29694 -mstrongarm[110[0]] StrongARM processors
29695 -mxscale XScale processors
29696 -m[arm]v[2345[t[e]]] Arm architectures
29697 -mall All (except the ARM1)
29699 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29700 -mfpe-old (No float load/store multiples)
29701 -mvfpxd VFP Single precision
29703 -mno-fpu Disable all floating point instructions
29705 The following CPU names are recognized:
29706 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29707 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29708 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29709 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29710 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29711 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29712 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29716 const char * md_shortopts
= "m:k";
29718 #ifdef ARM_BI_ENDIAN
29719 #define OPTION_EB (OPTION_MD_BASE + 0)
29720 #define OPTION_EL (OPTION_MD_BASE + 1)
29722 #if TARGET_BYTES_BIG_ENDIAN
29723 #define OPTION_EB (OPTION_MD_BASE + 0)
29725 #define OPTION_EL (OPTION_MD_BASE + 1)
29728 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29729 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29731 struct option md_longopts
[] =
29734 {"EB", no_argument
, NULL
, OPTION_EB
},
29737 {"EL", no_argument
, NULL
, OPTION_EL
},
29739 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29741 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29743 {NULL
, no_argument
, NULL
, 0}
29746 size_t md_longopts_size
= sizeof (md_longopts
);
29748 struct arm_option_table
29750 const char * option
; /* Option name to match. */
29751 const char * help
; /* Help information. */
29752 int * var
; /* Variable to change. */
29753 int value
; /* What to change it to. */
29754 const char * deprecated
; /* If non-null, print this message. */
29757 struct arm_option_table arm_opts
[] =
29759 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29760 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29761 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29762 &support_interwork
, 1, NULL
},
29763 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29764 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29765 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29767 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29768 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29769 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29770 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29773 /* These are recognized by the assembler, but have no affect on code. */
29774 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29775 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29777 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29778 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29779 &warn_on_deprecated
, 0, NULL
},
29780 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29781 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29782 {NULL
, NULL
, NULL
, 0, NULL
}
29785 struct arm_legacy_option_table
29787 const char * option
; /* Option name to match. */
29788 const arm_feature_set
** var
; /* Variable to change. */
29789 const arm_feature_set value
; /* What to change it to. */
29790 const char * deprecated
; /* If non-null, print this message. */
29793 const struct arm_legacy_option_table arm_legacy_opts
[] =
29795 /* DON'T add any new processors to this list -- we want the whole list
29796 to go away... Add them to the processors table instead. */
29797 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29798 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29799 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29800 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29801 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29802 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29803 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29804 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29805 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29806 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29807 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29808 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29809 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29810 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29811 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29812 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29813 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29814 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29815 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29816 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29817 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29818 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29819 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29820 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29821 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29822 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29823 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29824 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29825 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29826 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29827 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29828 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29829 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29830 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29831 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29832 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29833 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29834 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29835 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29836 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29837 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29838 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29839 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29840 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29841 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29842 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29843 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29844 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29845 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29846 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29847 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29848 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29849 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29850 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29851 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29852 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29853 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29854 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29855 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29856 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29857 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29858 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29859 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29860 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29861 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29862 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29863 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29864 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29865 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29866 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29867 N_("use -mcpu=strongarm110")},
29868 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29869 N_("use -mcpu=strongarm1100")},
29870 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29871 N_("use -mcpu=strongarm1110")},
29872 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29873 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29874 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29876 /* Architecture variants -- don't add any more to this list either. */
29877 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29878 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29879 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29880 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29881 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29882 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29883 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29884 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29885 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29886 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29887 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29888 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29889 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29890 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29891 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29892 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29893 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29894 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29896 /* Floating point variants -- don't add any more to this list either. */
29897 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29898 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29899 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29900 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29901 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29903 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29906 struct arm_cpu_option_table
29910 const arm_feature_set value
;
29911 const arm_feature_set ext
;
29912 /* For some CPUs we assume an FPU unless the user explicitly sets
29914 const arm_feature_set default_fpu
;
29915 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29917 const char * canonical_name
;
29920 /* This list should, at a minimum, contain all the cpu names
29921 recognized by GCC. */
29922 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29924 static const struct arm_cpu_option_table arm_cpus
[] =
29926 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29929 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29932 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29935 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29938 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29941 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
29944 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
29947 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
29950 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
29953 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
29956 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
29959 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
29962 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
29965 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
29968 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
29971 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
29974 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
29977 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
29980 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
29983 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
29986 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
29989 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
29992 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
29995 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
29998 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30001 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30004 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30007 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30010 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30013 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30016 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30019 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30022 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30025 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30028 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30031 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30034 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30037 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30040 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30043 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30046 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30049 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30052 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30055 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30058 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30061 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30065 /* For V5 or later processors we default to using VFP; but the user
30066 should really set the FPU type explicitly. */
30067 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30070 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30073 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30076 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30079 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30082 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30085 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30088 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30091 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30094 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30097 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30100 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30103 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30106 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30109 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30112 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30115 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30118 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30121 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30124 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30127 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30130 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30133 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30136 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30139 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30142 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30145 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30148 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30151 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30154 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30157 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30160 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30163 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30166 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30169 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30172 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30175 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30176 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30178 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30180 FPU_ARCH_NEON_VFP_V4
),
30181 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30182 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30183 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30184 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30185 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30186 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30187 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30189 FPU_ARCH_NEON_VFP_V4
),
30190 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30192 FPU_ARCH_NEON_VFP_V4
),
30193 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30195 FPU_ARCH_NEON_VFP_V4
),
30196 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30197 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30198 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30199 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30200 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30201 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30202 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30203 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30204 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30205 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30206 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30207 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30208 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30209 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30210 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30211 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30212 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30213 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30214 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30215 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30216 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30217 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30219 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30220 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30222 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30223 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30225 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30226 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30229 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30231 FPU_ARCH_VFP_V3D16
),
30232 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30233 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30235 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30236 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30237 FPU_ARCH_VFP_V3D16
),
30238 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30239 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30240 FPU_ARCH_VFP_V3D16
),
30241 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30242 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30243 FPU_ARCH_NEON_VFP_ARMV8
),
30244 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30245 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30247 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30250 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30253 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30256 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30259 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30262 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30265 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30268 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30269 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30270 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30271 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30272 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30273 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30274 /* ??? XSCALE is really an architecture. */
30275 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30279 /* ??? iwmmxt is not a processor. */
30280 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30283 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30286 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30291 ARM_CPU_OPT ("ep9312", "ARM920T",
30292 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30293 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30295 /* Marvell processors. */
30296 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30297 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30298 FPU_ARCH_VFP_V3D16
),
30299 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30300 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30301 FPU_ARCH_NEON_VFP_V4
),
30303 /* APM X-Gene family. */
30304 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30306 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30307 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30308 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30309 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30311 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30315 struct arm_ext_table
30319 const arm_feature_set merge
;
30320 const arm_feature_set clear
;
30323 struct arm_arch_option_table
30327 const arm_feature_set value
;
30328 const arm_feature_set default_fpu
;
30329 const struct arm_ext_table
* ext_table
;
30332 /* Used to add support for +E and +noE extension. */
30333 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30334 /* Used to add support for a +E extension. */
30335 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30336 /* Used to add support for a +noE extension. */
30337 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30339 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30340 ~0 & ~FPU_ENDIAN_PURE)
30342 static const struct arm_ext_table armv5te_ext_table
[] =
30344 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30345 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30348 static const struct arm_ext_table armv7_ext_table
[] =
30350 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30351 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30354 static const struct arm_ext_table armv7ve_ext_table
[] =
30356 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30357 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30358 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30359 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30360 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30361 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30362 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30364 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30365 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30367 /* Aliases for +simd. */
30368 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30370 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30371 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30372 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30374 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30377 static const struct arm_ext_table armv7a_ext_table
[] =
30379 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30380 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30381 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30382 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30383 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30384 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30385 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30387 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30388 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30390 /* Aliases for +simd. */
30391 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30392 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30394 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30395 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30397 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30398 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30399 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30402 static const struct arm_ext_table armv7r_ext_table
[] =
30404 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30405 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30406 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30407 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30408 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30409 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30410 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30411 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30412 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30415 static const struct arm_ext_table armv7em_ext_table
[] =
30417 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30418 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30419 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30420 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30421 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30422 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30423 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30426 static const struct arm_ext_table armv8a_ext_table
[] =
30428 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30429 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30430 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30431 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30433 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30434 should use the +simd option to turn on FP. */
30435 ARM_REMOVE ("fp", ALL_FP
),
30436 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30437 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30438 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30442 static const struct arm_ext_table armv81a_ext_table
[] =
30444 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30445 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30446 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30448 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30449 should use the +simd option to turn on FP. */
30450 ARM_REMOVE ("fp", ALL_FP
),
30451 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30452 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30453 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30456 static const struct arm_ext_table armv82a_ext_table
[] =
30458 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30459 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30460 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30461 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30462 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30463 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30465 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30466 should use the +simd option to turn on FP. */
30467 ARM_REMOVE ("fp", ALL_FP
),
30468 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30469 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30470 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30473 static const struct arm_ext_table armv84a_ext_table
[] =
30475 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30476 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30477 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30478 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30480 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30481 should use the +simd option to turn on FP. */
30482 ARM_REMOVE ("fp", ALL_FP
),
30483 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30484 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30485 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30488 static const struct arm_ext_table armv85a_ext_table
[] =
30490 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30491 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30492 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30493 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30495 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30496 should use the +simd option to turn on FP. */
30497 ARM_REMOVE ("fp", ALL_FP
),
30498 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30501 static const struct arm_ext_table armv8m_main_ext_table
[] =
30503 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30504 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30505 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30506 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30507 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30510 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30512 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30513 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30515 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30516 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30519 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30520 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30521 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30522 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30524 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30525 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30526 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30527 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30530 static const struct arm_ext_table armv8r_ext_table
[] =
30532 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30533 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30534 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30535 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30536 ARM_REMOVE ("fp", ALL_FP
),
30537 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30538 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30541 /* This list should, at a minimum, contain all the architecture names
30542 recognized by GCC. */
30543 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30544 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30545 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30547 static const struct arm_arch_option_table arm_archs
[] =
30549 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30550 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30551 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30552 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30553 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30554 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30555 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30556 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30557 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30558 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30559 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30560 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30561 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30562 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30563 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30564 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30565 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30566 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30567 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30568 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30569 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30570 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30571 kept to preserve existing behaviour. */
30572 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30573 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30574 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30575 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30576 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30577 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30578 kept to preserve existing behaviour. */
30579 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30580 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30581 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30582 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30583 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30584 /* The official spelling of the ARMv7 profile variants is the dashed form.
30585 Accept the non-dashed form for compatibility with old toolchains. */
30586 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30587 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30588 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30589 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30590 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30591 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30592 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30593 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30594 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30595 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30597 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30599 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30600 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30601 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30602 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30603 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30604 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30605 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30606 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30607 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30608 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30609 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30611 #undef ARM_ARCH_OPT
30613 /* ISA extensions in the co-processor and main instruction set space. */
30615 struct arm_option_extension_value_table
30619 const arm_feature_set merge_value
;
30620 const arm_feature_set clear_value
;
30621 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30622 indicates that an extension is available for all architectures while
30623 ARM_ANY marks an empty entry. */
30624 const arm_feature_set allowed_archs
[2];
30627 /* The following table must be in alphabetical order with a NULL last entry. */
30629 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30630 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30632 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30633 use the context sensitive approach using arm_ext_table's. */
30634 static const struct arm_option_extension_value_table arm_extensions
[] =
30636 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30637 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30638 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30639 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30640 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30641 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30642 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30644 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30645 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30646 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30647 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30648 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30649 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30650 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30652 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30653 | ARM_EXT2_FP16_FML
),
30654 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30655 | ARM_EXT2_FP16_FML
),
30657 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30658 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30659 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30660 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30661 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30662 Thumb divide instruction. Due to this having the same name as the
30663 previous entry, this will be ignored when doing command-line parsing and
30664 only considered by build attribute selection code. */
30665 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30666 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30667 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30668 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30669 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30670 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30671 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30672 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30673 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30674 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30675 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30676 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30677 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30678 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30679 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30680 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30681 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30682 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30683 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30684 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30685 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30687 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30688 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30689 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30690 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30691 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30692 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30693 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30694 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30696 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30697 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30698 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30699 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30700 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30701 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30702 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30703 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30705 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30706 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30707 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30708 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30709 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30713 /* ISA floating-point and Advanced SIMD extensions. */
30714 struct arm_option_fpu_value_table
30717 const arm_feature_set value
;
30720 /* This list should, at a minimum, contain all the fpu names
30721 recognized by GCC. */
30722 static const struct arm_option_fpu_value_table arm_fpus
[] =
30724 {"softfpa", FPU_NONE
},
30725 {"fpe", FPU_ARCH_FPE
},
30726 {"fpe2", FPU_ARCH_FPE
},
30727 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30728 {"fpa", FPU_ARCH_FPA
},
30729 {"fpa10", FPU_ARCH_FPA
},
30730 {"fpa11", FPU_ARCH_FPA
},
30731 {"arm7500fe", FPU_ARCH_FPA
},
30732 {"softvfp", FPU_ARCH_VFP
},
30733 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30734 {"vfp", FPU_ARCH_VFP_V2
},
30735 {"vfp9", FPU_ARCH_VFP_V2
},
30736 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30737 {"vfp10", FPU_ARCH_VFP_V2
},
30738 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30739 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30740 {"vfpv2", FPU_ARCH_VFP_V2
},
30741 {"vfpv3", FPU_ARCH_VFP_V3
},
30742 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30743 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30744 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30745 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30746 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30747 {"arm1020t", FPU_ARCH_VFP_V1
},
30748 {"arm1020e", FPU_ARCH_VFP_V2
},
30749 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30750 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30751 {"maverick", FPU_ARCH_MAVERICK
},
30752 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30753 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30754 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30755 {"vfpv4", FPU_ARCH_VFP_V4
},
30756 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30757 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30758 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30759 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30760 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30761 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30762 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30763 {"crypto-neon-fp-armv8",
30764 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30765 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30766 {"crypto-neon-fp-armv8.1",
30767 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30768 {NULL
, ARM_ARCH_NONE
}
30771 struct arm_option_value_table
30777 static const struct arm_option_value_table arm_float_abis
[] =
30779 {"hard", ARM_FLOAT_ABI_HARD
},
30780 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30781 {"soft", ARM_FLOAT_ABI_SOFT
},
30786 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30787 static const struct arm_option_value_table arm_eabis
[] =
30789 {"gnu", EF_ARM_EABI_UNKNOWN
},
30790 {"4", EF_ARM_EABI_VER4
},
30791 {"5", EF_ARM_EABI_VER5
},
30796 struct arm_long_option_table
30798 const char * option
; /* Substring to match. */
30799 const char * help
; /* Help information. */
30800 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30801 const char * deprecated
; /* If non-null, print this message. */
30805 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30806 arm_feature_set
*ext_set
,
30807 const struct arm_ext_table
*ext_table
)
30809 /* We insist on extensions being specified in alphabetical order, and with
30810 extensions being added before being removed. We achieve this by having
30811 the global ARM_EXTENSIONS table in alphabetical order, and using the
30812 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30813 or removing it (0) and only allowing it to change in the order
30815 const struct arm_option_extension_value_table
* opt
= NULL
;
30816 const arm_feature_set arm_any
= ARM_ANY
;
30817 int adding_value
= -1;
30819 while (str
!= NULL
&& *str
!= 0)
30826 as_bad (_("invalid architectural extension"));
30831 ext
= strchr (str
, '+');
30836 len
= strlen (str
);
30838 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30840 if (adding_value
!= 0)
30843 opt
= arm_extensions
;
30851 if (adding_value
== -1)
30854 opt
= arm_extensions
;
30856 else if (adding_value
!= 1)
30858 as_bad (_("must specify extensions to add before specifying "
30859 "those to remove"));
30866 as_bad (_("missing architectural extension"));
30870 gas_assert (adding_value
!= -1);
30871 gas_assert (opt
!= NULL
);
30873 if (ext_table
!= NULL
)
30875 const struct arm_ext_table
* ext_opt
= ext_table
;
30876 bfd_boolean found
= FALSE
;
30877 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30878 if (ext_opt
->name_len
== len
30879 && strncmp (ext_opt
->name
, str
, len
) == 0)
30883 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30884 /* TODO: Option not supported. When we remove the
30885 legacy table this case should error out. */
30888 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30892 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30893 /* TODO: Option not supported. When we remove the
30894 legacy table this case should error out. */
30896 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30908 /* Scan over the options table trying to find an exact match. */
30909 for (; opt
->name
!= NULL
; opt
++)
30910 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30912 int i
, nb_allowed_archs
=
30913 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30914 /* Check we can apply the extension to this architecture. */
30915 for (i
= 0; i
< nb_allowed_archs
; i
++)
30918 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30920 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30923 if (i
== nb_allowed_archs
)
30925 as_bad (_("extension does not apply to the base architecture"));
30929 /* Add or remove the extension. */
30931 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30933 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30935 /* Allowing Thumb division instructions for ARMv7 in autodetection
30936 rely on this break so that duplicate extensions (extensions
30937 with the same name as a previous extension in the list) are not
30938 considered for command-line parsing. */
30942 if (opt
->name
== NULL
)
30944 /* Did we fail to find an extension because it wasn't specified in
30945 alphabetical order, or because it does not exist? */
30947 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30948 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30951 if (opt
->name
== NULL
)
30952 as_bad (_("unknown architectural extension `%s'"), str
);
30954 as_bad (_("architectural extensions must be specified in "
30955 "alphabetical order"));
30961 /* We should skip the extension we've just matched the next time
30973 arm_parse_cpu (const char *str
)
30975 const struct arm_cpu_option_table
*opt
;
30976 const char *ext
= strchr (str
, '+');
30982 len
= strlen (str
);
30986 as_bad (_("missing cpu name `%s'"), str
);
30990 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
30991 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30993 mcpu_cpu_opt
= &opt
->value
;
30994 if (mcpu_ext_opt
== NULL
)
30995 mcpu_ext_opt
= XNEW (arm_feature_set
);
30996 *mcpu_ext_opt
= opt
->ext
;
30997 mcpu_fpu_opt
= &opt
->default_fpu
;
30998 if (opt
->canonical_name
)
31000 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31001 strcpy (selected_cpu_name
, opt
->canonical_name
);
31007 if (len
>= sizeof selected_cpu_name
)
31008 len
= (sizeof selected_cpu_name
) - 1;
31010 for (i
= 0; i
< len
; i
++)
31011 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31012 selected_cpu_name
[i
] = 0;
31016 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31021 as_bad (_("unknown cpu `%s'"), str
);
31026 arm_parse_arch (const char *str
)
31028 const struct arm_arch_option_table
*opt
;
31029 const char *ext
= strchr (str
, '+');
31035 len
= strlen (str
);
31039 as_bad (_("missing architecture name `%s'"), str
);
31043 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31044 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31046 march_cpu_opt
= &opt
->value
;
31047 if (march_ext_opt
== NULL
)
31048 march_ext_opt
= XNEW (arm_feature_set
);
31049 *march_ext_opt
= arm_arch_none
;
31050 march_fpu_opt
= &opt
->default_fpu
;
31051 strcpy (selected_cpu_name
, opt
->name
);
31054 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31060 as_bad (_("unknown architecture `%s'\n"), str
);
31065 arm_parse_fpu (const char * str
)
31067 const struct arm_option_fpu_value_table
* opt
;
31069 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31070 if (streq (opt
->name
, str
))
31072 mfpu_opt
= &opt
->value
;
31076 as_bad (_("unknown floating point format `%s'\n"), str
);
31081 arm_parse_float_abi (const char * str
)
31083 const struct arm_option_value_table
* opt
;
31085 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31086 if (streq (opt
->name
, str
))
31088 mfloat_abi_opt
= opt
->value
;
31092 as_bad (_("unknown floating point abi `%s'\n"), str
);
31098 arm_parse_eabi (const char * str
)
31100 const struct arm_option_value_table
*opt
;
31102 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31103 if (streq (opt
->name
, str
))
31105 meabi_flags
= opt
->value
;
31108 as_bad (_("unknown EABI `%s'\n"), str
);
31114 arm_parse_it_mode (const char * str
)
31116 bfd_boolean ret
= TRUE
;
31118 if (streq ("arm", str
))
31119 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31120 else if (streq ("thumb", str
))
31121 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31122 else if (streq ("always", str
))
31123 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31124 else if (streq ("never", str
))
31125 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31128 as_bad (_("unknown implicit IT mode `%s', should be "\
31129 "arm, thumb, always, or never."), str
);
31137 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31139 codecomposer_syntax
= TRUE
;
31140 arm_comment_chars
[0] = ';';
31141 arm_line_separator_chars
[0] = 0;
31145 struct arm_long_option_table arm_long_opts
[] =
31147 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31148 arm_parse_cpu
, NULL
},
31149 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31150 arm_parse_arch
, NULL
},
31151 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31152 arm_parse_fpu
, NULL
},
31153 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31154 arm_parse_float_abi
, NULL
},
31156 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31157 arm_parse_eabi
, NULL
},
31159 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31160 arm_parse_it_mode
, NULL
},
31161 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31162 arm_ccs_mode
, NULL
},
31163 {NULL
, NULL
, 0, NULL
}
31167 md_parse_option (int c
, const char * arg
)
31169 struct arm_option_table
*opt
;
31170 const struct arm_legacy_option_table
*fopt
;
31171 struct arm_long_option_table
*lopt
;
31177 target_big_endian
= 1;
31183 target_big_endian
= 0;
31187 case OPTION_FIX_V4BX
:
31195 #endif /* OBJ_ELF */
31198 /* Listing option. Just ignore these, we don't support additional
31203 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31205 if (c
== opt
->option
[0]
31206 && ((arg
== NULL
&& opt
->option
[1] == 0)
31207 || streq (arg
, opt
->option
+ 1)))
31209 /* If the option is deprecated, tell the user. */
31210 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31211 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31212 arg
? arg
: "", _(opt
->deprecated
));
31214 if (opt
->var
!= NULL
)
31215 *opt
->var
= opt
->value
;
31221 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31223 if (c
== fopt
->option
[0]
31224 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31225 || streq (arg
, fopt
->option
+ 1)))
31227 /* If the option is deprecated, tell the user. */
31228 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31229 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31230 arg
? arg
: "", _(fopt
->deprecated
));
31232 if (fopt
->var
!= NULL
)
31233 *fopt
->var
= &fopt
->value
;
31239 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31241 /* These options are expected to have an argument. */
31242 if (c
== lopt
->option
[0]
31244 && strncmp (arg
, lopt
->option
+ 1,
31245 strlen (lopt
->option
+ 1)) == 0)
31247 /* If the option is deprecated, tell the user. */
31248 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31249 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31250 _(lopt
->deprecated
));
31252 /* Call the sup-option parser. */
31253 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31264 md_show_usage (FILE * fp
)
31266 struct arm_option_table
*opt
;
31267 struct arm_long_option_table
*lopt
;
31269 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31271 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31272 if (opt
->help
!= NULL
)
31273 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31275 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31276 if (lopt
->help
!= NULL
)
31277 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31281 -EB assemble code for a big-endian cpu\n"));
31286 -EL assemble code for a little-endian cpu\n"));
31290 --fix-v4bx Allow BX in ARMv4 code\n"));
31294 --fdpic generate an FDPIC object file\n"));
31295 #endif /* OBJ_ELF */
31303 arm_feature_set flags
;
31304 } cpu_arch_ver_table
;
31306 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31307 chronologically for architectures, with an exception for ARMv6-M and
31308 ARMv6S-M due to legacy reasons. No new architecture should have a
31309 special case. This allows for build attribute selection results to be
31310 stable when new architectures are added. */
31311 static const cpu_arch_ver_table cpu_arch_ver
[] =
31313 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31314 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31315 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31316 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31317 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31318 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31319 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31320 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31321 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31322 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31323 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31324 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31325 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31326 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31327 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31328 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31329 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31330 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31331 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31332 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31333 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31334 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31335 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31336 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31338 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31339 always selected build attributes to match those of ARMv6-M
31340 (resp. ARMv6S-M). However, due to these architectures being a strict
31341 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31342 would be selected when fully respecting chronology of architectures.
31343 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31344 move them before ARMv7 architectures. */
31345 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31346 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31348 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31349 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31350 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31351 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31352 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31353 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31354 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31355 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31356 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31357 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31358 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31359 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31360 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31361 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31362 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31363 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31364 {-1, ARM_ARCH_NONE
}
31367 /* Set an attribute if it has not already been set by the user. */
31370 aeabi_set_attribute_int (int tag
, int value
)
31373 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31374 || !attributes_set_explicitly
[tag
])
31375 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31379 aeabi_set_attribute_string (int tag
, const char *value
)
31382 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31383 || !attributes_set_explicitly
[tag
])
31384 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31387 /* Return whether features in the *NEEDED feature set are available via
31388 extensions for the architecture whose feature set is *ARCH_FSET. */
31391 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31392 const arm_feature_set
*needed
)
31394 int i
, nb_allowed_archs
;
31395 arm_feature_set ext_fset
;
31396 const struct arm_option_extension_value_table
*opt
;
31398 ext_fset
= arm_arch_none
;
31399 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31401 /* Extension does not provide any feature we need. */
31402 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31406 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31407 for (i
= 0; i
< nb_allowed_archs
; i
++)
31410 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31413 /* Extension is available, add it. */
31414 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31415 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31419 /* Can we enable all features in *needed? */
31420 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31423 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31424 a given architecture feature set *ARCH_EXT_FSET including extension feature
31425 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31426 - if true, check for an exact match of the architecture modulo extensions;
31427 - otherwise, select build attribute value of the first superset
31428 architecture released so that results remains stable when new architectures
31430 For -march/-mcpu=all the build attribute value of the most featureful
31431 architecture is returned. Tag_CPU_arch_profile result is returned in
31435 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31436 const arm_feature_set
*ext_fset
,
31437 char *profile
, int exact_match
)
31439 arm_feature_set arch_fset
;
31440 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31442 /* Select most featureful architecture with all its extensions if building
31443 for -march=all as the feature sets used to set build attributes. */
31444 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31446 /* Force revisiting of decision for each new architecture. */
31447 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31449 return TAG_CPU_ARCH_V8
;
31452 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31454 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31456 arm_feature_set known_arch_fset
;
31458 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31461 /* Base architecture match user-specified architecture and
31462 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31463 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31468 /* Base architecture match user-specified architecture only
31469 (eg. ARMv6-M in the same case as above). Record it in case we
31470 find a match with above condition. */
31471 else if (p_ver_ret
== NULL
31472 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31478 /* Architecture has all features wanted. */
31479 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31481 arm_feature_set added_fset
;
31483 /* Compute features added by this architecture over the one
31484 recorded in p_ver_ret. */
31485 if (p_ver_ret
!= NULL
)
31486 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31488 /* First architecture that match incl. with extensions, or the
31489 only difference in features over the recorded match is
31490 features that were optional and are now mandatory. */
31491 if (p_ver_ret
== NULL
31492 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31498 else if (p_ver_ret
== NULL
)
31500 arm_feature_set needed_ext_fset
;
31502 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31504 /* Architecture has all features needed when using some
31505 extensions. Record it and continue searching in case there
31506 exist an architecture providing all needed features without
31507 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31509 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31516 if (p_ver_ret
== NULL
)
31520 /* Tag_CPU_arch_profile. */
31521 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31522 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31523 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31524 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31526 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31528 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31532 return p_ver_ret
->val
;
31535 /* Set the public EABI object attributes. */
31538 aeabi_set_public_attributes (void)
31540 char profile
= '\0';
31543 int fp16_optional
= 0;
31544 int skip_exact_match
= 0;
31545 arm_feature_set flags
, flags_arch
, flags_ext
;
31547 /* Autodetection mode, choose the architecture based the instructions
31549 if (no_cpu_selected ())
31551 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31553 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31554 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31556 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31557 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31559 /* Code run during relaxation relies on selected_cpu being set. */
31560 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31561 flags_ext
= arm_arch_none
;
31562 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31563 selected_ext
= flags_ext
;
31564 selected_cpu
= flags
;
31566 /* Otherwise, choose the architecture based on the capabilities of the
31570 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31571 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31572 flags_ext
= selected_ext
;
31573 flags
= selected_cpu
;
31575 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31577 /* Allow the user to override the reported architecture. */
31578 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31580 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31581 flags_ext
= arm_arch_none
;
31584 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31586 /* When this function is run again after relaxation has happened there is no
31587 way to determine whether an architecture or CPU was specified by the user:
31588 - selected_cpu is set above for relaxation to work;
31589 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31590 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31591 Therefore, if not in -march=all case we first try an exact match and fall
31592 back to autodetection. */
31593 if (!skip_exact_match
)
31594 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31596 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31598 as_bad (_("no architecture contains all the instructions used\n"));
31600 /* Tag_CPU_name. */
31601 if (selected_cpu_name
[0])
31605 q
= selected_cpu_name
;
31606 if (strncmp (q
, "armv", 4) == 0)
31611 for (i
= 0; q
[i
]; i
++)
31612 q
[i
] = TOUPPER (q
[i
]);
31614 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31617 /* Tag_CPU_arch. */
31618 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31620 /* Tag_CPU_arch_profile. */
31621 if (profile
!= '\0')
31622 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31624 /* Tag_DSP_extension. */
31625 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31626 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31628 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31629 /* Tag_ARM_ISA_use. */
31630 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31631 || ARM_FEATURE_ZERO (flags_arch
))
31632 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31634 /* Tag_THUMB_ISA_use. */
31635 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31636 || ARM_FEATURE_ZERO (flags_arch
))
31640 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31641 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31643 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31647 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31650 /* Tag_VFP_arch. */
31651 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31652 aeabi_set_attribute_int (Tag_VFP_arch
,
31653 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31655 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31656 aeabi_set_attribute_int (Tag_VFP_arch
,
31657 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31659 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31662 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31664 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31666 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31669 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31670 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31671 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31672 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31673 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31675 /* Tag_ABI_HardFP_use. */
31676 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31677 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31678 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31680 /* Tag_WMMX_arch. */
31681 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31682 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31683 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31684 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31686 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31687 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31688 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31689 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31690 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31691 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31693 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31695 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31699 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31704 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31705 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31706 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31707 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31709 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31710 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31711 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31715 We set Tag_DIV_use to two when integer divide instructions have been used
31716 in ARM state, or when Thumb integer divide instructions have been used,
31717 but we have no architecture profile set, nor have we any ARM instructions.
31719 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31720 by the base architecture.
31722 For new architectures we will have to check these tests. */
31723 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31724 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31725 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31726 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31727 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31728 || (profile
== '\0'
31729 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31730 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31731 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31733 /* Tag_MP_extension_use. */
31734 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31735 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31737 /* Tag Virtualization_use. */
31738 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31740 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31743 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31746 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31747 finished and free extension feature bits which will not be used anymore. */
31750 arm_md_post_relax (void)
31752 aeabi_set_public_attributes ();
31753 XDELETE (mcpu_ext_opt
);
31754 mcpu_ext_opt
= NULL
;
31755 XDELETE (march_ext_opt
);
31756 march_ext_opt
= NULL
;
31759 /* Add the default contents for the .ARM.attributes section. */
31764 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31767 aeabi_set_public_attributes ();
31769 #endif /* OBJ_ELF */
31771 /* Parse a .cpu directive. */
31774 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31776 const struct arm_cpu_option_table
*opt
;
31780 name
= input_line_pointer
;
31781 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31782 input_line_pointer
++;
31783 saved_char
= *input_line_pointer
;
31784 *input_line_pointer
= 0;
31786 /* Skip the first "all" entry. */
31787 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31788 if (streq (opt
->name
, name
))
31790 selected_arch
= opt
->value
;
31791 selected_ext
= opt
->ext
;
31792 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31793 if (opt
->canonical_name
)
31794 strcpy (selected_cpu_name
, opt
->canonical_name
);
31798 for (i
= 0; opt
->name
[i
]; i
++)
31799 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31801 selected_cpu_name
[i
] = 0;
31803 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31805 *input_line_pointer
= saved_char
;
31806 demand_empty_rest_of_line ();
31809 as_bad (_("unknown cpu `%s'"), name
);
31810 *input_line_pointer
= saved_char
;
31811 ignore_rest_of_line ();
31814 /* Parse a .arch directive. */
31817 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31819 const struct arm_arch_option_table
*opt
;
31823 name
= input_line_pointer
;
31824 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31825 input_line_pointer
++;
31826 saved_char
= *input_line_pointer
;
31827 *input_line_pointer
= 0;
31829 /* Skip the first "all" entry. */
31830 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31831 if (streq (opt
->name
, name
))
31833 selected_arch
= opt
->value
;
31834 selected_ext
= arm_arch_none
;
31835 selected_cpu
= selected_arch
;
31836 strcpy (selected_cpu_name
, opt
->name
);
31837 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31838 *input_line_pointer
= saved_char
;
31839 demand_empty_rest_of_line ();
31843 as_bad (_("unknown architecture `%s'\n"), name
);
31844 *input_line_pointer
= saved_char
;
31845 ignore_rest_of_line ();
31848 /* Parse a .object_arch directive. */
31851 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31853 const struct arm_arch_option_table
*opt
;
31857 name
= input_line_pointer
;
31858 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31859 input_line_pointer
++;
31860 saved_char
= *input_line_pointer
;
31861 *input_line_pointer
= 0;
31863 /* Skip the first "all" entry. */
31864 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31865 if (streq (opt
->name
, name
))
31867 selected_object_arch
= opt
->value
;
31868 *input_line_pointer
= saved_char
;
31869 demand_empty_rest_of_line ();
31873 as_bad (_("unknown architecture `%s'\n"), name
);
31874 *input_line_pointer
= saved_char
;
31875 ignore_rest_of_line ();
31878 /* Parse a .arch_extension directive. */
31881 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31883 const struct arm_option_extension_value_table
*opt
;
31886 int adding_value
= 1;
31888 name
= input_line_pointer
;
31889 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31890 input_line_pointer
++;
31891 saved_char
= *input_line_pointer
;
31892 *input_line_pointer
= 0;
31894 if (strlen (name
) >= 2
31895 && strncmp (name
, "no", 2) == 0)
31901 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31902 if (streq (opt
->name
, name
))
31904 int i
, nb_allowed_archs
=
31905 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31906 for (i
= 0; i
< nb_allowed_archs
; i
++)
31909 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31911 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31915 if (i
== nb_allowed_archs
)
31917 as_bad (_("architectural extension `%s' is not allowed for the "
31918 "current base architecture"), name
);
31923 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31926 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31928 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31929 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31930 *input_line_pointer
= saved_char
;
31931 demand_empty_rest_of_line ();
31932 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31933 on this return so that duplicate extensions (extensions with the
31934 same name as a previous extension in the list) are not considered
31935 for command-line parsing. */
31939 if (opt
->name
== NULL
)
31940 as_bad (_("unknown architecture extension `%s'\n"), name
);
31942 *input_line_pointer
= saved_char
;
31943 ignore_rest_of_line ();
31946 /* Parse a .fpu directive. */
31949 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
31951 const struct arm_option_fpu_value_table
*opt
;
31955 name
= input_line_pointer
;
31956 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31957 input_line_pointer
++;
31958 saved_char
= *input_line_pointer
;
31959 *input_line_pointer
= 0;
31961 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31962 if (streq (opt
->name
, name
))
31964 selected_fpu
= opt
->value
;
31965 #ifndef CPU_DEFAULT
31966 if (no_cpu_selected ())
31967 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
31970 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31971 *input_line_pointer
= saved_char
;
31972 demand_empty_rest_of_line ();
31976 as_bad (_("unknown floating point format `%s'\n"), name
);
31977 *input_line_pointer
= saved_char
;
31978 ignore_rest_of_line ();
31981 /* Copy symbol information. */
31984 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
31986 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
31990 /* Given a symbolic attribute NAME, return the proper integer value.
31991 Returns -1 if the attribute is not known. */
31994 arm_convert_symbolic_attribute (const char *name
)
31996 static const struct
32001 attribute_table
[] =
32003 /* When you modify this table you should
32004 also modify the list in doc/c-arm.texi. */
32005 #define T(tag) {#tag, tag}
32006 T (Tag_CPU_raw_name
),
32009 T (Tag_CPU_arch_profile
),
32010 T (Tag_ARM_ISA_use
),
32011 T (Tag_THUMB_ISA_use
),
32015 T (Tag_Advanced_SIMD_arch
),
32016 T (Tag_PCS_config
),
32017 T (Tag_ABI_PCS_R9_use
),
32018 T (Tag_ABI_PCS_RW_data
),
32019 T (Tag_ABI_PCS_RO_data
),
32020 T (Tag_ABI_PCS_GOT_use
),
32021 T (Tag_ABI_PCS_wchar_t
),
32022 T (Tag_ABI_FP_rounding
),
32023 T (Tag_ABI_FP_denormal
),
32024 T (Tag_ABI_FP_exceptions
),
32025 T (Tag_ABI_FP_user_exceptions
),
32026 T (Tag_ABI_FP_number_model
),
32027 T (Tag_ABI_align_needed
),
32028 T (Tag_ABI_align8_needed
),
32029 T (Tag_ABI_align_preserved
),
32030 T (Tag_ABI_align8_preserved
),
32031 T (Tag_ABI_enum_size
),
32032 T (Tag_ABI_HardFP_use
),
32033 T (Tag_ABI_VFP_args
),
32034 T (Tag_ABI_WMMX_args
),
32035 T (Tag_ABI_optimization_goals
),
32036 T (Tag_ABI_FP_optimization_goals
),
32037 T (Tag_compatibility
),
32038 T (Tag_CPU_unaligned_access
),
32039 T (Tag_FP_HP_extension
),
32040 T (Tag_VFP_HP_extension
),
32041 T (Tag_ABI_FP_16bit_format
),
32042 T (Tag_MPextension_use
),
32044 T (Tag_nodefaults
),
32045 T (Tag_also_compatible_with
),
32046 T (Tag_conformance
),
32048 T (Tag_Virtualization_use
),
32049 T (Tag_DSP_extension
),
32051 /* We deliberately do not include Tag_MPextension_use_legacy. */
32059 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32060 if (streq (name
, attribute_table
[i
].name
))
32061 return attribute_table
[i
].tag
;
32066 /* Apply sym value for relocations only in the case that they are for
32067 local symbols in the same segment as the fixup and you have the
32068 respective architectural feature for blx and simple switches. */
32071 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32074 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32075 /* PR 17444: If the local symbol is in a different section then a reloc
32076 will always be generated for it, so applying the symbol value now
32077 will result in a double offset being stored in the relocation. */
32078 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32079 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32081 switch (fixP
->fx_r_type
)
32083 case BFD_RELOC_ARM_PCREL_BLX
:
32084 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32085 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32089 case BFD_RELOC_ARM_PCREL_CALL
:
32090 case BFD_RELOC_THUMB_PCREL_BLX
:
32091 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32102 #endif /* OBJ_ELF */