1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1050 enum fp_16bit_format
1052 ARM_FP16_FORMAT_IEEE
= 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1054 ARM_FP16_FORMAT_DEFAULT
= 0x3
1057 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1061 skip_past_char (char ** str
, char c
)
1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str
);
1075 #define skip_past_comma(str) skip_past_char (str, ',')
1077 /* Arithmetic expressions (possibly involving symbols). */
1079 /* Return TRUE if anything in the expression is a bignum. */
1082 walk_no_bignums (symbolS
* sp
)
1084 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1087 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1089 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1090 || (symbol_get_value_expression (sp
)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1097 static bfd_boolean in_my_get_expression
= FALSE
;
1099 /* Third argument to my_get_expression. */
1100 #define GE_NO_PREFIX 0
1101 #define GE_IMM_PREFIX 1
1102 #define GE_OPT_PREFIX 2
1103 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105 #define GE_OPT_PREFIX_BIG 3
1108 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1112 /* In unified syntax, all prefixes are optional. */
1114 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1117 switch (prefix_mode
)
1119 case GE_NO_PREFIX
: break;
1121 if (!is_immediate_prefix (**str
))
1123 inst
.error
= _("immediate expression requires a # prefix");
1129 case GE_OPT_PREFIX_BIG
:
1130 if (is_immediate_prefix (**str
))
1137 memset (ep
, 0, sizeof (expressionS
));
1139 save_in
= input_line_pointer
;
1140 input_line_pointer
= *str
;
1141 in_my_get_expression
= TRUE
;
1143 in_my_get_expression
= FALSE
;
1145 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1147 /* We found a bad or missing expression in md_operand(). */
1148 *str
= input_line_pointer
;
1149 input_line_pointer
= save_in
;
1150 if (inst
.error
== NULL
)
1151 inst
.error
= (ep
->X_op
== O_absent
1152 ? _("missing expression") :_("bad expression"));
1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
1159 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1160 && (ep
->X_op
== O_big
1161 || (ep
->X_add_symbol
1162 && (walk_no_bignums (ep
->X_add_symbol
)
1164 && walk_no_bignums (ep
->X_op_symbol
))))))
1166 inst
.error
= _("invalid constant");
1167 *str
= input_line_pointer
;
1168 input_line_pointer
= save_in
;
1172 *str
= input_line_pointer
;
1173 input_line_pointer
= save_in
;
1177 /* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1192 md_atof (int type
, char * litP
, int * sizeP
)
1195 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1232 return _("Unrecognized or unsupported floating point constant");
1235 t
= atof_ieee (input_line_pointer
, type
, words
);
1237 input_line_pointer
= t
;
1238 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1240 if (target_big_endian
|| prec
== 1)
1241 for (i
= 0; i
< prec
; i
++)
1243 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1244 litP
+= sizeof (LITTLENUM_TYPE
);
1246 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1247 for (i
= prec
- 1; i
>= 0; i
--)
1249 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1250 litP
+= sizeof (LITTLENUM_TYPE
);
1253 /* For a 4 byte float the order of elements in `words' is 1 0.
1254 For an 8 byte float the order is 1 0 3 2. */
1255 for (i
= 0; i
< prec
; i
+= 2)
1257 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1258 sizeof (LITTLENUM_TYPE
));
1259 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1260 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1261 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1267 /* We handle all bad expressions here, so that we can report the faulty
1268 instruction in the error message. */
1271 md_operand (expressionS
* exp
)
1273 if (in_my_get_expression
)
1274 exp
->X_op
= O_illegal
;
1277 /* Immediate values. */
1280 /* Generic immediate-value read function for use in directives.
1281 Accepts anything that 'expression' can fold to a constant.
1282 *val receives the number. */
1285 immediate_for_directive (int *val
)
1288 exp
.X_op
= O_illegal
;
1290 if (is_immediate_prefix (*input_line_pointer
))
1292 input_line_pointer
++;
1296 if (exp
.X_op
!= O_constant
)
1298 as_bad (_("expected #constant"));
1299 ignore_rest_of_line ();
1302 *val
= exp
.X_add_number
;
1307 /* Register parsing. */
1309 /* Generic register parser. CCP points to what should be the
1310 beginning of a register name. If it is indeed a valid register
1311 name, advance CCP over it and return the reg_entry structure;
1312 otherwise return NULL. Does not issue diagnostics. */
1314 static struct reg_entry
*
1315 arm_reg_parse_multi (char **ccp
)
1319 struct reg_entry
*reg
;
1321 skip_whitespace (start
);
1323 #ifdef REGISTER_PREFIX
1324 if (*start
!= REGISTER_PREFIX
)
1328 #ifdef OPTIONAL_REGISTER_PREFIX
1329 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1334 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1339 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1341 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1351 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1352 enum arm_reg_type type
)
1354 /* Alternative syntaxes are accepted for a few register classes. */
1361 /* Generic coprocessor register names are allowed for these. */
1362 if (reg
&& reg
->type
== REG_TYPE_CN
)
1367 /* For backward compatibility, a bare number is valid here. */
1369 unsigned long processor
= strtoul (start
, ccp
, 10);
1370 if (*ccp
!= start
&& processor
<= 15)
1375 case REG_TYPE_MMXWC
:
1376 /* WC includes WCG. ??? I'm not sure this is true for all
1377 instructions that take WC registers. */
1378 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1389 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1390 return value is the register number or FAIL. */
1393 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1396 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1399 /* Do not allow a scalar (reg+index) to parse as a register. */
1400 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1403 if (reg
&& reg
->type
== type
)
1406 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1413 /* Parse a Neon type specifier. *STR should point at the leading '.'
1414 character. Does no verification at this stage that the type fits the opcode
1421 Can all be legally parsed by this function.
1423 Fills in neon_type struct pointer with parsed information, and updates STR
1424 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1425 type, FAIL if not. */
1428 parse_neon_type (struct neon_type
*type
, char **str
)
1435 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1437 enum neon_el_type thistype
= NT_untyped
;
1438 unsigned thissize
= -1u;
1445 /* Just a size without an explicit type. */
1449 switch (TOLOWER (*ptr
))
1451 case 'i': thistype
= NT_integer
; break;
1452 case 'f': thistype
= NT_float
; break;
1453 case 'p': thistype
= NT_poly
; break;
1454 case 's': thistype
= NT_signed
; break;
1455 case 'u': thistype
= NT_unsigned
; break;
1457 thistype
= NT_float
;
1462 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1468 /* .f is an abbreviation for .f32. */
1469 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1474 thissize
= strtoul (ptr
, &ptr
, 10);
1476 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1479 as_bad (_("bad size %d in type specifier"), thissize
);
1487 type
->el
[type
->elems
].type
= thistype
;
1488 type
->el
[type
->elems
].size
= thissize
;
1493 /* Empty/missing type is not a successful parse. */
1494 if (type
->elems
== 0)
1502 /* Errors may be set multiple times during parsing or bit encoding
1503 (particularly in the Neon bits), but usually the earliest error which is set
1504 will be the most meaningful. Avoid overwriting it with later (cascading)
1505 errors by calling this function. */
1508 first_error (const char *err
)
1514 /* Parse a single type, e.g. ".s32", leading period included. */
1516 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1519 struct neon_type optype
;
1523 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1525 if (optype
.elems
== 1)
1526 *vectype
= optype
.el
[0];
1529 first_error (_("only one type should be specified for operand"));
1535 first_error (_("vector type expected"));
1547 /* Special meanings for indices (which have a range of 0-7), which will fit into
1550 #define NEON_ALL_LANES 15
1551 #define NEON_INTERLEAVE_LANES 14
1553 /* Record a use of the given feature. */
1555 record_feature_use (const arm_feature_set
*feature
)
1558 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1560 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1563 /* If the given feature available in the selected CPU, mark it as used.
1564 Returns TRUE iff feature is available. */
1566 mark_feature_used (const arm_feature_set
*feature
)
1569 /* Do not support the use of MVE only instructions when in auto-detection or
1571 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1572 && ARM_CPU_IS_ANY (cpu_variant
))
1574 first_error (BAD_MVE_AUTO
);
1577 /* Ensure the option is valid on the current architecture. */
1578 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1581 /* Add the appropriate architecture feature for the barrier option used.
1583 record_feature_use (feature
);
1588 /* Parse either a register or a scalar, with an optional type. Return the
1589 register number, and optionally fill in the actual type of the register
1590 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1591 type/index information in *TYPEINFO. */
1594 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1595 enum arm_reg_type
*rtype
,
1596 struct neon_typed_alias
*typeinfo
)
1599 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1600 struct neon_typed_alias atype
;
1601 struct neon_type_el parsetype
;
1605 atype
.eltype
.type
= NT_invtype
;
1606 atype
.eltype
.size
= -1;
1608 /* Try alternate syntax for some types of register. Note these are mutually
1609 exclusive with the Neon syntax extensions. */
1612 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1620 /* Undo polymorphism when a set of register types may be accepted. */
1621 if ((type
== REG_TYPE_NDQ
1622 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1623 || (type
== REG_TYPE_VFSD
1624 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1625 || (type
== REG_TYPE_NSDQ
1626 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1627 || reg
->type
== REG_TYPE_NQ
))
1628 || (type
== REG_TYPE_NSD
1629 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1630 || (type
== REG_TYPE_MMXWC
1631 && (reg
->type
== REG_TYPE_MMXWCG
)))
1632 type
= (enum arm_reg_type
) reg
->type
;
1634 if (type
== REG_TYPE_MQ
)
1636 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1639 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1642 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1644 first_error (_("expected MVE register [q0..q7]"));
1649 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1650 && (type
== REG_TYPE_NQ
))
1654 if (type
!= reg
->type
)
1660 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1662 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1664 first_error (_("can't redefine type for operand"));
1667 atype
.defined
|= NTA_HASTYPE
;
1668 atype
.eltype
= parsetype
;
1671 if (skip_past_char (&str
, '[') == SUCCESS
)
1673 if (type
!= REG_TYPE_VFD
1674 && !(type
== REG_TYPE_VFS
1675 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1676 && !(type
== REG_TYPE_NQ
1677 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1679 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1680 first_error (_("only D and Q registers may be indexed"));
1682 first_error (_("only D registers may be indexed"));
1686 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1688 first_error (_("can't change index for operand"));
1692 atype
.defined
|= NTA_HASINDEX
;
1694 if (skip_past_char (&str
, ']') == SUCCESS
)
1695 atype
.index
= NEON_ALL_LANES
;
1700 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1702 if (exp
.X_op
!= O_constant
)
1704 first_error (_("constant expression required"));
1708 if (skip_past_char (&str
, ']') == FAIL
)
1711 atype
.index
= exp
.X_add_number
;
1726 /* Like arm_reg_parse, but also allow the following extra features:
1727 - If RTYPE is non-zero, return the (possibly restricted) type of the
1728 register (e.g. Neon double or quad reg when either has been requested).
1729 - If this is a Neon vector type with additional type information, fill
1730 in the struct pointed to by VECTYPE (if non-NULL).
1731 This function will fault on encountering a scalar. */
1734 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1735 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1737 struct neon_typed_alias atype
;
1739 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1744 /* Do not allow regname(... to parse as a register. */
1748 /* Do not allow a scalar (reg+index) to parse as a register. */
1749 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1751 first_error (_("register operand expected, but got scalar"));
1756 *vectype
= atype
.eltype
;
1763 #define NEON_SCALAR_REG(X) ((X) >> 4)
1764 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1766 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1767 have enough information to be able to do a good job bounds-checking. So, we
1768 just do easy checks here, and do further checks later. */
1771 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1772 arm_reg_type reg_type
)
1776 struct neon_typed_alias atype
;
1779 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1797 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1800 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1802 first_error (_("scalar must have an index"));
1805 else if (atype
.index
>= reg_size
/ elsize
)
1807 first_error (_("scalar index out of range"));
1812 *type
= atype
.eltype
;
1816 return reg
* 16 + atype
.index
;
1819 /* Types of registers in a list. */
1832 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1835 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1841 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1843 /* We come back here if we get ranges concatenated by '+' or '|'. */
1846 skip_whitespace (str
);
1859 const char apsr_str
[] = "apsr";
1860 int apsr_str_len
= strlen (apsr_str
);
1862 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1863 if (etype
== REGLIST_CLRM
)
1865 if (reg
== REG_SP
|| reg
== REG_PC
)
1867 else if (reg
== FAIL
1868 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1869 && !ISALPHA (*(str
+ apsr_str_len
)))
1872 str
+= apsr_str_len
;
1877 first_error (_("r0-r12, lr or APSR expected"));
1881 else /* etype == REGLIST_RN. */
1885 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1896 first_error (_("bad range in register list"));
1900 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1902 if (range
& (1 << i
))
1904 (_("Warning: duplicated register (r%d) in register list"),
1912 if (range
& (1 << reg
))
1913 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1915 else if (reg
<= cur_reg
)
1916 as_tsktsk (_("Warning: register range not in ascending order"));
1921 while (skip_past_comma (&str
) != FAIL
1922 || (in_range
= 1, *str
++ == '-'));
1925 if (skip_past_char (&str
, '}') == FAIL
)
1927 first_error (_("missing `}'"));
1931 else if (etype
== REGLIST_RN
)
1935 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1938 if (exp
.X_op
== O_constant
)
1940 if (exp
.X_add_number
1941 != (exp
.X_add_number
& 0x0000ffff))
1943 inst
.error
= _("invalid register mask");
1947 if ((range
& exp
.X_add_number
) != 0)
1949 int regno
= range
& exp
.X_add_number
;
1952 regno
= (1 << regno
) - 1;
1954 (_("Warning: duplicated register (r%d) in register list"),
1958 range
|= exp
.X_add_number
;
1962 if (inst
.relocs
[0].type
!= 0)
1964 inst
.error
= _("expression too complex");
1968 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1969 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1970 inst
.relocs
[0].pc_rel
= 0;
1974 if (*str
== '|' || *str
== '+')
1980 while (another_range
);
1986 /* Parse a VFP register list. If the string is invalid return FAIL.
1987 Otherwise return the number of registers, and set PBASE to the first
1988 register. Parses registers of type ETYPE.
1989 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1990 - Q registers can be used to specify pairs of D registers
1991 - { } can be omitted from around a singleton register list
1992 FIXME: This is not implemented, as it would require backtracking in
1995 This could be done (the meaning isn't really ambiguous), but doesn't
1996 fit in well with the current parsing framework.
1997 - 32 D registers may be used (also true for VFPv3).
1998 FIXME: Types are ignored in these register lists, which is probably a
2002 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2003 bfd_boolean
*partial_match
)
2008 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2012 unsigned long mask
= 0;
2014 bfd_boolean vpr_seen
= FALSE
;
2015 bfd_boolean expect_vpr
=
2016 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2018 if (skip_past_char (&str
, '{') == FAIL
)
2020 inst
.error
= _("expecting {");
2027 case REGLIST_VFP_S_VPR
:
2028 regtype
= REG_TYPE_VFS
;
2033 case REGLIST_VFP_D_VPR
:
2034 regtype
= REG_TYPE_VFD
;
2037 case REGLIST_NEON_D
:
2038 regtype
= REG_TYPE_NDQ
;
2045 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2047 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2052 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2055 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2062 base_reg
= max_regs
;
2063 *partial_match
= FALSE
;
2067 int setmask
= 1, addregs
= 1;
2068 const char vpr_str
[] = "vpr";
2069 int vpr_str_len
= strlen (vpr_str
);
2071 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2075 if (new_base
== FAIL
2076 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2077 && !ISALPHA (*(str
+ vpr_str_len
))
2083 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2087 first_error (_("VPR expected last"));
2090 else if (new_base
== FAIL
)
2092 if (regtype
== REG_TYPE_VFS
)
2093 first_error (_("VFP single precision register or VPR "
2095 else /* regtype == REG_TYPE_VFD. */
2096 first_error (_("VFP/Neon double precision register or VPR "
2101 else if (new_base
== FAIL
)
2103 first_error (_(reg_expected_msgs
[regtype
]));
2107 *partial_match
= TRUE
;
2111 if (new_base
>= max_regs
)
2113 first_error (_("register out of range in list"));
2117 /* Note: a value of 2 * n is returned for the register Q<n>. */
2118 if (regtype
== REG_TYPE_NQ
)
2124 if (new_base
< base_reg
)
2125 base_reg
= new_base
;
2127 if (mask
& (setmask
<< new_base
))
2129 first_error (_("invalid register list"));
2133 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2135 as_tsktsk (_("register list not in ascending order"));
2139 mask
|= setmask
<< new_base
;
2142 if (*str
== '-') /* We have the start of a range expression */
2148 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2151 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2155 if (high_range
>= max_regs
)
2157 first_error (_("register out of range in list"));
2161 if (regtype
== REG_TYPE_NQ
)
2162 high_range
= high_range
+ 1;
2164 if (high_range
<= new_base
)
2166 inst
.error
= _("register range not in ascending order");
2170 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2172 if (mask
& (setmask
<< new_base
))
2174 inst
.error
= _("invalid register list");
2178 mask
|= setmask
<< new_base
;
2183 while (skip_past_comma (&str
) != FAIL
);
2187 /* Sanity check -- should have raised a parse error above. */
2188 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2193 if (expect_vpr
&& !vpr_seen
)
2195 first_error (_("VPR expected last"));
2199 /* Final test -- the registers must be consecutive. */
2201 for (i
= 0; i
< count
; i
++)
2203 if ((mask
& (1u << i
)) == 0)
2205 inst
.error
= _("non-contiguous register range");
2215 /* True if two alias types are the same. */
2218 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2226 if (a
->defined
!= b
->defined
)
2229 if ((a
->defined
& NTA_HASTYPE
) != 0
2230 && (a
->eltype
.type
!= b
->eltype
.type
2231 || a
->eltype
.size
!= b
->eltype
.size
))
2234 if ((a
->defined
& NTA_HASINDEX
) != 0
2235 && (a
->index
!= b
->index
))
2241 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2242 The base register is put in *PBASE.
2243 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2245 The register stride (minus one) is put in bit 4 of the return value.
2246 Bits [6:5] encode the list length (minus one).
2247 The type of the list elements is put in *ELTYPE, if non-NULL. */
2249 #define NEON_LANE(X) ((X) & 0xf)
2250 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2251 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2254 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2256 struct neon_type_el
*eltype
)
2263 int leading_brace
= 0;
2264 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2265 const char *const incr_error
= mve
? _("register stride must be 1") :
2266 _("register stride must be 1 or 2");
2267 const char *const type_error
= _("mismatched element/structure types in list");
2268 struct neon_typed_alias firsttype
;
2269 firsttype
.defined
= 0;
2270 firsttype
.eltype
.type
= NT_invtype
;
2271 firsttype
.eltype
.size
= -1;
2272 firsttype
.index
= -1;
2274 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2279 struct neon_typed_alias atype
;
2281 rtype
= REG_TYPE_MQ
;
2282 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2286 first_error (_(reg_expected_msgs
[rtype
]));
2293 if (rtype
== REG_TYPE_NQ
)
2299 else if (reg_incr
== -1)
2301 reg_incr
= getreg
- base_reg
;
2302 if (reg_incr
< 1 || reg_incr
> 2)
2304 first_error (_(incr_error
));
2308 else if (getreg
!= base_reg
+ reg_incr
* count
)
2310 first_error (_(incr_error
));
2314 if (! neon_alias_types_same (&atype
, &firsttype
))
2316 first_error (_(type_error
));
2320 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2324 struct neon_typed_alias htype
;
2325 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2327 lane
= NEON_INTERLEAVE_LANES
;
2328 else if (lane
!= NEON_INTERLEAVE_LANES
)
2330 first_error (_(type_error
));
2335 else if (reg_incr
!= 1)
2337 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2341 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2344 first_error (_(reg_expected_msgs
[rtype
]));
2347 if (! neon_alias_types_same (&htype
, &firsttype
))
2349 first_error (_(type_error
));
2352 count
+= hireg
+ dregs
- getreg
;
2356 /* If we're using Q registers, we can't use [] or [n] syntax. */
2357 if (rtype
== REG_TYPE_NQ
)
2363 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2367 else if (lane
!= atype
.index
)
2369 first_error (_(type_error
));
2373 else if (lane
== -1)
2374 lane
= NEON_INTERLEAVE_LANES
;
2375 else if (lane
!= NEON_INTERLEAVE_LANES
)
2377 first_error (_(type_error
));
2382 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2384 /* No lane set by [x]. We must be interleaving structures. */
2386 lane
= NEON_INTERLEAVE_LANES
;
2389 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2390 || (count
> 1 && reg_incr
== -1))
2392 first_error (_("error parsing element/structure list"));
2396 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2398 first_error (_("expected }"));
2406 *eltype
= firsttype
.eltype
;
2411 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2414 /* Parse an explicit relocation suffix on an expression. This is
2415 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2416 arm_reloc_hsh contains no entries, so this function can only
2417 succeed if there is no () after the word. Returns -1 on error,
2418 BFD_RELOC_UNUSED if there wasn't any suffix. */
2421 parse_reloc (char **str
)
2423 struct reloc_entry
*r
;
2427 return BFD_RELOC_UNUSED
;
2432 while (*q
&& *q
!= ')' && *q
!= ',')
2437 if ((r
= (struct reloc_entry
*)
2438 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2445 /* Directives: register aliases. */
2447 static struct reg_entry
*
2448 insert_reg_alias (char *str
, unsigned number
, int type
)
2450 struct reg_entry
*new_reg
;
2453 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2455 if (new_reg
->builtin
)
2456 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2458 /* Only warn about a redefinition if it's not defined as the
2460 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2461 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2466 name
= xstrdup (str
);
2467 new_reg
= XNEW (struct reg_entry
);
2469 new_reg
->name
= name
;
2470 new_reg
->number
= number
;
2471 new_reg
->type
= type
;
2472 new_reg
->builtin
= FALSE
;
2473 new_reg
->neon
= NULL
;
2475 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2482 insert_neon_reg_alias (char *str
, int number
, int type
,
2483 struct neon_typed_alias
*atype
)
2485 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2489 first_error (_("attempt to redefine typed alias"));
2495 reg
->neon
= XNEW (struct neon_typed_alias
);
2496 *reg
->neon
= *atype
;
2500 /* Look for the .req directive. This is of the form:
2502 new_register_name .req existing_register_name
2504 If we find one, or if it looks sufficiently like one that we want to
2505 handle any error here, return TRUE. Otherwise return FALSE. */
2508 create_register_alias (char * newname
, char *p
)
2510 struct reg_entry
*old
;
2511 char *oldname
, *nbuf
;
2514 /* The input scrubber ensures that whitespace after the mnemonic is
2515 collapsed to single spaces. */
2517 if (strncmp (oldname
, " .req ", 6) != 0)
2521 if (*oldname
== '\0')
2524 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2527 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2531 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2532 the desired alias name, and p points to its end. If not, then
2533 the desired alias name is in the global original_case_string. */
2534 #ifdef TC_CASE_SENSITIVE
2537 newname
= original_case_string
;
2538 nlen
= strlen (newname
);
2541 nbuf
= xmemdup0 (newname
, nlen
);
2543 /* Create aliases under the new name as stated; an all-lowercase
2544 version of the new name; and an all-uppercase version of the new
2546 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2548 for (p
= nbuf
; *p
; p
++)
2551 if (strncmp (nbuf
, newname
, nlen
))
2553 /* If this attempt to create an additional alias fails, do not bother
2554 trying to create the all-lower case alias. We will fail and issue
2555 a second, duplicate error message. This situation arises when the
2556 programmer does something like:
2559 The second .req creates the "Foo" alias but then fails to create
2560 the artificial FOO alias because it has already been created by the
2562 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2569 for (p
= nbuf
; *p
; p
++)
2572 if (strncmp (nbuf
, newname
, nlen
))
2573 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2580 /* Create a Neon typed/indexed register alias using directives, e.g.:
2585 These typed registers can be used instead of the types specified after the
2586 Neon mnemonic, so long as all operands given have types. Types can also be
2587 specified directly, e.g.:
2588 vadd d0.s32, d1.s32, d2.s32 */
2591 create_neon_reg_alias (char *newname
, char *p
)
2593 enum arm_reg_type basetype
;
2594 struct reg_entry
*basereg
;
2595 struct reg_entry mybasereg
;
2596 struct neon_type ntype
;
2597 struct neon_typed_alias typeinfo
;
2598 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2601 typeinfo
.defined
= 0;
2602 typeinfo
.eltype
.type
= NT_invtype
;
2603 typeinfo
.eltype
.size
= -1;
2604 typeinfo
.index
= -1;
2608 if (strncmp (p
, " .dn ", 5) == 0)
2609 basetype
= REG_TYPE_VFD
;
2610 else if (strncmp (p
, " .qn ", 5) == 0)
2611 basetype
= REG_TYPE_NQ
;
2620 basereg
= arm_reg_parse_multi (&p
);
2622 if (basereg
&& basereg
->type
!= basetype
)
2624 as_bad (_("bad type for register"));
2628 if (basereg
== NULL
)
2631 /* Try parsing as an integer. */
2632 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2633 if (exp
.X_op
!= O_constant
)
2635 as_bad (_("expression must be constant"));
2638 basereg
= &mybasereg
;
2639 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2645 typeinfo
= *basereg
->neon
;
2647 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2649 /* We got a type. */
2650 if (typeinfo
.defined
& NTA_HASTYPE
)
2652 as_bad (_("can't redefine the type of a register alias"));
2656 typeinfo
.defined
|= NTA_HASTYPE
;
2657 if (ntype
.elems
!= 1)
2659 as_bad (_("you must specify a single type only"));
2662 typeinfo
.eltype
= ntype
.el
[0];
2665 if (skip_past_char (&p
, '[') == SUCCESS
)
2668 /* We got a scalar index. */
2670 if (typeinfo
.defined
& NTA_HASINDEX
)
2672 as_bad (_("can't redefine the index of a scalar alias"));
2676 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2678 if (exp
.X_op
!= O_constant
)
2680 as_bad (_("scalar index must be constant"));
2684 typeinfo
.defined
|= NTA_HASINDEX
;
2685 typeinfo
.index
= exp
.X_add_number
;
2687 if (skip_past_char (&p
, ']') == FAIL
)
2689 as_bad (_("expecting ]"));
2694 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2695 the desired alias name, and p points to its end. If not, then
2696 the desired alias name is in the global original_case_string. */
2697 #ifdef TC_CASE_SENSITIVE
2698 namelen
= nameend
- newname
;
2700 newname
= original_case_string
;
2701 namelen
= strlen (newname
);
2704 namebuf
= xmemdup0 (newname
, namelen
);
2706 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2707 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2709 /* Insert name in all uppercase. */
2710 for (p
= namebuf
; *p
; p
++)
2713 if (strncmp (namebuf
, newname
, namelen
))
2714 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2715 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2717 /* Insert name in all lowercase. */
2718 for (p
= namebuf
; *p
; p
++)
2721 if (strncmp (namebuf
, newname
, namelen
))
2722 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2723 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2729 /* Should never be called, as .req goes between the alias and the
2730 register name, not at the beginning of the line. */
2733 s_req (int a ATTRIBUTE_UNUSED
)
2735 as_bad (_("invalid syntax for .req directive"));
2739 s_dn (int a ATTRIBUTE_UNUSED
)
2741 as_bad (_("invalid syntax for .dn directive"));
2745 s_qn (int a ATTRIBUTE_UNUSED
)
2747 as_bad (_("invalid syntax for .qn directive"));
2750 /* The .unreq directive deletes an alias which was previously defined
2751 by .req. For example:
2757 s_unreq (int a ATTRIBUTE_UNUSED
)
2762 name
= input_line_pointer
;
2764 while (*input_line_pointer
!= 0
2765 && *input_line_pointer
!= ' '
2766 && *input_line_pointer
!= '\n')
2767 ++input_line_pointer
;
2769 saved_char
= *input_line_pointer
;
2770 *input_line_pointer
= 0;
2773 as_bad (_("invalid syntax for .unreq directive"));
2776 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2780 as_bad (_("unknown register alias '%s'"), name
);
2781 else if (reg
->builtin
)
2782 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2789 hash_delete (arm_reg_hsh
, name
, FALSE
);
2790 free ((char *) reg
->name
);
2795 /* Also locate the all upper case and all lower case versions.
2796 Do not complain if we cannot find one or the other as it
2797 was probably deleted above. */
2799 nbuf
= strdup (name
);
2800 for (p
= nbuf
; *p
; p
++)
2802 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2805 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2806 free ((char *) reg
->name
);
2812 for (p
= nbuf
; *p
; p
++)
2814 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2817 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2818 free ((char *) reg
->name
);
2828 *input_line_pointer
= saved_char
;
2829 demand_empty_rest_of_line ();
2832 /* Directives: Instruction set selection. */
2835 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2836 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2837 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2838 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2840 /* Create a new mapping symbol for the transition to STATE. */
2843 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2846 const char * symname
;
2853 type
= BSF_NO_FLAGS
;
2857 type
= BSF_NO_FLAGS
;
2861 type
= BSF_NO_FLAGS
;
2867 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2868 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2873 THUMB_SET_FUNC (symbolP
, 0);
2874 ARM_SET_THUMB (symbolP
, 0);
2875 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 THUMB_SET_FUNC (symbolP
, 1);
2880 ARM_SET_THUMB (symbolP
, 1);
2881 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2889 /* Save the mapping symbols for future reference. Also check that
2890 we do not place two mapping symbols at the same offset within a
2891 frag. We'll handle overlap between frags in
2892 check_mapping_symbols.
2894 If .fill or other data filling directive generates zero sized data,
2895 the mapping symbol for the following code will have the same value
2896 as the one generated for the data filling directive. In this case,
2897 we replace the old symbol with the new one at the same address. */
2900 if (frag
->tc_frag_data
.first_map
!= NULL
)
2902 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2903 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2905 frag
->tc_frag_data
.first_map
= symbolP
;
2907 if (frag
->tc_frag_data
.last_map
!= NULL
)
2909 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2910 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2911 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2913 frag
->tc_frag_data
.last_map
= symbolP
;
2916 /* We must sometimes convert a region marked as code to data during
2917 code alignment, if an odd number of bytes have to be padded. The
2918 code mapping symbol is pushed to an aligned address. */
2921 insert_data_mapping_symbol (enum mstate state
,
2922 valueT value
, fragS
*frag
, offsetT bytes
)
2924 /* If there was already a mapping symbol, remove it. */
2925 if (frag
->tc_frag_data
.last_map
!= NULL
2926 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2928 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2932 know (frag
->tc_frag_data
.first_map
== symp
);
2933 frag
->tc_frag_data
.first_map
= NULL
;
2935 frag
->tc_frag_data
.last_map
= NULL
;
2936 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2939 make_mapping_symbol (MAP_DATA
, value
, frag
);
2940 make_mapping_symbol (state
, value
+ bytes
, frag
);
2943 static void mapping_state_2 (enum mstate state
, int max_chars
);
2945 /* Set the mapping state to STATE. Only call this when about to
2946 emit some STATE bytes to the file. */
2948 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2950 mapping_state (enum mstate state
)
2952 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2954 if (mapstate
== state
)
2955 /* The mapping symbol has already been emitted.
2956 There is nothing else to do. */
2959 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2961 All ARM instructions require 4-byte alignment.
2962 (Almost) all Thumb instructions require 2-byte alignment.
2964 When emitting instructions into any section, mark the section
2967 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2968 but themselves require 2-byte alignment; this applies to some
2969 PC- relative forms. However, these cases will involve implicit
2970 literal pool generation or an explicit .align >=2, both of
2971 which will cause the section to me marked with sufficient
2972 alignment. Thus, we don't handle those cases here. */
2973 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2975 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2976 /* This case will be evaluated later. */
2979 mapping_state_2 (state
, 0);
2982 /* Same as mapping_state, but MAX_CHARS bytes have already been
2983 allocated. Put the mapping symbol that far back. */
2986 mapping_state_2 (enum mstate state
, int max_chars
)
2988 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2990 if (!SEG_NORMAL (now_seg
))
2993 if (mapstate
== state
)
2994 /* The mapping symbol has already been emitted.
2995 There is nothing else to do. */
2998 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2999 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3001 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3002 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3005 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3008 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3009 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3013 #define mapping_state(x) ((void)0)
3014 #define mapping_state_2(x, y) ((void)0)
3017 /* Find the real, Thumb encoded start of a Thumb function. */
3021 find_real_start (symbolS
* symbolP
)
3024 const char * name
= S_GET_NAME (symbolP
);
3025 symbolS
* new_target
;
3027 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3028 #define STUB_NAME ".real_start_of"
3033 /* The compiler may generate BL instructions to local labels because
3034 it needs to perform a branch to a far away location. These labels
3035 do not have a corresponding ".real_start_of" label. We check
3036 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3037 the ".real_start_of" convention for nonlocal branches. */
3038 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3041 real_start
= concat (STUB_NAME
, name
, NULL
);
3042 new_target
= symbol_find (real_start
);
3045 if (new_target
== NULL
)
3047 as_warn (_("Failed to find real start of function: %s\n"), name
);
3048 new_target
= symbolP
;
3056 opcode_select (int width
)
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3064 as_bad (_("selected processor does not support THUMB opcodes"));
3067 /* No need to force the alignment, since we will have been
3068 coming from ARM mode, which is word-aligned. */
3069 record_alignment (now_seg
, 1);
3076 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3077 as_bad (_("selected processor does not support ARM opcodes"));
3082 frag_align (2, 0, 0);
3084 record_alignment (now_seg
, 1);
3089 as_bad (_("invalid instruction size selected (%d)"), width
);
3094 s_arm (int ignore ATTRIBUTE_UNUSED
)
3097 demand_empty_rest_of_line ();
3101 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3104 demand_empty_rest_of_line ();
3108 s_code (int unused ATTRIBUTE_UNUSED
)
3112 temp
= get_absolute_expression ();
3117 opcode_select (temp
);
3121 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3126 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3128 /* If we are not already in thumb mode go into it, EVEN if
3129 the target processor does not support thumb instructions.
3130 This is used by gcc/config/arm/lib1funcs.asm for example
3131 to compile interworking support functions even if the
3132 target processor should not support interworking. */
3136 record_alignment (now_seg
, 1);
3139 demand_empty_rest_of_line ();
3143 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3147 /* The following label is the name/address of the start of a Thumb function.
3148 We need to know this for the interworking support. */
3149 label_is_thumb_function_name
= TRUE
;
3152 /* Perform a .set directive, but also mark the alias as
3153 being a thumb function. */
3156 s_thumb_set (int equiv
)
3158 /* XXX the following is a duplicate of the code for s_set() in read.c
3159 We cannot just call that code as we need to get at the symbol that
3166 /* Especial apologies for the random logic:
3167 This just grew, and could be parsed much more simply!
3169 delim
= get_symbol_name (& name
);
3170 end_name
= input_line_pointer
;
3171 (void) restore_line_pointer (delim
);
3173 if (*input_line_pointer
!= ',')
3176 as_bad (_("expected comma after name \"%s\""), name
);
3178 ignore_rest_of_line ();
3182 input_line_pointer
++;
3185 if (name
[0] == '.' && name
[1] == '\0')
3187 /* XXX - this should not happen to .thumb_set. */
3191 if ((symbolP
= symbol_find (name
)) == NULL
3192 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3195 /* When doing symbol listings, play games with dummy fragments living
3196 outside the normal fragment chain to record the file and line info
3198 if (listing
& LISTING_SYMBOLS
)
3200 extern struct list_info_struct
* listing_tail
;
3201 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3203 memset (dummy_frag
, 0, sizeof (fragS
));
3204 dummy_frag
->fr_type
= rs_fill
;
3205 dummy_frag
->line
= listing_tail
;
3206 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3207 dummy_frag
->fr_symbol
= symbolP
;
3211 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3214 /* "set" symbols are local unless otherwise specified. */
3215 SF_SET_LOCAL (symbolP
);
3216 #endif /* OBJ_COFF */
3217 } /* Make a new symbol. */
3219 symbol_table_insert (symbolP
);
3224 && S_IS_DEFINED (symbolP
)
3225 && S_GET_SEGMENT (symbolP
) != reg_section
)
3226 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3228 pseudo_set (symbolP
);
3230 demand_empty_rest_of_line ();
3232 /* XXX Now we come to the Thumb specific bit of code. */
3234 THUMB_SET_FUNC (symbolP
, 1);
3235 ARM_SET_THUMB (symbolP
, 1);
3236 #if defined OBJ_ELF || defined OBJ_COFF
3237 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3241 /* Directives: Mode selection. */
3243 /* .syntax [unified|divided] - choose the new unified syntax
3244 (same for Arm and Thumb encoding, modulo slight differences in what
3245 can be represented) or the old divergent syntax for each mode. */
3247 s_syntax (int unused ATTRIBUTE_UNUSED
)
3251 delim
= get_symbol_name (& name
);
3253 if (!strcasecmp (name
, "unified"))
3254 unified_syntax
= TRUE
;
3255 else if (!strcasecmp (name
, "divided"))
3256 unified_syntax
= FALSE
;
3259 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3262 (void) restore_line_pointer (delim
);
3263 demand_empty_rest_of_line ();
3266 /* Directives: sectioning and alignment. */
3269 s_bss (int ignore ATTRIBUTE_UNUSED
)
3271 /* We don't support putting frags in the BSS segment, we fake it by
3272 marking in_bss, then looking at s_skip for clues. */
3273 subseg_set (bss_section
, 0);
3274 demand_empty_rest_of_line ();
3276 #ifdef md_elf_section_change_hook
3277 md_elf_section_change_hook ();
3282 s_even (int ignore ATTRIBUTE_UNUSED
)
3284 /* Never make frag if expect extra pass. */
3286 frag_align (1, 0, 0);
3288 record_alignment (now_seg
, 1);
3290 demand_empty_rest_of_line ();
3293 /* Directives: CodeComposer Studio. */
3295 /* .ref (for CodeComposer Studio syntax only). */
3297 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3299 if (codecomposer_syntax
)
3300 ignore_rest_of_line ();
3302 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3305 /* If name is not NULL, then it is used for marking the beginning of a
3306 function, whereas if it is NULL then it means the function end. */
3308 asmfunc_debug (const char * name
)
3310 static const char * last_name
= NULL
;
3314 gas_assert (last_name
== NULL
);
3317 if (debug_type
== DEBUG_STABS
)
3318 stabs_generate_asm_func (name
, name
);
3322 gas_assert (last_name
!= NULL
);
3324 if (debug_type
== DEBUG_STABS
)
3325 stabs_generate_asm_endfunc (last_name
, last_name
);
3332 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3334 if (codecomposer_syntax
)
3336 switch (asmfunc_state
)
3338 case OUTSIDE_ASMFUNC
:
3339 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3342 case WAITING_ASMFUNC_NAME
:
3343 as_bad (_(".asmfunc repeated."));
3346 case WAITING_ENDASMFUNC
:
3347 as_bad (_(".asmfunc without function."));
3350 demand_empty_rest_of_line ();
3353 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3357 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3359 if (codecomposer_syntax
)
3361 switch (asmfunc_state
)
3363 case OUTSIDE_ASMFUNC
:
3364 as_bad (_(".endasmfunc without a .asmfunc."));
3367 case WAITING_ASMFUNC_NAME
:
3368 as_bad (_(".endasmfunc without function."));
3371 case WAITING_ENDASMFUNC
:
3372 asmfunc_state
= OUTSIDE_ASMFUNC
;
3373 asmfunc_debug (NULL
);
3376 demand_empty_rest_of_line ();
3379 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3383 s_ccs_def (int name
)
3385 if (codecomposer_syntax
)
3388 as_bad (_(".def pseudo-op only available with -mccs flag."));
3391 /* Directives: Literal pools. */
3393 static literal_pool
*
3394 find_literal_pool (void)
3396 literal_pool
* pool
;
3398 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3400 if (pool
->section
== now_seg
3401 && pool
->sub_section
== now_subseg
)
3408 static literal_pool
*
3409 find_or_make_literal_pool (void)
3411 /* Next literal pool ID number. */
3412 static unsigned int latest_pool_num
= 1;
3413 literal_pool
* pool
;
3415 pool
= find_literal_pool ();
3419 /* Create a new pool. */
3420 pool
= XNEW (literal_pool
);
3424 pool
->next_free_entry
= 0;
3425 pool
->section
= now_seg
;
3426 pool
->sub_section
= now_subseg
;
3427 pool
->next
= list_of_pools
;
3428 pool
->symbol
= NULL
;
3429 pool
->alignment
= 2;
3431 /* Add it to the list. */
3432 list_of_pools
= pool
;
3435 /* New pools, and emptied pools, will have a NULL symbol. */
3436 if (pool
->symbol
== NULL
)
3438 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3439 (valueT
) 0, &zero_address_frag
);
3440 pool
->id
= latest_pool_num
++;
3447 /* Add the literal in the global 'inst'
3448 structure to the relevant literal pool. */
3451 add_to_lit_pool (unsigned int nbytes
)
3453 #define PADDING_SLOT 0x1
3454 #define LIT_ENTRY_SIZE_MASK 0xFF
3455 literal_pool
* pool
;
3456 unsigned int entry
, pool_size
= 0;
3457 bfd_boolean padding_slot_p
= FALSE
;
3463 imm1
= inst
.operands
[1].imm
;
3464 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3465 : inst
.relocs
[0].exp
.X_unsigned
? 0
3466 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3467 if (target_big_endian
)
3470 imm2
= inst
.operands
[1].imm
;
3474 pool
= find_or_make_literal_pool ();
3476 /* Check if this literal value is already in the pool. */
3477 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3481 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3482 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3483 && (pool
->literals
[entry
].X_add_number
3484 == inst
.relocs
[0].exp
.X_add_number
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
)
3486 && (pool
->literals
[entry
].X_unsigned
3487 == inst
.relocs
[0].exp
.X_unsigned
))
3490 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3491 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3492 && (pool
->literals
[entry
].X_add_number
3493 == inst
.relocs
[0].exp
.X_add_number
)
3494 && (pool
->literals
[entry
].X_add_symbol
3495 == inst
.relocs
[0].exp
.X_add_symbol
)
3496 && (pool
->literals
[entry
].X_op_symbol
3497 == inst
.relocs
[0].exp
.X_op_symbol
)
3498 && (pool
->literals
[entry
].X_md
== nbytes
))
3501 else if ((nbytes
== 8)
3502 && !(pool_size
& 0x7)
3503 && ((entry
+ 1) != pool
->next_free_entry
)
3504 && (pool
->literals
[entry
].X_op
== O_constant
)
3505 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3506 && (pool
->literals
[entry
].X_unsigned
3507 == inst
.relocs
[0].exp
.X_unsigned
)
3508 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3509 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3510 && (pool
->literals
[entry
+ 1].X_unsigned
3511 == inst
.relocs
[0].exp
.X_unsigned
))
3514 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3515 if (padding_slot_p
&& (nbytes
== 4))
3521 /* Do we need to create a new entry? */
3522 if (entry
== pool
->next_free_entry
)
3524 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3526 inst
.error
= _("literal pool overflow");
3532 /* For 8-byte entries, we align to an 8-byte boundary,
3533 and split it into two 4-byte entries, because on 32-bit
3534 host, 8-byte constants are treated as big num, thus
3535 saved in "generic_bignum" which will be overwritten
3536 by later assignments.
3538 We also need to make sure there is enough space for
3541 We also check to make sure the literal operand is a
3543 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3544 || inst
.relocs
[0].exp
.X_op
== O_big
))
3546 inst
.error
= _("invalid type for literal pool");
3549 else if (pool_size
& 0x7)
3551 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= 0;
3560 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3561 pool
->next_free_entry
+= 1;
3564 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3566 inst
.error
= _("literal pool overflow");
3570 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3571 pool
->literals
[entry
].X_op
= O_constant
;
3572 pool
->literals
[entry
].X_add_number
= imm1
;
3573 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3574 pool
->literals
[entry
++].X_md
= 4;
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_op
= O_constant
;
3577 pool
->literals
[entry
].X_add_number
= imm2
;
3578 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3579 pool
->literals
[entry
].X_md
= 4;
3580 pool
->alignment
= 3;
3581 pool
->next_free_entry
+= 1;
3585 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3586 pool
->literals
[entry
].X_md
= 4;
3590 /* PR ld/12974: Record the location of the first source line to reference
3591 this entry in the literal pool. If it turns out during linking that the
3592 symbol does not exist we will be able to give an accurate line number for
3593 the (first use of the) missing reference. */
3594 if (debug_type
== DEBUG_DWARF2
)
3595 dwarf2_where (pool
->locs
+ entry
);
3597 pool
->next_free_entry
+= 1;
3599 else if (padding_slot_p
)
3601 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3602 pool
->literals
[entry
].X_md
= nbytes
;
3605 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3606 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3607 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3613 tc_start_label_without_colon (void)
3615 bfd_boolean ret
= TRUE
;
3617 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3619 const char *label
= input_line_pointer
;
3621 while (!is_end_of_line
[(int) label
[-1]])
3626 as_bad (_("Invalid label '%s'"), label
);
3630 asmfunc_debug (label
);
3632 asmfunc_state
= WAITING_ENDASMFUNC
;
3638 /* Can't use symbol_new here, so have to create a symbol and then at
3639 a later date assign it a value. That's what these functions do. */
3642 symbol_locate (symbolS
* symbolP
,
3643 const char * name
, /* It is copied, the caller can modify. */
3644 segT segment
, /* Segment identifier (SEG_<something>). */
3645 valueT valu
, /* Symbol value. */
3646 fragS
* frag
) /* Associated fragment. */
3649 char * preserved_copy_of_name
;
3651 name_length
= strlen (name
) + 1; /* +1 for \0. */
3652 obstack_grow (¬es
, name
, name_length
);
3653 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3655 #ifdef tc_canonicalize_symbol_name
3656 preserved_copy_of_name
=
3657 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3660 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3662 S_SET_SEGMENT (symbolP
, segment
);
3663 S_SET_VALUE (symbolP
, valu
);
3664 symbol_clear_list_pointers (symbolP
);
3666 symbol_set_frag (symbolP
, frag
);
3668 /* Link to end of symbol chain. */
3670 extern int symbol_table_frozen
;
3672 if (symbol_table_frozen
)
3676 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3678 obj_symbol_new_hook (symbolP
);
3680 #ifdef tc_symbol_new_hook
3681 tc_symbol_new_hook (symbolP
);
3685 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3686 #endif /* DEBUG_SYMS */
3690 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3693 literal_pool
* pool
;
3696 pool
= find_literal_pool ();
3698 || pool
->symbol
== NULL
3699 || pool
->next_free_entry
== 0)
3702 /* Align pool as you have word accesses.
3703 Only make a frag if we have to. */
3705 frag_align (pool
->alignment
, 0, 0);
3707 record_alignment (now_seg
, 2);
3710 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3711 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3713 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3715 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3716 (valueT
) frag_now_fix (), frag_now
);
3717 symbol_table_insert (pool
->symbol
);
3719 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3721 #if defined OBJ_COFF || defined OBJ_ELF
3722 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3725 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3728 if (debug_type
== DEBUG_DWARF2
)
3729 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3731 /* First output the expression in the instruction to the pool. */
3732 emit_expr (&(pool
->literals
[entry
]),
3733 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3736 /* Mark the pool as empty. */
3737 pool
->next_free_entry
= 0;
3738 pool
->symbol
= NULL
;
3742 /* Forward declarations for functions below, in the MD interface
3744 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3745 static valueT
create_unwind_entry (int);
3746 static void start_unwind_section (const segT
, int);
3747 static void add_unwind_opcode (valueT
, int);
3748 static void flush_pending_unwind (void);
3750 /* Directives: Data. */
3753 s_arm_elf_cons (int nbytes
)
3757 #ifdef md_flush_pending_output
3758 md_flush_pending_output ();
3761 if (is_it_end_of_statement ())
3763 demand_empty_rest_of_line ();
3767 #ifdef md_cons_align
3768 md_cons_align (nbytes
);
3771 mapping_state (MAP_DATA
);
3775 char *base
= input_line_pointer
;
3779 if (exp
.X_op
!= O_symbol
)
3780 emit_expr (&exp
, (unsigned int) nbytes
);
3783 char *before_reloc
= input_line_pointer
;
3784 reloc
= parse_reloc (&input_line_pointer
);
3787 as_bad (_("unrecognized relocation suffix"));
3788 ignore_rest_of_line ();
3791 else if (reloc
== BFD_RELOC_UNUSED
)
3792 emit_expr (&exp
, (unsigned int) nbytes
);
3795 reloc_howto_type
*howto
= (reloc_howto_type
*)
3796 bfd_reloc_type_lookup (stdoutput
,
3797 (bfd_reloc_code_real_type
) reloc
);
3798 int size
= bfd_get_reloc_size (howto
);
3800 if (reloc
== BFD_RELOC_ARM_PLT32
)
3802 as_bad (_("(plt) is only valid on branch targets"));
3803 reloc
= BFD_RELOC_UNUSED
;
3808 as_bad (ngettext ("%s relocations do not fit in %d byte",
3809 "%s relocations do not fit in %d bytes",
3811 howto
->name
, nbytes
);
3814 /* We've parsed an expression stopping at O_symbol.
3815 But there may be more expression left now that we
3816 have parsed the relocation marker. Parse it again.
3817 XXX Surely there is a cleaner way to do this. */
3818 char *p
= input_line_pointer
;
3820 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3822 memcpy (save_buf
, base
, input_line_pointer
- base
);
3823 memmove (base
+ (input_line_pointer
- before_reloc
),
3824 base
, before_reloc
- base
);
3826 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3828 memcpy (base
, save_buf
, p
- base
);
3830 offset
= nbytes
- size
;
3831 p
= frag_more (nbytes
);
3832 memset (p
, 0, nbytes
);
3833 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3834 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3840 while (*input_line_pointer
++ == ',');
3842 /* Put terminator back into stream. */
3843 input_line_pointer
--;
3844 demand_empty_rest_of_line ();
3847 /* Emit an expression containing a 32-bit thumb instruction.
3848 Implementation based on put_thumb32_insn. */
3851 emit_thumb32_expr (expressionS
* exp
)
3853 expressionS exp_high
= *exp
;
3855 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3856 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3857 exp
->X_add_number
&= 0xffff;
3858 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3861 /* Guess the instruction size based on the opcode. */
3864 thumb_insn_size (int opcode
)
3866 if ((unsigned int) opcode
< 0xe800u
)
3868 else if ((unsigned int) opcode
>= 0xe8000000u
)
3875 emit_insn (expressionS
*exp
, int nbytes
)
3879 if (exp
->X_op
== O_constant
)
3884 size
= thumb_insn_size (exp
->X_add_number
);
3888 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3890 as_bad (_(".inst.n operand too big. "\
3891 "Use .inst.w instead"));
3896 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3897 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3899 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3901 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3902 emit_thumb32_expr (exp
);
3904 emit_expr (exp
, (unsigned int) size
);
3906 it_fsm_post_encode ();
3910 as_bad (_("cannot determine Thumb instruction size. " \
3911 "Use .inst.n/.inst.w instead"));
3914 as_bad (_("constant expression required"));
3919 /* Like s_arm_elf_cons but do not use md_cons_align and
3920 set the mapping state to MAP_ARM/MAP_THUMB. */
3923 s_arm_elf_inst (int nbytes
)
3925 if (is_it_end_of_statement ())
3927 demand_empty_rest_of_line ();
3931 /* Calling mapping_state () here will not change ARM/THUMB,
3932 but will ensure not to be in DATA state. */
3935 mapping_state (MAP_THUMB
);
3940 as_bad (_("width suffixes are invalid in ARM mode"));
3941 ignore_rest_of_line ();
3947 mapping_state (MAP_ARM
);
3956 if (! emit_insn (& exp
, nbytes
))
3958 ignore_rest_of_line ();
3962 while (*input_line_pointer
++ == ',');
3964 /* Put terminator back into stream. */
3965 input_line_pointer
--;
3966 demand_empty_rest_of_line ();
3969 /* Parse a .rel31 directive. */
3972 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3979 if (*input_line_pointer
== '1')
3980 highbit
= 0x80000000;
3981 else if (*input_line_pointer
!= '0')
3982 as_bad (_("expected 0 or 1"));
3984 input_line_pointer
++;
3985 if (*input_line_pointer
!= ',')
3986 as_bad (_("missing comma"));
3987 input_line_pointer
++;
3989 #ifdef md_flush_pending_output
3990 md_flush_pending_output ();
3993 #ifdef md_cons_align
3997 mapping_state (MAP_DATA
);
4002 md_number_to_chars (p
, highbit
, 4);
4003 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4004 BFD_RELOC_ARM_PREL31
);
4006 demand_empty_rest_of_line ();
4009 /* Directives: AEABI stack-unwind tables. */
4011 /* Parse an unwind_fnstart directive. Simply records the current location. */
4014 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4016 demand_empty_rest_of_line ();
4017 if (unwind
.proc_start
)
4019 as_bad (_("duplicate .fnstart directive"));
4023 /* Mark the start of the function. */
4024 unwind
.proc_start
= expr_build_dot ();
4026 /* Reset the rest of the unwind info. */
4027 unwind
.opcode_count
= 0;
4028 unwind
.table_entry
= NULL
;
4029 unwind
.personality_routine
= NULL
;
4030 unwind
.personality_index
= -1;
4031 unwind
.frame_size
= 0;
4032 unwind
.fp_offset
= 0;
4033 unwind
.fp_reg
= REG_SP
;
4035 unwind
.sp_restored
= 0;
4039 /* Parse a handlerdata directive. Creates the exception handling table entry
4040 for the function. */
4043 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4045 demand_empty_rest_of_line ();
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 if (unwind
.table_entry
)
4050 as_bad (_("duplicate .handlerdata directive"));
4052 create_unwind_entry (1);
4055 /* Parse an unwind_fnend directive. Generates the index table entry. */
4058 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4063 unsigned int marked_pr_dependency
;
4065 demand_empty_rest_of_line ();
4067 if (!unwind
.proc_start
)
4069 as_bad (_(".fnend directive without .fnstart"));
4073 /* Add eh table entry. */
4074 if (unwind
.table_entry
== NULL
)
4075 val
= create_unwind_entry (0);
4079 /* Add index table entry. This is two words. */
4080 start_unwind_section (unwind
.saved_seg
, 1);
4081 frag_align (2, 0, 0);
4082 record_alignment (now_seg
, 2);
4084 ptr
= frag_more (8);
4086 where
= frag_now_fix () - 8;
4088 /* Self relative offset of the function start. */
4089 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4090 BFD_RELOC_ARM_PREL31
);
4092 /* Indicate dependency on EHABI-defined personality routines to the
4093 linker, if it hasn't been done already. */
4094 marked_pr_dependency
4095 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4096 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4097 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4099 static const char *const name
[] =
4101 "__aeabi_unwind_cpp_pr0",
4102 "__aeabi_unwind_cpp_pr1",
4103 "__aeabi_unwind_cpp_pr2"
4105 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4106 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4107 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4108 |= 1 << unwind
.personality_index
;
4112 /* Inline exception table entry. */
4113 md_number_to_chars (ptr
+ 4, val
, 4);
4115 /* Self relative offset of the table entry. */
4116 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4117 BFD_RELOC_ARM_PREL31
);
4119 /* Restore the original section. */
4120 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4122 unwind
.proc_start
= NULL
;
4126 /* Parse an unwind_cantunwind directive. */
4129 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4131 demand_empty_rest_of_line ();
4132 if (!unwind
.proc_start
)
4133 as_bad (MISSING_FNSTART
);
4135 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4136 as_bad (_("personality routine specified for cantunwind frame"));
4138 unwind
.personality_index
= -2;
4142 /* Parse a personalityindex directive. */
4145 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4149 if (!unwind
.proc_start
)
4150 as_bad (MISSING_FNSTART
);
4152 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4153 as_bad (_("duplicate .personalityindex directive"));
4157 if (exp
.X_op
!= O_constant
4158 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4160 as_bad (_("bad personality routine number"));
4161 ignore_rest_of_line ();
4165 unwind
.personality_index
= exp
.X_add_number
;
4167 demand_empty_rest_of_line ();
4171 /* Parse a personality directive. */
4174 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4178 if (!unwind
.proc_start
)
4179 as_bad (MISSING_FNSTART
);
4181 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4182 as_bad (_("duplicate .personality directive"));
4184 c
= get_symbol_name (& name
);
4185 p
= input_line_pointer
;
4187 ++ input_line_pointer
;
4188 unwind
.personality_routine
= symbol_find_or_make (name
);
4190 demand_empty_rest_of_line ();
4194 /* Parse a directive saving core registers. */
4197 s_arm_unwind_save_core (void)
4203 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4206 as_bad (_("expected register list"));
4207 ignore_rest_of_line ();
4211 demand_empty_rest_of_line ();
4213 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4214 into .unwind_save {..., sp...}. We aren't bothered about the value of
4215 ip because it is clobbered by calls. */
4216 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4217 && (range
& 0x3000) == 0x1000)
4219 unwind
.opcode_count
--;
4220 unwind
.sp_restored
= 0;
4221 range
= (range
| 0x2000) & ~0x1000;
4222 unwind
.pending_offset
= 0;
4228 /* See if we can use the short opcodes. These pop a block of up to 8
4229 registers starting with r4, plus maybe r14. */
4230 for (n
= 0; n
< 8; n
++)
4232 /* Break at the first non-saved register. */
4233 if ((range
& (1 << (n
+ 4))) == 0)
4236 /* See if there are any other bits set. */
4237 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4239 /* Use the long form. */
4240 op
= 0x8000 | ((range
>> 4) & 0xfff);
4241 add_unwind_opcode (op
, 2);
4245 /* Use the short form. */
4247 op
= 0xa8; /* Pop r14. */
4249 op
= 0xa0; /* Do not pop r14. */
4251 add_unwind_opcode (op
, 1);
4258 op
= 0xb100 | (range
& 0xf);
4259 add_unwind_opcode (op
, 2);
4262 /* Record the number of bytes pushed. */
4263 for (n
= 0; n
< 16; n
++)
4265 if (range
& (1 << n
))
4266 unwind
.frame_size
+= 4;
4271 /* Parse a directive saving FPA registers. */
4274 s_arm_unwind_save_fpa (int reg
)
4280 /* Get Number of registers to transfer. */
4281 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4284 exp
.X_op
= O_illegal
;
4286 if (exp
.X_op
!= O_constant
)
4288 as_bad (_("expected , <constant>"));
4289 ignore_rest_of_line ();
4293 num_regs
= exp
.X_add_number
;
4295 if (num_regs
< 1 || num_regs
> 4)
4297 as_bad (_("number of registers must be in the range [1:4]"));
4298 ignore_rest_of_line ();
4302 demand_empty_rest_of_line ();
4307 op
= 0xb4 | (num_regs
- 1);
4308 add_unwind_opcode (op
, 1);
4313 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4314 add_unwind_opcode (op
, 2);
4316 unwind
.frame_size
+= num_regs
* 12;
4320 /* Parse a directive saving VFP registers for ARMv6 and above. */
4323 s_arm_unwind_save_vfp_armv6 (void)
4328 int num_vfpv3_regs
= 0;
4329 int num_regs_below_16
;
4330 bfd_boolean partial_match
;
4332 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4336 as_bad (_("expected register list"));
4337 ignore_rest_of_line ();
4341 demand_empty_rest_of_line ();
4343 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4344 than FSTMX/FLDMX-style ones). */
4346 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4348 num_vfpv3_regs
= count
;
4349 else if (start
+ count
> 16)
4350 num_vfpv3_regs
= start
+ count
- 16;
4352 if (num_vfpv3_regs
> 0)
4354 int start_offset
= start
> 16 ? start
- 16 : 0;
4355 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4356 add_unwind_opcode (op
, 2);
4359 /* Generate opcode for registers numbered in the range 0 .. 15. */
4360 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4361 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4362 if (num_regs_below_16
> 0)
4364 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4365 add_unwind_opcode (op
, 2);
4368 unwind
.frame_size
+= count
* 8;
4372 /* Parse a directive saving VFP registers for pre-ARMv6. */
4375 s_arm_unwind_save_vfp (void)
4380 bfd_boolean partial_match
;
4382 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4386 as_bad (_("expected register list"));
4387 ignore_rest_of_line ();
4391 demand_empty_rest_of_line ();
4396 op
= 0xb8 | (count
- 1);
4397 add_unwind_opcode (op
, 1);
4402 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4403 add_unwind_opcode (op
, 2);
4405 unwind
.frame_size
+= count
* 8 + 4;
4409 /* Parse a directive saving iWMMXt data registers. */
4412 s_arm_unwind_save_mmxwr (void)
4420 if (*input_line_pointer
== '{')
4421 input_line_pointer
++;
4425 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4429 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4434 as_tsktsk (_("register list not in ascending order"));
4437 if (*input_line_pointer
== '-')
4439 input_line_pointer
++;
4440 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4443 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4446 else if (reg
>= hi_reg
)
4448 as_bad (_("bad register range"));
4451 for (; reg
< hi_reg
; reg
++)
4455 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4457 skip_past_char (&input_line_pointer
, '}');
4459 demand_empty_rest_of_line ();
4461 /* Generate any deferred opcodes because we're going to be looking at
4463 flush_pending_unwind ();
4465 for (i
= 0; i
< 16; i
++)
4467 if (mask
& (1 << i
))
4468 unwind
.frame_size
+= 8;
4471 /* Attempt to combine with a previous opcode. We do this because gcc
4472 likes to output separate unwind directives for a single block of
4474 if (unwind
.opcode_count
> 0)
4476 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4477 if ((i
& 0xf8) == 0xc0)
4480 /* Only merge if the blocks are contiguous. */
4483 if ((mask
& 0xfe00) == (1 << 9))
4485 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4486 unwind
.opcode_count
--;
4489 else if (i
== 6 && unwind
.opcode_count
>= 2)
4491 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4495 op
= 0xffff << (reg
- 1);
4497 && ((mask
& op
) == (1u << (reg
- 1))))
4499 op
= (1 << (reg
+ i
+ 1)) - 1;
4500 op
&= ~((1 << reg
) - 1);
4502 unwind
.opcode_count
-= 2;
4509 /* We want to generate opcodes in the order the registers have been
4510 saved, ie. descending order. */
4511 for (reg
= 15; reg
>= -1; reg
--)
4513 /* Save registers in blocks. */
4515 || !(mask
& (1 << reg
)))
4517 /* We found an unsaved reg. Generate opcodes to save the
4524 op
= 0xc0 | (hi_reg
- 10);
4525 add_unwind_opcode (op
, 1);
4530 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4531 add_unwind_opcode (op
, 2);
4540 ignore_rest_of_line ();
4544 s_arm_unwind_save_mmxwcg (void)
4551 if (*input_line_pointer
== '{')
4552 input_line_pointer
++;
4554 skip_whitespace (input_line_pointer
);
4558 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4562 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4568 as_tsktsk (_("register list not in ascending order"));
4571 if (*input_line_pointer
== '-')
4573 input_line_pointer
++;
4574 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4577 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4580 else if (reg
>= hi_reg
)
4582 as_bad (_("bad register range"));
4585 for (; reg
< hi_reg
; reg
++)
4589 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4591 skip_past_char (&input_line_pointer
, '}');
4593 demand_empty_rest_of_line ();
4595 /* Generate any deferred opcodes because we're going to be looking at
4597 flush_pending_unwind ();
4599 for (reg
= 0; reg
< 16; reg
++)
4601 if (mask
& (1 << reg
))
4602 unwind
.frame_size
+= 4;
4605 add_unwind_opcode (op
, 2);
4608 ignore_rest_of_line ();
4612 /* Parse an unwind_save directive.
4613 If the argument is non-zero, this is a .vsave directive. */
4616 s_arm_unwind_save (int arch_v6
)
4619 struct reg_entry
*reg
;
4620 bfd_boolean had_brace
= FALSE
;
4622 if (!unwind
.proc_start
)
4623 as_bad (MISSING_FNSTART
);
4625 /* Figure out what sort of save we have. */
4626 peek
= input_line_pointer
;
4634 reg
= arm_reg_parse_multi (&peek
);
4638 as_bad (_("register expected"));
4639 ignore_rest_of_line ();
4648 as_bad (_("FPA .unwind_save does not take a register list"));
4649 ignore_rest_of_line ();
4652 input_line_pointer
= peek
;
4653 s_arm_unwind_save_fpa (reg
->number
);
4657 s_arm_unwind_save_core ();
4662 s_arm_unwind_save_vfp_armv6 ();
4664 s_arm_unwind_save_vfp ();
4667 case REG_TYPE_MMXWR
:
4668 s_arm_unwind_save_mmxwr ();
4671 case REG_TYPE_MMXWCG
:
4672 s_arm_unwind_save_mmxwcg ();
4676 as_bad (_(".unwind_save does not support this kind of register"));
4677 ignore_rest_of_line ();
4682 /* Parse an unwind_movsp directive. */
4685 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4691 if (!unwind
.proc_start
)
4692 as_bad (MISSING_FNSTART
);
4694 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4697 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4698 ignore_rest_of_line ();
4702 /* Optional constant. */
4703 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4705 if (immediate_for_directive (&offset
) == FAIL
)
4711 demand_empty_rest_of_line ();
4713 if (reg
== REG_SP
|| reg
== REG_PC
)
4715 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4719 if (unwind
.fp_reg
!= REG_SP
)
4720 as_bad (_("unexpected .unwind_movsp directive"));
4722 /* Generate opcode to restore the value. */
4724 add_unwind_opcode (op
, 1);
4726 /* Record the information for later. */
4727 unwind
.fp_reg
= reg
;
4728 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4729 unwind
.sp_restored
= 1;
4732 /* Parse an unwind_pad directive. */
4735 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4739 if (!unwind
.proc_start
)
4740 as_bad (MISSING_FNSTART
);
4742 if (immediate_for_directive (&offset
) == FAIL
)
4747 as_bad (_("stack increment must be multiple of 4"));
4748 ignore_rest_of_line ();
4752 /* Don't generate any opcodes, just record the details for later. */
4753 unwind
.frame_size
+= offset
;
4754 unwind
.pending_offset
+= offset
;
4756 demand_empty_rest_of_line ();
4759 /* Parse an unwind_setfp directive. */
4762 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4768 if (!unwind
.proc_start
)
4769 as_bad (MISSING_FNSTART
);
4771 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4772 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4775 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4777 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4779 as_bad (_("expected <reg>, <reg>"));
4780 ignore_rest_of_line ();
4784 /* Optional constant. */
4785 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4787 if (immediate_for_directive (&offset
) == FAIL
)
4793 demand_empty_rest_of_line ();
4795 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4797 as_bad (_("register must be either sp or set by a previous"
4798 "unwind_movsp directive"));
4802 /* Don't generate any opcodes, just record the information for later. */
4803 unwind
.fp_reg
= fp_reg
;
4805 if (sp_reg
== REG_SP
)
4806 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4808 unwind
.fp_offset
-= offset
;
4811 /* Parse an unwind_raw directive. */
4814 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4817 /* This is an arbitrary limit. */
4818 unsigned char op
[16];
4821 if (!unwind
.proc_start
)
4822 as_bad (MISSING_FNSTART
);
4825 if (exp
.X_op
== O_constant
4826 && skip_past_comma (&input_line_pointer
) != FAIL
)
4828 unwind
.frame_size
+= exp
.X_add_number
;
4832 exp
.X_op
= O_illegal
;
4834 if (exp
.X_op
!= O_constant
)
4836 as_bad (_("expected <offset>, <opcode>"));
4837 ignore_rest_of_line ();
4843 /* Parse the opcode. */
4848 as_bad (_("unwind opcode too long"));
4849 ignore_rest_of_line ();
4851 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4853 as_bad (_("invalid unwind opcode"));
4854 ignore_rest_of_line ();
4857 op
[count
++] = exp
.X_add_number
;
4859 /* Parse the next byte. */
4860 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4866 /* Add the opcode bytes in reverse order. */
4868 add_unwind_opcode (op
[count
], 1);
4870 demand_empty_rest_of_line ();
4874 /* Parse a .eabi_attribute directive. */
4877 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4879 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4881 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4882 attributes_set_explicitly
[tag
] = 1;
4885 /* Emit a tls fix for the symbol. */
4888 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4892 #ifdef md_flush_pending_output
4893 md_flush_pending_output ();
4896 #ifdef md_cons_align
4900 /* Since we're just labelling the code, there's no need to define a
4903 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4904 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4905 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4906 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4908 #endif /* OBJ_ELF */
4910 static void s_arm_arch (int);
4911 static void s_arm_object_arch (int);
4912 static void s_arm_cpu (int);
4913 static void s_arm_fpu (int);
4914 static void s_arm_arch_extension (int);
4919 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4926 if (exp
.X_op
== O_symbol
)
4927 exp
.X_op
= O_secrel
;
4929 emit_expr (&exp
, 4);
4931 while (*input_line_pointer
++ == ',');
4933 input_line_pointer
--;
4934 demand_empty_rest_of_line ();
4939 arm_is_largest_exponent_ok (int precision
)
4941 /* precision == 1 ensures that this will only return
4942 true for 16 bit floats. */
4943 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4947 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4951 enum fp_16bit_format new_format
;
4953 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4955 name
= input_line_pointer
;
4956 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4957 input_line_pointer
++;
4959 saved_char
= *input_line_pointer
;
4960 *input_line_pointer
= 0;
4962 if (strcasecmp (name
, "ieee") == 0)
4963 new_format
= ARM_FP16_FORMAT_IEEE
;
4964 else if (strcasecmp (name
, "alternative") == 0)
4965 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
4968 as_bad (_("unrecognised float16 format \"%s\""), name
);
4972 /* Only set fp16_format if it is still the default (aka not already
4974 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
4975 fp16_format
= new_format
;
4978 if (new_format
!= fp16_format
)
4979 as_warn (_("float16 format cannot be set more than once, ignoring."));
4983 *input_line_pointer
= saved_char
;
4984 ignore_rest_of_line ();
4987 /* This table describes all the machine specific pseudo-ops the assembler
4988 has to support. The fields are:
4989 pseudo-op name without dot
4990 function to call to execute this pseudo-op
4991 Integer arg to pass to the function. */
4993 const pseudo_typeS md_pseudo_table
[] =
4995 /* Never called because '.req' does not start a line. */
4996 { "req", s_req
, 0 },
4997 /* Following two are likewise never called. */
5000 { "unreq", s_unreq
, 0 },
5001 { "bss", s_bss
, 0 },
5002 { "align", s_align_ptwo
, 2 },
5003 { "arm", s_arm
, 0 },
5004 { "thumb", s_thumb
, 0 },
5005 { "code", s_code
, 0 },
5006 { "force_thumb", s_force_thumb
, 0 },
5007 { "thumb_func", s_thumb_func
, 0 },
5008 { "thumb_set", s_thumb_set
, 0 },
5009 { "even", s_even
, 0 },
5010 { "ltorg", s_ltorg
, 0 },
5011 { "pool", s_ltorg
, 0 },
5012 { "syntax", s_syntax
, 0 },
5013 { "cpu", s_arm_cpu
, 0 },
5014 { "arch", s_arm_arch
, 0 },
5015 { "object_arch", s_arm_object_arch
, 0 },
5016 { "fpu", s_arm_fpu
, 0 },
5017 { "arch_extension", s_arm_arch_extension
, 0 },
5019 { "word", s_arm_elf_cons
, 4 },
5020 { "long", s_arm_elf_cons
, 4 },
5021 { "inst.n", s_arm_elf_inst
, 2 },
5022 { "inst.w", s_arm_elf_inst
, 4 },
5023 { "inst", s_arm_elf_inst
, 0 },
5024 { "rel31", s_arm_rel31
, 0 },
5025 { "fnstart", s_arm_unwind_fnstart
, 0 },
5026 { "fnend", s_arm_unwind_fnend
, 0 },
5027 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5028 { "personality", s_arm_unwind_personality
, 0 },
5029 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5030 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5031 { "save", s_arm_unwind_save
, 0 },
5032 { "vsave", s_arm_unwind_save
, 1 },
5033 { "movsp", s_arm_unwind_movsp
, 0 },
5034 { "pad", s_arm_unwind_pad
, 0 },
5035 { "setfp", s_arm_unwind_setfp
, 0 },
5036 { "unwind_raw", s_arm_unwind_raw
, 0 },
5037 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5038 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5042 /* These are used for dwarf. */
5046 /* These are used for dwarf2. */
5047 { "file", dwarf2_directive_file
, 0 },
5048 { "loc", dwarf2_directive_loc
, 0 },
5049 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5051 { "extend", float_cons
, 'x' },
5052 { "ldouble", float_cons
, 'x' },
5053 { "packed", float_cons
, 'p' },
5055 {"secrel32", pe_directive_secrel
, 0},
5058 /* These are for compatibility with CodeComposer Studio. */
5059 {"ref", s_ccs_ref
, 0},
5060 {"def", s_ccs_def
, 0},
5061 {"asmfunc", s_ccs_asmfunc
, 0},
5062 {"endasmfunc", s_ccs_endasmfunc
, 0},
5064 {"float16", float_cons
, 'h' },
5065 {"float16_format", set_fp16_format
, 0 },
5070 /* Parser functions used exclusively in instruction operands. */
5072 /* Generic immediate-value read function for use in insn parsing.
5073 STR points to the beginning of the immediate (the leading #);
5074 VAL receives the value; if the value is outside [MIN, MAX]
5075 issue an error. PREFIX_OPT is true if the immediate prefix is
5079 parse_immediate (char **str
, int *val
, int min
, int max
,
5080 bfd_boolean prefix_opt
)
5084 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5085 if (exp
.X_op
!= O_constant
)
5087 inst
.error
= _("constant expression required");
5091 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5093 inst
.error
= _("immediate value out of range");
5097 *val
= exp
.X_add_number
;
5101 /* Less-generic immediate-value read function with the possibility of loading a
5102 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5103 instructions. Puts the result directly in inst.operands[i]. */
5106 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5107 bfd_boolean allow_symbol_p
)
5110 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5113 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5115 if (exp_p
->X_op
== O_constant
)
5117 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5118 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5119 O_constant. We have to be careful not to break compilation for
5120 32-bit X_add_number, though. */
5121 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5123 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5124 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5126 inst
.operands
[i
].regisimm
= 1;
5129 else if (exp_p
->X_op
== O_big
5130 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5132 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5134 /* Bignums have their least significant bits in
5135 generic_bignum[0]. Make sure we put 32 bits in imm and
5136 32 bits in reg, in a (hopefully) portable way. */
5137 gas_assert (parts
!= 0);
5139 /* Make sure that the number is not too big.
5140 PR 11972: Bignums can now be sign-extended to the
5141 size of a .octa so check that the out of range bits
5142 are all zero or all one. */
5143 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5145 LITTLENUM_TYPE m
= -1;
5147 if (generic_bignum
[parts
* 2] != 0
5148 && generic_bignum
[parts
* 2] != m
)
5151 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5152 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5156 inst
.operands
[i
].imm
= 0;
5157 for (j
= 0; j
< parts
; j
++, idx
++)
5158 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5159 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5160 inst
.operands
[i
].reg
= 0;
5161 for (j
= 0; j
< parts
; j
++, idx
++)
5162 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5163 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5164 inst
.operands
[i
].regisimm
= 1;
5166 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5174 /* Returns the pseudo-register number of an FPA immediate constant,
5175 or FAIL if there isn't a valid constant here. */
5178 parse_fpa_immediate (char ** str
)
5180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5186 /* First try and match exact strings, this is to guarantee
5187 that some formats will work even for cross assembly. */
5189 for (i
= 0; fp_const
[i
]; i
++)
5191 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5195 *str
+= strlen (fp_const
[i
]);
5196 if (is_end_of_line
[(unsigned char) **str
])
5202 /* Just because we didn't get a match doesn't mean that the constant
5203 isn't valid, just that it is in a format that we don't
5204 automatically recognize. Try parsing it with the standard
5205 expression routines. */
5207 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5209 /* Look for a raw floating point number. */
5210 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5211 && is_end_of_line
[(unsigned char) *save_in
])
5213 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5215 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5217 if (words
[j
] != fp_values
[i
][j
])
5221 if (j
== MAX_LITTLENUMS
)
5229 /* Try and parse a more complex expression, this will probably fail
5230 unless the code uses a floating point prefix (eg "0f"). */
5231 save_in
= input_line_pointer
;
5232 input_line_pointer
= *str
;
5233 if (expression (&exp
) == absolute_section
5234 && exp
.X_op
== O_big
5235 && exp
.X_add_number
< 0)
5237 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5239 #define X_PRECISION 5
5240 #define E_PRECISION 15L
5241 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5243 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5245 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5247 if (words
[j
] != fp_values
[i
][j
])
5251 if (j
== MAX_LITTLENUMS
)
5253 *str
= input_line_pointer
;
5254 input_line_pointer
= save_in
;
5261 *str
= input_line_pointer
;
5262 input_line_pointer
= save_in
;
5263 inst
.error
= _("invalid FPA immediate expression");
5267 /* Returns 1 if a number has "quarter-precision" float format
5268 0baBbbbbbc defgh000 00000000 00000000. */
5271 is_quarter_float (unsigned imm
)
5273 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5274 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5278 /* Detect the presence of a floating point or integer zero constant,
5282 parse_ifimm_zero (char **in
)
5286 if (!is_immediate_prefix (**in
))
5288 /* In unified syntax, all prefixes are optional. */
5289 if (!unified_syntax
)
5295 /* Accept #0x0 as a synonym for #0. */
5296 if (strncmp (*in
, "0x", 2) == 0)
5299 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5304 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5305 &generic_floating_point_number
);
5308 && generic_floating_point_number
.sign
== '+'
5309 && (generic_floating_point_number
.low
5310 > generic_floating_point_number
.leader
))
5316 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5317 0baBbbbbbc defgh000 00000000 00000000.
5318 The zero and minus-zero cases need special handling, since they can't be
5319 encoded in the "quarter-precision" float format, but can nonetheless be
5320 loaded as integer constants. */
5323 parse_qfloat_immediate (char **ccp
, int *immed
)
5327 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5328 int found_fpchar
= 0;
5330 skip_past_char (&str
, '#');
5332 /* We must not accidentally parse an integer as a floating-point number. Make
5333 sure that the value we parse is not an integer by checking for special
5334 characters '.' or 'e'.
5335 FIXME: This is a horrible hack, but doing better is tricky because type
5336 information isn't in a very usable state at parse time. */
5338 skip_whitespace (fpnum
);
5340 if (strncmp (fpnum
, "0x", 2) == 0)
5344 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5345 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5355 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5357 unsigned fpword
= 0;
5360 /* Our FP word must be 32 bits (single-precision FP). */
5361 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5363 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5367 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5380 /* Shift operands. */
5383 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5386 struct asm_shift_name
5389 enum shift_kind kind
;
5392 /* Third argument to parse_shift. */
5393 enum parse_shift_mode
5395 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5396 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5397 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5398 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5399 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5400 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5403 /* Parse a <shift> specifier on an ARM data processing instruction.
5404 This has three forms:
5406 (LSL|LSR|ASL|ASR|ROR) Rs
5407 (LSL|LSR|ASL|ASR|ROR) #imm
5410 Note that ASL is assimilated to LSL in the instruction encoding, and
5411 RRX to ROR #0 (which cannot be written as such). */
5414 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5416 const struct asm_shift_name
*shift_name
;
5417 enum shift_kind shift
;
5422 for (p
= *str
; ISALPHA (*p
); p
++)
5427 inst
.error
= _("shift expression expected");
5431 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5434 if (shift_name
== NULL
)
5436 inst
.error
= _("shift expression expected");
5440 shift
= shift_name
->kind
;
5444 case NO_SHIFT_RESTRICT
:
5445 case SHIFT_IMMEDIATE
:
5446 if (shift
== SHIFT_UXTW
)
5448 inst
.error
= _("'UXTW' not allowed here");
5453 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5454 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5456 inst
.error
= _("'LSL' or 'ASR' required");
5461 case SHIFT_LSL_IMMEDIATE
:
5462 if (shift
!= SHIFT_LSL
)
5464 inst
.error
= _("'LSL' required");
5469 case SHIFT_ASR_IMMEDIATE
:
5470 if (shift
!= SHIFT_ASR
)
5472 inst
.error
= _("'ASR' required");
5476 case SHIFT_UXTW_IMMEDIATE
:
5477 if (shift
!= SHIFT_UXTW
)
5479 inst
.error
= _("'UXTW' required");
5487 if (shift
!= SHIFT_RRX
)
5489 /* Whitespace can appear here if the next thing is a bare digit. */
5490 skip_whitespace (p
);
5492 if (mode
== NO_SHIFT_RESTRICT
5493 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5495 inst
.operands
[i
].imm
= reg
;
5496 inst
.operands
[i
].immisreg
= 1;
5498 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5501 inst
.operands
[i
].shift_kind
= shift
;
5502 inst
.operands
[i
].shifted
= 1;
5507 /* Parse a <shifter_operand> for an ARM data processing instruction:
5510 #<immediate>, <rotate>
5514 where <shift> is defined by parse_shift above, and <rotate> is a
5515 multiple of 2 between 0 and 30. Validation of immediate operands
5516 is deferred to md_apply_fix. */
5519 parse_shifter_operand (char **str
, int i
)
5524 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5526 inst
.operands
[i
].reg
= value
;
5527 inst
.operands
[i
].isreg
= 1;
5529 /* parse_shift will override this if appropriate */
5530 inst
.relocs
[0].exp
.X_op
= O_constant
;
5531 inst
.relocs
[0].exp
.X_add_number
= 0;
5533 if (skip_past_comma (str
) == FAIL
)
5536 /* Shift operation on register. */
5537 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5540 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5543 if (skip_past_comma (str
) == SUCCESS
)
5545 /* #x, y -- ie explicit rotation by Y. */
5546 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5549 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5551 inst
.error
= _("constant expression expected");
5555 value
= exp
.X_add_number
;
5556 if (value
< 0 || value
> 30 || value
% 2 != 0)
5558 inst
.error
= _("invalid rotation");
5561 if (inst
.relocs
[0].exp
.X_add_number
< 0
5562 || inst
.relocs
[0].exp
.X_add_number
> 255)
5564 inst
.error
= _("invalid constant");
5568 /* Encode as specified. */
5569 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5573 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5574 inst
.relocs
[0].pc_rel
= 0;
5578 /* Group relocation information. Each entry in the table contains the
5579 textual name of the relocation as may appear in assembler source
5580 and must end with a colon.
5581 Along with this textual name are the relocation codes to be used if
5582 the corresponding instruction is an ALU instruction (ADD or SUB only),
5583 an LDR, an LDRS, or an LDC. */
5585 struct group_reloc_table_entry
5596 /* Varieties of non-ALU group relocation. */
5604 static struct group_reloc_table_entry group_reloc_table
[] =
5605 { /* Program counter relative: */
5607 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5612 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5613 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5614 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5615 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5617 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5622 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5627 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5631 /* Section base relative */
5633 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5638 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5639 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5640 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5641 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5643 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5648 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5653 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5656 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5657 /* Absolute thumb alu relocations. */
5659 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5679 /* Given the address of a pointer pointing to the textual name of a group
5680 relocation as may appear in assembler source, attempt to find its details
5681 in group_reloc_table. The pointer will be updated to the character after
5682 the trailing colon. On failure, FAIL will be returned; SUCCESS
5683 otherwise. On success, *entry will be updated to point at the relevant
5684 group_reloc_table entry. */
5687 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5690 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5692 int length
= strlen (group_reloc_table
[i
].name
);
5694 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5695 && (*str
)[length
] == ':')
5697 *out
= &group_reloc_table
[i
];
5698 *str
+= (length
+ 1);
5706 /* Parse a <shifter_operand> for an ARM data processing instruction
5707 (as for parse_shifter_operand) where group relocations are allowed:
5710 #<immediate>, <rotate>
5711 #:<group_reloc>:<expression>
5715 where <group_reloc> is one of the strings defined in group_reloc_table.
5716 The hashes are optional.
5718 Everything else is as for parse_shifter_operand. */
5720 static parse_operand_result
5721 parse_shifter_operand_group_reloc (char **str
, int i
)
5723 /* Determine if we have the sequence of characters #: or just :
5724 coming next. If we do, then we check for a group relocation.
5725 If we don't, punt the whole lot to parse_shifter_operand. */
5727 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5728 || (*str
)[0] == ':')
5730 struct group_reloc_table_entry
*entry
;
5732 if ((*str
)[0] == '#')
5737 /* Try to parse a group relocation. Anything else is an error. */
5738 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5740 inst
.error
= _("unknown group relocation");
5741 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5744 /* We now have the group relocation table entry corresponding to
5745 the name in the assembler source. Next, we parse the expression. */
5746 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5747 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5749 /* Record the relocation type (always the ALU variant here). */
5750 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5751 gas_assert (inst
.relocs
[0].type
!= 0);
5753 return PARSE_OPERAND_SUCCESS
;
5756 return parse_shifter_operand (str
, i
) == SUCCESS
5757 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5759 /* Never reached. */
5762 /* Parse a Neon alignment expression. Information is written to
5763 inst.operands[i]. We assume the initial ':' has been skipped.
5765 align .imm = align << 8, .immisalign=1, .preind=0 */
5766 static parse_operand_result
5767 parse_neon_alignment (char **str
, int i
)
5772 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5774 if (exp
.X_op
!= O_constant
)
5776 inst
.error
= _("alignment must be constant");
5777 return PARSE_OPERAND_FAIL
;
5780 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5781 inst
.operands
[i
].immisalign
= 1;
5782 /* Alignments are not pre-indexes. */
5783 inst
.operands
[i
].preind
= 0;
5786 return PARSE_OPERAND_SUCCESS
;
5789 /* Parse all forms of an ARM address expression. Information is written
5790 to inst.operands[i] and/or inst.relocs[0].
5792 Preindexed addressing (.preind=1):
5794 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5795 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5796 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5797 .shift_kind=shift .relocs[0].exp=shift_imm
5799 These three may have a trailing ! which causes .writeback to be set also.
5801 Postindexed addressing (.postind=1, .writeback=1):
5803 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5804 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5805 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5806 .shift_kind=shift .relocs[0].exp=shift_imm
5808 Unindexed addressing (.preind=0, .postind=0):
5810 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5814 [Rn]{!} shorthand for [Rn,#0]{!}
5815 =immediate .isreg=0 .relocs[0].exp=immediate
5816 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5818 It is the caller's responsibility to check for addressing modes not
5819 supported by the instruction, and to set inst.relocs[0].type. */
5821 static parse_operand_result
5822 parse_address_main (char **str
, int i
, int group_relocations
,
5823 group_reloc_type group_type
)
5828 if (skip_past_char (&p
, '[') == FAIL
)
5830 if (skip_past_char (&p
, '=') == FAIL
)
5832 /* Bare address - translate to PC-relative offset. */
5833 inst
.relocs
[0].pc_rel
= 1;
5834 inst
.operands
[i
].reg
= REG_PC
;
5835 inst
.operands
[i
].isreg
= 1;
5836 inst
.operands
[i
].preind
= 1;
5838 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5839 return PARSE_OPERAND_FAIL
;
5841 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5842 /*allow_symbol_p=*/TRUE
))
5843 return PARSE_OPERAND_FAIL
;
5846 return PARSE_OPERAND_SUCCESS
;
5849 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5850 skip_whitespace (p
);
5852 if (group_type
== GROUP_MVE
)
5854 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5855 struct neon_type_el et
;
5856 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5858 inst
.operands
[i
].isquad
= 1;
5860 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5862 inst
.error
= BAD_ADDR_MODE
;
5863 return PARSE_OPERAND_FAIL
;
5866 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5868 if (group_type
== GROUP_MVE
)
5869 inst
.error
= BAD_ADDR_MODE
;
5871 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5872 return PARSE_OPERAND_FAIL
;
5874 inst
.operands
[i
].reg
= reg
;
5875 inst
.operands
[i
].isreg
= 1;
5877 if (skip_past_comma (&p
) == SUCCESS
)
5879 inst
.operands
[i
].preind
= 1;
5882 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5884 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5885 struct neon_type_el et
;
5886 if (group_type
== GROUP_MVE
5887 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5889 inst
.operands
[i
].immisreg
= 2;
5890 inst
.operands
[i
].imm
= reg
;
5892 if (skip_past_comma (&p
) == SUCCESS
)
5894 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5896 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5897 inst
.relocs
[0].exp
.X_add_number
= 0;
5900 return PARSE_OPERAND_FAIL
;
5903 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5905 inst
.operands
[i
].imm
= reg
;
5906 inst
.operands
[i
].immisreg
= 1;
5908 if (skip_past_comma (&p
) == SUCCESS
)
5909 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5910 return PARSE_OPERAND_FAIL
;
5912 else if (skip_past_char (&p
, ':') == SUCCESS
)
5914 /* FIXME: '@' should be used here, but it's filtered out by generic
5915 code before we get to see it here. This may be subject to
5917 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5919 if (result
!= PARSE_OPERAND_SUCCESS
)
5924 if (inst
.operands
[i
].negative
)
5926 inst
.operands
[i
].negative
= 0;
5930 if (group_relocations
5931 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5933 struct group_reloc_table_entry
*entry
;
5935 /* Skip over the #: or : sequence. */
5941 /* Try to parse a group relocation. Anything else is an
5943 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5945 inst
.error
= _("unknown group relocation");
5946 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5949 /* We now have the group relocation table entry corresponding to
5950 the name in the assembler source. Next, we parse the
5952 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5953 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5955 /* Record the relocation type. */
5960 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5965 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5970 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5977 if (inst
.relocs
[0].type
== 0)
5979 inst
.error
= _("this group relocation is not allowed on this instruction");
5980 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5987 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5988 return PARSE_OPERAND_FAIL
;
5989 /* If the offset is 0, find out if it's a +0 or -0. */
5990 if (inst
.relocs
[0].exp
.X_op
== O_constant
5991 && inst
.relocs
[0].exp
.X_add_number
== 0)
5993 skip_whitespace (q
);
5997 skip_whitespace (q
);
6000 inst
.operands
[i
].negative
= 1;
6005 else if (skip_past_char (&p
, ':') == SUCCESS
)
6007 /* FIXME: '@' should be used here, but it's filtered out by generic code
6008 before we get to see it here. This may be subject to change. */
6009 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6011 if (result
!= PARSE_OPERAND_SUCCESS
)
6015 if (skip_past_char (&p
, ']') == FAIL
)
6017 inst
.error
= _("']' expected");
6018 return PARSE_OPERAND_FAIL
;
6021 if (skip_past_char (&p
, '!') == SUCCESS
)
6022 inst
.operands
[i
].writeback
= 1;
6024 else if (skip_past_comma (&p
) == SUCCESS
)
6026 if (skip_past_char (&p
, '{') == SUCCESS
)
6028 /* [Rn], {expr} - unindexed, with option */
6029 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6030 0, 255, TRUE
) == FAIL
)
6031 return PARSE_OPERAND_FAIL
;
6033 if (skip_past_char (&p
, '}') == FAIL
)
6035 inst
.error
= _("'}' expected at end of 'option' field");
6036 return PARSE_OPERAND_FAIL
;
6038 if (inst
.operands
[i
].preind
)
6040 inst
.error
= _("cannot combine index with option");
6041 return PARSE_OPERAND_FAIL
;
6044 return PARSE_OPERAND_SUCCESS
;
6048 inst
.operands
[i
].postind
= 1;
6049 inst
.operands
[i
].writeback
= 1;
6051 if (inst
.operands
[i
].preind
)
6053 inst
.error
= _("cannot combine pre- and post-indexing");
6054 return PARSE_OPERAND_FAIL
;
6058 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6060 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6061 struct neon_type_el et
;
6062 if (group_type
== GROUP_MVE
6063 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6065 inst
.operands
[i
].immisreg
= 2;
6066 inst
.operands
[i
].imm
= reg
;
6068 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6070 /* We might be using the immediate for alignment already. If we
6071 are, OR the register number into the low-order bits. */
6072 if (inst
.operands
[i
].immisalign
)
6073 inst
.operands
[i
].imm
|= reg
;
6075 inst
.operands
[i
].imm
= reg
;
6076 inst
.operands
[i
].immisreg
= 1;
6078 if (skip_past_comma (&p
) == SUCCESS
)
6079 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6080 return PARSE_OPERAND_FAIL
;
6086 if (inst
.operands
[i
].negative
)
6088 inst
.operands
[i
].negative
= 0;
6091 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6092 return PARSE_OPERAND_FAIL
;
6093 /* If the offset is 0, find out if it's a +0 or -0. */
6094 if (inst
.relocs
[0].exp
.X_op
== O_constant
6095 && inst
.relocs
[0].exp
.X_add_number
== 0)
6097 skip_whitespace (q
);
6101 skip_whitespace (q
);
6104 inst
.operands
[i
].negative
= 1;
6110 /* If at this point neither .preind nor .postind is set, we have a
6111 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6112 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6114 inst
.operands
[i
].preind
= 1;
6115 inst
.relocs
[0].exp
.X_op
= O_constant
;
6116 inst
.relocs
[0].exp
.X_add_number
= 0;
6119 return PARSE_OPERAND_SUCCESS
;
6123 parse_address (char **str
, int i
)
6125 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6129 static parse_operand_result
6130 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6132 return parse_address_main (str
, i
, 1, type
);
6135 /* Parse an operand for a MOVW or MOVT instruction. */
6137 parse_half (char **str
)
6142 skip_past_char (&p
, '#');
6143 if (strncasecmp (p
, ":lower16:", 9) == 0)
6144 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6145 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6146 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6148 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6151 skip_whitespace (p
);
6154 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6157 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6159 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6161 inst
.error
= _("constant expression expected");
6164 if (inst
.relocs
[0].exp
.X_add_number
< 0
6165 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6167 inst
.error
= _("immediate value out of range");
6175 /* Miscellaneous. */
6177 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6178 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6180 parse_psr (char **str
, bfd_boolean lhs
)
6183 unsigned long psr_field
;
6184 const struct asm_psr
*psr
;
6186 bfd_boolean is_apsr
= FALSE
;
6187 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6189 /* PR gas/12698: If the user has specified -march=all then m_profile will
6190 be TRUE, but we want to ignore it in this case as we are building for any
6191 CPU type, including non-m variants. */
6192 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6195 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6196 feature for ease of use and backwards compatibility. */
6198 if (strncasecmp (p
, "SPSR", 4) == 0)
6201 goto unsupported_psr
;
6203 psr_field
= SPSR_BIT
;
6205 else if (strncasecmp (p
, "CPSR", 4) == 0)
6208 goto unsupported_psr
;
6212 else if (strncasecmp (p
, "APSR", 4) == 0)
6214 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6215 and ARMv7-R architecture CPUs. */
6224 while (ISALNUM (*p
) || *p
== '_');
6226 if (strncasecmp (start
, "iapsr", 5) == 0
6227 || strncasecmp (start
, "eapsr", 5) == 0
6228 || strncasecmp (start
, "xpsr", 4) == 0
6229 || strncasecmp (start
, "psr", 3) == 0)
6230 p
= start
+ strcspn (start
, "rR") + 1;
6232 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6238 /* If APSR is being written, a bitfield may be specified. Note that
6239 APSR itself is handled above. */
6240 if (psr
->field
<= 3)
6242 psr_field
= psr
->field
;
6248 /* M-profile MSR instructions have the mask field set to "10", except
6249 *PSR variants which modify APSR, which may use a different mask (and
6250 have been handled already). Do that by setting the PSR_f field
6252 return psr
->field
| (lhs
? PSR_f
: 0);
6255 goto unsupported_psr
;
6261 /* A suffix follows. */
6267 while (ISALNUM (*p
) || *p
== '_');
6271 /* APSR uses a notation for bits, rather than fields. */
6272 unsigned int nzcvq_bits
= 0;
6273 unsigned int g_bit
= 0;
6276 for (bit
= start
; bit
!= p
; bit
++)
6278 switch (TOLOWER (*bit
))
6281 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6285 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6289 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6293 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6297 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6301 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6305 inst
.error
= _("unexpected bit specified after APSR");
6310 if (nzcvq_bits
== 0x1f)
6315 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6317 inst
.error
= _("selected processor does not "
6318 "support DSP extension");
6325 if ((nzcvq_bits
& 0x20) != 0
6326 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6327 || (g_bit
& 0x2) != 0)
6329 inst
.error
= _("bad bitmask specified after APSR");
6335 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6340 psr_field
|= psr
->field
;
6346 goto error
; /* Garbage after "[CS]PSR". */
6348 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6349 is deprecated, but allow it anyway. */
6353 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6356 else if (!m_profile
)
6357 /* These bits are never right for M-profile devices: don't set them
6358 (only code paths which read/write APSR reach here). */
6359 psr_field
|= (PSR_c
| PSR_f
);
6365 inst
.error
= _("selected processor does not support requested special "
6366 "purpose register");
6370 inst
.error
= _("flag for {c}psr instruction expected");
6375 parse_sys_vldr_vstr (char **str
)
6384 {"FPSCR", 0x1, 0x0},
6385 {"FPSCR_nzcvqc", 0x2, 0x0},
6388 {"FPCXTNS", 0x6, 0x1},
6389 {"FPCXTS", 0x7, 0x1}
6391 char *op_end
= strchr (*str
, ',');
6392 size_t op_strlen
= op_end
- *str
;
6394 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6396 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6398 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6407 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6408 value suitable for splatting into the AIF field of the instruction. */
6411 parse_cps_flags (char **str
)
6420 case '\0': case ',':
6423 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6424 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6425 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6428 inst
.error
= _("unrecognized CPS flag");
6433 if (saw_a_flag
== 0)
6435 inst
.error
= _("missing CPS flags");
6443 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6444 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6447 parse_endian_specifier (char **str
)
6452 if (strncasecmp (s
, "BE", 2))
6454 else if (strncasecmp (s
, "LE", 2))
6458 inst
.error
= _("valid endian specifiers are be or le");
6462 if (ISALNUM (s
[2]) || s
[2] == '_')
6464 inst
.error
= _("valid endian specifiers are be or le");
6469 return little_endian
;
6472 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6473 value suitable for poking into the rotate field of an sxt or sxta
6474 instruction, or FAIL on error. */
6477 parse_ror (char **str
)
6482 if (strncasecmp (s
, "ROR", 3) == 0)
6486 inst
.error
= _("missing rotation field after comma");
6490 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6495 case 0: *str
= s
; return 0x0;
6496 case 8: *str
= s
; return 0x1;
6497 case 16: *str
= s
; return 0x2;
6498 case 24: *str
= s
; return 0x3;
6501 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6506 /* Parse a conditional code (from conds[] below). The value returned is in the
6507 range 0 .. 14, or FAIL. */
6509 parse_cond (char **str
)
6512 const struct asm_cond
*c
;
6514 /* Condition codes are always 2 characters, so matching up to
6515 3 characters is sufficient. */
6520 while (ISALPHA (*q
) && n
< 3)
6522 cond
[n
] = TOLOWER (*q
);
6527 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6530 inst
.error
= _("condition required");
6538 /* Parse an option for a barrier instruction. Returns the encoding for the
6541 parse_barrier (char **str
)
6544 const struct asm_barrier_opt
*o
;
6547 while (ISALPHA (*q
))
6550 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6555 if (!mark_feature_used (&o
->arch
))
6562 /* Parse the operands of a table branch instruction. Similar to a memory
6565 parse_tb (char **str
)
6570 if (skip_past_char (&p
, '[') == FAIL
)
6572 inst
.error
= _("'[' expected");
6576 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6578 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6581 inst
.operands
[0].reg
= reg
;
6583 if (skip_past_comma (&p
) == FAIL
)
6585 inst
.error
= _("',' expected");
6589 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6591 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6594 inst
.operands
[0].imm
= reg
;
6596 if (skip_past_comma (&p
) == SUCCESS
)
6598 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6600 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6602 inst
.error
= _("invalid shift");
6605 inst
.operands
[0].shifted
= 1;
6608 if (skip_past_char (&p
, ']') == FAIL
)
6610 inst
.error
= _("']' expected");
6617 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6618 information on the types the operands can take and how they are encoded.
6619 Up to four operands may be read; this function handles setting the
6620 ".present" field for each read operand itself.
6621 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6622 else returns FAIL. */
6625 parse_neon_mov (char **str
, int *which_operand
)
6627 int i
= *which_operand
, val
;
6628 enum arm_reg_type rtype
;
6630 struct neon_type_el optype
;
6632 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6634 /* Cases 17 or 19. */
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isvec
= 1;
6637 inst
.operands
[i
].isscalar
= 2;
6638 inst
.operands
[i
].vectype
= optype
;
6639 inst
.operands
[i
++].present
= 1;
6641 if (skip_past_comma (&ptr
) == FAIL
)
6644 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6646 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6647 inst
.operands
[i
].reg
= val
;
6648 inst
.operands
[i
].isreg
= 1;
6649 inst
.operands
[i
].present
= 1;
6651 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6653 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6654 inst
.operands
[i
].reg
= val
;
6655 inst
.operands
[i
].isvec
= 1;
6656 inst
.operands
[i
].isscalar
= 2;
6657 inst
.operands
[i
].vectype
= optype
;
6658 inst
.operands
[i
++].present
= 1;
6660 if (skip_past_comma (&ptr
) == FAIL
)
6663 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6666 inst
.operands
[i
].reg
= val
;
6667 inst
.operands
[i
].isreg
= 1;
6668 inst
.operands
[i
++].present
= 1;
6670 if (skip_past_comma (&ptr
) == FAIL
)
6673 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6682 first_error (_("expected ARM or MVE vector register"));
6686 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6688 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isscalar
= 1;
6691 inst
.operands
[i
].vectype
= optype
;
6692 inst
.operands
[i
++].present
= 1;
6694 if (skip_past_comma (&ptr
) == FAIL
)
6697 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.operands
[i
].reg
= val
;
6701 inst
.operands
[i
].isreg
= 1;
6702 inst
.operands
[i
].present
= 1;
6704 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6706 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6709 /* Cases 0, 1, 2, 3, 5 (D only). */
6710 if (skip_past_comma (&ptr
) == FAIL
)
6713 inst
.operands
[i
].reg
= val
;
6714 inst
.operands
[i
].isreg
= 1;
6715 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6716 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6717 inst
.operands
[i
].isvec
= 1;
6718 inst
.operands
[i
].vectype
= optype
;
6719 inst
.operands
[i
++].present
= 1;
6721 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6723 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6724 Case 13: VMOV <Sd>, <Rm> */
6725 inst
.operands
[i
].reg
= val
;
6726 inst
.operands
[i
].isreg
= 1;
6727 inst
.operands
[i
].present
= 1;
6729 if (rtype
== REG_TYPE_NQ
)
6731 first_error (_("can't use Neon quad register here"));
6734 else if (rtype
!= REG_TYPE_VFS
)
6737 if (skip_past_comma (&ptr
) == FAIL
)
6739 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6741 inst
.operands
[i
].reg
= val
;
6742 inst
.operands
[i
].isreg
= 1;
6743 inst
.operands
[i
].present
= 1;
6746 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6748 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6751 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6752 Case 1: VMOV<c><q> <Dd>, <Dm>
6753 Case 8: VMOV.F32 <Sd>, <Sm>
6754 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6756 inst
.operands
[i
].reg
= val
;
6757 inst
.operands
[i
].isreg
= 1;
6758 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6759 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6760 inst
.operands
[i
].isvec
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6762 inst
.operands
[i
].present
= 1;
6764 if (skip_past_comma (&ptr
) == SUCCESS
)
6769 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6772 inst
.operands
[i
].reg
= val
;
6773 inst
.operands
[i
].isreg
= 1;
6774 inst
.operands
[i
++].present
= 1;
6776 if (skip_past_comma (&ptr
) == FAIL
)
6779 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6782 inst
.operands
[i
].reg
= val
;
6783 inst
.operands
[i
].isreg
= 1;
6784 inst
.operands
[i
].present
= 1;
6787 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6788 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6789 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6790 Case 10: VMOV.F32 <Sd>, #<imm>
6791 Case 11: VMOV.F64 <Dd>, #<imm> */
6792 inst
.operands
[i
].immisfloat
= 1;
6793 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6795 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6796 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6800 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6804 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6806 /* Cases 6, 7, 16, 18. */
6807 inst
.operands
[i
].reg
= val
;
6808 inst
.operands
[i
].isreg
= 1;
6809 inst
.operands
[i
++].present
= 1;
6811 if (skip_past_comma (&ptr
) == FAIL
)
6814 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6816 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6817 inst
.operands
[i
].reg
= val
;
6818 inst
.operands
[i
].isscalar
= 2;
6819 inst
.operands
[i
].present
= 1;
6820 inst
.operands
[i
].vectype
= optype
;
6822 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6824 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isscalar
= 1;
6827 inst
.operands
[i
].present
= 1;
6828 inst
.operands
[i
].vectype
= optype
;
6830 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6832 inst
.operands
[i
].reg
= val
;
6833 inst
.operands
[i
].isreg
= 1;
6834 inst
.operands
[i
++].present
= 1;
6836 if (skip_past_comma (&ptr
) == FAIL
)
6839 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6842 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6844 inst
.operands
[i
].reg
= val
;
6845 inst
.operands
[i
].isreg
= 1;
6846 inst
.operands
[i
].isvec
= 1;
6847 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6848 inst
.operands
[i
].vectype
= optype
;
6849 inst
.operands
[i
].present
= 1;
6851 if (rtype
== REG_TYPE_VFS
)
6855 if (skip_past_comma (&ptr
) == FAIL
)
6857 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6860 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6863 inst
.operands
[i
].reg
= val
;
6864 inst
.operands
[i
].isreg
= 1;
6865 inst
.operands
[i
].isvec
= 1;
6866 inst
.operands
[i
].issingle
= 1;
6867 inst
.operands
[i
].vectype
= optype
;
6868 inst
.operands
[i
].present
= 1;
6873 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6876 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6877 inst
.operands
[i
].reg
= val
;
6878 inst
.operands
[i
].isvec
= 1;
6879 inst
.operands
[i
].isscalar
= 2;
6880 inst
.operands
[i
].vectype
= optype
;
6881 inst
.operands
[i
++].present
= 1;
6883 if (skip_past_comma (&ptr
) == FAIL
)
6886 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6889 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6892 inst
.operands
[i
].reg
= val
;
6893 inst
.operands
[i
].isvec
= 1;
6894 inst
.operands
[i
].isscalar
= 2;
6895 inst
.operands
[i
].vectype
= optype
;
6896 inst
.operands
[i
].present
= 1;
6900 first_error (_("VFP single, double or MVE vector register"
6906 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6910 inst
.operands
[i
].reg
= val
;
6911 inst
.operands
[i
].isreg
= 1;
6912 inst
.operands
[i
].isvec
= 1;
6913 inst
.operands
[i
].issingle
= 1;
6914 inst
.operands
[i
].vectype
= optype
;
6915 inst
.operands
[i
].present
= 1;
6920 first_error (_("parse error"));
6924 /* Successfully parsed the operands. Update args. */
6930 first_error (_("expected comma"));
6934 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6938 /* Use this macro when the operand constraints are different
6939 for ARM and THUMB (e.g. ldrd). */
6940 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6941 ((arm_operand) | ((thumb_operand) << 16))
6943 /* Matcher codes for parse_operands. */
6944 enum operand_parse_code
6946 OP_stop
, /* end of line */
6948 OP_RR
, /* ARM register */
6949 OP_RRnpc
, /* ARM register, not r15 */
6950 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6951 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6952 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6953 optional trailing ! */
6954 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6955 OP_RCP
, /* Coprocessor number */
6956 OP_RCN
, /* Coprocessor register */
6957 OP_RF
, /* FPA register */
6958 OP_RVS
, /* VFP single precision register */
6959 OP_RVD
, /* VFP double precision register (0..15) */
6960 OP_RND
, /* Neon double precision register (0..31) */
6961 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6962 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6964 OP_RNQ
, /* Neon quad precision register */
6965 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6966 OP_RVSD
, /* VFP single or double precision register */
6967 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6968 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6969 OP_RNSD
, /* Neon single or double precision register */
6970 OP_RNDQ
, /* Neon double or quad precision register */
6971 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6972 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6973 OP_RNSDQ
, /* Neon single, double or quad precision register */
6974 OP_RNSC
, /* Neon scalar D[X] */
6975 OP_RVC
, /* VFP control register */
6976 OP_RMF
, /* Maverick F register */
6977 OP_RMD
, /* Maverick D register */
6978 OP_RMFX
, /* Maverick FX register */
6979 OP_RMDX
, /* Maverick DX register */
6980 OP_RMAX
, /* Maverick AX register */
6981 OP_RMDS
, /* Maverick DSPSC register */
6982 OP_RIWR
, /* iWMMXt wR register */
6983 OP_RIWC
, /* iWMMXt wC register */
6984 OP_RIWG
, /* iWMMXt wCG register */
6985 OP_RXA
, /* XScale accumulator register */
6987 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6989 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6991 OP_RMQ
, /* MVE vector register. */
6992 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6993 OP_RMQRR
, /* MVE vector or ARM register. */
6995 /* New operands for Armv8.1-M Mainline. */
6996 OP_LR
, /* ARM LR register */
6997 OP_RRe
, /* ARM register, only even numbered. */
6998 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6999 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7000 OP_RR_ZR
, /* ARM register or ZR but no PC */
7002 OP_REGLST
, /* ARM register list */
7003 OP_CLRMLST
, /* CLRM register list */
7004 OP_VRSLST
, /* VFP single-precision register list */
7005 OP_VRDLST
, /* VFP double-precision register list */
7006 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7007 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7008 OP_NSTRLST
, /* Neon element/structure list */
7009 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7010 OP_MSTRLST2
, /* MVE vector list with two elements. */
7011 OP_MSTRLST4
, /* MVE vector list with four elements. */
7013 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7014 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7015 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7016 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7018 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7019 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7020 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7021 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7023 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7024 scalar, or ARM register. */
7025 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7026 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7027 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7029 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7030 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7031 OP_VMOV
, /* Neon VMOV operands. */
7032 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7033 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7035 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7036 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7038 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7039 OP_VLDR
, /* VLDR operand. */
7041 OP_I0
, /* immediate zero */
7042 OP_I7
, /* immediate value 0 .. 7 */
7043 OP_I15
, /* 0 .. 15 */
7044 OP_I16
, /* 1 .. 16 */
7045 OP_I16z
, /* 0 .. 16 */
7046 OP_I31
, /* 0 .. 31 */
7047 OP_I31w
, /* 0 .. 31, optional trailing ! */
7048 OP_I32
, /* 1 .. 32 */
7049 OP_I32z
, /* 0 .. 32 */
7050 OP_I48_I64
, /* 48 or 64 */
7051 OP_I63
, /* 0 .. 63 */
7052 OP_I63s
, /* -64 .. 63 */
7053 OP_I64
, /* 1 .. 64 */
7054 OP_I64z
, /* 0 .. 64 */
7055 OP_I255
, /* 0 .. 255 */
7057 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7058 OP_I7b
, /* 0 .. 7 */
7059 OP_I15b
, /* 0 .. 15 */
7060 OP_I31b
, /* 0 .. 31 */
7062 OP_SH
, /* shifter operand */
7063 OP_SHG
, /* shifter operand with possible group relocation */
7064 OP_ADDR
, /* Memory address expression (any mode) */
7065 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7066 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7067 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7068 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7069 OP_EXP
, /* arbitrary expression */
7070 OP_EXPi
, /* same, with optional immediate prefix */
7071 OP_EXPr
, /* same, with optional relocation suffix */
7072 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7073 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7074 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7075 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7077 OP_CPSF
, /* CPS flags */
7078 OP_ENDI
, /* Endianness specifier */
7079 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7080 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7081 OP_COND
, /* conditional code */
7082 OP_TB
, /* Table branch. */
7084 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7086 OP_RRnpc_I0
, /* ARM register or literal 0 */
7087 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7088 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7089 OP_RF_IF
, /* FPA register or immediate */
7090 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7091 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7093 /* Optional operands. */
7094 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7095 OP_oI31b
, /* 0 .. 31 */
7096 OP_oI32b
, /* 1 .. 32 */
7097 OP_oI32z
, /* 0 .. 32 */
7098 OP_oIffffb
, /* 0 .. 65535 */
7099 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7101 OP_oRR
, /* ARM register */
7102 OP_oLR
, /* ARM LR register */
7103 OP_oRRnpc
, /* ARM register, not the PC */
7104 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7105 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7106 OP_oRND
, /* Optional Neon double precision register */
7107 OP_oRNQ
, /* Optional Neon quad precision register */
7108 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7109 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7110 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7111 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7113 OP_oSHll
, /* LSL immediate */
7114 OP_oSHar
, /* ASR immediate */
7115 OP_oSHllar
, /* LSL or ASR immediate */
7116 OP_oROR
, /* ROR 0/8/16/24 */
7117 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7119 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7121 /* Some pre-defined mixed (ARM/THUMB) operands. */
7122 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7123 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7124 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7126 OP_FIRST_OPTIONAL
= OP_oI7b
7129 /* Generic instruction operand parser. This does no encoding and no
7130 semantic validation; it merely squirrels values away in the inst
7131 structure. Returns SUCCESS or FAIL depending on whether the
7132 specified grammar matched. */
7134 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7136 unsigned const int *upat
= pattern
;
7137 char *backtrack_pos
= 0;
7138 const char *backtrack_error
= 0;
7139 int i
, val
= 0, backtrack_index
= 0;
7140 enum arm_reg_type rtype
;
7141 parse_operand_result result
;
7142 unsigned int op_parse_code
;
7143 bfd_boolean partial_match
;
7145 #define po_char_or_fail(chr) \
7148 if (skip_past_char (&str, chr) == FAIL) \
7153 #define po_reg_or_fail(regtype) \
7156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7157 & inst.operands[i].vectype); \
7160 first_error (_(reg_expected_msgs[regtype])); \
7163 inst.operands[i].reg = val; \
7164 inst.operands[i].isreg = 1; \
7165 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7166 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7167 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7168 || rtype == REG_TYPE_VFD \
7169 || rtype == REG_TYPE_NQ); \
7170 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7174 #define po_reg_or_goto(regtype, label) \
7177 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7178 & inst.operands[i].vectype); \
7182 inst.operands[i].reg = val; \
7183 inst.operands[i].isreg = 1; \
7184 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7185 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7186 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7187 || rtype == REG_TYPE_VFD \
7188 || rtype == REG_TYPE_NQ); \
7189 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7193 #define po_imm_or_fail(min, max, popt) \
7196 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7198 inst.operands[i].imm = val; \
7202 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7206 my_get_expression (&exp, &str, popt); \
7207 if (exp.X_op != O_constant) \
7209 inst.error = _("constant expression required"); \
7212 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7214 inst.error = _("immediate value 48 or 64 expected"); \
7217 inst.operands[i].imm = exp.X_add_number; \
7221 #define po_scalar_or_goto(elsz, label, reg_type) \
7224 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7228 inst.operands[i].reg = val; \
7229 inst.operands[i].isscalar = 1; \
7233 #define po_misc_or_fail(expr) \
7241 #define po_misc_or_fail_no_backtrack(expr) \
7245 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7246 backtrack_pos = 0; \
7247 if (result != PARSE_OPERAND_SUCCESS) \
7252 #define po_barrier_or_imm(str) \
7255 val = parse_barrier (&str); \
7256 if (val == FAIL && ! ISALPHA (*str)) \
7259 /* ISB can only take SY as an option. */ \
7260 || ((inst.instruction & 0xf0) == 0x60 \
7263 inst.error = _("invalid barrier type"); \
7264 backtrack_pos = 0; \
7270 skip_whitespace (str
);
7272 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7274 op_parse_code
= upat
[i
];
7275 if (op_parse_code
>= 1<<16)
7276 op_parse_code
= thumb
? (op_parse_code
>> 16)
7277 : (op_parse_code
& ((1<<16)-1));
7279 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7281 /* Remember where we are in case we need to backtrack. */
7282 backtrack_pos
= str
;
7283 backtrack_error
= inst
.error
;
7284 backtrack_index
= i
;
7287 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7288 po_char_or_fail (',');
7290 switch (op_parse_code
)
7302 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7303 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7304 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7305 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7306 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7307 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7310 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7314 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7317 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7319 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7321 /* Also accept generic coprocessor regs for unknown registers. */
7323 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7325 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7326 existing register with a value of 0, this seems like the
7327 best way to parse P0. */
7329 if (strncasecmp (str
, "P0", 2) == 0)
7332 inst
.operands
[i
].isreg
= 1;
7333 inst
.operands
[i
].reg
= 13;
7338 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7339 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7340 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7341 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7342 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7343 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7344 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7345 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7346 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7347 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7350 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7353 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7354 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7356 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7361 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7365 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7367 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7370 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7372 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7375 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7377 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7382 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7385 po_reg_or_fail (REG_TYPE_NSDQ
);
7389 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7393 po_reg_or_fail (REG_TYPE_MQ
);
7395 /* Neon scalar. Using an element size of 8 means that some invalid
7396 scalars are accepted here, so deal with those in later code. */
7397 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7401 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7404 po_imm_or_fail (0, 0, TRUE
);
7409 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7413 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7418 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7421 if (parse_ifimm_zero (&str
))
7422 inst
.operands
[i
].imm
= 0;
7426 = _("only floating point zero is allowed as immediate value");
7434 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7437 po_reg_or_fail (REG_TYPE_RN
);
7441 case OP_RNSDQ_RNSC_MQ_RR
:
7442 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7445 case OP_RNSDQ_RNSC_MQ
:
7446 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7451 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7455 po_reg_or_fail (REG_TYPE_NSDQ
);
7462 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7465 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7468 po_reg_or_fail (REG_TYPE_NSD
);
7472 case OP_RNDQMQ_RNSC_RR
:
7473 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7476 case OP_RNDQ_RNSC_RR
:
7477 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7479 case OP_RNDQMQ_RNSC
:
7480 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7485 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7488 po_reg_or_fail (REG_TYPE_NDQ
);
7494 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7497 po_reg_or_fail (REG_TYPE_VFD
);
7502 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7503 not careful then bad things might happen. */
7504 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7507 case OP_RNDQMQ_Ibig
:
7508 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7513 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7516 /* There's a possibility of getting a 64-bit immediate here, so
7517 we need special handling. */
7518 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7521 inst
.error
= _("immediate value is out of range");
7527 case OP_RNDQMQ_I63b_RR
:
7528 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7531 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7536 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7539 po_imm_or_fail (0, 63, TRUE
);
7544 po_char_or_fail ('[');
7545 po_reg_or_fail (REG_TYPE_RN
);
7546 po_char_or_fail (']');
7552 po_reg_or_fail (REG_TYPE_RN
);
7553 if (skip_past_char (&str
, '!') == SUCCESS
)
7554 inst
.operands
[i
].writeback
= 1;
7558 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7559 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7560 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7561 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7562 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7563 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7564 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7565 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7566 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7567 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7568 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7569 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7570 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7572 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7574 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7575 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7577 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7578 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7579 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7580 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7582 /* Immediate variants */
7584 po_char_or_fail ('{');
7585 po_imm_or_fail (0, 255, TRUE
);
7586 po_char_or_fail ('}');
7590 /* The expression parser chokes on a trailing !, so we have
7591 to find it first and zap it. */
7594 while (*s
&& *s
!= ',')
7599 inst
.operands
[i
].writeback
= 1;
7601 po_imm_or_fail (0, 31, TRUE
);
7609 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7614 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7619 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7621 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7623 val
= parse_reloc (&str
);
7626 inst
.error
= _("unrecognized relocation suffix");
7629 else if (val
!= BFD_RELOC_UNUSED
)
7631 inst
.operands
[i
].imm
= val
;
7632 inst
.operands
[i
].hasreloc
= 1;
7638 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7640 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7642 inst
.operands
[i
].hasreloc
= 1;
7644 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7646 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7647 inst
.operands
[i
].hasreloc
= 0;
7651 /* Operand for MOVW or MOVT. */
7653 po_misc_or_fail (parse_half (&str
));
7656 /* Register or expression. */
7657 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7658 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7660 /* Register or immediate. */
7661 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7662 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7664 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7665 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7667 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7669 if (!is_immediate_prefix (*str
))
7672 val
= parse_fpa_immediate (&str
);
7675 /* FPA immediates are encoded as registers 8-15.
7676 parse_fpa_immediate has already applied the offset. */
7677 inst
.operands
[i
].reg
= val
;
7678 inst
.operands
[i
].isreg
= 1;
7681 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7682 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7684 /* Two kinds of register. */
7687 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7689 || (rege
->type
!= REG_TYPE_MMXWR
7690 && rege
->type
!= REG_TYPE_MMXWC
7691 && rege
->type
!= REG_TYPE_MMXWCG
))
7693 inst
.error
= _("iWMMXt data or control register expected");
7696 inst
.operands
[i
].reg
= rege
->number
;
7697 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7703 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7705 || (rege
->type
!= REG_TYPE_MMXWC
7706 && rege
->type
!= REG_TYPE_MMXWCG
))
7708 inst
.error
= _("iWMMXt control register expected");
7711 inst
.operands
[i
].reg
= rege
->number
;
7712 inst
.operands
[i
].isreg
= 1;
7717 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7718 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7719 case OP_oROR
: val
= parse_ror (&str
); break;
7721 case OP_COND
: val
= parse_cond (&str
); break;
7722 case OP_oBARRIER_I15
:
7723 po_barrier_or_imm (str
); break;
7725 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7731 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7732 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7734 inst
.error
= _("Banked registers are not available with this "
7740 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7744 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7747 val
= parse_sys_vldr_vstr (&str
);
7751 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7754 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7756 if (strncasecmp (str
, "APSR_", 5) == 0)
7763 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7764 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7765 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7766 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7767 default: found
= 16;
7771 inst
.operands
[i
].isvec
= 1;
7772 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7773 inst
.operands
[i
].reg
= REG_PC
;
7780 po_misc_or_fail (parse_tb (&str
));
7783 /* Register lists. */
7785 val
= parse_reg_list (&str
, REGLIST_RN
);
7788 inst
.operands
[i
].writeback
= 1;
7794 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7798 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7803 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7808 /* Allow Q registers too. */
7809 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7810 REGLIST_NEON_D
, &partial_match
);
7814 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7815 REGLIST_VFP_S
, &partial_match
);
7816 inst
.operands
[i
].issingle
= 1;
7821 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7822 REGLIST_VFP_D_VPR
, &partial_match
);
7823 if (val
== FAIL
&& !partial_match
)
7826 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7827 REGLIST_VFP_S_VPR
, &partial_match
);
7828 inst
.operands
[i
].issingle
= 1;
7833 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7834 REGLIST_NEON_D
, &partial_match
);
7839 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7840 1, &inst
.operands
[i
].vectype
);
7841 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7845 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7846 0, &inst
.operands
[i
].vectype
);
7849 /* Addressing modes */
7851 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7855 po_misc_or_fail (parse_address (&str
, i
));
7859 po_misc_or_fail_no_backtrack (
7860 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7864 po_misc_or_fail_no_backtrack (
7865 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7869 po_misc_or_fail_no_backtrack (
7870 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7874 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7878 po_misc_or_fail_no_backtrack (
7879 parse_shifter_operand_group_reloc (&str
, i
));
7883 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7887 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7891 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7896 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7901 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7904 po_reg_or_fail (REG_TYPE_ZR
);
7908 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7911 /* Various value-based sanity checks and shared operations. We
7912 do not signal immediate failures for the register constraints;
7913 this allows a syntax error to take precedence. */
7914 switch (op_parse_code
)
7922 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7923 inst
.error
= BAD_PC
;
7928 case OP_RRnpcsp_I32
:
7929 if (inst
.operands
[i
].isreg
)
7931 if (inst
.operands
[i
].reg
== REG_PC
)
7932 inst
.error
= BAD_PC
;
7933 else if (inst
.operands
[i
].reg
== REG_SP
7934 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7935 relaxed since ARMv8-A. */
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7939 inst
.error
= BAD_SP
;
7945 if (inst
.operands
[i
].isreg
7946 && inst
.operands
[i
].reg
== REG_PC
7947 && (inst
.operands
[i
].writeback
|| thumb
))
7948 inst
.error
= BAD_PC
;
7953 if (inst
.operands
[i
].isreg
)
7963 case OP_oBARRIER_I15
:
7976 inst
.operands
[i
].imm
= val
;
7981 if (inst
.operands
[i
].reg
!= REG_LR
)
7982 inst
.error
= _("operand must be LR register");
7988 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7989 inst
.error
= BAD_PC
;
7993 if (inst
.operands
[i
].isreg
7994 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7995 inst
.error
= BAD_ODD
;
7999 if (inst
.operands
[i
].isreg
)
8001 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8002 inst
.error
= BAD_EVEN
;
8003 else if (inst
.operands
[i
].reg
== REG_SP
)
8004 as_tsktsk (MVE_BAD_SP
);
8005 else if (inst
.operands
[i
].reg
== REG_PC
)
8006 inst
.error
= BAD_PC
;
8014 /* If we get here, this operand was successfully parsed. */
8015 inst
.operands
[i
].present
= 1;
8019 inst
.error
= BAD_ARGS
;
8024 /* The parse routine should already have set inst.error, but set a
8025 default here just in case. */
8027 inst
.error
= BAD_SYNTAX
;
8031 /* Do not backtrack over a trailing optional argument that
8032 absorbed some text. We will only fail again, with the
8033 'garbage following instruction' error message, which is
8034 probably less helpful than the current one. */
8035 if (backtrack_index
== i
&& backtrack_pos
!= str
8036 && upat
[i
+1] == OP_stop
)
8039 inst
.error
= BAD_SYNTAX
;
8043 /* Try again, skipping the optional argument at backtrack_pos. */
8044 str
= backtrack_pos
;
8045 inst
.error
= backtrack_error
;
8046 inst
.operands
[backtrack_index
].present
= 0;
8047 i
= backtrack_index
;
8051 /* Check that we have parsed all the arguments. */
8052 if (*str
!= '\0' && !inst
.error
)
8053 inst
.error
= _("garbage following instruction");
8055 return inst
.error
? FAIL
: SUCCESS
;
8058 #undef po_char_or_fail
8059 #undef po_reg_or_fail
8060 #undef po_reg_or_goto
8061 #undef po_imm_or_fail
8062 #undef po_scalar_or_fail
8063 #undef po_barrier_or_imm
8065 /* Shorthand macro for instruction encoding functions issuing errors. */
8066 #define constraint(expr, err) \
8077 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8078 instructions are unpredictable if these registers are used. This
8079 is the BadReg predicate in ARM's Thumb-2 documentation.
8081 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8082 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8083 #define reject_bad_reg(reg) \
8085 if (reg == REG_PC) \
8087 inst.error = BAD_PC; \
8090 else if (reg == REG_SP \
8091 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8093 inst.error = BAD_SP; \
8098 /* If REG is R13 (the stack pointer), warn that its use is
8100 #define warn_deprecated_sp(reg) \
8102 if (warn_on_deprecated && reg == REG_SP) \
8103 as_tsktsk (_("use of r13 is deprecated")); \
8106 /* Functions for operand encoding. ARM, then Thumb. */
8108 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8110 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8112 The only binary encoding difference is the Coprocessor number. Coprocessor
8113 9 is used for half-precision calculations or conversions. The format of the
8114 instruction is the same as the equivalent Coprocessor 10 instruction that
8115 exists for Single-Precision operation. */
8118 do_scalar_fp16_v82_encode (void)
8120 if (inst
.cond
< COND_ALWAYS
)
8121 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8122 " the behaviour is UNPREDICTABLE"));
8123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8126 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8127 mark_feature_used (&arm_ext_fp16
);
8130 /* If VAL can be encoded in the immediate field of an ARM instruction,
8131 return the encoded form. Otherwise, return FAIL. */
8134 encode_arm_immediate (unsigned int val
)
8141 for (i
= 2; i
< 32; i
+= 2)
8142 if ((a
= rotate_left (val
, i
)) <= 0xff)
8143 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8148 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8149 return the encoded form. Otherwise, return FAIL. */
8151 encode_thumb32_immediate (unsigned int val
)
8158 for (i
= 1; i
<= 24; i
++)
8161 if ((val
& ~(0xff << i
)) == 0)
8162 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8166 if (val
== ((a
<< 16) | a
))
8168 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8172 if (val
== ((a
<< 16) | a
))
8173 return 0x200 | (a
>> 8);
8177 /* Encode a VFP SP or DP register number into inst.instruction. */
8180 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8182 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8185 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8188 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8191 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8196 first_error (_("D register out of range for selected VFP version"));
8204 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8208 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8212 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8216 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8220 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8224 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8232 /* Encode a <shift> in an ARM-format instruction. The immediate,
8233 if any, is handled by md_apply_fix. */
8235 encode_arm_shift (int i
)
8237 /* register-shifted register. */
8238 if (inst
.operands
[i
].immisreg
)
8241 for (op_index
= 0; op_index
<= i
; ++op_index
)
8243 /* Check the operand only when it's presented. In pre-UAL syntax,
8244 if the destination register is the same as the first operand, two
8245 register form of the instruction can be used. */
8246 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8247 && inst
.operands
[op_index
].reg
== REG_PC
)
8248 as_warn (UNPRED_REG ("r15"));
8251 if (inst
.operands
[i
].imm
== REG_PC
)
8252 as_warn (UNPRED_REG ("r15"));
8255 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8256 inst
.instruction
|= SHIFT_ROR
<< 5;
8259 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8260 if (inst
.operands
[i
].immisreg
)
8262 inst
.instruction
|= SHIFT_BY_REG
;
8263 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8266 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8271 encode_arm_shifter_operand (int i
)
8273 if (inst
.operands
[i
].isreg
)
8275 inst
.instruction
|= inst
.operands
[i
].reg
;
8276 encode_arm_shift (i
);
8280 inst
.instruction
|= INST_IMMEDIATE
;
8281 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8282 inst
.instruction
|= inst
.operands
[i
].imm
;
8286 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8288 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8291 Generate an error if the operand is not a register. */
8292 constraint (!inst
.operands
[i
].isreg
,
8293 _("Instruction does not support =N addresses"));
8295 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8297 if (inst
.operands
[i
].preind
)
8301 inst
.error
= _("instruction does not accept preindexed addressing");
8304 inst
.instruction
|= PRE_INDEX
;
8305 if (inst
.operands
[i
].writeback
)
8306 inst
.instruction
|= WRITE_BACK
;
8309 else if (inst
.operands
[i
].postind
)
8311 gas_assert (inst
.operands
[i
].writeback
);
8313 inst
.instruction
|= WRITE_BACK
;
8315 else /* unindexed - only for coprocessor */
8317 inst
.error
= _("instruction does not accept unindexed addressing");
8321 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8322 && (((inst
.instruction
& 0x000f0000) >> 16)
8323 == ((inst
.instruction
& 0x0000f000) >> 12)))
8324 as_warn ((inst
.instruction
& LOAD_BIT
)
8325 ? _("destination register same as write-back base")
8326 : _("source register same as write-back base"));
8329 /* inst.operands[i] was set up by parse_address. Encode it into an
8330 ARM-format mode 2 load or store instruction. If is_t is true,
8331 reject forms that cannot be used with a T instruction (i.e. not
8334 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8336 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8338 encode_arm_addr_mode_common (i
, is_t
);
8340 if (inst
.operands
[i
].immisreg
)
8342 constraint ((inst
.operands
[i
].imm
== REG_PC
8343 || (is_pc
&& inst
.operands
[i
].writeback
)),
8345 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8346 inst
.instruction
|= inst
.operands
[i
].imm
;
8347 if (!inst
.operands
[i
].negative
)
8348 inst
.instruction
|= INDEX_UP
;
8349 if (inst
.operands
[i
].shifted
)
8351 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8352 inst
.instruction
|= SHIFT_ROR
<< 5;
8355 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8356 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8360 else /* immediate offset in inst.relocs[0] */
8362 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8364 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8366 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8367 cannot use PC in addressing.
8368 PC cannot be used in writeback addressing, either. */
8369 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8372 /* Use of PC in str is deprecated for ARMv7. */
8373 if (warn_on_deprecated
8375 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8376 as_tsktsk (_("use of PC in this instruction is deprecated"));
8379 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8381 /* Prefer + for zero encoded value. */
8382 if (!inst
.operands
[i
].negative
)
8383 inst
.instruction
|= INDEX_UP
;
8384 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8389 /* inst.operands[i] was set up by parse_address. Encode it into an
8390 ARM-format mode 3 load or store instruction. Reject forms that
8391 cannot be used with such instructions. If is_t is true, reject
8392 forms that cannot be used with a T instruction (i.e. not
8395 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8397 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8399 inst
.error
= _("instruction does not accept scaled register index");
8403 encode_arm_addr_mode_common (i
, is_t
);
8405 if (inst
.operands
[i
].immisreg
)
8407 constraint ((inst
.operands
[i
].imm
== REG_PC
8408 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8410 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8412 inst
.instruction
|= inst
.operands
[i
].imm
;
8413 if (!inst
.operands
[i
].negative
)
8414 inst
.instruction
|= INDEX_UP
;
8416 else /* immediate offset in inst.relocs[0] */
8418 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8419 && inst
.operands
[i
].writeback
),
8421 inst
.instruction
|= HWOFFSET_IMM
;
8422 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8424 /* Prefer + for zero encoded value. */
8425 if (!inst
.operands
[i
].negative
)
8426 inst
.instruction
|= INDEX_UP
;
8428 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8433 /* Write immediate bits [7:0] to the following locations:
8435 |28/24|23 19|18 16|15 4|3 0|
8436 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8438 This function is used by VMOV/VMVN/VORR/VBIC. */
8441 neon_write_immbits (unsigned immbits
)
8443 inst
.instruction
|= immbits
& 0xf;
8444 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8445 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8448 /* Invert low-order SIZE bits of XHI:XLO. */
8451 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8453 unsigned immlo
= xlo
? *xlo
: 0;
8454 unsigned immhi
= xhi
? *xhi
: 0;
8459 immlo
= (~immlo
) & 0xff;
8463 immlo
= (~immlo
) & 0xffff;
8467 immhi
= (~immhi
) & 0xffffffff;
8471 immlo
= (~immlo
) & 0xffffffff;
8485 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8489 neon_bits_same_in_bytes (unsigned imm
)
8491 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8492 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8493 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8494 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8497 /* For immediate of above form, return 0bABCD. */
8500 neon_squash_bits (unsigned imm
)
8502 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8503 | ((imm
& 0x01000000) >> 21);
8506 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8509 neon_qfloat_bits (unsigned imm
)
8511 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8514 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8515 the instruction. *OP is passed as the initial value of the op field, and
8516 may be set to a different value depending on the constant (i.e.
8517 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8518 MVN). If the immediate looks like a repeated pattern then also
8519 try smaller element sizes. */
8522 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8523 unsigned *immbits
, int *op
, int size
,
8524 enum neon_el_type type
)
8526 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8528 if (type
== NT_float
&& !float_p
)
8531 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8533 if (size
!= 32 || *op
== 1)
8535 *immbits
= neon_qfloat_bits (immlo
);
8541 if (neon_bits_same_in_bytes (immhi
)
8542 && neon_bits_same_in_bytes (immlo
))
8546 *immbits
= (neon_squash_bits (immhi
) << 4)
8547 | neon_squash_bits (immlo
);
8558 if (immlo
== (immlo
& 0x000000ff))
8563 else if (immlo
== (immlo
& 0x0000ff00))
8565 *immbits
= immlo
>> 8;
8568 else if (immlo
== (immlo
& 0x00ff0000))
8570 *immbits
= immlo
>> 16;
8573 else if (immlo
== (immlo
& 0xff000000))
8575 *immbits
= immlo
>> 24;
8578 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8580 *immbits
= (immlo
>> 8) & 0xff;
8583 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8585 *immbits
= (immlo
>> 16) & 0xff;
8589 if ((immlo
& 0xffff) != (immlo
>> 16))
8596 if (immlo
== (immlo
& 0x000000ff))
8601 else if (immlo
== (immlo
& 0x0000ff00))
8603 *immbits
= immlo
>> 8;
8607 if ((immlo
& 0xff) != (immlo
>> 8))
8612 if (immlo
== (immlo
& 0x000000ff))
8614 /* Don't allow MVN with 8-bit immediate. */
8624 #if defined BFD_HOST_64_BIT
8625 /* Returns TRUE if double precision value V may be cast
8626 to single precision without loss of accuracy. */
8629 is_double_a_single (bfd_int64_t v
)
8631 int exp
= (int)((v
>> 52) & 0x7FF);
8632 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8634 return (exp
== 0 || exp
== 0x7FF
8635 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8636 && (mantissa
& 0x1FFFFFFFl
) == 0;
8639 /* Returns a double precision value casted to single precision
8640 (ignoring the least significant bits in exponent and mantissa). */
8643 double_to_single (bfd_int64_t v
)
8645 int sign
= (int) ((v
>> 63) & 1l);
8646 int exp
= (int) ((v
>> 52) & 0x7FF);
8647 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8653 exp
= exp
- 1023 + 127;
8662 /* No denormalized numbers. */
8668 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8670 #endif /* BFD_HOST_64_BIT */
8679 static void do_vfp_nsyn_opcode (const char *);
8681 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8682 Determine whether it can be performed with a move instruction; if
8683 it can, convert inst.instruction to that move instruction and
8684 return TRUE; if it can't, convert inst.instruction to a literal-pool
8685 load and return FALSE. If this is not a valid thing to do in the
8686 current context, set inst.error and return TRUE.
8688 inst.operands[i] describes the destination register. */
8691 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8694 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8695 bfd_boolean arm_p
= (t
== CONST_ARM
);
8698 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8702 if ((inst
.instruction
& tbit
) == 0)
8704 inst
.error
= _("invalid pseudo operation");
8708 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8709 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8710 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8712 inst
.error
= _("constant expression expected");
8716 if (inst
.relocs
[0].exp
.X_op
== O_constant
8717 || inst
.relocs
[0].exp
.X_op
== O_big
)
8719 #if defined BFD_HOST_64_BIT
8724 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8726 LITTLENUM_TYPE w
[X_PRECISION
];
8729 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8731 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8733 /* FIXME: Should we check words w[2..5] ? */
8738 #if defined BFD_HOST_64_BIT
8740 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8741 << LITTLENUM_NUMBER_OF_BITS
)
8742 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8743 << LITTLENUM_NUMBER_OF_BITS
)
8744 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8745 << LITTLENUM_NUMBER_OF_BITS
)
8746 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8748 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8749 | (l
[0] & LITTLENUM_MASK
);
8753 v
= inst
.relocs
[0].exp
.X_add_number
;
8755 if (!inst
.operands
[i
].issingle
)
8759 /* LDR should not use lead in a flag-setting instruction being
8760 chosen so we do not check whether movs can be used. */
8762 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8763 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8764 && inst
.operands
[i
].reg
!= 13
8765 && inst
.operands
[i
].reg
!= 15)
8767 /* Check if on thumb2 it can be done with a mov.w, mvn or
8768 movw instruction. */
8769 unsigned int newimm
;
8770 bfd_boolean isNegated
;
8772 newimm
= encode_thumb32_immediate (v
);
8773 if (newimm
!= (unsigned int) FAIL
)
8777 newimm
= encode_thumb32_immediate (~v
);
8778 if (newimm
!= (unsigned int) FAIL
)
8782 /* The number can be loaded with a mov.w or mvn
8784 if (newimm
!= (unsigned int) FAIL
8785 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8787 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8788 | (inst
.operands
[i
].reg
<< 8));
8789 /* Change to MOVN. */
8790 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8791 inst
.instruction
|= (newimm
& 0x800) << 15;
8792 inst
.instruction
|= (newimm
& 0x700) << 4;
8793 inst
.instruction
|= (newimm
& 0x0ff);
8796 /* The number can be loaded with a movw instruction. */
8797 else if ((v
& ~0xFFFF) == 0
8798 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8800 int imm
= v
& 0xFFFF;
8802 inst
.instruction
= 0xf2400000; /* MOVW. */
8803 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8804 inst
.instruction
|= (imm
& 0xf000) << 4;
8805 inst
.instruction
|= (imm
& 0x0800) << 15;
8806 inst
.instruction
|= (imm
& 0x0700) << 4;
8807 inst
.instruction
|= (imm
& 0x00ff);
8808 /* In case this replacement is being done on Armv8-M
8809 Baseline we need to make sure to disable the
8810 instruction size check, as otherwise GAS will reject
8811 the use of this T32 instruction. */
8819 int value
= encode_arm_immediate (v
);
8823 /* This can be done with a mov instruction. */
8824 inst
.instruction
&= LITERAL_MASK
;
8825 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8826 inst
.instruction
|= value
& 0xfff;
8830 value
= encode_arm_immediate (~ v
);
8833 /* This can be done with a mvn instruction. */
8834 inst
.instruction
&= LITERAL_MASK
;
8835 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8836 inst
.instruction
|= value
& 0xfff;
8840 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8843 unsigned immbits
= 0;
8844 unsigned immlo
= inst
.operands
[1].imm
;
8845 unsigned immhi
= inst
.operands
[1].regisimm
8846 ? inst
.operands
[1].reg
8847 : inst
.relocs
[0].exp
.X_unsigned
8849 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8850 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8851 &op
, 64, NT_invtype
);
8855 neon_invert_size (&immlo
, &immhi
, 64);
8857 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8858 &op
, 64, NT_invtype
);
8863 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8869 /* Fill other bits in vmov encoding for both thumb and arm. */
8871 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8873 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8874 neon_write_immbits (immbits
);
8882 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8883 if (inst
.operands
[i
].issingle
8884 && is_quarter_float (inst
.operands
[1].imm
)
8885 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8887 inst
.operands
[1].imm
=
8888 neon_qfloat_bits (v
);
8889 do_vfp_nsyn_opcode ("fconsts");
8893 /* If our host does not support a 64-bit type then we cannot perform
8894 the following optimization. This mean that there will be a
8895 discrepancy between the output produced by an assembler built for
8896 a 32-bit-only host and the output produced from a 64-bit host, but
8897 this cannot be helped. */
8898 #if defined BFD_HOST_64_BIT
8899 else if (!inst
.operands
[1].issingle
8900 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8902 if (is_double_a_single (v
)
8903 && is_quarter_float (double_to_single (v
)))
8905 inst
.operands
[1].imm
=
8906 neon_qfloat_bits (double_to_single (v
));
8907 do_vfp_nsyn_opcode ("fconstd");
8915 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8916 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8919 inst
.operands
[1].reg
= REG_PC
;
8920 inst
.operands
[1].isreg
= 1;
8921 inst
.operands
[1].preind
= 1;
8922 inst
.relocs
[0].pc_rel
= 1;
8923 inst
.relocs
[0].type
= (thumb_p
8924 ? BFD_RELOC_ARM_THUMB_OFFSET
8926 ? BFD_RELOC_ARM_HWLITERAL
8927 : BFD_RELOC_ARM_LITERAL
));
8931 /* inst.operands[i] was set up by parse_address. Encode it into an
8932 ARM-format instruction. Reject all forms which cannot be encoded
8933 into a coprocessor load/store instruction. If wb_ok is false,
8934 reject use of writeback; if unind_ok is false, reject use of
8935 unindexed addressing. If reloc_override is not 0, use it instead
8936 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8937 (in which case it is preserved). */
8940 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8942 if (!inst
.operands
[i
].isreg
)
8945 if (! inst
.operands
[0].isvec
)
8947 inst
.error
= _("invalid co-processor operand");
8950 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8954 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8956 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8958 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8960 gas_assert (!inst
.operands
[i
].writeback
);
8963 inst
.error
= _("instruction does not support unindexed addressing");
8966 inst
.instruction
|= inst
.operands
[i
].imm
;
8967 inst
.instruction
|= INDEX_UP
;
8971 if (inst
.operands
[i
].preind
)
8972 inst
.instruction
|= PRE_INDEX
;
8974 if (inst
.operands
[i
].writeback
)
8976 if (inst
.operands
[i
].reg
== REG_PC
)
8978 inst
.error
= _("pc may not be used with write-back");
8983 inst
.error
= _("instruction does not support writeback");
8986 inst
.instruction
|= WRITE_BACK
;
8990 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8991 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8992 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8993 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8996 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8998 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9001 /* Prefer + for zero encoded value. */
9002 if (!inst
.operands
[i
].negative
)
9003 inst
.instruction
|= INDEX_UP
;
9008 /* Functions for instruction encoding, sorted by sub-architecture.
9009 First some generics; their names are taken from the conventional
9010 bit positions for register arguments in ARM format instructions. */
9020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9033 inst
.instruction
|= inst
.operands
[1].reg
;
9039 inst
.instruction
|= inst
.operands
[0].reg
;
9040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9053 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9054 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9060 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9065 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9067 if (ARM_CPU_IS_ANY (cpu_variant
))
9069 as_tsktsk ("%s", msg
);
9072 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9084 unsigned Rn
= inst
.operands
[2].reg
;
9085 /* Enforce restrictions on SWP instruction. */
9086 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9088 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9089 _("Rn must not overlap other operands"));
9091 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9093 if (!check_obsolete (&arm_ext_v8
,
9094 _("swp{b} use is obsoleted for ARMv8 and later"))
9095 && warn_on_deprecated
9096 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9097 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].reg
;
9102 inst
.instruction
|= Rn
<< 16;
9108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9109 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9110 inst
.instruction
|= inst
.operands
[2].reg
;
9116 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9117 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9118 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9119 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9121 inst
.instruction
|= inst
.operands
[0].reg
;
9122 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9123 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9129 inst
.instruction
|= inst
.operands
[0].imm
;
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9139 /* ARM instructions, in alphabetical order by function name (except
9140 that wrapper functions appear immediately after the function they
9143 /* This is a pseudo-op of the form "adr rd, label" to be converted
9144 into a relative address of the form "add rd, pc, #label-.-8". */
9149 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9151 /* Frag hacking will turn this into a sub instruction if the offset turns
9152 out to be negative. */
9153 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9154 inst
.relocs
[0].pc_rel
= 1;
9155 inst
.relocs
[0].exp
.X_add_number
-= 8;
9157 if (support_interwork
9158 && inst
.relocs
[0].exp
.X_op
== O_symbol
9159 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9160 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9161 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9162 inst
.relocs
[0].exp
.X_add_number
|= 1;
9165 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9166 into a relative address of the form:
9167 add rd, pc, #low(label-.-8)"
9168 add rd, rd, #high(label-.-8)" */
9173 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9175 /* Frag hacking will turn this into a sub instruction if the offset turns
9176 out to be negative. */
9177 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9178 inst
.relocs
[0].pc_rel
= 1;
9179 inst
.size
= INSN_SIZE
* 2;
9180 inst
.relocs
[0].exp
.X_add_number
-= 8;
9182 if (support_interwork
9183 && inst
.relocs
[0].exp
.X_op
== O_symbol
9184 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9185 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9186 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9187 inst
.relocs
[0].exp
.X_add_number
|= 1;
9193 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9194 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9196 if (!inst
.operands
[1].present
)
9197 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9200 encode_arm_shifter_operand (2);
9206 if (inst
.operands
[0].present
)
9207 inst
.instruction
|= inst
.operands
[0].imm
;
9209 inst
.instruction
|= 0xf;
9215 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9216 constraint (msb
> 32, _("bit-field extends past end of register"));
9217 /* The instruction encoding stores the LSB and MSB,
9218 not the LSB and width. */
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9221 inst
.instruction
|= (msb
- 1) << 16;
9229 /* #0 in second position is alternative syntax for bfc, which is
9230 the same instruction but with REG_PC in the Rm field. */
9231 if (!inst
.operands
[1].isreg
)
9232 inst
.operands
[1].reg
= REG_PC
;
9234 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9235 constraint (msb
> 32, _("bit-field extends past end of register"));
9236 /* The instruction encoding stores the LSB and MSB,
9237 not the LSB and width. */
9238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9239 inst
.instruction
|= inst
.operands
[1].reg
;
9240 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9241 inst
.instruction
|= (msb
- 1) << 16;
9247 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9248 _("bit-field extends past end of register"));
9249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9250 inst
.instruction
|= inst
.operands
[1].reg
;
9251 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9252 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9255 /* ARM V5 breakpoint instruction (argument parse)
9256 BKPT <16 bit unsigned immediate>
9257 Instruction is not conditional.
9258 The bit pattern given in insns[] has the COND_ALWAYS condition,
9259 and it is an error if the caller tried to override that. */
9264 /* Top 12 of 16 bits to bits 19:8. */
9265 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9267 /* Bottom 4 of 16 bits to bits 3:0. */
9268 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9272 encode_branch (int default_reloc
)
9274 if (inst
.operands
[0].hasreloc
)
9276 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9277 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9278 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9279 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9280 ? BFD_RELOC_ARM_PLT32
9281 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9284 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9285 inst
.relocs
[0].pc_rel
= 1;
9292 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9293 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9296 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9303 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9305 if (inst
.cond
== COND_ALWAYS
)
9306 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9308 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9312 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9315 /* ARM V5 branch-link-exchange instruction (argument parse)
9316 BLX <target_addr> ie BLX(1)
9317 BLX{<condition>} <Rm> ie BLX(2)
9318 Unfortunately, there are two different opcodes for this mnemonic.
9319 So, the insns[].value is not used, and the code here zaps values
9320 into inst.instruction.
9321 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9326 if (inst
.operands
[0].isreg
)
9328 /* Arg is a register; the opcode provided by insns[] is correct.
9329 It is not illegal to do "blx pc", just useless. */
9330 if (inst
.operands
[0].reg
== REG_PC
)
9331 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9333 inst
.instruction
|= inst
.operands
[0].reg
;
9337 /* Arg is an address; this instruction cannot be executed
9338 conditionally, and the opcode must be adjusted.
9339 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9340 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9341 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9342 inst
.instruction
= 0xfa000000;
9343 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9350 bfd_boolean want_reloc
;
9352 if (inst
.operands
[0].reg
== REG_PC
)
9353 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9355 inst
.instruction
|= inst
.operands
[0].reg
;
9356 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9357 it is for ARMv4t or earlier. */
9358 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9359 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9360 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9364 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9369 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9373 /* ARM v5TEJ. Jump to Jazelle code. */
9378 if (inst
.operands
[0].reg
== REG_PC
)
9379 as_tsktsk (_("use of r15 in bxj is not really useful"));
9381 inst
.instruction
|= inst
.operands
[0].reg
;
9384 /* Co-processor data operation:
9385 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9386 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9390 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9391 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9392 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9393 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9394 inst
.instruction
|= inst
.operands
[4].reg
;
9395 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9401 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9402 encode_arm_shifter_operand (1);
9405 /* Transfer between coprocessor and ARM registers.
9406 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9411 No special properties. */
9413 struct deprecated_coproc_regs_s
9420 arm_feature_set deprecated
;
9421 arm_feature_set obsoleted
;
9422 const char *dep_msg
;
9423 const char *obs_msg
;
9426 #define DEPR_ACCESS_V8 \
9427 N_("This coprocessor register access is deprecated in ARMv8")
9429 /* Table of all deprecated coprocessor registers. */
9430 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9432 {15, 0, 7, 10, 5, /* CP15DMB. */
9433 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9434 DEPR_ACCESS_V8
, NULL
},
9435 {15, 0, 7, 10, 4, /* CP15DSB. */
9436 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9437 DEPR_ACCESS_V8
, NULL
},
9438 {15, 0, 7, 5, 4, /* CP15ISB. */
9439 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9440 DEPR_ACCESS_V8
, NULL
},
9441 {14, 6, 1, 0, 0, /* TEEHBR. */
9442 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9443 DEPR_ACCESS_V8
, NULL
},
9444 {14, 6, 0, 0, 0, /* TEECR. */
9445 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9446 DEPR_ACCESS_V8
, NULL
},
9449 #undef DEPR_ACCESS_V8
9451 static const size_t deprecated_coproc_reg_count
=
9452 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9460 Rd
= inst
.operands
[2].reg
;
9463 if (inst
.instruction
== 0xee000010
9464 || inst
.instruction
== 0xfe000010)
9466 reject_bad_reg (Rd
);
9467 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9469 constraint (Rd
== REG_SP
, BAD_SP
);
9474 if (inst
.instruction
== 0xe000010)
9475 constraint (Rd
== REG_PC
, BAD_PC
);
9478 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9480 const struct deprecated_coproc_regs_s
*r
=
9481 deprecated_coproc_regs
+ i
;
9483 if (inst
.operands
[0].reg
== r
->cp
9484 && inst
.operands
[1].imm
== r
->opc1
9485 && inst
.operands
[3].reg
== r
->crn
9486 && inst
.operands
[4].reg
== r
->crm
9487 && inst
.operands
[5].imm
== r
->opc2
)
9489 if (! ARM_CPU_IS_ANY (cpu_variant
)
9490 && warn_on_deprecated
9491 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9492 as_tsktsk ("%s", r
->dep_msg
);
9496 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9497 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9498 inst
.instruction
|= Rd
<< 12;
9499 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9500 inst
.instruction
|= inst
.operands
[4].reg
;
9501 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9504 /* Transfer between coprocessor register and pair of ARM registers.
9505 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9510 Two XScale instructions are special cases of these:
9512 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9513 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9515 Result unpredictable if Rd or Rn is R15. */
9522 Rd
= inst
.operands
[2].reg
;
9523 Rn
= inst
.operands
[3].reg
;
9527 reject_bad_reg (Rd
);
9528 reject_bad_reg (Rn
);
9532 constraint (Rd
== REG_PC
, BAD_PC
);
9533 constraint (Rn
== REG_PC
, BAD_PC
);
9536 /* Only check the MRRC{2} variants. */
9537 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9539 /* If Rd == Rn, error that the operation is
9540 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9541 constraint (Rd
== Rn
, BAD_OVERLAP
);
9544 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9545 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9546 inst
.instruction
|= Rd
<< 12;
9547 inst
.instruction
|= Rn
<< 16;
9548 inst
.instruction
|= inst
.operands
[4].reg
;
9554 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9555 if (inst
.operands
[1].present
)
9557 inst
.instruction
|= CPSI_MMOD
;
9558 inst
.instruction
|= inst
.operands
[1].imm
;
9565 inst
.instruction
|= inst
.operands
[0].imm
;
9571 unsigned Rd
, Rn
, Rm
;
9573 Rd
= inst
.operands
[0].reg
;
9574 Rn
= (inst
.operands
[1].present
9575 ? inst
.operands
[1].reg
: Rd
);
9576 Rm
= inst
.operands
[2].reg
;
9578 constraint ((Rd
== REG_PC
), BAD_PC
);
9579 constraint ((Rn
== REG_PC
), BAD_PC
);
9580 constraint ((Rm
== REG_PC
), BAD_PC
);
9582 inst
.instruction
|= Rd
<< 16;
9583 inst
.instruction
|= Rn
<< 0;
9584 inst
.instruction
|= Rm
<< 8;
9590 /* There is no IT instruction in ARM mode. We
9591 process it to do the validation as if in
9592 thumb mode, just in case the code gets
9593 assembled for thumb using the unified syntax. */
9598 set_pred_insn_type (IT_INSN
);
9599 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9600 now_pred
.cc
= inst
.operands
[0].imm
;
9604 /* If there is only one register in the register list,
9605 then return its register number. Otherwise return -1. */
9607 only_one_reg_in_list (int range
)
9609 int i
= ffs (range
) - 1;
9610 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9614 encode_ldmstm(int from_push_pop_mnem
)
9616 int base_reg
= inst
.operands
[0].reg
;
9617 int range
= inst
.operands
[1].imm
;
9620 inst
.instruction
|= base_reg
<< 16;
9621 inst
.instruction
|= range
;
9623 if (inst
.operands
[1].writeback
)
9624 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9626 if (inst
.operands
[0].writeback
)
9628 inst
.instruction
|= WRITE_BACK
;
9629 /* Check for unpredictable uses of writeback. */
9630 if (inst
.instruction
& LOAD_BIT
)
9632 /* Not allowed in LDM type 2. */
9633 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9634 && ((range
& (1 << REG_PC
)) == 0))
9635 as_warn (_("writeback of base register is UNPREDICTABLE"));
9636 /* Only allowed if base reg not in list for other types. */
9637 else if (range
& (1 << base_reg
))
9638 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9642 /* Not allowed for type 2. */
9643 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9644 as_warn (_("writeback of base register is UNPREDICTABLE"));
9645 /* Only allowed if base reg not in list, or first in list. */
9646 else if ((range
& (1 << base_reg
))
9647 && (range
& ((1 << base_reg
) - 1)))
9648 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9652 /* If PUSH/POP has only one register, then use the A2 encoding. */
9653 one_reg
= only_one_reg_in_list (range
);
9654 if (from_push_pop_mnem
&& one_reg
>= 0)
9656 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9658 if (is_push
&& one_reg
== 13 /* SP */)
9659 /* PR 22483: The A2 encoding cannot be used when
9660 pushing the stack pointer as this is UNPREDICTABLE. */
9663 inst
.instruction
&= A_COND_MASK
;
9664 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9665 inst
.instruction
|= one_reg
<< 12;
9672 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9675 /* ARMv5TE load-consecutive (argument parse)
9684 constraint (inst
.operands
[0].reg
% 2 != 0,
9685 _("first transfer register must be even"));
9686 constraint (inst
.operands
[1].present
9687 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9688 _("can only transfer two consecutive registers"));
9689 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9690 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9692 if (!inst
.operands
[1].present
)
9693 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9695 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9696 register and the first register written; we have to diagnose
9697 overlap between the base and the second register written here. */
9699 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9700 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9701 as_warn (_("base register written back, and overlaps "
9702 "second transfer register"));
9704 if (!(inst
.instruction
& V4_STR_BIT
))
9706 /* For an index-register load, the index register must not overlap the
9707 destination (even if not write-back). */
9708 if (inst
.operands
[2].immisreg
9709 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9710 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9711 as_warn (_("index register overlaps transfer register"));
9713 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9714 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9720 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9721 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9722 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9723 || inst
.operands
[1].negative
9724 /* This can arise if the programmer has written
9726 or if they have mistakenly used a register name as the last
9729 It is very difficult to distinguish between these two cases
9730 because "rX" might actually be a label. ie the register
9731 name has been occluded by a symbol of the same name. So we
9732 just generate a general 'bad addressing mode' type error
9733 message and leave it up to the programmer to discover the
9734 true cause and fix their mistake. */
9735 || (inst
.operands
[1].reg
== REG_PC
),
9738 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9739 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9740 _("offset must be zero in ARM encoding"));
9742 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9745 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9746 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9752 constraint (inst
.operands
[0].reg
% 2 != 0,
9753 _("even register required"));
9754 constraint (inst
.operands
[1].present
9755 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9756 _("can only load two consecutive registers"));
9757 /* If op 1 were present and equal to PC, this function wouldn't
9758 have been called in the first place. */
9759 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9762 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9765 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9766 which is not a multiple of four is UNPREDICTABLE. */
9768 check_ldr_r15_aligned (void)
9770 constraint (!(inst
.operands
[1].immisreg
)
9771 && (inst
.operands
[0].reg
== REG_PC
9772 && inst
.operands
[1].reg
== REG_PC
9773 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9774 _("ldr to register 15 must be 4-byte aligned"));
9780 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9781 if (!inst
.operands
[1].isreg
)
9782 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9784 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9785 check_ldr_r15_aligned ();
9791 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9793 if (inst
.operands
[1].preind
)
9795 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9796 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9797 _("this instruction requires a post-indexed address"));
9799 inst
.operands
[1].preind
= 0;
9800 inst
.operands
[1].postind
= 1;
9801 inst
.operands
[1].writeback
= 1;
9803 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9804 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9807 /* Halfword and signed-byte load/store operations. */
9812 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9813 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9814 if (!inst
.operands
[1].isreg
)
9815 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9817 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9823 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9825 if (inst
.operands
[1].preind
)
9827 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9828 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9829 _("this instruction requires a post-indexed address"));
9831 inst
.operands
[1].preind
= 0;
9832 inst
.operands
[1].postind
= 1;
9833 inst
.operands
[1].writeback
= 1;
9835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9836 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9839 /* Co-processor register load/store.
9840 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9845 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9846 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9852 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9853 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9854 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9855 && !(inst
.instruction
& 0x00400000))
9856 as_tsktsk (_("Rd and Rm should be different in mla"));
9858 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9859 inst
.instruction
|= inst
.operands
[1].reg
;
9860 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9861 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9867 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9868 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9871 encode_arm_shifter_operand (1);
9874 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9881 top
= (inst
.instruction
& 0x00400000) != 0;
9882 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9883 _(":lower16: not allowed in this instruction"));
9884 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9885 _(":upper16: not allowed in this instruction"));
9886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9887 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9889 imm
= inst
.relocs
[0].exp
.X_add_number
;
9890 /* The value is in two pieces: 0:11, 16:19. */
9891 inst
.instruction
|= (imm
& 0x00000fff);
9892 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9897 do_vfp_nsyn_mrs (void)
9899 if (inst
.operands
[0].isvec
)
9901 if (inst
.operands
[1].reg
!= 1)
9902 first_error (_("operand 1 must be FPSCR"));
9903 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9904 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9905 do_vfp_nsyn_opcode ("fmstat");
9907 else if (inst
.operands
[1].isvec
)
9908 do_vfp_nsyn_opcode ("fmrx");
9916 do_vfp_nsyn_msr (void)
9918 if (inst
.operands
[0].isvec
)
9919 do_vfp_nsyn_opcode ("fmxr");
9929 unsigned Rt
= inst
.operands
[0].reg
;
9931 if (thumb_mode
&& Rt
== REG_SP
)
9933 inst
.error
= BAD_SP
;
9937 switch (inst
.operands
[1].reg
)
9939 /* MVFR2 is only valid for Armv8-A. */
9941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9945 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9946 case 1: /* fpscr. */
9947 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9948 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9952 case 14: /* fpcxt_ns. */
9953 case 15: /* fpcxt_s. */
9954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9955 _("selected processor does not support instruction"));
9958 case 2: /* fpscr_nzcvqc. */
9961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9962 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9963 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9964 _("selected processor does not support instruction"));
9965 if (inst
.operands
[0].reg
!= 2
9966 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9967 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9974 /* APSR_ sets isvec. All other refs to PC are illegal. */
9975 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9977 inst
.error
= BAD_PC
;
9981 /* If we get through parsing the register name, we just insert the number
9982 generated into the instruction without further validation. */
9983 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9984 inst
.instruction
|= (Rt
<< 12);
9990 unsigned Rt
= inst
.operands
[1].reg
;
9993 reject_bad_reg (Rt
);
9994 else if (Rt
== REG_PC
)
9996 inst
.error
= BAD_PC
;
10000 switch (inst
.operands
[0].reg
)
10002 /* MVFR2 is only valid for Armv8-A. */
10004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10008 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10009 case 1: /* fpcr. */
10010 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10011 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10015 case 14: /* fpcxt_ns. */
10016 case 15: /* fpcxt_s. */
10017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10018 _("selected processor does not support instruction"));
10021 case 2: /* fpscr_nzcvqc. */
10022 case 12: /* vpr. */
10024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10025 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10026 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10027 _("selected processor does not support instruction"));
10028 if (inst
.operands
[0].reg
!= 2
10029 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10030 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10037 /* If we get through parsing the register name, we just insert the number
10038 generated into the instruction without further validation. */
10039 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10040 inst
.instruction
|= (Rt
<< 12);
10048 if (do_vfp_nsyn_mrs () == SUCCESS
)
10051 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 if (inst
.operands
[1].isreg
)
10056 br
= inst
.operands
[1].reg
;
10057 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10058 as_bad (_("bad register for mrs"));
10062 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10063 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10065 _("'APSR', 'CPSR' or 'SPSR' expected"));
10066 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10069 inst
.instruction
|= br
;
10072 /* Two possible forms:
10073 "{C|S}PSR_<field>, Rm",
10074 "{C|S}PSR_f, #expression". */
10079 if (do_vfp_nsyn_msr () == SUCCESS
)
10082 inst
.instruction
|= inst
.operands
[0].imm
;
10083 if (inst
.operands
[1].isreg
)
10084 inst
.instruction
|= inst
.operands
[1].reg
;
10087 inst
.instruction
|= INST_IMMEDIATE
;
10088 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10089 inst
.relocs
[0].pc_rel
= 0;
10096 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10098 if (!inst
.operands
[2].present
)
10099 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10101 inst
.instruction
|= inst
.operands
[1].reg
;
10102 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10104 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10105 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10106 as_tsktsk (_("Rd and Rm should be different in mul"));
10109 /* Long Multiply Parser
10110 UMULL RdLo, RdHi, Rm, Rs
10111 SMULL RdLo, RdHi, Rm, Rs
10112 UMLAL RdLo, RdHi, Rm, Rs
10113 SMLAL RdLo, RdHi, Rm, Rs. */
10118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10120 inst
.instruction
|= inst
.operands
[2].reg
;
10121 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10123 /* rdhi and rdlo must be different. */
10124 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10125 as_tsktsk (_("rdhi and rdlo must be different"));
10127 /* rdhi, rdlo and rm must all be different before armv6. */
10128 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10129 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10130 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10131 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10137 if (inst
.operands
[0].present
10138 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10140 /* Architectural NOP hints are CPSR sets with no bits selected. */
10141 inst
.instruction
&= 0xf0000000;
10142 inst
.instruction
|= 0x0320f000;
10143 if (inst
.operands
[0].present
)
10144 inst
.instruction
|= inst
.operands
[0].imm
;
10148 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10149 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10150 Condition defaults to COND_ALWAYS.
10151 Error if Rd, Rn or Rm are R15. */
10156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10157 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10158 inst
.instruction
|= inst
.operands
[2].reg
;
10159 if (inst
.operands
[3].present
)
10160 encode_arm_shift (3);
10163 /* ARM V6 PKHTB (Argument Parse). */
10168 if (!inst
.operands
[3].present
)
10170 /* If the shift specifier is omitted, turn the instruction
10171 into pkhbt rd, rm, rn. */
10172 inst
.instruction
&= 0xfff00010;
10173 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10174 inst
.instruction
|= inst
.operands
[1].reg
;
10175 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10181 inst
.instruction
|= inst
.operands
[2].reg
;
10182 encode_arm_shift (3);
10186 /* ARMv5TE: Preload-Cache
10187 MP Extensions: Preload for write
10191 Syntactically, like LDR with B=1, W=0, L=1. */
10196 constraint (!inst
.operands
[0].isreg
,
10197 _("'[' expected after PLD mnemonic"));
10198 constraint (inst
.operands
[0].postind
,
10199 _("post-indexed expression used in preload instruction"));
10200 constraint (inst
.operands
[0].writeback
,
10201 _("writeback used in preload instruction"));
10202 constraint (!inst
.operands
[0].preind
,
10203 _("unindexed addressing used in preload instruction"));
10204 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10207 /* ARMv7: PLI <addr_mode> */
10211 constraint (!inst
.operands
[0].isreg
,
10212 _("'[' expected after PLI mnemonic"));
10213 constraint (inst
.operands
[0].postind
,
10214 _("post-indexed expression used in preload instruction"));
10215 constraint (inst
.operands
[0].writeback
,
10216 _("writeback used in preload instruction"));
10217 constraint (!inst
.operands
[0].preind
,
10218 _("unindexed addressing used in preload instruction"));
10219 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10220 inst
.instruction
&= ~PRE_INDEX
;
10226 constraint (inst
.operands
[0].writeback
,
10227 _("push/pop do not support {reglist}^"));
10228 inst
.operands
[1] = inst
.operands
[0];
10229 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10230 inst
.operands
[0].isreg
= 1;
10231 inst
.operands
[0].writeback
= 1;
10232 inst
.operands
[0].reg
= REG_SP
;
10233 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10236 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10237 word at the specified address and the following word
10239 Unconditionally executed.
10240 Error if Rn is R15. */
10245 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10246 if (inst
.operands
[0].writeback
)
10247 inst
.instruction
|= WRITE_BACK
;
10250 /* ARM V6 ssat (argument parse). */
10255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10256 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10257 inst
.instruction
|= inst
.operands
[2].reg
;
10259 if (inst
.operands
[3].present
)
10260 encode_arm_shift (3);
10263 /* ARM V6 usat (argument parse). */
10268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10270 inst
.instruction
|= inst
.operands
[2].reg
;
10272 if (inst
.operands
[3].present
)
10273 encode_arm_shift (3);
10276 /* ARM V6 ssat16 (argument parse). */
10281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10282 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10283 inst
.instruction
|= inst
.operands
[2].reg
;
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10290 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10291 inst
.instruction
|= inst
.operands
[2].reg
;
10294 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10295 preserving the other bits.
10297 setend <endian_specifier>, where <endian_specifier> is either
10303 if (warn_on_deprecated
10304 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10305 as_tsktsk (_("setend use is deprecated for ARMv8"));
10307 if (inst
.operands
[0].imm
)
10308 inst
.instruction
|= 0x200;
10314 unsigned int Rm
= (inst
.operands
[1].present
10315 ? inst
.operands
[1].reg
10316 : inst
.operands
[0].reg
);
10318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10319 inst
.instruction
|= Rm
;
10320 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10322 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10323 inst
.instruction
|= SHIFT_BY_REG
;
10324 /* PR 12854: Error on extraneous shifts. */
10325 constraint (inst
.operands
[2].shifted
,
10326 _("extraneous shift as part of operand to shift insn"));
10329 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10335 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10336 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10338 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10339 inst
.relocs
[0].pc_rel
= 0;
10345 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10346 inst
.relocs
[0].pc_rel
= 0;
10352 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10353 inst
.relocs
[0].pc_rel
= 0;
10359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10360 _("selected processor does not support SETPAN instruction"));
10362 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10369 _("selected processor does not support SETPAN instruction"));
10371 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10374 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10375 SMLAxy{cond} Rd,Rm,Rs,Rn
10376 SMLAWy{cond} Rd,Rm,Rs,Rn
10377 Error if any register is R15. */
10382 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10383 inst
.instruction
|= inst
.operands
[1].reg
;
10384 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10385 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10388 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10389 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10390 Error if any register is R15.
10391 Warning if Rdlo == Rdhi. */
10396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10397 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10398 inst
.instruction
|= inst
.operands
[2].reg
;
10399 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10401 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10402 as_tsktsk (_("rdhi and rdlo must be different"));
10405 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10406 SMULxy{cond} Rd,Rm,Rs
10407 Error if any register is R15. */
10412 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10413 inst
.instruction
|= inst
.operands
[1].reg
;
10414 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10417 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10418 the same for both ARM and Thumb-2. */
10425 if (inst
.operands
[0].present
)
10427 reg
= inst
.operands
[0].reg
;
10428 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10433 inst
.instruction
|= reg
<< 16;
10434 inst
.instruction
|= inst
.operands
[1].imm
;
10435 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10436 inst
.instruction
|= WRITE_BACK
;
10439 /* ARM V6 strex (argument parse). */
10444 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10445 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10446 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10447 || inst
.operands
[2].negative
10448 /* See comment in do_ldrex(). */
10449 || (inst
.operands
[2].reg
== REG_PC
),
10452 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10453 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10455 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10456 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10457 _("offset must be zero in ARM encoding"));
10459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10460 inst
.instruction
|= inst
.operands
[1].reg
;
10461 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10462 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10466 do_t_strexbh (void)
10468 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10469 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10470 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10471 || inst
.operands
[2].negative
,
10474 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10475 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10483 constraint (inst
.operands
[1].reg
% 2 != 0,
10484 _("even register required"));
10485 constraint (inst
.operands
[2].present
10486 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10487 _("can only store two consecutive registers"));
10488 /* If op 2 were present and equal to PC, this function wouldn't
10489 have been called in the first place. */
10490 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10492 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10493 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10494 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10498 inst
.instruction
|= inst
.operands
[1].reg
;
10499 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10506 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10507 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10515 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10516 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10521 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10522 extends it to 32-bits, and adds the result to a value in another
10523 register. You can specify a rotation by 0, 8, 16, or 24 bits
10524 before extracting the 16-bit value.
10525 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10526 Condition defaults to COND_ALWAYS.
10527 Error if any register uses R15. */
10532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10533 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10534 inst
.instruction
|= inst
.operands
[2].reg
;
10535 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10540 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10541 Condition defaults to COND_ALWAYS.
10542 Error if any register uses R15. */
10547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10548 inst
.instruction
|= inst
.operands
[1].reg
;
10549 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10552 /* VFP instructions. In a logical order: SP variant first, monad
10553 before dyad, arithmetic then move then load/store. */
10556 do_vfp_sp_monadic (void)
10558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10559 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10563 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10567 do_vfp_sp_dyadic (void)
10569 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10570 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10571 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10575 do_vfp_sp_compare_z (void)
10577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10581 do_vfp_dp_sp_cvt (void)
10583 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10584 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10588 do_vfp_sp_dp_cvt (void)
10590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10595 do_vfp_reg_from_sp (void)
10597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10598 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10602 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10606 do_vfp_reg2_from_sp2 (void)
10608 constraint (inst
.operands
[2].imm
!= 2,
10609 _("only two consecutive VFP SP registers allowed here"));
10610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10611 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10612 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10616 do_vfp_sp_from_reg (void)
10618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10619 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10627 do_vfp_sp2_from_reg2 (void)
10629 constraint (inst
.operands
[0].imm
!= 2,
10630 _("only two consecutive VFP SP registers allowed here"));
10631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10632 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10633 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10637 do_vfp_sp_ldst (void)
10639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10640 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10644 do_vfp_dp_ldst (void)
10646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10647 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10652 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10654 if (inst
.operands
[0].writeback
)
10655 inst
.instruction
|= WRITE_BACK
;
10657 constraint (ldstm_type
!= VFP_LDSTMIA
,
10658 _("this addressing mode requires base-register writeback"));
10659 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10660 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10661 inst
.instruction
|= inst
.operands
[1].imm
;
10665 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10669 if (inst
.operands
[0].writeback
)
10670 inst
.instruction
|= WRITE_BACK
;
10672 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10673 _("this addressing mode requires base-register writeback"));
10675 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10676 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10678 count
= inst
.operands
[1].imm
<< 1;
10679 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10682 inst
.instruction
|= count
;
10686 do_vfp_sp_ldstmia (void)
10688 vfp_sp_ldstm (VFP_LDSTMIA
);
10692 do_vfp_sp_ldstmdb (void)
10694 vfp_sp_ldstm (VFP_LDSTMDB
);
10698 do_vfp_dp_ldstmia (void)
10700 vfp_dp_ldstm (VFP_LDSTMIA
);
10704 do_vfp_dp_ldstmdb (void)
10706 vfp_dp_ldstm (VFP_LDSTMDB
);
10710 do_vfp_xp_ldstmia (void)
10712 vfp_dp_ldstm (VFP_LDSTMIAX
);
10716 do_vfp_xp_ldstmdb (void)
10718 vfp_dp_ldstm (VFP_LDSTMDBX
);
10722 do_vfp_dp_rd_rm (void)
10724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10725 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10729 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10733 do_vfp_dp_rn_rd (void)
10735 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10736 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10740 do_vfp_dp_rd_rn (void)
10742 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10743 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10747 do_vfp_dp_rd_rn_rm (void)
10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10754 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10755 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10759 do_vfp_dp_rd (void)
10761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10765 do_vfp_dp_rm_rd_rn (void)
10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10768 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10772 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10773 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10776 /* VFPv3 instructions. */
10778 do_vfp_sp_const (void)
10780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10781 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10782 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10786 do_vfp_dp_const (void)
10788 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10789 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10790 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10794 vfp_conv (int srcsize
)
10796 int immbits
= srcsize
- inst
.operands
[1].imm
;
10798 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10800 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10801 i.e. immbits must be in range 0 - 16. */
10802 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10805 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10807 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10808 i.e. immbits must be in range 0 - 31. */
10809 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10813 inst
.instruction
|= (immbits
& 1) << 5;
10814 inst
.instruction
|= (immbits
>> 1);
10818 do_vfp_sp_conv_16 (void)
10820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10825 do_vfp_dp_conv_16 (void)
10827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10832 do_vfp_sp_conv_32 (void)
10834 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10839 do_vfp_dp_conv_32 (void)
10841 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10845 /* FPA instructions. Also in a logical order. */
10850 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10851 inst
.instruction
|= inst
.operands
[1].reg
;
10855 do_fpa_ldmstm (void)
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10858 switch (inst
.operands
[1].imm
)
10860 case 1: inst
.instruction
|= CP_T_X
; break;
10861 case 2: inst
.instruction
|= CP_T_Y
; break;
10862 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10867 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10869 /* The instruction specified "ea" or "fd", so we can only accept
10870 [Rn]{!}. The instruction does not really support stacking or
10871 unstacking, so we have to emulate these by setting appropriate
10872 bits and offsets. */
10873 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10874 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10875 _("this instruction does not support indexing"));
10877 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10878 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10880 if (!(inst
.instruction
& INDEX_UP
))
10881 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10883 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10885 inst
.operands
[2].preind
= 0;
10886 inst
.operands
[2].postind
= 1;
10890 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10893 /* iWMMXt instructions: strictly in alphabetical order. */
10896 do_iwmmxt_tandorc (void)
10898 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10902 do_iwmmxt_textrc (void)
10904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10905 inst
.instruction
|= inst
.operands
[1].imm
;
10909 do_iwmmxt_textrm (void)
10911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10913 inst
.instruction
|= inst
.operands
[2].imm
;
10917 do_iwmmxt_tinsr (void)
10919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10920 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10921 inst
.instruction
|= inst
.operands
[2].imm
;
10925 do_iwmmxt_tmia (void)
10927 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10928 inst
.instruction
|= inst
.operands
[1].reg
;
10929 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10933 do_iwmmxt_waligni (void)
10935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10937 inst
.instruction
|= inst
.operands
[2].reg
;
10938 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10942 do_iwmmxt_wmerge (void)
10944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10945 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10946 inst
.instruction
|= inst
.operands
[2].reg
;
10947 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10951 do_iwmmxt_wmov (void)
10953 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10956 inst
.instruction
|= inst
.operands
[1].reg
;
10960 do_iwmmxt_wldstbh (void)
10963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10965 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10967 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10968 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10972 do_iwmmxt_wldstw (void)
10974 /* RIWR_RIWC clears .isreg for a control register. */
10975 if (!inst
.operands
[0].isreg
)
10977 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10978 inst
.instruction
|= 0xf0000000;
10981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10982 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10986 do_iwmmxt_wldstd (void)
10988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10990 && inst
.operands
[1].immisreg
)
10992 inst
.instruction
&= ~0x1a000ff;
10993 inst
.instruction
|= (0xfU
<< 28);
10994 if (inst
.operands
[1].preind
)
10995 inst
.instruction
|= PRE_INDEX
;
10996 if (!inst
.operands
[1].negative
)
10997 inst
.instruction
|= INDEX_UP
;
10998 if (inst
.operands
[1].writeback
)
10999 inst
.instruction
|= WRITE_BACK
;
11000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11001 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11002 inst
.instruction
|= inst
.operands
[1].imm
;
11005 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11009 do_iwmmxt_wshufh (void)
11011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11013 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11014 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11018 do_iwmmxt_wzero (void)
11020 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11021 inst
.instruction
|= inst
.operands
[0].reg
;
11022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11027 do_iwmmxt_wrwrwr_or_imm5 (void)
11029 if (inst
.operands
[2].isreg
)
11032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11033 _("immediate operand requires iWMMXt2"));
11035 if (inst
.operands
[2].imm
== 0)
11037 switch ((inst
.instruction
>> 20) & 0xf)
11043 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11044 inst
.operands
[2].imm
= 16;
11045 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11051 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11052 inst
.operands
[2].imm
= 32;
11053 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11060 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11062 wrn
= (inst
.instruction
>> 16) & 0xf;
11063 inst
.instruction
&= 0xff0fff0f;
11064 inst
.instruction
|= wrn
;
11065 /* Bail out here; the instruction is now assembled. */
11070 /* Map 32 -> 0, etc. */
11071 inst
.operands
[2].imm
&= 0x1f;
11072 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11076 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11077 operations first, then control, shift, and load/store. */
11079 /* Insns like "foo X,Y,Z". */
11082 do_mav_triple (void)
11084 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11085 inst
.instruction
|= inst
.operands
[1].reg
;
11086 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11089 /* Insns like "foo W,X,Y,Z".
11090 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11095 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11097 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11098 inst
.instruction
|= inst
.operands
[3].reg
;
11101 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11103 do_mav_dspsc (void)
11105 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11108 /* Maverick shift immediate instructions.
11109 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11110 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11113 do_mav_shift (void)
11115 int imm
= inst
.operands
[2].imm
;
11117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11120 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11121 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11122 Bit 4 should be 0. */
11123 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11125 inst
.instruction
|= imm
;
11128 /* XScale instructions. Also sorted arithmetic before move. */
11130 /* Xscale multiply-accumulate (argument parse)
11133 MIAxycc acc0,Rm,Rs. */
11138 inst
.instruction
|= inst
.operands
[1].reg
;
11139 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11142 /* Xscale move-accumulator-register (argument parse)
11144 MARcc acc0,RdLo,RdHi. */
11149 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11150 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11153 /* Xscale move-register-accumulator (argument parse)
11155 MRAcc RdLo,RdHi,acc0. */
11160 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11165 /* Encoding functions relevant only to Thumb. */
11167 /* inst.operands[i] is a shifted-register operand; encode
11168 it into inst.instruction in the format used by Thumb32. */
11171 encode_thumb32_shifted_operand (int i
)
11173 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11174 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11176 constraint (inst
.operands
[i
].immisreg
,
11177 _("shift by register not allowed in thumb mode"));
11178 inst
.instruction
|= inst
.operands
[i
].reg
;
11179 if (shift
== SHIFT_RRX
)
11180 inst
.instruction
|= SHIFT_ROR
<< 4;
11183 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11184 _("expression too complex"));
11186 constraint (value
> 32
11187 || (value
== 32 && (shift
== SHIFT_LSL
11188 || shift
== SHIFT_ROR
)),
11189 _("shift expression is too large"));
11193 else if (value
== 32)
11196 inst
.instruction
|= shift
<< 4;
11197 inst
.instruction
|= (value
& 0x1c) << 10;
11198 inst
.instruction
|= (value
& 0x03) << 6;
11203 /* inst.operands[i] was set up by parse_address. Encode it into a
11204 Thumb32 format load or store instruction. Reject forms that cannot
11205 be used with such instructions. If is_t is true, reject forms that
11206 cannot be used with a T instruction; if is_d is true, reject forms
11207 that cannot be used with a D instruction. If it is a store insn,
11208 reject PC in Rn. */
11211 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11213 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11215 constraint (!inst
.operands
[i
].isreg
,
11216 _("Instruction does not support =N addresses"));
11218 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11219 if (inst
.operands
[i
].immisreg
)
11221 constraint (is_pc
, BAD_PC_ADDRESSING
);
11222 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11223 constraint (inst
.operands
[i
].negative
,
11224 _("Thumb does not support negative register indexing"));
11225 constraint (inst
.operands
[i
].postind
,
11226 _("Thumb does not support register post-indexing"));
11227 constraint (inst
.operands
[i
].writeback
,
11228 _("Thumb does not support register indexing with writeback"));
11229 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11230 _("Thumb supports only LSL in shifted register indexing"));
11232 inst
.instruction
|= inst
.operands
[i
].imm
;
11233 if (inst
.operands
[i
].shifted
)
11235 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11236 _("expression too complex"));
11237 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11238 || inst
.relocs
[0].exp
.X_add_number
> 3,
11239 _("shift out of range"));
11240 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11242 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11244 else if (inst
.operands
[i
].preind
)
11246 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11247 constraint (is_t
&& inst
.operands
[i
].writeback
,
11248 _("cannot use writeback with this instruction"));
11249 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11250 BAD_PC_ADDRESSING
);
11254 inst
.instruction
|= 0x01000000;
11255 if (inst
.operands
[i
].writeback
)
11256 inst
.instruction
|= 0x00200000;
11260 inst
.instruction
|= 0x00000c00;
11261 if (inst
.operands
[i
].writeback
)
11262 inst
.instruction
|= 0x00000100;
11264 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11266 else if (inst
.operands
[i
].postind
)
11268 gas_assert (inst
.operands
[i
].writeback
);
11269 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11270 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11273 inst
.instruction
|= 0x00200000;
11275 inst
.instruction
|= 0x00000900;
11276 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11278 else /* unindexed - only for coprocessor */
11279 inst
.error
= _("instruction does not accept unindexed addressing");
11282 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11283 encodings (the latter only in post-V6T2 cores). The index is the
11284 value used in the insns table below. When there is more than one
11285 possible 16-bit encoding for the instruction, this table always
11287 Also contains several pseudo-instructions used during relaxation. */
11288 #define T16_32_TAB \
11289 X(_adc, 4140, eb400000), \
11290 X(_adcs, 4140, eb500000), \
11291 X(_add, 1c00, eb000000), \
11292 X(_adds, 1c00, eb100000), \
11293 X(_addi, 0000, f1000000), \
11294 X(_addis, 0000, f1100000), \
11295 X(_add_pc,000f, f20f0000), \
11296 X(_add_sp,000d, f10d0000), \
11297 X(_adr, 000f, f20f0000), \
11298 X(_and, 4000, ea000000), \
11299 X(_ands, 4000, ea100000), \
11300 X(_asr, 1000, fa40f000), \
11301 X(_asrs, 1000, fa50f000), \
11302 X(_b, e000, f000b000), \
11303 X(_bcond, d000, f0008000), \
11304 X(_bf, 0000, f040e001), \
11305 X(_bfcsel,0000, f000e001), \
11306 X(_bfx, 0000, f060e001), \
11307 X(_bfl, 0000, f000c001), \
11308 X(_bflx, 0000, f070e001), \
11309 X(_bic, 4380, ea200000), \
11310 X(_bics, 4380, ea300000), \
11311 X(_cinc, 0000, ea509000), \
11312 X(_cinv, 0000, ea50a000), \
11313 X(_cmn, 42c0, eb100f00), \
11314 X(_cmp, 2800, ebb00f00), \
11315 X(_cneg, 0000, ea50b000), \
11316 X(_cpsie, b660, f3af8400), \
11317 X(_cpsid, b670, f3af8600), \
11318 X(_cpy, 4600, ea4f0000), \
11319 X(_csel, 0000, ea508000), \
11320 X(_cset, 0000, ea5f900f), \
11321 X(_csetm, 0000, ea5fa00f), \
11322 X(_csinc, 0000, ea509000), \
11323 X(_csinv, 0000, ea50a000), \
11324 X(_csneg, 0000, ea50b000), \
11325 X(_dec_sp,80dd, f1ad0d00), \
11326 X(_dls, 0000, f040e001), \
11327 X(_dlstp, 0000, f000e001), \
11328 X(_eor, 4040, ea800000), \
11329 X(_eors, 4040, ea900000), \
11330 X(_inc_sp,00dd, f10d0d00), \
11331 X(_lctp, 0000, f00fe001), \
11332 X(_ldmia, c800, e8900000), \
11333 X(_ldr, 6800, f8500000), \
11334 X(_ldrb, 7800, f8100000), \
11335 X(_ldrh, 8800, f8300000), \
11336 X(_ldrsb, 5600, f9100000), \
11337 X(_ldrsh, 5e00, f9300000), \
11338 X(_ldr_pc,4800, f85f0000), \
11339 X(_ldr_pc2,4800, f85f0000), \
11340 X(_ldr_sp,9800, f85d0000), \
11341 X(_le, 0000, f00fc001), \
11342 X(_letp, 0000, f01fc001), \
11343 X(_lsl, 0000, fa00f000), \
11344 X(_lsls, 0000, fa10f000), \
11345 X(_lsr, 0800, fa20f000), \
11346 X(_lsrs, 0800, fa30f000), \
11347 X(_mov, 2000, ea4f0000), \
11348 X(_movs, 2000, ea5f0000), \
11349 X(_mul, 4340, fb00f000), \
11350 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11351 X(_mvn, 43c0, ea6f0000), \
11352 X(_mvns, 43c0, ea7f0000), \
11353 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11354 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11355 X(_orr, 4300, ea400000), \
11356 X(_orrs, 4300, ea500000), \
11357 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11358 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11359 X(_rev, ba00, fa90f080), \
11360 X(_rev16, ba40, fa90f090), \
11361 X(_revsh, bac0, fa90f0b0), \
11362 X(_ror, 41c0, fa60f000), \
11363 X(_rors, 41c0, fa70f000), \
11364 X(_sbc, 4180, eb600000), \
11365 X(_sbcs, 4180, eb700000), \
11366 X(_stmia, c000, e8800000), \
11367 X(_str, 6000, f8400000), \
11368 X(_strb, 7000, f8000000), \
11369 X(_strh, 8000, f8200000), \
11370 X(_str_sp,9000, f84d0000), \
11371 X(_sub, 1e00, eba00000), \
11372 X(_subs, 1e00, ebb00000), \
11373 X(_subi, 8000, f1a00000), \
11374 X(_subis, 8000, f1b00000), \
11375 X(_sxtb, b240, fa4ff080), \
11376 X(_sxth, b200, fa0ff080), \
11377 X(_tst, 4200, ea100f00), \
11378 X(_uxtb, b2c0, fa5ff080), \
11379 X(_uxth, b280, fa1ff080), \
11380 X(_nop, bf00, f3af8000), \
11381 X(_yield, bf10, f3af8001), \
11382 X(_wfe, bf20, f3af8002), \
11383 X(_wfi, bf30, f3af8003), \
11384 X(_wls, 0000, f040c001), \
11385 X(_wlstp, 0000, f000c001), \
11386 X(_sev, bf40, f3af8004), \
11387 X(_sevl, bf50, f3af8005), \
11388 X(_udf, de00, f7f0a000)
11390 /* To catch errors in encoding functions, the codes are all offset by
11391 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11392 as 16-bit instructions. */
11393 #define X(a,b,c) T_MNEM##a
11394 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11397 #define X(a,b,c) 0x##b
11398 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11399 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11402 #define X(a,b,c) 0x##c
11403 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11404 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11405 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11409 /* Thumb instruction encoders, in alphabetical order. */
11411 /* ADDW or SUBW. */
11414 do_t_add_sub_w (void)
11418 Rd
= inst
.operands
[0].reg
;
11419 Rn
= inst
.operands
[1].reg
;
11421 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11422 is the SP-{plus,minus}-immediate form of the instruction. */
11424 constraint (Rd
== REG_PC
, BAD_PC
);
11426 reject_bad_reg (Rd
);
11428 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11429 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11432 /* Parse an add or subtract instruction. We get here with inst.instruction
11433 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11436 do_t_add_sub (void)
11440 Rd
= inst
.operands
[0].reg
;
11441 Rs
= (inst
.operands
[1].present
11442 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11443 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11446 set_pred_insn_type_last ();
11448 if (unified_syntax
)
11451 bfd_boolean narrow
;
11454 flags
= (inst
.instruction
== T_MNEM_adds
11455 || inst
.instruction
== T_MNEM_subs
);
11457 narrow
= !in_pred_block ();
11459 narrow
= in_pred_block ();
11460 if (!inst
.operands
[2].isreg
)
11464 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11465 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11467 add
= (inst
.instruction
== T_MNEM_add
11468 || inst
.instruction
== T_MNEM_adds
);
11470 if (inst
.size_req
!= 4)
11472 /* Attempt to use a narrow opcode, with relaxation if
11474 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11475 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11476 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11477 opcode
= T_MNEM_add_sp
;
11478 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11479 opcode
= T_MNEM_add_pc
;
11480 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11483 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11485 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11489 inst
.instruction
= THUMB_OP16(opcode
);
11490 inst
.instruction
|= (Rd
<< 4) | Rs
;
11491 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11492 || (inst
.relocs
[0].type
11493 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11495 if (inst
.size_req
== 2)
11496 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11498 inst
.relax
= opcode
;
11502 constraint (inst
.size_req
== 2, BAD_HIREG
);
11504 if (inst
.size_req
== 4
11505 || (inst
.size_req
!= 2 && !opcode
))
11507 constraint ((inst
.relocs
[0].type
11508 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11509 && (inst
.relocs
[0].type
11510 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11511 THUMB1_RELOC_ONLY
);
11514 constraint (add
, BAD_PC
);
11515 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11516 _("only SUBS PC, LR, #const allowed"));
11517 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11518 _("expression too complex"));
11519 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11520 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11521 _("immediate value out of range"));
11522 inst
.instruction
= T2_SUBS_PC_LR
11523 | inst
.relocs
[0].exp
.X_add_number
;
11524 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11527 else if (Rs
== REG_PC
)
11529 /* Always use addw/subw. */
11530 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11531 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11535 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11536 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11539 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11541 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11543 inst
.instruction
|= Rd
<< 8;
11544 inst
.instruction
|= Rs
<< 16;
11549 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11550 unsigned int shift
= inst
.operands
[2].shift_kind
;
11552 Rn
= inst
.operands
[2].reg
;
11553 /* See if we can do this with a 16-bit instruction. */
11554 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11556 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11561 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11562 || inst
.instruction
== T_MNEM_add
)
11564 : T_OPCODE_SUB_R3
);
11565 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11569 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11571 /* Thumb-1 cores (except v6-M) require at least one high
11572 register in a narrow non flag setting add. */
11573 if (Rd
> 7 || Rn
> 7
11574 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11575 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11582 inst
.instruction
= T_OPCODE_ADD_HI
;
11583 inst
.instruction
|= (Rd
& 8) << 4;
11584 inst
.instruction
|= (Rd
& 7);
11585 inst
.instruction
|= Rn
<< 3;
11591 constraint (Rd
== REG_PC
, BAD_PC
);
11592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11593 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11594 constraint (Rs
== REG_PC
, BAD_PC
);
11595 reject_bad_reg (Rn
);
11597 /* If we get here, it can't be done in 16 bits. */
11598 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11599 _("shift must be constant"));
11600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11601 inst
.instruction
|= Rd
<< 8;
11602 inst
.instruction
|= Rs
<< 16;
11603 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11604 _("shift value over 3 not allowed in thumb mode"));
11605 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11606 _("only LSL shift allowed in thumb mode"));
11607 encode_thumb32_shifted_operand (2);
11612 constraint (inst
.instruction
== T_MNEM_adds
11613 || inst
.instruction
== T_MNEM_subs
,
11616 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11618 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11619 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11622 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11623 ? 0x0000 : 0x8000);
11624 inst
.instruction
|= (Rd
<< 4) | Rs
;
11625 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11629 Rn
= inst
.operands
[2].reg
;
11630 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11632 /* We now have Rd, Rs, and Rn set to registers. */
11633 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11635 /* Can't do this for SUB. */
11636 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11637 inst
.instruction
= T_OPCODE_ADD_HI
;
11638 inst
.instruction
|= (Rd
& 8) << 4;
11639 inst
.instruction
|= (Rd
& 7);
11641 inst
.instruction
|= Rn
<< 3;
11643 inst
.instruction
|= Rs
<< 3;
11645 constraint (1, _("dest must overlap one source register"));
11649 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11650 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11651 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11661 Rd
= inst
.operands
[0].reg
;
11662 reject_bad_reg (Rd
);
11664 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11666 /* Defer to section relaxation. */
11667 inst
.relax
= inst
.instruction
;
11668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11669 inst
.instruction
|= Rd
<< 4;
11671 else if (unified_syntax
&& inst
.size_req
!= 2)
11673 /* Generate a 32-bit opcode. */
11674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11675 inst
.instruction
|= Rd
<< 8;
11676 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11677 inst
.relocs
[0].pc_rel
= 1;
11681 /* Generate a 16-bit opcode. */
11682 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11683 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11684 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11685 inst
.relocs
[0].pc_rel
= 1;
11686 inst
.instruction
|= Rd
<< 4;
11689 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11690 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11691 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11692 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11693 inst
.relocs
[0].exp
.X_add_number
+= 1;
11696 /* Arithmetic instructions for which there is just one 16-bit
11697 instruction encoding, and it allows only two low registers.
11698 For maximal compatibility with ARM syntax, we allow three register
11699 operands even when Thumb-32 instructions are not available, as long
11700 as the first two are identical. For instance, both "sbc r0,r1" and
11701 "sbc r0,r0,r1" are allowed. */
11707 Rd
= inst
.operands
[0].reg
;
11708 Rs
= (inst
.operands
[1].present
11709 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11710 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11711 Rn
= inst
.operands
[2].reg
;
11713 reject_bad_reg (Rd
);
11714 reject_bad_reg (Rs
);
11715 if (inst
.operands
[2].isreg
)
11716 reject_bad_reg (Rn
);
11718 if (unified_syntax
)
11720 if (!inst
.operands
[2].isreg
)
11722 /* For an immediate, we always generate a 32-bit opcode;
11723 section relaxation will shrink it later if possible. */
11724 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11725 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11726 inst
.instruction
|= Rd
<< 8;
11727 inst
.instruction
|= Rs
<< 16;
11728 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11732 bfd_boolean narrow
;
11734 /* See if we can do this with a 16-bit instruction. */
11735 if (THUMB_SETS_FLAGS (inst
.instruction
))
11736 narrow
= !in_pred_block ();
11738 narrow
= in_pred_block ();
11740 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11742 if (inst
.operands
[2].shifted
)
11744 if (inst
.size_req
== 4)
11750 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11751 inst
.instruction
|= Rd
;
11752 inst
.instruction
|= Rn
<< 3;
11756 /* If we get here, it can't be done in 16 bits. */
11757 constraint (inst
.operands
[2].shifted
11758 && inst
.operands
[2].immisreg
,
11759 _("shift must be constant"));
11760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11761 inst
.instruction
|= Rd
<< 8;
11762 inst
.instruction
|= Rs
<< 16;
11763 encode_thumb32_shifted_operand (2);
11768 /* On its face this is a lie - the instruction does set the
11769 flags. However, the only supported mnemonic in this mode
11770 says it doesn't. */
11771 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11773 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11774 _("unshifted register required"));
11775 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11776 constraint (Rd
!= Rs
,
11777 _("dest and source1 must be the same register"));
11779 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11780 inst
.instruction
|= Rd
;
11781 inst
.instruction
|= Rn
<< 3;
11785 /* Similarly, but for instructions where the arithmetic operation is
11786 commutative, so we can allow either of them to be different from
11787 the destination operand in a 16-bit instruction. For instance, all
11788 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11795 Rd
= inst
.operands
[0].reg
;
11796 Rs
= (inst
.operands
[1].present
11797 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11798 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11799 Rn
= inst
.operands
[2].reg
;
11801 reject_bad_reg (Rd
);
11802 reject_bad_reg (Rs
);
11803 if (inst
.operands
[2].isreg
)
11804 reject_bad_reg (Rn
);
11806 if (unified_syntax
)
11808 if (!inst
.operands
[2].isreg
)
11810 /* For an immediate, we always generate a 32-bit opcode;
11811 section relaxation will shrink it later if possible. */
11812 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11813 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11814 inst
.instruction
|= Rd
<< 8;
11815 inst
.instruction
|= Rs
<< 16;
11816 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11820 bfd_boolean narrow
;
11822 /* See if we can do this with a 16-bit instruction. */
11823 if (THUMB_SETS_FLAGS (inst
.instruction
))
11824 narrow
= !in_pred_block ();
11826 narrow
= in_pred_block ();
11828 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11830 if (inst
.operands
[2].shifted
)
11832 if (inst
.size_req
== 4)
11839 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11840 inst
.instruction
|= Rd
;
11841 inst
.instruction
|= Rn
<< 3;
11846 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11847 inst
.instruction
|= Rd
;
11848 inst
.instruction
|= Rs
<< 3;
11853 /* If we get here, it can't be done in 16 bits. */
11854 constraint (inst
.operands
[2].shifted
11855 && inst
.operands
[2].immisreg
,
11856 _("shift must be constant"));
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
|= Rd
<< 8;
11859 inst
.instruction
|= Rs
<< 16;
11860 encode_thumb32_shifted_operand (2);
11865 /* On its face this is a lie - the instruction does set the
11866 flags. However, the only supported mnemonic in this mode
11867 says it doesn't. */
11868 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11870 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11871 _("unshifted register required"));
11872 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11874 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11875 inst
.instruction
|= Rd
;
11878 inst
.instruction
|= Rn
<< 3;
11880 inst
.instruction
|= Rs
<< 3;
11882 constraint (1, _("dest must overlap one source register"));
11890 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11891 constraint (msb
> 32, _("bit-field extends past end of register"));
11892 /* The instruction encoding stores the LSB and MSB,
11893 not the LSB and width. */
11894 Rd
= inst
.operands
[0].reg
;
11895 reject_bad_reg (Rd
);
11896 inst
.instruction
|= Rd
<< 8;
11897 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11898 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11899 inst
.instruction
|= msb
- 1;
11908 Rd
= inst
.operands
[0].reg
;
11909 reject_bad_reg (Rd
);
11911 /* #0 in second position is alternative syntax for bfc, which is
11912 the same instruction but with REG_PC in the Rm field. */
11913 if (!inst
.operands
[1].isreg
)
11917 Rn
= inst
.operands
[1].reg
;
11918 reject_bad_reg (Rn
);
11921 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11922 constraint (msb
> 32, _("bit-field extends past end of register"));
11923 /* The instruction encoding stores the LSB and MSB,
11924 not the LSB and width. */
11925 inst
.instruction
|= Rd
<< 8;
11926 inst
.instruction
|= Rn
<< 16;
11927 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11928 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11929 inst
.instruction
|= msb
- 1;
11937 Rd
= inst
.operands
[0].reg
;
11938 Rn
= inst
.operands
[1].reg
;
11940 reject_bad_reg (Rd
);
11941 reject_bad_reg (Rn
);
11943 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11944 _("bit-field extends past end of register"));
11945 inst
.instruction
|= Rd
<< 8;
11946 inst
.instruction
|= Rn
<< 16;
11947 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11948 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11949 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11952 /* ARM V5 Thumb BLX (argument parse)
11953 BLX <target_addr> which is BLX(1)
11954 BLX <Rm> which is BLX(2)
11955 Unfortunately, there are two different opcodes for this mnemonic.
11956 So, the insns[].value is not used, and the code here zaps values
11957 into inst.instruction.
11959 ??? How to take advantage of the additional two bits of displacement
11960 available in Thumb32 mode? Need new relocation? */
11965 set_pred_insn_type_last ();
11967 if (inst
.operands
[0].isreg
)
11969 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11970 /* We have a register, so this is BLX(2). */
11971 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11975 /* No register. This must be BLX(1). */
11976 inst
.instruction
= 0xf000e800;
11977 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11986 bfd_reloc_code_real_type reloc
;
11989 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11991 if (in_pred_block ())
11993 /* Conditional branches inside IT blocks are encoded as unconditional
11995 cond
= COND_ALWAYS
;
12000 if (cond
!= COND_ALWAYS
)
12001 opcode
= T_MNEM_bcond
;
12003 opcode
= inst
.instruction
;
12006 && (inst
.size_req
== 4
12007 || (inst
.size_req
!= 2
12008 && (inst
.operands
[0].hasreloc
12009 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12011 inst
.instruction
= THUMB_OP32(opcode
);
12012 if (cond
== COND_ALWAYS
)
12013 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12017 _("selected architecture does not support "
12018 "wide conditional branch instruction"));
12020 gas_assert (cond
!= 0xF);
12021 inst
.instruction
|= cond
<< 22;
12022 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12027 inst
.instruction
= THUMB_OP16(opcode
);
12028 if (cond
== COND_ALWAYS
)
12029 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12032 inst
.instruction
|= cond
<< 8;
12033 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12035 /* Allow section relaxation. */
12036 if (unified_syntax
&& inst
.size_req
!= 2)
12037 inst
.relax
= opcode
;
12039 inst
.relocs
[0].type
= reloc
;
12040 inst
.relocs
[0].pc_rel
= 1;
12043 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12044 between the two is the maximum immediate allowed - which is passed in
12047 do_t_bkpt_hlt1 (int range
)
12049 constraint (inst
.cond
!= COND_ALWAYS
,
12050 _("instruction is always unconditional"));
12051 if (inst
.operands
[0].present
)
12053 constraint (inst
.operands
[0].imm
> range
,
12054 _("immediate value out of range"));
12055 inst
.instruction
|= inst
.operands
[0].imm
;
12058 set_pred_insn_type (NEUTRAL_IT_INSN
);
12064 do_t_bkpt_hlt1 (63);
12070 do_t_bkpt_hlt1 (255);
12074 do_t_branch23 (void)
12076 set_pred_insn_type_last ();
12077 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12079 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12080 this file. We used to simply ignore the PLT reloc type here --
12081 the branch encoding is now needed to deal with TLSCALL relocs.
12082 So if we see a PLT reloc now, put it back to how it used to be to
12083 keep the preexisting behaviour. */
12084 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12085 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12087 #if defined(OBJ_COFF)
12088 /* If the destination of the branch is a defined symbol which does not have
12089 the THUMB_FUNC attribute, then we must be calling a function which has
12090 the (interfacearm) attribute. We look for the Thumb entry point to that
12091 function and change the branch to refer to that function instead. */
12092 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12093 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12094 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12095 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12096 inst
.relocs
[0].exp
.X_add_symbol
12097 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12104 set_pred_insn_type_last ();
12105 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12106 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12107 should cause the alignment to be checked once it is known. This is
12108 because BX PC only works if the instruction is word aligned. */
12116 set_pred_insn_type_last ();
12117 Rm
= inst
.operands
[0].reg
;
12118 reject_bad_reg (Rm
);
12119 inst
.instruction
|= Rm
<< 16;
12128 Rd
= inst
.operands
[0].reg
;
12129 Rm
= inst
.operands
[1].reg
;
12131 reject_bad_reg (Rd
);
12132 reject_bad_reg (Rm
);
12134 inst
.instruction
|= Rd
<< 8;
12135 inst
.instruction
|= Rm
<< 16;
12136 inst
.instruction
|= Rm
;
12139 /* For the Armv8.1-M conditional instructions. */
12143 unsigned Rd
, Rn
, Rm
;
12146 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12148 Rd
= inst
.operands
[0].reg
;
12149 switch (inst
.instruction
)
12155 Rn
= inst
.operands
[1].reg
;
12156 Rm
= inst
.operands
[2].reg
;
12157 cond
= inst
.operands
[3].imm
;
12158 constraint (Rn
== REG_SP
, BAD_SP
);
12159 constraint (Rm
== REG_SP
, BAD_SP
);
12165 Rn
= inst
.operands
[1].reg
;
12166 cond
= inst
.operands
[2].imm
;
12167 /* Invert the last bit to invert the cond. */
12168 cond
= TOGGLE_BIT (cond
, 0);
12169 constraint (Rn
== REG_SP
, BAD_SP
);
12175 cond
= inst
.operands
[1].imm
;
12176 /* Invert the last bit to invert the cond. */
12177 cond
= TOGGLE_BIT (cond
, 0);
12185 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12186 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12187 inst
.instruction
|= Rd
<< 8;
12188 inst
.instruction
|= Rn
<< 16;
12189 inst
.instruction
|= Rm
;
12190 inst
.instruction
|= cond
<< 4;
12196 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12202 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12203 inst
.instruction
|= inst
.operands
[0].imm
;
12209 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12211 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12212 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12214 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12215 inst
.instruction
= 0xf3af8000;
12216 inst
.instruction
|= imod
<< 9;
12217 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12218 if (inst
.operands
[1].present
)
12219 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12224 && (inst
.operands
[0].imm
& 4),
12225 _("selected processor does not support 'A' form "
12226 "of this instruction"));
12227 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12228 _("Thumb does not support the 2-argument "
12229 "form of this instruction"));
12230 inst
.instruction
|= inst
.operands
[0].imm
;
12234 /* THUMB CPY instruction (argument parse). */
12239 if (inst
.size_req
== 4)
12241 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12242 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12243 inst
.instruction
|= inst
.operands
[1].reg
;
12247 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12248 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12249 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12256 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12257 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12258 inst
.instruction
|= inst
.operands
[0].reg
;
12259 inst
.relocs
[0].pc_rel
= 1;
12260 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12266 inst
.instruction
|= inst
.operands
[0].imm
;
12272 unsigned Rd
, Rn
, Rm
;
12274 Rd
= inst
.operands
[0].reg
;
12275 Rn
= (inst
.operands
[1].present
12276 ? inst
.operands
[1].reg
: Rd
);
12277 Rm
= inst
.operands
[2].reg
;
12279 reject_bad_reg (Rd
);
12280 reject_bad_reg (Rn
);
12281 reject_bad_reg (Rm
);
12283 inst
.instruction
|= Rd
<< 8;
12284 inst
.instruction
|= Rn
<< 16;
12285 inst
.instruction
|= Rm
;
12291 if (unified_syntax
&& inst
.size_req
== 4)
12292 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12294 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12300 unsigned int cond
= inst
.operands
[0].imm
;
12302 set_pred_insn_type (IT_INSN
);
12303 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12304 now_pred
.cc
= cond
;
12305 now_pred
.warn_deprecated
= FALSE
;
12306 now_pred
.type
= SCALAR_PRED
;
12308 /* If the condition is a negative condition, invert the mask. */
12309 if ((cond
& 0x1) == 0x0)
12311 unsigned int mask
= inst
.instruction
& 0x000f;
12313 if ((mask
& 0x7) == 0)
12315 /* No conversion needed. */
12316 now_pred
.block_length
= 1;
12318 else if ((mask
& 0x3) == 0)
12321 now_pred
.block_length
= 2;
12323 else if ((mask
& 0x1) == 0)
12326 now_pred
.block_length
= 3;
12331 now_pred
.block_length
= 4;
12334 inst
.instruction
&= 0xfff0;
12335 inst
.instruction
|= mask
;
12338 inst
.instruction
|= cond
<< 4;
12341 /* Helper function used for both push/pop and ldm/stm. */
12343 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12344 bfd_boolean writeback
)
12346 bfd_boolean load
, store
;
12348 gas_assert (base
!= -1 || !do_io
);
12349 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12350 store
= do_io
&& !load
;
12352 if (mask
& (1 << 13))
12353 inst
.error
= _("SP not allowed in register list");
12355 if (do_io
&& (mask
& (1 << base
)) != 0
12357 inst
.error
= _("having the base register in the register list when "
12358 "using write back is UNPREDICTABLE");
12362 if (mask
& (1 << 15))
12364 if (mask
& (1 << 14))
12365 inst
.error
= _("LR and PC should not both be in register list");
12367 set_pred_insn_type_last ();
12372 if (mask
& (1 << 15))
12373 inst
.error
= _("PC not allowed in register list");
12376 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12378 /* Single register transfers implemented as str/ldr. */
12381 if (inst
.instruction
& (1 << 23))
12382 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12384 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12388 if (inst
.instruction
& (1 << 23))
12389 inst
.instruction
= 0x00800000; /* ia -> [base] */
12391 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12394 inst
.instruction
|= 0xf8400000;
12396 inst
.instruction
|= 0x00100000;
12398 mask
= ffs (mask
) - 1;
12401 else if (writeback
)
12402 inst
.instruction
|= WRITE_BACK
;
12404 inst
.instruction
|= mask
;
12406 inst
.instruction
|= base
<< 16;
12412 /* This really doesn't seem worth it. */
12413 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12414 _("expression too complex"));
12415 constraint (inst
.operands
[1].writeback
,
12416 _("Thumb load/store multiple does not support {reglist}^"));
12418 if (unified_syntax
)
12420 bfd_boolean narrow
;
12424 /* See if we can use a 16-bit instruction. */
12425 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12426 && inst
.size_req
!= 4
12427 && !(inst
.operands
[1].imm
& ~0xff))
12429 mask
= 1 << inst
.operands
[0].reg
;
12431 if (inst
.operands
[0].reg
<= 7)
12433 if (inst
.instruction
== T_MNEM_stmia
12434 ? inst
.operands
[0].writeback
12435 : (inst
.operands
[0].writeback
12436 == !(inst
.operands
[1].imm
& mask
)))
12438 if (inst
.instruction
== T_MNEM_stmia
12439 && (inst
.operands
[1].imm
& mask
)
12440 && (inst
.operands
[1].imm
& (mask
- 1)))
12441 as_warn (_("value stored for r%d is UNKNOWN"),
12442 inst
.operands
[0].reg
);
12444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12445 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12446 inst
.instruction
|= inst
.operands
[1].imm
;
12449 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12451 /* This means 1 register in reg list one of 3 situations:
12452 1. Instruction is stmia, but without writeback.
12453 2. lmdia without writeback, but with Rn not in
12455 3. ldmia with writeback, but with Rn in reglist.
12456 Case 3 is UNPREDICTABLE behaviour, so we handle
12457 case 1 and 2 which can be converted into a 16-bit
12458 str or ldr. The SP cases are handled below. */
12459 unsigned long opcode
;
12460 /* First, record an error for Case 3. */
12461 if (inst
.operands
[1].imm
& mask
12462 && inst
.operands
[0].writeback
)
12464 _("having the base register in the register list when "
12465 "using write back is UNPREDICTABLE");
12467 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12469 inst
.instruction
= THUMB_OP16 (opcode
);
12470 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12471 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12475 else if (inst
.operands
[0] .reg
== REG_SP
)
12477 if (inst
.operands
[0].writeback
)
12480 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12481 ? T_MNEM_push
: T_MNEM_pop
);
12482 inst
.instruction
|= inst
.operands
[1].imm
;
12485 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12488 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12489 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12490 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12498 if (inst
.instruction
< 0xffff)
12499 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12501 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12502 inst
.operands
[1].imm
,
12503 inst
.operands
[0].writeback
);
12508 constraint (inst
.operands
[0].reg
> 7
12509 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12510 constraint (inst
.instruction
!= T_MNEM_ldmia
12511 && inst
.instruction
!= T_MNEM_stmia
,
12512 _("Thumb-2 instruction only valid in unified syntax"));
12513 if (inst
.instruction
== T_MNEM_stmia
)
12515 if (!inst
.operands
[0].writeback
)
12516 as_warn (_("this instruction will write back the base register"));
12517 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12518 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12519 as_warn (_("value stored for r%d is UNKNOWN"),
12520 inst
.operands
[0].reg
);
12524 if (!inst
.operands
[0].writeback
12525 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12526 as_warn (_("this instruction will write back the base register"));
12527 else if (inst
.operands
[0].writeback
12528 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12529 as_warn (_("this instruction will not write back the base register"));
12532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12533 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12534 inst
.instruction
|= inst
.operands
[1].imm
;
12541 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12542 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12543 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12544 || inst
.operands
[1].negative
,
12547 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12550 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12551 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12557 if (!inst
.operands
[1].present
)
12559 constraint (inst
.operands
[0].reg
== REG_LR
,
12560 _("r14 not allowed as first register "
12561 "when second register is omitted"));
12562 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12564 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12568 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12569 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12575 unsigned long opcode
;
12578 if (inst
.operands
[0].isreg
12579 && !inst
.operands
[0].preind
12580 && inst
.operands
[0].reg
== REG_PC
)
12581 set_pred_insn_type_last ();
12583 opcode
= inst
.instruction
;
12584 if (unified_syntax
)
12586 if (!inst
.operands
[1].isreg
)
12588 if (opcode
<= 0xffff)
12589 inst
.instruction
= THUMB_OP32 (opcode
);
12590 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12593 if (inst
.operands
[1].isreg
12594 && !inst
.operands
[1].writeback
12595 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12596 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12597 && opcode
<= 0xffff
12598 && inst
.size_req
!= 4)
12600 /* Insn may have a 16-bit form. */
12601 Rn
= inst
.operands
[1].reg
;
12602 if (inst
.operands
[1].immisreg
)
12604 inst
.instruction
= THUMB_OP16 (opcode
);
12606 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12608 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12609 reject_bad_reg (inst
.operands
[1].imm
);
12611 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12612 && opcode
!= T_MNEM_ldrsb
)
12613 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12614 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12621 if (inst
.relocs
[0].pc_rel
)
12622 opcode
= T_MNEM_ldr_pc2
;
12624 opcode
= T_MNEM_ldr_pc
;
12628 if (opcode
== T_MNEM_ldr
)
12629 opcode
= T_MNEM_ldr_sp
;
12631 opcode
= T_MNEM_str_sp
;
12633 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12637 inst
.instruction
= inst
.operands
[0].reg
;
12638 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12640 inst
.instruction
|= THUMB_OP16 (opcode
);
12641 if (inst
.size_req
== 2)
12642 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12644 inst
.relax
= opcode
;
12648 /* Definitely a 32-bit variant. */
12650 /* Warning for Erratum 752419. */
12651 if (opcode
== T_MNEM_ldr
12652 && inst
.operands
[0].reg
== REG_SP
12653 && inst
.operands
[1].writeback
== 1
12654 && !inst
.operands
[1].immisreg
)
12656 if (no_cpu_selected ()
12657 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12658 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12659 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12660 as_warn (_("This instruction may be unpredictable "
12661 "if executed on M-profile cores "
12662 "with interrupts enabled."));
12665 /* Do some validations regarding addressing modes. */
12666 if (inst
.operands
[1].immisreg
)
12667 reject_bad_reg (inst
.operands
[1].imm
);
12669 constraint (inst
.operands
[1].writeback
== 1
12670 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12673 inst
.instruction
= THUMB_OP32 (opcode
);
12674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12675 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12676 check_ldr_r15_aligned ();
12680 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12682 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12684 /* Only [Rn,Rm] is acceptable. */
12685 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12686 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12687 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12688 || inst
.operands
[1].negative
,
12689 _("Thumb does not support this addressing mode"));
12690 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12695 if (!inst
.operands
[1].isreg
)
12696 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12699 constraint (!inst
.operands
[1].preind
12700 || inst
.operands
[1].shifted
12701 || inst
.operands
[1].writeback
,
12702 _("Thumb does not support this addressing mode"));
12703 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12705 constraint (inst
.instruction
& 0x0600,
12706 _("byte or halfword not valid for base register"));
12707 constraint (inst
.operands
[1].reg
== REG_PC
12708 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12709 _("r15 based store not allowed"));
12710 constraint (inst
.operands
[1].immisreg
,
12711 _("invalid base register for register offset"));
12713 if (inst
.operands
[1].reg
== REG_PC
)
12714 inst
.instruction
= T_OPCODE_LDR_PC
;
12715 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12716 inst
.instruction
= T_OPCODE_LDR_SP
;
12718 inst
.instruction
= T_OPCODE_STR_SP
;
12720 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12721 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12725 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12726 if (!inst
.operands
[1].immisreg
)
12728 /* Immediate offset. */
12729 inst
.instruction
|= inst
.operands
[0].reg
;
12730 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12731 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12735 /* Register offset. */
12736 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12737 constraint (inst
.operands
[1].negative
,
12738 _("Thumb does not support this addressing mode"));
12741 switch (inst
.instruction
)
12743 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12744 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12745 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12746 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12747 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12748 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12749 case 0x5600 /* ldrsb */:
12750 case 0x5e00 /* ldrsh */: break;
12754 inst
.instruction
|= inst
.operands
[0].reg
;
12755 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12756 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12762 if (!inst
.operands
[1].present
)
12764 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12765 constraint (inst
.operands
[0].reg
== REG_LR
,
12766 _("r14 not allowed here"));
12767 constraint (inst
.operands
[0].reg
== REG_R12
,
12768 _("r12 not allowed here"));
12771 if (inst
.operands
[2].writeback
12772 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12773 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12774 as_warn (_("base register written back, and overlaps "
12775 "one of transfer registers"));
12777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12778 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12779 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12786 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12792 unsigned Rd
, Rn
, Rm
, Ra
;
12794 Rd
= inst
.operands
[0].reg
;
12795 Rn
= inst
.operands
[1].reg
;
12796 Rm
= inst
.operands
[2].reg
;
12797 Ra
= inst
.operands
[3].reg
;
12799 reject_bad_reg (Rd
);
12800 reject_bad_reg (Rn
);
12801 reject_bad_reg (Rm
);
12802 reject_bad_reg (Ra
);
12804 inst
.instruction
|= Rd
<< 8;
12805 inst
.instruction
|= Rn
<< 16;
12806 inst
.instruction
|= Rm
;
12807 inst
.instruction
|= Ra
<< 12;
12813 unsigned RdLo
, RdHi
, Rn
, Rm
;
12815 RdLo
= inst
.operands
[0].reg
;
12816 RdHi
= inst
.operands
[1].reg
;
12817 Rn
= inst
.operands
[2].reg
;
12818 Rm
= inst
.operands
[3].reg
;
12820 reject_bad_reg (RdLo
);
12821 reject_bad_reg (RdHi
);
12822 reject_bad_reg (Rn
);
12823 reject_bad_reg (Rm
);
12825 inst
.instruction
|= RdLo
<< 12;
12826 inst
.instruction
|= RdHi
<< 8;
12827 inst
.instruction
|= Rn
<< 16;
12828 inst
.instruction
|= Rm
;
12832 do_t_mov_cmp (void)
12836 Rn
= inst
.operands
[0].reg
;
12837 Rm
= inst
.operands
[1].reg
;
12840 set_pred_insn_type_last ();
12842 if (unified_syntax
)
12844 int r0off
= (inst
.instruction
== T_MNEM_mov
12845 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12846 unsigned long opcode
;
12847 bfd_boolean narrow
;
12848 bfd_boolean low_regs
;
12850 low_regs
= (Rn
<= 7 && Rm
<= 7);
12851 opcode
= inst
.instruction
;
12852 if (in_pred_block ())
12853 narrow
= opcode
!= T_MNEM_movs
;
12855 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12856 if (inst
.size_req
== 4
12857 || inst
.operands
[1].shifted
)
12860 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12861 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12862 && !inst
.operands
[1].shifted
12866 inst
.instruction
= T2_SUBS_PC_LR
;
12870 if (opcode
== T_MNEM_cmp
)
12872 constraint (Rn
== REG_PC
, BAD_PC
);
12875 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12877 warn_deprecated_sp (Rm
);
12878 /* R15 was documented as a valid choice for Rm in ARMv6,
12879 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12880 tools reject R15, so we do too. */
12881 constraint (Rm
== REG_PC
, BAD_PC
);
12884 reject_bad_reg (Rm
);
12886 else if (opcode
== T_MNEM_mov
12887 || opcode
== T_MNEM_movs
)
12889 if (inst
.operands
[1].isreg
)
12891 if (opcode
== T_MNEM_movs
)
12893 reject_bad_reg (Rn
);
12894 reject_bad_reg (Rm
);
12898 /* This is mov.n. */
12899 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12900 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12902 as_tsktsk (_("Use of r%u as a source register is "
12903 "deprecated when r%u is the destination "
12904 "register."), Rm
, Rn
);
12909 /* This is mov.w. */
12910 constraint (Rn
== REG_PC
, BAD_PC
);
12911 constraint (Rm
== REG_PC
, BAD_PC
);
12912 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12913 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12917 reject_bad_reg (Rn
);
12920 if (!inst
.operands
[1].isreg
)
12922 /* Immediate operand. */
12923 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12925 if (low_regs
&& narrow
)
12927 inst
.instruction
= THUMB_OP16 (opcode
);
12928 inst
.instruction
|= Rn
<< 8;
12929 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12930 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12932 if (inst
.size_req
== 2)
12933 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12935 inst
.relax
= opcode
;
12940 constraint ((inst
.relocs
[0].type
12941 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12942 && (inst
.relocs
[0].type
12943 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12944 THUMB1_RELOC_ONLY
);
12946 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12947 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12948 inst
.instruction
|= Rn
<< r0off
;
12949 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12952 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12953 && (inst
.instruction
== T_MNEM_mov
12954 || inst
.instruction
== T_MNEM_movs
))
12956 /* Register shifts are encoded as separate shift instructions. */
12957 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12959 if (in_pred_block ())
12964 if (inst
.size_req
== 4)
12967 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12973 switch (inst
.operands
[1].shift_kind
)
12976 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12979 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12982 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12985 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12991 inst
.instruction
= opcode
;
12994 inst
.instruction
|= Rn
;
12995 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13000 inst
.instruction
|= CONDS_BIT
;
13002 inst
.instruction
|= Rn
<< 8;
13003 inst
.instruction
|= Rm
<< 16;
13004 inst
.instruction
|= inst
.operands
[1].imm
;
13009 /* Some mov with immediate shift have narrow variants.
13010 Register shifts are handled above. */
13011 if (low_regs
&& inst
.operands
[1].shifted
13012 && (inst
.instruction
== T_MNEM_mov
13013 || inst
.instruction
== T_MNEM_movs
))
13015 if (in_pred_block ())
13016 narrow
= (inst
.instruction
== T_MNEM_mov
);
13018 narrow
= (inst
.instruction
== T_MNEM_movs
);
13023 switch (inst
.operands
[1].shift_kind
)
13025 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13026 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13027 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13028 default: narrow
= FALSE
; break;
13034 inst
.instruction
|= Rn
;
13035 inst
.instruction
|= Rm
<< 3;
13036 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13040 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13041 inst
.instruction
|= Rn
<< r0off
;
13042 encode_thumb32_shifted_operand (1);
13046 switch (inst
.instruction
)
13049 /* In v4t or v5t a move of two lowregs produces unpredictable
13050 results. Don't allow this. */
13053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13054 "MOV Rd, Rs with two low registers is not "
13055 "permitted on this architecture");
13056 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13060 inst
.instruction
= T_OPCODE_MOV_HR
;
13061 inst
.instruction
|= (Rn
& 0x8) << 4;
13062 inst
.instruction
|= (Rn
& 0x7);
13063 inst
.instruction
|= Rm
<< 3;
13067 /* We know we have low registers at this point.
13068 Generate LSLS Rd, Rs, #0. */
13069 inst
.instruction
= T_OPCODE_LSL_I
;
13070 inst
.instruction
|= Rn
;
13071 inst
.instruction
|= Rm
<< 3;
13077 inst
.instruction
= T_OPCODE_CMP_LR
;
13078 inst
.instruction
|= Rn
;
13079 inst
.instruction
|= Rm
<< 3;
13083 inst
.instruction
= T_OPCODE_CMP_HR
;
13084 inst
.instruction
|= (Rn
& 0x8) << 4;
13085 inst
.instruction
|= (Rn
& 0x7);
13086 inst
.instruction
|= Rm
<< 3;
13093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13095 /* PR 10443: Do not silently ignore shifted operands. */
13096 constraint (inst
.operands
[1].shifted
,
13097 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13099 if (inst
.operands
[1].isreg
)
13101 if (Rn
< 8 && Rm
< 8)
13103 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13104 since a MOV instruction produces unpredictable results. */
13105 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13106 inst
.instruction
= T_OPCODE_ADD_I3
;
13108 inst
.instruction
= T_OPCODE_CMP_LR
;
13110 inst
.instruction
|= Rn
;
13111 inst
.instruction
|= Rm
<< 3;
13115 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13116 inst
.instruction
= T_OPCODE_MOV_HR
;
13118 inst
.instruction
= T_OPCODE_CMP_HR
;
13124 constraint (Rn
> 7,
13125 _("only lo regs allowed with immediate"));
13126 inst
.instruction
|= Rn
<< 8;
13127 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13138 top
= (inst
.instruction
& 0x00800000) != 0;
13139 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13141 constraint (top
, _(":lower16: not allowed in this instruction"));
13142 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13144 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13146 constraint (!top
, _(":upper16: not allowed in this instruction"));
13147 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13150 Rd
= inst
.operands
[0].reg
;
13151 reject_bad_reg (Rd
);
13153 inst
.instruction
|= Rd
<< 8;
13154 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13156 imm
= inst
.relocs
[0].exp
.X_add_number
;
13157 inst
.instruction
|= (imm
& 0xf000) << 4;
13158 inst
.instruction
|= (imm
& 0x0800) << 15;
13159 inst
.instruction
|= (imm
& 0x0700) << 4;
13160 inst
.instruction
|= (imm
& 0x00ff);
13165 do_t_mvn_tst (void)
13169 Rn
= inst
.operands
[0].reg
;
13170 Rm
= inst
.operands
[1].reg
;
13172 if (inst
.instruction
== T_MNEM_cmp
13173 || inst
.instruction
== T_MNEM_cmn
)
13174 constraint (Rn
== REG_PC
, BAD_PC
);
13176 reject_bad_reg (Rn
);
13177 reject_bad_reg (Rm
);
13179 if (unified_syntax
)
13181 int r0off
= (inst
.instruction
== T_MNEM_mvn
13182 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13183 bfd_boolean narrow
;
13185 if (inst
.size_req
== 4
13186 || inst
.instruction
> 0xffff
13187 || inst
.operands
[1].shifted
13188 || Rn
> 7 || Rm
> 7)
13190 else if (inst
.instruction
== T_MNEM_cmn
13191 || inst
.instruction
== T_MNEM_tst
)
13193 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13194 narrow
= !in_pred_block ();
13196 narrow
= in_pred_block ();
13198 if (!inst
.operands
[1].isreg
)
13200 /* For an immediate, we always generate a 32-bit opcode;
13201 section relaxation will shrink it later if possible. */
13202 if (inst
.instruction
< 0xffff)
13203 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13204 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13205 inst
.instruction
|= Rn
<< r0off
;
13206 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13210 /* See if we can do this with a 16-bit instruction. */
13213 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13214 inst
.instruction
|= Rn
;
13215 inst
.instruction
|= Rm
<< 3;
13219 constraint (inst
.operands
[1].shifted
13220 && inst
.operands
[1].immisreg
,
13221 _("shift must be constant"));
13222 if (inst
.instruction
< 0xffff)
13223 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13224 inst
.instruction
|= Rn
<< r0off
;
13225 encode_thumb32_shifted_operand (1);
13231 constraint (inst
.instruction
> 0xffff
13232 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13233 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13234 _("unshifted register required"));
13235 constraint (Rn
> 7 || Rm
> 7,
13238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13239 inst
.instruction
|= Rn
;
13240 inst
.instruction
|= Rm
<< 3;
13249 if (do_vfp_nsyn_mrs () == SUCCESS
)
13252 Rd
= inst
.operands
[0].reg
;
13253 reject_bad_reg (Rd
);
13254 inst
.instruction
|= Rd
<< 8;
13256 if (inst
.operands
[1].isreg
)
13258 unsigned br
= inst
.operands
[1].reg
;
13259 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13260 as_bad (_("bad register for mrs"));
13262 inst
.instruction
|= br
& (0xf << 16);
13263 inst
.instruction
|= (br
& 0x300) >> 4;
13264 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13268 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13270 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13272 /* PR gas/12698: The constraint is only applied for m_profile.
13273 If the user has specified -march=all, we want to ignore it as
13274 we are building for any CPU type, including non-m variants. */
13275 bfd_boolean m_profile
=
13276 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13277 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13278 "not support requested special purpose register"));
13281 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13283 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13284 _("'APSR', 'CPSR' or 'SPSR' expected"));
13286 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13287 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13288 inst
.instruction
|= 0xf0000;
13298 if (do_vfp_nsyn_msr () == SUCCESS
)
13301 constraint (!inst
.operands
[1].isreg
,
13302 _("Thumb encoding does not support an immediate here"));
13304 if (inst
.operands
[0].isreg
)
13305 flags
= (int)(inst
.operands
[0].reg
);
13307 flags
= inst
.operands
[0].imm
;
13309 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13311 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13313 /* PR gas/12698: The constraint is only applied for m_profile.
13314 If the user has specified -march=all, we want to ignore it as
13315 we are building for any CPU type, including non-m variants. */
13316 bfd_boolean m_profile
=
13317 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13318 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13319 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13320 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13321 && bits
!= PSR_f
)) && m_profile
,
13322 _("selected processor does not support requested special "
13323 "purpose register"));
13326 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13327 "requested special purpose register"));
13329 Rn
= inst
.operands
[1].reg
;
13330 reject_bad_reg (Rn
);
13332 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13333 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13334 inst
.instruction
|= (flags
& 0x300) >> 4;
13335 inst
.instruction
|= (flags
& 0xff);
13336 inst
.instruction
|= Rn
<< 16;
13342 bfd_boolean narrow
;
13343 unsigned Rd
, Rn
, Rm
;
13345 if (!inst
.operands
[2].present
)
13346 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13348 Rd
= inst
.operands
[0].reg
;
13349 Rn
= inst
.operands
[1].reg
;
13350 Rm
= inst
.operands
[2].reg
;
13352 if (unified_syntax
)
13354 if (inst
.size_req
== 4
13360 else if (inst
.instruction
== T_MNEM_muls
)
13361 narrow
= !in_pred_block ();
13363 narrow
= in_pred_block ();
13367 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13368 constraint (Rn
> 7 || Rm
> 7,
13375 /* 16-bit MULS/Conditional MUL. */
13376 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13377 inst
.instruction
|= Rd
;
13380 inst
.instruction
|= Rm
<< 3;
13382 inst
.instruction
|= Rn
<< 3;
13384 constraint (1, _("dest must overlap one source register"));
13388 constraint (inst
.instruction
!= T_MNEM_mul
,
13389 _("Thumb-2 MUL must not set flags"));
13391 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13392 inst
.instruction
|= Rd
<< 8;
13393 inst
.instruction
|= Rn
<< 16;
13394 inst
.instruction
|= Rm
<< 0;
13396 reject_bad_reg (Rd
);
13397 reject_bad_reg (Rn
);
13398 reject_bad_reg (Rm
);
13405 unsigned RdLo
, RdHi
, Rn
, Rm
;
13407 RdLo
= inst
.operands
[0].reg
;
13408 RdHi
= inst
.operands
[1].reg
;
13409 Rn
= inst
.operands
[2].reg
;
13410 Rm
= inst
.operands
[3].reg
;
13412 reject_bad_reg (RdLo
);
13413 reject_bad_reg (RdHi
);
13414 reject_bad_reg (Rn
);
13415 reject_bad_reg (Rm
);
13417 inst
.instruction
|= RdLo
<< 12;
13418 inst
.instruction
|= RdHi
<< 8;
13419 inst
.instruction
|= Rn
<< 16;
13420 inst
.instruction
|= Rm
;
13423 as_tsktsk (_("rdhi and rdlo must be different"));
13429 set_pred_insn_type (NEUTRAL_IT_INSN
);
13431 if (unified_syntax
)
13433 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13436 inst
.instruction
|= inst
.operands
[0].imm
;
13440 /* PR9722: Check for Thumb2 availability before
13441 generating a thumb2 nop instruction. */
13442 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13445 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13448 inst
.instruction
= 0x46c0;
13453 constraint (inst
.operands
[0].present
,
13454 _("Thumb does not support NOP with hints"));
13455 inst
.instruction
= 0x46c0;
13462 if (unified_syntax
)
13464 bfd_boolean narrow
;
13466 if (THUMB_SETS_FLAGS (inst
.instruction
))
13467 narrow
= !in_pred_block ();
13469 narrow
= in_pred_block ();
13470 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13472 if (inst
.size_req
== 4)
13477 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13478 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13479 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13483 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13484 inst
.instruction
|= inst
.operands
[0].reg
;
13485 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13490 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13492 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13494 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13495 inst
.instruction
|= inst
.operands
[0].reg
;
13496 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13505 Rd
= inst
.operands
[0].reg
;
13506 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13508 reject_bad_reg (Rd
);
13509 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13510 reject_bad_reg (Rn
);
13512 inst
.instruction
|= Rd
<< 8;
13513 inst
.instruction
|= Rn
<< 16;
13515 if (!inst
.operands
[2].isreg
)
13517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13518 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13524 Rm
= inst
.operands
[2].reg
;
13525 reject_bad_reg (Rm
);
13527 constraint (inst
.operands
[2].shifted
13528 && inst
.operands
[2].immisreg
,
13529 _("shift must be constant"));
13530 encode_thumb32_shifted_operand (2);
13537 unsigned Rd
, Rn
, Rm
;
13539 Rd
= inst
.operands
[0].reg
;
13540 Rn
= inst
.operands
[1].reg
;
13541 Rm
= inst
.operands
[2].reg
;
13543 reject_bad_reg (Rd
);
13544 reject_bad_reg (Rn
);
13545 reject_bad_reg (Rm
);
13547 inst
.instruction
|= Rd
<< 8;
13548 inst
.instruction
|= Rn
<< 16;
13549 inst
.instruction
|= Rm
;
13550 if (inst
.operands
[3].present
)
13552 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13553 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13554 _("expression too complex"));
13555 inst
.instruction
|= (val
& 0x1c) << 10;
13556 inst
.instruction
|= (val
& 0x03) << 6;
13563 if (!inst
.operands
[3].present
)
13567 inst
.instruction
&= ~0x00000020;
13569 /* PR 10168. Swap the Rm and Rn registers. */
13570 Rtmp
= inst
.operands
[1].reg
;
13571 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13572 inst
.operands
[2].reg
= Rtmp
;
13580 if (inst
.operands
[0].immisreg
)
13581 reject_bad_reg (inst
.operands
[0].imm
);
13583 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13587 do_t_push_pop (void)
13591 constraint (inst
.operands
[0].writeback
,
13592 _("push/pop do not support {reglist}^"));
13593 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13594 _("expression too complex"));
13596 mask
= inst
.operands
[0].imm
;
13597 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13598 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13599 else if (inst
.size_req
!= 4
13600 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13601 ? REG_LR
: REG_PC
)))
13603 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13604 inst
.instruction
|= THUMB_PP_PC_LR
;
13605 inst
.instruction
|= mask
& 0xff;
13607 else if (unified_syntax
)
13609 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13610 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13614 inst
.error
= _("invalid register list to push/pop instruction");
13622 if (unified_syntax
)
13623 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13626 inst
.error
= _("invalid register list to push/pop instruction");
13632 do_t_vscclrm (void)
13634 if (inst
.operands
[0].issingle
)
13636 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13637 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13638 inst
.instruction
|= inst
.operands
[0].imm
;
13642 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13643 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13644 inst
.instruction
|= 1 << 8;
13645 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13654 Rd
= inst
.operands
[0].reg
;
13655 Rm
= inst
.operands
[1].reg
;
13657 reject_bad_reg (Rd
);
13658 reject_bad_reg (Rm
);
13660 inst
.instruction
|= Rd
<< 8;
13661 inst
.instruction
|= Rm
<< 16;
13662 inst
.instruction
|= Rm
;
13670 Rd
= inst
.operands
[0].reg
;
13671 Rm
= inst
.operands
[1].reg
;
13673 reject_bad_reg (Rd
);
13674 reject_bad_reg (Rm
);
13676 if (Rd
<= 7 && Rm
<= 7
13677 && inst
.size_req
!= 4)
13679 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13680 inst
.instruction
|= Rd
;
13681 inst
.instruction
|= Rm
<< 3;
13683 else if (unified_syntax
)
13685 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13686 inst
.instruction
|= Rd
<< 8;
13687 inst
.instruction
|= Rm
<< 16;
13688 inst
.instruction
|= Rm
;
13691 inst
.error
= BAD_HIREG
;
13699 Rd
= inst
.operands
[0].reg
;
13700 Rm
= inst
.operands
[1].reg
;
13702 reject_bad_reg (Rd
);
13703 reject_bad_reg (Rm
);
13705 inst
.instruction
|= Rd
<< 8;
13706 inst
.instruction
|= Rm
;
13714 Rd
= inst
.operands
[0].reg
;
13715 Rs
= (inst
.operands
[1].present
13716 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13717 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13719 reject_bad_reg (Rd
);
13720 reject_bad_reg (Rs
);
13721 if (inst
.operands
[2].isreg
)
13722 reject_bad_reg (inst
.operands
[2].reg
);
13724 inst
.instruction
|= Rd
<< 8;
13725 inst
.instruction
|= Rs
<< 16;
13726 if (!inst
.operands
[2].isreg
)
13728 bfd_boolean narrow
;
13730 if ((inst
.instruction
& 0x00100000) != 0)
13731 narrow
= !in_pred_block ();
13733 narrow
= in_pred_block ();
13735 if (Rd
> 7 || Rs
> 7)
13738 if (inst
.size_req
== 4 || !unified_syntax
)
13741 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13742 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13745 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13746 relaxation, but it doesn't seem worth the hassle. */
13749 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13750 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13751 inst
.instruction
|= Rs
<< 3;
13752 inst
.instruction
|= Rd
;
13756 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13757 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13761 encode_thumb32_shifted_operand (2);
13767 if (warn_on_deprecated
13768 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13769 as_tsktsk (_("setend use is deprecated for ARMv8"));
13771 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13772 if (inst
.operands
[0].imm
)
13773 inst
.instruction
|= 0x8;
13779 if (!inst
.operands
[1].present
)
13780 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13782 if (unified_syntax
)
13784 bfd_boolean narrow
;
13787 switch (inst
.instruction
)
13790 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13792 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13794 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13796 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13800 if (THUMB_SETS_FLAGS (inst
.instruction
))
13801 narrow
= !in_pred_block ();
13803 narrow
= in_pred_block ();
13804 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13806 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13808 if (inst
.operands
[2].isreg
13809 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13810 || inst
.operands
[2].reg
> 7))
13812 if (inst
.size_req
== 4)
13815 reject_bad_reg (inst
.operands
[0].reg
);
13816 reject_bad_reg (inst
.operands
[1].reg
);
13820 if (inst
.operands
[2].isreg
)
13822 reject_bad_reg (inst
.operands
[2].reg
);
13823 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13824 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13825 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13826 inst
.instruction
|= inst
.operands
[2].reg
;
13828 /* PR 12854: Error on extraneous shifts. */
13829 constraint (inst
.operands
[2].shifted
,
13830 _("extraneous shift as part of operand to shift insn"));
13834 inst
.operands
[1].shifted
= 1;
13835 inst
.operands
[1].shift_kind
= shift_kind
;
13836 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13837 ? T_MNEM_movs
: T_MNEM_mov
);
13838 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13839 encode_thumb32_shifted_operand (1);
13840 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13841 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13846 if (inst
.operands
[2].isreg
)
13848 switch (shift_kind
)
13850 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13851 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13852 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13853 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13857 inst
.instruction
|= inst
.operands
[0].reg
;
13858 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13860 /* PR 12854: Error on extraneous shifts. */
13861 constraint (inst
.operands
[2].shifted
,
13862 _("extraneous shift as part of operand to shift insn"));
13866 switch (shift_kind
)
13868 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13869 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13870 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13873 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13874 inst
.instruction
|= inst
.operands
[0].reg
;
13875 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13881 constraint (inst
.operands
[0].reg
> 7
13882 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13883 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13885 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13887 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13888 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13889 _("source1 and dest must be same register"));
13891 switch (inst
.instruction
)
13893 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13894 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13895 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13896 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13900 inst
.instruction
|= inst
.operands
[0].reg
;
13901 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13903 /* PR 12854: Error on extraneous shifts. */
13904 constraint (inst
.operands
[2].shifted
,
13905 _("extraneous shift as part of operand to shift insn"));
13909 switch (inst
.instruction
)
13911 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13912 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13913 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13914 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13917 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13918 inst
.instruction
|= inst
.operands
[0].reg
;
13919 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13927 unsigned Rd
, Rn
, Rm
;
13929 Rd
= inst
.operands
[0].reg
;
13930 Rn
= inst
.operands
[1].reg
;
13931 Rm
= inst
.operands
[2].reg
;
13933 reject_bad_reg (Rd
);
13934 reject_bad_reg (Rn
);
13935 reject_bad_reg (Rm
);
13937 inst
.instruction
|= Rd
<< 8;
13938 inst
.instruction
|= Rn
<< 16;
13939 inst
.instruction
|= Rm
;
13945 unsigned Rd
, Rn
, Rm
;
13947 Rd
= inst
.operands
[0].reg
;
13948 Rm
= inst
.operands
[1].reg
;
13949 Rn
= inst
.operands
[2].reg
;
13951 reject_bad_reg (Rd
);
13952 reject_bad_reg (Rn
);
13953 reject_bad_reg (Rm
);
13955 inst
.instruction
|= Rd
<< 8;
13956 inst
.instruction
|= Rn
<< 16;
13957 inst
.instruction
|= Rm
;
13963 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13965 _("SMC is not permitted on this architecture"));
13966 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13967 _("expression too complex"));
13968 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13970 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13971 inst
.instruction
|= (value
& 0x000f) << 16;
13973 /* PR gas/15623: SMC instructions must be last in an IT block. */
13974 set_pred_insn_type_last ();
13980 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13982 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13983 inst
.instruction
|= (value
& 0x0fff);
13984 inst
.instruction
|= (value
& 0xf000) << 4;
13988 do_t_ssat_usat (int bias
)
13992 Rd
= inst
.operands
[0].reg
;
13993 Rn
= inst
.operands
[2].reg
;
13995 reject_bad_reg (Rd
);
13996 reject_bad_reg (Rn
);
13998 inst
.instruction
|= Rd
<< 8;
13999 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14000 inst
.instruction
|= Rn
<< 16;
14002 if (inst
.operands
[3].present
)
14004 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14006 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14008 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14009 _("expression too complex"));
14011 if (shift_amount
!= 0)
14013 constraint (shift_amount
> 31,
14014 _("shift expression is too large"));
14016 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14017 inst
.instruction
|= 0x00200000; /* sh bit. */
14019 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14020 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14028 do_t_ssat_usat (1);
14036 Rd
= inst
.operands
[0].reg
;
14037 Rn
= inst
.operands
[2].reg
;
14039 reject_bad_reg (Rd
);
14040 reject_bad_reg (Rn
);
14042 inst
.instruction
|= Rd
<< 8;
14043 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14044 inst
.instruction
|= Rn
<< 16;
14050 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14051 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14052 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14053 || inst
.operands
[2].negative
,
14056 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14058 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14059 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14060 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14061 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14067 if (!inst
.operands
[2].present
)
14068 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14070 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14071 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14072 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14075 inst
.instruction
|= inst
.operands
[0].reg
;
14076 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14077 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14078 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14084 unsigned Rd
, Rn
, Rm
;
14086 Rd
= inst
.operands
[0].reg
;
14087 Rn
= inst
.operands
[1].reg
;
14088 Rm
= inst
.operands
[2].reg
;
14090 reject_bad_reg (Rd
);
14091 reject_bad_reg (Rn
);
14092 reject_bad_reg (Rm
);
14094 inst
.instruction
|= Rd
<< 8;
14095 inst
.instruction
|= Rn
<< 16;
14096 inst
.instruction
|= Rm
;
14097 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14105 Rd
= inst
.operands
[0].reg
;
14106 Rm
= inst
.operands
[1].reg
;
14108 reject_bad_reg (Rd
);
14109 reject_bad_reg (Rm
);
14111 if (inst
.instruction
<= 0xffff
14112 && inst
.size_req
!= 4
14113 && Rd
<= 7 && Rm
<= 7
14114 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14116 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14117 inst
.instruction
|= Rd
;
14118 inst
.instruction
|= Rm
<< 3;
14120 else if (unified_syntax
)
14122 if (inst
.instruction
<= 0xffff)
14123 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14124 inst
.instruction
|= Rd
<< 8;
14125 inst
.instruction
|= Rm
;
14126 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14130 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14131 _("Thumb encoding does not support rotation"));
14132 constraint (1, BAD_HIREG
);
14139 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14148 half
= (inst
.instruction
& 0x10) != 0;
14149 set_pred_insn_type_last ();
14150 constraint (inst
.operands
[0].immisreg
,
14151 _("instruction requires register index"));
14153 Rn
= inst
.operands
[0].reg
;
14154 Rm
= inst
.operands
[0].imm
;
14156 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14157 constraint (Rn
== REG_SP
, BAD_SP
);
14158 reject_bad_reg (Rm
);
14160 constraint (!half
&& inst
.operands
[0].shifted
,
14161 _("instruction does not allow shifted index"));
14162 inst
.instruction
|= (Rn
<< 16) | Rm
;
14168 if (!inst
.operands
[0].present
)
14169 inst
.operands
[0].imm
= 0;
14171 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14173 constraint (inst
.size_req
== 2,
14174 _("immediate value out of range"));
14175 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14176 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14177 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14181 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14182 inst
.instruction
|= inst
.operands
[0].imm
;
14185 set_pred_insn_type (NEUTRAL_IT_INSN
);
14192 do_t_ssat_usat (0);
14200 Rd
= inst
.operands
[0].reg
;
14201 Rn
= inst
.operands
[2].reg
;
14203 reject_bad_reg (Rd
);
14204 reject_bad_reg (Rn
);
14206 inst
.instruction
|= Rd
<< 8;
14207 inst
.instruction
|= inst
.operands
[1].imm
;
14208 inst
.instruction
|= Rn
<< 16;
14211 /* Checking the range of the branch offset (VAL) with NBITS bits
14212 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14214 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14216 gas_assert (nbits
> 0 && nbits
<= 32);
14219 int cmp
= (1 << (nbits
- 1));
14220 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14225 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14231 /* For branches in Armv8.1-M Mainline. */
14233 do_t_branch_future (void)
14235 unsigned long insn
= inst
.instruction
;
14237 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14238 if (inst
.operands
[0].hasreloc
== 0)
14240 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14241 as_bad (BAD_BRANCH_OFF
);
14243 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14247 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14248 inst
.relocs
[0].pc_rel
= 1;
14254 if (inst
.operands
[1].hasreloc
== 0)
14256 int val
= inst
.operands
[1].imm
;
14257 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14258 as_bad (BAD_BRANCH_OFF
);
14260 int immA
= (val
& 0x0001f000) >> 12;
14261 int immB
= (val
& 0x00000ffc) >> 2;
14262 int immC
= (val
& 0x00000002) >> 1;
14263 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14267 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14268 inst
.relocs
[1].pc_rel
= 1;
14273 if (inst
.operands
[1].hasreloc
== 0)
14275 int val
= inst
.operands
[1].imm
;
14276 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14277 as_bad (BAD_BRANCH_OFF
);
14279 int immA
= (val
& 0x0007f000) >> 12;
14280 int immB
= (val
& 0x00000ffc) >> 2;
14281 int immC
= (val
& 0x00000002) >> 1;
14282 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14286 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14287 inst
.relocs
[1].pc_rel
= 1;
14291 case T_MNEM_bfcsel
:
14293 if (inst
.operands
[1].hasreloc
== 0)
14295 int val
= inst
.operands
[1].imm
;
14296 int immA
= (val
& 0x00001000) >> 12;
14297 int immB
= (val
& 0x00000ffc) >> 2;
14298 int immC
= (val
& 0x00000002) >> 1;
14299 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14303 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14304 inst
.relocs
[1].pc_rel
= 1;
14308 if (inst
.operands
[2].hasreloc
== 0)
14310 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14311 int val2
= inst
.operands
[2].imm
;
14312 int val0
= inst
.operands
[0].imm
& 0x1f;
14313 int diff
= val2
- val0
;
14315 inst
.instruction
|= 1 << 17; /* T bit. */
14316 else if (diff
!= 2)
14317 as_bad (_("out of range label-relative fixup value"));
14321 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14322 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14323 inst
.relocs
[2].pc_rel
= 1;
14327 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14328 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14333 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14340 /* Helper function for do_t_loloop to handle relocations. */
14342 v8_1_loop_reloc (int is_le
)
14344 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14346 int value
= inst
.relocs
[0].exp
.X_add_number
;
14347 value
= (is_le
) ? -value
: value
;
14349 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14350 as_bad (BAD_BRANCH_OFF
);
14354 immh
= (value
& 0x00000ffc) >> 2;
14355 imml
= (value
& 0x00000002) >> 1;
14357 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14361 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14362 inst
.relocs
[0].pc_rel
= 1;
14366 /* For shifts with four operands in MVE. */
14368 do_mve_scalar_shift1 (void)
14370 unsigned int value
= inst
.operands
[2].imm
;
14372 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14373 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14375 /* Setting the bit for saturation. */
14376 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14378 /* Assuming Rm is already checked not to be 11x1. */
14379 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14380 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14381 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14384 /* For shifts in MVE. */
14386 do_mve_scalar_shift (void)
14388 if (!inst
.operands
[2].present
)
14390 inst
.operands
[2] = inst
.operands
[1];
14391 inst
.operands
[1].reg
= 0xf;
14394 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14395 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14397 if (inst
.operands
[2].isreg
)
14399 /* Assuming Rm is already checked not to be 11x1. */
14400 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14401 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14402 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14406 /* Assuming imm is already checked as [1,32]. */
14407 unsigned int value
= inst
.operands
[2].imm
;
14408 inst
.instruction
|= (value
& 0x1c) << 10;
14409 inst
.instruction
|= (value
& 0x03) << 6;
14410 /* Change last 4 bits from 0xd to 0xf. */
14411 inst
.instruction
|= 0x2;
14415 /* MVE instruction encoder helpers. */
14416 #define M_MNEM_vabav 0xee800f01
14417 #define M_MNEM_vmladav 0xeef00e00
14418 #define M_MNEM_vmladava 0xeef00e20
14419 #define M_MNEM_vmladavx 0xeef01e00
14420 #define M_MNEM_vmladavax 0xeef01e20
14421 #define M_MNEM_vmlsdav 0xeef00e01
14422 #define M_MNEM_vmlsdava 0xeef00e21
14423 #define M_MNEM_vmlsdavx 0xeef01e01
14424 #define M_MNEM_vmlsdavax 0xeef01e21
14425 #define M_MNEM_vmullt 0xee011e00
14426 #define M_MNEM_vmullb 0xee010e00
14427 #define M_MNEM_vst20 0xfc801e00
14428 #define M_MNEM_vst21 0xfc801e20
14429 #define M_MNEM_vst40 0xfc801e01
14430 #define M_MNEM_vst41 0xfc801e21
14431 #define M_MNEM_vst42 0xfc801e41
14432 #define M_MNEM_vst43 0xfc801e61
14433 #define M_MNEM_vld20 0xfc901e00
14434 #define M_MNEM_vld21 0xfc901e20
14435 #define M_MNEM_vld40 0xfc901e01
14436 #define M_MNEM_vld41 0xfc901e21
14437 #define M_MNEM_vld42 0xfc901e41
14438 #define M_MNEM_vld43 0xfc901e61
14439 #define M_MNEM_vstrb 0xec000e00
14440 #define M_MNEM_vstrh 0xec000e10
14441 #define M_MNEM_vstrw 0xec000e40
14442 #define M_MNEM_vstrd 0xec000e50
14443 #define M_MNEM_vldrb 0xec100e00
14444 #define M_MNEM_vldrh 0xec100e10
14445 #define M_MNEM_vldrw 0xec100e40
14446 #define M_MNEM_vldrd 0xec100e50
14447 #define M_MNEM_vmovlt 0xeea01f40
14448 #define M_MNEM_vmovlb 0xeea00f40
14449 #define M_MNEM_vmovnt 0xfe311e81
14450 #define M_MNEM_vmovnb 0xfe310e81
14451 #define M_MNEM_vadc 0xee300f00
14452 #define M_MNEM_vadci 0xee301f00
14453 #define M_MNEM_vbrsr 0xfe011e60
14454 #define M_MNEM_vaddlv 0xee890f00
14455 #define M_MNEM_vaddlva 0xee890f20
14456 #define M_MNEM_vaddv 0xeef10f00
14457 #define M_MNEM_vaddva 0xeef10f20
14458 #define M_MNEM_vddup 0xee011f6e
14459 #define M_MNEM_vdwdup 0xee011f60
14460 #define M_MNEM_vidup 0xee010f6e
14461 #define M_MNEM_viwdup 0xee010f60
14462 #define M_MNEM_vmaxv 0xeee20f00
14463 #define M_MNEM_vmaxav 0xeee00f00
14464 #define M_MNEM_vminv 0xeee20f80
14465 #define M_MNEM_vminav 0xeee00f80
14466 #define M_MNEM_vmlaldav 0xee800e00
14467 #define M_MNEM_vmlaldava 0xee800e20
14468 #define M_MNEM_vmlaldavx 0xee801e00
14469 #define M_MNEM_vmlaldavax 0xee801e20
14470 #define M_MNEM_vmlsldav 0xee800e01
14471 #define M_MNEM_vmlsldava 0xee800e21
14472 #define M_MNEM_vmlsldavx 0xee801e01
14473 #define M_MNEM_vmlsldavax 0xee801e21
14474 #define M_MNEM_vrmlaldavhx 0xee801f00
14475 #define M_MNEM_vrmlaldavhax 0xee801f20
14476 #define M_MNEM_vrmlsldavh 0xfe800e01
14477 #define M_MNEM_vrmlsldavha 0xfe800e21
14478 #define M_MNEM_vrmlsldavhx 0xfe801e01
14479 #define M_MNEM_vrmlsldavhax 0xfe801e21
14480 #define M_MNEM_vqmovnt 0xee331e01
14481 #define M_MNEM_vqmovnb 0xee330e01
14482 #define M_MNEM_vqmovunt 0xee311e81
14483 #define M_MNEM_vqmovunb 0xee310e81
14484 #define M_MNEM_vshrnt 0xee801fc1
14485 #define M_MNEM_vshrnb 0xee800fc1
14486 #define M_MNEM_vrshrnt 0xfe801fc1
14487 #define M_MNEM_vqshrnt 0xee801f40
14488 #define M_MNEM_vqshrnb 0xee800f40
14489 #define M_MNEM_vqshrunt 0xee801fc0
14490 #define M_MNEM_vqshrunb 0xee800fc0
14491 #define M_MNEM_vrshrnb 0xfe800fc1
14492 #define M_MNEM_vqrshrnt 0xee801f41
14493 #define M_MNEM_vqrshrnb 0xee800f41
14494 #define M_MNEM_vqrshrunt 0xfe801fc0
14495 #define M_MNEM_vqrshrunb 0xfe800fc0
14497 /* Neon instruction encoder helpers. */
14499 /* Encodings for the different types for various Neon opcodes. */
14501 /* An "invalid" code for the following tables. */
14504 struct neon_tab_entry
14507 unsigned float_or_poly
;
14508 unsigned scalar_or_imm
;
14511 /* Map overloaded Neon opcodes to their respective encodings. */
14512 #define NEON_ENC_TAB \
14513 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14514 X(vabdl, 0x0800700, N_INV, N_INV), \
14515 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14516 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14517 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14518 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14519 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14520 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14521 X(vaddl, 0x0800000, N_INV, N_INV), \
14522 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14523 X(vsubl, 0x0800200, N_INV, N_INV), \
14524 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14525 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14526 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14527 /* Register variants of the following two instructions are encoded as
14528 vcge / vcgt with the operands reversed. */ \
14529 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14530 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14531 X(vfma, N_INV, 0x0000c10, N_INV), \
14532 X(vfms, N_INV, 0x0200c10, N_INV), \
14533 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14534 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14535 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14536 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14537 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14538 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14539 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14540 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14541 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14542 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14543 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14544 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14545 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14546 X(vshl, 0x0000400, N_INV, 0x0800510), \
14547 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14548 X(vand, 0x0000110, N_INV, 0x0800030), \
14549 X(vbic, 0x0100110, N_INV, 0x0800030), \
14550 X(veor, 0x1000110, N_INV, N_INV), \
14551 X(vorn, 0x0300110, N_INV, 0x0800010), \
14552 X(vorr, 0x0200110, N_INV, 0x0800010), \
14553 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14554 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14555 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14556 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14557 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14558 X(vst1, 0x0000000, 0x0800000, N_INV), \
14559 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14560 X(vst2, 0x0000100, 0x0800100, N_INV), \
14561 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14562 X(vst3, 0x0000200, 0x0800200, N_INV), \
14563 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14564 X(vst4, 0x0000300, 0x0800300, N_INV), \
14565 X(vmovn, 0x1b20200, N_INV, N_INV), \
14566 X(vtrn, 0x1b20080, N_INV, N_INV), \
14567 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14568 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14569 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14570 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14571 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14572 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14573 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14574 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14575 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14576 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14577 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14578 X(vseleq, 0xe000a00, N_INV, N_INV), \
14579 X(vselvs, 0xe100a00, N_INV, N_INV), \
14580 X(vselge, 0xe200a00, N_INV, N_INV), \
14581 X(vselgt, 0xe300a00, N_INV, N_INV), \
14582 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14583 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14584 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14585 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14586 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14587 X(aes, 0x3b00300, N_INV, N_INV), \
14588 X(sha3op, 0x2000c00, N_INV, N_INV), \
14589 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14590 X(sha2op, 0x3ba0380, N_INV, N_INV)
14594 #define X(OPC,I,F,S) N_MNEM_##OPC
14599 static const struct neon_tab_entry neon_enc_tab
[] =
14601 #define X(OPC,I,F,S) { (I), (F), (S) }
14606 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14607 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14608 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14609 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14610 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14611 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14612 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14613 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14614 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14615 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14616 #define NEON_ENC_SINGLE_(X) \
14617 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14618 #define NEON_ENC_DOUBLE_(X) \
14619 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14620 #define NEON_ENC_FPV8_(X) \
14621 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14623 #define NEON_ENCODE(type, inst) \
14626 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14627 inst.is_neon = 1; \
14631 #define check_neon_suffixes \
14634 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14636 as_bad (_("invalid neon suffix for non neon instruction")); \
14642 /* Define shapes for instruction operands. The following mnemonic characters
14643 are used in this table:
14645 F - VFP S<n> register
14646 D - Neon D<n> register
14647 Q - Neon Q<n> register
14651 L - D<n> register list
14653 This table is used to generate various data:
14654 - enumerations of the form NS_DDR to be used as arguments to
14656 - a table classifying shapes into single, double, quad, mixed.
14657 - a table used to drive neon_select_shape. */
14659 #define NEON_SHAPE_DEF \
14660 X(4, (R, R, Q, Q), QUAD), \
14661 X(4, (Q, R, R, I), QUAD), \
14662 X(4, (R, R, S, S), QUAD), \
14663 X(4, (S, S, R, R), QUAD), \
14664 X(3, (Q, R, I), QUAD), \
14665 X(3, (I, Q, Q), QUAD), \
14666 X(3, (I, Q, R), QUAD), \
14667 X(3, (R, Q, Q), QUAD), \
14668 X(3, (D, D, D), DOUBLE), \
14669 X(3, (Q, Q, Q), QUAD), \
14670 X(3, (D, D, I), DOUBLE), \
14671 X(3, (Q, Q, I), QUAD), \
14672 X(3, (D, D, S), DOUBLE), \
14673 X(3, (Q, Q, S), QUAD), \
14674 X(3, (Q, Q, R), QUAD), \
14675 X(3, (R, R, Q), QUAD), \
14676 X(2, (R, Q), QUAD), \
14677 X(2, (D, D), DOUBLE), \
14678 X(2, (Q, Q), QUAD), \
14679 X(2, (D, S), DOUBLE), \
14680 X(2, (Q, S), QUAD), \
14681 X(2, (D, R), DOUBLE), \
14682 X(2, (Q, R), QUAD), \
14683 X(2, (D, I), DOUBLE), \
14684 X(2, (Q, I), QUAD), \
14685 X(3, (D, L, D), DOUBLE), \
14686 X(2, (D, Q), MIXED), \
14687 X(2, (Q, D), MIXED), \
14688 X(3, (D, Q, I), MIXED), \
14689 X(3, (Q, D, I), MIXED), \
14690 X(3, (Q, D, D), MIXED), \
14691 X(3, (D, Q, Q), MIXED), \
14692 X(3, (Q, Q, D), MIXED), \
14693 X(3, (Q, D, S), MIXED), \
14694 X(3, (D, Q, S), MIXED), \
14695 X(4, (D, D, D, I), DOUBLE), \
14696 X(4, (Q, Q, Q, I), QUAD), \
14697 X(4, (D, D, S, I), DOUBLE), \
14698 X(4, (Q, Q, S, I), QUAD), \
14699 X(2, (F, F), SINGLE), \
14700 X(3, (F, F, F), SINGLE), \
14701 X(2, (F, I), SINGLE), \
14702 X(2, (F, D), MIXED), \
14703 X(2, (D, F), MIXED), \
14704 X(3, (F, F, I), MIXED), \
14705 X(4, (R, R, F, F), SINGLE), \
14706 X(4, (F, F, R, R), SINGLE), \
14707 X(3, (D, R, R), DOUBLE), \
14708 X(3, (R, R, D), DOUBLE), \
14709 X(2, (S, R), SINGLE), \
14710 X(2, (R, S), SINGLE), \
14711 X(2, (F, R), SINGLE), \
14712 X(2, (R, F), SINGLE), \
14713 /* Used for MVE tail predicated loop instructions. */\
14714 X(2, (R, R), QUAD), \
14715 /* Half float shape supported so far. */\
14716 X (2, (H, D), MIXED), \
14717 X (2, (D, H), MIXED), \
14718 X (2, (H, F), MIXED), \
14719 X (2, (F, H), MIXED), \
14720 X (2, (H, H), HALF), \
14721 X (2, (H, R), HALF), \
14722 X (2, (R, H), HALF), \
14723 X (2, (H, I), HALF), \
14724 X (3, (H, H, H), HALF), \
14725 X (3, (H, F, I), MIXED), \
14726 X (3, (F, H, I), MIXED), \
14727 X (3, (D, H, H), MIXED), \
14728 X (3, (D, H, S), MIXED)
14730 #define S2(A,B) NS_##A##B
14731 #define S3(A,B,C) NS_##A##B##C
14732 #define S4(A,B,C,D) NS_##A##B##C##D
14734 #define X(N, L, C) S##N L
14747 enum neon_shape_class
14756 #define X(N, L, C) SC_##C
14758 static enum neon_shape_class neon_shape_class
[] =
14777 /* Register widths of above. */
14778 static unsigned neon_shape_el_size
[] =
14790 struct neon_shape_info
14793 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14796 #define S2(A,B) { SE_##A, SE_##B }
14797 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14798 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14800 #define X(N, L, C) { N, S##N L }
14802 static struct neon_shape_info neon_shape_tab
[] =
14812 /* Bit masks used in type checking given instructions.
14813 'N_EQK' means the type must be the same as (or based on in some way) the key
14814 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14815 set, various other bits can be set as well in order to modify the meaning of
14816 the type constraint. */
14818 enum neon_type_mask
14842 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14843 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14844 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14845 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14846 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14847 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14848 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14849 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14850 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14851 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14852 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14854 N_MAX_NONSPECIAL
= N_P64
14857 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14859 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14860 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14861 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14862 #define N_S_32 (N_S8 | N_S16 | N_S32)
14863 #define N_F_16_32 (N_F16 | N_F32)
14864 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14865 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14866 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14867 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14868 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14869 #define N_F_MVE (N_F16 | N_F32)
14870 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14872 /* Pass this as the first type argument to neon_check_type to ignore types
14874 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14876 /* Select a "shape" for the current instruction (describing register types or
14877 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14878 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14879 function of operand parsing, so this function doesn't need to be called.
14880 Shapes should be listed in order of decreasing length. */
14882 static enum neon_shape
14883 neon_select_shape (enum neon_shape shape
, ...)
14886 enum neon_shape first_shape
= shape
;
14888 /* Fix missing optional operands. FIXME: we don't know at this point how
14889 many arguments we should have, so this makes the assumption that we have
14890 > 1. This is true of all current Neon opcodes, I think, but may not be
14891 true in the future. */
14892 if (!inst
.operands
[1].present
)
14893 inst
.operands
[1] = inst
.operands
[0];
14895 va_start (ap
, shape
);
14897 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14902 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14904 if (!inst
.operands
[j
].present
)
14910 switch (neon_shape_tab
[shape
].el
[j
])
14912 /* If a .f16, .16, .u16, .s16 type specifier is given over
14913 a VFP single precision register operand, it's essentially
14914 means only half of the register is used.
14916 If the type specifier is given after the mnemonics, the
14917 information is stored in inst.vectype. If the type specifier
14918 is given after register operand, the information is stored
14919 in inst.operands[].vectype.
14921 When there is only one type specifier, and all the register
14922 operands are the same type of hardware register, the type
14923 specifier applies to all register operands.
14925 If no type specifier is given, the shape is inferred from
14926 operand information.
14929 vadd.f16 s0, s1, s2: NS_HHH
14930 vabs.f16 s0, s1: NS_HH
14931 vmov.f16 s0, r1: NS_HR
14932 vmov.f16 r0, s1: NS_RH
14933 vcvt.f16 r0, s1: NS_RH
14934 vcvt.f16.s32 s2, s2, #29: NS_HFI
14935 vcvt.f16.s32 s2, s2: NS_HF
14938 if (!(inst
.operands
[j
].isreg
14939 && inst
.operands
[j
].isvec
14940 && inst
.operands
[j
].issingle
14941 && !inst
.operands
[j
].isquad
14942 && ((inst
.vectype
.elems
== 1
14943 && inst
.vectype
.el
[0].size
== 16)
14944 || (inst
.vectype
.elems
> 1
14945 && inst
.vectype
.el
[j
].size
== 16)
14946 || (inst
.vectype
.elems
== 0
14947 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14948 && inst
.operands
[j
].vectype
.size
== 16))))
14953 if (!(inst
.operands
[j
].isreg
14954 && inst
.operands
[j
].isvec
14955 && inst
.operands
[j
].issingle
14956 && !inst
.operands
[j
].isquad
14957 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14958 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14959 || (inst
.vectype
.elems
== 0
14960 && (inst
.operands
[j
].vectype
.size
== 32
14961 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14966 if (!(inst
.operands
[j
].isreg
14967 && inst
.operands
[j
].isvec
14968 && !inst
.operands
[j
].isquad
14969 && !inst
.operands
[j
].issingle
))
14974 if (!(inst
.operands
[j
].isreg
14975 && !inst
.operands
[j
].isvec
))
14980 if (!(inst
.operands
[j
].isreg
14981 && inst
.operands
[j
].isvec
14982 && inst
.operands
[j
].isquad
14983 && !inst
.operands
[j
].issingle
))
14988 if (!(!inst
.operands
[j
].isreg
14989 && !inst
.operands
[j
].isscalar
))
14994 if (!(!inst
.operands
[j
].isreg
14995 && inst
.operands
[j
].isscalar
))
15005 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15006 /* We've matched all the entries in the shape table, and we don't
15007 have any left over operands which have not been matched. */
15013 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15014 first_error (_("invalid instruction shape"));
15019 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15020 means the Q bit should be set). */
15023 neon_quad (enum neon_shape shape
)
15025 return neon_shape_class
[shape
] == SC_QUAD
;
15029 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15032 /* Allow modification to be made to types which are constrained to be
15033 based on the key element, based on bits set alongside N_EQK. */
15034 if ((typebits
& N_EQK
) != 0)
15036 if ((typebits
& N_HLF
) != 0)
15038 else if ((typebits
& N_DBL
) != 0)
15040 if ((typebits
& N_SGN
) != 0)
15041 *g_type
= NT_signed
;
15042 else if ((typebits
& N_UNS
) != 0)
15043 *g_type
= NT_unsigned
;
15044 else if ((typebits
& N_INT
) != 0)
15045 *g_type
= NT_integer
;
15046 else if ((typebits
& N_FLT
) != 0)
15047 *g_type
= NT_float
;
15048 else if ((typebits
& N_SIZ
) != 0)
15049 *g_type
= NT_untyped
;
15053 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15054 operand type, i.e. the single type specified in a Neon instruction when it
15055 is the only one given. */
15057 static struct neon_type_el
15058 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15060 struct neon_type_el dest
= *key
;
15062 gas_assert ((thisarg
& N_EQK
) != 0);
15064 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15069 /* Convert Neon type and size into compact bitmask representation. */
15071 static enum neon_type_mask
15072 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15079 case 8: return N_8
;
15080 case 16: return N_16
;
15081 case 32: return N_32
;
15082 case 64: return N_64
;
15090 case 8: return N_I8
;
15091 case 16: return N_I16
;
15092 case 32: return N_I32
;
15093 case 64: return N_I64
;
15101 case 16: return N_F16
;
15102 case 32: return N_F32
;
15103 case 64: return N_F64
;
15111 case 8: return N_P8
;
15112 case 16: return N_P16
;
15113 case 64: return N_P64
;
15121 case 8: return N_S8
;
15122 case 16: return N_S16
;
15123 case 32: return N_S32
;
15124 case 64: return N_S64
;
15132 case 8: return N_U8
;
15133 case 16: return N_U16
;
15134 case 32: return N_U32
;
15135 case 64: return N_U64
;
15146 /* Convert compact Neon bitmask type representation to a type and size. Only
15147 handles the case where a single bit is set in the mask. */
15150 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15151 enum neon_type_mask mask
)
15153 if ((mask
& N_EQK
) != 0)
15156 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15158 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15160 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15162 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15167 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15169 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15170 *type
= NT_unsigned
;
15171 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15172 *type
= NT_integer
;
15173 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15174 *type
= NT_untyped
;
15175 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15177 else if ((mask
& (N_F_ALL
)) != 0)
15185 /* Modify a bitmask of allowed types. This is only needed for type
15189 modify_types_allowed (unsigned allowed
, unsigned mods
)
15192 enum neon_el_type type
;
15198 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15200 if (el_type_of_type_chk (&type
, &size
,
15201 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15203 neon_modify_type_size (mods
, &type
, &size
);
15204 destmask
|= type_chk_of_el_type (type
, size
);
15211 /* Check type and return type classification.
15212 The manual states (paraphrase): If one datatype is given, it indicates the
15214 - the second operand, if there is one
15215 - the operand, if there is no second operand
15216 - the result, if there are no operands.
15217 This isn't quite good enough though, so we use a concept of a "key" datatype
15218 which is set on a per-instruction basis, which is the one which matters when
15219 only one data type is written.
15220 Note: this function has side-effects (e.g. filling in missing operands). All
15221 Neon instructions should call it before performing bit encoding. */
15223 static struct neon_type_el
15224 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15227 unsigned i
, pass
, key_el
= 0;
15228 unsigned types
[NEON_MAX_TYPE_ELS
];
15229 enum neon_el_type k_type
= NT_invtype
;
15230 unsigned k_size
= -1u;
15231 struct neon_type_el badtype
= {NT_invtype
, -1};
15232 unsigned key_allowed
= 0;
15234 /* Optional registers in Neon instructions are always (not) in operand 1.
15235 Fill in the missing operand here, if it was omitted. */
15236 if (els
> 1 && !inst
.operands
[1].present
)
15237 inst
.operands
[1] = inst
.operands
[0];
15239 /* Suck up all the varargs. */
15241 for (i
= 0; i
< els
; i
++)
15243 unsigned thisarg
= va_arg (ap
, unsigned);
15244 if (thisarg
== N_IGNORE_TYPE
)
15249 types
[i
] = thisarg
;
15250 if ((thisarg
& N_KEY
) != 0)
15255 if (inst
.vectype
.elems
> 0)
15256 for (i
= 0; i
< els
; i
++)
15257 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15259 first_error (_("types specified in both the mnemonic and operands"));
15263 /* Duplicate inst.vectype elements here as necessary.
15264 FIXME: No idea if this is exactly the same as the ARM assembler,
15265 particularly when an insn takes one register and one non-register
15267 if (inst
.vectype
.elems
== 1 && els
> 1)
15270 inst
.vectype
.elems
= els
;
15271 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15272 for (j
= 0; j
< els
; j
++)
15274 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15277 else if (inst
.vectype
.elems
== 0 && els
> 0)
15280 /* No types were given after the mnemonic, so look for types specified
15281 after each operand. We allow some flexibility here; as long as the
15282 "key" operand has a type, we can infer the others. */
15283 for (j
= 0; j
< els
; j
++)
15284 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15285 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15287 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15289 for (j
= 0; j
< els
; j
++)
15290 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15291 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15296 first_error (_("operand types can't be inferred"));
15300 else if (inst
.vectype
.elems
!= els
)
15302 first_error (_("type specifier has the wrong number of parts"));
15306 for (pass
= 0; pass
< 2; pass
++)
15308 for (i
= 0; i
< els
; i
++)
15310 unsigned thisarg
= types
[i
];
15311 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15312 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15313 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15314 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15316 /* Decay more-specific signed & unsigned types to sign-insensitive
15317 integer types if sign-specific variants are unavailable. */
15318 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15319 && (types_allowed
& N_SU_ALL
) == 0)
15320 g_type
= NT_integer
;
15322 /* If only untyped args are allowed, decay any more specific types to
15323 them. Some instructions only care about signs for some element
15324 sizes, so handle that properly. */
15325 if (((types_allowed
& N_UNT
) == 0)
15326 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15327 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15328 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15329 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15330 g_type
= NT_untyped
;
15334 if ((thisarg
& N_KEY
) != 0)
15338 key_allowed
= thisarg
& ~N_KEY
;
15340 /* Check architecture constraint on FP16 extension. */
15342 && k_type
== NT_float
15343 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15345 inst
.error
= _(BAD_FP16
);
15352 if ((thisarg
& N_VFP
) != 0)
15354 enum neon_shape_el regshape
;
15355 unsigned regwidth
, match
;
15357 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15360 first_error (_("invalid instruction shape"));
15363 regshape
= neon_shape_tab
[ns
].el
[i
];
15364 regwidth
= neon_shape_el_size
[regshape
];
15366 /* In VFP mode, operands must match register widths. If we
15367 have a key operand, use its width, else use the width of
15368 the current operand. */
15374 /* FP16 will use a single precision register. */
15375 if (regwidth
== 32 && match
== 16)
15377 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15381 inst
.error
= _(BAD_FP16
);
15386 if (regwidth
!= match
)
15388 first_error (_("operand size must match register width"));
15393 if ((thisarg
& N_EQK
) == 0)
15395 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15397 if ((given_type
& types_allowed
) == 0)
15399 first_error (BAD_SIMD_TYPE
);
15405 enum neon_el_type mod_k_type
= k_type
;
15406 unsigned mod_k_size
= k_size
;
15407 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15408 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15410 first_error (_("inconsistent types in Neon instruction"));
15418 return inst
.vectype
.el
[key_el
];
15421 /* Neon-style VFP instruction forwarding. */
15423 /* Thumb VFP instructions have 0xE in the condition field. */
15426 do_vfp_cond_or_thumb (void)
15431 inst
.instruction
|= 0xe0000000;
15433 inst
.instruction
|= inst
.cond
<< 28;
15436 /* Look up and encode a simple mnemonic, for use as a helper function for the
15437 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15438 etc. It is assumed that operand parsing has already been done, and that the
15439 operands are in the form expected by the given opcode (this isn't necessarily
15440 the same as the form in which they were parsed, hence some massaging must
15441 take place before this function is called).
15442 Checks current arch version against that in the looked-up opcode. */
15445 do_vfp_nsyn_opcode (const char *opname
)
15447 const struct asm_opcode
*opcode
;
15449 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15455 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15462 inst
.instruction
= opcode
->tvalue
;
15463 opcode
->tencode ();
15467 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15468 opcode
->aencode ();
15473 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15475 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15477 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15480 do_vfp_nsyn_opcode ("fadds");
15482 do_vfp_nsyn_opcode ("fsubs");
15484 /* ARMv8.2 fp16 instruction. */
15486 do_scalar_fp16_v82_encode ();
15491 do_vfp_nsyn_opcode ("faddd");
15493 do_vfp_nsyn_opcode ("fsubd");
15497 /* Check operand types to see if this is a VFP instruction, and if so call
15501 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15503 enum neon_shape rs
;
15504 struct neon_type_el et
;
15509 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15510 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15514 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15515 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15516 N_F_ALL
| N_KEY
| N_VFP
);
15523 if (et
.type
!= NT_invtype
)
15534 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15536 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15538 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15541 do_vfp_nsyn_opcode ("fmacs");
15543 do_vfp_nsyn_opcode ("fnmacs");
15545 /* ARMv8.2 fp16 instruction. */
15547 do_scalar_fp16_v82_encode ();
15552 do_vfp_nsyn_opcode ("fmacd");
15554 do_vfp_nsyn_opcode ("fnmacd");
15559 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15561 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15563 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15566 do_vfp_nsyn_opcode ("ffmas");
15568 do_vfp_nsyn_opcode ("ffnmas");
15570 /* ARMv8.2 fp16 instruction. */
15572 do_scalar_fp16_v82_encode ();
15577 do_vfp_nsyn_opcode ("ffmad");
15579 do_vfp_nsyn_opcode ("ffnmad");
15584 do_vfp_nsyn_mul (enum neon_shape rs
)
15586 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15588 do_vfp_nsyn_opcode ("fmuls");
15590 /* ARMv8.2 fp16 instruction. */
15592 do_scalar_fp16_v82_encode ();
15595 do_vfp_nsyn_opcode ("fmuld");
15599 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15601 int is_neg
= (inst
.instruction
& 0x80) != 0;
15602 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15604 if (rs
== NS_FF
|| rs
== NS_HH
)
15607 do_vfp_nsyn_opcode ("fnegs");
15609 do_vfp_nsyn_opcode ("fabss");
15611 /* ARMv8.2 fp16 instruction. */
15613 do_scalar_fp16_v82_encode ();
15618 do_vfp_nsyn_opcode ("fnegd");
15620 do_vfp_nsyn_opcode ("fabsd");
15624 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15625 insns belong to Neon, and are handled elsewhere. */
15628 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15630 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15634 do_vfp_nsyn_opcode ("fldmdbs");
15636 do_vfp_nsyn_opcode ("fldmias");
15641 do_vfp_nsyn_opcode ("fstmdbs");
15643 do_vfp_nsyn_opcode ("fstmias");
15648 do_vfp_nsyn_sqrt (void)
15650 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15651 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15653 if (rs
== NS_FF
|| rs
== NS_HH
)
15655 do_vfp_nsyn_opcode ("fsqrts");
15657 /* ARMv8.2 fp16 instruction. */
15659 do_scalar_fp16_v82_encode ();
15662 do_vfp_nsyn_opcode ("fsqrtd");
15666 do_vfp_nsyn_div (void)
15668 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15669 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15670 N_F_ALL
| N_KEY
| N_VFP
);
15672 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15674 do_vfp_nsyn_opcode ("fdivs");
15676 /* ARMv8.2 fp16 instruction. */
15678 do_scalar_fp16_v82_encode ();
15681 do_vfp_nsyn_opcode ("fdivd");
15685 do_vfp_nsyn_nmul (void)
15687 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15688 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15689 N_F_ALL
| N_KEY
| N_VFP
);
15691 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15693 NEON_ENCODE (SINGLE
, inst
);
15694 do_vfp_sp_dyadic ();
15696 /* ARMv8.2 fp16 instruction. */
15698 do_scalar_fp16_v82_encode ();
15702 NEON_ENCODE (DOUBLE
, inst
);
15703 do_vfp_dp_rd_rn_rm ();
15705 do_vfp_cond_or_thumb ();
15709 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15713 neon_logbits (unsigned x
)
15715 return ffs (x
) - 4;
15718 #define LOW4(R) ((R) & 0xf)
15719 #define HI1(R) (((R) >> 4) & 1)
15722 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15727 first_error (BAD_EL_TYPE
);
15730 switch (inst
.operands
[0].imm
)
15733 first_error (_("invalid condition"));
15755 /* only accept eq and ne. */
15756 if (inst
.operands
[0].imm
> 1)
15758 first_error (_("invalid condition"));
15761 return inst
.operands
[0].imm
;
15763 if (inst
.operands
[0].imm
== 0x2)
15765 else if (inst
.operands
[0].imm
== 0x8)
15769 first_error (_("invalid condition"));
15773 switch (inst
.operands
[0].imm
)
15776 first_error (_("invalid condition"));
15792 /* Should be unreachable. */
15799 /* We are dealing with a vector predicated block. */
15800 if (inst
.operands
[0].present
)
15802 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15803 struct neon_type_el et
15804 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15807 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15809 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15811 if (et
.type
== NT_invtype
)
15814 if (et
.type
== NT_float
)
15816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15818 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15819 inst
.instruction
|= (et
.size
== 16) << 28;
15820 inst
.instruction
|= 0x3 << 20;
15824 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15826 inst
.instruction
|= 1 << 28;
15827 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15830 if (inst
.operands
[2].isquad
)
15832 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15833 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15834 inst
.instruction
|= (fcond
& 0x2) >> 1;
15838 if (inst
.operands
[2].reg
== REG_SP
)
15839 as_tsktsk (MVE_BAD_SP
);
15840 inst
.instruction
|= 1 << 6;
15841 inst
.instruction
|= (fcond
& 0x2) << 4;
15842 inst
.instruction
|= inst
.operands
[2].reg
;
15844 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15845 inst
.instruction
|= (fcond
& 0x4) << 10;
15846 inst
.instruction
|= (fcond
& 0x1) << 7;
15849 set_pred_insn_type (VPT_INSN
);
15851 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15852 | ((inst
.instruction
& 0xe000) >> 13);
15853 now_pred
.warn_deprecated
= FALSE
;
15854 now_pred
.type
= VECTOR_PRED
;
15861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15862 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15863 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15864 if (!inst
.operands
[2].present
)
15865 first_error (_("MVE vector or ARM register expected"));
15866 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15868 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15869 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15870 && inst
.operands
[1].isquad
)
15872 inst
.instruction
= N_MNEM_vcmp
;
15876 if (inst
.cond
> COND_ALWAYS
)
15877 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15879 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15881 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15882 struct neon_type_el et
15883 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15886 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15887 && !inst
.operands
[2].iszr
, BAD_PC
);
15889 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15891 inst
.instruction
= 0xee010f00;
15892 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15893 inst
.instruction
|= (fcond
& 0x4) << 10;
15894 inst
.instruction
|= (fcond
& 0x1) << 7;
15895 if (et
.type
== NT_float
)
15897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15899 inst
.instruction
|= (et
.size
== 16) << 28;
15900 inst
.instruction
|= 0x3 << 20;
15904 inst
.instruction
|= 1 << 28;
15905 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15907 if (inst
.operands
[2].isquad
)
15909 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15910 inst
.instruction
|= (fcond
& 0x2) >> 1;
15911 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15915 if (inst
.operands
[2].reg
== REG_SP
)
15916 as_tsktsk (MVE_BAD_SP
);
15917 inst
.instruction
|= 1 << 6;
15918 inst
.instruction
|= (fcond
& 0x2) << 4;
15919 inst
.instruction
|= inst
.operands
[2].reg
;
15927 do_mve_vmaxa_vmina (void)
15929 if (inst
.cond
> COND_ALWAYS
)
15930 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15932 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15934 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15935 struct neon_type_el et
15936 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15939 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15940 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15941 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15947 do_mve_vfmas (void)
15949 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15950 struct neon_type_el et
15951 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15953 if (inst
.cond
> COND_ALWAYS
)
15954 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15956 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15958 if (inst
.operands
[2].reg
== REG_SP
)
15959 as_tsktsk (MVE_BAD_SP
);
15960 else if (inst
.operands
[2].reg
== REG_PC
)
15961 as_tsktsk (MVE_BAD_PC
);
15963 inst
.instruction
|= (et
.size
== 16) << 28;
15964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15965 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15966 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15967 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15968 inst
.instruction
|= inst
.operands
[2].reg
;
15973 do_mve_viddup (void)
15975 if (inst
.cond
> COND_ALWAYS
)
15976 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15978 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15980 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15981 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15982 _("immediate must be either 1, 2, 4 or 8"));
15984 enum neon_shape rs
;
15985 struct neon_type_el et
;
15987 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15989 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15990 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15995 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15996 if (inst
.operands
[2].reg
== REG_SP
)
15997 as_tsktsk (MVE_BAD_SP
);
15998 else if (inst
.operands
[2].reg
== REG_PC
)
15999 first_error (BAD_PC
);
16001 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16002 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16003 Rm
= inst
.operands
[2].reg
>> 1;
16005 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16006 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16007 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16008 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16009 inst
.instruction
|= (imm
> 2) << 7;
16010 inst
.instruction
|= Rm
<< 1;
16011 inst
.instruction
|= (imm
== 2 || imm
== 8);
16016 do_mve_vmlas (void)
16018 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16019 struct neon_type_el et
16020 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16022 if (inst
.operands
[2].reg
== REG_PC
)
16023 as_tsktsk (MVE_BAD_PC
);
16024 else if (inst
.operands
[2].reg
== REG_SP
)
16025 as_tsktsk (MVE_BAD_SP
);
16027 if (inst
.cond
> COND_ALWAYS
)
16028 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16030 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16032 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16034 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16035 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16036 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16037 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16038 inst
.instruction
|= inst
.operands
[2].reg
;
16043 do_mve_vshll (void)
16045 struct neon_type_el et
16046 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16048 if (inst
.cond
> COND_ALWAYS
)
16049 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16051 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16053 int imm
= inst
.operands
[2].imm
;
16054 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16055 _("immediate value out of range"));
16057 if ((unsigned)imm
== et
.size
)
16059 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16060 inst
.instruction
|= 0x110001;
16064 inst
.instruction
|= (et
.size
+ imm
) << 16;
16065 inst
.instruction
|= 0x800140;
16068 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16069 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16070 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16071 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16072 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16077 do_mve_vshlc (void)
16079 if (inst
.cond
> COND_ALWAYS
)
16080 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16082 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16084 if (inst
.operands
[1].reg
== REG_PC
)
16085 as_tsktsk (MVE_BAD_PC
);
16086 else if (inst
.operands
[1].reg
== REG_SP
)
16087 as_tsktsk (MVE_BAD_SP
);
16089 int imm
= inst
.operands
[2].imm
;
16090 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16092 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16093 inst
.instruction
|= (imm
& 0x1f) << 16;
16094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16095 inst
.instruction
|= inst
.operands
[1].reg
;
16100 do_mve_vshrn (void)
16103 switch (inst
.instruction
)
16105 case M_MNEM_vshrnt
:
16106 case M_MNEM_vshrnb
:
16107 case M_MNEM_vrshrnt
:
16108 case M_MNEM_vrshrnb
:
16109 types
= N_I16
| N_I32
;
16111 case M_MNEM_vqshrnt
:
16112 case M_MNEM_vqshrnb
:
16113 case M_MNEM_vqrshrnt
:
16114 case M_MNEM_vqrshrnb
:
16115 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16117 case M_MNEM_vqshrunt
:
16118 case M_MNEM_vqshrunb
:
16119 case M_MNEM_vqrshrunt
:
16120 case M_MNEM_vqrshrunb
:
16121 types
= N_S16
| N_S32
;
16127 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16129 if (inst
.cond
> COND_ALWAYS
)
16130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16134 unsigned Qd
= inst
.operands
[0].reg
;
16135 unsigned Qm
= inst
.operands
[1].reg
;
16136 unsigned imm
= inst
.operands
[2].imm
;
16137 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16139 ? _("immediate operand expected in the range [1,8]")
16140 : _("immediate operand expected in the range [1,16]"));
16142 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16143 inst
.instruction
|= HI1 (Qd
) << 22;
16144 inst
.instruction
|= (et
.size
- imm
) << 16;
16145 inst
.instruction
|= LOW4 (Qd
) << 12;
16146 inst
.instruction
|= HI1 (Qm
) << 5;
16147 inst
.instruction
|= LOW4 (Qm
);
16152 do_mve_vqmovn (void)
16154 struct neon_type_el et
;
16155 if (inst
.instruction
== M_MNEM_vqmovnt
16156 || inst
.instruction
== M_MNEM_vqmovnb
)
16157 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16158 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16160 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16162 if (inst
.cond
> COND_ALWAYS
)
16163 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16165 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16167 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16168 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16169 inst
.instruction
|= (et
.size
== 32) << 18;
16170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16171 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16172 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16177 do_mve_vpsel (void)
16179 neon_select_shape (NS_QQQ
, NS_NULL
);
16181 if (inst
.cond
> COND_ALWAYS
)
16182 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16184 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16187 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16190 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16191 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16196 do_mve_vpnot (void)
16198 if (inst
.cond
> COND_ALWAYS
)
16199 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16201 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16205 do_mve_vmaxnma_vminnma (void)
16207 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16208 struct neon_type_el et
16209 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16211 if (inst
.cond
> COND_ALWAYS
)
16212 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16214 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16216 inst
.instruction
|= (et
.size
== 16) << 28;
16217 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16218 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16219 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16220 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16225 do_mve_vcmul (void)
16227 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16228 struct neon_type_el et
16229 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16231 if (inst
.cond
> COND_ALWAYS
)
16232 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16234 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16236 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16237 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16238 _("immediate out of range"));
16240 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16241 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16242 as_tsktsk (BAD_MVE_SRCDEST
);
16244 inst
.instruction
|= (et
.size
== 32) << 28;
16245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16248 inst
.instruction
|= (rot
> 90) << 12;
16249 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16250 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16251 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16252 inst
.instruction
|= (rot
== 90 || rot
== 270);
16256 /* To handle the Low Overhead Loop instructions
16257 in Armv8.1-M Mainline and MVE. */
16261 unsigned long insn
= inst
.instruction
;
16263 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16265 if (insn
== T_MNEM_lctp
)
16268 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16270 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16272 struct neon_type_el et
16273 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16274 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16281 constraint (!inst
.operands
[0].present
,
16283 /* fall through. */
16286 if (!inst
.operands
[0].present
)
16287 inst
.instruction
|= 1 << 21;
16289 v8_1_loop_reloc (TRUE
);
16294 v8_1_loop_reloc (FALSE
);
16295 /* fall through. */
16298 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16300 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16301 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16302 else if (inst
.operands
[1].reg
== REG_PC
)
16303 as_tsktsk (MVE_BAD_PC
);
16304 if (inst
.operands
[1].reg
== REG_SP
)
16305 as_tsktsk (MVE_BAD_SP
);
16307 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16317 do_vfp_nsyn_cmp (void)
16319 enum neon_shape rs
;
16320 if (!inst
.operands
[0].isreg
)
16327 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16328 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16332 if (inst
.operands
[1].isreg
)
16334 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16335 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16337 if (rs
== NS_FF
|| rs
== NS_HH
)
16339 NEON_ENCODE (SINGLE
, inst
);
16340 do_vfp_sp_monadic ();
16344 NEON_ENCODE (DOUBLE
, inst
);
16345 do_vfp_dp_rd_rm ();
16350 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16351 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16353 switch (inst
.instruction
& 0x0fffffff)
16356 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16359 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16365 if (rs
== NS_FI
|| rs
== NS_HI
)
16367 NEON_ENCODE (SINGLE
, inst
);
16368 do_vfp_sp_compare_z ();
16372 NEON_ENCODE (DOUBLE
, inst
);
16376 do_vfp_cond_or_thumb ();
16378 /* ARMv8.2 fp16 instruction. */
16379 if (rs
== NS_HI
|| rs
== NS_HH
)
16380 do_scalar_fp16_v82_encode ();
16384 nsyn_insert_sp (void)
16386 inst
.operands
[1] = inst
.operands
[0];
16387 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16388 inst
.operands
[0].reg
= REG_SP
;
16389 inst
.operands
[0].isreg
= 1;
16390 inst
.operands
[0].writeback
= 1;
16391 inst
.operands
[0].present
= 1;
16395 do_vfp_nsyn_push (void)
16399 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16400 _("register list must contain at least 1 and at most 16 "
16403 if (inst
.operands
[1].issingle
)
16404 do_vfp_nsyn_opcode ("fstmdbs");
16406 do_vfp_nsyn_opcode ("fstmdbd");
16410 do_vfp_nsyn_pop (void)
16414 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16415 _("register list must contain at least 1 and at most 16 "
16418 if (inst
.operands
[1].issingle
)
16419 do_vfp_nsyn_opcode ("fldmias");
16421 do_vfp_nsyn_opcode ("fldmiad");
16424 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16425 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16428 neon_dp_fixup (struct arm_it
* insn
)
16430 unsigned int i
= insn
->instruction
;
16435 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16446 insn
->instruction
= i
;
16450 mve_encode_qqr (int size
, int U
, int fp
)
16452 if (inst
.operands
[2].reg
== REG_SP
)
16453 as_tsktsk (MVE_BAD_SP
);
16454 else if (inst
.operands
[2].reg
== REG_PC
)
16455 as_tsktsk (MVE_BAD_PC
);
16460 if (((unsigned)inst
.instruction
) == 0xd00)
16461 inst
.instruction
= 0xee300f40;
16463 else if (((unsigned)inst
.instruction
) == 0x200d00)
16464 inst
.instruction
= 0xee301f40;
16466 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16467 inst
.instruction
= 0xee310e60;
16469 /* Setting size which is 1 for F16 and 0 for F32. */
16470 inst
.instruction
|= (size
== 16) << 28;
16475 if (((unsigned)inst
.instruction
) == 0x800)
16476 inst
.instruction
= 0xee010f40;
16478 else if (((unsigned)inst
.instruction
) == 0x1000800)
16479 inst
.instruction
= 0xee011f40;
16481 else if (((unsigned)inst
.instruction
) == 0)
16482 inst
.instruction
= 0xee000f40;
16484 else if (((unsigned)inst
.instruction
) == 0x200)
16485 inst
.instruction
= 0xee001f40;
16487 else if (((unsigned)inst
.instruction
) == 0x900)
16488 inst
.instruction
= 0xee010e40;
16490 else if (((unsigned)inst
.instruction
) == 0x910)
16491 inst
.instruction
= 0xee011e60;
16493 else if (((unsigned)inst
.instruction
) == 0x10)
16494 inst
.instruction
= 0xee000f60;
16496 else if (((unsigned)inst
.instruction
) == 0x210)
16497 inst
.instruction
= 0xee001f60;
16499 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16500 inst
.instruction
= 0xee000e40;
16502 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16503 inst
.instruction
= 0xee010e60;
16505 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16506 inst
.instruction
= 0xfe010e60;
16509 inst
.instruction
|= U
<< 28;
16511 /* Setting bits for size. */
16512 inst
.instruction
|= neon_logbits (size
) << 20;
16514 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16515 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16516 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16517 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16518 inst
.instruction
|= inst
.operands
[2].reg
;
16523 mve_encode_rqq (unsigned bit28
, unsigned size
)
16525 inst
.instruction
|= bit28
<< 28;
16526 inst
.instruction
|= neon_logbits (size
) << 20;
16527 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16528 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16529 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16530 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16531 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16536 mve_encode_qqq (int ubit
, int size
)
16539 inst
.instruction
|= (ubit
!= 0) << 28;
16540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16541 inst
.instruction
|= neon_logbits (size
) << 20;
16542 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16543 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16544 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16545 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16546 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16552 mve_encode_rq (unsigned bit28
, unsigned size
)
16554 inst
.instruction
|= bit28
<< 28;
16555 inst
.instruction
|= neon_logbits (size
) << 18;
16556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16557 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16562 mve_encode_rrqq (unsigned U
, unsigned size
)
16564 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16566 inst
.instruction
|= U
<< 28;
16567 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16568 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16569 inst
.instruction
|= (size
== 32) << 16;
16570 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16571 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16572 inst
.instruction
|= inst
.operands
[3].reg
;
16576 /* Encode insns with bit pattern:
16578 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16579 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16581 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16582 different meaning for some instruction. */
16585 neon_three_same (int isquad
, int ubit
, int size
)
16587 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16588 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16589 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16590 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16591 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16592 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16593 inst
.instruction
|= (isquad
!= 0) << 6;
16594 inst
.instruction
|= (ubit
!= 0) << 24;
16596 inst
.instruction
|= neon_logbits (size
) << 20;
16598 neon_dp_fixup (&inst
);
16601 /* Encode instructions of the form:
16603 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16604 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16606 Don't write size if SIZE == -1. */
16609 neon_two_same (int qbit
, int ubit
, int size
)
16611 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16612 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16613 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16614 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16615 inst
.instruction
|= (qbit
!= 0) << 6;
16616 inst
.instruction
|= (ubit
!= 0) << 24;
16619 inst
.instruction
|= neon_logbits (size
) << 18;
16621 neon_dp_fixup (&inst
);
16624 enum vfp_or_neon_is_neon_bits
16627 NEON_CHECK_ARCH
= 2,
16628 NEON_CHECK_ARCH8
= 4
16631 /* Call this function if an instruction which may have belonged to the VFP or
16632 Neon instruction sets, but turned out to be a Neon instruction (due to the
16633 operand types involved, etc.). We have to check and/or fix-up a couple of
16636 - Make sure the user hasn't attempted to make a Neon instruction
16638 - Alter the value in the condition code field if necessary.
16639 - Make sure that the arch supports Neon instructions.
16641 Which of these operations take place depends on bits from enum
16642 vfp_or_neon_is_neon_bits.
16644 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16645 current instruction's condition is COND_ALWAYS, the condition field is
16646 changed to inst.uncond_value. This is necessary because instructions shared
16647 between VFP and Neon may be conditional for the VFP variants only, and the
16648 unconditional Neon version must have, e.g., 0xF in the condition field. */
16651 vfp_or_neon_is_neon (unsigned check
)
16653 /* Conditions are always legal in Thumb mode (IT blocks). */
16654 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16656 if (inst
.cond
!= COND_ALWAYS
)
16658 first_error (_(BAD_COND
));
16661 if (inst
.uncond_value
!= -1)
16662 inst
.instruction
|= inst
.uncond_value
<< 28;
16666 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16667 || ((check
& NEON_CHECK_ARCH8
)
16668 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16670 first_error (_(BAD_FPU
));
16678 /* Return TRUE if the SIMD instruction is available for the current
16679 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16680 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16681 vfp_or_neon_is_neon for the NEON specific checks. */
16684 check_simd_pred_availability (int fp
, unsigned check
)
16686 if (inst
.cond
> COND_ALWAYS
)
16688 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16690 inst
.error
= BAD_FPU
;
16693 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16695 else if (inst
.cond
< COND_ALWAYS
)
16697 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16698 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16699 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16704 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16705 && vfp_or_neon_is_neon (check
) == FAIL
)
16708 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16709 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16714 /* Neon instruction encoders, in approximate order of appearance. */
16717 do_neon_dyadic_i_su (void)
16719 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16722 enum neon_shape rs
;
16723 struct neon_type_el et
;
16724 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16725 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16727 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16729 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16733 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16735 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16739 do_neon_dyadic_i64_su (void)
16741 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16743 enum neon_shape rs
;
16744 struct neon_type_el et
;
16745 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16747 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16748 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16752 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16753 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16756 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16758 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16762 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16765 unsigned size
= et
.size
>> 3;
16766 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16767 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16768 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16769 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16770 inst
.instruction
|= (isquad
!= 0) << 6;
16771 inst
.instruction
|= immbits
<< 16;
16772 inst
.instruction
|= (size
>> 3) << 7;
16773 inst
.instruction
|= (size
& 0x7) << 19;
16775 inst
.instruction
|= (uval
!= 0) << 24;
16777 neon_dp_fixup (&inst
);
16783 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16786 if (!inst
.operands
[2].isreg
)
16788 enum neon_shape rs
;
16789 struct neon_type_el et
;
16790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16792 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16793 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16797 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16798 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16800 int imm
= inst
.operands
[2].imm
;
16802 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16803 _("immediate out of range for shift"));
16804 NEON_ENCODE (IMMED
, inst
);
16805 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16809 enum neon_shape rs
;
16810 struct neon_type_el et
;
16811 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16813 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16814 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16818 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16819 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16825 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16826 _("invalid instruction shape"));
16827 if (inst
.operands
[2].reg
== REG_SP
)
16828 as_tsktsk (MVE_BAD_SP
);
16829 else if (inst
.operands
[2].reg
== REG_PC
)
16830 as_tsktsk (MVE_BAD_PC
);
16832 inst
.instruction
= 0xee311e60;
16833 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16834 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16835 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16836 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16837 inst
.instruction
|= inst
.operands
[2].reg
;
16844 /* VSHL/VQSHL 3-register variants have syntax such as:
16846 whereas other 3-register operations encoded by neon_three_same have
16849 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16850 operands[2].reg here. */
16851 tmp
= inst
.operands
[2].reg
;
16852 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16853 inst
.operands
[1].reg
= tmp
;
16854 NEON_ENCODE (INTEGER
, inst
);
16855 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16861 do_neon_qshl (void)
16863 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16866 if (!inst
.operands
[2].isreg
)
16868 enum neon_shape rs
;
16869 struct neon_type_el et
;
16870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16872 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16873 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16877 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16878 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16880 int imm
= inst
.operands
[2].imm
;
16882 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16883 _("immediate out of range for shift"));
16884 NEON_ENCODE (IMMED
, inst
);
16885 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16889 enum neon_shape rs
;
16890 struct neon_type_el et
;
16892 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16894 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16895 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16899 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16900 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16905 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16906 _("invalid instruction shape"));
16907 if (inst
.operands
[2].reg
== REG_SP
)
16908 as_tsktsk (MVE_BAD_SP
);
16909 else if (inst
.operands
[2].reg
== REG_PC
)
16910 as_tsktsk (MVE_BAD_PC
);
16912 inst
.instruction
= 0xee311ee0;
16913 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16914 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16915 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16916 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16917 inst
.instruction
|= inst
.operands
[2].reg
;
16924 /* See note in do_neon_shl. */
16925 tmp
= inst
.operands
[2].reg
;
16926 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16927 inst
.operands
[1].reg
= tmp
;
16928 NEON_ENCODE (INTEGER
, inst
);
16929 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16935 do_neon_rshl (void)
16937 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16940 enum neon_shape rs
;
16941 struct neon_type_el et
;
16942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16944 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16945 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16949 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16950 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16957 if (inst
.operands
[2].reg
== REG_PC
)
16958 as_tsktsk (MVE_BAD_PC
);
16959 else if (inst
.operands
[2].reg
== REG_SP
)
16960 as_tsktsk (MVE_BAD_SP
);
16962 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16963 _("invalid instruction shape"));
16965 if (inst
.instruction
== 0x0000510)
16966 /* We are dealing with vqrshl. */
16967 inst
.instruction
= 0xee331ee0;
16969 /* We are dealing with vrshl. */
16970 inst
.instruction
= 0xee331e60;
16972 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16973 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16974 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16976 inst
.instruction
|= inst
.operands
[2].reg
;
16981 tmp
= inst
.operands
[2].reg
;
16982 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16983 inst
.operands
[1].reg
= tmp
;
16984 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16989 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16991 /* Handle .I8 pseudo-instructions. */
16994 /* Unfortunately, this will make everything apart from zero out-of-range.
16995 FIXME is this the intended semantics? There doesn't seem much point in
16996 accepting .I8 if so. */
16997 immediate
|= immediate
<< 8;
17003 if (immediate
== (immediate
& 0x000000ff))
17005 *immbits
= immediate
;
17008 else if (immediate
== (immediate
& 0x0000ff00))
17010 *immbits
= immediate
>> 8;
17013 else if (immediate
== (immediate
& 0x00ff0000))
17015 *immbits
= immediate
>> 16;
17018 else if (immediate
== (immediate
& 0xff000000))
17020 *immbits
= immediate
>> 24;
17023 if ((immediate
& 0xffff) != (immediate
>> 16))
17024 goto bad_immediate
;
17025 immediate
&= 0xffff;
17028 if (immediate
== (immediate
& 0x000000ff))
17030 *immbits
= immediate
;
17033 else if (immediate
== (immediate
& 0x0000ff00))
17035 *immbits
= immediate
>> 8;
17040 first_error (_("immediate value out of range"));
17045 do_neon_logic (void)
17047 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17049 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17051 && !check_simd_pred_availability (FALSE
,
17052 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17054 else if (rs
!= NS_QQQ
17055 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17056 first_error (BAD_FPU
);
17058 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17059 /* U bit and size field were set as part of the bitmask. */
17060 NEON_ENCODE (INTEGER
, inst
);
17061 neon_three_same (neon_quad (rs
), 0, -1);
17065 const int three_ops_form
= (inst
.operands
[2].present
17066 && !inst
.operands
[2].isreg
);
17067 const int immoperand
= (three_ops_form
? 2 : 1);
17068 enum neon_shape rs
= (three_ops_form
17069 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17070 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17071 /* Because neon_select_shape makes the second operand a copy of the first
17072 if the second operand is not present. */
17074 && !check_simd_pred_availability (FALSE
,
17075 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17077 else if (rs
!= NS_QQI
17078 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17079 first_error (BAD_FPU
);
17081 struct neon_type_el et
;
17082 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17083 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17085 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17088 if (et
.type
== NT_invtype
)
17090 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17095 if (three_ops_form
)
17096 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17097 _("first and second operands shall be the same register"));
17099 NEON_ENCODE (IMMED
, inst
);
17101 immbits
= inst
.operands
[immoperand
].imm
;
17104 /* .i64 is a pseudo-op, so the immediate must be a repeating
17106 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17107 inst
.operands
[immoperand
].reg
: 0))
17109 /* Set immbits to an invalid constant. */
17110 immbits
= 0xdeadbeef;
17117 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17121 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17125 /* Pseudo-instruction for VBIC. */
17126 neon_invert_size (&immbits
, 0, et
.size
);
17127 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17131 /* Pseudo-instruction for VORR. */
17132 neon_invert_size (&immbits
, 0, et
.size
);
17133 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17143 inst
.instruction
|= neon_quad (rs
) << 6;
17144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17145 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17146 inst
.instruction
|= cmode
<< 8;
17147 neon_write_immbits (immbits
);
17149 neon_dp_fixup (&inst
);
17154 do_neon_bitfield (void)
17156 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17157 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17158 neon_three_same (neon_quad (rs
), 0, -1);
17162 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17165 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17166 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17168 if (et
.type
== NT_float
)
17170 NEON_ENCODE (FLOAT
, inst
);
17172 mve_encode_qqr (et
.size
, 0, 1);
17174 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17178 NEON_ENCODE (INTEGER
, inst
);
17180 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17182 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17188 do_neon_dyadic_if_su_d (void)
17190 /* This version only allow D registers, but that constraint is enforced during
17191 operand parsing so we don't need to do anything extra here. */
17192 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17196 do_neon_dyadic_if_i_d (void)
17198 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17199 affected if we specify unsigned args. */
17200 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17204 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17206 constraint (size
< 32, BAD_ADDR_MODE
);
17207 constraint (size
!= elsize
, BAD_EL_TYPE
);
17208 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17209 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17210 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17211 _("destination register and offset register may not be the"
17214 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17221 constraint ((imm
% (size
/ 8) != 0)
17222 || imm
> (0x7f << neon_logbits (size
)),
17223 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17224 " range of +/-[0,508]")
17225 : _("immediate must be a multiple of 8 in the"
17226 " range of +/-[0,1016]"));
17227 inst
.instruction
|= 0x11 << 24;
17228 inst
.instruction
|= add
<< 23;
17229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17230 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17233 inst
.instruction
|= 1 << 12;
17234 inst
.instruction
|= (size
== 64) << 8;
17235 inst
.instruction
&= 0xffffff00;
17236 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17237 inst
.instruction
|= imm
>> neon_logbits (size
);
17241 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17243 unsigned os
= inst
.operands
[1].imm
>> 5;
17244 constraint (os
!= 0 && size
== 8,
17245 _("can not shift offsets when accessing less than half-word"));
17246 constraint (os
&& os
!= neon_logbits (size
),
17247 _("shift immediate must be 1, 2 or 3 for half-word, word"
17248 " or double-word accesses respectively"));
17249 if (inst
.operands
[1].reg
== REG_PC
)
17250 as_tsktsk (MVE_BAD_PC
);
17255 constraint (elsize
>= 64, BAD_EL_TYPE
);
17258 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17262 constraint (elsize
!= size
, BAD_EL_TYPE
);
17267 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17271 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17272 _("destination register and offset register may not be"
17274 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17276 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17277 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17278 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17282 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17285 inst
.instruction
|= 1 << 23;
17286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17288 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17289 inst
.instruction
|= neon_logbits (elsize
) << 7;
17290 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17291 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17292 inst
.instruction
|= !!os
;
17296 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17298 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17300 constraint (size
>= 64, BAD_ADDR_MODE
);
17304 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17307 constraint (elsize
!= size
, BAD_EL_TYPE
);
17314 constraint (elsize
!= size
&& type
!= NT_unsigned
17315 && type
!= NT_signed
, BAD_EL_TYPE
);
17319 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17322 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17330 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17335 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17338 constraint (1, _("immediate must be a multiple of 2 in the"
17339 " range of +/-[0,254]"));
17342 constraint (1, _("immediate must be a multiple of 4 in the"
17343 " range of +/-[0,508]"));
17348 if (size
!= elsize
)
17350 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17351 constraint (inst
.operands
[0].reg
> 14,
17352 _("MVE vector register in the range [Q0..Q7] expected"));
17353 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17354 inst
.instruction
|= (size
== 16) << 19;
17355 inst
.instruction
|= neon_logbits (elsize
) << 7;
17359 if (inst
.operands
[1].reg
== REG_PC
)
17360 as_tsktsk (MVE_BAD_PC
);
17361 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17362 as_tsktsk (MVE_BAD_SP
);
17363 inst
.instruction
|= 1 << 12;
17364 inst
.instruction
|= neon_logbits (size
) << 7;
17366 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17367 inst
.instruction
|= add
<< 23;
17368 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17369 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17370 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17371 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17372 inst
.instruction
&= 0xffffff80;
17373 inst
.instruction
|= imm
>> neon_logbits (size
);
17378 do_mve_vstr_vldr (void)
17383 if (inst
.cond
> COND_ALWAYS
)
17384 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17386 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17388 switch (inst
.instruction
)
17395 /* fall through. */
17401 /* fall through. */
17407 /* fall through. */
17413 /* fall through. */
17418 unsigned elsize
= inst
.vectype
.el
[0].size
;
17420 if (inst
.operands
[1].isquad
)
17422 /* We are dealing with [Q, imm]{!} cases. */
17423 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17427 if (inst
.operands
[1].immisreg
== 2)
17429 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17430 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17432 else if (!inst
.operands
[1].immisreg
)
17434 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17435 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17438 constraint (1, BAD_ADDR_MODE
);
17445 do_mve_vst_vld (void)
17447 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17450 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17451 || inst
.relocs
[0].exp
.X_add_number
!= 0
17452 || inst
.operands
[1].immisreg
!= 0,
17454 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17455 if (inst
.operands
[1].reg
== REG_PC
)
17456 as_tsktsk (MVE_BAD_PC
);
17457 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17458 as_tsktsk (MVE_BAD_SP
);
17461 /* These instructions are one of the "exceptions" mentioned in
17462 handle_pred_state. They are MVE instructions that are not VPT compatible
17463 and do not accept a VPT code, thus appending such a code is a syntax
17465 if (inst
.cond
> COND_ALWAYS
)
17466 first_error (BAD_SYNTAX
);
17467 /* If we append a scalar condition code we can set this to
17468 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17469 else if (inst
.cond
< COND_ALWAYS
)
17470 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17472 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17475 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17478 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17483 do_mve_vaddlv (void)
17485 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17486 struct neon_type_el et
17487 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17489 if (et
.type
== NT_invtype
)
17490 first_error (BAD_EL_TYPE
);
17492 if (inst
.cond
> COND_ALWAYS
)
17493 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17495 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17497 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17499 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17500 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17502 inst
.instruction
|= inst
.operands
[2].reg
;
17507 do_neon_dyadic_if_su (void)
17509 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17510 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17513 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17514 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17515 && et
.type
== NT_float
17516 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17518 if (!check_simd_pred_availability (et
.type
== NT_float
,
17519 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17522 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17526 do_neon_addsub_if_i (void)
17528 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17529 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17532 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17533 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17534 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17536 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17537 /* If we are parsing Q registers and the element types match MVE, which NEON
17538 also supports, then we must check whether this is an instruction that can
17539 be used by both MVE/NEON. This distinction can be made based on whether
17540 they are predicated or not. */
17541 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17543 if (!check_simd_pred_availability (et
.type
== NT_float
,
17544 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17549 /* If they are either in a D register or are using an unsupported. */
17551 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17555 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17556 affected if we specify unsigned args. */
17557 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17560 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17562 V<op> A,B (A is operand 0, B is operand 2)
17567 so handle that case specially. */
17570 neon_exchange_operands (void)
17572 if (inst
.operands
[1].present
)
17574 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17576 /* Swap operands[1] and operands[2]. */
17577 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17578 inst
.operands
[1] = inst
.operands
[2];
17579 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17584 inst
.operands
[1] = inst
.operands
[2];
17585 inst
.operands
[2] = inst
.operands
[0];
17590 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17592 if (inst
.operands
[2].isreg
)
17595 neon_exchange_operands ();
17596 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17600 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17601 struct neon_type_el et
= neon_check_type (2, rs
,
17602 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17604 NEON_ENCODE (IMMED
, inst
);
17605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17609 inst
.instruction
|= neon_quad (rs
) << 6;
17610 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17611 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17613 neon_dp_fixup (&inst
);
17620 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17624 do_neon_cmp_inv (void)
17626 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17632 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17635 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17636 scalars, which are encoded in 5 bits, M : Rm.
17637 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17638 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17641 Dot Product instructions are similar to multiply instructions except elsize
17642 should always be 32.
17644 This function translates SCALAR, which is GAS's internal encoding of indexed
17645 scalar register, to raw encoding. There is also register and index range
17646 check based on ELSIZE. */
17649 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17651 unsigned regno
= NEON_SCALAR_REG (scalar
);
17652 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17657 if (regno
> 7 || elno
> 3)
17659 return regno
| (elno
<< 3);
17662 if (regno
> 15 || elno
> 1)
17664 return regno
| (elno
<< 4);
17668 first_error (_("scalar out of range for multiply instruction"));
17674 /* Encode multiply / multiply-accumulate scalar instructions. */
17677 neon_mul_mac (struct neon_type_el et
, int ubit
)
17681 /* Give a more helpful error message if we have an invalid type. */
17682 if (et
.type
== NT_invtype
)
17685 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17689 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17690 inst
.instruction
|= LOW4 (scalar
);
17691 inst
.instruction
|= HI1 (scalar
) << 5;
17692 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17693 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17694 inst
.instruction
|= (ubit
!= 0) << 24;
17696 neon_dp_fixup (&inst
);
17700 do_neon_mac_maybe_scalar (void)
17702 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17705 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17708 if (inst
.operands
[2].isscalar
)
17710 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17711 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17712 struct neon_type_el et
= neon_check_type (3, rs
,
17713 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17714 NEON_ENCODE (SCALAR
, inst
);
17715 neon_mul_mac (et
, neon_quad (rs
));
17717 else if (!inst
.operands
[2].isvec
)
17719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17721 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17722 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17724 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17728 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17729 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17730 affected if we specify unsigned args. */
17731 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17736 do_neon_fmac (void)
17738 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17739 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17742 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17745 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17747 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17748 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17753 if (inst
.operands
[2].reg
== REG_SP
)
17754 as_tsktsk (MVE_BAD_SP
);
17755 else if (inst
.operands
[2].reg
== REG_PC
)
17756 as_tsktsk (MVE_BAD_PC
);
17758 inst
.instruction
= 0xee310e40;
17759 inst
.instruction
|= (et
.size
== 16) << 28;
17760 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17761 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17762 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17764 inst
.instruction
|= inst
.operands
[2].reg
;
17771 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17774 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17780 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17781 struct neon_type_el et
= neon_check_type (3, rs
,
17782 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17783 neon_three_same (neon_quad (rs
), 0, et
.size
);
17786 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17787 same types as the MAC equivalents. The polynomial type for this instruction
17788 is encoded the same as the integer type. */
17793 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17796 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17799 if (inst
.operands
[2].isscalar
)
17801 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17802 do_neon_mac_maybe_scalar ();
17806 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17808 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17809 struct neon_type_el et
17810 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17811 if (et
.type
== NT_float
)
17812 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17815 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17819 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17820 neon_dyadic_misc (NT_poly
,
17821 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17827 do_neon_qdmulh (void)
17829 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17832 if (inst
.operands
[2].isscalar
)
17834 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17835 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17836 struct neon_type_el et
= neon_check_type (3, rs
,
17837 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17838 NEON_ENCODE (SCALAR
, inst
);
17839 neon_mul_mac (et
, neon_quad (rs
));
17843 enum neon_shape rs
;
17844 struct neon_type_el et
;
17845 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17847 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17848 et
= neon_check_type (3, rs
,
17849 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17853 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17854 et
= neon_check_type (3, rs
,
17855 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17858 NEON_ENCODE (INTEGER
, inst
);
17860 mve_encode_qqr (et
.size
, 0, 0);
17862 /* The U bit (rounding) comes from bit mask. */
17863 neon_three_same (neon_quad (rs
), 0, et
.size
);
17868 do_mve_vaddv (void)
17870 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17871 struct neon_type_el et
17872 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17874 if (et
.type
== NT_invtype
)
17875 first_error (BAD_EL_TYPE
);
17877 if (inst
.cond
> COND_ALWAYS
)
17878 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17880 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17882 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17884 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17888 do_mve_vhcadd (void)
17890 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17891 struct neon_type_el et
17892 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17894 if (inst
.cond
> COND_ALWAYS
)
17895 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17897 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17899 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17900 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17902 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17903 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17904 "operand makes instruction UNPREDICTABLE"));
17906 mve_encode_qqq (0, et
.size
);
17907 inst
.instruction
|= (rot
== 270) << 12;
17912 do_mve_vqdmull (void)
17914 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17915 struct neon_type_el et
17916 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17919 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17920 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17921 as_tsktsk (BAD_MVE_SRCDEST
);
17923 if (inst
.cond
> COND_ALWAYS
)
17924 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17926 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17930 mve_encode_qqq (et
.size
== 32, 64);
17931 inst
.instruction
|= 1;
17935 mve_encode_qqr (64, et
.size
== 32, 0);
17936 inst
.instruction
|= 0x3 << 5;
17943 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17944 struct neon_type_el et
17945 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17947 if (et
.type
== NT_invtype
)
17948 first_error (BAD_EL_TYPE
);
17950 if (inst
.cond
> COND_ALWAYS
)
17951 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17953 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17955 mve_encode_qqq (0, 64);
17959 do_mve_vbrsr (void)
17961 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17962 struct neon_type_el et
17963 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17965 if (inst
.cond
> COND_ALWAYS
)
17966 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17968 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17970 mve_encode_qqr (et
.size
, 0, 0);
17976 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17978 if (inst
.cond
> COND_ALWAYS
)
17979 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17981 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17983 mve_encode_qqq (1, 64);
17987 do_mve_vmulh (void)
17989 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17990 struct neon_type_el et
17991 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17993 if (inst
.cond
> COND_ALWAYS
)
17994 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17996 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17998 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18002 do_mve_vqdmlah (void)
18004 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18005 struct neon_type_el et
18006 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18008 if (inst
.cond
> COND_ALWAYS
)
18009 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18011 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18013 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18017 do_mve_vqdmladh (void)
18019 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18020 struct neon_type_el et
18021 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18023 if (inst
.cond
> COND_ALWAYS
)
18024 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18026 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18028 mve_encode_qqq (0, et
.size
);
18033 do_mve_vmull (void)
18036 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18037 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18038 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18039 && inst
.cond
== COND_ALWAYS
18040 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18045 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18046 N_SUF_32
| N_F64
| N_P8
18047 | N_P16
| N_I_MVE
| N_KEY
);
18048 if (((et
.type
== NT_poly
) && et
.size
== 8
18049 && ARM_CPU_IS_ANY (cpu_variant
))
18050 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18057 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18058 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18059 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18061 /* We are dealing with MVE's vmullt. */
18063 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18064 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18065 as_tsktsk (BAD_MVE_SRCDEST
);
18067 if (inst
.cond
> COND_ALWAYS
)
18068 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18070 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18072 if (et
.type
== NT_poly
)
18073 mve_encode_qqq (neon_logbits (et
.size
), 64);
18075 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18080 inst
.instruction
= N_MNEM_vmul
;
18083 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18088 do_mve_vabav (void)
18090 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18095 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18098 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18099 | N_S16
| N_S32
| N_U8
| N_U16
18102 if (inst
.cond
> COND_ALWAYS
)
18103 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18105 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18107 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18111 do_mve_vmladav (void)
18113 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18114 struct neon_type_el et
= neon_check_type (3, rs
,
18115 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18117 if (et
.type
== NT_unsigned
18118 && (inst
.instruction
== M_MNEM_vmladavx
18119 || inst
.instruction
== M_MNEM_vmladavax
18120 || inst
.instruction
== M_MNEM_vmlsdav
18121 || inst
.instruction
== M_MNEM_vmlsdava
18122 || inst
.instruction
== M_MNEM_vmlsdavx
18123 || inst
.instruction
== M_MNEM_vmlsdavax
))
18124 first_error (BAD_SIMD_TYPE
);
18126 constraint (inst
.operands
[2].reg
> 14,
18127 _("MVE vector register in the range [Q0..Q7] expected"));
18129 if (inst
.cond
> COND_ALWAYS
)
18130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18134 if (inst
.instruction
== M_MNEM_vmlsdav
18135 || inst
.instruction
== M_MNEM_vmlsdava
18136 || inst
.instruction
== M_MNEM_vmlsdavx
18137 || inst
.instruction
== M_MNEM_vmlsdavax
)
18138 inst
.instruction
|= (et
.size
== 8) << 28;
18140 inst
.instruction
|= (et
.size
== 8) << 8;
18142 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18143 inst
.instruction
|= (et
.size
== 32) << 16;
18147 do_mve_vmlaldav (void)
18149 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18150 struct neon_type_el et
18151 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18152 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18154 if (et
.type
== NT_unsigned
18155 && (inst
.instruction
== M_MNEM_vmlsldav
18156 || inst
.instruction
== M_MNEM_vmlsldava
18157 || inst
.instruction
== M_MNEM_vmlsldavx
18158 || inst
.instruction
== M_MNEM_vmlsldavax
))
18159 first_error (BAD_SIMD_TYPE
);
18161 if (inst
.cond
> COND_ALWAYS
)
18162 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18164 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18166 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18170 do_mve_vrmlaldavh (void)
18172 struct neon_type_el et
;
18173 if (inst
.instruction
== M_MNEM_vrmlsldavh
18174 || inst
.instruction
== M_MNEM_vrmlsldavha
18175 || inst
.instruction
== M_MNEM_vrmlsldavhx
18176 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18178 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18179 if (inst
.operands
[1].reg
== REG_SP
)
18180 as_tsktsk (MVE_BAD_SP
);
18184 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18185 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18186 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18188 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18189 N_U32
| N_S32
| N_KEY
);
18190 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18191 with vmax/min instructions, making the use of SP in assembly really
18192 nonsensical, so instead of issuing a warning like we do for other uses
18193 of SP for the odd register operand we error out. */
18194 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18197 /* Make sure we still check the second operand is an odd one and that PC is
18198 disallowed. This because we are parsing for any GPR operand, to be able
18199 to distinguish between giving a warning or an error for SP as described
18201 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18202 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18204 if (inst
.cond
> COND_ALWAYS
)
18205 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18207 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18209 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18214 do_mve_vmaxnmv (void)
18216 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18217 struct neon_type_el et
18218 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18220 if (inst
.cond
> COND_ALWAYS
)
18221 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18223 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18225 if (inst
.operands
[0].reg
== REG_SP
)
18226 as_tsktsk (MVE_BAD_SP
);
18227 else if (inst
.operands
[0].reg
== REG_PC
)
18228 as_tsktsk (MVE_BAD_PC
);
18230 mve_encode_rq (et
.size
== 16, 64);
18234 do_mve_vmaxv (void)
18236 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18237 struct neon_type_el et
;
18239 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18240 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18242 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18244 if (inst
.cond
> COND_ALWAYS
)
18245 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18247 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18249 if (inst
.operands
[0].reg
== REG_SP
)
18250 as_tsktsk (MVE_BAD_SP
);
18251 else if (inst
.operands
[0].reg
== REG_PC
)
18252 as_tsktsk (MVE_BAD_PC
);
18254 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18259 do_neon_qrdmlah (void)
18261 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18263 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18265 /* Check we're on the correct architecture. */
18266 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18268 = _("instruction form not available on this architecture.");
18269 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18271 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18272 record_feature_use (&fpu_neon_ext_v8_1
);
18274 if (inst
.operands
[2].isscalar
)
18276 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18277 struct neon_type_el et
= neon_check_type (3, rs
,
18278 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18279 NEON_ENCODE (SCALAR
, inst
);
18280 neon_mul_mac (et
, neon_quad (rs
));
18284 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18285 struct neon_type_el et
= neon_check_type (3, rs
,
18286 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18287 NEON_ENCODE (INTEGER
, inst
);
18288 /* The U bit (rounding) comes from bit mask. */
18289 neon_three_same (neon_quad (rs
), 0, et
.size
);
18294 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18295 struct neon_type_el et
18296 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18298 NEON_ENCODE (INTEGER
, inst
);
18299 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18304 do_neon_fcmp_absolute (void)
18306 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18307 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18308 N_F_16_32
| N_KEY
);
18309 /* Size field comes from bit mask. */
18310 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18314 do_neon_fcmp_absolute_inv (void)
18316 neon_exchange_operands ();
18317 do_neon_fcmp_absolute ();
18321 do_neon_step (void)
18323 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18324 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18325 N_F_16_32
| N_KEY
);
18326 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18330 do_neon_abs_neg (void)
18332 enum neon_shape rs
;
18333 struct neon_type_el et
;
18335 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18338 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18339 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18341 if (!check_simd_pred_availability (et
.type
== NT_float
,
18342 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18345 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18346 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18347 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18348 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18349 inst
.instruction
|= neon_quad (rs
) << 6;
18350 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18351 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18353 neon_dp_fixup (&inst
);
18359 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18362 enum neon_shape rs
;
18363 struct neon_type_el et
;
18364 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18366 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18367 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18371 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18372 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18376 int imm
= inst
.operands
[2].imm
;
18377 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18378 _("immediate out of range for insert"));
18379 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18385 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18388 enum neon_shape rs
;
18389 struct neon_type_el et
;
18390 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18392 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18393 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18397 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18398 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18401 int imm
= inst
.operands
[2].imm
;
18402 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18403 _("immediate out of range for insert"));
18404 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18408 do_neon_qshlu_imm (void)
18410 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18413 enum neon_shape rs
;
18414 struct neon_type_el et
;
18415 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18417 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18418 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18422 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18423 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18424 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18427 int imm
= inst
.operands
[2].imm
;
18428 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18429 _("immediate out of range for shift"));
18430 /* Only encodes the 'U present' variant of the instruction.
18431 In this case, signed types have OP (bit 8) set to 0.
18432 Unsigned types have OP set to 1. */
18433 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18434 /* The rest of the bits are the same as other immediate shifts. */
18435 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18439 do_neon_qmovn (void)
18441 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18442 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18443 /* Saturating move where operands can be signed or unsigned, and the
18444 destination has the same signedness. */
18445 NEON_ENCODE (INTEGER
, inst
);
18446 if (et
.type
== NT_unsigned
)
18447 inst
.instruction
|= 0xc0;
18449 inst
.instruction
|= 0x80;
18450 neon_two_same (0, 1, et
.size
/ 2);
18454 do_neon_qmovun (void)
18456 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18457 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18458 /* Saturating move with unsigned results. Operands must be signed. */
18459 NEON_ENCODE (INTEGER
, inst
);
18460 neon_two_same (0, 1, et
.size
/ 2);
18464 do_neon_rshift_sat_narrow (void)
18466 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18467 or unsigned. If operands are unsigned, results must also be unsigned. */
18468 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18469 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18470 int imm
= inst
.operands
[2].imm
;
18471 /* This gets the bounds check, size encoding and immediate bits calculation
18475 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18476 VQMOVN.I<size> <Dd>, <Qm>. */
18479 inst
.operands
[2].present
= 0;
18480 inst
.instruction
= N_MNEM_vqmovn
;
18485 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18486 _("immediate out of range"));
18487 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18491 do_neon_rshift_sat_narrow_u (void)
18493 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18494 or unsigned. If operands are unsigned, results must also be unsigned. */
18495 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18496 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18497 int imm
= inst
.operands
[2].imm
;
18498 /* This gets the bounds check, size encoding and immediate bits calculation
18502 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18503 VQMOVUN.I<size> <Dd>, <Qm>. */
18506 inst
.operands
[2].present
= 0;
18507 inst
.instruction
= N_MNEM_vqmovun
;
18512 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18513 _("immediate out of range"));
18514 /* FIXME: The manual is kind of unclear about what value U should have in
18515 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18517 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18521 do_neon_movn (void)
18523 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18524 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18525 NEON_ENCODE (INTEGER
, inst
);
18526 neon_two_same (0, 1, et
.size
/ 2);
18530 do_neon_rshift_narrow (void)
18532 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18533 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18534 int imm
= inst
.operands
[2].imm
;
18535 /* This gets the bounds check, size encoding and immediate bits calculation
18539 /* If immediate is zero then we are a pseudo-instruction for
18540 VMOVN.I<size> <Dd>, <Qm> */
18543 inst
.operands
[2].present
= 0;
18544 inst
.instruction
= N_MNEM_vmovn
;
18549 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18550 _("immediate out of range for narrowing operation"));
18551 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18555 do_neon_shll (void)
18557 /* FIXME: Type checking when lengthening. */
18558 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18559 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18560 unsigned imm
= inst
.operands
[2].imm
;
18562 if (imm
== et
.size
)
18564 /* Maximum shift variant. */
18565 NEON_ENCODE (INTEGER
, inst
);
18566 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18567 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18568 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18569 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18570 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18572 neon_dp_fixup (&inst
);
18576 /* A more-specific type check for non-max versions. */
18577 et
= neon_check_type (2, NS_QDI
,
18578 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18579 NEON_ENCODE (IMMED
, inst
);
18580 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18584 /* Check the various types for the VCVT instruction, and return which version
18585 the current instruction is. */
18587 #define CVT_FLAVOUR_VAR \
18588 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18589 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18590 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18591 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18592 /* Half-precision conversions. */ \
18593 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18594 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18595 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18596 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18597 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18598 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18599 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18600 Compared with single/double precision variants, only the co-processor \
18601 field is different, so the encoding flow is reused here. */ \
18602 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18603 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18604 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18605 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18606 /* VFP instructions. */ \
18607 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18608 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18609 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18610 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18611 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18612 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18613 /* VFP instructions with bitshift. */ \
18614 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18615 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18616 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18617 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18618 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18619 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18620 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18621 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18623 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18624 neon_cvt_flavour_##C,
18626 /* The different types of conversions we can do. */
18627 enum neon_cvt_flavour
18630 neon_cvt_flavour_invalid
,
18631 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18636 static enum neon_cvt_flavour
18637 get_neon_cvt_flavour (enum neon_shape rs
)
18639 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18640 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18641 if (et.type != NT_invtype) \
18643 inst.error = NULL; \
18644 return (neon_cvt_flavour_##C); \
18647 struct neon_type_el et
;
18648 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18649 || rs
== NS_FF
) ? N_VFP
: 0;
18650 /* The instruction versions which take an immediate take one register
18651 argument, which is extended to the width of the full register. Thus the
18652 "source" and "destination" registers must have the same width. Hack that
18653 here by making the size equal to the key (wider, in this case) operand. */
18654 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18658 return neon_cvt_flavour_invalid
;
18673 /* Neon-syntax VFP conversions. */
18676 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18678 const char *opname
= 0;
18680 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18681 || rs
== NS_FHI
|| rs
== NS_HFI
)
18683 /* Conversions with immediate bitshift. */
18684 const char *enc
[] =
18686 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18692 if (flavour
< (int) ARRAY_SIZE (enc
))
18694 opname
= enc
[flavour
];
18695 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18696 _("operands 0 and 1 must be the same register"));
18697 inst
.operands
[1] = inst
.operands
[2];
18698 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18703 /* Conversions without bitshift. */
18704 const char *enc
[] =
18706 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18712 if (flavour
< (int) ARRAY_SIZE (enc
))
18713 opname
= enc
[flavour
];
18717 do_vfp_nsyn_opcode (opname
);
18719 /* ARMv8.2 fp16 VCVT instruction. */
18720 if (flavour
== neon_cvt_flavour_s32_f16
18721 || flavour
== neon_cvt_flavour_u32_f16
18722 || flavour
== neon_cvt_flavour_f16_u32
18723 || flavour
== neon_cvt_flavour_f16_s32
)
18724 do_scalar_fp16_v82_encode ();
18728 do_vfp_nsyn_cvtz (void)
18730 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18731 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18732 const char *enc
[] =
18734 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18740 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18741 do_vfp_nsyn_opcode (enc
[flavour
]);
18745 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18746 enum neon_cvt_mode mode
)
18751 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18752 D register operands. */
18753 if (flavour
== neon_cvt_flavour_s32_f64
18754 || flavour
== neon_cvt_flavour_u32_f64
)
18755 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18758 if (flavour
== neon_cvt_flavour_s32_f16
18759 || flavour
== neon_cvt_flavour_u32_f16
)
18760 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18763 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18767 case neon_cvt_flavour_s32_f64
:
18771 case neon_cvt_flavour_s32_f32
:
18775 case neon_cvt_flavour_s32_f16
:
18779 case neon_cvt_flavour_u32_f64
:
18783 case neon_cvt_flavour_u32_f32
:
18787 case neon_cvt_flavour_u32_f16
:
18792 first_error (_("invalid instruction shape"));
18798 case neon_cvt_mode_a
: rm
= 0; break;
18799 case neon_cvt_mode_n
: rm
= 1; break;
18800 case neon_cvt_mode_p
: rm
= 2; break;
18801 case neon_cvt_mode_m
: rm
= 3; break;
18802 default: first_error (_("invalid rounding mode")); return;
18805 NEON_ENCODE (FPV8
, inst
);
18806 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18807 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18808 inst
.instruction
|= sz
<< 8;
18810 /* ARMv8.2 fp16 VCVT instruction. */
18811 if (flavour
== neon_cvt_flavour_s32_f16
18812 ||flavour
== neon_cvt_flavour_u32_f16
)
18813 do_scalar_fp16_v82_encode ();
18814 inst
.instruction
|= op
<< 7;
18815 inst
.instruction
|= rm
<< 16;
18816 inst
.instruction
|= 0xf0000000;
18817 inst
.is_neon
= TRUE
;
18821 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18823 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18824 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18825 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18827 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18829 if (flavour
== neon_cvt_flavour_invalid
)
18832 /* PR11109: Handle round-to-zero for VCVT conversions. */
18833 if (mode
== neon_cvt_mode_z
18834 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18835 && (flavour
== neon_cvt_flavour_s16_f16
18836 || flavour
== neon_cvt_flavour_u16_f16
18837 || flavour
== neon_cvt_flavour_s32_f32
18838 || flavour
== neon_cvt_flavour_u32_f32
18839 || flavour
== neon_cvt_flavour_s32_f64
18840 || flavour
== neon_cvt_flavour_u32_f64
)
18841 && (rs
== NS_FD
|| rs
== NS_FF
))
18843 do_vfp_nsyn_cvtz ();
18847 /* ARMv8.2 fp16 VCVT conversions. */
18848 if (mode
== neon_cvt_mode_z
18849 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18850 && (flavour
== neon_cvt_flavour_s32_f16
18851 || flavour
== neon_cvt_flavour_u32_f16
)
18854 do_vfp_nsyn_cvtz ();
18855 do_scalar_fp16_v82_encode ();
18859 /* VFP rather than Neon conversions. */
18860 if (flavour
>= neon_cvt_flavour_first_fp
)
18862 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18863 do_vfp_nsyn_cvt (rs
, flavour
);
18865 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18873 if (mode
== neon_cvt_mode_z
18874 && (flavour
== neon_cvt_flavour_f16_s16
18875 || flavour
== neon_cvt_flavour_f16_u16
18876 || flavour
== neon_cvt_flavour_s16_f16
18877 || flavour
== neon_cvt_flavour_u16_f16
18878 || flavour
== neon_cvt_flavour_f32_u32
18879 || flavour
== neon_cvt_flavour_f32_s32
18880 || flavour
== neon_cvt_flavour_s32_f32
18881 || flavour
== neon_cvt_flavour_u32_f32
))
18883 if (!check_simd_pred_availability (TRUE
,
18884 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18887 else if (mode
== neon_cvt_mode_n
)
18889 /* We are dealing with vcvt with the 'ne' condition. */
18891 inst
.instruction
= N_MNEM_vcvt
;
18892 do_neon_cvt_1 (neon_cvt_mode_z
);
18895 /* fall through. */
18899 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18900 0x0000100, 0x1000100, 0x0, 0x1000000};
18902 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18903 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18908 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18909 _("immediate value out of range"));
18912 case neon_cvt_flavour_f16_s16
:
18913 case neon_cvt_flavour_f16_u16
:
18914 case neon_cvt_flavour_s16_f16
:
18915 case neon_cvt_flavour_u16_f16
:
18916 constraint (inst
.operands
[2].imm
> 16,
18917 _("immediate value out of range"));
18919 case neon_cvt_flavour_f32_u32
:
18920 case neon_cvt_flavour_f32_s32
:
18921 case neon_cvt_flavour_s32_f32
:
18922 case neon_cvt_flavour_u32_f32
:
18923 constraint (inst
.operands
[2].imm
> 32,
18924 _("immediate value out of range"));
18927 inst
.error
= BAD_FPU
;
18932 /* Fixed-point conversion with #0 immediate is encoded as an
18933 integer conversion. */
18934 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18936 NEON_ENCODE (IMMED
, inst
);
18937 if (flavour
!= neon_cvt_flavour_invalid
)
18938 inst
.instruction
|= enctab
[flavour
];
18939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18941 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18943 inst
.instruction
|= neon_quad (rs
) << 6;
18944 inst
.instruction
|= 1 << 21;
18945 if (flavour
< neon_cvt_flavour_s16_f16
)
18947 inst
.instruction
|= 1 << 21;
18948 immbits
= 32 - inst
.operands
[2].imm
;
18949 inst
.instruction
|= immbits
<< 16;
18953 inst
.instruction
|= 3 << 20;
18954 immbits
= 16 - inst
.operands
[2].imm
;
18955 inst
.instruction
|= immbits
<< 16;
18956 inst
.instruction
&= ~(1 << 9);
18959 neon_dp_fixup (&inst
);
18964 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18965 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18966 && (flavour
== neon_cvt_flavour_s16_f16
18967 || flavour
== neon_cvt_flavour_u16_f16
18968 || flavour
== neon_cvt_flavour_s32_f32
18969 || flavour
== neon_cvt_flavour_u32_f32
))
18971 if (!check_simd_pred_availability (TRUE
,
18972 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18975 else if (mode
== neon_cvt_mode_z
18976 && (flavour
== neon_cvt_flavour_f16_s16
18977 || flavour
== neon_cvt_flavour_f16_u16
18978 || flavour
== neon_cvt_flavour_s16_f16
18979 || flavour
== neon_cvt_flavour_u16_f16
18980 || flavour
== neon_cvt_flavour_f32_u32
18981 || flavour
== neon_cvt_flavour_f32_s32
18982 || flavour
== neon_cvt_flavour_s32_f32
18983 || flavour
== neon_cvt_flavour_u32_f32
))
18985 if (!check_simd_pred_availability (TRUE
,
18986 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18989 /* fall through. */
18991 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18994 NEON_ENCODE (FLOAT
, inst
);
18995 if (!check_simd_pred_availability (TRUE
,
18996 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19000 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19001 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19002 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19003 inst
.instruction
|= neon_quad (rs
) << 6;
19004 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19005 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19006 inst
.instruction
|= mode
<< 8;
19007 if (flavour
== neon_cvt_flavour_u16_f16
19008 || flavour
== neon_cvt_flavour_s16_f16
)
19009 /* Mask off the original size bits and reencode them. */
19010 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19013 inst
.instruction
|= 0xfc000000;
19015 inst
.instruction
|= 0xf0000000;
19021 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19022 0x100, 0x180, 0x0, 0x080};
19024 NEON_ENCODE (INTEGER
, inst
);
19026 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19028 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19032 if (flavour
!= neon_cvt_flavour_invalid
)
19033 inst
.instruction
|= enctab
[flavour
];
19035 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19036 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19037 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19038 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19039 inst
.instruction
|= neon_quad (rs
) << 6;
19040 if (flavour
>= neon_cvt_flavour_s16_f16
19041 && flavour
<= neon_cvt_flavour_f16_u16
)
19042 /* Half precision. */
19043 inst
.instruction
|= 1 << 18;
19045 inst
.instruction
|= 2 << 18;
19047 neon_dp_fixup (&inst
);
19052 /* Half-precision conversions for Advanced SIMD -- neon. */
19055 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19059 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19061 as_bad (_("operand size must match register width"));
19066 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19068 as_bad (_("operand size must match register width"));
19073 inst
.instruction
= 0x3b60600;
19075 inst
.instruction
= 0x3b60700;
19077 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19078 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19079 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19080 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19081 neon_dp_fixup (&inst
);
19085 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19086 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19087 do_vfp_nsyn_cvt (rs
, flavour
);
19089 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19094 do_neon_cvtr (void)
19096 do_neon_cvt_1 (neon_cvt_mode_x
);
19102 do_neon_cvt_1 (neon_cvt_mode_z
);
19106 do_neon_cvta (void)
19108 do_neon_cvt_1 (neon_cvt_mode_a
);
19112 do_neon_cvtn (void)
19114 do_neon_cvt_1 (neon_cvt_mode_n
);
19118 do_neon_cvtp (void)
19120 do_neon_cvt_1 (neon_cvt_mode_p
);
19124 do_neon_cvtm (void)
19126 do_neon_cvt_1 (neon_cvt_mode_m
);
19130 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19133 mark_feature_used (&fpu_vfp_ext_armv8
);
19135 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19136 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19137 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19138 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19139 inst
.instruction
|= to
? 0x10000 : 0;
19140 inst
.instruction
|= t
? 0x80 : 0;
19141 inst
.instruction
|= is_double
? 0x100 : 0;
19142 do_vfp_cond_or_thumb ();
19146 do_neon_cvttb_1 (bfd_boolean t
)
19148 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19149 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19153 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19155 int single_to_half
= 0;
19156 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19159 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19161 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19162 && (flavour
== neon_cvt_flavour_u16_f16
19163 || flavour
== neon_cvt_flavour_s16_f16
19164 || flavour
== neon_cvt_flavour_f16_s16
19165 || flavour
== neon_cvt_flavour_f16_u16
19166 || flavour
== neon_cvt_flavour_u32_f32
19167 || flavour
== neon_cvt_flavour_s32_f32
19168 || flavour
== neon_cvt_flavour_f32_s32
19169 || flavour
== neon_cvt_flavour_f32_u32
))
19172 inst
.instruction
= N_MNEM_vcvt
;
19173 set_pred_insn_type (INSIDE_VPT_INSN
);
19174 do_neon_cvt_1 (neon_cvt_mode_z
);
19177 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19178 single_to_half
= 1;
19179 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19181 first_error (BAD_FPU
);
19185 inst
.instruction
= 0xee3f0e01;
19186 inst
.instruction
|= single_to_half
<< 28;
19187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19189 inst
.instruction
|= t
<< 12;
19190 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19191 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19194 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19197 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19199 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19202 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19204 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19206 /* The VCVTB and VCVTT instructions with D-register operands
19207 don't work for SP only targets. */
19208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19212 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19214 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19216 /* The VCVTB and VCVTT instructions with D-register operands
19217 don't work for SP only targets. */
19218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19222 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19229 do_neon_cvtb (void)
19231 do_neon_cvttb_1 (FALSE
);
19236 do_neon_cvtt (void)
19238 do_neon_cvttb_1 (TRUE
);
19242 neon_move_immediate (void)
19244 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19245 struct neon_type_el et
= neon_check_type (2, rs
,
19246 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19247 unsigned immlo
, immhi
= 0, immbits
;
19248 int op
, cmode
, float_p
;
19250 constraint (et
.type
== NT_invtype
,
19251 _("operand size must be specified for immediate VMOV"));
19253 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19254 op
= (inst
.instruction
& (1 << 5)) != 0;
19256 immlo
= inst
.operands
[1].imm
;
19257 if (inst
.operands
[1].regisimm
)
19258 immhi
= inst
.operands
[1].reg
;
19260 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19261 _("immediate has bits set outside the operand size"));
19263 float_p
= inst
.operands
[1].immisfloat
;
19265 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19266 et
.size
, et
.type
)) == FAIL
)
19268 /* Invert relevant bits only. */
19269 neon_invert_size (&immlo
, &immhi
, et
.size
);
19270 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19271 with one or the other; those cases are caught by
19272 neon_cmode_for_move_imm. */
19274 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19275 &op
, et
.size
, et
.type
)) == FAIL
)
19277 first_error (_("immediate out of range"));
19282 inst
.instruction
&= ~(1 << 5);
19283 inst
.instruction
|= op
<< 5;
19285 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19287 inst
.instruction
|= neon_quad (rs
) << 6;
19288 inst
.instruction
|= cmode
<< 8;
19290 neon_write_immbits (immbits
);
19296 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19299 if (inst
.operands
[1].isreg
)
19301 enum neon_shape rs
;
19302 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19303 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19305 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19307 NEON_ENCODE (INTEGER
, inst
);
19308 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19309 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19310 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19311 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19312 inst
.instruction
|= neon_quad (rs
) << 6;
19316 NEON_ENCODE (IMMED
, inst
);
19317 neon_move_immediate ();
19320 neon_dp_fixup (&inst
);
19322 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19324 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19325 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19326 _("immediate value out of range"));
19330 /* Encode instructions of form:
19332 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19333 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19336 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19339 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19340 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19341 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19342 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19343 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19344 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19345 inst
.instruction
|= neon_logbits (size
) << 20;
19347 neon_dp_fixup (&inst
);
19351 do_neon_dyadic_long (void)
19353 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19356 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19359 NEON_ENCODE (INTEGER
, inst
);
19360 /* FIXME: Type checking for lengthening op. */
19361 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19362 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19363 neon_mixed_length (et
, et
.size
);
19365 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19366 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19368 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19369 in an IT block with le/lt conditions. */
19371 if (inst
.cond
== 0xf)
19373 else if (inst
.cond
== 0x10)
19376 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19378 if (inst
.instruction
== N_MNEM_vaddl
)
19380 inst
.instruction
= N_MNEM_vadd
;
19381 do_neon_addsub_if_i ();
19383 else if (inst
.instruction
== N_MNEM_vsubl
)
19385 inst
.instruction
= N_MNEM_vsub
;
19386 do_neon_addsub_if_i ();
19388 else if (inst
.instruction
== N_MNEM_vabdl
)
19390 inst
.instruction
= N_MNEM_vabd
;
19391 do_neon_dyadic_if_su ();
19395 first_error (BAD_FPU
);
19399 do_neon_abal (void)
19401 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19402 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19403 neon_mixed_length (et
, et
.size
);
19407 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19409 if (inst
.operands
[2].isscalar
)
19411 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19412 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19413 NEON_ENCODE (SCALAR
, inst
);
19414 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19418 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19419 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19420 NEON_ENCODE (INTEGER
, inst
);
19421 neon_mixed_length (et
, et
.size
);
19426 do_neon_mac_maybe_scalar_long (void)
19428 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19431 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19432 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19435 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19437 unsigned regno
= NEON_SCALAR_REG (scalar
);
19438 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19442 if (regno
> 7 || elno
> 3)
19445 return ((regno
& 0x7)
19446 | ((elno
& 0x1) << 3)
19447 | (((elno
>> 1) & 0x1) << 5));
19451 if (regno
> 15 || elno
> 1)
19454 return (((regno
& 0x1) << 5)
19455 | ((regno
>> 1) & 0x7)
19456 | ((elno
& 0x1) << 3));
19460 first_error (_("scalar out of range for multiply instruction"));
19465 do_neon_fmac_maybe_scalar_long (int subtype
)
19467 enum neon_shape rs
;
19469 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19470 field (bits[21:20]) has different meaning. For scalar index variant, it's
19471 used to differentiate add and subtract, otherwise it's with fixed value
19475 if (inst
.cond
!= COND_ALWAYS
)
19476 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19477 "behaviour is UNPREDICTABLE"));
19479 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19482 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19485 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19486 be a scalar index register. */
19487 if (inst
.operands
[2].isscalar
)
19489 high8
= 0xfe000000;
19492 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19496 high8
= 0xfc000000;
19499 inst
.instruction
|= (0x1 << 23);
19500 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19503 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19505 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19506 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19507 so we simply pass -1 as size. */
19508 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19509 neon_three_same (quad_p
, 0, size
);
19511 /* Undo neon_dp_fixup. Redo the high eight bits. */
19512 inst
.instruction
&= 0x00ffffff;
19513 inst
.instruction
|= high8
;
19515 #define LOW1(R) ((R) & 0x1)
19516 #define HI4(R) (((R) >> 1) & 0xf)
19517 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19518 whether the instruction is in Q form and whether Vm is a scalar indexed
19520 if (inst
.operands
[2].isscalar
)
19523 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19524 inst
.instruction
&= 0xffffffd0;
19525 inst
.instruction
|= rm
;
19529 /* Redo Rn as well. */
19530 inst
.instruction
&= 0xfff0ff7f;
19531 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19532 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19537 /* Redo Rn and Rm. */
19538 inst
.instruction
&= 0xfff0ff50;
19539 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19540 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19541 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19542 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19547 do_neon_vfmal (void)
19549 return do_neon_fmac_maybe_scalar_long (0);
19553 do_neon_vfmsl (void)
19555 return do_neon_fmac_maybe_scalar_long (1);
19559 do_neon_dyadic_wide (void)
19561 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19562 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19563 neon_mixed_length (et
, et
.size
);
19567 do_neon_dyadic_narrow (void)
19569 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19570 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19571 /* Operand sign is unimportant, and the U bit is part of the opcode,
19572 so force the operand type to integer. */
19573 et
.type
= NT_integer
;
19574 neon_mixed_length (et
, et
.size
/ 2);
19578 do_neon_mul_sat_scalar_long (void)
19580 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19584 do_neon_vmull (void)
19586 if (inst
.operands
[2].isscalar
)
19587 do_neon_mac_maybe_scalar_long ();
19590 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19591 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19593 if (et
.type
== NT_poly
)
19594 NEON_ENCODE (POLY
, inst
);
19596 NEON_ENCODE (INTEGER
, inst
);
19598 /* For polynomial encoding the U bit must be zero, and the size must
19599 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19600 obviously, as 0b10). */
19603 /* Check we're on the correct architecture. */
19604 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19606 _("Instruction form not available on this architecture.");
19611 neon_mixed_length (et
, et
.size
);
19618 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19619 struct neon_type_el et
= neon_check_type (3, rs
,
19620 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19621 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19623 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19624 _("shift out of range"));
19625 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19626 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19627 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19628 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19629 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19630 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19631 inst
.instruction
|= neon_quad (rs
) << 6;
19632 inst
.instruction
|= imm
<< 8;
19634 neon_dp_fixup (&inst
);
19640 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19643 enum neon_shape rs
;
19644 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19645 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19647 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19649 struct neon_type_el et
= neon_check_type (2, rs
,
19650 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19652 unsigned op
= (inst
.instruction
>> 7) & 3;
19653 /* N (width of reversed regions) is encoded as part of the bitmask. We
19654 extract it here to check the elements to be reversed are smaller.
19655 Otherwise we'd get a reserved instruction. */
19656 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19658 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19659 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19660 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19661 " operands makes instruction UNPREDICTABLE"));
19663 gas_assert (elsize
!= 0);
19664 constraint (et
.size
>= elsize
,
19665 _("elements must be smaller than reversal region"));
19666 neon_two_same (neon_quad (rs
), 1, et
.size
);
19672 if (inst
.operands
[1].isscalar
)
19674 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19676 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19677 struct neon_type_el et
= neon_check_type (2, rs
,
19678 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19679 unsigned sizebits
= et
.size
>> 3;
19680 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19681 int logsize
= neon_logbits (et
.size
);
19682 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19684 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19687 NEON_ENCODE (SCALAR
, inst
);
19688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19690 inst
.instruction
|= LOW4 (dm
);
19691 inst
.instruction
|= HI1 (dm
) << 5;
19692 inst
.instruction
|= neon_quad (rs
) << 6;
19693 inst
.instruction
|= x
<< 17;
19694 inst
.instruction
|= sizebits
<< 16;
19696 neon_dp_fixup (&inst
);
19700 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19701 struct neon_type_el et
= neon_check_type (2, rs
,
19702 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19705 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19712 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19714 if (inst
.operands
[1].reg
== REG_SP
)
19715 as_tsktsk (MVE_BAD_SP
);
19716 else if (inst
.operands
[1].reg
== REG_PC
)
19717 as_tsktsk (MVE_BAD_PC
);
19720 /* Duplicate ARM register to lanes of vector. */
19721 NEON_ENCODE (ARMREG
, inst
);
19724 case 8: inst
.instruction
|= 0x400000; break;
19725 case 16: inst
.instruction
|= 0x000020; break;
19726 case 32: inst
.instruction
|= 0x000000; break;
19729 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19730 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19731 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19732 inst
.instruction
|= neon_quad (rs
) << 21;
19733 /* The encoding for this instruction is identical for the ARM and Thumb
19734 variants, except for the condition field. */
19735 do_vfp_cond_or_thumb ();
19740 do_mve_mov (int toQ
)
19742 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19744 if (inst
.cond
> COND_ALWAYS
)
19745 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19747 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19756 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19757 _("Index one must be [2,3] and index two must be two less than"
19759 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19760 _("General purpose registers may not be the same"));
19761 constraint (inst
.operands
[Rt
].reg
== REG_SP
19762 || inst
.operands
[Rt2
].reg
== REG_SP
,
19764 constraint (inst
.operands
[Rt
].reg
== REG_PC
19765 || inst
.operands
[Rt2
].reg
== REG_PC
,
19768 inst
.instruction
= 0xec000f00;
19769 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19770 inst
.instruction
|= !!toQ
<< 20;
19771 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19772 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19773 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19774 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19780 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19783 if (inst
.cond
> COND_ALWAYS
)
19784 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19786 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19788 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19791 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19792 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19794 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19800 /* VMOV has particularly many variations. It can be one of:
19801 0. VMOV<c><q> <Qd>, <Qm>
19802 1. VMOV<c><q> <Dd>, <Dm>
19803 (Register operations, which are VORR with Rm = Rn.)
19804 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19805 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19807 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19808 (ARM register to scalar.)
19809 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19810 (Two ARM registers to vector.)
19811 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19812 (Scalar to ARM register.)
19813 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19814 (Vector to two ARM registers.)
19815 8. VMOV.F32 <Sd>, <Sm>
19816 9. VMOV.F64 <Dd>, <Dm>
19817 (VFP register moves.)
19818 10. VMOV.F32 <Sd>, #imm
19819 11. VMOV.F64 <Dd>, #imm
19820 (VFP float immediate load.)
19821 12. VMOV <Rd>, <Sm>
19822 (VFP single to ARM reg.)
19823 13. VMOV <Sd>, <Rm>
19824 (ARM reg to VFP single.)
19825 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19826 (Two ARM regs to two VFP singles.)
19827 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19828 (Two VFP singles to two ARM regs.)
19829 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19830 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19831 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19832 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19834 These cases can be disambiguated using neon_select_shape, except cases 1/9
19835 and 3/11 which depend on the operand type too.
19837 All the encoded bits are hardcoded by this function.
19839 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19840 Cases 5, 7 may be used with VFPv2 and above.
19842 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19843 can specify a type where it doesn't make sense to, and is ignored). */
19848 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19849 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19850 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19851 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19853 struct neon_type_el et
;
19854 const char *ldconst
= 0;
19858 case NS_DD
: /* case 1/9. */
19859 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19860 /* It is not an error here if no type is given. */
19862 if (et
.type
== NT_float
&& et
.size
== 64)
19864 do_vfp_nsyn_opcode ("fcpyd");
19867 /* fall through. */
19869 case NS_QQ
: /* case 0/1. */
19871 if (!check_simd_pred_availability (FALSE
,
19872 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19874 /* The architecture manual I have doesn't explicitly state which
19875 value the U bit should have for register->register moves, but
19876 the equivalent VORR instruction has U = 0, so do that. */
19877 inst
.instruction
= 0x0200110;
19878 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19879 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19880 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19881 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19882 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19883 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19884 inst
.instruction
|= neon_quad (rs
) << 6;
19886 neon_dp_fixup (&inst
);
19890 case NS_DI
: /* case 3/11. */
19891 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19893 if (et
.type
== NT_float
&& et
.size
== 64)
19895 /* case 11 (fconstd). */
19896 ldconst
= "fconstd";
19897 goto encode_fconstd
;
19899 /* fall through. */
19901 case NS_QI
: /* case 2/3. */
19902 if (!check_simd_pred_availability (FALSE
,
19903 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19905 inst
.instruction
= 0x0800010;
19906 neon_move_immediate ();
19907 neon_dp_fixup (&inst
);
19910 case NS_SR
: /* case 4. */
19912 unsigned bcdebits
= 0;
19914 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19915 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19917 /* .<size> is optional here, defaulting to .32. */
19918 if (inst
.vectype
.elems
== 0
19919 && inst
.operands
[0].vectype
.type
== NT_invtype
19920 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19922 inst
.vectype
.el
[0].type
= NT_untyped
;
19923 inst
.vectype
.el
[0].size
= 32;
19924 inst
.vectype
.elems
= 1;
19927 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19928 logsize
= neon_logbits (et
.size
);
19932 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19933 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19938 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19939 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19943 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19945 if (inst
.operands
[1].reg
== REG_SP
)
19946 as_tsktsk (MVE_BAD_SP
);
19947 else if (inst
.operands
[1].reg
== REG_PC
)
19948 as_tsktsk (MVE_BAD_PC
);
19950 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19952 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19953 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19958 case 8: bcdebits
= 0x8; break;
19959 case 16: bcdebits
= 0x1; break;
19960 case 32: bcdebits
= 0x0; break;
19964 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19966 inst
.instruction
= 0xe000b10;
19967 do_vfp_cond_or_thumb ();
19968 inst
.instruction
|= LOW4 (dn
) << 16;
19969 inst
.instruction
|= HI1 (dn
) << 7;
19970 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19971 inst
.instruction
|= (bcdebits
& 3) << 5;
19972 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19973 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19977 case NS_DRR
: /* case 5 (fmdrr). */
19978 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19979 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19982 inst
.instruction
= 0xc400b10;
19983 do_vfp_cond_or_thumb ();
19984 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19985 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19986 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19987 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19990 case NS_RS
: /* case 6. */
19993 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19994 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19995 unsigned abcdebits
= 0;
19997 /* .<dt> is optional here, defaulting to .32. */
19998 if (inst
.vectype
.elems
== 0
19999 && inst
.operands
[0].vectype
.type
== NT_invtype
20000 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20002 inst
.vectype
.el
[0].type
= NT_untyped
;
20003 inst
.vectype
.el
[0].size
= 32;
20004 inst
.vectype
.elems
= 1;
20007 et
= neon_check_type (2, NS_NULL
,
20008 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20009 logsize
= neon_logbits (et
.size
);
20013 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20014 && vfp_or_neon_is_neon (NEON_CHECK_CC
20015 | NEON_CHECK_ARCH
) == FAIL
)
20020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20021 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20025 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20027 if (inst
.operands
[0].reg
== REG_SP
)
20028 as_tsktsk (MVE_BAD_SP
);
20029 else if (inst
.operands
[0].reg
== REG_PC
)
20030 as_tsktsk (MVE_BAD_PC
);
20033 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20035 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20036 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20040 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20041 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20042 case 32: abcdebits
= 0x00; break;
20046 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20047 inst
.instruction
= 0xe100b10;
20048 do_vfp_cond_or_thumb ();
20049 inst
.instruction
|= LOW4 (dn
) << 16;
20050 inst
.instruction
|= HI1 (dn
) << 7;
20051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20052 inst
.instruction
|= (abcdebits
& 3) << 5;
20053 inst
.instruction
|= (abcdebits
>> 2) << 21;
20054 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20058 case NS_RRD
: /* case 7 (fmrrd). */
20059 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20060 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20063 inst
.instruction
= 0xc500b10;
20064 do_vfp_cond_or_thumb ();
20065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20066 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20067 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20068 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20071 case NS_FF
: /* case 8 (fcpys). */
20072 do_vfp_nsyn_opcode ("fcpys");
20076 case NS_FI
: /* case 10 (fconsts). */
20077 ldconst
= "fconsts";
20079 if (!inst
.operands
[1].immisfloat
)
20082 /* Immediate has to fit in 8 bits so float is enough. */
20083 float imm
= (float) inst
.operands
[1].imm
;
20084 memcpy (&new_imm
, &imm
, sizeof (float));
20085 /* But the assembly may have been written to provide an integer
20086 bit pattern that equates to a float, so check that the
20087 conversion has worked. */
20088 if (is_quarter_float (new_imm
))
20090 if (is_quarter_float (inst
.operands
[1].imm
))
20091 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20093 inst
.operands
[1].imm
= new_imm
;
20094 inst
.operands
[1].immisfloat
= 1;
20098 if (is_quarter_float (inst
.operands
[1].imm
))
20100 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20101 do_vfp_nsyn_opcode (ldconst
);
20103 /* ARMv8.2 fp16 vmov.f16 instruction. */
20105 do_scalar_fp16_v82_encode ();
20108 first_error (_("immediate out of range"));
20112 case NS_RF
: /* case 12 (fmrs). */
20113 do_vfp_nsyn_opcode ("fmrs");
20114 /* ARMv8.2 fp16 vmov.f16 instruction. */
20116 do_scalar_fp16_v82_encode ();
20120 case NS_FR
: /* case 13 (fmsr). */
20121 do_vfp_nsyn_opcode ("fmsr");
20122 /* ARMv8.2 fp16 vmov.f16 instruction. */
20124 do_scalar_fp16_v82_encode ();
20134 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20135 (one of which is a list), but we have parsed four. Do some fiddling to
20136 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20138 case NS_RRFF
: /* case 14 (fmrrs). */
20139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20140 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20142 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20143 _("VFP registers must be adjacent"));
20144 inst
.operands
[2].imm
= 2;
20145 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20146 do_vfp_nsyn_opcode ("fmrrs");
20149 case NS_FFRR
: /* case 15 (fmsrr). */
20150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20151 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20153 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20154 _("VFP registers must be adjacent"));
20155 inst
.operands
[1] = inst
.operands
[2];
20156 inst
.operands
[2] = inst
.operands
[3];
20157 inst
.operands
[0].imm
= 2;
20158 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20159 do_vfp_nsyn_opcode ("fmsrr");
20163 /* neon_select_shape has determined that the instruction
20164 shape is wrong and has already set the error message. */
20175 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20176 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20177 && !inst
.operands
[2].present
))
20179 inst
.instruction
= 0;
20182 set_pred_insn_type (INSIDE_IT_INSN
);
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20190 if (inst
.cond
!= COND_ALWAYS
)
20191 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20193 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20194 | N_S16
| N_U16
| N_KEY
);
20196 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20197 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20198 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20199 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20200 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20201 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20206 do_neon_rshift_round_imm (void)
20208 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20211 enum neon_shape rs
;
20212 struct neon_type_el et
;
20214 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20216 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20217 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20221 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20222 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20224 int imm
= inst
.operands
[2].imm
;
20226 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20229 inst
.operands
[2].present
= 0;
20234 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20235 _("immediate out of range for shift"));
20236 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20241 do_neon_movhf (void)
20243 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20244 constraint (rs
!= NS_HH
, _("invalid suffix"));
20246 if (inst
.cond
!= COND_ALWAYS
)
20250 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20251 " the behaviour is UNPREDICTABLE"));
20255 inst
.error
= BAD_COND
;
20260 do_vfp_sp_monadic ();
20263 inst
.instruction
|= 0xf0000000;
20267 do_neon_movl (void)
20269 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20270 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20271 unsigned sizebits
= et
.size
>> 3;
20272 inst
.instruction
|= sizebits
<< 19;
20273 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20279 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20280 struct neon_type_el et
= neon_check_type (2, rs
,
20281 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20282 NEON_ENCODE (INTEGER
, inst
);
20283 neon_two_same (neon_quad (rs
), 1, et
.size
);
20287 do_neon_zip_uzp (void)
20289 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20290 struct neon_type_el et
= neon_check_type (2, rs
,
20291 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20292 if (rs
== NS_DD
&& et
.size
== 32)
20294 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20295 inst
.instruction
= N_MNEM_vtrn
;
20299 neon_two_same (neon_quad (rs
), 1, et
.size
);
20303 do_neon_sat_abs_neg (void)
20305 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20308 enum neon_shape rs
;
20309 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20310 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20312 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20313 struct neon_type_el et
= neon_check_type (2, rs
,
20314 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20315 neon_two_same (neon_quad (rs
), 1, et
.size
);
20319 do_neon_pair_long (void)
20321 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20322 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20323 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20324 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20325 neon_two_same (neon_quad (rs
), 1, et
.size
);
20329 do_neon_recip_est (void)
20331 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20332 struct neon_type_el et
= neon_check_type (2, rs
,
20333 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20334 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20335 neon_two_same (neon_quad (rs
), 1, et
.size
);
20341 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20344 enum neon_shape rs
;
20345 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20346 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20348 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20350 struct neon_type_el et
= neon_check_type (2, rs
,
20351 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20352 neon_two_same (neon_quad (rs
), 1, et
.size
);
20358 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20361 enum neon_shape rs
;
20362 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20363 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20365 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20367 struct neon_type_el et
= neon_check_type (2, rs
,
20368 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20369 neon_two_same (neon_quad (rs
), 1, et
.size
);
20375 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20376 struct neon_type_el et
= neon_check_type (2, rs
,
20377 N_EQK
| N_INT
, N_8
| N_KEY
);
20378 neon_two_same (neon_quad (rs
), 1, et
.size
);
20384 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20385 neon_two_same (neon_quad (rs
), 1, -1);
20389 do_neon_tbl_tbx (void)
20391 unsigned listlenbits
;
20392 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20394 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20396 first_error (_("bad list length for table lookup"));
20400 listlenbits
= inst
.operands
[1].imm
- 1;
20401 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20402 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20403 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20404 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20405 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20406 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20407 inst
.instruction
|= listlenbits
<< 8;
20409 neon_dp_fixup (&inst
);
20413 do_neon_ldm_stm (void)
20415 /* P, U and L bits are part of bitmask. */
20416 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20417 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20419 if (inst
.operands
[1].issingle
)
20421 do_vfp_nsyn_ldm_stm (is_dbmode
);
20425 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20426 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20428 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20429 _("register list must contain at least 1 and at most 16 "
20432 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20433 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20437 inst
.instruction
|= offsetbits
;
20439 do_vfp_cond_or_thumb ();
20443 do_neon_ldr_str (void)
20445 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20447 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20448 And is UNPREDICTABLE in thumb mode. */
20450 && inst
.operands
[1].reg
== REG_PC
20451 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20454 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20455 else if (warn_on_deprecated
)
20456 as_tsktsk (_("Use of PC here is deprecated"));
20459 if (inst
.operands
[0].issingle
)
20462 do_vfp_nsyn_opcode ("flds");
20464 do_vfp_nsyn_opcode ("fsts");
20466 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20467 if (inst
.vectype
.el
[0].size
== 16)
20468 do_scalar_fp16_v82_encode ();
20473 do_vfp_nsyn_opcode ("fldd");
20475 do_vfp_nsyn_opcode ("fstd");
20480 do_t_vldr_vstr_sysreg (void)
20482 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20483 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20485 /* Use of PC is UNPREDICTABLE. */
20486 if (inst
.operands
[1].reg
== REG_PC
)
20487 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20489 if (inst
.operands
[1].immisreg
)
20490 inst
.error
= _("instruction does not accept register index");
20492 if (!inst
.operands
[1].isreg
)
20493 inst
.error
= _("instruction does not accept PC-relative addressing");
20495 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20496 inst
.error
= _("immediate value out of range");
20498 inst
.instruction
= 0xec000f80;
20500 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20501 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20502 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20503 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20507 do_vldr_vstr (void)
20509 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20511 /* VLDR/VSTR (System Register). */
20514 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20515 as_bad (_("Instruction not permitted on this architecture"));
20517 do_t_vldr_vstr_sysreg ();
20522 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20523 as_bad (_("Instruction not permitted on this architecture"));
20524 do_neon_ldr_str ();
20528 /* "interleave" version also handles non-interleaving register VLD1/VST1
20532 do_neon_ld_st_interleave (void)
20534 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20535 N_8
| N_16
| N_32
| N_64
);
20536 unsigned alignbits
= 0;
20538 /* The bits in this table go:
20539 0: register stride of one (0) or two (1)
20540 1,2: register list length, minus one (1, 2, 3, 4).
20541 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20542 We use -1 for invalid entries. */
20543 const int typetable
[] =
20545 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20546 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20547 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20548 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20552 if (et
.type
== NT_invtype
)
20555 if (inst
.operands
[1].immisalign
)
20556 switch (inst
.operands
[1].imm
>> 8)
20558 case 64: alignbits
= 1; break;
20560 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20561 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20562 goto bad_alignment
;
20566 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20567 goto bad_alignment
;
20572 first_error (_("bad alignment"));
20576 inst
.instruction
|= alignbits
<< 4;
20577 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20579 /* Bits [4:6] of the immediate in a list specifier encode register stride
20580 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20581 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20582 up the right value for "type" in a table based on this value and the given
20583 list style, then stick it back. */
20584 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20585 | (((inst
.instruction
>> 8) & 3) << 3);
20587 typebits
= typetable
[idx
];
20589 constraint (typebits
== -1, _("bad list type for instruction"));
20590 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20593 inst
.instruction
&= ~0xf00;
20594 inst
.instruction
|= typebits
<< 8;
20597 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20598 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20599 otherwise. The variable arguments are a list of pairs of legal (size, align)
20600 values, terminated with -1. */
20603 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20606 int result
= FAIL
, thissize
, thisalign
;
20608 if (!inst
.operands
[1].immisalign
)
20614 va_start (ap
, do_alignment
);
20618 thissize
= va_arg (ap
, int);
20619 if (thissize
== -1)
20621 thisalign
= va_arg (ap
, int);
20623 if (size
== thissize
&& align
== thisalign
)
20626 while (result
!= SUCCESS
);
20630 if (result
== SUCCESS
)
20633 first_error (_("unsupported alignment for instruction"));
20639 do_neon_ld_st_lane (void)
20641 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20642 int align_good
, do_alignment
= 0;
20643 int logsize
= neon_logbits (et
.size
);
20644 int align
= inst
.operands
[1].imm
>> 8;
20645 int n
= (inst
.instruction
>> 8) & 3;
20646 int max_el
= 64 / et
.size
;
20648 if (et
.type
== NT_invtype
)
20651 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20652 _("bad list length"));
20653 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20654 _("scalar index out of range"));
20655 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20657 _("stride of 2 unavailable when element size is 8"));
20661 case 0: /* VLD1 / VST1. */
20662 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20664 if (align_good
== FAIL
)
20668 unsigned alignbits
= 0;
20671 case 16: alignbits
= 0x1; break;
20672 case 32: alignbits
= 0x3; break;
20675 inst
.instruction
|= alignbits
<< 4;
20679 case 1: /* VLD2 / VST2. */
20680 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20681 16, 32, 32, 64, -1);
20682 if (align_good
== FAIL
)
20685 inst
.instruction
|= 1 << 4;
20688 case 2: /* VLD3 / VST3. */
20689 constraint (inst
.operands
[1].immisalign
,
20690 _("can't use alignment with this instruction"));
20693 case 3: /* VLD4 / VST4. */
20694 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20695 16, 64, 32, 64, 32, 128, -1);
20696 if (align_good
== FAIL
)
20700 unsigned alignbits
= 0;
20703 case 8: alignbits
= 0x1; break;
20704 case 16: alignbits
= 0x1; break;
20705 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20708 inst
.instruction
|= alignbits
<< 4;
20715 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20716 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20717 inst
.instruction
|= 1 << (4 + logsize
);
20719 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20720 inst
.instruction
|= logsize
<< 10;
20723 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20726 do_neon_ld_dup (void)
20728 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20729 int align_good
, do_alignment
= 0;
20731 if (et
.type
== NT_invtype
)
20734 switch ((inst
.instruction
>> 8) & 3)
20736 case 0: /* VLD1. */
20737 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20738 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20739 &do_alignment
, 16, 16, 32, 32, -1);
20740 if (align_good
== FAIL
)
20742 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20745 case 2: inst
.instruction
|= 1 << 5; break;
20746 default: first_error (_("bad list length")); return;
20748 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20751 case 1: /* VLD2. */
20752 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20753 &do_alignment
, 8, 16, 16, 32, 32, 64,
20755 if (align_good
== FAIL
)
20757 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20758 _("bad list length"));
20759 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20760 inst
.instruction
|= 1 << 5;
20761 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20764 case 2: /* VLD3. */
20765 constraint (inst
.operands
[1].immisalign
,
20766 _("can't use alignment with this instruction"));
20767 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20768 _("bad list length"));
20769 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20770 inst
.instruction
|= 1 << 5;
20771 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20774 case 3: /* VLD4. */
20776 int align
= inst
.operands
[1].imm
>> 8;
20777 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20778 16, 64, 32, 64, 32, 128, -1);
20779 if (align_good
== FAIL
)
20781 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20782 _("bad list length"));
20783 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20784 inst
.instruction
|= 1 << 5;
20785 if (et
.size
== 32 && align
== 128)
20786 inst
.instruction
|= 0x3 << 6;
20788 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20795 inst
.instruction
|= do_alignment
<< 4;
20798 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20799 apart from bits [11:4]. */
20802 do_neon_ldx_stx (void)
20804 if (inst
.operands
[1].isreg
)
20805 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20807 switch (NEON_LANE (inst
.operands
[0].imm
))
20809 case NEON_INTERLEAVE_LANES
:
20810 NEON_ENCODE (INTERLV
, inst
);
20811 do_neon_ld_st_interleave ();
20814 case NEON_ALL_LANES
:
20815 NEON_ENCODE (DUP
, inst
);
20816 if (inst
.instruction
== N_INV
)
20818 first_error ("only loads support such operands");
20825 NEON_ENCODE (LANE
, inst
);
20826 do_neon_ld_st_lane ();
20829 /* L bit comes from bit mask. */
20830 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20832 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20834 if (inst
.operands
[1].postind
)
20836 int postreg
= inst
.operands
[1].imm
& 0xf;
20837 constraint (!inst
.operands
[1].immisreg
,
20838 _("post-index must be a register"));
20839 constraint (postreg
== 0xd || postreg
== 0xf,
20840 _("bad register for post-index"));
20841 inst
.instruction
|= postreg
;
20845 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20846 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20847 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20850 if (inst
.operands
[1].writeback
)
20852 inst
.instruction
|= 0xd;
20855 inst
.instruction
|= 0xf;
20859 inst
.instruction
|= 0xf9000000;
20861 inst
.instruction
|= 0xf4000000;
20866 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20868 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20869 D register operands. */
20870 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20871 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20874 NEON_ENCODE (FPV8
, inst
);
20876 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20878 do_vfp_sp_dyadic ();
20880 /* ARMv8.2 fp16 instruction. */
20882 do_scalar_fp16_v82_encode ();
20885 do_vfp_dp_rd_rn_rm ();
20888 inst
.instruction
|= 0x100;
20890 inst
.instruction
|= 0xf0000000;
20896 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20898 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20899 first_error (_("invalid instruction shape"));
20905 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20906 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20908 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20911 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20914 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20918 do_vrint_1 (enum neon_cvt_mode mode
)
20920 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20921 struct neon_type_el et
;
20926 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20927 D register operands. */
20928 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20932 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20934 if (et
.type
!= NT_invtype
)
20936 /* VFP encodings. */
20937 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20938 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20939 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20941 NEON_ENCODE (FPV8
, inst
);
20942 if (rs
== NS_FF
|| rs
== NS_HH
)
20943 do_vfp_sp_monadic ();
20945 do_vfp_dp_rd_rm ();
20949 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20950 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20951 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20952 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20953 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20954 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20955 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20959 inst
.instruction
|= (rs
== NS_DD
) << 8;
20960 do_vfp_cond_or_thumb ();
20962 /* ARMv8.2 fp16 vrint instruction. */
20964 do_scalar_fp16_v82_encode ();
20968 /* Neon encodings (or something broken...). */
20970 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20972 if (et
.type
== NT_invtype
)
20975 if (!check_simd_pred_availability (TRUE
,
20976 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20979 NEON_ENCODE (FLOAT
, inst
);
20981 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20982 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20983 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20984 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20985 inst
.instruction
|= neon_quad (rs
) << 6;
20986 /* Mask off the original size bits and reencode them. */
20987 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20988 | neon_logbits (et
.size
) << 18);
20992 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20993 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20994 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20995 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20996 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20997 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20998 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21003 inst
.instruction
|= 0xfc000000;
21005 inst
.instruction
|= 0xf0000000;
21012 do_vrint_1 (neon_cvt_mode_x
);
21018 do_vrint_1 (neon_cvt_mode_z
);
21024 do_vrint_1 (neon_cvt_mode_r
);
21030 do_vrint_1 (neon_cvt_mode_a
);
21036 do_vrint_1 (neon_cvt_mode_n
);
21042 do_vrint_1 (neon_cvt_mode_p
);
21048 do_vrint_1 (neon_cvt_mode_m
);
21052 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21054 unsigned regno
= NEON_SCALAR_REG (opnd
);
21055 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21057 if (elsize
== 16 && elno
< 2 && regno
< 16)
21058 return regno
| (elno
<< 4);
21059 else if (elsize
== 32 && elno
== 0)
21062 first_error (_("scalar out of range"));
21069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21070 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21071 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21072 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21073 _("expression too complex"));
21074 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21075 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21076 _("immediate out of range"));
21079 if (!check_simd_pred_availability (TRUE
,
21080 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21083 if (inst
.operands
[2].isscalar
)
21085 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21086 first_error (_("invalid instruction shape"));
21087 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21088 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21089 N_KEY
| N_F16
| N_F32
).size
;
21090 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21092 inst
.instruction
= 0xfe000800;
21093 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21096 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21097 inst
.instruction
|= LOW4 (m
);
21098 inst
.instruction
|= HI1 (m
) << 5;
21099 inst
.instruction
|= neon_quad (rs
) << 6;
21100 inst
.instruction
|= rot
<< 20;
21101 inst
.instruction
|= (size
== 32) << 23;
21105 enum neon_shape rs
;
21106 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21107 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21109 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21111 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21112 N_KEY
| N_F16
| N_F32
).size
;
21113 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21114 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21115 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21116 as_tsktsk (BAD_MVE_SRCDEST
);
21118 neon_three_same (neon_quad (rs
), 0, -1);
21119 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21120 inst
.instruction
|= 0xfc200800;
21121 inst
.instruction
|= rot
<< 23;
21122 inst
.instruction
|= (size
== 32) << 20;
21129 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21130 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21131 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21132 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21133 _("expression too complex"));
21135 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21136 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21137 enum neon_shape rs
;
21138 struct neon_type_el et
;
21139 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21141 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21142 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21146 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21147 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21149 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21150 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21151 "operand makes instruction UNPREDICTABLE"));
21154 if (et
.type
== NT_invtype
)
21157 if (!check_simd_pred_availability (et
.type
== NT_float
,
21158 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21161 if (et
.type
== NT_float
)
21163 neon_three_same (neon_quad (rs
), 0, -1);
21164 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21165 inst
.instruction
|= 0xfc800800;
21166 inst
.instruction
|= (rot
== 270) << 24;
21167 inst
.instruction
|= (et
.size
== 32) << 20;
21171 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21172 inst
.instruction
= 0xfe000f00;
21173 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21174 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21176 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21177 inst
.instruction
|= (rot
== 270) << 12;
21178 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21179 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21180 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21185 /* Dot Product instructions encoding support. */
21188 do_neon_dotproduct (int unsigned_p
)
21190 enum neon_shape rs
;
21191 unsigned scalar_oprd2
= 0;
21194 if (inst
.cond
!= COND_ALWAYS
)
21195 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21196 "is UNPREDICTABLE"));
21198 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21201 /* Dot Product instructions are in three-same D/Q register format or the third
21202 operand can be a scalar index register. */
21203 if (inst
.operands
[2].isscalar
)
21205 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21206 high8
= 0xfe000000;
21207 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21211 high8
= 0xfc000000;
21212 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21216 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21218 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21220 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21221 Product instruction, so we pass 0 as the "ubit" parameter. And the
21222 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21223 neon_three_same (neon_quad (rs
), 0, 32);
21225 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21226 different NEON three-same encoding. */
21227 inst
.instruction
&= 0x00ffffff;
21228 inst
.instruction
|= high8
;
21229 /* Encode 'U' bit which indicates signedness. */
21230 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21231 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21232 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21233 the instruction encoding. */
21234 if (inst
.operands
[2].isscalar
)
21236 inst
.instruction
&= 0xffffffd0;
21237 inst
.instruction
|= LOW4 (scalar_oprd2
);
21238 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21242 /* Dot Product instructions for signed integer. */
21245 do_neon_dotproduct_s (void)
21247 return do_neon_dotproduct (0);
21250 /* Dot Product instructions for unsigned integer. */
21253 do_neon_dotproduct_u (void)
21255 return do_neon_dotproduct (1);
21258 /* Crypto v1 instructions. */
21260 do_crypto_2op_1 (unsigned elttype
, int op
)
21262 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21264 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21270 NEON_ENCODE (INTEGER
, inst
);
21271 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21274 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21276 inst
.instruction
|= op
<< 6;
21279 inst
.instruction
|= 0xfc000000;
21281 inst
.instruction
|= 0xf0000000;
21285 do_crypto_3op_1 (int u
, int op
)
21287 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21289 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21290 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21295 NEON_ENCODE (INTEGER
, inst
);
21296 neon_three_same (1, u
, 8 << op
);
21302 do_crypto_2op_1 (N_8
, 0);
21308 do_crypto_2op_1 (N_8
, 1);
21314 do_crypto_2op_1 (N_8
, 2);
21320 do_crypto_2op_1 (N_8
, 3);
21326 do_crypto_3op_1 (0, 0);
21332 do_crypto_3op_1 (0, 1);
21338 do_crypto_3op_1 (0, 2);
21344 do_crypto_3op_1 (0, 3);
21350 do_crypto_3op_1 (1, 0);
21356 do_crypto_3op_1 (1, 1);
21360 do_sha256su1 (void)
21362 do_crypto_3op_1 (1, 2);
21368 do_crypto_2op_1 (N_32
, -1);
21374 do_crypto_2op_1 (N_32
, 0);
21378 do_sha256su0 (void)
21380 do_crypto_2op_1 (N_32
, 1);
21384 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21386 unsigned int Rd
= inst
.operands
[0].reg
;
21387 unsigned int Rn
= inst
.operands
[1].reg
;
21388 unsigned int Rm
= inst
.operands
[2].reg
;
21390 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21391 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21392 inst
.instruction
|= LOW4 (Rn
) << 16;
21393 inst
.instruction
|= LOW4 (Rm
);
21394 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21395 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21397 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21398 as_warn (UNPRED_REG ("r15"));
21440 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21442 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21443 do_vfp_sp_dp_cvt ();
21444 do_vfp_cond_or_thumb ();
21448 /* Overall per-instruction processing. */
21450 /* We need to be able to fix up arbitrary expressions in some statements.
21451 This is so that we can handle symbols that are an arbitrary distance from
21452 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21453 which returns part of an address in a form which will be valid for
21454 a data instruction. We do this by pushing the expression into a symbol
21455 in the expr_section, and creating a fix for that. */
21458 fix_new_arm (fragS
* frag
,
21472 /* Create an absolute valued symbol, so we have something to
21473 refer to in the object file. Unfortunately for us, gas's
21474 generic expression parsing will already have folded out
21475 any use of .set foo/.type foo %function that may have
21476 been used to set type information of the target location,
21477 that's being specified symbolically. We have to presume
21478 the user knows what they are doing. */
21482 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21484 symbol
= symbol_find_or_make (name
);
21485 S_SET_SEGMENT (symbol
, absolute_section
);
21486 symbol_set_frag (symbol
, &zero_address_frag
);
21487 S_SET_VALUE (symbol
, exp
->X_add_number
);
21488 exp
->X_op
= O_symbol
;
21489 exp
->X_add_symbol
= symbol
;
21490 exp
->X_add_number
= 0;
21496 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21497 (enum bfd_reloc_code_real
) reloc
);
21501 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21502 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21506 /* Mark whether the fix is to a THUMB instruction, or an ARM
21508 new_fix
->tc_fix_data
= thumb_mode
;
21511 /* Create a frg for an instruction requiring relaxation. */
21513 output_relax_insn (void)
21519 /* The size of the instruction is unknown, so tie the debug info to the
21520 start of the instruction. */
21521 dwarf2_emit_insn (0);
21523 switch (inst
.relocs
[0].exp
.X_op
)
21526 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21527 offset
= inst
.relocs
[0].exp
.X_add_number
;
21531 offset
= inst
.relocs
[0].exp
.X_add_number
;
21534 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21538 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21539 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21540 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21543 /* Write a 32-bit thumb instruction to buf. */
21545 put_thumb32_insn (char * buf
, unsigned long insn
)
21547 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21548 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21552 output_inst (const char * str
)
21558 as_bad ("%s -- `%s'", inst
.error
, str
);
21563 output_relax_insn ();
21566 if (inst
.size
== 0)
21569 to
= frag_more (inst
.size
);
21570 /* PR 9814: Record the thumb mode into the current frag so that we know
21571 what type of NOP padding to use, if necessary. We override any previous
21572 setting so that if the mode has changed then the NOPS that we use will
21573 match the encoding of the last instruction in the frag. */
21574 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21576 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21578 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21579 put_thumb32_insn (to
, inst
.instruction
);
21581 else if (inst
.size
> INSN_SIZE
)
21583 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21584 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21585 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21588 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21591 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21593 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21594 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21595 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21596 inst
.relocs
[r
].type
);
21599 dwarf2_emit_insn (inst
.size
);
21603 output_it_inst (int cond
, int mask
, char * to
)
21605 unsigned long instruction
= 0xbf00;
21608 instruction
|= mask
;
21609 instruction
|= cond
<< 4;
21613 to
= frag_more (2);
21615 dwarf2_emit_insn (2);
21619 md_number_to_chars (to
, instruction
, 2);
21624 /* Tag values used in struct asm_opcode's tag field. */
21627 OT_unconditional
, /* Instruction cannot be conditionalized.
21628 The ARM condition field is still 0xE. */
21629 OT_unconditionalF
, /* Instruction cannot be conditionalized
21630 and carries 0xF in its ARM condition field. */
21631 OT_csuffix
, /* Instruction takes a conditional suffix. */
21632 OT_csuffixF
, /* Some forms of the instruction take a scalar
21633 conditional suffix, others place 0xF where the
21634 condition field would be, others take a vector
21635 conditional suffix. */
21636 OT_cinfix3
, /* Instruction takes a conditional infix,
21637 beginning at character index 3. (In
21638 unified mode, it becomes a suffix.) */
21639 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21640 tsts, cmps, cmns, and teqs. */
21641 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21642 character index 3, even in unified mode. Used for
21643 legacy instructions where suffix and infix forms
21644 may be ambiguous. */
21645 OT_csuf_or_in3
, /* Instruction takes either a conditional
21646 suffix or an infix at character index 3. */
21647 OT_odd_infix_unc
, /* This is the unconditional variant of an
21648 instruction that takes a conditional infix
21649 at an unusual position. In unified mode,
21650 this variant will accept a suffix. */
21651 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21652 are the conditional variants of instructions that
21653 take conditional infixes in unusual positions.
21654 The infix appears at character index
21655 (tag - OT_odd_infix_0). These are not accepted
21656 in unified mode. */
21659 /* Subroutine of md_assemble, responsible for looking up the primary
21660 opcode from the mnemonic the user wrote. STR points to the
21661 beginning of the mnemonic.
21663 This is not simply a hash table lookup, because of conditional
21664 variants. Most instructions have conditional variants, which are
21665 expressed with a _conditional affix_ to the mnemonic. If we were
21666 to encode each conditional variant as a literal string in the opcode
21667 table, it would have approximately 20,000 entries.
21669 Most mnemonics take this affix as a suffix, and in unified syntax,
21670 'most' is upgraded to 'all'. However, in the divided syntax, some
21671 instructions take the affix as an infix, notably the s-variants of
21672 the arithmetic instructions. Of those instructions, all but six
21673 have the infix appear after the third character of the mnemonic.
21675 Accordingly, the algorithm for looking up primary opcodes given
21678 1. Look up the identifier in the opcode table.
21679 If we find a match, go to step U.
21681 2. Look up the last two characters of the identifier in the
21682 conditions table. If we find a match, look up the first N-2
21683 characters of the identifier in the opcode table. If we
21684 find a match, go to step CE.
21686 3. Look up the fourth and fifth characters of the identifier in
21687 the conditions table. If we find a match, extract those
21688 characters from the identifier, and look up the remaining
21689 characters in the opcode table. If we find a match, go
21694 U. Examine the tag field of the opcode structure, in case this is
21695 one of the six instructions with its conditional infix in an
21696 unusual place. If it is, the tag tells us where to find the
21697 infix; look it up in the conditions table and set inst.cond
21698 accordingly. Otherwise, this is an unconditional instruction.
21699 Again set inst.cond accordingly. Return the opcode structure.
21701 CE. Examine the tag field to make sure this is an instruction that
21702 should receive a conditional suffix. If it is not, fail.
21703 Otherwise, set inst.cond from the suffix we already looked up,
21704 and return the opcode structure.
21706 CM. Examine the tag field to make sure this is an instruction that
21707 should receive a conditional infix after the third character.
21708 If it is not, fail. Otherwise, undo the edits to the current
21709 line of input and proceed as for case CE. */
21711 static const struct asm_opcode
*
21712 opcode_lookup (char **str
)
21716 const struct asm_opcode
*opcode
;
21717 const struct asm_cond
*cond
;
21720 /* Scan up to the end of the mnemonic, which must end in white space,
21721 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21722 for (base
= end
= *str
; *end
!= '\0'; end
++)
21723 if (*end
== ' ' || *end
== '.')
21729 /* Handle a possible width suffix and/or Neon type suffix. */
21734 /* The .w and .n suffixes are only valid if the unified syntax is in
21736 if (unified_syntax
&& end
[1] == 'w')
21738 else if (unified_syntax
&& end
[1] == 'n')
21743 inst
.vectype
.elems
= 0;
21745 *str
= end
+ offset
;
21747 if (end
[offset
] == '.')
21749 /* See if we have a Neon type suffix (possible in either unified or
21750 non-unified ARM syntax mode). */
21751 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21754 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21760 /* Look for unaffixed or special-case affixed mnemonic. */
21761 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21766 if (opcode
->tag
< OT_odd_infix_0
)
21768 inst
.cond
= COND_ALWAYS
;
21772 if (warn_on_deprecated
&& unified_syntax
)
21773 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21774 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21775 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21778 inst
.cond
= cond
->value
;
21781 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21783 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21785 if (end
- base
< 2)
21788 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21789 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21791 /* If this opcode can not be vector predicated then don't accept it with a
21792 vector predication code. */
21793 if (opcode
&& !opcode
->mayBeVecPred
)
21796 if (!opcode
|| !cond
)
21798 /* Cannot have a conditional suffix on a mnemonic of less than two
21800 if (end
- base
< 3)
21803 /* Look for suffixed mnemonic. */
21805 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21806 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21810 if (opcode
&& cond
)
21813 switch (opcode
->tag
)
21815 case OT_cinfix3_legacy
:
21816 /* Ignore conditional suffixes matched on infix only mnemonics. */
21820 case OT_cinfix3_deprecated
:
21821 case OT_odd_infix_unc
:
21822 if (!unified_syntax
)
21824 /* Fall through. */
21828 case OT_csuf_or_in3
:
21829 inst
.cond
= cond
->value
;
21832 case OT_unconditional
:
21833 case OT_unconditionalF
:
21835 inst
.cond
= cond
->value
;
21838 /* Delayed diagnostic. */
21839 inst
.error
= BAD_COND
;
21840 inst
.cond
= COND_ALWAYS
;
21849 /* Cannot have a usual-position infix on a mnemonic of less than
21850 six characters (five would be a suffix). */
21851 if (end
- base
< 6)
21854 /* Look for infixed mnemonic in the usual position. */
21856 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21860 memcpy (save
, affix
, 2);
21861 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21862 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21864 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21865 memcpy (affix
, save
, 2);
21868 && (opcode
->tag
== OT_cinfix3
21869 || opcode
->tag
== OT_cinfix3_deprecated
21870 || opcode
->tag
== OT_csuf_or_in3
21871 || opcode
->tag
== OT_cinfix3_legacy
))
21874 if (warn_on_deprecated
&& unified_syntax
21875 && (opcode
->tag
== OT_cinfix3
21876 || opcode
->tag
== OT_cinfix3_deprecated
))
21877 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21879 inst
.cond
= cond
->value
;
21886 /* This function generates an initial IT instruction, leaving its block
21887 virtually open for the new instructions. Eventually,
21888 the mask will be updated by now_pred_add_mask () each time
21889 a new instruction needs to be included in the IT block.
21890 Finally, the block is closed with close_automatic_it_block ().
21891 The block closure can be requested either from md_assemble (),
21892 a tencode (), or due to a label hook. */
21895 new_automatic_it_block (int cond
)
21897 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21898 now_pred
.mask
= 0x18;
21899 now_pred
.cc
= cond
;
21900 now_pred
.block_length
= 1;
21901 mapping_state (MAP_THUMB
);
21902 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21903 now_pred
.warn_deprecated
= FALSE
;
21904 now_pred
.insn_cond
= TRUE
;
21907 /* Close an automatic IT block.
21908 See comments in new_automatic_it_block (). */
21911 close_automatic_it_block (void)
21913 now_pred
.mask
= 0x10;
21914 now_pred
.block_length
= 0;
21917 /* Update the mask of the current automatically-generated IT
21918 instruction. See comments in new_automatic_it_block (). */
21921 now_pred_add_mask (int cond
)
21923 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21924 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21925 | ((bitvalue) << (nbit)))
21926 const int resulting_bit
= (cond
& 1);
21928 now_pred
.mask
&= 0xf;
21929 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21931 (5 - now_pred
.block_length
));
21932 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21934 ((5 - now_pred
.block_length
) - 1));
21935 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21938 #undef SET_BIT_VALUE
21941 /* The IT blocks handling machinery is accessed through the these functions:
21942 it_fsm_pre_encode () from md_assemble ()
21943 set_pred_insn_type () optional, from the tencode functions
21944 set_pred_insn_type_last () ditto
21945 in_pred_block () ditto
21946 it_fsm_post_encode () from md_assemble ()
21947 force_automatic_it_block_close () from label handling functions
21950 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21951 initializing the IT insn type with a generic initial value depending
21952 on the inst.condition.
21953 2) During the tencode function, two things may happen:
21954 a) The tencode function overrides the IT insn type by
21955 calling either set_pred_insn_type (type) or
21956 set_pred_insn_type_last ().
21957 b) The tencode function queries the IT block state by
21958 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21960 Both set_pred_insn_type and in_pred_block run the internal FSM state
21961 handling function (handle_pred_state), because: a) setting the IT insn
21962 type may incur in an invalid state (exiting the function),
21963 and b) querying the state requires the FSM to be updated.
21964 Specifically we want to avoid creating an IT block for conditional
21965 branches, so it_fsm_pre_encode is actually a guess and we can't
21966 determine whether an IT block is required until the tencode () routine
21967 has decided what type of instruction this actually it.
21968 Because of this, if set_pred_insn_type and in_pred_block have to be
21969 used, set_pred_insn_type has to be called first.
21971 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21972 that determines the insn IT type depending on the inst.cond code.
21973 When a tencode () routine encodes an instruction that can be
21974 either outside an IT block, or, in the case of being inside, has to be
21975 the last one, set_pred_insn_type_last () will determine the proper
21976 IT instruction type based on the inst.cond code. Otherwise,
21977 set_pred_insn_type can be called for overriding that logic or
21978 for covering other cases.
21980 Calling handle_pred_state () may not transition the IT block state to
21981 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21982 still queried. Instead, if the FSM determines that the state should
21983 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21984 after the tencode () function: that's what it_fsm_post_encode () does.
21986 Since in_pred_block () calls the state handling function to get an
21987 updated state, an error may occur (due to invalid insns combination).
21988 In that case, inst.error is set.
21989 Therefore, inst.error has to be checked after the execution of
21990 the tencode () routine.
21992 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21993 any pending state change (if any) that didn't take place in
21994 handle_pred_state () as explained above. */
21997 it_fsm_pre_encode (void)
21999 if (inst
.cond
!= COND_ALWAYS
)
22000 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22002 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22004 now_pred
.state_handled
= 0;
22007 /* IT state FSM handling function. */
22008 /* MVE instructions and non-MVE instructions are handled differently because of
22009 the introduction of VPT blocks.
22010 Specifications say that any non-MVE instruction inside a VPT block is
22011 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22012 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22013 few exceptions we have MVE_UNPREDICABLE_INSN.
22014 The error messages provided depending on the different combinations possible
22015 are described in the cases below:
22016 For 'most' MVE instructions:
22017 1) In an IT block, with an IT code: syntax error
22018 2) In an IT block, with a VPT code: error: must be in a VPT block
22019 3) In an IT block, with no code: warning: UNPREDICTABLE
22020 4) In a VPT block, with an IT code: syntax error
22021 5) In a VPT block, with a VPT code: OK!
22022 6) In a VPT block, with no code: error: missing code
22023 7) Outside a pred block, with an IT code: error: syntax error
22024 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22025 9) Outside a pred block, with no code: OK!
22026 For non-MVE instructions:
22027 10) In an IT block, with an IT code: OK!
22028 11) In an IT block, with a VPT code: syntax error
22029 12) In an IT block, with no code: error: missing code
22030 13) In a VPT block, with an IT code: error: should be in an IT block
22031 14) In a VPT block, with a VPT code: syntax error
22032 15) In a VPT block, with no code: UNPREDICTABLE
22033 16) Outside a pred block, with an IT code: error: should be in an IT block
22034 17) Outside a pred block, with a VPT code: syntax error
22035 18) Outside a pred block, with no code: OK!
22040 handle_pred_state (void)
22042 now_pred
.state_handled
= 1;
22043 now_pred
.insn_cond
= FALSE
;
22045 switch (now_pred
.state
)
22047 case OUTSIDE_PRED_BLOCK
:
22048 switch (inst
.pred_insn_type
)
22050 case MVE_UNPREDICABLE_INSN
:
22051 case MVE_OUTSIDE_PRED_INSN
:
22052 if (inst
.cond
< COND_ALWAYS
)
22054 /* Case 7: Outside a pred block, with an IT code: error: syntax
22056 inst
.error
= BAD_SYNTAX
;
22059 /* Case 9: Outside a pred block, with no code: OK! */
22061 case OUTSIDE_PRED_INSN
:
22062 if (inst
.cond
> COND_ALWAYS
)
22064 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22066 inst
.error
= BAD_SYNTAX
;
22069 /* Case 18: Outside a pred block, with no code: OK! */
22072 case INSIDE_VPT_INSN
:
22073 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22075 inst
.error
= BAD_OUT_VPT
;
22078 case INSIDE_IT_INSN
:
22079 case INSIDE_IT_LAST_INSN
:
22080 if (inst
.cond
< COND_ALWAYS
)
22082 /* Case 16: Outside a pred block, with an IT code: error: should
22083 be in an IT block. */
22084 if (thumb_mode
== 0)
22087 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22088 as_tsktsk (_("Warning: conditional outside an IT block"\
22093 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22094 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22096 /* Automatically generate the IT instruction. */
22097 new_automatic_it_block (inst
.cond
);
22098 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22099 close_automatic_it_block ();
22103 inst
.error
= BAD_OUT_IT
;
22109 else if (inst
.cond
> COND_ALWAYS
)
22111 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22113 inst
.error
= BAD_SYNTAX
;
22118 case IF_INSIDE_IT_LAST_INSN
:
22119 case NEUTRAL_IT_INSN
:
22123 if (inst
.cond
!= COND_ALWAYS
)
22124 first_error (BAD_SYNTAX
);
22125 now_pred
.state
= MANUAL_PRED_BLOCK
;
22126 now_pred
.block_length
= 0;
22127 now_pred
.type
= VECTOR_PRED
;
22131 now_pred
.state
= MANUAL_PRED_BLOCK
;
22132 now_pred
.block_length
= 0;
22133 now_pred
.type
= SCALAR_PRED
;
22138 case AUTOMATIC_PRED_BLOCK
:
22139 /* Three things may happen now:
22140 a) We should increment current it block size;
22141 b) We should close current it block (closing insn or 4 insns);
22142 c) We should close current it block and start a new one (due
22143 to incompatible conditions or
22144 4 insns-length block reached). */
22146 switch (inst
.pred_insn_type
)
22148 case INSIDE_VPT_INSN
:
22150 case MVE_UNPREDICABLE_INSN
:
22151 case MVE_OUTSIDE_PRED_INSN
:
22153 case OUTSIDE_PRED_INSN
:
22154 /* The closure of the block shall happen immediately,
22155 so any in_pred_block () call reports the block as closed. */
22156 force_automatic_it_block_close ();
22159 case INSIDE_IT_INSN
:
22160 case INSIDE_IT_LAST_INSN
:
22161 case IF_INSIDE_IT_LAST_INSN
:
22162 now_pred
.block_length
++;
22164 if (now_pred
.block_length
> 4
22165 || !now_pred_compatible (inst
.cond
))
22167 force_automatic_it_block_close ();
22168 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22169 new_automatic_it_block (inst
.cond
);
22173 now_pred
.insn_cond
= TRUE
;
22174 now_pred_add_mask (inst
.cond
);
22177 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22178 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22179 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22180 close_automatic_it_block ();
22183 case NEUTRAL_IT_INSN
:
22184 now_pred
.block_length
++;
22185 now_pred
.insn_cond
= TRUE
;
22187 if (now_pred
.block_length
> 4)
22188 force_automatic_it_block_close ();
22190 now_pred_add_mask (now_pred
.cc
& 1);
22194 close_automatic_it_block ();
22195 now_pred
.state
= MANUAL_PRED_BLOCK
;
22200 case MANUAL_PRED_BLOCK
:
22203 if (now_pred
.type
== SCALAR_PRED
)
22205 /* Check conditional suffixes. */
22206 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22207 now_pred
.mask
<<= 1;
22208 now_pred
.mask
&= 0x1f;
22209 is_last
= (now_pred
.mask
== 0x10);
22213 now_pred
.cc
^= (now_pred
.mask
>> 4);
22214 cond
= now_pred
.cc
+ 0xf;
22215 now_pred
.mask
<<= 1;
22216 now_pred
.mask
&= 0x1f;
22217 is_last
= now_pred
.mask
== 0x10;
22219 now_pred
.insn_cond
= TRUE
;
22221 switch (inst
.pred_insn_type
)
22223 case OUTSIDE_PRED_INSN
:
22224 if (now_pred
.type
== SCALAR_PRED
)
22226 if (inst
.cond
== COND_ALWAYS
)
22228 /* Case 12: In an IT block, with no code: error: missing
22230 inst
.error
= BAD_NOT_IT
;
22233 else if (inst
.cond
> COND_ALWAYS
)
22235 /* Case 11: In an IT block, with a VPT code: syntax error.
22237 inst
.error
= BAD_SYNTAX
;
22240 else if (thumb_mode
)
22242 /* This is for some special cases where a non-MVE
22243 instruction is not allowed in an IT block, such as cbz,
22244 but are put into one with a condition code.
22245 You could argue this should be a syntax error, but we
22246 gave the 'not allowed in IT block' diagnostic in the
22247 past so we will keep doing so. */
22248 inst
.error
= BAD_NOT_IT
;
22255 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22256 as_tsktsk (MVE_NOT_VPT
);
22259 case MVE_OUTSIDE_PRED_INSN
:
22260 if (now_pred
.type
== SCALAR_PRED
)
22262 if (inst
.cond
== COND_ALWAYS
)
22264 /* Case 3: In an IT block, with no code: warning:
22266 as_tsktsk (MVE_NOT_IT
);
22269 else if (inst
.cond
< COND_ALWAYS
)
22271 /* Case 1: In an IT block, with an IT code: syntax error.
22273 inst
.error
= BAD_SYNTAX
;
22281 if (inst
.cond
< COND_ALWAYS
)
22283 /* Case 4: In a VPT block, with an IT code: syntax error.
22285 inst
.error
= BAD_SYNTAX
;
22288 else if (inst
.cond
== COND_ALWAYS
)
22290 /* Case 6: In a VPT block, with no code: error: missing
22292 inst
.error
= BAD_NOT_VPT
;
22300 case MVE_UNPREDICABLE_INSN
:
22301 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22303 case INSIDE_IT_INSN
:
22304 if (inst
.cond
> COND_ALWAYS
)
22306 /* Case 11: In an IT block, with a VPT code: syntax error. */
22307 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22308 inst
.error
= BAD_SYNTAX
;
22311 else if (now_pred
.type
== SCALAR_PRED
)
22313 /* Case 10: In an IT block, with an IT code: OK! */
22314 if (cond
!= inst
.cond
)
22316 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22323 /* Case 13: In a VPT block, with an IT code: error: should be
22325 inst
.error
= BAD_OUT_IT
;
22330 case INSIDE_VPT_INSN
:
22331 if (now_pred
.type
== SCALAR_PRED
)
22333 /* Case 2: In an IT block, with a VPT code: error: must be in a
22335 inst
.error
= BAD_OUT_VPT
;
22338 /* Case 5: In a VPT block, with a VPT code: OK! */
22339 else if (cond
!= inst
.cond
)
22341 inst
.error
= BAD_VPT_COND
;
22345 case INSIDE_IT_LAST_INSN
:
22346 case IF_INSIDE_IT_LAST_INSN
:
22347 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22349 /* Case 4: In a VPT block, with an IT code: syntax error. */
22350 /* Case 11: In an IT block, with a VPT code: syntax error. */
22351 inst
.error
= BAD_SYNTAX
;
22354 else if (cond
!= inst
.cond
)
22356 inst
.error
= BAD_IT_COND
;
22361 inst
.error
= BAD_BRANCH
;
22366 case NEUTRAL_IT_INSN
:
22367 /* The BKPT instruction is unconditional even in a IT or VPT
22372 if (now_pred
.type
== SCALAR_PRED
)
22374 inst
.error
= BAD_IT_IT
;
22377 /* fall through. */
22379 if (inst
.cond
== COND_ALWAYS
)
22381 /* Executing a VPT/VPST instruction inside an IT block or a
22382 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22384 if (now_pred
.type
== SCALAR_PRED
)
22385 as_tsktsk (MVE_NOT_IT
);
22387 as_tsktsk (MVE_NOT_VPT
);
22392 /* VPT/VPST do not accept condition codes. */
22393 inst
.error
= BAD_SYNTAX
;
22404 struct depr_insn_mask
22406 unsigned long pattern
;
22407 unsigned long mask
;
22408 const char* description
;
22411 /* List of 16-bit instruction patterns deprecated in an IT block in
22413 static const struct depr_insn_mask depr_it_insns
[] = {
22414 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22415 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22416 { 0xa000, 0xb800, N_("ADR") },
22417 { 0x4800, 0xf800, N_("Literal loads") },
22418 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22419 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22420 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22421 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22422 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22427 it_fsm_post_encode (void)
22431 if (!now_pred
.state_handled
)
22432 handle_pred_state ();
22434 if (now_pred
.insn_cond
22435 && !now_pred
.warn_deprecated
22436 && warn_on_deprecated
22437 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22438 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22440 if (inst
.instruction
>= 0x10000)
22442 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22443 "performance deprecated in ARMv8-A and ARMv8-R"));
22444 now_pred
.warn_deprecated
= TRUE
;
22448 const struct depr_insn_mask
*p
= depr_it_insns
;
22450 while (p
->mask
!= 0)
22452 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22454 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22455 "instructions of the following class are "
22456 "performance deprecated in ARMv8-A and "
22457 "ARMv8-R: %s"), p
->description
);
22458 now_pred
.warn_deprecated
= TRUE
;
22466 if (now_pred
.block_length
> 1)
22468 as_tsktsk (_("IT blocks containing more than one conditional "
22469 "instruction are performance deprecated in ARMv8-A and "
22471 now_pred
.warn_deprecated
= TRUE
;
22475 is_last
= (now_pred
.mask
== 0x10);
22478 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22484 force_automatic_it_block_close (void)
22486 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22488 close_automatic_it_block ();
22489 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22495 in_pred_block (void)
22497 if (!now_pred
.state_handled
)
22498 handle_pred_state ();
22500 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22503 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22504 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22505 here, hence the "known" in the function name. */
22508 known_t32_only_insn (const struct asm_opcode
*opcode
)
22510 /* Original Thumb-1 wide instruction. */
22511 if (opcode
->tencode
== do_t_blx
22512 || opcode
->tencode
== do_t_branch23
22513 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22514 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22517 /* Wide-only instruction added to ARMv8-M Baseline. */
22518 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22519 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22520 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22521 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22527 /* Whether wide instruction variant can be used if available for a valid OPCODE
22531 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22533 if (known_t32_only_insn (opcode
))
22536 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22537 of variant T3 of B.W is checked in do_t_branch. */
22538 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22539 && opcode
->tencode
== do_t_branch
)
22542 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22543 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22544 && opcode
->tencode
== do_t_mov_cmp
22545 /* Make sure CMP instruction is not affected. */
22546 && opcode
->aencode
== do_mov
)
22549 /* Wide instruction variants of all instructions with narrow *and* wide
22550 variants become available with ARMv6t2. Other opcodes are either
22551 narrow-only or wide-only and are thus available if OPCODE is valid. */
22552 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22555 /* OPCODE with narrow only instruction variant or wide variant not
22561 md_assemble (char *str
)
22564 const struct asm_opcode
* opcode
;
22566 /* Align the previous label if needed. */
22567 if (last_label_seen
!= NULL
)
22569 symbol_set_frag (last_label_seen
, frag_now
);
22570 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22571 S_SET_SEGMENT (last_label_seen
, now_seg
);
22574 memset (&inst
, '\0', sizeof (inst
));
22576 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22577 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22579 opcode
= opcode_lookup (&p
);
22582 /* It wasn't an instruction, but it might be a register alias of
22583 the form alias .req reg, or a Neon .dn/.qn directive. */
22584 if (! create_register_alias (str
, p
)
22585 && ! create_neon_reg_alias (str
, p
))
22586 as_bad (_("bad instruction `%s'"), str
);
22591 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22592 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22594 /* The value which unconditional instructions should have in place of the
22595 condition field. */
22596 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22600 arm_feature_set variant
;
22602 variant
= cpu_variant
;
22603 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22604 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22605 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22606 /* Check that this instruction is supported for this CPU. */
22607 if (!opcode
->tvariant
22608 || (thumb_mode
== 1
22609 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22611 if (opcode
->tencode
== do_t_swi
)
22612 as_bad (_("SVC is not permitted on this architecture"));
22614 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22617 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22618 && opcode
->tencode
!= do_t_branch
)
22620 as_bad (_("Thumb does not support conditional execution"));
22624 /* Two things are addressed here:
22625 1) Implicit require narrow instructions on Thumb-1.
22626 This avoids relaxation accidentally introducing Thumb-2
22628 2) Reject wide instructions in non Thumb-2 cores.
22630 Only instructions with narrow and wide variants need to be handled
22631 but selecting all non wide-only instructions is easier. */
22632 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22633 && !t32_insn_ok (variant
, opcode
))
22635 if (inst
.size_req
== 0)
22637 else if (inst
.size_req
== 4)
22639 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22640 as_bad (_("selected processor does not support 32bit wide "
22641 "variant of instruction `%s'"), str
);
22643 as_bad (_("selected processor does not support `%s' in "
22644 "Thumb-2 mode"), str
);
22649 inst
.instruction
= opcode
->tvalue
;
22651 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22653 /* Prepare the pred_insn_type for those encodings that don't set
22655 it_fsm_pre_encode ();
22657 opcode
->tencode ();
22659 it_fsm_post_encode ();
22662 if (!(inst
.error
|| inst
.relax
))
22664 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22665 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22666 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22668 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22673 /* Something has gone badly wrong if we try to relax a fixed size
22675 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22677 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22678 *opcode
->tvariant
);
22679 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22680 set those bits when Thumb-2 32-bit instructions are seen. The impact
22681 of relaxable instructions will be considered later after we finish all
22683 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22684 variant
= arm_arch_none
;
22686 variant
= cpu_variant
;
22687 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22688 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22691 check_neon_suffixes
;
22695 mapping_state (MAP_THUMB
);
22698 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22702 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22703 is_bx
= (opcode
->aencode
== do_bx
);
22705 /* Check that this instruction is supported for this CPU. */
22706 if (!(is_bx
&& fix_v4bx
)
22707 && !(opcode
->avariant
&&
22708 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22710 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22715 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22719 inst
.instruction
= opcode
->avalue
;
22720 if (opcode
->tag
== OT_unconditionalF
)
22721 inst
.instruction
|= 0xFU
<< 28;
22723 inst
.instruction
|= inst
.cond
<< 28;
22724 inst
.size
= INSN_SIZE
;
22725 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22727 it_fsm_pre_encode ();
22728 opcode
->aencode ();
22729 it_fsm_post_encode ();
22731 /* Arm mode bx is marked as both v4T and v5 because it's still required
22732 on a hypothetical non-thumb v5 core. */
22734 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22736 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22737 *opcode
->avariant
);
22739 check_neon_suffixes
;
22743 mapping_state (MAP_ARM
);
22748 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22756 check_pred_blocks_finished (void)
22761 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22762 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22763 == MANUAL_PRED_BLOCK
)
22765 if (now_pred
.type
== SCALAR_PRED
)
22766 as_warn (_("section '%s' finished with an open IT block."),
22769 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22773 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22775 if (now_pred
.type
== SCALAR_PRED
)
22776 as_warn (_("file finished with an open IT block."));
22778 as_warn (_("file finished with an open VPT/VPST block."));
22783 /* Various frobbings of labels and their addresses. */
22786 arm_start_line_hook (void)
22788 last_label_seen
= NULL
;
22792 arm_frob_label (symbolS
* sym
)
22794 last_label_seen
= sym
;
22796 ARM_SET_THUMB (sym
, thumb_mode
);
22798 #if defined OBJ_COFF || defined OBJ_ELF
22799 ARM_SET_INTERWORK (sym
, support_interwork
);
22802 force_automatic_it_block_close ();
22804 /* Note - do not allow local symbols (.Lxxx) to be labelled
22805 as Thumb functions. This is because these labels, whilst
22806 they exist inside Thumb code, are not the entry points for
22807 possible ARM->Thumb calls. Also, these labels can be used
22808 as part of a computed goto or switch statement. eg gcc
22809 can generate code that looks like this:
22811 ldr r2, [pc, .Laaa]
22821 The first instruction loads the address of the jump table.
22822 The second instruction converts a table index into a byte offset.
22823 The third instruction gets the jump address out of the table.
22824 The fourth instruction performs the jump.
22826 If the address stored at .Laaa is that of a symbol which has the
22827 Thumb_Func bit set, then the linker will arrange for this address
22828 to have the bottom bit set, which in turn would mean that the
22829 address computation performed by the third instruction would end
22830 up with the bottom bit set. Since the ARM is capable of unaligned
22831 word loads, the instruction would then load the incorrect address
22832 out of the jump table, and chaos would ensue. */
22833 if (label_is_thumb_function_name
22834 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22835 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22837 /* When the address of a Thumb function is taken the bottom
22838 bit of that address should be set. This will allow
22839 interworking between Arm and Thumb functions to work
22842 THUMB_SET_FUNC (sym
, 1);
22844 label_is_thumb_function_name
= FALSE
;
22847 dwarf2_emit_label (sym
);
22851 arm_data_in_code (void)
22853 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22855 *input_line_pointer
= '/';
22856 input_line_pointer
+= 5;
22857 *input_line_pointer
= 0;
22865 arm_canonicalize_symbol_name (char * name
)
22869 if (thumb_mode
&& (len
= strlen (name
)) > 5
22870 && streq (name
+ len
- 5, "/data"))
22871 *(name
+ len
- 5) = 0;
22876 /* Table of all register names defined by default. The user can
22877 define additional names with .req. Note that all register names
22878 should appear in both upper and lowercase variants. Some registers
22879 also have mixed-case names. */
22881 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22882 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22883 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22884 #define REGSET(p,t) \
22885 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22886 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22887 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22888 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22889 #define REGSETH(p,t) \
22890 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22891 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22892 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22893 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22894 #define REGSET2(p,t) \
22895 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22896 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22897 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22898 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22899 #define SPLRBANK(base,bank,t) \
22900 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22901 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22902 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22903 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22904 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22905 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22907 static const struct reg_entry reg_names
[] =
22909 /* ARM integer registers. */
22910 REGSET(r
, RN
), REGSET(R
, RN
),
22912 /* ATPCS synonyms. */
22913 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22914 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22915 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22917 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22918 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22919 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22921 /* Well-known aliases. */
22922 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22923 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22925 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22926 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22928 /* Defining the new Zero register from ARMv8.1-M. */
22932 /* Coprocessor numbers. */
22933 REGSET(p
, CP
), REGSET(P
, CP
),
22935 /* Coprocessor register numbers. The "cr" variants are for backward
22937 REGSET(c
, CN
), REGSET(C
, CN
),
22938 REGSET(cr
, CN
), REGSET(CR
, CN
),
22940 /* ARM banked registers. */
22941 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22942 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22943 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22944 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22945 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22946 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22947 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22949 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22950 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22951 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22952 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22953 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22954 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22955 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22956 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22958 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22959 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22960 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22961 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22962 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22963 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22964 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22965 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22966 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22968 /* FPA registers. */
22969 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22970 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22972 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22973 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22975 /* VFP SP registers. */
22976 REGSET(s
,VFS
), REGSET(S
,VFS
),
22977 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22979 /* VFP DP Registers. */
22980 REGSET(d
,VFD
), REGSET(D
,VFD
),
22981 /* Extra Neon DP registers. */
22982 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22984 /* Neon QP registers. */
22985 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22987 /* VFP control registers. */
22988 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22989 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22990 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22991 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22992 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22993 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22994 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22995 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
22996 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
22997 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
22998 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23000 /* Maverick DSP coprocessor registers. */
23001 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23002 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23004 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23005 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23006 REGDEF(dspsc
,0,DSPSC
),
23008 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23009 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23010 REGDEF(DSPSC
,0,DSPSC
),
23012 /* iWMMXt data registers - p0, c0-15. */
23013 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23015 /* iWMMXt control registers - p1, c0-3. */
23016 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23017 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23018 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23019 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23021 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23022 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23023 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23024 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23025 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23027 /* XScale accumulator registers. */
23028 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23034 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23035 within psr_required_here. */
23036 static const struct asm_psr psrs
[] =
23038 /* Backward compatibility notation. Note that "all" is no longer
23039 truly all possible PSR bits. */
23040 {"all", PSR_c
| PSR_f
},
23044 /* Individual flags. */
23050 /* Combinations of flags. */
23051 {"fs", PSR_f
| PSR_s
},
23052 {"fx", PSR_f
| PSR_x
},
23053 {"fc", PSR_f
| PSR_c
},
23054 {"sf", PSR_s
| PSR_f
},
23055 {"sx", PSR_s
| PSR_x
},
23056 {"sc", PSR_s
| PSR_c
},
23057 {"xf", PSR_x
| PSR_f
},
23058 {"xs", PSR_x
| PSR_s
},
23059 {"xc", PSR_x
| PSR_c
},
23060 {"cf", PSR_c
| PSR_f
},
23061 {"cs", PSR_c
| PSR_s
},
23062 {"cx", PSR_c
| PSR_x
},
23063 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23064 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23065 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23066 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23067 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23068 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23069 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23070 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23071 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23072 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23073 {"scf", PSR_s
| PSR_c
| PSR_f
},
23074 {"scx", PSR_s
| PSR_c
| PSR_x
},
23075 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23076 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23077 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23078 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23079 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23080 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23081 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23082 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23083 {"csf", PSR_c
| PSR_s
| PSR_f
},
23084 {"csx", PSR_c
| PSR_s
| PSR_x
},
23085 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23086 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23087 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23088 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23089 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23090 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23091 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23092 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23093 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23094 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23095 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23096 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23097 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23098 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23099 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23100 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23101 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23102 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23103 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23104 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23105 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23106 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23107 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23108 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23109 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23110 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23113 /* Table of V7M psr names. */
23114 static const struct asm_psr v7m_psrs
[] =
23116 {"apsr", 0x0 }, {"APSR", 0x0 },
23117 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23118 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23119 {"psr", 0x3 }, {"PSR", 0x3 },
23120 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23121 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23122 {"epsr", 0x6 }, {"EPSR", 0x6 },
23123 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23124 {"msp", 0x8 }, {"MSP", 0x8 },
23125 {"psp", 0x9 }, {"PSP", 0x9 },
23126 {"msplim", 0xa }, {"MSPLIM", 0xa },
23127 {"psplim", 0xb }, {"PSPLIM", 0xb },
23128 {"primask", 0x10}, {"PRIMASK", 0x10},
23129 {"basepri", 0x11}, {"BASEPRI", 0x11},
23130 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23131 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23132 {"control", 0x14}, {"CONTROL", 0x14},
23133 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23134 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23135 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23136 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23137 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23138 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23139 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23140 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23141 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23144 /* Table of all shift-in-operand names. */
23145 static const struct asm_shift_name shift_names
[] =
23147 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23148 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23149 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23150 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23151 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23152 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23153 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23156 /* Table of all explicit relocation names. */
23158 static struct reloc_entry reloc_names
[] =
23160 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23161 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23162 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23163 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23164 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23165 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23166 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23167 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23168 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23169 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23170 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23171 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23172 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23173 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23174 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23175 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23176 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23177 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23178 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23179 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23180 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23181 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23182 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23183 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23184 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23185 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23186 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23190 /* Table of all conditional affixes. */
23191 static const struct asm_cond conds
[] =
23195 {"cs", 0x2}, {"hs", 0x2},
23196 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23209 static const struct asm_cond vconds
[] =
23215 #define UL_BARRIER(L,U,CODE,FEAT) \
23216 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23217 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23219 static struct asm_barrier_opt barrier_opt_names
[] =
23221 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23222 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23223 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23224 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23225 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23226 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23227 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23228 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23229 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23230 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23231 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23232 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23233 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23234 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23235 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23236 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23241 /* Table of ARM-format instructions. */
23243 /* Macros for gluing together operand strings. N.B. In all cases
23244 other than OPS0, the trailing OP_stop comes from default
23245 zero-initialization of the unspecified elements of the array. */
23246 #define OPS0() { OP_stop, }
23247 #define OPS1(a) { OP_##a, }
23248 #define OPS2(a,b) { OP_##a,OP_##b, }
23249 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23250 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23251 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23252 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23254 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23255 This is useful when mixing operands for ARM and THUMB, i.e. using the
23256 MIX_ARM_THUMB_OPERANDS macro.
23257 In order to use these macros, prefix the number of operands with _
23259 #define OPS_1(a) { a, }
23260 #define OPS_2(a,b) { a,b, }
23261 #define OPS_3(a,b,c) { a,b,c, }
23262 #define OPS_4(a,b,c,d) { a,b,c,d, }
23263 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23264 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23266 /* These macros abstract out the exact format of the mnemonic table and
23267 save some repeated characters. */
23269 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23270 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23271 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23272 THUMB_VARIANT, do_##ae, do_##te, 0 }
23274 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23275 a T_MNEM_xyz enumerator. */
23276 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23277 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23278 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23279 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23281 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23282 infix after the third character. */
23283 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23284 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23285 THUMB_VARIANT, do_##ae, do_##te, 0 }
23286 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23287 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23288 THUMB_VARIANT, do_##ae, do_##te, 0 }
23289 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23290 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23291 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23292 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23293 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23294 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23295 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23296 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23298 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23299 field is still 0xE. Many of the Thumb variants can be executed
23300 conditionally, so this is checked separately. */
23301 #define TUE(mnem, op, top, nops, ops, ae, te) \
23302 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23303 THUMB_VARIANT, do_##ae, do_##te, 0 }
23305 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23306 Used by mnemonics that have very minimal differences in the encoding for
23307 ARM and Thumb variants and can be handled in a common function. */
23308 #define TUEc(mnem, op, top, nops, ops, en) \
23309 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23310 THUMB_VARIANT, do_##en, do_##en, 0 }
23312 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23313 condition code field. */
23314 #define TUF(mnem, op, top, nops, ops, ae, te) \
23315 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23316 THUMB_VARIANT, do_##ae, do_##te, 0 }
23318 /* ARM-only variants of all the above. */
23319 #define CE(mnem, op, nops, ops, ae) \
23320 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23322 #define C3(mnem, op, nops, ops, ae) \
23323 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23325 /* Thumb-only variants of TCE and TUE. */
23326 #define ToC(mnem, top, nops, ops, te) \
23327 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23330 #define ToU(mnem, top, nops, ops, te) \
23331 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23334 /* T_MNEM_xyz enumerator variants of ToC. */
23335 #define toC(mnem, top, nops, ops, te) \
23336 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23339 /* T_MNEM_xyz enumerator variants of ToU. */
23340 #define toU(mnem, top, nops, ops, te) \
23341 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23344 /* Legacy mnemonics that always have conditional infix after the third
23346 #define CL(mnem, op, nops, ops, ae) \
23347 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23348 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23350 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23351 #define cCE(mnem, op, nops, ops, ae) \
23352 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23354 /* mov instructions that are shared between coprocessor and MVE. */
23355 #define mcCE(mnem, op, nops, ops, ae) \
23356 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23358 /* Legacy coprocessor instructions where conditional infix and conditional
23359 suffix are ambiguous. For consistency this includes all FPA instructions,
23360 not just the potentially ambiguous ones. */
23361 #define cCL(mnem, op, nops, ops, ae) \
23362 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23363 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23365 /* Coprocessor, takes either a suffix or a position-3 infix
23366 (for an FPA corner case). */
23367 #define C3E(mnem, op, nops, ops, ae) \
23368 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23369 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23371 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23372 { m1 #m2 m3, OPS##nops ops, \
23373 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23374 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23376 #define CM(m1, m2, op, nops, ops, ae) \
23377 xCM_ (m1, , m2, op, nops, ops, ae), \
23378 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23379 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23380 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23381 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23382 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23383 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23384 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23385 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23386 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23387 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23388 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23389 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23390 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23391 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23392 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23393 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23394 xCM_ (m1, le, m2, op, nops, ops, ae), \
23395 xCM_ (m1, al, m2, op, nops, ops, ae)
23397 #define UE(mnem, op, nops, ops, ae) \
23398 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23400 #define UF(mnem, op, nops, ops, ae) \
23401 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23403 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23404 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23405 use the same encoding function for each. */
23406 #define NUF(mnem, op, nops, ops, enc) \
23407 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23408 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23410 /* Neon data processing, version which indirects through neon_enc_tab for
23411 the various overloaded versions of opcodes. */
23412 #define nUF(mnem, op, nops, ops, enc) \
23413 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23414 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23416 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23418 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23419 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23420 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23422 #define NCE(mnem, op, nops, ops, enc) \
23423 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23425 #define NCEF(mnem, op, nops, ops, enc) \
23426 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23428 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23429 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23430 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23431 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23433 #define nCE(mnem, op, nops, ops, enc) \
23434 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23436 #define nCEF(mnem, op, nops, ops, enc) \
23437 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23440 #define mCEF(mnem, op, nops, ops, enc) \
23441 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23442 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23445 /* nCEF but for MVE predicated instructions. */
23446 #define mnCEF(mnem, op, nops, ops, enc) \
23447 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23449 /* nCE but for MVE predicated instructions. */
23450 #define mnCE(mnem, op, nops, ops, enc) \
23451 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23453 /* NUF but for potentially MVE predicated instructions. */
23454 #define MNUF(mnem, op, nops, ops, enc) \
23455 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23456 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23458 /* nUF but for potentially MVE predicated instructions. */
23459 #define mnUF(mnem, op, nops, ops, enc) \
23460 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23461 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23463 /* ToC but for potentially MVE predicated instructions. */
23464 #define mToC(mnem, top, nops, ops, te) \
23465 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23468 /* NCE but for MVE predicated instructions. */
23469 #define MNCE(mnem, op, nops, ops, enc) \
23470 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23472 /* NCEF but for MVE predicated instructions. */
23473 #define MNCEF(mnem, op, nops, ops, enc) \
23474 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23477 static const struct asm_opcode insns
[] =
23479 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23480 #define THUMB_VARIANT & arm_ext_v4t
23481 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23482 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23483 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23484 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23485 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23486 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23487 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23488 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23489 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23490 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23491 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23492 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23493 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23494 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23495 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23496 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23498 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23499 for setting PSR flag bits. They are obsolete in V6 and do not
23500 have Thumb equivalents. */
23501 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23502 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23503 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23504 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23505 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23506 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23507 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23508 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23509 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23511 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23512 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23513 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23514 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23516 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23517 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23518 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23520 OP_ADDRGLDR
),ldst
, t_ldst
),
23521 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23523 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23524 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23525 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23526 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23527 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23528 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23530 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23531 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23534 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23535 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23536 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23537 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23539 /* Thumb-compatibility pseudo ops. */
23540 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23541 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23542 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23543 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23544 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23545 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23546 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23547 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23548 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23549 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23550 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23551 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23553 /* These may simplify to neg. */
23554 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23555 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23557 #undef THUMB_VARIANT
23558 #define THUMB_VARIANT & arm_ext_os
23560 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23561 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23563 #undef THUMB_VARIANT
23564 #define THUMB_VARIANT & arm_ext_v6
23566 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23568 /* V1 instructions with no Thumb analogue prior to V6T2. */
23569 #undef THUMB_VARIANT
23570 #define THUMB_VARIANT & arm_ext_v6t2
23572 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23573 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23574 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23576 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23577 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23578 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23579 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23581 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23582 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23584 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23585 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23587 /* V1 instructions with no Thumb analogue at all. */
23588 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23589 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23591 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23592 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23593 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23594 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23595 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23596 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23597 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23598 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23601 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23602 #undef THUMB_VARIANT
23603 #define THUMB_VARIANT & arm_ext_v4t
23605 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23606 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23608 #undef THUMB_VARIANT
23609 #define THUMB_VARIANT & arm_ext_v6t2
23611 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23612 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23614 /* Generic coprocessor instructions. */
23615 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23616 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23617 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23618 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23619 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23620 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23621 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23624 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23626 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23627 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23630 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23631 #undef THUMB_VARIANT
23632 #define THUMB_VARIANT & arm_ext_msr
23634 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23635 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23638 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23639 #undef THUMB_VARIANT
23640 #define THUMB_VARIANT & arm_ext_v6t2
23642 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23643 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23644 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23645 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23646 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23647 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23648 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23649 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23652 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23653 #undef THUMB_VARIANT
23654 #define THUMB_VARIANT & arm_ext_v4t
23656 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23657 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23658 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23659 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23660 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23661 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23664 #define ARM_VARIANT & arm_ext_v4t_5
23666 /* ARM Architecture 4T. */
23667 /* Note: bx (and blx) are required on V5, even if the processor does
23668 not support Thumb. */
23669 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23672 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23673 #undef THUMB_VARIANT
23674 #define THUMB_VARIANT & arm_ext_v5t
23676 /* Note: blx has 2 variants; the .value coded here is for
23677 BLX(2). Only this variant has conditional execution. */
23678 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23679 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23681 #undef THUMB_VARIANT
23682 #define THUMB_VARIANT & arm_ext_v6t2
23684 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23685 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23686 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23687 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23688 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23689 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23690 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23691 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23694 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23695 #undef THUMB_VARIANT
23696 #define THUMB_VARIANT & arm_ext_v5exp
23698 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23699 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23700 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23701 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23703 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23704 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23706 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23707 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23708 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23709 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23711 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23712 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23713 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23714 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23716 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23717 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23719 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23720 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23721 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23722 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23725 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23726 #undef THUMB_VARIANT
23727 #define THUMB_VARIANT & arm_ext_v6t2
23729 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23730 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23732 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23733 ADDRGLDRS
), ldrd
, t_ldstd
),
23735 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23736 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23739 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23741 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23744 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23745 #undef THUMB_VARIANT
23746 #define THUMB_VARIANT & arm_ext_v6
23748 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23749 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23750 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23751 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23752 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23753 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23754 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23755 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23756 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23757 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23759 #undef THUMB_VARIANT
23760 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23762 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23763 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23765 #undef THUMB_VARIANT
23766 #define THUMB_VARIANT & arm_ext_v6t2
23768 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23769 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23771 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23772 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23774 /* ARM V6 not included in V7M. */
23775 #undef THUMB_VARIANT
23776 #define THUMB_VARIANT & arm_ext_v6_notm
23777 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23778 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23779 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23780 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23781 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23782 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23783 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23784 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23785 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23786 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23787 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23788 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23789 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23790 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23791 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23792 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23793 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23794 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23795 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23797 /* ARM V6 not included in V7M (eg. integer SIMD). */
23798 #undef THUMB_VARIANT
23799 #define THUMB_VARIANT & arm_ext_v6_dsp
23800 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23801 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23802 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23803 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23804 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23805 /* Old name for QASX. */
23806 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23807 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23808 /* Old name for QSAX. */
23809 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23810 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23811 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23812 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23813 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23814 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23815 /* Old name for SASX. */
23816 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23817 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23818 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23819 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23820 /* Old name for SHASX. */
23821 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23822 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23823 /* Old name for SHSAX. */
23824 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23825 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23826 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23827 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23828 /* Old name for SSAX. */
23829 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23830 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23831 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23832 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23833 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23834 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23835 /* Old name for UASX. */
23836 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23837 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23838 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23839 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23840 /* Old name for UHASX. */
23841 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23842 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23843 /* Old name for UHSAX. */
23844 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23845 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23846 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23847 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23848 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23849 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23850 /* Old name for UQASX. */
23851 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23852 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23853 /* Old name for UQSAX. */
23854 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23855 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23856 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23857 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23858 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23859 /* Old name for USAX. */
23860 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23861 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23862 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23863 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23864 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23865 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23866 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23867 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23868 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23869 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23870 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23871 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23872 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23873 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23874 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23875 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23876 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23877 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23878 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23879 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23880 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23881 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23882 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23883 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23884 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23885 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23886 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23887 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23888 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23889 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23890 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23891 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23892 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23893 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23896 #define ARM_VARIANT & arm_ext_v6k_v6t2
23897 #undef THUMB_VARIANT
23898 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23900 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23901 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23902 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23903 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23905 #undef THUMB_VARIANT
23906 #define THUMB_VARIANT & arm_ext_v6_notm
23907 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23909 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23910 RRnpcb
), strexd
, t_strexd
),
23912 #undef THUMB_VARIANT
23913 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23914 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23916 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23918 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23920 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23922 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23925 #define ARM_VARIANT & arm_ext_sec
23926 #undef THUMB_VARIANT
23927 #define THUMB_VARIANT & arm_ext_sec
23929 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23932 #define ARM_VARIANT & arm_ext_virt
23933 #undef THUMB_VARIANT
23934 #define THUMB_VARIANT & arm_ext_virt
23936 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23937 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23940 #define ARM_VARIANT & arm_ext_pan
23941 #undef THUMB_VARIANT
23942 #define THUMB_VARIANT & arm_ext_pan
23944 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23947 #define ARM_VARIANT & arm_ext_v6t2
23948 #undef THUMB_VARIANT
23949 #define THUMB_VARIANT & arm_ext_v6t2
23951 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23952 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23953 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23954 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23956 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23957 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23959 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23960 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23961 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23962 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23965 #define ARM_VARIANT & arm_ext_v3
23966 #undef THUMB_VARIANT
23967 #define THUMB_VARIANT & arm_ext_v6t2
23969 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23970 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23971 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23974 #define ARM_VARIANT & arm_ext_v6t2
23975 #undef THUMB_VARIANT
23976 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23977 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23978 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23980 /* Thumb-only instructions. */
23982 #define ARM_VARIANT NULL
23983 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23984 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23986 /* ARM does not really have an IT instruction, so always allow it.
23987 The opcode is copied from Thumb in order to allow warnings in
23988 -mimplicit-it=[never | arm] modes. */
23990 #define ARM_VARIANT & arm_ext_v1
23991 #undef THUMB_VARIANT
23992 #define THUMB_VARIANT & arm_ext_v6t2
23994 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23995 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23996 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23997 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23998 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23999 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24000 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24001 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24002 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24003 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24004 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24005 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24006 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24007 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24008 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24009 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24010 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24011 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24013 /* Thumb2 only instructions. */
24015 #define ARM_VARIANT NULL
24017 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24018 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24019 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24020 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24021 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24022 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24024 /* Hardware division instructions. */
24026 #define ARM_VARIANT & arm_ext_adiv
24027 #undef THUMB_VARIANT
24028 #define THUMB_VARIANT & arm_ext_div
24030 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24031 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24033 /* ARM V6M/V7 instructions. */
24035 #define ARM_VARIANT & arm_ext_barrier
24036 #undef THUMB_VARIANT
24037 #define THUMB_VARIANT & arm_ext_barrier
24039 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24040 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24041 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24043 /* ARM V7 instructions. */
24045 #define ARM_VARIANT & arm_ext_v7
24046 #undef THUMB_VARIANT
24047 #define THUMB_VARIANT & arm_ext_v7
24049 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24050 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24053 #define ARM_VARIANT & arm_ext_mp
24054 #undef THUMB_VARIANT
24055 #define THUMB_VARIANT & arm_ext_mp
24057 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24059 /* AArchv8 instructions. */
24061 #define ARM_VARIANT & arm_ext_v8
24063 /* Instructions shared between armv8-a and armv8-m. */
24064 #undef THUMB_VARIANT
24065 #define THUMB_VARIANT & arm_ext_atomics
24067 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24068 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24069 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24070 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24071 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24072 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24073 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24074 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24075 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24076 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24078 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24080 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24082 #undef THUMB_VARIANT
24083 #define THUMB_VARIANT & arm_ext_v8
24085 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24086 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24088 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24091 /* Defined in V8 but is in undefined encoding space for earlier
24092 architectures. However earlier architectures are required to treat
24093 this instuction as a semihosting trap as well. Hence while not explicitly
24094 defined as such, it is in fact correct to define the instruction for all
24096 #undef THUMB_VARIANT
24097 #define THUMB_VARIANT & arm_ext_v1
24099 #define ARM_VARIANT & arm_ext_v1
24100 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24102 /* ARMv8 T32 only. */
24104 #define ARM_VARIANT NULL
24105 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24106 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24107 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24109 /* FP for ARMv8. */
24111 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24112 #undef THUMB_VARIANT
24113 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24115 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24116 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24117 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24118 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24119 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24120 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24121 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24122 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24123 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24124 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24125 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24127 /* Crypto v1 extensions. */
24129 #define ARM_VARIANT & fpu_crypto_ext_armv8
24130 #undef THUMB_VARIANT
24131 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24133 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24134 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24135 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24136 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24137 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24138 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24139 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24140 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24141 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24142 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24143 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24144 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24145 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24146 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24149 #define ARM_VARIANT & crc_ext_armv8
24150 #undef THUMB_VARIANT
24151 #define THUMB_VARIANT & crc_ext_armv8
24152 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24153 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24154 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24155 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24156 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24157 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24159 /* ARMv8.2 RAS extension. */
24161 #define ARM_VARIANT & arm_ext_ras
24162 #undef THUMB_VARIANT
24163 #define THUMB_VARIANT & arm_ext_ras
24164 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24167 #define ARM_VARIANT & arm_ext_v8_3
24168 #undef THUMB_VARIANT
24169 #define THUMB_VARIANT & arm_ext_v8_3
24170 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24173 #define ARM_VARIANT & fpu_neon_ext_dotprod
24174 #undef THUMB_VARIANT
24175 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24176 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24177 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24180 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24181 #undef THUMB_VARIANT
24182 #define THUMB_VARIANT NULL
24184 cCE("wfs", e200110
, 1, (RR
), rd
),
24185 cCE("rfs", e300110
, 1, (RR
), rd
),
24186 cCE("wfc", e400110
, 1, (RR
), rd
),
24187 cCE("rfc", e500110
, 1, (RR
), rd
),
24189 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24190 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24191 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24192 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24194 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24195 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24196 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24197 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24199 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24200 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24201 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24202 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24203 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24204 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24205 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24206 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24207 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24208 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24209 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24210 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24212 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24213 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24214 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24215 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24216 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24217 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24218 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24219 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24220 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24221 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24222 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24223 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24225 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24226 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24227 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24228 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24229 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24230 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24231 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24232 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24233 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24234 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24235 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24236 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24238 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24239 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24240 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24241 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24242 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24243 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24244 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24245 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24246 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24247 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24248 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24249 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24251 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24252 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24253 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24254 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24255 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24256 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24257 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24261 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24266 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24267 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24269 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24270 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24274 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24279 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24280 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24282 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24283 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24287 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24292 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24293 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24295 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24296 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24300 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24305 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24306 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24308 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24309 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24310 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24311 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24312 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24313 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24314 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24316 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24317 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24318 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24319 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24320 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24321 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24322 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24323 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24324 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24325 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24326 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24327 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24329 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24330 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24331 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24332 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24333 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24334 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24335 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24336 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24337 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24338 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24339 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24340 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24342 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24343 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24344 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24345 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24346 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24347 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24348 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24349 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24350 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24351 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24352 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24353 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24355 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24356 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24357 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24358 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24359 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24360 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24361 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24362 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24363 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24364 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24365 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24366 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24368 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24369 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24370 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24371 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24372 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24373 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24374 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24375 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24376 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24377 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24378 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24379 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24381 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24382 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24383 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24384 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24385 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24386 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24387 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24388 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24389 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24390 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24391 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24392 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24394 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24395 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24396 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24397 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24398 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24399 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24400 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24401 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24402 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24403 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24404 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24405 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24407 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24408 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24409 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24410 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24411 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24412 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24413 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24414 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24415 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24416 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24417 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24418 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24420 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24421 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24422 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24423 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24424 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24425 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24426 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24427 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24428 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24429 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24430 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24431 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24433 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24434 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24435 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24436 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24437 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24438 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24439 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24440 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24441 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24442 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24443 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24444 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24446 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24447 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24448 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24449 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24450 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24451 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24452 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24453 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24454 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24455 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24456 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24457 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24459 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24460 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24461 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24462 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24463 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24464 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24465 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24469 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24474 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24475 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24477 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24478 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24479 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24480 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24481 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24482 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24483 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24485 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24486 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24487 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24488 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24489 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24490 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24491 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24492 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24493 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24494 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24495 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24496 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24498 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24499 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24500 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24501 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24502 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24503 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24504 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24505 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24506 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24507 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24508 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24509 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24511 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24512 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24513 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24514 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24515 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24516 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24517 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24518 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24519 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24520 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24521 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24522 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24524 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24525 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24526 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24527 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24528 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24529 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24530 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24531 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24532 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24533 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24534 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24535 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24537 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24538 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24539 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24540 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24541 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24542 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24543 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24544 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24545 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24546 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24547 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24548 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24550 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24551 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24552 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24553 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24554 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24555 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24556 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24557 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24558 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24559 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24560 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24561 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24563 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24564 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24565 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24566 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24567 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24568 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24569 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24570 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24571 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24572 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24573 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24574 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24576 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24577 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24578 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24579 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24581 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24582 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24583 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24584 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24585 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24586 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24587 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24588 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24589 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24590 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24591 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24592 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24594 /* The implementation of the FIX instruction is broken on some
24595 assemblers, in that it accepts a precision specifier as well as a
24596 rounding specifier, despite the fact that this is meaningless.
24597 To be more compatible, we accept it as well, though of course it
24598 does not set any bits. */
24599 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24600 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24601 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24602 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24603 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24604 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24605 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24606 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24607 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24608 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24609 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24610 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24611 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24613 /* Instructions that were new with the real FPA, call them V2. */
24615 #define ARM_VARIANT & fpu_fpa_ext_v2
24617 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24618 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24619 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24620 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24621 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24622 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24625 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24626 #undef THUMB_VARIANT
24627 #define THUMB_VARIANT & arm_ext_v6t2
24628 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24629 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24630 #undef THUMB_VARIANT
24632 /* Moves and type conversions. */
24633 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24634 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24635 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24636 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24637 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24638 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24639 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24640 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24641 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24643 /* Memory operations. */
24644 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24645 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24646 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24647 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24648 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24649 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24650 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24651 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24652 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24653 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24654 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24655 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24656 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24657 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24658 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24659 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24660 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24661 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24663 /* Monadic operations. */
24664 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24665 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24666 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24668 /* Dyadic operations. */
24669 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24670 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24671 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24672 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24673 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24674 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24675 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24676 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24677 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24680 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24681 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24682 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24683 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24685 /* Double precision load/store are still present on single precision
24686 implementations. */
24687 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24688 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24689 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24690 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24691 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24692 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24693 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24694 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24695 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24696 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24699 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24701 /* Moves and type conversions. */
24702 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24703 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24704 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24705 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24706 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24707 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24708 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24709 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24710 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24711 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24712 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24713 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24715 /* Monadic operations. */
24716 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24717 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24718 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24720 /* Dyadic operations. */
24721 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24722 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24723 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24724 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24725 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24726 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24727 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24728 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24729 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24732 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24733 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24734 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24735 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24737 /* Instructions which may belong to either the Neon or VFP instruction sets.
24738 Individual encoder functions perform additional architecture checks. */
24740 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24741 #undef THUMB_VARIANT
24742 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24744 /* These mnemonics are unique to VFP. */
24745 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24746 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24747 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24748 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24749 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24750 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24751 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24752 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24754 /* Mnemonics shared by Neon and VFP. */
24755 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24757 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24758 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24759 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24760 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24761 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24762 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24764 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24765 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24766 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24767 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24770 /* NOTE: All VMOV encoding is special-cased! */
24771 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24773 #undef THUMB_VARIANT
24774 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24775 by different feature bits. Since we are setting the Thumb guard, we can
24776 require Thumb-1 which makes it a nop guard and set the right feature bit in
24777 do_vldr_vstr (). */
24778 #define THUMB_VARIANT & arm_ext_v4t
24779 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24780 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24783 #define ARM_VARIANT & arm_ext_fp16
24784 #undef THUMB_VARIANT
24785 #define THUMB_VARIANT & arm_ext_fp16
24786 /* New instructions added from v8.2, allowing the extraction and insertion of
24787 the upper 16 bits of a 32-bit vector register. */
24788 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24789 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24791 /* New backported fma/fms instructions optional in v8.2. */
24792 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24793 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24795 #undef THUMB_VARIANT
24796 #define THUMB_VARIANT & fpu_neon_ext_v1
24798 #define ARM_VARIANT & fpu_neon_ext_v1
24800 /* Data processing with three registers of the same length. */
24801 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24802 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24803 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24804 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24805 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24806 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24807 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24808 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24809 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24810 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24811 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24812 /* If not immediate, fall back to neon_dyadic_i64_su.
24813 shl should accept I8 I16 I32 I64,
24814 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24815 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24816 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24817 /* Logic ops, types optional & ignored. */
24818 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24819 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24820 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24821 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24822 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24823 /* Bitfield ops, untyped. */
24824 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24825 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24826 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24827 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24828 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24829 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24830 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24831 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24832 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24833 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24834 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24835 back to neon_dyadic_if_su. */
24836 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24837 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24838 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24839 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24840 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24841 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24842 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24843 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24844 /* Comparison. Type I8 I16 I32 F32. */
24845 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24846 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24847 /* As above, D registers only. */
24848 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24849 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24850 /* Int and float variants, signedness unimportant. */
24851 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24852 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24853 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24854 /* Add/sub take types I8 I16 I32 I64 F32. */
24855 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24856 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24857 /* vtst takes sizes 8, 16, 32. */
24858 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24859 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24860 /* VMUL takes I8 I16 I32 F32 P8. */
24861 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24862 /* VQD{R}MULH takes S16 S32. */
24863 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24864 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24865 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24866 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24867 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24868 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24869 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24870 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24871 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24872 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24873 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24874 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24875 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24876 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24877 /* ARM v8.1 extension. */
24878 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24879 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24880 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24882 /* Two address, int/float. Types S8 S16 S32 F32. */
24883 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24884 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24886 /* Data processing with two registers and a shift amount. */
24887 /* Right shifts, and variants with rounding.
24888 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24889 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24890 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24891 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24892 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24893 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24894 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24895 /* Shift and insert. Sizes accepted 8 16 32 64. */
24896 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24897 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24898 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24899 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24900 /* Right shift immediate, saturating & narrowing, with rounding variants.
24901 Types accepted S16 S32 S64 U16 U32 U64. */
24902 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24903 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24904 /* As above, unsigned. Types accepted S16 S32 S64. */
24905 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24906 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24907 /* Right shift narrowing. Types accepted I16 I32 I64. */
24908 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24909 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24910 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24911 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24912 /* CVT with optional immediate for fixed-point variant. */
24913 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24915 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24917 /* Data processing, three registers of different lengths. */
24918 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24919 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24920 /* If not scalar, fall back to neon_dyadic_long.
24921 Vector types as above, scalar types S16 S32 U16 U32. */
24922 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24923 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24924 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24925 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24926 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24927 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24928 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24929 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24930 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24931 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24932 /* Saturating doubling multiplies. Types S16 S32. */
24933 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24934 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24935 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24936 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24937 S16 S32 U16 U32. */
24938 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24940 /* Extract. Size 8. */
24941 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24942 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24944 /* Two registers, miscellaneous. */
24945 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24946 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24947 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24948 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24949 /* Vector replicate. Sizes 8 16 32. */
24950 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24951 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24952 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24953 /* VMOVN. Types I16 I32 I64. */
24954 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24955 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24956 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24957 /* VQMOVUN. Types S16 S32 S64. */
24958 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24959 /* VZIP / VUZP. Sizes 8 16 32. */
24960 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24961 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24962 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24963 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24964 /* VQABS / VQNEG. Types S8 S16 S32. */
24965 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24966 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24967 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24968 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24969 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24970 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24971 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24972 /* Reciprocal estimates. Types U32 F16 F32. */
24973 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24974 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24975 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24976 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24977 /* VCLS. Types S8 S16 S32. */
24978 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24979 /* VCLZ. Types I8 I16 I32. */
24980 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24981 /* VCNT. Size 8. */
24982 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24983 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24984 /* Two address, untyped. */
24985 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24986 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24987 /* VTRN. Sizes 8 16 32. */
24988 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24989 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24991 /* Table lookup. Size 8. */
24992 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24993 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24995 #undef THUMB_VARIANT
24996 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24998 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25000 /* Neon element/structure load/store. */
25001 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25002 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25003 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25004 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25005 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25006 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25007 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25008 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25010 #undef THUMB_VARIANT
25011 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25013 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25014 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25015 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25016 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25017 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25018 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25019 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25020 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25021 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25022 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25024 #undef THUMB_VARIANT
25025 #define THUMB_VARIANT & fpu_vfp_ext_v3
25027 #define ARM_VARIANT & fpu_vfp_ext_v3
25029 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25030 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25031 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25032 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25033 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25034 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25035 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25036 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25037 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25040 #define ARM_VARIANT & fpu_vfp_ext_fma
25041 #undef THUMB_VARIANT
25042 #define THUMB_VARIANT & fpu_vfp_ext_fma
25043 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
25044 VFP FMA variant; NEON and VFP FMA always includes the NEON
25045 FMA instructions. */
25046 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25047 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25049 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25050 the v form should always be used. */
25051 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25052 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25053 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25054 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25055 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25056 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25058 #undef THUMB_VARIANT
25060 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25062 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25063 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25064 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25065 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25066 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25067 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25068 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25069 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25072 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25074 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25075 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25076 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25077 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25078 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25079 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25080 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25081 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25082 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25083 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25084 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25085 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25086 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25087 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25088 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25089 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25090 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25091 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25092 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25093 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25094 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25095 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25096 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25097 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25098 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25099 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25100 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25101 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25102 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25103 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25104 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25105 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25106 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25107 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25108 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25109 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25110 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25111 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25112 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25113 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25114 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25115 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25116 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25117 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25118 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25119 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25120 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25121 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25122 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25123 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25124 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25125 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25126 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25127 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25128 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25129 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25130 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25131 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25132 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25133 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25134 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25135 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25136 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25137 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25138 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25139 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25140 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25141 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25142 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25143 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25144 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25145 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25146 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25147 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25148 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25149 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25150 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25151 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25152 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25153 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25154 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25155 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25156 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25157 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25158 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25159 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25160 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25161 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25162 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25163 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25164 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25165 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25166 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25167 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25168 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25169 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25170 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25171 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25173 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25174 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25175 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25176 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25177 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25178 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25179 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25180 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25181 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25182 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25183 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25184 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25185 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25186 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25187 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25188 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25189 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25190 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25191 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25192 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25193 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25194 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25195 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25196 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25197 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25198 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25199 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25200 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25201 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25202 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25203 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25204 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25205 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25206 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25207 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25208 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25209 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25210 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25211 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25212 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25213 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25214 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25215 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25216 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25217 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25218 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25219 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25220 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25221 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25222 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25223 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25224 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25225 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25226 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25227 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25228 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25229 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25230 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25231 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25232 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25233 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25234 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25235 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25238 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25240 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25241 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25242 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25243 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25244 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25245 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25246 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25247 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25248 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25249 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25250 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25251 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25252 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25253 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25254 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25255 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25256 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25257 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25258 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25259 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25260 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25261 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25262 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25263 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25264 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25265 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25266 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25267 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25268 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25269 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25270 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25271 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25272 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25273 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25274 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25275 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25276 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25277 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25278 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25279 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25280 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25281 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25282 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25283 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25284 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25285 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25286 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25287 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25288 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25289 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25290 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25291 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25292 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25293 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25294 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25295 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25296 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25299 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25301 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25302 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25303 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25304 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25305 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25306 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25307 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25308 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25309 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25310 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25311 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25312 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25313 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25314 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25315 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25316 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25317 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25318 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25319 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25320 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25321 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25322 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25323 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25324 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25325 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25326 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25327 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25328 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25329 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25330 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25331 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25332 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25333 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25334 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25335 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25336 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25337 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25338 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25339 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25340 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25341 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25342 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25343 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25344 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25345 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25346 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25347 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25348 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25349 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25350 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25351 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25352 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25353 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25354 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25355 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25356 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25357 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25358 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25359 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25360 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25361 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25362 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25363 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25364 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25365 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25366 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25367 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25368 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25369 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25370 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25371 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25372 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25373 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25374 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25375 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25376 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25378 /* ARMv8.5-A instructions. */
25380 #define ARM_VARIANT & arm_ext_sb
25381 #undef THUMB_VARIANT
25382 #define THUMB_VARIANT & arm_ext_sb
25383 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25386 #define ARM_VARIANT & arm_ext_predres
25387 #undef THUMB_VARIANT
25388 #define THUMB_VARIANT & arm_ext_predres
25389 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25390 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25391 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25393 /* ARMv8-M instructions. */
25395 #define ARM_VARIANT NULL
25396 #undef THUMB_VARIANT
25397 #define THUMB_VARIANT & arm_ext_v8m
25398 ToU("sg", e97fe97f
, 0, (), noargs
),
25399 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25400 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25401 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25402 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25403 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25404 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25406 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25407 instructions behave as nop if no VFP is present. */
25408 #undef THUMB_VARIANT
25409 #define THUMB_VARIANT & arm_ext_v8m_main
25410 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25411 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25413 /* Armv8.1-M Mainline instructions. */
25414 #undef THUMB_VARIANT
25415 #define THUMB_VARIANT & arm_ext_v8_1m_main
25416 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25417 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25418 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25419 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25420 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25421 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25422 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25423 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25424 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25426 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25427 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25428 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25429 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25430 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25432 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25433 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25434 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25436 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25437 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25439 #undef THUMB_VARIANT
25440 #define THUMB_VARIANT & mve_ext
25441 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25442 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25443 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25444 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25445 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25446 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25447 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25448 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25449 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25450 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25451 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25452 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25453 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25454 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25455 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25457 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25458 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25459 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25460 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25461 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25462 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25463 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25464 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25465 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25466 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25467 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25468 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25469 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25470 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25471 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25473 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25474 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25475 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25476 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25477 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25478 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25479 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25480 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25481 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25482 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25483 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25484 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25485 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25486 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25487 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25489 /* MVE and MVE FP only. */
25490 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25491 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25492 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25493 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25494 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25495 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25496 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25497 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25498 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25499 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25500 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25501 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25502 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25503 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25504 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25505 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25506 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25508 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25509 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25510 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25511 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25512 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25513 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25514 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25515 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25516 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25517 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25518 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25519 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25520 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25521 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25522 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25523 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25524 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25525 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25526 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25527 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25529 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25530 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25531 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25532 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25533 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25534 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25535 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25536 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25537 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25538 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25539 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25540 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25541 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25542 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25543 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25544 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25545 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25547 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25548 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25549 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25550 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25551 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25552 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25553 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25554 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25555 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25556 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25557 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25558 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25559 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25560 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25561 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25562 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25563 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25564 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25565 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25566 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25568 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25569 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25570 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25571 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25572 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25574 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25575 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25576 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25577 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25578 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25579 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25580 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25581 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25582 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25583 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25584 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25585 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25586 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25587 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25588 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25589 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25590 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25592 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25593 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25594 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25595 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25596 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25597 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25598 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25599 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25600 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25601 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25602 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25603 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25605 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25606 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25607 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25609 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25610 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25611 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25612 toU("lctp", _lctp
, 0, (), t_loloop
),
25614 #undef THUMB_VARIANT
25615 #define THUMB_VARIANT & mve_fp_ext
25616 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25617 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25618 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25619 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25620 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25621 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25622 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25623 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25626 #define ARM_VARIANT & fpu_vfp_ext_v1
25627 #undef THUMB_VARIANT
25628 #define THUMB_VARIANT & arm_ext_v6t2
25629 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25630 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25632 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25635 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25637 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25638 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25639 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25640 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25642 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25643 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25644 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25646 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25647 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25649 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25650 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25652 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25653 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25656 #define ARM_VARIANT & fpu_vfp_ext_v2
25658 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25659 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25660 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25661 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25664 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25665 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25666 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25667 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25668 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25669 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25670 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25673 #define ARM_VARIANT & fpu_neon_ext_v1
25674 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25675 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25676 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25677 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25678 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25679 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25680 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25681 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25682 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25683 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25684 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25685 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25686 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25687 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25688 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25689 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25690 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25691 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25692 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25693 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25694 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25695 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25696 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25697 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25698 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25699 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25700 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25701 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25702 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25703 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25704 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25705 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25706 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25707 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25708 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25709 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25710 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25713 #define ARM_VARIANT & arm_ext_v8_3
25714 #undef THUMB_VARIANT
25715 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25716 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25717 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25720 #undef THUMB_VARIANT
25752 /* MD interface: bits in the object file. */
25754 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25755 for use in the a.out file, and stores them in the array pointed to by buf.
25756 This knows about the endian-ness of the target machine and does
25757 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25758 2 (short) and 4 (long) Floating numbers are put out as a series of
25759 LITTLENUMS (shorts, here at least). */
25762 md_number_to_chars (char * buf
, valueT val
, int n
)
25764 if (target_big_endian
)
25765 number_to_chars_bigendian (buf
, val
, n
);
25767 number_to_chars_littleendian (buf
, val
, n
);
25771 md_chars_to_number (char * buf
, int n
)
25774 unsigned char * where
= (unsigned char *) buf
;
25776 if (target_big_endian
)
25781 result
|= (*where
++ & 255);
25789 result
|= (where
[n
] & 255);
25796 /* MD interface: Sections. */
25798 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25799 that an rs_machine_dependent frag may reach. */
25802 arm_frag_max_var (fragS
*fragp
)
25804 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25805 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25807 Note that we generate relaxable instructions even for cases that don't
25808 really need it, like an immediate that's a trivial constant. So we're
25809 overestimating the instruction size for some of those cases. Rather
25810 than putting more intelligence here, it would probably be better to
25811 avoid generating a relaxation frag in the first place when it can be
25812 determined up front that a short instruction will suffice. */
25814 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25818 /* Estimate the size of a frag before relaxing. Assume everything fits in
25822 md_estimate_size_before_relax (fragS
* fragp
,
25823 segT segtype ATTRIBUTE_UNUSED
)
25829 /* Convert a machine dependent frag. */
25832 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25834 unsigned long insn
;
25835 unsigned long old_op
;
25843 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25845 old_op
= bfd_get_16(abfd
, buf
);
25846 if (fragp
->fr_symbol
)
25848 exp
.X_op
= O_symbol
;
25849 exp
.X_add_symbol
= fragp
->fr_symbol
;
25853 exp
.X_op
= O_constant
;
25855 exp
.X_add_number
= fragp
->fr_offset
;
25856 opcode
= fragp
->fr_subtype
;
25859 case T_MNEM_ldr_pc
:
25860 case T_MNEM_ldr_pc2
:
25861 case T_MNEM_ldr_sp
:
25862 case T_MNEM_str_sp
:
25869 if (fragp
->fr_var
== 4)
25871 insn
= THUMB_OP32 (opcode
);
25872 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25874 insn
|= (old_op
& 0x700) << 4;
25878 insn
|= (old_op
& 7) << 12;
25879 insn
|= (old_op
& 0x38) << 13;
25881 insn
|= 0x00000c00;
25882 put_thumb32_insn (buf
, insn
);
25883 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25887 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25889 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25892 if (fragp
->fr_var
== 4)
25894 insn
= THUMB_OP32 (opcode
);
25895 insn
|= (old_op
& 0xf0) << 4;
25896 put_thumb32_insn (buf
, insn
);
25897 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25901 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25902 exp
.X_add_number
-= 4;
25910 if (fragp
->fr_var
== 4)
25912 int r0off
= (opcode
== T_MNEM_mov
25913 || opcode
== T_MNEM_movs
) ? 0 : 8;
25914 insn
= THUMB_OP32 (opcode
);
25915 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25916 insn
|= (old_op
& 0x700) << r0off
;
25917 put_thumb32_insn (buf
, insn
);
25918 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25922 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25927 if (fragp
->fr_var
== 4)
25929 insn
= THUMB_OP32(opcode
);
25930 put_thumb32_insn (buf
, insn
);
25931 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25934 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25938 if (fragp
->fr_var
== 4)
25940 insn
= THUMB_OP32(opcode
);
25941 insn
|= (old_op
& 0xf00) << 14;
25942 put_thumb32_insn (buf
, insn
);
25943 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25946 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25949 case T_MNEM_add_sp
:
25950 case T_MNEM_add_pc
:
25951 case T_MNEM_inc_sp
:
25952 case T_MNEM_dec_sp
:
25953 if (fragp
->fr_var
== 4)
25955 /* ??? Choose between add and addw. */
25956 insn
= THUMB_OP32 (opcode
);
25957 insn
|= (old_op
& 0xf0) << 4;
25958 put_thumb32_insn (buf
, insn
);
25959 if (opcode
== T_MNEM_add_pc
)
25960 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25962 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25965 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25973 if (fragp
->fr_var
== 4)
25975 insn
= THUMB_OP32 (opcode
);
25976 insn
|= (old_op
& 0xf0) << 4;
25977 insn
|= (old_op
& 0xf) << 16;
25978 put_thumb32_insn (buf
, insn
);
25979 if (insn
& (1 << 20))
25980 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25982 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25985 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25991 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25992 (enum bfd_reloc_code_real
) reloc_type
);
25993 fixp
->fx_file
= fragp
->fr_file
;
25994 fixp
->fx_line
= fragp
->fr_line
;
25995 fragp
->fr_fix
+= fragp
->fr_var
;
25997 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25998 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25999 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26000 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26003 /* Return the size of a relaxable immediate operand instruction.
26004 SHIFT and SIZE specify the form of the allowable immediate. */
26006 relax_immediate (fragS
*fragp
, int size
, int shift
)
26012 /* ??? Should be able to do better than this. */
26013 if (fragp
->fr_symbol
)
26016 low
= (1 << shift
) - 1;
26017 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26018 offset
= fragp
->fr_offset
;
26019 /* Force misaligned offsets to 32-bit variant. */
26022 if (offset
& ~mask
)
26027 /* Get the address of a symbol during relaxation. */
26029 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26035 sym
= fragp
->fr_symbol
;
26036 sym_frag
= symbol_get_frag (sym
);
26037 know (S_GET_SEGMENT (sym
) != absolute_section
26038 || sym_frag
== &zero_address_frag
);
26039 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26041 /* If frag has yet to be reached on this pass, assume it will
26042 move by STRETCH just as we did. If this is not so, it will
26043 be because some frag between grows, and that will force
26047 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26051 /* Adjust stretch for any alignment frag. Note that if have
26052 been expanding the earlier code, the symbol may be
26053 defined in what appears to be an earlier frag. FIXME:
26054 This doesn't handle the fr_subtype field, which specifies
26055 a maximum number of bytes to skip when doing an
26057 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26059 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26062 stretch
= - ((- stretch
)
26063 & ~ ((1 << (int) f
->fr_offset
) - 1));
26065 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26077 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26080 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26085 /* Assume worst case for symbols not known to be in the same section. */
26086 if (fragp
->fr_symbol
== NULL
26087 || !S_IS_DEFINED (fragp
->fr_symbol
)
26088 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26089 || S_IS_WEAK (fragp
->fr_symbol
))
26092 val
= relaxed_symbol_addr (fragp
, stretch
);
26093 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26094 addr
= (addr
+ 4) & ~3;
26095 /* Force misaligned targets to 32-bit variant. */
26099 if (val
< 0 || val
> 1020)
26104 /* Return the size of a relaxable add/sub immediate instruction. */
26106 relax_addsub (fragS
*fragp
, asection
*sec
)
26111 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26112 op
= bfd_get_16(sec
->owner
, buf
);
26113 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26114 return relax_immediate (fragp
, 8, 0);
26116 return relax_immediate (fragp
, 3, 0);
26119 /* Return TRUE iff the definition of symbol S could be pre-empted
26120 (overridden) at link or load time. */
26122 symbol_preemptible (symbolS
*s
)
26124 /* Weak symbols can always be pre-empted. */
26128 /* Non-global symbols cannot be pre-empted. */
26129 if (! S_IS_EXTERNAL (s
))
26133 /* In ELF, a global symbol can be marked protected, or private. In that
26134 case it can't be pre-empted (other definitions in the same link unit
26135 would violate the ODR). */
26136 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26140 /* Other global symbols might be pre-empted. */
26144 /* Return the size of a relaxable branch instruction. BITS is the
26145 size of the offset field in the narrow instruction. */
26148 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26154 /* Assume worst case for symbols not known to be in the same section. */
26155 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26156 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26157 || S_IS_WEAK (fragp
->fr_symbol
))
26161 /* A branch to a function in ARM state will require interworking. */
26162 if (S_IS_DEFINED (fragp
->fr_symbol
)
26163 && ARM_IS_FUNC (fragp
->fr_symbol
))
26167 if (symbol_preemptible (fragp
->fr_symbol
))
26170 val
= relaxed_symbol_addr (fragp
, stretch
);
26171 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26174 /* Offset is a signed value *2 */
26176 if (val
>= limit
|| val
< -limit
)
26182 /* Relax a machine dependent frag. This returns the amount by which
26183 the current size of the frag should change. */
26186 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26191 oldsize
= fragp
->fr_var
;
26192 switch (fragp
->fr_subtype
)
26194 case T_MNEM_ldr_pc2
:
26195 newsize
= relax_adr (fragp
, sec
, stretch
);
26197 case T_MNEM_ldr_pc
:
26198 case T_MNEM_ldr_sp
:
26199 case T_MNEM_str_sp
:
26200 newsize
= relax_immediate (fragp
, 8, 2);
26204 newsize
= relax_immediate (fragp
, 5, 2);
26208 newsize
= relax_immediate (fragp
, 5, 1);
26212 newsize
= relax_immediate (fragp
, 5, 0);
26215 newsize
= relax_adr (fragp
, sec
, stretch
);
26221 newsize
= relax_immediate (fragp
, 8, 0);
26224 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26227 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26229 case T_MNEM_add_sp
:
26230 case T_MNEM_add_pc
:
26231 newsize
= relax_immediate (fragp
, 8, 2);
26233 case T_MNEM_inc_sp
:
26234 case T_MNEM_dec_sp
:
26235 newsize
= relax_immediate (fragp
, 7, 2);
26241 newsize
= relax_addsub (fragp
, sec
);
26247 fragp
->fr_var
= newsize
;
26248 /* Freeze wide instructions that are at or before the same location as
26249 in the previous pass. This avoids infinite loops.
26250 Don't freeze them unconditionally because targets may be artificially
26251 misaligned by the expansion of preceding frags. */
26252 if (stretch
<= 0 && newsize
> 2)
26254 md_convert_frag (sec
->owner
, sec
, fragp
);
26258 return newsize
- oldsize
;
26261 /* Round up a section size to the appropriate boundary. */
26264 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26270 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26271 of an rs_align_code fragment. */
26274 arm_handle_align (fragS
* fragP
)
26276 static unsigned char const arm_noop
[2][2][4] =
26279 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26280 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26283 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26284 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26287 static unsigned char const thumb_noop
[2][2][2] =
26290 {0xc0, 0x46}, /* LE */
26291 {0x46, 0xc0}, /* BE */
26294 {0x00, 0xbf}, /* LE */
26295 {0xbf, 0x00} /* BE */
26298 static unsigned char const wide_thumb_noop
[2][4] =
26299 { /* Wide Thumb-2 */
26300 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26301 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26304 unsigned bytes
, fix
, noop_size
;
26306 const unsigned char * noop
;
26307 const unsigned char *narrow_noop
= NULL
;
26312 if (fragP
->fr_type
!= rs_align_code
)
26315 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26316 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26319 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26320 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26322 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26324 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26326 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26327 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26329 narrow_noop
= thumb_noop
[1][target_big_endian
];
26330 noop
= wide_thumb_noop
[target_big_endian
];
26333 noop
= thumb_noop
[0][target_big_endian
];
26341 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26342 ? selected_cpu
: arm_arch_none
,
26344 [target_big_endian
];
26351 fragP
->fr_var
= noop_size
;
26353 if (bytes
& (noop_size
- 1))
26355 fix
= bytes
& (noop_size
- 1);
26357 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26359 memset (p
, 0, fix
);
26366 if (bytes
& noop_size
)
26368 /* Insert a narrow noop. */
26369 memcpy (p
, narrow_noop
, noop_size
);
26371 bytes
-= noop_size
;
26375 /* Use wide noops for the remainder */
26379 while (bytes
>= noop_size
)
26381 memcpy (p
, noop
, noop_size
);
26383 bytes
-= noop_size
;
26387 fragP
->fr_fix
+= fix
;
26390 /* Called from md_do_align. Used to create an alignment
26391 frag in a code section. */
26394 arm_frag_align_code (int n
, int max
)
26398 /* We assume that there will never be a requirement
26399 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26400 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26405 _("alignments greater than %d bytes not supported in .text sections."),
26406 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26407 as_fatal ("%s", err_msg
);
26410 p
= frag_var (rs_align_code
,
26411 MAX_MEM_FOR_RS_ALIGN_CODE
,
26413 (relax_substateT
) max
,
26420 /* Perform target specific initialisation of a frag.
26421 Note - despite the name this initialisation is not done when the frag
26422 is created, but only when its type is assigned. A frag can be created
26423 and used a long time before its type is set, so beware of assuming that
26424 this initialisation is performed first. */
26428 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26430 /* Record whether this frag is in an ARM or a THUMB area. */
26431 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26434 #else /* OBJ_ELF is defined. */
26436 arm_init_frag (fragS
* fragP
, int max_chars
)
26438 bfd_boolean frag_thumb_mode
;
26440 /* If the current ARM vs THUMB mode has not already
26441 been recorded into this frag then do so now. */
26442 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26443 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26445 /* PR 21809: Do not set a mapping state for debug sections
26446 - it just confuses other tools. */
26447 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26450 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26452 /* Record a mapping symbol for alignment frags. We will delete this
26453 later if the alignment ends up empty. */
26454 switch (fragP
->fr_type
)
26457 case rs_align_test
:
26459 mapping_state_2 (MAP_DATA
, max_chars
);
26461 case rs_align_code
:
26462 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26469 /* When we change sections we need to issue a new mapping symbol. */
26472 arm_elf_change_section (void)
26474 /* Link an unlinked unwind index table section to the .text section. */
26475 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26476 && elf_linked_to_section (now_seg
) == NULL
)
26477 elf_linked_to_section (now_seg
) = text_section
;
26481 arm_elf_section_type (const char * str
, size_t len
)
26483 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26484 return SHT_ARM_EXIDX
;
26489 /* Code to deal with unwinding tables. */
26491 static void add_unwind_adjustsp (offsetT
);
26493 /* Generate any deferred unwind frame offset. */
26496 flush_pending_unwind (void)
26500 offset
= unwind
.pending_offset
;
26501 unwind
.pending_offset
= 0;
26503 add_unwind_adjustsp (offset
);
26506 /* Add an opcode to this list for this function. Two-byte opcodes should
26507 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26511 add_unwind_opcode (valueT op
, int length
)
26513 /* Add any deferred stack adjustment. */
26514 if (unwind
.pending_offset
)
26515 flush_pending_unwind ();
26517 unwind
.sp_restored
= 0;
26519 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26521 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26522 if (unwind
.opcodes
)
26523 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26524 unwind
.opcode_alloc
);
26526 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26531 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26533 unwind
.opcode_count
++;
26537 /* Add unwind opcodes to adjust the stack pointer. */
26540 add_unwind_adjustsp (offsetT offset
)
26544 if (offset
> 0x200)
26546 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26551 /* Long form: 0xb2, uleb128. */
26552 /* This might not fit in a word so add the individual bytes,
26553 remembering the list is built in reverse order. */
26554 o
= (valueT
) ((offset
- 0x204) >> 2);
26556 add_unwind_opcode (0, 1);
26558 /* Calculate the uleb128 encoding of the offset. */
26562 bytes
[n
] = o
& 0x7f;
26568 /* Add the insn. */
26570 add_unwind_opcode (bytes
[n
- 1], 1);
26571 add_unwind_opcode (0xb2, 1);
26573 else if (offset
> 0x100)
26575 /* Two short opcodes. */
26576 add_unwind_opcode (0x3f, 1);
26577 op
= (offset
- 0x104) >> 2;
26578 add_unwind_opcode (op
, 1);
26580 else if (offset
> 0)
26582 /* Short opcode. */
26583 op
= (offset
- 4) >> 2;
26584 add_unwind_opcode (op
, 1);
26586 else if (offset
< 0)
26589 while (offset
> 0x100)
26591 add_unwind_opcode (0x7f, 1);
26594 op
= ((offset
- 4) >> 2) | 0x40;
26595 add_unwind_opcode (op
, 1);
26599 /* Finish the list of unwind opcodes for this function. */
26602 finish_unwind_opcodes (void)
26606 if (unwind
.fp_used
)
26608 /* Adjust sp as necessary. */
26609 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26610 flush_pending_unwind ();
26612 /* After restoring sp from the frame pointer. */
26613 op
= 0x90 | unwind
.fp_reg
;
26614 add_unwind_opcode (op
, 1);
26617 flush_pending_unwind ();
26621 /* Start an exception table entry. If idx is nonzero this is an index table
26625 start_unwind_section (const segT text_seg
, int idx
)
26627 const char * text_name
;
26628 const char * prefix
;
26629 const char * prefix_once
;
26630 const char * group_name
;
26638 prefix
= ELF_STRING_ARM_unwind
;
26639 prefix_once
= ELF_STRING_ARM_unwind_once
;
26640 type
= SHT_ARM_EXIDX
;
26644 prefix
= ELF_STRING_ARM_unwind_info
;
26645 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26646 type
= SHT_PROGBITS
;
26649 text_name
= segment_name (text_seg
);
26650 if (streq (text_name
, ".text"))
26653 if (strncmp (text_name
, ".gnu.linkonce.t.",
26654 strlen (".gnu.linkonce.t.")) == 0)
26656 prefix
= prefix_once
;
26657 text_name
+= strlen (".gnu.linkonce.t.");
26660 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26666 /* Handle COMDAT group. */
26667 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26669 group_name
= elf_group_name (text_seg
);
26670 if (group_name
== NULL
)
26672 as_bad (_("Group section `%s' has no group signature"),
26673 segment_name (text_seg
));
26674 ignore_rest_of_line ();
26677 flags
|= SHF_GROUP
;
26681 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26684 /* Set the section link for index tables. */
26686 elf_linked_to_section (now_seg
) = text_seg
;
26690 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26691 personality routine data. Returns zero, or the index table value for
26692 an inline entry. */
26695 create_unwind_entry (int have_data
)
26700 /* The current word of data. */
26702 /* The number of bytes left in this word. */
26705 finish_unwind_opcodes ();
26707 /* Remember the current text section. */
26708 unwind
.saved_seg
= now_seg
;
26709 unwind
.saved_subseg
= now_subseg
;
26711 start_unwind_section (now_seg
, 0);
26713 if (unwind
.personality_routine
== NULL
)
26715 if (unwind
.personality_index
== -2)
26718 as_bad (_("handlerdata in cantunwind frame"));
26719 return 1; /* EXIDX_CANTUNWIND. */
26722 /* Use a default personality routine if none is specified. */
26723 if (unwind
.personality_index
== -1)
26725 if (unwind
.opcode_count
> 3)
26726 unwind
.personality_index
= 1;
26728 unwind
.personality_index
= 0;
26731 /* Space for the personality routine entry. */
26732 if (unwind
.personality_index
== 0)
26734 if (unwind
.opcode_count
> 3)
26735 as_bad (_("too many unwind opcodes for personality routine 0"));
26739 /* All the data is inline in the index table. */
26742 while (unwind
.opcode_count
> 0)
26744 unwind
.opcode_count
--;
26745 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26749 /* Pad with "finish" opcodes. */
26751 data
= (data
<< 8) | 0xb0;
26758 /* We get two opcodes "free" in the first word. */
26759 size
= unwind
.opcode_count
- 2;
26763 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26764 if (unwind
.personality_index
!= -1)
26766 as_bad (_("attempt to recreate an unwind entry"));
26770 /* An extra byte is required for the opcode count. */
26771 size
= unwind
.opcode_count
+ 1;
26774 size
= (size
+ 3) >> 2;
26776 as_bad (_("too many unwind opcodes"));
26778 frag_align (2, 0, 0);
26779 record_alignment (now_seg
, 2);
26780 unwind
.table_entry
= expr_build_dot ();
26782 /* Allocate the table entry. */
26783 ptr
= frag_more ((size
<< 2) + 4);
26784 /* PR 13449: Zero the table entries in case some of them are not used. */
26785 memset (ptr
, 0, (size
<< 2) + 4);
26786 where
= frag_now_fix () - ((size
<< 2) + 4);
26788 switch (unwind
.personality_index
)
26791 /* ??? Should this be a PLT generating relocation? */
26792 /* Custom personality routine. */
26793 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26794 BFD_RELOC_ARM_PREL31
);
26799 /* Set the first byte to the number of additional words. */
26800 data
= size
> 0 ? size
- 1 : 0;
26804 /* ABI defined personality routines. */
26806 /* Three opcodes bytes are packed into the first word. */
26813 /* The size and first two opcode bytes go in the first word. */
26814 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26819 /* Should never happen. */
26823 /* Pack the opcodes into words (MSB first), reversing the list at the same
26825 while (unwind
.opcode_count
> 0)
26829 md_number_to_chars (ptr
, data
, 4);
26834 unwind
.opcode_count
--;
26836 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26839 /* Finish off the last word. */
26842 /* Pad with "finish" opcodes. */
26844 data
= (data
<< 8) | 0xb0;
26846 md_number_to_chars (ptr
, data
, 4);
26851 /* Add an empty descriptor if there is no user-specified data. */
26852 ptr
= frag_more (4);
26853 md_number_to_chars (ptr
, 0, 4);
26860 /* Initialize the DWARF-2 unwind information for this procedure. */
26863 tc_arm_frame_initial_instructions (void)
26865 cfi_add_CFA_def_cfa (REG_SP
, 0);
26867 #endif /* OBJ_ELF */
26869 /* Convert REGNAME to a DWARF-2 register number. */
26872 tc_arm_regname_to_dw2regnum (char *regname
)
26874 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26878 /* PR 16694: Allow VFP registers as well. */
26879 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26883 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26892 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26896 exp
.X_op
= O_secrel
;
26897 exp
.X_add_symbol
= symbol
;
26898 exp
.X_add_number
= 0;
26899 emit_expr (&exp
, size
);
26903 /* MD interface: Symbol and relocation handling. */
26905 /* Return the address within the segment that a PC-relative fixup is
26906 relative to. For ARM, PC-relative fixups applied to instructions
26907 are generally relative to the location of the fixup plus 8 bytes.
26908 Thumb branches are offset by 4, and Thumb loads relative to PC
26909 require special handling. */
26912 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26914 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26916 /* If this is pc-relative and we are going to emit a relocation
26917 then we just want to put out any pipeline compensation that the linker
26918 will need. Otherwise we want to use the calculated base.
26919 For WinCE we skip the bias for externals as well, since this
26920 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26922 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26923 || (arm_force_relocation (fixP
)
26925 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26931 switch (fixP
->fx_r_type
)
26933 /* PC relative addressing on the Thumb is slightly odd as the
26934 bottom two bits of the PC are forced to zero for the
26935 calculation. This happens *after* application of the
26936 pipeline offset. However, Thumb adrl already adjusts for
26937 this, so we need not do it again. */
26938 case BFD_RELOC_ARM_THUMB_ADD
:
26941 case BFD_RELOC_ARM_THUMB_OFFSET
:
26942 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26943 case BFD_RELOC_ARM_T32_ADD_PC12
:
26944 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26945 return (base
+ 4) & ~3;
26947 /* Thumb branches are simply offset by +4. */
26948 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26949 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26950 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26951 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26952 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26953 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26954 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26955 case BFD_RELOC_ARM_THUMB_BF17
:
26956 case BFD_RELOC_ARM_THUMB_BF19
:
26957 case BFD_RELOC_ARM_THUMB_BF13
:
26958 case BFD_RELOC_ARM_THUMB_LOOP12
:
26961 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26963 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26964 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26965 && ARM_IS_FUNC (fixP
->fx_addsy
)
26966 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26967 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26970 /* BLX is like branches above, but forces the low two bits of PC to
26972 case BFD_RELOC_THUMB_PCREL_BLX
:
26974 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26975 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26976 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26977 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26978 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26979 return (base
+ 4) & ~3;
26981 /* ARM mode branches are offset by +8. However, the Windows CE
26982 loader expects the relocation not to take this into account. */
26983 case BFD_RELOC_ARM_PCREL_BLX
:
26985 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26986 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26987 && ARM_IS_FUNC (fixP
->fx_addsy
)
26988 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26989 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26992 case BFD_RELOC_ARM_PCREL_CALL
:
26994 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26995 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26996 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26997 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26998 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27001 case BFD_RELOC_ARM_PCREL_BRANCH
:
27002 case BFD_RELOC_ARM_PCREL_JUMP
:
27003 case BFD_RELOC_ARM_PLT32
:
27005 /* When handling fixups immediately, because we have already
27006 discovered the value of a symbol, or the address of the frag involved
27007 we must account for the offset by +8, as the OS loader will never see the reloc.
27008 see fixup_segment() in write.c
27009 The S_IS_EXTERNAL test handles the case of global symbols.
27010 Those need the calculated base, not just the pipe compensation the linker will need. */
27012 && fixP
->fx_addsy
!= NULL
27013 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27014 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27022 /* ARM mode loads relative to PC are also offset by +8. Unlike
27023 branches, the Windows CE loader *does* expect the relocation
27024 to take this into account. */
27025 case BFD_RELOC_ARM_OFFSET_IMM
:
27026 case BFD_RELOC_ARM_OFFSET_IMM8
:
27027 case BFD_RELOC_ARM_HWLITERAL
:
27028 case BFD_RELOC_ARM_LITERAL
:
27029 case BFD_RELOC_ARM_CP_OFF_IMM
:
27033 /* Other PC-relative relocations are un-offset. */
27039 static bfd_boolean flag_warn_syms
= TRUE
;
27042 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27044 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27045 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27046 does mean that the resulting code might be very confusing to the reader.
27047 Also this warning can be triggered if the user omits an operand before
27048 an immediate address, eg:
27052 GAS treats this as an assignment of the value of the symbol foo to a
27053 symbol LDR, and so (without this code) it will not issue any kind of
27054 warning or error message.
27056 Note - ARM instructions are case-insensitive but the strings in the hash
27057 table are all stored in lower case, so we must first ensure that name is
27059 if (flag_warn_syms
&& arm_ops_hsh
)
27061 char * nbuf
= strdup (name
);
27064 for (p
= nbuf
; *p
; p
++)
27066 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27068 static struct hash_control
* already_warned
= NULL
;
27070 if (already_warned
== NULL
)
27071 already_warned
= hash_new ();
27072 /* Only warn about the symbol once. To keep the code
27073 simple we let hash_insert do the lookup for us. */
27074 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27075 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27084 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27085 Otherwise we have no need to default values of symbols. */
27088 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27091 if (name
[0] == '_' && name
[1] == 'G'
27092 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27096 if (symbol_find (name
))
27097 as_bad (_("GOT already in the symbol table"));
27099 GOT_symbol
= symbol_new (name
, undefined_section
,
27100 (valueT
) 0, & zero_address_frag
);
27110 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27111 computed as two separate immediate values, added together. We
27112 already know that this value cannot be computed by just one ARM
27115 static unsigned int
27116 validate_immediate_twopart (unsigned int val
,
27117 unsigned int * highpart
)
27122 for (i
= 0; i
< 32; i
+= 2)
27123 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27129 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27131 else if (a
& 0xff0000)
27133 if (a
& 0xff000000)
27135 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27139 gas_assert (a
& 0xff000000);
27140 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27143 return (a
& 0xff) | (i
<< 7);
27150 validate_offset_imm (unsigned int val
, int hwse
)
27152 if ((hwse
&& val
> 255) || val
> 4095)
27157 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27158 negative immediate constant by altering the instruction. A bit of
27163 by inverting the second operand, and
27166 by negating the second operand. */
27169 negate_data_op (unsigned long * instruction
,
27170 unsigned long value
)
27173 unsigned long negated
, inverted
;
27175 negated
= encode_arm_immediate (-value
);
27176 inverted
= encode_arm_immediate (~value
);
27178 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27181 /* First negates. */
27182 case OPCODE_SUB
: /* ADD <-> SUB */
27183 new_inst
= OPCODE_ADD
;
27188 new_inst
= OPCODE_SUB
;
27192 case OPCODE_CMP
: /* CMP <-> CMN */
27193 new_inst
= OPCODE_CMN
;
27198 new_inst
= OPCODE_CMP
;
27202 /* Now Inverted ops. */
27203 case OPCODE_MOV
: /* MOV <-> MVN */
27204 new_inst
= OPCODE_MVN
;
27209 new_inst
= OPCODE_MOV
;
27213 case OPCODE_AND
: /* AND <-> BIC */
27214 new_inst
= OPCODE_BIC
;
27219 new_inst
= OPCODE_AND
;
27223 case OPCODE_ADC
: /* ADC <-> SBC */
27224 new_inst
= OPCODE_SBC
;
27229 new_inst
= OPCODE_ADC
;
27233 /* We cannot do anything. */
27238 if (value
== (unsigned) FAIL
)
27241 *instruction
&= OPCODE_MASK
;
27242 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27246 /* Like negate_data_op, but for Thumb-2. */
27248 static unsigned int
27249 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27253 unsigned int negated
, inverted
;
27255 negated
= encode_thumb32_immediate (-value
);
27256 inverted
= encode_thumb32_immediate (~value
);
27258 rd
= (*instruction
>> 8) & 0xf;
27259 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27262 /* ADD <-> SUB. Includes CMP <-> CMN. */
27263 case T2_OPCODE_SUB
:
27264 new_inst
= T2_OPCODE_ADD
;
27268 case T2_OPCODE_ADD
:
27269 new_inst
= T2_OPCODE_SUB
;
27273 /* ORR <-> ORN. Includes MOV <-> MVN. */
27274 case T2_OPCODE_ORR
:
27275 new_inst
= T2_OPCODE_ORN
;
27279 case T2_OPCODE_ORN
:
27280 new_inst
= T2_OPCODE_ORR
;
27284 /* AND <-> BIC. TST has no inverted equivalent. */
27285 case T2_OPCODE_AND
:
27286 new_inst
= T2_OPCODE_BIC
;
27293 case T2_OPCODE_BIC
:
27294 new_inst
= T2_OPCODE_AND
;
27299 case T2_OPCODE_ADC
:
27300 new_inst
= T2_OPCODE_SBC
;
27304 case T2_OPCODE_SBC
:
27305 new_inst
= T2_OPCODE_ADC
;
27309 /* We cannot do anything. */
27314 if (value
== (unsigned int)FAIL
)
27317 *instruction
&= T2_OPCODE_MASK
;
27318 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27322 /* Read a 32-bit thumb instruction from buf. */
27324 static unsigned long
27325 get_thumb32_insn (char * buf
)
27327 unsigned long insn
;
27328 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27329 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27334 /* We usually want to set the low bit on the address of thumb function
27335 symbols. In particular .word foo - . should have the low bit set.
27336 Generic code tries to fold the difference of two symbols to
27337 a constant. Prevent this and force a relocation when the first symbols
27338 is a thumb function. */
27341 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27343 if (op
== O_subtract
27344 && l
->X_op
== O_symbol
27345 && r
->X_op
== O_symbol
27346 && THUMB_IS_FUNC (l
->X_add_symbol
))
27348 l
->X_op
= O_subtract
;
27349 l
->X_op_symbol
= r
->X_add_symbol
;
27350 l
->X_add_number
-= r
->X_add_number
;
27354 /* Process as normal. */
27358 /* Encode Thumb2 unconditional branches and calls. The encoding
27359 for the 2 are identical for the immediate values. */
27362 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27364 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27367 addressT S
, I1
, I2
, lo
, hi
;
27369 S
= (value
>> 24) & 0x01;
27370 I1
= (value
>> 23) & 0x01;
27371 I2
= (value
>> 22) & 0x01;
27372 hi
= (value
>> 12) & 0x3ff;
27373 lo
= (value
>> 1) & 0x7ff;
27374 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27375 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27376 newval
|= (S
<< 10) | hi
;
27377 newval2
&= ~T2I1I2MASK
;
27378 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27379 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27380 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27384 md_apply_fix (fixS
* fixP
,
27388 offsetT value
= * valP
;
27390 unsigned int newimm
;
27391 unsigned long temp
;
27393 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27395 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27397 /* Note whether this will delete the relocation. */
27399 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27402 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27403 consistency with the behaviour on 32-bit hosts. Remember value
27405 value
&= 0xffffffff;
27406 value
^= 0x80000000;
27407 value
-= 0x80000000;
27410 fixP
->fx_addnumber
= value
;
27412 /* Same treatment for fixP->fx_offset. */
27413 fixP
->fx_offset
&= 0xffffffff;
27414 fixP
->fx_offset
^= 0x80000000;
27415 fixP
->fx_offset
-= 0x80000000;
27417 switch (fixP
->fx_r_type
)
27419 case BFD_RELOC_NONE
:
27420 /* This will need to go in the object file. */
27424 case BFD_RELOC_ARM_IMMEDIATE
:
27425 /* We claim that this fixup has been processed here,
27426 even if in fact we generate an error because we do
27427 not have a reloc for it, so tc_gen_reloc will reject it. */
27430 if (fixP
->fx_addsy
)
27432 const char *msg
= 0;
27434 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27435 msg
= _("undefined symbol %s used as an immediate value");
27436 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27437 msg
= _("symbol %s is in a different section");
27438 else if (S_IS_WEAK (fixP
->fx_addsy
))
27439 msg
= _("symbol %s is weak and may be overridden later");
27443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27444 msg
, S_GET_NAME (fixP
->fx_addsy
));
27449 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27451 /* If the offset is negative, we should use encoding A2 for ADR. */
27452 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27453 newimm
= negate_data_op (&temp
, value
);
27456 newimm
= encode_arm_immediate (value
);
27458 /* If the instruction will fail, see if we can fix things up by
27459 changing the opcode. */
27460 if (newimm
== (unsigned int) FAIL
)
27461 newimm
= negate_data_op (&temp
, value
);
27462 /* MOV accepts both ARM modified immediate (A1 encoding) and
27463 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27464 When disassembling, MOV is preferred when there is no encoding
27466 if (newimm
== (unsigned int) FAIL
27467 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27468 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27469 && !((temp
>> SBIT_SHIFT
) & 0x1)
27470 && value
>= 0 && value
<= 0xffff)
27472 /* Clear bits[23:20] to change encoding from A1 to A2. */
27473 temp
&= 0xff0fffff;
27474 /* Encoding high 4bits imm. Code below will encode the remaining
27476 temp
|= (value
& 0x0000f000) << 4;
27477 newimm
= value
& 0x00000fff;
27481 if (newimm
== (unsigned int) FAIL
)
27483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27484 _("invalid constant (%lx) after fixup"),
27485 (unsigned long) value
);
27489 newimm
|= (temp
& 0xfffff000);
27490 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27493 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27495 unsigned int highpart
= 0;
27496 unsigned int newinsn
= 0xe1a00000; /* nop. */
27498 if (fixP
->fx_addsy
)
27500 const char *msg
= 0;
27502 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27503 msg
= _("undefined symbol %s used as an immediate value");
27504 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27505 msg
= _("symbol %s is in a different section");
27506 else if (S_IS_WEAK (fixP
->fx_addsy
))
27507 msg
= _("symbol %s is weak and may be overridden later");
27511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27512 msg
, S_GET_NAME (fixP
->fx_addsy
));
27517 newimm
= encode_arm_immediate (value
);
27518 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27520 /* If the instruction will fail, see if we can fix things up by
27521 changing the opcode. */
27522 if (newimm
== (unsigned int) FAIL
27523 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27525 /* No ? OK - try using two ADD instructions to generate
27527 newimm
= validate_immediate_twopart (value
, & highpart
);
27529 /* Yes - then make sure that the second instruction is
27531 if (newimm
!= (unsigned int) FAIL
)
27533 /* Still No ? Try using a negated value. */
27534 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27535 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27536 /* Otherwise - give up. */
27539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27540 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27545 /* Replace the first operand in the 2nd instruction (which
27546 is the PC) with the destination register. We have
27547 already added in the PC in the first instruction and we
27548 do not want to do it again. */
27549 newinsn
&= ~ 0xf0000;
27550 newinsn
|= ((newinsn
& 0x0f000) << 4);
27553 newimm
|= (temp
& 0xfffff000);
27554 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27556 highpart
|= (newinsn
& 0xfffff000);
27557 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27561 case BFD_RELOC_ARM_OFFSET_IMM
:
27562 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27564 /* Fall through. */
27566 case BFD_RELOC_ARM_LITERAL
:
27572 if (validate_offset_imm (value
, 0) == FAIL
)
27574 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27576 _("invalid literal constant: pool needs to be closer"));
27578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27579 _("bad immediate value for offset (%ld)"),
27584 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27586 newval
&= 0xfffff000;
27589 newval
&= 0xff7ff000;
27590 newval
|= value
| (sign
? INDEX_UP
: 0);
27592 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27595 case BFD_RELOC_ARM_OFFSET_IMM8
:
27596 case BFD_RELOC_ARM_HWLITERAL
:
27602 if (validate_offset_imm (value
, 1) == FAIL
)
27604 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27606 _("invalid literal constant: pool needs to be closer"));
27608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27609 _("bad immediate value for 8-bit offset (%ld)"),
27614 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27616 newval
&= 0xfffff0f0;
27619 newval
&= 0xff7ff0f0;
27620 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27622 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27625 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27626 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27628 _("bad immediate value for offset (%ld)"), (long) value
);
27631 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27633 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27636 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27637 /* This is a complicated relocation used for all varieties of Thumb32
27638 load/store instruction with immediate offset:
27640 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27641 *4, optional writeback(W)
27642 (doubleword load/store)
27644 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27645 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27646 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27647 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27648 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27650 Uppercase letters indicate bits that are already encoded at
27651 this point. Lowercase letters are our problem. For the
27652 second block of instructions, the secondary opcode nybble
27653 (bits 8..11) is present, and bit 23 is zero, even if this is
27654 a PC-relative operation. */
27655 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27657 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27659 if ((newval
& 0xf0000000) == 0xe0000000)
27661 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27663 newval
|= (1 << 23);
27666 if (value
% 4 != 0)
27668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27669 _("offset not a multiple of 4"));
27675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27676 _("offset out of range"));
27681 else if ((newval
& 0x000f0000) == 0x000f0000)
27683 /* PC-relative, 12-bit offset. */
27685 newval
|= (1 << 23);
27690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27691 _("offset out of range"));
27696 else if ((newval
& 0x00000100) == 0x00000100)
27698 /* Writeback: 8-bit, +/- offset. */
27700 newval
|= (1 << 9);
27705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27706 _("offset out of range"));
27711 else if ((newval
& 0x00000f00) == 0x00000e00)
27713 /* T-instruction: positive 8-bit offset. */
27714 if (value
< 0 || value
> 0xff)
27716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27717 _("offset out of range"));
27725 /* Positive 12-bit or negative 8-bit offset. */
27729 newval
|= (1 << 23);
27739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27740 _("offset out of range"));
27747 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27748 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27751 case BFD_RELOC_ARM_SHIFT_IMM
:
27752 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27753 if (((unsigned long) value
) > 32
27755 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27758 _("shift expression is too large"));
27763 /* Shifts of zero must be done as lsl. */
27765 else if (value
== 32)
27767 newval
&= 0xfffff07f;
27768 newval
|= (value
& 0x1f) << 7;
27769 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27772 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27773 case BFD_RELOC_ARM_T32_ADD_IMM
:
27774 case BFD_RELOC_ARM_T32_IMM12
:
27775 case BFD_RELOC_ARM_T32_ADD_PC12
:
27776 /* We claim that this fixup has been processed here,
27777 even if in fact we generate an error because we do
27778 not have a reloc for it, so tc_gen_reloc will reject it. */
27782 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27785 _("undefined symbol %s used as an immediate value"),
27786 S_GET_NAME (fixP
->fx_addsy
));
27790 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27792 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27795 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27796 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27797 Thumb2 modified immediate encoding (T2). */
27798 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27799 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27801 newimm
= encode_thumb32_immediate (value
);
27802 if (newimm
== (unsigned int) FAIL
)
27803 newimm
= thumb32_negate_data_op (&newval
, value
);
27805 if (newimm
== (unsigned int) FAIL
)
27807 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27809 /* Turn add/sum into addw/subw. */
27810 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27811 newval
= (newval
& 0xfeffffff) | 0x02000000;
27812 /* No flat 12-bit imm encoding for addsw/subsw. */
27813 if ((newval
& 0x00100000) == 0)
27815 /* 12 bit immediate for addw/subw. */
27819 newval
^= 0x00a00000;
27822 newimm
= (unsigned int) FAIL
;
27829 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27830 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27831 disassembling, MOV is preferred when there is no encoding
27833 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27834 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27835 but with the Rn field [19:16] set to 1111. */
27836 && (((newval
>> 16) & 0xf) == 0xf)
27837 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27838 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27839 && value
>= 0 && value
<= 0xffff)
27841 /* Toggle bit[25] to change encoding from T2 to T3. */
27843 /* Clear bits[19:16]. */
27844 newval
&= 0xfff0ffff;
27845 /* Encoding high 4bits imm. Code below will encode the
27846 remaining low 12bits. */
27847 newval
|= (value
& 0x0000f000) << 4;
27848 newimm
= value
& 0x00000fff;
27853 if (newimm
== (unsigned int)FAIL
)
27855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27856 _("invalid constant (%lx) after fixup"),
27857 (unsigned long) value
);
27861 newval
|= (newimm
& 0x800) << 15;
27862 newval
|= (newimm
& 0x700) << 4;
27863 newval
|= (newimm
& 0x0ff);
27865 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27866 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27869 case BFD_RELOC_ARM_SMC
:
27870 if (((unsigned long) value
) > 0xf)
27871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27872 _("invalid smc expression"));
27874 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27875 newval
|= (value
& 0xf);
27876 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27879 case BFD_RELOC_ARM_HVC
:
27880 if (((unsigned long) value
) > 0xffff)
27881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27882 _("invalid hvc expression"));
27883 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27884 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27885 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27888 case BFD_RELOC_ARM_SWI
:
27889 if (fixP
->tc_fix_data
!= 0)
27891 if (((unsigned long) value
) > 0xff)
27892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27893 _("invalid swi expression"));
27894 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27896 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27900 if (((unsigned long) value
) > 0x00ffffff)
27901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27902 _("invalid swi expression"));
27903 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27905 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27909 case BFD_RELOC_ARM_MULTI
:
27910 if (((unsigned long) value
) > 0xffff)
27911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27912 _("invalid expression in load/store multiple"));
27913 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27914 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27918 case BFD_RELOC_ARM_PCREL_CALL
:
27920 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27922 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27923 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27924 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27925 /* Flip the bl to blx. This is a simple flip
27926 bit here because we generate PCREL_CALL for
27927 unconditional bls. */
27929 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27930 newval
= newval
| 0x10000000;
27931 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27937 goto arm_branch_common
;
27939 case BFD_RELOC_ARM_PCREL_JUMP
:
27940 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27942 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27943 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27944 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27946 /* This would map to a bl<cond>, b<cond>,
27947 b<always> to a Thumb function. We
27948 need to force a relocation for this particular
27950 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27953 /* Fall through. */
27955 case BFD_RELOC_ARM_PLT32
:
27957 case BFD_RELOC_ARM_PCREL_BRANCH
:
27959 goto arm_branch_common
;
27961 case BFD_RELOC_ARM_PCREL_BLX
:
27964 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27966 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27967 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27968 && ARM_IS_FUNC (fixP
->fx_addsy
))
27970 /* Flip the blx to a bl and warn. */
27971 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27972 newval
= 0xeb000000;
27973 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27974 _("blx to '%s' an ARM ISA state function changed to bl"),
27976 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27982 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27983 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27987 /* We are going to store value (shifted right by two) in the
27988 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27989 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27993 _("misaligned branch destination"));
27994 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27995 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28000 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28001 newval
|= (value
>> 2) & 0x00ffffff;
28002 /* Set the H bit on BLX instructions. */
28006 newval
|= 0x01000000;
28008 newval
&= ~0x01000000;
28010 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28014 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28015 /* CBZ can only branch forward. */
28017 /* Attempts to use CBZ to branch to the next instruction
28018 (which, strictly speaking, are prohibited) will be turned into
28021 FIXME: It may be better to remove the instruction completely and
28022 perform relaxation. */
28025 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28026 newval
= 0xbf00; /* NOP encoding T1 */
28027 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28034 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28036 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28037 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28038 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28043 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28044 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
28045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28047 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28049 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28050 newval
|= (value
& 0x1ff) >> 1;
28051 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28055 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28056 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
28057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28059 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28061 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28062 newval
|= (value
& 0xfff) >> 1;
28063 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28067 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28069 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28070 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28071 && ARM_IS_FUNC (fixP
->fx_addsy
)
28072 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28074 /* Force a relocation for a branch 20 bits wide. */
28077 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
28078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28079 _("conditional branch out of range"));
28081 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28084 addressT S
, J1
, J2
, lo
, hi
;
28086 S
= (value
& 0x00100000) >> 20;
28087 J2
= (value
& 0x00080000) >> 19;
28088 J1
= (value
& 0x00040000) >> 18;
28089 hi
= (value
& 0x0003f000) >> 12;
28090 lo
= (value
& 0x00000ffe) >> 1;
28092 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28093 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28094 newval
|= (S
<< 10) | hi
;
28095 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28096 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28097 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28101 case BFD_RELOC_THUMB_PCREL_BLX
:
28102 /* If there is a blx from a thumb state function to
28103 another thumb function flip this to a bl and warn
28107 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28108 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28109 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28111 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28112 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28113 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28115 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28116 newval
= newval
| 0x1000;
28117 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28118 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28123 goto thumb_bl_common
;
28125 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28126 /* A bl from Thumb state ISA to an internal ARM state function
28127 is converted to a blx. */
28129 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28130 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28131 && ARM_IS_FUNC (fixP
->fx_addsy
)
28132 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28134 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28135 newval
= newval
& ~0x1000;
28136 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28137 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28143 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28144 /* For a BLX instruction, make sure that the relocation is rounded up
28145 to a word boundary. This follows the semantics of the instruction
28146 which specifies that bit 1 of the target address will come from bit
28147 1 of the base address. */
28148 value
= (value
+ 3) & ~ 3;
28151 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28152 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28153 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28156 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
28158 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28160 else if ((value
& ~0x1ffffff)
28161 && ((value
& ~0x1ffffff) != ~0x1ffffff))
28162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28163 _("Thumb2 branch out of range"));
28166 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28167 encode_thumb2_b_bl_offset (buf
, value
);
28171 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28172 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
28173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28175 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28176 encode_thumb2_b_bl_offset (buf
, value
);
28181 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28186 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28187 md_number_to_chars (buf
, value
, 2);
28191 case BFD_RELOC_ARM_TLS_CALL
:
28192 case BFD_RELOC_ARM_THM_TLS_CALL
:
28193 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28194 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28195 case BFD_RELOC_ARM_TLS_GOTDESC
:
28196 case BFD_RELOC_ARM_TLS_GD32
:
28197 case BFD_RELOC_ARM_TLS_LE32
:
28198 case BFD_RELOC_ARM_TLS_IE32
:
28199 case BFD_RELOC_ARM_TLS_LDM32
:
28200 case BFD_RELOC_ARM_TLS_LDO32
:
28201 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28204 /* Same handling as above, but with the arm_fdpic guard. */
28205 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28206 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28207 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28210 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28215 _("Relocation supported only in FDPIC mode"));
28219 case BFD_RELOC_ARM_GOT32
:
28220 case BFD_RELOC_ARM_GOTOFF
:
28223 case BFD_RELOC_ARM_GOT_PREL
:
28224 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28225 md_number_to_chars (buf
, value
, 4);
28228 case BFD_RELOC_ARM_TARGET2
:
28229 /* TARGET2 is not partial-inplace, so we need to write the
28230 addend here for REL targets, because it won't be written out
28231 during reloc processing later. */
28232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28233 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28236 /* Relocations for FDPIC. */
28237 case BFD_RELOC_ARM_GOTFUNCDESC
:
28238 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28239 case BFD_RELOC_ARM_FUNCDESC
:
28242 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28243 md_number_to_chars (buf
, 0, 4);
28247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28248 _("Relocation supported only in FDPIC mode"));
28253 case BFD_RELOC_RVA
:
28255 case BFD_RELOC_ARM_TARGET1
:
28256 case BFD_RELOC_ARM_ROSEGREL32
:
28257 case BFD_RELOC_ARM_SBREL32
:
28258 case BFD_RELOC_32_PCREL
:
28260 case BFD_RELOC_32_SECREL
:
28262 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28264 /* For WinCE we only do this for pcrel fixups. */
28265 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28267 md_number_to_chars (buf
, value
, 4);
28271 case BFD_RELOC_ARM_PREL31
:
28272 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28274 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28275 if ((value
^ (value
>> 1)) & 0x40000000)
28277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28278 _("rel31 relocation overflow"));
28280 newval
|= value
& 0x7fffffff;
28281 md_number_to_chars (buf
, newval
, 4);
28286 case BFD_RELOC_ARM_CP_OFF_IMM
:
28287 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28288 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28289 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28290 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28292 newval
= get_thumb32_insn (buf
);
28293 if ((newval
& 0x0f200f00) == 0x0d000900)
28295 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28296 has permitted values that are multiples of 2, in the range 0
28298 if (value
< -510 || value
> 510 || (value
& 1))
28299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28300 _("co-processor offset out of range"));
28302 else if ((newval
& 0xfe001f80) == 0xec000f80)
28304 if (value
< -511 || value
> 512 || (value
& 3))
28305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28306 _("co-processor offset out of range"));
28308 else if (value
< -1023 || value
> 1023 || (value
& 3))
28309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28310 _("co-processor offset out of range"));
28315 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28316 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28317 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28319 newval
= get_thumb32_insn (buf
);
28322 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28323 newval
&= 0xffffff80;
28325 newval
&= 0xffffff00;
28329 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28330 newval
&= 0xff7fff80;
28332 newval
&= 0xff7fff00;
28333 if ((newval
& 0x0f200f00) == 0x0d000900)
28335 /* This is a fp16 vstr/vldr.
28337 It requires the immediate offset in the instruction is shifted
28338 left by 1 to be a half-word offset.
28340 Here, left shift by 1 first, and later right shift by 2
28341 should get the right offset. */
28344 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28346 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28347 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28348 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28350 put_thumb32_insn (buf
, newval
);
28353 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28354 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28355 if (value
< -255 || value
> 255)
28356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28357 _("co-processor offset out of range"));
28359 goto cp_off_common
;
28361 case BFD_RELOC_ARM_THUMB_OFFSET
:
28362 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28363 /* Exactly what ranges, and where the offset is inserted depends
28364 on the type of instruction, we can establish this from the
28366 switch (newval
>> 12)
28368 case 4: /* PC load. */
28369 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28370 forced to zero for these loads; md_pcrel_from has already
28371 compensated for this. */
28373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28374 _("invalid offset, target not word aligned (0x%08lX)"),
28375 (((unsigned long) fixP
->fx_frag
->fr_address
28376 + (unsigned long) fixP
->fx_where
) & ~3)
28377 + (unsigned long) value
);
28379 if (value
& ~0x3fc)
28380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28381 _("invalid offset, value too big (0x%08lX)"),
28384 newval
|= value
>> 2;
28387 case 9: /* SP load/store. */
28388 if (value
& ~0x3fc)
28389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28390 _("invalid offset, value too big (0x%08lX)"),
28392 newval
|= value
>> 2;
28395 case 6: /* Word load/store. */
28397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28398 _("invalid offset, value too big (0x%08lX)"),
28400 newval
|= value
<< 4; /* 6 - 2. */
28403 case 7: /* Byte load/store. */
28405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28406 _("invalid offset, value too big (0x%08lX)"),
28408 newval
|= value
<< 6;
28411 case 8: /* Halfword load/store. */
28413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28414 _("invalid offset, value too big (0x%08lX)"),
28416 newval
|= value
<< 5; /* 6 - 1. */
28420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28421 "Unable to process relocation for thumb opcode: %lx",
28422 (unsigned long) newval
);
28425 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28428 case BFD_RELOC_ARM_THUMB_ADD
:
28429 /* This is a complicated relocation, since we use it for all of
28430 the following immediate relocations:
28434 9bit ADD/SUB SP word-aligned
28435 10bit ADD PC/SP word-aligned
28437 The type of instruction being processed is encoded in the
28444 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28446 int rd
= (newval
>> 4) & 0xf;
28447 int rs
= newval
& 0xf;
28448 int subtract
= !!(newval
& 0x8000);
28450 /* Check for HI regs, only very restricted cases allowed:
28451 Adjusting SP, and using PC or SP to get an address. */
28452 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28453 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28455 _("invalid Hi register with immediate"));
28457 /* If value is negative, choose the opposite instruction. */
28461 subtract
= !subtract
;
28463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28464 _("immediate value out of range"));
28469 if (value
& ~0x1fc)
28470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28471 _("invalid immediate for stack address calculation"));
28472 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28473 newval
|= value
>> 2;
28475 else if (rs
== REG_PC
|| rs
== REG_SP
)
28477 /* PR gas/18541. If the addition is for a defined symbol
28478 within range of an ADR instruction then accept it. */
28481 && fixP
->fx_addsy
!= NULL
)
28485 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28486 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28487 || S_IS_WEAK (fixP
->fx_addsy
))
28489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28490 _("address calculation needs a strongly defined nearby symbol"));
28494 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28496 /* Round up to the next 4-byte boundary. */
28501 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28506 _("symbol too far away"));
28516 if (subtract
|| value
& ~0x3fc)
28517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28518 _("invalid immediate for address calculation (value = 0x%08lX)"),
28519 (unsigned long) (subtract
? - value
: value
));
28520 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28522 newval
|= value
>> 2;
28527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28528 _("immediate value out of range"));
28529 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28530 newval
|= (rd
<< 8) | value
;
28535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28536 _("immediate value out of range"));
28537 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28538 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28541 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28544 case BFD_RELOC_ARM_THUMB_IMM
:
28545 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28546 if (value
< 0 || value
> 255)
28547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28548 _("invalid immediate: %ld is out of range"),
28551 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28554 case BFD_RELOC_ARM_THUMB_SHIFT
:
28555 /* 5bit shift value (0..32). LSL cannot take 32. */
28556 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28557 temp
= newval
& 0xf800;
28558 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28560 _("invalid shift value: %ld"), (long) value
);
28561 /* Shifts of zero must be encoded as LSL. */
28563 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28564 /* Shifts of 32 are encoded as zero. */
28565 else if (value
== 32)
28567 newval
|= value
<< 6;
28568 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28571 case BFD_RELOC_VTABLE_INHERIT
:
28572 case BFD_RELOC_VTABLE_ENTRY
:
28576 case BFD_RELOC_ARM_MOVW
:
28577 case BFD_RELOC_ARM_MOVT
:
28578 case BFD_RELOC_ARM_THUMB_MOVW
:
28579 case BFD_RELOC_ARM_THUMB_MOVT
:
28580 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28582 /* REL format relocations are limited to a 16-bit addend. */
28583 if (!fixP
->fx_done
)
28585 if (value
< -0x8000 || value
> 0x7fff)
28586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28587 _("offset out of range"));
28589 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28590 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28595 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28596 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28598 newval
= get_thumb32_insn (buf
);
28599 newval
&= 0xfbf08f00;
28600 newval
|= (value
& 0xf000) << 4;
28601 newval
|= (value
& 0x0800) << 15;
28602 newval
|= (value
& 0x0700) << 4;
28603 newval
|= (value
& 0x00ff);
28604 put_thumb32_insn (buf
, newval
);
28608 newval
= md_chars_to_number (buf
, 4);
28609 newval
&= 0xfff0f000;
28610 newval
|= value
& 0x0fff;
28611 newval
|= (value
& 0xf000) << 4;
28612 md_number_to_chars (buf
, newval
, 4);
28617 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28618 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28619 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28620 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28621 gas_assert (!fixP
->fx_done
);
28624 bfd_boolean is_mov
;
28625 bfd_vma encoded_addend
= value
;
28627 /* Check that addend can be encoded in instruction. */
28628 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28630 _("the offset 0x%08lX is not representable"),
28631 (unsigned long) encoded_addend
);
28633 /* Extract the instruction. */
28634 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28635 is_mov
= (insn
& 0xf800) == 0x2000;
28640 if (!seg
->use_rela_p
)
28641 insn
|= encoded_addend
;
28647 /* Extract the instruction. */
28648 /* Encoding is the following
28653 /* The following conditions must be true :
28658 rd
= (insn
>> 4) & 0xf;
28660 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28662 _("Unable to process relocation for thumb opcode: %lx"),
28663 (unsigned long) insn
);
28665 /* Encode as ADD immediate8 thumb 1 code. */
28666 insn
= 0x3000 | (rd
<< 8);
28668 /* Place the encoded addend into the first 8 bits of the
28670 if (!seg
->use_rela_p
)
28671 insn
|= encoded_addend
;
28674 /* Update the instruction. */
28675 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28679 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28680 case BFD_RELOC_ARM_ALU_PC_G0
:
28681 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28682 case BFD_RELOC_ARM_ALU_PC_G1
:
28683 case BFD_RELOC_ARM_ALU_PC_G2
:
28684 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28685 case BFD_RELOC_ARM_ALU_SB_G0
:
28686 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28687 case BFD_RELOC_ARM_ALU_SB_G1
:
28688 case BFD_RELOC_ARM_ALU_SB_G2
:
28689 gas_assert (!fixP
->fx_done
);
28690 if (!seg
->use_rela_p
)
28693 bfd_vma encoded_addend
;
28694 bfd_vma addend_abs
= llabs (value
);
28696 /* Check that the absolute value of the addend can be
28697 expressed as an 8-bit constant plus a rotation. */
28698 encoded_addend
= encode_arm_immediate (addend_abs
);
28699 if (encoded_addend
== (unsigned int) FAIL
)
28700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28701 _("the offset 0x%08lX is not representable"),
28702 (unsigned long) addend_abs
);
28704 /* Extract the instruction. */
28705 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28707 /* If the addend is positive, use an ADD instruction.
28708 Otherwise use a SUB. Take care not to destroy the S bit. */
28709 insn
&= 0xff1fffff;
28715 /* Place the encoded addend into the first 12 bits of the
28717 insn
&= 0xfffff000;
28718 insn
|= encoded_addend
;
28720 /* Update the instruction. */
28721 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28725 case BFD_RELOC_ARM_LDR_PC_G0
:
28726 case BFD_RELOC_ARM_LDR_PC_G1
:
28727 case BFD_RELOC_ARM_LDR_PC_G2
:
28728 case BFD_RELOC_ARM_LDR_SB_G0
:
28729 case BFD_RELOC_ARM_LDR_SB_G1
:
28730 case BFD_RELOC_ARM_LDR_SB_G2
:
28731 gas_assert (!fixP
->fx_done
);
28732 if (!seg
->use_rela_p
)
28735 bfd_vma addend_abs
= llabs (value
);
28737 /* Check that the absolute value of the addend can be
28738 encoded in 12 bits. */
28739 if (addend_abs
>= 0x1000)
28740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28741 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28742 (unsigned long) addend_abs
);
28744 /* Extract the instruction. */
28745 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28747 /* If the addend is negative, clear bit 23 of the instruction.
28748 Otherwise set it. */
28750 insn
&= ~(1 << 23);
28754 /* Place the absolute value of the addend into the first 12 bits
28755 of the instruction. */
28756 insn
&= 0xfffff000;
28757 insn
|= addend_abs
;
28759 /* Update the instruction. */
28760 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28764 case BFD_RELOC_ARM_LDRS_PC_G0
:
28765 case BFD_RELOC_ARM_LDRS_PC_G1
:
28766 case BFD_RELOC_ARM_LDRS_PC_G2
:
28767 case BFD_RELOC_ARM_LDRS_SB_G0
:
28768 case BFD_RELOC_ARM_LDRS_SB_G1
:
28769 case BFD_RELOC_ARM_LDRS_SB_G2
:
28770 gas_assert (!fixP
->fx_done
);
28771 if (!seg
->use_rela_p
)
28774 bfd_vma addend_abs
= llabs (value
);
28776 /* Check that the absolute value of the addend can be
28777 encoded in 8 bits. */
28778 if (addend_abs
>= 0x100)
28779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28780 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28781 (unsigned long) addend_abs
);
28783 /* Extract the instruction. */
28784 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28786 /* If the addend is negative, clear bit 23 of the instruction.
28787 Otherwise set it. */
28789 insn
&= ~(1 << 23);
28793 /* Place the first four bits of the absolute value of the addend
28794 into the first 4 bits of the instruction, and the remaining
28795 four into bits 8 .. 11. */
28796 insn
&= 0xfffff0f0;
28797 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28799 /* Update the instruction. */
28800 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28804 case BFD_RELOC_ARM_LDC_PC_G0
:
28805 case BFD_RELOC_ARM_LDC_PC_G1
:
28806 case BFD_RELOC_ARM_LDC_PC_G2
:
28807 case BFD_RELOC_ARM_LDC_SB_G0
:
28808 case BFD_RELOC_ARM_LDC_SB_G1
:
28809 case BFD_RELOC_ARM_LDC_SB_G2
:
28810 gas_assert (!fixP
->fx_done
);
28811 if (!seg
->use_rela_p
)
28814 bfd_vma addend_abs
= llabs (value
);
28816 /* Check that the absolute value of the addend is a multiple of
28817 four and, when divided by four, fits in 8 bits. */
28818 if (addend_abs
& 0x3)
28819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28820 _("bad offset 0x%08lX (must be word-aligned)"),
28821 (unsigned long) addend_abs
);
28823 if ((addend_abs
>> 2) > 0xff)
28824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28825 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28826 (unsigned long) addend_abs
);
28828 /* Extract the instruction. */
28829 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28831 /* If the addend is negative, clear bit 23 of the instruction.
28832 Otherwise set it. */
28834 insn
&= ~(1 << 23);
28838 /* Place the addend (divided by four) into the first eight
28839 bits of the instruction. */
28840 insn
&= 0xfffffff0;
28841 insn
|= addend_abs
>> 2;
28843 /* Update the instruction. */
28844 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28848 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28850 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28851 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28852 && ARM_IS_FUNC (fixP
->fx_addsy
)
28853 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28855 /* Force a relocation for a branch 5 bits wide. */
28858 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28862 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28864 addressT boff
= value
>> 1;
28866 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28867 newval
|= (boff
<< 7);
28868 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28872 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28874 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28875 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28876 && ARM_IS_FUNC (fixP
->fx_addsy
)
28877 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28881 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28883 _("branch out of range"));
28885 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28887 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28889 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28890 addressT diff
= value
- boff
;
28894 newval
|= 1 << 1; /* T bit. */
28896 else if (diff
!= 2)
28898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28899 _("out of range label-relative fixup value"));
28901 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28905 case BFD_RELOC_ARM_THUMB_BF17
:
28907 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28908 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28909 && ARM_IS_FUNC (fixP
->fx_addsy
)
28910 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28912 /* Force a relocation for a branch 17 bits wide. */
28916 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28920 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28923 addressT immA
, immB
, immC
;
28925 immA
= (value
& 0x0001f000) >> 12;
28926 immB
= (value
& 0x00000ffc) >> 2;
28927 immC
= (value
& 0x00000002) >> 1;
28929 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28930 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28932 newval2
|= (immC
<< 11) | (immB
<< 1);
28933 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28934 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28938 case BFD_RELOC_ARM_THUMB_BF19
:
28940 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28941 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28942 && ARM_IS_FUNC (fixP
->fx_addsy
)
28943 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28945 /* Force a relocation for a branch 19 bits wide. */
28949 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28953 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28956 addressT immA
, immB
, immC
;
28958 immA
= (value
& 0x0007f000) >> 12;
28959 immB
= (value
& 0x00000ffc) >> 2;
28960 immC
= (value
& 0x00000002) >> 1;
28962 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28963 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28965 newval2
|= (immC
<< 11) | (immB
<< 1);
28966 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28967 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28971 case BFD_RELOC_ARM_THUMB_BF13
:
28973 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28974 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28975 && ARM_IS_FUNC (fixP
->fx_addsy
)
28976 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28978 /* Force a relocation for a branch 13 bits wide. */
28982 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28986 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28989 addressT immA
, immB
, immC
;
28991 immA
= (value
& 0x00001000) >> 12;
28992 immB
= (value
& 0x00000ffc) >> 2;
28993 immC
= (value
& 0x00000002) >> 1;
28995 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28996 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28998 newval2
|= (immC
<< 11) | (immB
<< 1);
28999 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29000 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29004 case BFD_RELOC_ARM_THUMB_LOOP12
:
29006 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29007 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29008 && ARM_IS_FUNC (fixP
->fx_addsy
)
29009 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29011 /* Force a relocation for a branch 12 bits wide. */
29015 bfd_vma insn
= get_thumb32_insn (buf
);
29016 /* le lr, <label>, le <label> or letp lr, <label> */
29017 if (((insn
& 0xffffffff) == 0xf00fc001)
29018 || ((insn
& 0xffffffff) == 0xf02fc001)
29019 || ((insn
& 0xffffffff) == 0xf01fc001))
29022 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29025 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29027 addressT imml
, immh
;
29029 immh
= (value
& 0x00000ffc) >> 2;
29030 imml
= (value
& 0x00000002) >> 1;
29032 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29033 newval
|= (imml
<< 11) | (immh
<< 1);
29034 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29038 case BFD_RELOC_ARM_V4BX
:
29039 /* This will need to go in the object file. */
29043 case BFD_RELOC_UNUSED
:
29045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29046 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29050 /* Translate internal representation of relocation info to BFD target
29054 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29057 bfd_reloc_code_real_type code
;
29059 reloc
= XNEW (arelent
);
29061 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29062 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29063 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29065 if (fixp
->fx_pcrel
)
29067 if (section
->use_rela_p
)
29068 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29070 fixp
->fx_offset
= reloc
->address
;
29072 reloc
->addend
= fixp
->fx_offset
;
29074 switch (fixp
->fx_r_type
)
29077 if (fixp
->fx_pcrel
)
29079 code
= BFD_RELOC_8_PCREL
;
29082 /* Fall through. */
29085 if (fixp
->fx_pcrel
)
29087 code
= BFD_RELOC_16_PCREL
;
29090 /* Fall through. */
29093 if (fixp
->fx_pcrel
)
29095 code
= BFD_RELOC_32_PCREL
;
29098 /* Fall through. */
29100 case BFD_RELOC_ARM_MOVW
:
29101 if (fixp
->fx_pcrel
)
29103 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29106 /* Fall through. */
29108 case BFD_RELOC_ARM_MOVT
:
29109 if (fixp
->fx_pcrel
)
29111 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29114 /* Fall through. */
29116 case BFD_RELOC_ARM_THUMB_MOVW
:
29117 if (fixp
->fx_pcrel
)
29119 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29122 /* Fall through. */
29124 case BFD_RELOC_ARM_THUMB_MOVT
:
29125 if (fixp
->fx_pcrel
)
29127 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29130 /* Fall through. */
29132 case BFD_RELOC_NONE
:
29133 case BFD_RELOC_ARM_PCREL_BRANCH
:
29134 case BFD_RELOC_ARM_PCREL_BLX
:
29135 case BFD_RELOC_RVA
:
29136 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29137 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29138 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29139 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29140 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29141 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29142 case BFD_RELOC_VTABLE_ENTRY
:
29143 case BFD_RELOC_VTABLE_INHERIT
:
29145 case BFD_RELOC_32_SECREL
:
29147 code
= fixp
->fx_r_type
;
29150 case BFD_RELOC_THUMB_PCREL_BLX
:
29152 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29153 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29156 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29159 case BFD_RELOC_ARM_LITERAL
:
29160 case BFD_RELOC_ARM_HWLITERAL
:
29161 /* If this is called then the a literal has
29162 been referenced across a section boundary. */
29163 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29164 _("literal referenced across section boundary"));
29168 case BFD_RELOC_ARM_TLS_CALL
:
29169 case BFD_RELOC_ARM_THM_TLS_CALL
:
29170 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29171 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29172 case BFD_RELOC_ARM_GOT32
:
29173 case BFD_RELOC_ARM_GOTOFF
:
29174 case BFD_RELOC_ARM_GOT_PREL
:
29175 case BFD_RELOC_ARM_PLT32
:
29176 case BFD_RELOC_ARM_TARGET1
:
29177 case BFD_RELOC_ARM_ROSEGREL32
:
29178 case BFD_RELOC_ARM_SBREL32
:
29179 case BFD_RELOC_ARM_PREL31
:
29180 case BFD_RELOC_ARM_TARGET2
:
29181 case BFD_RELOC_ARM_TLS_LDO32
:
29182 case BFD_RELOC_ARM_PCREL_CALL
:
29183 case BFD_RELOC_ARM_PCREL_JUMP
:
29184 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29185 case BFD_RELOC_ARM_ALU_PC_G0
:
29186 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29187 case BFD_RELOC_ARM_ALU_PC_G1
:
29188 case BFD_RELOC_ARM_ALU_PC_G2
:
29189 case BFD_RELOC_ARM_LDR_PC_G0
:
29190 case BFD_RELOC_ARM_LDR_PC_G1
:
29191 case BFD_RELOC_ARM_LDR_PC_G2
:
29192 case BFD_RELOC_ARM_LDRS_PC_G0
:
29193 case BFD_RELOC_ARM_LDRS_PC_G1
:
29194 case BFD_RELOC_ARM_LDRS_PC_G2
:
29195 case BFD_RELOC_ARM_LDC_PC_G0
:
29196 case BFD_RELOC_ARM_LDC_PC_G1
:
29197 case BFD_RELOC_ARM_LDC_PC_G2
:
29198 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29199 case BFD_RELOC_ARM_ALU_SB_G0
:
29200 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29201 case BFD_RELOC_ARM_ALU_SB_G1
:
29202 case BFD_RELOC_ARM_ALU_SB_G2
:
29203 case BFD_RELOC_ARM_LDR_SB_G0
:
29204 case BFD_RELOC_ARM_LDR_SB_G1
:
29205 case BFD_RELOC_ARM_LDR_SB_G2
:
29206 case BFD_RELOC_ARM_LDRS_SB_G0
:
29207 case BFD_RELOC_ARM_LDRS_SB_G1
:
29208 case BFD_RELOC_ARM_LDRS_SB_G2
:
29209 case BFD_RELOC_ARM_LDC_SB_G0
:
29210 case BFD_RELOC_ARM_LDC_SB_G1
:
29211 case BFD_RELOC_ARM_LDC_SB_G2
:
29212 case BFD_RELOC_ARM_V4BX
:
29213 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29214 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29215 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29216 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29217 case BFD_RELOC_ARM_GOTFUNCDESC
:
29218 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29219 case BFD_RELOC_ARM_FUNCDESC
:
29220 case BFD_RELOC_ARM_THUMB_BF17
:
29221 case BFD_RELOC_ARM_THUMB_BF19
:
29222 case BFD_RELOC_ARM_THUMB_BF13
:
29223 code
= fixp
->fx_r_type
;
29226 case BFD_RELOC_ARM_TLS_GOTDESC
:
29227 case BFD_RELOC_ARM_TLS_GD32
:
29228 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29229 case BFD_RELOC_ARM_TLS_LE32
:
29230 case BFD_RELOC_ARM_TLS_IE32
:
29231 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29232 case BFD_RELOC_ARM_TLS_LDM32
:
29233 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29234 /* BFD will include the symbol's address in the addend.
29235 But we don't want that, so subtract it out again here. */
29236 if (!S_IS_COMMON (fixp
->fx_addsy
))
29237 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29238 code
= fixp
->fx_r_type
;
29242 case BFD_RELOC_ARM_IMMEDIATE
:
29243 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29244 _("internal relocation (type: IMMEDIATE) not fixed up"));
29247 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29249 _("ADRL used for a symbol not defined in the same file"));
29252 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29253 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29254 case BFD_RELOC_ARM_THUMB_LOOP12
:
29255 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29256 _("%s used for a symbol not defined in the same file"),
29257 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29260 case BFD_RELOC_ARM_OFFSET_IMM
:
29261 if (section
->use_rela_p
)
29263 code
= fixp
->fx_r_type
;
29267 if (fixp
->fx_addsy
!= NULL
29268 && !S_IS_DEFINED (fixp
->fx_addsy
)
29269 && S_IS_LOCAL (fixp
->fx_addsy
))
29271 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29272 _("undefined local label `%s'"),
29273 S_GET_NAME (fixp
->fx_addsy
));
29277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29278 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29285 switch (fixp
->fx_r_type
)
29287 case BFD_RELOC_NONE
: type
= "NONE"; break;
29288 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29289 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29290 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29291 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29292 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29293 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29294 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29295 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29296 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29297 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29298 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29299 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29300 default: type
= _("<unknown>"); break;
29302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29303 _("cannot represent %s relocation in this object file format"),
29310 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29312 && fixp
->fx_addsy
== GOT_symbol
)
29314 code
= BFD_RELOC_ARM_GOTPC
;
29315 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29319 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29321 if (reloc
->howto
== NULL
)
29323 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29324 _("cannot represent %s relocation in this object file format"),
29325 bfd_get_reloc_code_name (code
));
29329 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29330 vtable entry to be used in the relocation's section offset. */
29331 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29332 reloc
->address
= fixp
->fx_offset
;
29337 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29340 cons_fix_new_arm (fragS
* frag
,
29344 bfd_reloc_code_real_type reloc
)
29349 FIXME: @@ Should look at CPU word size. */
29353 reloc
= BFD_RELOC_8
;
29356 reloc
= BFD_RELOC_16
;
29360 reloc
= BFD_RELOC_32
;
29363 reloc
= BFD_RELOC_64
;
29368 if (exp
->X_op
== O_secrel
)
29370 exp
->X_op
= O_symbol
;
29371 reloc
= BFD_RELOC_32_SECREL
;
29375 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29378 #if defined (OBJ_COFF)
29380 arm_validate_fix (fixS
* fixP
)
29382 /* If the destination of the branch is a defined symbol which does not have
29383 the THUMB_FUNC attribute, then we must be calling a function which has
29384 the (interfacearm) attribute. We look for the Thumb entry point to that
29385 function and change the branch to refer to that function instead. */
29386 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29387 && fixP
->fx_addsy
!= NULL
29388 && S_IS_DEFINED (fixP
->fx_addsy
)
29389 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29391 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29398 arm_force_relocation (struct fix
* fixp
)
29400 #if defined (OBJ_COFF) && defined (TE_PE)
29401 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29405 /* In case we have a call or a branch to a function in ARM ISA mode from
29406 a thumb function or vice-versa force the relocation. These relocations
29407 are cleared off for some cores that might have blx and simple transformations
29411 switch (fixp
->fx_r_type
)
29413 case BFD_RELOC_ARM_PCREL_JUMP
:
29414 case BFD_RELOC_ARM_PCREL_CALL
:
29415 case BFD_RELOC_THUMB_PCREL_BLX
:
29416 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29420 case BFD_RELOC_ARM_PCREL_BLX
:
29421 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29422 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29423 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29424 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29433 /* Resolve these relocations even if the symbol is extern or weak.
29434 Technically this is probably wrong due to symbol preemption.
29435 In practice these relocations do not have enough range to be useful
29436 at dynamic link time, and some code (e.g. in the Linux kernel)
29437 expects these references to be resolved. */
29438 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29439 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29440 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29441 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29442 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29443 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29444 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29445 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29446 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29447 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29448 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29449 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29450 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29451 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29454 /* Always leave these relocations for the linker. */
29455 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29456 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29457 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29460 /* Always generate relocations against function symbols. */
29461 if (fixp
->fx_r_type
== BFD_RELOC_32
29463 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29466 return generic_force_reloc (fixp
);
29469 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29470 /* Relocations against function names must be left unadjusted,
29471 so that the linker can use this information to generate interworking
29472 stubs. The MIPS version of this function
29473 also prevents relocations that are mips-16 specific, but I do not
29474 know why it does this.
29477 There is one other problem that ought to be addressed here, but
29478 which currently is not: Taking the address of a label (rather
29479 than a function) and then later jumping to that address. Such
29480 addresses also ought to have their bottom bit set (assuming that
29481 they reside in Thumb code), but at the moment they will not. */
29484 arm_fix_adjustable (fixS
* fixP
)
29486 if (fixP
->fx_addsy
== NULL
)
29489 /* Preserve relocations against symbols with function type. */
29490 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29493 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29494 && fixP
->fx_subsy
== NULL
)
29497 /* We need the symbol name for the VTABLE entries. */
29498 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29499 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29502 /* Don't allow symbols to be discarded on GOT related relocs. */
29503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29504 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29505 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29506 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29507 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29508 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29509 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29510 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29511 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29512 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29513 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29514 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29515 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29516 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29517 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29518 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29519 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29522 /* Similarly for group relocations. */
29523 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29524 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29525 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29528 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29529 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29530 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29531 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29532 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29533 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29534 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29535 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29536 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29539 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29540 offsets, so keep these symbols. */
29541 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29542 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29547 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29551 elf32_arm_target_format (void)
29554 return (target_big_endian
29555 ? "elf32-bigarm-symbian"
29556 : "elf32-littlearm-symbian");
29557 #elif defined (TE_VXWORKS)
29558 return (target_big_endian
29559 ? "elf32-bigarm-vxworks"
29560 : "elf32-littlearm-vxworks");
29561 #elif defined (TE_NACL)
29562 return (target_big_endian
29563 ? "elf32-bigarm-nacl"
29564 : "elf32-littlearm-nacl");
29568 if (target_big_endian
)
29569 return "elf32-bigarm-fdpic";
29571 return "elf32-littlearm-fdpic";
29575 if (target_big_endian
)
29576 return "elf32-bigarm";
29578 return "elf32-littlearm";
29584 armelf_frob_symbol (symbolS
* symp
,
29587 elf_frob_symbol (symp
, puntp
);
29591 /* MD interface: Finalization. */
29596 literal_pool
* pool
;
29598 /* Ensure that all the predication blocks are properly closed. */
29599 check_pred_blocks_finished ();
29601 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29603 /* Put it at the end of the relevant section. */
29604 subseg_set (pool
->section
, pool
->sub_section
);
29606 arm_elf_change_section ();
29613 /* Remove any excess mapping symbols generated for alignment frags in
29614 SEC. We may have created a mapping symbol before a zero byte
29615 alignment; remove it if there's a mapping symbol after the
29618 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29619 void *dummy ATTRIBUTE_UNUSED
)
29621 segment_info_type
*seginfo
= seg_info (sec
);
29624 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29627 for (fragp
= seginfo
->frchainP
->frch_root
;
29629 fragp
= fragp
->fr_next
)
29631 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29632 fragS
*next
= fragp
->fr_next
;
29634 /* Variable-sized frags have been converted to fixed size by
29635 this point. But if this was variable-sized to start with,
29636 there will be a fixed-size frag after it. So don't handle
29638 if (sym
== NULL
|| next
== NULL
)
29641 if (S_GET_VALUE (sym
) < next
->fr_address
)
29642 /* Not at the end of this frag. */
29644 know (S_GET_VALUE (sym
) == next
->fr_address
);
29648 if (next
->tc_frag_data
.first_map
!= NULL
)
29650 /* Next frag starts with a mapping symbol. Discard this
29652 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29656 if (next
->fr_next
== NULL
)
29658 /* This mapping symbol is at the end of the section. Discard
29660 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29661 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29665 /* As long as we have empty frags without any mapping symbols,
29667 /* If the next frag is non-empty and does not start with a
29668 mapping symbol, then this mapping symbol is required. */
29669 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29672 next
= next
->fr_next
;
29674 while (next
!= NULL
);
29679 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29683 arm_adjust_symtab (void)
29688 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29690 if (ARM_IS_THUMB (sym
))
29692 if (THUMB_IS_FUNC (sym
))
29694 /* Mark the symbol as a Thumb function. */
29695 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29696 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29697 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29699 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29700 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29702 as_bad (_("%s: unexpected function type: %d"),
29703 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29705 else switch (S_GET_STORAGE_CLASS (sym
))
29708 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29711 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29714 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29722 if (ARM_IS_INTERWORK (sym
))
29723 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29730 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29732 if (ARM_IS_THUMB (sym
))
29734 elf_symbol_type
* elf_sym
;
29736 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29737 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29739 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29740 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29742 /* If it's a .thumb_func, declare it as so,
29743 otherwise tag label as .code 16. */
29744 if (THUMB_IS_FUNC (sym
))
29745 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29746 ST_BRANCH_TO_THUMB
);
29747 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29748 elf_sym
->internal_elf_sym
.st_info
=
29749 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29754 /* Remove any overlapping mapping symbols generated by alignment frags. */
29755 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29756 /* Now do generic ELF adjustments. */
29757 elf_adjust_symtab ();
29761 /* MD interface: Initialization. */
29764 set_constant_flonums (void)
29768 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29769 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29773 /* Auto-select Thumb mode if it's the only available instruction set for the
29774 given architecture. */
29777 autoselect_thumb_from_cpu_variant (void)
29779 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29780 opcode_select (16);
29789 if ( (arm_ops_hsh
= hash_new ()) == NULL
29790 || (arm_cond_hsh
= hash_new ()) == NULL
29791 || (arm_vcond_hsh
= hash_new ()) == NULL
29792 || (arm_shift_hsh
= hash_new ()) == NULL
29793 || (arm_psr_hsh
= hash_new ()) == NULL
29794 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29795 || (arm_reg_hsh
= hash_new ()) == NULL
29796 || (arm_reloc_hsh
= hash_new ()) == NULL
29797 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29798 as_fatal (_("virtual memory exhausted"));
29800 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29801 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29802 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29803 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29804 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29805 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29806 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29807 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29808 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29809 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29810 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29811 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29812 (void *) (v7m_psrs
+ i
));
29813 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29814 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29816 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29818 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29819 (void *) (barrier_opt_names
+ i
));
29821 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29823 struct reloc_entry
* entry
= reloc_names
+ i
;
29825 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29826 /* This makes encode_branch() use the EABI versions of this relocation. */
29827 entry
->reloc
= BFD_RELOC_UNUSED
;
29829 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29833 set_constant_flonums ();
29835 /* Set the cpu variant based on the command-line options. We prefer
29836 -mcpu= over -march= if both are set (as for GCC); and we prefer
29837 -mfpu= over any other way of setting the floating point unit.
29838 Use of legacy options with new options are faulted. */
29841 if (mcpu_cpu_opt
|| march_cpu_opt
)
29842 as_bad (_("use of old and new-style options to set CPU type"));
29844 selected_arch
= *legacy_cpu
;
29846 else if (mcpu_cpu_opt
)
29848 selected_arch
= *mcpu_cpu_opt
;
29849 selected_ext
= *mcpu_ext_opt
;
29851 else if (march_cpu_opt
)
29853 selected_arch
= *march_cpu_opt
;
29854 selected_ext
= *march_ext_opt
;
29856 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29861 as_bad (_("use of old and new-style options to set FPU type"));
29863 selected_fpu
= *legacy_fpu
;
29866 selected_fpu
= *mfpu_opt
;
29869 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29870 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29871 /* Some environments specify a default FPU. If they don't, infer it
29872 from the processor. */
29874 selected_fpu
= *mcpu_fpu_opt
;
29875 else if (march_fpu_opt
)
29876 selected_fpu
= *march_fpu_opt
;
29878 selected_fpu
= fpu_default
;
29882 if (ARM_FEATURE_ZERO (selected_fpu
))
29884 if (!no_cpu_selected ())
29885 selected_fpu
= fpu_default
;
29887 selected_fpu
= fpu_arch_fpa
;
29891 if (ARM_FEATURE_ZERO (selected_arch
))
29893 selected_arch
= cpu_default
;
29894 selected_cpu
= selected_arch
;
29896 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29898 /* Autodection of feature mode: allow all features in cpu_variant but leave
29899 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29900 after all instruction have been processed and we can decide what CPU
29901 should be selected. */
29902 if (ARM_FEATURE_ZERO (selected_arch
))
29903 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29905 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29908 autoselect_thumb_from_cpu_variant ();
29910 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29912 #if defined OBJ_COFF || defined OBJ_ELF
29914 unsigned int flags
= 0;
29916 #if defined OBJ_ELF
29917 flags
= meabi_flags
;
29919 switch (meabi_flags
)
29921 case EF_ARM_EABI_UNKNOWN
:
29923 /* Set the flags in the private structure. */
29924 if (uses_apcs_26
) flags
|= F_APCS26
;
29925 if (support_interwork
) flags
|= F_INTERWORK
;
29926 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29927 if (pic_code
) flags
|= F_PIC
;
29928 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29929 flags
|= F_SOFT_FLOAT
;
29931 switch (mfloat_abi_opt
)
29933 case ARM_FLOAT_ABI_SOFT
:
29934 case ARM_FLOAT_ABI_SOFTFP
:
29935 flags
|= F_SOFT_FLOAT
;
29938 case ARM_FLOAT_ABI_HARD
:
29939 if (flags
& F_SOFT_FLOAT
)
29940 as_bad (_("hard-float conflicts with specified fpu"));
29944 /* Using pure-endian doubles (even if soft-float). */
29945 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29946 flags
|= F_VFP_FLOAT
;
29948 #if defined OBJ_ELF
29949 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29950 flags
|= EF_ARM_MAVERICK_FLOAT
;
29953 case EF_ARM_EABI_VER4
:
29954 case EF_ARM_EABI_VER5
:
29955 /* No additional flags to set. */
29962 bfd_set_private_flags (stdoutput
, flags
);
29964 /* We have run out flags in the COFF header to encode the
29965 status of ATPCS support, so instead we create a dummy,
29966 empty, debug section called .arm.atpcs. */
29971 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29975 bfd_set_section_flags
29976 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29977 bfd_set_section_size (stdoutput
, sec
, 0);
29978 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29984 /* Record the CPU type as well. */
29985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29986 mach
= bfd_mach_arm_iWMMXt2
;
29987 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29988 mach
= bfd_mach_arm_iWMMXt
;
29989 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29990 mach
= bfd_mach_arm_XScale
;
29991 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29992 mach
= bfd_mach_arm_ep9312
;
29993 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29994 mach
= bfd_mach_arm_5TE
;
29995 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29997 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29998 mach
= bfd_mach_arm_5T
;
30000 mach
= bfd_mach_arm_5
;
30002 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30004 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30005 mach
= bfd_mach_arm_4T
;
30007 mach
= bfd_mach_arm_4
;
30009 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30010 mach
= bfd_mach_arm_3M
;
30011 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30012 mach
= bfd_mach_arm_3
;
30013 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30014 mach
= bfd_mach_arm_2a
;
30015 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30016 mach
= bfd_mach_arm_2
;
30018 mach
= bfd_mach_arm_unknown
;
30020 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30023 /* Command line processing. */
30026 Invocation line includes a switch not recognized by the base assembler.
30027 See if it's a processor-specific option.
30029 This routine is somewhat complicated by the need for backwards
30030 compatibility (since older releases of gcc can't be changed).
30031 The new options try to make the interface as compatible as
30034 New options (supported) are:
30036 -mcpu=<cpu name> Assemble for selected processor
30037 -march=<architecture name> Assemble for selected architecture
30038 -mfpu=<fpu architecture> Assemble for selected FPU.
30039 -EB/-mbig-endian Big-endian
30040 -EL/-mlittle-endian Little-endian
30041 -k Generate PIC code
30042 -mthumb Start in Thumb mode
30043 -mthumb-interwork Code supports ARM/Thumb interworking
30045 -m[no-]warn-deprecated Warn about deprecated features
30046 -m[no-]warn-syms Warn when symbols match instructions
30048 For now we will also provide support for:
30050 -mapcs-32 32-bit Program counter
30051 -mapcs-26 26-bit Program counter
30052 -macps-float Floats passed in FP registers
30053 -mapcs-reentrant Reentrant code
30055 (sometime these will probably be replaced with -mapcs=<list of options>
30056 and -matpcs=<list of options>)
30058 The remaining options are only supported for back-wards compatibility.
30059 Cpu variants, the arm part is optional:
30060 -m[arm]1 Currently not supported.
30061 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30062 -m[arm]3 Arm 3 processor
30063 -m[arm]6[xx], Arm 6 processors
30064 -m[arm]7[xx][t][[d]m] Arm 7 processors
30065 -m[arm]8[10] Arm 8 processors
30066 -m[arm]9[20][tdmi] Arm 9 processors
30067 -mstrongarm[110[0]] StrongARM processors
30068 -mxscale XScale processors
30069 -m[arm]v[2345[t[e]]] Arm architectures
30070 -mall All (except the ARM1)
30072 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30073 -mfpe-old (No float load/store multiples)
30074 -mvfpxd VFP Single precision
30076 -mno-fpu Disable all floating point instructions
30078 The following CPU names are recognized:
30079 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30080 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30081 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30082 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30083 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30084 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30085 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30089 const char * md_shortopts
= "m:k";
30091 #ifdef ARM_BI_ENDIAN
30092 #define OPTION_EB (OPTION_MD_BASE + 0)
30093 #define OPTION_EL (OPTION_MD_BASE + 1)
30095 #if TARGET_BYTES_BIG_ENDIAN
30096 #define OPTION_EB (OPTION_MD_BASE + 0)
30098 #define OPTION_EL (OPTION_MD_BASE + 1)
30101 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30102 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30104 struct option md_longopts
[] =
30107 {"EB", no_argument
, NULL
, OPTION_EB
},
30110 {"EL", no_argument
, NULL
, OPTION_EL
},
30112 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30114 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30116 {NULL
, no_argument
, NULL
, 0}
30119 size_t md_longopts_size
= sizeof (md_longopts
);
30121 struct arm_option_table
30123 const char * option
; /* Option name to match. */
30124 const char * help
; /* Help information. */
30125 int * var
; /* Variable to change. */
30126 int value
; /* What to change it to. */
30127 const char * deprecated
; /* If non-null, print this message. */
30130 struct arm_option_table arm_opts
[] =
30132 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30133 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30134 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30135 &support_interwork
, 1, NULL
},
30136 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30137 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30138 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30140 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30141 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30142 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30143 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30146 /* These are recognized by the assembler, but have no affect on code. */
30147 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30148 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30150 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30151 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30152 &warn_on_deprecated
, 0, NULL
},
30153 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30154 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30155 {NULL
, NULL
, NULL
, 0, NULL
}
30158 struct arm_legacy_option_table
30160 const char * option
; /* Option name to match. */
30161 const arm_feature_set
** var
; /* Variable to change. */
30162 const arm_feature_set value
; /* What to change it to. */
30163 const char * deprecated
; /* If non-null, print this message. */
30166 const struct arm_legacy_option_table arm_legacy_opts
[] =
30168 /* DON'T add any new processors to this list -- we want the whole list
30169 to go away... Add them to the processors table instead. */
30170 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30171 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30172 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30173 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30174 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30175 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30176 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30177 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30178 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30179 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30180 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30181 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30182 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30183 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30184 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30185 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30186 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30187 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30188 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30189 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30190 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30191 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30192 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30193 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30194 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30195 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30196 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30197 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30198 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30199 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30200 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30201 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30202 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30203 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30204 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30205 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30206 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30207 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30208 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30209 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30210 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30211 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30212 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30213 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30214 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30215 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30216 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30217 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30218 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30219 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30220 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30221 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30222 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30223 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30224 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30225 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30226 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30227 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30228 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30229 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30230 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30231 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30232 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30233 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30234 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30235 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30236 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30237 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30238 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30239 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30240 N_("use -mcpu=strongarm110")},
30241 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30242 N_("use -mcpu=strongarm1100")},
30243 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30244 N_("use -mcpu=strongarm1110")},
30245 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30246 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30247 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30249 /* Architecture variants -- don't add any more to this list either. */
30250 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30251 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30252 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30253 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30254 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30255 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30256 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30257 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30258 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30259 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30260 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30261 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30262 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30263 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30264 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30265 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30266 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30267 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30269 /* Floating point variants -- don't add any more to this list either. */
30270 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30271 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30272 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30273 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30274 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30276 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30279 struct arm_cpu_option_table
30283 const arm_feature_set value
;
30284 const arm_feature_set ext
;
30285 /* For some CPUs we assume an FPU unless the user explicitly sets
30287 const arm_feature_set default_fpu
;
30288 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30290 const char * canonical_name
;
30293 /* This list should, at a minimum, contain all the cpu names
30294 recognized by GCC. */
30295 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30297 static const struct arm_cpu_option_table arm_cpus
[] =
30299 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30302 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30305 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30308 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30311 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30314 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30317 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30320 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30323 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30326 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30329 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30332 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30335 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30338 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30341 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30344 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30347 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30350 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30353 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30356 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30359 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30362 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30365 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30368 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30371 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30374 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30377 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30380 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30383 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30386 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30389 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30392 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30395 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30398 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30401 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30404 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30407 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30410 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30413 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30416 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30419 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30422 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30425 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30428 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30431 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30434 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30438 /* For V5 or later processors we default to using VFP; but the user
30439 should really set the FPU type explicitly. */
30440 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30443 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30446 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30449 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30452 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30455 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30458 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30461 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30464 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30467 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30470 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30473 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30476 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30479 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30482 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30485 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30488 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30491 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30494 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30497 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30500 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30503 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30506 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30509 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30512 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30515 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30518 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30521 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30524 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30527 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30530 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30533 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30536 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30539 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30542 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30545 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30548 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30549 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30551 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30553 FPU_ARCH_NEON_VFP_V4
),
30554 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30555 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30556 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30557 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30558 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30559 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30560 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30562 FPU_ARCH_NEON_VFP_V4
),
30563 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30565 FPU_ARCH_NEON_VFP_V4
),
30566 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30568 FPU_ARCH_NEON_VFP_V4
),
30569 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30570 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30571 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30572 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30573 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30574 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30575 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30576 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30577 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30578 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30579 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30580 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30581 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30582 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30583 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30584 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30585 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30586 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30587 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30588 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30590 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30591 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30593 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30594 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30596 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30597 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30598 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30599 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30600 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30601 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30602 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30603 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30604 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30605 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30608 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30610 FPU_ARCH_VFP_V3D16
),
30611 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30612 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30614 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30615 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30616 FPU_ARCH_VFP_V3D16
),
30617 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30618 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30619 FPU_ARCH_VFP_V3D16
),
30620 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30621 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30622 FPU_ARCH_NEON_VFP_ARMV8
),
30623 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30624 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30626 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30627 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30629 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30632 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30635 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30638 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30641 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30644 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30647 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30650 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30651 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30652 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30653 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30654 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30655 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30656 /* ??? XSCALE is really an architecture. */
30657 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30661 /* ??? iwmmxt is not a processor. */
30662 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30665 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30668 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30673 ARM_CPU_OPT ("ep9312", "ARM920T",
30674 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30675 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30677 /* Marvell processors. */
30678 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30679 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30680 FPU_ARCH_VFP_V3D16
),
30681 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30682 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30683 FPU_ARCH_NEON_VFP_V4
),
30685 /* APM X-Gene family. */
30686 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30688 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30689 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30690 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30691 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30693 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30697 struct arm_ext_table
30701 const arm_feature_set merge
;
30702 const arm_feature_set clear
;
30705 struct arm_arch_option_table
30709 const arm_feature_set value
;
30710 const arm_feature_set default_fpu
;
30711 const struct arm_ext_table
* ext_table
;
30714 /* Used to add support for +E and +noE extension. */
30715 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30716 /* Used to add support for a +E extension. */
30717 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30718 /* Used to add support for a +noE extension. */
30719 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30721 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30722 ~0 & ~FPU_ENDIAN_PURE)
30724 static const struct arm_ext_table armv5te_ext_table
[] =
30726 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30727 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30730 static const struct arm_ext_table armv7_ext_table
[] =
30732 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30733 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30736 static const struct arm_ext_table armv7ve_ext_table
[] =
30738 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30739 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30740 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30741 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30742 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30743 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30744 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30746 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30747 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30749 /* Aliases for +simd. */
30750 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30752 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30753 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30754 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30756 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30759 static const struct arm_ext_table armv7a_ext_table
[] =
30761 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30762 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30763 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30764 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30765 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30766 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30767 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30769 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30770 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30772 /* Aliases for +simd. */
30773 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30774 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30776 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30777 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30779 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30780 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30781 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30784 static const struct arm_ext_table armv7r_ext_table
[] =
30786 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30787 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30788 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30789 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30790 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30791 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30792 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30793 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30794 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30797 static const struct arm_ext_table armv7em_ext_table
[] =
30799 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30800 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30801 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30802 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30803 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30804 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30805 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30808 static const struct arm_ext_table armv8a_ext_table
[] =
30810 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30811 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30812 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30813 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30815 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30816 should use the +simd option to turn on FP. */
30817 ARM_REMOVE ("fp", ALL_FP
),
30818 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30819 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30820 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30824 static const struct arm_ext_table armv81a_ext_table
[] =
30826 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30827 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30828 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30830 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30831 should use the +simd option to turn on FP. */
30832 ARM_REMOVE ("fp", ALL_FP
),
30833 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30834 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30835 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30838 static const struct arm_ext_table armv82a_ext_table
[] =
30840 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30841 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30842 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30843 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30844 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30845 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30847 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30848 should use the +simd option to turn on FP. */
30849 ARM_REMOVE ("fp", ALL_FP
),
30850 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30851 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30852 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30855 static const struct arm_ext_table armv84a_ext_table
[] =
30857 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30858 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30859 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30860 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30862 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30863 should use the +simd option to turn on FP. */
30864 ARM_REMOVE ("fp", ALL_FP
),
30865 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30866 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30867 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30870 static const struct arm_ext_table armv85a_ext_table
[] =
30872 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30873 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30874 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30875 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30877 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30878 should use the +simd option to turn on FP. */
30879 ARM_REMOVE ("fp", ALL_FP
),
30880 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30883 static const struct arm_ext_table armv8m_main_ext_table
[] =
30885 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30886 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30887 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30888 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30889 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30892 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30894 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30895 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30897 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30898 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30901 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30902 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30903 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30904 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30906 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30907 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30908 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30909 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30912 static const struct arm_ext_table armv8r_ext_table
[] =
30914 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30915 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30916 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30917 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30918 ARM_REMOVE ("fp", ALL_FP
),
30919 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30920 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30923 /* This list should, at a minimum, contain all the architecture names
30924 recognized by GCC. */
30925 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30926 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30927 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30929 static const struct arm_arch_option_table arm_archs
[] =
30931 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30932 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30933 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30934 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30935 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30936 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30937 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30938 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30939 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30940 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30941 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30942 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30943 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30944 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30945 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30946 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30947 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30948 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30949 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30950 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30951 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30952 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30953 kept to preserve existing behaviour. */
30954 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30955 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30956 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30957 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30958 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30959 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30960 kept to preserve existing behaviour. */
30961 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30962 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30963 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30964 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30965 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30966 /* The official spelling of the ARMv7 profile variants is the dashed form.
30967 Accept the non-dashed form for compatibility with old toolchains. */
30968 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30969 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30970 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30971 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30972 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30973 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30974 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30975 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30976 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30977 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30979 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30981 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30982 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30983 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30984 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30985 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30986 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30987 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30988 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30989 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30990 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30991 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30993 #undef ARM_ARCH_OPT
30995 /* ISA extensions in the co-processor and main instruction set space. */
30997 struct arm_option_extension_value_table
31001 const arm_feature_set merge_value
;
31002 const arm_feature_set clear_value
;
31003 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31004 indicates that an extension is available for all architectures while
31005 ARM_ANY marks an empty entry. */
31006 const arm_feature_set allowed_archs
[2];
31009 /* The following table must be in alphabetical order with a NULL last entry. */
31011 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31012 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31014 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31015 use the context sensitive approach using arm_ext_table's. */
31016 static const struct arm_option_extension_value_table arm_extensions
[] =
31018 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31019 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31020 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31021 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31022 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31023 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31024 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31026 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31027 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31028 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31029 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31030 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31031 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31032 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31034 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31035 | ARM_EXT2_FP16_FML
),
31036 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31037 | ARM_EXT2_FP16_FML
),
31039 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31040 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31041 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31042 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31043 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31044 Thumb divide instruction. Due to this having the same name as the
31045 previous entry, this will be ignored when doing command-line parsing and
31046 only considered by build attribute selection code. */
31047 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31048 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31049 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31050 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31051 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31052 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31053 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31054 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31055 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31056 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31057 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31058 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31059 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31060 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31061 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31062 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31063 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31064 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31065 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31066 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31067 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31069 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31070 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31071 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31072 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31073 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31074 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31075 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31076 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31078 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31079 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31080 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31081 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31082 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31083 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31084 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31085 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31087 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31088 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31089 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31090 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31091 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31095 /* ISA floating-point and Advanced SIMD extensions. */
31096 struct arm_option_fpu_value_table
31099 const arm_feature_set value
;
31102 /* This list should, at a minimum, contain all the fpu names
31103 recognized by GCC. */
31104 static const struct arm_option_fpu_value_table arm_fpus
[] =
31106 {"softfpa", FPU_NONE
},
31107 {"fpe", FPU_ARCH_FPE
},
31108 {"fpe2", FPU_ARCH_FPE
},
31109 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31110 {"fpa", FPU_ARCH_FPA
},
31111 {"fpa10", FPU_ARCH_FPA
},
31112 {"fpa11", FPU_ARCH_FPA
},
31113 {"arm7500fe", FPU_ARCH_FPA
},
31114 {"softvfp", FPU_ARCH_VFP
},
31115 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31116 {"vfp", FPU_ARCH_VFP_V2
},
31117 {"vfp9", FPU_ARCH_VFP_V2
},
31118 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31119 {"vfp10", FPU_ARCH_VFP_V2
},
31120 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31121 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31122 {"vfpv2", FPU_ARCH_VFP_V2
},
31123 {"vfpv3", FPU_ARCH_VFP_V3
},
31124 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31125 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31126 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31127 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31128 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31129 {"arm1020t", FPU_ARCH_VFP_V1
},
31130 {"arm1020e", FPU_ARCH_VFP_V2
},
31131 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31132 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31133 {"maverick", FPU_ARCH_MAVERICK
},
31134 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31135 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31136 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31137 {"vfpv4", FPU_ARCH_VFP_V4
},
31138 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31139 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31140 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31141 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31142 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31143 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31144 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31145 {"crypto-neon-fp-armv8",
31146 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31147 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31148 {"crypto-neon-fp-armv8.1",
31149 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31150 {NULL
, ARM_ARCH_NONE
}
31153 struct arm_option_value_table
31159 static const struct arm_option_value_table arm_float_abis
[] =
31161 {"hard", ARM_FLOAT_ABI_HARD
},
31162 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31163 {"soft", ARM_FLOAT_ABI_SOFT
},
31168 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31169 static const struct arm_option_value_table arm_eabis
[] =
31171 {"gnu", EF_ARM_EABI_UNKNOWN
},
31172 {"4", EF_ARM_EABI_VER4
},
31173 {"5", EF_ARM_EABI_VER5
},
31178 struct arm_long_option_table
31180 const char * option
; /* Substring to match. */
31181 const char * help
; /* Help information. */
31182 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31183 const char * deprecated
; /* If non-null, print this message. */
31187 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31188 arm_feature_set
*ext_set
,
31189 const struct arm_ext_table
*ext_table
)
31191 /* We insist on extensions being specified in alphabetical order, and with
31192 extensions being added before being removed. We achieve this by having
31193 the global ARM_EXTENSIONS table in alphabetical order, and using the
31194 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31195 or removing it (0) and only allowing it to change in the order
31197 const struct arm_option_extension_value_table
* opt
= NULL
;
31198 const arm_feature_set arm_any
= ARM_ANY
;
31199 int adding_value
= -1;
31201 while (str
!= NULL
&& *str
!= 0)
31208 as_bad (_("invalid architectural extension"));
31213 ext
= strchr (str
, '+');
31218 len
= strlen (str
);
31220 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31222 if (adding_value
!= 0)
31225 opt
= arm_extensions
;
31233 if (adding_value
== -1)
31236 opt
= arm_extensions
;
31238 else if (adding_value
!= 1)
31240 as_bad (_("must specify extensions to add before specifying "
31241 "those to remove"));
31248 as_bad (_("missing architectural extension"));
31252 gas_assert (adding_value
!= -1);
31253 gas_assert (opt
!= NULL
);
31255 if (ext_table
!= NULL
)
31257 const struct arm_ext_table
* ext_opt
= ext_table
;
31258 bfd_boolean found
= FALSE
;
31259 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31260 if (ext_opt
->name_len
== len
31261 && strncmp (ext_opt
->name
, str
, len
) == 0)
31265 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31266 /* TODO: Option not supported. When we remove the
31267 legacy table this case should error out. */
31270 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31274 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31275 /* TODO: Option not supported. When we remove the
31276 legacy table this case should error out. */
31278 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31290 /* Scan over the options table trying to find an exact match. */
31291 for (; opt
->name
!= NULL
; opt
++)
31292 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31294 int i
, nb_allowed_archs
=
31295 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31296 /* Check we can apply the extension to this architecture. */
31297 for (i
= 0; i
< nb_allowed_archs
; i
++)
31300 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31302 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31305 if (i
== nb_allowed_archs
)
31307 as_bad (_("extension does not apply to the base architecture"));
31311 /* Add or remove the extension. */
31313 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31315 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31317 /* Allowing Thumb division instructions for ARMv7 in autodetection
31318 rely on this break so that duplicate extensions (extensions
31319 with the same name as a previous extension in the list) are not
31320 considered for command-line parsing. */
31324 if (opt
->name
== NULL
)
31326 /* Did we fail to find an extension because it wasn't specified in
31327 alphabetical order, or because it does not exist? */
31329 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31330 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31333 if (opt
->name
== NULL
)
31334 as_bad (_("unknown architectural extension `%s'"), str
);
31336 as_bad (_("architectural extensions must be specified in "
31337 "alphabetical order"));
31343 /* We should skip the extension we've just matched the next time
31355 arm_parse_fp16_opt (const char *str
)
31357 if (strcasecmp (str
, "ieee") == 0)
31358 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31359 else if (strcasecmp (str
, "alternative") == 0)
31360 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31363 as_bad (_("unrecognised float16 format \"%s\""), str
);
31371 arm_parse_cpu (const char *str
)
31373 const struct arm_cpu_option_table
*opt
;
31374 const char *ext
= strchr (str
, '+');
31380 len
= strlen (str
);
31384 as_bad (_("missing cpu name `%s'"), str
);
31388 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31389 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31391 mcpu_cpu_opt
= &opt
->value
;
31392 if (mcpu_ext_opt
== NULL
)
31393 mcpu_ext_opt
= XNEW (arm_feature_set
);
31394 *mcpu_ext_opt
= opt
->ext
;
31395 mcpu_fpu_opt
= &opt
->default_fpu
;
31396 if (opt
->canonical_name
)
31398 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31399 strcpy (selected_cpu_name
, opt
->canonical_name
);
31405 if (len
>= sizeof selected_cpu_name
)
31406 len
= (sizeof selected_cpu_name
) - 1;
31408 for (i
= 0; i
< len
; i
++)
31409 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31410 selected_cpu_name
[i
] = 0;
31414 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31419 as_bad (_("unknown cpu `%s'"), str
);
31424 arm_parse_arch (const char *str
)
31426 const struct arm_arch_option_table
*opt
;
31427 const char *ext
= strchr (str
, '+');
31433 len
= strlen (str
);
31437 as_bad (_("missing architecture name `%s'"), str
);
31441 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31442 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31444 march_cpu_opt
= &opt
->value
;
31445 if (march_ext_opt
== NULL
)
31446 march_ext_opt
= XNEW (arm_feature_set
);
31447 *march_ext_opt
= arm_arch_none
;
31448 march_fpu_opt
= &opt
->default_fpu
;
31449 strcpy (selected_cpu_name
, opt
->name
);
31452 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31458 as_bad (_("unknown architecture `%s'\n"), str
);
31463 arm_parse_fpu (const char * str
)
31465 const struct arm_option_fpu_value_table
* opt
;
31467 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31468 if (streq (opt
->name
, str
))
31470 mfpu_opt
= &opt
->value
;
31474 as_bad (_("unknown floating point format `%s'\n"), str
);
31479 arm_parse_float_abi (const char * str
)
31481 const struct arm_option_value_table
* opt
;
31483 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31484 if (streq (opt
->name
, str
))
31486 mfloat_abi_opt
= opt
->value
;
31490 as_bad (_("unknown floating point abi `%s'\n"), str
);
31496 arm_parse_eabi (const char * str
)
31498 const struct arm_option_value_table
*opt
;
31500 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31501 if (streq (opt
->name
, str
))
31503 meabi_flags
= opt
->value
;
31506 as_bad (_("unknown EABI `%s'\n"), str
);
31512 arm_parse_it_mode (const char * str
)
31514 bfd_boolean ret
= TRUE
;
31516 if (streq ("arm", str
))
31517 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31518 else if (streq ("thumb", str
))
31519 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31520 else if (streq ("always", str
))
31521 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31522 else if (streq ("never", str
))
31523 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31526 as_bad (_("unknown implicit IT mode `%s', should be "\
31527 "arm, thumb, always, or never."), str
);
31535 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31537 codecomposer_syntax
= TRUE
;
31538 arm_comment_chars
[0] = ';';
31539 arm_line_separator_chars
[0] = 0;
31543 struct arm_long_option_table arm_long_opts
[] =
31545 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31546 arm_parse_cpu
, NULL
},
31547 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31548 arm_parse_arch
, NULL
},
31549 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31550 arm_parse_fpu
, NULL
},
31551 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31552 arm_parse_float_abi
, NULL
},
31554 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31555 arm_parse_eabi
, NULL
},
31557 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31558 arm_parse_it_mode
, NULL
},
31559 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31560 arm_ccs_mode
, NULL
},
31562 N_("[ieee|alternative]\n\
31563 set the encoding for half precision floating point "
31564 "numbers to IEEE\n\
31565 or Arm alternative format."),
31566 arm_parse_fp16_opt
, NULL
},
31567 {NULL
, NULL
, 0, NULL
}
31571 md_parse_option (int c
, const char * arg
)
31573 struct arm_option_table
*opt
;
31574 const struct arm_legacy_option_table
*fopt
;
31575 struct arm_long_option_table
*lopt
;
31581 target_big_endian
= 1;
31587 target_big_endian
= 0;
31591 case OPTION_FIX_V4BX
:
31599 #endif /* OBJ_ELF */
31602 /* Listing option. Just ignore these, we don't support additional
31607 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31609 if (c
== opt
->option
[0]
31610 && ((arg
== NULL
&& opt
->option
[1] == 0)
31611 || streq (arg
, opt
->option
+ 1)))
31613 /* If the option is deprecated, tell the user. */
31614 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31615 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31616 arg
? arg
: "", _(opt
->deprecated
));
31618 if (opt
->var
!= NULL
)
31619 *opt
->var
= opt
->value
;
31625 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31627 if (c
== fopt
->option
[0]
31628 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31629 || streq (arg
, fopt
->option
+ 1)))
31631 /* If the option is deprecated, tell the user. */
31632 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31633 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31634 arg
? arg
: "", _(fopt
->deprecated
));
31636 if (fopt
->var
!= NULL
)
31637 *fopt
->var
= &fopt
->value
;
31643 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31645 /* These options are expected to have an argument. */
31646 if (c
== lopt
->option
[0]
31648 && strncmp (arg
, lopt
->option
+ 1,
31649 strlen (lopt
->option
+ 1)) == 0)
31651 /* If the option is deprecated, tell the user. */
31652 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31653 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31654 _(lopt
->deprecated
));
31656 /* Call the sup-option parser. */
31657 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31668 md_show_usage (FILE * fp
)
31670 struct arm_option_table
*opt
;
31671 struct arm_long_option_table
*lopt
;
31673 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31675 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31676 if (opt
->help
!= NULL
)
31677 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31679 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31680 if (lopt
->help
!= NULL
)
31681 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31685 -EB assemble code for a big-endian cpu\n"));
31690 -EL assemble code for a little-endian cpu\n"));
31694 --fix-v4bx Allow BX in ARMv4 code\n"));
31698 --fdpic generate an FDPIC object file\n"));
31699 #endif /* OBJ_ELF */
31707 arm_feature_set flags
;
31708 } cpu_arch_ver_table
;
31710 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31711 chronologically for architectures, with an exception for ARMv6-M and
31712 ARMv6S-M due to legacy reasons. No new architecture should have a
31713 special case. This allows for build attribute selection results to be
31714 stable when new architectures are added. */
31715 static const cpu_arch_ver_table cpu_arch_ver
[] =
31717 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31718 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31719 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31720 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31721 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31722 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31723 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31724 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31725 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31726 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31727 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31728 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31729 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31730 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31731 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31732 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31733 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31734 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31735 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31736 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31737 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31738 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31739 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31740 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31742 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31743 always selected build attributes to match those of ARMv6-M
31744 (resp. ARMv6S-M). However, due to these architectures being a strict
31745 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31746 would be selected when fully respecting chronology of architectures.
31747 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31748 move them before ARMv7 architectures. */
31749 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31750 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31752 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31753 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31754 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31755 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31756 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31757 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31758 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31759 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31760 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31761 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31762 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31763 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31764 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31765 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31766 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31767 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31768 {-1, ARM_ARCH_NONE
}
31771 /* Set an attribute if it has not already been set by the user. */
31774 aeabi_set_attribute_int (int tag
, int value
)
31777 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31778 || !attributes_set_explicitly
[tag
])
31779 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31783 aeabi_set_attribute_string (int tag
, const char *value
)
31786 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31787 || !attributes_set_explicitly
[tag
])
31788 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31791 /* Return whether features in the *NEEDED feature set are available via
31792 extensions for the architecture whose feature set is *ARCH_FSET. */
31795 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31796 const arm_feature_set
*needed
)
31798 int i
, nb_allowed_archs
;
31799 arm_feature_set ext_fset
;
31800 const struct arm_option_extension_value_table
*opt
;
31802 ext_fset
= arm_arch_none
;
31803 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31805 /* Extension does not provide any feature we need. */
31806 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31810 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31811 for (i
= 0; i
< nb_allowed_archs
; i
++)
31814 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31817 /* Extension is available, add it. */
31818 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31819 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31823 /* Can we enable all features in *needed? */
31824 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31827 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31828 a given architecture feature set *ARCH_EXT_FSET including extension feature
31829 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31830 - if true, check for an exact match of the architecture modulo extensions;
31831 - otherwise, select build attribute value of the first superset
31832 architecture released so that results remains stable when new architectures
31834 For -march/-mcpu=all the build attribute value of the most featureful
31835 architecture is returned. Tag_CPU_arch_profile result is returned in
31839 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31840 const arm_feature_set
*ext_fset
,
31841 char *profile
, int exact_match
)
31843 arm_feature_set arch_fset
;
31844 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31846 /* Select most featureful architecture with all its extensions if building
31847 for -march=all as the feature sets used to set build attributes. */
31848 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31850 /* Force revisiting of decision for each new architecture. */
31851 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31853 return TAG_CPU_ARCH_V8
;
31856 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31858 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31860 arm_feature_set known_arch_fset
;
31862 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31865 /* Base architecture match user-specified architecture and
31866 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31867 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31872 /* Base architecture match user-specified architecture only
31873 (eg. ARMv6-M in the same case as above). Record it in case we
31874 find a match with above condition. */
31875 else if (p_ver_ret
== NULL
31876 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31882 /* Architecture has all features wanted. */
31883 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31885 arm_feature_set added_fset
;
31887 /* Compute features added by this architecture over the one
31888 recorded in p_ver_ret. */
31889 if (p_ver_ret
!= NULL
)
31890 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31892 /* First architecture that match incl. with extensions, or the
31893 only difference in features over the recorded match is
31894 features that were optional and are now mandatory. */
31895 if (p_ver_ret
== NULL
31896 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31902 else if (p_ver_ret
== NULL
)
31904 arm_feature_set needed_ext_fset
;
31906 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31908 /* Architecture has all features needed when using some
31909 extensions. Record it and continue searching in case there
31910 exist an architecture providing all needed features without
31911 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31913 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31920 if (p_ver_ret
== NULL
)
31924 /* Tag_CPU_arch_profile. */
31925 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31926 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31927 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31928 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31930 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31932 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31936 return p_ver_ret
->val
;
31939 /* Set the public EABI object attributes. */
31942 aeabi_set_public_attributes (void)
31944 char profile
= '\0';
31947 int fp16_optional
= 0;
31948 int skip_exact_match
= 0;
31949 arm_feature_set flags
, flags_arch
, flags_ext
;
31951 /* Autodetection mode, choose the architecture based the instructions
31953 if (no_cpu_selected ())
31955 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31957 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31958 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31960 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31961 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31963 /* Code run during relaxation relies on selected_cpu being set. */
31964 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31965 flags_ext
= arm_arch_none
;
31966 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31967 selected_ext
= flags_ext
;
31968 selected_cpu
= flags
;
31970 /* Otherwise, choose the architecture based on the capabilities of the
31974 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31975 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31976 flags_ext
= selected_ext
;
31977 flags
= selected_cpu
;
31979 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31981 /* Allow the user to override the reported architecture. */
31982 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31984 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31985 flags_ext
= arm_arch_none
;
31988 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31990 /* When this function is run again after relaxation has happened there is no
31991 way to determine whether an architecture or CPU was specified by the user:
31992 - selected_cpu is set above for relaxation to work;
31993 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31994 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31995 Therefore, if not in -march=all case we first try an exact match and fall
31996 back to autodetection. */
31997 if (!skip_exact_match
)
31998 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32000 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32002 as_bad (_("no architecture contains all the instructions used\n"));
32004 /* Tag_CPU_name. */
32005 if (selected_cpu_name
[0])
32009 q
= selected_cpu_name
;
32010 if (strncmp (q
, "armv", 4) == 0)
32015 for (i
= 0; q
[i
]; i
++)
32016 q
[i
] = TOUPPER (q
[i
]);
32018 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32021 /* Tag_CPU_arch. */
32022 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32024 /* Tag_CPU_arch_profile. */
32025 if (profile
!= '\0')
32026 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32028 /* Tag_DSP_extension. */
32029 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32030 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32032 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32033 /* Tag_ARM_ISA_use. */
32034 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32035 || ARM_FEATURE_ZERO (flags_arch
))
32036 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32038 /* Tag_THUMB_ISA_use. */
32039 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32040 || ARM_FEATURE_ZERO (flags_arch
))
32044 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32045 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32047 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32051 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32054 /* Tag_VFP_arch. */
32055 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32056 aeabi_set_attribute_int (Tag_VFP_arch
,
32057 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32059 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32060 aeabi_set_attribute_int (Tag_VFP_arch
,
32061 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32063 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32066 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32068 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32070 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32073 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32074 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32075 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32076 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32077 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32079 /* Tag_ABI_HardFP_use. */
32080 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32081 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32082 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32084 /* Tag_WMMX_arch. */
32085 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32086 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32087 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32088 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32090 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32091 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32092 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32093 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32094 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32095 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32097 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32099 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32103 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32108 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32109 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32110 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32111 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32113 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32114 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32115 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32119 We set Tag_DIV_use to two when integer divide instructions have been used
32120 in ARM state, or when Thumb integer divide instructions have been used,
32121 but we have no architecture profile set, nor have we any ARM instructions.
32123 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32124 by the base architecture.
32126 For new architectures we will have to check these tests. */
32127 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32128 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32129 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32130 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32131 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32132 || (profile
== '\0'
32133 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32134 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32135 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32137 /* Tag_MP_extension_use. */
32138 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32139 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32141 /* Tag Virtualization_use. */
32142 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32144 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32147 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32149 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32150 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32153 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32154 finished and free extension feature bits which will not be used anymore. */
32157 arm_md_post_relax (void)
32159 aeabi_set_public_attributes ();
32160 XDELETE (mcpu_ext_opt
);
32161 mcpu_ext_opt
= NULL
;
32162 XDELETE (march_ext_opt
);
32163 march_ext_opt
= NULL
;
32166 /* Add the default contents for the .ARM.attributes section. */
32171 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32174 aeabi_set_public_attributes ();
32176 #endif /* OBJ_ELF */
32178 /* Parse a .cpu directive. */
32181 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32183 const struct arm_cpu_option_table
*opt
;
32187 name
= input_line_pointer
;
32188 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32189 input_line_pointer
++;
32190 saved_char
= *input_line_pointer
;
32191 *input_line_pointer
= 0;
32193 /* Skip the first "all" entry. */
32194 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32195 if (streq (opt
->name
, name
))
32197 selected_arch
= opt
->value
;
32198 selected_ext
= opt
->ext
;
32199 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32200 if (opt
->canonical_name
)
32201 strcpy (selected_cpu_name
, opt
->canonical_name
);
32205 for (i
= 0; opt
->name
[i
]; i
++)
32206 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32208 selected_cpu_name
[i
] = 0;
32210 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32212 *input_line_pointer
= saved_char
;
32213 demand_empty_rest_of_line ();
32216 as_bad (_("unknown cpu `%s'"), name
);
32217 *input_line_pointer
= saved_char
;
32218 ignore_rest_of_line ();
32221 /* Parse a .arch directive. */
32224 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32226 const struct arm_arch_option_table
*opt
;
32230 name
= input_line_pointer
;
32231 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32232 input_line_pointer
++;
32233 saved_char
= *input_line_pointer
;
32234 *input_line_pointer
= 0;
32236 /* Skip the first "all" entry. */
32237 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32238 if (streq (opt
->name
, name
))
32240 selected_arch
= opt
->value
;
32241 selected_ext
= arm_arch_none
;
32242 selected_cpu
= selected_arch
;
32243 strcpy (selected_cpu_name
, opt
->name
);
32244 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32245 *input_line_pointer
= saved_char
;
32246 demand_empty_rest_of_line ();
32250 as_bad (_("unknown architecture `%s'\n"), name
);
32251 *input_line_pointer
= saved_char
;
32252 ignore_rest_of_line ();
32255 /* Parse a .object_arch directive. */
32258 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32260 const struct arm_arch_option_table
*opt
;
32264 name
= input_line_pointer
;
32265 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32266 input_line_pointer
++;
32267 saved_char
= *input_line_pointer
;
32268 *input_line_pointer
= 0;
32270 /* Skip the first "all" entry. */
32271 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32272 if (streq (opt
->name
, name
))
32274 selected_object_arch
= opt
->value
;
32275 *input_line_pointer
= saved_char
;
32276 demand_empty_rest_of_line ();
32280 as_bad (_("unknown architecture `%s'\n"), name
);
32281 *input_line_pointer
= saved_char
;
32282 ignore_rest_of_line ();
32285 /* Parse a .arch_extension directive. */
32288 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32290 const struct arm_option_extension_value_table
*opt
;
32293 int adding_value
= 1;
32295 name
= input_line_pointer
;
32296 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32297 input_line_pointer
++;
32298 saved_char
= *input_line_pointer
;
32299 *input_line_pointer
= 0;
32301 if (strlen (name
) >= 2
32302 && strncmp (name
, "no", 2) == 0)
32308 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32309 if (streq (opt
->name
, name
))
32311 int i
, nb_allowed_archs
=
32312 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32313 for (i
= 0; i
< nb_allowed_archs
; i
++)
32316 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32318 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32322 if (i
== nb_allowed_archs
)
32324 as_bad (_("architectural extension `%s' is not allowed for the "
32325 "current base architecture"), name
);
32330 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32333 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32335 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32336 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32337 *input_line_pointer
= saved_char
;
32338 demand_empty_rest_of_line ();
32339 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32340 on this return so that duplicate extensions (extensions with the
32341 same name as a previous extension in the list) are not considered
32342 for command-line parsing. */
32346 if (opt
->name
== NULL
)
32347 as_bad (_("unknown architecture extension `%s'\n"), name
);
32349 *input_line_pointer
= saved_char
;
32350 ignore_rest_of_line ();
32353 /* Parse a .fpu directive. */
32356 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32358 const struct arm_option_fpu_value_table
*opt
;
32362 name
= input_line_pointer
;
32363 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32364 input_line_pointer
++;
32365 saved_char
= *input_line_pointer
;
32366 *input_line_pointer
= 0;
32368 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32369 if (streq (opt
->name
, name
))
32371 selected_fpu
= opt
->value
;
32372 #ifndef CPU_DEFAULT
32373 if (no_cpu_selected ())
32374 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32377 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32378 *input_line_pointer
= saved_char
;
32379 demand_empty_rest_of_line ();
32383 as_bad (_("unknown floating point format `%s'\n"), name
);
32384 *input_line_pointer
= saved_char
;
32385 ignore_rest_of_line ();
32388 /* Copy symbol information. */
32391 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32393 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32397 /* Given a symbolic attribute NAME, return the proper integer value.
32398 Returns -1 if the attribute is not known. */
32401 arm_convert_symbolic_attribute (const char *name
)
32403 static const struct
32408 attribute_table
[] =
32410 /* When you modify this table you should
32411 also modify the list in doc/c-arm.texi. */
32412 #define T(tag) {#tag, tag}
32413 T (Tag_CPU_raw_name
),
32416 T (Tag_CPU_arch_profile
),
32417 T (Tag_ARM_ISA_use
),
32418 T (Tag_THUMB_ISA_use
),
32422 T (Tag_Advanced_SIMD_arch
),
32423 T (Tag_PCS_config
),
32424 T (Tag_ABI_PCS_R9_use
),
32425 T (Tag_ABI_PCS_RW_data
),
32426 T (Tag_ABI_PCS_RO_data
),
32427 T (Tag_ABI_PCS_GOT_use
),
32428 T (Tag_ABI_PCS_wchar_t
),
32429 T (Tag_ABI_FP_rounding
),
32430 T (Tag_ABI_FP_denormal
),
32431 T (Tag_ABI_FP_exceptions
),
32432 T (Tag_ABI_FP_user_exceptions
),
32433 T (Tag_ABI_FP_number_model
),
32434 T (Tag_ABI_align_needed
),
32435 T (Tag_ABI_align8_needed
),
32436 T (Tag_ABI_align_preserved
),
32437 T (Tag_ABI_align8_preserved
),
32438 T (Tag_ABI_enum_size
),
32439 T (Tag_ABI_HardFP_use
),
32440 T (Tag_ABI_VFP_args
),
32441 T (Tag_ABI_WMMX_args
),
32442 T (Tag_ABI_optimization_goals
),
32443 T (Tag_ABI_FP_optimization_goals
),
32444 T (Tag_compatibility
),
32445 T (Tag_CPU_unaligned_access
),
32446 T (Tag_FP_HP_extension
),
32447 T (Tag_VFP_HP_extension
),
32448 T (Tag_ABI_FP_16bit_format
),
32449 T (Tag_MPextension_use
),
32451 T (Tag_nodefaults
),
32452 T (Tag_also_compatible_with
),
32453 T (Tag_conformance
),
32455 T (Tag_Virtualization_use
),
32456 T (Tag_DSP_extension
),
32458 /* We deliberately do not include Tag_MPextension_use_legacy. */
32466 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32467 if (streq (name
, attribute_table
[i
].name
))
32468 return attribute_table
[i
].tag
;
32473 /* Apply sym value for relocations only in the case that they are for
32474 local symbols in the same segment as the fixup and you have the
32475 respective architectural feature for blx and simple switches. */
32478 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32481 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32482 /* PR 17444: If the local symbol is in a different section then a reloc
32483 will always be generated for it, so applying the symbol value now
32484 will result in a double offset being stored in the relocation. */
32485 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32486 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32488 switch (fixP
->fx_r_type
)
32490 case BFD_RELOC_ARM_PCREL_BLX
:
32491 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32492 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32496 case BFD_RELOC_ARM_PCREL_CALL
:
32497 case BFD_RELOC_THUMB_PCREL_BLX
:
32498 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32509 #endif /* OBJ_ELF */