1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d10v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
44 #define MAX_INSN_FIXUPS (5)
51 bfd_reloc_code_real_type reloc
;
54 typedef struct _fixups
57 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
61 static Fixups FixUps
[2];
62 static Fixups
*fixups
;
64 static int do_not_ignore_hash
= 0;
66 typedef int packing_type
;
67 #define PACK_UNSPEC (0) /* Packing order not specified. */
68 #define PACK_PARALLEL (1) /* "||" */
69 #define PACK_LEFT_RIGHT (2) /* "->" */
70 #define PACK_RIGHT_LEFT (3) /* "<-" */
71 static packing_type etype
= PACK_UNSPEC
; /* Used by d10v_cleanup. */
73 /* True if instruction swapping warnings should be inhibited. */
74 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
76 /* Local functions. */
77 static int reg_name_search
PARAMS ((char *name
));
78 static int register_name
PARAMS ((expressionS
*expressionP
));
79 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
80 static int postfix
PARAMS ((char *p
));
81 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
82 static int get_operands
PARAMS ((expressionS exp
[]));
83 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
84 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
85 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
86 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
87 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
88 struct d10v_opcode
*opcode2
, unsigned long insn2
, packing_type exec_type
, Fixups
*fx
));
89 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
90 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
91 offsetT value
, int left
, fixS
*fix
));
92 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
93 struct d10v_opcode
*opcode2
, unsigned long insn2
,
94 packing_type exec_type
));
95 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
97 struct option md_longopts
[] =
99 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
100 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
101 {NULL
, no_argument
, NULL
, 0}
103 size_t md_longopts_size
= sizeof(md_longopts
);
105 static void d10v_dot_word
PARAMS ((int));
107 /* The target specific pseudo-ops which we support. */
108 const pseudo_typeS md_pseudo_table
[] =
110 { "word", d10v_dot_word
, 2 },
114 /* Opcode hash table. */
115 static struct hash_control
*d10v_hash
;
117 /* Do a binary search of the d10v_predefined_registers array to see if
118 NAME is a valid regiter name. Return the register number from the
119 array on success, or -1 on failure. */
122 reg_name_search (name
)
125 int middle
, low
, high
;
129 high
= d10v_reg_name_cnt () - 1;
133 middle
= (low
+ high
) / 2;
134 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
140 return d10v_predefined_registers
[middle
].value
;
146 /* Check the string at input_line_pointer
147 to see if it is a valid register name. */
150 register_name (expressionP
)
151 expressionS
*expressionP
;
154 char c
, *p
= input_line_pointer
;
157 && *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
164 /* Look to see if it's in the register table. */
165 reg_number
= reg_name_search (input_line_pointer
);
168 expressionP
->X_op
= O_register
;
169 /* Temporarily store a pointer to the string here. */
170 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
171 expressionP
->X_add_number
= reg_number
;
172 input_line_pointer
= p
;
181 check_range (num
, bits
, flags
)
189 /* Don't bother checking 16-bit values. */
193 if (flags
& OPERAND_SHIFT
)
195 /* All special shift operands are unsigned and <= 16.
196 We allow 0 for now. */
203 if (flags
& OPERAND_SIGNED
)
205 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
206 if (flags
& RESTRICTED_NUM3
)
208 if ((long) num
< -2 || (long) num
> 3)
213 max
= (1 << (bits
- 1)) - 1;
214 min
= - (1 << (bits
- 1));
215 if (((long) num
> max
) || ((long) num
< min
))
221 max
= (1 << bits
) - 1;
223 if ((num
> max
) || (num
< min
))
230 md_show_usage (stream
)
233 fprintf (stream
, _("D10V options:\n\
234 -O optimize. Will do some operations in parallel.\n"));
238 md_parse_option (c
, arg
)
245 /* Optimize. Will attempt to parallelize operations. */
248 case OPTION_NOWARNSWAP
:
249 flag_warn_suppress_instructionswap
= 1;
258 md_undefined_symbol (name
)
264 /* Turn a string in input_line_pointer into a floating point constant
265 of type TYPE, and store the appropriate bytes in *LITP. The number
266 of LITTLENUMS emitted is stored in *SIZEP. An error message is
267 returned, or NULL on OK. */
270 md_atof (type
, litP
, sizeP
)
276 LITTLENUM_TYPE words
[4];
290 return _("bad call to md_atof");
293 t
= atof_ieee (input_line_pointer
, type
, words
);
295 input_line_pointer
= t
;
299 for (i
= 0; i
< prec
; i
++)
301 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
308 md_convert_frag (abfd
, sec
, fragP
)
317 md_section_align (seg
, addr
)
321 int align
= bfd_get_section_alignment (stdoutput
, seg
);
322 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
328 char *prev_name
= "";
329 struct d10v_opcode
*opcode
;
330 d10v_hash
= hash_new ();
332 /* Insert unique names into hash table. The D10v instruction set
333 has many identical opcode names that have different opcodes based
334 on the operands. This hash table then provides a quick index to
335 the first opcode with a particular name in the opcode table. */
337 for (opcode
= (struct d10v_opcode
*) d10v_opcodes
; opcode
->name
; opcode
++)
339 if (strcmp (prev_name
, opcode
->name
))
341 prev_name
= (char *) opcode
->name
;
342 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
347 FixUps
[0].next
= &FixUps
[1];
348 FixUps
[1].next
= &FixUps
[0];
351 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
352 from an expression. */
358 while (*p
!= '-' && *p
!= '+')
360 if (*p
== 0 || *p
== '\n' || *p
== '\r')
379 static bfd_reloc_code_real_type
381 struct d10v_operand
*op
;
388 if (op
->flags
& OPERAND_ADDR
)
391 return (BFD_RELOC_D10V_10_PCREL_R
);
393 return (BFD_RELOC_D10V_18_PCREL
);
396 return (BFD_RELOC_16
);
399 /* Parse a string of operands. Return an array of expressions. */
405 char *p
= input_line_pointer
;
412 while (*p
== ' ' || *p
== '\t' || *p
== ',')
414 if (*p
== 0 || *p
== '\n' || *p
== '\r')
422 exp
[numops
].X_op
= O_absent
;
426 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
431 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
435 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
444 /* Just skip the trailing paren. */
449 input_line_pointer
= p
;
451 /* Check to see if it might be a register name. */
452 if (!register_name (&exp
[numops
]))
454 /* Parse as an expression. */
457 /* Any expression that involves the indirect addressing
458 cannot also involve immediate addressing. Therefore
459 the use of the hash character is illegal. */
460 int save
= do_not_ignore_hash
;
461 do_not_ignore_hash
= 1;
463 expression (&exp
[numops
]);
465 do_not_ignore_hash
= save
;
468 expression (&exp
[numops
]);
471 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
473 input_line_pointer
+= 5;
474 if (exp
[numops
].X_op
== O_register
)
476 /* If it looked like a register name but was followed by
477 "@word" then it was really a symbol, so change it to
479 exp
[numops
].X_op
= O_symbol
;
480 exp
[numops
].X_add_symbol
=
481 symbol_find_or_make ((char *) exp
[numops
].X_op_symbol
);
484 /* Check for identifier@word+constant. */
485 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
487 char *orig_line
= input_line_pointer
;
489 expression (&new_exp
);
490 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
493 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
496 memset (&new_exp
, 0, sizeof new_exp
);
497 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
498 new_exp
.X_op
= O_constant
;
499 new_exp
.X_unsigned
= 1;
500 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
501 exp
[numops
].X_op
= O_right_shift
;
504 know (AT_WORD_P (&exp
[numops
]));
507 if (exp
[numops
].X_op
== O_illegal
)
508 as_bad (_("illegal operand"));
509 else if (exp
[numops
].X_op
== O_absent
)
510 as_bad (_("missing operand"));
513 p
= input_line_pointer
;
518 case -1: /* Postdecrement mode. */
519 exp
[numops
].X_op
= O_absent
;
520 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
522 case 1: /* Postincrement mode. */
523 exp
[numops
].X_op
= O_absent
;
524 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
528 exp
[numops
].X_op
= 0;
533 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
542 shift
= d10v_operands
[op_type
].shift
;
546 bits
= d10v_operands
[op_type
].bits
;
548 /* Truncate to the proper number of bits. */
549 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
550 as_bad_where (fix
->fx_file
, fix
->fx_line
, _("operand out of range: %d"), value
);
552 value
&= 0x7FFFFFFF >> (31 - bits
);
553 insn
|= (value
<< shift
);
558 /* Take a pointer to the opcode entry in the opcode table and the
559 array of operand expressions. Return the instruction. */
562 build_insn (opcode
, opers
, insn
)
563 struct d10v_opcode
*opcode
;
567 int i
, bits
, shift
, flags
, format
;
568 unsigned long number
;
570 /* The insn argument is only used for the DIVS kludge. */
575 insn
= opcode
->opcode
;
576 format
= opcode
->format
;
579 for (i
= 0; opcode
->operands
[i
]; i
++)
581 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
582 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
583 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
584 number
= opers
[i
].X_add_number
;
586 if (flags
& OPERAND_REG
)
588 number
&= REGISTER_MASK
;
589 if (format
== LONG_L
)
593 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
595 /* Now create a fixup. */
597 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
598 as_fatal (_("too many fixups"));
600 if (AT_WORD_P (&opers
[i
]))
602 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
603 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
604 opers
[i
].X_op
= O_symbol
;
605 opers
[i
].X_op_symbol
= NULL
; /* Should free it. */
606 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
607 that, it is aligned with the symbol's value. Later,
608 BFD_RELOC_D10V_18 will right shift (symbol_value +
610 number
<<= AT_WORD_RIGHT_SHIFT
;
611 opers
[i
].X_add_number
= number
;
614 fixups
->fix
[fixups
->fc
].reloc
=
615 get_reloc ((struct d10v_operand
*) &d10v_operands
[opcode
->operands
[i
]]);
617 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
618 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
619 fixups
->fix
[fixups
->fc
].size
= 2;
621 fixups
->fix
[fixups
->fc
].size
= 4;
623 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
624 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
625 fixups
->fix
[fixups
->fc
].pcrel
=
626 (flags
& OPERAND_ADDR
) ? true : false;
630 /* Truncate to the proper number of bits. */
631 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
632 as_bad (_("operand out of range: %d"), number
);
633 number
&= 0x7FFFFFFF >> (31 - bits
);
634 insn
= insn
| (number
<< shift
);
637 /* kludge: for DIVS, we need to put the operands in twice */
638 /* on the second pass, format is changed to LONG_R to force
639 the second set of operands to not be shifted over 15. */
640 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
== LONG_L
))
641 insn
= build_insn (opcode
, opers
, insn
);
646 /* Write out a long form instruction. */
649 write_long (opcode
, insn
, fx
)
650 struct d10v_opcode
*opcode
;
655 char *f
= frag_more (4);
658 number_to_chars_bigendian (f
, insn
, 4);
660 for (i
= 0; i
< fx
->fc
; i
++)
662 if (fx
->fix
[i
].reloc
)
664 where
= f
- frag_now
->fr_literal
;
665 if (fx
->fix
[i
].size
== 2)
668 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
669 fx
->fix
[i
].operand
|= 4096;
671 fix_new_exp (frag_now
,
676 fx
->fix
[i
].operand
|2048);
682 /* Write out a short form instruction by itself. */
685 write_1_short (opcode
, insn
, fx
)
686 struct d10v_opcode
*opcode
;
690 char *f
= frag_more (4);
693 if (opcode
->exec_type
& PARONLY
)
694 as_fatal (_("Instruction must be executed in parallel with another instruction."));
696 /* The other container needs to be NOP. */
697 /* According to 4.3.1: for FM=00, sub-instructions performed only
698 by IU cannot be encoded in L-container. */
699 if (opcode
->unit
== IU
)
700 insn
|= FM00
| (NOP
<< 15); /* Right container. */
702 insn
= FM00
| (insn
<< 15) | NOP
; /* Left container. */
704 number_to_chars_bigendian (f
, insn
, 4);
705 for (i
= 0; i
< fx
->fc
; i
++)
707 if (fx
->fix
[i
].reloc
)
709 where
= f
- frag_now
->fr_literal
;
710 if (fx
->fix
[i
].size
== 2)
713 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
714 fx
->fix
[i
].operand
|= 4096;
716 /* If it's an R reloc, we may have to switch it to L. */
717 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
)
718 && (opcode
->unit
!= IU
))
719 fx
->fix
[i
].operand
|= 1024;
721 fix_new_exp (frag_now
,
726 fx
->fix
[i
].operand
|2048);
732 /* Expects two short instructions.
733 If possible, writes out both as a single packed instruction.
734 Otherwise, writes out the first one, packed with a NOP.
735 Returns number of instructions not written out. */
738 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
739 struct d10v_opcode
*opcode1
, *opcode2
;
740 unsigned long insn1
, insn2
;
741 packing_type exec_type
;
748 if ((exec_type
!= PACK_PARALLEL
)
749 && ((opcode1
->exec_type
& PARONLY
) || (opcode2
->exec_type
& PARONLY
)))
750 as_fatal (_("Instruction must be executed in parallel"));
752 if ((opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
753 as_fatal (_("Long instructions may not be combined."));
757 case PACK_UNSPEC
: /* Order not specified. */
758 if (opcode1
->exec_type
& ALONE
)
760 /* Case of a short branch on a separate GAS line.
762 write_1_short (opcode1
, insn1
, fx
->next
);
766 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
769 if (opcode1
->unit
== IU
)
770 insn
= FM00
| (insn2
<< 15) | insn1
;
771 else if (opcode2
->unit
== MU
)
772 insn
= FM00
| (insn2
<< 15) | insn1
;
775 insn
= FM00
| (insn1
<< 15) | insn2
;
776 /* Advance over dummy fixup since packed insn1 in L. */
780 else if (opcode1
->unit
== IU
)
781 /* Reverse sequential with IU opcode1 on right and done first. */
782 insn
= FM10
| (insn2
<< 15) | insn1
;
785 /* Sequential with non-IU opcode1 on left and done first. */
786 insn
= FM01
| (insn1
<< 15) | insn2
;
787 /* Advance over dummy fixup since packed insn1 in L. */
793 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
795 (_("One of these instructions may not be executed in parallel."));
796 if (opcode1
->unit
== IU
)
798 if (opcode2
->unit
== IU
)
799 as_fatal (_("Two IU instructions may not be executed in parallel"));
800 if (!flag_warn_suppress_instructionswap
)
801 as_warn (_("Swapping instruction order"));
802 insn
= FM00
| (insn2
<< 15) | insn1
;
804 else if (opcode2
->unit
== MU
)
806 if (opcode1
->unit
== MU
)
807 as_fatal (_("Two MU instructions may not be executed in parallel"));
808 if (!flag_warn_suppress_instructionswap
)
809 as_warn (_("Swapping instruction order"));
810 insn
= FM00
| (insn2
<< 15) | insn1
;
814 insn
= FM00
| (insn1
<< 15) | insn2
;
815 /* Advance over dummy fixup since packed insn1 in L. */
820 case PACK_LEFT_RIGHT
:
821 if (opcode1
->unit
!= IU
)
822 insn
= FM01
| (insn1
<< 15) | insn2
;
823 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
825 if (!flag_warn_suppress_instructionswap
)
826 as_warn (_("Swapping instruction order"));
827 insn
= FM10
| (insn2
<< 15) | insn1
;
830 as_fatal (_("IU instruction may not be in the left container"));
831 if (opcode1
->exec_type
& ALONE
)
832 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
833 /* Advance over dummy fixup. */
837 case PACK_RIGHT_LEFT
:
838 if (opcode2
->unit
!= MU
)
839 insn
= FM10
| (insn1
<< 15) | insn2
;
840 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
842 if (!flag_warn_suppress_instructionswap
)
843 as_warn (_("Swapping instruction order"));
844 insn
= FM01
| (insn2
<< 15) | insn1
;
847 as_fatal (_("MU instruction may not be in the right container"));
848 if (opcode2
->exec_type
& ALONE
)
849 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
850 /* Advance over dummy fixup. */
855 as_fatal (_("unknown execution type passed to write_2_short()"));
859 number_to_chars_bigendian (f
, insn
, 4);
861 /* Process fixup chains.
862 Note that the packing code above advanced fx conditionally.
863 dlindsay@cygnus.com: There's something subtle going on here involving
864 _dummy_first_bfd_reloc_code_real. This is related to the
865 difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
866 a fixup is done in the L or R container. A bug in this code
867 can pass Plum Hall fine, yet still affect hand-written assembler. */
869 for (j
= 0; j
< 2; j
++)
871 for (i
= 0; i
< fx
->fc
; i
++)
873 if (fx
->fix
[i
].reloc
)
875 where
= f
- frag_now
->fr_literal
;
876 if (fx
->fix
[i
].size
== 2)
879 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0))
880 fx
->fix
[i
].operand
|= 1024;
882 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
883 fx
->fix
[i
].operand
|= 4096;
885 fix_new_exp (frag_now
,
890 fx
->fix
[i
].operand
|2048);
899 /* Check 2 instructions and determine if they can be safely
900 executed in parallel. Return 1 if they can be. */
903 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
904 struct d10v_opcode
*op1
, *op2
;
905 unsigned long insn1
, insn2
;
906 packing_type exec_type
;
908 int i
, j
, flags
, mask
, shift
, regno
;
909 unsigned long ins
, mod
[2], used
[2];
910 struct d10v_opcode
*op
;
912 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
913 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
914 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
915 || (op1
->unit
== IU
&& op2
->unit
== IU
)
916 || (op1
->unit
== MU
&& op2
->unit
== MU
))
919 /* If this is auto parallization, and either instruction is a branch,
921 if (exec_type
== PACK_UNSPEC
922 && (op1
->exec_type
& ALONE
|| op2
->exec_type
& ALONE
))
925 /* The idea here is to create two sets of bitmasks (mod and used)
926 which indicate which registers are modified or used by each
927 instruction. The operation can only be done in parallel if
928 instruction 1 and instruction 2 modify different registers, and
929 the first instruction does not modify registers that the second
930 is using (The second instruction can modify registers that the
931 first is using as they are only written back after the first
932 instruction has completed). Accesses to control registers, PSW,
933 and memory are treated as accesses to a single register. So if
934 both instructions write memory or if the first instruction writes
935 memory and the second reads, then they cannot be done in
936 parallel. Likewise, if the first instruction mucks with the psw
937 and the second reads the PSW (which includes C, F0, and F1), then
938 they cannot operate safely in parallel. */
940 /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
943 /* cr (not psw) 18 */
947 for (j
= 0; j
< 2; j
++)
959 mod
[j
] = used
[j
] = 0;
960 if (op
->exec_type
& BRANCH_LINK
)
963 for (i
= 0; op
->operands
[i
]; i
++)
965 flags
= d10v_operands
[op
->operands
[i
]].flags
;
966 shift
= d10v_operands
[op
->operands
[i
]].shift
;
967 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
968 if (flags
& OPERAND_REG
)
970 regno
= (ins
>> shift
) & mask
;
971 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
973 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc. */
980 else if (flags
& (OPERAND_FFLAG
| OPERAND_CFLAG
))
983 if (flags
& OPERAND_DEST
)
985 mod
[j
] |= 1 << regno
;
986 if (flags
& OPERAND_EVEN
)
987 mod
[j
] |= 1 << (regno
+ 1);
991 used
[j
] |= 1 << regno
;
992 if (flags
& OPERAND_EVEN
)
993 used
[j
] |= 1 << (regno
+ 1);
995 /* Auto inc/dec also modifies the register. */
996 if (op
->operands
[i
+ 1] != 0
997 && (d10v_operands
[op
->operands
[i
+ 1]].flags
998 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
999 mod
[j
] |= 1 << regno
;
1002 else if (flags
& OPERAND_ATMINUS
)
1004 /* SP implicitly used/modified. */
1009 if (op
->exec_type
& RMEM
)
1011 else if (op
->exec_type
& WMEM
)
1013 else if (op
->exec_type
& RF0
)
1015 else if (op
->exec_type
& WF0
)
1017 else if (op
->exec_type
& WCAR
)
1020 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
1025 /* This is the main entry point for the machine-dependent assembler.
1026 STR points to a machine-dependent instruction. This function is
1027 supposed to emit the frags/bytes it assembles to. For the D10V, it
1028 mostly handles the special VLIW parsing and packing and leaves the
1029 difficult stuff to do_assemble(). */
1031 static unsigned long prev_insn
;
1032 static struct d10v_opcode
*prev_opcode
= 0;
1033 static subsegT prev_subseg
;
1034 static segT prev_seg
= 0;;
1040 /* etype is saved extype. For multi-line instructions. */
1042 packing_type extype
= PACK_UNSPEC
; /* Parallel, etc. */
1044 struct d10v_opcode
*opcode
;
1048 if (etype
== PACK_UNSPEC
)
1050 /* Look for the special multiple instruction separators. */
1051 str2
= strstr (str
, "||");
1053 extype
= PACK_PARALLEL
;
1056 str2
= strstr (str
, "->");
1058 extype
= PACK_LEFT_RIGHT
;
1061 str2
= strstr (str
, "<-");
1063 extype
= PACK_RIGHT_LEFT
;
1066 /* STR2 points to the separator, if there is one. */
1071 /* If two instructions are present and we already have one saved,
1072 then first write out the saved one. */
1075 /* Assemble first instruction and save it. */
1076 prev_insn
= do_assemble (str
, &prev_opcode
);
1077 if (prev_insn
== -1)
1078 as_fatal (_("can't find opcode "));
1079 fixups
= fixups
->next
;
1084 insn
= do_assemble (str
, &opcode
);
1087 if (extype
!= PACK_UNSPEC
)
1092 as_fatal (_("can't find opcode "));
1095 if (etype
!= PACK_UNSPEC
)
1098 etype
= PACK_UNSPEC
;
1101 /* If this is a long instruction, write it and any previous short
1103 if (opcode
->format
& LONG_OPCODE
)
1105 if (extype
!= PACK_UNSPEC
)
1106 as_fatal (_("Unable to mix instructions as specified"));
1108 write_long (opcode
, insn
, fixups
);
1115 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1119 && (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1121 /* No instructions saved. */
1126 if (extype
!= PACK_UNSPEC
)
1127 as_fatal (_("Unable to mix instructions as specified"));
1128 /* Save last instruction so it may be packed on next pass. */
1129 prev_opcode
= opcode
;
1132 prev_subseg
= now_subseg
;
1133 fixups
= fixups
->next
;
1137 /* Assemble a single instruction.
1138 Return an opcode, or -1 (an invalid opcode) on error. */
1140 static unsigned long
1141 do_assemble (str
, opcode
)
1143 struct d10v_opcode
**opcode
;
1145 unsigned char *op_start
, *save
;
1146 unsigned char *op_end
;
1149 expressionS myops
[6];
1152 /* Drop leading whitespace. */
1156 /* Find the opcode end. */
1157 for (op_start
= op_end
= (unsigned char *) (str
);
1160 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1163 name
[nlen
] = tolower (op_start
[nlen
]);
1171 /* Find the first opcode with the proper name. */
1172 *opcode
= (struct d10v_opcode
*) hash_find (d10v_hash
, name
);
1173 if (*opcode
== NULL
)
1174 as_fatal (_("unknown opcode: %s"), name
);
1176 save
= input_line_pointer
;
1177 input_line_pointer
= op_end
;
1178 *opcode
= find_opcode (*opcode
, myops
);
1181 input_line_pointer
= save
;
1183 insn
= build_insn ((*opcode
), myops
, 0);
1187 /* Find the symbol which has the same name as the register in EXP. */
1190 find_symbol_matching_register (exp
)
1195 if (exp
->X_op
!= O_register
)
1198 /* Find the name of the register. */
1199 for (i
= d10v_reg_name_cnt (); i
--;)
1200 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1206 /* Now see if a symbol has been defined with the same name. */
1207 return symbol_find (d10v_predefined_registers
[i
].name
);
1210 /* Get a pointer to an entry in the opcode table.
1211 The function must look at all opcodes with the same name and use
1212 the operands to choose the correct opcode. */
1214 static struct d10v_opcode
*
1215 find_opcode (opcode
, myops
)
1216 struct d10v_opcode
*opcode
;
1217 expressionS myops
[];
1220 struct d10v_opcode
*next_opcode
;
1222 /* Get all the operands and save them as expressions. */
1223 get_operands (myops
);
1225 /* Now see if the operand is a fake. If so, find the correct size
1226 instruction, if possible. */
1227 if (opcode
->format
== OPCODE_FAKE
)
1229 int opnum
= opcode
->operands
[0];
1232 if (myops
[opnum
].X_op
== O_register
)
1234 myops
[opnum
].X_op
= O_symbol
;
1235 myops
[opnum
].X_add_symbol
=
1236 symbol_find_or_make ((char *) myops
[opnum
].X_op_symbol
);
1237 myops
[opnum
].X_add_number
= 0;
1238 myops
[opnum
].X_op_symbol
= NULL
;
1241 next_opcode
= opcode
+ 1;
1243 /* If the first operand is supposed to be a register, make sure
1244 we got a valid one. */
1245 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1246 if (flags
& OPERAND_REG
)
1248 int X_op
= myops
[0].X_op
;
1249 int num
= myops
[0].X_add_number
;
1251 if (X_op
!= O_register
1253 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1254 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1256 as_bad (_("bad opcode or operands"));
1261 if (myops
[opnum
].X_op
== O_constant
1262 || (myops
[opnum
].X_op
== O_symbol
1263 && S_IS_DEFINED (myops
[opnum
].X_add_symbol
)
1264 && (S_GET_SEGMENT (myops
[opnum
].X_add_symbol
) == now_seg
)))
1266 for (i
= 0; opcode
->operands
[i
+ 1]; i
++)
1268 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1269 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1270 if (flags
& OPERAND_ADDR
)
1273 if (myops
[opnum
].X_op
== O_constant
)
1275 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1282 unsigned long current_position
;
1283 unsigned long symbol_position
;
1284 unsigned long value
;
1285 boolean found_symbol
;
1287 /* Calculate the address of the current instruction
1288 and the address of the symbol. Do this by summing
1289 the offsets of previous frags until we reach the
1290 frag containing the symbol, and the current frag. */
1291 sym_frag
= symbol_get_frag (myops
[opnum
].X_add_symbol
);
1292 found_symbol
= false;
1295 obstack_next_free (&frchain_now
->frch_obstack
)
1296 - frag_now
->fr_literal
;
1297 symbol_position
= S_GET_VALUE (myops
[opnum
].X_add_symbol
);
1299 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1301 current_position
+= f
->fr_fix
+ f
->fr_offset
;
1304 found_symbol
= true;
1307 symbol_position
+= f
->fr_fix
+ f
->fr_offset
;
1310 value
= symbol_position
;
1312 if (flags
& OPERAND_ADDR
)
1313 value
-= current_position
;
1315 if (AT_WORD_P (&myops
[opnum
]))
1320 if (!check_range (value
, bits
, flags
))
1324 else if (!check_range (value
, bits
, flags
))
1329 as_fatal (_("value out of range"));
1333 /* Not a constant, so use a long instruction. */
1340 /* Now search the opcode table table for one with operands
1341 that matches what we've got. */
1345 for (i
= 0; opcode
->operands
[i
]; i
++)
1347 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1348 int X_op
= myops
[i
].X_op
;
1349 int num
= myops
[i
].X_add_number
;
1357 if (flags
& OPERAND_REG
)
1359 if ((X_op
!= O_register
)
1361 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1362 | OPERAND_FFLAG
| OPERAND_CFLAG
1363 | OPERAND_CONTROL
)))
1370 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1371 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1372 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1373 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1374 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1380 /* Unfortunatly, for the indirect operand in
1381 instructions such as ``ldb r1, @(c,r14)'' this
1382 function can be passed X_op == O_register (because
1383 'c' is a valid register name). However we cannot
1384 just ignore the case when X_op == O_register but
1385 flags & OPERAND_REG is null, so we check to see if a
1386 symbol of the same name as the register exists. If
1387 the symbol does exist, then the parser was unable to
1388 distinguish the two cases and we fix things here.
1391 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1393 symbolS
*sym
= find_symbol_matching_register (&myops
[i
]);
1397 myops
[i
].X_op
= X_op
= O_symbol
;
1398 myops
[i
].X_add_symbol
= sym
;
1402 (_("illegal operand - register name found where none expected"));
1406 /* We're only done if the operands matched so far AND there
1407 are no more to check. */
1408 if (match
&& myops
[i
].X_op
== 0)
1413 next_opcode
= opcode
+ 1;
1415 if (next_opcode
->opcode
== 0)
1418 if (strcmp (next_opcode
->name
, opcode
->name
))
1421 opcode
= next_opcode
;
1427 as_bad (_("bad opcode or operands"));
1431 /* Check that all registers that are required to be even are.
1432 Also, if any operands were marked as registers, but were really symbols,
1434 for (i
= 0; opcode
->operands
[i
]; i
++)
1436 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1437 (myops
[i
].X_add_number
& 1))
1438 as_fatal (_("Register number must be EVEN"));
1439 if (myops
[i
].X_op
== O_register
)
1441 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1443 myops
[i
].X_op
= O_symbol
;
1444 myops
[i
].X_add_symbol
=
1445 symbol_find_or_make ((char *) myops
[i
].X_op_symbol
);
1446 myops
[i
].X_add_number
= 0;
1447 myops
[i
].X_op_symbol
= NULL
;
1454 /* If while processing a fixup, a reloc really needs to be created.
1455 Then it is done here. */
1458 tc_gen_reloc (seg
, fixp
)
1463 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1464 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1465 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1466 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1467 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1468 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1470 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1471 _("reloc %d not supported by object file format"),
1472 (int) fixp
->fx_r_type
);
1476 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1477 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1478 reloc
->address
= fixp
->fx_offset
;
1480 reloc
->addend
= fixp
->fx_addnumber
;
1486 md_estimate_size_before_relax (fragp
, seg
)
1495 md_pcrel_from_section (fixp
, sec
)
1499 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1500 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1501 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1503 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1507 md_apply_fix3 (fixp
, valuep
, seg
)
1518 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1523 else if (fixp
->fx_pcrel
)
1527 value
= fixp
->fx_offset
;
1528 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1530 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1531 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1534 /* We don't actually support subtracting a symbol. */
1535 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1536 _("expression too complex"));
1541 op_type
= fixp
->fx_r_type
;
1548 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1551 else if (op_type
& 4096)
1554 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1558 get_reloc ((struct d10v_operand
*) &d10v_operands
[op_type
]);
1561 /* Fetch the instruction, insert the fully resolved operand
1562 value, and stuff the instruction back again. */
1563 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1564 insn
= bfd_getb32 ((unsigned char *) where
);
1566 switch (fixp
->fx_r_type
)
1568 case BFD_RELOC_D10V_10_PCREL_L
:
1569 case BFD_RELOC_D10V_10_PCREL_R
:
1570 case BFD_RELOC_D10V_18_PCREL
:
1571 case BFD_RELOC_D10V_18
:
1572 /* Instruction addresses are always right-shifted by 2. */
1573 value
>>= AT_WORD_RIGHT_SHIFT
;
1574 if (fixp
->fx_size
== 2)
1575 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1578 struct d10v_opcode
*rep
, *repi
;
1580 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1581 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1582 if ((insn
& FM11
) == FM11
1583 && ((repi
!= NULL
&& (insn
& repi
->mask
) == repi
->opcode
)
1584 || (rep
!= NULL
&& (insn
& rep
->mask
) == rep
->opcode
))
1587 (_("line %d: rep or repi must include at least 4 instructions"),
1590 d10v_insert_operand (insn
, op_type
, (offsetT
) value
, left
, fixp
);
1591 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1595 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1598 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1601 case BFD_RELOC_VTABLE_INHERIT
:
1602 case BFD_RELOC_VTABLE_ENTRY
:
1607 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1608 fixp
->fx_line
, fixp
->fx_r_type
);
1613 /* Called after the assembler has finished parsing the input file or
1614 after a label is defined. Because the D10V assembler sometimes
1615 saves short instructions to see if it can package them with the
1616 next instruction, there may be a short instruction that still needs
1619 NOTE: accesses a global, etype.
1620 NOTE: invoked by various macros such as md_cleanup: see. */
1628 if (prev_opcode
&& etype
== PACK_UNSPEC
)
1631 subseg
= now_subseg
;
1633 subseg_set (prev_seg
, prev_subseg
);
1634 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1635 subseg_set (seg
, subseg
);
1641 /* Like normal .word, except support @word. */
1642 /* Clobbers input_line_pointer, checks end-of-line. */
1645 d10v_dot_word (nbytes
)
1646 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1649 bfd_reloc_code_real_type reloc
;
1653 if (is_it_end_of_statement ())
1655 demand_empty_rest_of_line ();
1662 if (!strncasecmp (input_line_pointer
, "@word", 5))
1664 exp
.X_add_number
= 0;
1665 input_line_pointer
+= 5;
1668 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1669 &exp
, 0, BFD_RELOC_D10V_18
);
1672 emit_expr (&exp
, 2);
1674 while (*input_line_pointer
++ == ',');
1676 input_line_pointer
--; /* Put terminator back into stream. */
1677 demand_empty_rest_of_line ();
1680 /* Mitsubishi asked that we support some old syntax that apparently
1681 had immediate operands starting with '#'. This is in some of their
1682 sample code but is not documented (although it appears in some
1683 examples in their assembler manual). For now, we'll solve this
1684 compatibility problem by simply ignoring any '#' at the beginning
1687 /* Operands that begin with '#' should fall through to here. */
1691 md_operand (expressionP
)
1692 expressionS
*expressionP
;
1694 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1696 input_line_pointer
++;
1697 expression (expressionP
);
1702 d10v_fix_adjustable (fixP
)
1705 if (fixP
->fx_addsy
== NULL
)
1708 /* Prevent all adjustments to global symbols. */
1709 if (S_IS_EXTERN (fixP
->fx_addsy
))
1711 if (S_IS_WEAK (fixP
->fx_addsy
))
1714 /* We need the symbol name for the VTABLE entries. */
1715 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1716 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1723 d10v_force_relocation (fixp
)
1726 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1727 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)