1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1018 CPU_ZNVER3_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1020 CPU_BTVER1_FLAGS
, 0 },
1021 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1022 CPU_BTVER2_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1024 CPU_8087_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1032 CPU_CMOV_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1034 CPU_FXSR_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE2_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4A_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1046 CPU_SSSE3_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_1_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1052 CPU_SSE4_2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1055 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX2_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512F_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512CD_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512ER_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512PF_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512DQ_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512BW_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1070 CPU_AVX512VL_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1074 CPU_VMFUNC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEOPT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVEC_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1084 CPU_XSAVES_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1090 CPU_PCLMUL_FLAGS
, 1 },
1091 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1092 CPU_FSGSBASE_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1094 CPU_RDRND_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1096 CPU_F16C_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1098 CPU_BMI2_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1102 CPU_FMA4_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1107 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1108 CPU_MOVBE_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1110 CPU_CX16_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_LZCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1116 CPU_POPCNT_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1121 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1122 CPU_INVPCID_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1124 CPU_CLFLUSH_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1127 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1128 CPU_SYSCALL_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1130 CPU_RDTSCP_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOW_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1134 CPU_3DNOWA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1136 CPU_PADLOCK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 1 },
1139 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1140 CPU_SVME_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1142 CPU_SSE4A_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1152 CPU_RDSEED_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1154 CPU_PRFCHW_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1156 CPU_SMAP_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1162 CPU_CLFLUSHOPT_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1164 CPU_PREFETCHWT1_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1167 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1168 CPU_CLWB_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512IFMA_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512VBMI_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VBMI2_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_VNNI_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_BITALG_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1186 CPU_AVX_VNNI_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1188 CPU_CLZERO_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1190 CPU_MWAITX_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1192 CPU_OSPKE_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1194 CPU_RDPID_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1196 CPU_PTWRITE_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1199 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1200 CPU_SHSTK_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1202 CPU_GFNI_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1204 CPU_VAES_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1206 CPU_VPCLMULQDQ_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1208 CPU_WBNOINVD_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1210 CPU_PCONFIG_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1212 CPU_WAITPKG_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1214 CPU_CLDEMOTE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_INT8_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1218 CPU_AMX_BF16_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1220 CPU_AMX_TILE_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1222 CPU_MOVDIRI_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1224 CPU_MOVDIR64B_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1226 CPU_AVX512_BF16_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1228 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1231 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1232 CPU_ENQCMD_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1234 CPU_SERIALIZE_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1236 CPU_RDPRU_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1238 CPU_MCOMMIT_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1240 CPU_SEV_ES_FLAGS
, 0 },
1241 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1242 CPU_TSXLDTRK_FLAGS
, 0 },
1243 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1245 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1246 CPU_WIDEKL_FLAGS
, 0 },
1247 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1248 CPU_UINTR_FLAGS
, 0 },
1249 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1250 CPU_HRESET_FLAGS
, 0 },
1253 static const noarch_entry cpu_noarch
[] =
1255 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1256 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1257 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1258 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1259 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1260 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1261 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1262 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1263 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1264 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1266 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1269 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1288 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1289 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1290 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1291 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1292 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1293 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1294 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1295 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1296 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1297 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1298 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1299 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1300 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1301 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1302 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1303 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1304 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1305 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1309 /* Like s_lcomm_internal in gas/read.c but the alignment string
1310 is allowed to be optional. */
1313 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1320 && *input_line_pointer
== ',')
1322 align
= parse_align (needs_align
- 1);
1324 if (align
== (addressT
) -1)
1339 bss_alloc (symbolP
, size
, align
);
1344 pe_lcomm (int needs_align
)
1346 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1350 const pseudo_typeS md_pseudo_table
[] =
1352 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1353 {"align", s_align_bytes
, 0},
1355 {"align", s_align_ptwo
, 0},
1357 {"arch", set_cpu_arch
, 0},
1361 {"lcomm", pe_lcomm
, 1},
1363 {"ffloat", float_cons
, 'f'},
1364 {"dfloat", float_cons
, 'd'},
1365 {"tfloat", float_cons
, 'x'},
1367 {"slong", signed_cons
, 4},
1368 {"noopt", s_ignore
, 0},
1369 {"optim", s_ignore
, 0},
1370 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1371 {"code16", set_code_flag
, CODE_16BIT
},
1372 {"code32", set_code_flag
, CODE_32BIT
},
1374 {"code64", set_code_flag
, CODE_64BIT
},
1376 {"intel_syntax", set_intel_syntax
, 1},
1377 {"att_syntax", set_intel_syntax
, 0},
1378 {"intel_mnemonic", set_intel_mnemonic
, 1},
1379 {"att_mnemonic", set_intel_mnemonic
, 0},
1380 {"allow_index_reg", set_allow_index_reg
, 1},
1381 {"disallow_index_reg", set_allow_index_reg
, 0},
1382 {"sse_check", set_check
, 0},
1383 {"operand_check", set_check
, 1},
1384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1385 {"largecomm", handle_large_common
, 0},
1387 {"file", dwarf2_directive_file
, 0},
1388 {"loc", dwarf2_directive_loc
, 0},
1389 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1392 {"secrel32", pe_directive_secrel
, 0},
1397 /* For interface with expression (). */
1398 extern char *input_line_pointer
;
1400 /* Hash table for instruction mnemonic lookup. */
1401 static htab_t op_hash
;
1403 /* Hash table for register lookup. */
1404 static htab_t reg_hash
;
1406 /* Various efficient no-op patterns for aligning code labels.
1407 Note: Don't try to assemble the instructions in the comments.
1408 0L and 0w are not legal. */
1409 static const unsigned char f32_1
[] =
1411 static const unsigned char f32_2
[] =
1412 {0x66,0x90}; /* xchg %ax,%ax */
1413 static const unsigned char f32_3
[] =
1414 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1415 static const unsigned char f32_4
[] =
1416 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1417 static const unsigned char f32_6
[] =
1418 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1419 static const unsigned char f32_7
[] =
1420 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1421 static const unsigned char f16_3
[] =
1422 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1423 static const unsigned char f16_4
[] =
1424 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1425 static const unsigned char jump_disp8
[] =
1426 {0xeb}; /* jmp disp8 */
1427 static const unsigned char jump32_disp32
[] =
1428 {0xe9}; /* jmp disp32 */
1429 static const unsigned char jump16_disp32
[] =
1430 {0x66,0xe9}; /* jmp disp32 */
1431 /* 32-bit NOPs patterns. */
1432 static const unsigned char *const f32_patt
[] = {
1433 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1435 /* 16-bit NOPs patterns. */
1436 static const unsigned char *const f16_patt
[] = {
1437 f32_1
, f32_2
, f16_3
, f16_4
1439 /* nopl (%[re]ax) */
1440 static const unsigned char alt_3
[] =
1442 /* nopl 0(%[re]ax) */
1443 static const unsigned char alt_4
[] =
1444 {0x0f,0x1f,0x40,0x00};
1445 /* nopl 0(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_5
[] =
1447 {0x0f,0x1f,0x44,0x00,0x00};
1448 /* nopw 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_6
[] =
1450 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopl 0L(%[re]ax) */
1452 static const unsigned char alt_7
[] =
1453 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1454 /* nopl 0L(%[re]ax,%[re]ax,1) */
1455 static const unsigned char alt_8
[] =
1456 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* nopw 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_9
[] =
1459 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_10
[] =
1462 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* data16 nopw %cs:0L(%eax,%eax,1) */
1464 static const unsigned char alt_11
[] =
1465 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* 32-bit and 64-bit NOPs patterns. */
1467 static const unsigned char *const alt_patt
[] = {
1468 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1469 alt_9
, alt_10
, alt_11
1472 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1473 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1476 i386_output_nops (char *where
, const unsigned char *const *patt
,
1477 int count
, int max_single_nop_size
)
1480 /* Place the longer NOP first. */
1483 const unsigned char *nops
;
1485 if (max_single_nop_size
< 1)
1487 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1488 max_single_nop_size
);
1492 nops
= patt
[max_single_nop_size
- 1];
1494 /* Use the smaller one if the requsted one isn't available. */
1497 max_single_nop_size
--;
1498 nops
= patt
[max_single_nop_size
- 1];
1501 last
= count
% max_single_nop_size
;
1504 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1505 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1509 nops
= patt
[last
- 1];
1512 /* Use the smaller one plus one-byte NOP if the needed one
1515 nops
= patt
[last
- 1];
1516 memcpy (where
+ offset
, nops
, last
);
1517 where
[offset
+ last
] = *patt
[0];
1520 memcpy (where
+ offset
, nops
, last
);
1525 fits_in_imm7 (offsetT num
)
1527 return (num
& 0x7f) == num
;
1531 fits_in_imm31 (offsetT num
)
1533 return (num
& 0x7fffffff) == num
;
1536 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1537 single NOP instruction LIMIT. */
1540 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1542 const unsigned char *const *patt
= NULL
;
1543 int max_single_nop_size
;
1544 /* Maximum number of NOPs before switching to jump over NOPs. */
1545 int max_number_of_nops
;
1547 switch (fragP
->fr_type
)
1552 case rs_machine_dependent
:
1553 /* Allow NOP padding for jumps and calls. */
1554 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1555 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1562 /* We need to decide which NOP sequence to use for 32bit and
1563 64bit. When -mtune= is used:
1565 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1566 PROCESSOR_GENERIC32, f32_patt will be used.
1567 2. For the rest, alt_patt will be used.
1569 When -mtune= isn't used, alt_patt will be used if
1570 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1573 When -march= or .arch is used, we can't use anything beyond
1574 cpu_arch_isa_flags. */
1576 if (flag_code
== CODE_16BIT
)
1579 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1580 /* Limit number of NOPs to 2 in 16-bit mode. */
1581 max_number_of_nops
= 2;
1585 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1587 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1588 switch (cpu_arch_tune
)
1590 case PROCESSOR_UNKNOWN
:
1591 /* We use cpu_arch_isa_flags to check if we SHOULD
1592 optimize with nops. */
1593 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1598 case PROCESSOR_PENTIUM4
:
1599 case PROCESSOR_NOCONA
:
1600 case PROCESSOR_CORE
:
1601 case PROCESSOR_CORE2
:
1602 case PROCESSOR_COREI7
:
1603 case PROCESSOR_L1OM
:
1604 case PROCESSOR_K1OM
:
1605 case PROCESSOR_GENERIC64
:
1607 case PROCESSOR_ATHLON
:
1609 case PROCESSOR_AMDFAM10
:
1611 case PROCESSOR_ZNVER
:
1615 case PROCESSOR_I386
:
1616 case PROCESSOR_I486
:
1617 case PROCESSOR_PENTIUM
:
1618 case PROCESSOR_PENTIUMPRO
:
1619 case PROCESSOR_IAMCU
:
1620 case PROCESSOR_GENERIC32
:
1627 switch (fragP
->tc_frag_data
.tune
)
1629 case PROCESSOR_UNKNOWN
:
1630 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1631 PROCESSOR_UNKNOWN. */
1635 case PROCESSOR_I386
:
1636 case PROCESSOR_I486
:
1637 case PROCESSOR_PENTIUM
:
1638 case PROCESSOR_IAMCU
:
1640 case PROCESSOR_ATHLON
:
1642 case PROCESSOR_AMDFAM10
:
1644 case PROCESSOR_ZNVER
:
1646 case PROCESSOR_GENERIC32
:
1647 /* We use cpu_arch_isa_flags to check if we CAN optimize
1649 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1654 case PROCESSOR_PENTIUMPRO
:
1655 case PROCESSOR_PENTIUM4
:
1656 case PROCESSOR_NOCONA
:
1657 case PROCESSOR_CORE
:
1658 case PROCESSOR_CORE2
:
1659 case PROCESSOR_COREI7
:
1660 case PROCESSOR_L1OM
:
1661 case PROCESSOR_K1OM
:
1662 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1667 case PROCESSOR_GENERIC64
:
1673 if (patt
== f32_patt
)
1675 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1676 /* Limit number of NOPs to 2 for older processors. */
1677 max_number_of_nops
= 2;
1681 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1682 /* Limit number of NOPs to 7 for newer processors. */
1683 max_number_of_nops
= 7;
1688 limit
= max_single_nop_size
;
1690 if (fragP
->fr_type
== rs_fill_nop
)
1692 /* Output NOPs for .nop directive. */
1693 if (limit
> max_single_nop_size
)
1695 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1696 _("invalid single nop size: %d "
1697 "(expect within [0, %d])"),
1698 limit
, max_single_nop_size
);
1702 else if (fragP
->fr_type
!= rs_machine_dependent
)
1703 fragP
->fr_var
= count
;
1705 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1707 /* Generate jump over NOPs. */
1708 offsetT disp
= count
- 2;
1709 if (fits_in_imm7 (disp
))
1711 /* Use "jmp disp8" if possible. */
1713 where
[0] = jump_disp8
[0];
1719 unsigned int size_of_jump
;
1721 if (flag_code
== CODE_16BIT
)
1723 where
[0] = jump16_disp32
[0];
1724 where
[1] = jump16_disp32
[1];
1729 where
[0] = jump32_disp32
[0];
1733 count
-= size_of_jump
+ 4;
1734 if (!fits_in_imm31 (count
))
1736 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1737 _("jump over nop padding out of range"));
1741 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1742 where
+= size_of_jump
+ 4;
1746 /* Generate multiple NOPs. */
1747 i386_output_nops (where
, patt
, count
, limit
);
1751 operand_type_all_zero (const union i386_operand_type
*x
)
1753 switch (ARRAY_SIZE(x
->array
))
1764 return !x
->array
[0];
1771 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1773 switch (ARRAY_SIZE(x
->array
))
1789 x
->bitfield
.class = ClassNone
;
1790 x
->bitfield
.instance
= InstanceNone
;
1794 operand_type_equal (const union i386_operand_type
*x
,
1795 const union i386_operand_type
*y
)
1797 switch (ARRAY_SIZE(x
->array
))
1800 if (x
->array
[2] != y
->array
[2])
1804 if (x
->array
[1] != y
->array
[1])
1808 return x
->array
[0] == y
->array
[0];
1816 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1818 switch (ARRAY_SIZE(x
->array
))
1833 return !x
->array
[0];
1840 cpu_flags_equal (const union i386_cpu_flags
*x
,
1841 const union i386_cpu_flags
*y
)
1843 switch (ARRAY_SIZE(x
->array
))
1846 if (x
->array
[3] != y
->array
[3])
1850 if (x
->array
[2] != y
->array
[2])
1854 if (x
->array
[1] != y
->array
[1])
1858 return x
->array
[0] == y
->array
[0];
1866 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1868 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1869 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1872 static INLINE i386_cpu_flags
1873 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1875 switch (ARRAY_SIZE (x
.array
))
1878 x
.array
[3] &= y
.array
[3];
1881 x
.array
[2] &= y
.array
[2];
1884 x
.array
[1] &= y
.array
[1];
1887 x
.array
[0] &= y
.array
[0];
1895 static INLINE i386_cpu_flags
1896 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1898 switch (ARRAY_SIZE (x
.array
))
1901 x
.array
[3] |= y
.array
[3];
1904 x
.array
[2] |= y
.array
[2];
1907 x
.array
[1] |= y
.array
[1];
1910 x
.array
[0] |= y
.array
[0];
1918 static INLINE i386_cpu_flags
1919 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1921 switch (ARRAY_SIZE (x
.array
))
1924 x
.array
[3] &= ~y
.array
[3];
1927 x
.array
[2] &= ~y
.array
[2];
1930 x
.array
[1] &= ~y
.array
[1];
1933 x
.array
[0] &= ~y
.array
[0];
1941 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1943 #define CPU_FLAGS_ARCH_MATCH 0x1
1944 #define CPU_FLAGS_64BIT_MATCH 0x2
1946 #define CPU_FLAGS_PERFECT_MATCH \
1947 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1949 /* Return CPU flags match bits. */
1952 cpu_flags_match (const insn_template
*t
)
1954 i386_cpu_flags x
= t
->cpu_flags
;
1955 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1957 x
.bitfield
.cpu64
= 0;
1958 x
.bitfield
.cpuno64
= 0;
1960 if (cpu_flags_all_zero (&x
))
1962 /* This instruction is available on all archs. */
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 /* This instruction is available only on some archs. */
1968 i386_cpu_flags cpu
= cpu_arch_flags
;
1970 /* AVX512VL is no standalone feature - match it and then strip it. */
1971 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1973 x
.bitfield
.cpuavx512vl
= 0;
1975 cpu
= cpu_flags_and (x
, cpu
);
1976 if (!cpu_flags_all_zero (&cpu
))
1978 if (x
.bitfield
.cpuavx
)
1980 /* We need to check a few extra flags with AVX. */
1981 if (cpu
.bitfield
.cpuavx
1982 && (!t
->opcode_modifier
.sse2avx
1983 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1984 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1985 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1986 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1989 else if (x
.bitfield
.cpuavx512f
)
1991 /* We need to check a few extra flags with AVX512F. */
1992 if (cpu
.bitfield
.cpuavx512f
1993 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1994 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1995 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1996 match
|= CPU_FLAGS_ARCH_MATCH
;
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2005 static INLINE i386_operand_type
2006 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2008 if (x
.bitfield
.class != y
.bitfield
.class)
2009 x
.bitfield
.class = ClassNone
;
2010 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2011 x
.bitfield
.instance
= InstanceNone
;
2013 switch (ARRAY_SIZE (x
.array
))
2016 x
.array
[2] &= y
.array
[2];
2019 x
.array
[1] &= y
.array
[1];
2022 x
.array
[0] &= y
.array
[0];
2030 static INLINE i386_operand_type
2031 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2033 gas_assert (y
.bitfield
.class == ClassNone
);
2034 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2036 switch (ARRAY_SIZE (x
.array
))
2039 x
.array
[2] &= ~y
.array
[2];
2042 x
.array
[1] &= ~y
.array
[1];
2045 x
.array
[0] &= ~y
.array
[0];
2053 static INLINE i386_operand_type
2054 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2056 gas_assert (x
.bitfield
.class == ClassNone
||
2057 y
.bitfield
.class == ClassNone
||
2058 x
.bitfield
.class == y
.bitfield
.class);
2059 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2060 y
.bitfield
.instance
== InstanceNone
||
2061 x
.bitfield
.instance
== y
.bitfield
.instance
);
2063 switch (ARRAY_SIZE (x
.array
))
2066 x
.array
[2] |= y
.array
[2];
2069 x
.array
[1] |= y
.array
[1];
2072 x
.array
[0] |= y
.array
[0];
2080 static INLINE i386_operand_type
2081 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2083 gas_assert (y
.bitfield
.class == ClassNone
);
2084 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2086 switch (ARRAY_SIZE (x
.array
))
2089 x
.array
[2] ^= y
.array
[2];
2092 x
.array
[1] ^= y
.array
[1];
2095 x
.array
[0] ^= y
.array
[0];
2103 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2104 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2105 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2106 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2107 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2108 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2109 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2110 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2111 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2112 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2113 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2114 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2115 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2116 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2117 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2118 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2119 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2130 operand_type_check (i386_operand_type t
, enum operand_type c
)
2135 return t
.bitfield
.class == Reg
;
2138 return (t
.bitfield
.imm8
2142 || t
.bitfield
.imm32s
2143 || t
.bitfield
.imm64
);
2146 return (t
.bitfield
.disp8
2147 || t
.bitfield
.disp16
2148 || t
.bitfield
.disp32
2149 || t
.bitfield
.disp32s
2150 || t
.bitfield
.disp64
);
2153 return (t
.bitfield
.disp8
2154 || t
.bitfield
.disp16
2155 || t
.bitfield
.disp32
2156 || t
.bitfield
.disp32s
2157 || t
.bitfield
.disp64
2158 || t
.bitfield
.baseindex
);
2167 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2168 between operand GIVEN and opeand WANTED for instruction template T. */
2171 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2174 return !((i
.types
[given
].bitfield
.byte
2175 && !t
->operand_types
[wanted
].bitfield
.byte
)
2176 || (i
.types
[given
].bitfield
.word
2177 && !t
->operand_types
[wanted
].bitfield
.word
)
2178 || (i
.types
[given
].bitfield
.dword
2179 && !t
->operand_types
[wanted
].bitfield
.dword
)
2180 || (i
.types
[given
].bitfield
.qword
2181 && !t
->operand_types
[wanted
].bitfield
.qword
)
2182 || (i
.types
[given
].bitfield
.tbyte
2183 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2186 /* Return 1 if there is no conflict in SIMD register between operand
2187 GIVEN and opeand WANTED for instruction template T. */
2190 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2193 return !((i
.types
[given
].bitfield
.xmmword
2194 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2195 || (i
.types
[given
].bitfield
.ymmword
2196 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2197 || (i
.types
[given
].bitfield
.zmmword
2198 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2199 || (i
.types
[given
].bitfield
.tmmword
2200 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2203 /* Return 1 if there is no conflict in any size between operand GIVEN
2204 and opeand WANTED for instruction template T. */
2207 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2210 return (match_operand_size (t
, wanted
, given
)
2211 && !((i
.types
[given
].bitfield
.unspecified
2213 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2214 || (i
.types
[given
].bitfield
.fword
2215 && !t
->operand_types
[wanted
].bitfield
.fword
)
2216 /* For scalar opcode templates to allow register and memory
2217 operands at the same time, some special casing is needed
2218 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2219 down-conversion vpmov*. */
2220 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2221 && t
->operand_types
[wanted
].bitfield
.byte
2222 + t
->operand_types
[wanted
].bitfield
.word
2223 + t
->operand_types
[wanted
].bitfield
.dword
2224 + t
->operand_types
[wanted
].bitfield
.qword
2225 > !!t
->opcode_modifier
.broadcast
)
2226 ? (i
.types
[given
].bitfield
.xmmword
2227 || i
.types
[given
].bitfield
.ymmword
2228 || i
.types
[given
].bitfield
.zmmword
)
2229 : !match_simd_size(t
, wanted
, given
))));
2232 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2233 operands for instruction template T, and it has MATCH_REVERSE set if there
2234 is no size conflict on any operands for the template with operands reversed
2235 (and the template allows for reversing in the first place). */
2237 #define MATCH_STRAIGHT 1
2238 #define MATCH_REVERSE 2
2240 static INLINE
unsigned int
2241 operand_size_match (const insn_template
*t
)
2243 unsigned int j
, match
= MATCH_STRAIGHT
;
2245 /* Don't check non-absolute jump instructions. */
2246 if (t
->opcode_modifier
.jump
2247 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2250 /* Check memory and accumulator operand size. */
2251 for (j
= 0; j
< i
.operands
; j
++)
2253 if (i
.types
[j
].bitfield
.class != Reg
2254 && i
.types
[j
].bitfield
.class != RegSIMD
2255 && t
->opcode_modifier
.anysize
)
2258 if (t
->operand_types
[j
].bitfield
.class == Reg
2259 && !match_operand_size (t
, j
, j
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, j
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2279 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2286 if (!t
->opcode_modifier
.d
)
2290 i
.error
= operand_size_mismatch
;
2294 /* Check reverse. */
2295 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2297 for (j
= 0; j
< i
.operands
; j
++)
2299 unsigned int given
= i
.operands
- j
- 1;
2301 if (t
->operand_types
[j
].bitfield
.class == Reg
2302 && !match_operand_size (t
, j
, given
))
2305 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2306 && !match_simd_size (t
, j
, given
))
2309 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2310 && (!match_operand_size (t
, j
, given
)
2311 || !match_simd_size (t
, j
, given
)))
2314 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2318 return match
| MATCH_REVERSE
;
2322 operand_type_match (i386_operand_type overlap
,
2323 i386_operand_type given
)
2325 i386_operand_type temp
= overlap
;
2327 temp
.bitfield
.unspecified
= 0;
2328 temp
.bitfield
.byte
= 0;
2329 temp
.bitfield
.word
= 0;
2330 temp
.bitfield
.dword
= 0;
2331 temp
.bitfield
.fword
= 0;
2332 temp
.bitfield
.qword
= 0;
2333 temp
.bitfield
.tbyte
= 0;
2334 temp
.bitfield
.xmmword
= 0;
2335 temp
.bitfield
.ymmword
= 0;
2336 temp
.bitfield
.zmmword
= 0;
2337 temp
.bitfield
.tmmword
= 0;
2338 if (operand_type_all_zero (&temp
))
2341 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2345 i
.error
= operand_type_mismatch
;
2349 /* If given types g0 and g1 are registers they must be of the same type
2350 unless the expected operand type register overlap is null.
2351 Some Intel syntax memory operand size checking also happens here. */
2354 operand_type_register_match (i386_operand_type g0
,
2355 i386_operand_type t0
,
2356 i386_operand_type g1
,
2357 i386_operand_type t1
)
2359 if (g0
.bitfield
.class != Reg
2360 && g0
.bitfield
.class != RegSIMD
2361 && (!operand_type_check (g0
, anymem
)
2362 || g0
.bitfield
.unspecified
2363 || (t0
.bitfield
.class != Reg
2364 && t0
.bitfield
.class != RegSIMD
)))
2367 if (g1
.bitfield
.class != Reg
2368 && g1
.bitfield
.class != RegSIMD
2369 && (!operand_type_check (g1
, anymem
)
2370 || g1
.bitfield
.unspecified
2371 || (t1
.bitfield
.class != Reg
2372 && t1
.bitfield
.class != RegSIMD
)))
2375 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2376 && g0
.bitfield
.word
== g1
.bitfield
.word
2377 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2378 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2379 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2380 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2381 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2384 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2385 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2386 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2387 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2388 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2389 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2390 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2393 i
.error
= register_type_mismatch
;
2398 static INLINE
unsigned int
2399 register_number (const reg_entry
*r
)
2401 unsigned int nr
= r
->reg_num
;
2403 if (r
->reg_flags
& RegRex
)
2406 if (r
->reg_flags
& RegVRex
)
2412 static INLINE
unsigned int
2413 mode_from_disp_size (i386_operand_type t
)
2415 if (t
.bitfield
.disp8
)
2417 else if (t
.bitfield
.disp16
2418 || t
.bitfield
.disp32
2419 || t
.bitfield
.disp32s
)
2426 fits_in_signed_byte (addressT num
)
2428 return num
+ 0x80 <= 0xff;
2432 fits_in_unsigned_byte (addressT num
)
2438 fits_in_unsigned_word (addressT num
)
2440 return num
<= 0xffff;
2444 fits_in_signed_word (addressT num
)
2446 return num
+ 0x8000 <= 0xffff;
2450 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2455 return num
+ 0x80000000 <= 0xffffffff;
2457 } /* fits_in_signed_long() */
2460 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2465 return num
<= 0xffffffff;
2467 } /* fits_in_unsigned_long() */
2470 fits_in_disp8 (offsetT num
)
2472 int shift
= i
.memshift
;
2478 mask
= (1 << shift
) - 1;
2480 /* Return 0 if NUM isn't properly aligned. */
2484 /* Check if NUM will fit in 8bit after shift. */
2485 return fits_in_signed_byte (num
>> shift
);
2489 fits_in_imm4 (offsetT num
)
2491 return (num
& 0xf) == num
;
2494 static i386_operand_type
2495 smallest_imm_type (offsetT num
)
2497 i386_operand_type t
;
2499 operand_type_set (&t
, 0);
2500 t
.bitfield
.imm64
= 1;
2502 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2504 /* This code is disabled on the 486 because all the Imm1 forms
2505 in the opcode table are slower on the i486. They're the
2506 versions with the implicitly specified single-position
2507 displacement, which has another syntax if you really want to
2509 t
.bitfield
.imm1
= 1;
2510 t
.bitfield
.imm8
= 1;
2511 t
.bitfield
.imm8s
= 1;
2512 t
.bitfield
.imm16
= 1;
2513 t
.bitfield
.imm32
= 1;
2514 t
.bitfield
.imm32s
= 1;
2516 else if (fits_in_signed_byte (num
))
2518 t
.bitfield
.imm8
= 1;
2519 t
.bitfield
.imm8s
= 1;
2520 t
.bitfield
.imm16
= 1;
2521 t
.bitfield
.imm32
= 1;
2522 t
.bitfield
.imm32s
= 1;
2524 else if (fits_in_unsigned_byte (num
))
2526 t
.bitfield
.imm8
= 1;
2527 t
.bitfield
.imm16
= 1;
2528 t
.bitfield
.imm32
= 1;
2529 t
.bitfield
.imm32s
= 1;
2531 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2533 t
.bitfield
.imm16
= 1;
2534 t
.bitfield
.imm32
= 1;
2535 t
.bitfield
.imm32s
= 1;
2537 else if (fits_in_signed_long (num
))
2539 t
.bitfield
.imm32
= 1;
2540 t
.bitfield
.imm32s
= 1;
2542 else if (fits_in_unsigned_long (num
))
2543 t
.bitfield
.imm32
= 1;
2549 offset_in_range (offsetT val
, int size
)
2555 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2556 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2557 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2559 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2564 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2566 char buf1
[40], buf2
[40];
2568 sprint_value (buf1
, val
);
2569 sprint_value (buf2
, val
& mask
);
2570 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2585 a. PREFIX_EXIST if attempting to add a prefix where one from the
2586 same class already exists.
2587 b. PREFIX_LOCK if lock prefix is added.
2588 c. PREFIX_REP if rep/repne prefix is added.
2589 d. PREFIX_DS if ds prefix is added.
2590 e. PREFIX_OTHER if other prefix is added.
2593 static enum PREFIX_GROUP
2594 add_prefix (unsigned int prefix
)
2596 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2599 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2600 && flag_code
== CODE_64BIT
)
2602 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2603 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2604 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2605 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2616 case DS_PREFIX_OPCODE
:
2619 case CS_PREFIX_OPCODE
:
2620 case ES_PREFIX_OPCODE
:
2621 case FS_PREFIX_OPCODE
:
2622 case GS_PREFIX_OPCODE
:
2623 case SS_PREFIX_OPCODE
:
2627 case REPNE_PREFIX_OPCODE
:
2628 case REPE_PREFIX_OPCODE
:
2633 case LOCK_PREFIX_OPCODE
:
2642 case ADDR_PREFIX_OPCODE
:
2646 case DATA_PREFIX_OPCODE
:
2650 if (i
.prefix
[q
] != 0)
2658 i
.prefix
[q
] |= prefix
;
2661 as_bad (_("same type of prefix used twice"));
2667 update_code_flag (int value
, int check
)
2669 PRINTF_LIKE ((*as_error
));
2671 flag_code
= (enum flag_code
) value
;
2672 if (flag_code
== CODE_64BIT
)
2674 cpu_arch_flags
.bitfield
.cpu64
= 1;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2679 cpu_arch_flags
.bitfield
.cpu64
= 0;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2682 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2685 as_error
= as_fatal
;
2688 (*as_error
) (_("64bit mode not supported on `%s'."),
2689 cpu_arch_name
? cpu_arch_name
: default_arch
);
2691 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2694 as_error
= as_fatal
;
2697 (*as_error
) (_("32bit mode not supported on `%s'."),
2698 cpu_arch_name
? cpu_arch_name
: default_arch
);
2700 stackop_size
= '\0';
2704 set_code_flag (int value
)
2706 update_code_flag (value
, 0);
2710 set_16bit_gcc_code_flag (int new_code_flag
)
2712 flag_code
= (enum flag_code
) new_code_flag
;
2713 if (flag_code
!= CODE_16BIT
)
2715 cpu_arch_flags
.bitfield
.cpu64
= 0;
2716 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2717 stackop_size
= LONG_MNEM_SUFFIX
;
2721 set_intel_syntax (int syntax_flag
)
2723 /* Find out if register prefixing is specified. */
2724 int ask_naked_reg
= 0;
2727 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2730 int e
= get_symbol_name (&string
);
2732 if (strcmp (string
, "prefix") == 0)
2734 else if (strcmp (string
, "noprefix") == 0)
2737 as_bad (_("bad argument to syntax directive."));
2738 (void) restore_line_pointer (e
);
2740 demand_empty_rest_of_line ();
2742 intel_syntax
= syntax_flag
;
2744 if (ask_naked_reg
== 0)
2745 allow_naked_reg
= (intel_syntax
2746 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2748 allow_naked_reg
= (ask_naked_reg
< 0);
2750 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2752 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2753 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2754 register_prefix
= allow_naked_reg
? "" : "%";
2758 set_intel_mnemonic (int mnemonic_flag
)
2760 intel_mnemonic
= mnemonic_flag
;
2764 set_allow_index_reg (int flag
)
2766 allow_index_reg
= flag
;
2770 set_check (int what
)
2772 enum check_kind
*kind
;
2777 kind
= &operand_check
;
2788 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2791 int e
= get_symbol_name (&string
);
2793 if (strcmp (string
, "none") == 0)
2795 else if (strcmp (string
, "warning") == 0)
2796 *kind
= check_warning
;
2797 else if (strcmp (string
, "error") == 0)
2798 *kind
= check_error
;
2800 as_bad (_("bad argument to %s_check directive."), str
);
2801 (void) restore_line_pointer (e
);
2804 as_bad (_("missing argument for %s_check directive"), str
);
2806 demand_empty_rest_of_line ();
2810 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2811 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2814 static const char *arch
;
2816 /* Intel LIOM is only supported on ELF. */
2822 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2823 use default_arch. */
2824 arch
= cpu_arch_name
;
2826 arch
= default_arch
;
2829 /* If we are targeting Intel MCU, we must enable it. */
2830 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2831 || new_flag
.bitfield
.cpuiamcu
)
2834 /* If we are targeting Intel L1OM, we must enable it. */
2835 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2836 || new_flag
.bitfield
.cpul1om
)
2839 /* If we are targeting Intel K1OM, we must enable it. */
2840 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2841 || new_flag
.bitfield
.cpuk1om
)
2844 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2849 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2853 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2856 int e
= get_symbol_name (&string
);
2858 i386_cpu_flags flags
;
2860 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2862 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2864 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2868 cpu_arch_name
= cpu_arch
[j
].name
;
2869 cpu_sub_arch_name
= NULL
;
2870 cpu_arch_flags
= cpu_arch
[j
].flags
;
2871 if (flag_code
== CODE_64BIT
)
2873 cpu_arch_flags
.bitfield
.cpu64
= 1;
2874 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2878 cpu_arch_flags
.bitfield
.cpu64
= 0;
2879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2881 cpu_arch_isa
= cpu_arch
[j
].type
;
2882 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2883 if (!cpu_arch_tune_set
)
2885 cpu_arch_tune
= cpu_arch_isa
;
2886 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2891 flags
= cpu_flags_or (cpu_arch_flags
,
2894 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2896 if (cpu_sub_arch_name
)
2898 char *name
= cpu_sub_arch_name
;
2899 cpu_sub_arch_name
= concat (name
,
2901 (const char *) NULL
);
2905 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2906 cpu_arch_flags
= flags
;
2907 cpu_arch_isa_flags
= flags
;
2911 = cpu_flags_or (cpu_arch_isa_flags
,
2913 (void) restore_line_pointer (e
);
2914 demand_empty_rest_of_line ();
2919 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2921 /* Disable an ISA extension. */
2922 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2923 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2925 flags
= cpu_flags_and_not (cpu_arch_flags
,
2926 cpu_noarch
[j
].flags
);
2927 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2929 if (cpu_sub_arch_name
)
2931 char *name
= cpu_sub_arch_name
;
2932 cpu_sub_arch_name
= concat (name
, string
,
2933 (const char *) NULL
);
2937 cpu_sub_arch_name
= xstrdup (string
);
2938 cpu_arch_flags
= flags
;
2939 cpu_arch_isa_flags
= flags
;
2941 (void) restore_line_pointer (e
);
2942 demand_empty_rest_of_line ();
2946 j
= ARRAY_SIZE (cpu_arch
);
2949 if (j
>= ARRAY_SIZE (cpu_arch
))
2950 as_bad (_("no such architecture: `%s'"), string
);
2952 *input_line_pointer
= e
;
2955 as_bad (_("missing cpu architecture"));
2957 no_cond_jump_promotion
= 0;
2958 if (*input_line_pointer
== ','
2959 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2964 ++input_line_pointer
;
2965 e
= get_symbol_name (&string
);
2967 if (strcmp (string
, "nojumps") == 0)
2968 no_cond_jump_promotion
= 1;
2969 else if (strcmp (string
, "jumps") == 0)
2972 as_bad (_("no such architecture modifier: `%s'"), string
);
2974 (void) restore_line_pointer (e
);
2977 demand_empty_rest_of_line ();
2980 enum bfd_architecture
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || flag_code
!= CODE_64BIT
)
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_arch_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || flag_code
!= CODE_64BIT
)
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_arch_k1om
;
2997 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2999 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3000 || flag_code
== CODE_64BIT
)
3001 as_fatal (_("Intel MCU is 32bit ELF only"));
3002 return bfd_arch_iamcu
;
3005 return bfd_arch_i386
;
3011 if (!strncmp (default_arch
, "x86_64", 6))
3013 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3016 || default_arch
[6] != '\0')
3017 as_fatal (_("Intel L1OM is 64bit ELF only"));
3018 return bfd_mach_l1om
;
3020 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3022 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3023 || default_arch
[6] != '\0')
3024 as_fatal (_("Intel K1OM is 64bit ELF only"));
3025 return bfd_mach_k1om
;
3027 else if (default_arch
[6] == '\0')
3028 return bfd_mach_x86_64
;
3030 return bfd_mach_x64_32
;
3032 else if (!strcmp (default_arch
, "i386")
3033 || !strcmp (default_arch
, "iamcu"))
3035 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3037 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3038 as_fatal (_("Intel MCU is 32bit ELF only"));
3039 return bfd_mach_i386_iamcu
;
3042 return bfd_mach_i386_i386
;
3045 as_fatal (_("unknown architecture"));
3051 /* Support pseudo prefixes like {disp32}. */
3052 lex_type
['{'] = LEX_BEGIN_NAME
;
3054 /* Initialize op_hash hash table. */
3055 op_hash
= str_htab_create ();
3058 const insn_template
*optab
;
3059 templates
*core_optab
;
3061 /* Setup for loop. */
3063 core_optab
= XNEW (templates
);
3064 core_optab
->start
= optab
;
3069 if (optab
->name
== NULL
3070 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3072 /* different name --> ship out current template list;
3073 add to hash table; & begin anew. */
3074 core_optab
->end
= optab
;
3075 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3076 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3078 if (optab
->name
== NULL
)
3080 core_optab
= XNEW (templates
);
3081 core_optab
->start
= optab
;
3086 /* Initialize reg_hash hash table. */
3087 reg_hash
= str_htab_create ();
3089 const reg_entry
*regtab
;
3090 unsigned int regtab_size
= i386_regtab_size
;
3092 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3093 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3094 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3097 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3102 for (c
= 0; c
< 256; c
++)
3107 mnemonic_chars
[c
] = c
;
3108 register_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3111 else if (ISLOWER (c
))
3113 mnemonic_chars
[c
] = c
;
3114 register_chars
[c
] = c
;
3115 operand_chars
[c
] = c
;
3117 else if (ISUPPER (c
))
3119 mnemonic_chars
[c
] = TOLOWER (c
);
3120 register_chars
[c
] = mnemonic_chars
[c
];
3121 operand_chars
[c
] = c
;
3123 else if (c
== '{' || c
== '}')
3125 mnemonic_chars
[c
] = c
;
3126 operand_chars
[c
] = c
;
3128 #ifdef SVR4_COMMENT_CHARS
3129 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3130 operand_chars
[c
] = c
;
3133 if (ISALPHA (c
) || ISDIGIT (c
))
3134 identifier_chars
[c
] = c
;
3137 identifier_chars
[c
] = c
;
3138 operand_chars
[c
] = c
;
3143 identifier_chars
['@'] = '@';
3146 identifier_chars
['?'] = '?';
3147 operand_chars
['?'] = '?';
3149 digit_chars
['-'] = '-';
3150 mnemonic_chars
['_'] = '_';
3151 mnemonic_chars
['-'] = '-';
3152 mnemonic_chars
['.'] = '.';
3153 identifier_chars
['_'] = '_';
3154 identifier_chars
['.'] = '.';
3156 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3157 operand_chars
[(unsigned char) *p
] = *p
;
3160 if (flag_code
== CODE_64BIT
)
3162 #if defined (OBJ_COFF) && defined (TE_PE)
3163 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3166 x86_dwarf2_return_column
= 16;
3168 x86_cie_data_alignment
= -8;
3172 x86_dwarf2_return_column
= 8;
3173 x86_cie_data_alignment
= -4;
3176 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3177 can be turned into BRANCH_PREFIX frag. */
3178 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3183 i386_print_statistics (FILE *file
)
3185 htab_print_statistics (file
, "i386 opcode", op_hash
);
3186 htab_print_statistics (file
, "i386 register", reg_hash
);
3191 /* Debugging routines for md_assemble. */
3192 static void pte (insn_template
*);
3193 static void pt (i386_operand_type
);
3194 static void pe (expressionS
*);
3195 static void ps (symbolS
*);
3198 pi (const char *line
, i386_insn
*x
)
3202 fprintf (stdout
, "%s: template ", line
);
3204 fprintf (stdout
, " address: base %s index %s scale %x\n",
3205 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3206 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3207 x
->log2_scale_factor
);
3208 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3209 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3210 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3211 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3212 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3213 (x
->rex
& REX_W
) != 0,
3214 (x
->rex
& REX_R
) != 0,
3215 (x
->rex
& REX_X
) != 0,
3216 (x
->rex
& REX_B
) != 0);
3217 for (j
= 0; j
< x
->operands
; j
++)
3219 fprintf (stdout
, " #%d: ", j
+ 1);
3221 fprintf (stdout
, "\n");
3222 if (x
->types
[j
].bitfield
.class == Reg
3223 || x
->types
[j
].bitfield
.class == RegMMX
3224 || x
->types
[j
].bitfield
.class == RegSIMD
3225 || x
->types
[j
].bitfield
.class == RegMask
3226 || x
->types
[j
].bitfield
.class == SReg
3227 || x
->types
[j
].bitfield
.class == RegCR
3228 || x
->types
[j
].bitfield
.class == RegDR
3229 || x
->types
[j
].bitfield
.class == RegTR
3230 || x
->types
[j
].bitfield
.class == RegBND
)
3231 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3232 if (operand_type_check (x
->types
[j
], imm
))
3234 if (operand_type_check (x
->types
[j
], disp
))
3235 pe (x
->op
[j
].disps
);
3240 pte (insn_template
*t
)
3243 fprintf (stdout
, " %d operands ", t
->operands
);
3244 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3245 if (t
->extension_opcode
!= None
)
3246 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3247 if (t
->opcode_modifier
.d
)
3248 fprintf (stdout
, "D");
3249 if (t
->opcode_modifier
.w
)
3250 fprintf (stdout
, "W");
3251 fprintf (stdout
, "\n");
3252 for (j
= 0; j
< t
->operands
; j
++)
3254 fprintf (stdout
, " #%d type ", j
+ 1);
3255 pt (t
->operand_types
[j
]);
3256 fprintf (stdout
, "\n");
3263 fprintf (stdout
, " operation %d\n", e
->X_op
);
3264 fprintf (stdout
, " add_number %ld (%lx)\n",
3265 (long) e
->X_add_number
, (long) e
->X_add_number
);
3266 if (e
->X_add_symbol
)
3268 fprintf (stdout
, " add_symbol ");
3269 ps (e
->X_add_symbol
);
3270 fprintf (stdout
, "\n");
3274 fprintf (stdout
, " op_symbol ");
3275 ps (e
->X_op_symbol
);
3276 fprintf (stdout
, "\n");
3283 fprintf (stdout
, "%s type %s%s",
3285 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3286 segment_name (S_GET_SEGMENT (s
)));
3289 static struct type_name
3291 i386_operand_type mask
;
3294 const type_names
[] =
3296 { OPERAND_TYPE_REG8
, "r8" },
3297 { OPERAND_TYPE_REG16
, "r16" },
3298 { OPERAND_TYPE_REG32
, "r32" },
3299 { OPERAND_TYPE_REG64
, "r64" },
3300 { OPERAND_TYPE_ACC8
, "acc8" },
3301 { OPERAND_TYPE_ACC16
, "acc16" },
3302 { OPERAND_TYPE_ACC32
, "acc32" },
3303 { OPERAND_TYPE_ACC64
, "acc64" },
3304 { OPERAND_TYPE_IMM8
, "i8" },
3305 { OPERAND_TYPE_IMM8
, "i8s" },
3306 { OPERAND_TYPE_IMM16
, "i16" },
3307 { OPERAND_TYPE_IMM32
, "i32" },
3308 { OPERAND_TYPE_IMM32S
, "i32s" },
3309 { OPERAND_TYPE_IMM64
, "i64" },
3310 { OPERAND_TYPE_IMM1
, "i1" },
3311 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3312 { OPERAND_TYPE_DISP8
, "d8" },
3313 { OPERAND_TYPE_DISP16
, "d16" },
3314 { OPERAND_TYPE_DISP32
, "d32" },
3315 { OPERAND_TYPE_DISP32S
, "d32s" },
3316 { OPERAND_TYPE_DISP64
, "d64" },
3317 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3318 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3319 { OPERAND_TYPE_CONTROL
, "control reg" },
3320 { OPERAND_TYPE_TEST
, "test reg" },
3321 { OPERAND_TYPE_DEBUG
, "debug reg" },
3322 { OPERAND_TYPE_FLOATREG
, "FReg" },
3323 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3324 { OPERAND_TYPE_SREG
, "SReg" },
3325 { OPERAND_TYPE_REGMMX
, "rMMX" },
3326 { OPERAND_TYPE_REGXMM
, "rXMM" },
3327 { OPERAND_TYPE_REGYMM
, "rYMM" },
3328 { OPERAND_TYPE_REGZMM
, "rZMM" },
3329 { OPERAND_TYPE_REGTMM
, "rTMM" },
3330 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3334 pt (i386_operand_type t
)
3337 i386_operand_type a
;
3339 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3341 a
= operand_type_and (t
, type_names
[j
].mask
);
3342 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3343 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3348 #endif /* DEBUG386 */
3350 static bfd_reloc_code_real_type
3351 reloc (unsigned int size
,
3354 bfd_reloc_code_real_type other
)
3356 if (other
!= NO_RELOC
)
3358 reloc_howto_type
*rel
;
3363 case BFD_RELOC_X86_64_GOT32
:
3364 return BFD_RELOC_X86_64_GOT64
;
3366 case BFD_RELOC_X86_64_GOTPLT64
:
3367 return BFD_RELOC_X86_64_GOTPLT64
;
3369 case BFD_RELOC_X86_64_PLTOFF64
:
3370 return BFD_RELOC_X86_64_PLTOFF64
;
3372 case BFD_RELOC_X86_64_GOTPC32
:
3373 other
= BFD_RELOC_X86_64_GOTPC64
;
3375 case BFD_RELOC_X86_64_GOTPCREL
:
3376 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3378 case BFD_RELOC_X86_64_TPOFF32
:
3379 other
= BFD_RELOC_X86_64_TPOFF64
;
3381 case BFD_RELOC_X86_64_DTPOFF32
:
3382 other
= BFD_RELOC_X86_64_DTPOFF64
;
3388 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3389 if (other
== BFD_RELOC_SIZE32
)
3392 other
= BFD_RELOC_SIZE64
;
3395 as_bad (_("there are no pc-relative size relocations"));
3401 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3402 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3405 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3407 as_bad (_("unknown relocation (%u)"), other
);
3408 else if (size
!= bfd_get_reloc_size (rel
))
3409 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3410 bfd_get_reloc_size (rel
),
3412 else if (pcrel
&& !rel
->pc_relative
)
3413 as_bad (_("non-pc-relative relocation for pc-relative field"));
3414 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3416 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3418 as_bad (_("relocated field and relocation type differ in signedness"));
3427 as_bad (_("there are no unsigned pc-relative relocations"));
3430 case 1: return BFD_RELOC_8_PCREL
;
3431 case 2: return BFD_RELOC_16_PCREL
;
3432 case 4: return BFD_RELOC_32_PCREL
;
3433 case 8: return BFD_RELOC_64_PCREL
;
3435 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3442 case 4: return BFD_RELOC_X86_64_32S
;
3447 case 1: return BFD_RELOC_8
;
3448 case 2: return BFD_RELOC_16
;
3449 case 4: return BFD_RELOC_32
;
3450 case 8: return BFD_RELOC_64
;
3452 as_bad (_("cannot do %s %u byte relocation"),
3453 sign
> 0 ? "signed" : "unsigned", size
);
3459 /* Here we decide which fixups can be adjusted to make them relative to
3460 the beginning of the section instead of the symbol. Basically we need
3461 to make sure that the dynamic relocations are done correctly, so in
3462 some cases we force the original symbol to be used. */
3465 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3467 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3471 /* Don't adjust pc-relative references to merge sections in 64-bit
3473 if (use_rela_relocations
3474 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3478 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3479 and changed later by validate_fix. */
3480 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3481 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3484 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3485 for size relocations. */
3486 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3487 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3488 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3489 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3490 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3492 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3493 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3494 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3495 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3496 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3497 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3498 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3499 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3500 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3506 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3507 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3508 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3509 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3510 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3511 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3512 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3513 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3515 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3516 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3523 intel_float_operand (const char *mnemonic
)
3525 /* Note that the value returned is meaningful only for opcodes with (memory)
3526 operands, hence the code here is free to improperly handle opcodes that
3527 have no operands (for better performance and smaller code). */
3529 if (mnemonic
[0] != 'f')
3530 return 0; /* non-math */
3532 switch (mnemonic
[1])
3534 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3535 the fs segment override prefix not currently handled because no
3536 call path can make opcodes without operands get here */
3538 return 2 /* integer op */;
3540 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3541 return 3; /* fldcw/fldenv */
3544 if (mnemonic
[2] != 'o' /* fnop */)
3545 return 3; /* non-waiting control op */
3548 if (mnemonic
[2] == 's')
3549 return 3; /* frstor/frstpm */
3552 if (mnemonic
[2] == 'a')
3553 return 3; /* fsave */
3554 if (mnemonic
[2] == 't')
3556 switch (mnemonic
[3])
3558 case 'c': /* fstcw */
3559 case 'd': /* fstdw */
3560 case 'e': /* fstenv */
3561 case 's': /* fsts[gw] */
3567 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3568 return 0; /* fxsave/fxrstor are not really math ops */
3575 /* Build the VEX prefix. */
3578 build_vex_prefix (const insn_template
*t
)
3580 unsigned int register_specifier
;
3581 unsigned int implied_prefix
;
3582 unsigned int vector_length
;
3585 /* Check register specifier. */
3586 if (i
.vex
.register_specifier
)
3588 register_specifier
=
3589 ~register_number (i
.vex
.register_specifier
) & 0xf;
3590 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3593 register_specifier
= 0xf;
3595 /* Use 2-byte VEX prefix by swapping destination and source operand
3596 if there are more than 1 register operand. */
3597 if (i
.reg_operands
> 1
3598 && i
.vec_encoding
!= vex_encoding_vex3
3599 && i
.dir_encoding
== dir_encoding_default
3600 && i
.operands
== i
.reg_operands
3601 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3602 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3603 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3606 unsigned int xchg
= i
.operands
- 1;
3607 union i386_op temp_op
;
3608 i386_operand_type temp_type
;
3610 temp_type
= i
.types
[xchg
];
3611 i
.types
[xchg
] = i
.types
[0];
3612 i
.types
[0] = temp_type
;
3613 temp_op
= i
.op
[xchg
];
3614 i
.op
[xchg
] = i
.op
[0];
3617 gas_assert (i
.rm
.mode
== 3);
3621 i
.rm
.regmem
= i
.rm
.reg
;
3624 if (i
.tm
.opcode_modifier
.d
)
3625 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3626 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3627 else /* Use the next insn. */
3631 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3632 are no memory operands and at least 3 register ones. */
3633 if (i
.reg_operands
>= 3
3634 && i
.vec_encoding
!= vex_encoding_vex3
3635 && i
.reg_operands
== i
.operands
- i
.imm_operands
3636 && i
.tm
.opcode_modifier
.vex
3637 && i
.tm
.opcode_modifier
.commutative
3638 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3640 && i
.vex
.register_specifier
3641 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3643 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3644 union i386_op temp_op
;
3645 i386_operand_type temp_type
;
3647 gas_assert (i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
);
3648 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3649 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3650 &i
.types
[i
.operands
- 3]));
3651 gas_assert (i
.rm
.mode
== 3);
3653 temp_type
= i
.types
[xchg
];
3654 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3655 i
.types
[xchg
+ 1] = temp_type
;
3656 temp_op
= i
.op
[xchg
];
3657 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3658 i
.op
[xchg
+ 1] = temp_op
;
3661 xchg
= i
.rm
.regmem
| 8;
3662 i
.rm
.regmem
= ~register_specifier
& 0xf;
3663 gas_assert (!(i
.rm
.regmem
& 8));
3664 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3665 register_specifier
= ~xchg
& 0xf;
3668 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3669 vector_length
= avxscalar
;
3670 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3676 /* Determine vector length from the last multi-length vector
3679 for (op
= t
->operands
; op
--;)
3680 if (t
->operand_types
[op
].bitfield
.xmmword
3681 && t
->operand_types
[op
].bitfield
.ymmword
3682 && i
.types
[op
].bitfield
.ymmword
)
3689 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3694 case DATA_PREFIX_OPCODE
:
3697 case REPE_PREFIX_OPCODE
:
3700 case REPNE_PREFIX_OPCODE
:
3707 /* Check the REX.W bit and VEXW. */
3708 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3709 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3710 else if (i
.tm
.opcode_modifier
.vexw
)
3711 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3713 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3715 /* Use 2-byte VEX prefix if possible. */
3717 && i
.vec_encoding
!= vex_encoding_vex3
3718 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3719 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3721 /* 2-byte VEX prefix. */
3725 i
.vex
.bytes
[0] = 0xc5;
3727 /* Check the REX.R bit. */
3728 r
= (i
.rex
& REX_R
) ? 0 : 1;
3729 i
.vex
.bytes
[1] = (r
<< 7
3730 | register_specifier
<< 3
3731 | vector_length
<< 2
3736 /* 3-byte VEX prefix. */
3741 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3745 i
.vex
.bytes
[0] = 0xc4;
3749 i
.vex
.bytes
[0] = 0xc4;
3753 i
.vex
.bytes
[0] = 0xc4;
3757 i
.vex
.bytes
[0] = 0x8f;
3761 i
.vex
.bytes
[0] = 0x8f;
3765 i
.vex
.bytes
[0] = 0x8f;
3771 /* The high 3 bits of the second VEX byte are 1's compliment
3772 of RXB bits from REX. */
3773 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3775 i
.vex
.bytes
[2] = (w
<< 7
3776 | register_specifier
<< 3
3777 | vector_length
<< 2
3782 static INLINE bfd_boolean
3783 is_evex_encoding (const insn_template
*t
)
3785 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3786 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3787 || t
->opcode_modifier
.sae
;
3790 static INLINE bfd_boolean
3791 is_any_vex_encoding (const insn_template
*t
)
3793 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3796 /* Build the EVEX prefix. */
3799 build_evex_prefix (void)
3801 unsigned int register_specifier
;
3802 unsigned int implied_prefix
;
3804 rex_byte vrex_used
= 0;
3806 /* Check register specifier. */
3807 if (i
.vex
.register_specifier
)
3809 gas_assert ((i
.vrex
& REX_X
) == 0);
3811 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3812 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3813 register_specifier
+= 8;
3814 /* The upper 16 registers are encoded in the fourth byte of the
3816 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3817 i
.vex
.bytes
[3] = 0x8;
3818 register_specifier
= ~register_specifier
& 0xf;
3822 register_specifier
= 0xf;
3824 /* Encode upper 16 vector index register in the fourth byte of
3826 if (!(i
.vrex
& REX_X
))
3827 i
.vex
.bytes
[3] = 0x8;
3832 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3837 case DATA_PREFIX_OPCODE
:
3840 case REPE_PREFIX_OPCODE
:
3843 case REPNE_PREFIX_OPCODE
:
3850 /* 4 byte EVEX prefix. */
3852 i
.vex
.bytes
[0] = 0x62;
3855 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3871 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3873 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3875 /* The fifth bit of the second EVEX byte is 1's compliment of the
3876 REX_R bit in VREX. */
3877 if (!(i
.vrex
& REX_R
))
3878 i
.vex
.bytes
[1] |= 0x10;
3882 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3884 /* When all operands are registers, the REX_X bit in REX is not
3885 used. We reuse it to encode the upper 16 registers, which is
3886 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3887 as 1's compliment. */
3888 if ((i
.vrex
& REX_B
))
3891 i
.vex
.bytes
[1] &= ~0x40;
3895 /* EVEX instructions shouldn't need the REX prefix. */
3896 i
.vrex
&= ~vrex_used
;
3897 gas_assert (i
.vrex
== 0);
3899 /* Check the REX.W bit and VEXW. */
3900 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3901 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3902 else if (i
.tm
.opcode_modifier
.vexw
)
3903 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3905 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3907 /* Encode the U bit. */
3908 implied_prefix
|= 0x4;
3910 /* The third byte of the EVEX prefix. */
3911 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3913 /* The fourth byte of the EVEX prefix. */
3914 /* The zeroing-masking bit. */
3915 if (i
.mask
&& i
.mask
->zeroing
)
3916 i
.vex
.bytes
[3] |= 0x80;
3918 /* Don't always set the broadcast bit if there is no RC. */
3921 /* Encode the vector length. */
3922 unsigned int vec_length
;
3924 if (!i
.tm
.opcode_modifier
.evex
3925 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3929 /* Determine vector length from the last multi-length vector
3931 for (op
= i
.operands
; op
--;)
3932 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3933 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3934 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3936 if (i
.types
[op
].bitfield
.zmmword
)
3938 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3941 else if (i
.types
[op
].bitfield
.ymmword
)
3943 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3946 else if (i
.types
[op
].bitfield
.xmmword
)
3948 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3951 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3953 switch (i
.broadcast
->bytes
)
3956 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3959 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3962 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3971 if (op
>= MAX_OPERANDS
)
3975 switch (i
.tm
.opcode_modifier
.evex
)
3977 case EVEXLIG
: /* LL' is ignored */
3978 vec_length
= evexlig
<< 5;
3981 vec_length
= 0 << 5;
3984 vec_length
= 1 << 5;
3987 vec_length
= 2 << 5;
3993 i
.vex
.bytes
[3] |= vec_length
;
3994 /* Encode the broadcast bit. */
3996 i
.vex
.bytes
[3] |= 0x10;
4000 if (i
.rounding
->type
!= saeonly
)
4001 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
4003 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4006 if (i
.mask
&& i
.mask
->mask
)
4007 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4011 process_immext (void)
4015 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4016 which is coded in the same place as an 8-bit immediate field
4017 would be. Here we fake an 8-bit immediate operand from the
4018 opcode suffix stored in tm.extension_opcode.
4020 AVX instructions also use this encoding, for some of
4021 3 argument instructions. */
4023 gas_assert (i
.imm_operands
<= 1
4025 || (is_any_vex_encoding (&i
.tm
)
4026 && i
.operands
<= 4)));
4028 exp
= &im_expressions
[i
.imm_operands
++];
4029 i
.op
[i
.operands
].imms
= exp
;
4030 i
.types
[i
.operands
] = imm8
;
4032 exp
->X_op
= O_constant
;
4033 exp
->X_add_number
= i
.tm
.extension_opcode
;
4034 i
.tm
.extension_opcode
= None
;
4041 switch (i
.tm
.opcode_modifier
.prefixok
)
4049 as_bad (_("invalid instruction `%s' after `%s'"),
4050 i
.tm
.name
, i
.hle_prefix
);
4053 if (i
.prefix
[LOCK_PREFIX
])
4055 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4059 case PrefixHLERelease
:
4060 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4062 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4066 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4068 as_bad (_("memory destination needed for instruction `%s'"
4069 " after `xrelease'"), i
.tm
.name
);
4076 /* Try the shortest encoding by shortening operand size. */
4079 optimize_encoding (void)
4083 if (optimize_for_space
4084 && !is_any_vex_encoding (&i
.tm
)
4085 && i
.reg_operands
== 1
4086 && i
.imm_operands
== 1
4087 && !i
.types
[1].bitfield
.byte
4088 && i
.op
[0].imms
->X_op
== O_constant
4089 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4090 && (i
.tm
.base_opcode
== 0xa8
4091 || (i
.tm
.base_opcode
== 0xf6
4092 && i
.tm
.extension_opcode
== 0x0)))
4095 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4097 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4098 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4100 i
.types
[1].bitfield
.byte
= 1;
4101 /* Ignore the suffix. */
4103 /* Convert to byte registers. */
4104 if (i
.types
[1].bitfield
.word
)
4106 else if (i
.types
[1].bitfield
.dword
)
4110 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4115 else if (flag_code
== CODE_64BIT
4116 && !is_any_vex_encoding (&i
.tm
)
4117 && ((i
.types
[1].bitfield
.qword
4118 && i
.reg_operands
== 1
4119 && i
.imm_operands
== 1
4120 && i
.op
[0].imms
->X_op
== O_constant
4121 && ((i
.tm
.base_opcode
== 0xb8
4122 && i
.tm
.extension_opcode
== None
4123 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4124 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4125 && ((i
.tm
.base_opcode
== 0x24
4126 || i
.tm
.base_opcode
== 0xa8)
4127 || (i
.tm
.base_opcode
== 0x80
4128 && i
.tm
.extension_opcode
== 0x4)
4129 || ((i
.tm
.base_opcode
== 0xf6
4130 || (i
.tm
.base_opcode
| 1) == 0xc7)
4131 && i
.tm
.extension_opcode
== 0x0)))
4132 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4133 && i
.tm
.base_opcode
== 0x83
4134 && i
.tm
.extension_opcode
== 0x4)))
4135 || (i
.types
[0].bitfield
.qword
4136 && ((i
.reg_operands
== 2
4137 && i
.op
[0].regs
== i
.op
[1].regs
4138 && (i
.tm
.base_opcode
== 0x30
4139 || i
.tm
.base_opcode
== 0x28))
4140 || (i
.reg_operands
== 1
4142 && i
.tm
.base_opcode
== 0x30)))))
4145 andq $imm31, %r64 -> andl $imm31, %r32
4146 andq $imm7, %r64 -> andl $imm7, %r32
4147 testq $imm31, %r64 -> testl $imm31, %r32
4148 xorq %r64, %r64 -> xorl %r32, %r32
4149 subq %r64, %r64 -> subl %r32, %r32
4150 movq $imm31, %r64 -> movl $imm31, %r32
4151 movq $imm32, %r64 -> movl $imm32, %r32
4153 i
.tm
.opcode_modifier
.norex64
= 1;
4154 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4157 movq $imm31, %r64 -> movl $imm31, %r32
4158 movq $imm32, %r64 -> movl $imm32, %r32
4160 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4161 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4162 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4163 i
.types
[0].bitfield
.imm32
= 1;
4164 i
.types
[0].bitfield
.imm32s
= 0;
4165 i
.types
[0].bitfield
.imm64
= 0;
4166 i
.types
[1].bitfield
.dword
= 1;
4167 i
.types
[1].bitfield
.qword
= 0;
4168 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4171 movq $imm31, %r64 -> movl $imm31, %r32
4173 i
.tm
.base_opcode
= 0xb8;
4174 i
.tm
.extension_opcode
= None
;
4175 i
.tm
.opcode_modifier
.w
= 0;
4176 i
.tm
.opcode_modifier
.modrm
= 0;
4180 else if (optimize
> 1
4181 && !optimize_for_space
4182 && !is_any_vex_encoding (&i
.tm
)
4183 && i
.reg_operands
== 2
4184 && i
.op
[0].regs
== i
.op
[1].regs
4185 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4186 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4187 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4190 andb %rN, %rN -> testb %rN, %rN
4191 andw %rN, %rN -> testw %rN, %rN
4192 andq %rN, %rN -> testq %rN, %rN
4193 orb %rN, %rN -> testb %rN, %rN
4194 orw %rN, %rN -> testw %rN, %rN
4195 orq %rN, %rN -> testq %rN, %rN
4197 and outside of 64-bit mode
4199 andl %rN, %rN -> testl %rN, %rN
4200 orl %rN, %rN -> testl %rN, %rN
4202 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4204 else if (i
.reg_operands
== 3
4205 && i
.op
[0].regs
== i
.op
[1].regs
4206 && !i
.types
[2].bitfield
.xmmword
4207 && (i
.tm
.opcode_modifier
.vex
4208 || ((!i
.mask
|| i
.mask
->zeroing
)
4210 && is_evex_encoding (&i
.tm
)
4211 && (i
.vec_encoding
!= vex_encoding_evex
4212 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4213 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4214 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4215 && i
.types
[2].bitfield
.ymmword
))))
4216 && ((i
.tm
.base_opcode
== 0x55
4217 || i
.tm
.base_opcode
== 0x6655
4218 || i
.tm
.base_opcode
== 0x66df
4219 || i
.tm
.base_opcode
== 0x57
4220 || i
.tm
.base_opcode
== 0x6657
4221 || i
.tm
.base_opcode
== 0x66ef
4222 || i
.tm
.base_opcode
== 0x66f8
4223 || i
.tm
.base_opcode
== 0x66f9
4224 || i
.tm
.base_opcode
== 0x66fa
4225 || i
.tm
.base_opcode
== 0x66fb
4226 || i
.tm
.base_opcode
== 0x42
4227 || i
.tm
.base_opcode
== 0x6642
4228 || i
.tm
.base_opcode
== 0x47
4229 || i
.tm
.base_opcode
== 0x6647)
4230 && i
.tm
.extension_opcode
== None
))
4233 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4235 EVEX VOP %zmmM, %zmmM, %zmmN
4236 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4237 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4238 EVEX VOP %ymmM, %ymmM, %ymmN
4239 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4240 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4241 VEX VOP %ymmM, %ymmM, %ymmN
4242 -> VEX VOP %xmmM, %xmmM, %xmmN
4243 VOP, one of vpandn and vpxor:
4244 VEX VOP %ymmM, %ymmM, %ymmN
4245 -> VEX VOP %xmmM, %xmmM, %xmmN
4246 VOP, one of vpandnd and vpandnq:
4247 EVEX VOP %zmmM, %zmmM, %zmmN
4248 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4249 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4250 EVEX VOP %ymmM, %ymmM, %ymmN
4251 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4252 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4253 VOP, one of vpxord and vpxorq:
4254 EVEX VOP %zmmM, %zmmM, %zmmN
4255 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4256 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4257 EVEX VOP %ymmM, %ymmM, %ymmN
4258 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4259 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4260 VOP, one of kxord and kxorq:
4261 VEX VOP %kM, %kM, %kN
4262 -> VEX kxorw %kM, %kM, %kN
4263 VOP, one of kandnd and kandnq:
4264 VEX VOP %kM, %kM, %kN
4265 -> VEX kandnw %kM, %kM, %kN
4267 if (is_evex_encoding (&i
.tm
))
4269 if (i
.vec_encoding
!= vex_encoding_evex
)
4271 i
.tm
.opcode_modifier
.vex
= VEX128
;
4272 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4273 i
.tm
.opcode_modifier
.evex
= 0;
4275 else if (optimize
> 1)
4276 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4280 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4282 i
.tm
.base_opcode
&= 0xff;
4283 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4286 i
.tm
.opcode_modifier
.vex
= VEX128
;
4288 if (i
.tm
.opcode_modifier
.vex
)
4289 for (j
= 0; j
< 3; j
++)
4291 i
.types
[j
].bitfield
.xmmword
= 1;
4292 i
.types
[j
].bitfield
.ymmword
= 0;
4295 else if (i
.vec_encoding
!= vex_encoding_evex
4296 && !i
.types
[0].bitfield
.zmmword
4297 && !i
.types
[1].bitfield
.zmmword
4300 && is_evex_encoding (&i
.tm
)
4301 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4302 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4303 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4304 || (i
.tm
.base_opcode
& ~4) == 0x66db
4305 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4306 && i
.tm
.extension_opcode
== None
)
4309 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4310 vmovdqu32 and vmovdqu64:
4311 EVEX VOP %xmmM, %xmmN
4312 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4313 EVEX VOP %ymmM, %ymmN
4314 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4316 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4318 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4320 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4322 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4323 VOP, one of vpand, vpandn, vpor, vpxor:
4324 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4325 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4326 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4327 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4328 EVEX VOP{d,q} mem, %xmmM, %xmmN
4329 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4330 EVEX VOP{d,q} mem, %ymmM, %ymmN
4331 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4333 for (j
= 0; j
< i
.operands
; j
++)
4334 if (operand_type_check (i
.types
[j
], disp
)
4335 && i
.op
[j
].disps
->X_op
== O_constant
)
4337 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4338 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4339 bytes, we choose EVEX Disp8 over VEX Disp32. */
4340 int evex_disp8
, vex_disp8
;
4341 unsigned int memshift
= i
.memshift
;
4342 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4344 evex_disp8
= fits_in_disp8 (n
);
4346 vex_disp8
= fits_in_disp8 (n
);
4347 if (evex_disp8
!= vex_disp8
)
4349 i
.memshift
= memshift
;
4353 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4356 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4357 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4358 i
.tm
.opcode_modifier
.vex
4359 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4360 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4361 /* VPAND, VPOR, and VPXOR are commutative. */
4362 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4363 i
.tm
.opcode_modifier
.commutative
= 1;
4364 i
.tm
.opcode_modifier
.evex
= 0;
4365 i
.tm
.opcode_modifier
.masking
= 0;
4366 i
.tm
.opcode_modifier
.broadcast
= 0;
4367 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4370 i
.types
[j
].bitfield
.disp8
4371 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4375 /* Return non-zero for load instruction. */
4381 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4382 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4386 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4387 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4388 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4389 if (i
.tm
.opcode_modifier
.anysize
)
4392 /* pop, popf, popa. */
4393 if (strcmp (i
.tm
.name
, "pop") == 0
4394 || i
.tm
.base_opcode
== 0x9d
4395 || i
.tm
.base_opcode
== 0x61)
4398 /* movs, cmps, lods, scas. */
4399 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4403 if (base_opcode
== 0x6f
4404 || i
.tm
.base_opcode
== 0xd7)
4406 /* NB: For AMD-specific insns with implicit memory operands,
4407 they're intentionally not covered. */
4410 /* No memory operand. */
4411 if (!i
.mem_operands
)
4417 if (i
.tm
.base_opcode
== 0xae
4418 && i
.tm
.opcode_modifier
.vex
4419 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
4420 && i
.tm
.extension_opcode
== 2)
4425 /* test, not, neg, mul, imul, div, idiv. */
4426 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4427 && i
.tm
.extension_opcode
!= 1)
4431 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4434 /* add, or, adc, sbb, and, sub, xor, cmp. */
4435 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4438 /* bt, bts, btr, btc. */
4439 if (i
.tm
.base_opcode
== 0xfba
4440 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4443 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4444 if ((base_opcode
== 0xc1
4445 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4446 && i
.tm
.extension_opcode
!= 6)
4449 /* cmpxchg8b, cmpxchg16b, xrstors. */
4450 if (i
.tm
.base_opcode
== 0xfc7
4451 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4452 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4455 /* fxrstor, ldmxcsr, xrstor. */
4456 if (i
.tm
.base_opcode
== 0xfae
4457 && (i
.tm
.extension_opcode
== 1
4458 || i
.tm
.extension_opcode
== 2
4459 || i
.tm
.extension_opcode
== 5))
4462 /* lgdt, lidt, lmsw. */
4463 if (i
.tm
.base_opcode
== 0xf01
4464 && (i
.tm
.extension_opcode
== 2
4465 || i
.tm
.extension_opcode
== 3
4466 || i
.tm
.extension_opcode
== 6))
4470 if (i
.tm
.base_opcode
== 0xfc7
4471 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4472 && i
.tm
.extension_opcode
== 6)
4475 /* Check for x87 instructions. */
4476 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4478 /* Skip fst, fstp, fstenv, fstcw. */
4479 if (i
.tm
.base_opcode
== 0xd9
4480 && (i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4486 /* Skip fisttp, fist, fistp, fstp. */
4487 if (i
.tm
.base_opcode
== 0xdb
4488 && (i
.tm
.extension_opcode
== 1
4489 || i
.tm
.extension_opcode
== 2
4490 || i
.tm
.extension_opcode
== 3
4491 || i
.tm
.extension_opcode
== 7))
4494 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4495 if (i
.tm
.base_opcode
== 0xdd
4496 && (i
.tm
.extension_opcode
== 1
4497 || i
.tm
.extension_opcode
== 2
4498 || i
.tm
.extension_opcode
== 3
4499 || i
.tm
.extension_opcode
== 6
4500 || i
.tm
.extension_opcode
== 7))
4503 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4504 if (i
.tm
.base_opcode
== 0xdf
4505 && (i
.tm
.extension_opcode
== 1
4506 || i
.tm
.extension_opcode
== 2
4507 || i
.tm
.extension_opcode
== 3
4508 || i
.tm
.extension_opcode
== 6
4509 || i
.tm
.extension_opcode
== 7))
4516 dest
= i
.operands
- 1;
4518 /* Check fake imm8 operand and 3 source operands. */
4519 if ((i
.tm
.opcode_modifier
.immext
4520 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4521 && i
.types
[dest
].bitfield
.imm8
)
4524 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4526 && (base_opcode
== 0x1
4527 || base_opcode
== 0x9
4528 || base_opcode
== 0x11
4529 || base_opcode
== 0x19
4530 || base_opcode
== 0x21
4531 || base_opcode
== 0x29
4532 || base_opcode
== 0x31
4533 || base_opcode
== 0x39
4534 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4535 || base_opcode
== 0xfc1))
4538 /* Check for load instruction. */
4539 return (i
.types
[dest
].bitfield
.class != ClassNone
4540 || i
.types
[dest
].bitfield
.instance
== Accum
);
4543 /* Output lfence, 0xfaee8, after instruction. */
4546 insert_lfence_after (void)
4548 if (lfence_after_load
&& load_insn_p ())
4550 /* There are also two REP string instructions that require
4551 special treatment. Specifically, the compare string (CMPS)
4552 and scan string (SCAS) instructions set EFLAGS in a manner
4553 that depends on the data being compared/scanned. When used
4554 with a REP prefix, the number of iterations may therefore
4555 vary depending on this data. If the data is a program secret
4556 chosen by the adversary using an LVI method,
4557 then this data-dependent behavior may leak some aspect
4559 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4560 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4561 && i
.prefix
[REP_PREFIX
])
4563 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4566 char *p
= frag_more (3);
4573 /* Output lfence, 0xfaee8, before instruction. */
4576 insert_lfence_before (void)
4580 if (is_any_vex_encoding (&i
.tm
))
4583 if (i
.tm
.base_opcode
== 0xff
4584 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4586 /* Insert lfence before indirect branch if needed. */
4588 if (lfence_before_indirect_branch
== lfence_branch_none
)
4591 if (i
.operands
!= 1)
4594 if (i
.reg_operands
== 1)
4596 /* Indirect branch via register. Don't insert lfence with
4597 -mlfence-after-load=yes. */
4598 if (lfence_after_load
4599 || lfence_before_indirect_branch
== lfence_branch_memory
)
4602 else if (i
.mem_operands
== 1
4603 && lfence_before_indirect_branch
!= lfence_branch_register
)
4605 as_warn (_("indirect `%s` with memory operand should be avoided"),
4612 if (last_insn
.kind
!= last_insn_other
4613 && last_insn
.seg
== now_seg
)
4615 as_warn_where (last_insn
.file
, last_insn
.line
,
4616 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4617 last_insn
.name
, i
.tm
.name
);
4628 /* Output or/not/shl and lfence before near ret. */
4629 if (lfence_before_ret
!= lfence_before_ret_none
4630 && (i
.tm
.base_opcode
== 0xc2
4631 || i
.tm
.base_opcode
== 0xc3))
4633 if (last_insn
.kind
!= last_insn_other
4634 && last_insn
.seg
== now_seg
)
4636 as_warn_where (last_insn
.file
, last_insn
.line
,
4637 _("`%s` skips -mlfence-before-ret on `%s`"),
4638 last_insn
.name
, i
.tm
.name
);
4642 /* Near ret ingore operand size override under CPU64. */
4643 char prefix
= flag_code
== CODE_64BIT
4645 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4647 if (lfence_before_ret
== lfence_before_ret_not
)
4649 /* not: 0xf71424, may add prefix
4650 for operand size override or 64-bit code. */
4651 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4665 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4668 if (lfence_before_ret
== lfence_before_ret_or
)
4670 /* or: 0x830c2400, may add prefix
4671 for operand size override or 64-bit code. */
4677 /* shl: 0xc1242400, may add prefix
4678 for operand size override or 64-bit code. */
4693 /* This is the guts of the machine-dependent assembler. LINE points to a
4694 machine dependent instruction. This function is supposed to emit
4695 the frags/bytes it assembles to. */
4698 md_assemble (char *line
)
4701 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4702 const insn_template
*t
;
4704 /* Initialize globals. */
4705 memset (&i
, '\0', sizeof (i
));
4706 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4707 i
.reloc
[j
] = NO_RELOC
;
4708 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4709 memset (im_expressions
, '\0', sizeof (im_expressions
));
4710 save_stack_p
= save_stack
;
4712 /* First parse an instruction mnemonic & call i386_operand for the operands.
4713 We assume that the scrubber has arranged it so that line[0] is the valid
4714 start of a (possibly prefixed) mnemonic. */
4716 line
= parse_insn (line
, mnemonic
);
4719 mnem_suffix
= i
.suffix
;
4721 line
= parse_operands (line
, mnemonic
);
4723 xfree (i
.memop1_string
);
4724 i
.memop1_string
= NULL
;
4728 /* Now we've parsed the mnemonic into a set of templates, and have the
4729 operands at hand. */
4731 /* All Intel opcodes have reversed operands except for "bound", "enter",
4732 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4733 intersegment "jmp" and "call" instructions with 2 immediate operands so
4734 that the immediate segment precedes the offset, as it does when in AT&T
4738 && (strcmp (mnemonic
, "bound") != 0)
4739 && (strcmp (mnemonic
, "invlpga") != 0)
4740 && (strncmp (mnemonic
, "monitor", 7) != 0)
4741 && (strncmp (mnemonic
, "mwait", 5) != 0)
4742 && (strcmp (mnemonic
, "tpause") != 0)
4743 && (strcmp (mnemonic
, "umwait") != 0)
4744 && !(operand_type_check (i
.types
[0], imm
)
4745 && operand_type_check (i
.types
[1], imm
)))
4748 /* The order of the immediates should be reversed
4749 for 2 immediates extrq and insertq instructions */
4750 if (i
.imm_operands
== 2
4751 && (strcmp (mnemonic
, "extrq") == 0
4752 || strcmp (mnemonic
, "insertq") == 0))
4753 swap_2_operands (0, 1);
4758 /* Don't optimize displacement for movabs since it only takes 64bit
4761 && i
.disp_encoding
!= disp_encoding_32bit
4762 && (flag_code
!= CODE_64BIT
4763 || strcmp (mnemonic
, "movabs") != 0))
4766 /* Next, we find a template that matches the given insn,
4767 making sure the overlap of the given operands types is consistent
4768 with the template operand types. */
4770 if (!(t
= match_template (mnem_suffix
)))
4773 if (sse_check
!= check_none
4774 && !i
.tm
.opcode_modifier
.noavx
4775 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4776 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4777 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4778 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4779 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4780 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4781 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4782 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4783 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4784 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4785 || i
.tm
.cpu_flags
.bitfield
.cpusha
4786 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4788 (sse_check
== check_warning
4790 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4793 if (i
.tm
.opcode_modifier
.fwait
)
4794 if (!add_prefix (FWAIT_OPCODE
))
4797 /* Check if REP prefix is OK. */
4798 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4800 as_bad (_("invalid instruction `%s' after `%s'"),
4801 i
.tm
.name
, i
.rep_prefix
);
4805 /* Check for lock without a lockable instruction. Destination operand
4806 must be memory unless it is xchg (0x86). */
4807 if (i
.prefix
[LOCK_PREFIX
]
4808 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4809 || i
.mem_operands
== 0
4810 || (i
.tm
.base_opcode
!= 0x86
4811 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4813 as_bad (_("expecting lockable instruction after `lock'"));
4817 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4818 if (i
.prefix
[DATA_PREFIX
]
4819 && (is_any_vex_encoding (&i
.tm
)
4820 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4821 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4823 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4827 /* Check if HLE prefix is OK. */
4828 if (i
.hle_prefix
&& !check_hle ())
4831 /* Check BND prefix. */
4832 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4833 as_bad (_("expecting valid branch instruction after `bnd'"));
4835 /* Check NOTRACK prefix. */
4836 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
4837 as_bad (_("expecting indirect branch instruction after `notrack'"));
4839 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4841 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4842 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4843 else if (flag_code
!= CODE_16BIT
4844 ? i
.prefix
[ADDR_PREFIX
]
4845 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4846 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4849 /* Insert BND prefix. */
4850 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4852 if (!i
.prefix
[BND_PREFIX
])
4853 add_prefix (BND_PREFIX_OPCODE
);
4854 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4856 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4857 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4861 /* Check string instruction segment overrides. */
4862 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4864 gas_assert (i
.mem_operands
);
4865 if (!check_string ())
4867 i
.disp_operands
= 0;
4870 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4871 optimize_encoding ();
4873 if (!process_suffix ())
4876 /* Update operand types and check extended states. */
4877 for (j
= 0; j
< i
.operands
; j
++)
4879 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4880 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4885 i
.xstate
|= xstate_mmx
;
4888 i
.xstate
|= xstate_mask
;
4891 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4892 i
.xstate
|= xstate_tmm
;
4893 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4894 i
.xstate
|= xstate_zmm
;
4895 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4896 i
.xstate
|= xstate_ymm
;
4897 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4898 i
.xstate
|= xstate_xmm
;
4903 /* Make still unresolved immediate matches conform to size of immediate
4904 given in i.suffix. */
4905 if (!finalize_imm ())
4908 if (i
.types
[0].bitfield
.imm1
)
4909 i
.imm_operands
= 0; /* kludge for shift insns. */
4911 /* We only need to check those implicit registers for instructions
4912 with 3 operands or less. */
4913 if (i
.operands
<= 3)
4914 for (j
= 0; j
< i
.operands
; j
++)
4915 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4916 && !i
.types
[j
].bitfield
.xmmword
)
4919 /* For insns with operands there are more diddles to do to the opcode. */
4922 if (!process_operands ())
4925 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4927 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4928 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4931 if (is_any_vex_encoding (&i
.tm
))
4933 if (!cpu_arch_flags
.bitfield
.cpui286
)
4935 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4940 /* Check for explicit REX prefix. */
4941 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4943 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4947 if (i
.tm
.opcode_modifier
.vex
)
4948 build_vex_prefix (t
);
4950 build_evex_prefix ();
4952 /* The individual REX.RXBW bits got consumed. */
4953 i
.rex
&= REX_OPCODE
;
4956 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4957 instructions may define INT_OPCODE as well, so avoid this corner
4958 case for those instructions that use MODRM. */
4959 if (i
.tm
.base_opcode
== INT_OPCODE
4960 && !i
.tm
.opcode_modifier
.modrm
4961 && i
.op
[0].imms
->X_add_number
== 3)
4963 i
.tm
.base_opcode
= INT3_OPCODE
;
4967 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4968 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4969 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4970 && i
.op
[0].disps
->X_op
== O_constant
)
4972 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4973 the absolute address given by the constant. Since ix86 jumps and
4974 calls are pc relative, we need to generate a reloc. */
4975 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4976 i
.op
[0].disps
->X_op
= O_symbol
;
4979 /* For 8 bit registers we need an empty rex prefix. Also if the
4980 instruction already has a prefix, we need to convert old
4981 registers to new ones. */
4983 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4984 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4985 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4986 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4987 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4988 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4993 i
.rex
|= REX_OPCODE
;
4994 for (x
= 0; x
< 2; x
++)
4996 /* Look for 8 bit operand that uses old registers. */
4997 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4998 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5000 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5001 /* In case it is "hi" register, give up. */
5002 if (i
.op
[x
].regs
->reg_num
> 3)
5003 as_bad (_("can't encode register '%s%s' in an "
5004 "instruction requiring REX prefix."),
5005 register_prefix
, i
.op
[x
].regs
->reg_name
);
5007 /* Otherwise it is equivalent to the extended register.
5008 Since the encoding doesn't change this is merely
5009 cosmetic cleanup for debug output. */
5011 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5016 if (i
.rex
== 0 && i
.rex_encoding
)
5018 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5019 that uses legacy register. If it is "hi" register, don't add
5020 the REX_OPCODE byte. */
5022 for (x
= 0; x
< 2; x
++)
5023 if (i
.types
[x
].bitfield
.class == Reg
5024 && i
.types
[x
].bitfield
.byte
5025 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5026 && i
.op
[x
].regs
->reg_num
> 3)
5028 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5029 i
.rex_encoding
= FALSE
;
5038 add_prefix (REX_OPCODE
| i
.rex
);
5040 insert_lfence_before ();
5042 /* We are ready to output the insn. */
5045 insert_lfence_after ();
5047 last_insn
.seg
= now_seg
;
5049 if (i
.tm
.opcode_modifier
.isprefix
)
5051 last_insn
.kind
= last_insn_prefix
;
5052 last_insn
.name
= i
.tm
.name
;
5053 last_insn
.file
= as_where (&last_insn
.line
);
5056 last_insn
.kind
= last_insn_other
;
5060 parse_insn (char *line
, char *mnemonic
)
5063 char *token_start
= l
;
5066 const insn_template
*t
;
5072 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5077 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5079 as_bad (_("no such instruction: `%s'"), token_start
);
5084 if (!is_space_char (*l
)
5085 && *l
!= END_OF_INSN
5087 || (*l
!= PREFIX_SEPARATOR
5090 as_bad (_("invalid character %s in mnemonic"),
5091 output_invalid (*l
));
5094 if (token_start
== l
)
5096 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5097 as_bad (_("expecting prefix; got nothing"));
5099 as_bad (_("expecting mnemonic; got nothing"));
5103 /* Look up instruction (or prefix) via hash table. */
5104 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5106 if (*l
!= END_OF_INSN
5107 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5108 && current_templates
5109 && current_templates
->start
->opcode_modifier
.isprefix
)
5111 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5113 as_bad ((flag_code
!= CODE_64BIT
5114 ? _("`%s' is only supported in 64-bit mode")
5115 : _("`%s' is not supported in 64-bit mode")),
5116 current_templates
->start
->name
);
5119 /* If we are in 16-bit mode, do not allow addr16 or data16.
5120 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5121 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5122 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5123 && flag_code
!= CODE_64BIT
5124 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5125 ^ (flag_code
== CODE_16BIT
)))
5127 as_bad (_("redundant %s prefix"),
5128 current_templates
->start
->name
);
5131 if (current_templates
->start
->opcode_length
== 0)
5133 /* Handle pseudo prefixes. */
5134 switch (current_templates
->start
->base_opcode
)
5138 i
.disp_encoding
= disp_encoding_8bit
;
5142 i
.disp_encoding
= disp_encoding_16bit
;
5146 i
.disp_encoding
= disp_encoding_32bit
;
5150 i
.dir_encoding
= dir_encoding_load
;
5154 i
.dir_encoding
= dir_encoding_store
;
5158 i
.vec_encoding
= vex_encoding_vex
;
5162 i
.vec_encoding
= vex_encoding_vex3
;
5166 i
.vec_encoding
= vex_encoding_evex
;
5170 i
.rex_encoding
= TRUE
;
5172 case Prefix_NoOptimize
:
5174 i
.no_optimize
= TRUE
;
5182 /* Add prefix, checking for repeated prefixes. */
5183 switch (add_prefix (current_templates
->start
->base_opcode
))
5188 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5189 i
.notrack_prefix
= current_templates
->start
->name
;
5192 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5193 i
.hle_prefix
= current_templates
->start
->name
;
5194 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5195 i
.bnd_prefix
= current_templates
->start
->name
;
5197 i
.rep_prefix
= current_templates
->start
->name
;
5203 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5210 if (!current_templates
)
5212 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5213 Check if we should swap operand or force 32bit displacement in
5215 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5216 i
.dir_encoding
= dir_encoding_swap
;
5217 else if (mnem_p
- 3 == dot_p
5220 i
.disp_encoding
= disp_encoding_8bit
;
5221 else if (mnem_p
- 4 == dot_p
5225 i
.disp_encoding
= disp_encoding_32bit
;
5230 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5233 if (!current_templates
)
5236 if (mnem_p
> mnemonic
)
5238 /* See if we can get a match by trimming off a suffix. */
5241 case WORD_MNEM_SUFFIX
:
5242 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5243 i
.suffix
= SHORT_MNEM_SUFFIX
;
5246 case BYTE_MNEM_SUFFIX
:
5247 case QWORD_MNEM_SUFFIX
:
5248 i
.suffix
= mnem_p
[-1];
5251 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5253 case SHORT_MNEM_SUFFIX
:
5254 case LONG_MNEM_SUFFIX
:
5257 i
.suffix
= mnem_p
[-1];
5260 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5268 if (intel_float_operand (mnemonic
) == 1)
5269 i
.suffix
= SHORT_MNEM_SUFFIX
;
5271 i
.suffix
= LONG_MNEM_SUFFIX
;
5274 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5280 if (!current_templates
)
5282 as_bad (_("no such instruction: `%s'"), token_start
);
5287 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5288 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5290 /* Check for a branch hint. We allow ",pt" and ",pn" for
5291 predict taken and predict not taken respectively.
5292 I'm not sure that branch hints actually do anything on loop
5293 and jcxz insns (JumpByte) for current Pentium4 chips. They
5294 may work in the future and it doesn't hurt to accept them
5296 if (l
[0] == ',' && l
[1] == 'p')
5300 if (!add_prefix (DS_PREFIX_OPCODE
))
5304 else if (l
[2] == 'n')
5306 if (!add_prefix (CS_PREFIX_OPCODE
))
5312 /* Any other comma loses. */
5315 as_bad (_("invalid character %s in mnemonic"),
5316 output_invalid (*l
));
5320 /* Check if instruction is supported on specified architecture. */
5322 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5324 supported
|= cpu_flags_match (t
);
5325 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5327 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5328 as_warn (_("use .code16 to ensure correct addressing mode"));
5334 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5335 as_bad (flag_code
== CODE_64BIT
5336 ? _("`%s' is not supported in 64-bit mode")
5337 : _("`%s' is only supported in 64-bit mode"),
5338 current_templates
->start
->name
);
5340 as_bad (_("`%s' is not supported on `%s%s'"),
5341 current_templates
->start
->name
,
5342 cpu_arch_name
? cpu_arch_name
: default_arch
,
5343 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5349 parse_operands (char *l
, const char *mnemonic
)
5353 /* 1 if operand is pending after ','. */
5354 unsigned int expecting_operand
= 0;
5356 /* Non-zero if operand parens not balanced. */
5357 unsigned int paren_not_balanced
;
5359 while (*l
!= END_OF_INSN
)
5361 /* Skip optional white space before operand. */
5362 if (is_space_char (*l
))
5364 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5366 as_bad (_("invalid character %s before operand %d"),
5367 output_invalid (*l
),
5371 token_start
= l
; /* After white space. */
5372 paren_not_balanced
= 0;
5373 while (paren_not_balanced
|| *l
!= ',')
5375 if (*l
== END_OF_INSN
)
5377 if (paren_not_balanced
)
5380 as_bad (_("unbalanced parenthesis in operand %d."),
5383 as_bad (_("unbalanced brackets in operand %d."),
5388 break; /* we are done */
5390 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5392 as_bad (_("invalid character %s in operand %d"),
5393 output_invalid (*l
),
5400 ++paren_not_balanced
;
5402 --paren_not_balanced
;
5407 ++paren_not_balanced
;
5409 --paren_not_balanced
;
5413 if (l
!= token_start
)
5414 { /* Yes, we've read in another operand. */
5415 unsigned int operand_ok
;
5416 this_operand
= i
.operands
++;
5417 if (i
.operands
> MAX_OPERANDS
)
5419 as_bad (_("spurious operands; (%d operands/instruction max)"),
5423 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5424 /* Now parse operand adding info to 'i' as we go along. */
5425 END_STRING_AND_SAVE (l
);
5427 if (i
.mem_operands
> 1)
5429 as_bad (_("too many memory references for `%s'"),
5436 i386_intel_operand (token_start
,
5437 intel_float_operand (mnemonic
));
5439 operand_ok
= i386_att_operand (token_start
);
5441 RESTORE_END_STRING (l
);
5447 if (expecting_operand
)
5449 expecting_operand_after_comma
:
5450 as_bad (_("expecting operand after ','; got nothing"));
5455 as_bad (_("expecting operand before ','; got nothing"));
5460 /* Now *l must be either ',' or END_OF_INSN. */
5463 if (*++l
== END_OF_INSN
)
5465 /* Just skip it, if it's \n complain. */
5466 goto expecting_operand_after_comma
;
5468 expecting_operand
= 1;
5475 swap_2_operands (int xchg1
, int xchg2
)
5477 union i386_op temp_op
;
5478 i386_operand_type temp_type
;
5479 unsigned int temp_flags
;
5480 enum bfd_reloc_code_real temp_reloc
;
5482 temp_type
= i
.types
[xchg2
];
5483 i
.types
[xchg2
] = i
.types
[xchg1
];
5484 i
.types
[xchg1
] = temp_type
;
5486 temp_flags
= i
.flags
[xchg2
];
5487 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5488 i
.flags
[xchg1
] = temp_flags
;
5490 temp_op
= i
.op
[xchg2
];
5491 i
.op
[xchg2
] = i
.op
[xchg1
];
5492 i
.op
[xchg1
] = temp_op
;
5494 temp_reloc
= i
.reloc
[xchg2
];
5495 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5496 i
.reloc
[xchg1
] = temp_reloc
;
5500 if (i
.mask
->operand
== xchg1
)
5501 i
.mask
->operand
= xchg2
;
5502 else if (i
.mask
->operand
== xchg2
)
5503 i
.mask
->operand
= xchg1
;
5507 if (i
.broadcast
->operand
== xchg1
)
5508 i
.broadcast
->operand
= xchg2
;
5509 else if (i
.broadcast
->operand
== xchg2
)
5510 i
.broadcast
->operand
= xchg1
;
5514 if (i
.rounding
->operand
== xchg1
)
5515 i
.rounding
->operand
= xchg2
;
5516 else if (i
.rounding
->operand
== xchg2
)
5517 i
.rounding
->operand
= xchg1
;
5522 swap_operands (void)
5528 swap_2_operands (1, i
.operands
- 2);
5532 swap_2_operands (0, i
.operands
- 1);
5538 if (i
.mem_operands
== 2)
5540 const seg_entry
*temp_seg
;
5541 temp_seg
= i
.seg
[0];
5542 i
.seg
[0] = i
.seg
[1];
5543 i
.seg
[1] = temp_seg
;
5547 /* Try to ensure constant immediates are represented in the smallest
5552 char guess_suffix
= 0;
5556 guess_suffix
= i
.suffix
;
5557 else if (i
.reg_operands
)
5559 /* Figure out a suffix from the last register operand specified.
5560 We can't do this properly yet, i.e. excluding special register
5561 instances, but the following works for instructions with
5562 immediates. In any case, we can't set i.suffix yet. */
5563 for (op
= i
.operands
; --op
>= 0;)
5564 if (i
.types
[op
].bitfield
.class != Reg
)
5566 else if (i
.types
[op
].bitfield
.byte
)
5568 guess_suffix
= BYTE_MNEM_SUFFIX
;
5571 else if (i
.types
[op
].bitfield
.word
)
5573 guess_suffix
= WORD_MNEM_SUFFIX
;
5576 else if (i
.types
[op
].bitfield
.dword
)
5578 guess_suffix
= LONG_MNEM_SUFFIX
;
5581 else if (i
.types
[op
].bitfield
.qword
)
5583 guess_suffix
= QWORD_MNEM_SUFFIX
;
5587 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5588 guess_suffix
= WORD_MNEM_SUFFIX
;
5590 for (op
= i
.operands
; --op
>= 0;)
5591 if (operand_type_check (i
.types
[op
], imm
))
5593 switch (i
.op
[op
].imms
->X_op
)
5596 /* If a suffix is given, this operand may be shortened. */
5597 switch (guess_suffix
)
5599 case LONG_MNEM_SUFFIX
:
5600 i
.types
[op
].bitfield
.imm32
= 1;
5601 i
.types
[op
].bitfield
.imm64
= 1;
5603 case WORD_MNEM_SUFFIX
:
5604 i
.types
[op
].bitfield
.imm16
= 1;
5605 i
.types
[op
].bitfield
.imm32
= 1;
5606 i
.types
[op
].bitfield
.imm32s
= 1;
5607 i
.types
[op
].bitfield
.imm64
= 1;
5609 case BYTE_MNEM_SUFFIX
:
5610 i
.types
[op
].bitfield
.imm8
= 1;
5611 i
.types
[op
].bitfield
.imm8s
= 1;
5612 i
.types
[op
].bitfield
.imm16
= 1;
5613 i
.types
[op
].bitfield
.imm32
= 1;
5614 i
.types
[op
].bitfield
.imm32s
= 1;
5615 i
.types
[op
].bitfield
.imm64
= 1;
5619 /* If this operand is at most 16 bits, convert it
5620 to a signed 16 bit number before trying to see
5621 whether it will fit in an even smaller size.
5622 This allows a 16-bit operand such as $0xffe0 to
5623 be recognised as within Imm8S range. */
5624 if ((i
.types
[op
].bitfield
.imm16
)
5625 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5627 i
.op
[op
].imms
->X_add_number
=
5628 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5631 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5632 if ((i
.types
[op
].bitfield
.imm32
)
5633 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5636 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5637 ^ ((offsetT
) 1 << 31))
5638 - ((offsetT
) 1 << 31));
5642 = operand_type_or (i
.types
[op
],
5643 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5645 /* We must avoid matching of Imm32 templates when 64bit
5646 only immediate is available. */
5647 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5648 i
.types
[op
].bitfield
.imm32
= 0;
5655 /* Symbols and expressions. */
5657 /* Convert symbolic operand to proper sizes for matching, but don't
5658 prevent matching a set of insns that only supports sizes other
5659 than those matching the insn suffix. */
5661 i386_operand_type mask
, allowed
;
5662 const insn_template
*t
;
5664 operand_type_set (&mask
, 0);
5665 operand_type_set (&allowed
, 0);
5667 for (t
= current_templates
->start
;
5668 t
< current_templates
->end
;
5671 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5672 allowed
= operand_type_and (allowed
, anyimm
);
5674 switch (guess_suffix
)
5676 case QWORD_MNEM_SUFFIX
:
5677 mask
.bitfield
.imm64
= 1;
5678 mask
.bitfield
.imm32s
= 1;
5680 case LONG_MNEM_SUFFIX
:
5681 mask
.bitfield
.imm32
= 1;
5683 case WORD_MNEM_SUFFIX
:
5684 mask
.bitfield
.imm16
= 1;
5686 case BYTE_MNEM_SUFFIX
:
5687 mask
.bitfield
.imm8
= 1;
5692 allowed
= operand_type_and (mask
, allowed
);
5693 if (!operand_type_all_zero (&allowed
))
5694 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5701 /* Try to use the smallest displacement type too. */
5703 optimize_disp (void)
5707 for (op
= i
.operands
; --op
>= 0;)
5708 if (operand_type_check (i
.types
[op
], disp
))
5710 if (i
.op
[op
].disps
->X_op
== O_constant
)
5712 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5714 if (i
.types
[op
].bitfield
.disp16
5715 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5717 /* If this operand is at most 16 bits, convert
5718 to a signed 16 bit number and don't use 64bit
5720 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5721 i
.types
[op
].bitfield
.disp64
= 0;
5724 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5725 if (i
.types
[op
].bitfield
.disp32
5726 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5728 /* If this operand is at most 32 bits, convert
5729 to a signed 32 bit number and don't use 64bit
5731 op_disp
&= (((offsetT
) 2 << 31) - 1);
5732 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5733 i
.types
[op
].bitfield
.disp64
= 0;
5736 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5738 i
.types
[op
].bitfield
.disp8
= 0;
5739 i
.types
[op
].bitfield
.disp16
= 0;
5740 i
.types
[op
].bitfield
.disp32
= 0;
5741 i
.types
[op
].bitfield
.disp32s
= 0;
5742 i
.types
[op
].bitfield
.disp64
= 0;
5746 else if (flag_code
== CODE_64BIT
)
5748 if (fits_in_signed_long (op_disp
))
5750 i
.types
[op
].bitfield
.disp64
= 0;
5751 i
.types
[op
].bitfield
.disp32s
= 1;
5753 if (i
.prefix
[ADDR_PREFIX
]
5754 && fits_in_unsigned_long (op_disp
))
5755 i
.types
[op
].bitfield
.disp32
= 1;
5757 if ((i
.types
[op
].bitfield
.disp32
5758 || i
.types
[op
].bitfield
.disp32s
5759 || i
.types
[op
].bitfield
.disp16
)
5760 && fits_in_disp8 (op_disp
))
5761 i
.types
[op
].bitfield
.disp8
= 1;
5763 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5764 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5766 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5767 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5768 i
.types
[op
].bitfield
.disp8
= 0;
5769 i
.types
[op
].bitfield
.disp16
= 0;
5770 i
.types
[op
].bitfield
.disp32
= 0;
5771 i
.types
[op
].bitfield
.disp32s
= 0;
5772 i
.types
[op
].bitfield
.disp64
= 0;
5775 /* We only support 64bit displacement on constants. */
5776 i
.types
[op
].bitfield
.disp64
= 0;
5780 /* Return 1 if there is a match in broadcast bytes between operand
5781 GIVEN and instruction template T. */
5784 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5786 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5787 && i
.types
[given
].bitfield
.byte
)
5788 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5789 && i
.types
[given
].bitfield
.word
)
5790 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5791 && i
.types
[given
].bitfield
.dword
)
5792 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5793 && i
.types
[given
].bitfield
.qword
));
5796 /* Check if operands are valid for the instruction. */
5799 check_VecOperands (const insn_template
*t
)
5804 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5805 any one operand are implicity requiring AVX512VL support if the actual
5806 operand size is YMMword or XMMword. Since this function runs after
5807 template matching, there's no need to check for YMMword/XMMword in
5809 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5810 if (!cpu_flags_all_zero (&cpu
)
5811 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5812 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5814 for (op
= 0; op
< t
->operands
; ++op
)
5816 if (t
->operand_types
[op
].bitfield
.zmmword
5817 && (i
.types
[op
].bitfield
.ymmword
5818 || i
.types
[op
].bitfield
.xmmword
))
5820 i
.error
= unsupported
;
5826 /* Without VSIB byte, we can't have a vector register for index. */
5827 if (!t
->opcode_modifier
.sib
5829 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5830 || i
.index_reg
->reg_type
.bitfield
.ymmword
5831 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5833 i
.error
= unsupported_vector_index_register
;
5837 /* Check if default mask is allowed. */
5838 if (t
->opcode_modifier
.nodefmask
5839 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5841 i
.error
= no_default_mask
;
5845 /* For VSIB byte, we need a vector register for index, and all vector
5846 registers must be distinct. */
5847 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5850 || !((t
->opcode_modifier
.sib
== VECSIB128
5851 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5852 || (t
->opcode_modifier
.sib
== VECSIB256
5853 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5854 || (t
->opcode_modifier
.sib
== VECSIB512
5855 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5857 i
.error
= invalid_vsib_address
;
5861 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5862 if (i
.reg_operands
== 2 && !i
.mask
)
5864 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5865 gas_assert (i
.types
[0].bitfield
.xmmword
5866 || i
.types
[0].bitfield
.ymmword
);
5867 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5868 gas_assert (i
.types
[2].bitfield
.xmmword
5869 || i
.types
[2].bitfield
.ymmword
);
5870 if (operand_check
== check_none
)
5872 if (register_number (i
.op
[0].regs
)
5873 != register_number (i
.index_reg
)
5874 && register_number (i
.op
[2].regs
)
5875 != register_number (i
.index_reg
)
5876 && register_number (i
.op
[0].regs
)
5877 != register_number (i
.op
[2].regs
))
5879 if (operand_check
== check_error
)
5881 i
.error
= invalid_vector_register_set
;
5884 as_warn (_("mask, index, and destination registers should be distinct"));
5886 else if (i
.reg_operands
== 1 && i
.mask
)
5888 if (i
.types
[1].bitfield
.class == RegSIMD
5889 && (i
.types
[1].bitfield
.xmmword
5890 || i
.types
[1].bitfield
.ymmword
5891 || i
.types
[1].bitfield
.zmmword
)
5892 && (register_number (i
.op
[1].regs
)
5893 == register_number (i
.index_reg
)))
5895 if (operand_check
== check_error
)
5897 i
.error
= invalid_vector_register_set
;
5900 if (operand_check
!= check_none
)
5901 as_warn (_("index and destination registers should be distinct"));
5906 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5908 if (t
->operand_types
[0].bitfield
.tmmword
5909 && i
.reg_operands
== 3)
5911 if (register_number (i
.op
[0].regs
)
5912 == register_number (i
.op
[1].regs
)
5913 || register_number (i
.op
[0].regs
)
5914 == register_number (i
.op
[2].regs
)
5915 || register_number (i
.op
[1].regs
)
5916 == register_number (i
.op
[2].regs
))
5918 i
.error
= invalid_tmm_register_set
;
5923 /* Check if broadcast is supported by the instruction and is applied
5924 to the memory operand. */
5927 i386_operand_type type
, overlap
;
5929 /* Check if specified broadcast is supported in this instruction,
5930 and its broadcast bytes match the memory operand. */
5931 op
= i
.broadcast
->operand
;
5932 if (!t
->opcode_modifier
.broadcast
5933 || !(i
.flags
[op
] & Operand_Mem
)
5934 || (!i
.types
[op
].bitfield
.unspecified
5935 && !match_broadcast_size (t
, op
)))
5938 i
.error
= unsupported_broadcast
;
5942 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5943 * i
.broadcast
->type
);
5944 operand_type_set (&type
, 0);
5945 switch (i
.broadcast
->bytes
)
5948 type
.bitfield
.word
= 1;
5951 type
.bitfield
.dword
= 1;
5954 type
.bitfield
.qword
= 1;
5957 type
.bitfield
.xmmword
= 1;
5960 type
.bitfield
.ymmword
= 1;
5963 type
.bitfield
.zmmword
= 1;
5969 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5970 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5971 && t
->operand_types
[op
].bitfield
.byte
5972 + t
->operand_types
[op
].bitfield
.word
5973 + t
->operand_types
[op
].bitfield
.dword
5974 + t
->operand_types
[op
].bitfield
.qword
> 1)
5976 overlap
.bitfield
.xmmword
= 0;
5977 overlap
.bitfield
.ymmword
= 0;
5978 overlap
.bitfield
.zmmword
= 0;
5980 if (operand_type_all_zero (&overlap
))
5983 if (t
->opcode_modifier
.checkregsize
)
5987 type
.bitfield
.baseindex
= 1;
5988 for (j
= 0; j
< i
.operands
; ++j
)
5991 && !operand_type_register_match(i
.types
[j
],
5992 t
->operand_types
[j
],
5994 t
->operand_types
[op
]))
5999 /* If broadcast is supported in this instruction, we need to check if
6000 operand of one-element size isn't specified without broadcast. */
6001 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6003 /* Find memory operand. */
6004 for (op
= 0; op
< i
.operands
; op
++)
6005 if (i
.flags
[op
] & Operand_Mem
)
6007 gas_assert (op
< i
.operands
);
6008 /* Check size of the memory operand. */
6009 if (match_broadcast_size (t
, op
))
6011 i
.error
= broadcast_needed
;
6016 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6018 /* Check if requested masking is supported. */
6021 switch (t
->opcode_modifier
.masking
)
6025 case MERGING_MASKING
:
6026 if (i
.mask
->zeroing
)
6029 i
.error
= unsupported_masking
;
6033 case DYNAMIC_MASKING
:
6034 /* Memory destinations allow only merging masking. */
6035 if (i
.mask
->zeroing
&& i
.mem_operands
)
6037 /* Find memory operand. */
6038 for (op
= 0; op
< i
.operands
; op
++)
6039 if (i
.flags
[op
] & Operand_Mem
)
6041 gas_assert (op
< i
.operands
);
6042 if (op
== i
.operands
- 1)
6044 i
.error
= unsupported_masking
;
6054 /* Check if masking is applied to dest operand. */
6055 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6057 i
.error
= mask_not_on_destination
;
6064 if (!t
->opcode_modifier
.sae
6065 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6067 i
.error
= unsupported_rc_sae
;
6070 /* If the instruction has several immediate operands and one of
6071 them is rounding, the rounding operand should be the last
6072 immediate operand. */
6073 if (i
.imm_operands
> 1
6074 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6076 i
.error
= rc_sae_operand_not_last_imm
;
6081 /* Check the special Imm4 cases; must be the first operand. */
6082 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6084 if (i
.op
[0].imms
->X_op
!= O_constant
6085 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6091 /* Turn off Imm<N> so that update_imm won't complain. */
6092 operand_type_set (&i
.types
[0], 0);
6095 /* Check vector Disp8 operand. */
6096 if (t
->opcode_modifier
.disp8memshift
6097 && i
.disp_encoding
!= disp_encoding_32bit
)
6100 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6101 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6102 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6105 const i386_operand_type
*type
= NULL
;
6108 for (op
= 0; op
< i
.operands
; op
++)
6109 if (i
.flags
[op
] & Operand_Mem
)
6111 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6112 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6113 else if (t
->operand_types
[op
].bitfield
.xmmword
6114 + t
->operand_types
[op
].bitfield
.ymmword
6115 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6116 type
= &t
->operand_types
[op
];
6117 else if (!i
.types
[op
].bitfield
.unspecified
)
6118 type
= &i
.types
[op
];
6120 else if (i
.types
[op
].bitfield
.class == RegSIMD
6121 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6123 if (i
.types
[op
].bitfield
.zmmword
)
6125 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6127 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6133 if (type
->bitfield
.zmmword
)
6135 else if (type
->bitfield
.ymmword
)
6137 else if (type
->bitfield
.xmmword
)
6141 /* For the check in fits_in_disp8(). */
6142 if (i
.memshift
== 0)
6146 for (op
= 0; op
< i
.operands
; op
++)
6147 if (operand_type_check (i
.types
[op
], disp
)
6148 && i
.op
[op
].disps
->X_op
== O_constant
)
6150 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6152 i
.types
[op
].bitfield
.disp8
= 1;
6155 i
.types
[op
].bitfield
.disp8
= 0;
6164 /* Check if encoding requirements are met by the instruction. */
6167 VEX_check_encoding (const insn_template
*t
)
6169 if (i
.vec_encoding
== vex_encoding_error
)
6171 i
.error
= unsupported
;
6175 if (i
.vec_encoding
== vex_encoding_evex
)
6177 /* This instruction must be encoded with EVEX prefix. */
6178 if (!is_evex_encoding (t
))
6180 i
.error
= unsupported
;
6186 if (!t
->opcode_modifier
.vex
)
6188 /* This instruction template doesn't have VEX prefix. */
6189 if (i
.vec_encoding
!= vex_encoding_default
)
6191 i
.error
= unsupported
;
6200 static const insn_template
*
6201 match_template (char mnem_suffix
)
6203 /* Points to template once we've found it. */
6204 const insn_template
*t
;
6205 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6206 i386_operand_type overlap4
;
6207 unsigned int found_reverse_match
;
6208 i386_opcode_modifier suffix_check
;
6209 i386_operand_type operand_types
[MAX_OPERANDS
];
6210 int addr_prefix_disp
;
6211 unsigned int j
, size_match
, check_register
;
6212 enum i386_error specific_error
= 0;
6214 #if MAX_OPERANDS != 5
6215 # error "MAX_OPERANDS must be 5."
6218 found_reverse_match
= 0;
6219 addr_prefix_disp
= -1;
6221 /* Prepare for mnemonic suffix check. */
6222 memset (&suffix_check
, 0, sizeof (suffix_check
));
6223 switch (mnem_suffix
)
6225 case BYTE_MNEM_SUFFIX
:
6226 suffix_check
.no_bsuf
= 1;
6228 case WORD_MNEM_SUFFIX
:
6229 suffix_check
.no_wsuf
= 1;
6231 case SHORT_MNEM_SUFFIX
:
6232 suffix_check
.no_ssuf
= 1;
6234 case LONG_MNEM_SUFFIX
:
6235 suffix_check
.no_lsuf
= 1;
6237 case QWORD_MNEM_SUFFIX
:
6238 suffix_check
.no_qsuf
= 1;
6241 /* NB: In Intel syntax, normally we can check for memory operand
6242 size when there is no mnemonic suffix. But jmp and call have
6243 2 different encodings with Dword memory operand size, one with
6244 No_ldSuf and the other without. i.suffix is set to
6245 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6246 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6247 suffix_check
.no_ldsuf
= 1;
6250 /* Must have right number of operands. */
6251 i
.error
= number_of_operands_mismatch
;
6253 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6255 addr_prefix_disp
= -1;
6256 found_reverse_match
= 0;
6258 if (i
.operands
!= t
->operands
)
6261 /* Check processor support. */
6262 i
.error
= unsupported
;
6263 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6266 /* Check Pseudo Prefix. */
6267 i
.error
= unsupported
;
6268 if (t
->opcode_modifier
.pseudovexprefix
6269 && !(i
.vec_encoding
== vex_encoding_vex
6270 || i
.vec_encoding
== vex_encoding_vex3
))
6273 /* Check AT&T mnemonic. */
6274 i
.error
= unsupported_with_intel_mnemonic
;
6275 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6278 /* Check AT&T/Intel syntax. */
6279 i
.error
= unsupported_syntax
;
6280 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6281 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6284 /* Check Intel64/AMD64 ISA. */
6288 /* Default: Don't accept Intel64. */
6289 if (t
->opcode_modifier
.isa64
== INTEL64
)
6293 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6294 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6298 /* -mintel64: Don't accept AMD64. */
6299 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6304 /* Check the suffix. */
6305 i
.error
= invalid_instruction_suffix
;
6306 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6307 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6308 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6309 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6310 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6311 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6314 size_match
= operand_size_match (t
);
6318 /* This is intentionally not
6320 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6322 as the case of a missing * on the operand is accepted (perhaps with
6323 a warning, issued further down). */
6324 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6326 i
.error
= operand_type_mismatch
;
6330 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6331 operand_types
[j
] = t
->operand_types
[j
];
6333 /* In general, don't allow
6334 - 64-bit operands outside of 64-bit mode,
6335 - 32-bit operands on pre-386. */
6336 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6337 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6338 && flag_code
!= CODE_64BIT
6339 && !(t
->base_opcode
== 0xfc7
6340 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
6341 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6342 || (i
.suffix
== LONG_MNEM_SUFFIX
6343 && !cpu_arch_flags
.bitfield
.cpui386
))
6345 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6346 && !intel_float_operand (t
->name
))
6347 : intel_float_operand (t
->name
) != 2)
6348 && (t
->operands
== i
.imm_operands
6349 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6350 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6351 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6352 || (operand_types
[j
].bitfield
.class != RegMMX
6353 && operand_types
[j
].bitfield
.class != RegSIMD
6354 && operand_types
[j
].bitfield
.class != RegMask
))
6355 && !t
->opcode_modifier
.sib
)
6358 /* Do not verify operands when there are none. */
6361 if (VEX_check_encoding (t
))
6363 specific_error
= i
.error
;
6367 /* We've found a match; break out of loop. */
6371 if (!t
->opcode_modifier
.jump
6372 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6374 /* There should be only one Disp operand. */
6375 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6376 if (operand_type_check (operand_types
[j
], disp
))
6378 if (j
< MAX_OPERANDS
)
6380 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6382 addr_prefix_disp
= j
;
6384 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6385 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6389 override
= !override
;
6392 if (operand_types
[j
].bitfield
.disp32
6393 && operand_types
[j
].bitfield
.disp16
)
6395 operand_types
[j
].bitfield
.disp16
= override
;
6396 operand_types
[j
].bitfield
.disp32
= !override
;
6398 operand_types
[j
].bitfield
.disp32s
= 0;
6399 operand_types
[j
].bitfield
.disp64
= 0;
6403 if (operand_types
[j
].bitfield
.disp32s
6404 || operand_types
[j
].bitfield
.disp64
)
6406 operand_types
[j
].bitfield
.disp64
&= !override
;
6407 operand_types
[j
].bitfield
.disp32s
&= !override
;
6408 operand_types
[j
].bitfield
.disp32
= override
;
6410 operand_types
[j
].bitfield
.disp16
= 0;
6416 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6417 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6420 /* We check register size if needed. */
6421 if (t
->opcode_modifier
.checkregsize
)
6423 check_register
= (1 << t
->operands
) - 1;
6425 check_register
&= ~(1 << i
.broadcast
->operand
);
6430 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6431 switch (t
->operands
)
6434 if (!operand_type_match (overlap0
, i
.types
[0]))
6438 /* xchg %eax, %eax is a special case. It is an alias for nop
6439 only in 32bit mode and we can use opcode 0x90. In 64bit
6440 mode, we can't use 0x90 for xchg %eax, %eax since it should
6441 zero-extend %eax to %rax. */
6442 if (flag_code
== CODE_64BIT
6443 && t
->base_opcode
== 0x90
6444 && i
.types
[0].bitfield
.instance
== Accum
6445 && i
.types
[0].bitfield
.dword
6446 && i
.types
[1].bitfield
.instance
== Accum
6447 && i
.types
[1].bitfield
.dword
)
6449 /* xrelease mov %eax, <disp> is another special case. It must not
6450 match the accumulator-only encoding of mov. */
6451 if (flag_code
!= CODE_64BIT
6453 && t
->base_opcode
== 0xa0
6454 && i
.types
[0].bitfield
.instance
== Accum
6455 && (i
.flags
[1] & Operand_Mem
))
6460 if (!(size_match
& MATCH_STRAIGHT
))
6462 /* Reverse direction of operands if swapping is possible in the first
6463 place (operands need to be symmetric) and
6464 - the load form is requested, and the template is a store form,
6465 - the store form is requested, and the template is a load form,
6466 - the non-default (swapped) form is requested. */
6467 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6468 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6469 && !operand_type_all_zero (&overlap1
))
6470 switch (i
.dir_encoding
)
6472 case dir_encoding_load
:
6473 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6474 || t
->opcode_modifier
.regmem
)
6478 case dir_encoding_store
:
6479 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6480 && !t
->opcode_modifier
.regmem
)
6484 case dir_encoding_swap
:
6487 case dir_encoding_default
:
6490 /* If we want store form, we skip the current load. */
6491 if ((i
.dir_encoding
== dir_encoding_store
6492 || i
.dir_encoding
== dir_encoding_swap
)
6493 && i
.mem_operands
== 0
6494 && t
->opcode_modifier
.load
)
6499 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6500 if (!operand_type_match (overlap0
, i
.types
[0])
6501 || !operand_type_match (overlap1
, i
.types
[1])
6502 || ((check_register
& 3) == 3
6503 && !operand_type_register_match (i
.types
[0],
6508 /* Check if other direction is valid ... */
6509 if (!t
->opcode_modifier
.d
)
6513 if (!(size_match
& MATCH_REVERSE
))
6515 /* Try reversing direction of operands. */
6516 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6517 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6518 if (!operand_type_match (overlap0
, i
.types
[0])
6519 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6521 && !operand_type_register_match (i
.types
[0],
6522 operand_types
[i
.operands
- 1],
6523 i
.types
[i
.operands
- 1],
6526 /* Does not match either direction. */
6529 /* found_reverse_match holds which of D or FloatR
6531 if (!t
->opcode_modifier
.d
)
6532 found_reverse_match
= 0;
6533 else if (operand_types
[0].bitfield
.tbyte
)
6534 found_reverse_match
= Opcode_FloatD
;
6535 else if (operand_types
[0].bitfield
.xmmword
6536 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6537 || operand_types
[0].bitfield
.class == RegMMX
6538 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6539 || is_any_vex_encoding(t
))
6540 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6541 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6543 found_reverse_match
= Opcode_D
;
6544 if (t
->opcode_modifier
.floatr
)
6545 found_reverse_match
|= Opcode_FloatR
;
6549 /* Found a forward 2 operand match here. */
6550 switch (t
->operands
)
6553 overlap4
= operand_type_and (i
.types
[4],
6557 overlap3
= operand_type_and (i
.types
[3],
6561 overlap2
= operand_type_and (i
.types
[2],
6566 switch (t
->operands
)
6569 if (!operand_type_match (overlap4
, i
.types
[4])
6570 || !operand_type_register_match (i
.types
[3],
6577 if (!operand_type_match (overlap3
, i
.types
[3])
6578 || ((check_register
& 0xa) == 0xa
6579 && !operand_type_register_match (i
.types
[1],
6583 || ((check_register
& 0xc) == 0xc
6584 && !operand_type_register_match (i
.types
[2],
6591 /* Here we make use of the fact that there are no
6592 reverse match 3 operand instructions. */
6593 if (!operand_type_match (overlap2
, i
.types
[2])
6594 || ((check_register
& 5) == 5
6595 && !operand_type_register_match (i
.types
[0],
6599 || ((check_register
& 6) == 6
6600 && !operand_type_register_match (i
.types
[1],
6608 /* Found either forward/reverse 2, 3 or 4 operand match here:
6609 slip through to break. */
6612 /* Check if vector operands are valid. */
6613 if (check_VecOperands (t
))
6615 specific_error
= i
.error
;
6619 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6620 if (VEX_check_encoding (t
))
6622 specific_error
= i
.error
;
6626 /* We've found a match; break out of loop. */
6630 if (t
== current_templates
->end
)
6632 /* We found no match. */
6633 const char *err_msg
;
6634 switch (specific_error
? specific_error
: i
.error
)
6638 case operand_size_mismatch
:
6639 err_msg
= _("operand size mismatch");
6641 case operand_type_mismatch
:
6642 err_msg
= _("operand type mismatch");
6644 case register_type_mismatch
:
6645 err_msg
= _("register type mismatch");
6647 case number_of_operands_mismatch
:
6648 err_msg
= _("number of operands mismatch");
6650 case invalid_instruction_suffix
:
6651 err_msg
= _("invalid instruction suffix");
6654 err_msg
= _("constant doesn't fit in 4 bits");
6656 case unsupported_with_intel_mnemonic
:
6657 err_msg
= _("unsupported with Intel mnemonic");
6659 case unsupported_syntax
:
6660 err_msg
= _("unsupported syntax");
6663 as_bad (_("unsupported instruction `%s'"),
6664 current_templates
->start
->name
);
6666 case invalid_sib_address
:
6667 err_msg
= _("invalid SIB address");
6669 case invalid_vsib_address
:
6670 err_msg
= _("invalid VSIB address");
6672 case invalid_vector_register_set
:
6673 err_msg
= _("mask, index, and destination registers must be distinct");
6675 case invalid_tmm_register_set
:
6676 err_msg
= _("all tmm registers must be distinct");
6678 case unsupported_vector_index_register
:
6679 err_msg
= _("unsupported vector index register");
6681 case unsupported_broadcast
:
6682 err_msg
= _("unsupported broadcast");
6684 case broadcast_needed
:
6685 err_msg
= _("broadcast is needed for operand of such type");
6687 case unsupported_masking
:
6688 err_msg
= _("unsupported masking");
6690 case mask_not_on_destination
:
6691 err_msg
= _("mask not on destination operand");
6693 case no_default_mask
:
6694 err_msg
= _("default mask isn't allowed");
6696 case unsupported_rc_sae
:
6697 err_msg
= _("unsupported static rounding/sae");
6699 case rc_sae_operand_not_last_imm
:
6701 err_msg
= _("RC/SAE operand must precede immediate operands");
6703 err_msg
= _("RC/SAE operand must follow immediate operands");
6705 case invalid_register_operand
:
6706 err_msg
= _("invalid register operand");
6709 as_bad (_("%s for `%s'"), err_msg
,
6710 current_templates
->start
->name
);
6714 if (!quiet_warnings
)
6717 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6718 as_warn (_("indirect %s without `*'"), t
->name
);
6720 if (t
->opcode_modifier
.isprefix
6721 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6723 /* Warn them that a data or address size prefix doesn't
6724 affect assembly of the next line of code. */
6725 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6729 /* Copy the template we found. */
6732 if (addr_prefix_disp
!= -1)
6733 i
.tm
.operand_types
[addr_prefix_disp
]
6734 = operand_types
[addr_prefix_disp
];
6736 if (found_reverse_match
)
6738 /* If we found a reverse match we must alter the opcode direction
6739 bit and clear/flip the regmem modifier one. found_reverse_match
6740 holds bits to change (different for int & float insns). */
6742 i
.tm
.base_opcode
^= found_reverse_match
;
6744 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6745 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6747 /* Certain SIMD insns have their load forms specified in the opcode
6748 table, and hence we need to _set_ RegMem instead of clearing it.
6749 We need to avoid setting the bit though on insns like KMOVW. */
6750 i
.tm
.opcode_modifier
.regmem
6751 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6752 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6753 && !i
.tm
.opcode_modifier
.regmem
;
6762 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6763 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6765 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6767 as_bad (_("`%s' operand %u must use `%ses' segment"),
6769 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6774 /* There's only ever one segment override allowed per instruction.
6775 This instruction possibly has a legal segment override on the
6776 second operand, so copy the segment to where non-string
6777 instructions store it, allowing common code. */
6778 i
.seg
[op
] = i
.seg
[1];
6784 process_suffix (void)
6786 bfd_boolean is_crc32
= FALSE
;
6788 /* If matched instruction specifies an explicit instruction mnemonic
6790 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6791 i
.suffix
= WORD_MNEM_SUFFIX
;
6792 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6793 i
.suffix
= LONG_MNEM_SUFFIX
;
6794 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6795 i
.suffix
= QWORD_MNEM_SUFFIX
;
6796 else if (i
.reg_operands
6797 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6798 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6800 unsigned int numop
= i
.operands
;
6802 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6803 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6805 /* movsx/movzx want only their source operand considered here, for the
6806 ambiguity checking below. The suffix will be replaced afterwards
6807 to represent the destination (register). */
6808 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6809 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6812 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6813 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6816 /* If there's no instruction mnemonic suffix we try to invent one
6817 based on GPR operands. */
6820 /* We take i.suffix from the last register operand specified,
6821 Destination register type is more significant than source
6822 register type. crc32 in SSE4.2 prefers source register
6824 unsigned int op
= is_crc32
? 1 : i
.operands
;
6827 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6828 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6830 if (i
.types
[op
].bitfield
.class != Reg
)
6832 if (i
.types
[op
].bitfield
.byte
)
6833 i
.suffix
= BYTE_MNEM_SUFFIX
;
6834 else if (i
.types
[op
].bitfield
.word
)
6835 i
.suffix
= WORD_MNEM_SUFFIX
;
6836 else if (i
.types
[op
].bitfield
.dword
)
6837 i
.suffix
= LONG_MNEM_SUFFIX
;
6838 else if (i
.types
[op
].bitfield
.qword
)
6839 i
.suffix
= QWORD_MNEM_SUFFIX
;
6845 /* As an exception, movsx/movzx silently default to a byte source
6847 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6848 && !i
.suffix
&& !intel_syntax
)
6849 i
.suffix
= BYTE_MNEM_SUFFIX
;
6851 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6854 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6855 && i
.tm
.opcode_modifier
.no_bsuf
)
6857 else if (!check_byte_reg ())
6860 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6863 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6864 && i
.tm
.opcode_modifier
.no_lsuf
6865 && !i
.tm
.opcode_modifier
.todword
6866 && !i
.tm
.opcode_modifier
.toqword
)
6868 else if (!check_long_reg ())
6871 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6874 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6875 && i
.tm
.opcode_modifier
.no_qsuf
6876 && !i
.tm
.opcode_modifier
.todword
6877 && !i
.tm
.opcode_modifier
.toqword
)
6879 else if (!check_qword_reg ())
6882 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6885 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6886 && i
.tm
.opcode_modifier
.no_wsuf
)
6888 else if (!check_word_reg ())
6891 else if (intel_syntax
6892 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6893 /* Do nothing if the instruction is going to ignore the prefix. */
6898 /* Undo the movsx/movzx change done above. */
6901 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6904 i
.suffix
= stackop_size
;
6905 if (stackop_size
== LONG_MNEM_SUFFIX
)
6907 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6908 .code16gcc directive to support 16-bit mode with
6909 32-bit address. For IRET without a suffix, generate
6910 16-bit IRET (opcode 0xcf) to return from an interrupt
6912 if (i
.tm
.base_opcode
== 0xcf)
6914 i
.suffix
= WORD_MNEM_SUFFIX
;
6915 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6917 /* Warn about changed behavior for segment register push/pop. */
6918 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6919 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6924 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6925 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6926 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6927 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6928 && i
.tm
.extension_opcode
<= 3)))
6933 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6935 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6936 || i
.tm
.opcode_modifier
.no_lsuf
)
6937 i
.suffix
= QWORD_MNEM_SUFFIX
;
6942 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6943 i
.suffix
= LONG_MNEM_SUFFIX
;
6946 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6947 i
.suffix
= WORD_MNEM_SUFFIX
;
6953 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6954 /* Also cover lret/retf/iret in 64-bit mode. */
6955 || (flag_code
== CODE_64BIT
6956 && !i
.tm
.opcode_modifier
.no_lsuf
6957 && !i
.tm
.opcode_modifier
.no_qsuf
))
6958 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6959 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6960 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6961 /* Accept FLDENV et al without suffix. */
6962 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6964 unsigned int suffixes
, evex
= 0;
6966 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6967 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6969 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6971 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6973 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6975 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6978 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6979 also suitable for AT&T syntax mode, it was requested that this be
6980 restricted to just Intel syntax. */
6981 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6985 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6987 if (is_evex_encoding (&i
.tm
)
6988 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6990 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6991 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6992 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6993 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6994 if (!i
.tm
.opcode_modifier
.evex
6995 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6996 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6999 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7000 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7001 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7004 /* Any properly sized operand disambiguates the insn. */
7005 if (i
.types
[op
].bitfield
.xmmword
7006 || i
.types
[op
].bitfield
.ymmword
7007 || i
.types
[op
].bitfield
.zmmword
)
7009 suffixes
&= ~(7 << 6);
7014 if ((i
.flags
[op
] & Operand_Mem
)
7015 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7017 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7019 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7021 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7023 if (is_evex_encoding (&i
.tm
))
7029 /* Are multiple suffixes / operand sizes allowed? */
7030 if (suffixes
& (suffixes
- 1))
7033 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7034 || operand_check
== check_error
))
7036 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7039 if (operand_check
== check_error
)
7041 as_bad (_("no instruction mnemonic suffix given and "
7042 "no register operands; can't size `%s'"), i
.tm
.name
);
7045 if (operand_check
== check_warning
)
7046 as_warn (_("%s; using default for `%s'"),
7048 ? _("ambiguous operand size")
7049 : _("no instruction mnemonic suffix given and "
7050 "no register operands"),
7053 if (i
.tm
.opcode_modifier
.floatmf
)
7054 i
.suffix
= SHORT_MNEM_SUFFIX
;
7055 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7056 || (i
.tm
.base_opcode
== 0x63
7057 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7058 /* handled below */;
7060 i
.tm
.opcode_modifier
.evex
= evex
;
7061 else if (flag_code
== CODE_16BIT
)
7062 i
.suffix
= WORD_MNEM_SUFFIX
;
7063 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7064 i
.suffix
= LONG_MNEM_SUFFIX
;
7066 i
.suffix
= QWORD_MNEM_SUFFIX
;
7070 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7071 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7073 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7074 In AT&T syntax, if there is no suffix (warned about above), the default
7075 will be byte extension. */
7076 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7077 i
.tm
.base_opcode
|= 1;
7079 /* For further processing, the suffix should represent the destination
7080 (register). This is already the case when one was used with
7081 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7082 no suffix to begin with. */
7083 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7085 if (i
.types
[1].bitfield
.word
)
7086 i
.suffix
= WORD_MNEM_SUFFIX
;
7087 else if (i
.types
[1].bitfield
.qword
)
7088 i
.suffix
= QWORD_MNEM_SUFFIX
;
7090 i
.suffix
= LONG_MNEM_SUFFIX
;
7092 i
.tm
.opcode_modifier
.w
= 0;
7096 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7097 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7098 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7100 /* Change the opcode based on the operand size given by i.suffix. */
7103 /* Size floating point instruction. */
7104 case LONG_MNEM_SUFFIX
:
7105 if (i
.tm
.opcode_modifier
.floatmf
)
7107 i
.tm
.base_opcode
^= 4;
7111 case WORD_MNEM_SUFFIX
:
7112 case QWORD_MNEM_SUFFIX
:
7113 /* It's not a byte, select word/dword operation. */
7114 if (i
.tm
.opcode_modifier
.w
)
7117 i
.tm
.base_opcode
|= 8;
7119 i
.tm
.base_opcode
|= 1;
7122 case SHORT_MNEM_SUFFIX
:
7123 /* Now select between word & dword operations via the operand
7124 size prefix, except for instructions that will ignore this
7126 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7127 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7128 && !i
.tm
.opcode_modifier
.floatmf
7129 && !is_any_vex_encoding (&i
.tm
)
7130 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7131 || (flag_code
== CODE_64BIT
7132 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7134 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7136 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7137 prefix
= ADDR_PREFIX_OPCODE
;
7139 if (!add_prefix (prefix
))
7143 /* Set mode64 for an operand. */
7144 if (i
.suffix
== QWORD_MNEM_SUFFIX
7145 && flag_code
== CODE_64BIT
7146 && !i
.tm
.opcode_modifier
.norex64
7147 && !i
.tm
.opcode_modifier
.vexw
7148 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7150 && ! (i
.operands
== 2
7151 && i
.tm
.base_opcode
== 0x90
7152 && i
.tm
.extension_opcode
== None
7153 && i
.types
[0].bitfield
.instance
== Accum
7154 && i
.types
[0].bitfield
.qword
7155 && i
.types
[1].bitfield
.instance
== Accum
7156 && i
.types
[1].bitfield
.qword
))
7162 /* Select word/dword/qword operation with explicit data sizing prefix
7163 when there are no suitable register operands. */
7164 if (i
.tm
.opcode_modifier
.w
7165 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7167 || (i
.reg_operands
== 1
7169 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7171 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7172 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7175 i
.tm
.base_opcode
|= 1;
7179 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7181 gas_assert (!i
.suffix
);
7182 gas_assert (i
.reg_operands
);
7184 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7187 /* The address size override prefix changes the size of the
7189 if (flag_code
== CODE_64BIT
7190 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7192 as_bad (_("16-bit addressing unavailable for `%s'"),
7197 if ((flag_code
== CODE_32BIT
7198 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7199 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7200 && !add_prefix (ADDR_PREFIX_OPCODE
))
7205 /* Check invalid register operand when the address size override
7206 prefix changes the size of register operands. */
7208 enum { need_word
, need_dword
, need_qword
} need
;
7210 /* Check the register operand for the address size prefix if
7211 the memory operand has no real registers, like symbol, DISP
7213 if (i
.mem_operands
== 1
7214 && i
.reg_operands
== 1
7216 && i
.types
[1].bitfield
.class == Reg
7217 && (flag_code
== CODE_32BIT
7218 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7219 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7220 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7222 && i
.base_reg
->reg_num
== RegIP
7223 && i
.base_reg
->reg_type
.bitfield
.qword
))
7224 && !add_prefix (ADDR_PREFIX_OPCODE
))
7227 if (flag_code
== CODE_32BIT
)
7228 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7229 else if (i
.prefix
[ADDR_PREFIX
])
7232 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7234 for (op
= 0; op
< i
.operands
; op
++)
7236 if (i
.types
[op
].bitfield
.class != Reg
)
7242 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7246 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7250 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7255 as_bad (_("invalid register operand size for `%s'"),
7266 check_byte_reg (void)
7270 for (op
= i
.operands
; --op
>= 0;)
7272 /* Skip non-register operands. */
7273 if (i
.types
[op
].bitfield
.class != Reg
)
7276 /* If this is an eight bit register, it's OK. If it's the 16 or
7277 32 bit version of an eight bit register, we will just use the
7278 low portion, and that's OK too. */
7279 if (i
.types
[op
].bitfield
.byte
)
7282 /* I/O port address operands are OK too. */
7283 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7284 && i
.tm
.operand_types
[op
].bitfield
.word
)
7287 /* crc32 only wants its source operand checked here. */
7288 if (i
.tm
.base_opcode
== 0xf38f0
7289 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7293 /* Any other register is bad. */
7294 as_bad (_("`%s%s' not allowed with `%s%c'"),
7295 register_prefix
, i
.op
[op
].regs
->reg_name
,
7296 i
.tm
.name
, i
.suffix
);
7303 check_long_reg (void)
7307 for (op
= i
.operands
; --op
>= 0;)
7308 /* Skip non-register operands. */
7309 if (i
.types
[op
].bitfield
.class != Reg
)
7311 /* Reject eight bit registers, except where the template requires
7312 them. (eg. movzb) */
7313 else if (i
.types
[op
].bitfield
.byte
7314 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7315 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7316 && (i
.tm
.operand_types
[op
].bitfield
.word
7317 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7319 as_bad (_("`%s%s' not allowed with `%s%c'"),
7321 i
.op
[op
].regs
->reg_name
,
7326 /* Error if the e prefix on a general reg is missing. */
7327 else if (i
.types
[op
].bitfield
.word
7328 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7329 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7330 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7332 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7333 register_prefix
, i
.op
[op
].regs
->reg_name
,
7337 /* Warn if the r prefix on a general reg is present. */
7338 else if (i
.types
[op
].bitfield
.qword
7339 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7340 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7341 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7344 && i
.tm
.opcode_modifier
.toqword
7345 && i
.types
[0].bitfield
.class != RegSIMD
)
7347 /* Convert to QWORD. We want REX byte. */
7348 i
.suffix
= QWORD_MNEM_SUFFIX
;
7352 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7353 register_prefix
, i
.op
[op
].regs
->reg_name
,
7362 check_qword_reg (void)
7366 for (op
= i
.operands
; --op
>= 0; )
7367 /* Skip non-register operands. */
7368 if (i
.types
[op
].bitfield
.class != Reg
)
7370 /* Reject eight bit registers, except where the template requires
7371 them. (eg. movzb) */
7372 else if (i
.types
[op
].bitfield
.byte
7373 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7374 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7375 && (i
.tm
.operand_types
[op
].bitfield
.word
7376 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7378 as_bad (_("`%s%s' not allowed with `%s%c'"),
7380 i
.op
[op
].regs
->reg_name
,
7385 /* Warn if the r prefix on a general reg is missing. */
7386 else if ((i
.types
[op
].bitfield
.word
7387 || i
.types
[op
].bitfield
.dword
)
7388 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7389 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7390 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7392 /* Prohibit these changes in the 64bit mode, since the
7393 lowering is more complicated. */
7395 && i
.tm
.opcode_modifier
.todword
7396 && i
.types
[0].bitfield
.class != RegSIMD
)
7398 /* Convert to DWORD. We don't want REX byte. */
7399 i
.suffix
= LONG_MNEM_SUFFIX
;
7403 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7404 register_prefix
, i
.op
[op
].regs
->reg_name
,
7413 check_word_reg (void)
7416 for (op
= i
.operands
; --op
>= 0;)
7417 /* Skip non-register operands. */
7418 if (i
.types
[op
].bitfield
.class != Reg
)
7420 /* Reject eight bit registers, except where the template requires
7421 them. (eg. movzb) */
7422 else if (i
.types
[op
].bitfield
.byte
7423 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7424 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7425 && (i
.tm
.operand_types
[op
].bitfield
.word
7426 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7428 as_bad (_("`%s%s' not allowed with `%s%c'"),
7430 i
.op
[op
].regs
->reg_name
,
7435 /* Error if the e or r prefix on a general reg is present. */
7436 else if ((i
.types
[op
].bitfield
.dword
7437 || i
.types
[op
].bitfield
.qword
)
7438 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7439 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7440 && i
.tm
.operand_types
[op
].bitfield
.word
)
7442 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7443 register_prefix
, i
.op
[op
].regs
->reg_name
,
7451 update_imm (unsigned int j
)
7453 i386_operand_type overlap
= i
.types
[j
];
7454 if ((overlap
.bitfield
.imm8
7455 || overlap
.bitfield
.imm8s
7456 || overlap
.bitfield
.imm16
7457 || overlap
.bitfield
.imm32
7458 || overlap
.bitfield
.imm32s
7459 || overlap
.bitfield
.imm64
)
7460 && !operand_type_equal (&overlap
, &imm8
)
7461 && !operand_type_equal (&overlap
, &imm8s
)
7462 && !operand_type_equal (&overlap
, &imm16
)
7463 && !operand_type_equal (&overlap
, &imm32
)
7464 && !operand_type_equal (&overlap
, &imm32s
)
7465 && !operand_type_equal (&overlap
, &imm64
))
7469 i386_operand_type temp
;
7471 operand_type_set (&temp
, 0);
7472 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7474 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7475 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7477 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7478 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7479 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7481 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7482 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7485 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7488 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7489 || operand_type_equal (&overlap
, &imm16_32
)
7490 || operand_type_equal (&overlap
, &imm16_32s
))
7492 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7497 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7498 overlap
= operand_type_and (overlap
, imm32s
);
7499 else if (i
.prefix
[DATA_PREFIX
])
7500 overlap
= operand_type_and (overlap
,
7501 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7502 if (!operand_type_equal (&overlap
, &imm8
)
7503 && !operand_type_equal (&overlap
, &imm8s
)
7504 && !operand_type_equal (&overlap
, &imm16
)
7505 && !operand_type_equal (&overlap
, &imm32
)
7506 && !operand_type_equal (&overlap
, &imm32s
)
7507 && !operand_type_equal (&overlap
, &imm64
))
7509 as_bad (_("no instruction mnemonic suffix given; "
7510 "can't determine immediate size"));
7514 i
.types
[j
] = overlap
;
7524 /* Update the first 2 immediate operands. */
7525 n
= i
.operands
> 2 ? 2 : i
.operands
;
7528 for (j
= 0; j
< n
; j
++)
7529 if (update_imm (j
) == 0)
7532 /* The 3rd operand can't be immediate operand. */
7533 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7540 process_operands (void)
7542 /* Default segment register this instruction will use for memory
7543 accesses. 0 means unknown. This is only for optimizing out
7544 unnecessary segment overrides. */
7545 const seg_entry
*default_seg
= 0;
7547 if (i
.tm
.opcode_modifier
.sse2avx
)
7549 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7551 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7552 i
.prefix
[REX_PREFIX
] = 0;
7555 /* ImmExt should be processed after SSE2AVX. */
7556 else if (i
.tm
.opcode_modifier
.immext
)
7559 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7561 unsigned int dupl
= i
.operands
;
7562 unsigned int dest
= dupl
- 1;
7565 /* The destination must be an xmm register. */
7566 gas_assert (i
.reg_operands
7567 && MAX_OPERANDS
> dupl
7568 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7570 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7571 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7573 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7575 /* Keep xmm0 for instructions with VEX prefix and 3
7577 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7578 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7583 /* We remove the first xmm0 and keep the number of
7584 operands unchanged, which in fact duplicates the
7586 for (j
= 1; j
< i
.operands
; j
++)
7588 i
.op
[j
- 1] = i
.op
[j
];
7589 i
.types
[j
- 1] = i
.types
[j
];
7590 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7591 i
.flags
[j
- 1] = i
.flags
[j
];
7595 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7597 gas_assert ((MAX_OPERANDS
- 1) > dupl
7598 && (i
.tm
.opcode_modifier
.vexsources
7601 /* Add the implicit xmm0 for instructions with VEX prefix
7603 for (j
= i
.operands
; j
> 0; j
--)
7605 i
.op
[j
] = i
.op
[j
- 1];
7606 i
.types
[j
] = i
.types
[j
- 1];
7607 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7608 i
.flags
[j
] = i
.flags
[j
- 1];
7611 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7612 i
.types
[0] = regxmm
;
7613 i
.tm
.operand_types
[0] = regxmm
;
7616 i
.reg_operands
+= 2;
7621 i
.op
[dupl
] = i
.op
[dest
];
7622 i
.types
[dupl
] = i
.types
[dest
];
7623 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7624 i
.flags
[dupl
] = i
.flags
[dest
];
7633 i
.op
[dupl
] = i
.op
[dest
];
7634 i
.types
[dupl
] = i
.types
[dest
];
7635 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7636 i
.flags
[dupl
] = i
.flags
[dest
];
7639 if (i
.tm
.opcode_modifier
.immext
)
7642 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7643 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7647 for (j
= 1; j
< i
.operands
; j
++)
7649 i
.op
[j
- 1] = i
.op
[j
];
7650 i
.types
[j
- 1] = i
.types
[j
];
7652 /* We need to adjust fields in i.tm since they are used by
7653 build_modrm_byte. */
7654 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7656 i
.flags
[j
- 1] = i
.flags
[j
];
7663 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7665 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7667 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7668 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7669 regnum
= register_number (i
.op
[1].regs
);
7670 first_reg_in_group
= regnum
& ~3;
7671 last_reg_in_group
= first_reg_in_group
+ 3;
7672 if (regnum
!= first_reg_in_group
)
7673 as_warn (_("source register `%s%s' implicitly denotes"
7674 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7675 register_prefix
, i
.op
[1].regs
->reg_name
,
7676 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7677 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7680 else if (i
.tm
.opcode_modifier
.regkludge
)
7682 /* The imul $imm, %reg instruction is converted into
7683 imul $imm, %reg, %reg, and the clr %reg instruction
7684 is converted into xor %reg, %reg. */
7686 unsigned int first_reg_op
;
7688 if (operand_type_check (i
.types
[0], reg
))
7692 /* Pretend we saw the extra register operand. */
7693 gas_assert (i
.reg_operands
== 1
7694 && i
.op
[first_reg_op
+ 1].regs
== 0);
7695 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7696 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7701 if (i
.tm
.opcode_modifier
.modrm
)
7703 /* The opcode is completed (modulo i.tm.extension_opcode which
7704 must be put into the modrm byte). Now, we make the modrm and
7705 index base bytes based on all the info we've collected. */
7707 default_seg
= build_modrm_byte ();
7709 else if (i
.types
[0].bitfield
.class == SReg
)
7711 if (flag_code
!= CODE_64BIT
7712 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7713 && i
.op
[0].regs
->reg_num
== 1
7714 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7715 && i
.op
[0].regs
->reg_num
< 4)
7717 as_bad (_("you can't `%s %s%s'"),
7718 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7721 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7723 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7724 i
.tm
.opcode_length
= 2;
7726 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7728 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7732 else if (i
.tm
.opcode_modifier
.isstring
)
7734 /* For the string instructions that allow a segment override
7735 on one of their operands, the default segment is ds. */
7738 else if (i
.short_form
)
7740 /* The register or float register operand is in operand
7742 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7744 /* Register goes in low 3 bits of opcode. */
7745 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7746 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7748 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7750 /* Warn about some common errors, but press on regardless.
7751 The first case can be generated by gcc (<= 2.8.1). */
7752 if (i
.operands
== 2)
7754 /* Reversed arguments on faddp, fsubp, etc. */
7755 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7756 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7757 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7761 /* Extraneous `l' suffix on fp insn. */
7762 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7763 register_prefix
, i
.op
[0].regs
->reg_name
);
7768 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7769 && i
.tm
.base_opcode
== 0x8d /* lea */
7770 && !is_any_vex_encoding(&i
.tm
))
7772 if (!quiet_warnings
)
7773 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7777 i
.prefix
[SEG_PREFIX
] = 0;
7781 /* If a segment was explicitly specified, and the specified segment
7782 is neither the default nor the one already recorded from a prefix,
7783 use an opcode prefix to select it. If we never figured out what
7784 the default segment is, then default_seg will be zero at this
7785 point, and the specified segment prefix will always be used. */
7787 && i
.seg
[0] != default_seg
7788 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7790 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7796 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7797 bfd_boolean do_sse2avx
)
7799 if (r
->reg_flags
& RegRex
)
7801 if (i
.rex
& rex_bit
)
7802 as_bad (_("same type of prefix used twice"));
7805 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7807 gas_assert (i
.vex
.register_specifier
== r
);
7808 i
.vex
.register_specifier
+= 8;
7811 if (r
->reg_flags
& RegVRex
)
7815 static const seg_entry
*
7816 build_modrm_byte (void)
7818 const seg_entry
*default_seg
= 0;
7819 unsigned int source
, dest
;
7822 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7825 unsigned int nds
, reg_slot
;
7828 dest
= i
.operands
- 1;
7831 /* There are 2 kinds of instructions:
7832 1. 5 operands: 4 register operands or 3 register operands
7833 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7834 VexW0 or VexW1. The destination must be either XMM, YMM or
7836 2. 4 operands: 4 register operands or 3 register operands
7837 plus 1 memory operand, with VexXDS. */
7838 gas_assert ((i
.reg_operands
== 4
7839 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7840 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7841 && i
.tm
.opcode_modifier
.vexw
7842 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7844 /* If VexW1 is set, the first non-immediate operand is the source and
7845 the second non-immediate one is encoded in the immediate operand. */
7846 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7848 source
= i
.imm_operands
;
7849 reg_slot
= i
.imm_operands
+ 1;
7853 source
= i
.imm_operands
+ 1;
7854 reg_slot
= i
.imm_operands
;
7857 if (i
.imm_operands
== 0)
7859 /* When there is no immediate operand, generate an 8bit
7860 immediate operand to encode the first operand. */
7861 exp
= &im_expressions
[i
.imm_operands
++];
7862 i
.op
[i
.operands
].imms
= exp
;
7863 i
.types
[i
.operands
] = imm8
;
7866 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7867 exp
->X_op
= O_constant
;
7868 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7869 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7873 gas_assert (i
.imm_operands
== 1);
7874 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7875 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7877 /* Turn on Imm8 again so that output_imm will generate it. */
7878 i
.types
[0].bitfield
.imm8
= 1;
7880 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7881 i
.op
[0].imms
->X_add_number
7882 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7883 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7886 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7887 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7892 /* i.reg_operands MUST be the number of real register operands;
7893 implicit registers do not count. If there are 3 register
7894 operands, it must be a instruction with VexNDS. For a
7895 instruction with VexNDD, the destination register is encoded
7896 in VEX prefix. If there are 4 register operands, it must be
7897 a instruction with VEX prefix and 3 sources. */
7898 if (i
.mem_operands
== 0
7899 && ((i
.reg_operands
== 2
7900 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7901 || (i
.reg_operands
== 3
7902 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7903 || (i
.reg_operands
== 4 && vex_3_sources
)))
7911 /* When there are 3 operands, one of them may be immediate,
7912 which may be the first or the last operand. Otherwise,
7913 the first operand must be shift count register (cl) or it
7914 is an instruction with VexNDS. */
7915 gas_assert (i
.imm_operands
== 1
7916 || (i
.imm_operands
== 0
7917 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7918 || (i
.types
[0].bitfield
.instance
== RegC
7919 && i
.types
[0].bitfield
.byte
))));
7920 if (operand_type_check (i
.types
[0], imm
)
7921 || (i
.types
[0].bitfield
.instance
== RegC
7922 && i
.types
[0].bitfield
.byte
))
7928 /* When there are 4 operands, the first two must be 8bit
7929 immediate operands. The source operand will be the 3rd
7932 For instructions with VexNDS, if the first operand
7933 an imm8, the source operand is the 2nd one. If the last
7934 operand is imm8, the source operand is the first one. */
7935 gas_assert ((i
.imm_operands
== 2
7936 && i
.types
[0].bitfield
.imm8
7937 && i
.types
[1].bitfield
.imm8
)
7938 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7939 && i
.imm_operands
== 1
7940 && (i
.types
[0].bitfield
.imm8
7941 || i
.types
[i
.operands
- 1].bitfield
.imm8
7943 if (i
.imm_operands
== 2)
7947 if (i
.types
[0].bitfield
.imm8
)
7954 if (is_evex_encoding (&i
.tm
))
7956 /* For EVEX instructions, when there are 5 operands, the
7957 first one must be immediate operand. If the second one
7958 is immediate operand, the source operand is the 3th
7959 one. If the last one is immediate operand, the source
7960 operand is the 2nd one. */
7961 gas_assert (i
.imm_operands
== 2
7962 && i
.tm
.opcode_modifier
.sae
7963 && operand_type_check (i
.types
[0], imm
));
7964 if (operand_type_check (i
.types
[1], imm
))
7966 else if (operand_type_check (i
.types
[4], imm
))
7980 /* RC/SAE operand could be between DEST and SRC. That happens
7981 when one operand is GPR and the other one is XMM/YMM/ZMM
7983 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7986 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7988 /* For instructions with VexNDS, the register-only source
7989 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7990 register. It is encoded in VEX prefix. */
7992 i386_operand_type op
;
7995 /* Swap two source operands if needed. */
7996 if (i
.tm
.opcode_modifier
.swapsources
)
8004 op
= i
.tm
.operand_types
[vvvv
];
8005 if ((dest
+ 1) >= i
.operands
8006 || ((op
.bitfield
.class != Reg
8007 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8008 && op
.bitfield
.class != RegSIMD
8009 && !operand_type_equal (&op
, ®mask
)))
8011 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8017 /* One of the register operands will be encoded in the i.rm.reg
8018 field, the other in the combined i.rm.mode and i.rm.regmem
8019 fields. If no form of this instruction supports a memory
8020 destination operand, then we assume the source operand may
8021 sometimes be a memory operand and so we need to store the
8022 destination in the i.rm.reg field. */
8023 if (!i
.tm
.opcode_modifier
.regmem
8024 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8026 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8027 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8028 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8029 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8033 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8034 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8035 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8036 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8038 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8040 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8043 add_prefix (LOCK_PREFIX_OPCODE
);
8047 { /* If it's not 2 reg operands... */
8052 unsigned int fake_zero_displacement
= 0;
8055 for (op
= 0; op
< i
.operands
; op
++)
8056 if (i
.flags
[op
] & Operand_Mem
)
8058 gas_assert (op
< i
.operands
);
8060 if (i
.tm
.opcode_modifier
.sib
)
8062 /* The index register of VSIB shouldn't be RegIZ. */
8063 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8064 && i
.index_reg
->reg_num
== RegIZ
)
8067 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8070 i
.sib
.base
= NO_BASE_REGISTER
;
8071 i
.sib
.scale
= i
.log2_scale_factor
;
8072 i
.types
[op
].bitfield
.disp8
= 0;
8073 i
.types
[op
].bitfield
.disp16
= 0;
8074 i
.types
[op
].bitfield
.disp64
= 0;
8075 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8077 /* Must be 32 bit */
8078 i
.types
[op
].bitfield
.disp32
= 1;
8079 i
.types
[op
].bitfield
.disp32s
= 0;
8083 i
.types
[op
].bitfield
.disp32
= 0;
8084 i
.types
[op
].bitfield
.disp32s
= 1;
8088 /* Since the mandatory SIB always has index register, so
8089 the code logic remains unchanged. The non-mandatory SIB
8090 without index register is allowed and will be handled
8094 if (i
.index_reg
->reg_num
== RegIZ
)
8095 i
.sib
.index
= NO_INDEX_REGISTER
;
8097 i
.sib
.index
= i
.index_reg
->reg_num
;
8098 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8104 if (i
.base_reg
== 0)
8107 if (!i
.disp_operands
)
8108 fake_zero_displacement
= 1;
8109 if (i
.index_reg
== 0)
8111 i386_operand_type newdisp
;
8113 /* Both check for VSIB and mandatory non-vector SIB. */
8114 gas_assert (!i
.tm
.opcode_modifier
.sib
8115 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8116 /* Operand is just <disp> */
8117 if (flag_code
== CODE_64BIT
)
8119 /* 64bit mode overwrites the 32bit absolute
8120 addressing by RIP relative addressing and
8121 absolute addressing is encoded by one of the
8122 redundant SIB forms. */
8123 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8124 i
.sib
.base
= NO_BASE_REGISTER
;
8125 i
.sib
.index
= NO_INDEX_REGISTER
;
8126 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8128 else if ((flag_code
== CODE_16BIT
)
8129 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8131 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8136 i
.rm
.regmem
= NO_BASE_REGISTER
;
8139 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8140 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8142 else if (!i
.tm
.opcode_modifier
.sib
)
8144 /* !i.base_reg && i.index_reg */
8145 if (i
.index_reg
->reg_num
== RegIZ
)
8146 i
.sib
.index
= NO_INDEX_REGISTER
;
8148 i
.sib
.index
= i
.index_reg
->reg_num
;
8149 i
.sib
.base
= NO_BASE_REGISTER
;
8150 i
.sib
.scale
= i
.log2_scale_factor
;
8151 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8152 i
.types
[op
].bitfield
.disp8
= 0;
8153 i
.types
[op
].bitfield
.disp16
= 0;
8154 i
.types
[op
].bitfield
.disp64
= 0;
8155 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8157 /* Must be 32 bit */
8158 i
.types
[op
].bitfield
.disp32
= 1;
8159 i
.types
[op
].bitfield
.disp32s
= 0;
8163 i
.types
[op
].bitfield
.disp32
= 0;
8164 i
.types
[op
].bitfield
.disp32s
= 1;
8166 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8170 /* RIP addressing for 64bit mode. */
8171 else if (i
.base_reg
->reg_num
== RegIP
)
8173 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8174 i
.rm
.regmem
= NO_BASE_REGISTER
;
8175 i
.types
[op
].bitfield
.disp8
= 0;
8176 i
.types
[op
].bitfield
.disp16
= 0;
8177 i
.types
[op
].bitfield
.disp32
= 0;
8178 i
.types
[op
].bitfield
.disp32s
= 1;
8179 i
.types
[op
].bitfield
.disp64
= 0;
8180 i
.flags
[op
] |= Operand_PCrel
;
8181 if (! i
.disp_operands
)
8182 fake_zero_displacement
= 1;
8184 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8186 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8187 switch (i
.base_reg
->reg_num
)
8190 if (i
.index_reg
== 0)
8192 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8193 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8197 if (i
.index_reg
== 0)
8200 if (operand_type_check (i
.types
[op
], disp
) == 0)
8202 /* fake (%bp) into 0(%bp) */
8203 if (i
.disp_encoding
== disp_encoding_16bit
)
8204 i
.types
[op
].bitfield
.disp16
= 1;
8206 i
.types
[op
].bitfield
.disp8
= 1;
8207 fake_zero_displacement
= 1;
8210 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8211 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8213 default: /* (%si) -> 4 or (%di) -> 5 */
8214 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8216 if (!fake_zero_displacement
8220 fake_zero_displacement
= 1;
8221 if (i
.disp_encoding
== disp_encoding_8bit
)
8222 i
.types
[op
].bitfield
.disp8
= 1;
8224 i
.types
[op
].bitfield
.disp16
= 1;
8226 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8228 else /* i.base_reg and 32/64 bit mode */
8230 if (flag_code
== CODE_64BIT
8231 && operand_type_check (i
.types
[op
], disp
))
8233 i
.types
[op
].bitfield
.disp16
= 0;
8234 i
.types
[op
].bitfield
.disp64
= 0;
8235 if (i
.prefix
[ADDR_PREFIX
] == 0)
8237 i
.types
[op
].bitfield
.disp32
= 0;
8238 i
.types
[op
].bitfield
.disp32s
= 1;
8242 i
.types
[op
].bitfield
.disp32
= 1;
8243 i
.types
[op
].bitfield
.disp32s
= 0;
8247 if (!i
.tm
.opcode_modifier
.sib
)
8248 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8249 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8251 i
.sib
.base
= i
.base_reg
->reg_num
;
8252 /* x86-64 ignores REX prefix bit here to avoid decoder
8254 if (!(i
.base_reg
->reg_flags
& RegRex
)
8255 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8256 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8258 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8260 fake_zero_displacement
= 1;
8261 if (i
.disp_encoding
== disp_encoding_32bit
)
8262 i
.types
[op
].bitfield
.disp32
= 1;
8264 i
.types
[op
].bitfield
.disp8
= 1;
8266 i
.sib
.scale
= i
.log2_scale_factor
;
8267 if (i
.index_reg
== 0)
8269 /* Only check for VSIB. */
8270 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8271 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8272 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8274 /* <disp>(%esp) becomes two byte modrm with no index
8275 register. We've already stored the code for esp
8276 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8277 Any base register besides %esp will not use the
8278 extra modrm byte. */
8279 i
.sib
.index
= NO_INDEX_REGISTER
;
8281 else if (!i
.tm
.opcode_modifier
.sib
)
8283 if (i
.index_reg
->reg_num
== RegIZ
)
8284 i
.sib
.index
= NO_INDEX_REGISTER
;
8286 i
.sib
.index
= i
.index_reg
->reg_num
;
8287 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8288 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8293 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8294 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8298 if (!fake_zero_displacement
8302 fake_zero_displacement
= 1;
8303 if (i
.disp_encoding
== disp_encoding_8bit
)
8304 i
.types
[op
].bitfield
.disp8
= 1;
8306 i
.types
[op
].bitfield
.disp32
= 1;
8308 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8312 if (fake_zero_displacement
)
8314 /* Fakes a zero displacement assuming that i.types[op]
8315 holds the correct displacement size. */
8318 gas_assert (i
.op
[op
].disps
== 0);
8319 exp
= &disp_expressions
[i
.disp_operands
++];
8320 i
.op
[op
].disps
= exp
;
8321 exp
->X_op
= O_constant
;
8322 exp
->X_add_number
= 0;
8323 exp
->X_add_symbol
= (symbolS
*) 0;
8324 exp
->X_op_symbol
= (symbolS
*) 0;
8332 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8334 if (operand_type_check (i
.types
[0], imm
))
8335 i
.vex
.register_specifier
= NULL
;
8338 /* VEX.vvvv encodes one of the sources when the first
8339 operand is not an immediate. */
8340 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8341 i
.vex
.register_specifier
= i
.op
[0].regs
;
8343 i
.vex
.register_specifier
= i
.op
[1].regs
;
8346 /* Destination is a XMM register encoded in the ModRM.reg
8348 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8349 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8352 /* ModRM.rm and VEX.B encodes the other source. */
8353 if (!i
.mem_operands
)
8357 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8358 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8360 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8362 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8366 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8368 i
.vex
.register_specifier
= i
.op
[2].regs
;
8369 if (!i
.mem_operands
)
8372 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8373 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8377 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8378 (if any) based on i.tm.extension_opcode. Again, we must be
8379 careful to make sure that segment/control/debug/test/MMX
8380 registers are coded into the i.rm.reg field. */
8381 else if (i
.reg_operands
)
8384 unsigned int vex_reg
= ~0;
8386 for (op
= 0; op
< i
.operands
; op
++)
8387 if (i
.types
[op
].bitfield
.class == Reg
8388 || i
.types
[op
].bitfield
.class == RegBND
8389 || i
.types
[op
].bitfield
.class == RegMask
8390 || i
.types
[op
].bitfield
.class == SReg
8391 || i
.types
[op
].bitfield
.class == RegCR
8392 || i
.types
[op
].bitfield
.class == RegDR
8393 || i
.types
[op
].bitfield
.class == RegTR
8394 || i
.types
[op
].bitfield
.class == RegSIMD
8395 || i
.types
[op
].bitfield
.class == RegMMX
)
8400 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8402 /* For instructions with VexNDS, the register-only
8403 source operand is encoded in VEX prefix. */
8404 gas_assert (mem
!= (unsigned int) ~0);
8409 gas_assert (op
< i
.operands
);
8413 /* Check register-only source operand when two source
8414 operands are swapped. */
8415 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8416 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8420 gas_assert (mem
== (vex_reg
+ 1)
8421 && op
< i
.operands
);
8426 gas_assert (vex_reg
< i
.operands
);
8430 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8432 /* For instructions with VexNDD, the register destination
8433 is encoded in VEX prefix. */
8434 if (i
.mem_operands
== 0)
8436 /* There is no memory operand. */
8437 gas_assert ((op
+ 2) == i
.operands
);
8442 /* There are only 2 non-immediate operands. */
8443 gas_assert (op
< i
.imm_operands
+ 2
8444 && i
.operands
== i
.imm_operands
+ 2);
8445 vex_reg
= i
.imm_operands
+ 1;
8449 gas_assert (op
< i
.operands
);
8451 if (vex_reg
!= (unsigned int) ~0)
8453 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8455 if ((type
->bitfield
.class != Reg
8456 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8457 && type
->bitfield
.class != RegSIMD
8458 && !operand_type_equal (type
, ®mask
))
8461 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8464 /* Don't set OP operand twice. */
8467 /* If there is an extension opcode to put here, the
8468 register number must be put into the regmem field. */
8469 if (i
.tm
.extension_opcode
!= None
)
8471 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8472 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8473 i
.tm
.opcode_modifier
.sse2avx
);
8477 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8478 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8479 i
.tm
.opcode_modifier
.sse2avx
);
8483 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8484 must set it to 3 to indicate this is a register operand
8485 in the regmem field. */
8486 if (!i
.mem_operands
)
8490 /* Fill in i.rm.reg field with extension opcode (if any). */
8491 if (i
.tm
.extension_opcode
!= None
)
8492 i
.rm
.reg
= i
.tm
.extension_opcode
;
8498 frag_opcode_byte (unsigned char byte
)
8500 if (now_seg
!= absolute_section
)
8501 FRAG_APPEND_1_CHAR (byte
);
8503 ++abs_section_offset
;
8507 flip_code16 (unsigned int code16
)
8509 gas_assert (i
.tm
.operands
== 1);
8511 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8512 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8513 || i
.tm
.operand_types
[0].bitfield
.disp32s
8514 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8519 output_branch (void)
8525 relax_substateT subtype
;
8529 if (now_seg
== absolute_section
)
8531 as_bad (_("relaxable branches not supported in absolute section"));
8535 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8536 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8539 if (i
.prefix
[DATA_PREFIX
] != 0)
8543 code16
^= flip_code16(code16
);
8545 /* Pentium4 branch hints. */
8546 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8547 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8552 if (i
.prefix
[REX_PREFIX
] != 0)
8558 /* BND prefixed jump. */
8559 if (i
.prefix
[BND_PREFIX
] != 0)
8565 if (i
.prefixes
!= 0)
8566 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8568 /* It's always a symbol; End frag & setup for relax.
8569 Make sure there is enough room in this frag for the largest
8570 instruction we may generate in md_convert_frag. This is 2
8571 bytes for the opcode and room for the prefix and largest
8573 frag_grow (prefix
+ 2 + 4);
8574 /* Prefix and 1 opcode byte go in fr_fix. */
8575 p
= frag_more (prefix
+ 1);
8576 if (i
.prefix
[DATA_PREFIX
] != 0)
8577 *p
++ = DATA_PREFIX_OPCODE
;
8578 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8579 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8580 *p
++ = i
.prefix
[SEG_PREFIX
];
8581 if (i
.prefix
[BND_PREFIX
] != 0)
8582 *p
++ = BND_PREFIX_OPCODE
;
8583 if (i
.prefix
[REX_PREFIX
] != 0)
8584 *p
++ = i
.prefix
[REX_PREFIX
];
8585 *p
= i
.tm
.base_opcode
;
8587 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8588 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8589 else if (cpu_arch_flags
.bitfield
.cpui386
)
8590 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8592 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8595 sym
= i
.op
[0].disps
->X_add_symbol
;
8596 off
= i
.op
[0].disps
->X_add_number
;
8598 if (i
.op
[0].disps
->X_op
!= O_constant
8599 && i
.op
[0].disps
->X_op
!= O_symbol
)
8601 /* Handle complex expressions. */
8602 sym
= make_expr_symbol (i
.op
[0].disps
);
8606 /* 1 possible extra opcode + 4 byte displacement go in var part.
8607 Pass reloc in fr_var. */
8608 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8612 /* Return TRUE iff PLT32 relocation should be used for branching to
8616 need_plt32_p (symbolS
*s
)
8618 /* PLT32 relocation is ELF only. */
8623 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8624 krtld support it. */
8628 /* Since there is no need to prepare for PLT branch on x86-64, we
8629 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8630 be used as a marker for 32-bit PC-relative branches. */
8637 /* Weak or undefined symbol need PLT32 relocation. */
8638 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8641 /* Non-global symbol doesn't need PLT32 relocation. */
8642 if (! S_IS_EXTERNAL (s
))
8645 /* Other global symbols need PLT32 relocation. NB: Symbol with
8646 non-default visibilities are treated as normal global symbol
8647 so that PLT32 relocation can be used as a marker for 32-bit
8648 PC-relative branches. It is useful for linker relaxation. */
8659 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8661 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8663 /* This is a loop or jecxz type instruction. */
8665 if (i
.prefix
[ADDR_PREFIX
] != 0)
8667 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8670 /* Pentium4 branch hints. */
8671 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8672 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8674 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8683 if (flag_code
== CODE_16BIT
)
8686 if (i
.prefix
[DATA_PREFIX
] != 0)
8688 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8690 code16
^= flip_code16(code16
);
8698 /* BND prefixed jump. */
8699 if (i
.prefix
[BND_PREFIX
] != 0)
8701 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8705 if (i
.prefix
[REX_PREFIX
] != 0)
8707 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8711 if (i
.prefixes
!= 0)
8712 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8714 if (now_seg
== absolute_section
)
8716 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8720 p
= frag_more (i
.tm
.opcode_length
+ size
);
8721 switch (i
.tm
.opcode_length
)
8724 *p
++ = i
.tm
.base_opcode
>> 8;
8727 *p
++ = i
.tm
.base_opcode
;
8733 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8735 && jump_reloc
== NO_RELOC
8736 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8737 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8740 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8742 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8743 i
.op
[0].disps
, 1, jump_reloc
);
8745 /* All jumps handled here are signed, but don't use a signed limit
8746 check for 32 and 16 bit jumps as we want to allow wrap around at
8747 4G and 64k respectively. */
8749 fixP
->fx_signed
= 1;
8753 output_interseg_jump (void)
8761 if (flag_code
== CODE_16BIT
)
8765 if (i
.prefix
[DATA_PREFIX
] != 0)
8772 gas_assert (!i
.prefix
[REX_PREFIX
]);
8778 if (i
.prefixes
!= 0)
8779 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8781 if (now_seg
== absolute_section
)
8783 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8787 /* 1 opcode; 2 segment; offset */
8788 p
= frag_more (prefix
+ 1 + 2 + size
);
8790 if (i
.prefix
[DATA_PREFIX
] != 0)
8791 *p
++ = DATA_PREFIX_OPCODE
;
8793 if (i
.prefix
[REX_PREFIX
] != 0)
8794 *p
++ = i
.prefix
[REX_PREFIX
];
8796 *p
++ = i
.tm
.base_opcode
;
8797 if (i
.op
[1].imms
->X_op
== O_constant
)
8799 offsetT n
= i
.op
[1].imms
->X_add_number
;
8802 && !fits_in_unsigned_word (n
)
8803 && !fits_in_signed_word (n
))
8805 as_bad (_("16-bit jump out of range"));
8808 md_number_to_chars (p
, n
, size
);
8811 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8812 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8815 if (i
.op
[0].imms
->X_op
== O_constant
)
8816 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8818 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8819 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8827 asection
*seg
= now_seg
;
8828 subsegT subseg
= now_subseg
;
8830 unsigned int alignment
, align_size_1
;
8831 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8832 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8833 unsigned int padding
;
8835 if (!IS_ELF
|| !x86_used_note
)
8838 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8840 /* The .note.gnu.property section layout:
8842 Field Length Contents
8845 n_descsz 4 The note descriptor size
8846 n_type 4 NT_GNU_PROPERTY_TYPE_0
8848 n_desc n_descsz The program property array
8852 /* Create the .note.gnu.property section. */
8853 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8854 bfd_set_section_flags (sec
,
8861 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8872 bfd_set_section_alignment (sec
, alignment
);
8873 elf_section_type (sec
) = SHT_NOTE
;
8875 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8877 isa_1_descsz_raw
= 4 + 4 + 4;
8878 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8879 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8881 feature_2_descsz_raw
= isa_1_descsz
;
8882 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8884 feature_2_descsz_raw
+= 4 + 4 + 4;
8885 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8886 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8889 descsz
= feature_2_descsz
;
8890 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8891 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8893 /* Write n_namsz. */
8894 md_number_to_chars (p
, (valueT
) 4, 4);
8896 /* Write n_descsz. */
8897 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8900 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8903 memcpy (p
+ 4 * 3, "GNU", 4);
8905 /* Write 4-byte type. */
8906 md_number_to_chars (p
+ 4 * 4,
8907 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8909 /* Write 4-byte data size. */
8910 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8912 /* Write 4-byte data. */
8913 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8915 /* Zero out paddings. */
8916 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8918 memset (p
+ 4 * 7, 0, padding
);
8920 /* Write 4-byte type. */
8921 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8922 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8924 /* Write 4-byte data size. */
8925 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8927 /* Write 4-byte data. */
8928 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8929 (valueT
) x86_feature_2_used
, 4);
8931 /* Zero out paddings. */
8932 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8934 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8936 /* We probably can't restore the current segment, for there likely
8939 subseg_set (seg
, subseg
);
8944 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8945 const char *frag_now_ptr
)
8947 unsigned int len
= 0;
8949 if (start_frag
!= frag_now
)
8951 const fragS
*fr
= start_frag
;
8956 } while (fr
&& fr
!= frag_now
);
8959 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8962 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8963 be macro-fused with conditional jumps.
8964 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8965 or is one of the following format:
8978 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8980 /* No RIP address. */
8981 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8984 /* No VEX/EVEX encoding. */
8985 if (is_any_vex_encoding (&i
.tm
))
8988 /* add, sub without add/sub m, imm. */
8989 if (i
.tm
.base_opcode
<= 5
8990 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8991 || ((i
.tm
.base_opcode
| 3) == 0x83
8992 && (i
.tm
.extension_opcode
== 0x5
8993 || i
.tm
.extension_opcode
== 0x0)))
8995 *mf_cmp_p
= mf_cmp_alu_cmp
;
8996 return !(i
.mem_operands
&& i
.imm_operands
);
8999 /* and without and m, imm. */
9000 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9001 || ((i
.tm
.base_opcode
| 3) == 0x83
9002 && i
.tm
.extension_opcode
== 0x4))
9004 *mf_cmp_p
= mf_cmp_test_and
;
9005 return !(i
.mem_operands
&& i
.imm_operands
);
9008 /* test without test m imm. */
9009 if ((i
.tm
.base_opcode
| 1) == 0x85
9010 || (i
.tm
.base_opcode
| 1) == 0xa9
9011 || ((i
.tm
.base_opcode
| 1) == 0xf7
9012 && i
.tm
.extension_opcode
== 0))
9014 *mf_cmp_p
= mf_cmp_test_and
;
9015 return !(i
.mem_operands
&& i
.imm_operands
);
9018 /* cmp without cmp m, imm. */
9019 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9020 || ((i
.tm
.base_opcode
| 3) == 0x83
9021 && (i
.tm
.extension_opcode
== 0x7)))
9023 *mf_cmp_p
= mf_cmp_alu_cmp
;
9024 return !(i
.mem_operands
&& i
.imm_operands
);
9027 /* inc, dec without inc/dec m. */
9028 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9029 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9030 || ((i
.tm
.base_opcode
| 1) == 0xff
9031 && i
.tm
.extension_opcode
<= 0x1))
9033 *mf_cmp_p
= mf_cmp_incdec
;
9034 return !i
.mem_operands
;
9040 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9043 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9045 /* NB: Don't work with COND_JUMP86 without i386. */
9046 if (!align_branch_power
9047 || now_seg
== absolute_section
9048 || !cpu_arch_flags
.bitfield
.cpui386
9049 || !(align_branch
& align_branch_fused_bit
))
9052 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9054 if (last_insn
.kind
== last_insn_other
9055 || last_insn
.seg
!= now_seg
)
9058 as_warn_where (last_insn
.file
, last_insn
.line
,
9059 _("`%s` skips -malign-branch-boundary on `%s`"),
9060 last_insn
.name
, i
.tm
.name
);
9066 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9069 add_branch_prefix_frag_p (void)
9071 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9072 to PadLock instructions since they include prefixes in opcode. */
9073 if (!align_branch_power
9074 || !align_branch_prefix_size
9075 || now_seg
== absolute_section
9076 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9077 || !cpu_arch_flags
.bitfield
.cpui386
)
9080 /* Don't add prefix if it is a prefix or there is no operand in case
9081 that segment prefix is special. */
9082 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9085 if (last_insn
.kind
== last_insn_other
9086 || last_insn
.seg
!= now_seg
)
9090 as_warn_where (last_insn
.file
, last_insn
.line
,
9091 _("`%s` skips -malign-branch-boundary on `%s`"),
9092 last_insn
.name
, i
.tm
.name
);
9097 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9100 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9101 enum mf_jcc_kind
*mf_jcc_p
)
9105 /* NB: Don't work with COND_JUMP86 without i386. */
9106 if (!align_branch_power
9107 || now_seg
== absolute_section
9108 || !cpu_arch_flags
.bitfield
.cpui386
)
9113 /* Check for jcc and direct jmp. */
9114 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9116 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9118 *branch_p
= align_branch_jmp
;
9119 add_padding
= align_branch
& align_branch_jmp_bit
;
9123 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9124 igore the lowest bit. */
9125 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9126 *branch_p
= align_branch_jcc
;
9127 if ((align_branch
& align_branch_jcc_bit
))
9131 else if (is_any_vex_encoding (&i
.tm
))
9133 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9136 *branch_p
= align_branch_ret
;
9137 if ((align_branch
& align_branch_ret_bit
))
9142 /* Check for indirect jmp, direct and indirect calls. */
9143 if (i
.tm
.base_opcode
== 0xe8)
9146 *branch_p
= align_branch_call
;
9147 if ((align_branch
& align_branch_call_bit
))
9150 else if (i
.tm
.base_opcode
== 0xff
9151 && (i
.tm
.extension_opcode
== 2
9152 || i
.tm
.extension_opcode
== 4))
9154 /* Indirect call and jmp. */
9155 *branch_p
= align_branch_indirect
;
9156 if ((align_branch
& align_branch_indirect_bit
))
9163 && (i
.op
[0].disps
->X_op
== O_symbol
9164 || (i
.op
[0].disps
->X_op
== O_subtract
9165 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9167 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9168 /* No padding to call to global or undefined tls_get_addr. */
9169 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9170 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9176 && last_insn
.kind
!= last_insn_other
9177 && last_insn
.seg
== now_seg
)
9180 as_warn_where (last_insn
.file
, last_insn
.line
,
9181 _("`%s` skips -malign-branch-boundary on `%s`"),
9182 last_insn
.name
, i
.tm
.name
);
9192 fragS
*insn_start_frag
;
9193 offsetT insn_start_off
;
9194 fragS
*fragP
= NULL
;
9195 enum align_branch_kind branch
= align_branch_none
;
9196 /* The initializer is arbitrary just to avoid uninitialized error.
9197 it's actually either assigned in add_branch_padding_frag_p
9198 or never be used. */
9199 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9202 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9204 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9205 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9206 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9208 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9209 || i
.tm
.cpu_flags
.bitfield
.cpu287
9210 || i
.tm
.cpu_flags
.bitfield
.cpu387
9211 || i
.tm
.cpu_flags
.bitfield
.cpu687
9212 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9213 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9215 if ((i
.xstate
& xstate_mmx
)
9216 || i
.tm
.base_opcode
== 0xf77 /* emms */
9217 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9218 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9222 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9223 i
.xstate
|= xstate_zmm
;
9224 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9225 i
.xstate
|= xstate_ymm
;
9226 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9227 i
.xstate
|= xstate_xmm
;
9230 /* vzeroall / vzeroupper */
9231 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9232 i
.xstate
|= xstate_ymm
;
9234 if ((i
.xstate
& xstate_xmm
)
9235 /* ldmxcsr / stmxcsr */
9236 || (i
.tm
.base_opcode
== 0xfae && i
.tm
.cpu_flags
.bitfield
.cpusse
)
9237 /* vldmxcsr / vstmxcsr */
9238 || (i
.tm
.base_opcode
== 0xae && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9239 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9240 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9241 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9243 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9244 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9245 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9246 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9247 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9248 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9249 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9250 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9251 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9252 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9253 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9254 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9255 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9256 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9258 if (x86_feature_2_used
9259 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9260 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9261 || (i
.tm
.base_opcode
== 0xfc7
9262 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
9263 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9264 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9265 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9266 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9267 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9268 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9269 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9270 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9271 /* LAHF-SAHF insns in 64-bit mode. */
9272 || (flag_code
== CODE_64BIT
9273 && (i
.tm
.base_opcode
| 1) == 0x9f))
9274 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9275 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9276 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9277 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9278 CpuAVX512DQ, LPW, TBM and AMX. */
9279 || (i
.tm
.opcode_modifier
.vex
9280 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9281 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9282 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9283 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9284 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9285 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9286 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9287 || i
.tm
.cpu_flags
.bitfield
.cpufma
9288 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9289 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9290 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9291 || (x86_feature_2_used
9292 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9293 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9294 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9295 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9296 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9297 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9298 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9299 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9300 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9302 || (i
.tm
.opcode_modifier
.evex
9303 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9304 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9305 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9306 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9310 /* Tie dwarf2 debug info to the address at the start of the insn.
9311 We can't do this after the insn has been output as the current
9312 frag may have been closed off. eg. by frag_var. */
9313 dwarf2_emit_insn (0);
9315 insn_start_frag
= frag_now
;
9316 insn_start_off
= frag_now_fix ();
9318 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9321 /* Branch can be 8 bytes. Leave some room for prefixes. */
9322 unsigned int max_branch_padding_size
= 14;
9324 /* Align section to boundary. */
9325 record_alignment (now_seg
, align_branch_power
);
9327 /* Make room for padding. */
9328 frag_grow (max_branch_padding_size
);
9330 /* Start of the padding. */
9335 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9336 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9339 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9340 fragP
->tc_frag_data
.branch_type
= branch
;
9341 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9345 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9347 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9348 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9350 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9351 output_interseg_jump ();
9354 /* Output normal instructions here. */
9358 enum mf_cmp_kind mf_cmp
;
9361 && (i
.tm
.base_opcode
== 0xfaee8
9362 || i
.tm
.base_opcode
== 0xfaef0
9363 || i
.tm
.base_opcode
== 0xfaef8))
9365 /* Encode lfence, mfence, and sfence as
9366 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9367 if (now_seg
!= absolute_section
)
9369 offsetT val
= 0x240483f0ULL
;
9372 md_number_to_chars (p
, val
, 5);
9375 abs_section_offset
+= 5;
9379 /* Some processors fail on LOCK prefix. This options makes
9380 assembler ignore LOCK prefix and serves as a workaround. */
9381 if (omit_lock_prefix
)
9383 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9385 i
.prefix
[LOCK_PREFIX
] = 0;
9389 /* Skip if this is a branch. */
9391 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9393 /* Make room for padding. */
9394 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9399 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9400 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9403 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9404 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9405 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9407 else if (add_branch_prefix_frag_p ())
9409 unsigned int max_prefix_size
= align_branch_prefix_size
;
9411 /* Make room for padding. */
9412 frag_grow (max_prefix_size
);
9417 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9418 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9421 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9424 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9425 don't need the explicit prefix. */
9426 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9428 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9437 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9438 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9442 switch (i
.tm
.opcode_length
)
9449 /* Check for pseudo prefixes. */
9450 as_bad_where (insn_start_frag
->fr_file
,
9451 insn_start_frag
->fr_line
,
9452 _("pseudo prefix without instruction"));
9462 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9463 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9464 R_X86_64_GOTTPOFF relocation so that linker can safely
9465 perform IE->LE optimization. A dummy REX_OPCODE prefix
9466 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9467 relocation for GDesc -> IE/LE optimization. */
9468 if (x86_elf_abi
== X86_64_X32_ABI
9470 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9471 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9472 && i
.prefix
[REX_PREFIX
] == 0)
9473 add_prefix (REX_OPCODE
);
9476 /* The prefix bytes. */
9477 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9479 frag_opcode_byte (*q
);
9483 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9489 frag_opcode_byte (*q
);
9492 /* There should be no other prefixes for instructions
9497 /* For EVEX instructions i.vrex should become 0 after
9498 build_evex_prefix. For VEX instructions upper 16 registers
9499 aren't available, so VREX should be 0. */
9502 /* Now the VEX prefix. */
9503 if (now_seg
!= absolute_section
)
9505 p
= frag_more (i
.vex
.length
);
9506 for (j
= 0; j
< i
.vex
.length
; j
++)
9507 p
[j
] = i
.vex
.bytes
[j
];
9510 abs_section_offset
+= i
.vex
.length
;
9513 /* Now the opcode; be careful about word order here! */
9514 if (now_seg
== absolute_section
)
9515 abs_section_offset
+= i
.tm
.opcode_length
;
9516 else if (i
.tm
.opcode_length
== 1)
9518 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9522 switch (i
.tm
.opcode_length
)
9526 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9527 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9531 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9541 /* Put out high byte first: can't use md_number_to_chars! */
9542 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9543 *p
= i
.tm
.base_opcode
& 0xff;
9546 /* Now the modrm byte and sib byte (if present). */
9547 if (i
.tm
.opcode_modifier
.modrm
)
9549 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9551 | (i
.rm
.mode
<< 6));
9552 /* If i.rm.regmem == ESP (4)
9553 && i.rm.mode != (Register mode)
9555 ==> need second modrm byte. */
9556 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9558 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9559 frag_opcode_byte ((i
.sib
.base
<< 0)
9560 | (i
.sib
.index
<< 3)
9561 | (i
.sib
.scale
<< 6));
9564 if (i
.disp_operands
)
9565 output_disp (insn_start_frag
, insn_start_off
);
9568 output_imm (insn_start_frag
, insn_start_off
);
9571 * frag_now_fix () returning plain abs_section_offset when we're in the
9572 * absolute section, and abs_section_offset not getting updated as data
9573 * gets added to the frag breaks the logic below.
9575 if (now_seg
!= absolute_section
)
9577 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9579 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9583 /* NB: Don't add prefix with GOTPC relocation since
9584 output_disp() above depends on the fixed encoding
9585 length. Can't add prefix with TLS relocation since
9586 it breaks TLS linker optimization. */
9587 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9588 /* Prefix count on the current instruction. */
9589 unsigned int count
= i
.vex
.length
;
9591 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9592 /* REX byte is encoded in VEX/EVEX prefix. */
9593 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9596 /* Count prefixes for extended opcode maps. */
9598 switch (i
.tm
.opcode_length
)
9601 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9604 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9616 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9625 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9628 /* Set the maximum prefix size in BRANCH_PREFIX
9630 if (fragP
->tc_frag_data
.max_bytes
> max
)
9631 fragP
->tc_frag_data
.max_bytes
= max
;
9632 if (fragP
->tc_frag_data
.max_bytes
> count
)
9633 fragP
->tc_frag_data
.max_bytes
-= count
;
9635 fragP
->tc_frag_data
.max_bytes
= 0;
9639 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9641 unsigned int max_prefix_size
;
9642 if (align_branch_prefix_size
> max
)
9643 max_prefix_size
= max
;
9645 max_prefix_size
= align_branch_prefix_size
;
9646 if (max_prefix_size
> count
)
9647 fragP
->tc_frag_data
.max_prefix_length
9648 = max_prefix_size
- count
;
9651 /* Use existing segment prefix if possible. Use CS
9652 segment prefix in 64-bit mode. In 32-bit mode, use SS
9653 segment prefix with ESP/EBP base register and use DS
9654 segment prefix without ESP/EBP base register. */
9655 if (i
.prefix
[SEG_PREFIX
])
9656 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9657 else if (flag_code
== CODE_64BIT
)
9658 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9660 && (i
.base_reg
->reg_num
== 4
9661 || i
.base_reg
->reg_num
== 5))
9662 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9664 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9669 /* NB: Don't work with COND_JUMP86 without i386. */
9670 if (align_branch_power
9671 && now_seg
!= absolute_section
9672 && cpu_arch_flags
.bitfield
.cpui386
)
9674 /* Terminate each frag so that we can add prefix and check for
9676 frag_wane (frag_now
);
9683 pi ("" /*line*/, &i
);
9685 #endif /* DEBUG386 */
9688 /* Return the size of the displacement operand N. */
9691 disp_size (unsigned int n
)
9695 if (i
.types
[n
].bitfield
.disp64
)
9697 else if (i
.types
[n
].bitfield
.disp8
)
9699 else if (i
.types
[n
].bitfield
.disp16
)
9704 /* Return the size of the immediate operand N. */
9707 imm_size (unsigned int n
)
9710 if (i
.types
[n
].bitfield
.imm64
)
9712 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9714 else if (i
.types
[n
].bitfield
.imm16
)
9720 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9725 for (n
= 0; n
< i
.operands
; n
++)
9727 if (operand_type_check (i
.types
[n
], disp
))
9729 int size
= disp_size (n
);
9731 if (now_seg
== absolute_section
)
9732 abs_section_offset
+= size
;
9733 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9735 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9737 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9739 p
= frag_more (size
);
9740 md_number_to_chars (p
, val
, size
);
9744 enum bfd_reloc_code_real reloc_type
;
9745 int sign
= i
.types
[n
].bitfield
.disp32s
;
9746 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9749 /* We can't have 8 bit displacement here. */
9750 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9752 /* The PC relative address is computed relative
9753 to the instruction boundary, so in case immediate
9754 fields follows, we need to adjust the value. */
9755 if (pcrel
&& i
.imm_operands
)
9760 for (n1
= 0; n1
< i
.operands
; n1
++)
9761 if (operand_type_check (i
.types
[n1
], imm
))
9763 /* Only one immediate is allowed for PC
9764 relative address. */
9765 gas_assert (sz
== 0);
9767 i
.op
[n
].disps
->X_add_number
-= sz
;
9769 /* We should find the immediate. */
9770 gas_assert (sz
!= 0);
9773 p
= frag_more (size
);
9774 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9776 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9777 && (((reloc_type
== BFD_RELOC_32
9778 || reloc_type
== BFD_RELOC_X86_64_32S
9779 || (reloc_type
== BFD_RELOC_64
9781 && (i
.op
[n
].disps
->X_op
== O_symbol
9782 || (i
.op
[n
].disps
->X_op
== O_add
9783 && ((symbol_get_value_expression
9784 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9786 || reloc_type
== BFD_RELOC_32_PCREL
))
9790 reloc_type
= BFD_RELOC_386_GOTPC
;
9791 i
.has_gotpc_tls_reloc
= TRUE
;
9792 i
.op
[n
].imms
->X_add_number
+=
9793 encoding_length (insn_start_frag
, insn_start_off
, p
);
9795 else if (reloc_type
== BFD_RELOC_64
)
9796 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9798 /* Don't do the adjustment for x86-64, as there
9799 the pcrel addressing is relative to the _next_
9800 insn, and that is taken care of in other code. */
9801 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9803 else if (align_branch_power
)
9807 case BFD_RELOC_386_TLS_GD
:
9808 case BFD_RELOC_386_TLS_LDM
:
9809 case BFD_RELOC_386_TLS_IE
:
9810 case BFD_RELOC_386_TLS_IE_32
:
9811 case BFD_RELOC_386_TLS_GOTIE
:
9812 case BFD_RELOC_386_TLS_GOTDESC
:
9813 case BFD_RELOC_386_TLS_DESC_CALL
:
9814 case BFD_RELOC_X86_64_TLSGD
:
9815 case BFD_RELOC_X86_64_TLSLD
:
9816 case BFD_RELOC_X86_64_GOTTPOFF
:
9817 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9818 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9819 i
.has_gotpc_tls_reloc
= TRUE
;
9824 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9825 size
, i
.op
[n
].disps
, pcrel
,
9827 /* Check for "call/jmp *mem", "mov mem, %reg",
9828 "test %reg, mem" and "binop mem, %reg" where binop
9829 is one of adc, add, and, cmp, or, sbb, sub, xor
9830 instructions without data prefix. Always generate
9831 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9832 if (i
.prefix
[DATA_PREFIX
] == 0
9833 && (generate_relax_relocations
9836 && i
.rm
.regmem
== 5))
9838 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9839 && !is_any_vex_encoding(&i
.tm
)
9840 && ((i
.operands
== 1
9841 && i
.tm
.base_opcode
== 0xff
9842 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9844 && (i
.tm
.base_opcode
== 0x8b
9845 || i
.tm
.base_opcode
== 0x85
9846 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9850 fixP
->fx_tcbit
= i
.rex
!= 0;
9852 && (i
.base_reg
->reg_num
== RegIP
))
9853 fixP
->fx_tcbit2
= 1;
9856 fixP
->fx_tcbit2
= 1;
9864 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9869 for (n
= 0; n
< i
.operands
; n
++)
9871 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9872 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9875 if (operand_type_check (i
.types
[n
], imm
))
9877 int size
= imm_size (n
);
9879 if (now_seg
== absolute_section
)
9880 abs_section_offset
+= size
;
9881 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9885 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9887 p
= frag_more (size
);
9888 md_number_to_chars (p
, val
, size
);
9892 /* Not absolute_section.
9893 Need a 32-bit fixup (don't support 8bit
9894 non-absolute imms). Try to support other
9896 enum bfd_reloc_code_real reloc_type
;
9899 if (i
.types
[n
].bitfield
.imm32s
9900 && (i
.suffix
== QWORD_MNEM_SUFFIX
9901 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9906 p
= frag_more (size
);
9907 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9909 /* This is tough to explain. We end up with this one if we
9910 * have operands that look like
9911 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9912 * obtain the absolute address of the GOT, and it is strongly
9913 * preferable from a performance point of view to avoid using
9914 * a runtime relocation for this. The actual sequence of
9915 * instructions often look something like:
9920 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9922 * The call and pop essentially return the absolute address
9923 * of the label .L66 and store it in %ebx. The linker itself
9924 * will ultimately change the first operand of the addl so
9925 * that %ebx points to the GOT, but to keep things simple, the
9926 * .o file must have this operand set so that it generates not
9927 * the absolute address of .L66, but the absolute address of
9928 * itself. This allows the linker itself simply treat a GOTPC
9929 * relocation as asking for a pcrel offset to the GOT to be
9930 * added in, and the addend of the relocation is stored in the
9931 * operand field for the instruction itself.
9933 * Our job here is to fix the operand so that it would add
9934 * the correct offset so that %ebx would point to itself. The
9935 * thing that is tricky is that .-.L66 will point to the
9936 * beginning of the instruction, so we need to further modify
9937 * the operand so that it will point to itself. There are
9938 * other cases where you have something like:
9940 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9942 * and here no correction would be required. Internally in
9943 * the assembler we treat operands of this form as not being
9944 * pcrel since the '.' is explicitly mentioned, and I wonder
9945 * whether it would simplify matters to do it this way. Who
9946 * knows. In earlier versions of the PIC patches, the
9947 * pcrel_adjust field was used to store the correction, but
9948 * since the expression is not pcrel, I felt it would be
9949 * confusing to do it this way. */
9951 if ((reloc_type
== BFD_RELOC_32
9952 || reloc_type
== BFD_RELOC_X86_64_32S
9953 || reloc_type
== BFD_RELOC_64
)
9955 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9956 && (i
.op
[n
].imms
->X_op
== O_symbol
9957 || (i
.op
[n
].imms
->X_op
== O_add
9958 && ((symbol_get_value_expression
9959 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9963 reloc_type
= BFD_RELOC_386_GOTPC
;
9965 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9967 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9968 i
.has_gotpc_tls_reloc
= TRUE
;
9969 i
.op
[n
].imms
->X_add_number
+=
9970 encoding_length (insn_start_frag
, insn_start_off
, p
);
9972 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9973 i
.op
[n
].imms
, 0, reloc_type
);
9979 /* x86_cons_fix_new is called via the expression parsing code when a
9980 reloc is needed. We use this hook to get the correct .got reloc. */
9981 static int cons_sign
= -1;
9984 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9985 expressionS
*exp
, bfd_reloc_code_real_type r
)
9987 r
= reloc (len
, 0, cons_sign
, r
);
9990 if (exp
->X_op
== O_secrel
)
9992 exp
->X_op
= O_symbol
;
9993 r
= BFD_RELOC_32_SECREL
;
9997 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10000 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10001 purpose of the `.dc.a' internal pseudo-op. */
10004 x86_address_bytes (void)
10006 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10008 return stdoutput
->arch_info
->bits_per_address
/ 8;
10011 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10012 || defined (LEX_AT)
10013 # define lex_got(reloc, adjust, types) NULL
10015 /* Parse operands of the form
10016 <symbol>@GOTOFF+<nnn>
10017 and similar .plt or .got references.
10019 If we find one, set up the correct relocation in RELOC and copy the
10020 input string, minus the `@GOTOFF' into a malloc'd buffer for
10021 parsing by the calling routine. Return this buffer, and if ADJUST
10022 is non-null set it to the length of the string we removed from the
10023 input line. Otherwise return NULL. */
10025 lex_got (enum bfd_reloc_code_real
*rel
,
10027 i386_operand_type
*types
)
10029 /* Some of the relocations depend on the size of what field is to
10030 be relocated. But in our callers i386_immediate and i386_displacement
10031 we don't yet know the operand size (this will be set by insn
10032 matching). Hence we record the word32 relocation here,
10033 and adjust the reloc according to the real size in reloc(). */
10034 static const struct {
10037 const enum bfd_reloc_code_real rel
[2];
10038 const i386_operand_type types64
;
10039 bfd_boolean need_GOT_symbol
;
10041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10042 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10043 BFD_RELOC_SIZE32
},
10044 OPERAND_TYPE_IMM32_64
, FALSE
},
10046 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10047 BFD_RELOC_X86_64_PLTOFF64
},
10048 OPERAND_TYPE_IMM64
, TRUE
},
10049 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10050 BFD_RELOC_X86_64_PLT32
},
10051 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10052 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10053 BFD_RELOC_X86_64_GOTPLT64
},
10054 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10055 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10056 BFD_RELOC_X86_64_GOTOFF64
},
10057 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10058 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10059 BFD_RELOC_X86_64_GOTPCREL
},
10060 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10061 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10062 BFD_RELOC_X86_64_TLSGD
},
10063 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10064 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10065 _dummy_first_bfd_reloc_code_real
},
10066 OPERAND_TYPE_NONE
, TRUE
},
10067 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10068 BFD_RELOC_X86_64_TLSLD
},
10069 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10070 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10071 BFD_RELOC_X86_64_GOTTPOFF
},
10072 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10073 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10074 BFD_RELOC_X86_64_TPOFF32
},
10075 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10076 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10077 _dummy_first_bfd_reloc_code_real
},
10078 OPERAND_TYPE_NONE
, TRUE
},
10079 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10080 BFD_RELOC_X86_64_DTPOFF32
},
10081 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10082 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10083 _dummy_first_bfd_reloc_code_real
},
10084 OPERAND_TYPE_NONE
, TRUE
},
10085 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10086 _dummy_first_bfd_reloc_code_real
},
10087 OPERAND_TYPE_NONE
, TRUE
},
10088 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10089 BFD_RELOC_X86_64_GOT32
},
10090 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10091 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10092 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10093 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10094 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10095 BFD_RELOC_X86_64_TLSDESC_CALL
},
10096 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10101 #if defined (OBJ_MAYBE_ELF)
10106 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10107 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10110 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10112 int len
= gotrel
[j
].len
;
10113 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10115 if (gotrel
[j
].rel
[object_64bit
] != 0)
10118 char *tmpbuf
, *past_reloc
;
10120 *rel
= gotrel
[j
].rel
[object_64bit
];
10124 if (flag_code
!= CODE_64BIT
)
10126 types
->bitfield
.imm32
= 1;
10127 types
->bitfield
.disp32
= 1;
10130 *types
= gotrel
[j
].types64
;
10133 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10134 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10136 /* The length of the first part of our input line. */
10137 first
= cp
- input_line_pointer
;
10139 /* The second part goes from after the reloc token until
10140 (and including) an end_of_line char or comma. */
10141 past_reloc
= cp
+ 1 + len
;
10143 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10145 second
= cp
+ 1 - past_reloc
;
10147 /* Allocate and copy string. The trailing NUL shouldn't
10148 be necessary, but be safe. */
10149 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10150 memcpy (tmpbuf
, input_line_pointer
, first
);
10151 if (second
!= 0 && *past_reloc
!= ' ')
10152 /* Replace the relocation token with ' ', so that
10153 errors like foo@GOTOFF1 will be detected. */
10154 tmpbuf
[first
++] = ' ';
10156 /* Increment length by 1 if the relocation token is
10161 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10162 tmpbuf
[first
+ second
] = '\0';
10166 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10167 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10172 /* Might be a symbol version string. Don't as_bad here. */
10181 /* Parse operands of the form
10182 <symbol>@SECREL32+<nnn>
10184 If we find one, set up the correct relocation in RELOC and copy the
10185 input string, minus the `@SECREL32' into a malloc'd buffer for
10186 parsing by the calling routine. Return this buffer, and if ADJUST
10187 is non-null set it to the length of the string we removed from the
10188 input line. Otherwise return NULL.
10190 This function is copied from the ELF version above adjusted for PE targets. */
10193 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10194 int *adjust ATTRIBUTE_UNUSED
,
10195 i386_operand_type
*types
)
10197 static const struct
10201 const enum bfd_reloc_code_real rel
[2];
10202 const i386_operand_type types64
;
10206 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10207 BFD_RELOC_32_SECREL
},
10208 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10214 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10215 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10218 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10220 int len
= gotrel
[j
].len
;
10222 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10224 if (gotrel
[j
].rel
[object_64bit
] != 0)
10227 char *tmpbuf
, *past_reloc
;
10229 *rel
= gotrel
[j
].rel
[object_64bit
];
10235 if (flag_code
!= CODE_64BIT
)
10237 types
->bitfield
.imm32
= 1;
10238 types
->bitfield
.disp32
= 1;
10241 *types
= gotrel
[j
].types64
;
10244 /* The length of the first part of our input line. */
10245 first
= cp
- input_line_pointer
;
10247 /* The second part goes from after the reloc token until
10248 (and including) an end_of_line char or comma. */
10249 past_reloc
= cp
+ 1 + len
;
10251 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10253 second
= cp
+ 1 - past_reloc
;
10255 /* Allocate and copy string. The trailing NUL shouldn't
10256 be necessary, but be safe. */
10257 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10258 memcpy (tmpbuf
, input_line_pointer
, first
);
10259 if (second
!= 0 && *past_reloc
!= ' ')
10260 /* Replace the relocation token with ' ', so that
10261 errors like foo@SECLREL321 will be detected. */
10262 tmpbuf
[first
++] = ' ';
10263 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10264 tmpbuf
[first
+ second
] = '\0';
10268 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10269 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10274 /* Might be a symbol version string. Don't as_bad here. */
10280 bfd_reloc_code_real_type
10281 x86_cons (expressionS
*exp
, int size
)
10283 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10285 intel_syntax
= -intel_syntax
;
10288 if (size
== 4 || (object_64bit
&& size
== 8))
10290 /* Handle @GOTOFF and the like in an expression. */
10292 char *gotfree_input_line
;
10295 save
= input_line_pointer
;
10296 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10297 if (gotfree_input_line
)
10298 input_line_pointer
= gotfree_input_line
;
10302 if (gotfree_input_line
)
10304 /* expression () has merrily parsed up to the end of line,
10305 or a comma - in the wrong buffer. Transfer how far
10306 input_line_pointer has moved to the right buffer. */
10307 input_line_pointer
= (save
10308 + (input_line_pointer
- gotfree_input_line
)
10310 free (gotfree_input_line
);
10311 if (exp
->X_op
== O_constant
10312 || exp
->X_op
== O_absent
10313 || exp
->X_op
== O_illegal
10314 || exp
->X_op
== O_register
10315 || exp
->X_op
== O_big
)
10317 char c
= *input_line_pointer
;
10318 *input_line_pointer
= 0;
10319 as_bad (_("missing or invalid expression `%s'"), save
);
10320 *input_line_pointer
= c
;
10322 else if ((got_reloc
== BFD_RELOC_386_PLT32
10323 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10324 && exp
->X_op
!= O_symbol
)
10326 char c
= *input_line_pointer
;
10327 *input_line_pointer
= 0;
10328 as_bad (_("invalid PLT expression `%s'"), save
);
10329 *input_line_pointer
= c
;
10336 intel_syntax
= -intel_syntax
;
10339 i386_intel_simplify (exp
);
10345 signed_cons (int size
)
10347 if (flag_code
== CODE_64BIT
)
10355 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10362 if (exp
.X_op
== O_symbol
)
10363 exp
.X_op
= O_secrel
;
10365 emit_expr (&exp
, 4);
10367 while (*input_line_pointer
++ == ',');
10369 input_line_pointer
--;
10370 demand_empty_rest_of_line ();
10374 /* Handle Vector operations. */
10377 check_VecOperations (char *op_string
, char *op_end
)
10379 const reg_entry
*mask
;
10384 && (op_end
== NULL
|| op_string
< op_end
))
10387 if (*op_string
== '{')
10391 /* Check broadcasts. */
10392 if (strncmp (op_string
, "1to", 3) == 0)
10397 goto duplicated_vec_op
;
10400 if (*op_string
== '8')
10402 else if (*op_string
== '4')
10404 else if (*op_string
== '2')
10406 else if (*op_string
== '1'
10407 && *(op_string
+1) == '6')
10414 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10419 broadcast_op
.type
= bcst_type
;
10420 broadcast_op
.operand
= this_operand
;
10421 broadcast_op
.bytes
= 0;
10422 i
.broadcast
= &broadcast_op
;
10424 /* Check masking operation. */
10425 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10427 if (mask
== &bad_reg
)
10430 /* k0 can't be used for write mask. */
10431 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10433 as_bad (_("`%s%s' can't be used for write mask"),
10434 register_prefix
, mask
->reg_name
);
10440 mask_op
.mask
= mask
;
10441 mask_op
.zeroing
= 0;
10442 mask_op
.operand
= this_operand
;
10448 goto duplicated_vec_op
;
10450 i
.mask
->mask
= mask
;
10452 /* Only "{z}" is allowed here. No need to check
10453 zeroing mask explicitly. */
10454 if (i
.mask
->operand
!= this_operand
)
10456 as_bad (_("invalid write mask `%s'"), saved
);
10461 op_string
= end_op
;
10463 /* Check zeroing-flag for masking operation. */
10464 else if (*op_string
== 'z')
10468 mask_op
.mask
= NULL
;
10469 mask_op
.zeroing
= 1;
10470 mask_op
.operand
= this_operand
;
10475 if (i
.mask
->zeroing
)
10478 as_bad (_("duplicated `%s'"), saved
);
10482 i
.mask
->zeroing
= 1;
10484 /* Only "{%k}" is allowed here. No need to check mask
10485 register explicitly. */
10486 if (i
.mask
->operand
!= this_operand
)
10488 as_bad (_("invalid zeroing-masking `%s'"),
10497 goto unknown_vec_op
;
10499 if (*op_string
!= '}')
10501 as_bad (_("missing `}' in `%s'"), saved
);
10506 /* Strip whitespace since the addition of pseudo prefixes
10507 changed how the scrubber treats '{'. */
10508 if (is_space_char (*op_string
))
10514 /* We don't know this one. */
10515 as_bad (_("unknown vector operation: `%s'"), saved
);
10519 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10521 as_bad (_("zeroing-masking only allowed with write mask"));
10529 i386_immediate (char *imm_start
)
10531 char *save_input_line_pointer
;
10532 char *gotfree_input_line
;
10535 i386_operand_type types
;
10537 operand_type_set (&types
, ~0);
10539 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10541 as_bad (_("at most %d immediate operands are allowed"),
10542 MAX_IMMEDIATE_OPERANDS
);
10546 exp
= &im_expressions
[i
.imm_operands
++];
10547 i
.op
[this_operand
].imms
= exp
;
10549 if (is_space_char (*imm_start
))
10552 save_input_line_pointer
= input_line_pointer
;
10553 input_line_pointer
= imm_start
;
10555 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10556 if (gotfree_input_line
)
10557 input_line_pointer
= gotfree_input_line
;
10559 exp_seg
= expression (exp
);
10561 SKIP_WHITESPACE ();
10563 /* Handle vector operations. */
10564 if (*input_line_pointer
== '{')
10566 input_line_pointer
= check_VecOperations (input_line_pointer
,
10568 if (input_line_pointer
== NULL
)
10572 if (*input_line_pointer
)
10573 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10575 input_line_pointer
= save_input_line_pointer
;
10576 if (gotfree_input_line
)
10578 free (gotfree_input_line
);
10580 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10581 exp
->X_op
= O_illegal
;
10584 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10588 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10589 i386_operand_type types
, const char *imm_start
)
10591 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10594 as_bad (_("missing or invalid immediate expression `%s'"),
10598 else if (exp
->X_op
== O_constant
)
10600 /* Size it properly later. */
10601 i
.types
[this_operand
].bitfield
.imm64
= 1;
10602 /* If not 64bit, sign extend val. */
10603 if (flag_code
!= CODE_64BIT
10604 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10606 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10608 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10609 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10610 && exp_seg
!= absolute_section
10611 && exp_seg
!= text_section
10612 && exp_seg
!= data_section
10613 && exp_seg
!= bss_section
10614 && exp_seg
!= undefined_section
10615 && !bfd_is_com_section (exp_seg
))
10617 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10621 else if (!intel_syntax
&& exp_seg
== reg_section
)
10624 as_bad (_("illegal immediate register operand %s"), imm_start
);
10629 /* This is an address. The size of the address will be
10630 determined later, depending on destination register,
10631 suffix, or the default for the section. */
10632 i
.types
[this_operand
].bitfield
.imm8
= 1;
10633 i
.types
[this_operand
].bitfield
.imm16
= 1;
10634 i
.types
[this_operand
].bitfield
.imm32
= 1;
10635 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10636 i
.types
[this_operand
].bitfield
.imm64
= 1;
10637 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10645 i386_scale (char *scale
)
10648 char *save
= input_line_pointer
;
10650 input_line_pointer
= scale
;
10651 val
= get_absolute_expression ();
10656 i
.log2_scale_factor
= 0;
10659 i
.log2_scale_factor
= 1;
10662 i
.log2_scale_factor
= 2;
10665 i
.log2_scale_factor
= 3;
10669 char sep
= *input_line_pointer
;
10671 *input_line_pointer
= '\0';
10672 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10674 *input_line_pointer
= sep
;
10675 input_line_pointer
= save
;
10679 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10681 as_warn (_("scale factor of %d without an index register"),
10682 1 << i
.log2_scale_factor
);
10683 i
.log2_scale_factor
= 0;
10685 scale
= input_line_pointer
;
10686 input_line_pointer
= save
;
10691 i386_displacement (char *disp_start
, char *disp_end
)
10695 char *save_input_line_pointer
;
10696 char *gotfree_input_line
;
10698 i386_operand_type bigdisp
, types
= anydisp
;
10701 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10703 as_bad (_("at most %d displacement operands are allowed"),
10704 MAX_MEMORY_OPERANDS
);
10708 operand_type_set (&bigdisp
, 0);
10710 || i
.types
[this_operand
].bitfield
.baseindex
10711 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10712 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10714 i386_addressing_mode ();
10715 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10716 if (flag_code
== CODE_64BIT
)
10720 bigdisp
.bitfield
.disp32s
= 1;
10721 bigdisp
.bitfield
.disp64
= 1;
10724 bigdisp
.bitfield
.disp32
= 1;
10726 else if ((flag_code
== CODE_16BIT
) ^ override
)
10727 bigdisp
.bitfield
.disp16
= 1;
10729 bigdisp
.bitfield
.disp32
= 1;
10733 /* For PC-relative branches, the width of the displacement may be
10734 dependent upon data size, but is never dependent upon address size.
10735 Also make sure to not unintentionally match against a non-PC-relative
10736 branch template. */
10737 static templates aux_templates
;
10738 const insn_template
*t
= current_templates
->start
;
10739 bfd_boolean has_intel64
= FALSE
;
10741 aux_templates
.start
= t
;
10742 while (++t
< current_templates
->end
)
10744 if (t
->opcode_modifier
.jump
10745 != current_templates
->start
->opcode_modifier
.jump
)
10747 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10748 has_intel64
= TRUE
;
10750 if (t
< current_templates
->end
)
10752 aux_templates
.end
= t
;
10753 current_templates
= &aux_templates
;
10756 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10757 if (flag_code
== CODE_64BIT
)
10759 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10760 && (!intel64
|| !has_intel64
))
10761 bigdisp
.bitfield
.disp16
= 1;
10763 bigdisp
.bitfield
.disp32s
= 1;
10768 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10770 : LONG_MNEM_SUFFIX
));
10771 bigdisp
.bitfield
.disp32
= 1;
10772 if ((flag_code
== CODE_16BIT
) ^ override
)
10774 bigdisp
.bitfield
.disp32
= 0;
10775 bigdisp
.bitfield
.disp16
= 1;
10779 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10782 exp
= &disp_expressions
[i
.disp_operands
];
10783 i
.op
[this_operand
].disps
= exp
;
10785 save_input_line_pointer
= input_line_pointer
;
10786 input_line_pointer
= disp_start
;
10787 END_STRING_AND_SAVE (disp_end
);
10789 #ifndef GCC_ASM_O_HACK
10790 #define GCC_ASM_O_HACK 0
10793 END_STRING_AND_SAVE (disp_end
+ 1);
10794 if (i
.types
[this_operand
].bitfield
.baseIndex
10795 && displacement_string_end
[-1] == '+')
10797 /* This hack is to avoid a warning when using the "o"
10798 constraint within gcc asm statements.
10801 #define _set_tssldt_desc(n,addr,limit,type) \
10802 __asm__ __volatile__ ( \
10803 "movw %w2,%0\n\t" \
10804 "movw %w1,2+%0\n\t" \
10805 "rorl $16,%1\n\t" \
10806 "movb %b1,4+%0\n\t" \
10807 "movb %4,5+%0\n\t" \
10808 "movb $0,6+%0\n\t" \
10809 "movb %h1,7+%0\n\t" \
10811 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10813 This works great except that the output assembler ends
10814 up looking a bit weird if it turns out that there is
10815 no offset. You end up producing code that looks like:
10828 So here we provide the missing zero. */
10830 *displacement_string_end
= '0';
10833 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10834 if (gotfree_input_line
)
10835 input_line_pointer
= gotfree_input_line
;
10837 exp_seg
= expression (exp
);
10839 SKIP_WHITESPACE ();
10840 if (*input_line_pointer
)
10841 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10843 RESTORE_END_STRING (disp_end
+ 1);
10845 input_line_pointer
= save_input_line_pointer
;
10846 if (gotfree_input_line
)
10848 free (gotfree_input_line
);
10850 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10851 exp
->X_op
= O_illegal
;
10854 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10856 RESTORE_END_STRING (disp_end
);
10862 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10863 i386_operand_type types
, const char *disp_start
)
10865 i386_operand_type bigdisp
;
10868 /* We do this to make sure that the section symbol is in
10869 the symbol table. We will ultimately change the relocation
10870 to be relative to the beginning of the section. */
10871 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10872 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10873 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10875 if (exp
->X_op
!= O_symbol
)
10878 if (S_IS_LOCAL (exp
->X_add_symbol
)
10879 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10880 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10881 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10882 exp
->X_op
= O_subtract
;
10883 exp
->X_op_symbol
= GOT_symbol
;
10884 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10885 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10886 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10887 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10889 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10892 else if (exp
->X_op
== O_absent
10893 || exp
->X_op
== O_illegal
10894 || exp
->X_op
== O_big
)
10897 as_bad (_("missing or invalid displacement expression `%s'"),
10902 else if (flag_code
== CODE_64BIT
10903 && !i
.prefix
[ADDR_PREFIX
]
10904 && exp
->X_op
== O_constant
)
10906 /* Since displacement is signed extended to 64bit, don't allow
10907 disp32 and turn off disp32s if they are out of range. */
10908 i
.types
[this_operand
].bitfield
.disp32
= 0;
10909 if (!fits_in_signed_long (exp
->X_add_number
))
10911 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10912 if (i
.types
[this_operand
].bitfield
.baseindex
)
10914 as_bad (_("0x%lx out range of signed 32bit displacement"),
10915 (long) exp
->X_add_number
);
10921 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10922 else if (exp
->X_op
!= O_constant
10923 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10924 && exp_seg
!= absolute_section
10925 && exp_seg
!= text_section
10926 && exp_seg
!= data_section
10927 && exp_seg
!= bss_section
10928 && exp_seg
!= undefined_section
10929 && !bfd_is_com_section (exp_seg
))
10931 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10936 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10937 /* Constants get taken care of by optimize_disp(). */
10938 && exp
->X_op
!= O_constant
)
10939 i
.types
[this_operand
].bitfield
.disp8
= 1;
10941 /* Check if this is a displacement only operand. */
10942 bigdisp
= i
.types
[this_operand
];
10943 bigdisp
.bitfield
.disp8
= 0;
10944 bigdisp
.bitfield
.disp16
= 0;
10945 bigdisp
.bitfield
.disp32
= 0;
10946 bigdisp
.bitfield
.disp32s
= 0;
10947 bigdisp
.bitfield
.disp64
= 0;
10948 if (operand_type_all_zero (&bigdisp
))
10949 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10955 /* Return the active addressing mode, taking address override and
10956 registers forming the address into consideration. Update the
10957 address override prefix if necessary. */
10959 static enum flag_code
10960 i386_addressing_mode (void)
10962 enum flag_code addr_mode
;
10964 if (i
.prefix
[ADDR_PREFIX
])
10965 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10966 else if (flag_code
== CODE_16BIT
10967 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10968 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10969 from md_assemble() by "is not a valid base/index expression"
10970 when there is a base and/or index. */
10971 && !i
.types
[this_operand
].bitfield
.baseindex
)
10973 /* MPX insn memory operands with neither base nor index must be forced
10974 to use 32-bit addressing in 16-bit mode. */
10975 addr_mode
= CODE_32BIT
;
10976 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10978 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10979 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10983 addr_mode
= flag_code
;
10985 #if INFER_ADDR_PREFIX
10986 if (i
.mem_operands
== 0)
10988 /* Infer address prefix from the first memory operand. */
10989 const reg_entry
*addr_reg
= i
.base_reg
;
10991 if (addr_reg
== NULL
)
10992 addr_reg
= i
.index_reg
;
10996 if (addr_reg
->reg_type
.bitfield
.dword
)
10997 addr_mode
= CODE_32BIT
;
10998 else if (flag_code
!= CODE_64BIT
10999 && addr_reg
->reg_type
.bitfield
.word
)
11000 addr_mode
= CODE_16BIT
;
11002 if (addr_mode
!= flag_code
)
11004 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11006 /* Change the size of any displacement too. At most one
11007 of Disp16 or Disp32 is set.
11008 FIXME. There doesn't seem to be any real need for
11009 separate Disp16 and Disp32 flags. The same goes for
11010 Imm16 and Imm32. Removing them would probably clean
11011 up the code quite a lot. */
11012 if (flag_code
!= CODE_64BIT
11013 && (i
.types
[this_operand
].bitfield
.disp16
11014 || i
.types
[this_operand
].bitfield
.disp32
))
11015 i
.types
[this_operand
]
11016 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11026 /* Make sure the memory operand we've been dealt is valid.
11027 Return 1 on success, 0 on a failure. */
11030 i386_index_check (const char *operand_string
)
11032 const char *kind
= "base/index";
11033 enum flag_code addr_mode
= i386_addressing_mode ();
11035 if (current_templates
->start
->opcode_modifier
.isstring
11036 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
11037 && (current_templates
->end
[-1].opcode_modifier
.isstring
11038 || i
.mem_operands
))
11040 /* Memory operands of string insns are special in that they only allow
11041 a single register (rDI, rSI, or rBX) as their memory address. */
11042 const reg_entry
*expected_reg
;
11043 static const char *di_si
[][2] =
11049 static const char *bx
[] = { "ebx", "bx", "rbx" };
11051 kind
= "string address";
11053 if (current_templates
->start
->opcode_modifier
.prefixok
== PrefixRep
)
11055 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11056 - IS_STRING_ES_OP0
;
11059 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11060 || ((!i
.mem_operands
!= !intel_syntax
)
11061 && current_templates
->end
[-1].operand_types
[1]
11062 .bitfield
.baseindex
))
11065 = (const reg_entry
*) str_hash_find (reg_hash
,
11066 di_si
[addr_mode
][op
== es_op
]);
11070 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11072 if (i
.base_reg
!= expected_reg
11074 || operand_type_check (i
.types
[this_operand
], disp
))
11076 /* The second memory operand must have the same size as
11080 && !((addr_mode
== CODE_64BIT
11081 && i
.base_reg
->reg_type
.bitfield
.qword
)
11082 || (addr_mode
== CODE_32BIT
11083 ? i
.base_reg
->reg_type
.bitfield
.dword
11084 : i
.base_reg
->reg_type
.bitfield
.word
)))
11087 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11089 intel_syntax
? '[' : '(',
11091 expected_reg
->reg_name
,
11092 intel_syntax
? ']' : ')');
11099 as_bad (_("`%s' is not a valid %s expression"),
11100 operand_string
, kind
);
11105 if (addr_mode
!= CODE_16BIT
)
11107 /* 32-bit/64-bit checks. */
11108 if (i
.disp_encoding
== disp_encoding_16bit
)
11111 as_bad (_("invalid `%s' prefix"),
11112 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11117 && ((addr_mode
== CODE_64BIT
11118 ? !i
.base_reg
->reg_type
.bitfield
.qword
11119 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11120 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11121 || i
.base_reg
->reg_num
== RegIZ
))
11123 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11124 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11125 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11126 && ((addr_mode
== CODE_64BIT
11127 ? !i
.index_reg
->reg_type
.bitfield
.qword
11128 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11129 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11132 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11133 if (current_templates
->start
->base_opcode
== 0xf30f1b
11134 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11135 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11137 /* They cannot use RIP-relative addressing. */
11138 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11140 as_bad (_("`%s' cannot be used here"), operand_string
);
11144 /* bndldx and bndstx ignore their scale factor. */
11145 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11146 && i
.log2_scale_factor
)
11147 as_warn (_("register scaling is being ignored here"));
11152 /* 16-bit checks. */
11153 if (i
.disp_encoding
== disp_encoding_32bit
)
11157 && (!i
.base_reg
->reg_type
.bitfield
.word
11158 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11160 && (!i
.index_reg
->reg_type
.bitfield
.word
11161 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11163 && i
.base_reg
->reg_num
< 6
11164 && i
.index_reg
->reg_num
>= 6
11165 && i
.log2_scale_factor
== 0))))
11172 /* Handle vector immediates. */
11175 RC_SAE_immediate (const char *imm_start
)
11177 unsigned int match_found
, j
;
11178 const char *pstr
= imm_start
;
11186 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11188 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11192 rc_op
.type
= RC_NamesTable
[j
].type
;
11193 rc_op
.operand
= this_operand
;
11194 i
.rounding
= &rc_op
;
11198 as_bad (_("duplicated `%s'"), imm_start
);
11201 pstr
+= RC_NamesTable
[j
].len
;
11209 if (*pstr
++ != '}')
11211 as_bad (_("Missing '}': '%s'"), imm_start
);
11214 /* RC/SAE immediate string should contain nothing more. */;
11217 as_bad (_("Junk after '}': '%s'"), imm_start
);
11221 exp
= &im_expressions
[i
.imm_operands
++];
11222 i
.op
[this_operand
].imms
= exp
;
11224 exp
->X_op
= O_constant
;
11225 exp
->X_add_number
= 0;
11226 exp
->X_add_symbol
= (symbolS
*) 0;
11227 exp
->X_op_symbol
= (symbolS
*) 0;
11229 i
.types
[this_operand
].bitfield
.imm8
= 1;
11233 /* Only string instructions can have a second memory operand, so
11234 reduce current_templates to just those if it contains any. */
11236 maybe_adjust_templates (void)
11238 const insn_template
*t
;
11240 gas_assert (i
.mem_operands
== 1);
11242 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11243 if (t
->opcode_modifier
.isstring
)
11246 if (t
< current_templates
->end
)
11248 static templates aux_templates
;
11249 bfd_boolean recheck
;
11251 aux_templates
.start
= t
;
11252 for (; t
< current_templates
->end
; ++t
)
11253 if (!t
->opcode_modifier
.isstring
)
11255 aux_templates
.end
= t
;
11257 /* Determine whether to re-check the first memory operand. */
11258 recheck
= (aux_templates
.start
!= current_templates
->start
11259 || t
!= current_templates
->end
);
11261 current_templates
= &aux_templates
;
11265 i
.mem_operands
= 0;
11266 if (i
.memop1_string
!= NULL
11267 && i386_index_check (i
.memop1_string
) == 0)
11269 i
.mem_operands
= 1;
11276 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11280 i386_att_operand (char *operand_string
)
11282 const reg_entry
*r
;
11284 char *op_string
= operand_string
;
11286 if (is_space_char (*op_string
))
11289 /* We check for an absolute prefix (differentiating,
11290 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11291 if (*op_string
== ABSOLUTE_PREFIX
)
11294 if (is_space_char (*op_string
))
11296 i
.jumpabsolute
= TRUE
;
11299 /* Check if operand is a register. */
11300 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11302 i386_operand_type temp
;
11307 /* Check for a segment override by searching for ':' after a
11308 segment register. */
11309 op_string
= end_op
;
11310 if (is_space_char (*op_string
))
11312 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11314 switch (r
->reg_num
)
11317 i
.seg
[i
.mem_operands
] = &es
;
11320 i
.seg
[i
.mem_operands
] = &cs
;
11323 i
.seg
[i
.mem_operands
] = &ss
;
11326 i
.seg
[i
.mem_operands
] = &ds
;
11329 i
.seg
[i
.mem_operands
] = &fs
;
11332 i
.seg
[i
.mem_operands
] = &gs
;
11336 /* Skip the ':' and whitespace. */
11338 if (is_space_char (*op_string
))
11341 if (!is_digit_char (*op_string
)
11342 && !is_identifier_char (*op_string
)
11343 && *op_string
!= '('
11344 && *op_string
!= ABSOLUTE_PREFIX
)
11346 as_bad (_("bad memory operand `%s'"), op_string
);
11349 /* Handle case of %es:*foo. */
11350 if (*op_string
== ABSOLUTE_PREFIX
)
11353 if (is_space_char (*op_string
))
11355 i
.jumpabsolute
= TRUE
;
11357 goto do_memory_reference
;
11360 /* Handle vector operations. */
11361 if (*op_string
== '{')
11363 op_string
= check_VecOperations (op_string
, NULL
);
11364 if (op_string
== NULL
)
11370 as_bad (_("junk `%s' after register"), op_string
);
11373 temp
= r
->reg_type
;
11374 temp
.bitfield
.baseindex
= 0;
11375 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11377 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11378 i
.op
[this_operand
].regs
= r
;
11381 else if (*op_string
== REGISTER_PREFIX
)
11383 as_bad (_("bad register name `%s'"), op_string
);
11386 else if (*op_string
== IMMEDIATE_PREFIX
)
11389 if (i
.jumpabsolute
)
11391 as_bad (_("immediate operand illegal with absolute jump"));
11394 if (!i386_immediate (op_string
))
11397 else if (RC_SAE_immediate (operand_string
))
11399 /* If it is a RC or SAE immediate, do nothing. */
11402 else if (is_digit_char (*op_string
)
11403 || is_identifier_char (*op_string
)
11404 || *op_string
== '"'
11405 || *op_string
== '(')
11407 /* This is a memory reference of some sort. */
11410 /* Start and end of displacement string expression (if found). */
11411 char *displacement_string_start
;
11412 char *displacement_string_end
;
11415 do_memory_reference
:
11416 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11418 if ((i
.mem_operands
== 1
11419 && !current_templates
->start
->opcode_modifier
.isstring
)
11420 || i
.mem_operands
== 2)
11422 as_bad (_("too many memory references for `%s'"),
11423 current_templates
->start
->name
);
11427 /* Check for base index form. We detect the base index form by
11428 looking for an ')' at the end of the operand, searching
11429 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11431 base_string
= op_string
+ strlen (op_string
);
11433 /* Handle vector operations. */
11434 vop_start
= strchr (op_string
, '{');
11435 if (vop_start
&& vop_start
< base_string
)
11437 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11439 base_string
= vop_start
;
11443 if (is_space_char (*base_string
))
11446 /* If we only have a displacement, set-up for it to be parsed later. */
11447 displacement_string_start
= op_string
;
11448 displacement_string_end
= base_string
+ 1;
11450 if (*base_string
== ')')
11453 unsigned int parens_balanced
= 1;
11454 /* We've already checked that the number of left & right ()'s are
11455 equal, so this loop will not be infinite. */
11459 if (*base_string
== ')')
11461 if (*base_string
== '(')
11464 while (parens_balanced
);
11466 temp_string
= base_string
;
11468 /* Skip past '(' and whitespace. */
11470 if (is_space_char (*base_string
))
11473 if (*base_string
== ','
11474 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11477 displacement_string_end
= temp_string
;
11479 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11483 if (i
.base_reg
== &bad_reg
)
11485 base_string
= end_op
;
11486 if (is_space_char (*base_string
))
11490 /* There may be an index reg or scale factor here. */
11491 if (*base_string
== ',')
11494 if (is_space_char (*base_string
))
11497 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11500 if (i
.index_reg
== &bad_reg
)
11502 base_string
= end_op
;
11503 if (is_space_char (*base_string
))
11505 if (*base_string
== ',')
11508 if (is_space_char (*base_string
))
11511 else if (*base_string
!= ')')
11513 as_bad (_("expecting `,' or `)' "
11514 "after index register in `%s'"),
11519 else if (*base_string
== REGISTER_PREFIX
)
11521 end_op
= strchr (base_string
, ',');
11524 as_bad (_("bad register name `%s'"), base_string
);
11528 /* Check for scale factor. */
11529 if (*base_string
!= ')')
11531 char *end_scale
= i386_scale (base_string
);
11536 base_string
= end_scale
;
11537 if (is_space_char (*base_string
))
11539 if (*base_string
!= ')')
11541 as_bad (_("expecting `)' "
11542 "after scale factor in `%s'"),
11547 else if (!i
.index_reg
)
11549 as_bad (_("expecting index register or scale factor "
11550 "after `,'; got '%c'"),
11555 else if (*base_string
!= ')')
11557 as_bad (_("expecting `,' or `)' "
11558 "after base register in `%s'"),
11563 else if (*base_string
== REGISTER_PREFIX
)
11565 end_op
= strchr (base_string
, ',');
11568 as_bad (_("bad register name `%s'"), base_string
);
11573 /* If there's an expression beginning the operand, parse it,
11574 assuming displacement_string_start and
11575 displacement_string_end are meaningful. */
11576 if (displacement_string_start
!= displacement_string_end
)
11578 if (!i386_displacement (displacement_string_start
,
11579 displacement_string_end
))
11583 /* Special case for (%dx) while doing input/output op. */
11585 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11586 && i
.base_reg
->reg_type
.bitfield
.word
11587 && i
.index_reg
== 0
11588 && i
.log2_scale_factor
== 0
11589 && i
.seg
[i
.mem_operands
] == 0
11590 && !operand_type_check (i
.types
[this_operand
], disp
))
11592 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11596 if (i386_index_check (operand_string
) == 0)
11598 i
.flags
[this_operand
] |= Operand_Mem
;
11599 if (i
.mem_operands
== 0)
11600 i
.memop1_string
= xstrdup (operand_string
);
11605 /* It's not a memory operand; argh! */
11606 as_bad (_("invalid char %s beginning operand %d `%s'"),
11607 output_invalid (*op_string
),
11612 return 1; /* Normal return. */
11615 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11616 that an rs_machine_dependent frag may reach. */
11619 i386_frag_max_var (fragS
*frag
)
11621 /* The only relaxable frags are for jumps.
11622 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11623 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11624 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11629 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11631 /* STT_GNU_IFUNC symbol must go through PLT. */
11632 if ((symbol_get_bfdsym (fr_symbol
)->flags
11633 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11636 if (!S_IS_EXTERNAL (fr_symbol
))
11637 /* Symbol may be weak or local. */
11638 return !S_IS_WEAK (fr_symbol
);
11640 /* Global symbols with non-default visibility can't be preempted. */
11641 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11644 if (fr_var
!= NO_RELOC
)
11645 switch ((enum bfd_reloc_code_real
) fr_var
)
11647 case BFD_RELOC_386_PLT32
:
11648 case BFD_RELOC_X86_64_PLT32
:
11649 /* Symbol with PLT relocation may be preempted. */
11655 /* Global symbols with default visibility in a shared library may be
11656 preempted by another definition. */
11661 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11662 Note also work for Skylake and Cascadelake.
11663 ---------------------------------------------------------------------
11664 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11665 | ------ | ----------- | ------- | -------- |
11667 | Jno | N | N | Y |
11668 | Jc/Jb | Y | N | Y |
11669 | Jae/Jnb | Y | N | Y |
11670 | Je/Jz | Y | Y | Y |
11671 | Jne/Jnz | Y | Y | Y |
11672 | Jna/Jbe | Y | N | Y |
11673 | Ja/Jnbe | Y | N | Y |
11675 | Jns | N | N | Y |
11676 | Jp/Jpe | N | N | Y |
11677 | Jnp/Jpo | N | N | Y |
11678 | Jl/Jnge | Y | Y | Y |
11679 | Jge/Jnl | Y | Y | Y |
11680 | Jle/Jng | Y | Y | Y |
11681 | Jg/Jnle | Y | Y | Y |
11682 --------------------------------------------------------------------- */
11684 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11686 if (mf_cmp
== mf_cmp_alu_cmp
)
11687 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11688 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11689 if (mf_cmp
== mf_cmp_incdec
)
11690 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11691 || mf_jcc
== mf_jcc_jle
);
11692 if (mf_cmp
== mf_cmp_test_and
)
11697 /* Return the next non-empty frag. */
11700 i386_next_non_empty_frag (fragS
*fragP
)
11702 /* There may be a frag with a ".fill 0" when there is no room in
11703 the current frag for frag_grow in output_insn. */
11704 for (fragP
= fragP
->fr_next
;
11706 && fragP
->fr_type
== rs_fill
11707 && fragP
->fr_fix
== 0);
11708 fragP
= fragP
->fr_next
)
11713 /* Return the next jcc frag after BRANCH_PADDING. */
11716 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11718 fragS
*branch_fragP
;
11722 if (pad_fragP
->fr_type
== rs_machine_dependent
11723 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11724 == BRANCH_PADDING
))
11726 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11727 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11729 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11730 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11731 pad_fragP
->tc_frag_data
.mf_type
))
11732 return branch_fragP
;
11738 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11741 i386_classify_machine_dependent_frag (fragS
*fragP
)
11745 fragS
*branch_fragP
;
11747 unsigned int max_prefix_length
;
11749 if (fragP
->tc_frag_data
.classified
)
11752 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11753 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11754 for (next_fragP
= fragP
;
11755 next_fragP
!= NULL
;
11756 next_fragP
= next_fragP
->fr_next
)
11758 next_fragP
->tc_frag_data
.classified
= 1;
11759 if (next_fragP
->fr_type
== rs_machine_dependent
)
11760 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11762 case BRANCH_PADDING
:
11763 /* The BRANCH_PADDING frag must be followed by a branch
11765 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11766 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11768 case FUSED_JCC_PADDING
:
11769 /* Check if this is a fused jcc:
11771 CMP like instruction
11775 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11776 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11777 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11780 /* The BRANCH_PADDING frag is merged with the
11781 FUSED_JCC_PADDING frag. */
11782 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11783 /* CMP like instruction size. */
11784 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11785 frag_wane (pad_fragP
);
11786 /* Skip to branch_fragP. */
11787 next_fragP
= branch_fragP
;
11789 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11791 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11793 next_fragP
->fr_subtype
11794 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11795 next_fragP
->tc_frag_data
.max_bytes
11796 = next_fragP
->tc_frag_data
.max_prefix_length
;
11797 /* This will be updated in the BRANCH_PREFIX scan. */
11798 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11801 frag_wane (next_fragP
);
11806 /* Stop if there is no BRANCH_PREFIX. */
11807 if (!align_branch_prefix_size
)
11810 /* Scan for BRANCH_PREFIX. */
11811 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11813 if (fragP
->fr_type
!= rs_machine_dependent
11814 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11818 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11819 COND_JUMP_PREFIX. */
11820 max_prefix_length
= 0;
11821 for (next_fragP
= fragP
;
11822 next_fragP
!= NULL
;
11823 next_fragP
= next_fragP
->fr_next
)
11825 if (next_fragP
->fr_type
== rs_fill
)
11826 /* Skip rs_fill frags. */
11828 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11829 /* Stop for all other frags. */
11832 /* rs_machine_dependent frags. */
11833 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11836 /* Count BRANCH_PREFIX frags. */
11837 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11839 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11840 frag_wane (next_fragP
);
11844 += next_fragP
->tc_frag_data
.max_bytes
;
11846 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11848 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11849 == FUSED_JCC_PADDING
))
11851 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11852 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11856 /* Stop for other rs_machine_dependent frags. */
11860 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11862 /* Skip to the next frag. */
11863 fragP
= next_fragP
;
11867 /* Compute padding size for
11870 CMP like instruction
11872 COND_JUMP/UNCOND_JUMP
11877 COND_JUMP/UNCOND_JUMP
11881 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11883 unsigned int offset
, size
, padding_size
;
11884 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11886 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11888 address
= fragP
->fr_address
;
11889 address
+= fragP
->fr_fix
;
11891 /* CMP like instrunction size. */
11892 size
= fragP
->tc_frag_data
.cmp_size
;
11894 /* The base size of the branch frag. */
11895 size
+= branch_fragP
->fr_fix
;
11897 /* Add opcode and displacement bytes for the rs_machine_dependent
11899 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11900 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11902 /* Check if branch is within boundary and doesn't end at the last
11904 offset
= address
& ((1U << align_branch_power
) - 1);
11905 if ((offset
+ size
) >= (1U << align_branch_power
))
11906 /* Padding needed to avoid crossing boundary. */
11907 padding_size
= (1U << align_branch_power
) - offset
;
11909 /* No padding needed. */
11912 /* The return value may be saved in tc_frag_data.length which is
11914 if (!fits_in_unsigned_byte (padding_size
))
11917 return padding_size
;
11920 /* i386_generic_table_relax_frag()
11922 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11923 grow/shrink padding to align branch frags. Hand others to
11927 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11929 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11930 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11932 long padding_size
= i386_branch_padding_size (fragP
, 0);
11933 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11935 /* When the BRANCH_PREFIX frag is used, the computed address
11936 must match the actual address and there should be no padding. */
11937 if (fragP
->tc_frag_data
.padding_address
11938 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11942 /* Update the padding size. */
11944 fragP
->tc_frag_data
.length
= padding_size
;
11948 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11950 fragS
*padding_fragP
, *next_fragP
;
11951 long padding_size
, left_size
, last_size
;
11953 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11954 if (!padding_fragP
)
11955 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11956 return (fragP
->tc_frag_data
.length
11957 - fragP
->tc_frag_data
.last_length
);
11959 /* Compute the relative address of the padding frag in the very
11960 first time where the BRANCH_PREFIX frag sizes are zero. */
11961 if (!fragP
->tc_frag_data
.padding_address
)
11962 fragP
->tc_frag_data
.padding_address
11963 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11965 /* First update the last length from the previous interation. */
11966 left_size
= fragP
->tc_frag_data
.prefix_length
;
11967 for (next_fragP
= fragP
;
11968 next_fragP
!= padding_fragP
;
11969 next_fragP
= next_fragP
->fr_next
)
11970 if (next_fragP
->fr_type
== rs_machine_dependent
11971 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11976 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11980 if (max
> left_size
)
11985 next_fragP
->tc_frag_data
.last_length
= size
;
11989 next_fragP
->tc_frag_data
.last_length
= 0;
11992 /* Check the padding size for the padding frag. */
11993 padding_size
= i386_branch_padding_size
11994 (padding_fragP
, (fragP
->fr_address
11995 + fragP
->tc_frag_data
.padding_address
));
11997 last_size
= fragP
->tc_frag_data
.prefix_length
;
11998 /* Check if there is change from the last interation. */
11999 if (padding_size
== last_size
)
12001 /* Update the expected address of the padding frag. */
12002 padding_fragP
->tc_frag_data
.padding_address
12003 = (fragP
->fr_address
+ padding_size
12004 + fragP
->tc_frag_data
.padding_address
);
12008 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12010 /* No padding if there is no sufficient room. Clear the
12011 expected address of the padding frag. */
12012 padding_fragP
->tc_frag_data
.padding_address
= 0;
12016 /* Store the expected address of the padding frag. */
12017 padding_fragP
->tc_frag_data
.padding_address
12018 = (fragP
->fr_address
+ padding_size
12019 + fragP
->tc_frag_data
.padding_address
);
12021 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12023 /* Update the length for the current interation. */
12024 left_size
= padding_size
;
12025 for (next_fragP
= fragP
;
12026 next_fragP
!= padding_fragP
;
12027 next_fragP
= next_fragP
->fr_next
)
12028 if (next_fragP
->fr_type
== rs_machine_dependent
12029 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12034 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12038 if (max
> left_size
)
12043 next_fragP
->tc_frag_data
.length
= size
;
12047 next_fragP
->tc_frag_data
.length
= 0;
12050 return (fragP
->tc_frag_data
.length
12051 - fragP
->tc_frag_data
.last_length
);
12053 return relax_frag (segment
, fragP
, stretch
);
12056 /* md_estimate_size_before_relax()
12058 Called just before relax() for rs_machine_dependent frags. The x86
12059 assembler uses these frags to handle variable size jump
12062 Any symbol that is now undefined will not become defined.
12063 Return the correct fr_subtype in the frag.
12064 Return the initial "guess for variable size of frag" to caller.
12065 The guess is actually the growth beyond the fixed part. Whatever
12066 we do to grow the fixed or variable part contributes to our
12070 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12072 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12073 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12074 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12076 i386_classify_machine_dependent_frag (fragP
);
12077 return fragP
->tc_frag_data
.length
;
12080 /* We've already got fragP->fr_subtype right; all we have to do is
12081 check for un-relaxable symbols. On an ELF system, we can't relax
12082 an externally visible symbol, because it may be overridden by a
12084 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12085 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12087 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12090 #if defined (OBJ_COFF) && defined (TE_PE)
12091 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12092 && S_IS_WEAK (fragP
->fr_symbol
))
12096 /* Symbol is undefined in this segment, or we need to keep a
12097 reloc so that weak symbols can be overridden. */
12098 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12099 enum bfd_reloc_code_real reloc_type
;
12100 unsigned char *opcode
;
12103 if (fragP
->fr_var
!= NO_RELOC
)
12104 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12105 else if (size
== 2)
12106 reloc_type
= BFD_RELOC_16_PCREL
;
12107 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12108 else if (need_plt32_p (fragP
->fr_symbol
))
12109 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12112 reloc_type
= BFD_RELOC_32_PCREL
;
12114 old_fr_fix
= fragP
->fr_fix
;
12115 opcode
= (unsigned char *) fragP
->fr_opcode
;
12117 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12120 /* Make jmp (0xeb) a (d)word displacement jump. */
12122 fragP
->fr_fix
+= size
;
12123 fix_new (fragP
, old_fr_fix
, size
,
12125 fragP
->fr_offset
, 1,
12131 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12133 /* Negate the condition, and branch past an
12134 unconditional jump. */
12137 /* Insert an unconditional jump. */
12139 /* We added two extra opcode bytes, and have a two byte
12141 fragP
->fr_fix
+= 2 + 2;
12142 fix_new (fragP
, old_fr_fix
+ 2, 2,
12144 fragP
->fr_offset
, 1,
12148 /* Fall through. */
12151 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12155 fragP
->fr_fix
+= 1;
12156 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12158 fragP
->fr_offset
, 1,
12159 BFD_RELOC_8_PCREL
);
12160 fixP
->fx_signed
= 1;
12164 /* This changes the byte-displacement jump 0x7N
12165 to the (d)word-displacement jump 0x0f,0x8N. */
12166 opcode
[1] = opcode
[0] + 0x10;
12167 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12168 /* We've added an opcode byte. */
12169 fragP
->fr_fix
+= 1 + size
;
12170 fix_new (fragP
, old_fr_fix
+ 1, size
,
12172 fragP
->fr_offset
, 1,
12177 BAD_CASE (fragP
->fr_subtype
);
12181 return fragP
->fr_fix
- old_fr_fix
;
12184 /* Guess size depending on current relax state. Initially the relax
12185 state will correspond to a short jump and we return 1, because
12186 the variable part of the frag (the branch offset) is one byte
12187 long. However, we can relax a section more than once and in that
12188 case we must either set fr_subtype back to the unrelaxed state,
12189 or return the value for the appropriate branch. */
12190 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12193 /* Called after relax() is finished.
12195 In: Address of frag.
12196 fr_type == rs_machine_dependent.
12197 fr_subtype is what the address relaxed to.
12199 Out: Any fixSs and constants are set up.
12200 Caller will turn frag into a ".space 0". */
12203 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12206 unsigned char *opcode
;
12207 unsigned char *where_to_put_displacement
= NULL
;
12208 offsetT target_address
;
12209 offsetT opcode_address
;
12210 unsigned int extension
= 0;
12211 offsetT displacement_from_opcode_start
;
12213 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12214 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12215 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12217 /* Generate nop padding. */
12218 unsigned int size
= fragP
->tc_frag_data
.length
;
12221 if (size
> fragP
->tc_frag_data
.max_bytes
)
12227 const char *branch
= "branch";
12228 const char *prefix
= "";
12229 fragS
*padding_fragP
;
12230 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12233 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12234 switch (fragP
->tc_frag_data
.default_prefix
)
12239 case CS_PREFIX_OPCODE
:
12242 case DS_PREFIX_OPCODE
:
12245 case ES_PREFIX_OPCODE
:
12248 case FS_PREFIX_OPCODE
:
12251 case GS_PREFIX_OPCODE
:
12254 case SS_PREFIX_OPCODE
:
12259 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12260 "%s within %d-byte boundary\n");
12262 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12263 "align %s within %d-byte boundary\n");
12267 padding_fragP
= fragP
;
12268 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12269 "%s within %d-byte boundary\n");
12273 switch (padding_fragP
->tc_frag_data
.branch_type
)
12275 case align_branch_jcc
:
12278 case align_branch_fused
:
12279 branch
= "fused jcc";
12281 case align_branch_jmp
:
12284 case align_branch_call
:
12287 case align_branch_indirect
:
12288 branch
= "indiret branch";
12290 case align_branch_ret
:
12297 fprintf (stdout
, msg
,
12298 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12299 (long long) fragP
->fr_address
, branch
,
12300 1 << align_branch_power
);
12302 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12303 memset (fragP
->fr_opcode
,
12304 fragP
->tc_frag_data
.default_prefix
, size
);
12306 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12308 fragP
->fr_fix
+= size
;
12313 opcode
= (unsigned char *) fragP
->fr_opcode
;
12315 /* Address we want to reach in file space. */
12316 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12318 /* Address opcode resides at in file space. */
12319 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12321 /* Displacement from opcode start to fill into instruction. */
12322 displacement_from_opcode_start
= target_address
- opcode_address
;
12324 if ((fragP
->fr_subtype
& BIG
) == 0)
12326 /* Don't have to change opcode. */
12327 extension
= 1; /* 1 opcode + 1 displacement */
12328 where_to_put_displacement
= &opcode
[1];
12332 if (no_cond_jump_promotion
12333 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12334 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12335 _("long jump required"));
12337 switch (fragP
->fr_subtype
)
12339 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12340 extension
= 4; /* 1 opcode + 4 displacement */
12342 where_to_put_displacement
= &opcode
[1];
12345 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12346 extension
= 2; /* 1 opcode + 2 displacement */
12348 where_to_put_displacement
= &opcode
[1];
12351 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12352 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12353 extension
= 5; /* 2 opcode + 4 displacement */
12354 opcode
[1] = opcode
[0] + 0x10;
12355 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12356 where_to_put_displacement
= &opcode
[2];
12359 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12360 extension
= 3; /* 2 opcode + 2 displacement */
12361 opcode
[1] = opcode
[0] + 0x10;
12362 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12363 where_to_put_displacement
= &opcode
[2];
12366 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12371 where_to_put_displacement
= &opcode
[3];
12375 BAD_CASE (fragP
->fr_subtype
);
12380 /* If size if less then four we are sure that the operand fits,
12381 but if it's 4, then it could be that the displacement is larger
12383 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12385 && ((addressT
) (displacement_from_opcode_start
- extension
12386 + ((addressT
) 1 << 31))
12387 > (((addressT
) 2 << 31) - 1)))
12389 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12390 _("jump target out of range"));
12391 /* Make us emit 0. */
12392 displacement_from_opcode_start
= extension
;
12394 /* Now put displacement after opcode. */
12395 md_number_to_chars ((char *) where_to_put_displacement
,
12396 (valueT
) (displacement_from_opcode_start
- extension
),
12397 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12398 fragP
->fr_fix
+= extension
;
12401 /* Apply a fixup (fixP) to segment data, once it has been determined
12402 by our caller that we have all the info we need to fix it up.
12404 Parameter valP is the pointer to the value of the bits.
12406 On the 386, immediates, displacements, and data pointers are all in
12407 the same (little-endian) format, so we don't need to care about which
12408 we are handling. */
12411 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12413 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12414 valueT value
= *valP
;
12416 #if !defined (TE_Mach)
12417 if (fixP
->fx_pcrel
)
12419 switch (fixP
->fx_r_type
)
12425 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12428 case BFD_RELOC_X86_64_32S
:
12429 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12432 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12435 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12440 if (fixP
->fx_addsy
!= NULL
12441 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12442 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12443 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12444 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12445 && !use_rela_relocations
)
12447 /* This is a hack. There should be a better way to handle this.
12448 This covers for the fact that bfd_install_relocation will
12449 subtract the current location (for partial_inplace, PC relative
12450 relocations); see more below. */
12454 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12457 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12462 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12464 if ((sym_seg
== seg
12465 || (symbol_section_p (fixP
->fx_addsy
)
12466 && sym_seg
!= absolute_section
))
12467 && !generic_force_reloc (fixP
))
12469 /* Yes, we add the values in twice. This is because
12470 bfd_install_relocation subtracts them out again. I think
12471 bfd_install_relocation is broken, but I don't dare change
12473 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12477 #if defined (OBJ_COFF) && defined (TE_PE)
12478 /* For some reason, the PE format does not store a
12479 section address offset for a PC relative symbol. */
12480 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12481 || S_IS_WEAK (fixP
->fx_addsy
))
12482 value
+= md_pcrel_from (fixP
);
12485 #if defined (OBJ_COFF) && defined (TE_PE)
12486 if (fixP
->fx_addsy
!= NULL
12487 && S_IS_WEAK (fixP
->fx_addsy
)
12488 /* PR 16858: Do not modify weak function references. */
12489 && ! fixP
->fx_pcrel
)
12491 #if !defined (TE_PEP)
12492 /* For x86 PE weak function symbols are neither PC-relative
12493 nor do they set S_IS_FUNCTION. So the only reliable way
12494 to detect them is to check the flags of their containing
12496 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12497 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12501 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12505 /* Fix a few things - the dynamic linker expects certain values here,
12506 and we must not disappoint it. */
12507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12508 if (IS_ELF
&& fixP
->fx_addsy
)
12509 switch (fixP
->fx_r_type
)
12511 case BFD_RELOC_386_PLT32
:
12512 case BFD_RELOC_X86_64_PLT32
:
12513 /* Make the jump instruction point to the address of the operand.
12514 At runtime we merely add the offset to the actual PLT entry.
12515 NB: Subtract the offset size only for jump instructions. */
12516 if (fixP
->fx_pcrel
)
12520 case BFD_RELOC_386_TLS_GD
:
12521 case BFD_RELOC_386_TLS_LDM
:
12522 case BFD_RELOC_386_TLS_IE_32
:
12523 case BFD_RELOC_386_TLS_IE
:
12524 case BFD_RELOC_386_TLS_GOTIE
:
12525 case BFD_RELOC_386_TLS_GOTDESC
:
12526 case BFD_RELOC_X86_64_TLSGD
:
12527 case BFD_RELOC_X86_64_TLSLD
:
12528 case BFD_RELOC_X86_64_GOTTPOFF
:
12529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12530 value
= 0; /* Fully resolved at runtime. No addend. */
12532 case BFD_RELOC_386_TLS_LE
:
12533 case BFD_RELOC_386_TLS_LDO_32
:
12534 case BFD_RELOC_386_TLS_LE_32
:
12535 case BFD_RELOC_X86_64_DTPOFF32
:
12536 case BFD_RELOC_X86_64_DTPOFF64
:
12537 case BFD_RELOC_X86_64_TPOFF32
:
12538 case BFD_RELOC_X86_64_TPOFF64
:
12539 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12542 case BFD_RELOC_386_TLS_DESC_CALL
:
12543 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12544 value
= 0; /* Fully resolved at runtime. No addend. */
12545 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12549 case BFD_RELOC_VTABLE_INHERIT
:
12550 case BFD_RELOC_VTABLE_ENTRY
:
12557 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12559 #endif /* !defined (TE_Mach) */
12561 /* Are we finished with this relocation now? */
12562 if (fixP
->fx_addsy
== NULL
)
12564 #if defined (OBJ_COFF) && defined (TE_PE)
12565 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12568 /* Remember value for tc_gen_reloc. */
12569 fixP
->fx_addnumber
= value
;
12570 /* Clear out the frag for now. */
12574 else if (use_rela_relocations
)
12576 fixP
->fx_no_overflow
= 1;
12577 /* Remember value for tc_gen_reloc. */
12578 fixP
->fx_addnumber
= value
;
12582 md_number_to_chars (p
, value
, fixP
->fx_size
);
12586 md_atof (int type
, char *litP
, int *sizeP
)
12588 /* This outputs the LITTLENUMs in REVERSE order;
12589 in accord with the bigendian 386. */
12590 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12593 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12596 output_invalid (int c
)
12599 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12602 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12603 "(0x%x)", (unsigned char) c
);
12604 return output_invalid_buf
;
12607 /* Verify that @r can be used in the current context. */
12609 static bfd_boolean
check_register (const reg_entry
*r
)
12611 if (allow_pseudo_reg
)
12614 if (operand_type_all_zero (&r
->reg_type
))
12617 if ((r
->reg_type
.bitfield
.dword
12618 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12619 || r
->reg_type
.bitfield
.class == RegCR
12620 || r
->reg_type
.bitfield
.class == RegDR
)
12621 && !cpu_arch_flags
.bitfield
.cpui386
)
12624 if (r
->reg_type
.bitfield
.class == RegTR
12625 && (flag_code
== CODE_64BIT
12626 || !cpu_arch_flags
.bitfield
.cpui386
12627 || cpu_arch_isa_flags
.bitfield
.cpui586
12628 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12631 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12634 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12636 if (r
->reg_type
.bitfield
.zmmword
12637 || r
->reg_type
.bitfield
.class == RegMask
)
12640 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12642 if (r
->reg_type
.bitfield
.ymmword
)
12645 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12650 if (r
->reg_type
.bitfield
.tmmword
12651 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12652 || flag_code
!= CODE_64BIT
))
12655 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12658 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12659 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12662 /* Upper 16 vector registers are only available with VREX in 64bit
12663 mode, and require EVEX encoding. */
12664 if (r
->reg_flags
& RegVRex
)
12666 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12667 || flag_code
!= CODE_64BIT
)
12670 if (i
.vec_encoding
== vex_encoding_default
)
12671 i
.vec_encoding
= vex_encoding_evex
;
12672 else if (i
.vec_encoding
!= vex_encoding_evex
)
12673 i
.vec_encoding
= vex_encoding_error
;
12676 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12677 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12678 && flag_code
!= CODE_64BIT
)
12681 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12688 /* REG_STRING starts *before* REGISTER_PREFIX. */
12690 static const reg_entry
*
12691 parse_real_register (char *reg_string
, char **end_op
)
12693 char *s
= reg_string
;
12695 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12696 const reg_entry
*r
;
12698 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12699 if (*s
== REGISTER_PREFIX
)
12702 if (is_space_char (*s
))
12705 p
= reg_name_given
;
12706 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12708 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12709 return (const reg_entry
*) NULL
;
12713 /* For naked regs, make sure that we are not dealing with an identifier.
12714 This prevents confusing an identifier like `eax_var' with register
12716 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12717 return (const reg_entry
*) NULL
;
12721 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12723 /* Handle floating point regs, allowing spaces in the (i) part. */
12724 if (r
== i386_regtab
/* %st is first entry of table */)
12726 if (!cpu_arch_flags
.bitfield
.cpu8087
12727 && !cpu_arch_flags
.bitfield
.cpu287
12728 && !cpu_arch_flags
.bitfield
.cpu387
12729 && !allow_pseudo_reg
)
12730 return (const reg_entry
*) NULL
;
12732 if (is_space_char (*s
))
12737 if (is_space_char (*s
))
12739 if (*s
>= '0' && *s
<= '7')
12741 int fpr
= *s
- '0';
12743 if (is_space_char (*s
))
12748 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12753 /* We have "%st(" then garbage. */
12754 return (const reg_entry
*) NULL
;
12758 return r
&& check_register (r
) ? r
: NULL
;
12761 /* REG_STRING starts *before* REGISTER_PREFIX. */
12763 static const reg_entry
*
12764 parse_register (char *reg_string
, char **end_op
)
12766 const reg_entry
*r
;
12768 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12769 r
= parse_real_register (reg_string
, end_op
);
12774 char *save
= input_line_pointer
;
12778 input_line_pointer
= reg_string
;
12779 c
= get_symbol_name (®_string
);
12780 symbolP
= symbol_find (reg_string
);
12781 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12783 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12785 know (e
->X_op
== O_register
);
12786 know (e
->X_add_number
>= 0
12787 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12788 r
= i386_regtab
+ e
->X_add_number
;
12789 if (!check_register (r
))
12791 as_bad (_("register '%s%s' cannot be used here"),
12792 register_prefix
, r
->reg_name
);
12795 *end_op
= input_line_pointer
;
12797 *input_line_pointer
= c
;
12798 input_line_pointer
= save
;
12804 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12806 const reg_entry
*r
;
12807 char *end
= input_line_pointer
;
12810 r
= parse_register (name
, &input_line_pointer
);
12811 if (r
&& end
<= input_line_pointer
)
12813 *nextcharP
= *input_line_pointer
;
12814 *input_line_pointer
= 0;
12817 e
->X_op
= O_register
;
12818 e
->X_add_number
= r
- i386_regtab
;
12821 e
->X_op
= O_illegal
;
12824 input_line_pointer
= end
;
12826 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12830 md_operand (expressionS
*e
)
12833 const reg_entry
*r
;
12835 switch (*input_line_pointer
)
12837 case REGISTER_PREFIX
:
12838 r
= parse_real_register (input_line_pointer
, &end
);
12841 e
->X_op
= O_register
;
12842 e
->X_add_number
= r
- i386_regtab
;
12843 input_line_pointer
= end
;
12848 gas_assert (intel_syntax
);
12849 end
= input_line_pointer
++;
12851 if (*input_line_pointer
== ']')
12853 ++input_line_pointer
;
12854 e
->X_op_symbol
= make_expr_symbol (e
);
12855 e
->X_add_symbol
= NULL
;
12856 e
->X_add_number
= 0;
12861 e
->X_op
= O_absent
;
12862 input_line_pointer
= end
;
12869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12870 const char *md_shortopts
= "kVQ:sqnO::";
12872 const char *md_shortopts
= "qnO::";
12875 #define OPTION_32 (OPTION_MD_BASE + 0)
12876 #define OPTION_64 (OPTION_MD_BASE + 1)
12877 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12878 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12879 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12880 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12881 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12882 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12883 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12884 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12885 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12886 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12887 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12888 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12889 #define OPTION_X32 (OPTION_MD_BASE + 14)
12890 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12891 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12892 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12893 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12894 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12895 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12896 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12897 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12898 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12899 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12900 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12901 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12902 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12903 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12904 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12905 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12906 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12907 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12908 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12910 struct option md_longopts
[] =
12912 {"32", no_argument
, NULL
, OPTION_32
},
12913 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12914 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12915 {"64", no_argument
, NULL
, OPTION_64
},
12917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12918 {"x32", no_argument
, NULL
, OPTION_X32
},
12919 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12920 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12922 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12923 {"march", required_argument
, NULL
, OPTION_MARCH
},
12924 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12925 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12926 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12927 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12928 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12929 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12930 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12931 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12932 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12933 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12934 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12935 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12936 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12937 # if defined (TE_PE) || defined (TE_PEP)
12938 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12940 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12941 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12942 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12943 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12944 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12945 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12946 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12947 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12948 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12949 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12950 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12951 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12952 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12953 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12954 {NULL
, no_argument
, NULL
, 0}
12956 size_t md_longopts_size
= sizeof (md_longopts
);
12959 md_parse_option (int c
, const char *arg
)
12962 char *arch
, *next
, *saved
, *type
;
12967 optimize_align_code
= 0;
12971 quiet_warnings
= 1;
12974 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12975 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12976 should be emitted or not. FIXME: Not implemented. */
12978 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12982 /* -V: SVR4 argument to print version ID. */
12984 print_version_id ();
12987 /* -k: Ignore for FreeBSD compatibility. */
12992 /* -s: On i386 Solaris, this tells the native assembler to use
12993 .stab instead of .stab.excl. We always use .stab anyhow. */
12996 case OPTION_MSHARED
:
13000 case OPTION_X86_USED_NOTE
:
13001 if (strcasecmp (arg
, "yes") == 0)
13003 else if (strcasecmp (arg
, "no") == 0)
13006 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13011 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13012 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13015 const char **list
, **l
;
13017 list
= bfd_target_list ();
13018 for (l
= list
; *l
!= NULL
; l
++)
13019 if (CONST_STRNEQ (*l
, "elf64-x86-64")
13020 || strcmp (*l
, "coff-x86-64") == 0
13021 || strcmp (*l
, "pe-x86-64") == 0
13022 || strcmp (*l
, "pei-x86-64") == 0
13023 || strcmp (*l
, "mach-o-x86-64") == 0)
13025 default_arch
= "x86_64";
13029 as_fatal (_("no compiled in support for x86_64"));
13035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13039 const char **list
, **l
;
13041 list
= bfd_target_list ();
13042 for (l
= list
; *l
!= NULL
; l
++)
13043 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
13045 default_arch
= "x86_64:32";
13049 as_fatal (_("no compiled in support for 32bit x86_64"));
13053 as_fatal (_("32bit x86_64 is only supported for ELF"));
13058 default_arch
= "i386";
13061 case OPTION_DIVIDE
:
13062 #ifdef SVR4_COMMENT_CHARS
13067 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13069 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13073 i386_comment_chars
= n
;
13079 saved
= xstrdup (arg
);
13081 /* Allow -march=+nosse. */
13087 as_fatal (_("invalid -march= option: `%s'"), arg
);
13088 next
= strchr (arch
, '+');
13091 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13093 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13096 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13099 cpu_arch_name
= cpu_arch
[j
].name
;
13100 cpu_sub_arch_name
= NULL
;
13101 cpu_arch_flags
= cpu_arch
[j
].flags
;
13102 cpu_arch_isa
= cpu_arch
[j
].type
;
13103 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13104 if (!cpu_arch_tune_set
)
13106 cpu_arch_tune
= cpu_arch_isa
;
13107 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13111 else if (*cpu_arch
[j
].name
== '.'
13112 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13114 /* ISA extension. */
13115 i386_cpu_flags flags
;
13117 flags
= cpu_flags_or (cpu_arch_flags
,
13118 cpu_arch
[j
].flags
);
13120 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13122 if (cpu_sub_arch_name
)
13124 char *name
= cpu_sub_arch_name
;
13125 cpu_sub_arch_name
= concat (name
,
13127 (const char *) NULL
);
13131 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13132 cpu_arch_flags
= flags
;
13133 cpu_arch_isa_flags
= flags
;
13137 = cpu_flags_or (cpu_arch_isa_flags
,
13138 cpu_arch
[j
].flags
);
13143 if (j
>= ARRAY_SIZE (cpu_arch
))
13145 /* Disable an ISA extension. */
13146 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13147 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13149 i386_cpu_flags flags
;
13151 flags
= cpu_flags_and_not (cpu_arch_flags
,
13152 cpu_noarch
[j
].flags
);
13153 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13155 if (cpu_sub_arch_name
)
13157 char *name
= cpu_sub_arch_name
;
13158 cpu_sub_arch_name
= concat (arch
,
13159 (const char *) NULL
);
13163 cpu_sub_arch_name
= xstrdup (arch
);
13164 cpu_arch_flags
= flags
;
13165 cpu_arch_isa_flags
= flags
;
13170 if (j
>= ARRAY_SIZE (cpu_noarch
))
13171 j
= ARRAY_SIZE (cpu_arch
);
13174 if (j
>= ARRAY_SIZE (cpu_arch
))
13175 as_fatal (_("invalid -march= option: `%s'"), arg
);
13179 while (next
!= NULL
);
13185 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13186 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13188 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13190 cpu_arch_tune_set
= 1;
13191 cpu_arch_tune
= cpu_arch
[j
].type
;
13192 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13196 if (j
>= ARRAY_SIZE (cpu_arch
))
13197 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13200 case OPTION_MMNEMONIC
:
13201 if (strcasecmp (arg
, "att") == 0)
13202 intel_mnemonic
= 0;
13203 else if (strcasecmp (arg
, "intel") == 0)
13204 intel_mnemonic
= 1;
13206 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13209 case OPTION_MSYNTAX
:
13210 if (strcasecmp (arg
, "att") == 0)
13212 else if (strcasecmp (arg
, "intel") == 0)
13215 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13218 case OPTION_MINDEX_REG
:
13219 allow_index_reg
= 1;
13222 case OPTION_MNAKED_REG
:
13223 allow_naked_reg
= 1;
13226 case OPTION_MSSE2AVX
:
13230 case OPTION_MSSE_CHECK
:
13231 if (strcasecmp (arg
, "error") == 0)
13232 sse_check
= check_error
;
13233 else if (strcasecmp (arg
, "warning") == 0)
13234 sse_check
= check_warning
;
13235 else if (strcasecmp (arg
, "none") == 0)
13236 sse_check
= check_none
;
13238 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13241 case OPTION_MOPERAND_CHECK
:
13242 if (strcasecmp (arg
, "error") == 0)
13243 operand_check
= check_error
;
13244 else if (strcasecmp (arg
, "warning") == 0)
13245 operand_check
= check_warning
;
13246 else if (strcasecmp (arg
, "none") == 0)
13247 operand_check
= check_none
;
13249 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13252 case OPTION_MAVXSCALAR
:
13253 if (strcasecmp (arg
, "128") == 0)
13254 avxscalar
= vex128
;
13255 else if (strcasecmp (arg
, "256") == 0)
13256 avxscalar
= vex256
;
13258 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13261 case OPTION_MVEXWIG
:
13262 if (strcmp (arg
, "0") == 0)
13264 else if (strcmp (arg
, "1") == 0)
13267 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13270 case OPTION_MADD_BND_PREFIX
:
13271 add_bnd_prefix
= 1;
13274 case OPTION_MEVEXLIG
:
13275 if (strcmp (arg
, "128") == 0)
13276 evexlig
= evexl128
;
13277 else if (strcmp (arg
, "256") == 0)
13278 evexlig
= evexl256
;
13279 else if (strcmp (arg
, "512") == 0)
13280 evexlig
= evexl512
;
13282 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13285 case OPTION_MEVEXRCIG
:
13286 if (strcmp (arg
, "rne") == 0)
13288 else if (strcmp (arg
, "rd") == 0)
13290 else if (strcmp (arg
, "ru") == 0)
13292 else if (strcmp (arg
, "rz") == 0)
13295 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13298 case OPTION_MEVEXWIG
:
13299 if (strcmp (arg
, "0") == 0)
13301 else if (strcmp (arg
, "1") == 0)
13304 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13307 # if defined (TE_PE) || defined (TE_PEP)
13308 case OPTION_MBIG_OBJ
:
13313 case OPTION_MOMIT_LOCK_PREFIX
:
13314 if (strcasecmp (arg
, "yes") == 0)
13315 omit_lock_prefix
= 1;
13316 else if (strcasecmp (arg
, "no") == 0)
13317 omit_lock_prefix
= 0;
13319 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13322 case OPTION_MFENCE_AS_LOCK_ADD
:
13323 if (strcasecmp (arg
, "yes") == 0)
13325 else if (strcasecmp (arg
, "no") == 0)
13328 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13331 case OPTION_MLFENCE_AFTER_LOAD
:
13332 if (strcasecmp (arg
, "yes") == 0)
13333 lfence_after_load
= 1;
13334 else if (strcasecmp (arg
, "no") == 0)
13335 lfence_after_load
= 0;
13337 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13340 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13341 if (strcasecmp (arg
, "all") == 0)
13343 lfence_before_indirect_branch
= lfence_branch_all
;
13344 if (lfence_before_ret
== lfence_before_ret_none
)
13345 lfence_before_ret
= lfence_before_ret_shl
;
13347 else if (strcasecmp (arg
, "memory") == 0)
13348 lfence_before_indirect_branch
= lfence_branch_memory
;
13349 else if (strcasecmp (arg
, "register") == 0)
13350 lfence_before_indirect_branch
= lfence_branch_register
;
13351 else if (strcasecmp (arg
, "none") == 0)
13352 lfence_before_indirect_branch
= lfence_branch_none
;
13354 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13358 case OPTION_MLFENCE_BEFORE_RET
:
13359 if (strcasecmp (arg
, "or") == 0)
13360 lfence_before_ret
= lfence_before_ret_or
;
13361 else if (strcasecmp (arg
, "not") == 0)
13362 lfence_before_ret
= lfence_before_ret_not
;
13363 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13364 lfence_before_ret
= lfence_before_ret_shl
;
13365 else if (strcasecmp (arg
, "none") == 0)
13366 lfence_before_ret
= lfence_before_ret_none
;
13368 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13372 case OPTION_MRELAX_RELOCATIONS
:
13373 if (strcasecmp (arg
, "yes") == 0)
13374 generate_relax_relocations
= 1;
13375 else if (strcasecmp (arg
, "no") == 0)
13376 generate_relax_relocations
= 0;
13378 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13381 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13384 long int align
= strtoul (arg
, &end
, 0);
13389 align_branch_power
= 0;
13392 else if (align
>= 16)
13395 for (align_power
= 0;
13397 align
>>= 1, align_power
++)
13399 /* Limit alignment power to 31. */
13400 if (align
== 1 && align_power
< 32)
13402 align_branch_power
= align_power
;
13407 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13411 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13414 int align
= strtoul (arg
, &end
, 0);
13415 /* Some processors only support 5 prefixes. */
13416 if (*end
== '\0' && align
>= 0 && align
< 6)
13418 align_branch_prefix_size
= align
;
13421 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13426 case OPTION_MALIGN_BRANCH
:
13428 saved
= xstrdup (arg
);
13432 next
= strchr (type
, '+');
13435 if (strcasecmp (type
, "jcc") == 0)
13436 align_branch
|= align_branch_jcc_bit
;
13437 else if (strcasecmp (type
, "fused") == 0)
13438 align_branch
|= align_branch_fused_bit
;
13439 else if (strcasecmp (type
, "jmp") == 0)
13440 align_branch
|= align_branch_jmp_bit
;
13441 else if (strcasecmp (type
, "call") == 0)
13442 align_branch
|= align_branch_call_bit
;
13443 else if (strcasecmp (type
, "ret") == 0)
13444 align_branch
|= align_branch_ret_bit
;
13445 else if (strcasecmp (type
, "indirect") == 0)
13446 align_branch
|= align_branch_indirect_bit
;
13448 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13451 while (next
!= NULL
);
13455 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13456 align_branch_power
= 5;
13457 align_branch_prefix_size
= 5;
13458 align_branch
= (align_branch_jcc_bit
13459 | align_branch_fused_bit
13460 | align_branch_jmp_bit
);
13463 case OPTION_MAMD64
:
13467 case OPTION_MINTEL64
:
13475 /* Turn off -Os. */
13476 optimize_for_space
= 0;
13478 else if (*arg
== 's')
13480 optimize_for_space
= 1;
13481 /* Turn on all encoding optimizations. */
13482 optimize
= INT_MAX
;
13486 optimize
= atoi (arg
);
13487 /* Turn off -Os. */
13488 optimize_for_space
= 0;
13498 #define MESSAGE_TEMPLATE \
13502 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13503 int *left_p
, const char *name
, int len
)
13505 int size
= sizeof (MESSAGE_TEMPLATE
);
13506 int left
= *left_p
;
13508 /* Reserve 2 spaces for ", " or ",\0" */
13511 /* Check if there is any room. */
13519 p
= mempcpy (p
, name
, len
);
13523 /* Output the current message now and start a new one. */
13526 fprintf (stream
, "%s\n", message
);
13528 left
= size
- (start
- message
) - len
- 2;
13530 gas_assert (left
>= 0);
13532 p
= mempcpy (p
, name
, len
);
13540 show_arch (FILE *stream
, int ext
, int check
)
13542 static char message
[] = MESSAGE_TEMPLATE
;
13543 char *start
= message
+ 27;
13545 int size
= sizeof (MESSAGE_TEMPLATE
);
13552 left
= size
- (start
- message
);
13553 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13555 /* Should it be skipped? */
13556 if (cpu_arch
[j
].skip
)
13559 name
= cpu_arch
[j
].name
;
13560 len
= cpu_arch
[j
].len
;
13563 /* It is an extension. Skip if we aren't asked to show it. */
13574 /* It is an processor. Skip if we show only extension. */
13577 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13579 /* It is an impossible processor - skip. */
13583 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13586 /* Display disabled extensions. */
13588 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13590 name
= cpu_noarch
[j
].name
;
13591 len
= cpu_noarch
[j
].len
;
13592 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13597 fprintf (stream
, "%s\n", message
);
13601 md_show_usage (FILE *stream
)
13603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13604 fprintf (stream
, _("\
13605 -Qy, -Qn ignored\n\
13606 -V print assembler version number\n\
13609 fprintf (stream
, _("\
13610 -n Do not optimize code alignment\n\
13611 -q quieten some warnings\n"));
13612 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13613 fprintf (stream
, _("\
13616 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13617 || defined (TE_PE) || defined (TE_PEP))
13618 fprintf (stream
, _("\
13619 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13621 #ifdef SVR4_COMMENT_CHARS
13622 fprintf (stream
, _("\
13623 --divide do not treat `/' as a comment character\n"));
13625 fprintf (stream
, _("\
13626 --divide ignored\n"));
13628 fprintf (stream
, _("\
13629 -march=CPU[,+EXTENSION...]\n\
13630 generate code for CPU and EXTENSION, CPU is one of:\n"));
13631 show_arch (stream
, 0, 1);
13632 fprintf (stream
, _("\
13633 EXTENSION is combination of:\n"));
13634 show_arch (stream
, 1, 0);
13635 fprintf (stream
, _("\
13636 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13637 show_arch (stream
, 0, 0);
13638 fprintf (stream
, _("\
13639 -msse2avx encode SSE instructions with VEX prefix\n"));
13640 fprintf (stream
, _("\
13641 -msse-check=[none|error|warning] (default: warning)\n\
13642 check SSE instructions\n"));
13643 fprintf (stream
, _("\
13644 -moperand-check=[none|error|warning] (default: warning)\n\
13645 check operand combinations for validity\n"));
13646 fprintf (stream
, _("\
13647 -mavxscalar=[128|256] (default: 128)\n\
13648 encode scalar AVX instructions with specific vector\n\
13650 fprintf (stream
, _("\
13651 -mvexwig=[0|1] (default: 0)\n\
13652 encode VEX instructions with specific VEX.W value\n\
13653 for VEX.W bit ignored instructions\n"));
13654 fprintf (stream
, _("\
13655 -mevexlig=[128|256|512] (default: 128)\n\
13656 encode scalar EVEX instructions with specific vector\n\
13658 fprintf (stream
, _("\
13659 -mevexwig=[0|1] (default: 0)\n\
13660 encode EVEX instructions with specific EVEX.W value\n\
13661 for EVEX.W bit ignored instructions\n"));
13662 fprintf (stream
, _("\
13663 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13664 encode EVEX instructions with specific EVEX.RC value\n\
13665 for SAE-only ignored instructions\n"));
13666 fprintf (stream
, _("\
13667 -mmnemonic=[att|intel] "));
13668 if (SYSV386_COMPAT
)
13669 fprintf (stream
, _("(default: att)\n"));
13671 fprintf (stream
, _("(default: intel)\n"));
13672 fprintf (stream
, _("\
13673 use AT&T/Intel mnemonic\n"));
13674 fprintf (stream
, _("\
13675 -msyntax=[att|intel] (default: att)\n\
13676 use AT&T/Intel syntax\n"));
13677 fprintf (stream
, _("\
13678 -mindex-reg support pseudo index registers\n"));
13679 fprintf (stream
, _("\
13680 -mnaked-reg don't require `%%' prefix for registers\n"));
13681 fprintf (stream
, _("\
13682 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13683 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13684 fprintf (stream
, _("\
13685 -mshared disable branch optimization for shared code\n"));
13686 fprintf (stream
, _("\
13687 -mx86-used-note=[no|yes] "));
13688 if (DEFAULT_X86_USED_NOTE
)
13689 fprintf (stream
, _("(default: yes)\n"));
13691 fprintf (stream
, _("(default: no)\n"));
13692 fprintf (stream
, _("\
13693 generate x86 used ISA and feature properties\n"));
13695 #if defined (TE_PE) || defined (TE_PEP)
13696 fprintf (stream
, _("\
13697 -mbig-obj generate big object files\n"));
13699 fprintf (stream
, _("\
13700 -momit-lock-prefix=[no|yes] (default: no)\n\
13701 strip all lock prefixes\n"));
13702 fprintf (stream
, _("\
13703 -mfence-as-lock-add=[no|yes] (default: no)\n\
13704 encode lfence, mfence and sfence as\n\
13705 lock addl $0x0, (%%{re}sp)\n"));
13706 fprintf (stream
, _("\
13707 -mrelax-relocations=[no|yes] "));
13708 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13709 fprintf (stream
, _("(default: yes)\n"));
13711 fprintf (stream
, _("(default: no)\n"));
13712 fprintf (stream
, _("\
13713 generate relax relocations\n"));
13714 fprintf (stream
, _("\
13715 -malign-branch-boundary=NUM (default: 0)\n\
13716 align branches within NUM byte boundary\n"));
13717 fprintf (stream
, _("\
13718 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13719 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13721 specify types of branches to align\n"));
13722 fprintf (stream
, _("\
13723 -malign-branch-prefix-size=NUM (default: 5)\n\
13724 align branches with NUM prefixes per instruction\n"));
13725 fprintf (stream
, _("\
13726 -mbranches-within-32B-boundaries\n\
13727 align branches within 32 byte boundary\n"));
13728 fprintf (stream
, _("\
13729 -mlfence-after-load=[no|yes] (default: no)\n\
13730 generate lfence after load\n"));
13731 fprintf (stream
, _("\
13732 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13733 generate lfence before indirect near branch\n"));
13734 fprintf (stream
, _("\
13735 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13736 generate lfence before ret\n"));
13737 fprintf (stream
, _("\
13738 -mamd64 accept only AMD64 ISA [default]\n"));
13739 fprintf (stream
, _("\
13740 -mintel64 accept only Intel64 ISA\n"));
13743 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13744 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13745 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13747 /* Pick the target format to use. */
13750 i386_target_format (void)
13752 if (!strncmp (default_arch
, "x86_64", 6))
13754 update_code_flag (CODE_64BIT
, 1);
13755 if (default_arch
[6] == '\0')
13756 x86_elf_abi
= X86_64_ABI
;
13758 x86_elf_abi
= X86_64_X32_ABI
;
13760 else if (!strcmp (default_arch
, "i386"))
13761 update_code_flag (CODE_32BIT
, 1);
13762 else if (!strcmp (default_arch
, "iamcu"))
13764 update_code_flag (CODE_32BIT
, 1);
13765 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13767 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13768 cpu_arch_name
= "iamcu";
13769 cpu_sub_arch_name
= NULL
;
13770 cpu_arch_flags
= iamcu_flags
;
13771 cpu_arch_isa
= PROCESSOR_IAMCU
;
13772 cpu_arch_isa_flags
= iamcu_flags
;
13773 if (!cpu_arch_tune_set
)
13775 cpu_arch_tune
= cpu_arch_isa
;
13776 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13779 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13780 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13784 as_fatal (_("unknown architecture"));
13786 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13787 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13788 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13789 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13791 switch (OUTPUT_FLAVOR
)
13793 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13794 case bfd_target_aout_flavour
:
13795 return AOUT_TARGET_FORMAT
;
13797 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13798 # if defined (TE_PE) || defined (TE_PEP)
13799 case bfd_target_coff_flavour
:
13800 if (flag_code
== CODE_64BIT
)
13801 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13803 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13804 # elif defined (TE_GO32)
13805 case bfd_target_coff_flavour
:
13806 return "coff-go32";
13808 case bfd_target_coff_flavour
:
13809 return "coff-i386";
13812 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13813 case bfd_target_elf_flavour
:
13815 const char *format
;
13817 switch (x86_elf_abi
)
13820 format
= ELF_TARGET_FORMAT
;
13822 tls_get_addr
= "___tls_get_addr";
13826 use_rela_relocations
= 1;
13829 tls_get_addr
= "__tls_get_addr";
13831 format
= ELF_TARGET_FORMAT64
;
13833 case X86_64_X32_ABI
:
13834 use_rela_relocations
= 1;
13837 tls_get_addr
= "__tls_get_addr";
13839 disallow_64bit_reloc
= 1;
13840 format
= ELF_TARGET_FORMAT32
;
13843 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13845 if (x86_elf_abi
!= X86_64_ABI
)
13846 as_fatal (_("Intel L1OM is 64bit only"));
13847 return ELF_TARGET_L1OM_FORMAT
;
13849 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13851 if (x86_elf_abi
!= X86_64_ABI
)
13852 as_fatal (_("Intel K1OM is 64bit only"));
13853 return ELF_TARGET_K1OM_FORMAT
;
13855 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13857 if (x86_elf_abi
!= I386_ABI
)
13858 as_fatal (_("Intel MCU is 32bit only"));
13859 return ELF_TARGET_IAMCU_FORMAT
;
13865 #if defined (OBJ_MACH_O)
13866 case bfd_target_mach_o_flavour
:
13867 if (flag_code
== CODE_64BIT
)
13869 use_rela_relocations
= 1;
13871 return "mach-o-x86-64";
13874 return "mach-o-i386";
13882 #endif /* OBJ_MAYBE_ more than one */
13885 md_undefined_symbol (char *name
)
13887 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13888 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13889 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13890 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13894 if (symbol_find (name
))
13895 as_bad (_("GOT already in symbol table"));
13896 GOT_symbol
= symbol_new (name
, undefined_section
,
13897 &zero_address_frag
, 0);
13904 /* Round up a section size to the appropriate boundary. */
13907 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13909 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13910 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13912 /* For a.out, force the section size to be aligned. If we don't do
13913 this, BFD will align it for us, but it will not write out the
13914 final bytes of the section. This may be a bug in BFD, but it is
13915 easier to fix it here since that is how the other a.out targets
13919 align
= bfd_section_alignment (segment
);
13920 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13927 /* On the i386, PC-relative offsets are relative to the start of the
13928 next instruction. That is, the address of the offset, plus its
13929 size, since the offset is always the last part of the insn. */
13932 md_pcrel_from (fixS
*fixP
)
13934 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13940 s_bss (int ignore ATTRIBUTE_UNUSED
)
13944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13946 obj_elf_section_change_hook ();
13948 temp
= get_absolute_expression ();
13949 subseg_set (bss_section
, (subsegT
) temp
);
13950 demand_empty_rest_of_line ();
13955 /* Remember constant directive. */
13958 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13960 if (last_insn
.kind
!= last_insn_directive
13961 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13963 last_insn
.seg
= now_seg
;
13964 last_insn
.kind
= last_insn_directive
;
13965 last_insn
.name
= "constant directive";
13966 last_insn
.file
= as_where (&last_insn
.line
);
13967 if (lfence_before_ret
!= lfence_before_ret_none
)
13969 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13970 as_warn (_("constant directive skips -mlfence-before-ret "
13971 "and -mlfence-before-indirect-branch"));
13973 as_warn (_("constant directive skips -mlfence-before-ret"));
13975 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13976 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13981 i386_validate_fix (fixS
*fixp
)
13983 if (fixp
->fx_subsy
)
13985 if (fixp
->fx_subsy
== GOT_symbol
)
13987 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13992 if (fixp
->fx_tcbit2
)
13993 fixp
->fx_r_type
= (fixp
->fx_tcbit
13994 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13995 : BFD_RELOC_X86_64_GOTPCRELX
);
13998 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14003 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14005 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14007 fixp
->fx_subsy
= 0;
14010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14013 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14014 to section. Since PLT32 relocation must be against symbols,
14015 turn such PLT32 relocation into PC32 relocation. */
14017 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14018 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14019 && symbol_section_p (fixp
->fx_addsy
))
14020 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14023 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14024 && fixp
->fx_tcbit2
)
14025 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14032 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14035 bfd_reloc_code_real_type code
;
14037 switch (fixp
->fx_r_type
)
14039 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14040 case BFD_RELOC_SIZE32
:
14041 case BFD_RELOC_SIZE64
:
14042 if (S_IS_DEFINED (fixp
->fx_addsy
)
14043 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14045 /* Resolve size relocation against local symbol to size of
14046 the symbol plus addend. */
14047 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14048 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14049 && !fits_in_unsigned_long (value
))
14050 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14051 _("symbol size computation overflow"));
14052 fixp
->fx_addsy
= NULL
;
14053 fixp
->fx_subsy
= NULL
;
14054 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14058 /* Fall through. */
14060 case BFD_RELOC_X86_64_PLT32
:
14061 case BFD_RELOC_X86_64_GOT32
:
14062 case BFD_RELOC_X86_64_GOTPCREL
:
14063 case BFD_RELOC_X86_64_GOTPCRELX
:
14064 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14065 case BFD_RELOC_386_PLT32
:
14066 case BFD_RELOC_386_GOT32
:
14067 case BFD_RELOC_386_GOT32X
:
14068 case BFD_RELOC_386_GOTOFF
:
14069 case BFD_RELOC_386_GOTPC
:
14070 case BFD_RELOC_386_TLS_GD
:
14071 case BFD_RELOC_386_TLS_LDM
:
14072 case BFD_RELOC_386_TLS_LDO_32
:
14073 case BFD_RELOC_386_TLS_IE_32
:
14074 case BFD_RELOC_386_TLS_IE
:
14075 case BFD_RELOC_386_TLS_GOTIE
:
14076 case BFD_RELOC_386_TLS_LE_32
:
14077 case BFD_RELOC_386_TLS_LE
:
14078 case BFD_RELOC_386_TLS_GOTDESC
:
14079 case BFD_RELOC_386_TLS_DESC_CALL
:
14080 case BFD_RELOC_X86_64_TLSGD
:
14081 case BFD_RELOC_X86_64_TLSLD
:
14082 case BFD_RELOC_X86_64_DTPOFF32
:
14083 case BFD_RELOC_X86_64_DTPOFF64
:
14084 case BFD_RELOC_X86_64_GOTTPOFF
:
14085 case BFD_RELOC_X86_64_TPOFF32
:
14086 case BFD_RELOC_X86_64_TPOFF64
:
14087 case BFD_RELOC_X86_64_GOTOFF64
:
14088 case BFD_RELOC_X86_64_GOTPC32
:
14089 case BFD_RELOC_X86_64_GOT64
:
14090 case BFD_RELOC_X86_64_GOTPCREL64
:
14091 case BFD_RELOC_X86_64_GOTPC64
:
14092 case BFD_RELOC_X86_64_GOTPLT64
:
14093 case BFD_RELOC_X86_64_PLTOFF64
:
14094 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14095 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14096 case BFD_RELOC_RVA
:
14097 case BFD_RELOC_VTABLE_ENTRY
:
14098 case BFD_RELOC_VTABLE_INHERIT
:
14100 case BFD_RELOC_32_SECREL
:
14102 code
= fixp
->fx_r_type
;
14104 case BFD_RELOC_X86_64_32S
:
14105 if (!fixp
->fx_pcrel
)
14107 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14108 code
= fixp
->fx_r_type
;
14111 /* Fall through. */
14113 if (fixp
->fx_pcrel
)
14115 switch (fixp
->fx_size
)
14118 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14119 _("can not do %d byte pc-relative relocation"),
14121 code
= BFD_RELOC_32_PCREL
;
14123 case 1: code
= BFD_RELOC_8_PCREL
; break;
14124 case 2: code
= BFD_RELOC_16_PCREL
; break;
14125 case 4: code
= BFD_RELOC_32_PCREL
; break;
14127 case 8: code
= BFD_RELOC_64_PCREL
; break;
14133 switch (fixp
->fx_size
)
14136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14137 _("can not do %d byte relocation"),
14139 code
= BFD_RELOC_32
;
14141 case 1: code
= BFD_RELOC_8
; break;
14142 case 2: code
= BFD_RELOC_16
; break;
14143 case 4: code
= BFD_RELOC_32
; break;
14145 case 8: code
= BFD_RELOC_64
; break;
14152 if ((code
== BFD_RELOC_32
14153 || code
== BFD_RELOC_32_PCREL
14154 || code
== BFD_RELOC_X86_64_32S
)
14156 && fixp
->fx_addsy
== GOT_symbol
)
14159 code
= BFD_RELOC_386_GOTPC
;
14161 code
= BFD_RELOC_X86_64_GOTPC32
;
14163 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14165 && fixp
->fx_addsy
== GOT_symbol
)
14167 code
= BFD_RELOC_X86_64_GOTPC64
;
14170 rel
= XNEW (arelent
);
14171 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14172 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14174 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14176 if (!use_rela_relocations
)
14178 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14179 vtable entry to be used in the relocation's section offset. */
14180 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14181 rel
->address
= fixp
->fx_offset
;
14182 #if defined (OBJ_COFF) && defined (TE_PE)
14183 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14184 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14189 /* Use the rela in 64bit mode. */
14192 if (disallow_64bit_reloc
)
14195 case BFD_RELOC_X86_64_DTPOFF64
:
14196 case BFD_RELOC_X86_64_TPOFF64
:
14197 case BFD_RELOC_64_PCREL
:
14198 case BFD_RELOC_X86_64_GOTOFF64
:
14199 case BFD_RELOC_X86_64_GOT64
:
14200 case BFD_RELOC_X86_64_GOTPCREL64
:
14201 case BFD_RELOC_X86_64_GOTPC64
:
14202 case BFD_RELOC_X86_64_GOTPLT64
:
14203 case BFD_RELOC_X86_64_PLTOFF64
:
14204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14205 _("cannot represent relocation type %s in x32 mode"),
14206 bfd_get_reloc_code_name (code
));
14212 if (!fixp
->fx_pcrel
)
14213 rel
->addend
= fixp
->fx_offset
;
14217 case BFD_RELOC_X86_64_PLT32
:
14218 case BFD_RELOC_X86_64_GOT32
:
14219 case BFD_RELOC_X86_64_GOTPCREL
:
14220 case BFD_RELOC_X86_64_GOTPCRELX
:
14221 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14222 case BFD_RELOC_X86_64_TLSGD
:
14223 case BFD_RELOC_X86_64_TLSLD
:
14224 case BFD_RELOC_X86_64_GOTTPOFF
:
14225 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14226 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14227 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14230 rel
->addend
= (section
->vma
14232 + fixp
->fx_addnumber
14233 + md_pcrel_from (fixp
));
14238 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14239 if (rel
->howto
== NULL
)
14241 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14242 _("cannot represent relocation type %s"),
14243 bfd_get_reloc_code_name (code
));
14244 /* Set howto to a garbage value so that we can keep going. */
14245 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14246 gas_assert (rel
->howto
!= NULL
);
14252 #include "tc-i386-intel.c"
14255 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14257 int saved_naked_reg
;
14258 char saved_register_dot
;
14260 saved_naked_reg
= allow_naked_reg
;
14261 allow_naked_reg
= 1;
14262 saved_register_dot
= register_chars
['.'];
14263 register_chars
['.'] = '.';
14264 allow_pseudo_reg
= 1;
14265 expression_and_evaluate (exp
);
14266 allow_pseudo_reg
= 0;
14267 register_chars
['.'] = saved_register_dot
;
14268 allow_naked_reg
= saved_naked_reg
;
14270 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14272 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14274 exp
->X_op
= O_constant
;
14275 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14276 .dw2_regnum
[flag_code
>> 1];
14279 exp
->X_op
= O_illegal
;
14284 tc_x86_frame_initial_instructions (void)
14286 static unsigned int sp_regno
[2];
14288 if (!sp_regno
[flag_code
>> 1])
14290 char *saved_input
= input_line_pointer
;
14291 char sp
[][4] = {"esp", "rsp"};
14294 input_line_pointer
= sp
[flag_code
>> 1];
14295 tc_x86_parse_to_dw2regnum (&exp
);
14296 gas_assert (exp
.X_op
== O_constant
);
14297 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14298 input_line_pointer
= saved_input
;
14301 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14302 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14306 x86_dwarf2_addr_size (void)
14308 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14309 if (x86_elf_abi
== X86_64_X32_ABI
)
14312 return bfd_arch_bits_per_address (stdoutput
) / 8;
14316 i386_elf_section_type (const char *str
, size_t len
)
14318 if (flag_code
== CODE_64BIT
14319 && len
== sizeof ("unwind") - 1
14320 && strncmp (str
, "unwind", 6) == 0)
14321 return SHT_X86_64_UNWIND
;
14328 i386_solaris_fix_up_eh_frame (segT sec
)
14330 if (flag_code
== CODE_64BIT
)
14331 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14337 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14341 exp
.X_op
= O_secrel
;
14342 exp
.X_add_symbol
= symbol
;
14343 exp
.X_add_number
= 0;
14344 emit_expr (&exp
, size
);
14348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14349 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14352 x86_64_section_letter (int letter
, const char **ptr_msg
)
14354 if (flag_code
== CODE_64BIT
)
14357 return SHF_X86_64_LARGE
;
14359 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14362 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14367 x86_64_section_word (char *str
, size_t len
)
14369 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14370 return SHF_X86_64_LARGE
;
14376 handle_large_common (int small ATTRIBUTE_UNUSED
)
14378 if (flag_code
!= CODE_64BIT
)
14380 s_comm_internal (0, elf_common_parse
);
14381 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14385 static segT lbss_section
;
14386 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14387 asection
*saved_bss_section
= bss_section
;
14389 if (lbss_section
== NULL
)
14391 flagword applicable
;
14392 segT seg
= now_seg
;
14393 subsegT subseg
= now_subseg
;
14395 /* The .lbss section is for local .largecomm symbols. */
14396 lbss_section
= subseg_new (".lbss", 0);
14397 applicable
= bfd_applicable_section_flags (stdoutput
);
14398 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14399 seg_info (lbss_section
)->bss
= 1;
14401 subseg_set (seg
, subseg
);
14404 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14405 bss_section
= lbss_section
;
14407 s_comm_internal (0, elf_common_parse
);
14409 elf_com_section_ptr
= saved_com_section_ptr
;
14410 bss_section
= saved_bss_section
;
14413 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */