1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
42 #define DEFAULT_ARCH "i386"
47 #define INLINE __inline__
53 /* Prefixes will be emitted in the order defined below.
54 WAIT_PREFIX must be the first prefix since FWAIT is really is an
55 instruction, and so must come before any prefixes.
56 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
57 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
63 #define HLE_PREFIX REP_PREFIX
64 #define BND_PREFIX REP_PREFIX
66 #define REX_PREFIX 6 /* must come last. */
67 #define MAX_PREFIXES 7 /* max prefixes per opcode */
69 /* we define the syntax here (modulo base,index,scale syntax) */
70 #define REGISTER_PREFIX '%'
71 #define IMMEDIATE_PREFIX '$'
72 #define ABSOLUTE_PREFIX '*'
74 /* these are the instruction mnemonic suffixes in AT&T syntax or
75 memory operand size in Intel syntax. */
76 #define WORD_MNEM_SUFFIX 'w'
77 #define BYTE_MNEM_SUFFIX 'b'
78 #define SHORT_MNEM_SUFFIX 's'
79 #define LONG_MNEM_SUFFIX 'l'
80 #define QWORD_MNEM_SUFFIX 'q'
81 /* Intel Syntax. Use a non-ascii letter since since it never appears
83 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
85 #define END_OF_INSN '\0'
87 /* This matches the C -> StaticRounding alias in the opcode table. */
88 #define commutative staticrounding
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (unsigned int, unsigned int);
171 static enum flag_code
i386_addressing_mode (void);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (char);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const reg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 /* GNU_PROPERTY_X86_ISA_1_USED. */
194 static unsigned int x86_isa_1_used
;
195 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
196 static unsigned int x86_feature_2_used
;
197 /* Generate x86 used ISA and feature properties. */
198 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
201 static const char *default_arch
= DEFAULT_ARCH
;
203 /* parse_register() returns this when a register alias cannot be used. */
204 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
205 { Dw2Inval
, Dw2Inval
} };
207 static const reg_entry
*reg_eax
;
208 static const reg_entry
*reg_ds
;
209 static const reg_entry
*reg_es
;
210 static const reg_entry
*reg_ss
;
211 static const reg_entry
*reg_st0
;
212 static const reg_entry
*reg_k0
;
217 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
218 unsigned char bytes
[4];
220 /* Destination or source register specifier. */
221 const reg_entry
*register_specifier
;
224 /* 'md_assemble ()' gathers together information and puts it into a
231 const reg_entry
*regs
;
236 operand_size_mismatch
,
237 operand_type_mismatch
,
238 register_type_mismatch
,
239 number_of_operands_mismatch
,
240 invalid_instruction_suffix
,
242 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 rc_sae_operand_not_last_imm
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* Copied first memory operand string, for re-checking. */
309 /* PREFIX holds all the given prefix opcodes (usually null).
310 PREFIXES is the number of prefix opcodes. */
311 unsigned int prefixes
;
312 unsigned char prefix
[MAX_PREFIXES
];
314 /* Register is in low 3 bits of opcode. */
317 /* The operand to a branch insn indicates an absolute branch. */
320 /* Extended states. */
328 xstate_ymm
= 1 << 2 | xstate_xmm
,
330 xstate_zmm
= 1 << 3 | xstate_ymm
,
333 /* Use MASK state. */
337 /* Has GOTPC or TLS relocation. */
338 bool has_gotpc_tls_reloc
;
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes.
350 The struct describes masking, applied to OPERAND in the instruction.
351 REG is a pointer to the corresponding mask register. ZEROING tells
352 whether merging or zeroing mask is used. */
353 struct Mask_Operation
355 const reg_entry
*reg
;
356 unsigned int zeroing
;
357 /* The operand where this operation is associated. */
358 unsigned int operand
;
361 /* Rounding control and SAE attributes. */
374 unsigned int operand
;
377 /* Broadcasting attributes.
379 The struct describes broadcasting, applied to OPERAND. TYPE is
380 expresses the broadcast factor. */
381 struct Broadcast_Operation
383 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
386 /* Index of broadcasted operand. */
387 unsigned int operand
;
389 /* Number of bytes to broadcast. */
393 /* Compressed disp8*N attribute. */
394 unsigned int memshift
;
396 /* Prefer load or store in encoding. */
399 dir_encoding_default
= 0,
405 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
408 disp_encoding_default
= 0,
414 /* Prefer the REX byte in encoding. */
417 /* Disable instruction size optimization. */
420 /* How to encode vector instructions. */
423 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
478 && !defined (TE_GNU) \
479 && !defined (TE_LINUX) \
480 && !defined (TE_FreeBSD) \
481 && !defined (TE_DragonFly) \
482 && !defined (TE_NetBSD))
483 /* This array holds the chars that always start a comment. If the
484 pre-processor is disabled, these aren't very useful. The option
485 --divide will remove '/' from this list. */
486 const char *i386_comment_chars
= "#/";
487 #define SVR4_COMMENT_CHARS 1
488 #define PREFIX_SEPARATOR '\\'
491 const char *i386_comment_chars
= "#";
492 #define PREFIX_SEPARATOR '/'
495 /* This array holds the chars that only start a comment at the beginning of
496 a line. If the line seems to have the form '# 123 filename'
497 .line and .file directives will appear in the pre-processed output.
498 Note that input_file.c hand checks for '#' at the beginning of the
499 first line of the input file. This is because the compiler outputs
500 #NO_APP at the beginning of its output.
501 Also note that comments started like this one will always work if
502 '/' isn't otherwise defined. */
503 const char line_comment_chars
[] = "#/";
505 const char line_separator_chars
[] = ";";
507 /* Chars that can be used to separate mant from exp in floating point
509 const char EXP_CHARS
[] = "eE";
511 /* Chars that mean this number is a floating point constant
514 const char FLT_CHARS
[] = "fFdDxX";
516 /* Tables for lexical analysis. */
517 static char mnemonic_chars
[256];
518 static char register_chars
[256];
519 static char operand_chars
[256];
520 static char identifier_chars
[256];
522 /* Lexical macros. */
523 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
524 #define is_operand_char(x) (operand_chars[(unsigned char) x])
525 #define is_register_char(x) (register_chars[(unsigned char) x])
526 #define is_space_char(x) ((x) == ' ')
527 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* 1 if lfence should be inserted after every load. */
633 static int lfence_after_load
= 0;
635 /* Non-zero if lfence should be inserted before indirect branch. */
636 static enum lfence_before_indirect_branch_kind
638 lfence_branch_none
= 0,
639 lfence_branch_register
,
640 lfence_branch_memory
,
643 lfence_before_indirect_branch
;
645 /* Non-zero if lfence should be inserted before ret. */
646 static enum lfence_before_ret_kind
648 lfence_before_ret_none
= 0,
649 lfence_before_ret_not
,
650 lfence_before_ret_or
,
651 lfence_before_ret_shl
655 /* Types of previous instruction is .byte or prefix. */
670 /* 1 if the assembler should generate relax relocations. */
672 static int generate_relax_relocations
673 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
675 static enum check_kind
681 sse_check
, operand_check
= check_warning
;
683 /* Non-zero if branches should be aligned within power of 2 boundary. */
684 static int align_branch_power
= 0;
686 /* Types of branches to align. */
687 enum align_branch_kind
689 align_branch_none
= 0,
690 align_branch_jcc
= 1,
691 align_branch_fused
= 2,
692 align_branch_jmp
= 3,
693 align_branch_call
= 4,
694 align_branch_indirect
= 5,
698 /* Type bits of branches to align. */
699 enum align_branch_bit
701 align_branch_jcc_bit
= 1 << align_branch_jcc
,
702 align_branch_fused_bit
= 1 << align_branch_fused
,
703 align_branch_jmp_bit
= 1 << align_branch_jmp
,
704 align_branch_call_bit
= 1 << align_branch_call
,
705 align_branch_indirect_bit
= 1 << align_branch_indirect
,
706 align_branch_ret_bit
= 1 << align_branch_ret
709 static unsigned int align_branch
= (align_branch_jcc_bit
710 | align_branch_fused_bit
711 | align_branch_jmp_bit
);
713 /* Types of condition jump used by macro-fusion. */
716 mf_jcc_jo
= 0, /* base opcode 0x70 */
717 mf_jcc_jc
, /* base opcode 0x72 */
718 mf_jcc_je
, /* base opcode 0x74 */
719 mf_jcc_jna
, /* base opcode 0x76 */
720 mf_jcc_js
, /* base opcode 0x78 */
721 mf_jcc_jp
, /* base opcode 0x7a */
722 mf_jcc_jl
, /* base opcode 0x7c */
723 mf_jcc_jle
, /* base opcode 0x7e */
726 /* Types of compare flag-modifying insntructions used by macro-fusion. */
729 mf_cmp_test_and
, /* test/cmp */
730 mf_cmp_alu_cmp
, /* add/sub/cmp */
731 mf_cmp_incdec
/* inc/dec */
734 /* The maximum padding size for fused jcc. CMP like instruction can
735 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
737 #define MAX_FUSED_JCC_PADDING_SIZE 20
739 /* The maximum number of prefixes added for an instruction. */
740 static unsigned int align_branch_prefix_size
= 5;
743 1. Clear the REX_W bit with register operand if possible.
744 2. Above plus use 128bit vector instruction to clear the full vector
747 static int optimize
= 0;
750 1. Clear the REX_W bit with register operand if possible.
751 2. Above plus use 128bit vector instruction to clear the full vector
753 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
756 static int optimize_for_space
= 0;
758 /* Register prefix used for error message. */
759 static const char *register_prefix
= "%";
761 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
762 leave, push, and pop instructions so that gcc has the same stack
763 frame as in 32 bit mode. */
764 static char stackop_size
= '\0';
766 /* Non-zero to optimize code alignment. */
767 int optimize_align_code
= 1;
769 /* Non-zero to quieten some warnings. */
770 static int quiet_warnings
= 0;
773 static const char *cpu_arch_name
= NULL
;
774 static char *cpu_sub_arch_name
= NULL
;
776 /* CPU feature flags. */
777 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
779 /* If we have selected a cpu we are generating instructions for. */
780 static int cpu_arch_tune_set
= 0;
782 /* Cpu we are generating instructions for. */
783 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
785 /* CPU feature flags of cpu we are generating instructions for. */
786 static i386_cpu_flags cpu_arch_tune_flags
;
788 /* CPU instruction set architecture used. */
789 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
791 /* CPU feature flags of instruction set architecture used. */
792 i386_cpu_flags cpu_arch_isa_flags
;
794 /* If set, conditional jumps are not automatically promoted to handle
795 larger than a byte offset. */
796 static unsigned int no_cond_jump_promotion
= 0;
798 /* Encode SSE instructions with VEX prefix. */
799 static unsigned int sse2avx
;
801 /* Encode scalar AVX instructions with specific vector length. */
808 /* Encode VEX WIG instructions with specific vex.w. */
815 /* Encode scalar EVEX LIG instructions with specific vector length. */
823 /* Encode EVEX WIG instructions with specific evex.w. */
830 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
831 static enum rc_type evexrcig
= rne
;
833 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
834 static symbolS
*GOT_symbol
;
836 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
837 unsigned int x86_dwarf2_return_column
;
839 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
840 int x86_cie_data_alignment
;
842 /* Interface to relax_segment.
843 There are 3 major relax states for 386 jump insns because the
844 different types of jumps add different sizes to frags when we're
845 figuring out what sort of jump to choose to reach a given label.
847 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
848 branches which are handled by md_estimate_size_before_relax() and
849 i386_generic_table_relax_frag(). */
852 #define UNCOND_JUMP 0
854 #define COND_JUMP86 2
855 #define BRANCH_PADDING 3
856 #define BRANCH_PREFIX 4
857 #define FUSED_JCC_PADDING 5
862 #define SMALL16 (SMALL | CODE16)
864 #define BIG16 (BIG | CODE16)
868 #define INLINE __inline__
874 #define ENCODE_RELAX_STATE(type, size) \
875 ((relax_substateT) (((type) << 2) | (size)))
876 #define TYPE_FROM_RELAX_STATE(s) \
878 #define DISP_SIZE_FROM_RELAX_STATE(s) \
879 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
881 /* This table is used by relax_frag to promote short jumps to long
882 ones where necessary. SMALL (short) jumps may be promoted to BIG
883 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
884 don't allow a short jump in a 32 bit code segment to be promoted to
885 a 16 bit offset jump because it's slower (requires data size
886 prefix), and doesn't work, unless the destination is in the bottom
887 64k of the code segment (The top 16 bits of eip are zeroed). */
889 const relax_typeS md_relax_table
[] =
892 1) most positive reach of this state,
893 2) most negative reach of this state,
894 3) how many bytes this mode will have in the variable part of the frag
895 4) which index into the table to try if we can't fit into this one. */
897 /* UNCOND_JUMP states. */
898 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
899 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
900 /* dword jmp adds 4 bytes to frag:
901 0 extra opcode bytes, 4 displacement bytes. */
903 /* word jmp adds 2 byte2 to frag:
904 0 extra opcode bytes, 2 displacement bytes. */
907 /* COND_JUMP states. */
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
910 /* dword conditionals adds 5 bytes to frag:
911 1 extra opcode byte, 4 displacement bytes. */
913 /* word conditionals add 3 bytes to frag:
914 1 extra opcode byte, 2 displacement bytes. */
917 /* COND_JUMP86 states. */
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
920 /* dword conditionals adds 5 bytes to frag:
921 1 extra opcode byte, 4 displacement bytes. */
923 /* word conditionals add 4 bytes to frag:
924 1 displacement byte and a 3 byte long branch insn. */
928 static const arch_entry cpu_arch
[] =
930 /* Do not replace the first two entries - i386_target_format()
931 relies on them being there in this order. */
932 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
933 CPU_GENERIC32_FLAGS
, 0 },
934 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
935 CPU_GENERIC64_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
944 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
946 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
948 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
950 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
952 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
953 CPU_PENTIUMPRO_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
956 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
958 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
960 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
962 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
963 CPU_NOCONA_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
966 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
968 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
969 CPU_CORE2_FLAGS
, 1 },
970 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
971 CPU_CORE2_FLAGS
, 0 },
972 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
973 CPU_COREI7_FLAGS
, 0 },
974 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
976 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
978 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
979 CPU_IAMCU_FLAGS
, 0 },
980 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
982 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
984 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
985 CPU_ATHLON_FLAGS
, 0 },
986 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
988 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
990 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
993 CPU_AMDFAM10_FLAGS
, 0 },
994 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
995 CPU_BDVER1_FLAGS
, 0 },
996 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
997 CPU_BDVER2_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
999 CPU_BDVER3_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1001 CPU_BDVER4_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1003 CPU_ZNVER1_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1005 CPU_ZNVER2_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER3_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1009 CPU_BTVER1_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1011 CPU_BTVER2_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1013 CPU_8087_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1021 CPU_CMOV_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1023 CPU_FXSR_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1026 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1029 CPU_SSE2_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE3_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE4A_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1035 CPU_SSSE3_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1037 CPU_SSE4_1_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_2_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX2_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512F_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512CD_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512ER_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512PF_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512DQ_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512BW_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512VL_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1062 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1063 CPU_VMFUNC_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1067 CPU_XSAVE_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVEOPT_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEC_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVES_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1076 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1077 CPU_PCLMUL_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 1 },
1080 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1081 CPU_FSGSBASE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1083 CPU_RDRND_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1085 CPU_F16C_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1087 CPU_BMI2_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1091 CPU_FMA4_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1094 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1097 CPU_MOVBE_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1099 CPU_CX16_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1102 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1103 CPU_LZCNT_FLAGS
, 0 },
1104 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_POPCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1108 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1111 CPU_INVPCID_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1113 CPU_CLFLUSH_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1116 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1117 CPU_SYSCALL_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1119 CPU_RDTSCP_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1121 CPU_3DNOW_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOWA_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1125 CPU_PADLOCK_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1127 CPU_SVME_FLAGS
, 1 },
1128 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1131 CPU_SSE4A_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1134 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1141 CPU_RDSEED_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1143 CPU_PRFCHW_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1145 CPU_SMAP_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1148 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1151 CPU_CLFLUSHOPT_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1153 CPU_PREFETCHWT1_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1156 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1157 CPU_CLWB_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1159 CPU_AVX512IFMA_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512VBMI_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VBMI2_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VNNI_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_BITALG_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX_VNNI_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1177 CPU_CLZERO_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1179 CPU_MWAITX_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1181 CPU_OSPKE_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1183 CPU_RDPID_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1185 CPU_PTWRITE_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1188 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1189 CPU_SHSTK_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1191 CPU_GFNI_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1193 CPU_VAES_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1195 CPU_VPCLMULQDQ_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1197 CPU_WBNOINVD_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1199 CPU_PCONFIG_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1201 CPU_WAITPKG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1203 CPU_CLDEMOTE_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1205 CPU_AMX_INT8_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1207 CPU_AMX_BF16_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1209 CPU_AMX_TILE_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1211 CPU_MOVDIRI_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1213 CPU_MOVDIR64B_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1215 CPU_AVX512_BF16_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1217 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1220 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1221 CPU_ENQCMD_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1223 CPU_SERIALIZE_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1225 CPU_RDPRU_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1227 CPU_MCOMMIT_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1229 CPU_SEV_ES_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1231 CPU_TSXLDTRK_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1234 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1235 CPU_WIDEKL_FLAGS
, 0 },
1236 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1237 CPU_UINTR_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1239 CPU_HRESET_FLAGS
, 0 },
1242 static const noarch_entry cpu_noarch
[] =
1244 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1245 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1246 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1247 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1248 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1249 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1250 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1251 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1255 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1256 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1257 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1258 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1277 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1278 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1279 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1280 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1282 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1283 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1286 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1287 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1288 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1289 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1290 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1291 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1292 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1293 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1294 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1298 /* Like s_lcomm_internal in gas/read.c but the alignment string
1299 is allowed to be optional. */
1302 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1309 && *input_line_pointer
== ',')
1311 align
= parse_align (needs_align
- 1);
1313 if (align
== (addressT
) -1)
1328 bss_alloc (symbolP
, size
, align
);
1333 pe_lcomm (int needs_align
)
1335 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1339 const pseudo_typeS md_pseudo_table
[] =
1341 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1342 {"align", s_align_bytes
, 0},
1344 {"align", s_align_ptwo
, 0},
1346 {"arch", set_cpu_arch
, 0},
1350 {"lcomm", pe_lcomm
, 1},
1352 {"ffloat", float_cons
, 'f'},
1353 {"dfloat", float_cons
, 'd'},
1354 {"tfloat", float_cons
, 'x'},
1356 {"slong", signed_cons
, 4},
1357 {"noopt", s_ignore
, 0},
1358 {"optim", s_ignore
, 0},
1359 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1360 {"code16", set_code_flag
, CODE_16BIT
},
1361 {"code32", set_code_flag
, CODE_32BIT
},
1363 {"code64", set_code_flag
, CODE_64BIT
},
1365 {"intel_syntax", set_intel_syntax
, 1},
1366 {"att_syntax", set_intel_syntax
, 0},
1367 {"intel_mnemonic", set_intel_mnemonic
, 1},
1368 {"att_mnemonic", set_intel_mnemonic
, 0},
1369 {"allow_index_reg", set_allow_index_reg
, 1},
1370 {"disallow_index_reg", set_allow_index_reg
, 0},
1371 {"sse_check", set_check
, 0},
1372 {"operand_check", set_check
, 1},
1373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1374 {"largecomm", handle_large_common
, 0},
1376 {"file", dwarf2_directive_file
, 0},
1377 {"loc", dwarf2_directive_loc
, 0},
1378 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1381 {"secrel32", pe_directive_secrel
, 0},
1386 /* For interface with expression (). */
1387 extern char *input_line_pointer
;
1389 /* Hash table for instruction mnemonic lookup. */
1390 static htab_t op_hash
;
1392 /* Hash table for register lookup. */
1393 static htab_t reg_hash
;
1395 /* Various efficient no-op patterns for aligning code labels.
1396 Note: Don't try to assemble the instructions in the comments.
1397 0L and 0w are not legal. */
1398 static const unsigned char f32_1
[] =
1400 static const unsigned char f32_2
[] =
1401 {0x66,0x90}; /* xchg %ax,%ax */
1402 static const unsigned char f32_3
[] =
1403 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1404 static const unsigned char f32_4
[] =
1405 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1406 static const unsigned char f32_6
[] =
1407 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1408 static const unsigned char f32_7
[] =
1409 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1410 static const unsigned char f16_3
[] =
1411 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1412 static const unsigned char f16_4
[] =
1413 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1414 static const unsigned char jump_disp8
[] =
1415 {0xeb}; /* jmp disp8 */
1416 static const unsigned char jump32_disp32
[] =
1417 {0xe9}; /* jmp disp32 */
1418 static const unsigned char jump16_disp32
[] =
1419 {0x66,0xe9}; /* jmp disp32 */
1420 /* 32-bit NOPs patterns. */
1421 static const unsigned char *const f32_patt
[] = {
1422 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1424 /* 16-bit NOPs patterns. */
1425 static const unsigned char *const f16_patt
[] = {
1426 f32_1
, f32_2
, f16_3
, f16_4
1428 /* nopl (%[re]ax) */
1429 static const unsigned char alt_3
[] =
1431 /* nopl 0(%[re]ax) */
1432 static const unsigned char alt_4
[] =
1433 {0x0f,0x1f,0x40,0x00};
1434 /* nopl 0(%[re]ax,%[re]ax,1) */
1435 static const unsigned char alt_5
[] =
1436 {0x0f,0x1f,0x44,0x00,0x00};
1437 /* nopw 0(%[re]ax,%[re]ax,1) */
1438 static const unsigned char alt_6
[] =
1439 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1440 /* nopl 0L(%[re]ax) */
1441 static const unsigned char alt_7
[] =
1442 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1443 /* nopl 0L(%[re]ax,%[re]ax,1) */
1444 static const unsigned char alt_8
[] =
1445 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1446 /* nopw 0L(%[re]ax,%[re]ax,1) */
1447 static const unsigned char alt_9
[] =
1448 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1449 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1450 static const unsigned char alt_10
[] =
1451 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1452 /* data16 nopw %cs:0L(%eax,%eax,1) */
1453 static const unsigned char alt_11
[] =
1454 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1455 /* 32-bit and 64-bit NOPs patterns. */
1456 static const unsigned char *const alt_patt
[] = {
1457 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1458 alt_9
, alt_10
, alt_11
1461 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1462 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1465 i386_output_nops (char *where
, const unsigned char *const *patt
,
1466 int count
, int max_single_nop_size
)
1469 /* Place the longer NOP first. */
1472 const unsigned char *nops
;
1474 if (max_single_nop_size
< 1)
1476 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1477 max_single_nop_size
);
1481 nops
= patt
[max_single_nop_size
- 1];
1483 /* Use the smaller one if the requsted one isn't available. */
1486 max_single_nop_size
--;
1487 nops
= patt
[max_single_nop_size
- 1];
1490 last
= count
% max_single_nop_size
;
1493 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1494 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1498 nops
= patt
[last
- 1];
1501 /* Use the smaller one plus one-byte NOP if the needed one
1504 nops
= patt
[last
- 1];
1505 memcpy (where
+ offset
, nops
, last
);
1506 where
[offset
+ last
] = *patt
[0];
1509 memcpy (where
+ offset
, nops
, last
);
1514 fits_in_imm7 (offsetT num
)
1516 return (num
& 0x7f) == num
;
1520 fits_in_imm31 (offsetT num
)
1522 return (num
& 0x7fffffff) == num
;
1525 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1526 single NOP instruction LIMIT. */
1529 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1531 const unsigned char *const *patt
= NULL
;
1532 int max_single_nop_size
;
1533 /* Maximum number of NOPs before switching to jump over NOPs. */
1534 int max_number_of_nops
;
1536 switch (fragP
->fr_type
)
1541 case rs_machine_dependent
:
1542 /* Allow NOP padding for jumps and calls. */
1543 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1544 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1551 /* We need to decide which NOP sequence to use for 32bit and
1552 64bit. When -mtune= is used:
1554 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1555 PROCESSOR_GENERIC32, f32_patt will be used.
1556 2. For the rest, alt_patt will be used.
1558 When -mtune= isn't used, alt_patt will be used if
1559 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1562 When -march= or .arch is used, we can't use anything beyond
1563 cpu_arch_isa_flags. */
1565 if (flag_code
== CODE_16BIT
)
1568 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1569 /* Limit number of NOPs to 2 in 16-bit mode. */
1570 max_number_of_nops
= 2;
1574 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1576 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1577 switch (cpu_arch_tune
)
1579 case PROCESSOR_UNKNOWN
:
1580 /* We use cpu_arch_isa_flags to check if we SHOULD
1581 optimize with nops. */
1582 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1587 case PROCESSOR_PENTIUM4
:
1588 case PROCESSOR_NOCONA
:
1589 case PROCESSOR_CORE
:
1590 case PROCESSOR_CORE2
:
1591 case PROCESSOR_COREI7
:
1592 case PROCESSOR_L1OM
:
1593 case PROCESSOR_K1OM
:
1594 case PROCESSOR_GENERIC64
:
1596 case PROCESSOR_ATHLON
:
1598 case PROCESSOR_AMDFAM10
:
1600 case PROCESSOR_ZNVER
:
1604 case PROCESSOR_I386
:
1605 case PROCESSOR_I486
:
1606 case PROCESSOR_PENTIUM
:
1607 case PROCESSOR_PENTIUMPRO
:
1608 case PROCESSOR_IAMCU
:
1609 case PROCESSOR_GENERIC32
:
1616 switch (fragP
->tc_frag_data
.tune
)
1618 case PROCESSOR_UNKNOWN
:
1619 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1620 PROCESSOR_UNKNOWN. */
1624 case PROCESSOR_I386
:
1625 case PROCESSOR_I486
:
1626 case PROCESSOR_PENTIUM
:
1627 case PROCESSOR_IAMCU
:
1629 case PROCESSOR_ATHLON
:
1631 case PROCESSOR_AMDFAM10
:
1633 case PROCESSOR_ZNVER
:
1635 case PROCESSOR_GENERIC32
:
1636 /* We use cpu_arch_isa_flags to check if we CAN optimize
1638 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1643 case PROCESSOR_PENTIUMPRO
:
1644 case PROCESSOR_PENTIUM4
:
1645 case PROCESSOR_NOCONA
:
1646 case PROCESSOR_CORE
:
1647 case PROCESSOR_CORE2
:
1648 case PROCESSOR_COREI7
:
1649 case PROCESSOR_L1OM
:
1650 case PROCESSOR_K1OM
:
1651 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1656 case PROCESSOR_GENERIC64
:
1662 if (patt
== f32_patt
)
1664 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1665 /* Limit number of NOPs to 2 for older processors. */
1666 max_number_of_nops
= 2;
1670 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1671 /* Limit number of NOPs to 7 for newer processors. */
1672 max_number_of_nops
= 7;
1677 limit
= max_single_nop_size
;
1679 if (fragP
->fr_type
== rs_fill_nop
)
1681 /* Output NOPs for .nop directive. */
1682 if (limit
> max_single_nop_size
)
1684 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1685 _("invalid single nop size: %d "
1686 "(expect within [0, %d])"),
1687 limit
, max_single_nop_size
);
1691 else if (fragP
->fr_type
!= rs_machine_dependent
)
1692 fragP
->fr_var
= count
;
1694 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1696 /* Generate jump over NOPs. */
1697 offsetT disp
= count
- 2;
1698 if (fits_in_imm7 (disp
))
1700 /* Use "jmp disp8" if possible. */
1702 where
[0] = jump_disp8
[0];
1708 unsigned int size_of_jump
;
1710 if (flag_code
== CODE_16BIT
)
1712 where
[0] = jump16_disp32
[0];
1713 where
[1] = jump16_disp32
[1];
1718 where
[0] = jump32_disp32
[0];
1722 count
-= size_of_jump
+ 4;
1723 if (!fits_in_imm31 (count
))
1725 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1726 _("jump over nop padding out of range"));
1730 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1731 where
+= size_of_jump
+ 4;
1735 /* Generate multiple NOPs. */
1736 i386_output_nops (where
, patt
, count
, limit
);
1740 operand_type_all_zero (const union i386_operand_type
*x
)
1742 switch (ARRAY_SIZE(x
->array
))
1753 return !x
->array
[0];
1760 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1762 switch (ARRAY_SIZE(x
->array
))
1778 x
->bitfield
.class = ClassNone
;
1779 x
->bitfield
.instance
= InstanceNone
;
1783 operand_type_equal (const union i386_operand_type
*x
,
1784 const union i386_operand_type
*y
)
1786 switch (ARRAY_SIZE(x
->array
))
1789 if (x
->array
[2] != y
->array
[2])
1793 if (x
->array
[1] != y
->array
[1])
1797 return x
->array
[0] == y
->array
[0];
1805 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1807 switch (ARRAY_SIZE(x
->array
))
1822 return !x
->array
[0];
1829 cpu_flags_equal (const union i386_cpu_flags
*x
,
1830 const union i386_cpu_flags
*y
)
1832 switch (ARRAY_SIZE(x
->array
))
1835 if (x
->array
[3] != y
->array
[3])
1839 if (x
->array
[2] != y
->array
[2])
1843 if (x
->array
[1] != y
->array
[1])
1847 return x
->array
[0] == y
->array
[0];
1855 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1857 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1858 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1861 static INLINE i386_cpu_flags
1862 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[3] &= y
.array
[3];
1870 x
.array
[2] &= y
.array
[2];
1873 x
.array
[1] &= y
.array
[1];
1876 x
.array
[0] &= y
.array
[0];
1884 static INLINE i386_cpu_flags
1885 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1887 switch (ARRAY_SIZE (x
.array
))
1890 x
.array
[3] |= y
.array
[3];
1893 x
.array
[2] |= y
.array
[2];
1896 x
.array
[1] |= y
.array
[1];
1899 x
.array
[0] |= y
.array
[0];
1907 static INLINE i386_cpu_flags
1908 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1910 switch (ARRAY_SIZE (x
.array
))
1913 x
.array
[3] &= ~y
.array
[3];
1916 x
.array
[2] &= ~y
.array
[2];
1919 x
.array
[1] &= ~y
.array
[1];
1922 x
.array
[0] &= ~y
.array
[0];
1930 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1932 #define CPU_FLAGS_ARCH_MATCH 0x1
1933 #define CPU_FLAGS_64BIT_MATCH 0x2
1935 #define CPU_FLAGS_PERFECT_MATCH \
1936 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1938 /* Return CPU flags match bits. */
1941 cpu_flags_match (const insn_template
*t
)
1943 i386_cpu_flags x
= t
->cpu_flags
;
1944 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1946 x
.bitfield
.cpu64
= 0;
1947 x
.bitfield
.cpuno64
= 0;
1949 if (cpu_flags_all_zero (&x
))
1951 /* This instruction is available on all archs. */
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1956 /* This instruction is available only on some archs. */
1957 i386_cpu_flags cpu
= cpu_arch_flags
;
1959 /* AVX512VL is no standalone feature - match it and then strip it. */
1960 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1962 x
.bitfield
.cpuavx512vl
= 0;
1964 cpu
= cpu_flags_and (x
, cpu
);
1965 if (!cpu_flags_all_zero (&cpu
))
1967 if (x
.bitfield
.cpuavx
)
1969 /* We need to check a few extra flags with AVX. */
1970 if (cpu
.bitfield
.cpuavx
1971 && (!t
->opcode_modifier
.sse2avx
1972 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1973 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1974 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1975 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1976 match
|= CPU_FLAGS_ARCH_MATCH
;
1978 else if (x
.bitfield
.cpuavx512f
)
1980 /* We need to check a few extra flags with AVX512F. */
1981 if (cpu
.bitfield
.cpuavx512f
1982 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1983 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1984 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1985 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 match
|= CPU_FLAGS_ARCH_MATCH
;
1994 static INLINE i386_operand_type
1995 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1997 if (x
.bitfield
.class != y
.bitfield
.class)
1998 x
.bitfield
.class = ClassNone
;
1999 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2000 x
.bitfield
.instance
= InstanceNone
;
2002 switch (ARRAY_SIZE (x
.array
))
2005 x
.array
[2] &= y
.array
[2];
2008 x
.array
[1] &= y
.array
[1];
2011 x
.array
[0] &= y
.array
[0];
2019 static INLINE i386_operand_type
2020 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2022 gas_assert (y
.bitfield
.class == ClassNone
);
2023 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2025 switch (ARRAY_SIZE (x
.array
))
2028 x
.array
[2] &= ~y
.array
[2];
2031 x
.array
[1] &= ~y
.array
[1];
2034 x
.array
[0] &= ~y
.array
[0];
2042 static INLINE i386_operand_type
2043 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2045 gas_assert (x
.bitfield
.class == ClassNone
||
2046 y
.bitfield
.class == ClassNone
||
2047 x
.bitfield
.class == y
.bitfield
.class);
2048 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2049 y
.bitfield
.instance
== InstanceNone
||
2050 x
.bitfield
.instance
== y
.bitfield
.instance
);
2052 switch (ARRAY_SIZE (x
.array
))
2055 x
.array
[2] |= y
.array
[2];
2058 x
.array
[1] |= y
.array
[1];
2061 x
.array
[0] |= y
.array
[0];
2069 static INLINE i386_operand_type
2070 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2072 gas_assert (y
.bitfield
.class == ClassNone
);
2073 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2075 switch (ARRAY_SIZE (x
.array
))
2078 x
.array
[2] ^= y
.array
[2];
2081 x
.array
[1] ^= y
.array
[1];
2084 x
.array
[0] ^= y
.array
[0];
2092 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2093 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2094 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2095 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2096 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2097 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2098 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2099 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2100 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2101 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2102 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2103 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2104 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2105 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2116 operand_type_check (i386_operand_type t
, enum operand_type c
)
2121 return t
.bitfield
.class == Reg
;
2124 return (t
.bitfield
.imm8
2128 || t
.bitfield
.imm32s
2129 || t
.bitfield
.imm64
);
2132 return (t
.bitfield
.disp8
2133 || t
.bitfield
.disp16
2134 || t
.bitfield
.disp32
2135 || t
.bitfield
.disp32s
2136 || t
.bitfield
.disp64
);
2139 return (t
.bitfield
.disp8
2140 || t
.bitfield
.disp16
2141 || t
.bitfield
.disp32
2142 || t
.bitfield
.disp32s
2143 || t
.bitfield
.disp64
2144 || t
.bitfield
.baseindex
);
2153 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2154 between operand GIVEN and opeand WANTED for instruction template T. */
2157 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2160 return !((i
.types
[given
].bitfield
.byte
2161 && !t
->operand_types
[wanted
].bitfield
.byte
)
2162 || (i
.types
[given
].bitfield
.word
2163 && !t
->operand_types
[wanted
].bitfield
.word
)
2164 || (i
.types
[given
].bitfield
.dword
2165 && !t
->operand_types
[wanted
].bitfield
.dword
)
2166 || (i
.types
[given
].bitfield
.qword
2167 && !t
->operand_types
[wanted
].bitfield
.qword
)
2168 || (i
.types
[given
].bitfield
.tbyte
2169 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2172 /* Return 1 if there is no conflict in SIMD register between operand
2173 GIVEN and opeand WANTED for instruction template T. */
2176 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2179 return !((i
.types
[given
].bitfield
.xmmword
2180 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2181 || (i
.types
[given
].bitfield
.ymmword
2182 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2183 || (i
.types
[given
].bitfield
.zmmword
2184 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2185 || (i
.types
[given
].bitfield
.tmmword
2186 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2189 /* Return 1 if there is no conflict in any size between operand GIVEN
2190 and opeand WANTED for instruction template T. */
2193 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2196 return (match_operand_size (t
, wanted
, given
)
2197 && !((i
.types
[given
].bitfield
.unspecified
2198 && !i
.broadcast
.type
2199 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2200 || (i
.types
[given
].bitfield
.fword
2201 && !t
->operand_types
[wanted
].bitfield
.fword
)
2202 /* For scalar opcode templates to allow register and memory
2203 operands at the same time, some special casing is needed
2204 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2205 down-conversion vpmov*. */
2206 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2207 && t
->operand_types
[wanted
].bitfield
.byte
2208 + t
->operand_types
[wanted
].bitfield
.word
2209 + t
->operand_types
[wanted
].bitfield
.dword
2210 + t
->operand_types
[wanted
].bitfield
.qword
2211 > !!t
->opcode_modifier
.broadcast
)
2212 ? (i
.types
[given
].bitfield
.xmmword
2213 || i
.types
[given
].bitfield
.ymmword
2214 || i
.types
[given
].bitfield
.zmmword
)
2215 : !match_simd_size(t
, wanted
, given
))));
2218 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2219 operands for instruction template T, and it has MATCH_REVERSE set if there
2220 is no size conflict on any operands for the template with operands reversed
2221 (and the template allows for reversing in the first place). */
2223 #define MATCH_STRAIGHT 1
2224 #define MATCH_REVERSE 2
2226 static INLINE
unsigned int
2227 operand_size_match (const insn_template
*t
)
2229 unsigned int j
, match
= MATCH_STRAIGHT
;
2231 /* Don't check non-absolute jump instructions. */
2232 if (t
->opcode_modifier
.jump
2233 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2236 /* Check memory and accumulator operand size. */
2237 for (j
= 0; j
< i
.operands
; j
++)
2239 if (i
.types
[j
].bitfield
.class != Reg
2240 && i
.types
[j
].bitfield
.class != RegSIMD
2241 && t
->opcode_modifier
.anysize
)
2244 if (t
->operand_types
[j
].bitfield
.class == Reg
2245 && !match_operand_size (t
, j
, j
))
2251 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2252 && !match_simd_size (t
, j
, j
))
2258 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2259 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2265 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2272 if (!t
->opcode_modifier
.d
)
2276 i
.error
= operand_size_mismatch
;
2280 /* Check reverse. */
2281 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2283 for (j
= 0; j
< i
.operands
; j
++)
2285 unsigned int given
= i
.operands
- j
- 1;
2287 if (t
->operand_types
[j
].bitfield
.class == Reg
2288 && !match_operand_size (t
, j
, given
))
2291 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2292 && !match_simd_size (t
, j
, given
))
2295 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2296 && (!match_operand_size (t
, j
, given
)
2297 || !match_simd_size (t
, j
, given
)))
2300 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2304 return match
| MATCH_REVERSE
;
2308 operand_type_match (i386_operand_type overlap
,
2309 i386_operand_type given
)
2311 i386_operand_type temp
= overlap
;
2313 temp
.bitfield
.unspecified
= 0;
2314 temp
.bitfield
.byte
= 0;
2315 temp
.bitfield
.word
= 0;
2316 temp
.bitfield
.dword
= 0;
2317 temp
.bitfield
.fword
= 0;
2318 temp
.bitfield
.qword
= 0;
2319 temp
.bitfield
.tbyte
= 0;
2320 temp
.bitfield
.xmmword
= 0;
2321 temp
.bitfield
.ymmword
= 0;
2322 temp
.bitfield
.zmmword
= 0;
2323 temp
.bitfield
.tmmword
= 0;
2324 if (operand_type_all_zero (&temp
))
2327 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2331 i
.error
= operand_type_mismatch
;
2335 /* If given types g0 and g1 are registers they must be of the same type
2336 unless the expected operand type register overlap is null.
2337 Some Intel syntax memory operand size checking also happens here. */
2340 operand_type_register_match (i386_operand_type g0
,
2341 i386_operand_type t0
,
2342 i386_operand_type g1
,
2343 i386_operand_type t1
)
2345 if (g0
.bitfield
.class != Reg
2346 && g0
.bitfield
.class != RegSIMD
2347 && (!operand_type_check (g0
, anymem
)
2348 || g0
.bitfield
.unspecified
2349 || (t0
.bitfield
.class != Reg
2350 && t0
.bitfield
.class != RegSIMD
)))
2353 if (g1
.bitfield
.class != Reg
2354 && g1
.bitfield
.class != RegSIMD
2355 && (!operand_type_check (g1
, anymem
)
2356 || g1
.bitfield
.unspecified
2357 || (t1
.bitfield
.class != Reg
2358 && t1
.bitfield
.class != RegSIMD
)))
2361 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2362 && g0
.bitfield
.word
== g1
.bitfield
.word
2363 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2364 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2365 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2366 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2367 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2370 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2371 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2372 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2373 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2374 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2375 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2376 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2379 i
.error
= register_type_mismatch
;
2384 static INLINE
unsigned int
2385 register_number (const reg_entry
*r
)
2387 unsigned int nr
= r
->reg_num
;
2389 if (r
->reg_flags
& RegRex
)
2392 if (r
->reg_flags
& RegVRex
)
2398 static INLINE
unsigned int
2399 mode_from_disp_size (i386_operand_type t
)
2401 if (t
.bitfield
.disp8
)
2403 else if (t
.bitfield
.disp16
2404 || t
.bitfield
.disp32
2405 || t
.bitfield
.disp32s
)
2412 fits_in_signed_byte (addressT num
)
2414 return num
+ 0x80 <= 0xff;
2418 fits_in_unsigned_byte (addressT num
)
2424 fits_in_unsigned_word (addressT num
)
2426 return num
<= 0xffff;
2430 fits_in_signed_word (addressT num
)
2432 return num
+ 0x8000 <= 0xffff;
2436 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2441 return num
+ 0x80000000 <= 0xffffffff;
2443 } /* fits_in_signed_long() */
2446 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2451 return num
<= 0xffffffff;
2453 } /* fits_in_unsigned_long() */
2455 static INLINE valueT
extend_to_32bit_address (addressT num
)
2458 if (fits_in_unsigned_long(num
))
2459 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2461 if (!fits_in_signed_long (num
))
2462 return num
& 0xffffffff;
2469 fits_in_disp8 (offsetT num
)
2471 int shift
= i
.memshift
;
2477 mask
= (1 << shift
) - 1;
2479 /* Return 0 if NUM isn't properly aligned. */
2483 /* Check if NUM will fit in 8bit after shift. */
2484 return fits_in_signed_byte (num
>> shift
);
2488 fits_in_imm4 (offsetT num
)
2490 return (num
& 0xf) == num
;
2493 static i386_operand_type
2494 smallest_imm_type (offsetT num
)
2496 i386_operand_type t
;
2498 operand_type_set (&t
, 0);
2499 t
.bitfield
.imm64
= 1;
2501 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2503 /* This code is disabled on the 486 because all the Imm1 forms
2504 in the opcode table are slower on the i486. They're the
2505 versions with the implicitly specified single-position
2506 displacement, which has another syntax if you really want to
2508 t
.bitfield
.imm1
= 1;
2509 t
.bitfield
.imm8
= 1;
2510 t
.bitfield
.imm8s
= 1;
2511 t
.bitfield
.imm16
= 1;
2512 t
.bitfield
.imm32
= 1;
2513 t
.bitfield
.imm32s
= 1;
2515 else if (fits_in_signed_byte (num
))
2517 t
.bitfield
.imm8
= 1;
2518 t
.bitfield
.imm8s
= 1;
2519 t
.bitfield
.imm16
= 1;
2520 t
.bitfield
.imm32
= 1;
2521 t
.bitfield
.imm32s
= 1;
2523 else if (fits_in_unsigned_byte (num
))
2525 t
.bitfield
.imm8
= 1;
2526 t
.bitfield
.imm16
= 1;
2527 t
.bitfield
.imm32
= 1;
2528 t
.bitfield
.imm32s
= 1;
2530 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2532 t
.bitfield
.imm16
= 1;
2533 t
.bitfield
.imm32
= 1;
2534 t
.bitfield
.imm32s
= 1;
2536 else if (fits_in_signed_long (num
))
2538 t
.bitfield
.imm32
= 1;
2539 t
.bitfield
.imm32s
= 1;
2541 else if (fits_in_unsigned_long (num
))
2542 t
.bitfield
.imm32
= 1;
2548 offset_in_range (offsetT val
, int size
)
2554 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2555 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2557 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2559 case sizeof (val
): return val
;
2563 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2564 as_warn (_("%"BFD_VMA_FMT
"x shortened to %"BFD_VMA_FMT
"x"),
2580 a. PREFIX_EXIST if attempting to add a prefix where one from the
2581 same class already exists.
2582 b. PREFIX_LOCK if lock prefix is added.
2583 c. PREFIX_REP if rep/repne prefix is added.
2584 d. PREFIX_DS if ds prefix is added.
2585 e. PREFIX_OTHER if other prefix is added.
2588 static enum PREFIX_GROUP
2589 add_prefix (unsigned int prefix
)
2591 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2594 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2595 && flag_code
== CODE_64BIT
)
2597 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2598 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2599 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2600 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2611 case DS_PREFIX_OPCODE
:
2614 case CS_PREFIX_OPCODE
:
2615 case ES_PREFIX_OPCODE
:
2616 case FS_PREFIX_OPCODE
:
2617 case GS_PREFIX_OPCODE
:
2618 case SS_PREFIX_OPCODE
:
2622 case REPNE_PREFIX_OPCODE
:
2623 case REPE_PREFIX_OPCODE
:
2628 case LOCK_PREFIX_OPCODE
:
2637 case ADDR_PREFIX_OPCODE
:
2641 case DATA_PREFIX_OPCODE
:
2645 if (i
.prefix
[q
] != 0)
2653 i
.prefix
[q
] |= prefix
;
2656 as_bad (_("same type of prefix used twice"));
2662 update_code_flag (int value
, int check
)
2664 PRINTF_LIKE ((*as_error
));
2666 flag_code
= (enum flag_code
) value
;
2667 if (flag_code
== CODE_64BIT
)
2669 cpu_arch_flags
.bitfield
.cpu64
= 1;
2670 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2674 cpu_arch_flags
.bitfield
.cpu64
= 0;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2677 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2680 as_error
= as_fatal
;
2683 (*as_error
) (_("64bit mode not supported on `%s'."),
2684 cpu_arch_name
? cpu_arch_name
: default_arch
);
2686 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2689 as_error
= as_fatal
;
2692 (*as_error
) (_("32bit mode not supported on `%s'."),
2693 cpu_arch_name
? cpu_arch_name
: default_arch
);
2695 stackop_size
= '\0';
2699 set_code_flag (int value
)
2701 update_code_flag (value
, 0);
2705 set_16bit_gcc_code_flag (int new_code_flag
)
2707 flag_code
= (enum flag_code
) new_code_flag
;
2708 if (flag_code
!= CODE_16BIT
)
2710 cpu_arch_flags
.bitfield
.cpu64
= 0;
2711 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2712 stackop_size
= LONG_MNEM_SUFFIX
;
2716 set_intel_syntax (int syntax_flag
)
2718 /* Find out if register prefixing is specified. */
2719 int ask_naked_reg
= 0;
2722 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2725 int e
= get_symbol_name (&string
);
2727 if (strcmp (string
, "prefix") == 0)
2729 else if (strcmp (string
, "noprefix") == 0)
2732 as_bad (_("bad argument to syntax directive."));
2733 (void) restore_line_pointer (e
);
2735 demand_empty_rest_of_line ();
2737 intel_syntax
= syntax_flag
;
2739 if (ask_naked_reg
== 0)
2740 allow_naked_reg
= (intel_syntax
2741 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2743 allow_naked_reg
= (ask_naked_reg
< 0);
2745 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2747 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2748 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2749 register_prefix
= allow_naked_reg
? "" : "%";
2753 set_intel_mnemonic (int mnemonic_flag
)
2755 intel_mnemonic
= mnemonic_flag
;
2759 set_allow_index_reg (int flag
)
2761 allow_index_reg
= flag
;
2765 set_check (int what
)
2767 enum check_kind
*kind
;
2772 kind
= &operand_check
;
2783 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2786 int e
= get_symbol_name (&string
);
2788 if (strcmp (string
, "none") == 0)
2790 else if (strcmp (string
, "warning") == 0)
2791 *kind
= check_warning
;
2792 else if (strcmp (string
, "error") == 0)
2793 *kind
= check_error
;
2795 as_bad (_("bad argument to %s_check directive."), str
);
2796 (void) restore_line_pointer (e
);
2799 as_bad (_("missing argument for %s_check directive"), str
);
2801 demand_empty_rest_of_line ();
2805 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2806 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2808 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2809 static const char *arch
;
2811 /* Intel LIOM is only supported on ELF. */
2817 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2818 use default_arch. */
2819 arch
= cpu_arch_name
;
2821 arch
= default_arch
;
2824 /* If we are targeting Intel MCU, we must enable it. */
2825 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2826 || new_flag
.bitfield
.cpuiamcu
)
2829 /* If we are targeting Intel L1OM, we must enable it. */
2830 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2831 || new_flag
.bitfield
.cpul1om
)
2834 /* If we are targeting Intel K1OM, we must enable it. */
2835 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2836 || new_flag
.bitfield
.cpuk1om
)
2839 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2844 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2848 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2851 int e
= get_symbol_name (&string
);
2853 i386_cpu_flags flags
;
2855 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2857 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2859 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2863 cpu_arch_name
= cpu_arch
[j
].name
;
2864 cpu_sub_arch_name
= NULL
;
2865 cpu_arch_flags
= cpu_arch
[j
].flags
;
2866 if (flag_code
== CODE_64BIT
)
2868 cpu_arch_flags
.bitfield
.cpu64
= 1;
2869 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2873 cpu_arch_flags
.bitfield
.cpu64
= 0;
2874 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2876 cpu_arch_isa
= cpu_arch
[j
].type
;
2877 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2878 if (!cpu_arch_tune_set
)
2880 cpu_arch_tune
= cpu_arch_isa
;
2881 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2886 flags
= cpu_flags_or (cpu_arch_flags
,
2889 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2891 if (cpu_sub_arch_name
)
2893 char *name
= cpu_sub_arch_name
;
2894 cpu_sub_arch_name
= concat (name
,
2896 (const char *) NULL
);
2900 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2901 cpu_arch_flags
= flags
;
2902 cpu_arch_isa_flags
= flags
;
2906 = cpu_flags_or (cpu_arch_isa_flags
,
2908 (void) restore_line_pointer (e
);
2909 demand_empty_rest_of_line ();
2914 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2916 /* Disable an ISA extension. */
2917 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2918 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2920 flags
= cpu_flags_and_not (cpu_arch_flags
,
2921 cpu_noarch
[j
].flags
);
2922 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2924 if (cpu_sub_arch_name
)
2926 char *name
= cpu_sub_arch_name
;
2927 cpu_sub_arch_name
= concat (name
, string
,
2928 (const char *) NULL
);
2932 cpu_sub_arch_name
= xstrdup (string
);
2933 cpu_arch_flags
= flags
;
2934 cpu_arch_isa_flags
= flags
;
2936 (void) restore_line_pointer (e
);
2937 demand_empty_rest_of_line ();
2941 j
= ARRAY_SIZE (cpu_arch
);
2944 if (j
>= ARRAY_SIZE (cpu_arch
))
2945 as_bad (_("no such architecture: `%s'"), string
);
2947 *input_line_pointer
= e
;
2950 as_bad (_("missing cpu architecture"));
2952 no_cond_jump_promotion
= 0;
2953 if (*input_line_pointer
== ','
2954 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2959 ++input_line_pointer
;
2960 e
= get_symbol_name (&string
);
2962 if (strcmp (string
, "nojumps") == 0)
2963 no_cond_jump_promotion
= 1;
2964 else if (strcmp (string
, "jumps") == 0)
2967 as_bad (_("no such architecture modifier: `%s'"), string
);
2969 (void) restore_line_pointer (e
);
2972 demand_empty_rest_of_line ();
2975 enum bfd_architecture
2978 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2980 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2981 || flag_code
!= CODE_64BIT
)
2982 as_fatal (_("Intel L1OM is 64bit ELF only"));
2983 return bfd_arch_l1om
;
2985 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2987 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2988 || flag_code
!= CODE_64BIT
)
2989 as_fatal (_("Intel K1OM is 64bit ELF only"));
2990 return bfd_arch_k1om
;
2992 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2994 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2995 || flag_code
== CODE_64BIT
)
2996 as_fatal (_("Intel MCU is 32bit ELF only"));
2997 return bfd_arch_iamcu
;
3000 return bfd_arch_i386
;
3006 if (startswith (default_arch
, "x86_64"))
3008 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3010 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3011 || default_arch
[6] != '\0')
3012 as_fatal (_("Intel L1OM is 64bit ELF only"));
3013 return bfd_mach_l1om
;
3015 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3017 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3018 || default_arch
[6] != '\0')
3019 as_fatal (_("Intel K1OM is 64bit ELF only"));
3020 return bfd_mach_k1om
;
3022 else if (default_arch
[6] == '\0')
3023 return bfd_mach_x86_64
;
3025 return bfd_mach_x64_32
;
3027 else if (!strcmp (default_arch
, "i386")
3028 || !strcmp (default_arch
, "iamcu"))
3030 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3032 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3033 as_fatal (_("Intel MCU is 32bit ELF only"));
3034 return bfd_mach_i386_iamcu
;
3037 return bfd_mach_i386_i386
;
3040 as_fatal (_("unknown architecture"));
3046 /* Support pseudo prefixes like {disp32}. */
3047 lex_type
['{'] = LEX_BEGIN_NAME
;
3049 /* Initialize op_hash hash table. */
3050 op_hash
= str_htab_create ();
3053 const insn_template
*optab
;
3054 templates
*core_optab
;
3056 /* Setup for loop. */
3058 core_optab
= XNEW (templates
);
3059 core_optab
->start
= optab
;
3064 if (optab
->name
== NULL
3065 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3067 /* different name --> ship out current template list;
3068 add to hash table; & begin anew. */
3069 core_optab
->end
= optab
;
3070 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3071 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3073 if (optab
->name
== NULL
)
3075 core_optab
= XNEW (templates
);
3076 core_optab
->start
= optab
;
3081 /* Initialize reg_hash hash table. */
3082 reg_hash
= str_htab_create ();
3084 const reg_entry
*regtab
;
3085 unsigned int regtab_size
= i386_regtab_size
;
3087 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3089 switch (regtab
->reg_type
.bitfield
.class)
3092 if (regtab
->reg_type
.bitfield
.dword
)
3094 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3097 else if (regtab
->reg_type
.bitfield
.tbyte
)
3099 /* There's no point inserting st(<N>) in the hash table, as
3100 parentheses aren't included in register_chars[] anyway. */
3101 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3108 switch (regtab
->reg_num
)
3110 case 0: reg_es
= regtab
; break;
3111 case 2: reg_ss
= regtab
; break;
3112 case 3: reg_ds
= regtab
; break;
3117 if (!regtab
->reg_num
)
3122 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3123 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3127 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3132 for (c
= 0; c
< 256; c
++)
3134 if (ISDIGIT (c
) || ISLOWER (c
))
3136 mnemonic_chars
[c
] = c
;
3137 register_chars
[c
] = c
;
3138 operand_chars
[c
] = c
;
3140 else if (ISUPPER (c
))
3142 mnemonic_chars
[c
] = TOLOWER (c
);
3143 register_chars
[c
] = mnemonic_chars
[c
];
3144 operand_chars
[c
] = c
;
3146 else if (c
== '{' || c
== '}')
3148 mnemonic_chars
[c
] = c
;
3149 operand_chars
[c
] = c
;
3151 #ifdef SVR4_COMMENT_CHARS
3152 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3153 operand_chars
[c
] = c
;
3156 if (ISALPHA (c
) || ISDIGIT (c
))
3157 identifier_chars
[c
] = c
;
3160 identifier_chars
[c
] = c
;
3161 operand_chars
[c
] = c
;
3166 identifier_chars
['@'] = '@';
3169 identifier_chars
['?'] = '?';
3170 operand_chars
['?'] = '?';
3172 mnemonic_chars
['_'] = '_';
3173 mnemonic_chars
['-'] = '-';
3174 mnemonic_chars
['.'] = '.';
3175 identifier_chars
['_'] = '_';
3176 identifier_chars
['.'] = '.';
3178 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3179 operand_chars
[(unsigned char) *p
] = *p
;
3182 if (flag_code
== CODE_64BIT
)
3184 #if defined (OBJ_COFF) && defined (TE_PE)
3185 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3188 x86_dwarf2_return_column
= 16;
3190 x86_cie_data_alignment
= -8;
3194 x86_dwarf2_return_column
= 8;
3195 x86_cie_data_alignment
= -4;
3198 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3199 can be turned into BRANCH_PREFIX frag. */
3200 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3205 i386_print_statistics (FILE *file
)
3207 htab_print_statistics (file
, "i386 opcode", op_hash
);
3208 htab_print_statistics (file
, "i386 register", reg_hash
);
3213 /* Debugging routines for md_assemble. */
3214 static void pte (insn_template
*);
3215 static void pt (i386_operand_type
);
3216 static void pe (expressionS
*);
3217 static void ps (symbolS
*);
3220 pi (const char *line
, i386_insn
*x
)
3224 fprintf (stdout
, "%s: template ", line
);
3226 fprintf (stdout
, " address: base %s index %s scale %x\n",
3227 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3228 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3229 x
->log2_scale_factor
);
3230 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3231 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3232 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3233 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3234 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3235 (x
->rex
& REX_W
) != 0,
3236 (x
->rex
& REX_R
) != 0,
3237 (x
->rex
& REX_X
) != 0,
3238 (x
->rex
& REX_B
) != 0);
3239 for (j
= 0; j
< x
->operands
; j
++)
3241 fprintf (stdout
, " #%d: ", j
+ 1);
3243 fprintf (stdout
, "\n");
3244 if (x
->types
[j
].bitfield
.class == Reg
3245 || x
->types
[j
].bitfield
.class == RegMMX
3246 || x
->types
[j
].bitfield
.class == RegSIMD
3247 || x
->types
[j
].bitfield
.class == RegMask
3248 || x
->types
[j
].bitfield
.class == SReg
3249 || x
->types
[j
].bitfield
.class == RegCR
3250 || x
->types
[j
].bitfield
.class == RegDR
3251 || x
->types
[j
].bitfield
.class == RegTR
3252 || x
->types
[j
].bitfield
.class == RegBND
)
3253 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3254 if (operand_type_check (x
->types
[j
], imm
))
3256 if (operand_type_check (x
->types
[j
], disp
))
3257 pe (x
->op
[j
].disps
);
3262 pte (insn_template
*t
)
3264 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3265 static const char *const opc_spc
[] = {
3266 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3267 "XOP08", "XOP09", "XOP0A",
3271 fprintf (stdout
, " %d operands ", t
->operands
);
3272 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3273 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3274 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3275 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3276 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3277 if (t
->extension_opcode
!= None
)
3278 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3279 if (t
->opcode_modifier
.d
)
3280 fprintf (stdout
, "D");
3281 if (t
->opcode_modifier
.w
)
3282 fprintf (stdout
, "W");
3283 fprintf (stdout
, "\n");
3284 for (j
= 0; j
< t
->operands
; j
++)
3286 fprintf (stdout
, " #%d type ", j
+ 1);
3287 pt (t
->operand_types
[j
]);
3288 fprintf (stdout
, "\n");
3295 fprintf (stdout
, " operation %d\n", e
->X_op
);
3296 fprintf (stdout
, " add_number %" BFD_VMA_FMT
"d (%" BFD_VMA_FMT
"x)\n",
3297 e
->X_add_number
, e
->X_add_number
);
3298 if (e
->X_add_symbol
)
3300 fprintf (stdout
, " add_symbol ");
3301 ps (e
->X_add_symbol
);
3302 fprintf (stdout
, "\n");
3306 fprintf (stdout
, " op_symbol ");
3307 ps (e
->X_op_symbol
);
3308 fprintf (stdout
, "\n");
3315 fprintf (stdout
, "%s type %s%s",
3317 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3318 segment_name (S_GET_SEGMENT (s
)));
3321 static struct type_name
3323 i386_operand_type mask
;
3326 const type_names
[] =
3328 { OPERAND_TYPE_REG8
, "r8" },
3329 { OPERAND_TYPE_REG16
, "r16" },
3330 { OPERAND_TYPE_REG32
, "r32" },
3331 { OPERAND_TYPE_REG64
, "r64" },
3332 { OPERAND_TYPE_ACC8
, "acc8" },
3333 { OPERAND_TYPE_ACC16
, "acc16" },
3334 { OPERAND_TYPE_ACC32
, "acc32" },
3335 { OPERAND_TYPE_ACC64
, "acc64" },
3336 { OPERAND_TYPE_IMM8
, "i8" },
3337 { OPERAND_TYPE_IMM8
, "i8s" },
3338 { OPERAND_TYPE_IMM16
, "i16" },
3339 { OPERAND_TYPE_IMM32
, "i32" },
3340 { OPERAND_TYPE_IMM32S
, "i32s" },
3341 { OPERAND_TYPE_IMM64
, "i64" },
3342 { OPERAND_TYPE_IMM1
, "i1" },
3343 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3344 { OPERAND_TYPE_DISP8
, "d8" },
3345 { OPERAND_TYPE_DISP16
, "d16" },
3346 { OPERAND_TYPE_DISP32
, "d32" },
3347 { OPERAND_TYPE_DISP32S
, "d32s" },
3348 { OPERAND_TYPE_DISP64
, "d64" },
3349 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3350 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3351 { OPERAND_TYPE_CONTROL
, "control reg" },
3352 { OPERAND_TYPE_TEST
, "test reg" },
3353 { OPERAND_TYPE_DEBUG
, "debug reg" },
3354 { OPERAND_TYPE_FLOATREG
, "FReg" },
3355 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3356 { OPERAND_TYPE_SREG
, "SReg" },
3357 { OPERAND_TYPE_REGMMX
, "rMMX" },
3358 { OPERAND_TYPE_REGXMM
, "rXMM" },
3359 { OPERAND_TYPE_REGYMM
, "rYMM" },
3360 { OPERAND_TYPE_REGZMM
, "rZMM" },
3361 { OPERAND_TYPE_REGTMM
, "rTMM" },
3362 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3366 pt (i386_operand_type t
)
3369 i386_operand_type a
;
3371 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3373 a
= operand_type_and (t
, type_names
[j
].mask
);
3374 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3375 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3380 #endif /* DEBUG386 */
3382 static bfd_reloc_code_real_type
3383 reloc (unsigned int size
,
3386 bfd_reloc_code_real_type other
)
3388 if (other
!= NO_RELOC
)
3390 reloc_howto_type
*rel
;
3395 case BFD_RELOC_X86_64_GOT32
:
3396 return BFD_RELOC_X86_64_GOT64
;
3398 case BFD_RELOC_X86_64_GOTPLT64
:
3399 return BFD_RELOC_X86_64_GOTPLT64
;
3401 case BFD_RELOC_X86_64_PLTOFF64
:
3402 return BFD_RELOC_X86_64_PLTOFF64
;
3404 case BFD_RELOC_X86_64_GOTPC32
:
3405 other
= BFD_RELOC_X86_64_GOTPC64
;
3407 case BFD_RELOC_X86_64_GOTPCREL
:
3408 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3410 case BFD_RELOC_X86_64_TPOFF32
:
3411 other
= BFD_RELOC_X86_64_TPOFF64
;
3413 case BFD_RELOC_X86_64_DTPOFF32
:
3414 other
= BFD_RELOC_X86_64_DTPOFF64
;
3420 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3421 if (other
== BFD_RELOC_SIZE32
)
3424 other
= BFD_RELOC_SIZE64
;
3427 as_bad (_("there are no pc-relative size relocations"));
3433 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3434 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3437 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3439 as_bad (_("unknown relocation (%u)"), other
);
3440 else if (size
!= bfd_get_reloc_size (rel
))
3441 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3442 bfd_get_reloc_size (rel
),
3444 else if (pcrel
&& !rel
->pc_relative
)
3445 as_bad (_("non-pc-relative relocation for pc-relative field"));
3446 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3448 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3450 as_bad (_("relocated field and relocation type differ in signedness"));
3459 as_bad (_("there are no unsigned pc-relative relocations"));
3462 case 1: return BFD_RELOC_8_PCREL
;
3463 case 2: return BFD_RELOC_16_PCREL
;
3464 case 4: return BFD_RELOC_32_PCREL
;
3465 case 8: return BFD_RELOC_64_PCREL
;
3467 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3474 case 4: return BFD_RELOC_X86_64_32S
;
3479 case 1: return BFD_RELOC_8
;
3480 case 2: return BFD_RELOC_16
;
3481 case 4: return BFD_RELOC_32
;
3482 case 8: return BFD_RELOC_64
;
3484 as_bad (_("cannot do %s %u byte relocation"),
3485 sign
> 0 ? "signed" : "unsigned", size
);
3491 /* Here we decide which fixups can be adjusted to make them relative to
3492 the beginning of the section instead of the symbol. Basically we need
3493 to make sure that the dynamic relocations are done correctly, so in
3494 some cases we force the original symbol to be used. */
3497 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3499 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3503 /* Don't adjust pc-relative references to merge sections in 64-bit
3505 if (use_rela_relocations
3506 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3510 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3511 and changed later by validate_fix. */
3512 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3513 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3516 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3517 for size relocations. */
3518 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3519 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3520 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3521 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3522 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3523 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3524 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3525 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3526 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3527 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3528 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3529 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3530 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3531 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3532 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3533 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3534 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3535 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3536 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3537 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3538 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3539 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3540 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3541 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3542 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3543 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3544 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3545 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3546 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3547 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3548 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3555 want_disp32 (const insn_template
*t
)
3557 return flag_code
!= CODE_64BIT
3558 || i
.prefix
[ADDR_PREFIX
]
3559 || (t
->base_opcode
== 0x8d
3560 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
3561 && (!i
.types
[1].bitfield
.qword
3562 || t
->opcode_modifier
.size
== SIZE32
));
3566 intel_float_operand (const char *mnemonic
)
3568 /* Note that the value returned is meaningful only for opcodes with (memory)
3569 operands, hence the code here is free to improperly handle opcodes that
3570 have no operands (for better performance and smaller code). */
3572 if (mnemonic
[0] != 'f')
3573 return 0; /* non-math */
3575 switch (mnemonic
[1])
3577 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3578 the fs segment override prefix not currently handled because no
3579 call path can make opcodes without operands get here */
3581 return 2 /* integer op */;
3583 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3584 return 3; /* fldcw/fldenv */
3587 if (mnemonic
[2] != 'o' /* fnop */)
3588 return 3; /* non-waiting control op */
3591 if (mnemonic
[2] == 's')
3592 return 3; /* frstor/frstpm */
3595 if (mnemonic
[2] == 'a')
3596 return 3; /* fsave */
3597 if (mnemonic
[2] == 't')
3599 switch (mnemonic
[3])
3601 case 'c': /* fstcw */
3602 case 'd': /* fstdw */
3603 case 'e': /* fstenv */
3604 case 's': /* fsts[gw] */
3610 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3611 return 0; /* fxsave/fxrstor are not really math ops */
3619 install_template (const insn_template
*t
)
3625 /* Note that for pseudo prefixes this produces a length of 1. But for them
3626 the length isn't interesting at all. */
3627 for (l
= 1; l
< 4; ++l
)
3628 if (!(t
->base_opcode
>> (8 * l
)))
3631 i
.opcode_length
= l
;
3634 /* Build the VEX prefix. */
3637 build_vex_prefix (const insn_template
*t
)
3639 unsigned int register_specifier
;
3640 unsigned int vector_length
;
3643 /* Check register specifier. */
3644 if (i
.vex
.register_specifier
)
3646 register_specifier
=
3647 ~register_number (i
.vex
.register_specifier
) & 0xf;
3648 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3651 register_specifier
= 0xf;
3653 /* Use 2-byte VEX prefix by swapping destination and source operand
3654 if there are more than 1 register operand. */
3655 if (i
.reg_operands
> 1
3656 && i
.vec_encoding
!= vex_encoding_vex3
3657 && i
.dir_encoding
== dir_encoding_default
3658 && i
.operands
== i
.reg_operands
3659 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3660 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3661 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3664 unsigned int xchg
= i
.operands
- 1;
3665 union i386_op temp_op
;
3666 i386_operand_type temp_type
;
3668 temp_type
= i
.types
[xchg
];
3669 i
.types
[xchg
] = i
.types
[0];
3670 i
.types
[0] = temp_type
;
3671 temp_op
= i
.op
[xchg
];
3672 i
.op
[xchg
] = i
.op
[0];
3675 gas_assert (i
.rm
.mode
== 3);
3679 i
.rm
.regmem
= i
.rm
.reg
;
3682 if (i
.tm
.opcode_modifier
.d
)
3683 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3684 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3685 else /* Use the next insn. */
3686 install_template (&t
[1]);
3689 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3690 are no memory operands and at least 3 register ones. */
3691 if (i
.reg_operands
>= 3
3692 && i
.vec_encoding
!= vex_encoding_vex3
3693 && i
.reg_operands
== i
.operands
- i
.imm_operands
3694 && i
.tm
.opcode_modifier
.vex
3695 && i
.tm
.opcode_modifier
.commutative
3696 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3698 && i
.vex
.register_specifier
3699 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3701 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3702 union i386_op temp_op
;
3703 i386_operand_type temp_type
;
3705 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3706 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3707 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3708 &i
.types
[i
.operands
- 3]));
3709 gas_assert (i
.rm
.mode
== 3);
3711 temp_type
= i
.types
[xchg
];
3712 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3713 i
.types
[xchg
+ 1] = temp_type
;
3714 temp_op
= i
.op
[xchg
];
3715 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3716 i
.op
[xchg
+ 1] = temp_op
;
3719 xchg
= i
.rm
.regmem
| 8;
3720 i
.rm
.regmem
= ~register_specifier
& 0xf;
3721 gas_assert (!(i
.rm
.regmem
& 8));
3722 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3723 register_specifier
= ~xchg
& 0xf;
3726 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3727 vector_length
= avxscalar
;
3728 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3734 /* Determine vector length from the last multi-length vector
3737 for (op
= t
->operands
; op
--;)
3738 if (t
->operand_types
[op
].bitfield
.xmmword
3739 && t
->operand_types
[op
].bitfield
.ymmword
3740 && i
.types
[op
].bitfield
.ymmword
)
3747 /* Check the REX.W bit and VEXW. */
3748 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3749 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3750 else if (i
.tm
.opcode_modifier
.vexw
)
3751 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3753 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3755 /* Use 2-byte VEX prefix if possible. */
3757 && i
.vec_encoding
!= vex_encoding_vex3
3758 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3759 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3761 /* 2-byte VEX prefix. */
3765 i
.vex
.bytes
[0] = 0xc5;
3767 /* Check the REX.R bit. */
3768 r
= (i
.rex
& REX_R
) ? 0 : 1;
3769 i
.vex
.bytes
[1] = (r
<< 7
3770 | register_specifier
<< 3
3771 | vector_length
<< 2
3772 | i
.tm
.opcode_modifier
.opcodeprefix
);
3776 /* 3-byte VEX prefix. */
3779 switch (i
.tm
.opcode_modifier
.opcodespace
)
3784 i
.vex
.bytes
[0] = 0xc4;
3789 i
.vex
.bytes
[0] = 0x8f;
3795 /* The high 3 bits of the second VEX byte are 1's compliment
3796 of RXB bits from REX. */
3797 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3799 i
.vex
.bytes
[2] = (w
<< 7
3800 | register_specifier
<< 3
3801 | vector_length
<< 2
3802 | i
.tm
.opcode_modifier
.opcodeprefix
);
3807 is_evex_encoding (const insn_template
*t
)
3809 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3810 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3811 || t
->opcode_modifier
.sae
;
3815 is_any_vex_encoding (const insn_template
*t
)
3817 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3820 /* Build the EVEX prefix. */
3823 build_evex_prefix (void)
3825 unsigned int register_specifier
, w
;
3826 rex_byte vrex_used
= 0;
3828 /* Check register specifier. */
3829 if (i
.vex
.register_specifier
)
3831 gas_assert ((i
.vrex
& REX_X
) == 0);
3833 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3834 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3835 register_specifier
+= 8;
3836 /* The upper 16 registers are encoded in the fourth byte of the
3838 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3839 i
.vex
.bytes
[3] = 0x8;
3840 register_specifier
= ~register_specifier
& 0xf;
3844 register_specifier
= 0xf;
3846 /* Encode upper 16 vector index register in the fourth byte of
3848 if (!(i
.vrex
& REX_X
))
3849 i
.vex
.bytes
[3] = 0x8;
3854 /* 4 byte EVEX prefix. */
3856 i
.vex
.bytes
[0] = 0x62;
3858 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3860 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3861 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3862 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3864 /* The fifth bit of the second EVEX byte is 1's compliment of the
3865 REX_R bit in VREX. */
3866 if (!(i
.vrex
& REX_R
))
3867 i
.vex
.bytes
[1] |= 0x10;
3871 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3873 /* When all operands are registers, the REX_X bit in REX is not
3874 used. We reuse it to encode the upper 16 registers, which is
3875 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3876 as 1's compliment. */
3877 if ((i
.vrex
& REX_B
))
3880 i
.vex
.bytes
[1] &= ~0x40;
3884 /* EVEX instructions shouldn't need the REX prefix. */
3885 i
.vrex
&= ~vrex_used
;
3886 gas_assert (i
.vrex
== 0);
3888 /* Check the REX.W bit and VEXW. */
3889 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3890 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3891 else if (i
.tm
.opcode_modifier
.vexw
)
3892 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3894 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3896 /* The third byte of the EVEX prefix. */
3897 i
.vex
.bytes
[2] = ((w
<< 7)
3898 | (register_specifier
<< 3)
3899 | 4 /* Encode the U bit. */
3900 | i
.tm
.opcode_modifier
.opcodeprefix
);
3902 /* The fourth byte of the EVEX prefix. */
3903 /* The zeroing-masking bit. */
3904 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3905 i
.vex
.bytes
[3] |= 0x80;
3907 /* Don't always set the broadcast bit if there is no RC. */
3908 if (i
.rounding
.type
== rc_none
)
3910 /* Encode the vector length. */
3911 unsigned int vec_length
;
3913 if (!i
.tm
.opcode_modifier
.evex
3914 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3918 /* Determine vector length from the last multi-length vector
3920 for (op
= i
.operands
; op
--;)
3921 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3922 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3923 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3925 if (i
.types
[op
].bitfield
.zmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3930 else if (i
.types
[op
].bitfield
.ymmword
)
3932 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3935 else if (i
.types
[op
].bitfield
.xmmword
)
3937 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3940 else if (i
.broadcast
.type
&& op
== i
.broadcast
.operand
)
3942 switch (i
.broadcast
.bytes
)
3945 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3948 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3951 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3960 if (op
>= MAX_OPERANDS
)
3964 switch (i
.tm
.opcode_modifier
.evex
)
3966 case EVEXLIG
: /* LL' is ignored */
3967 vec_length
= evexlig
<< 5;
3970 vec_length
= 0 << 5;
3973 vec_length
= 1 << 5;
3976 vec_length
= 2 << 5;
3982 i
.vex
.bytes
[3] |= vec_length
;
3983 /* Encode the broadcast bit. */
3984 if (i
.broadcast
.type
)
3985 i
.vex
.bytes
[3] |= 0x10;
3987 else if (i
.rounding
.type
!= saeonly
)
3988 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3990 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3993 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
3997 process_immext (void)
4001 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4002 which is coded in the same place as an 8-bit immediate field
4003 would be. Here we fake an 8-bit immediate operand from the
4004 opcode suffix stored in tm.extension_opcode.
4006 AVX instructions also use this encoding, for some of
4007 3 argument instructions. */
4009 gas_assert (i
.imm_operands
<= 1
4011 || (is_any_vex_encoding (&i
.tm
)
4012 && i
.operands
<= 4)));
4014 exp
= &im_expressions
[i
.imm_operands
++];
4015 i
.op
[i
.operands
].imms
= exp
;
4016 i
.types
[i
.operands
] = imm8
;
4018 exp
->X_op
= O_constant
;
4019 exp
->X_add_number
= i
.tm
.extension_opcode
;
4020 i
.tm
.extension_opcode
= None
;
4027 switch (i
.tm
.opcode_modifier
.prefixok
)
4035 as_bad (_("invalid instruction `%s' after `%s'"),
4036 i
.tm
.name
, i
.hle_prefix
);
4039 if (i
.prefix
[LOCK_PREFIX
])
4041 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4045 case PrefixHLERelease
:
4046 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4048 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4052 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4054 as_bad (_("memory destination needed for instruction `%s'"
4055 " after `xrelease'"), i
.tm
.name
);
4062 /* Try the shortest encoding by shortening operand size. */
4065 optimize_encoding (void)
4069 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4070 && i
.tm
.base_opcode
== 0x8d)
4073 lea symbol, %rN -> mov $symbol, %rN
4074 lea (%rM), %rN -> mov %rM, %rN
4075 lea (,%rM,1), %rN -> mov %rM, %rN
4077 and in 32-bit mode for 16-bit addressing
4079 lea (%rM), %rN -> movzx %rM, %rN
4081 and in 64-bit mode zap 32-bit addressing in favor of using a
4082 32-bit (or less) destination.
4084 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4086 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4087 i
.tm
.opcode_modifier
.size
= SIZE32
;
4088 i
.prefix
[ADDR_PREFIX
] = 0;
4091 if (!i
.index_reg
&& !i
.base_reg
)
4094 lea symbol, %rN -> mov $symbol, %rN
4096 if (flag_code
== CODE_64BIT
)
4098 /* Don't transform a relocation to a 16-bit one. */
4100 && i
.op
[0].disps
->X_op
!= O_constant
4101 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4104 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4105 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4107 i
.tm
.base_opcode
= 0xb8;
4108 i
.tm
.opcode_modifier
.modrm
= 0;
4109 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4110 i
.types
[0].bitfield
.imm32
= 1;
4113 i
.tm
.opcode_modifier
.size
= SIZE16
;
4114 i
.types
[0].bitfield
.imm16
= 1;
4119 /* Subject to further optimization below. */
4120 i
.tm
.base_opcode
= 0xc7;
4121 i
.tm
.extension_opcode
= 0;
4122 i
.types
[0].bitfield
.imm32s
= 1;
4123 i
.types
[0].bitfield
.baseindex
= 0;
4126 /* Outside of 64-bit mode address and operand sizes have to match if
4127 a relocation is involved, as otherwise we wouldn't (currently) or
4128 even couldn't express the relocation correctly. */
4129 else if (i
.op
[0].disps
4130 && i
.op
[0].disps
->X_op
!= O_constant
4131 && ((!i
.prefix
[ADDR_PREFIX
])
4132 != (flag_code
== CODE_32BIT
4133 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4134 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4136 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4137 destination is going to grow encoding size. */
4138 else if (flag_code
== CODE_16BIT
4139 && (optimize
<= 1 || optimize_for_space
)
4140 && !i
.prefix
[ADDR_PREFIX
]
4141 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4145 i
.tm
.base_opcode
= 0xb8;
4146 i
.tm
.opcode_modifier
.modrm
= 0;
4147 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4148 i
.types
[0].bitfield
.imm32
= 1;
4150 i
.types
[0].bitfield
.imm16
= 1;
4153 && i
.op
[0].disps
->X_op
== O_constant
4154 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4155 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4157 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4158 i
.op
[0].disps
->X_add_number
&= 0xffff;
4161 i
.tm
.operand_types
[0] = i
.types
[0];
4165 i
.op
[0].imms
= &im_expressions
[0];
4166 i
.op
[0].imms
->X_op
= O_absent
;
4169 else if (i
.op
[0].disps
4170 && (i
.op
[0].disps
->X_op
!= O_constant
4171 || i
.op
[0].disps
->X_add_number
))
4176 lea (%rM), %rN -> mov %rM, %rN
4177 lea (,%rM,1), %rN -> mov %rM, %rN
4178 lea (%rM), %rN -> movzx %rM, %rN
4180 const reg_entry
*addr_reg
;
4182 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4183 addr_reg
= i
.base_reg
;
4184 else if (!i
.base_reg
4185 && i
.index_reg
->reg_num
!= RegIZ
4186 && !i
.log2_scale_factor
)
4187 addr_reg
= i
.index_reg
;
4191 if (addr_reg
->reg_type
.bitfield
.word
4192 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4194 if (flag_code
!= CODE_32BIT
)
4196 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4197 i
.tm
.base_opcode
= 0xb7;
4200 i
.tm
.base_opcode
= 0x8b;
4202 if (addr_reg
->reg_type
.bitfield
.dword
4203 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4204 i
.tm
.opcode_modifier
.size
= SIZE32
;
4206 i
.op
[0].regs
= addr_reg
;
4211 i
.disp_operands
= 0;
4212 i
.prefix
[ADDR_PREFIX
] = 0;
4213 i
.prefix
[SEG_PREFIX
] = 0;
4217 if (optimize_for_space
4218 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4219 && i
.reg_operands
== 1
4220 && i
.imm_operands
== 1
4221 && !i
.types
[1].bitfield
.byte
4222 && i
.op
[0].imms
->X_op
== O_constant
4223 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4224 && (i
.tm
.base_opcode
== 0xa8
4225 || (i
.tm
.base_opcode
== 0xf6
4226 && i
.tm
.extension_opcode
== 0x0)))
4229 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4231 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4232 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4234 i
.types
[1].bitfield
.byte
= 1;
4235 /* Ignore the suffix. */
4237 /* Convert to byte registers. */
4238 if (i
.types
[1].bitfield
.word
)
4240 else if (i
.types
[1].bitfield
.dword
)
4244 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4249 else if (flag_code
== CODE_64BIT
4250 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4251 && ((i
.types
[1].bitfield
.qword
4252 && i
.reg_operands
== 1
4253 && i
.imm_operands
== 1
4254 && i
.op
[0].imms
->X_op
== O_constant
4255 && ((i
.tm
.base_opcode
== 0xb8
4256 && i
.tm
.extension_opcode
== None
4257 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4258 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4259 && ((i
.tm
.base_opcode
== 0x24
4260 || i
.tm
.base_opcode
== 0xa8)
4261 || (i
.tm
.base_opcode
== 0x80
4262 && i
.tm
.extension_opcode
== 0x4)
4263 || ((i
.tm
.base_opcode
== 0xf6
4264 || (i
.tm
.base_opcode
| 1) == 0xc7)
4265 && i
.tm
.extension_opcode
== 0x0)))
4266 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4267 && i
.tm
.base_opcode
== 0x83
4268 && i
.tm
.extension_opcode
== 0x4)))
4269 || (i
.types
[0].bitfield
.qword
4270 && ((i
.reg_operands
== 2
4271 && i
.op
[0].regs
== i
.op
[1].regs
4272 && (i
.tm
.base_opcode
== 0x30
4273 || i
.tm
.base_opcode
== 0x28))
4274 || (i
.reg_operands
== 1
4276 && i
.tm
.base_opcode
== 0x30)))))
4279 andq $imm31, %r64 -> andl $imm31, %r32
4280 andq $imm7, %r64 -> andl $imm7, %r32
4281 testq $imm31, %r64 -> testl $imm31, %r32
4282 xorq %r64, %r64 -> xorl %r32, %r32
4283 subq %r64, %r64 -> subl %r32, %r32
4284 movq $imm31, %r64 -> movl $imm31, %r32
4285 movq $imm32, %r64 -> movl $imm32, %r32
4287 i
.tm
.opcode_modifier
.norex64
= 1;
4288 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4291 movq $imm31, %r64 -> movl $imm31, %r32
4292 movq $imm32, %r64 -> movl $imm32, %r32
4294 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4295 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4296 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4297 i
.types
[0].bitfield
.imm32
= 1;
4298 i
.types
[0].bitfield
.imm32s
= 0;
4299 i
.types
[0].bitfield
.imm64
= 0;
4300 i
.types
[1].bitfield
.dword
= 1;
4301 i
.types
[1].bitfield
.qword
= 0;
4302 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4305 movq $imm31, %r64 -> movl $imm31, %r32
4307 i
.tm
.base_opcode
= 0xb8;
4308 i
.tm
.extension_opcode
= None
;
4309 i
.tm
.opcode_modifier
.w
= 0;
4310 i
.tm
.opcode_modifier
.modrm
= 0;
4314 else if (optimize
> 1
4315 && !optimize_for_space
4316 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4317 && i
.reg_operands
== 2
4318 && i
.op
[0].regs
== i
.op
[1].regs
4319 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4320 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4321 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4324 andb %rN, %rN -> testb %rN, %rN
4325 andw %rN, %rN -> testw %rN, %rN
4326 andq %rN, %rN -> testq %rN, %rN
4327 orb %rN, %rN -> testb %rN, %rN
4328 orw %rN, %rN -> testw %rN, %rN
4329 orq %rN, %rN -> testq %rN, %rN
4331 and outside of 64-bit mode
4333 andl %rN, %rN -> testl %rN, %rN
4334 orl %rN, %rN -> testl %rN, %rN
4336 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4338 else if (i
.reg_operands
== 3
4339 && i
.op
[0].regs
== i
.op
[1].regs
4340 && !i
.types
[2].bitfield
.xmmword
4341 && (i
.tm
.opcode_modifier
.vex
4342 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4343 && i
.rounding
.type
== rc_none
4344 && is_evex_encoding (&i
.tm
)
4345 && (i
.vec_encoding
!= vex_encoding_evex
4346 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4347 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4348 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4349 && i
.types
[2].bitfield
.ymmword
))))
4350 && ((i
.tm
.base_opcode
== 0x55
4351 || i
.tm
.base_opcode
== 0x57
4352 || i
.tm
.base_opcode
== 0xdf
4353 || i
.tm
.base_opcode
== 0xef
4354 || i
.tm
.base_opcode
== 0xf8
4355 || i
.tm
.base_opcode
== 0xf9
4356 || i
.tm
.base_opcode
== 0xfa
4357 || i
.tm
.base_opcode
== 0xfb
4358 || i
.tm
.base_opcode
== 0x42
4359 || i
.tm
.base_opcode
== 0x47)
4360 && i
.tm
.extension_opcode
== None
))
4363 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4365 EVEX VOP %zmmM, %zmmM, %zmmN
4366 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4367 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4368 EVEX VOP %ymmM, %ymmM, %ymmN
4369 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4370 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4371 VEX VOP %ymmM, %ymmM, %ymmN
4372 -> VEX VOP %xmmM, %xmmM, %xmmN
4373 VOP, one of vpandn and vpxor:
4374 VEX VOP %ymmM, %ymmM, %ymmN
4375 -> VEX VOP %xmmM, %xmmM, %xmmN
4376 VOP, one of vpandnd and vpandnq:
4377 EVEX VOP %zmmM, %zmmM, %zmmN
4378 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4379 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4380 EVEX VOP %ymmM, %ymmM, %ymmN
4381 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4382 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4383 VOP, one of vpxord and vpxorq:
4384 EVEX VOP %zmmM, %zmmM, %zmmN
4385 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4386 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4387 EVEX VOP %ymmM, %ymmM, %ymmN
4388 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4389 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4390 VOP, one of kxord and kxorq:
4391 VEX VOP %kM, %kM, %kN
4392 -> VEX kxorw %kM, %kM, %kN
4393 VOP, one of kandnd and kandnq:
4394 VEX VOP %kM, %kM, %kN
4395 -> VEX kandnw %kM, %kM, %kN
4397 if (is_evex_encoding (&i
.tm
))
4399 if (i
.vec_encoding
!= vex_encoding_evex
)
4401 i
.tm
.opcode_modifier
.vex
= VEX128
;
4402 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4403 i
.tm
.opcode_modifier
.evex
= 0;
4405 else if (optimize
> 1)
4406 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4410 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4412 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4413 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4416 i
.tm
.opcode_modifier
.vex
= VEX128
;
4418 if (i
.tm
.opcode_modifier
.vex
)
4419 for (j
= 0; j
< 3; j
++)
4421 i
.types
[j
].bitfield
.xmmword
= 1;
4422 i
.types
[j
].bitfield
.ymmword
= 0;
4425 else if (i
.vec_encoding
!= vex_encoding_evex
4426 && !i
.types
[0].bitfield
.zmmword
4427 && !i
.types
[1].bitfield
.zmmword
4429 && !i
.broadcast
.type
4430 && is_evex_encoding (&i
.tm
)
4431 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4432 || (i
.tm
.base_opcode
& ~4) == 0xdb
4433 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4434 && i
.tm
.extension_opcode
== None
)
4437 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4438 vmovdqu32 and vmovdqu64:
4439 EVEX VOP %xmmM, %xmmN
4440 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4441 EVEX VOP %ymmM, %ymmN
4442 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4444 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4446 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4448 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4450 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4451 VOP, one of vpand, vpandn, vpor, vpxor:
4452 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4453 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4454 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4455 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4456 EVEX VOP{d,q} mem, %xmmM, %xmmN
4457 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4458 EVEX VOP{d,q} mem, %ymmM, %ymmN
4459 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4461 for (j
= 0; j
< i
.operands
; j
++)
4462 if (operand_type_check (i
.types
[j
], disp
)
4463 && i
.op
[j
].disps
->X_op
== O_constant
)
4465 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4466 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4467 bytes, we choose EVEX Disp8 over VEX Disp32. */
4468 int evex_disp8
, vex_disp8
;
4469 unsigned int memshift
= i
.memshift
;
4470 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4472 evex_disp8
= fits_in_disp8 (n
);
4474 vex_disp8
= fits_in_disp8 (n
);
4475 if (evex_disp8
!= vex_disp8
)
4477 i
.memshift
= memshift
;
4481 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4484 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4485 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4486 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4487 i
.tm
.opcode_modifier
.vex
4488 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4489 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4490 /* VPAND, VPOR, and VPXOR are commutative. */
4491 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4492 i
.tm
.opcode_modifier
.commutative
= 1;
4493 i
.tm
.opcode_modifier
.evex
= 0;
4494 i
.tm
.opcode_modifier
.masking
= 0;
4495 i
.tm
.opcode_modifier
.broadcast
= 0;
4496 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4499 i
.types
[j
].bitfield
.disp8
4500 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4504 /* Return non-zero for load instruction. */
4510 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4511 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4515 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4516 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4517 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4518 if (i
.tm
.opcode_modifier
.anysize
)
4522 if (strcmp (i
.tm
.name
, "pop") == 0)
4526 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4529 if (i
.tm
.base_opcode
== 0x9d
4530 || i
.tm
.base_opcode
== 0x61)
4533 /* movs, cmps, lods, scas. */
4534 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4538 if (base_opcode
== 0x6f
4539 || i
.tm
.base_opcode
== 0xd7)
4541 /* NB: For AMD-specific insns with implicit memory operands,
4542 they're intentionally not covered. */
4545 /* No memory operand. */
4546 if (!i
.mem_operands
)
4552 if (i
.tm
.base_opcode
== 0xae
4553 && i
.tm
.opcode_modifier
.vex
4554 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4555 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4556 && i
.tm
.extension_opcode
== 2)
4559 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4561 /* test, not, neg, mul, imul, div, idiv. */
4562 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4563 && i
.tm
.extension_opcode
!= 1)
4567 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4570 /* add, or, adc, sbb, and, sub, xor, cmp. */
4571 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4574 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4575 if ((base_opcode
== 0xc1
4576 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4577 && i
.tm
.extension_opcode
!= 6)
4580 /* Check for x87 instructions. */
4581 if (base_opcode
>= 0xd8 && base_opcode
<= 0xdf)
4583 /* Skip fst, fstp, fstenv, fstcw. */
4584 if (i
.tm
.base_opcode
== 0xd9
4585 && (i
.tm
.extension_opcode
== 2
4586 || i
.tm
.extension_opcode
== 3
4587 || i
.tm
.extension_opcode
== 6
4588 || i
.tm
.extension_opcode
== 7))
4591 /* Skip fisttp, fist, fistp, fstp. */
4592 if (i
.tm
.base_opcode
== 0xdb
4593 && (i
.tm
.extension_opcode
== 1
4594 || i
.tm
.extension_opcode
== 2
4595 || i
.tm
.extension_opcode
== 3
4596 || i
.tm
.extension_opcode
== 7))
4599 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4600 if (i
.tm
.base_opcode
== 0xdd
4601 && (i
.tm
.extension_opcode
== 1
4602 || i
.tm
.extension_opcode
== 2
4603 || i
.tm
.extension_opcode
== 3
4604 || i
.tm
.extension_opcode
== 6
4605 || i
.tm
.extension_opcode
== 7))
4608 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4609 if (i
.tm
.base_opcode
== 0xdf
4610 && (i
.tm
.extension_opcode
== 1
4611 || i
.tm
.extension_opcode
== 2
4612 || i
.tm
.extension_opcode
== 3
4613 || i
.tm
.extension_opcode
== 6
4614 || i
.tm
.extension_opcode
== 7))
4620 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4622 /* bt, bts, btr, btc. */
4623 if (i
.tm
.base_opcode
== 0xba
4624 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4627 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4628 if (i
.tm
.base_opcode
== 0xc7
4629 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4630 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4631 || i
.tm
.extension_opcode
== 6))
4634 /* fxrstor, ldmxcsr, xrstor. */
4635 if (i
.tm
.base_opcode
== 0xae
4636 && (i
.tm
.extension_opcode
== 1
4637 || i
.tm
.extension_opcode
== 2
4638 || i
.tm
.extension_opcode
== 5))
4641 /* lgdt, lidt, lmsw. */
4642 if (i
.tm
.base_opcode
== 0x01
4643 && (i
.tm
.extension_opcode
== 2
4644 || i
.tm
.extension_opcode
== 3
4645 || i
.tm
.extension_opcode
== 6))
4649 dest
= i
.operands
- 1;
4651 /* Check fake imm8 operand and 3 source operands. */
4652 if ((i
.tm
.opcode_modifier
.immext
4653 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4654 && i
.types
[dest
].bitfield
.imm8
)
4657 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4658 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4659 && (base_opcode
== 0x1
4660 || base_opcode
== 0x9
4661 || base_opcode
== 0x11
4662 || base_opcode
== 0x19
4663 || base_opcode
== 0x21
4664 || base_opcode
== 0x29
4665 || base_opcode
== 0x31
4666 || base_opcode
== 0x39
4667 || (base_opcode
| 2) == 0x87))
4671 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4672 && base_opcode
== 0xc1)
4675 /* Check for load instruction. */
4676 return (i
.types
[dest
].bitfield
.class != ClassNone
4677 || i
.types
[dest
].bitfield
.instance
== Accum
);
4680 /* Output lfence, 0xfaee8, after instruction. */
4683 insert_lfence_after (void)
4685 if (lfence_after_load
&& load_insn_p ())
4687 /* There are also two REP string instructions that require
4688 special treatment. Specifically, the compare string (CMPS)
4689 and scan string (SCAS) instructions set EFLAGS in a manner
4690 that depends on the data being compared/scanned. When used
4691 with a REP prefix, the number of iterations may therefore
4692 vary depending on this data. If the data is a program secret
4693 chosen by the adversary using an LVI method,
4694 then this data-dependent behavior may leak some aspect
4696 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4697 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4698 && i
.prefix
[REP_PREFIX
])
4700 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4703 char *p
= frag_more (3);
4710 /* Output lfence, 0xfaee8, before instruction. */
4713 insert_lfence_before (void)
4717 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4720 if (i
.tm
.base_opcode
== 0xff
4721 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4723 /* Insert lfence before indirect branch if needed. */
4725 if (lfence_before_indirect_branch
== lfence_branch_none
)
4728 if (i
.operands
!= 1)
4731 if (i
.reg_operands
== 1)
4733 /* Indirect branch via register. Don't insert lfence with
4734 -mlfence-after-load=yes. */
4735 if (lfence_after_load
4736 || lfence_before_indirect_branch
== lfence_branch_memory
)
4739 else if (i
.mem_operands
== 1
4740 && lfence_before_indirect_branch
!= lfence_branch_register
)
4742 as_warn (_("indirect `%s` with memory operand should be avoided"),
4749 if (last_insn
.kind
!= last_insn_other
4750 && last_insn
.seg
== now_seg
)
4752 as_warn_where (last_insn
.file
, last_insn
.line
,
4753 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4754 last_insn
.name
, i
.tm
.name
);
4765 /* Output or/not/shl and lfence before near ret. */
4766 if (lfence_before_ret
!= lfence_before_ret_none
4767 && (i
.tm
.base_opcode
== 0xc2
4768 || i
.tm
.base_opcode
== 0xc3))
4770 if (last_insn
.kind
!= last_insn_other
4771 && last_insn
.seg
== now_seg
)
4773 as_warn_where (last_insn
.file
, last_insn
.line
,
4774 _("`%s` skips -mlfence-before-ret on `%s`"),
4775 last_insn
.name
, i
.tm
.name
);
4779 /* Near ret ingore operand size override under CPU64. */
4780 char prefix
= flag_code
== CODE_64BIT
4782 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4784 if (lfence_before_ret
== lfence_before_ret_not
)
4786 /* not: 0xf71424, may add prefix
4787 for operand size override or 64-bit code. */
4788 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4802 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4805 if (lfence_before_ret
== lfence_before_ret_or
)
4807 /* or: 0x830c2400, may add prefix
4808 for operand size override or 64-bit code. */
4814 /* shl: 0xc1242400, may add prefix
4815 for operand size override or 64-bit code. */
4830 /* This is the guts of the machine-dependent assembler. LINE points to a
4831 machine dependent instruction. This function is supposed to emit
4832 the frags/bytes it assembles to. */
4835 md_assemble (char *line
)
4838 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4839 const insn_template
*t
;
4841 /* Initialize globals. */
4842 memset (&i
, '\0', sizeof (i
));
4843 i
.rounding
.type
= rc_none
;
4844 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4845 i
.reloc
[j
] = NO_RELOC
;
4846 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4847 memset (im_expressions
, '\0', sizeof (im_expressions
));
4848 save_stack_p
= save_stack
;
4850 /* First parse an instruction mnemonic & call i386_operand for the operands.
4851 We assume that the scrubber has arranged it so that line[0] is the valid
4852 start of a (possibly prefixed) mnemonic. */
4854 line
= parse_insn (line
, mnemonic
);
4857 mnem_suffix
= i
.suffix
;
4859 line
= parse_operands (line
, mnemonic
);
4861 xfree (i
.memop1_string
);
4862 i
.memop1_string
= NULL
;
4866 /* Now we've parsed the mnemonic into a set of templates, and have the
4867 operands at hand. */
4869 /* All Intel opcodes have reversed operands except for "bound", "enter",
4870 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4871 "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
4872 and "call" instructions with 2 immediate operands so that the immediate
4873 segment precedes the offset consistently in Intel and AT&T modes. */
4876 && (strcmp (mnemonic
, "bound") != 0)
4877 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4878 && !startswith (mnemonic
, "monitor")
4879 && !startswith (mnemonic
, "mwait")
4880 && (strcmp (mnemonic
, "pvalidate") != 0)
4881 && !startswith (mnemonic
, "rmp")
4882 && (strcmp (mnemonic
, "tpause") != 0)
4883 && (strcmp (mnemonic
, "umwait") != 0)
4884 && !(operand_type_check (i
.types
[0], imm
)
4885 && operand_type_check (i
.types
[1], imm
)))
4888 /* The order of the immediates should be reversed
4889 for 2 immediates extrq and insertq instructions */
4890 if (i
.imm_operands
== 2
4891 && (strcmp (mnemonic
, "extrq") == 0
4892 || strcmp (mnemonic
, "insertq") == 0))
4893 swap_2_operands (0, 1);
4898 if (i
.disp_operands
&& !want_disp32 (current_templates
->start
))
4900 for (j
= 0; j
< i
.operands
; ++j
)
4902 const expressionS
*exp
= i
.op
[j
].disps
;
4904 if (!operand_type_check (i
.types
[j
], disp
))
4907 if (exp
->X_op
!= O_constant
)
4910 /* Since displacement is signed extended to 64bit, don't allow
4911 disp32 and turn off disp32s if they are out of range. */
4912 i
.types
[j
].bitfield
.disp32
= 0;
4913 if (fits_in_signed_long (exp
->X_add_number
))
4916 i
.types
[j
].bitfield
.disp32s
= 0;
4917 if (i
.types
[j
].bitfield
.baseindex
)
4919 as_bad (_("0x%" BFD_VMA_FMT
"x out of range of signed 32bit displacement"),
4926 /* Don't optimize displacement for movabs since it only takes 64bit
4929 && i
.disp_encoding
!= disp_encoding_32bit
4930 && (flag_code
!= CODE_64BIT
4931 || strcmp (mnemonic
, "movabs") != 0))
4934 /* Next, we find a template that matches the given insn,
4935 making sure the overlap of the given operands types is consistent
4936 with the template operand types. */
4938 if (!(t
= match_template (mnem_suffix
)))
4941 if (sse_check
!= check_none
4942 && !i
.tm
.opcode_modifier
.noavx
4943 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4944 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4945 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4946 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4947 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4948 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4949 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4950 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4951 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4952 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4953 || i
.tm
.cpu_flags
.bitfield
.cpusha
4954 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4956 (sse_check
== check_warning
4958 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4961 if (i
.tm
.opcode_modifier
.fwait
)
4962 if (!add_prefix (FWAIT_OPCODE
))
4965 /* Check if REP prefix is OK. */
4966 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4968 as_bad (_("invalid instruction `%s' after `%s'"),
4969 i
.tm
.name
, i
.rep_prefix
);
4973 /* Check for lock without a lockable instruction. Destination operand
4974 must be memory unless it is xchg (0x86). */
4975 if (i
.prefix
[LOCK_PREFIX
]
4976 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4977 || i
.mem_operands
== 0
4978 || (i
.tm
.base_opcode
!= 0x86
4979 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4981 as_bad (_("expecting lockable instruction after `lock'"));
4985 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4986 if (i
.prefix
[DATA_PREFIX
]
4987 && (is_any_vex_encoding (&i
.tm
)
4988 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4989 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4991 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4995 /* Check if HLE prefix is OK. */
4996 if (i
.hle_prefix
&& !check_hle ())
4999 /* Check BND prefix. */
5000 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5001 as_bad (_("expecting valid branch instruction after `bnd'"));
5003 /* Check NOTRACK prefix. */
5004 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5005 as_bad (_("expecting indirect branch instruction after `notrack'"));
5007 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5009 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5010 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5011 else if (flag_code
!= CODE_16BIT
5012 ? i
.prefix
[ADDR_PREFIX
]
5013 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5014 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5017 /* Insert BND prefix. */
5018 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5020 if (!i
.prefix
[BND_PREFIX
])
5021 add_prefix (BND_PREFIX_OPCODE
);
5022 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5024 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5025 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5029 /* Check string instruction segment overrides. */
5030 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5032 gas_assert (i
.mem_operands
);
5033 if (!check_string ())
5035 i
.disp_operands
= 0;
5038 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5039 optimize_encoding ();
5041 if (!process_suffix ())
5044 /* Update operand types and check extended states. */
5045 for (j
= 0; j
< i
.operands
; j
++)
5047 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5048 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5053 i
.xstate
|= xstate_mmx
;
5056 i
.xstate
|= xstate_mask
;
5059 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5060 i
.xstate
|= xstate_tmm
;
5061 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5062 i
.xstate
|= xstate_zmm
;
5063 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5064 i
.xstate
|= xstate_ymm
;
5065 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5066 i
.xstate
|= xstate_xmm
;
5071 /* Make still unresolved immediate matches conform to size of immediate
5072 given in i.suffix. */
5073 if (!finalize_imm ())
5076 if (i
.types
[0].bitfield
.imm1
)
5077 i
.imm_operands
= 0; /* kludge for shift insns. */
5079 /* We only need to check those implicit registers for instructions
5080 with 3 operands or less. */
5081 if (i
.operands
<= 3)
5082 for (j
= 0; j
< i
.operands
; j
++)
5083 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
5084 && !i
.types
[j
].bitfield
.xmmword
)
5087 /* For insns with operands there are more diddles to do to the opcode. */
5090 if (!process_operands ())
5093 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5095 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5096 as_warn (_("translating to `%sp'"), i
.tm
.name
);
5099 if (is_any_vex_encoding (&i
.tm
))
5101 if (!cpu_arch_flags
.bitfield
.cpui286
)
5103 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5108 /* Check for explicit REX prefix. */
5109 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5111 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
5115 if (i
.tm
.opcode_modifier
.vex
)
5116 build_vex_prefix (t
);
5118 build_evex_prefix ();
5120 /* The individual REX.RXBW bits got consumed. */
5121 i
.rex
&= REX_OPCODE
;
5124 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
5125 instructions may define INT_OPCODE as well, so avoid this corner
5126 case for those instructions that use MODRM. */
5127 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
5128 && i
.tm
.base_opcode
== INT_OPCODE
5129 && !i
.tm
.opcode_modifier
.modrm
5130 && i
.op
[0].imms
->X_add_number
== 3)
5132 i
.tm
.base_opcode
= INT3_OPCODE
;
5136 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5137 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5138 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5139 && i
.op
[0].disps
->X_op
== O_constant
)
5141 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5142 the absolute address given by the constant. Since ix86 jumps and
5143 calls are pc relative, we need to generate a reloc. */
5144 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5145 i
.op
[0].disps
->X_op
= O_symbol
;
5148 /* For 8 bit registers we need an empty rex prefix. Also if the
5149 instruction already has a prefix, we need to convert old
5150 registers to new ones. */
5152 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5153 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5154 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5155 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5156 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5157 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5162 i
.rex
|= REX_OPCODE
;
5163 for (x
= 0; x
< 2; x
++)
5165 /* Look for 8 bit operand that uses old registers. */
5166 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5167 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5169 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5170 /* In case it is "hi" register, give up. */
5171 if (i
.op
[x
].regs
->reg_num
> 3)
5172 as_bad (_("can't encode register '%s%s' in an "
5173 "instruction requiring REX prefix."),
5174 register_prefix
, i
.op
[x
].regs
->reg_name
);
5176 /* Otherwise it is equivalent to the extended register.
5177 Since the encoding doesn't change this is merely
5178 cosmetic cleanup for debug output. */
5180 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5185 if (i
.rex
== 0 && i
.rex_encoding
)
5187 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5188 that uses legacy register. If it is "hi" register, don't add
5189 the REX_OPCODE byte. */
5191 for (x
= 0; x
< 2; x
++)
5192 if (i
.types
[x
].bitfield
.class == Reg
5193 && i
.types
[x
].bitfield
.byte
5194 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5195 && i
.op
[x
].regs
->reg_num
> 3)
5197 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5198 i
.rex_encoding
= false;
5207 add_prefix (REX_OPCODE
| i
.rex
);
5209 insert_lfence_before ();
5211 /* We are ready to output the insn. */
5214 insert_lfence_after ();
5216 last_insn
.seg
= now_seg
;
5218 if (i
.tm
.opcode_modifier
.isprefix
)
5220 last_insn
.kind
= last_insn_prefix
;
5221 last_insn
.name
= i
.tm
.name
;
5222 last_insn
.file
= as_where (&last_insn
.line
);
5225 last_insn
.kind
= last_insn_other
;
5229 parse_insn (char *line
, char *mnemonic
)
5232 char *token_start
= l
;
5235 const insn_template
*t
;
5241 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5246 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5248 as_bad (_("no such instruction: `%s'"), token_start
);
5253 if (!is_space_char (*l
)
5254 && *l
!= END_OF_INSN
5256 || (*l
!= PREFIX_SEPARATOR
5259 as_bad (_("invalid character %s in mnemonic"),
5260 output_invalid (*l
));
5263 if (token_start
== l
)
5265 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5266 as_bad (_("expecting prefix; got nothing"));
5268 as_bad (_("expecting mnemonic; got nothing"));
5272 /* Look up instruction (or prefix) via hash table. */
5273 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5275 if (*l
!= END_OF_INSN
5276 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5277 && current_templates
5278 && current_templates
->start
->opcode_modifier
.isprefix
)
5280 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5282 as_bad ((flag_code
!= CODE_64BIT
5283 ? _("`%s' is only supported in 64-bit mode")
5284 : _("`%s' is not supported in 64-bit mode")),
5285 current_templates
->start
->name
);
5288 /* If we are in 16-bit mode, do not allow addr16 or data16.
5289 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5290 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5291 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5292 && flag_code
!= CODE_64BIT
5293 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5294 ^ (flag_code
== CODE_16BIT
)))
5296 as_bad (_("redundant %s prefix"),
5297 current_templates
->start
->name
);
5301 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5303 /* Handle pseudo prefixes. */
5304 switch (current_templates
->start
->extension_opcode
)
5308 i
.disp_encoding
= disp_encoding_8bit
;
5312 i
.disp_encoding
= disp_encoding_16bit
;
5316 i
.disp_encoding
= disp_encoding_32bit
;
5320 i
.dir_encoding
= dir_encoding_load
;
5324 i
.dir_encoding
= dir_encoding_store
;
5328 i
.vec_encoding
= vex_encoding_vex
;
5332 i
.vec_encoding
= vex_encoding_vex3
;
5336 i
.vec_encoding
= vex_encoding_evex
;
5340 i
.rex_encoding
= true;
5342 case Prefix_NoOptimize
:
5344 i
.no_optimize
= true;
5352 /* Add prefix, checking for repeated prefixes. */
5353 switch (add_prefix (current_templates
->start
->base_opcode
))
5358 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5359 i
.notrack_prefix
= current_templates
->start
->name
;
5362 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5363 i
.hle_prefix
= current_templates
->start
->name
;
5364 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5365 i
.bnd_prefix
= current_templates
->start
->name
;
5367 i
.rep_prefix
= current_templates
->start
->name
;
5373 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5380 if (!current_templates
)
5382 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5383 Check if we should swap operand or force 32bit displacement in
5385 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5386 i
.dir_encoding
= dir_encoding_swap
;
5387 else if (mnem_p
- 3 == dot_p
5390 i
.disp_encoding
= disp_encoding_8bit
;
5391 else if (mnem_p
- 4 == dot_p
5395 i
.disp_encoding
= disp_encoding_32bit
;
5400 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5403 if (!current_templates
)
5406 if (mnem_p
> mnemonic
)
5408 /* See if we can get a match by trimming off a suffix. */
5411 case WORD_MNEM_SUFFIX
:
5412 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5413 i
.suffix
= SHORT_MNEM_SUFFIX
;
5416 case BYTE_MNEM_SUFFIX
:
5417 case QWORD_MNEM_SUFFIX
:
5418 i
.suffix
= mnem_p
[-1];
5421 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5423 case SHORT_MNEM_SUFFIX
:
5424 case LONG_MNEM_SUFFIX
:
5427 i
.suffix
= mnem_p
[-1];
5430 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5438 if (intel_float_operand (mnemonic
) == 1)
5439 i
.suffix
= SHORT_MNEM_SUFFIX
;
5441 i
.suffix
= LONG_MNEM_SUFFIX
;
5444 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5450 if (!current_templates
)
5452 as_bad (_("no such instruction: `%s'"), token_start
);
5457 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5458 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5460 /* Check for a branch hint. We allow ",pt" and ",pn" for
5461 predict taken and predict not taken respectively.
5462 I'm not sure that branch hints actually do anything on loop
5463 and jcxz insns (JumpByte) for current Pentium4 chips. They
5464 may work in the future and it doesn't hurt to accept them
5466 if (l
[0] == ',' && l
[1] == 'p')
5470 if (!add_prefix (DS_PREFIX_OPCODE
))
5474 else if (l
[2] == 'n')
5476 if (!add_prefix (CS_PREFIX_OPCODE
))
5482 /* Any other comma loses. */
5485 as_bad (_("invalid character %s in mnemonic"),
5486 output_invalid (*l
));
5490 /* Check if instruction is supported on specified architecture. */
5492 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5494 supported
|= cpu_flags_match (t
);
5495 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5497 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5498 as_warn (_("use .code16 to ensure correct addressing mode"));
5504 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5505 as_bad (flag_code
== CODE_64BIT
5506 ? _("`%s' is not supported in 64-bit mode")
5507 : _("`%s' is only supported in 64-bit mode"),
5508 current_templates
->start
->name
);
5510 as_bad (_("`%s' is not supported on `%s%s'"),
5511 current_templates
->start
->name
,
5512 cpu_arch_name
? cpu_arch_name
: default_arch
,
5513 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5519 parse_operands (char *l
, const char *mnemonic
)
5523 /* 1 if operand is pending after ','. */
5524 unsigned int expecting_operand
= 0;
5526 while (*l
!= END_OF_INSN
)
5528 /* Non-zero if operand parens not balanced. */
5529 unsigned int paren_not_balanced
= 0;
5530 /* True if inside double quotes. */
5531 bool in_quotes
= false;
5533 /* Skip optional white space before operand. */
5534 if (is_space_char (*l
))
5536 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5538 as_bad (_("invalid character %s before operand %d"),
5539 output_invalid (*l
),
5543 token_start
= l
; /* After white space. */
5544 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5546 if (*l
== END_OF_INSN
)
5550 as_bad (_("unbalanced double quotes in operand %d."),
5554 if (paren_not_balanced
)
5556 know (!intel_syntax
);
5557 as_bad (_("unbalanced parenthesis in operand %d."),
5562 break; /* we are done */
5564 else if (*l
== '\\' && l
[1] == '"')
5567 in_quotes
= !in_quotes
;
5568 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5570 as_bad (_("invalid character %s in operand %d"),
5571 output_invalid (*l
),
5575 if (!intel_syntax
&& !in_quotes
)
5578 ++paren_not_balanced
;
5580 --paren_not_balanced
;
5584 if (l
!= token_start
)
5585 { /* Yes, we've read in another operand. */
5586 unsigned int operand_ok
;
5587 this_operand
= i
.operands
++;
5588 if (i
.operands
> MAX_OPERANDS
)
5590 as_bad (_("spurious operands; (%d operands/instruction max)"),
5594 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5595 /* Now parse operand adding info to 'i' as we go along. */
5596 END_STRING_AND_SAVE (l
);
5598 if (i
.mem_operands
> 1)
5600 as_bad (_("too many memory references for `%s'"),
5607 i386_intel_operand (token_start
,
5608 intel_float_operand (mnemonic
));
5610 operand_ok
= i386_att_operand (token_start
);
5612 RESTORE_END_STRING (l
);
5618 if (expecting_operand
)
5620 expecting_operand_after_comma
:
5621 as_bad (_("expecting operand after ','; got nothing"));
5626 as_bad (_("expecting operand before ','; got nothing"));
5631 /* Now *l must be either ',' or END_OF_INSN. */
5634 if (*++l
== END_OF_INSN
)
5636 /* Just skip it, if it's \n complain. */
5637 goto expecting_operand_after_comma
;
5639 expecting_operand
= 1;
5646 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5648 union i386_op temp_op
;
5649 i386_operand_type temp_type
;
5650 unsigned int temp_flags
;
5651 enum bfd_reloc_code_real temp_reloc
;
5653 temp_type
= i
.types
[xchg2
];
5654 i
.types
[xchg2
] = i
.types
[xchg1
];
5655 i
.types
[xchg1
] = temp_type
;
5657 temp_flags
= i
.flags
[xchg2
];
5658 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5659 i
.flags
[xchg1
] = temp_flags
;
5661 temp_op
= i
.op
[xchg2
];
5662 i
.op
[xchg2
] = i
.op
[xchg1
];
5663 i
.op
[xchg1
] = temp_op
;
5665 temp_reloc
= i
.reloc
[xchg2
];
5666 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5667 i
.reloc
[xchg1
] = temp_reloc
;
5671 if (i
.mask
.operand
== xchg1
)
5672 i
.mask
.operand
= xchg2
;
5673 else if (i
.mask
.operand
== xchg2
)
5674 i
.mask
.operand
= xchg1
;
5676 if (i
.broadcast
.type
)
5678 if (i
.broadcast
.operand
== xchg1
)
5679 i
.broadcast
.operand
= xchg2
;
5680 else if (i
.broadcast
.operand
== xchg2
)
5681 i
.broadcast
.operand
= xchg1
;
5683 if (i
.rounding
.type
!= rc_none
)
5685 if (i
.rounding
.operand
== xchg1
)
5686 i
.rounding
.operand
= xchg2
;
5687 else if (i
.rounding
.operand
== xchg2
)
5688 i
.rounding
.operand
= xchg1
;
5693 swap_operands (void)
5699 swap_2_operands (1, i
.operands
- 2);
5703 swap_2_operands (0, i
.operands
- 1);
5709 if (i
.mem_operands
== 2)
5711 const reg_entry
*temp_seg
;
5712 temp_seg
= i
.seg
[0];
5713 i
.seg
[0] = i
.seg
[1];
5714 i
.seg
[1] = temp_seg
;
5718 /* Try to ensure constant immediates are represented in the smallest
5723 char guess_suffix
= 0;
5727 guess_suffix
= i
.suffix
;
5728 else if (i
.reg_operands
)
5730 /* Figure out a suffix from the last register operand specified.
5731 We can't do this properly yet, i.e. excluding special register
5732 instances, but the following works for instructions with
5733 immediates. In any case, we can't set i.suffix yet. */
5734 for (op
= i
.operands
; --op
>= 0;)
5735 if (i
.types
[op
].bitfield
.class != Reg
)
5737 else if (i
.types
[op
].bitfield
.byte
)
5739 guess_suffix
= BYTE_MNEM_SUFFIX
;
5742 else if (i
.types
[op
].bitfield
.word
)
5744 guess_suffix
= WORD_MNEM_SUFFIX
;
5747 else if (i
.types
[op
].bitfield
.dword
)
5749 guess_suffix
= LONG_MNEM_SUFFIX
;
5752 else if (i
.types
[op
].bitfield
.qword
)
5754 guess_suffix
= QWORD_MNEM_SUFFIX
;
5758 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5759 guess_suffix
= WORD_MNEM_SUFFIX
;
5761 for (op
= i
.operands
; --op
>= 0;)
5762 if (operand_type_check (i
.types
[op
], imm
))
5764 switch (i
.op
[op
].imms
->X_op
)
5767 /* If a suffix is given, this operand may be shortened. */
5768 switch (guess_suffix
)
5770 case LONG_MNEM_SUFFIX
:
5771 i
.types
[op
].bitfield
.imm32
= 1;
5772 i
.types
[op
].bitfield
.imm64
= 1;
5774 case WORD_MNEM_SUFFIX
:
5775 i
.types
[op
].bitfield
.imm16
= 1;
5776 i
.types
[op
].bitfield
.imm32
= 1;
5777 i
.types
[op
].bitfield
.imm32s
= 1;
5778 i
.types
[op
].bitfield
.imm64
= 1;
5780 case BYTE_MNEM_SUFFIX
:
5781 i
.types
[op
].bitfield
.imm8
= 1;
5782 i
.types
[op
].bitfield
.imm8s
= 1;
5783 i
.types
[op
].bitfield
.imm16
= 1;
5784 i
.types
[op
].bitfield
.imm32
= 1;
5785 i
.types
[op
].bitfield
.imm32s
= 1;
5786 i
.types
[op
].bitfield
.imm64
= 1;
5790 /* If this operand is at most 16 bits, convert it
5791 to a signed 16 bit number before trying to see
5792 whether it will fit in an even smaller size.
5793 This allows a 16-bit operand such as $0xffe0 to
5794 be recognised as within Imm8S range. */
5795 if ((i
.types
[op
].bitfield
.imm16
)
5796 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
5798 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5799 ^ 0x8000) - 0x8000);
5802 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5803 if ((i
.types
[op
].bitfield
.imm32
)
5804 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
5806 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5807 ^ ((offsetT
) 1 << 31))
5808 - ((offsetT
) 1 << 31));
5812 = operand_type_or (i
.types
[op
],
5813 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5815 /* We must avoid matching of Imm32 templates when 64bit
5816 only immediate is available. */
5817 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5818 i
.types
[op
].bitfield
.imm32
= 0;
5825 /* Symbols and expressions. */
5827 /* Convert symbolic operand to proper sizes for matching, but don't
5828 prevent matching a set of insns that only supports sizes other
5829 than those matching the insn suffix. */
5831 i386_operand_type mask
, allowed
;
5832 const insn_template
*t
= current_templates
->start
;
5834 operand_type_set (&mask
, 0);
5835 allowed
= t
->operand_types
[op
];
5837 while (++t
< current_templates
->end
)
5839 allowed
= operand_type_and (allowed
, anyimm
);
5840 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5842 switch (guess_suffix
)
5844 case QWORD_MNEM_SUFFIX
:
5845 mask
.bitfield
.imm64
= 1;
5846 mask
.bitfield
.imm32s
= 1;
5848 case LONG_MNEM_SUFFIX
:
5849 mask
.bitfield
.imm32
= 1;
5851 case WORD_MNEM_SUFFIX
:
5852 mask
.bitfield
.imm16
= 1;
5854 case BYTE_MNEM_SUFFIX
:
5855 mask
.bitfield
.imm8
= 1;
5860 allowed
= operand_type_and (mask
, allowed
);
5861 if (!operand_type_all_zero (&allowed
))
5862 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5869 /* Try to use the smallest displacement type too. */
5871 optimize_disp (void)
5875 for (op
= i
.operands
; --op
>= 0;)
5876 if (operand_type_check (i
.types
[op
], disp
))
5878 if (i
.op
[op
].disps
->X_op
== O_constant
)
5880 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5882 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5884 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
5885 i
.op
[op
].disps
= NULL
;
5890 if (i
.types
[op
].bitfield
.disp16
5891 && fits_in_unsigned_word (op_disp
))
5893 /* If this operand is at most 16 bits, convert
5894 to a signed 16 bit number and don't use 64bit
5896 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
5897 i
.types
[op
].bitfield
.disp64
= 0;
5901 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5902 if ((i
.types
[op
].bitfield
.disp32
5903 || (flag_code
== CODE_64BIT
5904 && want_disp32 (current_templates
->start
)))
5905 && fits_in_unsigned_long (op_disp
))
5907 /* If this operand is at most 32 bits, convert
5908 to a signed 32 bit number and don't use 64bit
5910 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5911 i
.types
[op
].bitfield
.disp64
= 0;
5912 i
.types
[op
].bitfield
.disp32
= 1;
5915 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
5917 i
.types
[op
].bitfield
.disp64
= 0;
5918 i
.types
[op
].bitfield
.disp32s
= 1;
5921 if ((i
.types
[op
].bitfield
.disp32
5922 || i
.types
[op
].bitfield
.disp32s
5923 || i
.types
[op
].bitfield
.disp16
)
5924 && fits_in_disp8 (op_disp
))
5925 i
.types
[op
].bitfield
.disp8
= 1;
5927 i
.op
[op
].disps
->X_add_number
= op_disp
;
5929 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5930 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5932 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5933 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5934 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
5937 /* We only support 64bit displacement on constants. */
5938 i
.types
[op
].bitfield
.disp64
= 0;
5942 /* Return 1 if there is a match in broadcast bytes between operand
5943 GIVEN and instruction template T. */
5946 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5948 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5949 && i
.types
[given
].bitfield
.byte
)
5950 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5951 && i
.types
[given
].bitfield
.word
)
5952 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5953 && i
.types
[given
].bitfield
.dword
)
5954 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5955 && i
.types
[given
].bitfield
.qword
));
5958 /* Check if operands are valid for the instruction. */
5961 check_VecOperands (const insn_template
*t
)
5966 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5967 any one operand are implicity requiring AVX512VL support if the actual
5968 operand size is YMMword or XMMword. Since this function runs after
5969 template matching, there's no need to check for YMMword/XMMword in
5971 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5972 if (!cpu_flags_all_zero (&cpu
)
5973 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5974 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5976 for (op
= 0; op
< t
->operands
; ++op
)
5978 if (t
->operand_types
[op
].bitfield
.zmmword
5979 && (i
.types
[op
].bitfield
.ymmword
5980 || i
.types
[op
].bitfield
.xmmword
))
5982 i
.error
= unsupported
;
5988 /* Without VSIB byte, we can't have a vector register for index. */
5989 if (!t
->opcode_modifier
.sib
5991 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5992 || i
.index_reg
->reg_type
.bitfield
.ymmword
5993 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5995 i
.error
= unsupported_vector_index_register
;
5999 /* Check if default mask is allowed. */
6000 if (t
->opcode_modifier
.nodefmask
6001 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6003 i
.error
= no_default_mask
;
6007 /* For VSIB byte, we need a vector register for index, and all vector
6008 registers must be distinct. */
6009 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6012 || !((t
->opcode_modifier
.sib
== VECSIB128
6013 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6014 || (t
->opcode_modifier
.sib
== VECSIB256
6015 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6016 || (t
->opcode_modifier
.sib
== VECSIB512
6017 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6019 i
.error
= invalid_vsib_address
;
6023 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6024 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6026 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6027 gas_assert (i
.types
[0].bitfield
.xmmword
6028 || i
.types
[0].bitfield
.ymmword
);
6029 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6030 gas_assert (i
.types
[2].bitfield
.xmmword
6031 || i
.types
[2].bitfield
.ymmword
);
6032 if (operand_check
== check_none
)
6034 if (register_number (i
.op
[0].regs
)
6035 != register_number (i
.index_reg
)
6036 && register_number (i
.op
[2].regs
)
6037 != register_number (i
.index_reg
)
6038 && register_number (i
.op
[0].regs
)
6039 != register_number (i
.op
[2].regs
))
6041 if (operand_check
== check_error
)
6043 i
.error
= invalid_vector_register_set
;
6046 as_warn (_("mask, index, and destination registers should be distinct"));
6048 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6050 if (i
.types
[1].bitfield
.class == RegSIMD
6051 && (i
.types
[1].bitfield
.xmmword
6052 || i
.types
[1].bitfield
.ymmword
6053 || i
.types
[1].bitfield
.zmmword
)
6054 && (register_number (i
.op
[1].regs
)
6055 == register_number (i
.index_reg
)))
6057 if (operand_check
== check_error
)
6059 i
.error
= invalid_vector_register_set
;
6062 if (operand_check
!= check_none
)
6063 as_warn (_("index and destination registers should be distinct"));
6068 /* For AMX instructions with three tmmword operands, all tmmword operand must be
6070 if (t
->operand_types
[0].bitfield
.tmmword
6071 && i
.reg_operands
== 3)
6073 if (register_number (i
.op
[0].regs
)
6074 == register_number (i
.op
[1].regs
)
6075 || register_number (i
.op
[0].regs
)
6076 == register_number (i
.op
[2].regs
)
6077 || register_number (i
.op
[1].regs
)
6078 == register_number (i
.op
[2].regs
))
6080 i
.error
= invalid_tmm_register_set
;
6085 /* Check if broadcast is supported by the instruction and is applied
6086 to the memory operand. */
6087 if (i
.broadcast
.type
)
6089 i386_operand_type type
, overlap
;
6091 /* Check if specified broadcast is supported in this instruction,
6092 and its broadcast bytes match the memory operand. */
6093 op
= i
.broadcast
.operand
;
6094 if (!t
->opcode_modifier
.broadcast
6095 || !(i
.flags
[op
] & Operand_Mem
)
6096 || (!i
.types
[op
].bitfield
.unspecified
6097 && !match_broadcast_size (t
, op
)))
6100 i
.error
= unsupported_broadcast
;
6104 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6105 * i
.broadcast
.type
);
6106 operand_type_set (&type
, 0);
6107 switch (i
.broadcast
.bytes
)
6110 type
.bitfield
.word
= 1;
6113 type
.bitfield
.dword
= 1;
6116 type
.bitfield
.qword
= 1;
6119 type
.bitfield
.xmmword
= 1;
6122 type
.bitfield
.ymmword
= 1;
6125 type
.bitfield
.zmmword
= 1;
6131 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6132 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6133 && t
->operand_types
[op
].bitfield
.byte
6134 + t
->operand_types
[op
].bitfield
.word
6135 + t
->operand_types
[op
].bitfield
.dword
6136 + t
->operand_types
[op
].bitfield
.qword
> 1)
6138 overlap
.bitfield
.xmmword
= 0;
6139 overlap
.bitfield
.ymmword
= 0;
6140 overlap
.bitfield
.zmmword
= 0;
6142 if (operand_type_all_zero (&overlap
))
6145 if (t
->opcode_modifier
.checkregsize
)
6149 type
.bitfield
.baseindex
= 1;
6150 for (j
= 0; j
< i
.operands
; ++j
)
6153 && !operand_type_register_match(i
.types
[j
],
6154 t
->operand_types
[j
],
6156 t
->operand_types
[op
]))
6161 /* If broadcast is supported in this instruction, we need to check if
6162 operand of one-element size isn't specified without broadcast. */
6163 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6165 /* Find memory operand. */
6166 for (op
= 0; op
< i
.operands
; op
++)
6167 if (i
.flags
[op
] & Operand_Mem
)
6169 gas_assert (op
< i
.operands
);
6170 /* Check size of the memory operand. */
6171 if (match_broadcast_size (t
, op
))
6173 i
.error
= broadcast_needed
;
6178 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6180 /* Check if requested masking is supported. */
6183 switch (t
->opcode_modifier
.masking
)
6187 case MERGING_MASKING
:
6191 i
.error
= unsupported_masking
;
6195 case DYNAMIC_MASKING
:
6196 /* Memory destinations allow only merging masking. */
6197 if (i
.mask
.zeroing
&& i
.mem_operands
)
6199 /* Find memory operand. */
6200 for (op
= 0; op
< i
.operands
; op
++)
6201 if (i
.flags
[op
] & Operand_Mem
)
6203 gas_assert (op
< i
.operands
);
6204 if (op
== i
.operands
- 1)
6206 i
.error
= unsupported_masking
;
6216 /* Check if masking is applied to dest operand. */
6217 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6219 i
.error
= mask_not_on_destination
;
6224 if (i
.rounding
.type
!= rc_none
)
6226 if (!t
->opcode_modifier
.sae
6227 || (i
.rounding
.type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6229 i
.error
= unsupported_rc_sae
;
6232 /* If the instruction has several immediate operands and one of
6233 them is rounding, the rounding operand should be the last
6234 immediate operand. */
6235 if (i
.imm_operands
> 1
6236 && i
.rounding
.operand
!= i
.imm_operands
- 1)
6238 i
.error
= rc_sae_operand_not_last_imm
;
6243 /* Check the special Imm4 cases; must be the first operand. */
6244 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6246 if (i
.op
[0].imms
->X_op
!= O_constant
6247 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6253 /* Turn off Imm<N> so that update_imm won't complain. */
6254 operand_type_set (&i
.types
[0], 0);
6257 /* Check vector Disp8 operand. */
6258 if (t
->opcode_modifier
.disp8memshift
6259 && i
.disp_encoding
!= disp_encoding_32bit
)
6261 if (i
.broadcast
.type
)
6262 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6263 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6264 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6267 const i386_operand_type
*type
= NULL
;
6270 for (op
= 0; op
< i
.operands
; op
++)
6271 if (i
.flags
[op
] & Operand_Mem
)
6273 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6274 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6275 else if (t
->operand_types
[op
].bitfield
.xmmword
6276 + t
->operand_types
[op
].bitfield
.ymmword
6277 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6278 type
= &t
->operand_types
[op
];
6279 else if (!i
.types
[op
].bitfield
.unspecified
)
6280 type
= &i
.types
[op
];
6282 else if (i
.types
[op
].bitfield
.class == RegSIMD
6283 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6285 if (i
.types
[op
].bitfield
.zmmword
)
6287 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6289 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6295 if (type
->bitfield
.zmmword
)
6297 else if (type
->bitfield
.ymmword
)
6299 else if (type
->bitfield
.xmmword
)
6303 /* For the check in fits_in_disp8(). */
6304 if (i
.memshift
== 0)
6308 for (op
= 0; op
< i
.operands
; op
++)
6309 if (operand_type_check (i
.types
[op
], disp
)
6310 && i
.op
[op
].disps
->X_op
== O_constant
)
6312 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6314 i
.types
[op
].bitfield
.disp8
= 1;
6317 i
.types
[op
].bitfield
.disp8
= 0;
6326 /* Check if encoding requirements are met by the instruction. */
6329 VEX_check_encoding (const insn_template
*t
)
6331 if (i
.vec_encoding
== vex_encoding_error
)
6333 i
.error
= unsupported
;
6337 if (i
.vec_encoding
== vex_encoding_evex
)
6339 /* This instruction must be encoded with EVEX prefix. */
6340 if (!is_evex_encoding (t
))
6342 i
.error
= unsupported
;
6348 if (!t
->opcode_modifier
.vex
)
6350 /* This instruction template doesn't have VEX prefix. */
6351 if (i
.vec_encoding
!= vex_encoding_default
)
6353 i
.error
= unsupported
;
6362 static const insn_template
*
6363 match_template (char mnem_suffix
)
6365 /* Points to template once we've found it. */
6366 const insn_template
*t
;
6367 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6368 i386_operand_type overlap4
;
6369 unsigned int found_reverse_match
;
6370 i386_opcode_modifier suffix_check
;
6371 i386_operand_type operand_types
[MAX_OPERANDS
];
6372 int addr_prefix_disp
;
6373 unsigned int j
, size_match
, check_register
;
6374 enum i386_error specific_error
= 0;
6376 #if MAX_OPERANDS != 5
6377 # error "MAX_OPERANDS must be 5."
6380 found_reverse_match
= 0;
6381 addr_prefix_disp
= -1;
6383 /* Prepare for mnemonic suffix check. */
6384 memset (&suffix_check
, 0, sizeof (suffix_check
));
6385 switch (mnem_suffix
)
6387 case BYTE_MNEM_SUFFIX
:
6388 suffix_check
.no_bsuf
= 1;
6390 case WORD_MNEM_SUFFIX
:
6391 suffix_check
.no_wsuf
= 1;
6393 case SHORT_MNEM_SUFFIX
:
6394 suffix_check
.no_ssuf
= 1;
6396 case LONG_MNEM_SUFFIX
:
6397 suffix_check
.no_lsuf
= 1;
6399 case QWORD_MNEM_SUFFIX
:
6400 suffix_check
.no_qsuf
= 1;
6403 /* NB: In Intel syntax, normally we can check for memory operand
6404 size when there is no mnemonic suffix. But jmp and call have
6405 2 different encodings with Dword memory operand size, one with
6406 No_ldSuf and the other without. i.suffix is set to
6407 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6408 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6409 suffix_check
.no_ldsuf
= 1;
6412 /* Must have right number of operands. */
6413 i
.error
= number_of_operands_mismatch
;
6415 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6417 addr_prefix_disp
= -1;
6418 found_reverse_match
= 0;
6420 if (i
.operands
!= t
->operands
)
6423 /* Check processor support. */
6424 i
.error
= unsupported
;
6425 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6428 /* Check Pseudo Prefix. */
6429 i
.error
= unsupported
;
6430 if (t
->opcode_modifier
.pseudovexprefix
6431 && !(i
.vec_encoding
== vex_encoding_vex
6432 || i
.vec_encoding
== vex_encoding_vex3
))
6435 /* Check AT&T mnemonic. */
6436 i
.error
= unsupported_with_intel_mnemonic
;
6437 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6440 /* Check AT&T/Intel syntax. */
6441 i
.error
= unsupported_syntax
;
6442 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6443 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6446 /* Check Intel64/AMD64 ISA. */
6450 /* Default: Don't accept Intel64. */
6451 if (t
->opcode_modifier
.isa64
== INTEL64
)
6455 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6456 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6460 /* -mintel64: Don't accept AMD64. */
6461 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6466 /* Check the suffix. */
6467 i
.error
= invalid_instruction_suffix
;
6468 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6469 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6470 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6471 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6472 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6473 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6476 size_match
= operand_size_match (t
);
6480 /* This is intentionally not
6482 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6484 as the case of a missing * on the operand is accepted (perhaps with
6485 a warning, issued further down). */
6486 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6488 i
.error
= operand_type_mismatch
;
6492 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6493 operand_types
[j
] = t
->operand_types
[j
];
6495 /* In general, don't allow
6496 - 64-bit operands outside of 64-bit mode,
6497 - 32-bit operands on pre-386. */
6498 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6499 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6500 && flag_code
!= CODE_64BIT
6501 && !(t
->opcode_modifier
.opcodespace
== SPACE_0F
6502 && t
->base_opcode
== 0xc7
6503 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6504 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6505 || (i
.suffix
== LONG_MNEM_SUFFIX
6506 && !cpu_arch_flags
.bitfield
.cpui386
))
6508 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6509 && !intel_float_operand (t
->name
))
6510 : intel_float_operand (t
->name
) != 2)
6511 && (t
->operands
== i
.imm_operands
6512 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6513 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6514 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6515 || (operand_types
[j
].bitfield
.class != RegMMX
6516 && operand_types
[j
].bitfield
.class != RegSIMD
6517 && operand_types
[j
].bitfield
.class != RegMask
))
6518 && !t
->opcode_modifier
.sib
)
6521 /* Do not verify operands when there are none. */
6524 if (VEX_check_encoding (t
))
6526 specific_error
= i
.error
;
6530 /* We've found a match; break out of loop. */
6534 if (!t
->opcode_modifier
.jump
6535 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6537 /* There should be only one Disp operand. */
6538 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6539 if (operand_type_check (operand_types
[j
], disp
))
6541 if (j
< MAX_OPERANDS
)
6543 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6545 addr_prefix_disp
= j
;
6547 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6548 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6552 override
= !override
;
6555 if (operand_types
[j
].bitfield
.disp32
6556 && operand_types
[j
].bitfield
.disp16
)
6558 operand_types
[j
].bitfield
.disp16
= override
;
6559 operand_types
[j
].bitfield
.disp32
= !override
;
6561 operand_types
[j
].bitfield
.disp32s
= 0;
6562 operand_types
[j
].bitfield
.disp64
= 0;
6566 if (operand_types
[j
].bitfield
.disp32s
6567 || operand_types
[j
].bitfield
.disp64
)
6569 operand_types
[j
].bitfield
.disp64
&= !override
;
6570 operand_types
[j
].bitfield
.disp32s
&= !override
;
6571 operand_types
[j
].bitfield
.disp32
= override
;
6573 operand_types
[j
].bitfield
.disp16
= 0;
6579 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6580 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6581 && t
->base_opcode
== 0xa0
6582 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6585 /* We check register size if needed. */
6586 if (t
->opcode_modifier
.checkregsize
)
6588 check_register
= (1 << t
->operands
) - 1;
6589 if (i
.broadcast
.type
)
6590 check_register
&= ~(1 << i
.broadcast
.operand
);
6595 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6596 switch (t
->operands
)
6599 if (!operand_type_match (overlap0
, i
.types
[0]))
6603 /* xchg %eax, %eax is a special case. It is an alias for nop
6604 only in 32bit mode and we can use opcode 0x90. In 64bit
6605 mode, we can't use 0x90 for xchg %eax, %eax since it should
6606 zero-extend %eax to %rax. */
6607 if (flag_code
== CODE_64BIT
6608 && t
->base_opcode
== 0x90
6609 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6610 && i
.types
[0].bitfield
.instance
== Accum
6611 && i
.types
[0].bitfield
.dword
6612 && i
.types
[1].bitfield
.instance
== Accum
6613 && i
.types
[1].bitfield
.dword
)
6615 /* xrelease mov %eax, <disp> is another special case. It must not
6616 match the accumulator-only encoding of mov. */
6617 if (flag_code
!= CODE_64BIT
6619 && t
->base_opcode
== 0xa0
6620 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6621 && i
.types
[0].bitfield
.instance
== Accum
6622 && (i
.flags
[1] & Operand_Mem
))
6627 if (!(size_match
& MATCH_STRAIGHT
))
6629 /* Reverse direction of operands if swapping is possible in the first
6630 place (operands need to be symmetric) and
6631 - the load form is requested, and the template is a store form,
6632 - the store form is requested, and the template is a load form,
6633 - the non-default (swapped) form is requested. */
6634 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6635 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6636 && !operand_type_all_zero (&overlap1
))
6637 switch (i
.dir_encoding
)
6639 case dir_encoding_load
:
6640 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6641 || t
->opcode_modifier
.regmem
)
6645 case dir_encoding_store
:
6646 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6647 && !t
->opcode_modifier
.regmem
)
6651 case dir_encoding_swap
:
6654 case dir_encoding_default
:
6657 /* If we want store form, we skip the current load. */
6658 if ((i
.dir_encoding
== dir_encoding_store
6659 || i
.dir_encoding
== dir_encoding_swap
)
6660 && i
.mem_operands
== 0
6661 && t
->opcode_modifier
.load
)
6666 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6667 if (!operand_type_match (overlap0
, i
.types
[0])
6668 || !operand_type_match (overlap1
, i
.types
[1])
6669 || ((check_register
& 3) == 3
6670 && !operand_type_register_match (i
.types
[0],
6675 /* Check if other direction is valid ... */
6676 if (!t
->opcode_modifier
.d
)
6680 if (!(size_match
& MATCH_REVERSE
))
6682 /* Try reversing direction of operands. */
6683 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6684 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6685 if (!operand_type_match (overlap0
, i
.types
[0])
6686 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6688 && !operand_type_register_match (i
.types
[0],
6689 operand_types
[i
.operands
- 1],
6690 i
.types
[i
.operands
- 1],
6693 /* Does not match either direction. */
6696 /* found_reverse_match holds which of D or FloatR
6698 if (!t
->opcode_modifier
.d
)
6699 found_reverse_match
= 0;
6700 else if (operand_types
[0].bitfield
.tbyte
)
6701 found_reverse_match
= Opcode_FloatD
;
6702 else if (operand_types
[0].bitfield
.xmmword
6703 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6704 || operand_types
[0].bitfield
.class == RegMMX
6705 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6706 || is_any_vex_encoding(t
))
6707 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6708 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6710 found_reverse_match
= Opcode_D
;
6711 if (t
->opcode_modifier
.floatr
)
6712 found_reverse_match
|= Opcode_FloatR
;
6716 /* Found a forward 2 operand match here. */
6717 switch (t
->operands
)
6720 overlap4
= operand_type_and (i
.types
[4],
6724 overlap3
= operand_type_and (i
.types
[3],
6728 overlap2
= operand_type_and (i
.types
[2],
6733 switch (t
->operands
)
6736 if (!operand_type_match (overlap4
, i
.types
[4])
6737 || !operand_type_register_match (i
.types
[3],
6744 if (!operand_type_match (overlap3
, i
.types
[3])
6745 || ((check_register
& 0xa) == 0xa
6746 && !operand_type_register_match (i
.types
[1],
6750 || ((check_register
& 0xc) == 0xc
6751 && !operand_type_register_match (i
.types
[2],
6758 /* Here we make use of the fact that there are no
6759 reverse match 3 operand instructions. */
6760 if (!operand_type_match (overlap2
, i
.types
[2])
6761 || ((check_register
& 5) == 5
6762 && !operand_type_register_match (i
.types
[0],
6766 || ((check_register
& 6) == 6
6767 && !operand_type_register_match (i
.types
[1],
6775 /* Found either forward/reverse 2, 3 or 4 operand match here:
6776 slip through to break. */
6779 /* Check if vector operands are valid. */
6780 if (check_VecOperands (t
))
6782 specific_error
= i
.error
;
6786 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6787 if (VEX_check_encoding (t
))
6789 specific_error
= i
.error
;
6793 /* We've found a match; break out of loop. */
6797 if (t
== current_templates
->end
)
6799 /* We found no match. */
6800 const char *err_msg
;
6801 switch (specific_error
? specific_error
: i
.error
)
6805 case operand_size_mismatch
:
6806 err_msg
= _("operand size mismatch");
6808 case operand_type_mismatch
:
6809 err_msg
= _("operand type mismatch");
6811 case register_type_mismatch
:
6812 err_msg
= _("register type mismatch");
6814 case number_of_operands_mismatch
:
6815 err_msg
= _("number of operands mismatch");
6817 case invalid_instruction_suffix
:
6818 err_msg
= _("invalid instruction suffix");
6821 err_msg
= _("constant doesn't fit in 4 bits");
6823 case unsupported_with_intel_mnemonic
:
6824 err_msg
= _("unsupported with Intel mnemonic");
6826 case unsupported_syntax
:
6827 err_msg
= _("unsupported syntax");
6830 as_bad (_("unsupported instruction `%s'"),
6831 current_templates
->start
->name
);
6833 case invalid_sib_address
:
6834 err_msg
= _("invalid SIB address");
6836 case invalid_vsib_address
:
6837 err_msg
= _("invalid VSIB address");
6839 case invalid_vector_register_set
:
6840 err_msg
= _("mask, index, and destination registers must be distinct");
6842 case invalid_tmm_register_set
:
6843 err_msg
= _("all tmm registers must be distinct");
6845 case unsupported_vector_index_register
:
6846 err_msg
= _("unsupported vector index register");
6848 case unsupported_broadcast
:
6849 err_msg
= _("unsupported broadcast");
6851 case broadcast_needed
:
6852 err_msg
= _("broadcast is needed for operand of such type");
6854 case unsupported_masking
:
6855 err_msg
= _("unsupported masking");
6857 case mask_not_on_destination
:
6858 err_msg
= _("mask not on destination operand");
6860 case no_default_mask
:
6861 err_msg
= _("default mask isn't allowed");
6863 case unsupported_rc_sae
:
6864 err_msg
= _("unsupported static rounding/sae");
6866 case rc_sae_operand_not_last_imm
:
6868 err_msg
= _("RC/SAE operand must precede immediate operands");
6870 err_msg
= _("RC/SAE operand must follow immediate operands");
6872 case invalid_register_operand
:
6873 err_msg
= _("invalid register operand");
6876 as_bad (_("%s for `%s'"), err_msg
,
6877 current_templates
->start
->name
);
6881 if (!quiet_warnings
)
6884 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6885 as_warn (_("indirect %s without `*'"), t
->name
);
6887 if (t
->opcode_modifier
.isprefix
6888 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6890 /* Warn them that a data or address size prefix doesn't
6891 affect assembly of the next line of code. */
6892 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6896 /* Copy the template we found. */
6897 install_template (t
);
6899 if (addr_prefix_disp
!= -1)
6900 i
.tm
.operand_types
[addr_prefix_disp
]
6901 = operand_types
[addr_prefix_disp
];
6903 if (found_reverse_match
)
6905 /* If we found a reverse match we must alter the opcode direction
6906 bit and clear/flip the regmem modifier one. found_reverse_match
6907 holds bits to change (different for int & float insns). */
6909 i
.tm
.base_opcode
^= found_reverse_match
;
6911 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6912 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6914 /* Certain SIMD insns have their load forms specified in the opcode
6915 table, and hence we need to _set_ RegMem instead of clearing it.
6916 We need to avoid setting the bit though on insns like KMOVW. */
6917 i
.tm
.opcode_modifier
.regmem
6918 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6919 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6920 && !i
.tm
.opcode_modifier
.regmem
;
6929 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6930 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6932 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
6934 as_bad (_("`%s' operand %u must use `%ses' segment"),
6936 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6941 /* There's only ever one segment override allowed per instruction.
6942 This instruction possibly has a legal segment override on the
6943 second operand, so copy the segment to where non-string
6944 instructions store it, allowing common code. */
6945 i
.seg
[op
] = i
.seg
[1];
6951 process_suffix (void)
6953 bool is_crc32
= false, is_movx
= false;
6955 /* If matched instruction specifies an explicit instruction mnemonic
6957 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6958 i
.suffix
= WORD_MNEM_SUFFIX
;
6959 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6960 i
.suffix
= LONG_MNEM_SUFFIX
;
6961 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6962 i
.suffix
= QWORD_MNEM_SUFFIX
;
6963 else if (i
.reg_operands
6964 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6965 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6967 unsigned int numop
= i
.operands
;
6970 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
6971 && (i
.tm
.base_opcode
| 8) == 0xbe)
6972 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6973 && i
.tm
.base_opcode
== 0x63
6974 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
6977 is_crc32
= (i
.tm
.base_opcode
== 0xf0
6978 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
6979 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6981 /* movsx/movzx want only their source operand considered here, for the
6982 ambiguity checking below. The suffix will be replaced afterwards
6983 to represent the destination (register). */
6984 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
6987 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6988 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6991 /* If there's no instruction mnemonic suffix we try to invent one
6992 based on GPR operands. */
6995 /* We take i.suffix from the last register operand specified,
6996 Destination register type is more significant than source
6997 register type. crc32 in SSE4.2 prefers source register
6999 unsigned int op
= is_crc32
? 1 : i
.operands
;
7002 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7003 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7005 if (i
.types
[op
].bitfield
.class != Reg
)
7007 if (i
.types
[op
].bitfield
.byte
)
7008 i
.suffix
= BYTE_MNEM_SUFFIX
;
7009 else if (i
.types
[op
].bitfield
.word
)
7010 i
.suffix
= WORD_MNEM_SUFFIX
;
7011 else if (i
.types
[op
].bitfield
.dword
)
7012 i
.suffix
= LONG_MNEM_SUFFIX
;
7013 else if (i
.types
[op
].bitfield
.qword
)
7014 i
.suffix
= QWORD_MNEM_SUFFIX
;
7020 /* As an exception, movsx/movzx silently default to a byte source
7022 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7023 i
.suffix
= BYTE_MNEM_SUFFIX
;
7025 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7028 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7029 && i
.tm
.opcode_modifier
.no_bsuf
)
7031 else if (!check_byte_reg ())
7034 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7037 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7038 && i
.tm
.opcode_modifier
.no_lsuf
7039 && !i
.tm
.opcode_modifier
.todword
7040 && !i
.tm
.opcode_modifier
.toqword
)
7042 else if (!check_long_reg ())
7045 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7048 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7049 && i
.tm
.opcode_modifier
.no_qsuf
7050 && !i
.tm
.opcode_modifier
.todword
7051 && !i
.tm
.opcode_modifier
.toqword
)
7053 else if (!check_qword_reg ())
7056 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7059 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7060 && i
.tm
.opcode_modifier
.no_wsuf
)
7062 else if (!check_word_reg ())
7065 else if (intel_syntax
7066 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7067 /* Do nothing if the instruction is going to ignore the prefix. */
7072 /* Undo the movsx/movzx change done above. */
7075 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7078 i
.suffix
= stackop_size
;
7079 if (stackop_size
== LONG_MNEM_SUFFIX
)
7081 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7082 .code16gcc directive to support 16-bit mode with
7083 32-bit address. For IRET without a suffix, generate
7084 16-bit IRET (opcode 0xcf) to return from an interrupt
7086 if (i
.tm
.base_opcode
== 0xcf)
7088 i
.suffix
= WORD_MNEM_SUFFIX
;
7089 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7091 /* Warn about changed behavior for segment register push/pop. */
7092 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7093 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7098 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7099 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7100 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7101 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7102 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7103 && i
.tm
.extension_opcode
<= 3)))
7108 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7110 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7111 || i
.tm
.opcode_modifier
.no_lsuf
)
7112 i
.suffix
= QWORD_MNEM_SUFFIX
;
7117 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7118 i
.suffix
= LONG_MNEM_SUFFIX
;
7121 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7122 i
.suffix
= WORD_MNEM_SUFFIX
;
7128 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7129 /* Also cover lret/retf/iret in 64-bit mode. */
7130 || (flag_code
== CODE_64BIT
7131 && !i
.tm
.opcode_modifier
.no_lsuf
7132 && !i
.tm
.opcode_modifier
.no_qsuf
))
7133 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7134 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7135 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7136 /* Accept FLDENV et al without suffix. */
7137 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7139 unsigned int suffixes
, evex
= 0;
7141 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7142 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7144 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7146 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
7148 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7150 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7153 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7154 also suitable for AT&T syntax mode, it was requested that this be
7155 restricted to just Intel syntax. */
7156 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
.type
)
7160 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7162 if (is_evex_encoding (&i
.tm
)
7163 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7165 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7166 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7167 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7168 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7169 if (!i
.tm
.opcode_modifier
.evex
7170 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7171 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7174 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7175 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7176 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7179 /* Any properly sized operand disambiguates the insn. */
7180 if (i
.types
[op
].bitfield
.xmmword
7181 || i
.types
[op
].bitfield
.ymmword
7182 || i
.types
[op
].bitfield
.zmmword
)
7184 suffixes
&= ~(7 << 6);
7189 if ((i
.flags
[op
] & Operand_Mem
)
7190 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7192 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7194 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7196 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7198 if (is_evex_encoding (&i
.tm
))
7204 /* Are multiple suffixes / operand sizes allowed? */
7205 if (suffixes
& (suffixes
- 1))
7208 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7209 || operand_check
== check_error
))
7211 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7214 if (operand_check
== check_error
)
7216 as_bad (_("no instruction mnemonic suffix given and "
7217 "no register operands; can't size `%s'"), i
.tm
.name
);
7220 if (operand_check
== check_warning
)
7221 as_warn (_("%s; using default for `%s'"),
7223 ? _("ambiguous operand size")
7224 : _("no instruction mnemonic suffix given and "
7225 "no register operands"),
7228 if (i
.tm
.opcode_modifier
.floatmf
)
7229 i
.suffix
= SHORT_MNEM_SUFFIX
;
7231 /* handled below */;
7233 i
.tm
.opcode_modifier
.evex
= evex
;
7234 else if (flag_code
== CODE_16BIT
)
7235 i
.suffix
= WORD_MNEM_SUFFIX
;
7236 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7237 i
.suffix
= LONG_MNEM_SUFFIX
;
7239 i
.suffix
= QWORD_MNEM_SUFFIX
;
7245 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7246 In AT&T syntax, if there is no suffix (warned about above), the default
7247 will be byte extension. */
7248 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7249 i
.tm
.base_opcode
|= 1;
7251 /* For further processing, the suffix should represent the destination
7252 (register). This is already the case when one was used with
7253 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7254 no suffix to begin with. */
7255 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7257 if (i
.types
[1].bitfield
.word
)
7258 i
.suffix
= WORD_MNEM_SUFFIX
;
7259 else if (i
.types
[1].bitfield
.qword
)
7260 i
.suffix
= QWORD_MNEM_SUFFIX
;
7262 i
.suffix
= LONG_MNEM_SUFFIX
;
7264 i
.tm
.opcode_modifier
.w
= 0;
7268 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7269 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7270 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7272 /* Change the opcode based on the operand size given by i.suffix. */
7275 /* Size floating point instruction. */
7276 case LONG_MNEM_SUFFIX
:
7277 if (i
.tm
.opcode_modifier
.floatmf
)
7279 i
.tm
.base_opcode
^= 4;
7283 case WORD_MNEM_SUFFIX
:
7284 case QWORD_MNEM_SUFFIX
:
7285 /* It's not a byte, select word/dword operation. */
7286 if (i
.tm
.opcode_modifier
.w
)
7289 i
.tm
.base_opcode
|= 8;
7291 i
.tm
.base_opcode
|= 1;
7294 case SHORT_MNEM_SUFFIX
:
7295 /* Now select between word & dword operations via the operand
7296 size prefix, except for instructions that will ignore this
7298 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7299 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7300 && !i
.tm
.opcode_modifier
.floatmf
7301 && !is_any_vex_encoding (&i
.tm
)
7302 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7303 || (flag_code
== CODE_64BIT
7304 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7306 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7308 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7309 prefix
= ADDR_PREFIX_OPCODE
;
7311 if (!add_prefix (prefix
))
7315 /* Set mode64 for an operand. */
7316 if (i
.suffix
== QWORD_MNEM_SUFFIX
7317 && flag_code
== CODE_64BIT
7318 && !i
.tm
.opcode_modifier
.norex64
7319 && !i
.tm
.opcode_modifier
.vexw
7320 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7322 && ! (i
.operands
== 2
7323 && i
.tm
.base_opcode
== 0x90
7324 && i
.tm
.extension_opcode
== None
7325 && i
.types
[0].bitfield
.instance
== Accum
7326 && i
.types
[0].bitfield
.qword
7327 && i
.types
[1].bitfield
.instance
== Accum
7328 && i
.types
[1].bitfield
.qword
))
7334 /* Select word/dword/qword operation with explicit data sizing prefix
7335 when there are no suitable register operands. */
7336 if (i
.tm
.opcode_modifier
.w
7337 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7339 || (i
.reg_operands
== 1
7341 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7343 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7344 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7347 i
.tm
.base_opcode
|= 1;
7351 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7353 gas_assert (!i
.suffix
);
7354 gas_assert (i
.reg_operands
);
7356 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7359 /* The address size override prefix changes the size of the
7361 if (flag_code
== CODE_64BIT
7362 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7364 as_bad (_("16-bit addressing unavailable for `%s'"),
7369 if ((flag_code
== CODE_32BIT
7370 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7371 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7372 && !add_prefix (ADDR_PREFIX_OPCODE
))
7377 /* Check invalid register operand when the address size override
7378 prefix changes the size of register operands. */
7380 enum { need_word
, need_dword
, need_qword
} need
;
7382 /* Check the register operand for the address size prefix if
7383 the memory operand has no real registers, like symbol, DISP
7384 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7385 if (i
.mem_operands
== 1
7386 && i
.reg_operands
== 1
7388 && i
.types
[1].bitfield
.class == Reg
7389 && (flag_code
== CODE_32BIT
7390 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7391 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7392 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7393 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7394 || (x86_elf_abi
== X86_64_X32_ABI
7396 && i
.base_reg
->reg_num
== RegIP
7397 && i
.base_reg
->reg_type
.bitfield
.qword
))
7401 && !add_prefix (ADDR_PREFIX_OPCODE
))
7404 if (flag_code
== CODE_32BIT
)
7405 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7406 else if (i
.prefix
[ADDR_PREFIX
])
7409 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7411 for (op
= 0; op
< i
.operands
; op
++)
7413 if (i
.types
[op
].bitfield
.class != Reg
)
7419 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7423 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7427 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7432 as_bad (_("invalid register operand size for `%s'"),
7443 check_byte_reg (void)
7447 for (op
= i
.operands
; --op
>= 0;)
7449 /* Skip non-register operands. */
7450 if (i
.types
[op
].bitfield
.class != Reg
)
7453 /* If this is an eight bit register, it's OK. If it's the 16 or
7454 32 bit version of an eight bit register, we will just use the
7455 low portion, and that's OK too. */
7456 if (i
.types
[op
].bitfield
.byte
)
7459 /* I/O port address operands are OK too. */
7460 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7461 && i
.tm
.operand_types
[op
].bitfield
.word
)
7464 /* crc32 only wants its source operand checked here. */
7465 if (i
.tm
.base_opcode
== 0xf0
7466 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7467 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7471 /* Any other register is bad. */
7472 as_bad (_("`%s%s' not allowed with `%s%c'"),
7473 register_prefix
, i
.op
[op
].regs
->reg_name
,
7474 i
.tm
.name
, i
.suffix
);
7481 check_long_reg (void)
7485 for (op
= i
.operands
; --op
>= 0;)
7486 /* Skip non-register operands. */
7487 if (i
.types
[op
].bitfield
.class != Reg
)
7489 /* Reject eight bit registers, except where the template requires
7490 them. (eg. movzb) */
7491 else if (i
.types
[op
].bitfield
.byte
7492 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7493 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7494 && (i
.tm
.operand_types
[op
].bitfield
.word
7495 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7497 as_bad (_("`%s%s' not allowed with `%s%c'"),
7499 i
.op
[op
].regs
->reg_name
,
7504 /* Error if the e prefix on a general reg is missing. */
7505 else if (i
.types
[op
].bitfield
.word
7506 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7507 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7508 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7510 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7511 register_prefix
, i
.op
[op
].regs
->reg_name
,
7515 /* Warn if the r prefix on a general reg is present. */
7516 else if (i
.types
[op
].bitfield
.qword
7517 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7518 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7519 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7522 && i
.tm
.opcode_modifier
.toqword
7523 && i
.types
[0].bitfield
.class != RegSIMD
)
7525 /* Convert to QWORD. We want REX byte. */
7526 i
.suffix
= QWORD_MNEM_SUFFIX
;
7530 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7531 register_prefix
, i
.op
[op
].regs
->reg_name
,
7540 check_qword_reg (void)
7544 for (op
= i
.operands
; --op
>= 0; )
7545 /* Skip non-register operands. */
7546 if (i
.types
[op
].bitfield
.class != Reg
)
7548 /* Reject eight bit registers, except where the template requires
7549 them. (eg. movzb) */
7550 else if (i
.types
[op
].bitfield
.byte
7551 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7552 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7553 && (i
.tm
.operand_types
[op
].bitfield
.word
7554 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7556 as_bad (_("`%s%s' not allowed with `%s%c'"),
7558 i
.op
[op
].regs
->reg_name
,
7563 /* Warn if the r prefix on a general reg is missing. */
7564 else if ((i
.types
[op
].bitfield
.word
7565 || i
.types
[op
].bitfield
.dword
)
7566 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7567 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7568 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7570 /* Prohibit these changes in the 64bit mode, since the
7571 lowering is more complicated. */
7573 && i
.tm
.opcode_modifier
.todword
7574 && i
.types
[0].bitfield
.class != RegSIMD
)
7576 /* Convert to DWORD. We don't want REX byte. */
7577 i
.suffix
= LONG_MNEM_SUFFIX
;
7581 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7582 register_prefix
, i
.op
[op
].regs
->reg_name
,
7591 check_word_reg (void)
7594 for (op
= i
.operands
; --op
>= 0;)
7595 /* Skip non-register operands. */
7596 if (i
.types
[op
].bitfield
.class != Reg
)
7598 /* Reject eight bit registers, except where the template requires
7599 them. (eg. movzb) */
7600 else if (i
.types
[op
].bitfield
.byte
7601 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7602 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7603 && (i
.tm
.operand_types
[op
].bitfield
.word
7604 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7606 as_bad (_("`%s%s' not allowed with `%s%c'"),
7608 i
.op
[op
].regs
->reg_name
,
7613 /* Error if the e or r prefix on a general reg is present. */
7614 else if ((i
.types
[op
].bitfield
.dword
7615 || i
.types
[op
].bitfield
.qword
)
7616 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7617 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7618 && i
.tm
.operand_types
[op
].bitfield
.word
)
7620 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7621 register_prefix
, i
.op
[op
].regs
->reg_name
,
7629 update_imm (unsigned int j
)
7631 i386_operand_type overlap
= i
.types
[j
];
7632 if ((overlap
.bitfield
.imm8
7633 || overlap
.bitfield
.imm8s
7634 || overlap
.bitfield
.imm16
7635 || overlap
.bitfield
.imm32
7636 || overlap
.bitfield
.imm32s
7637 || overlap
.bitfield
.imm64
)
7638 && !operand_type_equal (&overlap
, &imm8
)
7639 && !operand_type_equal (&overlap
, &imm8s
)
7640 && !operand_type_equal (&overlap
, &imm16
)
7641 && !operand_type_equal (&overlap
, &imm32
)
7642 && !operand_type_equal (&overlap
, &imm32s
)
7643 && !operand_type_equal (&overlap
, &imm64
))
7647 i386_operand_type temp
;
7649 operand_type_set (&temp
, 0);
7650 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7652 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7653 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7655 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7656 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7657 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7659 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7660 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7663 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7666 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7667 || operand_type_equal (&overlap
, &imm16_32
)
7668 || operand_type_equal (&overlap
, &imm16_32s
))
7670 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7675 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7676 overlap
= operand_type_and (overlap
, imm32s
);
7677 else if (i
.prefix
[DATA_PREFIX
])
7678 overlap
= operand_type_and (overlap
,
7679 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7680 if (!operand_type_equal (&overlap
, &imm8
)
7681 && !operand_type_equal (&overlap
, &imm8s
)
7682 && !operand_type_equal (&overlap
, &imm16
)
7683 && !operand_type_equal (&overlap
, &imm32
)
7684 && !operand_type_equal (&overlap
, &imm32s
)
7685 && !operand_type_equal (&overlap
, &imm64
))
7687 as_bad (_("no instruction mnemonic suffix given; "
7688 "can't determine immediate size"));
7692 i
.types
[j
] = overlap
;
7702 /* Update the first 2 immediate operands. */
7703 n
= i
.operands
> 2 ? 2 : i
.operands
;
7706 for (j
= 0; j
< n
; j
++)
7707 if (update_imm (j
) == 0)
7710 /* The 3rd operand can't be immediate operand. */
7711 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7718 process_operands (void)
7720 /* Default segment register this instruction will use for memory
7721 accesses. 0 means unknown. This is only for optimizing out
7722 unnecessary segment overrides. */
7723 const reg_entry
*default_seg
= NULL
;
7725 if (i
.tm
.opcode_modifier
.sse2avx
)
7727 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7729 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7730 i
.prefix
[REX_PREFIX
] = 0;
7733 /* ImmExt should be processed after SSE2AVX. */
7734 else if (i
.tm
.opcode_modifier
.immext
)
7737 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7739 unsigned int dupl
= i
.operands
;
7740 unsigned int dest
= dupl
- 1;
7743 /* The destination must be an xmm register. */
7744 gas_assert (i
.reg_operands
7745 && MAX_OPERANDS
> dupl
7746 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7748 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7749 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7751 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7753 /* Keep xmm0 for instructions with VEX prefix and 3
7755 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7756 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7761 /* We remove the first xmm0 and keep the number of
7762 operands unchanged, which in fact duplicates the
7764 for (j
= 1; j
< i
.operands
; j
++)
7766 i
.op
[j
- 1] = i
.op
[j
];
7767 i
.types
[j
- 1] = i
.types
[j
];
7768 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7769 i
.flags
[j
- 1] = i
.flags
[j
];
7773 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7775 gas_assert ((MAX_OPERANDS
- 1) > dupl
7776 && (i
.tm
.opcode_modifier
.vexsources
7779 /* Add the implicit xmm0 for instructions with VEX prefix
7781 for (j
= i
.operands
; j
> 0; j
--)
7783 i
.op
[j
] = i
.op
[j
- 1];
7784 i
.types
[j
] = i
.types
[j
- 1];
7785 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7786 i
.flags
[j
] = i
.flags
[j
- 1];
7789 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7790 i
.types
[0] = regxmm
;
7791 i
.tm
.operand_types
[0] = regxmm
;
7794 i
.reg_operands
+= 2;
7799 i
.op
[dupl
] = i
.op
[dest
];
7800 i
.types
[dupl
] = i
.types
[dest
];
7801 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7802 i
.flags
[dupl
] = i
.flags
[dest
];
7811 i
.op
[dupl
] = i
.op
[dest
];
7812 i
.types
[dupl
] = i
.types
[dest
];
7813 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7814 i
.flags
[dupl
] = i
.flags
[dest
];
7817 if (i
.tm
.opcode_modifier
.immext
)
7820 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7821 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7825 for (j
= 1; j
< i
.operands
; j
++)
7827 i
.op
[j
- 1] = i
.op
[j
];
7828 i
.types
[j
- 1] = i
.types
[j
];
7830 /* We need to adjust fields in i.tm since they are used by
7831 build_modrm_byte. */
7832 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7834 i
.flags
[j
- 1] = i
.flags
[j
];
7841 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7843 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7845 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7846 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7847 regnum
= register_number (i
.op
[1].regs
);
7848 first_reg_in_group
= regnum
& ~3;
7849 last_reg_in_group
= first_reg_in_group
+ 3;
7850 if (regnum
!= first_reg_in_group
)
7851 as_warn (_("source register `%s%s' implicitly denotes"
7852 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7853 register_prefix
, i
.op
[1].regs
->reg_name
,
7854 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7855 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7858 else if (i
.tm
.opcode_modifier
.regkludge
)
7860 /* The imul $imm, %reg instruction is converted into
7861 imul $imm, %reg, %reg, and the clr %reg instruction
7862 is converted into xor %reg, %reg. */
7864 unsigned int first_reg_op
;
7866 if (operand_type_check (i
.types
[0], reg
))
7870 /* Pretend we saw the extra register operand. */
7871 gas_assert (i
.reg_operands
== 1
7872 && i
.op
[first_reg_op
+ 1].regs
== 0);
7873 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7874 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7879 if (i
.tm
.opcode_modifier
.modrm
)
7881 /* The opcode is completed (modulo i.tm.extension_opcode which
7882 must be put into the modrm byte). Now, we make the modrm and
7883 index base bytes based on all the info we've collected. */
7885 default_seg
= build_modrm_byte ();
7887 else if (i
.types
[0].bitfield
.class == SReg
)
7889 if (flag_code
!= CODE_64BIT
7890 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7891 && i
.op
[0].regs
->reg_num
== 1
7892 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
7893 && i
.op
[0].regs
->reg_num
< 4)
7895 as_bad (_("you can't `%s %s%s'"),
7896 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7899 if (i
.op
[0].regs
->reg_num
> 3
7900 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
7902 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
7903 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
7905 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7907 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7908 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
7910 default_seg
= reg_ds
;
7912 else if (i
.tm
.opcode_modifier
.isstring
)
7914 /* For the string instructions that allow a segment override
7915 on one of their operands, the default segment is ds. */
7916 default_seg
= reg_ds
;
7918 else if (i
.short_form
)
7920 /* The register or float register operand is in operand
7922 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7924 /* Register goes in low 3 bits of opcode. */
7925 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7926 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7928 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7930 /* Warn about some common errors, but press on regardless.
7931 The first case can be generated by gcc (<= 2.8.1). */
7932 if (i
.operands
== 2)
7934 /* Reversed arguments on faddp, fsubp, etc. */
7935 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7936 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7937 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7941 /* Extraneous `l' suffix on fp insn. */
7942 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7943 register_prefix
, i
.op
[0].regs
->reg_name
);
7948 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7949 && i
.tm
.base_opcode
== 0x8d /* lea */
7950 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7951 && !is_any_vex_encoding(&i
.tm
))
7953 if (!quiet_warnings
)
7954 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7958 i
.prefix
[SEG_PREFIX
] = 0;
7962 /* If a segment was explicitly specified, and the specified segment
7963 is neither the default nor the one already recorded from a prefix,
7964 use an opcode prefix to select it. If we never figured out what
7965 the default segment is, then default_seg will be zero at this
7966 point, and the specified segment prefix will always be used. */
7968 && i
.seg
[0] != default_seg
7969 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
7971 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
7977 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7980 if (r
->reg_flags
& RegRex
)
7982 if (i
.rex
& rex_bit
)
7983 as_bad (_("same type of prefix used twice"));
7986 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7988 gas_assert (i
.vex
.register_specifier
== r
);
7989 i
.vex
.register_specifier
+= 8;
7992 if (r
->reg_flags
& RegVRex
)
7996 static const reg_entry
*
7997 build_modrm_byte (void)
7999 const reg_entry
*default_seg
= NULL
;
8000 unsigned int source
, dest
;
8003 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8006 unsigned int nds
, reg_slot
;
8009 dest
= i
.operands
- 1;
8012 /* There are 2 kinds of instructions:
8013 1. 5 operands: 4 register operands or 3 register operands
8014 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8015 VexW0 or VexW1. The destination must be either XMM, YMM or
8017 2. 4 operands: 4 register operands or 3 register operands
8018 plus 1 memory operand, with VexXDS. */
8019 gas_assert ((i
.reg_operands
== 4
8020 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8021 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8022 && i
.tm
.opcode_modifier
.vexw
8023 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8025 /* If VexW1 is set, the first non-immediate operand is the source and
8026 the second non-immediate one is encoded in the immediate operand. */
8027 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8029 source
= i
.imm_operands
;
8030 reg_slot
= i
.imm_operands
+ 1;
8034 source
= i
.imm_operands
+ 1;
8035 reg_slot
= i
.imm_operands
;
8038 if (i
.imm_operands
== 0)
8040 /* When there is no immediate operand, generate an 8bit
8041 immediate operand to encode the first operand. */
8042 exp
= &im_expressions
[i
.imm_operands
++];
8043 i
.op
[i
.operands
].imms
= exp
;
8044 i
.types
[i
.operands
] = imm8
;
8047 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8048 exp
->X_op
= O_constant
;
8049 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8050 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8054 gas_assert (i
.imm_operands
== 1);
8055 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8056 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8058 /* Turn on Imm8 again so that output_imm will generate it. */
8059 i
.types
[0].bitfield
.imm8
= 1;
8061 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8062 i
.op
[0].imms
->X_add_number
8063 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8064 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8067 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8068 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8073 /* i.reg_operands MUST be the number of real register operands;
8074 implicit registers do not count. If there are 3 register
8075 operands, it must be a instruction with VexNDS. For a
8076 instruction with VexNDD, the destination register is encoded
8077 in VEX prefix. If there are 4 register operands, it must be
8078 a instruction with VEX prefix and 3 sources. */
8079 if (i
.mem_operands
== 0
8080 && ((i
.reg_operands
== 2
8081 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8082 || (i
.reg_operands
== 3
8083 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8084 || (i
.reg_operands
== 4 && vex_3_sources
)))
8092 /* When there are 3 operands, one of them may be immediate,
8093 which may be the first or the last operand. Otherwise,
8094 the first operand must be shift count register (cl) or it
8095 is an instruction with VexNDS. */
8096 gas_assert (i
.imm_operands
== 1
8097 || (i
.imm_operands
== 0
8098 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8099 || (i
.types
[0].bitfield
.instance
== RegC
8100 && i
.types
[0].bitfield
.byte
))));
8101 if (operand_type_check (i
.types
[0], imm
)
8102 || (i
.types
[0].bitfield
.instance
== RegC
8103 && i
.types
[0].bitfield
.byte
))
8109 /* When there are 4 operands, the first two must be 8bit
8110 immediate operands. The source operand will be the 3rd
8113 For instructions with VexNDS, if the first operand
8114 an imm8, the source operand is the 2nd one. If the last
8115 operand is imm8, the source operand is the first one. */
8116 gas_assert ((i
.imm_operands
== 2
8117 && i
.types
[0].bitfield
.imm8
8118 && i
.types
[1].bitfield
.imm8
)
8119 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8120 && i
.imm_operands
== 1
8121 && (i
.types
[0].bitfield
.imm8
8122 || i
.types
[i
.operands
- 1].bitfield
.imm8
8123 || i
.rounding
.type
!= rc_none
)));
8124 if (i
.imm_operands
== 2)
8128 if (i
.types
[0].bitfield
.imm8
)
8135 if (is_evex_encoding (&i
.tm
))
8137 /* For EVEX instructions, when there are 5 operands, the
8138 first one must be immediate operand. If the second one
8139 is immediate operand, the source operand is the 3th
8140 one. If the last one is immediate operand, the source
8141 operand is the 2nd one. */
8142 gas_assert (i
.imm_operands
== 2
8143 && i
.tm
.opcode_modifier
.sae
8144 && operand_type_check (i
.types
[0], imm
));
8145 if (operand_type_check (i
.types
[1], imm
))
8147 else if (operand_type_check (i
.types
[4], imm
))
8161 /* RC/SAE operand could be between DEST and SRC. That happens
8162 when one operand is GPR and the other one is XMM/YMM/ZMM
8164 if (i
.rounding
.type
!= rc_none
&& i
.rounding
.operand
== dest
)
8167 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8169 /* For instructions with VexNDS, the register-only source
8170 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8171 register. It is encoded in VEX prefix. */
8173 i386_operand_type op
;
8176 /* Swap two source operands if needed. */
8177 if (i
.tm
.opcode_modifier
.swapsources
)
8185 op
= i
.tm
.operand_types
[vvvv
];
8186 if ((dest
+ 1) >= i
.operands
8187 || ((op
.bitfield
.class != Reg
8188 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8189 && op
.bitfield
.class != RegSIMD
8190 && !operand_type_equal (&op
, ®mask
)))
8192 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8198 /* One of the register operands will be encoded in the i.rm.reg
8199 field, the other in the combined i.rm.mode and i.rm.regmem
8200 fields. If no form of this instruction supports a memory
8201 destination operand, then we assume the source operand may
8202 sometimes be a memory operand and so we need to store the
8203 destination in the i.rm.reg field. */
8204 if (!i
.tm
.opcode_modifier
.regmem
8205 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8207 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8208 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8209 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8210 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8214 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8215 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8216 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8217 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8219 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8221 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8224 add_prefix (LOCK_PREFIX_OPCODE
);
8228 { /* If it's not 2 reg operands... */
8233 unsigned int fake_zero_displacement
= 0;
8236 for (op
= 0; op
< i
.operands
; op
++)
8237 if (i
.flags
[op
] & Operand_Mem
)
8239 gas_assert (op
< i
.operands
);
8241 if (i
.tm
.opcode_modifier
.sib
)
8243 /* The index register of VSIB shouldn't be RegIZ. */
8244 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8245 && i
.index_reg
->reg_num
== RegIZ
)
8248 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8251 i
.sib
.base
= NO_BASE_REGISTER
;
8252 i
.sib
.scale
= i
.log2_scale_factor
;
8253 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8254 if (want_disp32 (&i
.tm
))
8255 i
.types
[op
].bitfield
.disp32
= 1;
8257 i
.types
[op
].bitfield
.disp32s
= 1;
8260 /* Since the mandatory SIB always has index register, so
8261 the code logic remains unchanged. The non-mandatory SIB
8262 without index register is allowed and will be handled
8266 if (i
.index_reg
->reg_num
== RegIZ
)
8267 i
.sib
.index
= NO_INDEX_REGISTER
;
8269 i
.sib
.index
= i
.index_reg
->reg_num
;
8270 set_rex_vrex (i
.index_reg
, REX_X
, false);
8274 default_seg
= reg_ds
;
8276 if (i
.base_reg
== 0)
8279 if (!i
.disp_operands
)
8280 fake_zero_displacement
= 1;
8281 if (i
.index_reg
== 0)
8283 /* Both check for VSIB and mandatory non-vector SIB. */
8284 gas_assert (!i
.tm
.opcode_modifier
.sib
8285 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8286 /* Operand is just <disp> */
8287 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8288 if (flag_code
== CODE_64BIT
)
8290 /* 64bit mode overwrites the 32bit absolute
8291 addressing by RIP relative addressing and
8292 absolute addressing is encoded by one of the
8293 redundant SIB forms. */
8294 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8295 i
.sib
.base
= NO_BASE_REGISTER
;
8296 i
.sib
.index
= NO_INDEX_REGISTER
;
8297 if (want_disp32 (&i
.tm
))
8298 i
.types
[op
].bitfield
.disp32
= 1;
8300 i
.types
[op
].bitfield
.disp32s
= 1;
8302 else if ((flag_code
== CODE_16BIT
)
8303 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8305 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8306 i
.types
[op
].bitfield
.disp16
= 1;
8310 i
.rm
.regmem
= NO_BASE_REGISTER
;
8311 i
.types
[op
].bitfield
.disp32
= 1;
8314 else if (!i
.tm
.opcode_modifier
.sib
)
8316 /* !i.base_reg && i.index_reg */
8317 if (i
.index_reg
->reg_num
== RegIZ
)
8318 i
.sib
.index
= NO_INDEX_REGISTER
;
8320 i
.sib
.index
= i
.index_reg
->reg_num
;
8321 i
.sib
.base
= NO_BASE_REGISTER
;
8322 i
.sib
.scale
= i
.log2_scale_factor
;
8323 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8324 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8325 if (want_disp32 (&i
.tm
))
8326 i
.types
[op
].bitfield
.disp32
= 1;
8328 i
.types
[op
].bitfield
.disp32s
= 1;
8329 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8333 /* RIP addressing for 64bit mode. */
8334 else if (i
.base_reg
->reg_num
== RegIP
)
8336 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8337 i
.rm
.regmem
= NO_BASE_REGISTER
;
8338 i
.types
[op
].bitfield
.disp8
= 0;
8339 i
.types
[op
].bitfield
.disp16
= 0;
8340 i
.types
[op
].bitfield
.disp32
= 0;
8341 i
.types
[op
].bitfield
.disp32s
= 1;
8342 i
.types
[op
].bitfield
.disp64
= 0;
8343 i
.flags
[op
] |= Operand_PCrel
;
8344 if (! i
.disp_operands
)
8345 fake_zero_displacement
= 1;
8347 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8349 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8350 switch (i
.base_reg
->reg_num
)
8353 if (i
.index_reg
== 0)
8355 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8356 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8359 default_seg
= reg_ss
;
8360 if (i
.index_reg
== 0)
8363 if (operand_type_check (i
.types
[op
], disp
) == 0)
8365 /* fake (%bp) into 0(%bp) */
8366 if (i
.disp_encoding
== disp_encoding_16bit
)
8367 i
.types
[op
].bitfield
.disp16
= 1;
8369 i
.types
[op
].bitfield
.disp8
= 1;
8370 fake_zero_displacement
= 1;
8373 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8374 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8376 default: /* (%si) -> 4 or (%di) -> 5 */
8377 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8379 if (!fake_zero_displacement
8383 fake_zero_displacement
= 1;
8384 if (i
.disp_encoding
== disp_encoding_8bit
)
8385 i
.types
[op
].bitfield
.disp8
= 1;
8387 i
.types
[op
].bitfield
.disp16
= 1;
8389 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8391 else /* i.base_reg and 32/64 bit mode */
8393 if (operand_type_check (i
.types
[op
], disp
))
8395 i
.types
[op
].bitfield
.disp16
= 0;
8396 i
.types
[op
].bitfield
.disp64
= 0;
8397 if (!want_disp32 (&i
.tm
))
8399 i
.types
[op
].bitfield
.disp32
= 0;
8400 i
.types
[op
].bitfield
.disp32s
= 1;
8404 i
.types
[op
].bitfield
.disp32
= 1;
8405 i
.types
[op
].bitfield
.disp32s
= 0;
8409 if (!i
.tm
.opcode_modifier
.sib
)
8410 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8411 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8413 i
.sib
.base
= i
.base_reg
->reg_num
;
8414 /* x86-64 ignores REX prefix bit here to avoid decoder
8416 if (!(i
.base_reg
->reg_flags
& RegRex
)
8417 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8418 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8419 default_seg
= reg_ss
;
8420 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8422 fake_zero_displacement
= 1;
8423 if (i
.disp_encoding
== disp_encoding_32bit
)
8424 i
.types
[op
].bitfield
.disp32
= 1;
8426 i
.types
[op
].bitfield
.disp8
= 1;
8428 i
.sib
.scale
= i
.log2_scale_factor
;
8429 if (i
.index_reg
== 0)
8431 /* Only check for VSIB. */
8432 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8433 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8434 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8436 /* <disp>(%esp) becomes two byte modrm with no index
8437 register. We've already stored the code for esp
8438 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8439 Any base register besides %esp will not use the
8440 extra modrm byte. */
8441 i
.sib
.index
= NO_INDEX_REGISTER
;
8443 else if (!i
.tm
.opcode_modifier
.sib
)
8445 if (i
.index_reg
->reg_num
== RegIZ
)
8446 i
.sib
.index
= NO_INDEX_REGISTER
;
8448 i
.sib
.index
= i
.index_reg
->reg_num
;
8449 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8450 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8455 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8456 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8460 if (!fake_zero_displacement
8464 fake_zero_displacement
= 1;
8465 if (i
.disp_encoding
== disp_encoding_8bit
)
8466 i
.types
[op
].bitfield
.disp8
= 1;
8468 i
.types
[op
].bitfield
.disp32
= 1;
8470 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8474 if (fake_zero_displacement
)
8476 /* Fakes a zero displacement assuming that i.types[op]
8477 holds the correct displacement size. */
8480 gas_assert (i
.op
[op
].disps
== 0);
8481 exp
= &disp_expressions
[i
.disp_operands
++];
8482 i
.op
[op
].disps
= exp
;
8483 exp
->X_op
= O_constant
;
8484 exp
->X_add_number
= 0;
8485 exp
->X_add_symbol
= (symbolS
*) 0;
8486 exp
->X_op_symbol
= (symbolS
*) 0;
8494 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8496 if (operand_type_check (i
.types
[0], imm
))
8497 i
.vex
.register_specifier
= NULL
;
8500 /* VEX.vvvv encodes one of the sources when the first
8501 operand is not an immediate. */
8502 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8503 i
.vex
.register_specifier
= i
.op
[0].regs
;
8505 i
.vex
.register_specifier
= i
.op
[1].regs
;
8508 /* Destination is a XMM register encoded in the ModRM.reg
8510 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8511 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8514 /* ModRM.rm and VEX.B encodes the other source. */
8515 if (!i
.mem_operands
)
8519 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8520 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8522 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8524 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8528 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8530 i
.vex
.register_specifier
= i
.op
[2].regs
;
8531 if (!i
.mem_operands
)
8534 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8535 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8539 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8540 (if any) based on i.tm.extension_opcode. Again, we must be
8541 careful to make sure that segment/control/debug/test/MMX
8542 registers are coded into the i.rm.reg field. */
8543 else if (i
.reg_operands
)
8546 unsigned int vex_reg
= ~0;
8548 for (op
= 0; op
< i
.operands
; op
++)
8549 if (i
.types
[op
].bitfield
.class == Reg
8550 || i
.types
[op
].bitfield
.class == RegBND
8551 || i
.types
[op
].bitfield
.class == RegMask
8552 || i
.types
[op
].bitfield
.class == SReg
8553 || i
.types
[op
].bitfield
.class == RegCR
8554 || i
.types
[op
].bitfield
.class == RegDR
8555 || i
.types
[op
].bitfield
.class == RegTR
8556 || i
.types
[op
].bitfield
.class == RegSIMD
8557 || i
.types
[op
].bitfield
.class == RegMMX
)
8562 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8564 /* For instructions with VexNDS, the register-only
8565 source operand is encoded in VEX prefix. */
8566 gas_assert (mem
!= (unsigned int) ~0);
8571 gas_assert (op
< i
.operands
);
8575 /* Check register-only source operand when two source
8576 operands are swapped. */
8577 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8578 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8582 gas_assert (mem
== (vex_reg
+ 1)
8583 && op
< i
.operands
);
8588 gas_assert (vex_reg
< i
.operands
);
8592 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8594 /* For instructions with VexNDD, the register destination
8595 is encoded in VEX prefix. */
8596 if (i
.mem_operands
== 0)
8598 /* There is no memory operand. */
8599 gas_assert ((op
+ 2) == i
.operands
);
8604 /* There are only 2 non-immediate operands. */
8605 gas_assert (op
< i
.imm_operands
+ 2
8606 && i
.operands
== i
.imm_operands
+ 2);
8607 vex_reg
= i
.imm_operands
+ 1;
8611 gas_assert (op
< i
.operands
);
8613 if (vex_reg
!= (unsigned int) ~0)
8615 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8617 if ((type
->bitfield
.class != Reg
8618 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8619 && type
->bitfield
.class != RegSIMD
8620 && !operand_type_equal (type
, ®mask
))
8623 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8626 /* Don't set OP operand twice. */
8629 /* If there is an extension opcode to put here, the
8630 register number must be put into the regmem field. */
8631 if (i
.tm
.extension_opcode
!= None
)
8633 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8634 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8635 i
.tm
.opcode_modifier
.sse2avx
);
8639 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8640 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8641 i
.tm
.opcode_modifier
.sse2avx
);
8645 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8646 must set it to 3 to indicate this is a register operand
8647 in the regmem field. */
8648 if (!i
.mem_operands
)
8652 /* Fill in i.rm.reg field with extension opcode (if any). */
8653 if (i
.tm
.extension_opcode
!= None
)
8654 i
.rm
.reg
= i
.tm
.extension_opcode
;
8660 frag_opcode_byte (unsigned char byte
)
8662 if (now_seg
!= absolute_section
)
8663 FRAG_APPEND_1_CHAR (byte
);
8665 ++abs_section_offset
;
8669 flip_code16 (unsigned int code16
)
8671 gas_assert (i
.tm
.operands
== 1);
8673 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8674 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8675 || i
.tm
.operand_types
[0].bitfield
.disp32s
8676 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8681 output_branch (void)
8687 relax_substateT subtype
;
8691 if (now_seg
== absolute_section
)
8693 as_bad (_("relaxable branches not supported in absolute section"));
8697 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8698 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8701 if (i
.prefix
[DATA_PREFIX
] != 0)
8705 code16
^= flip_code16(code16
);
8707 /* Pentium4 branch hints. */
8708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8714 if (i
.prefix
[REX_PREFIX
] != 0)
8720 /* BND prefixed jump. */
8721 if (i
.prefix
[BND_PREFIX
] != 0)
8727 if (i
.prefixes
!= 0)
8728 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8730 /* It's always a symbol; End frag & setup for relax.
8731 Make sure there is enough room in this frag for the largest
8732 instruction we may generate in md_convert_frag. This is 2
8733 bytes for the opcode and room for the prefix and largest
8735 frag_grow (prefix
+ 2 + 4);
8736 /* Prefix and 1 opcode byte go in fr_fix. */
8737 p
= frag_more (prefix
+ 1);
8738 if (i
.prefix
[DATA_PREFIX
] != 0)
8739 *p
++ = DATA_PREFIX_OPCODE
;
8740 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8741 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8742 *p
++ = i
.prefix
[SEG_PREFIX
];
8743 if (i
.prefix
[BND_PREFIX
] != 0)
8744 *p
++ = BND_PREFIX_OPCODE
;
8745 if (i
.prefix
[REX_PREFIX
] != 0)
8746 *p
++ = i
.prefix
[REX_PREFIX
];
8747 *p
= i
.tm
.base_opcode
;
8749 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8750 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8751 else if (cpu_arch_flags
.bitfield
.cpui386
)
8752 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8754 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8757 sym
= i
.op
[0].disps
->X_add_symbol
;
8758 off
= i
.op
[0].disps
->X_add_number
;
8760 if (i
.op
[0].disps
->X_op
!= O_constant
8761 && i
.op
[0].disps
->X_op
!= O_symbol
)
8763 /* Handle complex expressions. */
8764 sym
= make_expr_symbol (i
.op
[0].disps
);
8768 /* 1 possible extra opcode + 4 byte displacement go in var part.
8769 Pass reloc in fr_var. */
8770 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8773 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8774 /* Return TRUE iff PLT32 relocation should be used for branching to
8778 need_plt32_p (symbolS
*s
)
8780 /* PLT32 relocation is ELF only. */
8785 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8786 krtld support it. */
8790 /* Since there is no need to prepare for PLT branch on x86-64, we
8791 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8792 be used as a marker for 32-bit PC-relative branches. */
8799 /* Weak or undefined symbol need PLT32 relocation. */
8800 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8803 /* Non-global symbol doesn't need PLT32 relocation. */
8804 if (! S_IS_EXTERNAL (s
))
8807 /* Other global symbols need PLT32 relocation. NB: Symbol with
8808 non-default visibilities are treated as normal global symbol
8809 so that PLT32 relocation can be used as a marker for 32-bit
8810 PC-relative branches. It is useful for linker relaxation. */
8821 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8823 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8825 /* This is a loop or jecxz type instruction. */
8827 if (i
.prefix
[ADDR_PREFIX
] != 0)
8829 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8832 /* Pentium4 branch hints. */
8833 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8834 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8836 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8845 if (flag_code
== CODE_16BIT
)
8848 if (i
.prefix
[DATA_PREFIX
] != 0)
8850 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8852 code16
^= flip_code16(code16
);
8860 /* BND prefixed jump. */
8861 if (i
.prefix
[BND_PREFIX
] != 0)
8863 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8867 if (i
.prefix
[REX_PREFIX
] != 0)
8869 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8873 if (i
.prefixes
!= 0)
8874 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8876 if (now_seg
== absolute_section
)
8878 abs_section_offset
+= i
.opcode_length
+ size
;
8882 p
= frag_more (i
.opcode_length
+ size
);
8883 switch (i
.opcode_length
)
8886 *p
++ = i
.tm
.base_opcode
>> 8;
8889 *p
++ = i
.tm
.base_opcode
;
8895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8897 && jump_reloc
== NO_RELOC
8898 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8899 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8902 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8904 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8905 i
.op
[0].disps
, 1, jump_reloc
);
8907 /* All jumps handled here are signed, but don't unconditionally use a
8908 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8909 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8914 fixP
->fx_signed
= 1;
8918 if (i
.tm
.base_opcode
== 0xc7f8)
8919 fixP
->fx_signed
= 1;
8923 if (flag_code
== CODE_64BIT
)
8924 fixP
->fx_signed
= 1;
8930 output_interseg_jump (void)
8938 if (flag_code
== CODE_16BIT
)
8942 if (i
.prefix
[DATA_PREFIX
] != 0)
8949 gas_assert (!i
.prefix
[REX_PREFIX
]);
8955 if (i
.prefixes
!= 0)
8956 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8958 if (now_seg
== absolute_section
)
8960 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8964 /* 1 opcode; 2 segment; offset */
8965 p
= frag_more (prefix
+ 1 + 2 + size
);
8967 if (i
.prefix
[DATA_PREFIX
] != 0)
8968 *p
++ = DATA_PREFIX_OPCODE
;
8970 if (i
.prefix
[REX_PREFIX
] != 0)
8971 *p
++ = i
.prefix
[REX_PREFIX
];
8973 *p
++ = i
.tm
.base_opcode
;
8974 if (i
.op
[1].imms
->X_op
== O_constant
)
8976 offsetT n
= i
.op
[1].imms
->X_add_number
;
8979 && !fits_in_unsigned_word (n
)
8980 && !fits_in_signed_word (n
))
8982 as_bad (_("16-bit jump out of range"));
8985 md_number_to_chars (p
, n
, size
);
8988 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8989 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8992 if (i
.op
[0].imms
->X_op
== O_constant
)
8993 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8995 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8996 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9004 asection
*seg
= now_seg
;
9005 subsegT subseg
= now_subseg
;
9007 unsigned int alignment
, align_size_1
;
9008 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9009 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9010 unsigned int padding
;
9012 if (!IS_ELF
|| !x86_used_note
)
9015 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9017 /* The .note.gnu.property section layout:
9019 Field Length Contents
9022 n_descsz 4 The note descriptor size
9023 n_type 4 NT_GNU_PROPERTY_TYPE_0
9025 n_desc n_descsz The program property array
9029 /* Create the .note.gnu.property section. */
9030 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9031 bfd_set_section_flags (sec
,
9038 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9049 bfd_set_section_alignment (sec
, alignment
);
9050 elf_section_type (sec
) = SHT_NOTE
;
9052 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9054 isa_1_descsz_raw
= 4 + 4 + 4;
9055 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9056 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9058 feature_2_descsz_raw
= isa_1_descsz
;
9059 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9061 feature_2_descsz_raw
+= 4 + 4 + 4;
9062 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9063 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9066 descsz
= feature_2_descsz
;
9067 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9068 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9070 /* Write n_namsz. */
9071 md_number_to_chars (p
, (valueT
) 4, 4);
9073 /* Write n_descsz. */
9074 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9077 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9080 memcpy (p
+ 4 * 3, "GNU", 4);
9082 /* Write 4-byte type. */
9083 md_number_to_chars (p
+ 4 * 4,
9084 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9086 /* Write 4-byte data size. */
9087 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9089 /* Write 4-byte data. */
9090 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9092 /* Zero out paddings. */
9093 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9095 memset (p
+ 4 * 7, 0, padding
);
9097 /* Write 4-byte type. */
9098 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9099 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9101 /* Write 4-byte data size. */
9102 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9104 /* Write 4-byte data. */
9105 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9106 (valueT
) x86_feature_2_used
, 4);
9108 /* Zero out paddings. */
9109 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9111 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9113 /* We probably can't restore the current segment, for there likely
9116 subseg_set (seg
, subseg
);
9121 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9122 const char *frag_now_ptr
)
9124 unsigned int len
= 0;
9126 if (start_frag
!= frag_now
)
9128 const fragS
*fr
= start_frag
;
9133 } while (fr
&& fr
!= frag_now
);
9136 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9139 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9140 be macro-fused with conditional jumps.
9141 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9142 or is one of the following format:
9155 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9157 /* No RIP address. */
9158 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9161 /* No opcodes outside of base encoding space. */
9162 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9165 /* add, sub without add/sub m, imm. */
9166 if (i
.tm
.base_opcode
<= 5
9167 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9168 || ((i
.tm
.base_opcode
| 3) == 0x83
9169 && (i
.tm
.extension_opcode
== 0x5
9170 || i
.tm
.extension_opcode
== 0x0)))
9172 *mf_cmp_p
= mf_cmp_alu_cmp
;
9173 return !(i
.mem_operands
&& i
.imm_operands
);
9176 /* and without and m, imm. */
9177 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9178 || ((i
.tm
.base_opcode
| 3) == 0x83
9179 && i
.tm
.extension_opcode
== 0x4))
9181 *mf_cmp_p
= mf_cmp_test_and
;
9182 return !(i
.mem_operands
&& i
.imm_operands
);
9185 /* test without test m imm. */
9186 if ((i
.tm
.base_opcode
| 1) == 0x85
9187 || (i
.tm
.base_opcode
| 1) == 0xa9
9188 || ((i
.tm
.base_opcode
| 1) == 0xf7
9189 && i
.tm
.extension_opcode
== 0))
9191 *mf_cmp_p
= mf_cmp_test_and
;
9192 return !(i
.mem_operands
&& i
.imm_operands
);
9195 /* cmp without cmp m, imm. */
9196 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9197 || ((i
.tm
.base_opcode
| 3) == 0x83
9198 && (i
.tm
.extension_opcode
== 0x7)))
9200 *mf_cmp_p
= mf_cmp_alu_cmp
;
9201 return !(i
.mem_operands
&& i
.imm_operands
);
9204 /* inc, dec without inc/dec m. */
9205 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9206 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9207 || ((i
.tm
.base_opcode
| 1) == 0xff
9208 && i
.tm
.extension_opcode
<= 0x1))
9210 *mf_cmp_p
= mf_cmp_incdec
;
9211 return !i
.mem_operands
;
9217 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9220 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9222 /* NB: Don't work with COND_JUMP86 without i386. */
9223 if (!align_branch_power
9224 || now_seg
== absolute_section
9225 || !cpu_arch_flags
.bitfield
.cpui386
9226 || !(align_branch
& align_branch_fused_bit
))
9229 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9231 if (last_insn
.kind
== last_insn_other
9232 || last_insn
.seg
!= now_seg
)
9235 as_warn_where (last_insn
.file
, last_insn
.line
,
9236 _("`%s` skips -malign-branch-boundary on `%s`"),
9237 last_insn
.name
, i
.tm
.name
);
9243 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9246 add_branch_prefix_frag_p (void)
9248 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9249 to PadLock instructions since they include prefixes in opcode. */
9250 if (!align_branch_power
9251 || !align_branch_prefix_size
9252 || now_seg
== absolute_section
9253 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9254 || !cpu_arch_flags
.bitfield
.cpui386
)
9257 /* Don't add prefix if it is a prefix or there is no operand in case
9258 that segment prefix is special. */
9259 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9262 if (last_insn
.kind
== last_insn_other
9263 || last_insn
.seg
!= now_seg
)
9267 as_warn_where (last_insn
.file
, last_insn
.line
,
9268 _("`%s` skips -malign-branch-boundary on `%s`"),
9269 last_insn
.name
, i
.tm
.name
);
9274 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9277 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9278 enum mf_jcc_kind
*mf_jcc_p
)
9282 /* NB: Don't work with COND_JUMP86 without i386. */
9283 if (!align_branch_power
9284 || now_seg
== absolute_section
9285 || !cpu_arch_flags
.bitfield
.cpui386
9286 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9291 /* Check for jcc and direct jmp. */
9292 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9294 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9296 *branch_p
= align_branch_jmp
;
9297 add_padding
= align_branch
& align_branch_jmp_bit
;
9301 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9302 igore the lowest bit. */
9303 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9304 *branch_p
= align_branch_jcc
;
9305 if ((align_branch
& align_branch_jcc_bit
))
9309 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9312 *branch_p
= align_branch_ret
;
9313 if ((align_branch
& align_branch_ret_bit
))
9318 /* Check for indirect jmp, direct and indirect calls. */
9319 if (i
.tm
.base_opcode
== 0xe8)
9322 *branch_p
= align_branch_call
;
9323 if ((align_branch
& align_branch_call_bit
))
9326 else if (i
.tm
.base_opcode
== 0xff
9327 && (i
.tm
.extension_opcode
== 2
9328 || i
.tm
.extension_opcode
== 4))
9330 /* Indirect call and jmp. */
9331 *branch_p
= align_branch_indirect
;
9332 if ((align_branch
& align_branch_indirect_bit
))
9339 && (i
.op
[0].disps
->X_op
== O_symbol
9340 || (i
.op
[0].disps
->X_op
== O_subtract
9341 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9343 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9344 /* No padding to call to global or undefined tls_get_addr. */
9345 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9346 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9352 && last_insn
.kind
!= last_insn_other
9353 && last_insn
.seg
== now_seg
)
9356 as_warn_where (last_insn
.file
, last_insn
.line
,
9357 _("`%s` skips -malign-branch-boundary on `%s`"),
9358 last_insn
.name
, i
.tm
.name
);
9368 fragS
*insn_start_frag
;
9369 offsetT insn_start_off
;
9370 fragS
*fragP
= NULL
;
9371 enum align_branch_kind branch
= align_branch_none
;
9372 /* The initializer is arbitrary just to avoid uninitialized error.
9373 it's actually either assigned in add_branch_padding_frag_p
9374 or never be used. */
9375 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9378 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9380 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9381 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9382 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9384 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9385 || i
.tm
.cpu_flags
.bitfield
.cpu287
9386 || i
.tm
.cpu_flags
.bitfield
.cpu387
9387 || i
.tm
.cpu_flags
.bitfield
.cpu687
9388 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9389 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9391 if ((i
.xstate
& xstate_mmx
)
9392 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9393 && !is_any_vex_encoding (&i
.tm
)
9394 && (i
.tm
.base_opcode
== 0x77 /* emms */
9395 || i
.tm
.base_opcode
== 0x0e /* femms */)))
9396 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9400 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9401 i
.xstate
|= xstate_zmm
;
9402 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9403 i
.xstate
|= xstate_ymm
;
9404 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9405 i
.xstate
|= xstate_xmm
;
9408 /* vzeroall / vzeroupper */
9409 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9410 i
.xstate
|= xstate_ymm
;
9412 if ((i
.xstate
& xstate_xmm
)
9413 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9414 || (i
.tm
.base_opcode
== 0xae
9415 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9416 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9417 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9418 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9419 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9421 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9422 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9423 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9424 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9425 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9426 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9427 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9428 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9429 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9430 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9431 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9432 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9433 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9434 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9436 if (x86_feature_2_used
9437 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9438 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9439 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9440 && i
.tm
.base_opcode
== 0xc7
9441 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9442 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9443 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9444 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9445 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9446 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9447 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9448 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9449 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9450 /* LAHF-SAHF insns in 64-bit mode. */
9451 || (flag_code
== CODE_64BIT
9452 && (i
.tm
.base_opcode
| 1) == 0x9f
9453 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9454 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9455 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9456 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9457 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9458 CpuAVX512DQ, LPW, TBM and AMX. */
9459 || (i
.tm
.opcode_modifier
.vex
9460 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9461 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9462 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9463 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9464 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9465 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9466 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9467 || i
.tm
.cpu_flags
.bitfield
.cpufma
9468 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9469 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9470 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9471 || (x86_feature_2_used
9472 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9473 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9474 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9475 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9476 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9477 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9478 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9479 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9480 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9482 || (i
.tm
.opcode_modifier
.evex
9483 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9484 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9485 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9486 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9490 /* Tie dwarf2 debug info to the address at the start of the insn.
9491 We can't do this after the insn has been output as the current
9492 frag may have been closed off. eg. by frag_var. */
9493 dwarf2_emit_insn (0);
9495 insn_start_frag
= frag_now
;
9496 insn_start_off
= frag_now_fix ();
9498 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9501 /* Branch can be 8 bytes. Leave some room for prefixes. */
9502 unsigned int max_branch_padding_size
= 14;
9504 /* Align section to boundary. */
9505 record_alignment (now_seg
, align_branch_power
);
9507 /* Make room for padding. */
9508 frag_grow (max_branch_padding_size
);
9510 /* Start of the padding. */
9515 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9516 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9519 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9520 fragP
->tc_frag_data
.branch_type
= branch
;
9521 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9525 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9527 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9528 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9530 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9531 output_interseg_jump ();
9534 /* Output normal instructions here. */
9538 enum mf_cmp_kind mf_cmp
;
9541 && (i
.tm
.base_opcode
== 0xaee8
9542 || i
.tm
.base_opcode
== 0xaef0
9543 || i
.tm
.base_opcode
== 0xaef8))
9545 /* Encode lfence, mfence, and sfence as
9546 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9547 if (now_seg
!= absolute_section
)
9549 offsetT val
= 0x240483f0ULL
;
9552 md_number_to_chars (p
, val
, 5);
9555 abs_section_offset
+= 5;
9559 /* Some processors fail on LOCK prefix. This options makes
9560 assembler ignore LOCK prefix and serves as a workaround. */
9561 if (omit_lock_prefix
)
9563 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9564 && i
.tm
.opcode_modifier
.isprefix
)
9566 i
.prefix
[LOCK_PREFIX
] = 0;
9570 /* Skip if this is a branch. */
9572 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9574 /* Make room for padding. */
9575 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9580 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9581 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9584 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9585 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9586 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9588 else if (add_branch_prefix_frag_p ())
9590 unsigned int max_prefix_size
= align_branch_prefix_size
;
9592 /* Make room for padding. */
9593 frag_grow (max_prefix_size
);
9598 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9599 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9602 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9605 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9606 don't need the explicit prefix. */
9607 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9609 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9618 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9619 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9623 switch (i
.opcode_length
)
9628 /* Check for pseudo prefixes. */
9629 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9631 as_bad_where (insn_start_frag
->fr_file
,
9632 insn_start_frag
->fr_line
,
9633 _("pseudo prefix without instruction"));
9643 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9644 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9645 R_X86_64_GOTTPOFF relocation so that linker can safely
9646 perform IE->LE optimization. A dummy REX_OPCODE prefix
9647 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9648 relocation for GDesc -> IE/LE optimization. */
9649 if (x86_elf_abi
== X86_64_X32_ABI
9651 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9652 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9653 && i
.prefix
[REX_PREFIX
] == 0)
9654 add_prefix (REX_OPCODE
);
9657 /* The prefix bytes. */
9658 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9660 frag_opcode_byte (*q
);
9664 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9670 frag_opcode_byte (*q
);
9673 /* There should be no other prefixes for instructions
9678 /* For EVEX instructions i.vrex should become 0 after
9679 build_evex_prefix. For VEX instructions upper 16 registers
9680 aren't available, so VREX should be 0. */
9683 /* Now the VEX prefix. */
9684 if (now_seg
!= absolute_section
)
9686 p
= frag_more (i
.vex
.length
);
9687 for (j
= 0; j
< i
.vex
.length
; j
++)
9688 p
[j
] = i
.vex
.bytes
[j
];
9691 abs_section_offset
+= i
.vex
.length
;
9694 /* Now the opcode; be careful about word order here! */
9695 j
= i
.opcode_length
;
9697 switch (i
.tm
.opcode_modifier
.opcodespace
)
9712 if (now_seg
== absolute_section
)
9713 abs_section_offset
+= j
;
9716 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9722 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9725 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9726 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9730 switch (i
.opcode_length
)
9733 /* Put out high byte first: can't use md_number_to_chars! */
9734 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9737 *p
= i
.tm
.base_opcode
& 0xff;
9746 /* Now the modrm byte and sib byte (if present). */
9747 if (i
.tm
.opcode_modifier
.modrm
)
9749 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9751 | (i
.rm
.mode
<< 6));
9752 /* If i.rm.regmem == ESP (4)
9753 && i.rm.mode != (Register mode)
9755 ==> need second modrm byte. */
9756 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9758 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9759 frag_opcode_byte ((i
.sib
.base
<< 0)
9760 | (i
.sib
.index
<< 3)
9761 | (i
.sib
.scale
<< 6));
9764 if (i
.disp_operands
)
9765 output_disp (insn_start_frag
, insn_start_off
);
9768 output_imm (insn_start_frag
, insn_start_off
);
9771 * frag_now_fix () returning plain abs_section_offset when we're in the
9772 * absolute section, and abs_section_offset not getting updated as data
9773 * gets added to the frag breaks the logic below.
9775 if (now_seg
!= absolute_section
)
9777 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9779 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9783 /* NB: Don't add prefix with GOTPC relocation since
9784 output_disp() above depends on the fixed encoding
9785 length. Can't add prefix with TLS relocation since
9786 it breaks TLS linker optimization. */
9787 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9788 /* Prefix count on the current instruction. */
9789 unsigned int count
= i
.vex
.length
;
9791 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9792 /* REX byte is encoded in VEX/EVEX prefix. */
9793 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9796 /* Count prefixes for extended opcode maps. */
9798 switch (i
.tm
.opcode_modifier
.opcodespace
)
9813 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9816 /* Set the maximum prefix size in BRANCH_PREFIX
9818 if (fragP
->tc_frag_data
.max_bytes
> max
)
9819 fragP
->tc_frag_data
.max_bytes
= max
;
9820 if (fragP
->tc_frag_data
.max_bytes
> count
)
9821 fragP
->tc_frag_data
.max_bytes
-= count
;
9823 fragP
->tc_frag_data
.max_bytes
= 0;
9827 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9829 unsigned int max_prefix_size
;
9830 if (align_branch_prefix_size
> max
)
9831 max_prefix_size
= max
;
9833 max_prefix_size
= align_branch_prefix_size
;
9834 if (max_prefix_size
> count
)
9835 fragP
->tc_frag_data
.max_prefix_length
9836 = max_prefix_size
- count
;
9839 /* Use existing segment prefix if possible. Use CS
9840 segment prefix in 64-bit mode. In 32-bit mode, use SS
9841 segment prefix with ESP/EBP base register and use DS
9842 segment prefix without ESP/EBP base register. */
9843 if (i
.prefix
[SEG_PREFIX
])
9844 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9845 else if (flag_code
== CODE_64BIT
)
9846 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9848 && (i
.base_reg
->reg_num
== 4
9849 || i
.base_reg
->reg_num
== 5))
9850 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9852 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9857 /* NB: Don't work with COND_JUMP86 without i386. */
9858 if (align_branch_power
9859 && now_seg
!= absolute_section
9860 && cpu_arch_flags
.bitfield
.cpui386
)
9862 /* Terminate each frag so that we can add prefix and check for
9864 frag_wane (frag_now
);
9871 pi ("" /*line*/, &i
);
9873 #endif /* DEBUG386 */
9876 /* Return the size of the displacement operand N. */
9879 disp_size (unsigned int n
)
9883 if (i
.types
[n
].bitfield
.disp64
)
9885 else if (i
.types
[n
].bitfield
.disp8
)
9887 else if (i
.types
[n
].bitfield
.disp16
)
9892 /* Return the size of the immediate operand N. */
9895 imm_size (unsigned int n
)
9898 if (i
.types
[n
].bitfield
.imm64
)
9900 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9902 else if (i
.types
[n
].bitfield
.imm16
)
9908 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9913 for (n
= 0; n
< i
.operands
; n
++)
9915 if (operand_type_check (i
.types
[n
], disp
))
9917 int size
= disp_size (n
);
9919 if (now_seg
== absolute_section
)
9920 abs_section_offset
+= size
;
9921 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9923 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9925 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9927 p
= frag_more (size
);
9928 md_number_to_chars (p
, val
, size
);
9932 enum bfd_reloc_code_real reloc_type
;
9933 int sign
= i
.types
[n
].bitfield
.disp32s
;
9934 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9937 /* We can't have 8 bit displacement here. */
9938 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9940 /* The PC relative address is computed relative
9941 to the instruction boundary, so in case immediate
9942 fields follows, we need to adjust the value. */
9943 if (pcrel
&& i
.imm_operands
)
9948 for (n1
= 0; n1
< i
.operands
; n1
++)
9949 if (operand_type_check (i
.types
[n1
], imm
))
9951 /* Only one immediate is allowed for PC
9952 relative address. */
9953 gas_assert (sz
== 0);
9955 i
.op
[n
].disps
->X_add_number
-= sz
;
9957 /* We should find the immediate. */
9958 gas_assert (sz
!= 0);
9961 p
= frag_more (size
);
9962 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9964 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9965 && (((reloc_type
== BFD_RELOC_32
9966 || reloc_type
== BFD_RELOC_X86_64_32S
9967 || (reloc_type
== BFD_RELOC_64
9969 && (i
.op
[n
].disps
->X_op
== O_symbol
9970 || (i
.op
[n
].disps
->X_op
== O_add
9971 && ((symbol_get_value_expression
9972 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9974 || reloc_type
== BFD_RELOC_32_PCREL
))
9978 reloc_type
= BFD_RELOC_386_GOTPC
;
9979 i
.has_gotpc_tls_reloc
= true;
9980 i
.op
[n
].disps
->X_add_number
+=
9981 encoding_length (insn_start_frag
, insn_start_off
, p
);
9983 else if (reloc_type
== BFD_RELOC_64
)
9984 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9986 /* Don't do the adjustment for x86-64, as there
9987 the pcrel addressing is relative to the _next_
9988 insn, and that is taken care of in other code. */
9989 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9991 else if (align_branch_power
)
9995 case BFD_RELOC_386_TLS_GD
:
9996 case BFD_RELOC_386_TLS_LDM
:
9997 case BFD_RELOC_386_TLS_IE
:
9998 case BFD_RELOC_386_TLS_IE_32
:
9999 case BFD_RELOC_386_TLS_GOTIE
:
10000 case BFD_RELOC_386_TLS_GOTDESC
:
10001 case BFD_RELOC_386_TLS_DESC_CALL
:
10002 case BFD_RELOC_X86_64_TLSGD
:
10003 case BFD_RELOC_X86_64_TLSLD
:
10004 case BFD_RELOC_X86_64_GOTTPOFF
:
10005 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10006 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10007 i
.has_gotpc_tls_reloc
= true;
10012 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10013 size
, i
.op
[n
].disps
, pcrel
,
10016 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10017 && !i
.prefix
[ADDR_PREFIX
])
10018 fixP
->fx_signed
= 1;
10020 /* Check for "call/jmp *mem", "mov mem, %reg",
10021 "test %reg, mem" and "binop mem, %reg" where binop
10022 is one of adc, add, and, cmp, or, sbb, sub, xor
10023 instructions without data prefix. Always generate
10024 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10025 if (i
.prefix
[DATA_PREFIX
] == 0
10026 && (generate_relax_relocations
10029 && i
.rm
.regmem
== 5))
10031 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10032 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10033 && ((i
.operands
== 1
10034 && i
.tm
.base_opcode
== 0xff
10035 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10036 || (i
.operands
== 2
10037 && (i
.tm
.base_opcode
== 0x8b
10038 || i
.tm
.base_opcode
== 0x85
10039 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10043 fixP
->fx_tcbit
= i
.rex
!= 0;
10045 && (i
.base_reg
->reg_num
== RegIP
))
10046 fixP
->fx_tcbit2
= 1;
10049 fixP
->fx_tcbit2
= 1;
10057 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10062 for (n
= 0; n
< i
.operands
; n
++)
10064 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
10065 if (i
.rounding
.type
!= rc_none
&& n
== i
.rounding
.operand
)
10068 if (operand_type_check (i
.types
[n
], imm
))
10070 int size
= imm_size (n
);
10072 if (now_seg
== absolute_section
)
10073 abs_section_offset
+= size
;
10074 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10078 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10080 p
= frag_more (size
);
10081 md_number_to_chars (p
, val
, size
);
10085 /* Not absolute_section.
10086 Need a 32-bit fixup (don't support 8bit
10087 non-absolute imms). Try to support other
10089 enum bfd_reloc_code_real reloc_type
;
10092 if (i
.types
[n
].bitfield
.imm32s
10093 && (i
.suffix
== QWORD_MNEM_SUFFIX
10094 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10099 p
= frag_more (size
);
10100 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10102 /* This is tough to explain. We end up with this one if we
10103 * have operands that look like
10104 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10105 * obtain the absolute address of the GOT, and it is strongly
10106 * preferable from a performance point of view to avoid using
10107 * a runtime relocation for this. The actual sequence of
10108 * instructions often look something like:
10113 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10115 * The call and pop essentially return the absolute address
10116 * of the label .L66 and store it in %ebx. The linker itself
10117 * will ultimately change the first operand of the addl so
10118 * that %ebx points to the GOT, but to keep things simple, the
10119 * .o file must have this operand set so that it generates not
10120 * the absolute address of .L66, but the absolute address of
10121 * itself. This allows the linker itself simply treat a GOTPC
10122 * relocation as asking for a pcrel offset to the GOT to be
10123 * added in, and the addend of the relocation is stored in the
10124 * operand field for the instruction itself.
10126 * Our job here is to fix the operand so that it would add
10127 * the correct offset so that %ebx would point to itself. The
10128 * thing that is tricky is that .-.L66 will point to the
10129 * beginning of the instruction, so we need to further modify
10130 * the operand so that it will point to itself. There are
10131 * other cases where you have something like:
10133 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10135 * and here no correction would be required. Internally in
10136 * the assembler we treat operands of this form as not being
10137 * pcrel since the '.' is explicitly mentioned, and I wonder
10138 * whether it would simplify matters to do it this way. Who
10139 * knows. In earlier versions of the PIC patches, the
10140 * pcrel_adjust field was used to store the correction, but
10141 * since the expression is not pcrel, I felt it would be
10142 * confusing to do it this way. */
10144 if ((reloc_type
== BFD_RELOC_32
10145 || reloc_type
== BFD_RELOC_X86_64_32S
10146 || reloc_type
== BFD_RELOC_64
)
10148 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10149 && (i
.op
[n
].imms
->X_op
== O_symbol
10150 || (i
.op
[n
].imms
->X_op
== O_add
10151 && ((symbol_get_value_expression
10152 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10156 reloc_type
= BFD_RELOC_386_GOTPC
;
10157 else if (size
== 4)
10158 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10159 else if (size
== 8)
10160 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10161 i
.has_gotpc_tls_reloc
= true;
10162 i
.op
[n
].imms
->X_add_number
+=
10163 encoding_length (insn_start_frag
, insn_start_off
, p
);
10165 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10166 i
.op
[n
].imms
, 0, reloc_type
);
10172 /* x86_cons_fix_new is called via the expression parsing code when a
10173 reloc is needed. We use this hook to get the correct .got reloc. */
10174 static int cons_sign
= -1;
10177 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10178 expressionS
*exp
, bfd_reloc_code_real_type r
)
10180 r
= reloc (len
, 0, cons_sign
, r
);
10183 if (exp
->X_op
== O_secrel
)
10185 exp
->X_op
= O_symbol
;
10186 r
= BFD_RELOC_32_SECREL
;
10190 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10193 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10194 purpose of the `.dc.a' internal pseudo-op. */
10197 x86_address_bytes (void)
10199 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10201 return stdoutput
->arch_info
->bits_per_address
/ 8;
10204 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10205 || defined (LEX_AT)) && !defined (TE_PE)
10206 # define lex_got(reloc, adjust, types) NULL
10208 /* Parse operands of the form
10209 <symbol>@GOTOFF+<nnn>
10210 and similar .plt or .got references.
10212 If we find one, set up the correct relocation in RELOC and copy the
10213 input string, minus the `@GOTOFF' into a malloc'd buffer for
10214 parsing by the calling routine. Return this buffer, and if ADJUST
10215 is non-null set it to the length of the string we removed from the
10216 input line. Otherwise return NULL. */
10218 lex_got (enum bfd_reloc_code_real
*rel
,
10220 i386_operand_type
*types
)
10222 /* Some of the relocations depend on the size of what field is to
10223 be relocated. But in our callers i386_immediate and i386_displacement
10224 we don't yet know the operand size (this will be set by insn
10225 matching). Hence we record the word32 relocation here,
10226 and adjust the reloc according to the real size in reloc(). */
10227 static const struct {
10230 const enum bfd_reloc_code_real rel
[2];
10231 const i386_operand_type types64
;
10232 bool need_GOT_symbol
;
10235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10236 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10237 BFD_RELOC_SIZE32
},
10238 OPERAND_TYPE_IMM32_64
, false },
10240 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10241 BFD_RELOC_X86_64_PLTOFF64
},
10242 OPERAND_TYPE_IMM64
, true },
10243 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10244 BFD_RELOC_X86_64_PLT32
},
10245 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10246 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10247 BFD_RELOC_X86_64_GOTPLT64
},
10248 OPERAND_TYPE_IMM64_DISP64
, true },
10249 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10250 BFD_RELOC_X86_64_GOTOFF64
},
10251 OPERAND_TYPE_IMM64_DISP64
, true },
10252 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10253 BFD_RELOC_X86_64_GOTPCREL
},
10254 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10255 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10256 BFD_RELOC_X86_64_TLSGD
},
10257 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10258 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10259 _dummy_first_bfd_reloc_code_real
},
10260 OPERAND_TYPE_NONE
, true },
10261 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10262 BFD_RELOC_X86_64_TLSLD
},
10263 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10264 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10265 BFD_RELOC_X86_64_GOTTPOFF
},
10266 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10267 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10268 BFD_RELOC_X86_64_TPOFF32
},
10269 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10270 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10271 _dummy_first_bfd_reloc_code_real
},
10272 OPERAND_TYPE_NONE
, true },
10273 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10274 BFD_RELOC_X86_64_DTPOFF32
},
10275 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10276 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10277 _dummy_first_bfd_reloc_code_real
},
10278 OPERAND_TYPE_NONE
, true },
10279 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10280 _dummy_first_bfd_reloc_code_real
},
10281 OPERAND_TYPE_NONE
, true },
10282 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10283 BFD_RELOC_X86_64_GOT32
},
10284 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10285 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10286 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10287 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10288 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10289 BFD_RELOC_X86_64_TLSDESC_CALL
},
10290 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10292 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10293 BFD_RELOC_32_SECREL
},
10294 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10300 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10305 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10306 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10309 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10311 int len
= gotrel
[j
].len
;
10312 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10314 if (gotrel
[j
].rel
[object_64bit
] != 0)
10317 char *tmpbuf
, *past_reloc
;
10319 *rel
= gotrel
[j
].rel
[object_64bit
];
10323 if (flag_code
!= CODE_64BIT
)
10325 types
->bitfield
.imm32
= 1;
10326 types
->bitfield
.disp32
= 1;
10329 *types
= gotrel
[j
].types64
;
10332 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10333 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10335 /* The length of the first part of our input line. */
10336 first
= cp
- input_line_pointer
;
10338 /* The second part goes from after the reloc token until
10339 (and including) an end_of_line char or comma. */
10340 past_reloc
= cp
+ 1 + len
;
10342 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10344 second
= cp
+ 1 - past_reloc
;
10346 /* Allocate and copy string. The trailing NUL shouldn't
10347 be necessary, but be safe. */
10348 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10349 memcpy (tmpbuf
, input_line_pointer
, first
);
10350 if (second
!= 0 && *past_reloc
!= ' ')
10351 /* Replace the relocation token with ' ', so that
10352 errors like foo@GOTOFF1 will be detected. */
10353 tmpbuf
[first
++] = ' ';
10355 /* Increment length by 1 if the relocation token is
10360 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10361 tmpbuf
[first
+ second
] = '\0';
10365 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10366 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10371 /* Might be a symbol version string. Don't as_bad here. */
10376 bfd_reloc_code_real_type
10377 x86_cons (expressionS
*exp
, int size
)
10379 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10381 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10382 && !defined (LEX_AT)) \
10384 intel_syntax
= -intel_syntax
;
10387 if (size
== 4 || (object_64bit
&& size
== 8))
10389 /* Handle @GOTOFF and the like in an expression. */
10391 char *gotfree_input_line
;
10394 save
= input_line_pointer
;
10395 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10396 if (gotfree_input_line
)
10397 input_line_pointer
= gotfree_input_line
;
10401 if (gotfree_input_line
)
10403 /* expression () has merrily parsed up to the end of line,
10404 or a comma - in the wrong buffer. Transfer how far
10405 input_line_pointer has moved to the right buffer. */
10406 input_line_pointer
= (save
10407 + (input_line_pointer
- gotfree_input_line
)
10409 free (gotfree_input_line
);
10410 if (exp
->X_op
== O_constant
10411 || exp
->X_op
== O_absent
10412 || exp
->X_op
== O_illegal
10413 || exp
->X_op
== O_register
10414 || exp
->X_op
== O_big
)
10416 char c
= *input_line_pointer
;
10417 *input_line_pointer
= 0;
10418 as_bad (_("missing or invalid expression `%s'"), save
);
10419 *input_line_pointer
= c
;
10421 else if ((got_reloc
== BFD_RELOC_386_PLT32
10422 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10423 && exp
->X_op
!= O_symbol
)
10425 char c
= *input_line_pointer
;
10426 *input_line_pointer
= 0;
10427 as_bad (_("invalid PLT expression `%s'"), save
);
10428 *input_line_pointer
= c
;
10435 intel_syntax
= -intel_syntax
;
10438 i386_intel_simplify (exp
);
10443 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10444 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10445 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10451 signed_cons (int size
)
10461 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10468 if (exp
.X_op
== O_symbol
)
10469 exp
.X_op
= O_secrel
;
10471 emit_expr (&exp
, 4);
10473 while (*input_line_pointer
++ == ',');
10475 input_line_pointer
--;
10476 demand_empty_rest_of_line ();
10480 /* Handle Vector operations. */
10483 check_VecOperations (char *op_string
)
10485 const reg_entry
*mask
;
10492 if (*op_string
== '{')
10496 /* Check broadcasts. */
10497 if (startswith (op_string
, "1to"))
10499 unsigned int bcst_type
;
10501 if (i
.broadcast
.type
)
10502 goto duplicated_vec_op
;
10505 if (*op_string
== '8')
10507 else if (*op_string
== '4')
10509 else if (*op_string
== '2')
10511 else if (*op_string
== '1'
10512 && *(op_string
+1) == '6')
10519 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10524 i
.broadcast
.type
= bcst_type
;
10525 i
.broadcast
.operand
= this_operand
;
10527 /* Check masking operation. */
10528 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10530 if (mask
== &bad_reg
)
10533 /* k0 can't be used for write mask. */
10534 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10536 as_bad (_("`%s%s' can't be used for write mask"),
10537 register_prefix
, mask
->reg_name
);
10544 i
.mask
.operand
= this_operand
;
10546 else if (i
.mask
.reg
->reg_num
)
10547 goto duplicated_vec_op
;
10552 /* Only "{z}" is allowed here. No need to check
10553 zeroing mask explicitly. */
10554 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10556 as_bad (_("invalid write mask `%s'"), saved
);
10561 op_string
= end_op
;
10563 /* Check zeroing-flag for masking operation. */
10564 else if (*op_string
== 'z')
10568 i
.mask
.reg
= reg_k0
;
10569 i
.mask
.zeroing
= 1;
10570 i
.mask
.operand
= this_operand
;
10574 if (i
.mask
.zeroing
)
10577 as_bad (_("duplicated `%s'"), saved
);
10581 i
.mask
.zeroing
= 1;
10583 /* Only "{%k}" is allowed here. No need to check mask
10584 register explicitly. */
10585 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10587 as_bad (_("invalid zeroing-masking `%s'"),
10596 goto unknown_vec_op
;
10598 if (*op_string
!= '}')
10600 as_bad (_("missing `}' in `%s'"), saved
);
10605 /* Strip whitespace since the addition of pseudo prefixes
10606 changed how the scrubber treats '{'. */
10607 if (is_space_char (*op_string
))
10613 /* We don't know this one. */
10614 as_bad (_("unknown vector operation: `%s'"), saved
);
10618 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10620 as_bad (_("zeroing-masking only allowed with write mask"));
10628 i386_immediate (char *imm_start
)
10630 char *save_input_line_pointer
;
10631 char *gotfree_input_line
;
10634 i386_operand_type types
;
10636 operand_type_set (&types
, ~0);
10638 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10640 as_bad (_("at most %d immediate operands are allowed"),
10641 MAX_IMMEDIATE_OPERANDS
);
10645 exp
= &im_expressions
[i
.imm_operands
++];
10646 i
.op
[this_operand
].imms
= exp
;
10648 if (is_space_char (*imm_start
))
10651 save_input_line_pointer
= input_line_pointer
;
10652 input_line_pointer
= imm_start
;
10654 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10655 if (gotfree_input_line
)
10656 input_line_pointer
= gotfree_input_line
;
10658 exp_seg
= expression (exp
);
10660 SKIP_WHITESPACE ();
10661 if (*input_line_pointer
)
10662 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10664 input_line_pointer
= save_input_line_pointer
;
10665 if (gotfree_input_line
)
10667 free (gotfree_input_line
);
10669 if (exp
->X_op
== O_constant
)
10670 exp
->X_op
= O_illegal
;
10673 if (exp_seg
== reg_section
)
10675 as_bad (_("illegal immediate register operand %s"), imm_start
);
10679 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10683 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10684 i386_operand_type types
, const char *imm_start
)
10686 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10689 as_bad (_("missing or invalid immediate expression `%s'"),
10693 else if (exp
->X_op
== O_constant
)
10695 /* Size it properly later. */
10696 i
.types
[this_operand
].bitfield
.imm64
= 1;
10698 /* If not 64bit, sign/zero extend val, to account for wraparound
10700 if (flag_code
!= CODE_64BIT
)
10701 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10703 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10704 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10705 && exp_seg
!= absolute_section
10706 && exp_seg
!= text_section
10707 && exp_seg
!= data_section
10708 && exp_seg
!= bss_section
10709 && exp_seg
!= undefined_section
10710 && !bfd_is_com_section (exp_seg
))
10712 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10718 /* This is an address. The size of the address will be
10719 determined later, depending on destination register,
10720 suffix, or the default for the section. */
10721 i
.types
[this_operand
].bitfield
.imm8
= 1;
10722 i
.types
[this_operand
].bitfield
.imm16
= 1;
10723 i
.types
[this_operand
].bitfield
.imm32
= 1;
10724 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10725 i
.types
[this_operand
].bitfield
.imm64
= 1;
10726 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10734 i386_scale (char *scale
)
10737 char *save
= input_line_pointer
;
10739 input_line_pointer
= scale
;
10740 val
= get_absolute_expression ();
10745 i
.log2_scale_factor
= 0;
10748 i
.log2_scale_factor
= 1;
10751 i
.log2_scale_factor
= 2;
10754 i
.log2_scale_factor
= 3;
10758 char sep
= *input_line_pointer
;
10760 *input_line_pointer
= '\0';
10761 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10763 *input_line_pointer
= sep
;
10764 input_line_pointer
= save
;
10768 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10770 as_warn (_("scale factor of %d without an index register"),
10771 1 << i
.log2_scale_factor
);
10772 i
.log2_scale_factor
= 0;
10774 scale
= input_line_pointer
;
10775 input_line_pointer
= save
;
10780 i386_displacement (char *disp_start
, char *disp_end
)
10784 char *save_input_line_pointer
;
10785 char *gotfree_input_line
;
10787 i386_operand_type bigdisp
, types
= anydisp
;
10790 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10792 as_bad (_("at most %d displacement operands are allowed"),
10793 MAX_MEMORY_OPERANDS
);
10797 operand_type_set (&bigdisp
, 0);
10799 || i
.types
[this_operand
].bitfield
.baseindex
10800 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10801 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10803 i386_addressing_mode ();
10804 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10805 if (flag_code
== CODE_64BIT
)
10809 bigdisp
.bitfield
.disp32s
= 1;
10810 bigdisp
.bitfield
.disp64
= 1;
10813 bigdisp
.bitfield
.disp32
= 1;
10815 else if ((flag_code
== CODE_16BIT
) ^ override
)
10816 bigdisp
.bitfield
.disp16
= 1;
10818 bigdisp
.bitfield
.disp32
= 1;
10822 /* For PC-relative branches, the width of the displacement may be
10823 dependent upon data size, but is never dependent upon address size.
10824 Also make sure to not unintentionally match against a non-PC-relative
10825 branch template. */
10826 static templates aux_templates
;
10827 const insn_template
*t
= current_templates
->start
;
10828 bool has_intel64
= false;
10830 aux_templates
.start
= t
;
10831 while (++t
< current_templates
->end
)
10833 if (t
->opcode_modifier
.jump
10834 != current_templates
->start
->opcode_modifier
.jump
)
10836 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10837 has_intel64
= true;
10839 if (t
< current_templates
->end
)
10841 aux_templates
.end
= t
;
10842 current_templates
= &aux_templates
;
10845 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10846 if (flag_code
== CODE_64BIT
)
10848 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10849 && (!intel64
|| !has_intel64
))
10850 bigdisp
.bitfield
.disp16
= 1;
10852 bigdisp
.bitfield
.disp32s
= 1;
10857 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10859 : LONG_MNEM_SUFFIX
));
10860 bigdisp
.bitfield
.disp32
= 1;
10861 if ((flag_code
== CODE_16BIT
) ^ override
)
10863 bigdisp
.bitfield
.disp32
= 0;
10864 bigdisp
.bitfield
.disp16
= 1;
10868 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10871 exp
= &disp_expressions
[i
.disp_operands
];
10872 i
.op
[this_operand
].disps
= exp
;
10874 save_input_line_pointer
= input_line_pointer
;
10875 input_line_pointer
= disp_start
;
10876 END_STRING_AND_SAVE (disp_end
);
10878 #ifndef GCC_ASM_O_HACK
10879 #define GCC_ASM_O_HACK 0
10882 END_STRING_AND_SAVE (disp_end
+ 1);
10883 if (i
.types
[this_operand
].bitfield
.baseIndex
10884 && displacement_string_end
[-1] == '+')
10886 /* This hack is to avoid a warning when using the "o"
10887 constraint within gcc asm statements.
10890 #define _set_tssldt_desc(n,addr,limit,type) \
10891 __asm__ __volatile__ ( \
10892 "movw %w2,%0\n\t" \
10893 "movw %w1,2+%0\n\t" \
10894 "rorl $16,%1\n\t" \
10895 "movb %b1,4+%0\n\t" \
10896 "movb %4,5+%0\n\t" \
10897 "movb $0,6+%0\n\t" \
10898 "movb %h1,7+%0\n\t" \
10900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10902 This works great except that the output assembler ends
10903 up looking a bit weird if it turns out that there is
10904 no offset. You end up producing code that looks like:
10917 So here we provide the missing zero. */
10919 *displacement_string_end
= '0';
10922 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10923 if (gotfree_input_line
)
10924 input_line_pointer
= gotfree_input_line
;
10926 exp_seg
= expression (exp
);
10928 SKIP_WHITESPACE ();
10929 if (*input_line_pointer
)
10930 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10932 RESTORE_END_STRING (disp_end
+ 1);
10934 input_line_pointer
= save_input_line_pointer
;
10935 if (gotfree_input_line
)
10937 free (gotfree_input_line
);
10939 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10940 exp
->X_op
= O_illegal
;
10943 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10945 RESTORE_END_STRING (disp_end
);
10951 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10952 i386_operand_type types
, const char *disp_start
)
10954 i386_operand_type bigdisp
;
10957 /* We do this to make sure that the section symbol is in
10958 the symbol table. We will ultimately change the relocation
10959 to be relative to the beginning of the section. */
10960 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10961 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10962 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10964 if (exp
->X_op
!= O_symbol
)
10967 if (S_IS_LOCAL (exp
->X_add_symbol
)
10968 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10969 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10970 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10971 exp
->X_op
= O_subtract
;
10972 exp
->X_op_symbol
= GOT_symbol
;
10973 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10974 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10975 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10976 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10978 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10981 else if (exp
->X_op
== O_absent
10982 || exp
->X_op
== O_illegal
10983 || exp
->X_op
== O_big
)
10986 as_bad (_("missing or invalid displacement expression `%s'"),
10991 else if (exp
->X_op
== O_constant
)
10993 /* Sizing gets taken care of by optimize_disp().
10995 If not 64bit, sign/zero extend val, to account for wraparound
10997 if (flag_code
!= CODE_64BIT
)
10998 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11001 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11002 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11003 && exp_seg
!= absolute_section
11004 && exp_seg
!= text_section
11005 && exp_seg
!= data_section
11006 && exp_seg
!= bss_section
11007 && exp_seg
!= undefined_section
11008 && !bfd_is_com_section (exp_seg
))
11010 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11015 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
11016 i
.types
[this_operand
].bitfield
.disp8
= 1;
11018 /* Check if this is a displacement only operand. */
11019 bigdisp
= operand_type_and_not (i
.types
[this_operand
], anydisp
);
11020 if (operand_type_all_zero (&bigdisp
))
11021 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11027 /* Return the active addressing mode, taking address override and
11028 registers forming the address into consideration. Update the
11029 address override prefix if necessary. */
11031 static enum flag_code
11032 i386_addressing_mode (void)
11034 enum flag_code addr_mode
;
11036 if (i
.prefix
[ADDR_PREFIX
])
11037 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11038 else if (flag_code
== CODE_16BIT
11039 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11040 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11041 from md_assemble() by "is not a valid base/index expression"
11042 when there is a base and/or index. */
11043 && !i
.types
[this_operand
].bitfield
.baseindex
)
11045 /* MPX insn memory operands with neither base nor index must be forced
11046 to use 32-bit addressing in 16-bit mode. */
11047 addr_mode
= CODE_32BIT
;
11048 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11050 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11051 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11055 addr_mode
= flag_code
;
11057 #if INFER_ADDR_PREFIX
11058 if (i
.mem_operands
== 0)
11060 /* Infer address prefix from the first memory operand. */
11061 const reg_entry
*addr_reg
= i
.base_reg
;
11063 if (addr_reg
== NULL
)
11064 addr_reg
= i
.index_reg
;
11068 if (addr_reg
->reg_type
.bitfield
.dword
)
11069 addr_mode
= CODE_32BIT
;
11070 else if (flag_code
!= CODE_64BIT
11071 && addr_reg
->reg_type
.bitfield
.word
)
11072 addr_mode
= CODE_16BIT
;
11074 if (addr_mode
!= flag_code
)
11076 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11078 /* Change the size of any displacement too. At most one
11079 of Disp16 or Disp32 is set.
11080 FIXME. There doesn't seem to be any real need for
11081 separate Disp16 and Disp32 flags. The same goes for
11082 Imm16 and Imm32. Removing them would probably clean
11083 up the code quite a lot. */
11084 if (flag_code
!= CODE_64BIT
11085 && (i
.types
[this_operand
].bitfield
.disp16
11086 || i
.types
[this_operand
].bitfield
.disp32
))
11087 i
.types
[this_operand
]
11088 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11098 /* Make sure the memory operand we've been dealt is valid.
11099 Return 1 on success, 0 on a failure. */
11102 i386_index_check (const char *operand_string
)
11104 const char *kind
= "base/index";
11105 enum flag_code addr_mode
= i386_addressing_mode ();
11106 const insn_template
*t
= current_templates
->start
;
11108 if (t
->opcode_modifier
.isstring
11109 && !t
->cpu_flags
.bitfield
.cpupadlock
11110 && (current_templates
->end
[-1].opcode_modifier
.isstring
11111 || i
.mem_operands
))
11113 /* Memory operands of string insns are special in that they only allow
11114 a single register (rDI, rSI, or rBX) as their memory address. */
11115 const reg_entry
*expected_reg
;
11116 static const char *di_si
[][2] =
11122 static const char *bx
[] = { "ebx", "bx", "rbx" };
11124 kind
= "string address";
11126 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11128 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11129 - IS_STRING_ES_OP0
;
11132 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11133 || ((!i
.mem_operands
!= !intel_syntax
)
11134 && current_templates
->end
[-1].operand_types
[1]
11135 .bitfield
.baseindex
))
11138 = (const reg_entry
*) str_hash_find (reg_hash
,
11139 di_si
[addr_mode
][op
== es_op
]);
11143 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11145 if (i
.base_reg
!= expected_reg
11147 || operand_type_check (i
.types
[this_operand
], disp
))
11149 /* The second memory operand must have the same size as
11153 && !((addr_mode
== CODE_64BIT
11154 && i
.base_reg
->reg_type
.bitfield
.qword
)
11155 || (addr_mode
== CODE_32BIT
11156 ? i
.base_reg
->reg_type
.bitfield
.dword
11157 : i
.base_reg
->reg_type
.bitfield
.word
)))
11160 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11162 intel_syntax
? '[' : '(',
11164 expected_reg
->reg_name
,
11165 intel_syntax
? ']' : ')');
11172 as_bad (_("`%s' is not a valid %s expression"),
11173 operand_string
, kind
);
11178 if (addr_mode
!= CODE_16BIT
)
11180 /* 32-bit/64-bit checks. */
11181 if (i
.disp_encoding
== disp_encoding_16bit
)
11184 as_bad (_("invalid `%s' prefix"),
11185 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11190 && ((addr_mode
== CODE_64BIT
11191 ? !i
.base_reg
->reg_type
.bitfield
.qword
11192 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11193 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11194 || i
.base_reg
->reg_num
== RegIZ
))
11196 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11197 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11198 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11199 && ((addr_mode
== CODE_64BIT
11200 ? !i
.index_reg
->reg_type
.bitfield
.qword
11201 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11202 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11205 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11206 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11207 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11208 && t
->base_opcode
== 0x1b)
11209 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11210 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11211 && (t
->base_opcode
& ~1) == 0x1a)
11212 || t
->opcode_modifier
.sib
== SIBMEM
)
11214 /* They cannot use RIP-relative addressing. */
11215 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11217 as_bad (_("`%s' cannot be used here"), operand_string
);
11221 /* bndldx and bndstx ignore their scale factor. */
11222 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11223 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11224 && (t
->base_opcode
& ~1) == 0x1a
11225 && i
.log2_scale_factor
)
11226 as_warn (_("register scaling is being ignored here"));
11231 /* 16-bit checks. */
11232 if (i
.disp_encoding
== disp_encoding_32bit
)
11236 && (!i
.base_reg
->reg_type
.bitfield
.word
11237 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11239 && (!i
.index_reg
->reg_type
.bitfield
.word
11240 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11242 && i
.base_reg
->reg_num
< 6
11243 && i
.index_reg
->reg_num
>= 6
11244 && i
.log2_scale_factor
== 0))))
11251 /* Handle vector immediates. */
11254 RC_SAE_immediate (const char *imm_start
)
11256 unsigned int match_found
, j
;
11257 const char *pstr
= imm_start
;
11265 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11267 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11269 if (i
.rounding
.type
!= rc_none
)
11271 as_bad (_("duplicated `%s'"), imm_start
);
11275 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11276 i
.rounding
.operand
= this_operand
;
11278 pstr
+= RC_NamesTable
[j
].len
;
11286 if (*pstr
++ != '}')
11288 as_bad (_("Missing '}': '%s'"), imm_start
);
11291 /* RC/SAE immediate string should contain nothing more. */;
11294 as_bad (_("Junk after '}': '%s'"), imm_start
);
11298 exp
= &im_expressions
[i
.imm_operands
++];
11299 i
.op
[this_operand
].imms
= exp
;
11301 exp
->X_op
= O_constant
;
11302 exp
->X_add_number
= 0;
11303 exp
->X_add_symbol
= (symbolS
*) 0;
11304 exp
->X_op_symbol
= (symbolS
*) 0;
11306 i
.types
[this_operand
].bitfield
.imm8
= 1;
11310 /* Only string instructions can have a second memory operand, so
11311 reduce current_templates to just those if it contains any. */
11313 maybe_adjust_templates (void)
11315 const insn_template
*t
;
11317 gas_assert (i
.mem_operands
== 1);
11319 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11320 if (t
->opcode_modifier
.isstring
)
11323 if (t
< current_templates
->end
)
11325 static templates aux_templates
;
11328 aux_templates
.start
= t
;
11329 for (; t
< current_templates
->end
; ++t
)
11330 if (!t
->opcode_modifier
.isstring
)
11332 aux_templates
.end
= t
;
11334 /* Determine whether to re-check the first memory operand. */
11335 recheck
= (aux_templates
.start
!= current_templates
->start
11336 || t
!= current_templates
->end
);
11338 current_templates
= &aux_templates
;
11342 i
.mem_operands
= 0;
11343 if (i
.memop1_string
!= NULL
11344 && i386_index_check (i
.memop1_string
) == 0)
11346 i
.mem_operands
= 1;
11353 static INLINE
bool starts_memory_operand (char c
)
11356 || is_identifier_char (c
)
11357 || strchr ("([\"+-!~", c
);
11360 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11364 i386_att_operand (char *operand_string
)
11366 const reg_entry
*r
;
11368 char *op_string
= operand_string
;
11370 if (is_space_char (*op_string
))
11373 /* We check for an absolute prefix (differentiating,
11374 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11375 if (*op_string
== ABSOLUTE_PREFIX
)
11378 if (is_space_char (*op_string
))
11380 i
.jumpabsolute
= true;
11383 /* Check if operand is a register. */
11384 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11386 i386_operand_type temp
;
11391 /* Check for a segment override by searching for ':' after a
11392 segment register. */
11393 op_string
= end_op
;
11394 if (is_space_char (*op_string
))
11396 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11398 i
.seg
[i
.mem_operands
] = r
;
11400 /* Skip the ':' and whitespace. */
11402 if (is_space_char (*op_string
))
11405 /* Handle case of %es:*foo. */
11406 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
)
11409 if (is_space_char (*op_string
))
11411 i
.jumpabsolute
= true;
11414 if (!starts_memory_operand (*op_string
))
11416 as_bad (_("bad memory operand `%s'"), op_string
);
11419 goto do_memory_reference
;
11422 /* Handle vector operations. */
11423 if (*op_string
== '{')
11425 op_string
= check_VecOperations (op_string
);
11426 if (op_string
== NULL
)
11432 as_bad (_("junk `%s' after register"), op_string
);
11435 temp
= r
->reg_type
;
11436 temp
.bitfield
.baseindex
= 0;
11437 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11439 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11440 i
.op
[this_operand
].regs
= r
;
11443 else if (*op_string
== REGISTER_PREFIX
)
11445 as_bad (_("bad register name `%s'"), op_string
);
11448 else if (*op_string
== IMMEDIATE_PREFIX
)
11451 if (i
.jumpabsolute
)
11453 as_bad (_("immediate operand illegal with absolute jump"));
11456 if (!i386_immediate (op_string
))
11459 else if (RC_SAE_immediate (operand_string
))
11461 /* If it is a RC or SAE immediate, do nothing. */
11464 else if (starts_memory_operand (*op_string
))
11466 /* This is a memory reference of some sort. */
11469 /* Start and end of displacement string expression (if found). */
11470 char *displacement_string_start
;
11471 char *displacement_string_end
;
11473 do_memory_reference
:
11474 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11476 if ((i
.mem_operands
== 1
11477 && !current_templates
->start
->opcode_modifier
.isstring
)
11478 || i
.mem_operands
== 2)
11480 as_bad (_("too many memory references for `%s'"),
11481 current_templates
->start
->name
);
11485 /* Check for base index form. We detect the base index form by
11486 looking for an ')' at the end of the operand, searching
11487 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11489 base_string
= op_string
+ strlen (op_string
);
11491 /* Handle vector operations. */
11493 if (is_space_char (*base_string
))
11496 if (*base_string
== '}')
11498 char *vop_start
= NULL
;
11500 while (base_string
-- > op_string
)
11502 if (*base_string
== '"')
11504 if (*base_string
!= '{')
11507 vop_start
= base_string
;
11510 if (is_space_char (*base_string
))
11513 if (*base_string
!= '}')
11521 as_bad (_("unbalanced figure braces"));
11525 if (check_VecOperations (vop_start
) == NULL
)
11529 /* If we only have a displacement, set-up for it to be parsed later. */
11530 displacement_string_start
= op_string
;
11531 displacement_string_end
= base_string
+ 1;
11533 if (*base_string
== ')')
11536 unsigned int parens_not_balanced
= 1;
11538 /* We've already checked that the number of left & right ()'s are
11539 equal, so this loop will not be infinite. */
11543 if (*base_string
== ')')
11544 parens_not_balanced
++;
11545 if (*base_string
== '(')
11546 parens_not_balanced
--;
11548 while (parens_not_balanced
&& *base_string
!= '"');
11550 temp_string
= base_string
;
11552 /* Skip past '(' and whitespace. */
11553 if (*base_string
== '(')
11555 if (is_space_char (*base_string
))
11558 if (*base_string
== ','
11559 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11562 displacement_string_end
= temp_string
;
11564 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11568 if (i
.base_reg
== &bad_reg
)
11570 base_string
= end_op
;
11571 if (is_space_char (*base_string
))
11575 /* There may be an index reg or scale factor here. */
11576 if (*base_string
== ',')
11579 if (is_space_char (*base_string
))
11582 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11585 if (i
.index_reg
== &bad_reg
)
11587 base_string
= end_op
;
11588 if (is_space_char (*base_string
))
11590 if (*base_string
== ',')
11593 if (is_space_char (*base_string
))
11596 else if (*base_string
!= ')')
11598 as_bad (_("expecting `,' or `)' "
11599 "after index register in `%s'"),
11604 else if (*base_string
== REGISTER_PREFIX
)
11606 end_op
= strchr (base_string
, ',');
11609 as_bad (_("bad register name `%s'"), base_string
);
11613 /* Check for scale factor. */
11614 if (*base_string
!= ')')
11616 char *end_scale
= i386_scale (base_string
);
11621 base_string
= end_scale
;
11622 if (is_space_char (*base_string
))
11624 if (*base_string
!= ')')
11626 as_bad (_("expecting `)' "
11627 "after scale factor in `%s'"),
11632 else if (!i
.index_reg
)
11634 as_bad (_("expecting index register or scale factor "
11635 "after `,'; got '%c'"),
11640 else if (*base_string
!= ')')
11642 as_bad (_("expecting `,' or `)' "
11643 "after base register in `%s'"),
11648 else if (*base_string
== REGISTER_PREFIX
)
11650 end_op
= strchr (base_string
, ',');
11653 as_bad (_("bad register name `%s'"), base_string
);
11658 /* If there's an expression beginning the operand, parse it,
11659 assuming displacement_string_start and
11660 displacement_string_end are meaningful. */
11661 if (displacement_string_start
!= displacement_string_end
)
11663 if (!i386_displacement (displacement_string_start
,
11664 displacement_string_end
))
11668 /* Special case for (%dx) while doing input/output op. */
11670 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11671 && i
.base_reg
->reg_type
.bitfield
.word
11672 && i
.index_reg
== 0
11673 && i
.log2_scale_factor
== 0
11674 && i
.seg
[i
.mem_operands
] == 0
11675 && !operand_type_check (i
.types
[this_operand
], disp
))
11677 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11681 if (i386_index_check (operand_string
) == 0)
11683 i
.flags
[this_operand
] |= Operand_Mem
;
11684 if (i
.mem_operands
== 0)
11685 i
.memop1_string
= xstrdup (operand_string
);
11690 /* It's not a memory operand; argh! */
11691 as_bad (_("invalid char %s beginning operand %d `%s'"),
11692 output_invalid (*op_string
),
11697 return 1; /* Normal return. */
11700 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11701 that an rs_machine_dependent frag may reach. */
11704 i386_frag_max_var (fragS
*frag
)
11706 /* The only relaxable frags are for jumps.
11707 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11708 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11709 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11714 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11716 /* STT_GNU_IFUNC symbol must go through PLT. */
11717 if ((symbol_get_bfdsym (fr_symbol
)->flags
11718 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11721 if (!S_IS_EXTERNAL (fr_symbol
))
11722 /* Symbol may be weak or local. */
11723 return !S_IS_WEAK (fr_symbol
);
11725 /* Global symbols with non-default visibility can't be preempted. */
11726 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11729 if (fr_var
!= NO_RELOC
)
11730 switch ((enum bfd_reloc_code_real
) fr_var
)
11732 case BFD_RELOC_386_PLT32
:
11733 case BFD_RELOC_X86_64_PLT32
:
11734 /* Symbol with PLT relocation may be preempted. */
11740 /* Global symbols with default visibility in a shared library may be
11741 preempted by another definition. */
11746 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11747 Note also work for Skylake and Cascadelake.
11748 ---------------------------------------------------------------------
11749 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11750 | ------ | ----------- | ------- | -------- |
11752 | Jno | N | N | Y |
11753 | Jc/Jb | Y | N | Y |
11754 | Jae/Jnb | Y | N | Y |
11755 | Je/Jz | Y | Y | Y |
11756 | Jne/Jnz | Y | Y | Y |
11757 | Jna/Jbe | Y | N | Y |
11758 | Ja/Jnbe | Y | N | Y |
11760 | Jns | N | N | Y |
11761 | Jp/Jpe | N | N | Y |
11762 | Jnp/Jpo | N | N | Y |
11763 | Jl/Jnge | Y | Y | Y |
11764 | Jge/Jnl | Y | Y | Y |
11765 | Jle/Jng | Y | Y | Y |
11766 | Jg/Jnle | Y | Y | Y |
11767 --------------------------------------------------------------------- */
11769 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11771 if (mf_cmp
== mf_cmp_alu_cmp
)
11772 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11773 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11774 if (mf_cmp
== mf_cmp_incdec
)
11775 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11776 || mf_jcc
== mf_jcc_jle
);
11777 if (mf_cmp
== mf_cmp_test_and
)
11782 /* Return the next non-empty frag. */
11785 i386_next_non_empty_frag (fragS
*fragP
)
11787 /* There may be a frag with a ".fill 0" when there is no room in
11788 the current frag for frag_grow in output_insn. */
11789 for (fragP
= fragP
->fr_next
;
11791 && fragP
->fr_type
== rs_fill
11792 && fragP
->fr_fix
== 0);
11793 fragP
= fragP
->fr_next
)
11798 /* Return the next jcc frag after BRANCH_PADDING. */
11801 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11803 fragS
*branch_fragP
;
11807 if (pad_fragP
->fr_type
== rs_machine_dependent
11808 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11809 == BRANCH_PADDING
))
11811 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11812 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11814 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11815 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11816 pad_fragP
->tc_frag_data
.mf_type
))
11817 return branch_fragP
;
11823 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11826 i386_classify_machine_dependent_frag (fragS
*fragP
)
11830 fragS
*branch_fragP
;
11832 unsigned int max_prefix_length
;
11834 if (fragP
->tc_frag_data
.classified
)
11837 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11838 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11839 for (next_fragP
= fragP
;
11840 next_fragP
!= NULL
;
11841 next_fragP
= next_fragP
->fr_next
)
11843 next_fragP
->tc_frag_data
.classified
= 1;
11844 if (next_fragP
->fr_type
== rs_machine_dependent
)
11845 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11847 case BRANCH_PADDING
:
11848 /* The BRANCH_PADDING frag must be followed by a branch
11850 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11851 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11853 case FUSED_JCC_PADDING
:
11854 /* Check if this is a fused jcc:
11856 CMP like instruction
11860 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11861 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11862 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11865 /* The BRANCH_PADDING frag is merged with the
11866 FUSED_JCC_PADDING frag. */
11867 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11868 /* CMP like instruction size. */
11869 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11870 frag_wane (pad_fragP
);
11871 /* Skip to branch_fragP. */
11872 next_fragP
= branch_fragP
;
11874 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11876 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11878 next_fragP
->fr_subtype
11879 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11880 next_fragP
->tc_frag_data
.max_bytes
11881 = next_fragP
->tc_frag_data
.max_prefix_length
;
11882 /* This will be updated in the BRANCH_PREFIX scan. */
11883 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11886 frag_wane (next_fragP
);
11891 /* Stop if there is no BRANCH_PREFIX. */
11892 if (!align_branch_prefix_size
)
11895 /* Scan for BRANCH_PREFIX. */
11896 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11898 if (fragP
->fr_type
!= rs_machine_dependent
11899 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11903 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11904 COND_JUMP_PREFIX. */
11905 max_prefix_length
= 0;
11906 for (next_fragP
= fragP
;
11907 next_fragP
!= NULL
;
11908 next_fragP
= next_fragP
->fr_next
)
11910 if (next_fragP
->fr_type
== rs_fill
)
11911 /* Skip rs_fill frags. */
11913 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11914 /* Stop for all other frags. */
11917 /* rs_machine_dependent frags. */
11918 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11921 /* Count BRANCH_PREFIX frags. */
11922 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11924 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11925 frag_wane (next_fragP
);
11929 += next_fragP
->tc_frag_data
.max_bytes
;
11931 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11933 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11934 == FUSED_JCC_PADDING
))
11936 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11937 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11941 /* Stop for other rs_machine_dependent frags. */
11945 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11947 /* Skip to the next frag. */
11948 fragP
= next_fragP
;
11952 /* Compute padding size for
11955 CMP like instruction
11957 COND_JUMP/UNCOND_JUMP
11962 COND_JUMP/UNCOND_JUMP
11966 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11968 unsigned int offset
, size
, padding_size
;
11969 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11971 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11973 address
= fragP
->fr_address
;
11974 address
+= fragP
->fr_fix
;
11976 /* CMP like instrunction size. */
11977 size
= fragP
->tc_frag_data
.cmp_size
;
11979 /* The base size of the branch frag. */
11980 size
+= branch_fragP
->fr_fix
;
11982 /* Add opcode and displacement bytes for the rs_machine_dependent
11984 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11985 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11987 /* Check if branch is within boundary and doesn't end at the last
11989 offset
= address
& ((1U << align_branch_power
) - 1);
11990 if ((offset
+ size
) >= (1U << align_branch_power
))
11991 /* Padding needed to avoid crossing boundary. */
11992 padding_size
= (1U << align_branch_power
) - offset
;
11994 /* No padding needed. */
11997 /* The return value may be saved in tc_frag_data.length which is
11999 if (!fits_in_unsigned_byte (padding_size
))
12002 return padding_size
;
12005 /* i386_generic_table_relax_frag()
12007 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12008 grow/shrink padding to align branch frags. Hand others to
12012 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12014 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12015 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12017 long padding_size
= i386_branch_padding_size (fragP
, 0);
12018 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12020 /* When the BRANCH_PREFIX frag is used, the computed address
12021 must match the actual address and there should be no padding. */
12022 if (fragP
->tc_frag_data
.padding_address
12023 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12027 /* Update the padding size. */
12029 fragP
->tc_frag_data
.length
= padding_size
;
12033 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12035 fragS
*padding_fragP
, *next_fragP
;
12036 long padding_size
, left_size
, last_size
;
12038 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12039 if (!padding_fragP
)
12040 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12041 return (fragP
->tc_frag_data
.length
12042 - fragP
->tc_frag_data
.last_length
);
12044 /* Compute the relative address of the padding frag in the very
12045 first time where the BRANCH_PREFIX frag sizes are zero. */
12046 if (!fragP
->tc_frag_data
.padding_address
)
12047 fragP
->tc_frag_data
.padding_address
12048 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12050 /* First update the last length from the previous interation. */
12051 left_size
= fragP
->tc_frag_data
.prefix_length
;
12052 for (next_fragP
= fragP
;
12053 next_fragP
!= padding_fragP
;
12054 next_fragP
= next_fragP
->fr_next
)
12055 if (next_fragP
->fr_type
== rs_machine_dependent
12056 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12061 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12065 if (max
> left_size
)
12070 next_fragP
->tc_frag_data
.last_length
= size
;
12074 next_fragP
->tc_frag_data
.last_length
= 0;
12077 /* Check the padding size for the padding frag. */
12078 padding_size
= i386_branch_padding_size
12079 (padding_fragP
, (fragP
->fr_address
12080 + fragP
->tc_frag_data
.padding_address
));
12082 last_size
= fragP
->tc_frag_data
.prefix_length
;
12083 /* Check if there is change from the last interation. */
12084 if (padding_size
== last_size
)
12086 /* Update the expected address of the padding frag. */
12087 padding_fragP
->tc_frag_data
.padding_address
12088 = (fragP
->fr_address
+ padding_size
12089 + fragP
->tc_frag_data
.padding_address
);
12093 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12095 /* No padding if there is no sufficient room. Clear the
12096 expected address of the padding frag. */
12097 padding_fragP
->tc_frag_data
.padding_address
= 0;
12101 /* Store the expected address of the padding frag. */
12102 padding_fragP
->tc_frag_data
.padding_address
12103 = (fragP
->fr_address
+ padding_size
12104 + fragP
->tc_frag_data
.padding_address
);
12106 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12108 /* Update the length for the current interation. */
12109 left_size
= padding_size
;
12110 for (next_fragP
= fragP
;
12111 next_fragP
!= padding_fragP
;
12112 next_fragP
= next_fragP
->fr_next
)
12113 if (next_fragP
->fr_type
== rs_machine_dependent
12114 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12119 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12123 if (max
> left_size
)
12128 next_fragP
->tc_frag_data
.length
= size
;
12132 next_fragP
->tc_frag_data
.length
= 0;
12135 return (fragP
->tc_frag_data
.length
12136 - fragP
->tc_frag_data
.last_length
);
12138 return relax_frag (segment
, fragP
, stretch
);
12141 /* md_estimate_size_before_relax()
12143 Called just before relax() for rs_machine_dependent frags. The x86
12144 assembler uses these frags to handle variable size jump
12147 Any symbol that is now undefined will not become defined.
12148 Return the correct fr_subtype in the frag.
12149 Return the initial "guess for variable size of frag" to caller.
12150 The guess is actually the growth beyond the fixed part. Whatever
12151 we do to grow the fixed or variable part contributes to our
12155 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12157 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12158 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12159 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12161 i386_classify_machine_dependent_frag (fragP
);
12162 return fragP
->tc_frag_data
.length
;
12165 /* We've already got fragP->fr_subtype right; all we have to do is
12166 check for un-relaxable symbols. On an ELF system, we can't relax
12167 an externally visible symbol, because it may be overridden by a
12169 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12170 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12172 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12175 #if defined (OBJ_COFF) && defined (TE_PE)
12176 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12177 && S_IS_WEAK (fragP
->fr_symbol
))
12181 /* Symbol is undefined in this segment, or we need to keep a
12182 reloc so that weak symbols can be overridden. */
12183 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12184 enum bfd_reloc_code_real reloc_type
;
12185 unsigned char *opcode
;
12189 if (fragP
->fr_var
!= NO_RELOC
)
12190 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12191 else if (size
== 2)
12192 reloc_type
= BFD_RELOC_16_PCREL
;
12193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12194 else if (need_plt32_p (fragP
->fr_symbol
))
12195 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12198 reloc_type
= BFD_RELOC_32_PCREL
;
12200 old_fr_fix
= fragP
->fr_fix
;
12201 opcode
= (unsigned char *) fragP
->fr_opcode
;
12203 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12206 /* Make jmp (0xeb) a (d)word displacement jump. */
12208 fragP
->fr_fix
+= size
;
12209 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12211 fragP
->fr_offset
, 1,
12217 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12219 /* Negate the condition, and branch past an
12220 unconditional jump. */
12223 /* Insert an unconditional jump. */
12225 /* We added two extra opcode bytes, and have a two byte
12227 fragP
->fr_fix
+= 2 + 2;
12228 fix_new (fragP
, old_fr_fix
+ 2, 2,
12230 fragP
->fr_offset
, 1,
12234 /* Fall through. */
12237 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12239 fragP
->fr_fix
+= 1;
12240 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12242 fragP
->fr_offset
, 1,
12243 BFD_RELOC_8_PCREL
);
12244 fixP
->fx_signed
= 1;
12248 /* This changes the byte-displacement jump 0x7N
12249 to the (d)word-displacement jump 0x0f,0x8N. */
12250 opcode
[1] = opcode
[0] + 0x10;
12251 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12252 /* We've added an opcode byte. */
12253 fragP
->fr_fix
+= 1 + size
;
12254 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12256 fragP
->fr_offset
, 1,
12261 BAD_CASE (fragP
->fr_subtype
);
12265 /* All jumps handled here are signed, but don't unconditionally use a
12266 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12267 around at 4G (outside of 64-bit mode) and 64k. */
12268 if (size
== 4 && flag_code
== CODE_64BIT
)
12269 fixP
->fx_signed
= 1;
12272 return fragP
->fr_fix
- old_fr_fix
;
12275 /* Guess size depending on current relax state. Initially the relax
12276 state will correspond to a short jump and we return 1, because
12277 the variable part of the frag (the branch offset) is one byte
12278 long. However, we can relax a section more than once and in that
12279 case we must either set fr_subtype back to the unrelaxed state,
12280 or return the value for the appropriate branch. */
12281 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12284 /* Called after relax() is finished.
12286 In: Address of frag.
12287 fr_type == rs_machine_dependent.
12288 fr_subtype is what the address relaxed to.
12290 Out: Any fixSs and constants are set up.
12291 Caller will turn frag into a ".space 0". */
12294 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12297 unsigned char *opcode
;
12298 unsigned char *where_to_put_displacement
= NULL
;
12299 offsetT target_address
;
12300 offsetT opcode_address
;
12301 unsigned int extension
= 0;
12302 offsetT displacement_from_opcode_start
;
12304 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12305 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12306 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12308 /* Generate nop padding. */
12309 unsigned int size
= fragP
->tc_frag_data
.length
;
12312 if (size
> fragP
->tc_frag_data
.max_bytes
)
12318 const char *branch
= "branch";
12319 const char *prefix
= "";
12320 fragS
*padding_fragP
;
12321 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12324 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12325 switch (fragP
->tc_frag_data
.default_prefix
)
12330 case CS_PREFIX_OPCODE
:
12333 case DS_PREFIX_OPCODE
:
12336 case ES_PREFIX_OPCODE
:
12339 case FS_PREFIX_OPCODE
:
12342 case GS_PREFIX_OPCODE
:
12345 case SS_PREFIX_OPCODE
:
12350 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12351 "%s within %d-byte boundary\n");
12353 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12354 "align %s within %d-byte boundary\n");
12358 padding_fragP
= fragP
;
12359 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12360 "%s within %d-byte boundary\n");
12364 switch (padding_fragP
->tc_frag_data
.branch_type
)
12366 case align_branch_jcc
:
12369 case align_branch_fused
:
12370 branch
= "fused jcc";
12372 case align_branch_jmp
:
12375 case align_branch_call
:
12378 case align_branch_indirect
:
12379 branch
= "indiret branch";
12381 case align_branch_ret
:
12388 fprintf (stdout
, msg
,
12389 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12390 (long long) fragP
->fr_address
, branch
,
12391 1 << align_branch_power
);
12393 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12394 memset (fragP
->fr_opcode
,
12395 fragP
->tc_frag_data
.default_prefix
, size
);
12397 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12399 fragP
->fr_fix
+= size
;
12404 opcode
= (unsigned char *) fragP
->fr_opcode
;
12406 /* Address we want to reach in file space. */
12407 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12409 /* Address opcode resides at in file space. */
12410 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12412 /* Displacement from opcode start to fill into instruction. */
12413 displacement_from_opcode_start
= target_address
- opcode_address
;
12415 if ((fragP
->fr_subtype
& BIG
) == 0)
12417 /* Don't have to change opcode. */
12418 extension
= 1; /* 1 opcode + 1 displacement */
12419 where_to_put_displacement
= &opcode
[1];
12423 if (no_cond_jump_promotion
12424 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12425 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12426 _("long jump required"));
12428 switch (fragP
->fr_subtype
)
12430 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12431 extension
= 4; /* 1 opcode + 4 displacement */
12433 where_to_put_displacement
= &opcode
[1];
12436 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12437 extension
= 2; /* 1 opcode + 2 displacement */
12439 where_to_put_displacement
= &opcode
[1];
12442 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12443 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12444 extension
= 5; /* 2 opcode + 4 displacement */
12445 opcode
[1] = opcode
[0] + 0x10;
12446 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12447 where_to_put_displacement
= &opcode
[2];
12450 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12451 extension
= 3; /* 2 opcode + 2 displacement */
12452 opcode
[1] = opcode
[0] + 0x10;
12453 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12454 where_to_put_displacement
= &opcode
[2];
12457 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12462 where_to_put_displacement
= &opcode
[3];
12466 BAD_CASE (fragP
->fr_subtype
);
12471 /* If size if less then four we are sure that the operand fits,
12472 but if it's 4, then it could be that the displacement is larger
12474 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12476 && ((addressT
) (displacement_from_opcode_start
- extension
12477 + ((addressT
) 1 << 31))
12478 > (((addressT
) 2 << 31) - 1)))
12480 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12481 _("jump target out of range"));
12482 /* Make us emit 0. */
12483 displacement_from_opcode_start
= extension
;
12485 /* Now put displacement after opcode. */
12486 md_number_to_chars ((char *) where_to_put_displacement
,
12487 (valueT
) (displacement_from_opcode_start
- extension
),
12488 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12489 fragP
->fr_fix
+= extension
;
12492 /* Apply a fixup (fixP) to segment data, once it has been determined
12493 by our caller that we have all the info we need to fix it up.
12495 Parameter valP is the pointer to the value of the bits.
12497 On the 386, immediates, displacements, and data pointers are all in
12498 the same (little-endian) format, so we don't need to care about which
12499 we are handling. */
12502 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12504 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12505 valueT value
= *valP
;
12507 #if !defined (TE_Mach)
12508 if (fixP
->fx_pcrel
)
12510 switch (fixP
->fx_r_type
)
12516 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12519 case BFD_RELOC_X86_64_32S
:
12520 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12523 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12526 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12531 if (fixP
->fx_addsy
!= NULL
12532 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12533 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12534 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12535 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12536 && !use_rela_relocations
)
12538 /* This is a hack. There should be a better way to handle this.
12539 This covers for the fact that bfd_install_relocation will
12540 subtract the current location (for partial_inplace, PC relative
12541 relocations); see more below. */
12545 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12548 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12553 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12555 if ((sym_seg
== seg
12556 || (symbol_section_p (fixP
->fx_addsy
)
12557 && sym_seg
!= absolute_section
))
12558 && !generic_force_reloc (fixP
))
12560 /* Yes, we add the values in twice. This is because
12561 bfd_install_relocation subtracts them out again. I think
12562 bfd_install_relocation is broken, but I don't dare change
12564 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12568 #if defined (OBJ_COFF) && defined (TE_PE)
12569 /* For some reason, the PE format does not store a
12570 section address offset for a PC relative symbol. */
12571 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12572 || S_IS_WEAK (fixP
->fx_addsy
))
12573 value
+= md_pcrel_from (fixP
);
12576 #if defined (OBJ_COFF) && defined (TE_PE)
12577 if (fixP
->fx_addsy
!= NULL
12578 && S_IS_WEAK (fixP
->fx_addsy
)
12579 /* PR 16858: Do not modify weak function references. */
12580 && ! fixP
->fx_pcrel
)
12582 #if !defined (TE_PEP)
12583 /* For x86 PE weak function symbols are neither PC-relative
12584 nor do they set S_IS_FUNCTION. So the only reliable way
12585 to detect them is to check the flags of their containing
12587 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12588 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12592 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12596 /* Fix a few things - the dynamic linker expects certain values here,
12597 and we must not disappoint it. */
12598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12599 if (IS_ELF
&& fixP
->fx_addsy
)
12600 switch (fixP
->fx_r_type
)
12602 case BFD_RELOC_386_PLT32
:
12603 case BFD_RELOC_X86_64_PLT32
:
12604 /* Make the jump instruction point to the address of the operand.
12605 At runtime we merely add the offset to the actual PLT entry.
12606 NB: Subtract the offset size only for jump instructions. */
12607 if (fixP
->fx_pcrel
)
12611 case BFD_RELOC_386_TLS_GD
:
12612 case BFD_RELOC_386_TLS_LDM
:
12613 case BFD_RELOC_386_TLS_IE_32
:
12614 case BFD_RELOC_386_TLS_IE
:
12615 case BFD_RELOC_386_TLS_GOTIE
:
12616 case BFD_RELOC_386_TLS_GOTDESC
:
12617 case BFD_RELOC_X86_64_TLSGD
:
12618 case BFD_RELOC_X86_64_TLSLD
:
12619 case BFD_RELOC_X86_64_GOTTPOFF
:
12620 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12621 value
= 0; /* Fully resolved at runtime. No addend. */
12623 case BFD_RELOC_386_TLS_LE
:
12624 case BFD_RELOC_386_TLS_LDO_32
:
12625 case BFD_RELOC_386_TLS_LE_32
:
12626 case BFD_RELOC_X86_64_DTPOFF32
:
12627 case BFD_RELOC_X86_64_DTPOFF64
:
12628 case BFD_RELOC_X86_64_TPOFF32
:
12629 case BFD_RELOC_X86_64_TPOFF64
:
12630 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12633 case BFD_RELOC_386_TLS_DESC_CALL
:
12634 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12635 value
= 0; /* Fully resolved at runtime. No addend. */
12636 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12640 case BFD_RELOC_VTABLE_INHERIT
:
12641 case BFD_RELOC_VTABLE_ENTRY
:
12648 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12650 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12652 value
= extend_to_32bit_address (value
);
12655 #endif /* !defined (TE_Mach) */
12657 /* Are we finished with this relocation now? */
12658 if (fixP
->fx_addsy
== NULL
)
12661 switch (fixP
->fx_r_type
)
12663 case BFD_RELOC_X86_64_32S
:
12664 fixP
->fx_signed
= 1;
12671 #if defined (OBJ_COFF) && defined (TE_PE)
12672 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12675 /* Remember value for tc_gen_reloc. */
12676 fixP
->fx_addnumber
= value
;
12677 /* Clear out the frag for now. */
12681 else if (use_rela_relocations
)
12683 fixP
->fx_no_overflow
= 1;
12684 /* Remember value for tc_gen_reloc. */
12685 fixP
->fx_addnumber
= value
;
12689 md_number_to_chars (p
, value
, fixP
->fx_size
);
12693 md_atof (int type
, char *litP
, int *sizeP
)
12695 /* This outputs the LITTLENUMs in REVERSE order;
12696 in accord with the bigendian 386. */
12697 return ieee_md_atof (type
, litP
, sizeP
, false);
12700 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12703 output_invalid (int c
)
12706 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12709 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12710 "(0x%x)", (unsigned char) c
);
12711 return output_invalid_buf
;
12714 /* Verify that @r can be used in the current context. */
12716 static bool check_register (const reg_entry
*r
)
12718 if (allow_pseudo_reg
)
12721 if (operand_type_all_zero (&r
->reg_type
))
12724 if ((r
->reg_type
.bitfield
.dword
12725 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12726 || r
->reg_type
.bitfield
.class == RegCR
12727 || r
->reg_type
.bitfield
.class == RegDR
)
12728 && !cpu_arch_flags
.bitfield
.cpui386
)
12731 if (r
->reg_type
.bitfield
.class == RegTR
12732 && (flag_code
== CODE_64BIT
12733 || !cpu_arch_flags
.bitfield
.cpui386
12734 || cpu_arch_isa_flags
.bitfield
.cpui586
12735 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12738 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12741 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12743 if (r
->reg_type
.bitfield
.zmmword
12744 || r
->reg_type
.bitfield
.class == RegMask
)
12747 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12749 if (r
->reg_type
.bitfield
.ymmword
)
12752 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12757 if (r
->reg_type
.bitfield
.tmmword
12758 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12759 || flag_code
!= CODE_64BIT
))
12762 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12765 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12766 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12769 /* Upper 16 vector registers are only available with VREX in 64bit
12770 mode, and require EVEX encoding. */
12771 if (r
->reg_flags
& RegVRex
)
12773 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12774 || flag_code
!= CODE_64BIT
)
12777 if (i
.vec_encoding
== vex_encoding_default
)
12778 i
.vec_encoding
= vex_encoding_evex
;
12779 else if (i
.vec_encoding
!= vex_encoding_evex
)
12780 i
.vec_encoding
= vex_encoding_error
;
12783 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12784 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12785 && flag_code
!= CODE_64BIT
)
12788 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12795 /* REG_STRING starts *before* REGISTER_PREFIX. */
12797 static const reg_entry
*
12798 parse_real_register (char *reg_string
, char **end_op
)
12800 char *s
= reg_string
;
12802 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12803 const reg_entry
*r
;
12805 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12806 if (*s
== REGISTER_PREFIX
)
12809 if (is_space_char (*s
))
12812 p
= reg_name_given
;
12813 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12815 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12816 return (const reg_entry
*) NULL
;
12820 /* For naked regs, make sure that we are not dealing with an identifier.
12821 This prevents confusing an identifier like `eax_var' with register
12823 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12824 return (const reg_entry
*) NULL
;
12828 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12830 /* Handle floating point regs, allowing spaces in the (i) part. */
12833 if (!cpu_arch_flags
.bitfield
.cpu8087
12834 && !cpu_arch_flags
.bitfield
.cpu287
12835 && !cpu_arch_flags
.bitfield
.cpu387
12836 && !allow_pseudo_reg
)
12837 return (const reg_entry
*) NULL
;
12839 if (is_space_char (*s
))
12844 if (is_space_char (*s
))
12846 if (*s
>= '0' && *s
<= '7')
12848 int fpr
= *s
- '0';
12850 if (is_space_char (*s
))
12855 know (r
[fpr
].reg_num
== fpr
);
12859 /* We have "%st(" then garbage. */
12860 return (const reg_entry
*) NULL
;
12864 return r
&& check_register (r
) ? r
: NULL
;
12867 /* REG_STRING starts *before* REGISTER_PREFIX. */
12869 static const reg_entry
*
12870 parse_register (char *reg_string
, char **end_op
)
12872 const reg_entry
*r
;
12874 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12875 r
= parse_real_register (reg_string
, end_op
);
12880 char *save
= input_line_pointer
;
12884 input_line_pointer
= reg_string
;
12885 c
= get_symbol_name (®_string
);
12886 symbolP
= symbol_find (reg_string
);
12887 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12889 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12891 know (e
->X_op
== O_register
);
12892 know (e
->X_add_number
>= 0
12893 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12894 r
= i386_regtab
+ e
->X_add_number
;
12895 if (!check_register (r
))
12897 as_bad (_("register '%s%s' cannot be used here"),
12898 register_prefix
, r
->reg_name
);
12901 *end_op
= input_line_pointer
;
12903 *input_line_pointer
= c
;
12904 input_line_pointer
= save
;
12910 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12912 const reg_entry
*r
;
12913 char *end
= input_line_pointer
;
12916 r
= parse_register (name
, &input_line_pointer
);
12917 if (r
&& end
<= input_line_pointer
)
12919 *nextcharP
= *input_line_pointer
;
12920 *input_line_pointer
= 0;
12923 e
->X_op
= O_register
;
12924 e
->X_add_number
= r
- i386_regtab
;
12927 e
->X_op
= O_illegal
;
12930 input_line_pointer
= end
;
12932 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12936 md_operand (expressionS
*e
)
12939 const reg_entry
*r
;
12941 switch (*input_line_pointer
)
12943 case REGISTER_PREFIX
:
12944 r
= parse_real_register (input_line_pointer
, &end
);
12947 e
->X_op
= O_register
;
12948 e
->X_add_number
= r
- i386_regtab
;
12949 input_line_pointer
= end
;
12954 gas_assert (intel_syntax
);
12955 end
= input_line_pointer
++;
12957 if (*input_line_pointer
== ']')
12959 ++input_line_pointer
;
12960 e
->X_op_symbol
= make_expr_symbol (e
);
12961 e
->X_add_symbol
= NULL
;
12962 e
->X_add_number
= 0;
12967 e
->X_op
= O_absent
;
12968 input_line_pointer
= end
;
12975 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12976 const char *md_shortopts
= "kVQ:sqnO::";
12978 const char *md_shortopts
= "qnO::";
12981 #define OPTION_32 (OPTION_MD_BASE + 0)
12982 #define OPTION_64 (OPTION_MD_BASE + 1)
12983 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12984 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12985 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12986 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12987 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12988 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12989 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12990 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12991 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12992 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12993 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12994 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12995 #define OPTION_X32 (OPTION_MD_BASE + 14)
12996 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12997 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12998 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12999 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13000 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13001 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13002 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13003 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13004 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13005 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13006 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13007 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13008 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13009 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13010 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13011 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13012 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13013 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13014 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13016 struct option md_longopts
[] =
13018 {"32", no_argument
, NULL
, OPTION_32
},
13019 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13020 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13021 {"64", no_argument
, NULL
, OPTION_64
},
13023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13024 {"x32", no_argument
, NULL
, OPTION_X32
},
13025 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13026 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13028 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13029 {"march", required_argument
, NULL
, OPTION_MARCH
},
13030 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13031 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13032 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13033 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13034 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13035 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13036 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13037 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13038 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13039 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13040 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13041 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13042 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13043 # if defined (TE_PE) || defined (TE_PEP)
13044 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13046 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13047 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13048 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13049 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13050 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13051 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13052 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13053 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13054 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13055 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13056 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13057 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13058 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13059 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13060 {NULL
, no_argument
, NULL
, 0}
13062 size_t md_longopts_size
= sizeof (md_longopts
);
13065 md_parse_option (int c
, const char *arg
)
13068 char *arch
, *next
, *saved
, *type
;
13073 optimize_align_code
= 0;
13077 quiet_warnings
= 1;
13080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13081 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13082 should be emitted or not. FIXME: Not implemented. */
13084 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13088 /* -V: SVR4 argument to print version ID. */
13090 print_version_id ();
13093 /* -k: Ignore for FreeBSD compatibility. */
13098 /* -s: On i386 Solaris, this tells the native assembler to use
13099 .stab instead of .stab.excl. We always use .stab anyhow. */
13102 case OPTION_MSHARED
:
13106 case OPTION_X86_USED_NOTE
:
13107 if (strcasecmp (arg
, "yes") == 0)
13109 else if (strcasecmp (arg
, "no") == 0)
13112 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13117 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13118 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13121 const char **list
, **l
;
13123 list
= bfd_target_list ();
13124 for (l
= list
; *l
!= NULL
; l
++)
13125 if (startswith (*l
, "elf64-x86-64")
13126 || strcmp (*l
, "coff-x86-64") == 0
13127 || strcmp (*l
, "pe-x86-64") == 0
13128 || strcmp (*l
, "pei-x86-64") == 0
13129 || strcmp (*l
, "mach-o-x86-64") == 0)
13131 default_arch
= "x86_64";
13135 as_fatal (_("no compiled in support for x86_64"));
13141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13145 const char **list
, **l
;
13147 list
= bfd_target_list ();
13148 for (l
= list
; *l
!= NULL
; l
++)
13149 if (startswith (*l
, "elf32-x86-64"))
13151 default_arch
= "x86_64:32";
13155 as_fatal (_("no compiled in support for 32bit x86_64"));
13159 as_fatal (_("32bit x86_64 is only supported for ELF"));
13164 default_arch
= "i386";
13167 case OPTION_DIVIDE
:
13168 #ifdef SVR4_COMMENT_CHARS
13173 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13175 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13179 i386_comment_chars
= n
;
13185 saved
= xstrdup (arg
);
13187 /* Allow -march=+nosse. */
13193 as_fatal (_("invalid -march= option: `%s'"), arg
);
13194 next
= strchr (arch
, '+');
13197 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13199 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13202 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13205 cpu_arch_name
= cpu_arch
[j
].name
;
13206 cpu_sub_arch_name
= NULL
;
13207 cpu_arch_flags
= cpu_arch
[j
].flags
;
13208 cpu_arch_isa
= cpu_arch
[j
].type
;
13209 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13210 if (!cpu_arch_tune_set
)
13212 cpu_arch_tune
= cpu_arch_isa
;
13213 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13217 else if (*cpu_arch
[j
].name
== '.'
13218 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13220 /* ISA extension. */
13221 i386_cpu_flags flags
;
13223 flags
= cpu_flags_or (cpu_arch_flags
,
13224 cpu_arch
[j
].flags
);
13226 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13228 if (cpu_sub_arch_name
)
13230 char *name
= cpu_sub_arch_name
;
13231 cpu_sub_arch_name
= concat (name
,
13233 (const char *) NULL
);
13237 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13238 cpu_arch_flags
= flags
;
13239 cpu_arch_isa_flags
= flags
;
13243 = cpu_flags_or (cpu_arch_isa_flags
,
13244 cpu_arch
[j
].flags
);
13249 if (j
>= ARRAY_SIZE (cpu_arch
))
13251 /* Disable an ISA extension. */
13252 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13253 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13255 i386_cpu_flags flags
;
13257 flags
= cpu_flags_and_not (cpu_arch_flags
,
13258 cpu_noarch
[j
].flags
);
13259 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13261 if (cpu_sub_arch_name
)
13263 char *name
= cpu_sub_arch_name
;
13264 cpu_sub_arch_name
= concat (arch
,
13265 (const char *) NULL
);
13269 cpu_sub_arch_name
= xstrdup (arch
);
13270 cpu_arch_flags
= flags
;
13271 cpu_arch_isa_flags
= flags
;
13276 if (j
>= ARRAY_SIZE (cpu_noarch
))
13277 j
= ARRAY_SIZE (cpu_arch
);
13280 if (j
>= ARRAY_SIZE (cpu_arch
))
13281 as_fatal (_("invalid -march= option: `%s'"), arg
);
13285 while (next
!= NULL
);
13291 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13292 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13294 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13296 cpu_arch_tune_set
= 1;
13297 cpu_arch_tune
= cpu_arch
[j
].type
;
13298 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13302 if (j
>= ARRAY_SIZE (cpu_arch
))
13303 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13306 case OPTION_MMNEMONIC
:
13307 if (strcasecmp (arg
, "att") == 0)
13308 intel_mnemonic
= 0;
13309 else if (strcasecmp (arg
, "intel") == 0)
13310 intel_mnemonic
= 1;
13312 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13315 case OPTION_MSYNTAX
:
13316 if (strcasecmp (arg
, "att") == 0)
13318 else if (strcasecmp (arg
, "intel") == 0)
13321 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13324 case OPTION_MINDEX_REG
:
13325 allow_index_reg
= 1;
13328 case OPTION_MNAKED_REG
:
13329 allow_naked_reg
= 1;
13332 case OPTION_MSSE2AVX
:
13336 case OPTION_MSSE_CHECK
:
13337 if (strcasecmp (arg
, "error") == 0)
13338 sse_check
= check_error
;
13339 else if (strcasecmp (arg
, "warning") == 0)
13340 sse_check
= check_warning
;
13341 else if (strcasecmp (arg
, "none") == 0)
13342 sse_check
= check_none
;
13344 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13347 case OPTION_MOPERAND_CHECK
:
13348 if (strcasecmp (arg
, "error") == 0)
13349 operand_check
= check_error
;
13350 else if (strcasecmp (arg
, "warning") == 0)
13351 operand_check
= check_warning
;
13352 else if (strcasecmp (arg
, "none") == 0)
13353 operand_check
= check_none
;
13355 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13358 case OPTION_MAVXSCALAR
:
13359 if (strcasecmp (arg
, "128") == 0)
13360 avxscalar
= vex128
;
13361 else if (strcasecmp (arg
, "256") == 0)
13362 avxscalar
= vex256
;
13364 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13367 case OPTION_MVEXWIG
:
13368 if (strcmp (arg
, "0") == 0)
13370 else if (strcmp (arg
, "1") == 0)
13373 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13376 case OPTION_MADD_BND_PREFIX
:
13377 add_bnd_prefix
= 1;
13380 case OPTION_MEVEXLIG
:
13381 if (strcmp (arg
, "128") == 0)
13382 evexlig
= evexl128
;
13383 else if (strcmp (arg
, "256") == 0)
13384 evexlig
= evexl256
;
13385 else if (strcmp (arg
, "512") == 0)
13386 evexlig
= evexl512
;
13388 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13391 case OPTION_MEVEXRCIG
:
13392 if (strcmp (arg
, "rne") == 0)
13394 else if (strcmp (arg
, "rd") == 0)
13396 else if (strcmp (arg
, "ru") == 0)
13398 else if (strcmp (arg
, "rz") == 0)
13401 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13404 case OPTION_MEVEXWIG
:
13405 if (strcmp (arg
, "0") == 0)
13407 else if (strcmp (arg
, "1") == 0)
13410 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13413 # if defined (TE_PE) || defined (TE_PEP)
13414 case OPTION_MBIG_OBJ
:
13419 case OPTION_MOMIT_LOCK_PREFIX
:
13420 if (strcasecmp (arg
, "yes") == 0)
13421 omit_lock_prefix
= 1;
13422 else if (strcasecmp (arg
, "no") == 0)
13423 omit_lock_prefix
= 0;
13425 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13428 case OPTION_MFENCE_AS_LOCK_ADD
:
13429 if (strcasecmp (arg
, "yes") == 0)
13431 else if (strcasecmp (arg
, "no") == 0)
13434 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13437 case OPTION_MLFENCE_AFTER_LOAD
:
13438 if (strcasecmp (arg
, "yes") == 0)
13439 lfence_after_load
= 1;
13440 else if (strcasecmp (arg
, "no") == 0)
13441 lfence_after_load
= 0;
13443 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13446 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13447 if (strcasecmp (arg
, "all") == 0)
13449 lfence_before_indirect_branch
= lfence_branch_all
;
13450 if (lfence_before_ret
== lfence_before_ret_none
)
13451 lfence_before_ret
= lfence_before_ret_shl
;
13453 else if (strcasecmp (arg
, "memory") == 0)
13454 lfence_before_indirect_branch
= lfence_branch_memory
;
13455 else if (strcasecmp (arg
, "register") == 0)
13456 lfence_before_indirect_branch
= lfence_branch_register
;
13457 else if (strcasecmp (arg
, "none") == 0)
13458 lfence_before_indirect_branch
= lfence_branch_none
;
13460 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13464 case OPTION_MLFENCE_BEFORE_RET
:
13465 if (strcasecmp (arg
, "or") == 0)
13466 lfence_before_ret
= lfence_before_ret_or
;
13467 else if (strcasecmp (arg
, "not") == 0)
13468 lfence_before_ret
= lfence_before_ret_not
;
13469 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13470 lfence_before_ret
= lfence_before_ret_shl
;
13471 else if (strcasecmp (arg
, "none") == 0)
13472 lfence_before_ret
= lfence_before_ret_none
;
13474 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13478 case OPTION_MRELAX_RELOCATIONS
:
13479 if (strcasecmp (arg
, "yes") == 0)
13480 generate_relax_relocations
= 1;
13481 else if (strcasecmp (arg
, "no") == 0)
13482 generate_relax_relocations
= 0;
13484 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13487 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13490 long int align
= strtoul (arg
, &end
, 0);
13495 align_branch_power
= 0;
13498 else if (align
>= 16)
13501 for (align_power
= 0;
13503 align
>>= 1, align_power
++)
13505 /* Limit alignment power to 31. */
13506 if (align
== 1 && align_power
< 32)
13508 align_branch_power
= align_power
;
13513 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13517 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13520 int align
= strtoul (arg
, &end
, 0);
13521 /* Some processors only support 5 prefixes. */
13522 if (*end
== '\0' && align
>= 0 && align
< 6)
13524 align_branch_prefix_size
= align
;
13527 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13532 case OPTION_MALIGN_BRANCH
:
13534 saved
= xstrdup (arg
);
13538 next
= strchr (type
, '+');
13541 if (strcasecmp (type
, "jcc") == 0)
13542 align_branch
|= align_branch_jcc_bit
;
13543 else if (strcasecmp (type
, "fused") == 0)
13544 align_branch
|= align_branch_fused_bit
;
13545 else if (strcasecmp (type
, "jmp") == 0)
13546 align_branch
|= align_branch_jmp_bit
;
13547 else if (strcasecmp (type
, "call") == 0)
13548 align_branch
|= align_branch_call_bit
;
13549 else if (strcasecmp (type
, "ret") == 0)
13550 align_branch
|= align_branch_ret_bit
;
13551 else if (strcasecmp (type
, "indirect") == 0)
13552 align_branch
|= align_branch_indirect_bit
;
13554 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13557 while (next
!= NULL
);
13561 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13562 align_branch_power
= 5;
13563 align_branch_prefix_size
= 5;
13564 align_branch
= (align_branch_jcc_bit
13565 | align_branch_fused_bit
13566 | align_branch_jmp_bit
);
13569 case OPTION_MAMD64
:
13573 case OPTION_MINTEL64
:
13581 /* Turn off -Os. */
13582 optimize_for_space
= 0;
13584 else if (*arg
== 's')
13586 optimize_for_space
= 1;
13587 /* Turn on all encoding optimizations. */
13588 optimize
= INT_MAX
;
13592 optimize
= atoi (arg
);
13593 /* Turn off -Os. */
13594 optimize_for_space
= 0;
13604 #define MESSAGE_TEMPLATE \
13608 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13609 int *left_p
, const char *name
, int len
)
13611 int size
= sizeof (MESSAGE_TEMPLATE
);
13612 int left
= *left_p
;
13614 /* Reserve 2 spaces for ", " or ",\0" */
13617 /* Check if there is any room. */
13625 p
= mempcpy (p
, name
, len
);
13629 /* Output the current message now and start a new one. */
13632 fprintf (stream
, "%s\n", message
);
13634 left
= size
- (start
- message
) - len
- 2;
13636 gas_assert (left
>= 0);
13638 p
= mempcpy (p
, name
, len
);
13646 show_arch (FILE *stream
, int ext
, int check
)
13648 static char message
[] = MESSAGE_TEMPLATE
;
13649 char *start
= message
+ 27;
13651 int size
= sizeof (MESSAGE_TEMPLATE
);
13658 left
= size
- (start
- message
);
13659 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13661 /* Should it be skipped? */
13662 if (cpu_arch
[j
].skip
)
13665 name
= cpu_arch
[j
].name
;
13666 len
= cpu_arch
[j
].len
;
13669 /* It is an extension. Skip if we aren't asked to show it. */
13680 /* It is an processor. Skip if we show only extension. */
13683 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13685 /* It is an impossible processor - skip. */
13689 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13692 /* Display disabled extensions. */
13694 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13696 name
= cpu_noarch
[j
].name
;
13697 len
= cpu_noarch
[j
].len
;
13698 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13703 fprintf (stream
, "%s\n", message
);
13707 md_show_usage (FILE *stream
)
13709 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13710 fprintf (stream
, _("\
13711 -Qy, -Qn ignored\n\
13712 -V print assembler version number\n\
13715 fprintf (stream
, _("\
13716 -n Do not optimize code alignment\n\
13717 -q quieten some warnings\n"));
13718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13719 fprintf (stream
, _("\
13722 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13723 || defined (TE_PE) || defined (TE_PEP))
13724 fprintf (stream
, _("\
13725 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13727 #ifdef SVR4_COMMENT_CHARS
13728 fprintf (stream
, _("\
13729 --divide do not treat `/' as a comment character\n"));
13731 fprintf (stream
, _("\
13732 --divide ignored\n"));
13734 fprintf (stream
, _("\
13735 -march=CPU[,+EXTENSION...]\n\
13736 generate code for CPU and EXTENSION, CPU is one of:\n"));
13737 show_arch (stream
, 0, 1);
13738 fprintf (stream
, _("\
13739 EXTENSION is combination of:\n"));
13740 show_arch (stream
, 1, 0);
13741 fprintf (stream
, _("\
13742 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13743 show_arch (stream
, 0, 0);
13744 fprintf (stream
, _("\
13745 -msse2avx encode SSE instructions with VEX prefix\n"));
13746 fprintf (stream
, _("\
13747 -msse-check=[none|error|warning] (default: warning)\n\
13748 check SSE instructions\n"));
13749 fprintf (stream
, _("\
13750 -moperand-check=[none|error|warning] (default: warning)\n\
13751 check operand combinations for validity\n"));
13752 fprintf (stream
, _("\
13753 -mavxscalar=[128|256] (default: 128)\n\
13754 encode scalar AVX instructions with specific vector\n\
13756 fprintf (stream
, _("\
13757 -mvexwig=[0|1] (default: 0)\n\
13758 encode VEX instructions with specific VEX.W value\n\
13759 for VEX.W bit ignored instructions\n"));
13760 fprintf (stream
, _("\
13761 -mevexlig=[128|256|512] (default: 128)\n\
13762 encode scalar EVEX instructions with specific vector\n\
13764 fprintf (stream
, _("\
13765 -mevexwig=[0|1] (default: 0)\n\
13766 encode EVEX instructions with specific EVEX.W value\n\
13767 for EVEX.W bit ignored instructions\n"));
13768 fprintf (stream
, _("\
13769 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13770 encode EVEX instructions with specific EVEX.RC value\n\
13771 for SAE-only ignored instructions\n"));
13772 fprintf (stream
, _("\
13773 -mmnemonic=[att|intel] "));
13774 if (SYSV386_COMPAT
)
13775 fprintf (stream
, _("(default: att)\n"));
13777 fprintf (stream
, _("(default: intel)\n"));
13778 fprintf (stream
, _("\
13779 use AT&T/Intel mnemonic\n"));
13780 fprintf (stream
, _("\
13781 -msyntax=[att|intel] (default: att)\n\
13782 use AT&T/Intel syntax\n"));
13783 fprintf (stream
, _("\
13784 -mindex-reg support pseudo index registers\n"));
13785 fprintf (stream
, _("\
13786 -mnaked-reg don't require `%%' prefix for registers\n"));
13787 fprintf (stream
, _("\
13788 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13790 fprintf (stream
, _("\
13791 -mshared disable branch optimization for shared code\n"));
13792 fprintf (stream
, _("\
13793 -mx86-used-note=[no|yes] "));
13794 if (DEFAULT_X86_USED_NOTE
)
13795 fprintf (stream
, _("(default: yes)\n"));
13797 fprintf (stream
, _("(default: no)\n"));
13798 fprintf (stream
, _("\
13799 generate x86 used ISA and feature properties\n"));
13801 #if defined (TE_PE) || defined (TE_PEP)
13802 fprintf (stream
, _("\
13803 -mbig-obj generate big object files\n"));
13805 fprintf (stream
, _("\
13806 -momit-lock-prefix=[no|yes] (default: no)\n\
13807 strip all lock prefixes\n"));
13808 fprintf (stream
, _("\
13809 -mfence-as-lock-add=[no|yes] (default: no)\n\
13810 encode lfence, mfence and sfence as\n\
13811 lock addl $0x0, (%%{re}sp)\n"));
13812 fprintf (stream
, _("\
13813 -mrelax-relocations=[no|yes] "));
13814 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13815 fprintf (stream
, _("(default: yes)\n"));
13817 fprintf (stream
, _("(default: no)\n"));
13818 fprintf (stream
, _("\
13819 generate relax relocations\n"));
13820 fprintf (stream
, _("\
13821 -malign-branch-boundary=NUM (default: 0)\n\
13822 align branches within NUM byte boundary\n"));
13823 fprintf (stream
, _("\
13824 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13825 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13827 specify types of branches to align\n"));
13828 fprintf (stream
, _("\
13829 -malign-branch-prefix-size=NUM (default: 5)\n\
13830 align branches with NUM prefixes per instruction\n"));
13831 fprintf (stream
, _("\
13832 -mbranches-within-32B-boundaries\n\
13833 align branches within 32 byte boundary\n"));
13834 fprintf (stream
, _("\
13835 -mlfence-after-load=[no|yes] (default: no)\n\
13836 generate lfence after load\n"));
13837 fprintf (stream
, _("\
13838 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13839 generate lfence before indirect near branch\n"));
13840 fprintf (stream
, _("\
13841 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13842 generate lfence before ret\n"));
13843 fprintf (stream
, _("\
13844 -mamd64 accept only AMD64 ISA [default]\n"));
13845 fprintf (stream
, _("\
13846 -mintel64 accept only Intel64 ISA\n"));
13849 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13850 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13851 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13853 /* Pick the target format to use. */
13856 i386_target_format (void)
13858 if (startswith (default_arch
, "x86_64"))
13860 update_code_flag (CODE_64BIT
, 1);
13861 if (default_arch
[6] == '\0')
13862 x86_elf_abi
= X86_64_ABI
;
13864 x86_elf_abi
= X86_64_X32_ABI
;
13866 else if (!strcmp (default_arch
, "i386"))
13867 update_code_flag (CODE_32BIT
, 1);
13868 else if (!strcmp (default_arch
, "iamcu"))
13870 update_code_flag (CODE_32BIT
, 1);
13871 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13873 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13874 cpu_arch_name
= "iamcu";
13875 cpu_sub_arch_name
= NULL
;
13876 cpu_arch_flags
= iamcu_flags
;
13877 cpu_arch_isa
= PROCESSOR_IAMCU
;
13878 cpu_arch_isa_flags
= iamcu_flags
;
13879 if (!cpu_arch_tune_set
)
13881 cpu_arch_tune
= cpu_arch_isa
;
13882 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13885 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13886 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13890 as_fatal (_("unknown architecture"));
13892 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13893 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13894 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13895 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13897 switch (OUTPUT_FLAVOR
)
13899 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13900 case bfd_target_aout_flavour
:
13901 return AOUT_TARGET_FORMAT
;
13903 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13904 # if defined (TE_PE) || defined (TE_PEP)
13905 case bfd_target_coff_flavour
:
13906 if (flag_code
== CODE_64BIT
)
13909 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13911 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13912 # elif defined (TE_GO32)
13913 case bfd_target_coff_flavour
:
13914 return "coff-go32";
13916 case bfd_target_coff_flavour
:
13917 return "coff-i386";
13920 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13921 case bfd_target_elf_flavour
:
13923 const char *format
;
13925 switch (x86_elf_abi
)
13928 format
= ELF_TARGET_FORMAT
;
13930 tls_get_addr
= "___tls_get_addr";
13934 use_rela_relocations
= 1;
13937 tls_get_addr
= "__tls_get_addr";
13939 format
= ELF_TARGET_FORMAT64
;
13941 case X86_64_X32_ABI
:
13942 use_rela_relocations
= 1;
13945 tls_get_addr
= "__tls_get_addr";
13947 disallow_64bit_reloc
= 1;
13948 format
= ELF_TARGET_FORMAT32
;
13951 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13953 if (x86_elf_abi
!= X86_64_ABI
)
13954 as_fatal (_("Intel L1OM is 64bit only"));
13955 return ELF_TARGET_L1OM_FORMAT
;
13957 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13959 if (x86_elf_abi
!= X86_64_ABI
)
13960 as_fatal (_("Intel K1OM is 64bit only"));
13961 return ELF_TARGET_K1OM_FORMAT
;
13963 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13965 if (x86_elf_abi
!= I386_ABI
)
13966 as_fatal (_("Intel MCU is 32bit only"));
13967 return ELF_TARGET_IAMCU_FORMAT
;
13973 #if defined (OBJ_MACH_O)
13974 case bfd_target_mach_o_flavour
:
13975 if (flag_code
== CODE_64BIT
)
13977 use_rela_relocations
= 1;
13979 return "mach-o-x86-64";
13982 return "mach-o-i386";
13990 #endif /* OBJ_MAYBE_ more than one */
13993 md_undefined_symbol (char *name
)
13995 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13996 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13997 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13998 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14002 if (symbol_find (name
))
14003 as_bad (_("GOT already in symbol table"));
14004 GOT_symbol
= symbol_new (name
, undefined_section
,
14005 &zero_address_frag
, 0);
14012 /* Round up a section size to the appropriate boundary. */
14015 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14017 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14018 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14020 /* For a.out, force the section size to be aligned. If we don't do
14021 this, BFD will align it for us, but it will not write out the
14022 final bytes of the section. This may be a bug in BFD, but it is
14023 easier to fix it here since that is how the other a.out targets
14027 align
= bfd_section_alignment (segment
);
14028 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14035 /* On the i386, PC-relative offsets are relative to the start of the
14036 next instruction. That is, the address of the offset, plus its
14037 size, since the offset is always the last part of the insn. */
14040 md_pcrel_from (fixS
*fixP
)
14042 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14048 s_bss (int ignore ATTRIBUTE_UNUSED
)
14052 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14054 obj_elf_section_change_hook ();
14056 temp
= get_absolute_expression ();
14057 subseg_set (bss_section
, (subsegT
) temp
);
14058 demand_empty_rest_of_line ();
14063 /* Remember constant directive. */
14066 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14068 if (last_insn
.kind
!= last_insn_directive
14069 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14071 last_insn
.seg
= now_seg
;
14072 last_insn
.kind
= last_insn_directive
;
14073 last_insn
.name
= "constant directive";
14074 last_insn
.file
= as_where (&last_insn
.line
);
14075 if (lfence_before_ret
!= lfence_before_ret_none
)
14077 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14078 as_warn (_("constant directive skips -mlfence-before-ret "
14079 "and -mlfence-before-indirect-branch"));
14081 as_warn (_("constant directive skips -mlfence-before-ret"));
14083 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14084 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14089 i386_validate_fix (fixS
*fixp
)
14091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14092 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14093 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14094 return IS_ELF
&& fixp
->fx_addsy
14095 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14096 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14099 if (fixp
->fx_subsy
)
14101 if (fixp
->fx_subsy
== GOT_symbol
)
14103 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14107 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14108 if (fixp
->fx_tcbit2
)
14109 fixp
->fx_r_type
= (fixp
->fx_tcbit
14110 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14111 : BFD_RELOC_X86_64_GOTPCRELX
);
14114 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14119 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14121 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14123 fixp
->fx_subsy
= 0;
14126 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14129 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14130 to section. Since PLT32 relocation must be against symbols,
14131 turn such PLT32 relocation into PC32 relocation. */
14133 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14134 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14135 && symbol_section_p (fixp
->fx_addsy
))
14136 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14139 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14140 && fixp
->fx_tcbit2
)
14141 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14150 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14153 bfd_reloc_code_real_type code
;
14155 switch (fixp
->fx_r_type
)
14157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14160 case BFD_RELOC_SIZE32
:
14161 case BFD_RELOC_SIZE64
:
14163 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14164 && (!fixp
->fx_subsy
14165 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14166 sym
= fixp
->fx_addsy
;
14167 else if (fixp
->fx_subsy
14168 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14169 && (!fixp
->fx_addsy
14170 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14171 sym
= fixp
->fx_subsy
;
14174 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14176 /* Resolve size relocation against local symbol to size of
14177 the symbol plus addend. */
14178 valueT value
= S_GET_SIZE (sym
);
14180 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14181 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14182 if (sym
== fixp
->fx_subsy
)
14185 if (fixp
->fx_addsy
)
14186 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14188 else if (fixp
->fx_subsy
)
14189 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14190 value
+= fixp
->fx_offset
;
14191 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14193 && !fits_in_unsigned_long (value
))
14194 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14195 _("symbol size computation overflow"));
14196 fixp
->fx_addsy
= NULL
;
14197 fixp
->fx_subsy
= NULL
;
14198 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14201 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14204 "unsupported expression involving @size");
14208 /* Fall through. */
14210 case BFD_RELOC_X86_64_PLT32
:
14211 case BFD_RELOC_X86_64_GOT32
:
14212 case BFD_RELOC_X86_64_GOTPCREL
:
14213 case BFD_RELOC_X86_64_GOTPCRELX
:
14214 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14215 case BFD_RELOC_386_PLT32
:
14216 case BFD_RELOC_386_GOT32
:
14217 case BFD_RELOC_386_GOT32X
:
14218 case BFD_RELOC_386_GOTOFF
:
14219 case BFD_RELOC_386_GOTPC
:
14220 case BFD_RELOC_386_TLS_GD
:
14221 case BFD_RELOC_386_TLS_LDM
:
14222 case BFD_RELOC_386_TLS_LDO_32
:
14223 case BFD_RELOC_386_TLS_IE_32
:
14224 case BFD_RELOC_386_TLS_IE
:
14225 case BFD_RELOC_386_TLS_GOTIE
:
14226 case BFD_RELOC_386_TLS_LE_32
:
14227 case BFD_RELOC_386_TLS_LE
:
14228 case BFD_RELOC_386_TLS_GOTDESC
:
14229 case BFD_RELOC_386_TLS_DESC_CALL
:
14230 case BFD_RELOC_X86_64_TLSGD
:
14231 case BFD_RELOC_X86_64_TLSLD
:
14232 case BFD_RELOC_X86_64_DTPOFF32
:
14233 case BFD_RELOC_X86_64_DTPOFF64
:
14234 case BFD_RELOC_X86_64_GOTTPOFF
:
14235 case BFD_RELOC_X86_64_TPOFF32
:
14236 case BFD_RELOC_X86_64_TPOFF64
:
14237 case BFD_RELOC_X86_64_GOTOFF64
:
14238 case BFD_RELOC_X86_64_GOTPC32
:
14239 case BFD_RELOC_X86_64_GOT64
:
14240 case BFD_RELOC_X86_64_GOTPCREL64
:
14241 case BFD_RELOC_X86_64_GOTPC64
:
14242 case BFD_RELOC_X86_64_GOTPLT64
:
14243 case BFD_RELOC_X86_64_PLTOFF64
:
14244 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14245 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14246 case BFD_RELOC_RVA
:
14247 case BFD_RELOC_VTABLE_ENTRY
:
14248 case BFD_RELOC_VTABLE_INHERIT
:
14250 case BFD_RELOC_32_SECREL
:
14252 code
= fixp
->fx_r_type
;
14254 case BFD_RELOC_X86_64_32S
:
14255 if (!fixp
->fx_pcrel
)
14257 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14258 code
= fixp
->fx_r_type
;
14261 /* Fall through. */
14263 if (fixp
->fx_pcrel
)
14265 switch (fixp
->fx_size
)
14268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14269 _("can not do %d byte pc-relative relocation"),
14271 code
= BFD_RELOC_32_PCREL
;
14273 case 1: code
= BFD_RELOC_8_PCREL
; break;
14274 case 2: code
= BFD_RELOC_16_PCREL
; break;
14275 case 4: code
= BFD_RELOC_32_PCREL
; break;
14277 case 8: code
= BFD_RELOC_64_PCREL
; break;
14283 switch (fixp
->fx_size
)
14286 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14287 _("can not do %d byte relocation"),
14289 code
= BFD_RELOC_32
;
14291 case 1: code
= BFD_RELOC_8
; break;
14292 case 2: code
= BFD_RELOC_16
; break;
14293 case 4: code
= BFD_RELOC_32
; break;
14295 case 8: code
= BFD_RELOC_64
; break;
14302 if ((code
== BFD_RELOC_32
14303 || code
== BFD_RELOC_32_PCREL
14304 || code
== BFD_RELOC_X86_64_32S
)
14306 && fixp
->fx_addsy
== GOT_symbol
)
14309 code
= BFD_RELOC_386_GOTPC
;
14311 code
= BFD_RELOC_X86_64_GOTPC32
;
14313 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14315 && fixp
->fx_addsy
== GOT_symbol
)
14317 code
= BFD_RELOC_X86_64_GOTPC64
;
14320 rel
= XNEW (arelent
);
14321 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14322 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14324 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14326 if (!use_rela_relocations
)
14328 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14329 vtable entry to be used in the relocation's section offset. */
14330 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14331 rel
->address
= fixp
->fx_offset
;
14332 #if defined (OBJ_COFF) && defined (TE_PE)
14333 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14334 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14339 /* Use the rela in 64bit mode. */
14342 if (disallow_64bit_reloc
)
14345 case BFD_RELOC_X86_64_DTPOFF64
:
14346 case BFD_RELOC_X86_64_TPOFF64
:
14347 case BFD_RELOC_64_PCREL
:
14348 case BFD_RELOC_X86_64_GOTOFF64
:
14349 case BFD_RELOC_X86_64_GOT64
:
14350 case BFD_RELOC_X86_64_GOTPCREL64
:
14351 case BFD_RELOC_X86_64_GOTPC64
:
14352 case BFD_RELOC_X86_64_GOTPLT64
:
14353 case BFD_RELOC_X86_64_PLTOFF64
:
14354 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14355 _("cannot represent relocation type %s in x32 mode"),
14356 bfd_get_reloc_code_name (code
));
14362 if (!fixp
->fx_pcrel
)
14363 rel
->addend
= fixp
->fx_offset
;
14367 case BFD_RELOC_X86_64_PLT32
:
14368 case BFD_RELOC_X86_64_GOT32
:
14369 case BFD_RELOC_X86_64_GOTPCREL
:
14370 case BFD_RELOC_X86_64_GOTPCRELX
:
14371 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14372 case BFD_RELOC_X86_64_TLSGD
:
14373 case BFD_RELOC_X86_64_TLSLD
:
14374 case BFD_RELOC_X86_64_GOTTPOFF
:
14375 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14376 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14377 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14380 rel
->addend
= (section
->vma
14382 + fixp
->fx_addnumber
14383 + md_pcrel_from (fixp
));
14388 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14389 if (rel
->howto
== NULL
)
14391 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14392 _("cannot represent relocation type %s"),
14393 bfd_get_reloc_code_name (code
));
14394 /* Set howto to a garbage value so that we can keep going. */
14395 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14396 gas_assert (rel
->howto
!= NULL
);
14402 #include "tc-i386-intel.c"
14405 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14407 int saved_naked_reg
;
14408 char saved_register_dot
;
14410 saved_naked_reg
= allow_naked_reg
;
14411 allow_naked_reg
= 1;
14412 saved_register_dot
= register_chars
['.'];
14413 register_chars
['.'] = '.';
14414 allow_pseudo_reg
= 1;
14415 expression_and_evaluate (exp
);
14416 allow_pseudo_reg
= 0;
14417 register_chars
['.'] = saved_register_dot
;
14418 allow_naked_reg
= saved_naked_reg
;
14420 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14422 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14424 exp
->X_op
= O_constant
;
14425 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14426 .dw2_regnum
[flag_code
>> 1];
14429 exp
->X_op
= O_illegal
;
14434 tc_x86_frame_initial_instructions (void)
14436 static unsigned int sp_regno
[2];
14438 if (!sp_regno
[flag_code
>> 1])
14440 char *saved_input
= input_line_pointer
;
14441 char sp
[][4] = {"esp", "rsp"};
14444 input_line_pointer
= sp
[flag_code
>> 1];
14445 tc_x86_parse_to_dw2regnum (&exp
);
14446 gas_assert (exp
.X_op
== O_constant
);
14447 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14448 input_line_pointer
= saved_input
;
14451 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14452 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14456 x86_dwarf2_addr_size (void)
14458 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14459 if (x86_elf_abi
== X86_64_X32_ABI
)
14462 return bfd_arch_bits_per_address (stdoutput
) / 8;
14466 i386_elf_section_type (const char *str
, size_t len
)
14468 if (flag_code
== CODE_64BIT
14469 && len
== sizeof ("unwind") - 1
14470 && startswith (str
, "unwind"))
14471 return SHT_X86_64_UNWIND
;
14478 i386_solaris_fix_up_eh_frame (segT sec
)
14480 if (flag_code
== CODE_64BIT
)
14481 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14487 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14491 exp
.X_op
= O_secrel
;
14492 exp
.X_add_symbol
= symbol
;
14493 exp
.X_add_number
= 0;
14494 emit_expr (&exp
, size
);
14498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14499 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14502 x86_64_section_letter (int letter
, const char **ptr_msg
)
14504 if (flag_code
== CODE_64BIT
)
14507 return SHF_X86_64_LARGE
;
14509 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14512 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14517 x86_64_section_word (char *str
, size_t len
)
14519 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14520 return SHF_X86_64_LARGE
;
14526 handle_large_common (int small ATTRIBUTE_UNUSED
)
14528 if (flag_code
!= CODE_64BIT
)
14530 s_comm_internal (0, elf_common_parse
);
14531 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14535 static segT lbss_section
;
14536 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14537 asection
*saved_bss_section
= bss_section
;
14539 if (lbss_section
== NULL
)
14541 flagword applicable
;
14542 segT seg
= now_seg
;
14543 subsegT subseg
= now_subseg
;
14545 /* The .lbss section is for local .largecomm symbols. */
14546 lbss_section
= subseg_new (".lbss", 0);
14547 applicable
= bfd_applicable_section_flags (stdoutput
);
14548 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14549 seg_info (lbss_section
)->bss
= 1;
14551 subseg_set (seg
, subseg
);
14554 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14555 bss_section
= lbss_section
;
14557 s_comm_internal (0, elf_common_parse
);
14559 elf_com_section_ptr
= saved_com_section_ptr
;
14560 bss_section
= saved_bss_section
;
14563 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */