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1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifdef HAVE_LIMITS_H
37 #include <limits.h>
38 #else
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
41 #endif
42 #ifndef INT_MAX
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
44 #endif
45 #endif
46
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
49 #endif
50
51 #ifndef DEFAULT_ARCH
52 #define DEFAULT_ARCH "i386"
53 #endif
54
55 #ifndef INLINE
56 #if __GNUC__ >= 2
57 #define INLINE __inline__
58 #else
59 #define INLINE
60 #endif
61 #endif
62
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
68 #define WAIT_PREFIX 0
69 #define SEG_PREFIX 1
70 #define ADDR_PREFIX 2
71 #define DATA_PREFIX 3
72 #define REP_PREFIX 4
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
75 #define LOCK_PREFIX 5
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
83
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 in instructions. */
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94
95 #define END_OF_INSN '\0'
96
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
99
100 /*
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
105 END.
106 */
107 typedef struct
108 {
109 const insn_template *start;
110 const insn_template *end;
111 }
112 templates;
113
114 /* 386 operand encoding bytes: see 386 book for details of this. */
115 typedef struct
116 {
117 unsigned int regmem; /* codes register or memory operand */
118 unsigned int reg; /* codes register operand (or extended opcode) */
119 unsigned int mode; /* how to interpret regmem & reg */
120 }
121 modrm_byte;
122
123 /* x86-64 extension prefix. */
124 typedef int rex_byte;
125
126 /* 386 opcode byte to code indirect addressing. */
127 typedef struct
128 {
129 unsigned base;
130 unsigned index;
131 unsigned scale;
132 }
133 sib_byte;
134
135 /* x86 arch names, types and features */
136 typedef struct
137 {
138 const char *name; /* arch name */
139 unsigned int len; /* arch string length */
140 enum processor_type type; /* arch type */
141 i386_cpu_flags flags; /* cpu feature flags */
142 unsigned int skip; /* show_arch should skip this. */
143 }
144 arch_entry;
145
146 /* Used to turn off indicated flags. */
147 typedef struct
148 {
149 const char *name; /* arch name */
150 unsigned int len; /* arch string length */
151 i386_cpu_flags flags; /* cpu feature flags */
152 }
153 noarch_entry;
154
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
163 #ifdef TE_PE
164 static void pe_directive_secrel (int);
165 #endif
166 static void signed_cons (int);
167 static char *output_invalid (int c);
168 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
169 const char *);
170 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
171 const char *);
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS *);
175 static int i386_intel_parse_name (const char *, expressionS *);
176 static const reg_entry *parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template *match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry *build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS *, offsetT);
196 static void output_disp (fragS *, offsetT);
197 #ifndef I386COFF
198 static void s_bss (int);
199 #endif
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED);
202
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
209 #endif
210
211 static const char *default_arch = DEFAULT_ARCH;
212
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,
215 { Dw2Inval, Dw2Inval } };
216
217 /* This struct describes rounding control and SAE in the instruction. */
218 struct RC_Operation
219 {
220 enum rc_type
221 {
222 rne = 0,
223 rd,
224 ru,
225 rz,
226 saeonly
227 } type;
228 int operand;
229 };
230
231 static struct RC_Operation rc_op;
232
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
237 {
238 const reg_entry *mask;
239 unsigned int zeroing;
240 /* The operand where this operation is associated. */
241 int operand;
242 };
243
244 static struct Mask_Operation mask_op;
245
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 broadcast factor. */
248 struct Broadcast_Operation
249 {
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
251 int type;
252
253 /* Index of broadcasted operand. */
254 int operand;
255
256 /* Number of bytes to broadcast. */
257 int bytes;
258 };
259
260 static struct Broadcast_Operation broadcast_op;
261
262 /* VEX prefix. */
263 typedef struct
264 {
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes[4];
267 unsigned int length;
268 /* Destination or source register specifier. */
269 const reg_entry *register_specifier;
270 } vex_prefix;
271
272 /* 'md_assemble ()' gathers together information and puts it into a
273 i386_insn. */
274
275 union i386_op
276 {
277 expressionS *disps;
278 expressionS *imms;
279 const reg_entry *regs;
280 };
281
282 enum i386_error
283 {
284 operand_size_mismatch,
285 operand_type_mismatch,
286 register_type_mismatch,
287 number_of_operands_mismatch,
288 invalid_instruction_suffix,
289 bad_imm4,
290 unsupported_with_intel_mnemonic,
291 unsupported_syntax,
292 unsupported,
293 invalid_sib_address,
294 invalid_vsib_address,
295 invalid_vector_register_set,
296 invalid_tmm_register_set,
297 unsupported_vector_index_register,
298 unsupported_broadcast,
299 broadcast_needed,
300 unsupported_masking,
301 mask_not_on_destination,
302 no_default_mask,
303 unsupported_rc_sae,
304 rc_sae_operand_not_last_imm,
305 invalid_register_operand,
306 };
307
308 struct _i386_insn
309 {
310 /* TM holds the template for the insn were currently assembling. */
311 insn_template tm;
312
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
315 char suffix;
316
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands;
319
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
322 operands. */
323 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
324
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types[MAX_OPERANDS];
328
329 /* Displacement expression, immediate expression, or register for each
330 operand. */
331 union i386_op op[MAX_OPERANDS];
332
333 /* Flags for operands. */
334 unsigned int flags[MAX_OPERANDS];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
337
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
340
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry *base_reg;
344 const reg_entry *index_reg;
345 unsigned int log2_scale_factor;
346
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry *seg[2];
350
351 /* Copied first memory operand string, for re-checking. */
352 char *memop1_string;
353
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes;
357 unsigned char prefix[MAX_PREFIXES];
358
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form;
361
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute;
364
365 /* Extended states. */
366 enum
367 {
368 /* Use MMX state. */
369 xstate_mmx = 1 << 0,
370 /* Use XMM state. */
371 xstate_xmm = 1 << 1,
372 /* Use YMM state. */
373 xstate_ymm = 1 << 2 | xstate_xmm,
374 /* Use ZMM state. */
375 xstate_zmm = 1 << 3 | xstate_ymm,
376 /* Use TMM state. */
377 xstate_tmm = 1 << 4
378 } xstate;
379
380 /* Has GOTPC or TLS relocation. */
381 bfd_boolean has_gotpc_tls_reloc;
382
383 /* RM and SIB are the modrm byte and the sib byte where the
384 addressing modes of this insn are encoded. */
385 modrm_byte rm;
386 rex_byte rex;
387 rex_byte vrex;
388 sib_byte sib;
389 vex_prefix vex;
390
391 /* Masking attributes. */
392 struct Mask_Operation *mask;
393
394 /* Rounding control and SAE attributes. */
395 struct RC_Operation *rounding;
396
397 /* Broadcasting attributes. */
398 struct Broadcast_Operation *broadcast;
399
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift;
402
403 /* Prefer load or store in encoding. */
404 enum
405 {
406 dir_encoding_default = 0,
407 dir_encoding_load,
408 dir_encoding_store,
409 dir_encoding_swap
410 } dir_encoding;
411
412 /* Prefer 8bit or 32bit displacement in encoding. */
413 enum
414 {
415 disp_encoding_default = 0,
416 disp_encoding_8bit,
417 disp_encoding_32bit
418 } disp_encoding;
419
420 /* Prefer the REX byte in encoding. */
421 bfd_boolean rex_encoding;
422
423 /* Disable instruction size optimization. */
424 bfd_boolean no_optimize;
425
426 /* How to encode vector instructions. */
427 enum
428 {
429 vex_encoding_default = 0,
430 vex_encoding_vex,
431 vex_encoding_vex3,
432 vex_encoding_evex,
433 vex_encoding_error
434 } vec_encoding;
435
436 /* REP prefix. */
437 const char *rep_prefix;
438
439 /* HLE prefix. */
440 const char *hle_prefix;
441
442 /* Have BND prefix. */
443 const char *bnd_prefix;
444
445 /* Have NOTRACK prefix. */
446 const char *notrack_prefix;
447
448 /* Error message. */
449 enum i386_error error;
450 };
451
452 typedef struct _i386_insn i386_insn;
453
454 /* Link RC type with corresponding string, that'll be looked for in
455 asm. */
456 struct RC_name
457 {
458 enum rc_type type;
459 const char *name;
460 unsigned int len;
461 };
462
463 static const struct RC_name RC_NamesTable[] =
464 {
465 { rne, STRING_COMMA_LEN ("rn-sae") },
466 { rd, STRING_COMMA_LEN ("rd-sae") },
467 { ru, STRING_COMMA_LEN ("ru-sae") },
468 { rz, STRING_COMMA_LEN ("rz-sae") },
469 { saeonly, STRING_COMMA_LEN ("sae") },
470 };
471
472 /* List of chars besides those in app.c:symbol_chars that can start an
473 operand. Used to prevent the scrubber eating vital white-space. */
474 const char extra_symbol_chars[] = "*%-([{}"
475 #ifdef LEX_AT
476 "@"
477 #endif
478 #ifdef LEX_QM
479 "?"
480 #endif
481 ;
482
483 #if (defined (TE_I386AIX) \
484 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
485 && !defined (TE_GNU) \
486 && !defined (TE_LINUX) \
487 && !defined (TE_FreeBSD) \
488 && !defined (TE_DragonFly) \
489 && !defined (TE_NetBSD)))
490 /* This array holds the chars that always start a comment. If the
491 pre-processor is disabled, these aren't very useful. The option
492 --divide will remove '/' from this list. */
493 const char *i386_comment_chars = "#/";
494 #define SVR4_COMMENT_CHARS 1
495 #define PREFIX_SEPARATOR '\\'
496
497 #else
498 const char *i386_comment_chars = "#";
499 #define PREFIX_SEPARATOR '/'
500 #endif
501
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output.
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
508 Also note that comments started like this one will always work if
509 '/' isn't otherwise defined. */
510 const char line_comment_chars[] = "#/";
511
512 const char line_separator_chars[] = ";";
513
514 /* Chars that can be used to separate mant from exp in floating point
515 nums. */
516 const char EXP_CHARS[] = "eE";
517
518 /* Chars that mean this number is a floating point constant
519 As in 0f12.456
520 or 0d1.2345e12. */
521 const char FLT_CHARS[] = "fFdDxX";
522
523 /* Tables for lexical analysis. */
524 static char mnemonic_chars[256];
525 static char register_chars[256];
526 static char operand_chars[256];
527 static char identifier_chars[256];
528 static char digit_chars[256];
529
530 /* Lexical macros. */
531 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
532 #define is_operand_char(x) (operand_chars[(unsigned char) x])
533 #define is_register_char(x) (register_chars[(unsigned char) x])
534 #define is_space_char(x) ((x) == ' ')
535 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
536 #define is_digit_char(x) (digit_chars[(unsigned char) x])
537
538 /* All non-digit non-letter characters that may occur in an operand. */
539 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
540
541 /* md_assemble() always leaves the strings it's passed unaltered. To
542 effect this we maintain a stack of saved characters that we've smashed
543 with '\0's (indicating end of strings for various sub-fields of the
544 assembler instruction). */
545 static char save_stack[32];
546 static char *save_stack_p;
547 #define END_STRING_AND_SAVE(s) \
548 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
549 #define RESTORE_END_STRING(s) \
550 do { *(s) = *--save_stack_p; } while (0)
551
552 /* The instruction we're assembling. */
553 static i386_insn i;
554
555 /* Possible templates for current insn. */
556 static const templates *current_templates;
557
558 /* Per instruction expressionS buffers: max displacements & immediates. */
559 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
560 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
561
562 /* Current operand we are working on. */
563 static int this_operand = -1;
564
565 /* We support four different modes. FLAG_CODE variable is used to distinguish
566 these. */
567
568 enum flag_code {
569 CODE_32BIT,
570 CODE_16BIT,
571 CODE_64BIT };
572
573 static enum flag_code flag_code;
574 static unsigned int object_64bit;
575 static unsigned int disallow_64bit_reloc;
576 static int use_rela_relocations = 0;
577 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
578 static const char *tls_get_addr;
579
580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
583
584 /* The ELF ABI to use. */
585 enum x86_elf_abi
586 {
587 I386_ABI,
588 X86_64_ABI,
589 X86_64_X32_ABI
590 };
591
592 static enum x86_elf_abi x86_elf_abi = I386_ABI;
593 #endif
594
595 #if defined (TE_PE) || defined (TE_PEP)
596 /* Use big object file format. */
597 static int use_big_obj = 0;
598 #endif
599
600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
601 /* 1 if generating code for a shared library. */
602 static int shared = 0;
603 #endif
604
605 /* 1 for intel syntax,
606 0 if att syntax. */
607 static int intel_syntax = 0;
608
609 static enum x86_64_isa
610 {
611 amd64 = 1, /* AMD64 ISA. */
612 intel64 /* Intel64 ISA. */
613 } isa64;
614
615 /* 1 for intel mnemonic,
616 0 if att mnemonic. */
617 static int intel_mnemonic = !SYSV386_COMPAT;
618
619 /* 1 if pseudo registers are permitted. */
620 static int allow_pseudo_reg = 0;
621
622 /* 1 if register prefix % not required. */
623 static int allow_naked_reg = 0;
624
625 /* 1 if the assembler should add BND prefix for all control-transferring
626 instructions supporting it, even if this prefix wasn't specified
627 explicitly. */
628 static int add_bnd_prefix = 0;
629
630 /* 1 if pseudo index register, eiz/riz, is allowed . */
631 static int allow_index_reg = 0;
632
633 /* 1 if the assembler should ignore LOCK prefix, even if it was
634 specified explicitly. */
635 static int omit_lock_prefix = 0;
636
637 /* 1 if the assembler should encode lfence, mfence, and sfence as
638 "lock addl $0, (%{re}sp)". */
639 static int avoid_fence = 0;
640
641 /* 1 if lfence should be inserted after every load. */
642 static int lfence_after_load = 0;
643
644 /* Non-zero if lfence should be inserted before indirect branch. */
645 static enum lfence_before_indirect_branch_kind
646 {
647 lfence_branch_none = 0,
648 lfence_branch_register,
649 lfence_branch_memory,
650 lfence_branch_all
651 }
652 lfence_before_indirect_branch;
653
654 /* Non-zero if lfence should be inserted before ret. */
655 static enum lfence_before_ret_kind
656 {
657 lfence_before_ret_none = 0,
658 lfence_before_ret_not,
659 lfence_before_ret_or,
660 lfence_before_ret_shl
661 }
662 lfence_before_ret;
663
664 /* Types of previous instruction is .byte or prefix. */
665 static struct
666 {
667 segT seg;
668 const char *file;
669 const char *name;
670 unsigned int line;
671 enum last_insn_kind
672 {
673 last_insn_other = 0,
674 last_insn_directive,
675 last_insn_prefix
676 } kind;
677 } last_insn;
678
679 /* 1 if the assembler should generate relax relocations. */
680
681 static int generate_relax_relocations
682 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
683
684 static enum check_kind
685 {
686 check_none = 0,
687 check_warning,
688 check_error
689 }
690 sse_check, operand_check = check_warning;
691
692 /* Non-zero if branches should be aligned within power of 2 boundary. */
693 static int align_branch_power = 0;
694
695 /* Types of branches to align. */
696 enum align_branch_kind
697 {
698 align_branch_none = 0,
699 align_branch_jcc = 1,
700 align_branch_fused = 2,
701 align_branch_jmp = 3,
702 align_branch_call = 4,
703 align_branch_indirect = 5,
704 align_branch_ret = 6
705 };
706
707 /* Type bits of branches to align. */
708 enum align_branch_bit
709 {
710 align_branch_jcc_bit = 1 << align_branch_jcc,
711 align_branch_fused_bit = 1 << align_branch_fused,
712 align_branch_jmp_bit = 1 << align_branch_jmp,
713 align_branch_call_bit = 1 << align_branch_call,
714 align_branch_indirect_bit = 1 << align_branch_indirect,
715 align_branch_ret_bit = 1 << align_branch_ret
716 };
717
718 static unsigned int align_branch = (align_branch_jcc_bit
719 | align_branch_fused_bit
720 | align_branch_jmp_bit);
721
722 /* Types of condition jump used by macro-fusion. */
723 enum mf_jcc_kind
724 {
725 mf_jcc_jo = 0, /* base opcode 0x70 */
726 mf_jcc_jc, /* base opcode 0x72 */
727 mf_jcc_je, /* base opcode 0x74 */
728 mf_jcc_jna, /* base opcode 0x76 */
729 mf_jcc_js, /* base opcode 0x78 */
730 mf_jcc_jp, /* base opcode 0x7a */
731 mf_jcc_jl, /* base opcode 0x7c */
732 mf_jcc_jle, /* base opcode 0x7e */
733 };
734
735 /* Types of compare flag-modifying insntructions used by macro-fusion. */
736 enum mf_cmp_kind
737 {
738 mf_cmp_test_and, /* test/cmp */
739 mf_cmp_alu_cmp, /* add/sub/cmp */
740 mf_cmp_incdec /* inc/dec */
741 };
742
743 /* The maximum padding size for fused jcc. CMP like instruction can
744 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
745 prefixes. */
746 #define MAX_FUSED_JCC_PADDING_SIZE 20
747
748 /* The maximum number of prefixes added for an instruction. */
749 static unsigned int align_branch_prefix_size = 5;
750
751 /* Optimization:
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
754 register.
755 */
756 static int optimize = 0;
757
758 /* Optimization:
759 1. Clear the REX_W bit with register operand if possible.
760 2. Above plus use 128bit vector instruction to clear the full vector
761 register.
762 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
763 "testb $imm7,%r8".
764 */
765 static int optimize_for_space = 0;
766
767 /* Register prefix used for error message. */
768 static const char *register_prefix = "%";
769
770 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
771 leave, push, and pop instructions so that gcc has the same stack
772 frame as in 32 bit mode. */
773 static char stackop_size = '\0';
774
775 /* Non-zero to optimize code alignment. */
776 int optimize_align_code = 1;
777
778 /* Non-zero to quieten some warnings. */
779 static int quiet_warnings = 0;
780
781 /* CPU name. */
782 static const char *cpu_arch_name = NULL;
783 static char *cpu_sub_arch_name = NULL;
784
785 /* CPU feature flags. */
786 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
787
788 /* If we have selected a cpu we are generating instructions for. */
789 static int cpu_arch_tune_set = 0;
790
791 /* Cpu we are generating instructions for. */
792 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
793
794 /* CPU feature flags of cpu we are generating instructions for. */
795 static i386_cpu_flags cpu_arch_tune_flags;
796
797 /* CPU instruction set architecture used. */
798 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
799
800 /* CPU feature flags of instruction set architecture used. */
801 i386_cpu_flags cpu_arch_isa_flags;
802
803 /* If set, conditional jumps are not automatically promoted to handle
804 larger than a byte offset. */
805 static unsigned int no_cond_jump_promotion = 0;
806
807 /* Encode SSE instructions with VEX prefix. */
808 static unsigned int sse2avx;
809
810 /* Encode scalar AVX instructions with specific vector length. */
811 static enum
812 {
813 vex128 = 0,
814 vex256
815 } avxscalar;
816
817 /* Encode VEX WIG instructions with specific vex.w. */
818 static enum
819 {
820 vexw0 = 0,
821 vexw1
822 } vexwig;
823
824 /* Encode scalar EVEX LIG instructions with specific vector length. */
825 static enum
826 {
827 evexl128 = 0,
828 evexl256,
829 evexl512
830 } evexlig;
831
832 /* Encode EVEX WIG instructions with specific evex.w. */
833 static enum
834 {
835 evexw0 = 0,
836 evexw1
837 } evexwig;
838
839 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
840 static enum rc_type evexrcig = rne;
841
842 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
843 static symbolS *GOT_symbol;
844
845 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
846 unsigned int x86_dwarf2_return_column;
847
848 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
849 int x86_cie_data_alignment;
850
851 /* Interface to relax_segment.
852 There are 3 major relax states for 386 jump insns because the
853 different types of jumps add different sizes to frags when we're
854 figuring out what sort of jump to choose to reach a given label.
855
856 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
857 branches which are handled by md_estimate_size_before_relax() and
858 i386_generic_table_relax_frag(). */
859
860 /* Types. */
861 #define UNCOND_JUMP 0
862 #define COND_JUMP 1
863 #define COND_JUMP86 2
864 #define BRANCH_PADDING 3
865 #define BRANCH_PREFIX 4
866 #define FUSED_JCC_PADDING 5
867
868 /* Sizes. */
869 #define CODE16 1
870 #define SMALL 0
871 #define SMALL16 (SMALL | CODE16)
872 #define BIG 2
873 #define BIG16 (BIG | CODE16)
874
875 #ifndef INLINE
876 #ifdef __GNUC__
877 #define INLINE __inline__
878 #else
879 #define INLINE
880 #endif
881 #endif
882
883 #define ENCODE_RELAX_STATE(type, size) \
884 ((relax_substateT) (((type) << 2) | (size)))
885 #define TYPE_FROM_RELAX_STATE(s) \
886 ((s) >> 2)
887 #define DISP_SIZE_FROM_RELAX_STATE(s) \
888 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
889
890 /* This table is used by relax_frag to promote short jumps to long
891 ones where necessary. SMALL (short) jumps may be promoted to BIG
892 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
893 don't allow a short jump in a 32 bit code segment to be promoted to
894 a 16 bit offset jump because it's slower (requires data size
895 prefix), and doesn't work, unless the destination is in the bottom
896 64k of the code segment (The top 16 bits of eip are zeroed). */
897
898 const relax_typeS md_relax_table[] =
899 {
900 /* The fields are:
901 1) most positive reach of this state,
902 2) most negative reach of this state,
903 3) how many bytes this mode will have in the variable part of the frag
904 4) which index into the table to try if we can't fit into this one. */
905
906 /* UNCOND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
909 /* dword jmp adds 4 bytes to frag:
910 0 extra opcode bytes, 4 displacement bytes. */
911 {0, 0, 4, 0},
912 /* word jmp adds 2 byte2 to frag:
913 0 extra opcode bytes, 2 displacement bytes. */
914 {0, 0, 2, 0},
915
916 /* COND_JUMP states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
921 {0, 0, 5, 0},
922 /* word conditionals add 3 bytes to frag:
923 1 extra opcode byte, 2 displacement bytes. */
924 {0, 0, 3, 0},
925
926 /* COND_JUMP86 states. */
927 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
928 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
929 /* dword conditionals adds 5 bytes to frag:
930 1 extra opcode byte, 4 displacement bytes. */
931 {0, 0, 5, 0},
932 /* word conditionals add 4 bytes to frag:
933 1 displacement byte and a 3 byte long branch insn. */
934 {0, 0, 4, 0}
935 };
936
937 static const arch_entry cpu_arch[] =
938 {
939 /* Do not replace the first two entries - i386_target_format()
940 relies on them being there in this order. */
941 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
942 CPU_GENERIC32_FLAGS, 0 },
943 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
944 CPU_GENERIC64_FLAGS, 0 },
945 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
946 CPU_NONE_FLAGS, 0 },
947 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
948 CPU_I186_FLAGS, 0 },
949 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
950 CPU_I286_FLAGS, 0 },
951 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
952 CPU_I386_FLAGS, 0 },
953 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
954 CPU_I486_FLAGS, 0 },
955 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
956 CPU_I586_FLAGS, 0 },
957 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
958 CPU_I686_FLAGS, 0 },
959 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
960 CPU_I586_FLAGS, 0 },
961 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
962 CPU_PENTIUMPRO_FLAGS, 0 },
963 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
964 CPU_P2_FLAGS, 0 },
965 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
966 CPU_P3_FLAGS, 0 },
967 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
968 CPU_P4_FLAGS, 0 },
969 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
970 CPU_CORE_FLAGS, 0 },
971 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
972 CPU_NOCONA_FLAGS, 0 },
973 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
974 CPU_CORE_FLAGS, 1 },
975 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
976 CPU_CORE_FLAGS, 0 },
977 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
978 CPU_CORE2_FLAGS, 1 },
979 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
980 CPU_CORE2_FLAGS, 0 },
981 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
982 CPU_COREI7_FLAGS, 0 },
983 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
984 CPU_L1OM_FLAGS, 0 },
985 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
986 CPU_K1OM_FLAGS, 0 },
987 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
988 CPU_IAMCU_FLAGS, 0 },
989 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
990 CPU_K6_FLAGS, 0 },
991 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
992 CPU_K6_2_FLAGS, 0 },
993 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
994 CPU_ATHLON_FLAGS, 0 },
995 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
996 CPU_K8_FLAGS, 1 },
997 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
998 CPU_K8_FLAGS, 0 },
999 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
1000 CPU_K8_FLAGS, 0 },
1001 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
1002 CPU_AMDFAM10_FLAGS, 0 },
1003 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
1004 CPU_BDVER1_FLAGS, 0 },
1005 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
1006 CPU_BDVER2_FLAGS, 0 },
1007 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
1008 CPU_BDVER3_FLAGS, 0 },
1009 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
1010 CPU_BDVER4_FLAGS, 0 },
1011 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
1012 CPU_ZNVER1_FLAGS, 0 },
1013 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
1014 CPU_ZNVER2_FLAGS, 0 },
1015 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
1016 CPU_BTVER1_FLAGS, 0 },
1017 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
1018 CPU_BTVER2_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
1020 CPU_8087_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
1022 CPU_287_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
1024 CPU_387_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
1026 CPU_687_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
1028 CPU_CMOV_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
1030 CPU_FXSR_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
1032 CPU_MMX_FLAGS, 0 },
1033 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
1034 CPU_SSE_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
1036 CPU_SSE2_FLAGS, 0 },
1037 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
1038 CPU_SSE3_FLAGS, 0 },
1039 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1040 CPU_SSE4A_FLAGS, 0 },
1041 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
1042 CPU_SSSE3_FLAGS, 0 },
1043 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
1044 CPU_SSE4_1_FLAGS, 0 },
1045 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
1046 CPU_SSE4_2_FLAGS, 0 },
1047 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
1048 CPU_SSE4_2_FLAGS, 0 },
1049 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
1050 CPU_AVX_FLAGS, 0 },
1051 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
1052 CPU_AVX2_FLAGS, 0 },
1053 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
1054 CPU_AVX512F_FLAGS, 0 },
1055 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
1056 CPU_AVX512CD_FLAGS, 0 },
1057 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
1058 CPU_AVX512ER_FLAGS, 0 },
1059 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
1060 CPU_AVX512PF_FLAGS, 0 },
1061 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
1062 CPU_AVX512DQ_FLAGS, 0 },
1063 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
1064 CPU_AVX512BW_FLAGS, 0 },
1065 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
1066 CPU_AVX512VL_FLAGS, 0 },
1067 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
1068 CPU_VMX_FLAGS, 0 },
1069 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
1070 CPU_VMFUNC_FLAGS, 0 },
1071 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
1072 CPU_SMX_FLAGS, 0 },
1073 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
1074 CPU_XSAVE_FLAGS, 0 },
1075 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
1076 CPU_XSAVEOPT_FLAGS, 0 },
1077 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
1078 CPU_XSAVEC_FLAGS, 0 },
1079 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
1080 CPU_XSAVES_FLAGS, 0 },
1081 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
1082 CPU_AES_FLAGS, 0 },
1083 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
1084 CPU_PCLMUL_FLAGS, 0 },
1085 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
1086 CPU_PCLMUL_FLAGS, 1 },
1087 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
1088 CPU_FSGSBASE_FLAGS, 0 },
1089 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
1090 CPU_RDRND_FLAGS, 0 },
1091 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
1092 CPU_F16C_FLAGS, 0 },
1093 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
1094 CPU_BMI2_FLAGS, 0 },
1095 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
1096 CPU_FMA_FLAGS, 0 },
1097 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
1098 CPU_FMA4_FLAGS, 0 },
1099 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
1100 CPU_XOP_FLAGS, 0 },
1101 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
1102 CPU_LWP_FLAGS, 0 },
1103 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
1104 CPU_MOVBE_FLAGS, 0 },
1105 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
1106 CPU_CX16_FLAGS, 0 },
1107 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
1108 CPU_EPT_FLAGS, 0 },
1109 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
1110 CPU_LZCNT_FLAGS, 0 },
1111 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN,
1112 CPU_POPCNT_FLAGS, 0 },
1113 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
1114 CPU_HLE_FLAGS, 0 },
1115 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
1116 CPU_RTM_FLAGS, 0 },
1117 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
1118 CPU_INVPCID_FLAGS, 0 },
1119 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
1120 CPU_CLFLUSH_FLAGS, 0 },
1121 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
1122 CPU_NOP_FLAGS, 0 },
1123 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
1124 CPU_SYSCALL_FLAGS, 0 },
1125 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
1126 CPU_RDTSCP_FLAGS, 0 },
1127 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
1128 CPU_3DNOW_FLAGS, 0 },
1129 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
1130 CPU_3DNOWA_FLAGS, 0 },
1131 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
1132 CPU_PADLOCK_FLAGS, 0 },
1133 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
1134 CPU_SVME_FLAGS, 1 },
1135 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
1136 CPU_SVME_FLAGS, 0 },
1137 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1138 CPU_SSE4A_FLAGS, 0 },
1139 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
1140 CPU_ABM_FLAGS, 0 },
1141 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
1142 CPU_BMI_FLAGS, 0 },
1143 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
1144 CPU_TBM_FLAGS, 0 },
1145 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
1146 CPU_ADX_FLAGS, 0 },
1147 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1148 CPU_RDSEED_FLAGS, 0 },
1149 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1150 CPU_PRFCHW_FLAGS, 0 },
1151 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1152 CPU_SMAP_FLAGS, 0 },
1153 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1154 CPU_MPX_FLAGS, 0 },
1155 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1156 CPU_SHA_FLAGS, 0 },
1157 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1158 CPU_CLFLUSHOPT_FLAGS, 0 },
1159 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1160 CPU_PREFETCHWT1_FLAGS, 0 },
1161 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1162 CPU_SE1_FLAGS, 0 },
1163 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1164 CPU_CLWB_FLAGS, 0 },
1165 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1166 CPU_AVX512IFMA_FLAGS, 0 },
1167 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1168 CPU_AVX512VBMI_FLAGS, 0 },
1169 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1170 CPU_AVX512_4FMAPS_FLAGS, 0 },
1171 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1172 CPU_AVX512_4VNNIW_FLAGS, 0 },
1173 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1174 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1175 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1176 CPU_AVX512_VBMI2_FLAGS, 0 },
1177 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1178 CPU_AVX512_VNNI_FLAGS, 0 },
1179 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1180 CPU_AVX512_BITALG_FLAGS, 0 },
1181 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1182 CPU_CLZERO_FLAGS, 0 },
1183 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1184 CPU_MWAITX_FLAGS, 0 },
1185 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1186 CPU_OSPKE_FLAGS, 0 },
1187 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1188 CPU_RDPID_FLAGS, 0 },
1189 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1190 CPU_PTWRITE_FLAGS, 0 },
1191 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1192 CPU_IBT_FLAGS, 0 },
1193 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1194 CPU_SHSTK_FLAGS, 0 },
1195 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1196 CPU_GFNI_FLAGS, 0 },
1197 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1198 CPU_VAES_FLAGS, 0 },
1199 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1200 CPU_VPCLMULQDQ_FLAGS, 0 },
1201 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1202 CPU_WBNOINVD_FLAGS, 0 },
1203 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1204 CPU_PCONFIG_FLAGS, 0 },
1205 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1206 CPU_WAITPKG_FLAGS, 0 },
1207 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1208 CPU_CLDEMOTE_FLAGS, 0 },
1209 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN,
1210 CPU_AMX_INT8_FLAGS, 0 },
1211 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN,
1212 CPU_AMX_BF16_FLAGS, 0 },
1213 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN,
1214 CPU_AMX_TILE_FLAGS, 0 },
1215 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1216 CPU_MOVDIRI_FLAGS, 0 },
1217 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1218 CPU_MOVDIR64B_FLAGS, 0 },
1219 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
1220 CPU_AVX512_BF16_FLAGS, 0 },
1221 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
1222 CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
1223 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
1224 CPU_ENQCMD_FLAGS, 0 },
1225 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN,
1226 CPU_SERIALIZE_FLAGS, 0 },
1227 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN,
1228 CPU_RDPRU_FLAGS, 0 },
1229 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
1230 CPU_MCOMMIT_FLAGS, 0 },
1231 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN,
1232 CPU_SEV_ES_FLAGS, 0 },
1233 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN,
1234 CPU_TSXLDTRK_FLAGS, 0 },
1235 };
1236
1237 static const noarch_entry cpu_noarch[] =
1238 {
1239 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1240 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1241 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1242 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1243 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1244 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1245 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1246 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1247 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1248 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1249 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS },
1250 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1251 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1252 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1253 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1254 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1255 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1256 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1257 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1258 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1259 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1260 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1261 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1262 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1263 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1264 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1265 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1266 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1267 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1268 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1269 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1270 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1271 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1272 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1273 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS },
1274 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS },
1275 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS },
1276 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1277 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1278 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
1279 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1280 CPU_ANY_AVX512_VP2INTERSECT_FLAGS },
1281 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
1282 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS },
1283 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS },
1284 };
1285
1286 #ifdef I386COFF
1287 /* Like s_lcomm_internal in gas/read.c but the alignment string
1288 is allowed to be optional. */
1289
1290 static symbolS *
1291 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1292 {
1293 addressT align = 0;
1294
1295 SKIP_WHITESPACE ();
1296
1297 if (needs_align
1298 && *input_line_pointer == ',')
1299 {
1300 align = parse_align (needs_align - 1);
1301
1302 if (align == (addressT) -1)
1303 return NULL;
1304 }
1305 else
1306 {
1307 if (size >= 8)
1308 align = 3;
1309 else if (size >= 4)
1310 align = 2;
1311 else if (size >= 2)
1312 align = 1;
1313 else
1314 align = 0;
1315 }
1316
1317 bss_alloc (symbolP, size, align);
1318 return symbolP;
1319 }
1320
1321 static void
1322 pe_lcomm (int needs_align)
1323 {
1324 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1325 }
1326 #endif
1327
1328 const pseudo_typeS md_pseudo_table[] =
1329 {
1330 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1331 {"align", s_align_bytes, 0},
1332 #else
1333 {"align", s_align_ptwo, 0},
1334 #endif
1335 {"arch", set_cpu_arch, 0},
1336 #ifndef I386COFF
1337 {"bss", s_bss, 0},
1338 #else
1339 {"lcomm", pe_lcomm, 1},
1340 #endif
1341 {"ffloat", float_cons, 'f'},
1342 {"dfloat", float_cons, 'd'},
1343 {"tfloat", float_cons, 'x'},
1344 {"value", cons, 2},
1345 {"slong", signed_cons, 4},
1346 {"noopt", s_ignore, 0},
1347 {"optim", s_ignore, 0},
1348 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1349 {"code16", set_code_flag, CODE_16BIT},
1350 {"code32", set_code_flag, CODE_32BIT},
1351 #ifdef BFD64
1352 {"code64", set_code_flag, CODE_64BIT},
1353 #endif
1354 {"intel_syntax", set_intel_syntax, 1},
1355 {"att_syntax", set_intel_syntax, 0},
1356 {"intel_mnemonic", set_intel_mnemonic, 1},
1357 {"att_mnemonic", set_intel_mnemonic, 0},
1358 {"allow_index_reg", set_allow_index_reg, 1},
1359 {"disallow_index_reg", set_allow_index_reg, 0},
1360 {"sse_check", set_check, 0},
1361 {"operand_check", set_check, 1},
1362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1363 {"largecomm", handle_large_common, 0},
1364 #else
1365 {"file", dwarf2_directive_file, 0},
1366 {"loc", dwarf2_directive_loc, 0},
1367 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1368 #endif
1369 #ifdef TE_PE
1370 {"secrel32", pe_directive_secrel, 0},
1371 #endif
1372 {0, 0, 0}
1373 };
1374
1375 /* For interface with expression (). */
1376 extern char *input_line_pointer;
1377
1378 /* Hash table for instruction mnemonic lookup. */
1379 static struct hash_control *op_hash;
1380
1381 /* Hash table for register lookup. */
1382 static struct hash_control *reg_hash;
1383 \f
1384 /* Various efficient no-op patterns for aligning code labels.
1385 Note: Don't try to assemble the instructions in the comments.
1386 0L and 0w are not legal. */
1387 static const unsigned char f32_1[] =
1388 {0x90}; /* nop */
1389 static const unsigned char f32_2[] =
1390 {0x66,0x90}; /* xchg %ax,%ax */
1391 static const unsigned char f32_3[] =
1392 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1393 static const unsigned char f32_4[] =
1394 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1395 static const unsigned char f32_6[] =
1396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1397 static const unsigned char f32_7[] =
1398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1399 static const unsigned char f16_3[] =
1400 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1401 static const unsigned char f16_4[] =
1402 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1403 static const unsigned char jump_disp8[] =
1404 {0xeb}; /* jmp disp8 */
1405 static const unsigned char jump32_disp32[] =
1406 {0xe9}; /* jmp disp32 */
1407 static const unsigned char jump16_disp32[] =
1408 {0x66,0xe9}; /* jmp disp32 */
1409 /* 32-bit NOPs patterns. */
1410 static const unsigned char *const f32_patt[] = {
1411 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1412 };
1413 /* 16-bit NOPs patterns. */
1414 static const unsigned char *const f16_patt[] = {
1415 f32_1, f32_2, f16_3, f16_4
1416 };
1417 /* nopl (%[re]ax) */
1418 static const unsigned char alt_3[] =
1419 {0x0f,0x1f,0x00};
1420 /* nopl 0(%[re]ax) */
1421 static const unsigned char alt_4[] =
1422 {0x0f,0x1f,0x40,0x00};
1423 /* nopl 0(%[re]ax,%[re]ax,1) */
1424 static const unsigned char alt_5[] =
1425 {0x0f,0x1f,0x44,0x00,0x00};
1426 /* nopw 0(%[re]ax,%[re]ax,1) */
1427 static const unsigned char alt_6[] =
1428 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1429 /* nopl 0L(%[re]ax) */
1430 static const unsigned char alt_7[] =
1431 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1432 /* nopl 0L(%[re]ax,%[re]ax,1) */
1433 static const unsigned char alt_8[] =
1434 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1435 /* nopw 0L(%[re]ax,%[re]ax,1) */
1436 static const unsigned char alt_9[] =
1437 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1438 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1439 static const unsigned char alt_10[] =
1440 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1441 /* data16 nopw %cs:0L(%eax,%eax,1) */
1442 static const unsigned char alt_11[] =
1443 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1444 /* 32-bit and 64-bit NOPs patterns. */
1445 static const unsigned char *const alt_patt[] = {
1446 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1447 alt_9, alt_10, alt_11
1448 };
1449
1450 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1451 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1452
1453 static void
1454 i386_output_nops (char *where, const unsigned char *const *patt,
1455 int count, int max_single_nop_size)
1456
1457 {
1458 /* Place the longer NOP first. */
1459 int last;
1460 int offset;
1461 const unsigned char *nops;
1462
1463 if (max_single_nop_size < 1)
1464 {
1465 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1466 max_single_nop_size);
1467 return;
1468 }
1469
1470 nops = patt[max_single_nop_size - 1];
1471
1472 /* Use the smaller one if the requsted one isn't available. */
1473 if (nops == NULL)
1474 {
1475 max_single_nop_size--;
1476 nops = patt[max_single_nop_size - 1];
1477 }
1478
1479 last = count % max_single_nop_size;
1480
1481 count -= last;
1482 for (offset = 0; offset < count; offset += max_single_nop_size)
1483 memcpy (where + offset, nops, max_single_nop_size);
1484
1485 if (last)
1486 {
1487 nops = patt[last - 1];
1488 if (nops == NULL)
1489 {
1490 /* Use the smaller one plus one-byte NOP if the needed one
1491 isn't available. */
1492 last--;
1493 nops = patt[last - 1];
1494 memcpy (where + offset, nops, last);
1495 where[offset + last] = *patt[0];
1496 }
1497 else
1498 memcpy (where + offset, nops, last);
1499 }
1500 }
1501
1502 static INLINE int
1503 fits_in_imm7 (offsetT num)
1504 {
1505 return (num & 0x7f) == num;
1506 }
1507
1508 static INLINE int
1509 fits_in_imm31 (offsetT num)
1510 {
1511 return (num & 0x7fffffff) == num;
1512 }
1513
1514 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1515 single NOP instruction LIMIT. */
1516
1517 void
1518 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1519 {
1520 const unsigned char *const *patt = NULL;
1521 int max_single_nop_size;
1522 /* Maximum number of NOPs before switching to jump over NOPs. */
1523 int max_number_of_nops;
1524
1525 switch (fragP->fr_type)
1526 {
1527 case rs_fill_nop:
1528 case rs_align_code:
1529 break;
1530 case rs_machine_dependent:
1531 /* Allow NOP padding for jumps and calls. */
1532 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1533 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1534 break;
1535 /* Fall through. */
1536 default:
1537 return;
1538 }
1539
1540 /* We need to decide which NOP sequence to use for 32bit and
1541 64bit. When -mtune= is used:
1542
1543 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1544 PROCESSOR_GENERIC32, f32_patt will be used.
1545 2. For the rest, alt_patt will be used.
1546
1547 When -mtune= isn't used, alt_patt will be used if
1548 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1549 be used.
1550
1551 When -march= or .arch is used, we can't use anything beyond
1552 cpu_arch_isa_flags. */
1553
1554 if (flag_code == CODE_16BIT)
1555 {
1556 patt = f16_patt;
1557 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1558 /* Limit number of NOPs to 2 in 16-bit mode. */
1559 max_number_of_nops = 2;
1560 }
1561 else
1562 {
1563 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1564 {
1565 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1566 switch (cpu_arch_tune)
1567 {
1568 case PROCESSOR_UNKNOWN:
1569 /* We use cpu_arch_isa_flags to check if we SHOULD
1570 optimize with nops. */
1571 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1572 patt = alt_patt;
1573 else
1574 patt = f32_patt;
1575 break;
1576 case PROCESSOR_PENTIUM4:
1577 case PROCESSOR_NOCONA:
1578 case PROCESSOR_CORE:
1579 case PROCESSOR_CORE2:
1580 case PROCESSOR_COREI7:
1581 case PROCESSOR_L1OM:
1582 case PROCESSOR_K1OM:
1583 case PROCESSOR_GENERIC64:
1584 case PROCESSOR_K6:
1585 case PROCESSOR_ATHLON:
1586 case PROCESSOR_K8:
1587 case PROCESSOR_AMDFAM10:
1588 case PROCESSOR_BD:
1589 case PROCESSOR_ZNVER:
1590 case PROCESSOR_BT:
1591 patt = alt_patt;
1592 break;
1593 case PROCESSOR_I386:
1594 case PROCESSOR_I486:
1595 case PROCESSOR_PENTIUM:
1596 case PROCESSOR_PENTIUMPRO:
1597 case PROCESSOR_IAMCU:
1598 case PROCESSOR_GENERIC32:
1599 patt = f32_patt;
1600 break;
1601 }
1602 }
1603 else
1604 {
1605 switch (fragP->tc_frag_data.tune)
1606 {
1607 case PROCESSOR_UNKNOWN:
1608 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1609 PROCESSOR_UNKNOWN. */
1610 abort ();
1611 break;
1612
1613 case PROCESSOR_I386:
1614 case PROCESSOR_I486:
1615 case PROCESSOR_PENTIUM:
1616 case PROCESSOR_IAMCU:
1617 case PROCESSOR_K6:
1618 case PROCESSOR_ATHLON:
1619 case PROCESSOR_K8:
1620 case PROCESSOR_AMDFAM10:
1621 case PROCESSOR_BD:
1622 case PROCESSOR_ZNVER:
1623 case PROCESSOR_BT:
1624 case PROCESSOR_GENERIC32:
1625 /* We use cpu_arch_isa_flags to check if we CAN optimize
1626 with nops. */
1627 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1628 patt = alt_patt;
1629 else
1630 patt = f32_patt;
1631 break;
1632 case PROCESSOR_PENTIUMPRO:
1633 case PROCESSOR_PENTIUM4:
1634 case PROCESSOR_NOCONA:
1635 case PROCESSOR_CORE:
1636 case PROCESSOR_CORE2:
1637 case PROCESSOR_COREI7:
1638 case PROCESSOR_L1OM:
1639 case PROCESSOR_K1OM:
1640 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1641 patt = alt_patt;
1642 else
1643 patt = f32_patt;
1644 break;
1645 case PROCESSOR_GENERIC64:
1646 patt = alt_patt;
1647 break;
1648 }
1649 }
1650
1651 if (patt == f32_patt)
1652 {
1653 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1654 /* Limit number of NOPs to 2 for older processors. */
1655 max_number_of_nops = 2;
1656 }
1657 else
1658 {
1659 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1660 /* Limit number of NOPs to 7 for newer processors. */
1661 max_number_of_nops = 7;
1662 }
1663 }
1664
1665 if (limit == 0)
1666 limit = max_single_nop_size;
1667
1668 if (fragP->fr_type == rs_fill_nop)
1669 {
1670 /* Output NOPs for .nop directive. */
1671 if (limit > max_single_nop_size)
1672 {
1673 as_bad_where (fragP->fr_file, fragP->fr_line,
1674 _("invalid single nop size: %d "
1675 "(expect within [0, %d])"),
1676 limit, max_single_nop_size);
1677 return;
1678 }
1679 }
1680 else if (fragP->fr_type != rs_machine_dependent)
1681 fragP->fr_var = count;
1682
1683 if ((count / max_single_nop_size) > max_number_of_nops)
1684 {
1685 /* Generate jump over NOPs. */
1686 offsetT disp = count - 2;
1687 if (fits_in_imm7 (disp))
1688 {
1689 /* Use "jmp disp8" if possible. */
1690 count = disp;
1691 where[0] = jump_disp8[0];
1692 where[1] = count;
1693 where += 2;
1694 }
1695 else
1696 {
1697 unsigned int size_of_jump;
1698
1699 if (flag_code == CODE_16BIT)
1700 {
1701 where[0] = jump16_disp32[0];
1702 where[1] = jump16_disp32[1];
1703 size_of_jump = 2;
1704 }
1705 else
1706 {
1707 where[0] = jump32_disp32[0];
1708 size_of_jump = 1;
1709 }
1710
1711 count -= size_of_jump + 4;
1712 if (!fits_in_imm31 (count))
1713 {
1714 as_bad_where (fragP->fr_file, fragP->fr_line,
1715 _("jump over nop padding out of range"));
1716 return;
1717 }
1718
1719 md_number_to_chars (where + size_of_jump, count, 4);
1720 where += size_of_jump + 4;
1721 }
1722 }
1723
1724 /* Generate multiple NOPs. */
1725 i386_output_nops (where, patt, count, limit);
1726 }
1727
1728 static INLINE int
1729 operand_type_all_zero (const union i386_operand_type *x)
1730 {
1731 switch (ARRAY_SIZE(x->array))
1732 {
1733 case 3:
1734 if (x->array[2])
1735 return 0;
1736 /* Fall through. */
1737 case 2:
1738 if (x->array[1])
1739 return 0;
1740 /* Fall through. */
1741 case 1:
1742 return !x->array[0];
1743 default:
1744 abort ();
1745 }
1746 }
1747
1748 static INLINE void
1749 operand_type_set (union i386_operand_type *x, unsigned int v)
1750 {
1751 switch (ARRAY_SIZE(x->array))
1752 {
1753 case 3:
1754 x->array[2] = v;
1755 /* Fall through. */
1756 case 2:
1757 x->array[1] = v;
1758 /* Fall through. */
1759 case 1:
1760 x->array[0] = v;
1761 /* Fall through. */
1762 break;
1763 default:
1764 abort ();
1765 }
1766
1767 x->bitfield.class = ClassNone;
1768 x->bitfield.instance = InstanceNone;
1769 }
1770
1771 static INLINE int
1772 operand_type_equal (const union i386_operand_type *x,
1773 const union i386_operand_type *y)
1774 {
1775 switch (ARRAY_SIZE(x->array))
1776 {
1777 case 3:
1778 if (x->array[2] != y->array[2])
1779 return 0;
1780 /* Fall through. */
1781 case 2:
1782 if (x->array[1] != y->array[1])
1783 return 0;
1784 /* Fall through. */
1785 case 1:
1786 return x->array[0] == y->array[0];
1787 break;
1788 default:
1789 abort ();
1790 }
1791 }
1792
1793 static INLINE int
1794 cpu_flags_all_zero (const union i386_cpu_flags *x)
1795 {
1796 switch (ARRAY_SIZE(x->array))
1797 {
1798 case 4:
1799 if (x->array[3])
1800 return 0;
1801 /* Fall through. */
1802 case 3:
1803 if (x->array[2])
1804 return 0;
1805 /* Fall through. */
1806 case 2:
1807 if (x->array[1])
1808 return 0;
1809 /* Fall through. */
1810 case 1:
1811 return !x->array[0];
1812 default:
1813 abort ();
1814 }
1815 }
1816
1817 static INLINE int
1818 cpu_flags_equal (const union i386_cpu_flags *x,
1819 const union i386_cpu_flags *y)
1820 {
1821 switch (ARRAY_SIZE(x->array))
1822 {
1823 case 4:
1824 if (x->array[3] != y->array[3])
1825 return 0;
1826 /* Fall through. */
1827 case 3:
1828 if (x->array[2] != y->array[2])
1829 return 0;
1830 /* Fall through. */
1831 case 2:
1832 if (x->array[1] != y->array[1])
1833 return 0;
1834 /* Fall through. */
1835 case 1:
1836 return x->array[0] == y->array[0];
1837 break;
1838 default:
1839 abort ();
1840 }
1841 }
1842
1843 static INLINE int
1844 cpu_flags_check_cpu64 (i386_cpu_flags f)
1845 {
1846 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1847 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1848 }
1849
1850 static INLINE i386_cpu_flags
1851 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1852 {
1853 switch (ARRAY_SIZE (x.array))
1854 {
1855 case 4:
1856 x.array [3] &= y.array [3];
1857 /* Fall through. */
1858 case 3:
1859 x.array [2] &= y.array [2];
1860 /* Fall through. */
1861 case 2:
1862 x.array [1] &= y.array [1];
1863 /* Fall through. */
1864 case 1:
1865 x.array [0] &= y.array [0];
1866 break;
1867 default:
1868 abort ();
1869 }
1870 return x;
1871 }
1872
1873 static INLINE i386_cpu_flags
1874 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1875 {
1876 switch (ARRAY_SIZE (x.array))
1877 {
1878 case 4:
1879 x.array [3] |= y.array [3];
1880 /* Fall through. */
1881 case 3:
1882 x.array [2] |= y.array [2];
1883 /* Fall through. */
1884 case 2:
1885 x.array [1] |= y.array [1];
1886 /* Fall through. */
1887 case 1:
1888 x.array [0] |= y.array [0];
1889 break;
1890 default:
1891 abort ();
1892 }
1893 return x;
1894 }
1895
1896 static INLINE i386_cpu_flags
1897 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1898 {
1899 switch (ARRAY_SIZE (x.array))
1900 {
1901 case 4:
1902 x.array [3] &= ~y.array [3];
1903 /* Fall through. */
1904 case 3:
1905 x.array [2] &= ~y.array [2];
1906 /* Fall through. */
1907 case 2:
1908 x.array [1] &= ~y.array [1];
1909 /* Fall through. */
1910 case 1:
1911 x.array [0] &= ~y.array [0];
1912 break;
1913 default:
1914 abort ();
1915 }
1916 return x;
1917 }
1918
1919 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
1920
1921 #define CPU_FLAGS_ARCH_MATCH 0x1
1922 #define CPU_FLAGS_64BIT_MATCH 0x2
1923
1924 #define CPU_FLAGS_PERFECT_MATCH \
1925 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1926
1927 /* Return CPU flags match bits. */
1928
1929 static int
1930 cpu_flags_match (const insn_template *t)
1931 {
1932 i386_cpu_flags x = t->cpu_flags;
1933 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1934
1935 x.bitfield.cpu64 = 0;
1936 x.bitfield.cpuno64 = 0;
1937
1938 if (cpu_flags_all_zero (&x))
1939 {
1940 /* This instruction is available on all archs. */
1941 match |= CPU_FLAGS_ARCH_MATCH;
1942 }
1943 else
1944 {
1945 /* This instruction is available only on some archs. */
1946 i386_cpu_flags cpu = cpu_arch_flags;
1947
1948 /* AVX512VL is no standalone feature - match it and then strip it. */
1949 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1950 return match;
1951 x.bitfield.cpuavx512vl = 0;
1952
1953 cpu = cpu_flags_and (x, cpu);
1954 if (!cpu_flags_all_zero (&cpu))
1955 {
1956 if (x.bitfield.cpuavx)
1957 {
1958 /* We need to check a few extra flags with AVX. */
1959 if (cpu.bitfield.cpuavx
1960 && (!t->opcode_modifier.sse2avx
1961 || (sse2avx && !i.prefix[DATA_PREFIX]))
1962 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1963 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1964 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1965 match |= CPU_FLAGS_ARCH_MATCH;
1966 }
1967 else if (x.bitfield.cpuavx512f)
1968 {
1969 /* We need to check a few extra flags with AVX512F. */
1970 if (cpu.bitfield.cpuavx512f
1971 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1972 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1973 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1974 match |= CPU_FLAGS_ARCH_MATCH;
1975 }
1976 else
1977 match |= CPU_FLAGS_ARCH_MATCH;
1978 }
1979 }
1980 return match;
1981 }
1982
1983 static INLINE i386_operand_type
1984 operand_type_and (i386_operand_type x, i386_operand_type y)
1985 {
1986 if (x.bitfield.class != y.bitfield.class)
1987 x.bitfield.class = ClassNone;
1988 if (x.bitfield.instance != y.bitfield.instance)
1989 x.bitfield.instance = InstanceNone;
1990
1991 switch (ARRAY_SIZE (x.array))
1992 {
1993 case 3:
1994 x.array [2] &= y.array [2];
1995 /* Fall through. */
1996 case 2:
1997 x.array [1] &= y.array [1];
1998 /* Fall through. */
1999 case 1:
2000 x.array [0] &= y.array [0];
2001 break;
2002 default:
2003 abort ();
2004 }
2005 return x;
2006 }
2007
2008 static INLINE i386_operand_type
2009 operand_type_and_not (i386_operand_type x, i386_operand_type y)
2010 {
2011 gas_assert (y.bitfield.class == ClassNone);
2012 gas_assert (y.bitfield.instance == InstanceNone);
2013
2014 switch (ARRAY_SIZE (x.array))
2015 {
2016 case 3:
2017 x.array [2] &= ~y.array [2];
2018 /* Fall through. */
2019 case 2:
2020 x.array [1] &= ~y.array [1];
2021 /* Fall through. */
2022 case 1:
2023 x.array [0] &= ~y.array [0];
2024 break;
2025 default:
2026 abort ();
2027 }
2028 return x;
2029 }
2030
2031 static INLINE i386_operand_type
2032 operand_type_or (i386_operand_type x, i386_operand_type y)
2033 {
2034 gas_assert (x.bitfield.class == ClassNone ||
2035 y.bitfield.class == ClassNone ||
2036 x.bitfield.class == y.bitfield.class);
2037 gas_assert (x.bitfield.instance == InstanceNone ||
2038 y.bitfield.instance == InstanceNone ||
2039 x.bitfield.instance == y.bitfield.instance);
2040
2041 switch (ARRAY_SIZE (x.array))
2042 {
2043 case 3:
2044 x.array [2] |= y.array [2];
2045 /* Fall through. */
2046 case 2:
2047 x.array [1] |= y.array [1];
2048 /* Fall through. */
2049 case 1:
2050 x.array [0] |= y.array [0];
2051 break;
2052 default:
2053 abort ();
2054 }
2055 return x;
2056 }
2057
2058 static INLINE i386_operand_type
2059 operand_type_xor (i386_operand_type x, i386_operand_type y)
2060 {
2061 gas_assert (y.bitfield.class == ClassNone);
2062 gas_assert (y.bitfield.instance == InstanceNone);
2063
2064 switch (ARRAY_SIZE (x.array))
2065 {
2066 case 3:
2067 x.array [2] ^= y.array [2];
2068 /* Fall through. */
2069 case 2:
2070 x.array [1] ^= y.array [1];
2071 /* Fall through. */
2072 case 1:
2073 x.array [0] ^= y.array [0];
2074 break;
2075 default:
2076 abort ();
2077 }
2078 return x;
2079 }
2080
2081 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
2082 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
2083 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
2084 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
2085 static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
2086 static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
2087 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
2088 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
2089 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
2090 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
2091 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
2092 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
2093 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
2094 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
2095 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
2096 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
2097 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
2098
2099 enum operand_type
2100 {
2101 reg,
2102 imm,
2103 disp,
2104 anymem
2105 };
2106
2107 static INLINE int
2108 operand_type_check (i386_operand_type t, enum operand_type c)
2109 {
2110 switch (c)
2111 {
2112 case reg:
2113 return t.bitfield.class == Reg;
2114
2115 case imm:
2116 return (t.bitfield.imm8
2117 || t.bitfield.imm8s
2118 || t.bitfield.imm16
2119 || t.bitfield.imm32
2120 || t.bitfield.imm32s
2121 || t.bitfield.imm64);
2122
2123 case disp:
2124 return (t.bitfield.disp8
2125 || t.bitfield.disp16
2126 || t.bitfield.disp32
2127 || t.bitfield.disp32s
2128 || t.bitfield.disp64);
2129
2130 case anymem:
2131 return (t.bitfield.disp8
2132 || t.bitfield.disp16
2133 || t.bitfield.disp32
2134 || t.bitfield.disp32s
2135 || t.bitfield.disp64
2136 || t.bitfield.baseindex);
2137
2138 default:
2139 abort ();
2140 }
2141
2142 return 0;
2143 }
2144
2145 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2146 between operand GIVEN and opeand WANTED for instruction template T. */
2147
2148 static INLINE int
2149 match_operand_size (const insn_template *t, unsigned int wanted,
2150 unsigned int given)
2151 {
2152 return !((i.types[given].bitfield.byte
2153 && !t->operand_types[wanted].bitfield.byte)
2154 || (i.types[given].bitfield.word
2155 && !t->operand_types[wanted].bitfield.word)
2156 || (i.types[given].bitfield.dword
2157 && !t->operand_types[wanted].bitfield.dword)
2158 || (i.types[given].bitfield.qword
2159 && !t->operand_types[wanted].bitfield.qword)
2160 || (i.types[given].bitfield.tbyte
2161 && !t->operand_types[wanted].bitfield.tbyte));
2162 }
2163
2164 /* Return 1 if there is no conflict in SIMD register between operand
2165 GIVEN and opeand WANTED for instruction template T. */
2166
2167 static INLINE int
2168 match_simd_size (const insn_template *t, unsigned int wanted,
2169 unsigned int given)
2170 {
2171 return !((i.types[given].bitfield.xmmword
2172 && !t->operand_types[wanted].bitfield.xmmword)
2173 || (i.types[given].bitfield.ymmword
2174 && !t->operand_types[wanted].bitfield.ymmword)
2175 || (i.types[given].bitfield.zmmword
2176 && !t->operand_types[wanted].bitfield.zmmword)
2177 || (i.types[given].bitfield.tmmword
2178 && !t->operand_types[wanted].bitfield.tmmword));
2179 }
2180
2181 /* Return 1 if there is no conflict in any size between operand GIVEN
2182 and opeand WANTED for instruction template T. */
2183
2184 static INLINE int
2185 match_mem_size (const insn_template *t, unsigned int wanted,
2186 unsigned int given)
2187 {
2188 return (match_operand_size (t, wanted, given)
2189 && !((i.types[given].bitfield.unspecified
2190 && !i.broadcast
2191 && !t->operand_types[wanted].bitfield.unspecified)
2192 || (i.types[given].bitfield.fword
2193 && !t->operand_types[wanted].bitfield.fword)
2194 /* For scalar opcode templates to allow register and memory
2195 operands at the same time, some special casing is needed
2196 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2197 down-conversion vpmov*. */
2198 || ((t->operand_types[wanted].bitfield.class == RegSIMD
2199 && t->operand_types[wanted].bitfield.byte
2200 + t->operand_types[wanted].bitfield.word
2201 + t->operand_types[wanted].bitfield.dword
2202 + t->operand_types[wanted].bitfield.qword
2203 > !!t->opcode_modifier.broadcast)
2204 ? (i.types[given].bitfield.xmmword
2205 || i.types[given].bitfield.ymmword
2206 || i.types[given].bitfield.zmmword)
2207 : !match_simd_size(t, wanted, given))));
2208 }
2209
2210 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2211 operands for instruction template T, and it has MATCH_REVERSE set if there
2212 is no size conflict on any operands for the template with operands reversed
2213 (and the template allows for reversing in the first place). */
2214
2215 #define MATCH_STRAIGHT 1
2216 #define MATCH_REVERSE 2
2217
2218 static INLINE unsigned int
2219 operand_size_match (const insn_template *t)
2220 {
2221 unsigned int j, match = MATCH_STRAIGHT;
2222
2223 /* Don't check non-absolute jump instructions. */
2224 if (t->opcode_modifier.jump
2225 && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2226 return match;
2227
2228 /* Check memory and accumulator operand size. */
2229 for (j = 0; j < i.operands; j++)
2230 {
2231 if (i.types[j].bitfield.class != Reg
2232 && i.types[j].bitfield.class != RegSIMD
2233 && t->opcode_modifier.anysize)
2234 continue;
2235
2236 if (t->operand_types[j].bitfield.class == Reg
2237 && !match_operand_size (t, j, j))
2238 {
2239 match = 0;
2240 break;
2241 }
2242
2243 if (t->operand_types[j].bitfield.class == RegSIMD
2244 && !match_simd_size (t, j, j))
2245 {
2246 match = 0;
2247 break;
2248 }
2249
2250 if (t->operand_types[j].bitfield.instance == Accum
2251 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2252 {
2253 match = 0;
2254 break;
2255 }
2256
2257 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2258 {
2259 match = 0;
2260 break;
2261 }
2262 }
2263
2264 if (!t->opcode_modifier.d)
2265 {
2266 mismatch:
2267 if (!match)
2268 i.error = operand_size_mismatch;
2269 return match;
2270 }
2271
2272 /* Check reverse. */
2273 gas_assert (i.operands >= 2 && i.operands <= 3);
2274
2275 for (j = 0; j < i.operands; j++)
2276 {
2277 unsigned int given = i.operands - j - 1;
2278
2279 if (t->operand_types[j].bitfield.class == Reg
2280 && !match_operand_size (t, j, given))
2281 goto mismatch;
2282
2283 if (t->operand_types[j].bitfield.class == RegSIMD
2284 && !match_simd_size (t, j, given))
2285 goto mismatch;
2286
2287 if (t->operand_types[j].bitfield.instance == Accum
2288 && (!match_operand_size (t, j, given)
2289 || !match_simd_size (t, j, given)))
2290 goto mismatch;
2291
2292 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2293 goto mismatch;
2294 }
2295
2296 return match | MATCH_REVERSE;
2297 }
2298
2299 static INLINE int
2300 operand_type_match (i386_operand_type overlap,
2301 i386_operand_type given)
2302 {
2303 i386_operand_type temp = overlap;
2304
2305 temp.bitfield.unspecified = 0;
2306 temp.bitfield.byte = 0;
2307 temp.bitfield.word = 0;
2308 temp.bitfield.dword = 0;
2309 temp.bitfield.fword = 0;
2310 temp.bitfield.qword = 0;
2311 temp.bitfield.tbyte = 0;
2312 temp.bitfield.xmmword = 0;
2313 temp.bitfield.ymmword = 0;
2314 temp.bitfield.zmmword = 0;
2315 temp.bitfield.tmmword = 0;
2316 if (operand_type_all_zero (&temp))
2317 goto mismatch;
2318
2319 if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2320 return 1;
2321
2322 mismatch:
2323 i.error = operand_type_mismatch;
2324 return 0;
2325 }
2326
2327 /* If given types g0 and g1 are registers they must be of the same type
2328 unless the expected operand type register overlap is null.
2329 Some Intel syntax memory operand size checking also happens here. */
2330
2331 static INLINE int
2332 operand_type_register_match (i386_operand_type g0,
2333 i386_operand_type t0,
2334 i386_operand_type g1,
2335 i386_operand_type t1)
2336 {
2337 if (g0.bitfield.class != Reg
2338 && g0.bitfield.class != RegSIMD
2339 && (!operand_type_check (g0, anymem)
2340 || g0.bitfield.unspecified
2341 || (t0.bitfield.class != Reg
2342 && t0.bitfield.class != RegSIMD)))
2343 return 1;
2344
2345 if (g1.bitfield.class != Reg
2346 && g1.bitfield.class != RegSIMD
2347 && (!operand_type_check (g1, anymem)
2348 || g1.bitfield.unspecified
2349 || (t1.bitfield.class != Reg
2350 && t1.bitfield.class != RegSIMD)))
2351 return 1;
2352
2353 if (g0.bitfield.byte == g1.bitfield.byte
2354 && g0.bitfield.word == g1.bitfield.word
2355 && g0.bitfield.dword == g1.bitfield.dword
2356 && g0.bitfield.qword == g1.bitfield.qword
2357 && g0.bitfield.xmmword == g1.bitfield.xmmword
2358 && g0.bitfield.ymmword == g1.bitfield.ymmword
2359 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2360 return 1;
2361
2362 if (!(t0.bitfield.byte & t1.bitfield.byte)
2363 && !(t0.bitfield.word & t1.bitfield.word)
2364 && !(t0.bitfield.dword & t1.bitfield.dword)
2365 && !(t0.bitfield.qword & t1.bitfield.qword)
2366 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2367 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2368 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2369 return 1;
2370
2371 i.error = register_type_mismatch;
2372
2373 return 0;
2374 }
2375
2376 static INLINE unsigned int
2377 register_number (const reg_entry *r)
2378 {
2379 unsigned int nr = r->reg_num;
2380
2381 if (r->reg_flags & RegRex)
2382 nr += 8;
2383
2384 if (r->reg_flags & RegVRex)
2385 nr += 16;
2386
2387 return nr;
2388 }
2389
2390 static INLINE unsigned int
2391 mode_from_disp_size (i386_operand_type t)
2392 {
2393 if (t.bitfield.disp8)
2394 return 1;
2395 else if (t.bitfield.disp16
2396 || t.bitfield.disp32
2397 || t.bitfield.disp32s)
2398 return 2;
2399 else
2400 return 0;
2401 }
2402
2403 static INLINE int
2404 fits_in_signed_byte (addressT num)
2405 {
2406 return num + 0x80 <= 0xff;
2407 }
2408
2409 static INLINE int
2410 fits_in_unsigned_byte (addressT num)
2411 {
2412 return num <= 0xff;
2413 }
2414
2415 static INLINE int
2416 fits_in_unsigned_word (addressT num)
2417 {
2418 return num <= 0xffff;
2419 }
2420
2421 static INLINE int
2422 fits_in_signed_word (addressT num)
2423 {
2424 return num + 0x8000 <= 0xffff;
2425 }
2426
2427 static INLINE int
2428 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2429 {
2430 #ifndef BFD64
2431 return 1;
2432 #else
2433 return num + 0x80000000 <= 0xffffffff;
2434 #endif
2435 } /* fits_in_signed_long() */
2436
2437 static INLINE int
2438 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2439 {
2440 #ifndef BFD64
2441 return 1;
2442 #else
2443 return num <= 0xffffffff;
2444 #endif
2445 } /* fits_in_unsigned_long() */
2446
2447 static INLINE int
2448 fits_in_disp8 (offsetT num)
2449 {
2450 int shift = i.memshift;
2451 unsigned int mask;
2452
2453 if (shift == -1)
2454 abort ();
2455
2456 mask = (1 << shift) - 1;
2457
2458 /* Return 0 if NUM isn't properly aligned. */
2459 if ((num & mask))
2460 return 0;
2461
2462 /* Check if NUM will fit in 8bit after shift. */
2463 return fits_in_signed_byte (num >> shift);
2464 }
2465
2466 static INLINE int
2467 fits_in_imm4 (offsetT num)
2468 {
2469 return (num & 0xf) == num;
2470 }
2471
2472 static i386_operand_type
2473 smallest_imm_type (offsetT num)
2474 {
2475 i386_operand_type t;
2476
2477 operand_type_set (&t, 0);
2478 t.bitfield.imm64 = 1;
2479
2480 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2481 {
2482 /* This code is disabled on the 486 because all the Imm1 forms
2483 in the opcode table are slower on the i486. They're the
2484 versions with the implicitly specified single-position
2485 displacement, which has another syntax if you really want to
2486 use that form. */
2487 t.bitfield.imm1 = 1;
2488 t.bitfield.imm8 = 1;
2489 t.bitfield.imm8s = 1;
2490 t.bitfield.imm16 = 1;
2491 t.bitfield.imm32 = 1;
2492 t.bitfield.imm32s = 1;
2493 }
2494 else if (fits_in_signed_byte (num))
2495 {
2496 t.bitfield.imm8 = 1;
2497 t.bitfield.imm8s = 1;
2498 t.bitfield.imm16 = 1;
2499 t.bitfield.imm32 = 1;
2500 t.bitfield.imm32s = 1;
2501 }
2502 else if (fits_in_unsigned_byte (num))
2503 {
2504 t.bitfield.imm8 = 1;
2505 t.bitfield.imm16 = 1;
2506 t.bitfield.imm32 = 1;
2507 t.bitfield.imm32s = 1;
2508 }
2509 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2510 {
2511 t.bitfield.imm16 = 1;
2512 t.bitfield.imm32 = 1;
2513 t.bitfield.imm32s = 1;
2514 }
2515 else if (fits_in_signed_long (num))
2516 {
2517 t.bitfield.imm32 = 1;
2518 t.bitfield.imm32s = 1;
2519 }
2520 else if (fits_in_unsigned_long (num))
2521 t.bitfield.imm32 = 1;
2522
2523 return t;
2524 }
2525
2526 static offsetT
2527 offset_in_range (offsetT val, int size)
2528 {
2529 addressT mask;
2530
2531 switch (size)
2532 {
2533 case 1: mask = ((addressT) 1 << 8) - 1; break;
2534 case 2: mask = ((addressT) 1 << 16) - 1; break;
2535 case 4: mask = ((addressT) 2 << 31) - 1; break;
2536 #ifdef BFD64
2537 case 8: mask = ((addressT) 2 << 63) - 1; break;
2538 #endif
2539 default: abort ();
2540 }
2541
2542 #ifdef BFD64
2543 /* If BFD64, sign extend val for 32bit address mode. */
2544 if (flag_code != CODE_64BIT
2545 || i.prefix[ADDR_PREFIX])
2546 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2547 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2548 #endif
2549
2550 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2551 {
2552 char buf1[40], buf2[40];
2553
2554 sprint_value (buf1, val);
2555 sprint_value (buf2, val & mask);
2556 as_warn (_("%s shortened to %s"), buf1, buf2);
2557 }
2558 return val & mask;
2559 }
2560
2561 enum PREFIX_GROUP
2562 {
2563 PREFIX_EXIST = 0,
2564 PREFIX_LOCK,
2565 PREFIX_REP,
2566 PREFIX_DS,
2567 PREFIX_OTHER
2568 };
2569
2570 /* Returns
2571 a. PREFIX_EXIST if attempting to add a prefix where one from the
2572 same class already exists.
2573 b. PREFIX_LOCK if lock prefix is added.
2574 c. PREFIX_REP if rep/repne prefix is added.
2575 d. PREFIX_DS if ds prefix is added.
2576 e. PREFIX_OTHER if other prefix is added.
2577 */
2578
2579 static enum PREFIX_GROUP
2580 add_prefix (unsigned int prefix)
2581 {
2582 enum PREFIX_GROUP ret = PREFIX_OTHER;
2583 unsigned int q;
2584
2585 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2586 && flag_code == CODE_64BIT)
2587 {
2588 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2589 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2590 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2591 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2592 ret = PREFIX_EXIST;
2593 q = REX_PREFIX;
2594 }
2595 else
2596 {
2597 switch (prefix)
2598 {
2599 default:
2600 abort ();
2601
2602 case DS_PREFIX_OPCODE:
2603 ret = PREFIX_DS;
2604 /* Fall through. */
2605 case CS_PREFIX_OPCODE:
2606 case ES_PREFIX_OPCODE:
2607 case FS_PREFIX_OPCODE:
2608 case GS_PREFIX_OPCODE:
2609 case SS_PREFIX_OPCODE:
2610 q = SEG_PREFIX;
2611 break;
2612
2613 case REPNE_PREFIX_OPCODE:
2614 case REPE_PREFIX_OPCODE:
2615 q = REP_PREFIX;
2616 ret = PREFIX_REP;
2617 break;
2618
2619 case LOCK_PREFIX_OPCODE:
2620 q = LOCK_PREFIX;
2621 ret = PREFIX_LOCK;
2622 break;
2623
2624 case FWAIT_OPCODE:
2625 q = WAIT_PREFIX;
2626 break;
2627
2628 case ADDR_PREFIX_OPCODE:
2629 q = ADDR_PREFIX;
2630 break;
2631
2632 case DATA_PREFIX_OPCODE:
2633 q = DATA_PREFIX;
2634 break;
2635 }
2636 if (i.prefix[q] != 0)
2637 ret = PREFIX_EXIST;
2638 }
2639
2640 if (ret)
2641 {
2642 if (!i.prefix[q])
2643 ++i.prefixes;
2644 i.prefix[q] |= prefix;
2645 }
2646 else
2647 as_bad (_("same type of prefix used twice"));
2648
2649 return ret;
2650 }
2651
2652 static void
2653 update_code_flag (int value, int check)
2654 {
2655 PRINTF_LIKE ((*as_error));
2656
2657 flag_code = (enum flag_code) value;
2658 if (flag_code == CODE_64BIT)
2659 {
2660 cpu_arch_flags.bitfield.cpu64 = 1;
2661 cpu_arch_flags.bitfield.cpuno64 = 0;
2662 }
2663 else
2664 {
2665 cpu_arch_flags.bitfield.cpu64 = 0;
2666 cpu_arch_flags.bitfield.cpuno64 = 1;
2667 }
2668 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2669 {
2670 if (check)
2671 as_error = as_fatal;
2672 else
2673 as_error = as_bad;
2674 (*as_error) (_("64bit mode not supported on `%s'."),
2675 cpu_arch_name ? cpu_arch_name : default_arch);
2676 }
2677 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2678 {
2679 if (check)
2680 as_error = as_fatal;
2681 else
2682 as_error = as_bad;
2683 (*as_error) (_("32bit mode not supported on `%s'."),
2684 cpu_arch_name ? cpu_arch_name : default_arch);
2685 }
2686 stackop_size = '\0';
2687 }
2688
2689 static void
2690 set_code_flag (int value)
2691 {
2692 update_code_flag (value, 0);
2693 }
2694
2695 static void
2696 set_16bit_gcc_code_flag (int new_code_flag)
2697 {
2698 flag_code = (enum flag_code) new_code_flag;
2699 if (flag_code != CODE_16BIT)
2700 abort ();
2701 cpu_arch_flags.bitfield.cpu64 = 0;
2702 cpu_arch_flags.bitfield.cpuno64 = 1;
2703 stackop_size = LONG_MNEM_SUFFIX;
2704 }
2705
2706 static void
2707 set_intel_syntax (int syntax_flag)
2708 {
2709 /* Find out if register prefixing is specified. */
2710 int ask_naked_reg = 0;
2711
2712 SKIP_WHITESPACE ();
2713 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2714 {
2715 char *string;
2716 int e = get_symbol_name (&string);
2717
2718 if (strcmp (string, "prefix") == 0)
2719 ask_naked_reg = 1;
2720 else if (strcmp (string, "noprefix") == 0)
2721 ask_naked_reg = -1;
2722 else
2723 as_bad (_("bad argument to syntax directive."));
2724 (void) restore_line_pointer (e);
2725 }
2726 demand_empty_rest_of_line ();
2727
2728 intel_syntax = syntax_flag;
2729
2730 if (ask_naked_reg == 0)
2731 allow_naked_reg = (intel_syntax
2732 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2733 else
2734 allow_naked_reg = (ask_naked_reg < 0);
2735
2736 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2737
2738 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2739 identifier_chars['$'] = intel_syntax ? '$' : 0;
2740 register_prefix = allow_naked_reg ? "" : "%";
2741 }
2742
2743 static void
2744 set_intel_mnemonic (int mnemonic_flag)
2745 {
2746 intel_mnemonic = mnemonic_flag;
2747 }
2748
2749 static void
2750 set_allow_index_reg (int flag)
2751 {
2752 allow_index_reg = flag;
2753 }
2754
2755 static void
2756 set_check (int what)
2757 {
2758 enum check_kind *kind;
2759 const char *str;
2760
2761 if (what)
2762 {
2763 kind = &operand_check;
2764 str = "operand";
2765 }
2766 else
2767 {
2768 kind = &sse_check;
2769 str = "sse";
2770 }
2771
2772 SKIP_WHITESPACE ();
2773
2774 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2775 {
2776 char *string;
2777 int e = get_symbol_name (&string);
2778
2779 if (strcmp (string, "none") == 0)
2780 *kind = check_none;
2781 else if (strcmp (string, "warning") == 0)
2782 *kind = check_warning;
2783 else if (strcmp (string, "error") == 0)
2784 *kind = check_error;
2785 else
2786 as_bad (_("bad argument to %s_check directive."), str);
2787 (void) restore_line_pointer (e);
2788 }
2789 else
2790 as_bad (_("missing argument for %s_check directive"), str);
2791
2792 demand_empty_rest_of_line ();
2793 }
2794
2795 static void
2796 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2797 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2798 {
2799 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2800 static const char *arch;
2801
2802 /* Intel LIOM is only supported on ELF. */
2803 if (!IS_ELF)
2804 return;
2805
2806 if (!arch)
2807 {
2808 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2809 use default_arch. */
2810 arch = cpu_arch_name;
2811 if (!arch)
2812 arch = default_arch;
2813 }
2814
2815 /* If we are targeting Intel MCU, we must enable it. */
2816 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2817 || new_flag.bitfield.cpuiamcu)
2818 return;
2819
2820 /* If we are targeting Intel L1OM, we must enable it. */
2821 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2822 || new_flag.bitfield.cpul1om)
2823 return;
2824
2825 /* If we are targeting Intel K1OM, we must enable it. */
2826 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2827 || new_flag.bitfield.cpuk1om)
2828 return;
2829
2830 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2831 #endif
2832 }
2833
2834 static void
2835 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2836 {
2837 SKIP_WHITESPACE ();
2838
2839 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2840 {
2841 char *string;
2842 int e = get_symbol_name (&string);
2843 unsigned int j;
2844 i386_cpu_flags flags;
2845
2846 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2847 {
2848 if (strcmp (string, cpu_arch[j].name) == 0)
2849 {
2850 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2851
2852 if (*string != '.')
2853 {
2854 cpu_arch_name = cpu_arch[j].name;
2855 cpu_sub_arch_name = NULL;
2856 cpu_arch_flags = cpu_arch[j].flags;
2857 if (flag_code == CODE_64BIT)
2858 {
2859 cpu_arch_flags.bitfield.cpu64 = 1;
2860 cpu_arch_flags.bitfield.cpuno64 = 0;
2861 }
2862 else
2863 {
2864 cpu_arch_flags.bitfield.cpu64 = 0;
2865 cpu_arch_flags.bitfield.cpuno64 = 1;
2866 }
2867 cpu_arch_isa = cpu_arch[j].type;
2868 cpu_arch_isa_flags = cpu_arch[j].flags;
2869 if (!cpu_arch_tune_set)
2870 {
2871 cpu_arch_tune = cpu_arch_isa;
2872 cpu_arch_tune_flags = cpu_arch_isa_flags;
2873 }
2874 break;
2875 }
2876
2877 flags = cpu_flags_or (cpu_arch_flags,
2878 cpu_arch[j].flags);
2879
2880 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2881 {
2882 if (cpu_sub_arch_name)
2883 {
2884 char *name = cpu_sub_arch_name;
2885 cpu_sub_arch_name = concat (name,
2886 cpu_arch[j].name,
2887 (const char *) NULL);
2888 free (name);
2889 }
2890 else
2891 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2892 cpu_arch_flags = flags;
2893 cpu_arch_isa_flags = flags;
2894 }
2895 else
2896 cpu_arch_isa_flags
2897 = cpu_flags_or (cpu_arch_isa_flags,
2898 cpu_arch[j].flags);
2899 (void) restore_line_pointer (e);
2900 demand_empty_rest_of_line ();
2901 return;
2902 }
2903 }
2904
2905 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2906 {
2907 /* Disable an ISA extension. */
2908 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2909 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2910 {
2911 flags = cpu_flags_and_not (cpu_arch_flags,
2912 cpu_noarch[j].flags);
2913 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2914 {
2915 if (cpu_sub_arch_name)
2916 {
2917 char *name = cpu_sub_arch_name;
2918 cpu_sub_arch_name = concat (name, string,
2919 (const char *) NULL);
2920 free (name);
2921 }
2922 else
2923 cpu_sub_arch_name = xstrdup (string);
2924 cpu_arch_flags = flags;
2925 cpu_arch_isa_flags = flags;
2926 }
2927 (void) restore_line_pointer (e);
2928 demand_empty_rest_of_line ();
2929 return;
2930 }
2931
2932 j = ARRAY_SIZE (cpu_arch);
2933 }
2934
2935 if (j >= ARRAY_SIZE (cpu_arch))
2936 as_bad (_("no such architecture: `%s'"), string);
2937
2938 *input_line_pointer = e;
2939 }
2940 else
2941 as_bad (_("missing cpu architecture"));
2942
2943 no_cond_jump_promotion = 0;
2944 if (*input_line_pointer == ','
2945 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2946 {
2947 char *string;
2948 char e;
2949
2950 ++input_line_pointer;
2951 e = get_symbol_name (&string);
2952
2953 if (strcmp (string, "nojumps") == 0)
2954 no_cond_jump_promotion = 1;
2955 else if (strcmp (string, "jumps") == 0)
2956 ;
2957 else
2958 as_bad (_("no such architecture modifier: `%s'"), string);
2959
2960 (void) restore_line_pointer (e);
2961 }
2962
2963 demand_empty_rest_of_line ();
2964 }
2965
2966 enum bfd_architecture
2967 i386_arch (void)
2968 {
2969 if (cpu_arch_isa == PROCESSOR_L1OM)
2970 {
2971 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2972 || flag_code != CODE_64BIT)
2973 as_fatal (_("Intel L1OM is 64bit ELF only"));
2974 return bfd_arch_l1om;
2975 }
2976 else if (cpu_arch_isa == PROCESSOR_K1OM)
2977 {
2978 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2979 || flag_code != CODE_64BIT)
2980 as_fatal (_("Intel K1OM is 64bit ELF only"));
2981 return bfd_arch_k1om;
2982 }
2983 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2984 {
2985 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2986 || flag_code == CODE_64BIT)
2987 as_fatal (_("Intel MCU is 32bit ELF only"));
2988 return bfd_arch_iamcu;
2989 }
2990 else
2991 return bfd_arch_i386;
2992 }
2993
2994 unsigned long
2995 i386_mach (void)
2996 {
2997 if (!strncmp (default_arch, "x86_64", 6))
2998 {
2999 if (cpu_arch_isa == PROCESSOR_L1OM)
3000 {
3001 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
3002 || default_arch[6] != '\0')
3003 as_fatal (_("Intel L1OM is 64bit ELF only"));
3004 return bfd_mach_l1om;
3005 }
3006 else if (cpu_arch_isa == PROCESSOR_K1OM)
3007 {
3008 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
3009 || default_arch[6] != '\0')
3010 as_fatal (_("Intel K1OM is 64bit ELF only"));
3011 return bfd_mach_k1om;
3012 }
3013 else if (default_arch[6] == '\0')
3014 return bfd_mach_x86_64;
3015 else
3016 return bfd_mach_x64_32;
3017 }
3018 else if (!strcmp (default_arch, "i386")
3019 || !strcmp (default_arch, "iamcu"))
3020 {
3021 if (cpu_arch_isa == PROCESSOR_IAMCU)
3022 {
3023 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
3024 as_fatal (_("Intel MCU is 32bit ELF only"));
3025 return bfd_mach_i386_iamcu;
3026 }
3027 else
3028 return bfd_mach_i386_i386;
3029 }
3030 else
3031 as_fatal (_("unknown architecture"));
3032 }
3033 \f
3034 void
3035 md_begin (void)
3036 {
3037 const char *hash_err;
3038
3039 /* Support pseudo prefixes like {disp32}. */
3040 lex_type ['{'] = LEX_BEGIN_NAME;
3041
3042 /* Initialize op_hash hash table. */
3043 op_hash = hash_new ();
3044
3045 {
3046 const insn_template *optab;
3047 templates *core_optab;
3048
3049 /* Setup for loop. */
3050 optab = i386_optab;
3051 core_optab = XNEW (templates);
3052 core_optab->start = optab;
3053
3054 while (1)
3055 {
3056 ++optab;
3057 if (optab->name == NULL
3058 || strcmp (optab->name, (optab - 1)->name) != 0)
3059 {
3060 /* different name --> ship out current template list;
3061 add to hash table; & begin anew. */
3062 core_optab->end = optab;
3063 hash_err = hash_insert (op_hash,
3064 (optab - 1)->name,
3065 (void *) core_optab);
3066 if (hash_err)
3067 {
3068 as_fatal (_("can't hash %s: %s"),
3069 (optab - 1)->name,
3070 hash_err);
3071 }
3072 if (optab->name == NULL)
3073 break;
3074 core_optab = XNEW (templates);
3075 core_optab->start = optab;
3076 }
3077 }
3078 }
3079
3080 /* Initialize reg_hash hash table. */
3081 reg_hash = hash_new ();
3082 {
3083 const reg_entry *regtab;
3084 unsigned int regtab_size = i386_regtab_size;
3085
3086 for (regtab = i386_regtab; regtab_size--; regtab++)
3087 {
3088 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
3089 if (hash_err)
3090 as_fatal (_("can't hash %s: %s"),
3091 regtab->reg_name,
3092 hash_err);
3093 }
3094 }
3095
3096 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3097 {
3098 int c;
3099 char *p;
3100
3101 for (c = 0; c < 256; c++)
3102 {
3103 if (ISDIGIT (c))
3104 {
3105 digit_chars[c] = c;
3106 mnemonic_chars[c] = c;
3107 register_chars[c] = c;
3108 operand_chars[c] = c;
3109 }
3110 else if (ISLOWER (c))
3111 {
3112 mnemonic_chars[c] = c;
3113 register_chars[c] = c;
3114 operand_chars[c] = c;
3115 }
3116 else if (ISUPPER (c))
3117 {
3118 mnemonic_chars[c] = TOLOWER (c);
3119 register_chars[c] = mnemonic_chars[c];
3120 operand_chars[c] = c;
3121 }
3122 else if (c == '{' || c == '}')
3123 {
3124 mnemonic_chars[c] = c;
3125 operand_chars[c] = c;
3126 }
3127
3128 if (ISALPHA (c) || ISDIGIT (c))
3129 identifier_chars[c] = c;
3130 else if (c >= 128)
3131 {
3132 identifier_chars[c] = c;
3133 operand_chars[c] = c;
3134 }
3135 }
3136
3137 #ifdef LEX_AT
3138 identifier_chars['@'] = '@';
3139 #endif
3140 #ifdef LEX_QM
3141 identifier_chars['?'] = '?';
3142 operand_chars['?'] = '?';
3143 #endif
3144 digit_chars['-'] = '-';
3145 mnemonic_chars['_'] = '_';
3146 mnemonic_chars['-'] = '-';
3147 mnemonic_chars['.'] = '.';
3148 identifier_chars['_'] = '_';
3149 identifier_chars['.'] = '.';
3150
3151 for (p = operand_special_chars; *p != '\0'; p++)
3152 operand_chars[(unsigned char) *p] = *p;
3153 }
3154
3155 if (flag_code == CODE_64BIT)
3156 {
3157 #if defined (OBJ_COFF) && defined (TE_PE)
3158 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
3159 ? 32 : 16);
3160 #else
3161 x86_dwarf2_return_column = 16;
3162 #endif
3163 x86_cie_data_alignment = -8;
3164 }
3165 else
3166 {
3167 x86_dwarf2_return_column = 8;
3168 x86_cie_data_alignment = -4;
3169 }
3170
3171 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3172 can be turned into BRANCH_PREFIX frag. */
3173 if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3174 abort ();
3175 }
3176
3177 void
3178 i386_print_statistics (FILE *file)
3179 {
3180 hash_print_statistics (file, "i386 opcode", op_hash);
3181 hash_print_statistics (file, "i386 register", reg_hash);
3182 }
3183 \f
3184 #ifdef DEBUG386
3185
3186 /* Debugging routines for md_assemble. */
3187 static void pte (insn_template *);
3188 static void pt (i386_operand_type);
3189 static void pe (expressionS *);
3190 static void ps (symbolS *);
3191
3192 static void
3193 pi (const char *line, i386_insn *x)
3194 {
3195 unsigned int j;
3196
3197 fprintf (stdout, "%s: template ", line);
3198 pte (&x->tm);
3199 fprintf (stdout, " address: base %s index %s scale %x\n",
3200 x->base_reg ? x->base_reg->reg_name : "none",
3201 x->index_reg ? x->index_reg->reg_name : "none",
3202 x->log2_scale_factor);
3203 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
3204 x->rm.mode, x->rm.reg, x->rm.regmem);
3205 fprintf (stdout, " sib: base %x index %x scale %x\n",
3206 x->sib.base, x->sib.index, x->sib.scale);
3207 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
3208 (x->rex & REX_W) != 0,
3209 (x->rex & REX_R) != 0,
3210 (x->rex & REX_X) != 0,
3211 (x->rex & REX_B) != 0);
3212 for (j = 0; j < x->operands; j++)
3213 {
3214 fprintf (stdout, " #%d: ", j + 1);
3215 pt (x->types[j]);
3216 fprintf (stdout, "\n");
3217 if (x->types[j].bitfield.class == Reg
3218 || x->types[j].bitfield.class == RegMMX
3219 || x->types[j].bitfield.class == RegSIMD
3220 || x->types[j].bitfield.class == RegMask
3221 || x->types[j].bitfield.class == SReg
3222 || x->types[j].bitfield.class == RegCR
3223 || x->types[j].bitfield.class == RegDR
3224 || x->types[j].bitfield.class == RegTR
3225 || x->types[j].bitfield.class == RegBND)
3226 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3227 if (operand_type_check (x->types[j], imm))
3228 pe (x->op[j].imms);
3229 if (operand_type_check (x->types[j], disp))
3230 pe (x->op[j].disps);
3231 }
3232 }
3233
3234 static void
3235 pte (insn_template *t)
3236 {
3237 unsigned int j;
3238 fprintf (stdout, " %d operands ", t->operands);
3239 fprintf (stdout, "opcode %x ", t->base_opcode);
3240 if (t->extension_opcode != None)
3241 fprintf (stdout, "ext %x ", t->extension_opcode);
3242 if (t->opcode_modifier.d)
3243 fprintf (stdout, "D");
3244 if (t->opcode_modifier.w)
3245 fprintf (stdout, "W");
3246 fprintf (stdout, "\n");
3247 for (j = 0; j < t->operands; j++)
3248 {
3249 fprintf (stdout, " #%d type ", j + 1);
3250 pt (t->operand_types[j]);
3251 fprintf (stdout, "\n");
3252 }
3253 }
3254
3255 static void
3256 pe (expressionS *e)
3257 {
3258 fprintf (stdout, " operation %d\n", e->X_op);
3259 fprintf (stdout, " add_number %ld (%lx)\n",
3260 (long) e->X_add_number, (long) e->X_add_number);
3261 if (e->X_add_symbol)
3262 {
3263 fprintf (stdout, " add_symbol ");
3264 ps (e->X_add_symbol);
3265 fprintf (stdout, "\n");
3266 }
3267 if (e->X_op_symbol)
3268 {
3269 fprintf (stdout, " op_symbol ");
3270 ps (e->X_op_symbol);
3271 fprintf (stdout, "\n");
3272 }
3273 }
3274
3275 static void
3276 ps (symbolS *s)
3277 {
3278 fprintf (stdout, "%s type %s%s",
3279 S_GET_NAME (s),
3280 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3281 segment_name (S_GET_SEGMENT (s)));
3282 }
3283
3284 static struct type_name
3285 {
3286 i386_operand_type mask;
3287 const char *name;
3288 }
3289 const type_names[] =
3290 {
3291 { OPERAND_TYPE_REG8, "r8" },
3292 { OPERAND_TYPE_REG16, "r16" },
3293 { OPERAND_TYPE_REG32, "r32" },
3294 { OPERAND_TYPE_REG64, "r64" },
3295 { OPERAND_TYPE_ACC8, "acc8" },
3296 { OPERAND_TYPE_ACC16, "acc16" },
3297 { OPERAND_TYPE_ACC32, "acc32" },
3298 { OPERAND_TYPE_ACC64, "acc64" },
3299 { OPERAND_TYPE_IMM8, "i8" },
3300 { OPERAND_TYPE_IMM8, "i8s" },
3301 { OPERAND_TYPE_IMM16, "i16" },
3302 { OPERAND_TYPE_IMM32, "i32" },
3303 { OPERAND_TYPE_IMM32S, "i32s" },
3304 { OPERAND_TYPE_IMM64, "i64" },
3305 { OPERAND_TYPE_IMM1, "i1" },
3306 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3307 { OPERAND_TYPE_DISP8, "d8" },
3308 { OPERAND_TYPE_DISP16, "d16" },
3309 { OPERAND_TYPE_DISP32, "d32" },
3310 { OPERAND_TYPE_DISP32S, "d32s" },
3311 { OPERAND_TYPE_DISP64, "d64" },
3312 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3313 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3314 { OPERAND_TYPE_CONTROL, "control reg" },
3315 { OPERAND_TYPE_TEST, "test reg" },
3316 { OPERAND_TYPE_DEBUG, "debug reg" },
3317 { OPERAND_TYPE_FLOATREG, "FReg" },
3318 { OPERAND_TYPE_FLOATACC, "FAcc" },
3319 { OPERAND_TYPE_SREG, "SReg" },
3320 { OPERAND_TYPE_REGMMX, "rMMX" },
3321 { OPERAND_TYPE_REGXMM, "rXMM" },
3322 { OPERAND_TYPE_REGYMM, "rYMM" },
3323 { OPERAND_TYPE_REGZMM, "rZMM" },
3324 { OPERAND_TYPE_REGTMM, "rTMM" },
3325 { OPERAND_TYPE_REGMASK, "Mask reg" },
3326 };
3327
3328 static void
3329 pt (i386_operand_type t)
3330 {
3331 unsigned int j;
3332 i386_operand_type a;
3333
3334 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3335 {
3336 a = operand_type_and (t, type_names[j].mask);
3337 if (operand_type_equal (&a, &type_names[j].mask))
3338 fprintf (stdout, "%s, ", type_names[j].name);
3339 }
3340 fflush (stdout);
3341 }
3342
3343 #endif /* DEBUG386 */
3344 \f
3345 static bfd_reloc_code_real_type
3346 reloc (unsigned int size,
3347 int pcrel,
3348 int sign,
3349 bfd_reloc_code_real_type other)
3350 {
3351 if (other != NO_RELOC)
3352 {
3353 reloc_howto_type *rel;
3354
3355 if (size == 8)
3356 switch (other)
3357 {
3358 case BFD_RELOC_X86_64_GOT32:
3359 return BFD_RELOC_X86_64_GOT64;
3360 break;
3361 case BFD_RELOC_X86_64_GOTPLT64:
3362 return BFD_RELOC_X86_64_GOTPLT64;
3363 break;
3364 case BFD_RELOC_X86_64_PLTOFF64:
3365 return BFD_RELOC_X86_64_PLTOFF64;
3366 break;
3367 case BFD_RELOC_X86_64_GOTPC32:
3368 other = BFD_RELOC_X86_64_GOTPC64;
3369 break;
3370 case BFD_RELOC_X86_64_GOTPCREL:
3371 other = BFD_RELOC_X86_64_GOTPCREL64;
3372 break;
3373 case BFD_RELOC_X86_64_TPOFF32:
3374 other = BFD_RELOC_X86_64_TPOFF64;
3375 break;
3376 case BFD_RELOC_X86_64_DTPOFF32:
3377 other = BFD_RELOC_X86_64_DTPOFF64;
3378 break;
3379 default:
3380 break;
3381 }
3382
3383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3384 if (other == BFD_RELOC_SIZE32)
3385 {
3386 if (size == 8)
3387 other = BFD_RELOC_SIZE64;
3388 if (pcrel)
3389 {
3390 as_bad (_("there are no pc-relative size relocations"));
3391 return NO_RELOC;
3392 }
3393 }
3394 #endif
3395
3396 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3397 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3398 sign = -1;
3399
3400 rel = bfd_reloc_type_lookup (stdoutput, other);
3401 if (!rel)
3402 as_bad (_("unknown relocation (%u)"), other);
3403 else if (size != bfd_get_reloc_size (rel))
3404 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3405 bfd_get_reloc_size (rel),
3406 size);
3407 else if (pcrel && !rel->pc_relative)
3408 as_bad (_("non-pc-relative relocation for pc-relative field"));
3409 else if ((rel->complain_on_overflow == complain_overflow_signed
3410 && !sign)
3411 || (rel->complain_on_overflow == complain_overflow_unsigned
3412 && sign > 0))
3413 as_bad (_("relocated field and relocation type differ in signedness"));
3414 else
3415 return other;
3416 return NO_RELOC;
3417 }
3418
3419 if (pcrel)
3420 {
3421 if (!sign)
3422 as_bad (_("there are no unsigned pc-relative relocations"));
3423 switch (size)
3424 {
3425 case 1: return BFD_RELOC_8_PCREL;
3426 case 2: return BFD_RELOC_16_PCREL;
3427 case 4: return BFD_RELOC_32_PCREL;
3428 case 8: return BFD_RELOC_64_PCREL;
3429 }
3430 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3431 }
3432 else
3433 {
3434 if (sign > 0)
3435 switch (size)
3436 {
3437 case 4: return BFD_RELOC_X86_64_32S;
3438 }
3439 else
3440 switch (size)
3441 {
3442 case 1: return BFD_RELOC_8;
3443 case 2: return BFD_RELOC_16;
3444 case 4: return BFD_RELOC_32;
3445 case 8: return BFD_RELOC_64;
3446 }
3447 as_bad (_("cannot do %s %u byte relocation"),
3448 sign > 0 ? "signed" : "unsigned", size);
3449 }
3450
3451 return NO_RELOC;
3452 }
3453
3454 /* Here we decide which fixups can be adjusted to make them relative to
3455 the beginning of the section instead of the symbol. Basically we need
3456 to make sure that the dynamic relocations are done correctly, so in
3457 some cases we force the original symbol to be used. */
3458
3459 int
3460 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3461 {
3462 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3463 if (!IS_ELF)
3464 return 1;
3465
3466 /* Don't adjust pc-relative references to merge sections in 64-bit
3467 mode. */
3468 if (use_rela_relocations
3469 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3470 && fixP->fx_pcrel)
3471 return 0;
3472
3473 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3474 and changed later by validate_fix. */
3475 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3476 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3477 return 0;
3478
3479 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3480 for size relocations. */
3481 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3482 || fixP->fx_r_type == BFD_RELOC_SIZE64
3483 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3484 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3485 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3486 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3487 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3488 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3489 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3490 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3491 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3492 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3493 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3494 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3495 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3496 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3497 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3498 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3499 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3500 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3501 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3502 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3503 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3504 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3505 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3506 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3507 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3508 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3509 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3510 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3511 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3512 return 0;
3513 #endif
3514 return 1;
3515 }
3516
3517 static int
3518 intel_float_operand (const char *mnemonic)
3519 {
3520 /* Note that the value returned is meaningful only for opcodes with (memory)
3521 operands, hence the code here is free to improperly handle opcodes that
3522 have no operands (for better performance and smaller code). */
3523
3524 if (mnemonic[0] != 'f')
3525 return 0; /* non-math */
3526
3527 switch (mnemonic[1])
3528 {
3529 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3530 the fs segment override prefix not currently handled because no
3531 call path can make opcodes without operands get here */
3532 case 'i':
3533 return 2 /* integer op */;
3534 case 'l':
3535 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3536 return 3; /* fldcw/fldenv */
3537 break;
3538 case 'n':
3539 if (mnemonic[2] != 'o' /* fnop */)
3540 return 3; /* non-waiting control op */
3541 break;
3542 case 'r':
3543 if (mnemonic[2] == 's')
3544 return 3; /* frstor/frstpm */
3545 break;
3546 case 's':
3547 if (mnemonic[2] == 'a')
3548 return 3; /* fsave */
3549 if (mnemonic[2] == 't')
3550 {
3551 switch (mnemonic[3])
3552 {
3553 case 'c': /* fstcw */
3554 case 'd': /* fstdw */
3555 case 'e': /* fstenv */
3556 case 's': /* fsts[gw] */
3557 return 3;
3558 }
3559 }
3560 break;
3561 case 'x':
3562 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3563 return 0; /* fxsave/fxrstor are not really math ops */
3564 break;
3565 }
3566
3567 return 1;
3568 }
3569
3570 /* Build the VEX prefix. */
3571
3572 static void
3573 build_vex_prefix (const insn_template *t)
3574 {
3575 unsigned int register_specifier;
3576 unsigned int implied_prefix;
3577 unsigned int vector_length;
3578 unsigned int w;
3579
3580 /* Check register specifier. */
3581 if (i.vex.register_specifier)
3582 {
3583 register_specifier =
3584 ~register_number (i.vex.register_specifier) & 0xf;
3585 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3586 }
3587 else
3588 register_specifier = 0xf;
3589
3590 /* Use 2-byte VEX prefix by swapping destination and source operand
3591 if there are more than 1 register operand. */
3592 if (i.reg_operands > 1
3593 && i.vec_encoding != vex_encoding_vex3
3594 && i.dir_encoding == dir_encoding_default
3595 && i.operands == i.reg_operands
3596 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3597 && i.tm.opcode_modifier.vexopcode == VEX0F
3598 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3599 && i.rex == REX_B)
3600 {
3601 unsigned int xchg = i.operands - 1;
3602 union i386_op temp_op;
3603 i386_operand_type temp_type;
3604
3605 temp_type = i.types[xchg];
3606 i.types[xchg] = i.types[0];
3607 i.types[0] = temp_type;
3608 temp_op = i.op[xchg];
3609 i.op[xchg] = i.op[0];
3610 i.op[0] = temp_op;
3611
3612 gas_assert (i.rm.mode == 3);
3613
3614 i.rex = REX_R;
3615 xchg = i.rm.regmem;
3616 i.rm.regmem = i.rm.reg;
3617 i.rm.reg = xchg;
3618
3619 if (i.tm.opcode_modifier.d)
3620 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3621 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3622 else /* Use the next insn. */
3623 i.tm = t[1];
3624 }
3625
3626 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3627 are no memory operands and at least 3 register ones. */
3628 if (i.reg_operands >= 3
3629 && i.vec_encoding != vex_encoding_vex3
3630 && i.reg_operands == i.operands - i.imm_operands
3631 && i.tm.opcode_modifier.vex
3632 && i.tm.opcode_modifier.commutative
3633 && (i.tm.opcode_modifier.sse2avx || optimize > 1)
3634 && i.rex == REX_B
3635 && i.vex.register_specifier
3636 && !(i.vex.register_specifier->reg_flags & RegRex))
3637 {
3638 unsigned int xchg = i.operands - i.reg_operands;
3639 union i386_op temp_op;
3640 i386_operand_type temp_type;
3641
3642 gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
3643 gas_assert (!i.tm.opcode_modifier.sae);
3644 gas_assert (operand_type_equal (&i.types[i.operands - 2],
3645 &i.types[i.operands - 3]));
3646 gas_assert (i.rm.mode == 3);
3647
3648 temp_type = i.types[xchg];
3649 i.types[xchg] = i.types[xchg + 1];
3650 i.types[xchg + 1] = temp_type;
3651 temp_op = i.op[xchg];
3652 i.op[xchg] = i.op[xchg + 1];
3653 i.op[xchg + 1] = temp_op;
3654
3655 i.rex = 0;
3656 xchg = i.rm.regmem | 8;
3657 i.rm.regmem = ~register_specifier & 0xf;
3658 gas_assert (!(i.rm.regmem & 8));
3659 i.vex.register_specifier += xchg - i.rm.regmem;
3660 register_specifier = ~xchg & 0xf;
3661 }
3662
3663 if (i.tm.opcode_modifier.vex == VEXScalar)
3664 vector_length = avxscalar;
3665 else if (i.tm.opcode_modifier.vex == VEX256)
3666 vector_length = 1;
3667 else
3668 {
3669 unsigned int op;
3670
3671 /* Determine vector length from the last multi-length vector
3672 operand. */
3673 vector_length = 0;
3674 for (op = t->operands; op--;)
3675 if (t->operand_types[op].bitfield.xmmword
3676 && t->operand_types[op].bitfield.ymmword
3677 && i.types[op].bitfield.ymmword)
3678 {
3679 vector_length = 1;
3680 break;
3681 }
3682 }
3683
3684 switch ((i.tm.base_opcode >> (i.tm.opcode_length << 3)) & 0xff)
3685 {
3686 case 0:
3687 implied_prefix = 0;
3688 break;
3689 case DATA_PREFIX_OPCODE:
3690 implied_prefix = 1;
3691 break;
3692 case REPE_PREFIX_OPCODE:
3693 implied_prefix = 2;
3694 break;
3695 case REPNE_PREFIX_OPCODE:
3696 implied_prefix = 3;
3697 break;
3698 default:
3699 abort ();
3700 }
3701
3702 /* Check the REX.W bit and VEXW. */
3703 if (i.tm.opcode_modifier.vexw == VEXWIG)
3704 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3705 else if (i.tm.opcode_modifier.vexw)
3706 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3707 else
3708 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3709
3710 /* Use 2-byte VEX prefix if possible. */
3711 if (w == 0
3712 && i.vec_encoding != vex_encoding_vex3
3713 && i.tm.opcode_modifier.vexopcode == VEX0F
3714 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3715 {
3716 /* 2-byte VEX prefix. */
3717 unsigned int r;
3718
3719 i.vex.length = 2;
3720 i.vex.bytes[0] = 0xc5;
3721
3722 /* Check the REX.R bit. */
3723 r = (i.rex & REX_R) ? 0 : 1;
3724 i.vex.bytes[1] = (r << 7
3725 | register_specifier << 3
3726 | vector_length << 2
3727 | implied_prefix);
3728 }
3729 else
3730 {
3731 /* 3-byte VEX prefix. */
3732 unsigned int m;
3733
3734 i.vex.length = 3;
3735
3736 switch (i.tm.opcode_modifier.vexopcode)
3737 {
3738 case VEX0F:
3739 m = 0x1;
3740 i.vex.bytes[0] = 0xc4;
3741 break;
3742 case VEX0F38:
3743 m = 0x2;
3744 i.vex.bytes[0] = 0xc4;
3745 break;
3746 case VEX0F3A:
3747 m = 0x3;
3748 i.vex.bytes[0] = 0xc4;
3749 break;
3750 case XOP08:
3751 m = 0x8;
3752 i.vex.bytes[0] = 0x8f;
3753 break;
3754 case XOP09:
3755 m = 0x9;
3756 i.vex.bytes[0] = 0x8f;
3757 break;
3758 case XOP0A:
3759 m = 0xa;
3760 i.vex.bytes[0] = 0x8f;
3761 break;
3762 default:
3763 abort ();
3764 }
3765
3766 /* The high 3 bits of the second VEX byte are 1's compliment
3767 of RXB bits from REX. */
3768 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3769
3770 i.vex.bytes[2] = (w << 7
3771 | register_specifier << 3
3772 | vector_length << 2
3773 | implied_prefix);
3774 }
3775 }
3776
3777 static INLINE bfd_boolean
3778 is_evex_encoding (const insn_template *t)
3779 {
3780 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3781 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3782 || t->opcode_modifier.sae;
3783 }
3784
3785 static INLINE bfd_boolean
3786 is_any_vex_encoding (const insn_template *t)
3787 {
3788 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3789 || is_evex_encoding (t);
3790 }
3791
3792 /* Build the EVEX prefix. */
3793
3794 static void
3795 build_evex_prefix (void)
3796 {
3797 unsigned int register_specifier;
3798 unsigned int implied_prefix;
3799 unsigned int m, w;
3800 rex_byte vrex_used = 0;
3801
3802 /* Check register specifier. */
3803 if (i.vex.register_specifier)
3804 {
3805 gas_assert ((i.vrex & REX_X) == 0);
3806
3807 register_specifier = i.vex.register_specifier->reg_num;
3808 if ((i.vex.register_specifier->reg_flags & RegRex))
3809 register_specifier += 8;
3810 /* The upper 16 registers are encoded in the fourth byte of the
3811 EVEX prefix. */
3812 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3813 i.vex.bytes[3] = 0x8;
3814 register_specifier = ~register_specifier & 0xf;
3815 }
3816 else
3817 {
3818 register_specifier = 0xf;
3819
3820 /* Encode upper 16 vector index register in the fourth byte of
3821 the EVEX prefix. */
3822 if (!(i.vrex & REX_X))
3823 i.vex.bytes[3] = 0x8;
3824 else
3825 vrex_used |= REX_X;
3826 }
3827
3828 switch ((i.tm.base_opcode >> 8) & 0xff)
3829 {
3830 case 0:
3831 implied_prefix = 0;
3832 break;
3833 case DATA_PREFIX_OPCODE:
3834 implied_prefix = 1;
3835 break;
3836 case REPE_PREFIX_OPCODE:
3837 implied_prefix = 2;
3838 break;
3839 case REPNE_PREFIX_OPCODE:
3840 implied_prefix = 3;
3841 break;
3842 default:
3843 abort ();
3844 }
3845
3846 /* 4 byte EVEX prefix. */
3847 i.vex.length = 4;
3848 i.vex.bytes[0] = 0x62;
3849
3850 /* mmmm bits. */
3851 switch (i.tm.opcode_modifier.vexopcode)
3852 {
3853 case VEX0F:
3854 m = 1;
3855 break;
3856 case VEX0F38:
3857 m = 2;
3858 break;
3859 case VEX0F3A:
3860 m = 3;
3861 break;
3862 default:
3863 abort ();
3864 break;
3865 }
3866
3867 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3868 bits from REX. */
3869 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3870
3871 /* The fifth bit of the second EVEX byte is 1's compliment of the
3872 REX_R bit in VREX. */
3873 if (!(i.vrex & REX_R))
3874 i.vex.bytes[1] |= 0x10;
3875 else
3876 vrex_used |= REX_R;
3877
3878 if ((i.reg_operands + i.imm_operands) == i.operands)
3879 {
3880 /* When all operands are registers, the REX_X bit in REX is not
3881 used. We reuse it to encode the upper 16 registers, which is
3882 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3883 as 1's compliment. */
3884 if ((i.vrex & REX_B))
3885 {
3886 vrex_used |= REX_B;
3887 i.vex.bytes[1] &= ~0x40;
3888 }
3889 }
3890
3891 /* EVEX instructions shouldn't need the REX prefix. */
3892 i.vrex &= ~vrex_used;
3893 gas_assert (i.vrex == 0);
3894
3895 /* Check the REX.W bit and VEXW. */
3896 if (i.tm.opcode_modifier.vexw == VEXWIG)
3897 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3898 else if (i.tm.opcode_modifier.vexw)
3899 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3900 else
3901 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
3902
3903 /* Encode the U bit. */
3904 implied_prefix |= 0x4;
3905
3906 /* The third byte of the EVEX prefix. */
3907 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3908
3909 /* The fourth byte of the EVEX prefix. */
3910 /* The zeroing-masking bit. */
3911 if (i.mask && i.mask->zeroing)
3912 i.vex.bytes[3] |= 0x80;
3913
3914 /* Don't always set the broadcast bit if there is no RC. */
3915 if (!i.rounding)
3916 {
3917 /* Encode the vector length. */
3918 unsigned int vec_length;
3919
3920 if (!i.tm.opcode_modifier.evex
3921 || i.tm.opcode_modifier.evex == EVEXDYN)
3922 {
3923 unsigned int op;
3924
3925 /* Determine vector length from the last multi-length vector
3926 operand. */
3927 for (op = i.operands; op--;)
3928 if (i.tm.operand_types[op].bitfield.xmmword
3929 + i.tm.operand_types[op].bitfield.ymmword
3930 + i.tm.operand_types[op].bitfield.zmmword > 1)
3931 {
3932 if (i.types[op].bitfield.zmmword)
3933 {
3934 i.tm.opcode_modifier.evex = EVEX512;
3935 break;
3936 }
3937 else if (i.types[op].bitfield.ymmword)
3938 {
3939 i.tm.opcode_modifier.evex = EVEX256;
3940 break;
3941 }
3942 else if (i.types[op].bitfield.xmmword)
3943 {
3944 i.tm.opcode_modifier.evex = EVEX128;
3945 break;
3946 }
3947 else if (i.broadcast && (int) op == i.broadcast->operand)
3948 {
3949 switch (i.broadcast->bytes)
3950 {
3951 case 64:
3952 i.tm.opcode_modifier.evex = EVEX512;
3953 break;
3954 case 32:
3955 i.tm.opcode_modifier.evex = EVEX256;
3956 break;
3957 case 16:
3958 i.tm.opcode_modifier.evex = EVEX128;
3959 break;
3960 default:
3961 abort ();
3962 }
3963 break;
3964 }
3965 }
3966
3967 if (op >= MAX_OPERANDS)
3968 abort ();
3969 }
3970
3971 switch (i.tm.opcode_modifier.evex)
3972 {
3973 case EVEXLIG: /* LL' is ignored */
3974 vec_length = evexlig << 5;
3975 break;
3976 case EVEX128:
3977 vec_length = 0 << 5;
3978 break;
3979 case EVEX256:
3980 vec_length = 1 << 5;
3981 break;
3982 case EVEX512:
3983 vec_length = 2 << 5;
3984 break;
3985 default:
3986 abort ();
3987 break;
3988 }
3989 i.vex.bytes[3] |= vec_length;
3990 /* Encode the broadcast bit. */
3991 if (i.broadcast)
3992 i.vex.bytes[3] |= 0x10;
3993 }
3994 else
3995 {
3996 if (i.rounding->type != saeonly)
3997 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3998 else
3999 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
4000 }
4001
4002 if (i.mask && i.mask->mask)
4003 i.vex.bytes[3] |= i.mask->mask->reg_num;
4004 }
4005
4006 static void
4007 process_immext (void)
4008 {
4009 expressionS *exp;
4010
4011 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4012 which is coded in the same place as an 8-bit immediate field
4013 would be. Here we fake an 8-bit immediate operand from the
4014 opcode suffix stored in tm.extension_opcode.
4015
4016 AVX instructions also use this encoding, for some of
4017 3 argument instructions. */
4018
4019 gas_assert (i.imm_operands <= 1
4020 && (i.operands <= 2
4021 || (is_any_vex_encoding (&i.tm)
4022 && i.operands <= 4)));
4023
4024 exp = &im_expressions[i.imm_operands++];
4025 i.op[i.operands].imms = exp;
4026 i.types[i.operands] = imm8;
4027 i.operands++;
4028 exp->X_op = O_constant;
4029 exp->X_add_number = i.tm.extension_opcode;
4030 i.tm.extension_opcode = None;
4031 }
4032
4033
4034 static int
4035 check_hle (void)
4036 {
4037 switch (i.tm.opcode_modifier.hleprefixok)
4038 {
4039 default:
4040 abort ();
4041 case HLEPrefixNone:
4042 as_bad (_("invalid instruction `%s' after `%s'"),
4043 i.tm.name, i.hle_prefix);
4044 return 0;
4045 case HLEPrefixLock:
4046 if (i.prefix[LOCK_PREFIX])
4047 return 1;
4048 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4049 return 0;
4050 case HLEPrefixAny:
4051 return 1;
4052 case HLEPrefixRelease:
4053 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4054 {
4055 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4056 i.tm.name);
4057 return 0;
4058 }
4059 if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4060 {
4061 as_bad (_("memory destination needed for instruction `%s'"
4062 " after `xrelease'"), i.tm.name);
4063 return 0;
4064 }
4065 return 1;
4066 }
4067 }
4068
4069 /* Try the shortest encoding by shortening operand size. */
4070
4071 static void
4072 optimize_encoding (void)
4073 {
4074 unsigned int j;
4075
4076 if (optimize_for_space
4077 && !is_any_vex_encoding (&i.tm)
4078 && i.reg_operands == 1
4079 && i.imm_operands == 1
4080 && !i.types[1].bitfield.byte
4081 && i.op[0].imms->X_op == O_constant
4082 && fits_in_imm7 (i.op[0].imms->X_add_number)
4083 && (i.tm.base_opcode == 0xa8
4084 || (i.tm.base_opcode == 0xf6
4085 && i.tm.extension_opcode == 0x0)))
4086 {
4087 /* Optimize: -Os:
4088 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4089 */
4090 unsigned int base_regnum = i.op[1].regs->reg_num;
4091 if (flag_code == CODE_64BIT || base_regnum < 4)
4092 {
4093 i.types[1].bitfield.byte = 1;
4094 /* Ignore the suffix. */
4095 i.suffix = 0;
4096 /* Convert to byte registers. */
4097 if (i.types[1].bitfield.word)
4098 j = 16;
4099 else if (i.types[1].bitfield.dword)
4100 j = 32;
4101 else
4102 j = 48;
4103 if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4)
4104 j += 8;
4105 i.op[1].regs -= j;
4106 }
4107 }
4108 else if (flag_code == CODE_64BIT
4109 && !is_any_vex_encoding (&i.tm)
4110 && ((i.types[1].bitfield.qword
4111 && i.reg_operands == 1
4112 && i.imm_operands == 1
4113 && i.op[0].imms->X_op == O_constant
4114 && ((i.tm.base_opcode == 0xb8
4115 && i.tm.extension_opcode == None
4116 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
4117 || (fits_in_imm31 (i.op[0].imms->X_add_number)
4118 && ((i.tm.base_opcode == 0x24
4119 || i.tm.base_opcode == 0xa8)
4120 || (i.tm.base_opcode == 0x80
4121 && i.tm.extension_opcode == 0x4)
4122 || ((i.tm.base_opcode == 0xf6
4123 || (i.tm.base_opcode | 1) == 0xc7)
4124 && i.tm.extension_opcode == 0x0)))
4125 || (fits_in_imm7 (i.op[0].imms->X_add_number)
4126 && i.tm.base_opcode == 0x83
4127 && i.tm.extension_opcode == 0x4)))
4128 || (i.types[0].bitfield.qword
4129 && ((i.reg_operands == 2
4130 && i.op[0].regs == i.op[1].regs
4131 && (i.tm.base_opcode == 0x30
4132 || i.tm.base_opcode == 0x28))
4133 || (i.reg_operands == 1
4134 && i.operands == 1
4135 && i.tm.base_opcode == 0x30)))))
4136 {
4137 /* Optimize: -O:
4138 andq $imm31, %r64 -> andl $imm31, %r32
4139 andq $imm7, %r64 -> andl $imm7, %r32
4140 testq $imm31, %r64 -> testl $imm31, %r32
4141 xorq %r64, %r64 -> xorl %r32, %r32
4142 subq %r64, %r64 -> subl %r32, %r32
4143 movq $imm31, %r64 -> movl $imm31, %r32
4144 movq $imm32, %r64 -> movl $imm32, %r32
4145 */
4146 i.tm.opcode_modifier.norex64 = 1;
4147 if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7)
4148 {
4149 /* Handle
4150 movq $imm31, %r64 -> movl $imm31, %r32
4151 movq $imm32, %r64 -> movl $imm32, %r32
4152 */
4153 i.tm.operand_types[0].bitfield.imm32 = 1;
4154 i.tm.operand_types[0].bitfield.imm32s = 0;
4155 i.tm.operand_types[0].bitfield.imm64 = 0;
4156 i.types[0].bitfield.imm32 = 1;
4157 i.types[0].bitfield.imm32s = 0;
4158 i.types[0].bitfield.imm64 = 0;
4159 i.types[1].bitfield.dword = 1;
4160 i.types[1].bitfield.qword = 0;
4161 if ((i.tm.base_opcode | 1) == 0xc7)
4162 {
4163 /* Handle
4164 movq $imm31, %r64 -> movl $imm31, %r32
4165 */
4166 i.tm.base_opcode = 0xb8;
4167 i.tm.extension_opcode = None;
4168 i.tm.opcode_modifier.w = 0;
4169 i.tm.opcode_modifier.modrm = 0;
4170 }
4171 }
4172 }
4173 else if (optimize > 1
4174 && !optimize_for_space
4175 && !is_any_vex_encoding (&i.tm)
4176 && i.reg_operands == 2
4177 && i.op[0].regs == i.op[1].regs
4178 && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
4179 || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20)
4180 && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4181 {
4182 /* Optimize: -O2:
4183 andb %rN, %rN -> testb %rN, %rN
4184 andw %rN, %rN -> testw %rN, %rN
4185 andq %rN, %rN -> testq %rN, %rN
4186 orb %rN, %rN -> testb %rN, %rN
4187 orw %rN, %rN -> testw %rN, %rN
4188 orq %rN, %rN -> testq %rN, %rN
4189
4190 and outside of 64-bit mode
4191
4192 andl %rN, %rN -> testl %rN, %rN
4193 orl %rN, %rN -> testl %rN, %rN
4194 */
4195 i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4196 }
4197 else if (i.reg_operands == 3
4198 && i.op[0].regs == i.op[1].regs
4199 && !i.types[2].bitfield.xmmword
4200 && (i.tm.opcode_modifier.vex
4201 || ((!i.mask || i.mask->zeroing)
4202 && !i.rounding
4203 && is_evex_encoding (&i.tm)
4204 && (i.vec_encoding != vex_encoding_evex
4205 || cpu_arch_isa_flags.bitfield.cpuavx512vl
4206 || i.tm.cpu_flags.bitfield.cpuavx512vl
4207 || (i.tm.operand_types[2].bitfield.zmmword
4208 && i.types[2].bitfield.ymmword))))
4209 && ((i.tm.base_opcode == 0x55
4210 || i.tm.base_opcode == 0x6655
4211 || i.tm.base_opcode == 0x66df
4212 || i.tm.base_opcode == 0x57
4213 || i.tm.base_opcode == 0x6657
4214 || i.tm.base_opcode == 0x66ef
4215 || i.tm.base_opcode == 0x66f8
4216 || i.tm.base_opcode == 0x66f9
4217 || i.tm.base_opcode == 0x66fa
4218 || i.tm.base_opcode == 0x66fb
4219 || i.tm.base_opcode == 0x42
4220 || i.tm.base_opcode == 0x6642
4221 || i.tm.base_opcode == 0x47
4222 || i.tm.base_opcode == 0x6647)
4223 && i.tm.extension_opcode == None))
4224 {
4225 /* Optimize: -O1:
4226 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4227 vpsubq and vpsubw:
4228 EVEX VOP %zmmM, %zmmM, %zmmN
4229 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4230 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4231 EVEX VOP %ymmM, %ymmM, %ymmN
4232 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4233 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4234 VEX VOP %ymmM, %ymmM, %ymmN
4235 -> VEX VOP %xmmM, %xmmM, %xmmN
4236 VOP, one of vpandn and vpxor:
4237 VEX VOP %ymmM, %ymmM, %ymmN
4238 -> VEX VOP %xmmM, %xmmM, %xmmN
4239 VOP, one of vpandnd and vpandnq:
4240 EVEX VOP %zmmM, %zmmM, %zmmN
4241 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4242 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4243 EVEX VOP %ymmM, %ymmM, %ymmN
4244 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4245 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4246 VOP, one of vpxord and vpxorq:
4247 EVEX VOP %zmmM, %zmmM, %zmmN
4248 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4249 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4250 EVEX VOP %ymmM, %ymmM, %ymmN
4251 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4252 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4253 VOP, one of kxord and kxorq:
4254 VEX VOP %kM, %kM, %kN
4255 -> VEX kxorw %kM, %kM, %kN
4256 VOP, one of kandnd and kandnq:
4257 VEX VOP %kM, %kM, %kN
4258 -> VEX kandnw %kM, %kM, %kN
4259 */
4260 if (is_evex_encoding (&i.tm))
4261 {
4262 if (i.vec_encoding != vex_encoding_evex)
4263 {
4264 i.tm.opcode_modifier.vex = VEX128;
4265 i.tm.opcode_modifier.vexw = VEXW0;
4266 i.tm.opcode_modifier.evex = 0;
4267 }
4268 else if (optimize > 1)
4269 i.tm.opcode_modifier.evex = EVEX128;
4270 else
4271 return;
4272 }
4273 else if (i.tm.operand_types[0].bitfield.class == RegMask)
4274 {
4275 i.tm.base_opcode &= 0xff;
4276 i.tm.opcode_modifier.vexw = VEXW0;
4277 }
4278 else
4279 i.tm.opcode_modifier.vex = VEX128;
4280
4281 if (i.tm.opcode_modifier.vex)
4282 for (j = 0; j < 3; j++)
4283 {
4284 i.types[j].bitfield.xmmword = 1;
4285 i.types[j].bitfield.ymmword = 0;
4286 }
4287 }
4288 else if (i.vec_encoding != vex_encoding_evex
4289 && !i.types[0].bitfield.zmmword
4290 && !i.types[1].bitfield.zmmword
4291 && !i.mask
4292 && !i.broadcast
4293 && is_evex_encoding (&i.tm)
4294 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
4295 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
4296 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
4297 || (i.tm.base_opcode & ~4) == 0x66db
4298 || (i.tm.base_opcode & ~4) == 0x66eb)
4299 && i.tm.extension_opcode == None)
4300 {
4301 /* Optimize: -O1:
4302 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4303 vmovdqu32 and vmovdqu64:
4304 EVEX VOP %xmmM, %xmmN
4305 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP %ymmM, %ymmN
4307 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4308 EVEX VOP %xmmM, mem
4309 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4310 EVEX VOP %ymmM, mem
4311 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4312 EVEX VOP mem, %xmmN
4313 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4314 EVEX VOP mem, %ymmN
4315 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4316 VOP, one of vpand, vpandn, vpor, vpxor:
4317 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4318 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4319 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4320 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4321 EVEX VOP{d,q} mem, %xmmM, %xmmN
4322 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4323 EVEX VOP{d,q} mem, %ymmM, %ymmN
4324 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4325 */
4326 for (j = 0; j < i.operands; j++)
4327 if (operand_type_check (i.types[j], disp)
4328 && i.op[j].disps->X_op == O_constant)
4329 {
4330 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4331 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4332 bytes, we choose EVEX Disp8 over VEX Disp32. */
4333 int evex_disp8, vex_disp8;
4334 unsigned int memshift = i.memshift;
4335 offsetT n = i.op[j].disps->X_add_number;
4336
4337 evex_disp8 = fits_in_disp8 (n);
4338 i.memshift = 0;
4339 vex_disp8 = fits_in_disp8 (n);
4340 if (evex_disp8 != vex_disp8)
4341 {
4342 i.memshift = memshift;
4343 return;
4344 }
4345
4346 i.types[j].bitfield.disp8 = vex_disp8;
4347 break;
4348 }
4349 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
4350 i.tm.base_opcode ^= 0xf36f ^ 0xf26f;
4351 i.tm.opcode_modifier.vex
4352 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4353 i.tm.opcode_modifier.vexw = VEXW0;
4354 /* VPAND, VPOR, and VPXOR are commutative. */
4355 if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df)
4356 i.tm.opcode_modifier.commutative = 1;
4357 i.tm.opcode_modifier.evex = 0;
4358 i.tm.opcode_modifier.masking = 0;
4359 i.tm.opcode_modifier.broadcast = 0;
4360 i.tm.opcode_modifier.disp8memshift = 0;
4361 i.memshift = 0;
4362 if (j < i.operands)
4363 i.types[j].bitfield.disp8
4364 = fits_in_disp8 (i.op[j].disps->X_add_number);
4365 }
4366 }
4367
4368 /* Return non-zero for load instruction. */
4369
4370 static int
4371 load_insn_p (void)
4372 {
4373 unsigned int dest;
4374 int any_vex_p = is_any_vex_encoding (&i.tm);
4375 unsigned int base_opcode = i.tm.base_opcode | 1;
4376
4377 if (!any_vex_p)
4378 {
4379 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4380 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4381 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4382 if (i.tm.opcode_modifier.anysize)
4383 return 0;
4384
4385 /* pop, popf, popa. */
4386 if (strcmp (i.tm.name, "pop") == 0
4387 || i.tm.base_opcode == 0x9d
4388 || i.tm.base_opcode == 0x61)
4389 return 1;
4390
4391 /* movs, cmps, lods, scas. */
4392 if ((i.tm.base_opcode | 0xb) == 0xaf)
4393 return 1;
4394
4395 /* outs, xlatb. */
4396 if (base_opcode == 0x6f
4397 || i.tm.base_opcode == 0xd7)
4398 return 1;
4399 /* NB: For AMD-specific insns with implicit memory operands,
4400 they're intentionally not covered. */
4401 }
4402
4403 /* No memory operand. */
4404 if (!i.mem_operands)
4405 return 0;
4406
4407 if (any_vex_p)
4408 {
4409 /* vldmxcsr. */
4410 if (i.tm.base_opcode == 0xae
4411 && i.tm.opcode_modifier.vex
4412 && i.tm.opcode_modifier.vexopcode == VEX0F
4413 && i.tm.extension_opcode == 2)
4414 return 1;
4415 }
4416 else
4417 {
4418 /* test, not, neg, mul, imul, div, idiv. */
4419 if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7)
4420 && i.tm.extension_opcode != 1)
4421 return 1;
4422
4423 /* inc, dec. */
4424 if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
4425 return 1;
4426
4427 /* add, or, adc, sbb, and, sub, xor, cmp. */
4428 if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
4429 return 1;
4430
4431 /* bt, bts, btr, btc. */
4432 if (i.tm.base_opcode == 0xfba
4433 && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
4434 return 1;
4435
4436 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4437 if ((base_opcode == 0xc1
4438 || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3))
4439 && i.tm.extension_opcode != 6)
4440 return 1;
4441
4442 /* cmpxchg8b, cmpxchg16b, xrstors. */
4443 if (i.tm.base_opcode == 0xfc7
4444 && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3))
4445 return 1;
4446
4447 /* fxrstor, ldmxcsr, xrstor. */
4448 if (i.tm.base_opcode == 0xfae
4449 && (i.tm.extension_opcode == 1
4450 || i.tm.extension_opcode == 2
4451 || i.tm.extension_opcode == 5))
4452 return 1;
4453
4454 /* lgdt, lidt, lmsw. */
4455 if (i.tm.base_opcode == 0xf01
4456 && (i.tm.extension_opcode == 2
4457 || i.tm.extension_opcode == 3
4458 || i.tm.extension_opcode == 6))
4459 return 1;
4460
4461 /* vmptrld */
4462 if (i.tm.base_opcode == 0xfc7
4463 && i.tm.extension_opcode == 6)
4464 return 1;
4465
4466 /* Check for x87 instructions. */
4467 if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf)
4468 {
4469 /* Skip fst, fstp, fstenv, fstcw. */
4470 if (i.tm.base_opcode == 0xd9
4471 && (i.tm.extension_opcode == 2
4472 || i.tm.extension_opcode == 3
4473 || i.tm.extension_opcode == 6
4474 || i.tm.extension_opcode == 7))
4475 return 0;
4476
4477 /* Skip fisttp, fist, fistp, fstp. */
4478 if (i.tm.base_opcode == 0xdb
4479 && (i.tm.extension_opcode == 1
4480 || i.tm.extension_opcode == 2
4481 || i.tm.extension_opcode == 3
4482 || i.tm.extension_opcode == 7))
4483 return 0;
4484
4485 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4486 if (i.tm.base_opcode == 0xdd
4487 && (i.tm.extension_opcode == 1
4488 || i.tm.extension_opcode == 2
4489 || i.tm.extension_opcode == 3
4490 || i.tm.extension_opcode == 6
4491 || i.tm.extension_opcode == 7))
4492 return 0;
4493
4494 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4495 if (i.tm.base_opcode == 0xdf
4496 && (i.tm.extension_opcode == 1
4497 || i.tm.extension_opcode == 2
4498 || i.tm.extension_opcode == 3
4499 || i.tm.extension_opcode == 6
4500 || i.tm.extension_opcode == 7))
4501 return 0;
4502
4503 return 1;
4504 }
4505 }
4506
4507 dest = i.operands - 1;
4508
4509 /* Check fake imm8 operand and 3 source operands. */
4510 if ((i.tm.opcode_modifier.immext
4511 || i.tm.opcode_modifier.vexsources == VEX3SOURCES)
4512 && i.types[dest].bitfield.imm8)
4513 dest--;
4514
4515 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4516 if (!any_vex_p
4517 && (base_opcode == 0x1
4518 || base_opcode == 0x9
4519 || base_opcode == 0x11
4520 || base_opcode == 0x19
4521 || base_opcode == 0x21
4522 || base_opcode == 0x29
4523 || base_opcode == 0x31
4524 || base_opcode == 0x39
4525 || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87)
4526 || base_opcode == 0xfc1))
4527 return 1;
4528
4529 /* Check for load instruction. */
4530 return (i.types[dest].bitfield.class != ClassNone
4531 || i.types[dest].bitfield.instance == Accum);
4532 }
4533
4534 /* Output lfence, 0xfaee8, after instruction. */
4535
4536 static void
4537 insert_lfence_after (void)
4538 {
4539 if (lfence_after_load && load_insn_p ())
4540 {
4541 /* There are also two REP string instructions that require
4542 special treatment. Specifically, the compare string (CMPS)
4543 and scan string (SCAS) instructions set EFLAGS in a manner
4544 that depends on the data being compared/scanned. When used
4545 with a REP prefix, the number of iterations may therefore
4546 vary depending on this data. If the data is a program secret
4547 chosen by the adversary using an LVI method,
4548 then this data-dependent behavior may leak some aspect
4549 of the secret. */
4550 if (((i.tm.base_opcode | 0x1) == 0xa7
4551 || (i.tm.base_opcode | 0x1) == 0xaf)
4552 && i.prefix[REP_PREFIX])
4553 {
4554 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4555 i.tm.name);
4556 }
4557 char *p = frag_more (3);
4558 *p++ = 0xf;
4559 *p++ = 0xae;
4560 *p = 0xe8;
4561 }
4562 }
4563
4564 /* Output lfence, 0xfaee8, before instruction. */
4565
4566 static void
4567 insert_lfence_before (void)
4568 {
4569 char *p;
4570
4571 if (is_any_vex_encoding (&i.tm))
4572 return;
4573
4574 if (i.tm.base_opcode == 0xff
4575 && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
4576 {
4577 /* Insert lfence before indirect branch if needed. */
4578
4579 if (lfence_before_indirect_branch == lfence_branch_none)
4580 return;
4581
4582 if (i.operands != 1)
4583 abort ();
4584
4585 if (i.reg_operands == 1)
4586 {
4587 /* Indirect branch via register. Don't insert lfence with
4588 -mlfence-after-load=yes. */
4589 if (lfence_after_load
4590 || lfence_before_indirect_branch == lfence_branch_memory)
4591 return;
4592 }
4593 else if (i.mem_operands == 1
4594 && lfence_before_indirect_branch != lfence_branch_register)
4595 {
4596 as_warn (_("indirect `%s` with memory operand should be avoided"),
4597 i.tm.name);
4598 return;
4599 }
4600 else
4601 return;
4602
4603 if (last_insn.kind != last_insn_other
4604 && last_insn.seg == now_seg)
4605 {
4606 as_warn_where (last_insn.file, last_insn.line,
4607 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4608 last_insn.name, i.tm.name);
4609 return;
4610 }
4611
4612 p = frag_more (3);
4613 *p++ = 0xf;
4614 *p++ = 0xae;
4615 *p = 0xe8;
4616 return;
4617 }
4618
4619 /* Output or/not/shl and lfence before near ret. */
4620 if (lfence_before_ret != lfence_before_ret_none
4621 && (i.tm.base_opcode == 0xc2
4622 || i.tm.base_opcode == 0xc3))
4623 {
4624 if (last_insn.kind != last_insn_other
4625 && last_insn.seg == now_seg)
4626 {
4627 as_warn_where (last_insn.file, last_insn.line,
4628 _("`%s` skips -mlfence-before-ret on `%s`"),
4629 last_insn.name, i.tm.name);
4630 return;
4631 }
4632
4633 /* Near ret ingore operand size override under CPU64. */
4634 char prefix = flag_code == CODE_64BIT
4635 ? 0x48
4636 : i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
4637
4638 if (lfence_before_ret == lfence_before_ret_not)
4639 {
4640 /* not: 0xf71424, may add prefix
4641 for operand size override or 64-bit code. */
4642 p = frag_more ((prefix ? 2 : 0) + 6 + 3);
4643 if (prefix)
4644 *p++ = prefix;
4645 *p++ = 0xf7;
4646 *p++ = 0x14;
4647 *p++ = 0x24;
4648 if (prefix)
4649 *p++ = prefix;
4650 *p++ = 0xf7;
4651 *p++ = 0x14;
4652 *p++ = 0x24;
4653 }
4654 else
4655 {
4656 p = frag_more ((prefix ? 1 : 0) + 4 + 3);
4657 if (prefix)
4658 *p++ = prefix;
4659 if (lfence_before_ret == lfence_before_ret_or)
4660 {
4661 /* or: 0x830c2400, may add prefix
4662 for operand size override or 64-bit code. */
4663 *p++ = 0x83;
4664 *p++ = 0x0c;
4665 }
4666 else
4667 {
4668 /* shl: 0xc1242400, may add prefix
4669 for operand size override or 64-bit code. */
4670 *p++ = 0xc1;
4671 *p++ = 0x24;
4672 }
4673
4674 *p++ = 0x24;
4675 *p++ = 0x0;
4676 }
4677
4678 *p++ = 0xf;
4679 *p++ = 0xae;
4680 *p = 0xe8;
4681 }
4682 }
4683
4684 /* This is the guts of the machine-dependent assembler. LINE points to a
4685 machine dependent instruction. This function is supposed to emit
4686 the frags/bytes it assembles to. */
4687
4688 void
4689 md_assemble (char *line)
4690 {
4691 unsigned int j;
4692 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4693 const insn_template *t;
4694
4695 /* Initialize globals. */
4696 memset (&i, '\0', sizeof (i));
4697 for (j = 0; j < MAX_OPERANDS; j++)
4698 i.reloc[j] = NO_RELOC;
4699 memset (disp_expressions, '\0', sizeof (disp_expressions));
4700 memset (im_expressions, '\0', sizeof (im_expressions));
4701 save_stack_p = save_stack;
4702
4703 /* First parse an instruction mnemonic & call i386_operand for the operands.
4704 We assume that the scrubber has arranged it so that line[0] is the valid
4705 start of a (possibly prefixed) mnemonic. */
4706
4707 line = parse_insn (line, mnemonic);
4708 if (line == NULL)
4709 return;
4710 mnem_suffix = i.suffix;
4711
4712 line = parse_operands (line, mnemonic);
4713 this_operand = -1;
4714 xfree (i.memop1_string);
4715 i.memop1_string = NULL;
4716 if (line == NULL)
4717 return;
4718
4719 /* Now we've parsed the mnemonic into a set of templates, and have the
4720 operands at hand. */
4721
4722 /* All Intel opcodes have reversed operands except for "bound", "enter",
4723 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4724 intersegment "jmp" and "call" instructions with 2 immediate operands so
4725 that the immediate segment precedes the offset, as it does when in AT&T
4726 mode. */
4727 if (intel_syntax
4728 && i.operands > 1
4729 && (strcmp (mnemonic, "bound") != 0)
4730 && (strcmp (mnemonic, "invlpga") != 0)
4731 && (strncmp (mnemonic, "monitor", 7) != 0)
4732 && (strncmp (mnemonic, "mwait", 5) != 0)
4733 && (strcmp (mnemonic, "tpause") != 0)
4734 && (strcmp (mnemonic, "umwait") != 0)
4735 && !(operand_type_check (i.types[0], imm)
4736 && operand_type_check (i.types[1], imm)))
4737 swap_operands ();
4738
4739 /* The order of the immediates should be reversed
4740 for 2 immediates extrq and insertq instructions */
4741 if (i.imm_operands == 2
4742 && (strcmp (mnemonic, "extrq") == 0
4743 || strcmp (mnemonic, "insertq") == 0))
4744 swap_2_operands (0, 1);
4745
4746 if (i.imm_operands)
4747 optimize_imm ();
4748
4749 /* Don't optimize displacement for movabs since it only takes 64bit
4750 displacement. */
4751 if (i.disp_operands
4752 && i.disp_encoding != disp_encoding_32bit
4753 && (flag_code != CODE_64BIT
4754 || strcmp (mnemonic, "movabs") != 0))
4755 optimize_disp ();
4756
4757 /* Next, we find a template that matches the given insn,
4758 making sure the overlap of the given operands types is consistent
4759 with the template operand types. */
4760
4761 if (!(t = match_template (mnem_suffix)))
4762 return;
4763
4764 if (sse_check != check_none
4765 && !i.tm.opcode_modifier.noavx
4766 && !i.tm.cpu_flags.bitfield.cpuavx
4767 && !i.tm.cpu_flags.bitfield.cpuavx512f
4768 && (i.tm.cpu_flags.bitfield.cpusse
4769 || i.tm.cpu_flags.bitfield.cpusse2
4770 || i.tm.cpu_flags.bitfield.cpusse3
4771 || i.tm.cpu_flags.bitfield.cpussse3
4772 || i.tm.cpu_flags.bitfield.cpusse4_1
4773 || i.tm.cpu_flags.bitfield.cpusse4_2
4774 || i.tm.cpu_flags.bitfield.cpupclmul
4775 || i.tm.cpu_flags.bitfield.cpuaes
4776 || i.tm.cpu_flags.bitfield.cpusha
4777 || i.tm.cpu_flags.bitfield.cpugfni))
4778 {
4779 (sse_check == check_warning
4780 ? as_warn
4781 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4782 }
4783
4784 if (i.tm.opcode_modifier.fwait)
4785 if (!add_prefix (FWAIT_OPCODE))
4786 return;
4787
4788 /* Check if REP prefix is OK. */
4789 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4790 {
4791 as_bad (_("invalid instruction `%s' after `%s'"),
4792 i.tm.name, i.rep_prefix);
4793 return;
4794 }
4795
4796 /* Check for lock without a lockable instruction. Destination operand
4797 must be memory unless it is xchg (0x86). */
4798 if (i.prefix[LOCK_PREFIX]
4799 && (!i.tm.opcode_modifier.islockable
4800 || i.mem_operands == 0
4801 || (i.tm.base_opcode != 0x86
4802 && !(i.flags[i.operands - 1] & Operand_Mem))))
4803 {
4804 as_bad (_("expecting lockable instruction after `lock'"));
4805 return;
4806 }
4807
4808 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4809 if (i.prefix[DATA_PREFIX]
4810 && (is_any_vex_encoding (&i.tm)
4811 || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
4812 || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX))
4813 {
4814 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4815 return;
4816 }
4817
4818 /* Check if HLE prefix is OK. */
4819 if (i.hle_prefix && !check_hle ())
4820 return;
4821
4822 /* Check BND prefix. */
4823 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4824 as_bad (_("expecting valid branch instruction after `bnd'"));
4825
4826 /* Check NOTRACK prefix. */
4827 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4828 as_bad (_("expecting indirect branch instruction after `notrack'"));
4829
4830 if (i.tm.cpu_flags.bitfield.cpumpx)
4831 {
4832 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4833 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4834 else if (flag_code != CODE_16BIT
4835 ? i.prefix[ADDR_PREFIX]
4836 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4837 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4838 }
4839
4840 /* Insert BND prefix. */
4841 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4842 {
4843 if (!i.prefix[BND_PREFIX])
4844 add_prefix (BND_PREFIX_OPCODE);
4845 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4846 {
4847 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4848 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4849 }
4850 }
4851
4852 /* Check string instruction segment overrides. */
4853 if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
4854 {
4855 gas_assert (i.mem_operands);
4856 if (!check_string ())
4857 return;
4858 i.disp_operands = 0;
4859 }
4860
4861 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4862 optimize_encoding ();
4863
4864 if (!process_suffix ())
4865 return;
4866
4867 /* Update operand types and check extended states. */
4868 for (j = 0; j < i.operands; j++)
4869 {
4870 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4871 switch (i.tm.operand_types[j].bitfield.class)
4872 {
4873 default:
4874 break;
4875 case RegMMX:
4876 i.xstate |= xstate_mmx;
4877 break;
4878 case RegMask:
4879 i.xstate |= xstate_zmm;
4880 break;
4881 case RegSIMD:
4882 if (i.tm.operand_types[j].bitfield.tmmword)
4883 i.xstate |= xstate_tmm;
4884 else if (i.tm.operand_types[j].bitfield.zmmword)
4885 i.xstate |= xstate_zmm;
4886 else if (i.tm.operand_types[j].bitfield.ymmword)
4887 i.xstate |= xstate_ymm;
4888 else if (i.tm.operand_types[j].bitfield.xmmword)
4889 i.xstate |= xstate_xmm;
4890 break;
4891 }
4892 }
4893
4894 /* Make still unresolved immediate matches conform to size of immediate
4895 given in i.suffix. */
4896 if (!finalize_imm ())
4897 return;
4898
4899 if (i.types[0].bitfield.imm1)
4900 i.imm_operands = 0; /* kludge for shift insns. */
4901
4902 /* We only need to check those implicit registers for instructions
4903 with 3 operands or less. */
4904 if (i.operands <= 3)
4905 for (j = 0; j < i.operands; j++)
4906 if (i.types[j].bitfield.instance != InstanceNone
4907 && !i.types[j].bitfield.xmmword)
4908 i.reg_operands--;
4909
4910 /* For insns with operands there are more diddles to do to the opcode. */
4911 if (i.operands)
4912 {
4913 if (!process_operands ())
4914 return;
4915 }
4916 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4917 {
4918 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4919 as_warn (_("translating to `%sp'"), i.tm.name);
4920 }
4921
4922 if (is_any_vex_encoding (&i.tm))
4923 {
4924 if (!cpu_arch_flags.bitfield.cpui286)
4925 {
4926 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4927 i.tm.name);
4928 return;
4929 }
4930
4931 /* Check for explicit REX prefix. */
4932 if (i.prefix[REX_PREFIX] || i.rex_encoding)
4933 {
4934 as_bad (_("REX prefix invalid with `%s'"), i.tm.name);
4935 return;
4936 }
4937
4938 if (i.tm.opcode_modifier.vex)
4939 build_vex_prefix (t);
4940 else
4941 build_evex_prefix ();
4942
4943 /* The individual REX.RXBW bits got consumed. */
4944 i.rex &= REX_OPCODE;
4945 }
4946
4947 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4948 instructions may define INT_OPCODE as well, so avoid this corner
4949 case for those instructions that use MODRM. */
4950 if (i.tm.base_opcode == INT_OPCODE
4951 && !i.tm.opcode_modifier.modrm
4952 && i.op[0].imms->X_add_number == 3)
4953 {
4954 i.tm.base_opcode = INT3_OPCODE;
4955 i.imm_operands = 0;
4956 }
4957
4958 if ((i.tm.opcode_modifier.jump == JUMP
4959 || i.tm.opcode_modifier.jump == JUMP_BYTE
4960 || i.tm.opcode_modifier.jump == JUMP_DWORD)
4961 && i.op[0].disps->X_op == O_constant)
4962 {
4963 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4964 the absolute address given by the constant. Since ix86 jumps and
4965 calls are pc relative, we need to generate a reloc. */
4966 i.op[0].disps->X_add_symbol = &abs_symbol;
4967 i.op[0].disps->X_op = O_symbol;
4968 }
4969
4970 /* For 8 bit registers we need an empty rex prefix. Also if the
4971 instruction already has a prefix, we need to convert old
4972 registers to new ones. */
4973
4974 if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte
4975 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4976 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte
4977 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4978 || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte)
4979 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte))
4980 && i.rex != 0))
4981 {
4982 int x;
4983
4984 i.rex |= REX_OPCODE;
4985 for (x = 0; x < 2; x++)
4986 {
4987 /* Look for 8 bit operand that uses old registers. */
4988 if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4989 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4990 {
4991 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4992 /* In case it is "hi" register, give up. */
4993 if (i.op[x].regs->reg_num > 3)
4994 as_bad (_("can't encode register '%s%s' in an "
4995 "instruction requiring REX prefix."),
4996 register_prefix, i.op[x].regs->reg_name);
4997
4998 /* Otherwise it is equivalent to the extended register.
4999 Since the encoding doesn't change this is merely
5000 cosmetic cleanup for debug output. */
5001
5002 i.op[x].regs = i.op[x].regs + 8;
5003 }
5004 }
5005 }
5006
5007 if (i.rex == 0 && i.rex_encoding)
5008 {
5009 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5010 that uses legacy register. If it is "hi" register, don't add
5011 the REX_OPCODE byte. */
5012 int x;
5013 for (x = 0; x < 2; x++)
5014 if (i.types[x].bitfield.class == Reg
5015 && i.types[x].bitfield.byte
5016 && (i.op[x].regs->reg_flags & RegRex64) == 0
5017 && i.op[x].regs->reg_num > 3)
5018 {
5019 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
5020 i.rex_encoding = FALSE;
5021 break;
5022 }
5023
5024 if (i.rex_encoding)
5025 i.rex = REX_OPCODE;
5026 }
5027
5028 if (i.rex != 0)
5029 add_prefix (REX_OPCODE | i.rex);
5030
5031 insert_lfence_before ();
5032
5033 /* We are ready to output the insn. */
5034 output_insn ();
5035
5036 insert_lfence_after ();
5037
5038 last_insn.seg = now_seg;
5039
5040 if (i.tm.opcode_modifier.isprefix)
5041 {
5042 last_insn.kind = last_insn_prefix;
5043 last_insn.name = i.tm.name;
5044 last_insn.file = as_where (&last_insn.line);
5045 }
5046 else
5047 last_insn.kind = last_insn_other;
5048 }
5049
5050 static char *
5051 parse_insn (char *line, char *mnemonic)
5052 {
5053 char *l = line;
5054 char *token_start = l;
5055 char *mnem_p;
5056 int supported;
5057 const insn_template *t;
5058 char *dot_p = NULL;
5059
5060 while (1)
5061 {
5062 mnem_p = mnemonic;
5063 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
5064 {
5065 if (*mnem_p == '.')
5066 dot_p = mnem_p;
5067 mnem_p++;
5068 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
5069 {
5070 as_bad (_("no such instruction: `%s'"), token_start);
5071 return NULL;
5072 }
5073 l++;
5074 }
5075 if (!is_space_char (*l)
5076 && *l != END_OF_INSN
5077 && (intel_syntax
5078 || (*l != PREFIX_SEPARATOR
5079 && *l != ',')))
5080 {
5081 as_bad (_("invalid character %s in mnemonic"),
5082 output_invalid (*l));
5083 return NULL;
5084 }
5085 if (token_start == l)
5086 {
5087 if (!intel_syntax && *l == PREFIX_SEPARATOR)
5088 as_bad (_("expecting prefix; got nothing"));
5089 else
5090 as_bad (_("expecting mnemonic; got nothing"));
5091 return NULL;
5092 }
5093
5094 /* Look up instruction (or prefix) via hash table. */
5095 current_templates = (const templates *) hash_find (op_hash, mnemonic);
5096
5097 if (*l != END_OF_INSN
5098 && (!is_space_char (*l) || l[1] != END_OF_INSN)
5099 && current_templates
5100 && current_templates->start->opcode_modifier.isprefix)
5101 {
5102 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
5103 {
5104 as_bad ((flag_code != CODE_64BIT
5105 ? _("`%s' is only supported in 64-bit mode")
5106 : _("`%s' is not supported in 64-bit mode")),
5107 current_templates->start->name);
5108 return NULL;
5109 }
5110 /* If we are in 16-bit mode, do not allow addr16 or data16.
5111 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5112 if ((current_templates->start->opcode_modifier.size == SIZE16
5113 || current_templates->start->opcode_modifier.size == SIZE32)
5114 && flag_code != CODE_64BIT
5115 && ((current_templates->start->opcode_modifier.size == SIZE32)
5116 ^ (flag_code == CODE_16BIT)))
5117 {
5118 as_bad (_("redundant %s prefix"),
5119 current_templates->start->name);
5120 return NULL;
5121 }
5122 if (current_templates->start->opcode_length == 0)
5123 {
5124 /* Handle pseudo prefixes. */
5125 switch (current_templates->start->base_opcode)
5126 {
5127 case 0x0:
5128 /* {disp8} */
5129 i.disp_encoding = disp_encoding_8bit;
5130 break;
5131 case 0x1:
5132 /* {disp32} */
5133 i.disp_encoding = disp_encoding_32bit;
5134 break;
5135 case 0x2:
5136 /* {load} */
5137 i.dir_encoding = dir_encoding_load;
5138 break;
5139 case 0x3:
5140 /* {store} */
5141 i.dir_encoding = dir_encoding_store;
5142 break;
5143 case 0x4:
5144 /* {vex} */
5145 i.vec_encoding = vex_encoding_vex;
5146 break;
5147 case 0x5:
5148 /* {vex3} */
5149 i.vec_encoding = vex_encoding_vex3;
5150 break;
5151 case 0x6:
5152 /* {evex} */
5153 i.vec_encoding = vex_encoding_evex;
5154 break;
5155 case 0x7:
5156 /* {rex} */
5157 i.rex_encoding = TRUE;
5158 break;
5159 case 0x8:
5160 /* {nooptimize} */
5161 i.no_optimize = TRUE;
5162 break;
5163 default:
5164 abort ();
5165 }
5166 }
5167 else
5168 {
5169 /* Add prefix, checking for repeated prefixes. */
5170 switch (add_prefix (current_templates->start->base_opcode))
5171 {
5172 case PREFIX_EXIST:
5173 return NULL;
5174 case PREFIX_DS:
5175 if (current_templates->start->cpu_flags.bitfield.cpuibt)
5176 i.notrack_prefix = current_templates->start->name;
5177 break;
5178 case PREFIX_REP:
5179 if (current_templates->start->cpu_flags.bitfield.cpuhle)
5180 i.hle_prefix = current_templates->start->name;
5181 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
5182 i.bnd_prefix = current_templates->start->name;
5183 else
5184 i.rep_prefix = current_templates->start->name;
5185 break;
5186 default:
5187 break;
5188 }
5189 }
5190 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5191 token_start = ++l;
5192 }
5193 else
5194 break;
5195 }
5196
5197 if (!current_templates)
5198 {
5199 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5200 Check if we should swap operand or force 32bit displacement in
5201 encoding. */
5202 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
5203 i.dir_encoding = dir_encoding_swap;
5204 else if (mnem_p - 3 == dot_p
5205 && dot_p[1] == 'd'
5206 && dot_p[2] == '8')
5207 i.disp_encoding = disp_encoding_8bit;
5208 else if (mnem_p - 4 == dot_p
5209 && dot_p[1] == 'd'
5210 && dot_p[2] == '3'
5211 && dot_p[3] == '2')
5212 i.disp_encoding = disp_encoding_32bit;
5213 else
5214 goto check_suffix;
5215 mnem_p = dot_p;
5216 *dot_p = '\0';
5217 current_templates = (const templates *) hash_find (op_hash, mnemonic);
5218 }
5219
5220 if (!current_templates)
5221 {
5222 check_suffix:
5223 if (mnem_p > mnemonic)
5224 {
5225 /* See if we can get a match by trimming off a suffix. */
5226 switch (mnem_p[-1])
5227 {
5228 case WORD_MNEM_SUFFIX:
5229 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
5230 i.suffix = SHORT_MNEM_SUFFIX;
5231 else
5232 /* Fall through. */
5233 case BYTE_MNEM_SUFFIX:
5234 case QWORD_MNEM_SUFFIX:
5235 i.suffix = mnem_p[-1];
5236 mnem_p[-1] = '\0';
5237 current_templates = (const templates *) hash_find (op_hash,
5238 mnemonic);
5239 break;
5240 case SHORT_MNEM_SUFFIX:
5241 case LONG_MNEM_SUFFIX:
5242 if (!intel_syntax)
5243 {
5244 i.suffix = mnem_p[-1];
5245 mnem_p[-1] = '\0';
5246 current_templates = (const templates *) hash_find (op_hash,
5247 mnemonic);
5248 }
5249 break;
5250
5251 /* Intel Syntax. */
5252 case 'd':
5253 if (intel_syntax)
5254 {
5255 if (intel_float_operand (mnemonic) == 1)
5256 i.suffix = SHORT_MNEM_SUFFIX;
5257 else
5258 i.suffix = LONG_MNEM_SUFFIX;
5259 mnem_p[-1] = '\0';
5260 current_templates = (const templates *) hash_find (op_hash,
5261 mnemonic);
5262 }
5263 break;
5264 }
5265 }
5266
5267 if (!current_templates)
5268 {
5269 as_bad (_("no such instruction: `%s'"), token_start);
5270 return NULL;
5271 }
5272 }
5273
5274 if (current_templates->start->opcode_modifier.jump == JUMP
5275 || current_templates->start->opcode_modifier.jump == JUMP_BYTE)
5276 {
5277 /* Check for a branch hint. We allow ",pt" and ",pn" for
5278 predict taken and predict not taken respectively.
5279 I'm not sure that branch hints actually do anything on loop
5280 and jcxz insns (JumpByte) for current Pentium4 chips. They
5281 may work in the future and it doesn't hurt to accept them
5282 now. */
5283 if (l[0] == ',' && l[1] == 'p')
5284 {
5285 if (l[2] == 't')
5286 {
5287 if (!add_prefix (DS_PREFIX_OPCODE))
5288 return NULL;
5289 l += 3;
5290 }
5291 else if (l[2] == 'n')
5292 {
5293 if (!add_prefix (CS_PREFIX_OPCODE))
5294 return NULL;
5295 l += 3;
5296 }
5297 }
5298 }
5299 /* Any other comma loses. */
5300 if (*l == ',')
5301 {
5302 as_bad (_("invalid character %s in mnemonic"),
5303 output_invalid (*l));
5304 return NULL;
5305 }
5306
5307 /* Check if instruction is supported on specified architecture. */
5308 supported = 0;
5309 for (t = current_templates->start; t < current_templates->end; ++t)
5310 {
5311 supported |= cpu_flags_match (t);
5312 if (supported == CPU_FLAGS_PERFECT_MATCH)
5313 {
5314 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
5315 as_warn (_("use .code16 to ensure correct addressing mode"));
5316
5317 return l;
5318 }
5319 }
5320
5321 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5322 as_bad (flag_code == CODE_64BIT
5323 ? _("`%s' is not supported in 64-bit mode")
5324 : _("`%s' is only supported in 64-bit mode"),
5325 current_templates->start->name);
5326 else
5327 as_bad (_("`%s' is not supported on `%s%s'"),
5328 current_templates->start->name,
5329 cpu_arch_name ? cpu_arch_name : default_arch,
5330 cpu_sub_arch_name ? cpu_sub_arch_name : "");
5331
5332 return NULL;
5333 }
5334
5335 static char *
5336 parse_operands (char *l, const char *mnemonic)
5337 {
5338 char *token_start;
5339
5340 /* 1 if operand is pending after ','. */
5341 unsigned int expecting_operand = 0;
5342
5343 /* Non-zero if operand parens not balanced. */
5344 unsigned int paren_not_balanced;
5345
5346 while (*l != END_OF_INSN)
5347 {
5348 /* Skip optional white space before operand. */
5349 if (is_space_char (*l))
5350 ++l;
5351 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
5352 {
5353 as_bad (_("invalid character %s before operand %d"),
5354 output_invalid (*l),
5355 i.operands + 1);
5356 return NULL;
5357 }
5358 token_start = l; /* After white space. */
5359 paren_not_balanced = 0;
5360 while (paren_not_balanced || *l != ',')
5361 {
5362 if (*l == END_OF_INSN)
5363 {
5364 if (paren_not_balanced)
5365 {
5366 if (!intel_syntax)
5367 as_bad (_("unbalanced parenthesis in operand %d."),
5368 i.operands + 1);
5369 else
5370 as_bad (_("unbalanced brackets in operand %d."),
5371 i.operands + 1);
5372 return NULL;
5373 }
5374 else
5375 break; /* we are done */
5376 }
5377 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
5378 {
5379 as_bad (_("invalid character %s in operand %d"),
5380 output_invalid (*l),
5381 i.operands + 1);
5382 return NULL;
5383 }
5384 if (!intel_syntax)
5385 {
5386 if (*l == '(')
5387 ++paren_not_balanced;
5388 if (*l == ')')
5389 --paren_not_balanced;
5390 }
5391 else
5392 {
5393 if (*l == '[')
5394 ++paren_not_balanced;
5395 if (*l == ']')
5396 --paren_not_balanced;
5397 }
5398 l++;
5399 }
5400 if (l != token_start)
5401 { /* Yes, we've read in another operand. */
5402 unsigned int operand_ok;
5403 this_operand = i.operands++;
5404 if (i.operands > MAX_OPERANDS)
5405 {
5406 as_bad (_("spurious operands; (%d operands/instruction max)"),
5407 MAX_OPERANDS);
5408 return NULL;
5409 }
5410 i.types[this_operand].bitfield.unspecified = 1;
5411 /* Now parse operand adding info to 'i' as we go along. */
5412 END_STRING_AND_SAVE (l);
5413
5414 if (i.mem_operands > 1)
5415 {
5416 as_bad (_("too many memory references for `%s'"),
5417 mnemonic);
5418 return 0;
5419 }
5420
5421 if (intel_syntax)
5422 operand_ok =
5423 i386_intel_operand (token_start,
5424 intel_float_operand (mnemonic));
5425 else
5426 operand_ok = i386_att_operand (token_start);
5427
5428 RESTORE_END_STRING (l);
5429 if (!operand_ok)
5430 return NULL;
5431 }
5432 else
5433 {
5434 if (expecting_operand)
5435 {
5436 expecting_operand_after_comma:
5437 as_bad (_("expecting operand after ','; got nothing"));
5438 return NULL;
5439 }
5440 if (*l == ',')
5441 {
5442 as_bad (_("expecting operand before ','; got nothing"));
5443 return NULL;
5444 }
5445 }
5446
5447 /* Now *l must be either ',' or END_OF_INSN. */
5448 if (*l == ',')
5449 {
5450 if (*++l == END_OF_INSN)
5451 {
5452 /* Just skip it, if it's \n complain. */
5453 goto expecting_operand_after_comma;
5454 }
5455 expecting_operand = 1;
5456 }
5457 }
5458 return l;
5459 }
5460
5461 static void
5462 swap_2_operands (int xchg1, int xchg2)
5463 {
5464 union i386_op temp_op;
5465 i386_operand_type temp_type;
5466 unsigned int temp_flags;
5467 enum bfd_reloc_code_real temp_reloc;
5468
5469 temp_type = i.types[xchg2];
5470 i.types[xchg2] = i.types[xchg1];
5471 i.types[xchg1] = temp_type;
5472
5473 temp_flags = i.flags[xchg2];
5474 i.flags[xchg2] = i.flags[xchg1];
5475 i.flags[xchg1] = temp_flags;
5476
5477 temp_op = i.op[xchg2];
5478 i.op[xchg2] = i.op[xchg1];
5479 i.op[xchg1] = temp_op;
5480
5481 temp_reloc = i.reloc[xchg2];
5482 i.reloc[xchg2] = i.reloc[xchg1];
5483 i.reloc[xchg1] = temp_reloc;
5484
5485 if (i.mask)
5486 {
5487 if (i.mask->operand == xchg1)
5488 i.mask->operand = xchg2;
5489 else if (i.mask->operand == xchg2)
5490 i.mask->operand = xchg1;
5491 }
5492 if (i.broadcast)
5493 {
5494 if (i.broadcast->operand == xchg1)
5495 i.broadcast->operand = xchg2;
5496 else if (i.broadcast->operand == xchg2)
5497 i.broadcast->operand = xchg1;
5498 }
5499 if (i.rounding)
5500 {
5501 if (i.rounding->operand == xchg1)
5502 i.rounding->operand = xchg2;
5503 else if (i.rounding->operand == xchg2)
5504 i.rounding->operand = xchg1;
5505 }
5506 }
5507
5508 static void
5509 swap_operands (void)
5510 {
5511 switch (i.operands)
5512 {
5513 case 5:
5514 case 4:
5515 swap_2_operands (1, i.operands - 2);
5516 /* Fall through. */
5517 case 3:
5518 case 2:
5519 swap_2_operands (0, i.operands - 1);
5520 break;
5521 default:
5522 abort ();
5523 }
5524
5525 if (i.mem_operands == 2)
5526 {
5527 const seg_entry *temp_seg;
5528 temp_seg = i.seg[0];
5529 i.seg[0] = i.seg[1];
5530 i.seg[1] = temp_seg;
5531 }
5532 }
5533
5534 /* Try to ensure constant immediates are represented in the smallest
5535 opcode possible. */
5536 static void
5537 optimize_imm (void)
5538 {
5539 char guess_suffix = 0;
5540 int op;
5541
5542 if (i.suffix)
5543 guess_suffix = i.suffix;
5544 else if (i.reg_operands)
5545 {
5546 /* Figure out a suffix from the last register operand specified.
5547 We can't do this properly yet, i.e. excluding special register
5548 instances, but the following works for instructions with
5549 immediates. In any case, we can't set i.suffix yet. */
5550 for (op = i.operands; --op >= 0;)
5551 if (i.types[op].bitfield.class != Reg)
5552 continue;
5553 else if (i.types[op].bitfield.byte)
5554 {
5555 guess_suffix = BYTE_MNEM_SUFFIX;
5556 break;
5557 }
5558 else if (i.types[op].bitfield.word)
5559 {
5560 guess_suffix = WORD_MNEM_SUFFIX;
5561 break;
5562 }
5563 else if (i.types[op].bitfield.dword)
5564 {
5565 guess_suffix = LONG_MNEM_SUFFIX;
5566 break;
5567 }
5568 else if (i.types[op].bitfield.qword)
5569 {
5570 guess_suffix = QWORD_MNEM_SUFFIX;
5571 break;
5572 }
5573 }
5574 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5575 guess_suffix = WORD_MNEM_SUFFIX;
5576
5577 for (op = i.operands; --op >= 0;)
5578 if (operand_type_check (i.types[op], imm))
5579 {
5580 switch (i.op[op].imms->X_op)
5581 {
5582 case O_constant:
5583 /* If a suffix is given, this operand may be shortened. */
5584 switch (guess_suffix)
5585 {
5586 case LONG_MNEM_SUFFIX:
5587 i.types[op].bitfield.imm32 = 1;
5588 i.types[op].bitfield.imm64 = 1;
5589 break;
5590 case WORD_MNEM_SUFFIX:
5591 i.types[op].bitfield.imm16 = 1;
5592 i.types[op].bitfield.imm32 = 1;
5593 i.types[op].bitfield.imm32s = 1;
5594 i.types[op].bitfield.imm64 = 1;
5595 break;
5596 case BYTE_MNEM_SUFFIX:
5597 i.types[op].bitfield.imm8 = 1;
5598 i.types[op].bitfield.imm8s = 1;
5599 i.types[op].bitfield.imm16 = 1;
5600 i.types[op].bitfield.imm32 = 1;
5601 i.types[op].bitfield.imm32s = 1;
5602 i.types[op].bitfield.imm64 = 1;
5603 break;
5604 }
5605
5606 /* If this operand is at most 16 bits, convert it
5607 to a signed 16 bit number before trying to see
5608 whether it will fit in an even smaller size.
5609 This allows a 16-bit operand such as $0xffe0 to
5610 be recognised as within Imm8S range. */
5611 if ((i.types[op].bitfield.imm16)
5612 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
5613 {
5614 i.op[op].imms->X_add_number =
5615 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
5616 }
5617 #ifdef BFD64
5618 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5619 if ((i.types[op].bitfield.imm32)
5620 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
5621 == 0))
5622 {
5623 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
5624 ^ ((offsetT) 1 << 31))
5625 - ((offsetT) 1 << 31));
5626 }
5627 #endif
5628 i.types[op]
5629 = operand_type_or (i.types[op],
5630 smallest_imm_type (i.op[op].imms->X_add_number));
5631
5632 /* We must avoid matching of Imm32 templates when 64bit
5633 only immediate is available. */
5634 if (guess_suffix == QWORD_MNEM_SUFFIX)
5635 i.types[op].bitfield.imm32 = 0;
5636 break;
5637
5638 case O_absent:
5639 case O_register:
5640 abort ();
5641
5642 /* Symbols and expressions. */
5643 default:
5644 /* Convert symbolic operand to proper sizes for matching, but don't
5645 prevent matching a set of insns that only supports sizes other
5646 than those matching the insn suffix. */
5647 {
5648 i386_operand_type mask, allowed;
5649 const insn_template *t;
5650
5651 operand_type_set (&mask, 0);
5652 operand_type_set (&allowed, 0);
5653
5654 for (t = current_templates->start;
5655 t < current_templates->end;
5656 ++t)
5657 {
5658 allowed = operand_type_or (allowed, t->operand_types[op]);
5659 allowed = operand_type_and (allowed, anyimm);
5660 }
5661 switch (guess_suffix)
5662 {
5663 case QWORD_MNEM_SUFFIX:
5664 mask.bitfield.imm64 = 1;
5665 mask.bitfield.imm32s = 1;
5666 break;
5667 case LONG_MNEM_SUFFIX:
5668 mask.bitfield.imm32 = 1;
5669 break;
5670 case WORD_MNEM_SUFFIX:
5671 mask.bitfield.imm16 = 1;
5672 break;
5673 case BYTE_MNEM_SUFFIX:
5674 mask.bitfield.imm8 = 1;
5675 break;
5676 default:
5677 break;
5678 }
5679 allowed = operand_type_and (mask, allowed);
5680 if (!operand_type_all_zero (&allowed))
5681 i.types[op] = operand_type_and (i.types[op], mask);
5682 }
5683 break;
5684 }
5685 }
5686 }
5687
5688 /* Try to use the smallest displacement type too. */
5689 static void
5690 optimize_disp (void)
5691 {
5692 int op;
5693
5694 for (op = i.operands; --op >= 0;)
5695 if (operand_type_check (i.types[op], disp))
5696 {
5697 if (i.op[op].disps->X_op == O_constant)
5698 {
5699 offsetT op_disp = i.op[op].disps->X_add_number;
5700
5701 if (i.types[op].bitfield.disp16
5702 && (op_disp & ~(offsetT) 0xffff) == 0)
5703 {
5704 /* If this operand is at most 16 bits, convert
5705 to a signed 16 bit number and don't use 64bit
5706 displacement. */
5707 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5708 i.types[op].bitfield.disp64 = 0;
5709 }
5710 #ifdef BFD64
5711 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5712 if (i.types[op].bitfield.disp32
5713 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5714 {
5715 /* If this operand is at most 32 bits, convert
5716 to a signed 32 bit number and don't use 64bit
5717 displacement. */
5718 op_disp &= (((offsetT) 2 << 31) - 1);
5719 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5720 i.types[op].bitfield.disp64 = 0;
5721 }
5722 #endif
5723 if (!op_disp && i.types[op].bitfield.baseindex)
5724 {
5725 i.types[op].bitfield.disp8 = 0;
5726 i.types[op].bitfield.disp16 = 0;
5727 i.types[op].bitfield.disp32 = 0;
5728 i.types[op].bitfield.disp32s = 0;
5729 i.types[op].bitfield.disp64 = 0;
5730 i.op[op].disps = 0;
5731 i.disp_operands--;
5732 }
5733 else if (flag_code == CODE_64BIT)
5734 {
5735 if (fits_in_signed_long (op_disp))
5736 {
5737 i.types[op].bitfield.disp64 = 0;
5738 i.types[op].bitfield.disp32s = 1;
5739 }
5740 if (i.prefix[ADDR_PREFIX]
5741 && fits_in_unsigned_long (op_disp))
5742 i.types[op].bitfield.disp32 = 1;
5743 }
5744 if ((i.types[op].bitfield.disp32
5745 || i.types[op].bitfield.disp32s
5746 || i.types[op].bitfield.disp16)
5747 && fits_in_disp8 (op_disp))
5748 i.types[op].bitfield.disp8 = 1;
5749 }
5750 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5751 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5752 {
5753 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5754 i.op[op].disps, 0, i.reloc[op]);
5755 i.types[op].bitfield.disp8 = 0;
5756 i.types[op].bitfield.disp16 = 0;
5757 i.types[op].bitfield.disp32 = 0;
5758 i.types[op].bitfield.disp32s = 0;
5759 i.types[op].bitfield.disp64 = 0;
5760 }
5761 else
5762 /* We only support 64bit displacement on constants. */
5763 i.types[op].bitfield.disp64 = 0;
5764 }
5765 }
5766
5767 /* Return 1 if there is a match in broadcast bytes between operand
5768 GIVEN and instruction template T. */
5769
5770 static INLINE int
5771 match_broadcast_size (const insn_template *t, unsigned int given)
5772 {
5773 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5774 && i.types[given].bitfield.byte)
5775 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5776 && i.types[given].bitfield.word)
5777 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5778 && i.types[given].bitfield.dword)
5779 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5780 && i.types[given].bitfield.qword));
5781 }
5782
5783 /* Check if operands are valid for the instruction. */
5784
5785 static int
5786 check_VecOperands (const insn_template *t)
5787 {
5788 unsigned int op;
5789 i386_cpu_flags cpu;
5790
5791 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5792 any one operand are implicity requiring AVX512VL support if the actual
5793 operand size is YMMword or XMMword. Since this function runs after
5794 template matching, there's no need to check for YMMword/XMMword in
5795 the template. */
5796 cpu = cpu_flags_and (t->cpu_flags, avx512);
5797 if (!cpu_flags_all_zero (&cpu)
5798 && !t->cpu_flags.bitfield.cpuavx512vl
5799 && !cpu_arch_flags.bitfield.cpuavx512vl)
5800 {
5801 for (op = 0; op < t->operands; ++op)
5802 {
5803 if (t->operand_types[op].bitfield.zmmword
5804 && (i.types[op].bitfield.ymmword
5805 || i.types[op].bitfield.xmmword))
5806 {
5807 i.error = unsupported;
5808 return 1;
5809 }
5810 }
5811 }
5812
5813 /* Without VSIB byte, we can't have a vector register for index. */
5814 if (!t->opcode_modifier.sib
5815 && i.index_reg
5816 && (i.index_reg->reg_type.bitfield.xmmword
5817 || i.index_reg->reg_type.bitfield.ymmword
5818 || i.index_reg->reg_type.bitfield.zmmword))
5819 {
5820 i.error = unsupported_vector_index_register;
5821 return 1;
5822 }
5823
5824 /* Check if default mask is allowed. */
5825 if (t->opcode_modifier.nodefmask
5826 && (!i.mask || i.mask->mask->reg_num == 0))
5827 {
5828 i.error = no_default_mask;
5829 return 1;
5830 }
5831
5832 /* For VSIB byte, we need a vector register for index, and all vector
5833 registers must be distinct. */
5834 if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM)
5835 {
5836 if (!i.index_reg
5837 || !((t->opcode_modifier.sib == VECSIB128
5838 && i.index_reg->reg_type.bitfield.xmmword)
5839 || (t->opcode_modifier.sib == VECSIB256
5840 && i.index_reg->reg_type.bitfield.ymmword)
5841 || (t->opcode_modifier.sib == VECSIB512
5842 && i.index_reg->reg_type.bitfield.zmmword)))
5843 {
5844 i.error = invalid_vsib_address;
5845 return 1;
5846 }
5847
5848 gas_assert (i.reg_operands == 2 || i.mask);
5849 if (i.reg_operands == 2 && !i.mask)
5850 {
5851 gas_assert (i.types[0].bitfield.class == RegSIMD);
5852 gas_assert (i.types[0].bitfield.xmmword
5853 || i.types[0].bitfield.ymmword);
5854 gas_assert (i.types[2].bitfield.class == RegSIMD);
5855 gas_assert (i.types[2].bitfield.xmmword
5856 || i.types[2].bitfield.ymmword);
5857 if (operand_check == check_none)
5858 return 0;
5859 if (register_number (i.op[0].regs)
5860 != register_number (i.index_reg)
5861 && register_number (i.op[2].regs)
5862 != register_number (i.index_reg)
5863 && register_number (i.op[0].regs)
5864 != register_number (i.op[2].regs))
5865 return 0;
5866 if (operand_check == check_error)
5867 {
5868 i.error = invalid_vector_register_set;
5869 return 1;
5870 }
5871 as_warn (_("mask, index, and destination registers should be distinct"));
5872 }
5873 else if (i.reg_operands == 1 && i.mask)
5874 {
5875 if (i.types[1].bitfield.class == RegSIMD
5876 && (i.types[1].bitfield.xmmword
5877 || i.types[1].bitfield.ymmword
5878 || i.types[1].bitfield.zmmword)
5879 && (register_number (i.op[1].regs)
5880 == register_number (i.index_reg)))
5881 {
5882 if (operand_check == check_error)
5883 {
5884 i.error = invalid_vector_register_set;
5885 return 1;
5886 }
5887 if (operand_check != check_none)
5888 as_warn (_("index and destination registers should be distinct"));
5889 }
5890 }
5891 }
5892
5893 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5894 distinct */
5895 if (t->operand_types[0].bitfield.tmmword
5896 && i.reg_operands == 3)
5897 {
5898 if (register_number (i.op[0].regs)
5899 == register_number (i.op[1].regs)
5900 || register_number (i.op[0].regs)
5901 == register_number (i.op[2].regs)
5902 || register_number (i.op[1].regs)
5903 == register_number (i.op[2].regs))
5904 {
5905 i.error = invalid_tmm_register_set;
5906 return 1;
5907 }
5908 }
5909
5910 /* Check if broadcast is supported by the instruction and is applied
5911 to the memory operand. */
5912 if (i.broadcast)
5913 {
5914 i386_operand_type type, overlap;
5915
5916 /* Check if specified broadcast is supported in this instruction,
5917 and its broadcast bytes match the memory operand. */
5918 op = i.broadcast->operand;
5919 if (!t->opcode_modifier.broadcast
5920 || !(i.flags[op] & Operand_Mem)
5921 || (!i.types[op].bitfield.unspecified
5922 && !match_broadcast_size (t, op)))
5923 {
5924 bad_broadcast:
5925 i.error = unsupported_broadcast;
5926 return 1;
5927 }
5928
5929 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5930 * i.broadcast->type);
5931 operand_type_set (&type, 0);
5932 switch (i.broadcast->bytes)
5933 {
5934 case 2:
5935 type.bitfield.word = 1;
5936 break;
5937 case 4:
5938 type.bitfield.dword = 1;
5939 break;
5940 case 8:
5941 type.bitfield.qword = 1;
5942 break;
5943 case 16:
5944 type.bitfield.xmmword = 1;
5945 break;
5946 case 32:
5947 type.bitfield.ymmword = 1;
5948 break;
5949 case 64:
5950 type.bitfield.zmmword = 1;
5951 break;
5952 default:
5953 goto bad_broadcast;
5954 }
5955
5956 overlap = operand_type_and (type, t->operand_types[op]);
5957 if (t->operand_types[op].bitfield.class == RegSIMD
5958 && t->operand_types[op].bitfield.byte
5959 + t->operand_types[op].bitfield.word
5960 + t->operand_types[op].bitfield.dword
5961 + t->operand_types[op].bitfield.qword > 1)
5962 {
5963 overlap.bitfield.xmmword = 0;
5964 overlap.bitfield.ymmword = 0;
5965 overlap.bitfield.zmmword = 0;
5966 }
5967 if (operand_type_all_zero (&overlap))
5968 goto bad_broadcast;
5969
5970 if (t->opcode_modifier.checkregsize)
5971 {
5972 unsigned int j;
5973
5974 type.bitfield.baseindex = 1;
5975 for (j = 0; j < i.operands; ++j)
5976 {
5977 if (j != op
5978 && !operand_type_register_match(i.types[j],
5979 t->operand_types[j],
5980 type,
5981 t->operand_types[op]))
5982 goto bad_broadcast;
5983 }
5984 }
5985 }
5986 /* If broadcast is supported in this instruction, we need to check if
5987 operand of one-element size isn't specified without broadcast. */
5988 else if (t->opcode_modifier.broadcast && i.mem_operands)
5989 {
5990 /* Find memory operand. */
5991 for (op = 0; op < i.operands; op++)
5992 if (i.flags[op] & Operand_Mem)
5993 break;
5994 gas_assert (op < i.operands);
5995 /* Check size of the memory operand. */
5996 if (match_broadcast_size (t, op))
5997 {
5998 i.error = broadcast_needed;
5999 return 1;
6000 }
6001 }
6002 else
6003 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
6004
6005 /* Check if requested masking is supported. */
6006 if (i.mask)
6007 {
6008 switch (t->opcode_modifier.masking)
6009 {
6010 case BOTH_MASKING:
6011 break;
6012 case MERGING_MASKING:
6013 if (i.mask->zeroing)
6014 {
6015 case 0:
6016 i.error = unsupported_masking;
6017 return 1;
6018 }
6019 break;
6020 case DYNAMIC_MASKING:
6021 /* Memory destinations allow only merging masking. */
6022 if (i.mask->zeroing && i.mem_operands)
6023 {
6024 /* Find memory operand. */
6025 for (op = 0; op < i.operands; op++)
6026 if (i.flags[op] & Operand_Mem)
6027 break;
6028 gas_assert (op < i.operands);
6029 if (op == i.operands - 1)
6030 {
6031 i.error = unsupported_masking;
6032 return 1;
6033 }
6034 }
6035 break;
6036 default:
6037 abort ();
6038 }
6039 }
6040
6041 /* Check if masking is applied to dest operand. */
6042 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
6043 {
6044 i.error = mask_not_on_destination;
6045 return 1;
6046 }
6047
6048 /* Check RC/SAE. */
6049 if (i.rounding)
6050 {
6051 if (!t->opcode_modifier.sae
6052 || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding))
6053 {
6054 i.error = unsupported_rc_sae;
6055 return 1;
6056 }
6057 /* If the instruction has several immediate operands and one of
6058 them is rounding, the rounding operand should be the last
6059 immediate operand. */
6060 if (i.imm_operands > 1
6061 && i.rounding->operand != (int) (i.imm_operands - 1))
6062 {
6063 i.error = rc_sae_operand_not_last_imm;
6064 return 1;
6065 }
6066 }
6067
6068 /* Check the special Imm4 cases; must be the first operand. */
6069 if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
6070 {
6071 if (i.op[0].imms->X_op != O_constant
6072 || !fits_in_imm4 (i.op[0].imms->X_add_number))
6073 {
6074 i.error = bad_imm4;
6075 return 1;
6076 }
6077
6078 /* Turn off Imm<N> so that update_imm won't complain. */
6079 operand_type_set (&i.types[0], 0);
6080 }
6081
6082 /* Check vector Disp8 operand. */
6083 if (t->opcode_modifier.disp8memshift
6084 && i.disp_encoding != disp_encoding_32bit)
6085 {
6086 if (i.broadcast)
6087 i.memshift = t->opcode_modifier.broadcast - 1;
6088 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
6089 i.memshift = t->opcode_modifier.disp8memshift;
6090 else
6091 {
6092 const i386_operand_type *type = NULL;
6093
6094 i.memshift = 0;
6095 for (op = 0; op < i.operands; op++)
6096 if (i.flags[op] & Operand_Mem)
6097 {
6098 if (t->opcode_modifier.evex == EVEXLIG)
6099 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
6100 else if (t->operand_types[op].bitfield.xmmword
6101 + t->operand_types[op].bitfield.ymmword
6102 + t->operand_types[op].bitfield.zmmword <= 1)
6103 type = &t->operand_types[op];
6104 else if (!i.types[op].bitfield.unspecified)
6105 type = &i.types[op];
6106 }
6107 else if (i.types[op].bitfield.class == RegSIMD
6108 && t->opcode_modifier.evex != EVEXLIG)
6109 {
6110 if (i.types[op].bitfield.zmmword)
6111 i.memshift = 6;
6112 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
6113 i.memshift = 5;
6114 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
6115 i.memshift = 4;
6116 }
6117
6118 if (type)
6119 {
6120 if (type->bitfield.zmmword)
6121 i.memshift = 6;
6122 else if (type->bitfield.ymmword)
6123 i.memshift = 5;
6124 else if (type->bitfield.xmmword)
6125 i.memshift = 4;
6126 }
6127
6128 /* For the check in fits_in_disp8(). */
6129 if (i.memshift == 0)
6130 i.memshift = -1;
6131 }
6132
6133 for (op = 0; op < i.operands; op++)
6134 if (operand_type_check (i.types[op], disp)
6135 && i.op[op].disps->X_op == O_constant)
6136 {
6137 if (fits_in_disp8 (i.op[op].disps->X_add_number))
6138 {
6139 i.types[op].bitfield.disp8 = 1;
6140 return 0;
6141 }
6142 i.types[op].bitfield.disp8 = 0;
6143 }
6144 }
6145
6146 i.memshift = 0;
6147
6148 return 0;
6149 }
6150
6151 /* Check if encoding requirements are met by the instruction. */
6152
6153 static int
6154 VEX_check_encoding (const insn_template *t)
6155 {
6156 if (i.vec_encoding == vex_encoding_error)
6157 {
6158 i.error = unsupported;
6159 return 1;
6160 }
6161
6162 if (i.vec_encoding == vex_encoding_evex)
6163 {
6164 /* This instruction must be encoded with EVEX prefix. */
6165 if (!is_evex_encoding (t))
6166 {
6167 i.error = unsupported;
6168 return 1;
6169 }
6170 return 0;
6171 }
6172
6173 if (!t->opcode_modifier.vex)
6174 {
6175 /* This instruction template doesn't have VEX prefix. */
6176 if (i.vec_encoding != vex_encoding_default)
6177 {
6178 i.error = unsupported;
6179 return 1;
6180 }
6181 return 0;
6182 }
6183
6184 return 0;
6185 }
6186
6187 static const insn_template *
6188 match_template (char mnem_suffix)
6189 {
6190 /* Points to template once we've found it. */
6191 const insn_template *t;
6192 i386_operand_type overlap0, overlap1, overlap2, overlap3;
6193 i386_operand_type overlap4;
6194 unsigned int found_reverse_match;
6195 i386_opcode_modifier suffix_check;
6196 i386_operand_type operand_types [MAX_OPERANDS];
6197 int addr_prefix_disp;
6198 unsigned int j, size_match, check_register;
6199 enum i386_error specific_error = 0;
6200
6201 #if MAX_OPERANDS != 5
6202 # error "MAX_OPERANDS must be 5."
6203 #endif
6204
6205 found_reverse_match = 0;
6206 addr_prefix_disp = -1;
6207
6208 /* Prepare for mnemonic suffix check. */
6209 memset (&suffix_check, 0, sizeof (suffix_check));
6210 switch (mnem_suffix)
6211 {
6212 case BYTE_MNEM_SUFFIX:
6213 suffix_check.no_bsuf = 1;
6214 break;
6215 case WORD_MNEM_SUFFIX:
6216 suffix_check.no_wsuf = 1;
6217 break;
6218 case SHORT_MNEM_SUFFIX:
6219 suffix_check.no_ssuf = 1;
6220 break;
6221 case LONG_MNEM_SUFFIX:
6222 suffix_check.no_lsuf = 1;
6223 break;
6224 case QWORD_MNEM_SUFFIX:
6225 suffix_check.no_qsuf = 1;
6226 break;
6227 default:
6228 /* NB: In Intel syntax, normally we can check for memory operand
6229 size when there is no mnemonic suffix. But jmp and call have
6230 2 different encodings with Dword memory operand size, one with
6231 No_ldSuf and the other without. i.suffix is set to
6232 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6233 if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
6234 suffix_check.no_ldsuf = 1;
6235 }
6236
6237 /* Must have right number of operands. */
6238 i.error = number_of_operands_mismatch;
6239
6240 for (t = current_templates->start; t < current_templates->end; t++)
6241 {
6242 addr_prefix_disp = -1;
6243 found_reverse_match = 0;
6244
6245 if (i.operands != t->operands)
6246 continue;
6247
6248 /* Check processor support. */
6249 i.error = unsupported;
6250 if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
6251 continue;
6252
6253 /* Check AT&T mnemonic. */
6254 i.error = unsupported_with_intel_mnemonic;
6255 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
6256 continue;
6257
6258 /* Check AT&T/Intel syntax. */
6259 i.error = unsupported_syntax;
6260 if ((intel_syntax && t->opcode_modifier.attsyntax)
6261 || (!intel_syntax && t->opcode_modifier.intelsyntax))
6262 continue;
6263
6264 /* Check Intel64/AMD64 ISA. */
6265 switch (isa64)
6266 {
6267 default:
6268 /* Default: Don't accept Intel64. */
6269 if (t->opcode_modifier.isa64 == INTEL64)
6270 continue;
6271 break;
6272 case amd64:
6273 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6274 if (t->opcode_modifier.isa64 >= INTEL64)
6275 continue;
6276 break;
6277 case intel64:
6278 /* -mintel64: Don't accept AMD64. */
6279 if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
6280 continue;
6281 break;
6282 }
6283
6284 /* Check the suffix. */
6285 i.error = invalid_instruction_suffix;
6286 if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
6287 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
6288 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
6289 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
6290 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
6291 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))
6292 continue;
6293
6294 size_match = operand_size_match (t);
6295 if (!size_match)
6296 continue;
6297
6298 /* This is intentionally not
6299
6300 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6301
6302 as the case of a missing * on the operand is accepted (perhaps with
6303 a warning, issued further down). */
6304 if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
6305 {
6306 i.error = operand_type_mismatch;
6307 continue;
6308 }
6309
6310 for (j = 0; j < MAX_OPERANDS; j++)
6311 operand_types[j] = t->operand_types[j];
6312
6313 /* In general, don't allow
6314 - 64-bit operands outside of 64-bit mode,
6315 - 32-bit operands on pre-386. */
6316 j = i.imm_operands + (t->operands > i.imm_operands + 1);
6317 if (((i.suffix == QWORD_MNEM_SUFFIX
6318 && flag_code != CODE_64BIT
6319 && (t->base_opcode != 0x0fc7
6320 || t->extension_opcode != 1 /* cmpxchg8b */))
6321 || (i.suffix == LONG_MNEM_SUFFIX
6322 && !cpu_arch_flags.bitfield.cpui386))
6323 && (intel_syntax
6324 ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
6325 && !intel_float_operand (t->name))
6326 : intel_float_operand (t->name) != 2)
6327 && (t->operands == i.imm_operands
6328 || (operand_types[i.imm_operands].bitfield.class != RegMMX
6329 && operand_types[i.imm_operands].bitfield.class != RegSIMD
6330 && operand_types[i.imm_operands].bitfield.class != RegMask)
6331 || (operand_types[j].bitfield.class != RegMMX
6332 && operand_types[j].bitfield.class != RegSIMD
6333 && operand_types[j].bitfield.class != RegMask))
6334 && !t->opcode_modifier.sib)
6335 continue;
6336
6337 /* Do not verify operands when there are none. */
6338 if (!t->operands)
6339 {
6340 if (VEX_check_encoding (t))
6341 {
6342 specific_error = i.error;
6343 continue;
6344 }
6345
6346 /* We've found a match; break out of loop. */
6347 break;
6348 }
6349
6350 if (!t->opcode_modifier.jump
6351 || t->opcode_modifier.jump == JUMP_ABSOLUTE)
6352 {
6353 /* There should be only one Disp operand. */
6354 for (j = 0; j < MAX_OPERANDS; j++)
6355 if (operand_type_check (operand_types[j], disp))
6356 break;
6357 if (j < MAX_OPERANDS)
6358 {
6359 bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
6360
6361 addr_prefix_disp = j;
6362
6363 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6364 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6365 switch (flag_code)
6366 {
6367 case CODE_16BIT:
6368 override = !override;
6369 /* Fall through. */
6370 case CODE_32BIT:
6371 if (operand_types[j].bitfield.disp32
6372 && operand_types[j].bitfield.disp16)
6373 {
6374 operand_types[j].bitfield.disp16 = override;
6375 operand_types[j].bitfield.disp32 = !override;
6376 }
6377 operand_types[j].bitfield.disp32s = 0;
6378 operand_types[j].bitfield.disp64 = 0;
6379 break;
6380
6381 case CODE_64BIT:
6382 if (operand_types[j].bitfield.disp32s
6383 || operand_types[j].bitfield.disp64)
6384 {
6385 operand_types[j].bitfield.disp64 &= !override;
6386 operand_types[j].bitfield.disp32s &= !override;
6387 operand_types[j].bitfield.disp32 = override;
6388 }
6389 operand_types[j].bitfield.disp16 = 0;
6390 break;
6391 }
6392 }
6393 }
6394
6395 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6396 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
6397 continue;
6398
6399 /* We check register size if needed. */
6400 if (t->opcode_modifier.checkregsize)
6401 {
6402 check_register = (1 << t->operands) - 1;
6403 if (i.broadcast)
6404 check_register &= ~(1 << i.broadcast->operand);
6405 }
6406 else
6407 check_register = 0;
6408
6409 overlap0 = operand_type_and (i.types[0], operand_types[0]);
6410 switch (t->operands)
6411 {
6412 case 1:
6413 if (!operand_type_match (overlap0, i.types[0]))
6414 continue;
6415 break;
6416 case 2:
6417 /* xchg %eax, %eax is a special case. It is an alias for nop
6418 only in 32bit mode and we can use opcode 0x90. In 64bit
6419 mode, we can't use 0x90 for xchg %eax, %eax since it should
6420 zero-extend %eax to %rax. */
6421 if (flag_code == CODE_64BIT
6422 && t->base_opcode == 0x90
6423 && i.types[0].bitfield.instance == Accum
6424 && i.types[0].bitfield.dword
6425 && i.types[1].bitfield.instance == Accum
6426 && i.types[1].bitfield.dword)
6427 continue;
6428 /* xrelease mov %eax, <disp> is another special case. It must not
6429 match the accumulator-only encoding of mov. */
6430 if (flag_code != CODE_64BIT
6431 && i.hle_prefix
6432 && t->base_opcode == 0xa0
6433 && i.types[0].bitfield.instance == Accum
6434 && (i.flags[1] & Operand_Mem))
6435 continue;
6436 /* Fall through. */
6437
6438 case 3:
6439 if (!(size_match & MATCH_STRAIGHT))
6440 goto check_reverse;
6441 /* Reverse direction of operands if swapping is possible in the first
6442 place (operands need to be symmetric) and
6443 - the load form is requested, and the template is a store form,
6444 - the store form is requested, and the template is a load form,
6445 - the non-default (swapped) form is requested. */
6446 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
6447 if (t->opcode_modifier.d && i.reg_operands == i.operands
6448 && !operand_type_all_zero (&overlap1))
6449 switch (i.dir_encoding)
6450 {
6451 case dir_encoding_load:
6452 if (operand_type_check (operand_types[i.operands - 1], anymem)
6453 || t->opcode_modifier.regmem)
6454 goto check_reverse;
6455 break;
6456
6457 case dir_encoding_store:
6458 if (!operand_type_check (operand_types[i.operands - 1], anymem)
6459 && !t->opcode_modifier.regmem)
6460 goto check_reverse;
6461 break;
6462
6463 case dir_encoding_swap:
6464 goto check_reverse;
6465
6466 case dir_encoding_default:
6467 break;
6468 }
6469 /* If we want store form, we skip the current load. */
6470 if ((i.dir_encoding == dir_encoding_store
6471 || i.dir_encoding == dir_encoding_swap)
6472 && i.mem_operands == 0
6473 && t->opcode_modifier.load)
6474 continue;
6475 /* Fall through. */
6476 case 4:
6477 case 5:
6478 overlap1 = operand_type_and (i.types[1], operand_types[1]);
6479 if (!operand_type_match (overlap0, i.types[0])
6480 || !operand_type_match (overlap1, i.types[1])
6481 || ((check_register & 3) == 3
6482 && !operand_type_register_match (i.types[0],
6483 operand_types[0],
6484 i.types[1],
6485 operand_types[1])))
6486 {
6487 /* Check if other direction is valid ... */
6488 if (!t->opcode_modifier.d)
6489 continue;
6490
6491 check_reverse:
6492 if (!(size_match & MATCH_REVERSE))
6493 continue;
6494 /* Try reversing direction of operands. */
6495 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
6496 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
6497 if (!operand_type_match (overlap0, i.types[0])
6498 || !operand_type_match (overlap1, i.types[i.operands - 1])
6499 || (check_register
6500 && !operand_type_register_match (i.types[0],
6501 operand_types[i.operands - 1],
6502 i.types[i.operands - 1],
6503 operand_types[0])))
6504 {
6505 /* Does not match either direction. */
6506 continue;
6507 }
6508 /* found_reverse_match holds which of D or FloatR
6509 we've found. */
6510 if (!t->opcode_modifier.d)
6511 found_reverse_match = 0;
6512 else if (operand_types[0].bitfield.tbyte)
6513 found_reverse_match = Opcode_FloatD;
6514 else if (operand_types[0].bitfield.xmmword
6515 || operand_types[i.operands - 1].bitfield.xmmword
6516 || operand_types[0].bitfield.class == RegMMX
6517 || operand_types[i.operands - 1].bitfield.class == RegMMX
6518 || is_any_vex_encoding(t))
6519 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
6520 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
6521 else
6522 found_reverse_match = Opcode_D;
6523 if (t->opcode_modifier.floatr)
6524 found_reverse_match |= Opcode_FloatR;
6525 }
6526 else
6527 {
6528 /* Found a forward 2 operand match here. */
6529 switch (t->operands)
6530 {
6531 case 5:
6532 overlap4 = operand_type_and (i.types[4],
6533 operand_types[4]);
6534 /* Fall through. */
6535 case 4:
6536 overlap3 = operand_type_and (i.types[3],
6537 operand_types[3]);
6538 /* Fall through. */
6539 case 3:
6540 overlap2 = operand_type_and (i.types[2],
6541 operand_types[2]);
6542 break;
6543 }
6544
6545 switch (t->operands)
6546 {
6547 case 5:
6548 if (!operand_type_match (overlap4, i.types[4])
6549 || !operand_type_register_match (i.types[3],
6550 operand_types[3],
6551 i.types[4],
6552 operand_types[4]))
6553 continue;
6554 /* Fall through. */
6555 case 4:
6556 if (!operand_type_match (overlap3, i.types[3])
6557 || ((check_register & 0xa) == 0xa
6558 && !operand_type_register_match (i.types[1],
6559 operand_types[1],
6560 i.types[3],
6561 operand_types[3]))
6562 || ((check_register & 0xc) == 0xc
6563 && !operand_type_register_match (i.types[2],
6564 operand_types[2],
6565 i.types[3],
6566 operand_types[3])))
6567 continue;
6568 /* Fall through. */
6569 case 3:
6570 /* Here we make use of the fact that there are no
6571 reverse match 3 operand instructions. */
6572 if (!operand_type_match (overlap2, i.types[2])
6573 || ((check_register & 5) == 5
6574 && !operand_type_register_match (i.types[0],
6575 operand_types[0],
6576 i.types[2],
6577 operand_types[2]))
6578 || ((check_register & 6) == 6
6579 && !operand_type_register_match (i.types[1],
6580 operand_types[1],
6581 i.types[2],
6582 operand_types[2])))
6583 continue;
6584 break;
6585 }
6586 }
6587 /* Found either forward/reverse 2, 3 or 4 operand match here:
6588 slip through to break. */
6589 }
6590
6591 /* Check if vector operands are valid. */
6592 if (check_VecOperands (t))
6593 {
6594 specific_error = i.error;
6595 continue;
6596 }
6597
6598 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6599 if (VEX_check_encoding (t))
6600 {
6601 specific_error = i.error;
6602 continue;
6603 }
6604
6605 /* We've found a match; break out of loop. */
6606 break;
6607 }
6608
6609 if (t == current_templates->end)
6610 {
6611 /* We found no match. */
6612 const char *err_msg;
6613 switch (specific_error ? specific_error : i.error)
6614 {
6615 default:
6616 abort ();
6617 case operand_size_mismatch:
6618 err_msg = _("operand size mismatch");
6619 break;
6620 case operand_type_mismatch:
6621 err_msg = _("operand type mismatch");
6622 break;
6623 case register_type_mismatch:
6624 err_msg = _("register type mismatch");
6625 break;
6626 case number_of_operands_mismatch:
6627 err_msg = _("number of operands mismatch");
6628 break;
6629 case invalid_instruction_suffix:
6630 err_msg = _("invalid instruction suffix");
6631 break;
6632 case bad_imm4:
6633 err_msg = _("constant doesn't fit in 4 bits");
6634 break;
6635 case unsupported_with_intel_mnemonic:
6636 err_msg = _("unsupported with Intel mnemonic");
6637 break;
6638 case unsupported_syntax:
6639 err_msg = _("unsupported syntax");
6640 break;
6641 case unsupported:
6642 as_bad (_("unsupported instruction `%s'"),
6643 current_templates->start->name);
6644 return NULL;
6645 case invalid_sib_address:
6646 err_msg = _("invalid SIB address");
6647 break;
6648 case invalid_vsib_address:
6649 err_msg = _("invalid VSIB address");
6650 break;
6651 case invalid_vector_register_set:
6652 err_msg = _("mask, index, and destination registers must be distinct");
6653 break;
6654 case invalid_tmm_register_set:
6655 err_msg = _("all tmm registers must be distinct");
6656 break;
6657 case unsupported_vector_index_register:
6658 err_msg = _("unsupported vector index register");
6659 break;
6660 case unsupported_broadcast:
6661 err_msg = _("unsupported broadcast");
6662 break;
6663 case broadcast_needed:
6664 err_msg = _("broadcast is needed for operand of such type");
6665 break;
6666 case unsupported_masking:
6667 err_msg = _("unsupported masking");
6668 break;
6669 case mask_not_on_destination:
6670 err_msg = _("mask not on destination operand");
6671 break;
6672 case no_default_mask:
6673 err_msg = _("default mask isn't allowed");
6674 break;
6675 case unsupported_rc_sae:
6676 err_msg = _("unsupported static rounding/sae");
6677 break;
6678 case rc_sae_operand_not_last_imm:
6679 if (intel_syntax)
6680 err_msg = _("RC/SAE operand must precede immediate operands");
6681 else
6682 err_msg = _("RC/SAE operand must follow immediate operands");
6683 break;
6684 case invalid_register_operand:
6685 err_msg = _("invalid register operand");
6686 break;
6687 }
6688 as_bad (_("%s for `%s'"), err_msg,
6689 current_templates->start->name);
6690 return NULL;
6691 }
6692
6693 if (!quiet_warnings)
6694 {
6695 if (!intel_syntax
6696 && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
6697 as_warn (_("indirect %s without `*'"), t->name);
6698
6699 if (t->opcode_modifier.isprefix
6700 && t->opcode_modifier.mnemonicsize == IGNORESIZE)
6701 {
6702 /* Warn them that a data or address size prefix doesn't
6703 affect assembly of the next line of code. */
6704 as_warn (_("stand-alone `%s' prefix"), t->name);
6705 }
6706 }
6707
6708 /* Copy the template we found. */
6709 i.tm = *t;
6710
6711 if (addr_prefix_disp != -1)
6712 i.tm.operand_types[addr_prefix_disp]
6713 = operand_types[addr_prefix_disp];
6714
6715 if (found_reverse_match)
6716 {
6717 /* If we found a reverse match we must alter the opcode direction
6718 bit and clear/flip the regmem modifier one. found_reverse_match
6719 holds bits to change (different for int & float insns). */
6720
6721 i.tm.base_opcode ^= found_reverse_match;
6722
6723 i.tm.operand_types[0] = operand_types[i.operands - 1];
6724 i.tm.operand_types[i.operands - 1] = operand_types[0];
6725
6726 /* Certain SIMD insns have their load forms specified in the opcode
6727 table, and hence we need to _set_ RegMem instead of clearing it.
6728 We need to avoid setting the bit though on insns like KMOVW. */
6729 i.tm.opcode_modifier.regmem
6730 = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
6731 && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
6732 && !i.tm.opcode_modifier.regmem;
6733 }
6734
6735 return t;
6736 }
6737
6738 static int
6739 check_string (void)
6740 {
6741 unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
6742 unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
6743
6744 if (i.seg[op] != NULL && i.seg[op] != &es)
6745 {
6746 as_bad (_("`%s' operand %u must use `%ses' segment"),
6747 i.tm.name,
6748 intel_syntax ? i.tm.operands - es_op : es_op + 1,
6749 register_prefix);
6750 return 0;
6751 }
6752
6753 /* There's only ever one segment override allowed per instruction.
6754 This instruction possibly has a legal segment override on the
6755 second operand, so copy the segment to where non-string
6756 instructions store it, allowing common code. */
6757 i.seg[op] = i.seg[1];
6758
6759 return 1;
6760 }
6761
6762 static int
6763 process_suffix (void)
6764 {
6765 /* If matched instruction specifies an explicit instruction mnemonic
6766 suffix, use it. */
6767 if (i.tm.opcode_modifier.size == SIZE16)
6768 i.suffix = WORD_MNEM_SUFFIX;
6769 else if (i.tm.opcode_modifier.size == SIZE32)
6770 i.suffix = LONG_MNEM_SUFFIX;
6771 else if (i.tm.opcode_modifier.size == SIZE64)
6772 i.suffix = QWORD_MNEM_SUFFIX;
6773 else if (i.reg_operands
6774 && (i.operands > 1 || i.types[0].bitfield.class == Reg)
6775 && !i.tm.opcode_modifier.addrprefixopreg)
6776 {
6777 unsigned int numop = i.operands;
6778
6779 /* movsx/movzx want only their source operand considered here, for the
6780 ambiguity checking below. The suffix will be replaced afterwards
6781 to represent the destination (register). */
6782 if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w)
6783 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
6784 --i.operands;
6785
6786 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6787 if (i.tm.base_opcode == 0xf20f38f0
6788 && i.tm.operand_types[1].bitfield.qword)
6789 i.rex |= REX_W;
6790
6791 /* If there's no instruction mnemonic suffix we try to invent one
6792 based on GPR operands. */
6793 if (!i.suffix)
6794 {
6795 /* We take i.suffix from the last register operand specified,
6796 Destination register type is more significant than source
6797 register type. crc32 in SSE4.2 prefers source register
6798 type. */
6799 unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
6800
6801 while (op--)
6802 if (i.tm.operand_types[op].bitfield.instance == InstanceNone
6803 || i.tm.operand_types[op].bitfield.instance == Accum)
6804 {
6805 if (i.types[op].bitfield.class != Reg)
6806 continue;
6807 if (i.types[op].bitfield.byte)
6808 i.suffix = BYTE_MNEM_SUFFIX;
6809 else if (i.types[op].bitfield.word)
6810 i.suffix = WORD_MNEM_SUFFIX;
6811 else if (i.types[op].bitfield.dword)
6812 i.suffix = LONG_MNEM_SUFFIX;
6813 else if (i.types[op].bitfield.qword)
6814 i.suffix = QWORD_MNEM_SUFFIX;
6815 else
6816 continue;
6817 break;
6818 }
6819
6820 /* As an exception, movsx/movzx silently default to a byte source
6821 in AT&T mode. */
6822 if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w
6823 && !i.suffix && !intel_syntax)
6824 i.suffix = BYTE_MNEM_SUFFIX;
6825 }
6826 else if (i.suffix == BYTE_MNEM_SUFFIX)
6827 {
6828 if (intel_syntax
6829 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6830 && i.tm.opcode_modifier.no_bsuf)
6831 i.suffix = 0;
6832 else if (!check_byte_reg ())
6833 return 0;
6834 }
6835 else if (i.suffix == LONG_MNEM_SUFFIX)
6836 {
6837 if (intel_syntax
6838 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6839 && i.tm.opcode_modifier.no_lsuf
6840 && !i.tm.opcode_modifier.todword
6841 && !i.tm.opcode_modifier.toqword)
6842 i.suffix = 0;
6843 else if (!check_long_reg ())
6844 return 0;
6845 }
6846 else if (i.suffix == QWORD_MNEM_SUFFIX)
6847 {
6848 if (intel_syntax
6849 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6850 && i.tm.opcode_modifier.no_qsuf
6851 && !i.tm.opcode_modifier.todword
6852 && !i.tm.opcode_modifier.toqword)
6853 i.suffix = 0;
6854 else if (!check_qword_reg ())
6855 return 0;
6856 }
6857 else if (i.suffix == WORD_MNEM_SUFFIX)
6858 {
6859 if (intel_syntax
6860 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6861 && i.tm.opcode_modifier.no_wsuf)
6862 i.suffix = 0;
6863 else if (!check_word_reg ())
6864 return 0;
6865 }
6866 else if (intel_syntax
6867 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
6868 /* Do nothing if the instruction is going to ignore the prefix. */
6869 ;
6870 else
6871 abort ();
6872
6873 /* Undo the movsx/movzx change done above. */
6874 i.operands = numop;
6875 }
6876 else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
6877 && !i.suffix)
6878 {
6879 i.suffix = stackop_size;
6880 if (stackop_size == LONG_MNEM_SUFFIX)
6881 {
6882 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6883 .code16gcc directive to support 16-bit mode with
6884 32-bit address. For IRET without a suffix, generate
6885 16-bit IRET (opcode 0xcf) to return from an interrupt
6886 handler. */
6887 if (i.tm.base_opcode == 0xcf)
6888 {
6889 i.suffix = WORD_MNEM_SUFFIX;
6890 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6891 }
6892 /* Warn about changed behavior for segment register push/pop. */
6893 else if ((i.tm.base_opcode | 1) == 0x07)
6894 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6895 i.tm.name);
6896 }
6897 }
6898 else if (!i.suffix
6899 && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
6900 || i.tm.opcode_modifier.jump == JUMP_BYTE
6901 || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
6902 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6903 && i.tm.extension_opcode <= 3)))
6904 {
6905 switch (flag_code)
6906 {
6907 case CODE_64BIT:
6908 if (!i.tm.opcode_modifier.no_qsuf)
6909 {
6910 if (i.tm.opcode_modifier.jump == JUMP_BYTE
6911 || i.tm.opcode_modifier.no_lsuf)
6912 i.suffix = QWORD_MNEM_SUFFIX;
6913 break;
6914 }
6915 /* Fall through. */
6916 case CODE_32BIT:
6917 if (!i.tm.opcode_modifier.no_lsuf)
6918 i.suffix = LONG_MNEM_SUFFIX;
6919 break;
6920 case CODE_16BIT:
6921 if (!i.tm.opcode_modifier.no_wsuf)
6922 i.suffix = WORD_MNEM_SUFFIX;
6923 break;
6924 }
6925 }
6926
6927 if (!i.suffix
6928 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
6929 /* Also cover lret/retf/iret in 64-bit mode. */
6930 || (flag_code == CODE_64BIT
6931 && !i.tm.opcode_modifier.no_lsuf
6932 && !i.tm.opcode_modifier.no_qsuf))
6933 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
6934 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6935 && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W)
6936 /* Accept FLDENV et al without suffix. */
6937 && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
6938 {
6939 unsigned int suffixes, evex = 0;
6940
6941 suffixes = !i.tm.opcode_modifier.no_bsuf;
6942 if (!i.tm.opcode_modifier.no_wsuf)
6943 suffixes |= 1 << 1;
6944 if (!i.tm.opcode_modifier.no_lsuf)
6945 suffixes |= 1 << 2;
6946 if (!i.tm.opcode_modifier.no_ldsuf)
6947 suffixes |= 1 << 3;
6948 if (!i.tm.opcode_modifier.no_ssuf)
6949 suffixes |= 1 << 4;
6950 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6951 suffixes |= 1 << 5;
6952
6953 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6954 also suitable for AT&T syntax mode, it was requested that this be
6955 restricted to just Intel syntax. */
6956 if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast)
6957 {
6958 unsigned int op;
6959
6960 for (op = 0; op < i.tm.operands; ++op)
6961 {
6962 if (is_evex_encoding (&i.tm)
6963 && !cpu_arch_flags.bitfield.cpuavx512vl)
6964 {
6965 if (i.tm.operand_types[op].bitfield.ymmword)
6966 i.tm.operand_types[op].bitfield.xmmword = 0;
6967 if (i.tm.operand_types[op].bitfield.zmmword)
6968 i.tm.operand_types[op].bitfield.ymmword = 0;
6969 if (!i.tm.opcode_modifier.evex
6970 || i.tm.opcode_modifier.evex == EVEXDYN)
6971 i.tm.opcode_modifier.evex = EVEX512;
6972 }
6973
6974 if (i.tm.operand_types[op].bitfield.xmmword
6975 + i.tm.operand_types[op].bitfield.ymmword
6976 + i.tm.operand_types[op].bitfield.zmmword < 2)
6977 continue;
6978
6979 /* Any properly sized operand disambiguates the insn. */
6980 if (i.types[op].bitfield.xmmword
6981 || i.types[op].bitfield.ymmword
6982 || i.types[op].bitfield.zmmword)
6983 {
6984 suffixes &= ~(7 << 6);
6985 evex = 0;
6986 break;
6987 }
6988
6989 if ((i.flags[op] & Operand_Mem)
6990 && i.tm.operand_types[op].bitfield.unspecified)
6991 {
6992 if (i.tm.operand_types[op].bitfield.xmmword)
6993 suffixes |= 1 << 6;
6994 if (i.tm.operand_types[op].bitfield.ymmword)
6995 suffixes |= 1 << 7;
6996 if (i.tm.operand_types[op].bitfield.zmmword)
6997 suffixes |= 1 << 8;
6998 if (is_evex_encoding (&i.tm))
6999 evex = EVEX512;
7000 }
7001 }
7002 }
7003
7004 /* Are multiple suffixes / operand sizes allowed? */
7005 if (suffixes & (suffixes - 1))
7006 {
7007 if (intel_syntax
7008 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
7009 || operand_check == check_error))
7010 {
7011 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
7012 return 0;
7013 }
7014 if (operand_check == check_error)
7015 {
7016 as_bad (_("no instruction mnemonic suffix given and "
7017 "no register operands; can't size `%s'"), i.tm.name);
7018 return 0;
7019 }
7020 if (operand_check == check_warning)
7021 as_warn (_("%s; using default for `%s'"),
7022 intel_syntax
7023 ? _("ambiguous operand size")
7024 : _("no instruction mnemonic suffix given and "
7025 "no register operands"),
7026 i.tm.name);
7027
7028 if (i.tm.opcode_modifier.floatmf)
7029 i.suffix = SHORT_MNEM_SUFFIX;
7030 else if ((i.tm.base_opcode | 8) == 0xfbe
7031 || (i.tm.base_opcode == 0x63
7032 && i.tm.cpu_flags.bitfield.cpu64))
7033 /* handled below */;
7034 else if (evex)
7035 i.tm.opcode_modifier.evex = evex;
7036 else if (flag_code == CODE_16BIT)
7037 i.suffix = WORD_MNEM_SUFFIX;
7038 else if (!i.tm.opcode_modifier.no_lsuf)
7039 i.suffix = LONG_MNEM_SUFFIX;
7040 else
7041 i.suffix = QWORD_MNEM_SUFFIX;
7042 }
7043 }
7044
7045 if ((i.tm.base_opcode | 8) == 0xfbe
7046 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
7047 {
7048 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7049 In AT&T syntax, if there is no suffix (warned about above), the default
7050 will be byte extension. */
7051 if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
7052 i.tm.base_opcode |= 1;
7053
7054 /* For further processing, the suffix should represent the destination
7055 (register). This is already the case when one was used with
7056 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7057 no suffix to begin with. */
7058 if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
7059 {
7060 if (i.types[1].bitfield.word)
7061 i.suffix = WORD_MNEM_SUFFIX;
7062 else if (i.types[1].bitfield.qword)
7063 i.suffix = QWORD_MNEM_SUFFIX;
7064 else
7065 i.suffix = LONG_MNEM_SUFFIX;
7066
7067 i.tm.opcode_modifier.w = 0;
7068 }
7069 }
7070
7071 if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
7072 i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
7073 != (i.tm.operand_types[1].bitfield.class == Reg);
7074
7075 /* Change the opcode based on the operand size given by i.suffix. */
7076 switch (i.suffix)
7077 {
7078 /* Size floating point instruction. */
7079 case LONG_MNEM_SUFFIX:
7080 if (i.tm.opcode_modifier.floatmf)
7081 {
7082 i.tm.base_opcode ^= 4;
7083 break;
7084 }
7085 /* fall through */
7086 case WORD_MNEM_SUFFIX:
7087 case QWORD_MNEM_SUFFIX:
7088 /* It's not a byte, select word/dword operation. */
7089 if (i.tm.opcode_modifier.w)
7090 {
7091 if (i.short_form)
7092 i.tm.base_opcode |= 8;
7093 else
7094 i.tm.base_opcode |= 1;
7095 }
7096 /* fall through */
7097 case SHORT_MNEM_SUFFIX:
7098 /* Now select between word & dword operations via the operand
7099 size prefix, except for instructions that will ignore this
7100 prefix anyway. */
7101 if (i.suffix != QWORD_MNEM_SUFFIX
7102 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
7103 && !i.tm.opcode_modifier.floatmf
7104 && !is_any_vex_encoding (&i.tm)
7105 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
7106 || (flag_code == CODE_64BIT
7107 && i.tm.opcode_modifier.jump == JUMP_BYTE)))
7108 {
7109 unsigned int prefix = DATA_PREFIX_OPCODE;
7110
7111 if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
7112 prefix = ADDR_PREFIX_OPCODE;
7113
7114 if (!add_prefix (prefix))
7115 return 0;
7116 }
7117
7118 /* Set mode64 for an operand. */
7119 if (i.suffix == QWORD_MNEM_SUFFIX
7120 && flag_code == CODE_64BIT
7121 && !i.tm.opcode_modifier.norex64
7122 && !i.tm.opcode_modifier.vexw
7123 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7124 need rex64. */
7125 && ! (i.operands == 2
7126 && i.tm.base_opcode == 0x90
7127 && i.tm.extension_opcode == None
7128 && i.types[0].bitfield.instance == Accum
7129 && i.types[0].bitfield.qword
7130 && i.types[1].bitfield.instance == Accum
7131 && i.types[1].bitfield.qword))
7132 i.rex |= REX_W;
7133
7134 break;
7135
7136 case 0:
7137 /* Select word/dword/qword operation with explict data sizing prefix
7138 when there are no suitable register operands. */
7139 if (i.tm.opcode_modifier.w
7140 && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W))
7141 && (!i.reg_operands
7142 || (i.reg_operands == 1
7143 /* ShiftCount */
7144 && (i.tm.operand_types[0].bitfield.instance == RegC
7145 /* InOutPortReg */
7146 || i.tm.operand_types[0].bitfield.instance == RegD
7147 || i.tm.operand_types[1].bitfield.instance == RegD
7148 /* CRC32 */
7149 || i.tm.base_opcode == 0xf20f38f0))))
7150 i.tm.base_opcode |= 1;
7151 break;
7152 }
7153
7154 if (i.tm.opcode_modifier.addrprefixopreg)
7155 {
7156 gas_assert (!i.suffix);
7157 gas_assert (i.reg_operands);
7158
7159 if (i.tm.operand_types[0].bitfield.instance == Accum
7160 || i.operands == 1)
7161 {
7162 /* The address size override prefix changes the size of the
7163 first operand. */
7164 if (flag_code == CODE_64BIT
7165 && i.op[0].regs->reg_type.bitfield.word)
7166 {
7167 as_bad (_("16-bit addressing unavailable for `%s'"),
7168 i.tm.name);
7169 return 0;
7170 }
7171
7172 if ((flag_code == CODE_32BIT
7173 ? i.op[0].regs->reg_type.bitfield.word
7174 : i.op[0].regs->reg_type.bitfield.dword)
7175 && !add_prefix (ADDR_PREFIX_OPCODE))
7176 return 0;
7177 }
7178 else
7179 {
7180 /* Check invalid register operand when the address size override
7181 prefix changes the size of register operands. */
7182 unsigned int op;
7183 enum { need_word, need_dword, need_qword } need;
7184
7185 if (flag_code == CODE_32BIT)
7186 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
7187 else if (i.prefix[ADDR_PREFIX])
7188 need = need_dword;
7189 else
7190 need = flag_code == CODE_64BIT ? need_qword : need_word;
7191
7192 for (op = 0; op < i.operands; op++)
7193 {
7194 if (i.types[op].bitfield.class != Reg)
7195 continue;
7196
7197 switch (need)
7198 {
7199 case need_word:
7200 if (i.op[op].regs->reg_type.bitfield.word)
7201 continue;
7202 break;
7203 case need_dword:
7204 if (i.op[op].regs->reg_type.bitfield.dword)
7205 continue;
7206 break;
7207 case need_qword:
7208 if (i.op[op].regs->reg_type.bitfield.qword)
7209 continue;
7210 break;
7211 }
7212
7213 as_bad (_("invalid register operand size for `%s'"),
7214 i.tm.name);
7215 return 0;
7216 }
7217 }
7218 }
7219
7220 return 1;
7221 }
7222
7223 static int
7224 check_byte_reg (void)
7225 {
7226 int op;
7227
7228 for (op = i.operands; --op >= 0;)
7229 {
7230 /* Skip non-register operands. */
7231 if (i.types[op].bitfield.class != Reg)
7232 continue;
7233
7234 /* If this is an eight bit register, it's OK. If it's the 16 or
7235 32 bit version of an eight bit register, we will just use the
7236 low portion, and that's OK too. */
7237 if (i.types[op].bitfield.byte)
7238 continue;
7239
7240 /* I/O port address operands are OK too. */
7241 if (i.tm.operand_types[op].bitfield.instance == RegD
7242 && i.tm.operand_types[op].bitfield.word)
7243 continue;
7244
7245 /* crc32 only wants its source operand checked here. */
7246 if (i.tm.base_opcode == 0xf20f38f0 && op)
7247 continue;
7248
7249 /* Any other register is bad. */
7250 as_bad (_("`%s%s' not allowed with `%s%c'"),
7251 register_prefix, i.op[op].regs->reg_name,
7252 i.tm.name, i.suffix);
7253 return 0;
7254 }
7255 return 1;
7256 }
7257
7258 static int
7259 check_long_reg (void)
7260 {
7261 int op;
7262
7263 for (op = i.operands; --op >= 0;)
7264 /* Skip non-register operands. */
7265 if (i.types[op].bitfield.class != Reg)
7266 continue;
7267 /* Reject eight bit registers, except where the template requires
7268 them. (eg. movzb) */
7269 else if (i.types[op].bitfield.byte
7270 && (i.tm.operand_types[op].bitfield.class == Reg
7271 || i.tm.operand_types[op].bitfield.instance == Accum)
7272 && (i.tm.operand_types[op].bitfield.word
7273 || i.tm.operand_types[op].bitfield.dword))
7274 {
7275 as_bad (_("`%s%s' not allowed with `%s%c'"),
7276 register_prefix,
7277 i.op[op].regs->reg_name,
7278 i.tm.name,
7279 i.suffix);
7280 return 0;
7281 }
7282 /* Error if the e prefix on a general reg is missing. */
7283 else if (i.types[op].bitfield.word
7284 && (i.tm.operand_types[op].bitfield.class == Reg
7285 || i.tm.operand_types[op].bitfield.instance == Accum)
7286 && i.tm.operand_types[op].bitfield.dword)
7287 {
7288 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7289 register_prefix, i.op[op].regs->reg_name,
7290 i.suffix);
7291 return 0;
7292 }
7293 /* Warn if the r prefix on a general reg is present. */
7294 else if (i.types[op].bitfield.qword
7295 && (i.tm.operand_types[op].bitfield.class == Reg
7296 || i.tm.operand_types[op].bitfield.instance == Accum)
7297 && i.tm.operand_types[op].bitfield.dword)
7298 {
7299 if (intel_syntax
7300 && i.tm.opcode_modifier.toqword
7301 && i.types[0].bitfield.class != RegSIMD)
7302 {
7303 /* Convert to QWORD. We want REX byte. */
7304 i.suffix = QWORD_MNEM_SUFFIX;
7305 }
7306 else
7307 {
7308 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7309 register_prefix, i.op[op].regs->reg_name,
7310 i.suffix);
7311 return 0;
7312 }
7313 }
7314 return 1;
7315 }
7316
7317 static int
7318 check_qword_reg (void)
7319 {
7320 int op;
7321
7322 for (op = i.operands; --op >= 0; )
7323 /* Skip non-register operands. */
7324 if (i.types[op].bitfield.class != Reg)
7325 continue;
7326 /* Reject eight bit registers, except where the template requires
7327 them. (eg. movzb) */
7328 else if (i.types[op].bitfield.byte
7329 && (i.tm.operand_types[op].bitfield.class == Reg
7330 || i.tm.operand_types[op].bitfield.instance == Accum)
7331 && (i.tm.operand_types[op].bitfield.word
7332 || i.tm.operand_types[op].bitfield.dword))
7333 {
7334 as_bad (_("`%s%s' not allowed with `%s%c'"),
7335 register_prefix,
7336 i.op[op].regs->reg_name,
7337 i.tm.name,
7338 i.suffix);
7339 return 0;
7340 }
7341 /* Warn if the r prefix on a general reg is missing. */
7342 else if ((i.types[op].bitfield.word
7343 || i.types[op].bitfield.dword)
7344 && (i.tm.operand_types[op].bitfield.class == Reg
7345 || i.tm.operand_types[op].bitfield.instance == Accum)
7346 && i.tm.operand_types[op].bitfield.qword)
7347 {
7348 /* Prohibit these changes in the 64bit mode, since the
7349 lowering is more complicated. */
7350 if (intel_syntax
7351 && i.tm.opcode_modifier.todword
7352 && i.types[0].bitfield.class != RegSIMD)
7353 {
7354 /* Convert to DWORD. We don't want REX byte. */
7355 i.suffix = LONG_MNEM_SUFFIX;
7356 }
7357 else
7358 {
7359 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7360 register_prefix, i.op[op].regs->reg_name,
7361 i.suffix);
7362 return 0;
7363 }
7364 }
7365 return 1;
7366 }
7367
7368 static int
7369 check_word_reg (void)
7370 {
7371 int op;
7372 for (op = i.operands; --op >= 0;)
7373 /* Skip non-register operands. */
7374 if (i.types[op].bitfield.class != Reg)
7375 continue;
7376 /* Reject eight bit registers, except where the template requires
7377 them. (eg. movzb) */
7378 else if (i.types[op].bitfield.byte
7379 && (i.tm.operand_types[op].bitfield.class == Reg
7380 || i.tm.operand_types[op].bitfield.instance == Accum)
7381 && (i.tm.operand_types[op].bitfield.word
7382 || i.tm.operand_types[op].bitfield.dword))
7383 {
7384 as_bad (_("`%s%s' not allowed with `%s%c'"),
7385 register_prefix,
7386 i.op[op].regs->reg_name,
7387 i.tm.name,
7388 i.suffix);
7389 return 0;
7390 }
7391 /* Error if the e or r prefix on a general reg is present. */
7392 else if ((i.types[op].bitfield.dword
7393 || i.types[op].bitfield.qword)
7394 && (i.tm.operand_types[op].bitfield.class == Reg
7395 || i.tm.operand_types[op].bitfield.instance == Accum)
7396 && i.tm.operand_types[op].bitfield.word)
7397 {
7398 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7399 register_prefix, i.op[op].regs->reg_name,
7400 i.suffix);
7401 return 0;
7402 }
7403 return 1;
7404 }
7405
7406 static int
7407 update_imm (unsigned int j)
7408 {
7409 i386_operand_type overlap = i.types[j];
7410 if ((overlap.bitfield.imm8
7411 || overlap.bitfield.imm8s
7412 || overlap.bitfield.imm16
7413 || overlap.bitfield.imm32
7414 || overlap.bitfield.imm32s
7415 || overlap.bitfield.imm64)
7416 && !operand_type_equal (&overlap, &imm8)
7417 && !operand_type_equal (&overlap, &imm8s)
7418 && !operand_type_equal (&overlap, &imm16)
7419 && !operand_type_equal (&overlap, &imm32)
7420 && !operand_type_equal (&overlap, &imm32s)
7421 && !operand_type_equal (&overlap, &imm64))
7422 {
7423 if (i.suffix)
7424 {
7425 i386_operand_type temp;
7426
7427 operand_type_set (&temp, 0);
7428 if (i.suffix == BYTE_MNEM_SUFFIX)
7429 {
7430 temp.bitfield.imm8 = overlap.bitfield.imm8;
7431 temp.bitfield.imm8s = overlap.bitfield.imm8s;
7432 }
7433 else if (i.suffix == WORD_MNEM_SUFFIX)
7434 temp.bitfield.imm16 = overlap.bitfield.imm16;
7435 else if (i.suffix == QWORD_MNEM_SUFFIX)
7436 {
7437 temp.bitfield.imm64 = overlap.bitfield.imm64;
7438 temp.bitfield.imm32s = overlap.bitfield.imm32s;
7439 }
7440 else
7441 temp.bitfield.imm32 = overlap.bitfield.imm32;
7442 overlap = temp;
7443 }
7444 else if (operand_type_equal (&overlap, &imm16_32_32s)
7445 || operand_type_equal (&overlap, &imm16_32)
7446 || operand_type_equal (&overlap, &imm16_32s))
7447 {
7448 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
7449 overlap = imm16;
7450 else
7451 overlap = imm32s;
7452 }
7453 else if (i.prefix[REX_PREFIX] & REX_W)
7454 overlap = operand_type_and (overlap, imm32s);
7455 else if (i.prefix[DATA_PREFIX])
7456 overlap = operand_type_and (overlap,
7457 flag_code != CODE_16BIT ? imm16 : imm32);
7458 if (!operand_type_equal (&overlap, &imm8)
7459 && !operand_type_equal (&overlap, &imm8s)
7460 && !operand_type_equal (&overlap, &imm16)
7461 && !operand_type_equal (&overlap, &imm32)
7462 && !operand_type_equal (&overlap, &imm32s)
7463 && !operand_type_equal (&overlap, &imm64))
7464 {
7465 as_bad (_("no instruction mnemonic suffix given; "
7466 "can't determine immediate size"));
7467 return 0;
7468 }
7469 }
7470 i.types[j] = overlap;
7471
7472 return 1;
7473 }
7474
7475 static int
7476 finalize_imm (void)
7477 {
7478 unsigned int j, n;
7479
7480 /* Update the first 2 immediate operands. */
7481 n = i.operands > 2 ? 2 : i.operands;
7482 if (n)
7483 {
7484 for (j = 0; j < n; j++)
7485 if (update_imm (j) == 0)
7486 return 0;
7487
7488 /* The 3rd operand can't be immediate operand. */
7489 gas_assert (operand_type_check (i.types[2], imm) == 0);
7490 }
7491
7492 return 1;
7493 }
7494
7495 static int
7496 process_operands (void)
7497 {
7498 /* Default segment register this instruction will use for memory
7499 accesses. 0 means unknown. This is only for optimizing out
7500 unnecessary segment overrides. */
7501 const seg_entry *default_seg = 0;
7502
7503 if (i.tm.opcode_modifier.sse2avx)
7504 {
7505 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7506 need converting. */
7507 i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B);
7508 i.prefix[REX_PREFIX] = 0;
7509 i.rex_encoding = 0;
7510 }
7511 /* ImmExt should be processed after SSE2AVX. */
7512 else if (i.tm.opcode_modifier.immext)
7513 process_immext ();
7514
7515 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
7516 {
7517 unsigned int dupl = i.operands;
7518 unsigned int dest = dupl - 1;
7519 unsigned int j;
7520
7521 /* The destination must be an xmm register. */
7522 gas_assert (i.reg_operands
7523 && MAX_OPERANDS > dupl
7524 && operand_type_equal (&i.types[dest], &regxmm));
7525
7526 if (i.tm.operand_types[0].bitfield.instance == Accum
7527 && i.tm.operand_types[0].bitfield.xmmword)
7528 {
7529 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
7530 {
7531 /* Keep xmm0 for instructions with VEX prefix and 3
7532 sources. */
7533 i.tm.operand_types[0].bitfield.instance = InstanceNone;
7534 i.tm.operand_types[0].bitfield.class = RegSIMD;
7535 goto duplicate;
7536 }
7537 else
7538 {
7539 /* We remove the first xmm0 and keep the number of
7540 operands unchanged, which in fact duplicates the
7541 destination. */
7542 for (j = 1; j < i.operands; j++)
7543 {
7544 i.op[j - 1] = i.op[j];
7545 i.types[j - 1] = i.types[j];
7546 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
7547 i.flags[j - 1] = i.flags[j];
7548 }
7549 }
7550 }
7551 else if (i.tm.opcode_modifier.implicit1stxmm0)
7552 {
7553 gas_assert ((MAX_OPERANDS - 1) > dupl
7554 && (i.tm.opcode_modifier.vexsources
7555 == VEX3SOURCES));
7556
7557 /* Add the implicit xmm0 for instructions with VEX prefix
7558 and 3 sources. */
7559 for (j = i.operands; j > 0; j--)
7560 {
7561 i.op[j] = i.op[j - 1];
7562 i.types[j] = i.types[j - 1];
7563 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
7564 i.flags[j] = i.flags[j - 1];
7565 }
7566 i.op[0].regs
7567 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7568 i.types[0] = regxmm;
7569 i.tm.operand_types[0] = regxmm;
7570
7571 i.operands += 2;
7572 i.reg_operands += 2;
7573 i.tm.operands += 2;
7574
7575 dupl++;
7576 dest++;
7577 i.op[dupl] = i.op[dest];
7578 i.types[dupl] = i.types[dest];
7579 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7580 i.flags[dupl] = i.flags[dest];
7581 }
7582 else
7583 {
7584 duplicate:
7585 i.operands++;
7586 i.reg_operands++;
7587 i.tm.operands++;
7588
7589 i.op[dupl] = i.op[dest];
7590 i.types[dupl] = i.types[dest];
7591 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7592 i.flags[dupl] = i.flags[dest];
7593 }
7594
7595 if (i.tm.opcode_modifier.immext)
7596 process_immext ();
7597 }
7598 else if (i.tm.operand_types[0].bitfield.instance == Accum
7599 && i.tm.operand_types[0].bitfield.xmmword)
7600 {
7601 unsigned int j;
7602
7603 for (j = 1; j < i.operands; j++)
7604 {
7605 i.op[j - 1] = i.op[j];
7606 i.types[j - 1] = i.types[j];
7607
7608 /* We need to adjust fields in i.tm since they are used by
7609 build_modrm_byte. */
7610 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
7611
7612 i.flags[j - 1] = i.flags[j];
7613 }
7614
7615 i.operands--;
7616 i.reg_operands--;
7617 i.tm.operands--;
7618 }
7619 else if (i.tm.opcode_modifier.implicitquadgroup)
7620 {
7621 unsigned int regnum, first_reg_in_group, last_reg_in_group;
7622
7623 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7624 gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
7625 regnum = register_number (i.op[1].regs);
7626 first_reg_in_group = regnum & ~3;
7627 last_reg_in_group = first_reg_in_group + 3;
7628 if (regnum != first_reg_in_group)
7629 as_warn (_("source register `%s%s' implicitly denotes"
7630 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7631 register_prefix, i.op[1].regs->reg_name,
7632 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
7633 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
7634 i.tm.name);
7635 }
7636 else if (i.tm.opcode_modifier.regkludge)
7637 {
7638 /* The imul $imm, %reg instruction is converted into
7639 imul $imm, %reg, %reg, and the clr %reg instruction
7640 is converted into xor %reg, %reg. */
7641
7642 unsigned int first_reg_op;
7643
7644 if (operand_type_check (i.types[0], reg))
7645 first_reg_op = 0;
7646 else
7647 first_reg_op = 1;
7648 /* Pretend we saw the extra register operand. */
7649 gas_assert (i.reg_operands == 1
7650 && i.op[first_reg_op + 1].regs == 0);
7651 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
7652 i.types[first_reg_op + 1] = i.types[first_reg_op];
7653 i.operands++;
7654 i.reg_operands++;
7655 }
7656
7657 if (i.tm.opcode_modifier.modrm)
7658 {
7659 /* The opcode is completed (modulo i.tm.extension_opcode which
7660 must be put into the modrm byte). Now, we make the modrm and
7661 index base bytes based on all the info we've collected. */
7662
7663 default_seg = build_modrm_byte ();
7664 }
7665 else if (i.types[0].bitfield.class == SReg)
7666 {
7667 if (flag_code != CODE_64BIT
7668 ? i.tm.base_opcode == POP_SEG_SHORT
7669 && i.op[0].regs->reg_num == 1
7670 : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
7671 && i.op[0].regs->reg_num < 4)
7672 {
7673 as_bad (_("you can't `%s %s%s'"),
7674 i.tm.name, register_prefix, i.op[0].regs->reg_name);
7675 return 0;
7676 }
7677 if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
7678 {
7679 i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
7680 i.tm.opcode_length = 2;
7681 }
7682 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
7683 }
7684 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
7685 {
7686 default_seg = &ds;
7687 }
7688 else if (i.tm.opcode_modifier.isstring)
7689 {
7690 /* For the string instructions that allow a segment override
7691 on one of their operands, the default segment is ds. */
7692 default_seg = &ds;
7693 }
7694 else if (i.short_form)
7695 {
7696 /* The register or float register operand is in operand
7697 0 or 1. */
7698 unsigned int op = i.tm.operand_types[0].bitfield.class != Reg;
7699
7700 /* Register goes in low 3 bits of opcode. */
7701 i.tm.base_opcode |= i.op[op].regs->reg_num;
7702 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7703 i.rex |= REX_B;
7704 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
7705 {
7706 /* Warn about some common errors, but press on regardless.
7707 The first case can be generated by gcc (<= 2.8.1). */
7708 if (i.operands == 2)
7709 {
7710 /* Reversed arguments on faddp, fsubp, etc. */
7711 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
7712 register_prefix, i.op[!intel_syntax].regs->reg_name,
7713 register_prefix, i.op[intel_syntax].regs->reg_name);
7714 }
7715 else
7716 {
7717 /* Extraneous `l' suffix on fp insn. */
7718 as_warn (_("translating to `%s %s%s'"), i.tm.name,
7719 register_prefix, i.op[0].regs->reg_name);
7720 }
7721 }
7722 }
7723
7724 if ((i.seg[0] || i.prefix[SEG_PREFIX])
7725 && i.tm.base_opcode == 0x8d /* lea */
7726 && !is_any_vex_encoding(&i.tm))
7727 {
7728 if (!quiet_warnings)
7729 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
7730 if (optimize)
7731 {
7732 i.seg[0] = NULL;
7733 i.prefix[SEG_PREFIX] = 0;
7734 }
7735 }
7736
7737 /* If a segment was explicitly specified, and the specified segment
7738 is neither the default nor the one already recorded from a prefix,
7739 use an opcode prefix to select it. If we never figured out what
7740 the default segment is, then default_seg will be zero at this
7741 point, and the specified segment prefix will always be used. */
7742 if (i.seg[0]
7743 && i.seg[0] != default_seg
7744 && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX])
7745 {
7746 if (!add_prefix (i.seg[0]->seg_prefix))
7747 return 0;
7748 }
7749 return 1;
7750 }
7751
7752 static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
7753 bfd_boolean do_sse2avx)
7754 {
7755 if (r->reg_flags & RegRex)
7756 {
7757 if (i.rex & rex_bit)
7758 as_bad (_("same type of prefix used twice"));
7759 i.rex |= rex_bit;
7760 }
7761 else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier)
7762 {
7763 gas_assert (i.vex.register_specifier == r);
7764 i.vex.register_specifier += 8;
7765 }
7766
7767 if (r->reg_flags & RegVRex)
7768 i.vrex |= rex_bit;
7769 }
7770
7771 static const seg_entry *
7772 build_modrm_byte (void)
7773 {
7774 const seg_entry *default_seg = 0;
7775 unsigned int source, dest;
7776 int vex_3_sources;
7777
7778 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
7779 if (vex_3_sources)
7780 {
7781 unsigned int nds, reg_slot;
7782 expressionS *exp;
7783
7784 dest = i.operands - 1;
7785 nds = dest - 1;
7786
7787 /* There are 2 kinds of instructions:
7788 1. 5 operands: 4 register operands or 3 register operands
7789 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7790 VexW0 or VexW1. The destination must be either XMM, YMM or
7791 ZMM register.
7792 2. 4 operands: 4 register operands or 3 register operands
7793 plus 1 memory operand, with VexXDS. */
7794 gas_assert ((i.reg_operands == 4
7795 || (i.reg_operands == 3 && i.mem_operands == 1))
7796 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7797 && i.tm.opcode_modifier.vexw
7798 && i.tm.operand_types[dest].bitfield.class == RegSIMD);
7799
7800 /* If VexW1 is set, the first non-immediate operand is the source and
7801 the second non-immediate one is encoded in the immediate operand. */
7802 if (i.tm.opcode_modifier.vexw == VEXW1)
7803 {
7804 source = i.imm_operands;
7805 reg_slot = i.imm_operands + 1;
7806 }
7807 else
7808 {
7809 source = i.imm_operands + 1;
7810 reg_slot = i.imm_operands;
7811 }
7812
7813 if (i.imm_operands == 0)
7814 {
7815 /* When there is no immediate operand, generate an 8bit
7816 immediate operand to encode the first operand. */
7817 exp = &im_expressions[i.imm_operands++];
7818 i.op[i.operands].imms = exp;
7819 i.types[i.operands] = imm8;
7820 i.operands++;
7821
7822 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7823 exp->X_op = O_constant;
7824 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
7825 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7826 }
7827 else
7828 {
7829 gas_assert (i.imm_operands == 1);
7830 gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
7831 gas_assert (!i.tm.opcode_modifier.immext);
7832
7833 /* Turn on Imm8 again so that output_imm will generate it. */
7834 i.types[0].bitfield.imm8 = 1;
7835
7836 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7837 i.op[0].imms->X_add_number
7838 |= register_number (i.op[reg_slot].regs) << 4;
7839 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7840 }
7841
7842 gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
7843 i.vex.register_specifier = i.op[nds].regs;
7844 }
7845 else
7846 source = dest = 0;
7847
7848 /* i.reg_operands MUST be the number of real register operands;
7849 implicit registers do not count. If there are 3 register
7850 operands, it must be a instruction with VexNDS. For a
7851 instruction with VexNDD, the destination register is encoded
7852 in VEX prefix. If there are 4 register operands, it must be
7853 a instruction with VEX prefix and 3 sources. */
7854 if (i.mem_operands == 0
7855 && ((i.reg_operands == 2
7856 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7857 || (i.reg_operands == 3
7858 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7859 || (i.reg_operands == 4 && vex_3_sources)))
7860 {
7861 switch (i.operands)
7862 {
7863 case 2:
7864 source = 0;
7865 break;
7866 case 3:
7867 /* When there are 3 operands, one of them may be immediate,
7868 which may be the first or the last operand. Otherwise,
7869 the first operand must be shift count register (cl) or it
7870 is an instruction with VexNDS. */
7871 gas_assert (i.imm_operands == 1
7872 || (i.imm_operands == 0
7873 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7874 || (i.types[0].bitfield.instance == RegC
7875 && i.types[0].bitfield.byte))));
7876 if (operand_type_check (i.types[0], imm)
7877 || (i.types[0].bitfield.instance == RegC
7878 && i.types[0].bitfield.byte))
7879 source = 1;
7880 else
7881 source = 0;
7882 break;
7883 case 4:
7884 /* When there are 4 operands, the first two must be 8bit
7885 immediate operands. The source operand will be the 3rd
7886 one.
7887
7888 For instructions with VexNDS, if the first operand
7889 an imm8, the source operand is the 2nd one. If the last
7890 operand is imm8, the source operand is the first one. */
7891 gas_assert ((i.imm_operands == 2
7892 && i.types[0].bitfield.imm8
7893 && i.types[1].bitfield.imm8)
7894 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7895 && i.imm_operands == 1
7896 && (i.types[0].bitfield.imm8
7897 || i.types[i.operands - 1].bitfield.imm8
7898 || i.rounding)));
7899 if (i.imm_operands == 2)
7900 source = 2;
7901 else
7902 {
7903 if (i.types[0].bitfield.imm8)
7904 source = 1;
7905 else
7906 source = 0;
7907 }
7908 break;
7909 case 5:
7910 if (is_evex_encoding (&i.tm))
7911 {
7912 /* For EVEX instructions, when there are 5 operands, the
7913 first one must be immediate operand. If the second one
7914 is immediate operand, the source operand is the 3th
7915 one. If the last one is immediate operand, the source
7916 operand is the 2nd one. */
7917 gas_assert (i.imm_operands == 2
7918 && i.tm.opcode_modifier.sae
7919 && operand_type_check (i.types[0], imm));
7920 if (operand_type_check (i.types[1], imm))
7921 source = 2;
7922 else if (operand_type_check (i.types[4], imm))
7923 source = 1;
7924 else
7925 abort ();
7926 }
7927 break;
7928 default:
7929 abort ();
7930 }
7931
7932 if (!vex_3_sources)
7933 {
7934 dest = source + 1;
7935
7936 /* RC/SAE operand could be between DEST and SRC. That happens
7937 when one operand is GPR and the other one is XMM/YMM/ZMM
7938 register. */
7939 if (i.rounding && i.rounding->operand == (int) dest)
7940 dest++;
7941
7942 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7943 {
7944 /* For instructions with VexNDS, the register-only source
7945 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7946 register. It is encoded in VEX prefix. */
7947
7948 i386_operand_type op;
7949 unsigned int vvvv;
7950
7951 /* Swap two source operands if needed. */
7952 if (i.tm.opcode_modifier.swapsources)
7953 {
7954 vvvv = source;
7955 source = dest;
7956 }
7957 else
7958 vvvv = dest;
7959
7960 op = i.tm.operand_types[vvvv];
7961 if ((dest + 1) >= i.operands
7962 || ((op.bitfield.class != Reg
7963 || (!op.bitfield.dword && !op.bitfield.qword))
7964 && op.bitfield.class != RegSIMD
7965 && !operand_type_equal (&op, &regmask)))
7966 abort ();
7967 i.vex.register_specifier = i.op[vvvv].regs;
7968 dest++;
7969 }
7970 }
7971
7972 i.rm.mode = 3;
7973 /* One of the register operands will be encoded in the i.rm.reg
7974 field, the other in the combined i.rm.mode and i.rm.regmem
7975 fields. If no form of this instruction supports a memory
7976 destination operand, then we assume the source operand may
7977 sometimes be a memory operand and so we need to store the
7978 destination in the i.rm.reg field. */
7979 if (!i.tm.opcode_modifier.regmem
7980 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7981 {
7982 i.rm.reg = i.op[dest].regs->reg_num;
7983 i.rm.regmem = i.op[source].regs->reg_num;
7984 set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
7985 set_rex_vrex (i.op[source].regs, REX_B, FALSE);
7986 }
7987 else
7988 {
7989 i.rm.reg = i.op[source].regs->reg_num;
7990 i.rm.regmem = i.op[dest].regs->reg_num;
7991 set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
7992 set_rex_vrex (i.op[source].regs, REX_R, FALSE);
7993 }
7994 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7995 {
7996 if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
7997 abort ();
7998 i.rex &= ~REX_R;
7999 add_prefix (LOCK_PREFIX_OPCODE);
8000 }
8001 }
8002 else
8003 { /* If it's not 2 reg operands... */
8004 unsigned int mem;
8005
8006 if (i.mem_operands)
8007 {
8008 unsigned int fake_zero_displacement = 0;
8009 unsigned int op;
8010
8011 for (op = 0; op < i.operands; op++)
8012 if (i.flags[op] & Operand_Mem)
8013 break;
8014 gas_assert (op < i.operands);
8015
8016 if (i.tm.opcode_modifier.sib)
8017 {
8018 /* The index register of VSIB shouldn't be RegIZ. */
8019 if (i.tm.opcode_modifier.sib != SIBMEM
8020 && i.index_reg->reg_num == RegIZ)
8021 abort ();
8022
8023 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8024 if (!i.base_reg)
8025 {
8026 i.sib.base = NO_BASE_REGISTER;
8027 i.sib.scale = i.log2_scale_factor;
8028 i.types[op].bitfield.disp8 = 0;
8029 i.types[op].bitfield.disp16 = 0;
8030 i.types[op].bitfield.disp64 = 0;
8031 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
8032 {
8033 /* Must be 32 bit */
8034 i.types[op].bitfield.disp32 = 1;
8035 i.types[op].bitfield.disp32s = 0;
8036 }
8037 else
8038 {
8039 i.types[op].bitfield.disp32 = 0;
8040 i.types[op].bitfield.disp32s = 1;
8041 }
8042 }
8043
8044 /* Since the mandatory SIB always has index register, so
8045 the code logic remains unchanged. The non-mandatory SIB
8046 without index register is allowed and will be handled
8047 later. */
8048 if (i.index_reg)
8049 {
8050 if (i.index_reg->reg_num == RegIZ)
8051 i.sib.index = NO_INDEX_REGISTER;
8052 else
8053 i.sib.index = i.index_reg->reg_num;
8054 set_rex_vrex (i.index_reg, REX_X, FALSE);
8055 }
8056 }
8057
8058 default_seg = &ds;
8059
8060 if (i.base_reg == 0)
8061 {
8062 i.rm.mode = 0;
8063 if (!i.disp_operands)
8064 fake_zero_displacement = 1;
8065 if (i.index_reg == 0)
8066 {
8067 i386_operand_type newdisp;
8068
8069 /* Both check for VSIB and mandatory non-vector SIB. */
8070 gas_assert (!i.tm.opcode_modifier.sib
8071 || i.tm.opcode_modifier.sib == SIBMEM);
8072 /* Operand is just <disp> */
8073 if (flag_code == CODE_64BIT)
8074 {
8075 /* 64bit mode overwrites the 32bit absolute
8076 addressing by RIP relative addressing and
8077 absolute addressing is encoded by one of the
8078 redundant SIB forms. */
8079 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8080 i.sib.base = NO_BASE_REGISTER;
8081 i.sib.index = NO_INDEX_REGISTER;
8082 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
8083 }
8084 else if ((flag_code == CODE_16BIT)
8085 ^ (i.prefix[ADDR_PREFIX] != 0))
8086 {
8087 i.rm.regmem = NO_BASE_REGISTER_16;
8088 newdisp = disp16;
8089 }
8090 else
8091 {
8092 i.rm.regmem = NO_BASE_REGISTER;
8093 newdisp = disp32;
8094 }
8095 i.types[op] = operand_type_and_not (i.types[op], anydisp);
8096 i.types[op] = operand_type_or (i.types[op], newdisp);
8097 }
8098 else if (!i.tm.opcode_modifier.sib)
8099 {
8100 /* !i.base_reg && i.index_reg */
8101 if (i.index_reg->reg_num == RegIZ)
8102 i.sib.index = NO_INDEX_REGISTER;
8103 else
8104 i.sib.index = i.index_reg->reg_num;
8105 i.sib.base = NO_BASE_REGISTER;
8106 i.sib.scale = i.log2_scale_factor;
8107 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8108 i.types[op].bitfield.disp8 = 0;
8109 i.types[op].bitfield.disp16 = 0;
8110 i.types[op].bitfield.disp64 = 0;
8111 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
8112 {
8113 /* Must be 32 bit */
8114 i.types[op].bitfield.disp32 = 1;
8115 i.types[op].bitfield.disp32s = 0;
8116 }
8117 else
8118 {
8119 i.types[op].bitfield.disp32 = 0;
8120 i.types[op].bitfield.disp32s = 1;
8121 }
8122 if ((i.index_reg->reg_flags & RegRex) != 0)
8123 i.rex |= REX_X;
8124 }
8125 }
8126 /* RIP addressing for 64bit mode. */
8127 else if (i.base_reg->reg_num == RegIP)
8128 {
8129 gas_assert (!i.tm.opcode_modifier.sib);
8130 i.rm.regmem = NO_BASE_REGISTER;
8131 i.types[op].bitfield.disp8 = 0;
8132 i.types[op].bitfield.disp16 = 0;
8133 i.types[op].bitfield.disp32 = 0;
8134 i.types[op].bitfield.disp32s = 1;
8135 i.types[op].bitfield.disp64 = 0;
8136 i.flags[op] |= Operand_PCrel;
8137 if (! i.disp_operands)
8138 fake_zero_displacement = 1;
8139 }
8140 else if (i.base_reg->reg_type.bitfield.word)
8141 {
8142 gas_assert (!i.tm.opcode_modifier.sib);
8143 switch (i.base_reg->reg_num)
8144 {
8145 case 3: /* (%bx) */
8146 if (i.index_reg == 0)
8147 i.rm.regmem = 7;
8148 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8149 i.rm.regmem = i.index_reg->reg_num - 6;
8150 break;
8151 case 5: /* (%bp) */
8152 default_seg = &ss;
8153 if (i.index_reg == 0)
8154 {
8155 i.rm.regmem = 6;
8156 if (operand_type_check (i.types[op], disp) == 0)
8157 {
8158 /* fake (%bp) into 0(%bp) */
8159 i.types[op].bitfield.disp8 = 1;
8160 fake_zero_displacement = 1;
8161 }
8162 }
8163 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8164 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
8165 break;
8166 default: /* (%si) -> 4 or (%di) -> 5 */
8167 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
8168 }
8169 i.rm.mode = mode_from_disp_size (i.types[op]);
8170 }
8171 else /* i.base_reg and 32/64 bit mode */
8172 {
8173 if (flag_code == CODE_64BIT
8174 && operand_type_check (i.types[op], disp))
8175 {
8176 i.types[op].bitfield.disp16 = 0;
8177 i.types[op].bitfield.disp64 = 0;
8178 if (i.prefix[ADDR_PREFIX] == 0)
8179 {
8180 i.types[op].bitfield.disp32 = 0;
8181 i.types[op].bitfield.disp32s = 1;
8182 }
8183 else
8184 {
8185 i.types[op].bitfield.disp32 = 1;
8186 i.types[op].bitfield.disp32s = 0;
8187 }
8188 }
8189
8190 if (!i.tm.opcode_modifier.sib)
8191 i.rm.regmem = i.base_reg->reg_num;
8192 if ((i.base_reg->reg_flags & RegRex) != 0)
8193 i.rex |= REX_B;
8194 i.sib.base = i.base_reg->reg_num;
8195 /* x86-64 ignores REX prefix bit here to avoid decoder
8196 complications. */
8197 if (!(i.base_reg->reg_flags & RegRex)
8198 && (i.base_reg->reg_num == EBP_REG_NUM
8199 || i.base_reg->reg_num == ESP_REG_NUM))
8200 default_seg = &ss;
8201 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
8202 {
8203 fake_zero_displacement = 1;
8204 i.types[op].bitfield.disp8 = 1;
8205 }
8206 i.sib.scale = i.log2_scale_factor;
8207 if (i.index_reg == 0)
8208 {
8209 /* Only check for VSIB. */
8210 gas_assert (i.tm.opcode_modifier.sib != VECSIB128
8211 && i.tm.opcode_modifier.sib != VECSIB256
8212 && i.tm.opcode_modifier.sib != VECSIB512);
8213
8214 /* <disp>(%esp) becomes two byte modrm with no index
8215 register. We've already stored the code for esp
8216 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8217 Any base register besides %esp will not use the
8218 extra modrm byte. */
8219 i.sib.index = NO_INDEX_REGISTER;
8220 }
8221 else if (!i.tm.opcode_modifier.sib)
8222 {
8223 if (i.index_reg->reg_num == RegIZ)
8224 i.sib.index = NO_INDEX_REGISTER;
8225 else
8226 i.sib.index = i.index_reg->reg_num;
8227 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8228 if ((i.index_reg->reg_flags & RegRex) != 0)
8229 i.rex |= REX_X;
8230 }
8231
8232 if (i.disp_operands
8233 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
8234 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
8235 i.rm.mode = 0;
8236 else
8237 {
8238 if (!fake_zero_displacement
8239 && !i.disp_operands
8240 && i.disp_encoding)
8241 {
8242 fake_zero_displacement = 1;
8243 if (i.disp_encoding == disp_encoding_8bit)
8244 i.types[op].bitfield.disp8 = 1;
8245 else
8246 i.types[op].bitfield.disp32 = 1;
8247 }
8248 i.rm.mode = mode_from_disp_size (i.types[op]);
8249 }
8250 }
8251
8252 if (fake_zero_displacement)
8253 {
8254 /* Fakes a zero displacement assuming that i.types[op]
8255 holds the correct displacement size. */
8256 expressionS *exp;
8257
8258 gas_assert (i.op[op].disps == 0);
8259 exp = &disp_expressions[i.disp_operands++];
8260 i.op[op].disps = exp;
8261 exp->X_op = O_constant;
8262 exp->X_add_number = 0;
8263 exp->X_add_symbol = (symbolS *) 0;
8264 exp->X_op_symbol = (symbolS *) 0;
8265 }
8266
8267 mem = op;
8268 }
8269 else
8270 mem = ~0;
8271
8272 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
8273 {
8274 if (operand_type_check (i.types[0], imm))
8275 i.vex.register_specifier = NULL;
8276 else
8277 {
8278 /* VEX.vvvv encodes one of the sources when the first
8279 operand is not an immediate. */
8280 if (i.tm.opcode_modifier.vexw == VEXW0)
8281 i.vex.register_specifier = i.op[0].regs;
8282 else
8283 i.vex.register_specifier = i.op[1].regs;
8284 }
8285
8286 /* Destination is a XMM register encoded in the ModRM.reg
8287 and VEX.R bit. */
8288 i.rm.reg = i.op[2].regs->reg_num;
8289 if ((i.op[2].regs->reg_flags & RegRex) != 0)
8290 i.rex |= REX_R;
8291
8292 /* ModRM.rm and VEX.B encodes the other source. */
8293 if (!i.mem_operands)
8294 {
8295 i.rm.mode = 3;
8296
8297 if (i.tm.opcode_modifier.vexw == VEXW0)
8298 i.rm.regmem = i.op[1].regs->reg_num;
8299 else
8300 i.rm.regmem = i.op[0].regs->reg_num;
8301
8302 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8303 i.rex |= REX_B;
8304 }
8305 }
8306 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
8307 {
8308 i.vex.register_specifier = i.op[2].regs;
8309 if (!i.mem_operands)
8310 {
8311 i.rm.mode = 3;
8312 i.rm.regmem = i.op[1].regs->reg_num;
8313 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8314 i.rex |= REX_B;
8315 }
8316 }
8317 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8318 (if any) based on i.tm.extension_opcode. Again, we must be
8319 careful to make sure that segment/control/debug/test/MMX
8320 registers are coded into the i.rm.reg field. */
8321 else if (i.reg_operands)
8322 {
8323 unsigned int op;
8324 unsigned int vex_reg = ~0;
8325
8326 for (op = 0; op < i.operands; op++)
8327 if (i.types[op].bitfield.class == Reg
8328 || i.types[op].bitfield.class == RegBND
8329 || i.types[op].bitfield.class == RegMask
8330 || i.types[op].bitfield.class == SReg
8331 || i.types[op].bitfield.class == RegCR
8332 || i.types[op].bitfield.class == RegDR
8333 || i.types[op].bitfield.class == RegTR
8334 || i.types[op].bitfield.class == RegSIMD
8335 || i.types[op].bitfield.class == RegMMX)
8336 break;
8337
8338 if (vex_3_sources)
8339 op = dest;
8340 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
8341 {
8342 /* For instructions with VexNDS, the register-only
8343 source operand is encoded in VEX prefix. */
8344 gas_assert (mem != (unsigned int) ~0);
8345
8346 if (op > mem)
8347 {
8348 vex_reg = op++;
8349 gas_assert (op < i.operands);
8350 }
8351 else
8352 {
8353 /* Check register-only source operand when two source
8354 operands are swapped. */
8355 if (!i.tm.operand_types[op].bitfield.baseindex
8356 && i.tm.operand_types[op + 1].bitfield.baseindex)
8357 {
8358 vex_reg = op;
8359 op += 2;
8360 gas_assert (mem == (vex_reg + 1)
8361 && op < i.operands);
8362 }
8363 else
8364 {
8365 vex_reg = op + 1;
8366 gas_assert (vex_reg < i.operands);
8367 }
8368 }
8369 }
8370 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
8371 {
8372 /* For instructions with VexNDD, the register destination
8373 is encoded in VEX prefix. */
8374 if (i.mem_operands == 0)
8375 {
8376 /* There is no memory operand. */
8377 gas_assert ((op + 2) == i.operands);
8378 vex_reg = op + 1;
8379 }
8380 else
8381 {
8382 /* There are only 2 non-immediate operands. */
8383 gas_assert (op < i.imm_operands + 2
8384 && i.operands == i.imm_operands + 2);
8385 vex_reg = i.imm_operands + 1;
8386 }
8387 }
8388 else
8389 gas_assert (op < i.operands);
8390
8391 if (vex_reg != (unsigned int) ~0)
8392 {
8393 i386_operand_type *type = &i.tm.operand_types[vex_reg];
8394
8395 if ((type->bitfield.class != Reg
8396 || (!type->bitfield.dword && !type->bitfield.qword))
8397 && type->bitfield.class != RegSIMD
8398 && !operand_type_equal (type, &regmask))
8399 abort ();
8400
8401 i.vex.register_specifier = i.op[vex_reg].regs;
8402 }
8403
8404 /* Don't set OP operand twice. */
8405 if (vex_reg != op)
8406 {
8407 /* If there is an extension opcode to put here, the
8408 register number must be put into the regmem field. */
8409 if (i.tm.extension_opcode != None)
8410 {
8411 i.rm.regmem = i.op[op].regs->reg_num;
8412 set_rex_vrex (i.op[op].regs, REX_B,
8413 i.tm.opcode_modifier.sse2avx);
8414 }
8415 else
8416 {
8417 i.rm.reg = i.op[op].regs->reg_num;
8418 set_rex_vrex (i.op[op].regs, REX_R,
8419 i.tm.opcode_modifier.sse2avx);
8420 }
8421 }
8422
8423 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8424 must set it to 3 to indicate this is a register operand
8425 in the regmem field. */
8426 if (!i.mem_operands)
8427 i.rm.mode = 3;
8428 }
8429
8430 /* Fill in i.rm.reg field with extension opcode (if any). */
8431 if (i.tm.extension_opcode != None)
8432 i.rm.reg = i.tm.extension_opcode;
8433 }
8434 return default_seg;
8435 }
8436
8437 static unsigned int
8438 flip_code16 (unsigned int code16)
8439 {
8440 gas_assert (i.tm.operands == 1);
8441
8442 return !(i.prefix[REX_PREFIX] & REX_W)
8443 && (code16 ? i.tm.operand_types[0].bitfield.disp32
8444 || i.tm.operand_types[0].bitfield.disp32s
8445 : i.tm.operand_types[0].bitfield.disp16)
8446 ? CODE16 : 0;
8447 }
8448
8449 static void
8450 output_branch (void)
8451 {
8452 char *p;
8453 int size;
8454 int code16;
8455 int prefix;
8456 relax_substateT subtype;
8457 symbolS *sym;
8458 offsetT off;
8459
8460 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
8461 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
8462
8463 prefix = 0;
8464 if (i.prefix[DATA_PREFIX] != 0)
8465 {
8466 prefix = 1;
8467 i.prefixes -= 1;
8468 code16 ^= flip_code16(code16);
8469 }
8470 /* Pentium4 branch hints. */
8471 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8472 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8473 {
8474 prefix++;
8475 i.prefixes--;
8476 }
8477 if (i.prefix[REX_PREFIX] != 0)
8478 {
8479 prefix++;
8480 i.prefixes--;
8481 }
8482
8483 /* BND prefixed jump. */
8484 if (i.prefix[BND_PREFIX] != 0)
8485 {
8486 prefix++;
8487 i.prefixes--;
8488 }
8489
8490 if (i.prefixes != 0)
8491 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8492
8493 /* It's always a symbol; End frag & setup for relax.
8494 Make sure there is enough room in this frag for the largest
8495 instruction we may generate in md_convert_frag. This is 2
8496 bytes for the opcode and room for the prefix and largest
8497 displacement. */
8498 frag_grow (prefix + 2 + 4);
8499 /* Prefix and 1 opcode byte go in fr_fix. */
8500 p = frag_more (prefix + 1);
8501 if (i.prefix[DATA_PREFIX] != 0)
8502 *p++ = DATA_PREFIX_OPCODE;
8503 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
8504 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
8505 *p++ = i.prefix[SEG_PREFIX];
8506 if (i.prefix[BND_PREFIX] != 0)
8507 *p++ = BND_PREFIX_OPCODE;
8508 if (i.prefix[REX_PREFIX] != 0)
8509 *p++ = i.prefix[REX_PREFIX];
8510 *p = i.tm.base_opcode;
8511
8512 if ((unsigned char) *p == JUMP_PC_RELATIVE)
8513 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
8514 else if (cpu_arch_flags.bitfield.cpui386)
8515 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
8516 else
8517 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
8518 subtype |= code16;
8519
8520 sym = i.op[0].disps->X_add_symbol;
8521 off = i.op[0].disps->X_add_number;
8522
8523 if (i.op[0].disps->X_op != O_constant
8524 && i.op[0].disps->X_op != O_symbol)
8525 {
8526 /* Handle complex expressions. */
8527 sym = make_expr_symbol (i.op[0].disps);
8528 off = 0;
8529 }
8530
8531 /* 1 possible extra opcode + 4 byte displacement go in var part.
8532 Pass reloc in fr_var. */
8533 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
8534 }
8535
8536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8537 /* Return TRUE iff PLT32 relocation should be used for branching to
8538 symbol S. */
8539
8540 static bfd_boolean
8541 need_plt32_p (symbolS *s)
8542 {
8543 /* PLT32 relocation is ELF only. */
8544 if (!IS_ELF)
8545 return FALSE;
8546
8547 #ifdef TE_SOLARIS
8548 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8549 krtld support it. */
8550 return FALSE;
8551 #endif
8552
8553 /* Since there is no need to prepare for PLT branch on x86-64, we
8554 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8555 be used as a marker for 32-bit PC-relative branches. */
8556 if (!object_64bit)
8557 return FALSE;
8558
8559 /* Weak or undefined symbol need PLT32 relocation. */
8560 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
8561 return TRUE;
8562
8563 /* Non-global symbol doesn't need PLT32 relocation. */
8564 if (! S_IS_EXTERNAL (s))
8565 return FALSE;
8566
8567 /* Other global symbols need PLT32 relocation. NB: Symbol with
8568 non-default visibilities are treated as normal global symbol
8569 so that PLT32 relocation can be used as a marker for 32-bit
8570 PC-relative branches. It is useful for linker relaxation. */
8571 return TRUE;
8572 }
8573 #endif
8574
8575 static void
8576 output_jump (void)
8577 {
8578 char *p;
8579 int size;
8580 fixS *fixP;
8581 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
8582
8583 if (i.tm.opcode_modifier.jump == JUMP_BYTE)
8584 {
8585 /* This is a loop or jecxz type instruction. */
8586 size = 1;
8587 if (i.prefix[ADDR_PREFIX] != 0)
8588 {
8589 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
8590 i.prefixes -= 1;
8591 }
8592 /* Pentium4 branch hints. */
8593 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8594 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8595 {
8596 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
8597 i.prefixes--;
8598 }
8599 }
8600 else
8601 {
8602 int code16;
8603
8604 code16 = 0;
8605 if (flag_code == CODE_16BIT)
8606 code16 = CODE16;
8607
8608 if (i.prefix[DATA_PREFIX] != 0)
8609 {
8610 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
8611 i.prefixes -= 1;
8612 code16 ^= flip_code16(code16);
8613 }
8614
8615 size = 4;
8616 if (code16)
8617 size = 2;
8618 }
8619
8620 /* BND prefixed jump. */
8621 if (i.prefix[BND_PREFIX] != 0)
8622 {
8623 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
8624 i.prefixes -= 1;
8625 }
8626
8627 if (i.prefix[REX_PREFIX] != 0)
8628 {
8629 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
8630 i.prefixes -= 1;
8631 }
8632
8633 if (i.prefixes != 0)
8634 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8635
8636 p = frag_more (i.tm.opcode_length + size);
8637 switch (i.tm.opcode_length)
8638 {
8639 case 2:
8640 *p++ = i.tm.base_opcode >> 8;
8641 /* Fall through. */
8642 case 1:
8643 *p++ = i.tm.base_opcode;
8644 break;
8645 default:
8646 abort ();
8647 }
8648
8649 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8650 if (size == 4
8651 && jump_reloc == NO_RELOC
8652 && need_plt32_p (i.op[0].disps->X_add_symbol))
8653 jump_reloc = BFD_RELOC_X86_64_PLT32;
8654 #endif
8655
8656 jump_reloc = reloc (size, 1, 1, jump_reloc);
8657
8658 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8659 i.op[0].disps, 1, jump_reloc);
8660
8661 /* All jumps handled here are signed, but don't use a signed limit
8662 check for 32 and 16 bit jumps as we want to allow wrap around at
8663 4G and 64k respectively. */
8664 if (size == 1)
8665 fixP->fx_signed = 1;
8666 }
8667
8668 static void
8669 output_interseg_jump (void)
8670 {
8671 char *p;
8672 int size;
8673 int prefix;
8674 int code16;
8675
8676 code16 = 0;
8677 if (flag_code == CODE_16BIT)
8678 code16 = CODE16;
8679
8680 prefix = 0;
8681 if (i.prefix[DATA_PREFIX] != 0)
8682 {
8683 prefix = 1;
8684 i.prefixes -= 1;
8685 code16 ^= CODE16;
8686 }
8687
8688 gas_assert (!i.prefix[REX_PREFIX]);
8689
8690 size = 4;
8691 if (code16)
8692 size = 2;
8693
8694 if (i.prefixes != 0)
8695 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8696
8697 /* 1 opcode; 2 segment; offset */
8698 p = frag_more (prefix + 1 + 2 + size);
8699
8700 if (i.prefix[DATA_PREFIX] != 0)
8701 *p++ = DATA_PREFIX_OPCODE;
8702
8703 if (i.prefix[REX_PREFIX] != 0)
8704 *p++ = i.prefix[REX_PREFIX];
8705
8706 *p++ = i.tm.base_opcode;
8707 if (i.op[1].imms->X_op == O_constant)
8708 {
8709 offsetT n = i.op[1].imms->X_add_number;
8710
8711 if (size == 2
8712 && !fits_in_unsigned_word (n)
8713 && !fits_in_signed_word (n))
8714 {
8715 as_bad (_("16-bit jump out of range"));
8716 return;
8717 }
8718 md_number_to_chars (p, n, size);
8719 }
8720 else
8721 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8722 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
8723 if (i.op[0].imms->X_op != O_constant)
8724 as_bad (_("can't handle non absolute segment in `%s'"),
8725 i.tm.name);
8726 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
8727 }
8728
8729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8730 void
8731 x86_cleanup (void)
8732 {
8733 char *p;
8734 asection *seg = now_seg;
8735 subsegT subseg = now_subseg;
8736 asection *sec;
8737 unsigned int alignment, align_size_1;
8738 unsigned int isa_1_descsz, feature_2_descsz, descsz;
8739 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
8740 unsigned int padding;
8741
8742 if (!IS_ELF || !x86_used_note)
8743 return;
8744
8745 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
8746
8747 /* The .note.gnu.property section layout:
8748
8749 Field Length Contents
8750 ---- ---- ----
8751 n_namsz 4 4
8752 n_descsz 4 The note descriptor size
8753 n_type 4 NT_GNU_PROPERTY_TYPE_0
8754 n_name 4 "GNU"
8755 n_desc n_descsz The program property array
8756 .... .... ....
8757 */
8758
8759 /* Create the .note.gnu.property section. */
8760 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
8761 bfd_set_section_flags (sec,
8762 (SEC_ALLOC
8763 | SEC_LOAD
8764 | SEC_DATA
8765 | SEC_HAS_CONTENTS
8766 | SEC_READONLY));
8767
8768 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
8769 {
8770 align_size_1 = 7;
8771 alignment = 3;
8772 }
8773 else
8774 {
8775 align_size_1 = 3;
8776 alignment = 2;
8777 }
8778
8779 bfd_set_section_alignment (sec, alignment);
8780 elf_section_type (sec) = SHT_NOTE;
8781
8782 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8783 + 4-byte data */
8784 isa_1_descsz_raw = 4 + 4 + 4;
8785 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8786 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
8787
8788 feature_2_descsz_raw = isa_1_descsz;
8789 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8790 + 4-byte data */
8791 feature_2_descsz_raw += 4 + 4 + 4;
8792 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8793 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
8794 & ~align_size_1);
8795
8796 descsz = feature_2_descsz;
8797 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8798 p = frag_more (4 + 4 + 4 + 4 + descsz);
8799
8800 /* Write n_namsz. */
8801 md_number_to_chars (p, (valueT) 4, 4);
8802
8803 /* Write n_descsz. */
8804 md_number_to_chars (p + 4, (valueT) descsz, 4);
8805
8806 /* Write n_type. */
8807 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
8808
8809 /* Write n_name. */
8810 memcpy (p + 4 * 3, "GNU", 4);
8811
8812 /* Write 4-byte type. */
8813 md_number_to_chars (p + 4 * 4,
8814 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
8815
8816 /* Write 4-byte data size. */
8817 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
8818
8819 /* Write 4-byte data. */
8820 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
8821
8822 /* Zero out paddings. */
8823 padding = isa_1_descsz - isa_1_descsz_raw;
8824 if (padding)
8825 memset (p + 4 * 7, 0, padding);
8826
8827 /* Write 4-byte type. */
8828 md_number_to_chars (p + isa_1_descsz + 4 * 4,
8829 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
8830
8831 /* Write 4-byte data size. */
8832 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8833
8834 /* Write 4-byte data. */
8835 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8836 (valueT) x86_feature_2_used, 4);
8837
8838 /* Zero out paddings. */
8839 padding = feature_2_descsz - feature_2_descsz_raw;
8840 if (padding)
8841 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8842
8843 /* We probably can't restore the current segment, for there likely
8844 isn't one yet... */
8845 if (seg && subseg)
8846 subseg_set (seg, subseg);
8847 }
8848 #endif
8849
8850 static unsigned int
8851 encoding_length (const fragS *start_frag, offsetT start_off,
8852 const char *frag_now_ptr)
8853 {
8854 unsigned int len = 0;
8855
8856 if (start_frag != frag_now)
8857 {
8858 const fragS *fr = start_frag;
8859
8860 do {
8861 len += fr->fr_fix;
8862 fr = fr->fr_next;
8863 } while (fr && fr != frag_now);
8864 }
8865
8866 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
8867 }
8868
8869 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8870 be macro-fused with conditional jumps.
8871 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8872 or is one of the following format:
8873
8874 cmp m, imm
8875 add m, imm
8876 sub m, imm
8877 test m, imm
8878 and m, imm
8879 inc m
8880 dec m
8881
8882 it is unfusible. */
8883
8884 static int
8885 maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
8886 {
8887 /* No RIP address. */
8888 if (i.base_reg && i.base_reg->reg_num == RegIP)
8889 return 0;
8890
8891 /* No VEX/EVEX encoding. */
8892 if (is_any_vex_encoding (&i.tm))
8893 return 0;
8894
8895 /* add, sub without add/sub m, imm. */
8896 if (i.tm.base_opcode <= 5
8897 || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
8898 || ((i.tm.base_opcode | 3) == 0x83
8899 && (i.tm.extension_opcode == 0x5
8900 || i.tm.extension_opcode == 0x0)))
8901 {
8902 *mf_cmp_p = mf_cmp_alu_cmp;
8903 return !(i.mem_operands && i.imm_operands);
8904 }
8905
8906 /* and without and m, imm. */
8907 if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
8908 || ((i.tm.base_opcode | 3) == 0x83
8909 && i.tm.extension_opcode == 0x4))
8910 {
8911 *mf_cmp_p = mf_cmp_test_and;
8912 return !(i.mem_operands && i.imm_operands);
8913 }
8914
8915 /* test without test m imm. */
8916 if ((i.tm.base_opcode | 1) == 0x85
8917 || (i.tm.base_opcode | 1) == 0xa9
8918 || ((i.tm.base_opcode | 1) == 0xf7
8919 && i.tm.extension_opcode == 0))
8920 {
8921 *mf_cmp_p = mf_cmp_test_and;
8922 return !(i.mem_operands && i.imm_operands);
8923 }
8924
8925 /* cmp without cmp m, imm. */
8926 if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
8927 || ((i.tm.base_opcode | 3) == 0x83
8928 && (i.tm.extension_opcode == 0x7)))
8929 {
8930 *mf_cmp_p = mf_cmp_alu_cmp;
8931 return !(i.mem_operands && i.imm_operands);
8932 }
8933
8934 /* inc, dec without inc/dec m. */
8935 if ((i.tm.cpu_flags.bitfield.cpuno64
8936 && (i.tm.base_opcode | 0xf) == 0x4f)
8937 || ((i.tm.base_opcode | 1) == 0xff
8938 && i.tm.extension_opcode <= 0x1))
8939 {
8940 *mf_cmp_p = mf_cmp_incdec;
8941 return !i.mem_operands;
8942 }
8943
8944 return 0;
8945 }
8946
8947 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8948
8949 static int
8950 add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p)
8951 {
8952 /* NB: Don't work with COND_JUMP86 without i386. */
8953 if (!align_branch_power
8954 || now_seg == absolute_section
8955 || !cpu_arch_flags.bitfield.cpui386
8956 || !(align_branch & align_branch_fused_bit))
8957 return 0;
8958
8959 if (maybe_fused_with_jcc_p (mf_cmp_p))
8960 {
8961 if (last_insn.kind == last_insn_other
8962 || last_insn.seg != now_seg)
8963 return 1;
8964 if (flag_debug)
8965 as_warn_where (last_insn.file, last_insn.line,
8966 _("`%s` skips -malign-branch-boundary on `%s`"),
8967 last_insn.name, i.tm.name);
8968 }
8969
8970 return 0;
8971 }
8972
8973 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8974
8975 static int
8976 add_branch_prefix_frag_p (void)
8977 {
8978 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8979 to PadLock instructions since they include prefixes in opcode. */
8980 if (!align_branch_power
8981 || !align_branch_prefix_size
8982 || now_seg == absolute_section
8983 || i.tm.cpu_flags.bitfield.cpupadlock
8984 || !cpu_arch_flags.bitfield.cpui386)
8985 return 0;
8986
8987 /* Don't add prefix if it is a prefix or there is no operand in case
8988 that segment prefix is special. */
8989 if (!i.operands || i.tm.opcode_modifier.isprefix)
8990 return 0;
8991
8992 if (last_insn.kind == last_insn_other
8993 || last_insn.seg != now_seg)
8994 return 1;
8995
8996 if (flag_debug)
8997 as_warn_where (last_insn.file, last_insn.line,
8998 _("`%s` skips -malign-branch-boundary on `%s`"),
8999 last_insn.name, i.tm.name);
9000
9001 return 0;
9002 }
9003
9004 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9005
9006 static int
9007 add_branch_padding_frag_p (enum align_branch_kind *branch_p,
9008 enum mf_jcc_kind *mf_jcc_p)
9009 {
9010 int add_padding;
9011
9012 /* NB: Don't work with COND_JUMP86 without i386. */
9013 if (!align_branch_power
9014 || now_seg == absolute_section
9015 || !cpu_arch_flags.bitfield.cpui386)
9016 return 0;
9017
9018 add_padding = 0;
9019
9020 /* Check for jcc and direct jmp. */
9021 if (i.tm.opcode_modifier.jump == JUMP)
9022 {
9023 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
9024 {
9025 *branch_p = align_branch_jmp;
9026 add_padding = align_branch & align_branch_jmp_bit;
9027 }
9028 else
9029 {
9030 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9031 igore the lowest bit. */
9032 *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
9033 *branch_p = align_branch_jcc;
9034 if ((align_branch & align_branch_jcc_bit))
9035 add_padding = 1;
9036 }
9037 }
9038 else if (is_any_vex_encoding (&i.tm))
9039 return 0;
9040 else if ((i.tm.base_opcode | 1) == 0xc3)
9041 {
9042 /* Near ret. */
9043 *branch_p = align_branch_ret;
9044 if ((align_branch & align_branch_ret_bit))
9045 add_padding = 1;
9046 }
9047 else
9048 {
9049 /* Check for indirect jmp, direct and indirect calls. */
9050 if (i.tm.base_opcode == 0xe8)
9051 {
9052 /* Direct call. */
9053 *branch_p = align_branch_call;
9054 if ((align_branch & align_branch_call_bit))
9055 add_padding = 1;
9056 }
9057 else if (i.tm.base_opcode == 0xff
9058 && (i.tm.extension_opcode == 2
9059 || i.tm.extension_opcode == 4))
9060 {
9061 /* Indirect call and jmp. */
9062 *branch_p = align_branch_indirect;
9063 if ((align_branch & align_branch_indirect_bit))
9064 add_padding = 1;
9065 }
9066
9067 if (add_padding
9068 && i.disp_operands
9069 && tls_get_addr
9070 && (i.op[0].disps->X_op == O_symbol
9071 || (i.op[0].disps->X_op == O_subtract
9072 && i.op[0].disps->X_op_symbol == GOT_symbol)))
9073 {
9074 symbolS *s = i.op[0].disps->X_add_symbol;
9075 /* No padding to call to global or undefined tls_get_addr. */
9076 if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
9077 && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
9078 return 0;
9079 }
9080 }
9081
9082 if (add_padding
9083 && last_insn.kind != last_insn_other
9084 && last_insn.seg == now_seg)
9085 {
9086 if (flag_debug)
9087 as_warn_where (last_insn.file, last_insn.line,
9088 _("`%s` skips -malign-branch-boundary on `%s`"),
9089 last_insn.name, i.tm.name);
9090 return 0;
9091 }
9092
9093 return add_padding;
9094 }
9095
9096 static void
9097 output_insn (void)
9098 {
9099 fragS *insn_start_frag;
9100 offsetT insn_start_off;
9101 fragS *fragP = NULL;
9102 enum align_branch_kind branch = align_branch_none;
9103 /* The initializer is arbitrary just to avoid uninitialized error.
9104 it's actually either assigned in add_branch_padding_frag_p
9105 or never be used. */
9106 enum mf_jcc_kind mf_jcc = mf_jcc_jo;
9107
9108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9109 if (IS_ELF && x86_used_note)
9110 {
9111 if (i.tm.cpu_flags.bitfield.cpucmov)
9112 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
9113 if (i.tm.cpu_flags.bitfield.cpusse)
9114 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
9115 if (i.tm.cpu_flags.bitfield.cpusse2)
9116 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
9117 if (i.tm.cpu_flags.bitfield.cpusse3)
9118 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
9119 if (i.tm.cpu_flags.bitfield.cpussse3)
9120 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
9121 if (i.tm.cpu_flags.bitfield.cpusse4_1)
9122 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
9123 if (i.tm.cpu_flags.bitfield.cpusse4_2)
9124 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
9125 if (i.tm.cpu_flags.bitfield.cpuavx)
9126 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
9127 if (i.tm.cpu_flags.bitfield.cpuavx2)
9128 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
9129 if (i.tm.cpu_flags.bitfield.cpufma)
9130 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
9131 if (i.tm.cpu_flags.bitfield.cpuavx512f)
9132 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
9133 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
9134 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
9135 if (i.tm.cpu_flags.bitfield.cpuavx512er)
9136 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
9137 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
9138 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
9139 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
9140 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
9141 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
9142 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
9143 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
9144 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
9145 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
9146 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
9147 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
9148 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
9149 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
9150 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
9151 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
9152 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
9153 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
9154 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
9155 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
9156 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
9157 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
9158 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
9159 if (i.tm.cpu_flags.bitfield.cpuavx512_bf16)
9160 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16;
9161
9162 if (i.tm.cpu_flags.bitfield.cpu8087
9163 || i.tm.cpu_flags.bitfield.cpu287
9164 || i.tm.cpu_flags.bitfield.cpu387
9165 || i.tm.cpu_flags.bitfield.cpu687
9166 || i.tm.cpu_flags.bitfield.cpufisttp)
9167 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
9168 if ((i.xstate & xstate_mmx)
9169 || i.tm.base_opcode == 0xf77 /* emms */
9170 || i.tm.base_opcode == 0xf0e /* femms */)
9171 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
9172 if ((i.xstate & xstate_xmm))
9173 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
9174 if ((i.xstate & xstate_ymm) == xstate_ymm)
9175 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
9176 if ((i.xstate & xstate_zmm) == xstate_zmm)
9177 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
9178 if (i.tm.cpu_flags.bitfield.cpufxsr)
9179 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
9180 if (i.tm.cpu_flags.bitfield.cpuxsave)
9181 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
9182 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
9183 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
9184 if (i.tm.cpu_flags.bitfield.cpuxsavec)
9185 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
9186
9187 if ((i.xstate & xstate_tmm) == xstate_tmm
9188 || i.tm.cpu_flags.bitfield.cpuamx_tile)
9189 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
9190 }
9191 #endif
9192
9193 /* Tie dwarf2 debug info to the address at the start of the insn.
9194 We can't do this after the insn has been output as the current
9195 frag may have been closed off. eg. by frag_var. */
9196 dwarf2_emit_insn (0);
9197
9198 insn_start_frag = frag_now;
9199 insn_start_off = frag_now_fix ();
9200
9201 if (add_branch_padding_frag_p (&branch, &mf_jcc))
9202 {
9203 char *p;
9204 /* Branch can be 8 bytes. Leave some room for prefixes. */
9205 unsigned int max_branch_padding_size = 14;
9206
9207 /* Align section to boundary. */
9208 record_alignment (now_seg, align_branch_power);
9209
9210 /* Make room for padding. */
9211 frag_grow (max_branch_padding_size);
9212
9213 /* Start of the padding. */
9214 p = frag_more (0);
9215
9216 fragP = frag_now;
9217
9218 frag_var (rs_machine_dependent, max_branch_padding_size, 0,
9219 ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
9220 NULL, 0, p);
9221
9222 fragP->tc_frag_data.mf_type = mf_jcc;
9223 fragP->tc_frag_data.branch_type = branch;
9224 fragP->tc_frag_data.max_bytes = max_branch_padding_size;
9225 }
9226
9227 /* Output jumps. */
9228 if (i.tm.opcode_modifier.jump == JUMP)
9229 output_branch ();
9230 else if (i.tm.opcode_modifier.jump == JUMP_BYTE
9231 || i.tm.opcode_modifier.jump == JUMP_DWORD)
9232 output_jump ();
9233 else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
9234 output_interseg_jump ();
9235 else
9236 {
9237 /* Output normal instructions here. */
9238 char *p;
9239 unsigned char *q;
9240 unsigned int j;
9241 unsigned int prefix;
9242 enum mf_cmp_kind mf_cmp;
9243
9244 if (avoid_fence
9245 && (i.tm.base_opcode == 0xfaee8
9246 || i.tm.base_opcode == 0xfaef0
9247 || i.tm.base_opcode == 0xfaef8))
9248 {
9249 /* Encode lfence, mfence, and sfence as
9250 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9251 offsetT val = 0x240483f0ULL;
9252 p = frag_more (5);
9253 md_number_to_chars (p, val, 5);
9254 return;
9255 }
9256
9257 /* Some processors fail on LOCK prefix. This options makes
9258 assembler ignore LOCK prefix and serves as a workaround. */
9259 if (omit_lock_prefix)
9260 {
9261 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
9262 return;
9263 i.prefix[LOCK_PREFIX] = 0;
9264 }
9265
9266 if (branch)
9267 /* Skip if this is a branch. */
9268 ;
9269 else if (add_fused_jcc_padding_frag_p (&mf_cmp))
9270 {
9271 /* Make room for padding. */
9272 frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
9273 p = frag_more (0);
9274
9275 fragP = frag_now;
9276
9277 frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
9278 ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
9279 NULL, 0, p);
9280
9281 fragP->tc_frag_data.mf_type = mf_cmp;
9282 fragP->tc_frag_data.branch_type = align_branch_fused;
9283 fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
9284 }
9285 else if (add_branch_prefix_frag_p ())
9286 {
9287 unsigned int max_prefix_size = align_branch_prefix_size;
9288
9289 /* Make room for padding. */
9290 frag_grow (max_prefix_size);
9291 p = frag_more (0);
9292
9293 fragP = frag_now;
9294
9295 frag_var (rs_machine_dependent, max_prefix_size, 0,
9296 ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
9297 NULL, 0, p);
9298
9299 fragP->tc_frag_data.max_bytes = max_prefix_size;
9300 }
9301
9302 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9303 don't need the explicit prefix. */
9304 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
9305 {
9306 switch (i.tm.opcode_length)
9307 {
9308 case 3:
9309 if (i.tm.base_opcode & 0xff000000)
9310 {
9311 prefix = (i.tm.base_opcode >> 24) & 0xff;
9312 if (!i.tm.cpu_flags.bitfield.cpupadlock
9313 || prefix != REPE_PREFIX_OPCODE
9314 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
9315 add_prefix (prefix);
9316 }
9317 break;
9318 case 2:
9319 if ((i.tm.base_opcode & 0xff0000) != 0)
9320 {
9321 prefix = (i.tm.base_opcode >> 16) & 0xff;
9322 add_prefix (prefix);
9323 }
9324 break;
9325 case 1:
9326 break;
9327 case 0:
9328 /* Check for pseudo prefixes. */
9329 as_bad_where (insn_start_frag->fr_file,
9330 insn_start_frag->fr_line,
9331 _("pseudo prefix without instruction"));
9332 return;
9333 default:
9334 abort ();
9335 }
9336
9337 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9338 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9339 R_X86_64_GOTTPOFF relocation so that linker can safely
9340 perform IE->LE optimization. A dummy REX_OPCODE prefix
9341 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9342 relocation for GDesc -> IE/LE optimization. */
9343 if (x86_elf_abi == X86_64_X32_ABI
9344 && i.operands == 2
9345 && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
9346 || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
9347 && i.prefix[REX_PREFIX] == 0)
9348 add_prefix (REX_OPCODE);
9349 #endif
9350
9351 /* The prefix bytes. */
9352 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
9353 if (*q)
9354 FRAG_APPEND_1_CHAR (*q);
9355 }
9356 else
9357 {
9358 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
9359 if (*q)
9360 switch (j)
9361 {
9362 case SEG_PREFIX:
9363 case ADDR_PREFIX:
9364 FRAG_APPEND_1_CHAR (*q);
9365 break;
9366 default:
9367 /* There should be no other prefixes for instructions
9368 with VEX prefix. */
9369 abort ();
9370 }
9371
9372 /* For EVEX instructions i.vrex should become 0 after
9373 build_evex_prefix. For VEX instructions upper 16 registers
9374 aren't available, so VREX should be 0. */
9375 if (i.vrex)
9376 abort ();
9377 /* Now the VEX prefix. */
9378 p = frag_more (i.vex.length);
9379 for (j = 0; j < i.vex.length; j++)
9380 p[j] = i.vex.bytes[j];
9381 }
9382
9383 /* Now the opcode; be careful about word order here! */
9384 if (i.tm.opcode_length == 1)
9385 {
9386 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
9387 }
9388 else
9389 {
9390 switch (i.tm.opcode_length)
9391 {
9392 case 4:
9393 p = frag_more (4);
9394 *p++ = (i.tm.base_opcode >> 24) & 0xff;
9395 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9396 break;
9397 case 3:
9398 p = frag_more (3);
9399 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9400 break;
9401 case 2:
9402 p = frag_more (2);
9403 break;
9404 default:
9405 abort ();
9406 break;
9407 }
9408
9409 /* Put out high byte first: can't use md_number_to_chars! */
9410 *p++ = (i.tm.base_opcode >> 8) & 0xff;
9411 *p = i.tm.base_opcode & 0xff;
9412 }
9413
9414 /* Now the modrm byte and sib byte (if present). */
9415 if (i.tm.opcode_modifier.modrm)
9416 {
9417 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
9418 | i.rm.reg << 3
9419 | i.rm.mode << 6));
9420 /* If i.rm.regmem == ESP (4)
9421 && i.rm.mode != (Register mode)
9422 && not 16 bit
9423 ==> need second modrm byte. */
9424 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
9425 && i.rm.mode != 3
9426 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
9427 FRAG_APPEND_1_CHAR ((i.sib.base << 0
9428 | i.sib.index << 3
9429 | i.sib.scale << 6));
9430 }
9431
9432 if (i.disp_operands)
9433 output_disp (insn_start_frag, insn_start_off);
9434
9435 if (i.imm_operands)
9436 output_imm (insn_start_frag, insn_start_off);
9437
9438 /*
9439 * frag_now_fix () returning plain abs_section_offset when we're in the
9440 * absolute section, and abs_section_offset not getting updated as data
9441 * gets added to the frag breaks the logic below.
9442 */
9443 if (now_seg != absolute_section)
9444 {
9445 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
9446 if (j > 15)
9447 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9448 j);
9449 else if (fragP)
9450 {
9451 /* NB: Don't add prefix with GOTPC relocation since
9452 output_disp() above depends on the fixed encoding
9453 length. Can't add prefix with TLS relocation since
9454 it breaks TLS linker optimization. */
9455 unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
9456 /* Prefix count on the current instruction. */
9457 unsigned int count = i.vex.length;
9458 unsigned int k;
9459 for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
9460 /* REX byte is encoded in VEX/EVEX prefix. */
9461 if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
9462 count++;
9463
9464 /* Count prefixes for extended opcode maps. */
9465 if (!i.vex.length)
9466 switch (i.tm.opcode_length)
9467 {
9468 case 3:
9469 if (((i.tm.base_opcode >> 16) & 0xff) == 0xf)
9470 {
9471 count++;
9472 switch ((i.tm.base_opcode >> 8) & 0xff)
9473 {
9474 case 0x38:
9475 case 0x3a:
9476 count++;
9477 break;
9478 default:
9479 break;
9480 }
9481 }
9482 break;
9483 case 2:
9484 if (((i.tm.base_opcode >> 8) & 0xff) == 0xf)
9485 count++;
9486 break;
9487 case 1:
9488 break;
9489 default:
9490 abort ();
9491 }
9492
9493 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
9494 == BRANCH_PREFIX)
9495 {
9496 /* Set the maximum prefix size in BRANCH_PREFIX
9497 frag. */
9498 if (fragP->tc_frag_data.max_bytes > max)
9499 fragP->tc_frag_data.max_bytes = max;
9500 if (fragP->tc_frag_data.max_bytes > count)
9501 fragP->tc_frag_data.max_bytes -= count;
9502 else
9503 fragP->tc_frag_data.max_bytes = 0;
9504 }
9505 else
9506 {
9507 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9508 frag. */
9509 unsigned int max_prefix_size;
9510 if (align_branch_prefix_size > max)
9511 max_prefix_size = max;
9512 else
9513 max_prefix_size = align_branch_prefix_size;
9514 if (max_prefix_size > count)
9515 fragP->tc_frag_data.max_prefix_length
9516 = max_prefix_size - count;
9517 }
9518
9519 /* Use existing segment prefix if possible. Use CS
9520 segment prefix in 64-bit mode. In 32-bit mode, use SS
9521 segment prefix with ESP/EBP base register and use DS
9522 segment prefix without ESP/EBP base register. */
9523 if (i.prefix[SEG_PREFIX])
9524 fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
9525 else if (flag_code == CODE_64BIT)
9526 fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
9527 else if (i.base_reg
9528 && (i.base_reg->reg_num == 4
9529 || i.base_reg->reg_num == 5))
9530 fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
9531 else
9532 fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
9533 }
9534 }
9535 }
9536
9537 /* NB: Don't work with COND_JUMP86 without i386. */
9538 if (align_branch_power
9539 && now_seg != absolute_section
9540 && cpu_arch_flags.bitfield.cpui386)
9541 {
9542 /* Terminate each frag so that we can add prefix and check for
9543 fused jcc. */
9544 frag_wane (frag_now);
9545 frag_new (0);
9546 }
9547
9548 #ifdef DEBUG386
9549 if (flag_debug)
9550 {
9551 pi ("" /*line*/, &i);
9552 }
9553 #endif /* DEBUG386 */
9554 }
9555
9556 /* Return the size of the displacement operand N. */
9557
9558 static int
9559 disp_size (unsigned int n)
9560 {
9561 int size = 4;
9562
9563 if (i.types[n].bitfield.disp64)
9564 size = 8;
9565 else if (i.types[n].bitfield.disp8)
9566 size = 1;
9567 else if (i.types[n].bitfield.disp16)
9568 size = 2;
9569 return size;
9570 }
9571
9572 /* Return the size of the immediate operand N. */
9573
9574 static int
9575 imm_size (unsigned int n)
9576 {
9577 int size = 4;
9578 if (i.types[n].bitfield.imm64)
9579 size = 8;
9580 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
9581 size = 1;
9582 else if (i.types[n].bitfield.imm16)
9583 size = 2;
9584 return size;
9585 }
9586
9587 static void
9588 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
9589 {
9590 char *p;
9591 unsigned int n;
9592
9593 for (n = 0; n < i.operands; n++)
9594 {
9595 if (operand_type_check (i.types[n], disp))
9596 {
9597 if (i.op[n].disps->X_op == O_constant)
9598 {
9599 int size = disp_size (n);
9600 offsetT val = i.op[n].disps->X_add_number;
9601
9602 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
9603 size);
9604 p = frag_more (size);
9605 md_number_to_chars (p, val, size);
9606 }
9607 else
9608 {
9609 enum bfd_reloc_code_real reloc_type;
9610 int size = disp_size (n);
9611 int sign = i.types[n].bitfield.disp32s;
9612 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
9613 fixS *fixP;
9614
9615 /* We can't have 8 bit displacement here. */
9616 gas_assert (!i.types[n].bitfield.disp8);
9617
9618 /* The PC relative address is computed relative
9619 to the instruction boundary, so in case immediate
9620 fields follows, we need to adjust the value. */
9621 if (pcrel && i.imm_operands)
9622 {
9623 unsigned int n1;
9624 int sz = 0;
9625
9626 for (n1 = 0; n1 < i.operands; n1++)
9627 if (operand_type_check (i.types[n1], imm))
9628 {
9629 /* Only one immediate is allowed for PC
9630 relative address. */
9631 gas_assert (sz == 0);
9632 sz = imm_size (n1);
9633 i.op[n].disps->X_add_number -= sz;
9634 }
9635 /* We should find the immediate. */
9636 gas_assert (sz != 0);
9637 }
9638
9639 p = frag_more (size);
9640 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
9641 if (GOT_symbol
9642 && GOT_symbol == i.op[n].disps->X_add_symbol
9643 && (((reloc_type == BFD_RELOC_32
9644 || reloc_type == BFD_RELOC_X86_64_32S
9645 || (reloc_type == BFD_RELOC_64
9646 && object_64bit))
9647 && (i.op[n].disps->X_op == O_symbol
9648 || (i.op[n].disps->X_op == O_add
9649 && ((symbol_get_value_expression
9650 (i.op[n].disps->X_op_symbol)->X_op)
9651 == O_subtract))))
9652 || reloc_type == BFD_RELOC_32_PCREL))
9653 {
9654 if (!object_64bit)
9655 {
9656 reloc_type = BFD_RELOC_386_GOTPC;
9657 i.has_gotpc_tls_reloc = TRUE;
9658 i.op[n].imms->X_add_number +=
9659 encoding_length (insn_start_frag, insn_start_off, p);
9660 }
9661 else if (reloc_type == BFD_RELOC_64)
9662 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9663 else
9664 /* Don't do the adjustment for x86-64, as there
9665 the pcrel addressing is relative to the _next_
9666 insn, and that is taken care of in other code. */
9667 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9668 }
9669 else if (align_branch_power)
9670 {
9671 switch (reloc_type)
9672 {
9673 case BFD_RELOC_386_TLS_GD:
9674 case BFD_RELOC_386_TLS_LDM:
9675 case BFD_RELOC_386_TLS_IE:
9676 case BFD_RELOC_386_TLS_IE_32:
9677 case BFD_RELOC_386_TLS_GOTIE:
9678 case BFD_RELOC_386_TLS_GOTDESC:
9679 case BFD_RELOC_386_TLS_DESC_CALL:
9680 case BFD_RELOC_X86_64_TLSGD:
9681 case BFD_RELOC_X86_64_TLSLD:
9682 case BFD_RELOC_X86_64_GOTTPOFF:
9683 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9684 case BFD_RELOC_X86_64_TLSDESC_CALL:
9685 i.has_gotpc_tls_reloc = TRUE;
9686 default:
9687 break;
9688 }
9689 }
9690 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
9691 size, i.op[n].disps, pcrel,
9692 reloc_type);
9693 /* Check for "call/jmp *mem", "mov mem, %reg",
9694 "test %reg, mem" and "binop mem, %reg" where binop
9695 is one of adc, add, and, cmp, or, sbb, sub, xor
9696 instructions without data prefix. Always generate
9697 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9698 if (i.prefix[DATA_PREFIX] == 0
9699 && (generate_relax_relocations
9700 || (!object_64bit
9701 && i.rm.mode == 0
9702 && i.rm.regmem == 5))
9703 && (i.rm.mode == 2
9704 || (i.rm.mode == 0 && i.rm.regmem == 5))
9705 && !is_any_vex_encoding(&i.tm)
9706 && ((i.operands == 1
9707 && i.tm.base_opcode == 0xff
9708 && (i.rm.reg == 2 || i.rm.reg == 4))
9709 || (i.operands == 2
9710 && (i.tm.base_opcode == 0x8b
9711 || i.tm.base_opcode == 0x85
9712 || (i.tm.base_opcode & ~0x38) == 0x03))))
9713 {
9714 if (object_64bit)
9715 {
9716 fixP->fx_tcbit = i.rex != 0;
9717 if (i.base_reg
9718 && (i.base_reg->reg_num == RegIP))
9719 fixP->fx_tcbit2 = 1;
9720 }
9721 else
9722 fixP->fx_tcbit2 = 1;
9723 }
9724 }
9725 }
9726 }
9727 }
9728
9729 static void
9730 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
9731 {
9732 char *p;
9733 unsigned int n;
9734
9735 for (n = 0; n < i.operands; n++)
9736 {
9737 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9738 if (i.rounding && (int) n == i.rounding->operand)
9739 continue;
9740
9741 if (operand_type_check (i.types[n], imm))
9742 {
9743 if (i.op[n].imms->X_op == O_constant)
9744 {
9745 int size = imm_size (n);
9746 offsetT val;
9747
9748 val = offset_in_range (i.op[n].imms->X_add_number,
9749 size);
9750 p = frag_more (size);
9751 md_number_to_chars (p, val, size);
9752 }
9753 else
9754 {
9755 /* Not absolute_section.
9756 Need a 32-bit fixup (don't support 8bit
9757 non-absolute imms). Try to support other
9758 sizes ... */
9759 enum bfd_reloc_code_real reloc_type;
9760 int size = imm_size (n);
9761 int sign;
9762
9763 if (i.types[n].bitfield.imm32s
9764 && (i.suffix == QWORD_MNEM_SUFFIX
9765 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
9766 sign = 1;
9767 else
9768 sign = 0;
9769
9770 p = frag_more (size);
9771 reloc_type = reloc (size, 0, sign, i.reloc[n]);
9772
9773 /* This is tough to explain. We end up with this one if we
9774 * have operands that look like
9775 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9776 * obtain the absolute address of the GOT, and it is strongly
9777 * preferable from a performance point of view to avoid using
9778 * a runtime relocation for this. The actual sequence of
9779 * instructions often look something like:
9780 *
9781 * call .L66
9782 * .L66:
9783 * popl %ebx
9784 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9785 *
9786 * The call and pop essentially return the absolute address
9787 * of the label .L66 and store it in %ebx. The linker itself
9788 * will ultimately change the first operand of the addl so
9789 * that %ebx points to the GOT, but to keep things simple, the
9790 * .o file must have this operand set so that it generates not
9791 * the absolute address of .L66, but the absolute address of
9792 * itself. This allows the linker itself simply treat a GOTPC
9793 * relocation as asking for a pcrel offset to the GOT to be
9794 * added in, and the addend of the relocation is stored in the
9795 * operand field for the instruction itself.
9796 *
9797 * Our job here is to fix the operand so that it would add
9798 * the correct offset so that %ebx would point to itself. The
9799 * thing that is tricky is that .-.L66 will point to the
9800 * beginning of the instruction, so we need to further modify
9801 * the operand so that it will point to itself. There are
9802 * other cases where you have something like:
9803 *
9804 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9805 *
9806 * and here no correction would be required. Internally in
9807 * the assembler we treat operands of this form as not being
9808 * pcrel since the '.' is explicitly mentioned, and I wonder
9809 * whether it would simplify matters to do it this way. Who
9810 * knows. In earlier versions of the PIC patches, the
9811 * pcrel_adjust field was used to store the correction, but
9812 * since the expression is not pcrel, I felt it would be
9813 * confusing to do it this way. */
9814
9815 if ((reloc_type == BFD_RELOC_32
9816 || reloc_type == BFD_RELOC_X86_64_32S
9817 || reloc_type == BFD_RELOC_64)
9818 && GOT_symbol
9819 && GOT_symbol == i.op[n].imms->X_add_symbol
9820 && (i.op[n].imms->X_op == O_symbol
9821 || (i.op[n].imms->X_op == O_add
9822 && ((symbol_get_value_expression
9823 (i.op[n].imms->X_op_symbol)->X_op)
9824 == O_subtract))))
9825 {
9826 if (!object_64bit)
9827 reloc_type = BFD_RELOC_386_GOTPC;
9828 else if (size == 4)
9829 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9830 else if (size == 8)
9831 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9832 i.has_gotpc_tls_reloc = TRUE;
9833 i.op[n].imms->X_add_number +=
9834 encoding_length (insn_start_frag, insn_start_off, p);
9835 }
9836 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
9837 i.op[n].imms, 0, reloc_type);
9838 }
9839 }
9840 }
9841 }
9842 \f
9843 /* x86_cons_fix_new is called via the expression parsing code when a
9844 reloc is needed. We use this hook to get the correct .got reloc. */
9845 static int cons_sign = -1;
9846
9847 void
9848 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
9849 expressionS *exp, bfd_reloc_code_real_type r)
9850 {
9851 r = reloc (len, 0, cons_sign, r);
9852
9853 #ifdef TE_PE
9854 if (exp->X_op == O_secrel)
9855 {
9856 exp->X_op = O_symbol;
9857 r = BFD_RELOC_32_SECREL;
9858 }
9859 #endif
9860
9861 fix_new_exp (frag, off, len, exp, 0, r);
9862 }
9863
9864 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9865 purpose of the `.dc.a' internal pseudo-op. */
9866
9867 int
9868 x86_address_bytes (void)
9869 {
9870 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
9871 return 4;
9872 return stdoutput->arch_info->bits_per_address / 8;
9873 }
9874
9875 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9876 || defined (LEX_AT)
9877 # define lex_got(reloc, adjust, types) NULL
9878 #else
9879 /* Parse operands of the form
9880 <symbol>@GOTOFF+<nnn>
9881 and similar .plt or .got references.
9882
9883 If we find one, set up the correct relocation in RELOC and copy the
9884 input string, minus the `@GOTOFF' into a malloc'd buffer for
9885 parsing by the calling routine. Return this buffer, and if ADJUST
9886 is non-null set it to the length of the string we removed from the
9887 input line. Otherwise return NULL. */
9888 static char *
9889 lex_got (enum bfd_reloc_code_real *rel,
9890 int *adjust,
9891 i386_operand_type *types)
9892 {
9893 /* Some of the relocations depend on the size of what field is to
9894 be relocated. But in our callers i386_immediate and i386_displacement
9895 we don't yet know the operand size (this will be set by insn
9896 matching). Hence we record the word32 relocation here,
9897 and adjust the reloc according to the real size in reloc(). */
9898 static const struct {
9899 const char *str;
9900 int len;
9901 const enum bfd_reloc_code_real rel[2];
9902 const i386_operand_type types64;
9903 } gotrel[] = {
9904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9905 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
9906 BFD_RELOC_SIZE32 },
9907 OPERAND_TYPE_IMM32_64 },
9908 #endif
9909 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
9910 BFD_RELOC_X86_64_PLTOFF64 },
9911 OPERAND_TYPE_IMM64 },
9912 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
9913 BFD_RELOC_X86_64_PLT32 },
9914 OPERAND_TYPE_IMM32_32S_DISP32 },
9915 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
9916 BFD_RELOC_X86_64_GOTPLT64 },
9917 OPERAND_TYPE_IMM64_DISP64 },
9918 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
9919 BFD_RELOC_X86_64_GOTOFF64 },
9920 OPERAND_TYPE_IMM64_DISP64 },
9921 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
9922 BFD_RELOC_X86_64_GOTPCREL },
9923 OPERAND_TYPE_IMM32_32S_DISP32 },
9924 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
9925 BFD_RELOC_X86_64_TLSGD },
9926 OPERAND_TYPE_IMM32_32S_DISP32 },
9927 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
9928 _dummy_first_bfd_reloc_code_real },
9929 OPERAND_TYPE_NONE },
9930 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
9931 BFD_RELOC_X86_64_TLSLD },
9932 OPERAND_TYPE_IMM32_32S_DISP32 },
9933 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
9934 BFD_RELOC_X86_64_GOTTPOFF },
9935 OPERAND_TYPE_IMM32_32S_DISP32 },
9936 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
9937 BFD_RELOC_X86_64_TPOFF32 },
9938 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9939 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
9940 _dummy_first_bfd_reloc_code_real },
9941 OPERAND_TYPE_NONE },
9942 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
9943 BFD_RELOC_X86_64_DTPOFF32 },
9944 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9945 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
9946 _dummy_first_bfd_reloc_code_real },
9947 OPERAND_TYPE_NONE },
9948 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
9949 _dummy_first_bfd_reloc_code_real },
9950 OPERAND_TYPE_NONE },
9951 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
9952 BFD_RELOC_X86_64_GOT32 },
9953 OPERAND_TYPE_IMM32_32S_64_DISP32 },
9954 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
9955 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
9956 OPERAND_TYPE_IMM32_32S_DISP32 },
9957 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
9958 BFD_RELOC_X86_64_TLSDESC_CALL },
9959 OPERAND_TYPE_IMM32_32S_DISP32 },
9960 };
9961 char *cp;
9962 unsigned int j;
9963
9964 #if defined (OBJ_MAYBE_ELF)
9965 if (!IS_ELF)
9966 return NULL;
9967 #endif
9968
9969 for (cp = input_line_pointer; *cp != '@'; cp++)
9970 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9971 return NULL;
9972
9973 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9974 {
9975 int len = gotrel[j].len;
9976 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9977 {
9978 if (gotrel[j].rel[object_64bit] != 0)
9979 {
9980 int first, second;
9981 char *tmpbuf, *past_reloc;
9982
9983 *rel = gotrel[j].rel[object_64bit];
9984
9985 if (types)
9986 {
9987 if (flag_code != CODE_64BIT)
9988 {
9989 types->bitfield.imm32 = 1;
9990 types->bitfield.disp32 = 1;
9991 }
9992 else
9993 *types = gotrel[j].types64;
9994 }
9995
9996 if (j != 0 && GOT_symbol == NULL)
9997 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
9998
9999 /* The length of the first part of our input line. */
10000 first = cp - input_line_pointer;
10001
10002 /* The second part goes from after the reloc token until
10003 (and including) an end_of_line char or comma. */
10004 past_reloc = cp + 1 + len;
10005 cp = past_reloc;
10006 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
10007 ++cp;
10008 second = cp + 1 - past_reloc;
10009
10010 /* Allocate and copy string. The trailing NUL shouldn't
10011 be necessary, but be safe. */
10012 tmpbuf = XNEWVEC (char, first + second + 2);
10013 memcpy (tmpbuf, input_line_pointer, first);
10014 if (second != 0 && *past_reloc != ' ')
10015 /* Replace the relocation token with ' ', so that
10016 errors like foo@GOTOFF1 will be detected. */
10017 tmpbuf[first++] = ' ';
10018 else
10019 /* Increment length by 1 if the relocation token is
10020 removed. */
10021 len++;
10022 if (adjust)
10023 *adjust = len;
10024 memcpy (tmpbuf + first, past_reloc, second);
10025 tmpbuf[first + second] = '\0';
10026 return tmpbuf;
10027 }
10028
10029 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10030 gotrel[j].str, 1 << (5 + object_64bit));
10031 return NULL;
10032 }
10033 }
10034
10035 /* Might be a symbol version string. Don't as_bad here. */
10036 return NULL;
10037 }
10038 #endif
10039
10040 #ifdef TE_PE
10041 #ifdef lex_got
10042 #undef lex_got
10043 #endif
10044 /* Parse operands of the form
10045 <symbol>@SECREL32+<nnn>
10046
10047 If we find one, set up the correct relocation in RELOC and copy the
10048 input string, minus the `@SECREL32' into a malloc'd buffer for
10049 parsing by the calling routine. Return this buffer, and if ADJUST
10050 is non-null set it to the length of the string we removed from the
10051 input line. Otherwise return NULL.
10052
10053 This function is copied from the ELF version above adjusted for PE targets. */
10054
10055 static char *
10056 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
10057 int *adjust ATTRIBUTE_UNUSED,
10058 i386_operand_type *types)
10059 {
10060 static const struct
10061 {
10062 const char *str;
10063 int len;
10064 const enum bfd_reloc_code_real rel[2];
10065 const i386_operand_type types64;
10066 }
10067 gotrel[] =
10068 {
10069 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
10070 BFD_RELOC_32_SECREL },
10071 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
10072 };
10073
10074 char *cp;
10075 unsigned j;
10076
10077 for (cp = input_line_pointer; *cp != '@'; cp++)
10078 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
10079 return NULL;
10080
10081 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
10082 {
10083 int len = gotrel[j].len;
10084
10085 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
10086 {
10087 if (gotrel[j].rel[object_64bit] != 0)
10088 {
10089 int first, second;
10090 char *tmpbuf, *past_reloc;
10091
10092 *rel = gotrel[j].rel[object_64bit];
10093 if (adjust)
10094 *adjust = len;
10095
10096 if (types)
10097 {
10098 if (flag_code != CODE_64BIT)
10099 {
10100 types->bitfield.imm32 = 1;
10101 types->bitfield.disp32 = 1;
10102 }
10103 else
10104 *types = gotrel[j].types64;
10105 }
10106
10107 /* The length of the first part of our input line. */
10108 first = cp - input_line_pointer;
10109
10110 /* The second part goes from after the reloc token until
10111 (and including) an end_of_line char or comma. */
10112 past_reloc = cp + 1 + len;
10113 cp = past_reloc;
10114 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
10115 ++cp;
10116 second = cp + 1 - past_reloc;
10117
10118 /* Allocate and copy string. The trailing NUL shouldn't
10119 be necessary, but be safe. */
10120 tmpbuf = XNEWVEC (char, first + second + 2);
10121 memcpy (tmpbuf, input_line_pointer, first);
10122 if (second != 0 && *past_reloc != ' ')
10123 /* Replace the relocation token with ' ', so that
10124 errors like foo@SECLREL321 will be detected. */
10125 tmpbuf[first++] = ' ';
10126 memcpy (tmpbuf + first, past_reloc, second);
10127 tmpbuf[first + second] = '\0';
10128 return tmpbuf;
10129 }
10130
10131 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10132 gotrel[j].str, 1 << (5 + object_64bit));
10133 return NULL;
10134 }
10135 }
10136
10137 /* Might be a symbol version string. Don't as_bad here. */
10138 return NULL;
10139 }
10140
10141 #endif /* TE_PE */
10142
10143 bfd_reloc_code_real_type
10144 x86_cons (expressionS *exp, int size)
10145 {
10146 bfd_reloc_code_real_type got_reloc = NO_RELOC;
10147
10148 intel_syntax = -intel_syntax;
10149
10150 exp->X_md = 0;
10151 if (size == 4 || (object_64bit && size == 8))
10152 {
10153 /* Handle @GOTOFF and the like in an expression. */
10154 char *save;
10155 char *gotfree_input_line;
10156 int adjust = 0;
10157
10158 save = input_line_pointer;
10159 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
10160 if (gotfree_input_line)
10161 input_line_pointer = gotfree_input_line;
10162
10163 expression (exp);
10164
10165 if (gotfree_input_line)
10166 {
10167 /* expression () has merrily parsed up to the end of line,
10168 or a comma - in the wrong buffer. Transfer how far
10169 input_line_pointer has moved to the right buffer. */
10170 input_line_pointer = (save
10171 + (input_line_pointer - gotfree_input_line)
10172 + adjust);
10173 free (gotfree_input_line);
10174 if (exp->X_op == O_constant
10175 || exp->X_op == O_absent
10176 || exp->X_op == O_illegal
10177 || exp->X_op == O_register
10178 || exp->X_op == O_big)
10179 {
10180 char c = *input_line_pointer;
10181 *input_line_pointer = 0;
10182 as_bad (_("missing or invalid expression `%s'"), save);
10183 *input_line_pointer = c;
10184 }
10185 else if ((got_reloc == BFD_RELOC_386_PLT32
10186 || got_reloc == BFD_RELOC_X86_64_PLT32)
10187 && exp->X_op != O_symbol)
10188 {
10189 char c = *input_line_pointer;
10190 *input_line_pointer = 0;
10191 as_bad (_("invalid PLT expression `%s'"), save);
10192 *input_line_pointer = c;
10193 }
10194 }
10195 }
10196 else
10197 expression (exp);
10198
10199 intel_syntax = -intel_syntax;
10200
10201 if (intel_syntax)
10202 i386_intel_simplify (exp);
10203
10204 return got_reloc;
10205 }
10206
10207 static void
10208 signed_cons (int size)
10209 {
10210 if (flag_code == CODE_64BIT)
10211 cons_sign = 1;
10212 cons (size);
10213 cons_sign = -1;
10214 }
10215
10216 #ifdef TE_PE
10217 static void
10218 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
10219 {
10220 expressionS exp;
10221
10222 do
10223 {
10224 expression (&exp);
10225 if (exp.X_op == O_symbol)
10226 exp.X_op = O_secrel;
10227
10228 emit_expr (&exp, 4);
10229 }
10230 while (*input_line_pointer++ == ',');
10231
10232 input_line_pointer--;
10233 demand_empty_rest_of_line ();
10234 }
10235 #endif
10236
10237 /* Handle Vector operations. */
10238
10239 static char *
10240 check_VecOperations (char *op_string, char *op_end)
10241 {
10242 const reg_entry *mask;
10243 const char *saved;
10244 char *end_op;
10245
10246 while (*op_string
10247 && (op_end == NULL || op_string < op_end))
10248 {
10249 saved = op_string;
10250 if (*op_string == '{')
10251 {
10252 op_string++;
10253
10254 /* Check broadcasts. */
10255 if (strncmp (op_string, "1to", 3) == 0)
10256 {
10257 int bcst_type;
10258
10259 if (i.broadcast)
10260 goto duplicated_vec_op;
10261
10262 op_string += 3;
10263 if (*op_string == '8')
10264 bcst_type = 8;
10265 else if (*op_string == '4')
10266 bcst_type = 4;
10267 else if (*op_string == '2')
10268 bcst_type = 2;
10269 else if (*op_string == '1'
10270 && *(op_string+1) == '6')
10271 {
10272 bcst_type = 16;
10273 op_string++;
10274 }
10275 else
10276 {
10277 as_bad (_("Unsupported broadcast: `%s'"), saved);
10278 return NULL;
10279 }
10280 op_string++;
10281
10282 broadcast_op.type = bcst_type;
10283 broadcast_op.operand = this_operand;
10284 broadcast_op.bytes = 0;
10285 i.broadcast = &broadcast_op;
10286 }
10287 /* Check masking operation. */
10288 else if ((mask = parse_register (op_string, &end_op)) != NULL)
10289 {
10290 if (mask == &bad_reg)
10291 return NULL;
10292
10293 /* k0 can't be used for write mask. */
10294 if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
10295 {
10296 as_bad (_("`%s%s' can't be used for write mask"),
10297 register_prefix, mask->reg_name);
10298 return NULL;
10299 }
10300
10301 if (!i.mask)
10302 {
10303 mask_op.mask = mask;
10304 mask_op.zeroing = 0;
10305 mask_op.operand = this_operand;
10306 i.mask = &mask_op;
10307 }
10308 else
10309 {
10310 if (i.mask->mask)
10311 goto duplicated_vec_op;
10312
10313 i.mask->mask = mask;
10314
10315 /* Only "{z}" is allowed here. No need to check
10316 zeroing mask explicitly. */
10317 if (i.mask->operand != this_operand)
10318 {
10319 as_bad (_("invalid write mask `%s'"), saved);
10320 return NULL;
10321 }
10322 }
10323
10324 op_string = end_op;
10325 }
10326 /* Check zeroing-flag for masking operation. */
10327 else if (*op_string == 'z')
10328 {
10329 if (!i.mask)
10330 {
10331 mask_op.mask = NULL;
10332 mask_op.zeroing = 1;
10333 mask_op.operand = this_operand;
10334 i.mask = &mask_op;
10335 }
10336 else
10337 {
10338 if (i.mask->zeroing)
10339 {
10340 duplicated_vec_op:
10341 as_bad (_("duplicated `%s'"), saved);
10342 return NULL;
10343 }
10344
10345 i.mask->zeroing = 1;
10346
10347 /* Only "{%k}" is allowed here. No need to check mask
10348 register explicitly. */
10349 if (i.mask->operand != this_operand)
10350 {
10351 as_bad (_("invalid zeroing-masking `%s'"),
10352 saved);
10353 return NULL;
10354 }
10355 }
10356
10357 op_string++;
10358 }
10359 else
10360 goto unknown_vec_op;
10361
10362 if (*op_string != '}')
10363 {
10364 as_bad (_("missing `}' in `%s'"), saved);
10365 return NULL;
10366 }
10367 op_string++;
10368
10369 /* Strip whitespace since the addition of pseudo prefixes
10370 changed how the scrubber treats '{'. */
10371 if (is_space_char (*op_string))
10372 ++op_string;
10373
10374 continue;
10375 }
10376 unknown_vec_op:
10377 /* We don't know this one. */
10378 as_bad (_("unknown vector operation: `%s'"), saved);
10379 return NULL;
10380 }
10381
10382 if (i.mask && i.mask->zeroing && !i.mask->mask)
10383 {
10384 as_bad (_("zeroing-masking only allowed with write mask"));
10385 return NULL;
10386 }
10387
10388 return op_string;
10389 }
10390
10391 static int
10392 i386_immediate (char *imm_start)
10393 {
10394 char *save_input_line_pointer;
10395 char *gotfree_input_line;
10396 segT exp_seg = 0;
10397 expressionS *exp;
10398 i386_operand_type types;
10399
10400 operand_type_set (&types, ~0);
10401
10402 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
10403 {
10404 as_bad (_("at most %d immediate operands are allowed"),
10405 MAX_IMMEDIATE_OPERANDS);
10406 return 0;
10407 }
10408
10409 exp = &im_expressions[i.imm_operands++];
10410 i.op[this_operand].imms = exp;
10411
10412 if (is_space_char (*imm_start))
10413 ++imm_start;
10414
10415 save_input_line_pointer = input_line_pointer;
10416 input_line_pointer = imm_start;
10417
10418 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10419 if (gotfree_input_line)
10420 input_line_pointer = gotfree_input_line;
10421
10422 exp_seg = expression (exp);
10423
10424 SKIP_WHITESPACE ();
10425
10426 /* Handle vector operations. */
10427 if (*input_line_pointer == '{')
10428 {
10429 input_line_pointer = check_VecOperations (input_line_pointer,
10430 NULL);
10431 if (input_line_pointer == NULL)
10432 return 0;
10433 }
10434
10435 if (*input_line_pointer)
10436 as_bad (_("junk `%s' after expression"), input_line_pointer);
10437
10438 input_line_pointer = save_input_line_pointer;
10439 if (gotfree_input_line)
10440 {
10441 free (gotfree_input_line);
10442
10443 if (exp->X_op == O_constant || exp->X_op == O_register)
10444 exp->X_op = O_illegal;
10445 }
10446
10447 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
10448 }
10449
10450 static int
10451 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10452 i386_operand_type types, const char *imm_start)
10453 {
10454 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
10455 {
10456 if (imm_start)
10457 as_bad (_("missing or invalid immediate expression `%s'"),
10458 imm_start);
10459 return 0;
10460 }
10461 else if (exp->X_op == O_constant)
10462 {
10463 /* Size it properly later. */
10464 i.types[this_operand].bitfield.imm64 = 1;
10465 /* If not 64bit, sign extend val. */
10466 if (flag_code != CODE_64BIT
10467 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
10468 exp->X_add_number
10469 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
10470 }
10471 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10472 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
10473 && exp_seg != absolute_section
10474 && exp_seg != text_section
10475 && exp_seg != data_section
10476 && exp_seg != bss_section
10477 && exp_seg != undefined_section
10478 && !bfd_is_com_section (exp_seg))
10479 {
10480 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10481 return 0;
10482 }
10483 #endif
10484 else if (!intel_syntax && exp_seg == reg_section)
10485 {
10486 if (imm_start)
10487 as_bad (_("illegal immediate register operand %s"), imm_start);
10488 return 0;
10489 }
10490 else
10491 {
10492 /* This is an address. The size of the address will be
10493 determined later, depending on destination register,
10494 suffix, or the default for the section. */
10495 i.types[this_operand].bitfield.imm8 = 1;
10496 i.types[this_operand].bitfield.imm16 = 1;
10497 i.types[this_operand].bitfield.imm32 = 1;
10498 i.types[this_operand].bitfield.imm32s = 1;
10499 i.types[this_operand].bitfield.imm64 = 1;
10500 i.types[this_operand] = operand_type_and (i.types[this_operand],
10501 types);
10502 }
10503
10504 return 1;
10505 }
10506
10507 static char *
10508 i386_scale (char *scale)
10509 {
10510 offsetT val;
10511 char *save = input_line_pointer;
10512
10513 input_line_pointer = scale;
10514 val = get_absolute_expression ();
10515
10516 switch (val)
10517 {
10518 case 1:
10519 i.log2_scale_factor = 0;
10520 break;
10521 case 2:
10522 i.log2_scale_factor = 1;
10523 break;
10524 case 4:
10525 i.log2_scale_factor = 2;
10526 break;
10527 case 8:
10528 i.log2_scale_factor = 3;
10529 break;
10530 default:
10531 {
10532 char sep = *input_line_pointer;
10533
10534 *input_line_pointer = '\0';
10535 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10536 scale);
10537 *input_line_pointer = sep;
10538 input_line_pointer = save;
10539 return NULL;
10540 }
10541 }
10542 if (i.log2_scale_factor != 0 && i.index_reg == 0)
10543 {
10544 as_warn (_("scale factor of %d without an index register"),
10545 1 << i.log2_scale_factor);
10546 i.log2_scale_factor = 0;
10547 }
10548 scale = input_line_pointer;
10549 input_line_pointer = save;
10550 return scale;
10551 }
10552
10553 static int
10554 i386_displacement (char *disp_start, char *disp_end)
10555 {
10556 expressionS *exp;
10557 segT exp_seg = 0;
10558 char *save_input_line_pointer;
10559 char *gotfree_input_line;
10560 int override;
10561 i386_operand_type bigdisp, types = anydisp;
10562 int ret;
10563
10564 if (i.disp_operands == MAX_MEMORY_OPERANDS)
10565 {
10566 as_bad (_("at most %d displacement operands are allowed"),
10567 MAX_MEMORY_OPERANDS);
10568 return 0;
10569 }
10570
10571 operand_type_set (&bigdisp, 0);
10572 if (i.jumpabsolute
10573 || i.types[this_operand].bitfield.baseindex
10574 || (current_templates->start->opcode_modifier.jump != JUMP
10575 && current_templates->start->opcode_modifier.jump != JUMP_DWORD))
10576 {
10577 i386_addressing_mode ();
10578 override = (i.prefix[ADDR_PREFIX] != 0);
10579 if (flag_code == CODE_64BIT)
10580 {
10581 if (!override)
10582 {
10583 bigdisp.bitfield.disp32s = 1;
10584 bigdisp.bitfield.disp64 = 1;
10585 }
10586 else
10587 bigdisp.bitfield.disp32 = 1;
10588 }
10589 else if ((flag_code == CODE_16BIT) ^ override)
10590 bigdisp.bitfield.disp16 = 1;
10591 else
10592 bigdisp.bitfield.disp32 = 1;
10593 }
10594 else
10595 {
10596 /* For PC-relative branches, the width of the displacement may be
10597 dependent upon data size, but is never dependent upon address size.
10598 Also make sure to not unintentionally match against a non-PC-relative
10599 branch template. */
10600 static templates aux_templates;
10601 const insn_template *t = current_templates->start;
10602 bfd_boolean has_intel64 = FALSE;
10603
10604 aux_templates.start = t;
10605 while (++t < current_templates->end)
10606 {
10607 if (t->opcode_modifier.jump
10608 != current_templates->start->opcode_modifier.jump)
10609 break;
10610 if ((t->opcode_modifier.isa64 >= INTEL64))
10611 has_intel64 = TRUE;
10612 }
10613 if (t < current_templates->end)
10614 {
10615 aux_templates.end = t;
10616 current_templates = &aux_templates;
10617 }
10618
10619 override = (i.prefix[DATA_PREFIX] != 0);
10620 if (flag_code == CODE_64BIT)
10621 {
10622 if ((override || i.suffix == WORD_MNEM_SUFFIX)
10623 && (!intel64 || !has_intel64))
10624 bigdisp.bitfield.disp16 = 1;
10625 else
10626 bigdisp.bitfield.disp32s = 1;
10627 }
10628 else
10629 {
10630 if (!override)
10631 override = (i.suffix == (flag_code != CODE_16BIT
10632 ? WORD_MNEM_SUFFIX
10633 : LONG_MNEM_SUFFIX));
10634 bigdisp.bitfield.disp32 = 1;
10635 if ((flag_code == CODE_16BIT) ^ override)
10636 {
10637 bigdisp.bitfield.disp32 = 0;
10638 bigdisp.bitfield.disp16 = 1;
10639 }
10640 }
10641 }
10642 i.types[this_operand] = operand_type_or (i.types[this_operand],
10643 bigdisp);
10644
10645 exp = &disp_expressions[i.disp_operands];
10646 i.op[this_operand].disps = exp;
10647 i.disp_operands++;
10648 save_input_line_pointer = input_line_pointer;
10649 input_line_pointer = disp_start;
10650 END_STRING_AND_SAVE (disp_end);
10651
10652 #ifndef GCC_ASM_O_HACK
10653 #define GCC_ASM_O_HACK 0
10654 #endif
10655 #if GCC_ASM_O_HACK
10656 END_STRING_AND_SAVE (disp_end + 1);
10657 if (i.types[this_operand].bitfield.baseIndex
10658 && displacement_string_end[-1] == '+')
10659 {
10660 /* This hack is to avoid a warning when using the "o"
10661 constraint within gcc asm statements.
10662 For instance:
10663
10664 #define _set_tssldt_desc(n,addr,limit,type) \
10665 __asm__ __volatile__ ( \
10666 "movw %w2,%0\n\t" \
10667 "movw %w1,2+%0\n\t" \
10668 "rorl $16,%1\n\t" \
10669 "movb %b1,4+%0\n\t" \
10670 "movb %4,5+%0\n\t" \
10671 "movb $0,6+%0\n\t" \
10672 "movb %h1,7+%0\n\t" \
10673 "rorl $16,%1" \
10674 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10675
10676 This works great except that the output assembler ends
10677 up looking a bit weird if it turns out that there is
10678 no offset. You end up producing code that looks like:
10679
10680 #APP
10681 movw $235,(%eax)
10682 movw %dx,2+(%eax)
10683 rorl $16,%edx
10684 movb %dl,4+(%eax)
10685 movb $137,5+(%eax)
10686 movb $0,6+(%eax)
10687 movb %dh,7+(%eax)
10688 rorl $16,%edx
10689 #NO_APP
10690
10691 So here we provide the missing zero. */
10692
10693 *displacement_string_end = '0';
10694 }
10695 #endif
10696 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10697 if (gotfree_input_line)
10698 input_line_pointer = gotfree_input_line;
10699
10700 exp_seg = expression (exp);
10701
10702 SKIP_WHITESPACE ();
10703 if (*input_line_pointer)
10704 as_bad (_("junk `%s' after expression"), input_line_pointer);
10705 #if GCC_ASM_O_HACK
10706 RESTORE_END_STRING (disp_end + 1);
10707 #endif
10708 input_line_pointer = save_input_line_pointer;
10709 if (gotfree_input_line)
10710 {
10711 free (gotfree_input_line);
10712
10713 if (exp->X_op == O_constant || exp->X_op == O_register)
10714 exp->X_op = O_illegal;
10715 }
10716
10717 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
10718
10719 RESTORE_END_STRING (disp_end);
10720
10721 return ret;
10722 }
10723
10724 static int
10725 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10726 i386_operand_type types, const char *disp_start)
10727 {
10728 i386_operand_type bigdisp;
10729 int ret = 1;
10730
10731 /* We do this to make sure that the section symbol is in
10732 the symbol table. We will ultimately change the relocation
10733 to be relative to the beginning of the section. */
10734 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
10735 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
10736 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10737 {
10738 if (exp->X_op != O_symbol)
10739 goto inv_disp;
10740
10741 if (S_IS_LOCAL (exp->X_add_symbol)
10742 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
10743 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
10744 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
10745 exp->X_op = O_subtract;
10746 exp->X_op_symbol = GOT_symbol;
10747 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
10748 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
10749 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10750 i.reloc[this_operand] = BFD_RELOC_64;
10751 else
10752 i.reloc[this_operand] = BFD_RELOC_32;
10753 }
10754
10755 else if (exp->X_op == O_absent
10756 || exp->X_op == O_illegal
10757 || exp->X_op == O_big)
10758 {
10759 inv_disp:
10760 as_bad (_("missing or invalid displacement expression `%s'"),
10761 disp_start);
10762 ret = 0;
10763 }
10764
10765 else if (flag_code == CODE_64BIT
10766 && !i.prefix[ADDR_PREFIX]
10767 && exp->X_op == O_constant)
10768 {
10769 /* Since displacement is signed extended to 64bit, don't allow
10770 disp32 and turn off disp32s if they are out of range. */
10771 i.types[this_operand].bitfield.disp32 = 0;
10772 if (!fits_in_signed_long (exp->X_add_number))
10773 {
10774 i.types[this_operand].bitfield.disp32s = 0;
10775 if (i.types[this_operand].bitfield.baseindex)
10776 {
10777 as_bad (_("0x%lx out range of signed 32bit displacement"),
10778 (long) exp->X_add_number);
10779 ret = 0;
10780 }
10781 }
10782 }
10783
10784 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10785 else if (exp->X_op != O_constant
10786 && OUTPUT_FLAVOR == bfd_target_aout_flavour
10787 && exp_seg != absolute_section
10788 && exp_seg != text_section
10789 && exp_seg != data_section
10790 && exp_seg != bss_section
10791 && exp_seg != undefined_section
10792 && !bfd_is_com_section (exp_seg))
10793 {
10794 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10795 ret = 0;
10796 }
10797 #endif
10798
10799 if (current_templates->start->opcode_modifier.jump == JUMP_BYTE
10800 /* Constants get taken care of by optimize_disp(). */
10801 && exp->X_op != O_constant)
10802 i.types[this_operand].bitfield.disp8 = 1;
10803
10804 /* Check if this is a displacement only operand. */
10805 bigdisp = i.types[this_operand];
10806 bigdisp.bitfield.disp8 = 0;
10807 bigdisp.bitfield.disp16 = 0;
10808 bigdisp.bitfield.disp32 = 0;
10809 bigdisp.bitfield.disp32s = 0;
10810 bigdisp.bitfield.disp64 = 0;
10811 if (operand_type_all_zero (&bigdisp))
10812 i.types[this_operand] = operand_type_and (i.types[this_operand],
10813 types);
10814
10815 return ret;
10816 }
10817
10818 /* Return the active addressing mode, taking address override and
10819 registers forming the address into consideration. Update the
10820 address override prefix if necessary. */
10821
10822 static enum flag_code
10823 i386_addressing_mode (void)
10824 {
10825 enum flag_code addr_mode;
10826
10827 if (i.prefix[ADDR_PREFIX])
10828 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
10829 else if (flag_code == CODE_16BIT
10830 && current_templates->start->cpu_flags.bitfield.cpumpx
10831 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10832 from md_assemble() by "is not a valid base/index expression"
10833 when there is a base and/or index. */
10834 && !i.types[this_operand].bitfield.baseindex)
10835 {
10836 /* MPX insn memory operands with neither base nor index must be forced
10837 to use 32-bit addressing in 16-bit mode. */
10838 addr_mode = CODE_32BIT;
10839 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10840 ++i.prefixes;
10841 gas_assert (!i.types[this_operand].bitfield.disp16);
10842 gas_assert (!i.types[this_operand].bitfield.disp32);
10843 }
10844 else
10845 {
10846 addr_mode = flag_code;
10847
10848 #if INFER_ADDR_PREFIX
10849 if (i.mem_operands == 0)
10850 {
10851 /* Infer address prefix from the first memory operand. */
10852 const reg_entry *addr_reg = i.base_reg;
10853
10854 if (addr_reg == NULL)
10855 addr_reg = i.index_reg;
10856
10857 if (addr_reg)
10858 {
10859 if (addr_reg->reg_type.bitfield.dword)
10860 addr_mode = CODE_32BIT;
10861 else if (flag_code != CODE_64BIT
10862 && addr_reg->reg_type.bitfield.word)
10863 addr_mode = CODE_16BIT;
10864
10865 if (addr_mode != flag_code)
10866 {
10867 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10868 i.prefixes += 1;
10869 /* Change the size of any displacement too. At most one
10870 of Disp16 or Disp32 is set.
10871 FIXME. There doesn't seem to be any real need for
10872 separate Disp16 and Disp32 flags. The same goes for
10873 Imm16 and Imm32. Removing them would probably clean
10874 up the code quite a lot. */
10875 if (flag_code != CODE_64BIT
10876 && (i.types[this_operand].bitfield.disp16
10877 || i.types[this_operand].bitfield.disp32))
10878 i.types[this_operand]
10879 = operand_type_xor (i.types[this_operand], disp16_32);
10880 }
10881 }
10882 }
10883 #endif
10884 }
10885
10886 return addr_mode;
10887 }
10888
10889 /* Make sure the memory operand we've been dealt is valid.
10890 Return 1 on success, 0 on a failure. */
10891
10892 static int
10893 i386_index_check (const char *operand_string)
10894 {
10895 const char *kind = "base/index";
10896 enum flag_code addr_mode = i386_addressing_mode ();
10897
10898 if (current_templates->start->opcode_modifier.isstring
10899 && !current_templates->start->cpu_flags.bitfield.cpupadlock
10900 && (current_templates->end[-1].opcode_modifier.isstring
10901 || i.mem_operands))
10902 {
10903 /* Memory operands of string insns are special in that they only allow
10904 a single register (rDI, rSI, or rBX) as their memory address. */
10905 const reg_entry *expected_reg;
10906 static const char *di_si[][2] =
10907 {
10908 { "esi", "edi" },
10909 { "si", "di" },
10910 { "rsi", "rdi" }
10911 };
10912 static const char *bx[] = { "ebx", "bx", "rbx" };
10913
10914 kind = "string address";
10915
10916 if (current_templates->start->opcode_modifier.repprefixok)
10917 {
10918 int es_op = current_templates->end[-1].opcode_modifier.isstring
10919 - IS_STRING_ES_OP0;
10920 int op = 0;
10921
10922 if (!current_templates->end[-1].operand_types[0].bitfield.baseindex
10923 || ((!i.mem_operands != !intel_syntax)
10924 && current_templates->end[-1].operand_types[1]
10925 .bitfield.baseindex))
10926 op = 1;
10927 expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]);
10928 }
10929 else
10930 expected_reg = hash_find (reg_hash, bx[addr_mode]);
10931
10932 if (i.base_reg != expected_reg
10933 || i.index_reg
10934 || operand_type_check (i.types[this_operand], disp))
10935 {
10936 /* The second memory operand must have the same size as
10937 the first one. */
10938 if (i.mem_operands
10939 && i.base_reg
10940 && !((addr_mode == CODE_64BIT
10941 && i.base_reg->reg_type.bitfield.qword)
10942 || (addr_mode == CODE_32BIT
10943 ? i.base_reg->reg_type.bitfield.dword
10944 : i.base_reg->reg_type.bitfield.word)))
10945 goto bad_address;
10946
10947 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10948 operand_string,
10949 intel_syntax ? '[' : '(',
10950 register_prefix,
10951 expected_reg->reg_name,
10952 intel_syntax ? ']' : ')');
10953 return 1;
10954 }
10955 else
10956 return 1;
10957
10958 bad_address:
10959 as_bad (_("`%s' is not a valid %s expression"),
10960 operand_string, kind);
10961 return 0;
10962 }
10963 else
10964 {
10965 if (addr_mode != CODE_16BIT)
10966 {
10967 /* 32-bit/64-bit checks. */
10968 if ((i.base_reg
10969 && ((addr_mode == CODE_64BIT
10970 ? !i.base_reg->reg_type.bitfield.qword
10971 : !i.base_reg->reg_type.bitfield.dword)
10972 || (i.index_reg && i.base_reg->reg_num == RegIP)
10973 || i.base_reg->reg_num == RegIZ))
10974 || (i.index_reg
10975 && !i.index_reg->reg_type.bitfield.xmmword
10976 && !i.index_reg->reg_type.bitfield.ymmword
10977 && !i.index_reg->reg_type.bitfield.zmmword
10978 && ((addr_mode == CODE_64BIT
10979 ? !i.index_reg->reg_type.bitfield.qword
10980 : !i.index_reg->reg_type.bitfield.dword)
10981 || !i.index_reg->reg_type.bitfield.baseindex)))
10982 goto bad_address;
10983
10984 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
10985 if (current_templates->start->base_opcode == 0xf30f1b
10986 || (current_templates->start->base_opcode & ~1) == 0x0f1a
10987 || current_templates->start->opcode_modifier.sib == SIBMEM)
10988 {
10989 /* They cannot use RIP-relative addressing. */
10990 if (i.base_reg && i.base_reg->reg_num == RegIP)
10991 {
10992 as_bad (_("`%s' cannot be used here"), operand_string);
10993 return 0;
10994 }
10995
10996 /* bndldx and bndstx ignore their scale factor. */
10997 if ((current_templates->start->base_opcode & ~1) == 0x0f1a
10998 && i.log2_scale_factor)
10999 as_warn (_("register scaling is being ignored here"));
11000 }
11001 }
11002 else
11003 {
11004 /* 16-bit checks. */
11005 if ((i.base_reg
11006 && (!i.base_reg->reg_type.bitfield.word
11007 || !i.base_reg->reg_type.bitfield.baseindex))
11008 || (i.index_reg
11009 && (!i.index_reg->reg_type.bitfield.word
11010 || !i.index_reg->reg_type.bitfield.baseindex
11011 || !(i.base_reg
11012 && i.base_reg->reg_num < 6
11013 && i.index_reg->reg_num >= 6
11014 && i.log2_scale_factor == 0))))
11015 goto bad_address;
11016 }
11017 }
11018 return 1;
11019 }
11020
11021 /* Handle vector immediates. */
11022
11023 static int
11024 RC_SAE_immediate (const char *imm_start)
11025 {
11026 unsigned int match_found, j;
11027 const char *pstr = imm_start;
11028 expressionS *exp;
11029
11030 if (*pstr != '{')
11031 return 0;
11032
11033 pstr++;
11034 match_found = 0;
11035 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
11036 {
11037 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
11038 {
11039 if (!i.rounding)
11040 {
11041 rc_op.type = RC_NamesTable[j].type;
11042 rc_op.operand = this_operand;
11043 i.rounding = &rc_op;
11044 }
11045 else
11046 {
11047 as_bad (_("duplicated `%s'"), imm_start);
11048 return 0;
11049 }
11050 pstr += RC_NamesTable[j].len;
11051 match_found = 1;
11052 break;
11053 }
11054 }
11055 if (!match_found)
11056 return 0;
11057
11058 if (*pstr++ != '}')
11059 {
11060 as_bad (_("Missing '}': '%s'"), imm_start);
11061 return 0;
11062 }
11063 /* RC/SAE immediate string should contain nothing more. */;
11064 if (*pstr != 0)
11065 {
11066 as_bad (_("Junk after '}': '%s'"), imm_start);
11067 return 0;
11068 }
11069
11070 exp = &im_expressions[i.imm_operands++];
11071 i.op[this_operand].imms = exp;
11072
11073 exp->X_op = O_constant;
11074 exp->X_add_number = 0;
11075 exp->X_add_symbol = (symbolS *) 0;
11076 exp->X_op_symbol = (symbolS *) 0;
11077
11078 i.types[this_operand].bitfield.imm8 = 1;
11079 return 1;
11080 }
11081
11082 /* Only string instructions can have a second memory operand, so
11083 reduce current_templates to just those if it contains any. */
11084 static int
11085 maybe_adjust_templates (void)
11086 {
11087 const insn_template *t;
11088
11089 gas_assert (i.mem_operands == 1);
11090
11091 for (t = current_templates->start; t < current_templates->end; ++t)
11092 if (t->opcode_modifier.isstring)
11093 break;
11094
11095 if (t < current_templates->end)
11096 {
11097 static templates aux_templates;
11098 bfd_boolean recheck;
11099
11100 aux_templates.start = t;
11101 for (; t < current_templates->end; ++t)
11102 if (!t->opcode_modifier.isstring)
11103 break;
11104 aux_templates.end = t;
11105
11106 /* Determine whether to re-check the first memory operand. */
11107 recheck = (aux_templates.start != current_templates->start
11108 || t != current_templates->end);
11109
11110 current_templates = &aux_templates;
11111
11112 if (recheck)
11113 {
11114 i.mem_operands = 0;
11115 if (i.memop1_string != NULL
11116 && i386_index_check (i.memop1_string) == 0)
11117 return 0;
11118 i.mem_operands = 1;
11119 }
11120 }
11121
11122 return 1;
11123 }
11124
11125 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11126 on error. */
11127
11128 static int
11129 i386_att_operand (char *operand_string)
11130 {
11131 const reg_entry *r;
11132 char *end_op;
11133 char *op_string = operand_string;
11134
11135 if (is_space_char (*op_string))
11136 ++op_string;
11137
11138 /* We check for an absolute prefix (differentiating,
11139 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11140 if (*op_string == ABSOLUTE_PREFIX)
11141 {
11142 ++op_string;
11143 if (is_space_char (*op_string))
11144 ++op_string;
11145 i.jumpabsolute = TRUE;
11146 }
11147
11148 /* Check if operand is a register. */
11149 if ((r = parse_register (op_string, &end_op)) != NULL)
11150 {
11151 i386_operand_type temp;
11152
11153 if (r == &bad_reg)
11154 return 0;
11155
11156 /* Check for a segment override by searching for ':' after a
11157 segment register. */
11158 op_string = end_op;
11159 if (is_space_char (*op_string))
11160 ++op_string;
11161 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
11162 {
11163 switch (r->reg_num)
11164 {
11165 case 0:
11166 i.seg[i.mem_operands] = &es;
11167 break;
11168 case 1:
11169 i.seg[i.mem_operands] = &cs;
11170 break;
11171 case 2:
11172 i.seg[i.mem_operands] = &ss;
11173 break;
11174 case 3:
11175 i.seg[i.mem_operands] = &ds;
11176 break;
11177 case 4:
11178 i.seg[i.mem_operands] = &fs;
11179 break;
11180 case 5:
11181 i.seg[i.mem_operands] = &gs;
11182 break;
11183 }
11184
11185 /* Skip the ':' and whitespace. */
11186 ++op_string;
11187 if (is_space_char (*op_string))
11188 ++op_string;
11189
11190 if (!is_digit_char (*op_string)
11191 && !is_identifier_char (*op_string)
11192 && *op_string != '('
11193 && *op_string != ABSOLUTE_PREFIX)
11194 {
11195 as_bad (_("bad memory operand `%s'"), op_string);
11196 return 0;
11197 }
11198 /* Handle case of %es:*foo. */
11199 if (*op_string == ABSOLUTE_PREFIX)
11200 {
11201 ++op_string;
11202 if (is_space_char (*op_string))
11203 ++op_string;
11204 i.jumpabsolute = TRUE;
11205 }
11206 goto do_memory_reference;
11207 }
11208
11209 /* Handle vector operations. */
11210 if (*op_string == '{')
11211 {
11212 op_string = check_VecOperations (op_string, NULL);
11213 if (op_string == NULL)
11214 return 0;
11215 }
11216
11217 if (*op_string)
11218 {
11219 as_bad (_("junk `%s' after register"), op_string);
11220 return 0;
11221 }
11222 temp = r->reg_type;
11223 temp.bitfield.baseindex = 0;
11224 i.types[this_operand] = operand_type_or (i.types[this_operand],
11225 temp);
11226 i.types[this_operand].bitfield.unspecified = 0;
11227 i.op[this_operand].regs = r;
11228 i.reg_operands++;
11229 }
11230 else if (*op_string == REGISTER_PREFIX)
11231 {
11232 as_bad (_("bad register name `%s'"), op_string);
11233 return 0;
11234 }
11235 else if (*op_string == IMMEDIATE_PREFIX)
11236 {
11237 ++op_string;
11238 if (i.jumpabsolute)
11239 {
11240 as_bad (_("immediate operand illegal with absolute jump"));
11241 return 0;
11242 }
11243 if (!i386_immediate (op_string))
11244 return 0;
11245 }
11246 else if (RC_SAE_immediate (operand_string))
11247 {
11248 /* If it is a RC or SAE immediate, do nothing. */
11249 ;
11250 }
11251 else if (is_digit_char (*op_string)
11252 || is_identifier_char (*op_string)
11253 || *op_string == '"'
11254 || *op_string == '(')
11255 {
11256 /* This is a memory reference of some sort. */
11257 char *base_string;
11258
11259 /* Start and end of displacement string expression (if found). */
11260 char *displacement_string_start;
11261 char *displacement_string_end;
11262 char *vop_start;
11263
11264 do_memory_reference:
11265 if (i.mem_operands == 1 && !maybe_adjust_templates ())
11266 return 0;
11267 if ((i.mem_operands == 1
11268 && !current_templates->start->opcode_modifier.isstring)
11269 || i.mem_operands == 2)
11270 {
11271 as_bad (_("too many memory references for `%s'"),
11272 current_templates->start->name);
11273 return 0;
11274 }
11275
11276 /* Check for base index form. We detect the base index form by
11277 looking for an ')' at the end of the operand, searching
11278 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11279 after the '('. */
11280 base_string = op_string + strlen (op_string);
11281
11282 /* Handle vector operations. */
11283 vop_start = strchr (op_string, '{');
11284 if (vop_start && vop_start < base_string)
11285 {
11286 if (check_VecOperations (vop_start, base_string) == NULL)
11287 return 0;
11288 base_string = vop_start;
11289 }
11290
11291 --base_string;
11292 if (is_space_char (*base_string))
11293 --base_string;
11294
11295 /* If we only have a displacement, set-up for it to be parsed later. */
11296 displacement_string_start = op_string;
11297 displacement_string_end = base_string + 1;
11298
11299 if (*base_string == ')')
11300 {
11301 char *temp_string;
11302 unsigned int parens_balanced = 1;
11303 /* We've already checked that the number of left & right ()'s are
11304 equal, so this loop will not be infinite. */
11305 do
11306 {
11307 base_string--;
11308 if (*base_string == ')')
11309 parens_balanced++;
11310 if (*base_string == '(')
11311 parens_balanced--;
11312 }
11313 while (parens_balanced);
11314
11315 temp_string = base_string;
11316
11317 /* Skip past '(' and whitespace. */
11318 ++base_string;
11319 if (is_space_char (*base_string))
11320 ++base_string;
11321
11322 if (*base_string == ','
11323 || ((i.base_reg = parse_register (base_string, &end_op))
11324 != NULL))
11325 {
11326 displacement_string_end = temp_string;
11327
11328 i.types[this_operand].bitfield.baseindex = 1;
11329
11330 if (i.base_reg)
11331 {
11332 if (i.base_reg == &bad_reg)
11333 return 0;
11334 base_string = end_op;
11335 if (is_space_char (*base_string))
11336 ++base_string;
11337 }
11338
11339 /* There may be an index reg or scale factor here. */
11340 if (*base_string == ',')
11341 {
11342 ++base_string;
11343 if (is_space_char (*base_string))
11344 ++base_string;
11345
11346 if ((i.index_reg = parse_register (base_string, &end_op))
11347 != NULL)
11348 {
11349 if (i.index_reg == &bad_reg)
11350 return 0;
11351 base_string = end_op;
11352 if (is_space_char (*base_string))
11353 ++base_string;
11354 if (*base_string == ',')
11355 {
11356 ++base_string;
11357 if (is_space_char (*base_string))
11358 ++base_string;
11359 }
11360 else if (*base_string != ')')
11361 {
11362 as_bad (_("expecting `,' or `)' "
11363 "after index register in `%s'"),
11364 operand_string);
11365 return 0;
11366 }
11367 }
11368 else if (*base_string == REGISTER_PREFIX)
11369 {
11370 end_op = strchr (base_string, ',');
11371 if (end_op)
11372 *end_op = '\0';
11373 as_bad (_("bad register name `%s'"), base_string);
11374 return 0;
11375 }
11376
11377 /* Check for scale factor. */
11378 if (*base_string != ')')
11379 {
11380 char *end_scale = i386_scale (base_string);
11381
11382 if (!end_scale)
11383 return 0;
11384
11385 base_string = end_scale;
11386 if (is_space_char (*base_string))
11387 ++base_string;
11388 if (*base_string != ')')
11389 {
11390 as_bad (_("expecting `)' "
11391 "after scale factor in `%s'"),
11392 operand_string);
11393 return 0;
11394 }
11395 }
11396 else if (!i.index_reg)
11397 {
11398 as_bad (_("expecting index register or scale factor "
11399 "after `,'; got '%c'"),
11400 *base_string);
11401 return 0;
11402 }
11403 }
11404 else if (*base_string != ')')
11405 {
11406 as_bad (_("expecting `,' or `)' "
11407 "after base register in `%s'"),
11408 operand_string);
11409 return 0;
11410 }
11411 }
11412 else if (*base_string == REGISTER_PREFIX)
11413 {
11414 end_op = strchr (base_string, ',');
11415 if (end_op)
11416 *end_op = '\0';
11417 as_bad (_("bad register name `%s'"), base_string);
11418 return 0;
11419 }
11420 }
11421
11422 /* If there's an expression beginning the operand, parse it,
11423 assuming displacement_string_start and
11424 displacement_string_end are meaningful. */
11425 if (displacement_string_start != displacement_string_end)
11426 {
11427 if (!i386_displacement (displacement_string_start,
11428 displacement_string_end))
11429 return 0;
11430 }
11431
11432 /* Special case for (%dx) while doing input/output op. */
11433 if (i.base_reg
11434 && i.base_reg->reg_type.bitfield.instance == RegD
11435 && i.base_reg->reg_type.bitfield.word
11436 && i.index_reg == 0
11437 && i.log2_scale_factor == 0
11438 && i.seg[i.mem_operands] == 0
11439 && !operand_type_check (i.types[this_operand], disp))
11440 {
11441 i.types[this_operand] = i.base_reg->reg_type;
11442 return 1;
11443 }
11444
11445 if (i386_index_check (operand_string) == 0)
11446 return 0;
11447 i.flags[this_operand] |= Operand_Mem;
11448 if (i.mem_operands == 0)
11449 i.memop1_string = xstrdup (operand_string);
11450 i.mem_operands++;
11451 }
11452 else
11453 {
11454 /* It's not a memory operand; argh! */
11455 as_bad (_("invalid char %s beginning operand %d `%s'"),
11456 output_invalid (*op_string),
11457 this_operand + 1,
11458 op_string);
11459 return 0;
11460 }
11461 return 1; /* Normal return. */
11462 }
11463 \f
11464 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11465 that an rs_machine_dependent frag may reach. */
11466
11467 unsigned int
11468 i386_frag_max_var (fragS *frag)
11469 {
11470 /* The only relaxable frags are for jumps.
11471 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11472 gas_assert (frag->fr_type == rs_machine_dependent);
11473 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
11474 }
11475
11476 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11477 static int
11478 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
11479 {
11480 /* STT_GNU_IFUNC symbol must go through PLT. */
11481 if ((symbol_get_bfdsym (fr_symbol)->flags
11482 & BSF_GNU_INDIRECT_FUNCTION) != 0)
11483 return 0;
11484
11485 if (!S_IS_EXTERNAL (fr_symbol))
11486 /* Symbol may be weak or local. */
11487 return !S_IS_WEAK (fr_symbol);
11488
11489 /* Global symbols with non-default visibility can't be preempted. */
11490 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
11491 return 1;
11492
11493 if (fr_var != NO_RELOC)
11494 switch ((enum bfd_reloc_code_real) fr_var)
11495 {
11496 case BFD_RELOC_386_PLT32:
11497 case BFD_RELOC_X86_64_PLT32:
11498 /* Symbol with PLT relocation may be preempted. */
11499 return 0;
11500 default:
11501 abort ();
11502 }
11503
11504 /* Global symbols with default visibility in a shared library may be
11505 preempted by another definition. */
11506 return !shared;
11507 }
11508 #endif
11509
11510 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11511 Note also work for Skylake and Cascadelake.
11512 ---------------------------------------------------------------------
11513 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11514 | ------ | ----------- | ------- | -------- |
11515 | Jo | N | N | Y |
11516 | Jno | N | N | Y |
11517 | Jc/Jb | Y | N | Y |
11518 | Jae/Jnb | Y | N | Y |
11519 | Je/Jz | Y | Y | Y |
11520 | Jne/Jnz | Y | Y | Y |
11521 | Jna/Jbe | Y | N | Y |
11522 | Ja/Jnbe | Y | N | Y |
11523 | Js | N | N | Y |
11524 | Jns | N | N | Y |
11525 | Jp/Jpe | N | N | Y |
11526 | Jnp/Jpo | N | N | Y |
11527 | Jl/Jnge | Y | Y | Y |
11528 | Jge/Jnl | Y | Y | Y |
11529 | Jle/Jng | Y | Y | Y |
11530 | Jg/Jnle | Y | Y | Y |
11531 --------------------------------------------------------------------- */
11532 static int
11533 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
11534 {
11535 if (mf_cmp == mf_cmp_alu_cmp)
11536 return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
11537 || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
11538 if (mf_cmp == mf_cmp_incdec)
11539 return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
11540 || mf_jcc == mf_jcc_jle);
11541 if (mf_cmp == mf_cmp_test_and)
11542 return 1;
11543 return 0;
11544 }
11545
11546 /* Return the next non-empty frag. */
11547
11548 static fragS *
11549 i386_next_non_empty_frag (fragS *fragP)
11550 {
11551 /* There may be a frag with a ".fill 0" when there is no room in
11552 the current frag for frag_grow in output_insn. */
11553 for (fragP = fragP->fr_next;
11554 (fragP != NULL
11555 && fragP->fr_type == rs_fill
11556 && fragP->fr_fix == 0);
11557 fragP = fragP->fr_next)
11558 ;
11559 return fragP;
11560 }
11561
11562 /* Return the next jcc frag after BRANCH_PADDING. */
11563
11564 static fragS *
11565 i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
11566 {
11567 fragS *branch_fragP;
11568 if (!pad_fragP)
11569 return NULL;
11570
11571 if (pad_fragP->fr_type == rs_machine_dependent
11572 && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
11573 == BRANCH_PADDING))
11574 {
11575 branch_fragP = i386_next_non_empty_frag (pad_fragP);
11576 if (branch_fragP->fr_type != rs_machine_dependent)
11577 return NULL;
11578 if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
11579 && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
11580 pad_fragP->tc_frag_data.mf_type))
11581 return branch_fragP;
11582 }
11583
11584 return NULL;
11585 }
11586
11587 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11588
11589 static void
11590 i386_classify_machine_dependent_frag (fragS *fragP)
11591 {
11592 fragS *cmp_fragP;
11593 fragS *pad_fragP;
11594 fragS *branch_fragP;
11595 fragS *next_fragP;
11596 unsigned int max_prefix_length;
11597
11598 if (fragP->tc_frag_data.classified)
11599 return;
11600
11601 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11602 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11603 for (next_fragP = fragP;
11604 next_fragP != NULL;
11605 next_fragP = next_fragP->fr_next)
11606 {
11607 next_fragP->tc_frag_data.classified = 1;
11608 if (next_fragP->fr_type == rs_machine_dependent)
11609 switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
11610 {
11611 case BRANCH_PADDING:
11612 /* The BRANCH_PADDING frag must be followed by a branch
11613 frag. */
11614 branch_fragP = i386_next_non_empty_frag (next_fragP);
11615 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11616 break;
11617 case FUSED_JCC_PADDING:
11618 /* Check if this is a fused jcc:
11619 FUSED_JCC_PADDING
11620 CMP like instruction
11621 BRANCH_PADDING
11622 COND_JUMP
11623 */
11624 cmp_fragP = i386_next_non_empty_frag (next_fragP);
11625 pad_fragP = i386_next_non_empty_frag (cmp_fragP);
11626 branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
11627 if (branch_fragP)
11628 {
11629 /* The BRANCH_PADDING frag is merged with the
11630 FUSED_JCC_PADDING frag. */
11631 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11632 /* CMP like instruction size. */
11633 next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
11634 frag_wane (pad_fragP);
11635 /* Skip to branch_fragP. */
11636 next_fragP = branch_fragP;
11637 }
11638 else if (next_fragP->tc_frag_data.max_prefix_length)
11639 {
11640 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11641 a fused jcc. */
11642 next_fragP->fr_subtype
11643 = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
11644 next_fragP->tc_frag_data.max_bytes
11645 = next_fragP->tc_frag_data.max_prefix_length;
11646 /* This will be updated in the BRANCH_PREFIX scan. */
11647 next_fragP->tc_frag_data.max_prefix_length = 0;
11648 }
11649 else
11650 frag_wane (next_fragP);
11651 break;
11652 }
11653 }
11654
11655 /* Stop if there is no BRANCH_PREFIX. */
11656 if (!align_branch_prefix_size)
11657 return;
11658
11659 /* Scan for BRANCH_PREFIX. */
11660 for (; fragP != NULL; fragP = fragP->fr_next)
11661 {
11662 if (fragP->fr_type != rs_machine_dependent
11663 || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11664 != BRANCH_PREFIX))
11665 continue;
11666
11667 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11668 COND_JUMP_PREFIX. */
11669 max_prefix_length = 0;
11670 for (next_fragP = fragP;
11671 next_fragP != NULL;
11672 next_fragP = next_fragP->fr_next)
11673 {
11674 if (next_fragP->fr_type == rs_fill)
11675 /* Skip rs_fill frags. */
11676 continue;
11677 else if (next_fragP->fr_type != rs_machine_dependent)
11678 /* Stop for all other frags. */
11679 break;
11680
11681 /* rs_machine_dependent frags. */
11682 if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11683 == BRANCH_PREFIX)
11684 {
11685 /* Count BRANCH_PREFIX frags. */
11686 if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
11687 {
11688 max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
11689 frag_wane (next_fragP);
11690 }
11691 else
11692 max_prefix_length
11693 += next_fragP->tc_frag_data.max_bytes;
11694 }
11695 else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11696 == BRANCH_PADDING)
11697 || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11698 == FUSED_JCC_PADDING))
11699 {
11700 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11701 fragP->tc_frag_data.u.padding_fragP = next_fragP;
11702 break;
11703 }
11704 else
11705 /* Stop for other rs_machine_dependent frags. */
11706 break;
11707 }
11708
11709 fragP->tc_frag_data.max_prefix_length = max_prefix_length;
11710
11711 /* Skip to the next frag. */
11712 fragP = next_fragP;
11713 }
11714 }
11715
11716 /* Compute padding size for
11717
11718 FUSED_JCC_PADDING
11719 CMP like instruction
11720 BRANCH_PADDING
11721 COND_JUMP/UNCOND_JUMP
11722
11723 or
11724
11725 BRANCH_PADDING
11726 COND_JUMP/UNCOND_JUMP
11727 */
11728
11729 static int
11730 i386_branch_padding_size (fragS *fragP, offsetT address)
11731 {
11732 unsigned int offset, size, padding_size;
11733 fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
11734
11735 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11736 if (!address)
11737 address = fragP->fr_address;
11738 address += fragP->fr_fix;
11739
11740 /* CMP like instrunction size. */
11741 size = fragP->tc_frag_data.cmp_size;
11742
11743 /* The base size of the branch frag. */
11744 size += branch_fragP->fr_fix;
11745
11746 /* Add opcode and displacement bytes for the rs_machine_dependent
11747 branch frag. */
11748 if (branch_fragP->fr_type == rs_machine_dependent)
11749 size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
11750
11751 /* Check if branch is within boundary and doesn't end at the last
11752 byte. */
11753 offset = address & ((1U << align_branch_power) - 1);
11754 if ((offset + size) >= (1U << align_branch_power))
11755 /* Padding needed to avoid crossing boundary. */
11756 padding_size = (1U << align_branch_power) - offset;
11757 else
11758 /* No padding needed. */
11759 padding_size = 0;
11760
11761 /* The return value may be saved in tc_frag_data.length which is
11762 unsigned byte. */
11763 if (!fits_in_unsigned_byte (padding_size))
11764 abort ();
11765
11766 return padding_size;
11767 }
11768
11769 /* i386_generic_table_relax_frag()
11770
11771 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11772 grow/shrink padding to align branch frags. Hand others to
11773 relax_frag(). */
11774
11775 long
11776 i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
11777 {
11778 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11779 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11780 {
11781 long padding_size = i386_branch_padding_size (fragP, 0);
11782 long grow = padding_size - fragP->tc_frag_data.length;
11783
11784 /* When the BRANCH_PREFIX frag is used, the computed address
11785 must match the actual address and there should be no padding. */
11786 if (fragP->tc_frag_data.padding_address
11787 && (fragP->tc_frag_data.padding_address != fragP->fr_address
11788 || padding_size))
11789 abort ();
11790
11791 /* Update the padding size. */
11792 if (grow)
11793 fragP->tc_frag_data.length = padding_size;
11794
11795 return grow;
11796 }
11797 else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11798 {
11799 fragS *padding_fragP, *next_fragP;
11800 long padding_size, left_size, last_size;
11801
11802 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
11803 if (!padding_fragP)
11804 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11805 return (fragP->tc_frag_data.length
11806 - fragP->tc_frag_data.last_length);
11807
11808 /* Compute the relative address of the padding frag in the very
11809 first time where the BRANCH_PREFIX frag sizes are zero. */
11810 if (!fragP->tc_frag_data.padding_address)
11811 fragP->tc_frag_data.padding_address
11812 = padding_fragP->fr_address - (fragP->fr_address - stretch);
11813
11814 /* First update the last length from the previous interation. */
11815 left_size = fragP->tc_frag_data.prefix_length;
11816 for (next_fragP = fragP;
11817 next_fragP != padding_fragP;
11818 next_fragP = next_fragP->fr_next)
11819 if (next_fragP->fr_type == rs_machine_dependent
11820 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11821 == BRANCH_PREFIX))
11822 {
11823 if (left_size)
11824 {
11825 int max = next_fragP->tc_frag_data.max_bytes;
11826 if (max)
11827 {
11828 int size;
11829 if (max > left_size)
11830 size = left_size;
11831 else
11832 size = max;
11833 left_size -= size;
11834 next_fragP->tc_frag_data.last_length = size;
11835 }
11836 }
11837 else
11838 next_fragP->tc_frag_data.last_length = 0;
11839 }
11840
11841 /* Check the padding size for the padding frag. */
11842 padding_size = i386_branch_padding_size
11843 (padding_fragP, (fragP->fr_address
11844 + fragP->tc_frag_data.padding_address));
11845
11846 last_size = fragP->tc_frag_data.prefix_length;
11847 /* Check if there is change from the last interation. */
11848 if (padding_size == last_size)
11849 {
11850 /* Update the expected address of the padding frag. */
11851 padding_fragP->tc_frag_data.padding_address
11852 = (fragP->fr_address + padding_size
11853 + fragP->tc_frag_data.padding_address);
11854 return 0;
11855 }
11856
11857 if (padding_size > fragP->tc_frag_data.max_prefix_length)
11858 {
11859 /* No padding if there is no sufficient room. Clear the
11860 expected address of the padding frag. */
11861 padding_fragP->tc_frag_data.padding_address = 0;
11862 padding_size = 0;
11863 }
11864 else
11865 /* Store the expected address of the padding frag. */
11866 padding_fragP->tc_frag_data.padding_address
11867 = (fragP->fr_address + padding_size
11868 + fragP->tc_frag_data.padding_address);
11869
11870 fragP->tc_frag_data.prefix_length = padding_size;
11871
11872 /* Update the length for the current interation. */
11873 left_size = padding_size;
11874 for (next_fragP = fragP;
11875 next_fragP != padding_fragP;
11876 next_fragP = next_fragP->fr_next)
11877 if (next_fragP->fr_type == rs_machine_dependent
11878 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11879 == BRANCH_PREFIX))
11880 {
11881 if (left_size)
11882 {
11883 int max = next_fragP->tc_frag_data.max_bytes;
11884 if (max)
11885 {
11886 int size;
11887 if (max > left_size)
11888 size = left_size;
11889 else
11890 size = max;
11891 left_size -= size;
11892 next_fragP->tc_frag_data.length = size;
11893 }
11894 }
11895 else
11896 next_fragP->tc_frag_data.length = 0;
11897 }
11898
11899 return (fragP->tc_frag_data.length
11900 - fragP->tc_frag_data.last_length);
11901 }
11902 return relax_frag (segment, fragP, stretch);
11903 }
11904
11905 /* md_estimate_size_before_relax()
11906
11907 Called just before relax() for rs_machine_dependent frags. The x86
11908 assembler uses these frags to handle variable size jump
11909 instructions.
11910
11911 Any symbol that is now undefined will not become defined.
11912 Return the correct fr_subtype in the frag.
11913 Return the initial "guess for variable size of frag" to caller.
11914 The guess is actually the growth beyond the fixed part. Whatever
11915 we do to grow the fixed or variable part contributes to our
11916 returned value. */
11917
11918 int
11919 md_estimate_size_before_relax (fragS *fragP, segT segment)
11920 {
11921 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11922 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
11923 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11924 {
11925 i386_classify_machine_dependent_frag (fragP);
11926 return fragP->tc_frag_data.length;
11927 }
11928
11929 /* We've already got fragP->fr_subtype right; all we have to do is
11930 check for un-relaxable symbols. On an ELF system, we can't relax
11931 an externally visible symbol, because it may be overridden by a
11932 shared library. */
11933 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
11934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11935 || (IS_ELF
11936 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
11937 fragP->fr_var))
11938 #endif
11939 #if defined (OBJ_COFF) && defined (TE_PE)
11940 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
11941 && S_IS_WEAK (fragP->fr_symbol))
11942 #endif
11943 )
11944 {
11945 /* Symbol is undefined in this segment, or we need to keep a
11946 reloc so that weak symbols can be overridden. */
11947 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
11948 enum bfd_reloc_code_real reloc_type;
11949 unsigned char *opcode;
11950 int old_fr_fix;
11951
11952 if (fragP->fr_var != NO_RELOC)
11953 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
11954 else if (size == 2)
11955 reloc_type = BFD_RELOC_16_PCREL;
11956 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11957 else if (need_plt32_p (fragP->fr_symbol))
11958 reloc_type = BFD_RELOC_X86_64_PLT32;
11959 #endif
11960 else
11961 reloc_type = BFD_RELOC_32_PCREL;
11962
11963 old_fr_fix = fragP->fr_fix;
11964 opcode = (unsigned char *) fragP->fr_opcode;
11965
11966 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
11967 {
11968 case UNCOND_JUMP:
11969 /* Make jmp (0xeb) a (d)word displacement jump. */
11970 opcode[0] = 0xe9;
11971 fragP->fr_fix += size;
11972 fix_new (fragP, old_fr_fix, size,
11973 fragP->fr_symbol,
11974 fragP->fr_offset, 1,
11975 reloc_type);
11976 break;
11977
11978 case COND_JUMP86:
11979 if (size == 2
11980 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
11981 {
11982 /* Negate the condition, and branch past an
11983 unconditional jump. */
11984 opcode[0] ^= 1;
11985 opcode[1] = 3;
11986 /* Insert an unconditional jump. */
11987 opcode[2] = 0xe9;
11988 /* We added two extra opcode bytes, and have a two byte
11989 offset. */
11990 fragP->fr_fix += 2 + 2;
11991 fix_new (fragP, old_fr_fix + 2, 2,
11992 fragP->fr_symbol,
11993 fragP->fr_offset, 1,
11994 reloc_type);
11995 break;
11996 }
11997 /* Fall through. */
11998
11999 case COND_JUMP:
12000 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
12001 {
12002 fixS *fixP;
12003
12004 fragP->fr_fix += 1;
12005 fixP = fix_new (fragP, old_fr_fix, 1,
12006 fragP->fr_symbol,
12007 fragP->fr_offset, 1,
12008 BFD_RELOC_8_PCREL);
12009 fixP->fx_signed = 1;
12010 break;
12011 }
12012
12013 /* This changes the byte-displacement jump 0x7N
12014 to the (d)word-displacement jump 0x0f,0x8N. */
12015 opcode[1] = opcode[0] + 0x10;
12016 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12017 /* We've added an opcode byte. */
12018 fragP->fr_fix += 1 + size;
12019 fix_new (fragP, old_fr_fix + 1, size,
12020 fragP->fr_symbol,
12021 fragP->fr_offset, 1,
12022 reloc_type);
12023 break;
12024
12025 default:
12026 BAD_CASE (fragP->fr_subtype);
12027 break;
12028 }
12029 frag_wane (fragP);
12030 return fragP->fr_fix - old_fr_fix;
12031 }
12032
12033 /* Guess size depending on current relax state. Initially the relax
12034 state will correspond to a short jump and we return 1, because
12035 the variable part of the frag (the branch offset) is one byte
12036 long. However, we can relax a section more than once and in that
12037 case we must either set fr_subtype back to the unrelaxed state,
12038 or return the value for the appropriate branch. */
12039 return md_relax_table[fragP->fr_subtype].rlx_length;
12040 }
12041
12042 /* Called after relax() is finished.
12043
12044 In: Address of frag.
12045 fr_type == rs_machine_dependent.
12046 fr_subtype is what the address relaxed to.
12047
12048 Out: Any fixSs and constants are set up.
12049 Caller will turn frag into a ".space 0". */
12050
12051 void
12052 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
12053 fragS *fragP)
12054 {
12055 unsigned char *opcode;
12056 unsigned char *where_to_put_displacement = NULL;
12057 offsetT target_address;
12058 offsetT opcode_address;
12059 unsigned int extension = 0;
12060 offsetT displacement_from_opcode_start;
12061
12062 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
12063 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
12064 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
12065 {
12066 /* Generate nop padding. */
12067 unsigned int size = fragP->tc_frag_data.length;
12068 if (size)
12069 {
12070 if (size > fragP->tc_frag_data.max_bytes)
12071 abort ();
12072
12073 if (flag_debug)
12074 {
12075 const char *msg;
12076 const char *branch = "branch";
12077 const char *prefix = "";
12078 fragS *padding_fragP;
12079 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
12080 == BRANCH_PREFIX)
12081 {
12082 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
12083 switch (fragP->tc_frag_data.default_prefix)
12084 {
12085 default:
12086 abort ();
12087 break;
12088 case CS_PREFIX_OPCODE:
12089 prefix = " cs";
12090 break;
12091 case DS_PREFIX_OPCODE:
12092 prefix = " ds";
12093 break;
12094 case ES_PREFIX_OPCODE:
12095 prefix = " es";
12096 break;
12097 case FS_PREFIX_OPCODE:
12098 prefix = " fs";
12099 break;
12100 case GS_PREFIX_OPCODE:
12101 prefix = " gs";
12102 break;
12103 case SS_PREFIX_OPCODE:
12104 prefix = " ss";
12105 break;
12106 }
12107 if (padding_fragP)
12108 msg = _("%s:%u: add %d%s at 0x%llx to align "
12109 "%s within %d-byte boundary\n");
12110 else
12111 msg = _("%s:%u: add additional %d%s at 0x%llx to "
12112 "align %s within %d-byte boundary\n");
12113 }
12114 else
12115 {
12116 padding_fragP = fragP;
12117 msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12118 "%s within %d-byte boundary\n");
12119 }
12120
12121 if (padding_fragP)
12122 switch (padding_fragP->tc_frag_data.branch_type)
12123 {
12124 case align_branch_jcc:
12125 branch = "jcc";
12126 break;
12127 case align_branch_fused:
12128 branch = "fused jcc";
12129 break;
12130 case align_branch_jmp:
12131 branch = "jmp";
12132 break;
12133 case align_branch_call:
12134 branch = "call";
12135 break;
12136 case align_branch_indirect:
12137 branch = "indiret branch";
12138 break;
12139 case align_branch_ret:
12140 branch = "ret";
12141 break;
12142 default:
12143 break;
12144 }
12145
12146 fprintf (stdout, msg,
12147 fragP->fr_file, fragP->fr_line, size, prefix,
12148 (long long) fragP->fr_address, branch,
12149 1 << align_branch_power);
12150 }
12151 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
12152 memset (fragP->fr_opcode,
12153 fragP->tc_frag_data.default_prefix, size);
12154 else
12155 i386_generate_nops (fragP, (char *) fragP->fr_opcode,
12156 size, 0);
12157 fragP->fr_fix += size;
12158 }
12159 return;
12160 }
12161
12162 opcode = (unsigned char *) fragP->fr_opcode;
12163
12164 /* Address we want to reach in file space. */
12165 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
12166
12167 /* Address opcode resides at in file space. */
12168 opcode_address = fragP->fr_address + fragP->fr_fix;
12169
12170 /* Displacement from opcode start to fill into instruction. */
12171 displacement_from_opcode_start = target_address - opcode_address;
12172
12173 if ((fragP->fr_subtype & BIG) == 0)
12174 {
12175 /* Don't have to change opcode. */
12176 extension = 1; /* 1 opcode + 1 displacement */
12177 where_to_put_displacement = &opcode[1];
12178 }
12179 else
12180 {
12181 if (no_cond_jump_promotion
12182 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
12183 as_warn_where (fragP->fr_file, fragP->fr_line,
12184 _("long jump required"));
12185
12186 switch (fragP->fr_subtype)
12187 {
12188 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
12189 extension = 4; /* 1 opcode + 4 displacement */
12190 opcode[0] = 0xe9;
12191 where_to_put_displacement = &opcode[1];
12192 break;
12193
12194 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
12195 extension = 2; /* 1 opcode + 2 displacement */
12196 opcode[0] = 0xe9;
12197 where_to_put_displacement = &opcode[1];
12198 break;
12199
12200 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
12201 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
12202 extension = 5; /* 2 opcode + 4 displacement */
12203 opcode[1] = opcode[0] + 0x10;
12204 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12205 where_to_put_displacement = &opcode[2];
12206 break;
12207
12208 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
12209 extension = 3; /* 2 opcode + 2 displacement */
12210 opcode[1] = opcode[0] + 0x10;
12211 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12212 where_to_put_displacement = &opcode[2];
12213 break;
12214
12215 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
12216 extension = 4;
12217 opcode[0] ^= 1;
12218 opcode[1] = 3;
12219 opcode[2] = 0xe9;
12220 where_to_put_displacement = &opcode[3];
12221 break;
12222
12223 default:
12224 BAD_CASE (fragP->fr_subtype);
12225 break;
12226 }
12227 }
12228
12229 /* If size if less then four we are sure that the operand fits,
12230 but if it's 4, then it could be that the displacement is larger
12231 then -/+ 2GB. */
12232 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
12233 && object_64bit
12234 && ((addressT) (displacement_from_opcode_start - extension
12235 + ((addressT) 1 << 31))
12236 > (((addressT) 2 << 31) - 1)))
12237 {
12238 as_bad_where (fragP->fr_file, fragP->fr_line,
12239 _("jump target out of range"));
12240 /* Make us emit 0. */
12241 displacement_from_opcode_start = extension;
12242 }
12243 /* Now put displacement after opcode. */
12244 md_number_to_chars ((char *) where_to_put_displacement,
12245 (valueT) (displacement_from_opcode_start - extension),
12246 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
12247 fragP->fr_fix += extension;
12248 }
12249 \f
12250 /* Apply a fixup (fixP) to segment data, once it has been determined
12251 by our caller that we have all the info we need to fix it up.
12252
12253 Parameter valP is the pointer to the value of the bits.
12254
12255 On the 386, immediates, displacements, and data pointers are all in
12256 the same (little-endian) format, so we don't need to care about which
12257 we are handling. */
12258
12259 void
12260 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12261 {
12262 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
12263 valueT value = *valP;
12264
12265 #if !defined (TE_Mach)
12266 if (fixP->fx_pcrel)
12267 {
12268 switch (fixP->fx_r_type)
12269 {
12270 default:
12271 break;
12272
12273 case BFD_RELOC_64:
12274 fixP->fx_r_type = BFD_RELOC_64_PCREL;
12275 break;
12276 case BFD_RELOC_32:
12277 case BFD_RELOC_X86_64_32S:
12278 fixP->fx_r_type = BFD_RELOC_32_PCREL;
12279 break;
12280 case BFD_RELOC_16:
12281 fixP->fx_r_type = BFD_RELOC_16_PCREL;
12282 break;
12283 case BFD_RELOC_8:
12284 fixP->fx_r_type = BFD_RELOC_8_PCREL;
12285 break;
12286 }
12287 }
12288
12289 if (fixP->fx_addsy != NULL
12290 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
12291 || fixP->fx_r_type == BFD_RELOC_64_PCREL
12292 || fixP->fx_r_type == BFD_RELOC_16_PCREL
12293 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
12294 && !use_rela_relocations)
12295 {
12296 /* This is a hack. There should be a better way to handle this.
12297 This covers for the fact that bfd_install_relocation will
12298 subtract the current location (for partial_inplace, PC relative
12299 relocations); see more below. */
12300 #ifndef OBJ_AOUT
12301 if (IS_ELF
12302 #ifdef TE_PE
12303 || OUTPUT_FLAVOR == bfd_target_coff_flavour
12304 #endif
12305 )
12306 value += fixP->fx_where + fixP->fx_frag->fr_address;
12307 #endif
12308 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12309 if (IS_ELF)
12310 {
12311 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
12312
12313 if ((sym_seg == seg
12314 || (symbol_section_p (fixP->fx_addsy)
12315 && sym_seg != absolute_section))
12316 && !generic_force_reloc (fixP))
12317 {
12318 /* Yes, we add the values in twice. This is because
12319 bfd_install_relocation subtracts them out again. I think
12320 bfd_install_relocation is broken, but I don't dare change
12321 it. FIXME. */
12322 value += fixP->fx_where + fixP->fx_frag->fr_address;
12323 }
12324 }
12325 #endif
12326 #if defined (OBJ_COFF) && defined (TE_PE)
12327 /* For some reason, the PE format does not store a
12328 section address offset for a PC relative symbol. */
12329 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
12330 || S_IS_WEAK (fixP->fx_addsy))
12331 value += md_pcrel_from (fixP);
12332 #endif
12333 }
12334 #if defined (OBJ_COFF) && defined (TE_PE)
12335 if (fixP->fx_addsy != NULL
12336 && S_IS_WEAK (fixP->fx_addsy)
12337 /* PR 16858: Do not modify weak function references. */
12338 && ! fixP->fx_pcrel)
12339 {
12340 #if !defined (TE_PEP)
12341 /* For x86 PE weak function symbols are neither PC-relative
12342 nor do they set S_IS_FUNCTION. So the only reliable way
12343 to detect them is to check the flags of their containing
12344 section. */
12345 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
12346 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
12347 ;
12348 else
12349 #endif
12350 value -= S_GET_VALUE (fixP->fx_addsy);
12351 }
12352 #endif
12353
12354 /* Fix a few things - the dynamic linker expects certain values here,
12355 and we must not disappoint it. */
12356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12357 if (IS_ELF && fixP->fx_addsy)
12358 switch (fixP->fx_r_type)
12359 {
12360 case BFD_RELOC_386_PLT32:
12361 case BFD_RELOC_X86_64_PLT32:
12362 /* Make the jump instruction point to the address of the operand.
12363 At runtime we merely add the offset to the actual PLT entry.
12364 NB: Subtract the offset size only for jump instructions. */
12365 if (fixP->fx_pcrel)
12366 value = -4;
12367 break;
12368
12369 case BFD_RELOC_386_TLS_GD:
12370 case BFD_RELOC_386_TLS_LDM:
12371 case BFD_RELOC_386_TLS_IE_32:
12372 case BFD_RELOC_386_TLS_IE:
12373 case BFD_RELOC_386_TLS_GOTIE:
12374 case BFD_RELOC_386_TLS_GOTDESC:
12375 case BFD_RELOC_X86_64_TLSGD:
12376 case BFD_RELOC_X86_64_TLSLD:
12377 case BFD_RELOC_X86_64_GOTTPOFF:
12378 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12379 value = 0; /* Fully resolved at runtime. No addend. */
12380 /* Fallthrough */
12381 case BFD_RELOC_386_TLS_LE:
12382 case BFD_RELOC_386_TLS_LDO_32:
12383 case BFD_RELOC_386_TLS_LE_32:
12384 case BFD_RELOC_X86_64_DTPOFF32:
12385 case BFD_RELOC_X86_64_DTPOFF64:
12386 case BFD_RELOC_X86_64_TPOFF32:
12387 case BFD_RELOC_X86_64_TPOFF64:
12388 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12389 break;
12390
12391 case BFD_RELOC_386_TLS_DESC_CALL:
12392 case BFD_RELOC_X86_64_TLSDESC_CALL:
12393 value = 0; /* Fully resolved at runtime. No addend. */
12394 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12395 fixP->fx_done = 0;
12396 return;
12397
12398 case BFD_RELOC_VTABLE_INHERIT:
12399 case BFD_RELOC_VTABLE_ENTRY:
12400 fixP->fx_done = 0;
12401 return;
12402
12403 default:
12404 break;
12405 }
12406 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12407 *valP = value;
12408 #endif /* !defined (TE_Mach) */
12409
12410 /* Are we finished with this relocation now? */
12411 if (fixP->fx_addsy == NULL)
12412 fixP->fx_done = 1;
12413 #if defined (OBJ_COFF) && defined (TE_PE)
12414 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
12415 {
12416 fixP->fx_done = 0;
12417 /* Remember value for tc_gen_reloc. */
12418 fixP->fx_addnumber = value;
12419 /* Clear out the frag for now. */
12420 value = 0;
12421 }
12422 #endif
12423 else if (use_rela_relocations)
12424 {
12425 fixP->fx_no_overflow = 1;
12426 /* Remember value for tc_gen_reloc. */
12427 fixP->fx_addnumber = value;
12428 value = 0;
12429 }
12430
12431 md_number_to_chars (p, value, fixP->fx_size);
12432 }
12433 \f
12434 const char *
12435 md_atof (int type, char *litP, int *sizeP)
12436 {
12437 /* This outputs the LITTLENUMs in REVERSE order;
12438 in accord with the bigendian 386. */
12439 return ieee_md_atof (type, litP, sizeP, FALSE);
12440 }
12441 \f
12442 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
12443
12444 static char *
12445 output_invalid (int c)
12446 {
12447 if (ISPRINT (c))
12448 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12449 "'%c'", c);
12450 else
12451 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12452 "(0x%x)", (unsigned char) c);
12453 return output_invalid_buf;
12454 }
12455
12456 /* Verify that @r can be used in the current context. */
12457
12458 static bfd_boolean check_register (const reg_entry *r)
12459 {
12460 if (allow_pseudo_reg)
12461 return TRUE;
12462
12463 if (operand_type_all_zero (&r->reg_type))
12464 return FALSE;
12465
12466 if ((r->reg_type.bitfield.dword
12467 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
12468 || r->reg_type.bitfield.class == RegCR
12469 || r->reg_type.bitfield.class == RegDR)
12470 && !cpu_arch_flags.bitfield.cpui386)
12471 return FALSE;
12472
12473 if (r->reg_type.bitfield.class == RegTR
12474 && (flag_code == CODE_64BIT
12475 || !cpu_arch_flags.bitfield.cpui386
12476 || cpu_arch_isa_flags.bitfield.cpui586
12477 || cpu_arch_isa_flags.bitfield.cpui686))
12478 return FALSE;
12479
12480 if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
12481 return FALSE;
12482
12483 if (!cpu_arch_flags.bitfield.cpuavx512f)
12484 {
12485 if (r->reg_type.bitfield.zmmword
12486 || r->reg_type.bitfield.class == RegMask)
12487 return FALSE;
12488
12489 if (!cpu_arch_flags.bitfield.cpuavx)
12490 {
12491 if (r->reg_type.bitfield.ymmword)
12492 return FALSE;
12493
12494 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
12495 return FALSE;
12496 }
12497 }
12498
12499 if (r->reg_type.bitfield.tmmword
12500 && (!cpu_arch_flags.bitfield.cpuamx_tile
12501 || flag_code != CODE_64BIT))
12502 return FALSE;
12503
12504 if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
12505 return FALSE;
12506
12507 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12508 if (!allow_index_reg && r->reg_num == RegIZ)
12509 return FALSE;
12510
12511 /* Upper 16 vector registers are only available with VREX in 64bit
12512 mode, and require EVEX encoding. */
12513 if (r->reg_flags & RegVRex)
12514 {
12515 if (!cpu_arch_flags.bitfield.cpuavx512f
12516 || flag_code != CODE_64BIT)
12517 return FALSE;
12518
12519 if (i.vec_encoding == vex_encoding_default)
12520 i.vec_encoding = vex_encoding_evex;
12521 else if (i.vec_encoding != vex_encoding_evex)
12522 i.vec_encoding = vex_encoding_error;
12523 }
12524
12525 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
12526 && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
12527 && flag_code != CODE_64BIT)
12528 return FALSE;
12529
12530 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
12531 && !intel_syntax)
12532 return FALSE;
12533
12534 return TRUE;
12535 }
12536
12537 /* REG_STRING starts *before* REGISTER_PREFIX. */
12538
12539 static const reg_entry *
12540 parse_real_register (char *reg_string, char **end_op)
12541 {
12542 char *s = reg_string;
12543 char *p;
12544 char reg_name_given[MAX_REG_NAME_SIZE + 1];
12545 const reg_entry *r;
12546
12547 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12548 if (*s == REGISTER_PREFIX)
12549 ++s;
12550
12551 if (is_space_char (*s))
12552 ++s;
12553
12554 p = reg_name_given;
12555 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
12556 {
12557 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
12558 return (const reg_entry *) NULL;
12559 s++;
12560 }
12561
12562 /* For naked regs, make sure that we are not dealing with an identifier.
12563 This prevents confusing an identifier like `eax_var' with register
12564 `eax'. */
12565 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
12566 return (const reg_entry *) NULL;
12567
12568 *end_op = s;
12569
12570 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
12571
12572 /* Handle floating point regs, allowing spaces in the (i) part. */
12573 if (r == i386_regtab /* %st is first entry of table */)
12574 {
12575 if (!cpu_arch_flags.bitfield.cpu8087
12576 && !cpu_arch_flags.bitfield.cpu287
12577 && !cpu_arch_flags.bitfield.cpu387
12578 && !allow_pseudo_reg)
12579 return (const reg_entry *) NULL;
12580
12581 if (is_space_char (*s))
12582 ++s;
12583 if (*s == '(')
12584 {
12585 ++s;
12586 if (is_space_char (*s))
12587 ++s;
12588 if (*s >= '0' && *s <= '7')
12589 {
12590 int fpr = *s - '0';
12591 ++s;
12592 if (is_space_char (*s))
12593 ++s;
12594 if (*s == ')')
12595 {
12596 *end_op = s + 1;
12597 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
12598 know (r);
12599 return r + fpr;
12600 }
12601 }
12602 /* We have "%st(" then garbage. */
12603 return (const reg_entry *) NULL;
12604 }
12605 }
12606
12607 return r && check_register (r) ? r : NULL;
12608 }
12609
12610 /* REG_STRING starts *before* REGISTER_PREFIX. */
12611
12612 static const reg_entry *
12613 parse_register (char *reg_string, char **end_op)
12614 {
12615 const reg_entry *r;
12616
12617 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
12618 r = parse_real_register (reg_string, end_op);
12619 else
12620 r = NULL;
12621 if (!r)
12622 {
12623 char *save = input_line_pointer;
12624 char c;
12625 symbolS *symbolP;
12626
12627 input_line_pointer = reg_string;
12628 c = get_symbol_name (&reg_string);
12629 symbolP = symbol_find (reg_string);
12630 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
12631 {
12632 const expressionS *e = symbol_get_value_expression (symbolP);
12633
12634 know (e->X_op == O_register);
12635 know (e->X_add_number >= 0
12636 && (valueT) e->X_add_number < i386_regtab_size);
12637 r = i386_regtab + e->X_add_number;
12638 if (!check_register (r))
12639 {
12640 as_bad (_("register '%s%s' cannot be used here"),
12641 register_prefix, r->reg_name);
12642 r = &bad_reg;
12643 }
12644 *end_op = input_line_pointer;
12645 }
12646 *input_line_pointer = c;
12647 input_line_pointer = save;
12648 }
12649 return r;
12650 }
12651
12652 int
12653 i386_parse_name (char *name, expressionS *e, char *nextcharP)
12654 {
12655 const reg_entry *r;
12656 char *end = input_line_pointer;
12657
12658 *end = *nextcharP;
12659 r = parse_register (name, &input_line_pointer);
12660 if (r && end <= input_line_pointer)
12661 {
12662 *nextcharP = *input_line_pointer;
12663 *input_line_pointer = 0;
12664 if (r != &bad_reg)
12665 {
12666 e->X_op = O_register;
12667 e->X_add_number = r - i386_regtab;
12668 }
12669 else
12670 e->X_op = O_illegal;
12671 return 1;
12672 }
12673 input_line_pointer = end;
12674 *end = 0;
12675 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
12676 }
12677
12678 void
12679 md_operand (expressionS *e)
12680 {
12681 char *end;
12682 const reg_entry *r;
12683
12684 switch (*input_line_pointer)
12685 {
12686 case REGISTER_PREFIX:
12687 r = parse_real_register (input_line_pointer, &end);
12688 if (r)
12689 {
12690 e->X_op = O_register;
12691 e->X_add_number = r - i386_regtab;
12692 input_line_pointer = end;
12693 }
12694 break;
12695
12696 case '[':
12697 gas_assert (intel_syntax);
12698 end = input_line_pointer++;
12699 expression (e);
12700 if (*input_line_pointer == ']')
12701 {
12702 ++input_line_pointer;
12703 e->X_op_symbol = make_expr_symbol (e);
12704 e->X_add_symbol = NULL;
12705 e->X_add_number = 0;
12706 e->X_op = O_index;
12707 }
12708 else
12709 {
12710 e->X_op = O_absent;
12711 input_line_pointer = end;
12712 }
12713 break;
12714 }
12715 }
12716
12717 \f
12718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12719 const char *md_shortopts = "kVQ:sqnO::";
12720 #else
12721 const char *md_shortopts = "qnO::";
12722 #endif
12723
12724 #define OPTION_32 (OPTION_MD_BASE + 0)
12725 #define OPTION_64 (OPTION_MD_BASE + 1)
12726 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12727 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12728 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12729 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12730 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12731 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12732 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12733 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12734 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12735 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12736 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12737 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12738 #define OPTION_X32 (OPTION_MD_BASE + 14)
12739 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12740 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12741 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12742 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12743 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12744 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12745 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12746 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12747 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12748 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12749 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12750 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12751 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12752 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12753 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12754 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12755 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12756 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12757 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12758
12759 struct option md_longopts[] =
12760 {
12761 {"32", no_argument, NULL, OPTION_32},
12762 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12763 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12764 {"64", no_argument, NULL, OPTION_64},
12765 #endif
12766 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12767 {"x32", no_argument, NULL, OPTION_X32},
12768 {"mshared", no_argument, NULL, OPTION_MSHARED},
12769 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
12770 #endif
12771 {"divide", no_argument, NULL, OPTION_DIVIDE},
12772 {"march", required_argument, NULL, OPTION_MARCH},
12773 {"mtune", required_argument, NULL, OPTION_MTUNE},
12774 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
12775 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
12776 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
12777 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
12778 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
12779 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
12780 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
12781 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
12782 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
12783 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
12784 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
12785 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
12786 # if defined (TE_PE) || defined (TE_PEP)
12787 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
12788 #endif
12789 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
12790 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
12791 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
12792 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
12793 {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
12794 {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
12795 {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
12796 {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
12797 {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
12798 {"mlfence-before-indirect-branch", required_argument, NULL,
12799 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
12800 {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
12801 {"mamd64", no_argument, NULL, OPTION_MAMD64},
12802 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
12803 {NULL, no_argument, NULL, 0}
12804 };
12805 size_t md_longopts_size = sizeof (md_longopts);
12806
12807 int
12808 md_parse_option (int c, const char *arg)
12809 {
12810 unsigned int j;
12811 char *arch, *next, *saved, *type;
12812
12813 switch (c)
12814 {
12815 case 'n':
12816 optimize_align_code = 0;
12817 break;
12818
12819 case 'q':
12820 quiet_warnings = 1;
12821 break;
12822
12823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12824 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12825 should be emitted or not. FIXME: Not implemented. */
12826 case 'Q':
12827 if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
12828 return 0;
12829 break;
12830
12831 /* -V: SVR4 argument to print version ID. */
12832 case 'V':
12833 print_version_id ();
12834 break;
12835
12836 /* -k: Ignore for FreeBSD compatibility. */
12837 case 'k':
12838 break;
12839
12840 case 's':
12841 /* -s: On i386 Solaris, this tells the native assembler to use
12842 .stab instead of .stab.excl. We always use .stab anyhow. */
12843 break;
12844
12845 case OPTION_MSHARED:
12846 shared = 1;
12847 break;
12848
12849 case OPTION_X86_USED_NOTE:
12850 if (strcasecmp (arg, "yes") == 0)
12851 x86_used_note = 1;
12852 else if (strcasecmp (arg, "no") == 0)
12853 x86_used_note = 0;
12854 else
12855 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
12856 break;
12857
12858
12859 #endif
12860 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12861 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12862 case OPTION_64:
12863 {
12864 const char **list, **l;
12865
12866 list = bfd_target_list ();
12867 for (l = list; *l != NULL; l++)
12868 if (CONST_STRNEQ (*l, "elf64-x86-64")
12869 || strcmp (*l, "coff-x86-64") == 0
12870 || strcmp (*l, "pe-x86-64") == 0
12871 || strcmp (*l, "pei-x86-64") == 0
12872 || strcmp (*l, "mach-o-x86-64") == 0)
12873 {
12874 default_arch = "x86_64";
12875 break;
12876 }
12877 if (*l == NULL)
12878 as_fatal (_("no compiled in support for x86_64"));
12879 free (list);
12880 }
12881 break;
12882 #endif
12883
12884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12885 case OPTION_X32:
12886 if (IS_ELF)
12887 {
12888 const char **list, **l;
12889
12890 list = bfd_target_list ();
12891 for (l = list; *l != NULL; l++)
12892 if (CONST_STRNEQ (*l, "elf32-x86-64"))
12893 {
12894 default_arch = "x86_64:32";
12895 break;
12896 }
12897 if (*l == NULL)
12898 as_fatal (_("no compiled in support for 32bit x86_64"));
12899 free (list);
12900 }
12901 else
12902 as_fatal (_("32bit x86_64 is only supported for ELF"));
12903 break;
12904 #endif
12905
12906 case OPTION_32:
12907 default_arch = "i386";
12908 break;
12909
12910 case OPTION_DIVIDE:
12911 #ifdef SVR4_COMMENT_CHARS
12912 {
12913 char *n, *t;
12914 const char *s;
12915
12916 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
12917 t = n;
12918 for (s = i386_comment_chars; *s != '\0'; s++)
12919 if (*s != '/')
12920 *t++ = *s;
12921 *t = '\0';
12922 i386_comment_chars = n;
12923 }
12924 #endif
12925 break;
12926
12927 case OPTION_MARCH:
12928 saved = xstrdup (arg);
12929 arch = saved;
12930 /* Allow -march=+nosse. */
12931 if (*arch == '+')
12932 arch++;
12933 do
12934 {
12935 if (*arch == '.')
12936 as_fatal (_("invalid -march= option: `%s'"), arg);
12937 next = strchr (arch, '+');
12938 if (next)
12939 *next++ = '\0';
12940 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
12941 {
12942 if (strcmp (arch, cpu_arch [j].name) == 0)
12943 {
12944 /* Processor. */
12945 if (! cpu_arch[j].flags.bitfield.cpui386)
12946 continue;
12947
12948 cpu_arch_name = cpu_arch[j].name;
12949 cpu_sub_arch_name = NULL;
12950 cpu_arch_flags = cpu_arch[j].flags;
12951 cpu_arch_isa = cpu_arch[j].type;
12952 cpu_arch_isa_flags = cpu_arch[j].flags;
12953 if (!cpu_arch_tune_set)
12954 {
12955 cpu_arch_tune = cpu_arch_isa;
12956 cpu_arch_tune_flags = cpu_arch_isa_flags;
12957 }
12958 break;
12959 }
12960 else if (*cpu_arch [j].name == '.'
12961 && strcmp (arch, cpu_arch [j].name + 1) == 0)
12962 {
12963 /* ISA extension. */
12964 i386_cpu_flags flags;
12965
12966 flags = cpu_flags_or (cpu_arch_flags,
12967 cpu_arch[j].flags);
12968
12969 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
12970 {
12971 if (cpu_sub_arch_name)
12972 {
12973 char *name = cpu_sub_arch_name;
12974 cpu_sub_arch_name = concat (name,
12975 cpu_arch[j].name,
12976 (const char *) NULL);
12977 free (name);
12978 }
12979 else
12980 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
12981 cpu_arch_flags = flags;
12982 cpu_arch_isa_flags = flags;
12983 }
12984 else
12985 cpu_arch_isa_flags
12986 = cpu_flags_or (cpu_arch_isa_flags,
12987 cpu_arch[j].flags);
12988 break;
12989 }
12990 }
12991
12992 if (j >= ARRAY_SIZE (cpu_arch))
12993 {
12994 /* Disable an ISA extension. */
12995 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
12996 if (strcmp (arch, cpu_noarch [j].name) == 0)
12997 {
12998 i386_cpu_flags flags;
12999
13000 flags = cpu_flags_and_not (cpu_arch_flags,
13001 cpu_noarch[j].flags);
13002 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
13003 {
13004 if (cpu_sub_arch_name)
13005 {
13006 char *name = cpu_sub_arch_name;
13007 cpu_sub_arch_name = concat (arch,
13008 (const char *) NULL);
13009 free (name);
13010 }
13011 else
13012 cpu_sub_arch_name = xstrdup (arch);
13013 cpu_arch_flags = flags;
13014 cpu_arch_isa_flags = flags;
13015 }
13016 break;
13017 }
13018
13019 if (j >= ARRAY_SIZE (cpu_noarch))
13020 j = ARRAY_SIZE (cpu_arch);
13021 }
13022
13023 if (j >= ARRAY_SIZE (cpu_arch))
13024 as_fatal (_("invalid -march= option: `%s'"), arg);
13025
13026 arch = next;
13027 }
13028 while (next != NULL);
13029 free (saved);
13030 break;
13031
13032 case OPTION_MTUNE:
13033 if (*arg == '.')
13034 as_fatal (_("invalid -mtune= option: `%s'"), arg);
13035 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
13036 {
13037 if (strcmp (arg, cpu_arch [j].name) == 0)
13038 {
13039 cpu_arch_tune_set = 1;
13040 cpu_arch_tune = cpu_arch [j].type;
13041 cpu_arch_tune_flags = cpu_arch[j].flags;
13042 break;
13043 }
13044 }
13045 if (j >= ARRAY_SIZE (cpu_arch))
13046 as_fatal (_("invalid -mtune= option: `%s'"), arg);
13047 break;
13048
13049 case OPTION_MMNEMONIC:
13050 if (strcasecmp (arg, "att") == 0)
13051 intel_mnemonic = 0;
13052 else if (strcasecmp (arg, "intel") == 0)
13053 intel_mnemonic = 1;
13054 else
13055 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
13056 break;
13057
13058 case OPTION_MSYNTAX:
13059 if (strcasecmp (arg, "att") == 0)
13060 intel_syntax = 0;
13061 else if (strcasecmp (arg, "intel") == 0)
13062 intel_syntax = 1;
13063 else
13064 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
13065 break;
13066
13067 case OPTION_MINDEX_REG:
13068 allow_index_reg = 1;
13069 break;
13070
13071 case OPTION_MNAKED_REG:
13072 allow_naked_reg = 1;
13073 break;
13074
13075 case OPTION_MSSE2AVX:
13076 sse2avx = 1;
13077 break;
13078
13079 case OPTION_MSSE_CHECK:
13080 if (strcasecmp (arg, "error") == 0)
13081 sse_check = check_error;
13082 else if (strcasecmp (arg, "warning") == 0)
13083 sse_check = check_warning;
13084 else if (strcasecmp (arg, "none") == 0)
13085 sse_check = check_none;
13086 else
13087 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
13088 break;
13089
13090 case OPTION_MOPERAND_CHECK:
13091 if (strcasecmp (arg, "error") == 0)
13092 operand_check = check_error;
13093 else if (strcasecmp (arg, "warning") == 0)
13094 operand_check = check_warning;
13095 else if (strcasecmp (arg, "none") == 0)
13096 operand_check = check_none;
13097 else
13098 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
13099 break;
13100
13101 case OPTION_MAVXSCALAR:
13102 if (strcasecmp (arg, "128") == 0)
13103 avxscalar = vex128;
13104 else if (strcasecmp (arg, "256") == 0)
13105 avxscalar = vex256;
13106 else
13107 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
13108 break;
13109
13110 case OPTION_MVEXWIG:
13111 if (strcmp (arg, "0") == 0)
13112 vexwig = vexw0;
13113 else if (strcmp (arg, "1") == 0)
13114 vexwig = vexw1;
13115 else
13116 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
13117 break;
13118
13119 case OPTION_MADD_BND_PREFIX:
13120 add_bnd_prefix = 1;
13121 break;
13122
13123 case OPTION_MEVEXLIG:
13124 if (strcmp (arg, "128") == 0)
13125 evexlig = evexl128;
13126 else if (strcmp (arg, "256") == 0)
13127 evexlig = evexl256;
13128 else if (strcmp (arg, "512") == 0)
13129 evexlig = evexl512;
13130 else
13131 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
13132 break;
13133
13134 case OPTION_MEVEXRCIG:
13135 if (strcmp (arg, "rne") == 0)
13136 evexrcig = rne;
13137 else if (strcmp (arg, "rd") == 0)
13138 evexrcig = rd;
13139 else if (strcmp (arg, "ru") == 0)
13140 evexrcig = ru;
13141 else if (strcmp (arg, "rz") == 0)
13142 evexrcig = rz;
13143 else
13144 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
13145 break;
13146
13147 case OPTION_MEVEXWIG:
13148 if (strcmp (arg, "0") == 0)
13149 evexwig = evexw0;
13150 else if (strcmp (arg, "1") == 0)
13151 evexwig = evexw1;
13152 else
13153 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
13154 break;
13155
13156 # if defined (TE_PE) || defined (TE_PEP)
13157 case OPTION_MBIG_OBJ:
13158 use_big_obj = 1;
13159 break;
13160 #endif
13161
13162 case OPTION_MOMIT_LOCK_PREFIX:
13163 if (strcasecmp (arg, "yes") == 0)
13164 omit_lock_prefix = 1;
13165 else if (strcasecmp (arg, "no") == 0)
13166 omit_lock_prefix = 0;
13167 else
13168 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
13169 break;
13170
13171 case OPTION_MFENCE_AS_LOCK_ADD:
13172 if (strcasecmp (arg, "yes") == 0)
13173 avoid_fence = 1;
13174 else if (strcasecmp (arg, "no") == 0)
13175 avoid_fence = 0;
13176 else
13177 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
13178 break;
13179
13180 case OPTION_MLFENCE_AFTER_LOAD:
13181 if (strcasecmp (arg, "yes") == 0)
13182 lfence_after_load = 1;
13183 else if (strcasecmp (arg, "no") == 0)
13184 lfence_after_load = 0;
13185 else
13186 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
13187 break;
13188
13189 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
13190 if (strcasecmp (arg, "all") == 0)
13191 {
13192 lfence_before_indirect_branch = lfence_branch_all;
13193 if (lfence_before_ret == lfence_before_ret_none)
13194 lfence_before_ret = lfence_before_ret_shl;
13195 }
13196 else if (strcasecmp (arg, "memory") == 0)
13197 lfence_before_indirect_branch = lfence_branch_memory;
13198 else if (strcasecmp (arg, "register") == 0)
13199 lfence_before_indirect_branch = lfence_branch_register;
13200 else if (strcasecmp (arg, "none") == 0)
13201 lfence_before_indirect_branch = lfence_branch_none;
13202 else
13203 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13204 arg);
13205 break;
13206
13207 case OPTION_MLFENCE_BEFORE_RET:
13208 if (strcasecmp (arg, "or") == 0)
13209 lfence_before_ret = lfence_before_ret_or;
13210 else if (strcasecmp (arg, "not") == 0)
13211 lfence_before_ret = lfence_before_ret_not;
13212 else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
13213 lfence_before_ret = lfence_before_ret_shl;
13214 else if (strcasecmp (arg, "none") == 0)
13215 lfence_before_ret = lfence_before_ret_none;
13216 else
13217 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13218 arg);
13219 break;
13220
13221 case OPTION_MRELAX_RELOCATIONS:
13222 if (strcasecmp (arg, "yes") == 0)
13223 generate_relax_relocations = 1;
13224 else if (strcasecmp (arg, "no") == 0)
13225 generate_relax_relocations = 0;
13226 else
13227 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
13228 break;
13229
13230 case OPTION_MALIGN_BRANCH_BOUNDARY:
13231 {
13232 char *end;
13233 long int align = strtoul (arg, &end, 0);
13234 if (*end == '\0')
13235 {
13236 if (align == 0)
13237 {
13238 align_branch_power = 0;
13239 break;
13240 }
13241 else if (align >= 16)
13242 {
13243 int align_power;
13244 for (align_power = 0;
13245 (align & 1) == 0;
13246 align >>= 1, align_power++)
13247 continue;
13248 /* Limit alignment power to 31. */
13249 if (align == 1 && align_power < 32)
13250 {
13251 align_branch_power = align_power;
13252 break;
13253 }
13254 }
13255 }
13256 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
13257 }
13258 break;
13259
13260 case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
13261 {
13262 char *end;
13263 int align = strtoul (arg, &end, 0);
13264 /* Some processors only support 5 prefixes. */
13265 if (*end == '\0' && align >= 0 && align < 6)
13266 {
13267 align_branch_prefix_size = align;
13268 break;
13269 }
13270 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13271 arg);
13272 }
13273 break;
13274
13275 case OPTION_MALIGN_BRANCH:
13276 align_branch = 0;
13277 saved = xstrdup (arg);
13278 type = saved;
13279 do
13280 {
13281 next = strchr (type, '+');
13282 if (next)
13283 *next++ = '\0';
13284 if (strcasecmp (type, "jcc") == 0)
13285 align_branch |= align_branch_jcc_bit;
13286 else if (strcasecmp (type, "fused") == 0)
13287 align_branch |= align_branch_fused_bit;
13288 else if (strcasecmp (type, "jmp") == 0)
13289 align_branch |= align_branch_jmp_bit;
13290 else if (strcasecmp (type, "call") == 0)
13291 align_branch |= align_branch_call_bit;
13292 else if (strcasecmp (type, "ret") == 0)
13293 align_branch |= align_branch_ret_bit;
13294 else if (strcasecmp (type, "indirect") == 0)
13295 align_branch |= align_branch_indirect_bit;
13296 else
13297 as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
13298 type = next;
13299 }
13300 while (next != NULL);
13301 free (saved);
13302 break;
13303
13304 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
13305 align_branch_power = 5;
13306 align_branch_prefix_size = 5;
13307 align_branch = (align_branch_jcc_bit
13308 | align_branch_fused_bit
13309 | align_branch_jmp_bit);
13310 break;
13311
13312 case OPTION_MAMD64:
13313 isa64 = amd64;
13314 break;
13315
13316 case OPTION_MINTEL64:
13317 isa64 = intel64;
13318 break;
13319
13320 case 'O':
13321 if (arg == NULL)
13322 {
13323 optimize = 1;
13324 /* Turn off -Os. */
13325 optimize_for_space = 0;
13326 }
13327 else if (*arg == 's')
13328 {
13329 optimize_for_space = 1;
13330 /* Turn on all encoding optimizations. */
13331 optimize = INT_MAX;
13332 }
13333 else
13334 {
13335 optimize = atoi (arg);
13336 /* Turn off -Os. */
13337 optimize_for_space = 0;
13338 }
13339 break;
13340
13341 default:
13342 return 0;
13343 }
13344 return 1;
13345 }
13346
13347 #define MESSAGE_TEMPLATE \
13348 " "
13349
13350 static char *
13351 output_message (FILE *stream, char *p, char *message, char *start,
13352 int *left_p, const char *name, int len)
13353 {
13354 int size = sizeof (MESSAGE_TEMPLATE);
13355 int left = *left_p;
13356
13357 /* Reserve 2 spaces for ", " or ",\0" */
13358 left -= len + 2;
13359
13360 /* Check if there is any room. */
13361 if (left >= 0)
13362 {
13363 if (p != start)
13364 {
13365 *p++ = ',';
13366 *p++ = ' ';
13367 }
13368 p = mempcpy (p, name, len);
13369 }
13370 else
13371 {
13372 /* Output the current message now and start a new one. */
13373 *p++ = ',';
13374 *p = '\0';
13375 fprintf (stream, "%s\n", message);
13376 p = start;
13377 left = size - (start - message) - len - 2;
13378
13379 gas_assert (left >= 0);
13380
13381 p = mempcpy (p, name, len);
13382 }
13383
13384 *left_p = left;
13385 return p;
13386 }
13387
13388 static void
13389 show_arch (FILE *stream, int ext, int check)
13390 {
13391 static char message[] = MESSAGE_TEMPLATE;
13392 char *start = message + 27;
13393 char *p;
13394 int size = sizeof (MESSAGE_TEMPLATE);
13395 int left;
13396 const char *name;
13397 int len;
13398 unsigned int j;
13399
13400 p = start;
13401 left = size - (start - message);
13402 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
13403 {
13404 /* Should it be skipped? */
13405 if (cpu_arch [j].skip)
13406 continue;
13407
13408 name = cpu_arch [j].name;
13409 len = cpu_arch [j].len;
13410 if (*name == '.')
13411 {
13412 /* It is an extension. Skip if we aren't asked to show it. */
13413 if (ext)
13414 {
13415 name++;
13416 len--;
13417 }
13418 else
13419 continue;
13420 }
13421 else if (ext)
13422 {
13423 /* It is an processor. Skip if we show only extension. */
13424 continue;
13425 }
13426 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
13427 {
13428 /* It is an impossible processor - skip. */
13429 continue;
13430 }
13431
13432 p = output_message (stream, p, message, start, &left, name, len);
13433 }
13434
13435 /* Display disabled extensions. */
13436 if (ext)
13437 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
13438 {
13439 name = cpu_noarch [j].name;
13440 len = cpu_noarch [j].len;
13441 p = output_message (stream, p, message, start, &left, name,
13442 len);
13443 }
13444
13445 *p = '\0';
13446 fprintf (stream, "%s\n", message);
13447 }
13448
13449 void
13450 md_show_usage (FILE *stream)
13451 {
13452 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13453 fprintf (stream, _("\
13454 -Qy, -Qn ignored\n\
13455 -V print assembler version number\n\
13456 -k ignored\n"));
13457 #endif
13458 fprintf (stream, _("\
13459 -n Do not optimize code alignment\n\
13460 -q quieten some warnings\n"));
13461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13462 fprintf (stream, _("\
13463 -s ignored\n"));
13464 #endif
13465 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13466 || defined (TE_PE) || defined (TE_PEP))
13467 fprintf (stream, _("\
13468 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13469 #endif
13470 #ifdef SVR4_COMMENT_CHARS
13471 fprintf (stream, _("\
13472 --divide do not treat `/' as a comment character\n"));
13473 #else
13474 fprintf (stream, _("\
13475 --divide ignored\n"));
13476 #endif
13477 fprintf (stream, _("\
13478 -march=CPU[,+EXTENSION...]\n\
13479 generate code for CPU and EXTENSION, CPU is one of:\n"));
13480 show_arch (stream, 0, 1);
13481 fprintf (stream, _("\
13482 EXTENSION is combination of:\n"));
13483 show_arch (stream, 1, 0);
13484 fprintf (stream, _("\
13485 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13486 show_arch (stream, 0, 0);
13487 fprintf (stream, _("\
13488 -msse2avx encode SSE instructions with VEX prefix\n"));
13489 fprintf (stream, _("\
13490 -msse-check=[none|error|warning] (default: warning)\n\
13491 check SSE instructions\n"));
13492 fprintf (stream, _("\
13493 -moperand-check=[none|error|warning] (default: warning)\n\
13494 check operand combinations for validity\n"));
13495 fprintf (stream, _("\
13496 -mavxscalar=[128|256] (default: 128)\n\
13497 encode scalar AVX instructions with specific vector\n\
13498 length\n"));
13499 fprintf (stream, _("\
13500 -mvexwig=[0|1] (default: 0)\n\
13501 encode VEX instructions with specific VEX.W value\n\
13502 for VEX.W bit ignored instructions\n"));
13503 fprintf (stream, _("\
13504 -mevexlig=[128|256|512] (default: 128)\n\
13505 encode scalar EVEX instructions with specific vector\n\
13506 length\n"));
13507 fprintf (stream, _("\
13508 -mevexwig=[0|1] (default: 0)\n\
13509 encode EVEX instructions with specific EVEX.W value\n\
13510 for EVEX.W bit ignored instructions\n"));
13511 fprintf (stream, _("\
13512 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13513 encode EVEX instructions with specific EVEX.RC value\n\
13514 for SAE-only ignored instructions\n"));
13515 fprintf (stream, _("\
13516 -mmnemonic=[att|intel] "));
13517 if (SYSV386_COMPAT)
13518 fprintf (stream, _("(default: att)\n"));
13519 else
13520 fprintf (stream, _("(default: intel)\n"));
13521 fprintf (stream, _("\
13522 use AT&T/Intel mnemonic\n"));
13523 fprintf (stream, _("\
13524 -msyntax=[att|intel] (default: att)\n\
13525 use AT&T/Intel syntax\n"));
13526 fprintf (stream, _("\
13527 -mindex-reg support pseudo index registers\n"));
13528 fprintf (stream, _("\
13529 -mnaked-reg don't require `%%' prefix for registers\n"));
13530 fprintf (stream, _("\
13531 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13533 fprintf (stream, _("\
13534 -mshared disable branch optimization for shared code\n"));
13535 fprintf (stream, _("\
13536 -mx86-used-note=[no|yes] "));
13537 if (DEFAULT_X86_USED_NOTE)
13538 fprintf (stream, _("(default: yes)\n"));
13539 else
13540 fprintf (stream, _("(default: no)\n"));
13541 fprintf (stream, _("\
13542 generate x86 used ISA and feature properties\n"));
13543 #endif
13544 #if defined (TE_PE) || defined (TE_PEP)
13545 fprintf (stream, _("\
13546 -mbig-obj generate big object files\n"));
13547 #endif
13548 fprintf (stream, _("\
13549 -momit-lock-prefix=[no|yes] (default: no)\n\
13550 strip all lock prefixes\n"));
13551 fprintf (stream, _("\
13552 -mfence-as-lock-add=[no|yes] (default: no)\n\
13553 encode lfence, mfence and sfence as\n\
13554 lock addl $0x0, (%%{re}sp)\n"));
13555 fprintf (stream, _("\
13556 -mrelax-relocations=[no|yes] "));
13557 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
13558 fprintf (stream, _("(default: yes)\n"));
13559 else
13560 fprintf (stream, _("(default: no)\n"));
13561 fprintf (stream, _("\
13562 generate relax relocations\n"));
13563 fprintf (stream, _("\
13564 -malign-branch-boundary=NUM (default: 0)\n\
13565 align branches within NUM byte boundary\n"));
13566 fprintf (stream, _("\
13567 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13568 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13569 indirect\n\
13570 specify types of branches to align\n"));
13571 fprintf (stream, _("\
13572 -malign-branch-prefix-size=NUM (default: 5)\n\
13573 align branches with NUM prefixes per instruction\n"));
13574 fprintf (stream, _("\
13575 -mbranches-within-32B-boundaries\n\
13576 align branches within 32 byte boundary\n"));
13577 fprintf (stream, _("\
13578 -mlfence-after-load=[no|yes] (default: no)\n\
13579 generate lfence after load\n"));
13580 fprintf (stream, _("\
13581 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13582 generate lfence before indirect near branch\n"));
13583 fprintf (stream, _("\
13584 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13585 generate lfence before ret\n"));
13586 fprintf (stream, _("\
13587 -mamd64 accept only AMD64 ISA [default]\n"));
13588 fprintf (stream, _("\
13589 -mintel64 accept only Intel64 ISA\n"));
13590 }
13591
13592 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13593 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13594 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13595
13596 /* Pick the target format to use. */
13597
13598 const char *
13599 i386_target_format (void)
13600 {
13601 if (!strncmp (default_arch, "x86_64", 6))
13602 {
13603 update_code_flag (CODE_64BIT, 1);
13604 if (default_arch[6] == '\0')
13605 x86_elf_abi = X86_64_ABI;
13606 else
13607 x86_elf_abi = X86_64_X32_ABI;
13608 }
13609 else if (!strcmp (default_arch, "i386"))
13610 update_code_flag (CODE_32BIT, 1);
13611 else if (!strcmp (default_arch, "iamcu"))
13612 {
13613 update_code_flag (CODE_32BIT, 1);
13614 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
13615 {
13616 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
13617 cpu_arch_name = "iamcu";
13618 cpu_sub_arch_name = NULL;
13619 cpu_arch_flags = iamcu_flags;
13620 cpu_arch_isa = PROCESSOR_IAMCU;
13621 cpu_arch_isa_flags = iamcu_flags;
13622 if (!cpu_arch_tune_set)
13623 {
13624 cpu_arch_tune = cpu_arch_isa;
13625 cpu_arch_tune_flags = cpu_arch_isa_flags;
13626 }
13627 }
13628 else if (cpu_arch_isa != PROCESSOR_IAMCU)
13629 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13630 cpu_arch_name);
13631 }
13632 else
13633 as_fatal (_("unknown architecture"));
13634
13635 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
13636 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13637 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
13638 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13639
13640 switch (OUTPUT_FLAVOR)
13641 {
13642 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13643 case bfd_target_aout_flavour:
13644 return AOUT_TARGET_FORMAT;
13645 #endif
13646 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13647 # if defined (TE_PE) || defined (TE_PEP)
13648 case bfd_target_coff_flavour:
13649 if (flag_code == CODE_64BIT)
13650 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
13651 else
13652 return use_big_obj ? "pe-bigobj-i386" : "pe-i386";
13653 # elif defined (TE_GO32)
13654 case bfd_target_coff_flavour:
13655 return "coff-go32";
13656 # else
13657 case bfd_target_coff_flavour:
13658 return "coff-i386";
13659 # endif
13660 #endif
13661 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13662 case bfd_target_elf_flavour:
13663 {
13664 const char *format;
13665
13666 switch (x86_elf_abi)
13667 {
13668 default:
13669 format = ELF_TARGET_FORMAT;
13670 #ifndef TE_SOLARIS
13671 tls_get_addr = "___tls_get_addr";
13672 #endif
13673 break;
13674 case X86_64_ABI:
13675 use_rela_relocations = 1;
13676 object_64bit = 1;
13677 #ifndef TE_SOLARIS
13678 tls_get_addr = "__tls_get_addr";
13679 #endif
13680 format = ELF_TARGET_FORMAT64;
13681 break;
13682 case X86_64_X32_ABI:
13683 use_rela_relocations = 1;
13684 object_64bit = 1;
13685 #ifndef TE_SOLARIS
13686 tls_get_addr = "__tls_get_addr";
13687 #endif
13688 disallow_64bit_reloc = 1;
13689 format = ELF_TARGET_FORMAT32;
13690 break;
13691 }
13692 if (cpu_arch_isa == PROCESSOR_L1OM)
13693 {
13694 if (x86_elf_abi != X86_64_ABI)
13695 as_fatal (_("Intel L1OM is 64bit only"));
13696 return ELF_TARGET_L1OM_FORMAT;
13697 }
13698 else if (cpu_arch_isa == PROCESSOR_K1OM)
13699 {
13700 if (x86_elf_abi != X86_64_ABI)
13701 as_fatal (_("Intel K1OM is 64bit only"));
13702 return ELF_TARGET_K1OM_FORMAT;
13703 }
13704 else if (cpu_arch_isa == PROCESSOR_IAMCU)
13705 {
13706 if (x86_elf_abi != I386_ABI)
13707 as_fatal (_("Intel MCU is 32bit only"));
13708 return ELF_TARGET_IAMCU_FORMAT;
13709 }
13710 else
13711 return format;
13712 }
13713 #endif
13714 #if defined (OBJ_MACH_O)
13715 case bfd_target_mach_o_flavour:
13716 if (flag_code == CODE_64BIT)
13717 {
13718 use_rela_relocations = 1;
13719 object_64bit = 1;
13720 return "mach-o-x86-64";
13721 }
13722 else
13723 return "mach-o-i386";
13724 #endif
13725 default:
13726 abort ();
13727 return NULL;
13728 }
13729 }
13730
13731 #endif /* OBJ_MAYBE_ more than one */
13732 \f
13733 symbolS *
13734 md_undefined_symbol (char *name)
13735 {
13736 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
13737 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
13738 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
13739 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
13740 {
13741 if (!GOT_symbol)
13742 {
13743 if (symbol_find (name))
13744 as_bad (_("GOT already in symbol table"));
13745 GOT_symbol = symbol_new (name, undefined_section,
13746 (valueT) 0, &zero_address_frag);
13747 };
13748 return GOT_symbol;
13749 }
13750 return 0;
13751 }
13752
13753 /* Round up a section size to the appropriate boundary. */
13754
13755 valueT
13756 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
13757 {
13758 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13759 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
13760 {
13761 /* For a.out, force the section size to be aligned. If we don't do
13762 this, BFD will align it for us, but it will not write out the
13763 final bytes of the section. This may be a bug in BFD, but it is
13764 easier to fix it here since that is how the other a.out targets
13765 work. */
13766 int align;
13767
13768 align = bfd_section_alignment (segment);
13769 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
13770 }
13771 #endif
13772
13773 return size;
13774 }
13775
13776 /* On the i386, PC-relative offsets are relative to the start of the
13777 next instruction. That is, the address of the offset, plus its
13778 size, since the offset is always the last part of the insn. */
13779
13780 long
13781 md_pcrel_from (fixS *fixP)
13782 {
13783 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
13784 }
13785
13786 #ifndef I386COFF
13787
13788 static void
13789 s_bss (int ignore ATTRIBUTE_UNUSED)
13790 {
13791 int temp;
13792
13793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13794 if (IS_ELF)
13795 obj_elf_section_change_hook ();
13796 #endif
13797 temp = get_absolute_expression ();
13798 subseg_set (bss_section, (subsegT) temp);
13799 demand_empty_rest_of_line ();
13800 }
13801
13802 #endif
13803
13804 /* Remember constant directive. */
13805
13806 void
13807 i386_cons_align (int ignore ATTRIBUTE_UNUSED)
13808 {
13809 if (last_insn.kind != last_insn_directive
13810 && (bfd_section_flags (now_seg) & SEC_CODE))
13811 {
13812 last_insn.seg = now_seg;
13813 last_insn.kind = last_insn_directive;
13814 last_insn.name = "constant directive";
13815 last_insn.file = as_where (&last_insn.line);
13816 if (lfence_before_ret != lfence_before_ret_none)
13817 {
13818 if (lfence_before_indirect_branch != lfence_branch_none)
13819 as_warn (_("constant directive skips -mlfence-before-ret "
13820 "and -mlfence-before-indirect-branch"));
13821 else
13822 as_warn (_("constant directive skips -mlfence-before-ret"));
13823 }
13824 else if (lfence_before_indirect_branch != lfence_branch_none)
13825 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13826 }
13827 }
13828
13829 void
13830 i386_validate_fix (fixS *fixp)
13831 {
13832 if (fixp->fx_subsy)
13833 {
13834 if (fixp->fx_subsy == GOT_symbol)
13835 {
13836 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
13837 {
13838 if (!object_64bit)
13839 abort ();
13840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13841 if (fixp->fx_tcbit2)
13842 fixp->fx_r_type = (fixp->fx_tcbit
13843 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13844 : BFD_RELOC_X86_64_GOTPCRELX);
13845 else
13846 #endif
13847 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
13848 }
13849 else
13850 {
13851 if (!object_64bit)
13852 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
13853 else
13854 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
13855 }
13856 fixp->fx_subsy = 0;
13857 }
13858 }
13859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13860 else if (!object_64bit)
13861 {
13862 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
13863 && fixp->fx_tcbit2)
13864 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
13865 }
13866 #endif
13867 }
13868
13869 arelent *
13870 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13871 {
13872 arelent *rel;
13873 bfd_reloc_code_real_type code;
13874
13875 switch (fixp->fx_r_type)
13876 {
13877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13878 case BFD_RELOC_SIZE32:
13879 case BFD_RELOC_SIZE64:
13880 if (S_IS_DEFINED (fixp->fx_addsy)
13881 && !S_IS_EXTERNAL (fixp->fx_addsy))
13882 {
13883 /* Resolve size relocation against local symbol to size of
13884 the symbol plus addend. */
13885 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
13886 if (fixp->fx_r_type == BFD_RELOC_SIZE32
13887 && !fits_in_unsigned_long (value))
13888 as_bad_where (fixp->fx_file, fixp->fx_line,
13889 _("symbol size computation overflow"));
13890 fixp->fx_addsy = NULL;
13891 fixp->fx_subsy = NULL;
13892 md_apply_fix (fixp, (valueT *) &value, NULL);
13893 return NULL;
13894 }
13895 #endif
13896 /* Fall through. */
13897
13898 case BFD_RELOC_X86_64_PLT32:
13899 case BFD_RELOC_X86_64_GOT32:
13900 case BFD_RELOC_X86_64_GOTPCREL:
13901 case BFD_RELOC_X86_64_GOTPCRELX:
13902 case BFD_RELOC_X86_64_REX_GOTPCRELX:
13903 case BFD_RELOC_386_PLT32:
13904 case BFD_RELOC_386_GOT32:
13905 case BFD_RELOC_386_GOT32X:
13906 case BFD_RELOC_386_GOTOFF:
13907 case BFD_RELOC_386_GOTPC:
13908 case BFD_RELOC_386_TLS_GD:
13909 case BFD_RELOC_386_TLS_LDM:
13910 case BFD_RELOC_386_TLS_LDO_32:
13911 case BFD_RELOC_386_TLS_IE_32:
13912 case BFD_RELOC_386_TLS_IE:
13913 case BFD_RELOC_386_TLS_GOTIE:
13914 case BFD_RELOC_386_TLS_LE_32:
13915 case BFD_RELOC_386_TLS_LE:
13916 case BFD_RELOC_386_TLS_GOTDESC:
13917 case BFD_RELOC_386_TLS_DESC_CALL:
13918 case BFD_RELOC_X86_64_TLSGD:
13919 case BFD_RELOC_X86_64_TLSLD:
13920 case BFD_RELOC_X86_64_DTPOFF32:
13921 case BFD_RELOC_X86_64_DTPOFF64:
13922 case BFD_RELOC_X86_64_GOTTPOFF:
13923 case BFD_RELOC_X86_64_TPOFF32:
13924 case BFD_RELOC_X86_64_TPOFF64:
13925 case BFD_RELOC_X86_64_GOTOFF64:
13926 case BFD_RELOC_X86_64_GOTPC32:
13927 case BFD_RELOC_X86_64_GOT64:
13928 case BFD_RELOC_X86_64_GOTPCREL64:
13929 case BFD_RELOC_X86_64_GOTPC64:
13930 case BFD_RELOC_X86_64_GOTPLT64:
13931 case BFD_RELOC_X86_64_PLTOFF64:
13932 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
13933 case BFD_RELOC_X86_64_TLSDESC_CALL:
13934 case BFD_RELOC_RVA:
13935 case BFD_RELOC_VTABLE_ENTRY:
13936 case BFD_RELOC_VTABLE_INHERIT:
13937 #ifdef TE_PE
13938 case BFD_RELOC_32_SECREL:
13939 #endif
13940 code = fixp->fx_r_type;
13941 break;
13942 case BFD_RELOC_X86_64_32S:
13943 if (!fixp->fx_pcrel)
13944 {
13945 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13946 code = fixp->fx_r_type;
13947 break;
13948 }
13949 /* Fall through. */
13950 default:
13951 if (fixp->fx_pcrel)
13952 {
13953 switch (fixp->fx_size)
13954 {
13955 default:
13956 as_bad_where (fixp->fx_file, fixp->fx_line,
13957 _("can not do %d byte pc-relative relocation"),
13958 fixp->fx_size);
13959 code = BFD_RELOC_32_PCREL;
13960 break;
13961 case 1: code = BFD_RELOC_8_PCREL; break;
13962 case 2: code = BFD_RELOC_16_PCREL; break;
13963 case 4: code = BFD_RELOC_32_PCREL; break;
13964 #ifdef BFD64
13965 case 8: code = BFD_RELOC_64_PCREL; break;
13966 #endif
13967 }
13968 }
13969 else
13970 {
13971 switch (fixp->fx_size)
13972 {
13973 default:
13974 as_bad_where (fixp->fx_file, fixp->fx_line,
13975 _("can not do %d byte relocation"),
13976 fixp->fx_size);
13977 code = BFD_RELOC_32;
13978 break;
13979 case 1: code = BFD_RELOC_8; break;
13980 case 2: code = BFD_RELOC_16; break;
13981 case 4: code = BFD_RELOC_32; break;
13982 #ifdef BFD64
13983 case 8: code = BFD_RELOC_64; break;
13984 #endif
13985 }
13986 }
13987 break;
13988 }
13989
13990 if ((code == BFD_RELOC_32
13991 || code == BFD_RELOC_32_PCREL
13992 || code == BFD_RELOC_X86_64_32S)
13993 && GOT_symbol
13994 && fixp->fx_addsy == GOT_symbol)
13995 {
13996 if (!object_64bit)
13997 code = BFD_RELOC_386_GOTPC;
13998 else
13999 code = BFD_RELOC_X86_64_GOTPC32;
14000 }
14001 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
14002 && GOT_symbol
14003 && fixp->fx_addsy == GOT_symbol)
14004 {
14005 code = BFD_RELOC_X86_64_GOTPC64;
14006 }
14007
14008 rel = XNEW (arelent);
14009 rel->sym_ptr_ptr = XNEW (asymbol *);
14010 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14011
14012 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
14013
14014 if (!use_rela_relocations)
14015 {
14016 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14017 vtable entry to be used in the relocation's section offset. */
14018 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14019 rel->address = fixp->fx_offset;
14020 #if defined (OBJ_COFF) && defined (TE_PE)
14021 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
14022 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
14023 else
14024 #endif
14025 rel->addend = 0;
14026 }
14027 /* Use the rela in 64bit mode. */
14028 else
14029 {
14030 if (disallow_64bit_reloc)
14031 switch (code)
14032 {
14033 case BFD_RELOC_X86_64_DTPOFF64:
14034 case BFD_RELOC_X86_64_TPOFF64:
14035 case BFD_RELOC_64_PCREL:
14036 case BFD_RELOC_X86_64_GOTOFF64:
14037 case BFD_RELOC_X86_64_GOT64:
14038 case BFD_RELOC_X86_64_GOTPCREL64:
14039 case BFD_RELOC_X86_64_GOTPC64:
14040 case BFD_RELOC_X86_64_GOTPLT64:
14041 case BFD_RELOC_X86_64_PLTOFF64:
14042 as_bad_where (fixp->fx_file, fixp->fx_line,
14043 _("cannot represent relocation type %s in x32 mode"),
14044 bfd_get_reloc_code_name (code));
14045 break;
14046 default:
14047 break;
14048 }
14049
14050 if (!fixp->fx_pcrel)
14051 rel->addend = fixp->fx_offset;
14052 else
14053 switch (code)
14054 {
14055 case BFD_RELOC_X86_64_PLT32:
14056 case BFD_RELOC_X86_64_GOT32:
14057 case BFD_RELOC_X86_64_GOTPCREL:
14058 case BFD_RELOC_X86_64_GOTPCRELX:
14059 case BFD_RELOC_X86_64_REX_GOTPCRELX:
14060 case BFD_RELOC_X86_64_TLSGD:
14061 case BFD_RELOC_X86_64_TLSLD:
14062 case BFD_RELOC_X86_64_GOTTPOFF:
14063 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
14064 case BFD_RELOC_X86_64_TLSDESC_CALL:
14065 rel->addend = fixp->fx_offset - fixp->fx_size;
14066 break;
14067 default:
14068 rel->addend = (section->vma
14069 - fixp->fx_size
14070 + fixp->fx_addnumber
14071 + md_pcrel_from (fixp));
14072 break;
14073 }
14074 }
14075
14076 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
14077 if (rel->howto == NULL)
14078 {
14079 as_bad_where (fixp->fx_file, fixp->fx_line,
14080 _("cannot represent relocation type %s"),
14081 bfd_get_reloc_code_name (code));
14082 /* Set howto to a garbage value so that we can keep going. */
14083 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
14084 gas_assert (rel->howto != NULL);
14085 }
14086
14087 return rel;
14088 }
14089
14090 #include "tc-i386-intel.c"
14091
14092 void
14093 tc_x86_parse_to_dw2regnum (expressionS *exp)
14094 {
14095 int saved_naked_reg;
14096 char saved_register_dot;
14097
14098 saved_naked_reg = allow_naked_reg;
14099 allow_naked_reg = 1;
14100 saved_register_dot = register_chars['.'];
14101 register_chars['.'] = '.';
14102 allow_pseudo_reg = 1;
14103 expression_and_evaluate (exp);
14104 allow_pseudo_reg = 0;
14105 register_chars['.'] = saved_register_dot;
14106 allow_naked_reg = saved_naked_reg;
14107
14108 if (exp->X_op == O_register && exp->X_add_number >= 0)
14109 {
14110 if ((addressT) exp->X_add_number < i386_regtab_size)
14111 {
14112 exp->X_op = O_constant;
14113 exp->X_add_number = i386_regtab[exp->X_add_number]
14114 .dw2_regnum[flag_code >> 1];
14115 }
14116 else
14117 exp->X_op = O_illegal;
14118 }
14119 }
14120
14121 void
14122 tc_x86_frame_initial_instructions (void)
14123 {
14124 static unsigned int sp_regno[2];
14125
14126 if (!sp_regno[flag_code >> 1])
14127 {
14128 char *saved_input = input_line_pointer;
14129 char sp[][4] = {"esp", "rsp"};
14130 expressionS exp;
14131
14132 input_line_pointer = sp[flag_code >> 1];
14133 tc_x86_parse_to_dw2regnum (&exp);
14134 gas_assert (exp.X_op == O_constant);
14135 sp_regno[flag_code >> 1] = exp.X_add_number;
14136 input_line_pointer = saved_input;
14137 }
14138
14139 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
14140 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
14141 }
14142
14143 int
14144 x86_dwarf2_addr_size (void)
14145 {
14146 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14147 if (x86_elf_abi == X86_64_X32_ABI)
14148 return 4;
14149 #endif
14150 return bfd_arch_bits_per_address (stdoutput) / 8;
14151 }
14152
14153 int
14154 i386_elf_section_type (const char *str, size_t len)
14155 {
14156 if (flag_code == CODE_64BIT
14157 && len == sizeof ("unwind") - 1
14158 && strncmp (str, "unwind", 6) == 0)
14159 return SHT_X86_64_UNWIND;
14160
14161 return -1;
14162 }
14163
14164 #ifdef TE_SOLARIS
14165 void
14166 i386_solaris_fix_up_eh_frame (segT sec)
14167 {
14168 if (flag_code == CODE_64BIT)
14169 elf_section_type (sec) = SHT_X86_64_UNWIND;
14170 }
14171 #endif
14172
14173 #ifdef TE_PE
14174 void
14175 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
14176 {
14177 expressionS exp;
14178
14179 exp.X_op = O_secrel;
14180 exp.X_add_symbol = symbol;
14181 exp.X_add_number = 0;
14182 emit_expr (&exp, size);
14183 }
14184 #endif
14185
14186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14187 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14188
14189 bfd_vma
14190 x86_64_section_letter (int letter, const char **ptr_msg)
14191 {
14192 if (flag_code == CODE_64BIT)
14193 {
14194 if (letter == 'l')
14195 return SHF_X86_64_LARGE;
14196
14197 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14198 }
14199 else
14200 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
14201 return -1;
14202 }
14203
14204 bfd_vma
14205 x86_64_section_word (char *str, size_t len)
14206 {
14207 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
14208 return SHF_X86_64_LARGE;
14209
14210 return -1;
14211 }
14212
14213 static void
14214 handle_large_common (int small ATTRIBUTE_UNUSED)
14215 {
14216 if (flag_code != CODE_64BIT)
14217 {
14218 s_comm_internal (0, elf_common_parse);
14219 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14220 }
14221 else
14222 {
14223 static segT lbss_section;
14224 asection *saved_com_section_ptr = elf_com_section_ptr;
14225 asection *saved_bss_section = bss_section;
14226
14227 if (lbss_section == NULL)
14228 {
14229 flagword applicable;
14230 segT seg = now_seg;
14231 subsegT subseg = now_subseg;
14232
14233 /* The .lbss section is for local .largecomm symbols. */
14234 lbss_section = subseg_new (".lbss", 0);
14235 applicable = bfd_applicable_section_flags (stdoutput);
14236 bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
14237 seg_info (lbss_section)->bss = 1;
14238
14239 subseg_set (seg, subseg);
14240 }
14241
14242 elf_com_section_ptr = &_bfd_elf_large_com_section;
14243 bss_section = lbss_section;
14244
14245 s_comm_internal (0, elf_common_parse);
14246
14247 elf_com_section_ptr = saved_com_section_ptr;
14248 bss_section = saved_bss_section;
14249 }
14250 }
14251 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */