1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1018 CPU_ZNVER3_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1020 CPU_BTVER1_FLAGS
, 0 },
1021 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1022 CPU_BTVER2_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1024 CPU_8087_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1032 CPU_CMOV_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1034 CPU_FXSR_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE2_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4A_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1046 CPU_SSSE3_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_1_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1052 CPU_SSE4_2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1055 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX2_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512F_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512CD_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512ER_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512PF_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512DQ_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512BW_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1070 CPU_AVX512VL_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1074 CPU_VMFUNC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEOPT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVEC_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1084 CPU_XSAVES_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1090 CPU_PCLMUL_FLAGS
, 1 },
1091 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1092 CPU_FSGSBASE_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1094 CPU_RDRND_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1096 CPU_F16C_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1098 CPU_BMI2_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1102 CPU_FMA4_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1107 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1108 CPU_MOVBE_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1110 CPU_CX16_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_LZCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1116 CPU_POPCNT_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1121 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1122 CPU_INVPCID_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1124 CPU_CLFLUSH_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1127 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1128 CPU_SYSCALL_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1130 CPU_RDTSCP_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOW_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1134 CPU_3DNOWA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1136 CPU_PADLOCK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 1 },
1139 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1140 CPU_SVME_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1142 CPU_SSE4A_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1152 CPU_RDSEED_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1154 CPU_PRFCHW_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1156 CPU_SMAP_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1162 CPU_CLFLUSHOPT_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1164 CPU_PREFETCHWT1_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1167 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1168 CPU_CLWB_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512IFMA_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512VBMI_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VBMI2_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_VNNI_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_BITALG_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1186 CPU_AVX_VNNI_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1188 CPU_CLZERO_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1190 CPU_MWAITX_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1192 CPU_OSPKE_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1194 CPU_RDPID_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1196 CPU_PTWRITE_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1199 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1200 CPU_SHSTK_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1202 CPU_GFNI_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1204 CPU_VAES_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1206 CPU_VPCLMULQDQ_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1208 CPU_WBNOINVD_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1210 CPU_PCONFIG_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1212 CPU_WAITPKG_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1214 CPU_CLDEMOTE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_INT8_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1218 CPU_AMX_BF16_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1220 CPU_AMX_TILE_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1222 CPU_MOVDIRI_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1224 CPU_MOVDIR64B_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1226 CPU_AVX512_BF16_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1228 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1231 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1232 CPU_ENQCMD_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1234 CPU_SERIALIZE_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1236 CPU_RDPRU_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1238 CPU_MCOMMIT_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1240 CPU_SEV_ES_FLAGS
, 0 },
1241 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1242 CPU_TSXLDTRK_FLAGS
, 0 },
1243 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1245 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1246 CPU_WIDEKL_FLAGS
, 0 },
1247 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1248 CPU_UINTR_FLAGS
, 0 },
1249 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1250 CPU_HRESET_FLAGS
, 0 },
1253 static const noarch_entry cpu_noarch
[] =
1255 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1256 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1257 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1258 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1259 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1260 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1261 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1262 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1263 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1264 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1266 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1269 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1288 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1289 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1290 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1291 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1292 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1293 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1294 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1295 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1296 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1297 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1298 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1299 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1300 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1301 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1302 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1303 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1304 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1305 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1309 /* Like s_lcomm_internal in gas/read.c but the alignment string
1310 is allowed to be optional. */
1313 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1320 && *input_line_pointer
== ',')
1322 align
= parse_align (needs_align
- 1);
1324 if (align
== (addressT
) -1)
1339 bss_alloc (symbolP
, size
, align
);
1344 pe_lcomm (int needs_align
)
1346 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1350 const pseudo_typeS md_pseudo_table
[] =
1352 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1353 {"align", s_align_bytes
, 0},
1355 {"align", s_align_ptwo
, 0},
1357 {"arch", set_cpu_arch
, 0},
1361 {"lcomm", pe_lcomm
, 1},
1363 {"ffloat", float_cons
, 'f'},
1364 {"dfloat", float_cons
, 'd'},
1365 {"tfloat", float_cons
, 'x'},
1367 {"slong", signed_cons
, 4},
1368 {"noopt", s_ignore
, 0},
1369 {"optim", s_ignore
, 0},
1370 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1371 {"code16", set_code_flag
, CODE_16BIT
},
1372 {"code32", set_code_flag
, CODE_32BIT
},
1374 {"code64", set_code_flag
, CODE_64BIT
},
1376 {"intel_syntax", set_intel_syntax
, 1},
1377 {"att_syntax", set_intel_syntax
, 0},
1378 {"intel_mnemonic", set_intel_mnemonic
, 1},
1379 {"att_mnemonic", set_intel_mnemonic
, 0},
1380 {"allow_index_reg", set_allow_index_reg
, 1},
1381 {"disallow_index_reg", set_allow_index_reg
, 0},
1382 {"sse_check", set_check
, 0},
1383 {"operand_check", set_check
, 1},
1384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1385 {"largecomm", handle_large_common
, 0},
1387 {"file", dwarf2_directive_file
, 0},
1388 {"loc", dwarf2_directive_loc
, 0},
1389 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1392 {"secrel32", pe_directive_secrel
, 0},
1397 /* For interface with expression (). */
1398 extern char *input_line_pointer
;
1400 /* Hash table for instruction mnemonic lookup. */
1401 static htab_t op_hash
;
1403 /* Hash table for register lookup. */
1404 static htab_t reg_hash
;
1406 /* Various efficient no-op patterns for aligning code labels.
1407 Note: Don't try to assemble the instructions in the comments.
1408 0L and 0w are not legal. */
1409 static const unsigned char f32_1
[] =
1411 static const unsigned char f32_2
[] =
1412 {0x66,0x90}; /* xchg %ax,%ax */
1413 static const unsigned char f32_3
[] =
1414 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1415 static const unsigned char f32_4
[] =
1416 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1417 static const unsigned char f32_6
[] =
1418 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1419 static const unsigned char f32_7
[] =
1420 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1421 static const unsigned char f16_3
[] =
1422 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1423 static const unsigned char f16_4
[] =
1424 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1425 static const unsigned char jump_disp8
[] =
1426 {0xeb}; /* jmp disp8 */
1427 static const unsigned char jump32_disp32
[] =
1428 {0xe9}; /* jmp disp32 */
1429 static const unsigned char jump16_disp32
[] =
1430 {0x66,0xe9}; /* jmp disp32 */
1431 /* 32-bit NOPs patterns. */
1432 static const unsigned char *const f32_patt
[] = {
1433 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1435 /* 16-bit NOPs patterns. */
1436 static const unsigned char *const f16_patt
[] = {
1437 f32_1
, f32_2
, f16_3
, f16_4
1439 /* nopl (%[re]ax) */
1440 static const unsigned char alt_3
[] =
1442 /* nopl 0(%[re]ax) */
1443 static const unsigned char alt_4
[] =
1444 {0x0f,0x1f,0x40,0x00};
1445 /* nopl 0(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_5
[] =
1447 {0x0f,0x1f,0x44,0x00,0x00};
1448 /* nopw 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_6
[] =
1450 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopl 0L(%[re]ax) */
1452 static const unsigned char alt_7
[] =
1453 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1454 /* nopl 0L(%[re]ax,%[re]ax,1) */
1455 static const unsigned char alt_8
[] =
1456 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* nopw 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_9
[] =
1459 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_10
[] =
1462 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* data16 nopw %cs:0L(%eax,%eax,1) */
1464 static const unsigned char alt_11
[] =
1465 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* 32-bit and 64-bit NOPs patterns. */
1467 static const unsigned char *const alt_patt
[] = {
1468 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1469 alt_9
, alt_10
, alt_11
1472 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1473 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1476 i386_output_nops (char *where
, const unsigned char *const *patt
,
1477 int count
, int max_single_nop_size
)
1480 /* Place the longer NOP first. */
1483 const unsigned char *nops
;
1485 if (max_single_nop_size
< 1)
1487 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1488 max_single_nop_size
);
1492 nops
= patt
[max_single_nop_size
- 1];
1494 /* Use the smaller one if the requsted one isn't available. */
1497 max_single_nop_size
--;
1498 nops
= patt
[max_single_nop_size
- 1];
1501 last
= count
% max_single_nop_size
;
1504 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1505 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1509 nops
= patt
[last
- 1];
1512 /* Use the smaller one plus one-byte NOP if the needed one
1515 nops
= patt
[last
- 1];
1516 memcpy (where
+ offset
, nops
, last
);
1517 where
[offset
+ last
] = *patt
[0];
1520 memcpy (where
+ offset
, nops
, last
);
1525 fits_in_imm7 (offsetT num
)
1527 return (num
& 0x7f) == num
;
1531 fits_in_imm31 (offsetT num
)
1533 return (num
& 0x7fffffff) == num
;
1536 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1537 single NOP instruction LIMIT. */
1540 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1542 const unsigned char *const *patt
= NULL
;
1543 int max_single_nop_size
;
1544 /* Maximum number of NOPs before switching to jump over NOPs. */
1545 int max_number_of_nops
;
1547 switch (fragP
->fr_type
)
1552 case rs_machine_dependent
:
1553 /* Allow NOP padding for jumps and calls. */
1554 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1555 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1562 /* We need to decide which NOP sequence to use for 32bit and
1563 64bit. When -mtune= is used:
1565 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1566 PROCESSOR_GENERIC32, f32_patt will be used.
1567 2. For the rest, alt_patt will be used.
1569 When -mtune= isn't used, alt_patt will be used if
1570 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1573 When -march= or .arch is used, we can't use anything beyond
1574 cpu_arch_isa_flags. */
1576 if (flag_code
== CODE_16BIT
)
1579 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1580 /* Limit number of NOPs to 2 in 16-bit mode. */
1581 max_number_of_nops
= 2;
1585 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1587 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1588 switch (cpu_arch_tune
)
1590 case PROCESSOR_UNKNOWN
:
1591 /* We use cpu_arch_isa_flags to check if we SHOULD
1592 optimize with nops. */
1593 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1598 case PROCESSOR_PENTIUM4
:
1599 case PROCESSOR_NOCONA
:
1600 case PROCESSOR_CORE
:
1601 case PROCESSOR_CORE2
:
1602 case PROCESSOR_COREI7
:
1603 case PROCESSOR_L1OM
:
1604 case PROCESSOR_K1OM
:
1605 case PROCESSOR_GENERIC64
:
1607 case PROCESSOR_ATHLON
:
1609 case PROCESSOR_AMDFAM10
:
1611 case PROCESSOR_ZNVER
:
1615 case PROCESSOR_I386
:
1616 case PROCESSOR_I486
:
1617 case PROCESSOR_PENTIUM
:
1618 case PROCESSOR_PENTIUMPRO
:
1619 case PROCESSOR_IAMCU
:
1620 case PROCESSOR_GENERIC32
:
1627 switch (fragP
->tc_frag_data
.tune
)
1629 case PROCESSOR_UNKNOWN
:
1630 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1631 PROCESSOR_UNKNOWN. */
1635 case PROCESSOR_I386
:
1636 case PROCESSOR_I486
:
1637 case PROCESSOR_PENTIUM
:
1638 case PROCESSOR_IAMCU
:
1640 case PROCESSOR_ATHLON
:
1642 case PROCESSOR_AMDFAM10
:
1644 case PROCESSOR_ZNVER
:
1646 case PROCESSOR_GENERIC32
:
1647 /* We use cpu_arch_isa_flags to check if we CAN optimize
1649 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1654 case PROCESSOR_PENTIUMPRO
:
1655 case PROCESSOR_PENTIUM4
:
1656 case PROCESSOR_NOCONA
:
1657 case PROCESSOR_CORE
:
1658 case PROCESSOR_CORE2
:
1659 case PROCESSOR_COREI7
:
1660 case PROCESSOR_L1OM
:
1661 case PROCESSOR_K1OM
:
1662 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1667 case PROCESSOR_GENERIC64
:
1673 if (patt
== f32_patt
)
1675 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1676 /* Limit number of NOPs to 2 for older processors. */
1677 max_number_of_nops
= 2;
1681 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1682 /* Limit number of NOPs to 7 for newer processors. */
1683 max_number_of_nops
= 7;
1688 limit
= max_single_nop_size
;
1690 if (fragP
->fr_type
== rs_fill_nop
)
1692 /* Output NOPs for .nop directive. */
1693 if (limit
> max_single_nop_size
)
1695 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1696 _("invalid single nop size: %d "
1697 "(expect within [0, %d])"),
1698 limit
, max_single_nop_size
);
1702 else if (fragP
->fr_type
!= rs_machine_dependent
)
1703 fragP
->fr_var
= count
;
1705 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1707 /* Generate jump over NOPs. */
1708 offsetT disp
= count
- 2;
1709 if (fits_in_imm7 (disp
))
1711 /* Use "jmp disp8" if possible. */
1713 where
[0] = jump_disp8
[0];
1719 unsigned int size_of_jump
;
1721 if (flag_code
== CODE_16BIT
)
1723 where
[0] = jump16_disp32
[0];
1724 where
[1] = jump16_disp32
[1];
1729 where
[0] = jump32_disp32
[0];
1733 count
-= size_of_jump
+ 4;
1734 if (!fits_in_imm31 (count
))
1736 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1737 _("jump over nop padding out of range"));
1741 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1742 where
+= size_of_jump
+ 4;
1746 /* Generate multiple NOPs. */
1747 i386_output_nops (where
, patt
, count
, limit
);
1751 operand_type_all_zero (const union i386_operand_type
*x
)
1753 switch (ARRAY_SIZE(x
->array
))
1764 return !x
->array
[0];
1771 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1773 switch (ARRAY_SIZE(x
->array
))
1789 x
->bitfield
.class = ClassNone
;
1790 x
->bitfield
.instance
= InstanceNone
;
1794 operand_type_equal (const union i386_operand_type
*x
,
1795 const union i386_operand_type
*y
)
1797 switch (ARRAY_SIZE(x
->array
))
1800 if (x
->array
[2] != y
->array
[2])
1804 if (x
->array
[1] != y
->array
[1])
1808 return x
->array
[0] == y
->array
[0];
1816 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1818 switch (ARRAY_SIZE(x
->array
))
1833 return !x
->array
[0];
1840 cpu_flags_equal (const union i386_cpu_flags
*x
,
1841 const union i386_cpu_flags
*y
)
1843 switch (ARRAY_SIZE(x
->array
))
1846 if (x
->array
[3] != y
->array
[3])
1850 if (x
->array
[2] != y
->array
[2])
1854 if (x
->array
[1] != y
->array
[1])
1858 return x
->array
[0] == y
->array
[0];
1866 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1868 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1869 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1872 static INLINE i386_cpu_flags
1873 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1875 switch (ARRAY_SIZE (x
.array
))
1878 x
.array
[3] &= y
.array
[3];
1881 x
.array
[2] &= y
.array
[2];
1884 x
.array
[1] &= y
.array
[1];
1887 x
.array
[0] &= y
.array
[0];
1895 static INLINE i386_cpu_flags
1896 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1898 switch (ARRAY_SIZE (x
.array
))
1901 x
.array
[3] |= y
.array
[3];
1904 x
.array
[2] |= y
.array
[2];
1907 x
.array
[1] |= y
.array
[1];
1910 x
.array
[0] |= y
.array
[0];
1918 static INLINE i386_cpu_flags
1919 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1921 switch (ARRAY_SIZE (x
.array
))
1924 x
.array
[3] &= ~y
.array
[3];
1927 x
.array
[2] &= ~y
.array
[2];
1930 x
.array
[1] &= ~y
.array
[1];
1933 x
.array
[0] &= ~y
.array
[0];
1941 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1943 #define CPU_FLAGS_ARCH_MATCH 0x1
1944 #define CPU_FLAGS_64BIT_MATCH 0x2
1946 #define CPU_FLAGS_PERFECT_MATCH \
1947 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1949 /* Return CPU flags match bits. */
1952 cpu_flags_match (const insn_template
*t
)
1954 i386_cpu_flags x
= t
->cpu_flags
;
1955 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1957 x
.bitfield
.cpu64
= 0;
1958 x
.bitfield
.cpuno64
= 0;
1960 if (cpu_flags_all_zero (&x
))
1962 /* This instruction is available on all archs. */
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 /* This instruction is available only on some archs. */
1968 i386_cpu_flags cpu
= cpu_arch_flags
;
1970 /* AVX512VL is no standalone feature - match it and then strip it. */
1971 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1973 x
.bitfield
.cpuavx512vl
= 0;
1975 cpu
= cpu_flags_and (x
, cpu
);
1976 if (!cpu_flags_all_zero (&cpu
))
1978 if (x
.bitfield
.cpuavx
)
1980 /* We need to check a few extra flags with AVX. */
1981 if (cpu
.bitfield
.cpuavx
1982 && (!t
->opcode_modifier
.sse2avx
1983 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1984 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1985 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1986 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1989 else if (x
.bitfield
.cpuavx512f
)
1991 /* We need to check a few extra flags with AVX512F. */
1992 if (cpu
.bitfield
.cpuavx512f
1993 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1994 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1995 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1996 match
|= CPU_FLAGS_ARCH_MATCH
;
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2005 static INLINE i386_operand_type
2006 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2008 if (x
.bitfield
.class != y
.bitfield
.class)
2009 x
.bitfield
.class = ClassNone
;
2010 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2011 x
.bitfield
.instance
= InstanceNone
;
2013 switch (ARRAY_SIZE (x
.array
))
2016 x
.array
[2] &= y
.array
[2];
2019 x
.array
[1] &= y
.array
[1];
2022 x
.array
[0] &= y
.array
[0];
2030 static INLINE i386_operand_type
2031 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2033 gas_assert (y
.bitfield
.class == ClassNone
);
2034 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2036 switch (ARRAY_SIZE (x
.array
))
2039 x
.array
[2] &= ~y
.array
[2];
2042 x
.array
[1] &= ~y
.array
[1];
2045 x
.array
[0] &= ~y
.array
[0];
2053 static INLINE i386_operand_type
2054 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2056 gas_assert (x
.bitfield
.class == ClassNone
||
2057 y
.bitfield
.class == ClassNone
||
2058 x
.bitfield
.class == y
.bitfield
.class);
2059 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2060 y
.bitfield
.instance
== InstanceNone
||
2061 x
.bitfield
.instance
== y
.bitfield
.instance
);
2063 switch (ARRAY_SIZE (x
.array
))
2066 x
.array
[2] |= y
.array
[2];
2069 x
.array
[1] |= y
.array
[1];
2072 x
.array
[0] |= y
.array
[0];
2080 static INLINE i386_operand_type
2081 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2083 gas_assert (y
.bitfield
.class == ClassNone
);
2084 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2086 switch (ARRAY_SIZE (x
.array
))
2089 x
.array
[2] ^= y
.array
[2];
2092 x
.array
[1] ^= y
.array
[1];
2095 x
.array
[0] ^= y
.array
[0];
2103 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2104 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2105 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2106 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2107 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2108 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2109 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2110 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2111 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2112 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2113 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2114 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2115 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2116 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2117 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2118 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2119 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2130 operand_type_check (i386_operand_type t
, enum operand_type c
)
2135 return t
.bitfield
.class == Reg
;
2138 return (t
.bitfield
.imm8
2142 || t
.bitfield
.imm32s
2143 || t
.bitfield
.imm64
);
2146 return (t
.bitfield
.disp8
2147 || t
.bitfield
.disp16
2148 || t
.bitfield
.disp32
2149 || t
.bitfield
.disp32s
2150 || t
.bitfield
.disp64
);
2153 return (t
.bitfield
.disp8
2154 || t
.bitfield
.disp16
2155 || t
.bitfield
.disp32
2156 || t
.bitfield
.disp32s
2157 || t
.bitfield
.disp64
2158 || t
.bitfield
.baseindex
);
2167 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2168 between operand GIVEN and opeand WANTED for instruction template T. */
2171 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2174 return !((i
.types
[given
].bitfield
.byte
2175 && !t
->operand_types
[wanted
].bitfield
.byte
)
2176 || (i
.types
[given
].bitfield
.word
2177 && !t
->operand_types
[wanted
].bitfield
.word
)
2178 || (i
.types
[given
].bitfield
.dword
2179 && !t
->operand_types
[wanted
].bitfield
.dword
)
2180 || (i
.types
[given
].bitfield
.qword
2181 && !t
->operand_types
[wanted
].bitfield
.qword
)
2182 || (i
.types
[given
].bitfield
.tbyte
2183 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2186 /* Return 1 if there is no conflict in SIMD register between operand
2187 GIVEN and opeand WANTED for instruction template T. */
2190 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2193 return !((i
.types
[given
].bitfield
.xmmword
2194 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2195 || (i
.types
[given
].bitfield
.ymmword
2196 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2197 || (i
.types
[given
].bitfield
.zmmword
2198 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2199 || (i
.types
[given
].bitfield
.tmmword
2200 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2203 /* Return 1 if there is no conflict in any size between operand GIVEN
2204 and opeand WANTED for instruction template T. */
2207 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2210 return (match_operand_size (t
, wanted
, given
)
2211 && !((i
.types
[given
].bitfield
.unspecified
2213 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2214 || (i
.types
[given
].bitfield
.fword
2215 && !t
->operand_types
[wanted
].bitfield
.fword
)
2216 /* For scalar opcode templates to allow register and memory
2217 operands at the same time, some special casing is needed
2218 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2219 down-conversion vpmov*. */
2220 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2221 && t
->operand_types
[wanted
].bitfield
.byte
2222 + t
->operand_types
[wanted
].bitfield
.word
2223 + t
->operand_types
[wanted
].bitfield
.dword
2224 + t
->operand_types
[wanted
].bitfield
.qword
2225 > !!t
->opcode_modifier
.broadcast
)
2226 ? (i
.types
[given
].bitfield
.xmmword
2227 || i
.types
[given
].bitfield
.ymmword
2228 || i
.types
[given
].bitfield
.zmmword
)
2229 : !match_simd_size(t
, wanted
, given
))));
2232 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2233 operands for instruction template T, and it has MATCH_REVERSE set if there
2234 is no size conflict on any operands for the template with operands reversed
2235 (and the template allows for reversing in the first place). */
2237 #define MATCH_STRAIGHT 1
2238 #define MATCH_REVERSE 2
2240 static INLINE
unsigned int
2241 operand_size_match (const insn_template
*t
)
2243 unsigned int j
, match
= MATCH_STRAIGHT
;
2245 /* Don't check non-absolute jump instructions. */
2246 if (t
->opcode_modifier
.jump
2247 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2250 /* Check memory and accumulator operand size. */
2251 for (j
= 0; j
< i
.operands
; j
++)
2253 if (i
.types
[j
].bitfield
.class != Reg
2254 && i
.types
[j
].bitfield
.class != RegSIMD
2255 && t
->opcode_modifier
.anysize
)
2258 if (t
->operand_types
[j
].bitfield
.class == Reg
2259 && !match_operand_size (t
, j
, j
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, j
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2279 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2286 if (!t
->opcode_modifier
.d
)
2290 i
.error
= operand_size_mismatch
;
2294 /* Check reverse. */
2295 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2297 for (j
= 0; j
< i
.operands
; j
++)
2299 unsigned int given
= i
.operands
- j
- 1;
2301 if (t
->operand_types
[j
].bitfield
.class == Reg
2302 && !match_operand_size (t
, j
, given
))
2305 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2306 && !match_simd_size (t
, j
, given
))
2309 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2310 && (!match_operand_size (t
, j
, given
)
2311 || !match_simd_size (t
, j
, given
)))
2314 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2318 return match
| MATCH_REVERSE
;
2322 operand_type_match (i386_operand_type overlap
,
2323 i386_operand_type given
)
2325 i386_operand_type temp
= overlap
;
2327 temp
.bitfield
.unspecified
= 0;
2328 temp
.bitfield
.byte
= 0;
2329 temp
.bitfield
.word
= 0;
2330 temp
.bitfield
.dword
= 0;
2331 temp
.bitfield
.fword
= 0;
2332 temp
.bitfield
.qword
= 0;
2333 temp
.bitfield
.tbyte
= 0;
2334 temp
.bitfield
.xmmword
= 0;
2335 temp
.bitfield
.ymmword
= 0;
2336 temp
.bitfield
.zmmword
= 0;
2337 temp
.bitfield
.tmmword
= 0;
2338 if (operand_type_all_zero (&temp
))
2341 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2345 i
.error
= operand_type_mismatch
;
2349 /* If given types g0 and g1 are registers they must be of the same type
2350 unless the expected operand type register overlap is null.
2351 Some Intel syntax memory operand size checking also happens here. */
2354 operand_type_register_match (i386_operand_type g0
,
2355 i386_operand_type t0
,
2356 i386_operand_type g1
,
2357 i386_operand_type t1
)
2359 if (g0
.bitfield
.class != Reg
2360 && g0
.bitfield
.class != RegSIMD
2361 && (!operand_type_check (g0
, anymem
)
2362 || g0
.bitfield
.unspecified
2363 || (t0
.bitfield
.class != Reg
2364 && t0
.bitfield
.class != RegSIMD
)))
2367 if (g1
.bitfield
.class != Reg
2368 && g1
.bitfield
.class != RegSIMD
2369 && (!operand_type_check (g1
, anymem
)
2370 || g1
.bitfield
.unspecified
2371 || (t1
.bitfield
.class != Reg
2372 && t1
.bitfield
.class != RegSIMD
)))
2375 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2376 && g0
.bitfield
.word
== g1
.bitfield
.word
2377 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2378 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2379 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2380 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2381 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2384 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2385 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2386 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2387 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2388 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2389 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2390 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2393 i
.error
= register_type_mismatch
;
2398 static INLINE
unsigned int
2399 register_number (const reg_entry
*r
)
2401 unsigned int nr
= r
->reg_num
;
2403 if (r
->reg_flags
& RegRex
)
2406 if (r
->reg_flags
& RegVRex
)
2412 static INLINE
unsigned int
2413 mode_from_disp_size (i386_operand_type t
)
2415 if (t
.bitfield
.disp8
)
2417 else if (t
.bitfield
.disp16
2418 || t
.bitfield
.disp32
2419 || t
.bitfield
.disp32s
)
2426 fits_in_signed_byte (addressT num
)
2428 return num
+ 0x80 <= 0xff;
2432 fits_in_unsigned_byte (addressT num
)
2438 fits_in_unsigned_word (addressT num
)
2440 return num
<= 0xffff;
2444 fits_in_signed_word (addressT num
)
2446 return num
+ 0x8000 <= 0xffff;
2450 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2455 return num
+ 0x80000000 <= 0xffffffff;
2457 } /* fits_in_signed_long() */
2460 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2465 return num
<= 0xffffffff;
2467 } /* fits_in_unsigned_long() */
2470 fits_in_disp8 (offsetT num
)
2472 int shift
= i
.memshift
;
2478 mask
= (1 << shift
) - 1;
2480 /* Return 0 if NUM isn't properly aligned. */
2484 /* Check if NUM will fit in 8bit after shift. */
2485 return fits_in_signed_byte (num
>> shift
);
2489 fits_in_imm4 (offsetT num
)
2491 return (num
& 0xf) == num
;
2494 static i386_operand_type
2495 smallest_imm_type (offsetT num
)
2497 i386_operand_type t
;
2499 operand_type_set (&t
, 0);
2500 t
.bitfield
.imm64
= 1;
2502 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2504 /* This code is disabled on the 486 because all the Imm1 forms
2505 in the opcode table are slower on the i486. They're the
2506 versions with the implicitly specified single-position
2507 displacement, which has another syntax if you really want to
2509 t
.bitfield
.imm1
= 1;
2510 t
.bitfield
.imm8
= 1;
2511 t
.bitfield
.imm8s
= 1;
2512 t
.bitfield
.imm16
= 1;
2513 t
.bitfield
.imm32
= 1;
2514 t
.bitfield
.imm32s
= 1;
2516 else if (fits_in_signed_byte (num
))
2518 t
.bitfield
.imm8
= 1;
2519 t
.bitfield
.imm8s
= 1;
2520 t
.bitfield
.imm16
= 1;
2521 t
.bitfield
.imm32
= 1;
2522 t
.bitfield
.imm32s
= 1;
2524 else if (fits_in_unsigned_byte (num
))
2526 t
.bitfield
.imm8
= 1;
2527 t
.bitfield
.imm16
= 1;
2528 t
.bitfield
.imm32
= 1;
2529 t
.bitfield
.imm32s
= 1;
2531 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2533 t
.bitfield
.imm16
= 1;
2534 t
.bitfield
.imm32
= 1;
2535 t
.bitfield
.imm32s
= 1;
2537 else if (fits_in_signed_long (num
))
2539 t
.bitfield
.imm32
= 1;
2540 t
.bitfield
.imm32s
= 1;
2542 else if (fits_in_unsigned_long (num
))
2543 t
.bitfield
.imm32
= 1;
2549 offset_in_range (offsetT val
, int size
)
2555 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2556 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2557 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2559 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2564 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2566 char buf1
[40], buf2
[40];
2568 sprint_value (buf1
, val
);
2569 sprint_value (buf2
, val
& mask
);
2570 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2585 a. PREFIX_EXIST if attempting to add a prefix where one from the
2586 same class already exists.
2587 b. PREFIX_LOCK if lock prefix is added.
2588 c. PREFIX_REP if rep/repne prefix is added.
2589 d. PREFIX_DS if ds prefix is added.
2590 e. PREFIX_OTHER if other prefix is added.
2593 static enum PREFIX_GROUP
2594 add_prefix (unsigned int prefix
)
2596 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2599 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2600 && flag_code
== CODE_64BIT
)
2602 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2603 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2604 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2605 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2616 case DS_PREFIX_OPCODE
:
2619 case CS_PREFIX_OPCODE
:
2620 case ES_PREFIX_OPCODE
:
2621 case FS_PREFIX_OPCODE
:
2622 case GS_PREFIX_OPCODE
:
2623 case SS_PREFIX_OPCODE
:
2627 case REPNE_PREFIX_OPCODE
:
2628 case REPE_PREFIX_OPCODE
:
2633 case LOCK_PREFIX_OPCODE
:
2642 case ADDR_PREFIX_OPCODE
:
2646 case DATA_PREFIX_OPCODE
:
2650 if (i
.prefix
[q
] != 0)
2658 i
.prefix
[q
] |= prefix
;
2661 as_bad (_("same type of prefix used twice"));
2667 update_code_flag (int value
, int check
)
2669 PRINTF_LIKE ((*as_error
));
2671 flag_code
= (enum flag_code
) value
;
2672 if (flag_code
== CODE_64BIT
)
2674 cpu_arch_flags
.bitfield
.cpu64
= 1;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2679 cpu_arch_flags
.bitfield
.cpu64
= 0;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2682 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2685 as_error
= as_fatal
;
2688 (*as_error
) (_("64bit mode not supported on `%s'."),
2689 cpu_arch_name
? cpu_arch_name
: default_arch
);
2691 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2694 as_error
= as_fatal
;
2697 (*as_error
) (_("32bit mode not supported on `%s'."),
2698 cpu_arch_name
? cpu_arch_name
: default_arch
);
2700 stackop_size
= '\0';
2704 set_code_flag (int value
)
2706 update_code_flag (value
, 0);
2710 set_16bit_gcc_code_flag (int new_code_flag
)
2712 flag_code
= (enum flag_code
) new_code_flag
;
2713 if (flag_code
!= CODE_16BIT
)
2715 cpu_arch_flags
.bitfield
.cpu64
= 0;
2716 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2717 stackop_size
= LONG_MNEM_SUFFIX
;
2721 set_intel_syntax (int syntax_flag
)
2723 /* Find out if register prefixing is specified. */
2724 int ask_naked_reg
= 0;
2727 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2730 int e
= get_symbol_name (&string
);
2732 if (strcmp (string
, "prefix") == 0)
2734 else if (strcmp (string
, "noprefix") == 0)
2737 as_bad (_("bad argument to syntax directive."));
2738 (void) restore_line_pointer (e
);
2740 demand_empty_rest_of_line ();
2742 intel_syntax
= syntax_flag
;
2744 if (ask_naked_reg
== 0)
2745 allow_naked_reg
= (intel_syntax
2746 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2748 allow_naked_reg
= (ask_naked_reg
< 0);
2750 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2752 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2753 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2754 register_prefix
= allow_naked_reg
? "" : "%";
2758 set_intel_mnemonic (int mnemonic_flag
)
2760 intel_mnemonic
= mnemonic_flag
;
2764 set_allow_index_reg (int flag
)
2766 allow_index_reg
= flag
;
2770 set_check (int what
)
2772 enum check_kind
*kind
;
2777 kind
= &operand_check
;
2788 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2791 int e
= get_symbol_name (&string
);
2793 if (strcmp (string
, "none") == 0)
2795 else if (strcmp (string
, "warning") == 0)
2796 *kind
= check_warning
;
2797 else if (strcmp (string
, "error") == 0)
2798 *kind
= check_error
;
2800 as_bad (_("bad argument to %s_check directive."), str
);
2801 (void) restore_line_pointer (e
);
2804 as_bad (_("missing argument for %s_check directive"), str
);
2806 demand_empty_rest_of_line ();
2810 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2811 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2814 static const char *arch
;
2816 /* Intel LIOM is only supported on ELF. */
2822 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2823 use default_arch. */
2824 arch
= cpu_arch_name
;
2826 arch
= default_arch
;
2829 /* If we are targeting Intel MCU, we must enable it. */
2830 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2831 || new_flag
.bitfield
.cpuiamcu
)
2834 /* If we are targeting Intel L1OM, we must enable it. */
2835 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2836 || new_flag
.bitfield
.cpul1om
)
2839 /* If we are targeting Intel K1OM, we must enable it. */
2840 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2841 || new_flag
.bitfield
.cpuk1om
)
2844 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2849 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2853 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2856 int e
= get_symbol_name (&string
);
2858 i386_cpu_flags flags
;
2860 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2862 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2864 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2868 cpu_arch_name
= cpu_arch
[j
].name
;
2869 cpu_sub_arch_name
= NULL
;
2870 cpu_arch_flags
= cpu_arch
[j
].flags
;
2871 if (flag_code
== CODE_64BIT
)
2873 cpu_arch_flags
.bitfield
.cpu64
= 1;
2874 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2878 cpu_arch_flags
.bitfield
.cpu64
= 0;
2879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2881 cpu_arch_isa
= cpu_arch
[j
].type
;
2882 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2883 if (!cpu_arch_tune_set
)
2885 cpu_arch_tune
= cpu_arch_isa
;
2886 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2891 flags
= cpu_flags_or (cpu_arch_flags
,
2894 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2896 if (cpu_sub_arch_name
)
2898 char *name
= cpu_sub_arch_name
;
2899 cpu_sub_arch_name
= concat (name
,
2901 (const char *) NULL
);
2905 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2906 cpu_arch_flags
= flags
;
2907 cpu_arch_isa_flags
= flags
;
2911 = cpu_flags_or (cpu_arch_isa_flags
,
2913 (void) restore_line_pointer (e
);
2914 demand_empty_rest_of_line ();
2919 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2921 /* Disable an ISA extension. */
2922 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2923 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2925 flags
= cpu_flags_and_not (cpu_arch_flags
,
2926 cpu_noarch
[j
].flags
);
2927 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2929 if (cpu_sub_arch_name
)
2931 char *name
= cpu_sub_arch_name
;
2932 cpu_sub_arch_name
= concat (name
, string
,
2933 (const char *) NULL
);
2937 cpu_sub_arch_name
= xstrdup (string
);
2938 cpu_arch_flags
= flags
;
2939 cpu_arch_isa_flags
= flags
;
2941 (void) restore_line_pointer (e
);
2942 demand_empty_rest_of_line ();
2946 j
= ARRAY_SIZE (cpu_arch
);
2949 if (j
>= ARRAY_SIZE (cpu_arch
))
2950 as_bad (_("no such architecture: `%s'"), string
);
2952 *input_line_pointer
= e
;
2955 as_bad (_("missing cpu architecture"));
2957 no_cond_jump_promotion
= 0;
2958 if (*input_line_pointer
== ','
2959 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2964 ++input_line_pointer
;
2965 e
= get_symbol_name (&string
);
2967 if (strcmp (string
, "nojumps") == 0)
2968 no_cond_jump_promotion
= 1;
2969 else if (strcmp (string
, "jumps") == 0)
2972 as_bad (_("no such architecture modifier: `%s'"), string
);
2974 (void) restore_line_pointer (e
);
2977 demand_empty_rest_of_line ();
2980 enum bfd_architecture
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || flag_code
!= CODE_64BIT
)
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_arch_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || flag_code
!= CODE_64BIT
)
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_arch_k1om
;
2997 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2999 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3000 || flag_code
== CODE_64BIT
)
3001 as_fatal (_("Intel MCU is 32bit ELF only"));
3002 return bfd_arch_iamcu
;
3005 return bfd_arch_i386
;
3011 if (!strncmp (default_arch
, "x86_64", 6))
3013 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3016 || default_arch
[6] != '\0')
3017 as_fatal (_("Intel L1OM is 64bit ELF only"));
3018 return bfd_mach_l1om
;
3020 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3022 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3023 || default_arch
[6] != '\0')
3024 as_fatal (_("Intel K1OM is 64bit ELF only"));
3025 return bfd_mach_k1om
;
3027 else if (default_arch
[6] == '\0')
3028 return bfd_mach_x86_64
;
3030 return bfd_mach_x64_32
;
3032 else if (!strcmp (default_arch
, "i386")
3033 || !strcmp (default_arch
, "iamcu"))
3035 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3037 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3038 as_fatal (_("Intel MCU is 32bit ELF only"));
3039 return bfd_mach_i386_iamcu
;
3042 return bfd_mach_i386_i386
;
3045 as_fatal (_("unknown architecture"));
3051 /* Support pseudo prefixes like {disp32}. */
3052 lex_type
['{'] = LEX_BEGIN_NAME
;
3054 /* Initialize op_hash hash table. */
3055 op_hash
= str_htab_create ();
3058 const insn_template
*optab
;
3059 templates
*core_optab
;
3061 /* Setup for loop. */
3063 core_optab
= XNEW (templates
);
3064 core_optab
->start
= optab
;
3069 if (optab
->name
== NULL
3070 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3072 /* different name --> ship out current template list;
3073 add to hash table; & begin anew. */
3074 core_optab
->end
= optab
;
3075 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3076 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3078 if (optab
->name
== NULL
)
3080 core_optab
= XNEW (templates
);
3081 core_optab
->start
= optab
;
3086 /* Initialize reg_hash hash table. */
3087 reg_hash
= str_htab_create ();
3089 const reg_entry
*regtab
;
3090 unsigned int regtab_size
= i386_regtab_size
;
3092 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3093 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3094 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3097 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3102 for (c
= 0; c
< 256; c
++)
3107 mnemonic_chars
[c
] = c
;
3108 register_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3111 else if (ISLOWER (c
))
3113 mnemonic_chars
[c
] = c
;
3114 register_chars
[c
] = c
;
3115 operand_chars
[c
] = c
;
3117 else if (ISUPPER (c
))
3119 mnemonic_chars
[c
] = TOLOWER (c
);
3120 register_chars
[c
] = mnemonic_chars
[c
];
3121 operand_chars
[c
] = c
;
3123 else if (c
== '{' || c
== '}')
3125 mnemonic_chars
[c
] = c
;
3126 operand_chars
[c
] = c
;
3128 #ifdef SVR4_COMMENT_CHARS
3129 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3130 operand_chars
[c
] = c
;
3133 if (ISALPHA (c
) || ISDIGIT (c
))
3134 identifier_chars
[c
] = c
;
3137 identifier_chars
[c
] = c
;
3138 operand_chars
[c
] = c
;
3143 identifier_chars
['@'] = '@';
3146 identifier_chars
['?'] = '?';
3147 operand_chars
['?'] = '?';
3149 digit_chars
['-'] = '-';
3150 mnemonic_chars
['_'] = '_';
3151 mnemonic_chars
['-'] = '-';
3152 mnemonic_chars
['.'] = '.';
3153 identifier_chars
['_'] = '_';
3154 identifier_chars
['.'] = '.';
3156 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3157 operand_chars
[(unsigned char) *p
] = *p
;
3160 if (flag_code
== CODE_64BIT
)
3162 #if defined (OBJ_COFF) && defined (TE_PE)
3163 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3166 x86_dwarf2_return_column
= 16;
3168 x86_cie_data_alignment
= -8;
3172 x86_dwarf2_return_column
= 8;
3173 x86_cie_data_alignment
= -4;
3176 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3177 can be turned into BRANCH_PREFIX frag. */
3178 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3183 i386_print_statistics (FILE *file
)
3185 htab_print_statistics (file
, "i386 opcode", op_hash
);
3186 htab_print_statistics (file
, "i386 register", reg_hash
);
3191 /* Debugging routines for md_assemble. */
3192 static void pte (insn_template
*);
3193 static void pt (i386_operand_type
);
3194 static void pe (expressionS
*);
3195 static void ps (symbolS
*);
3198 pi (const char *line
, i386_insn
*x
)
3202 fprintf (stdout
, "%s: template ", line
);
3204 fprintf (stdout
, " address: base %s index %s scale %x\n",
3205 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3206 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3207 x
->log2_scale_factor
);
3208 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3209 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3210 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3211 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3212 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3213 (x
->rex
& REX_W
) != 0,
3214 (x
->rex
& REX_R
) != 0,
3215 (x
->rex
& REX_X
) != 0,
3216 (x
->rex
& REX_B
) != 0);
3217 for (j
= 0; j
< x
->operands
; j
++)
3219 fprintf (stdout
, " #%d: ", j
+ 1);
3221 fprintf (stdout
, "\n");
3222 if (x
->types
[j
].bitfield
.class == Reg
3223 || x
->types
[j
].bitfield
.class == RegMMX
3224 || x
->types
[j
].bitfield
.class == RegSIMD
3225 || x
->types
[j
].bitfield
.class == RegMask
3226 || x
->types
[j
].bitfield
.class == SReg
3227 || x
->types
[j
].bitfield
.class == RegCR
3228 || x
->types
[j
].bitfield
.class == RegDR
3229 || x
->types
[j
].bitfield
.class == RegTR
3230 || x
->types
[j
].bitfield
.class == RegBND
)
3231 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3232 if (operand_type_check (x
->types
[j
], imm
))
3234 if (operand_type_check (x
->types
[j
], disp
))
3235 pe (x
->op
[j
].disps
);
3240 pte (insn_template
*t
)
3242 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3243 static const char *const opc_spc
[] = {
3244 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3245 "XOP08", "XOP09", "XOP0A",
3249 fprintf (stdout
, " %d operands ", t
->operands
);
3250 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3251 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3252 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3253 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3254 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3255 if (t
->extension_opcode
!= None
)
3256 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3257 if (t
->opcode_modifier
.d
)
3258 fprintf (stdout
, "D");
3259 if (t
->opcode_modifier
.w
)
3260 fprintf (stdout
, "W");
3261 fprintf (stdout
, "\n");
3262 for (j
= 0; j
< t
->operands
; j
++)
3264 fprintf (stdout
, " #%d type ", j
+ 1);
3265 pt (t
->operand_types
[j
]);
3266 fprintf (stdout
, "\n");
3273 fprintf (stdout
, " operation %d\n", e
->X_op
);
3274 fprintf (stdout
, " add_number %ld (%lx)\n",
3275 (long) e
->X_add_number
, (long) e
->X_add_number
);
3276 if (e
->X_add_symbol
)
3278 fprintf (stdout
, " add_symbol ");
3279 ps (e
->X_add_symbol
);
3280 fprintf (stdout
, "\n");
3284 fprintf (stdout
, " op_symbol ");
3285 ps (e
->X_op_symbol
);
3286 fprintf (stdout
, "\n");
3293 fprintf (stdout
, "%s type %s%s",
3295 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3296 segment_name (S_GET_SEGMENT (s
)));
3299 static struct type_name
3301 i386_operand_type mask
;
3304 const type_names
[] =
3306 { OPERAND_TYPE_REG8
, "r8" },
3307 { OPERAND_TYPE_REG16
, "r16" },
3308 { OPERAND_TYPE_REG32
, "r32" },
3309 { OPERAND_TYPE_REG64
, "r64" },
3310 { OPERAND_TYPE_ACC8
, "acc8" },
3311 { OPERAND_TYPE_ACC16
, "acc16" },
3312 { OPERAND_TYPE_ACC32
, "acc32" },
3313 { OPERAND_TYPE_ACC64
, "acc64" },
3314 { OPERAND_TYPE_IMM8
, "i8" },
3315 { OPERAND_TYPE_IMM8
, "i8s" },
3316 { OPERAND_TYPE_IMM16
, "i16" },
3317 { OPERAND_TYPE_IMM32
, "i32" },
3318 { OPERAND_TYPE_IMM32S
, "i32s" },
3319 { OPERAND_TYPE_IMM64
, "i64" },
3320 { OPERAND_TYPE_IMM1
, "i1" },
3321 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3322 { OPERAND_TYPE_DISP8
, "d8" },
3323 { OPERAND_TYPE_DISP16
, "d16" },
3324 { OPERAND_TYPE_DISP32
, "d32" },
3325 { OPERAND_TYPE_DISP32S
, "d32s" },
3326 { OPERAND_TYPE_DISP64
, "d64" },
3327 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3328 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3329 { OPERAND_TYPE_CONTROL
, "control reg" },
3330 { OPERAND_TYPE_TEST
, "test reg" },
3331 { OPERAND_TYPE_DEBUG
, "debug reg" },
3332 { OPERAND_TYPE_FLOATREG
, "FReg" },
3333 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3334 { OPERAND_TYPE_SREG
, "SReg" },
3335 { OPERAND_TYPE_REGMMX
, "rMMX" },
3336 { OPERAND_TYPE_REGXMM
, "rXMM" },
3337 { OPERAND_TYPE_REGYMM
, "rYMM" },
3338 { OPERAND_TYPE_REGZMM
, "rZMM" },
3339 { OPERAND_TYPE_REGTMM
, "rTMM" },
3340 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3344 pt (i386_operand_type t
)
3347 i386_operand_type a
;
3349 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3351 a
= operand_type_and (t
, type_names
[j
].mask
);
3352 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3353 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3358 #endif /* DEBUG386 */
3360 static bfd_reloc_code_real_type
3361 reloc (unsigned int size
,
3364 bfd_reloc_code_real_type other
)
3366 if (other
!= NO_RELOC
)
3368 reloc_howto_type
*rel
;
3373 case BFD_RELOC_X86_64_GOT32
:
3374 return BFD_RELOC_X86_64_GOT64
;
3376 case BFD_RELOC_X86_64_GOTPLT64
:
3377 return BFD_RELOC_X86_64_GOTPLT64
;
3379 case BFD_RELOC_X86_64_PLTOFF64
:
3380 return BFD_RELOC_X86_64_PLTOFF64
;
3382 case BFD_RELOC_X86_64_GOTPC32
:
3383 other
= BFD_RELOC_X86_64_GOTPC64
;
3385 case BFD_RELOC_X86_64_GOTPCREL
:
3386 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3388 case BFD_RELOC_X86_64_TPOFF32
:
3389 other
= BFD_RELOC_X86_64_TPOFF64
;
3391 case BFD_RELOC_X86_64_DTPOFF32
:
3392 other
= BFD_RELOC_X86_64_DTPOFF64
;
3398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3399 if (other
== BFD_RELOC_SIZE32
)
3402 other
= BFD_RELOC_SIZE64
;
3405 as_bad (_("there are no pc-relative size relocations"));
3411 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3412 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3415 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3417 as_bad (_("unknown relocation (%u)"), other
);
3418 else if (size
!= bfd_get_reloc_size (rel
))
3419 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3420 bfd_get_reloc_size (rel
),
3422 else if (pcrel
&& !rel
->pc_relative
)
3423 as_bad (_("non-pc-relative relocation for pc-relative field"));
3424 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3426 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3428 as_bad (_("relocated field and relocation type differ in signedness"));
3437 as_bad (_("there are no unsigned pc-relative relocations"));
3440 case 1: return BFD_RELOC_8_PCREL
;
3441 case 2: return BFD_RELOC_16_PCREL
;
3442 case 4: return BFD_RELOC_32_PCREL
;
3443 case 8: return BFD_RELOC_64_PCREL
;
3445 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3452 case 4: return BFD_RELOC_X86_64_32S
;
3457 case 1: return BFD_RELOC_8
;
3458 case 2: return BFD_RELOC_16
;
3459 case 4: return BFD_RELOC_32
;
3460 case 8: return BFD_RELOC_64
;
3462 as_bad (_("cannot do %s %u byte relocation"),
3463 sign
> 0 ? "signed" : "unsigned", size
);
3469 /* Here we decide which fixups can be adjusted to make them relative to
3470 the beginning of the section instead of the symbol. Basically we need
3471 to make sure that the dynamic relocations are done correctly, so in
3472 some cases we force the original symbol to be used. */
3475 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3481 /* Don't adjust pc-relative references to merge sections in 64-bit
3483 if (use_rela_relocations
3484 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3488 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3489 and changed later by validate_fix. */
3490 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3491 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3494 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3495 for size relocations. */
3496 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3497 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3498 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3499 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3500 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3501 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3502 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3503 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3504 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3505 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3506 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3507 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3508 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3509 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3510 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3511 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3512 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3513 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3515 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3516 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3517 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3518 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3519 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3520 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3521 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3522 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3523 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3524 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3525 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3526 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3533 intel_float_operand (const char *mnemonic
)
3535 /* Note that the value returned is meaningful only for opcodes with (memory)
3536 operands, hence the code here is free to improperly handle opcodes that
3537 have no operands (for better performance and smaller code). */
3539 if (mnemonic
[0] != 'f')
3540 return 0; /* non-math */
3542 switch (mnemonic
[1])
3544 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3545 the fs segment override prefix not currently handled because no
3546 call path can make opcodes without operands get here */
3548 return 2 /* integer op */;
3550 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3551 return 3; /* fldcw/fldenv */
3554 if (mnemonic
[2] != 'o' /* fnop */)
3555 return 3; /* non-waiting control op */
3558 if (mnemonic
[2] == 's')
3559 return 3; /* frstor/frstpm */
3562 if (mnemonic
[2] == 'a')
3563 return 3; /* fsave */
3564 if (mnemonic
[2] == 't')
3566 switch (mnemonic
[3])
3568 case 'c': /* fstcw */
3569 case 'd': /* fstdw */
3570 case 'e': /* fstenv */
3571 case 's': /* fsts[gw] */
3577 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3578 return 0; /* fxsave/fxrstor are not really math ops */
3585 /* Build the VEX prefix. */
3588 build_vex_prefix (const insn_template
*t
)
3590 unsigned int register_specifier
;
3591 unsigned int implied_prefix
;
3592 unsigned int vector_length
;
3595 /* Check register specifier. */
3596 if (i
.vex
.register_specifier
)
3598 register_specifier
=
3599 ~register_number (i
.vex
.register_specifier
) & 0xf;
3600 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3603 register_specifier
= 0xf;
3605 /* Use 2-byte VEX prefix by swapping destination and source operand
3606 if there are more than 1 register operand. */
3607 if (i
.reg_operands
> 1
3608 && i
.vec_encoding
!= vex_encoding_vex3
3609 && i
.dir_encoding
== dir_encoding_default
3610 && i
.operands
== i
.reg_operands
3611 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3612 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3613 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3616 unsigned int xchg
= i
.operands
- 1;
3617 union i386_op temp_op
;
3618 i386_operand_type temp_type
;
3620 temp_type
= i
.types
[xchg
];
3621 i
.types
[xchg
] = i
.types
[0];
3622 i
.types
[0] = temp_type
;
3623 temp_op
= i
.op
[xchg
];
3624 i
.op
[xchg
] = i
.op
[0];
3627 gas_assert (i
.rm
.mode
== 3);
3631 i
.rm
.regmem
= i
.rm
.reg
;
3634 if (i
.tm
.opcode_modifier
.d
)
3635 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3636 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3637 else /* Use the next insn. */
3641 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3642 are no memory operands and at least 3 register ones. */
3643 if (i
.reg_operands
>= 3
3644 && i
.vec_encoding
!= vex_encoding_vex3
3645 && i
.reg_operands
== i
.operands
- i
.imm_operands
3646 && i
.tm
.opcode_modifier
.vex
3647 && i
.tm
.opcode_modifier
.commutative
3648 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3650 && i
.vex
.register_specifier
3651 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3653 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3654 union i386_op temp_op
;
3655 i386_operand_type temp_type
;
3657 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3658 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3659 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3660 &i
.types
[i
.operands
- 3]));
3661 gas_assert (i
.rm
.mode
== 3);
3663 temp_type
= i
.types
[xchg
];
3664 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3665 i
.types
[xchg
+ 1] = temp_type
;
3666 temp_op
= i
.op
[xchg
];
3667 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3668 i
.op
[xchg
+ 1] = temp_op
;
3671 xchg
= i
.rm
.regmem
| 8;
3672 i
.rm
.regmem
= ~register_specifier
& 0xf;
3673 gas_assert (!(i
.rm
.regmem
& 8));
3674 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3675 register_specifier
= ~xchg
& 0xf;
3678 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3679 vector_length
= avxscalar
;
3680 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3686 /* Determine vector length from the last multi-length vector
3689 for (op
= t
->operands
; op
--;)
3690 if (t
->operand_types
[op
].bitfield
.xmmword
3691 && t
->operand_types
[op
].bitfield
.ymmword
3692 && i
.types
[op
].bitfield
.ymmword
)
3699 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3704 case DATA_PREFIX_OPCODE
:
3707 case REPE_PREFIX_OPCODE
:
3710 case REPNE_PREFIX_OPCODE
:
3717 /* Check the REX.W bit and VEXW. */
3718 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3719 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3720 else if (i
.tm
.opcode_modifier
.vexw
)
3721 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3723 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3725 /* Use 2-byte VEX prefix if possible. */
3727 && i
.vec_encoding
!= vex_encoding_vex3
3728 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3729 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3731 /* 2-byte VEX prefix. */
3735 i
.vex
.bytes
[0] = 0xc5;
3737 /* Check the REX.R bit. */
3738 r
= (i
.rex
& REX_R
) ? 0 : 1;
3739 i
.vex
.bytes
[1] = (r
<< 7
3740 | register_specifier
<< 3
3741 | vector_length
<< 2
3746 /* 3-byte VEX prefix. */
3749 switch (i
.tm
.opcode_modifier
.opcodespace
)
3754 i
.vex
.bytes
[0] = 0xc4;
3759 i
.vex
.bytes
[0] = 0x8f;
3765 /* The high 3 bits of the second VEX byte are 1's compliment
3766 of RXB bits from REX. */
3767 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3769 i
.vex
.bytes
[2] = (w
<< 7
3770 | register_specifier
<< 3
3771 | vector_length
<< 2
3776 static INLINE bfd_boolean
3777 is_evex_encoding (const insn_template
*t
)
3779 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3780 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3781 || t
->opcode_modifier
.sae
;
3784 static INLINE bfd_boolean
3785 is_any_vex_encoding (const insn_template
*t
)
3787 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3790 /* Build the EVEX prefix. */
3793 build_evex_prefix (void)
3795 unsigned int register_specifier
;
3796 unsigned int implied_prefix
, w
;
3797 rex_byte vrex_used
= 0;
3799 /* Check register specifier. */
3800 if (i
.vex
.register_specifier
)
3802 gas_assert ((i
.vrex
& REX_X
) == 0);
3804 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3805 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3806 register_specifier
+= 8;
3807 /* The upper 16 registers are encoded in the fourth byte of the
3809 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3810 i
.vex
.bytes
[3] = 0x8;
3811 register_specifier
= ~register_specifier
& 0xf;
3815 register_specifier
= 0xf;
3817 /* Encode upper 16 vector index register in the fourth byte of
3819 if (!(i
.vrex
& REX_X
))
3820 i
.vex
.bytes
[3] = 0x8;
3825 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3830 case DATA_PREFIX_OPCODE
:
3833 case REPE_PREFIX_OPCODE
:
3836 case REPNE_PREFIX_OPCODE
:
3843 /* 4 byte EVEX prefix. */
3845 i
.vex
.bytes
[0] = 0x62;
3847 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3849 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3850 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3851 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* Encode the U bit. */
3886 implied_prefix
|= 0x4;
3888 /* The third byte of the EVEX prefix. */
3889 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
&& i
.mask
->zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3909 for (op
= i
.operands
; op
--;)
3910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3914 if (i
.types
[op
].bitfield
.zmmword
)
3916 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3919 else if (i
.types
[op
].bitfield
.ymmword
)
3921 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3924 else if (i
.types
[op
].bitfield
.xmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3929 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3931 switch (i
.broadcast
->bytes
)
3934 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3937 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3949 if (op
>= MAX_OPERANDS
)
3953 switch (i
.tm
.opcode_modifier
.evex
)
3955 case EVEXLIG
: /* LL' is ignored */
3956 vec_length
= evexlig
<< 5;
3959 vec_length
= 0 << 5;
3962 vec_length
= 1 << 5;
3965 vec_length
= 2 << 5;
3971 i
.vex
.bytes
[3] |= vec_length
;
3972 /* Encode the broadcast bit. */
3974 i
.vex
.bytes
[3] |= 0x10;
3978 if (i
.rounding
->type
!= saeonly
)
3979 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3981 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3984 if (i
.mask
&& i
.mask
->mask
)
3985 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3989 process_immext (void)
3993 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3994 which is coded in the same place as an 8-bit immediate field
3995 would be. Here we fake an 8-bit immediate operand from the
3996 opcode suffix stored in tm.extension_opcode.
3998 AVX instructions also use this encoding, for some of
3999 3 argument instructions. */
4001 gas_assert (i
.imm_operands
<= 1
4003 || (is_any_vex_encoding (&i
.tm
)
4004 && i
.operands
<= 4)));
4006 exp
= &im_expressions
[i
.imm_operands
++];
4007 i
.op
[i
.operands
].imms
= exp
;
4008 i
.types
[i
.operands
] = imm8
;
4010 exp
->X_op
= O_constant
;
4011 exp
->X_add_number
= i
.tm
.extension_opcode
;
4012 i
.tm
.extension_opcode
= None
;
4019 switch (i
.tm
.opcode_modifier
.prefixok
)
4027 as_bad (_("invalid instruction `%s' after `%s'"),
4028 i
.tm
.name
, i
.hle_prefix
);
4031 if (i
.prefix
[LOCK_PREFIX
])
4033 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4037 case PrefixHLERelease
:
4038 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4040 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4044 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4046 as_bad (_("memory destination needed for instruction `%s'"
4047 " after `xrelease'"), i
.tm
.name
);
4054 /* Try the shortest encoding by shortening operand size. */
4057 optimize_encoding (void)
4061 if (optimize_for_space
4062 && !is_any_vex_encoding (&i
.tm
)
4063 && i
.reg_operands
== 1
4064 && i
.imm_operands
== 1
4065 && !i
.types
[1].bitfield
.byte
4066 && i
.op
[0].imms
->X_op
== O_constant
4067 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4068 && (i
.tm
.base_opcode
== 0xa8
4069 || (i
.tm
.base_opcode
== 0xf6
4070 && i
.tm
.extension_opcode
== 0x0)))
4073 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4075 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4076 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4078 i
.types
[1].bitfield
.byte
= 1;
4079 /* Ignore the suffix. */
4081 /* Convert to byte registers. */
4082 if (i
.types
[1].bitfield
.word
)
4084 else if (i
.types
[1].bitfield
.dword
)
4088 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4093 else if (flag_code
== CODE_64BIT
4094 && !is_any_vex_encoding (&i
.tm
)
4095 && ((i
.types
[1].bitfield
.qword
4096 && i
.reg_operands
== 1
4097 && i
.imm_operands
== 1
4098 && i
.op
[0].imms
->X_op
== O_constant
4099 && ((i
.tm
.base_opcode
== 0xb8
4100 && i
.tm
.extension_opcode
== None
4101 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4102 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4103 && ((i
.tm
.base_opcode
== 0x24
4104 || i
.tm
.base_opcode
== 0xa8)
4105 || (i
.tm
.base_opcode
== 0x80
4106 && i
.tm
.extension_opcode
== 0x4)
4107 || ((i
.tm
.base_opcode
== 0xf6
4108 || (i
.tm
.base_opcode
| 1) == 0xc7)
4109 && i
.tm
.extension_opcode
== 0x0)))
4110 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4111 && i
.tm
.base_opcode
== 0x83
4112 && i
.tm
.extension_opcode
== 0x4)))
4113 || (i
.types
[0].bitfield
.qword
4114 && ((i
.reg_operands
== 2
4115 && i
.op
[0].regs
== i
.op
[1].regs
4116 && (i
.tm
.base_opcode
== 0x30
4117 || i
.tm
.base_opcode
== 0x28))
4118 || (i
.reg_operands
== 1
4120 && i
.tm
.base_opcode
== 0x30)))))
4123 andq $imm31, %r64 -> andl $imm31, %r32
4124 andq $imm7, %r64 -> andl $imm7, %r32
4125 testq $imm31, %r64 -> testl $imm31, %r32
4126 xorq %r64, %r64 -> xorl %r32, %r32
4127 subq %r64, %r64 -> subl %r32, %r32
4128 movq $imm31, %r64 -> movl $imm31, %r32
4129 movq $imm32, %r64 -> movl $imm32, %r32
4131 i
.tm
.opcode_modifier
.norex64
= 1;
4132 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4135 movq $imm31, %r64 -> movl $imm31, %r32
4136 movq $imm32, %r64 -> movl $imm32, %r32
4138 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4139 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4140 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4141 i
.types
[0].bitfield
.imm32
= 1;
4142 i
.types
[0].bitfield
.imm32s
= 0;
4143 i
.types
[0].bitfield
.imm64
= 0;
4144 i
.types
[1].bitfield
.dword
= 1;
4145 i
.types
[1].bitfield
.qword
= 0;
4146 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4149 movq $imm31, %r64 -> movl $imm31, %r32
4151 i
.tm
.base_opcode
= 0xb8;
4152 i
.tm
.extension_opcode
= None
;
4153 i
.tm
.opcode_modifier
.w
= 0;
4154 i
.tm
.opcode_modifier
.modrm
= 0;
4158 else if (optimize
> 1
4159 && !optimize_for_space
4160 && !is_any_vex_encoding (&i
.tm
)
4161 && i
.reg_operands
== 2
4162 && i
.op
[0].regs
== i
.op
[1].regs
4163 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4164 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4165 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4168 andb %rN, %rN -> testb %rN, %rN
4169 andw %rN, %rN -> testw %rN, %rN
4170 andq %rN, %rN -> testq %rN, %rN
4171 orb %rN, %rN -> testb %rN, %rN
4172 orw %rN, %rN -> testw %rN, %rN
4173 orq %rN, %rN -> testq %rN, %rN
4175 and outside of 64-bit mode
4177 andl %rN, %rN -> testl %rN, %rN
4178 orl %rN, %rN -> testl %rN, %rN
4180 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4182 else if (i
.reg_operands
== 3
4183 && i
.op
[0].regs
== i
.op
[1].regs
4184 && !i
.types
[2].bitfield
.xmmword
4185 && (i
.tm
.opcode_modifier
.vex
4186 || ((!i
.mask
|| i
.mask
->zeroing
)
4188 && is_evex_encoding (&i
.tm
)
4189 && (i
.vec_encoding
!= vex_encoding_evex
4190 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4191 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4192 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4193 && i
.types
[2].bitfield
.ymmword
))))
4194 && ((i
.tm
.base_opcode
== 0x55
4195 || i
.tm
.base_opcode
== 0x6655
4196 || i
.tm
.base_opcode
== 0x66df
4197 || i
.tm
.base_opcode
== 0x57
4198 || i
.tm
.base_opcode
== 0x6657
4199 || i
.tm
.base_opcode
== 0x66ef
4200 || i
.tm
.base_opcode
== 0x66f8
4201 || i
.tm
.base_opcode
== 0x66f9
4202 || i
.tm
.base_opcode
== 0x66fa
4203 || i
.tm
.base_opcode
== 0x66fb
4204 || i
.tm
.base_opcode
== 0x42
4205 || i
.tm
.base_opcode
== 0x6642
4206 || i
.tm
.base_opcode
== 0x47
4207 || i
.tm
.base_opcode
== 0x6647)
4208 && i
.tm
.extension_opcode
== None
))
4211 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4213 EVEX VOP %zmmM, %zmmM, %zmmN
4214 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4215 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4216 EVEX VOP %ymmM, %ymmM, %ymmN
4217 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4218 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4219 VEX VOP %ymmM, %ymmM, %ymmN
4220 -> VEX VOP %xmmM, %xmmM, %xmmN
4221 VOP, one of vpandn and vpxor:
4222 VEX VOP %ymmM, %ymmM, %ymmN
4223 -> VEX VOP %xmmM, %xmmM, %xmmN
4224 VOP, one of vpandnd and vpandnq:
4225 EVEX VOP %zmmM, %zmmM, %zmmN
4226 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4227 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4228 EVEX VOP %ymmM, %ymmM, %ymmN
4229 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4230 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4231 VOP, one of vpxord and vpxorq:
4232 EVEX VOP %zmmM, %zmmM, %zmmN
4233 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4234 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4235 EVEX VOP %ymmM, %ymmM, %ymmN
4236 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4237 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4238 VOP, one of kxord and kxorq:
4239 VEX VOP %kM, %kM, %kN
4240 -> VEX kxorw %kM, %kM, %kN
4241 VOP, one of kandnd and kandnq:
4242 VEX VOP %kM, %kM, %kN
4243 -> VEX kandnw %kM, %kM, %kN
4245 if (is_evex_encoding (&i
.tm
))
4247 if (i
.vec_encoding
!= vex_encoding_evex
)
4249 i
.tm
.opcode_modifier
.vex
= VEX128
;
4250 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4251 i
.tm
.opcode_modifier
.evex
= 0;
4253 else if (optimize
> 1)
4254 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4258 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4260 i
.tm
.base_opcode
&= 0xff;
4261 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4264 i
.tm
.opcode_modifier
.vex
= VEX128
;
4266 if (i
.tm
.opcode_modifier
.vex
)
4267 for (j
= 0; j
< 3; j
++)
4269 i
.types
[j
].bitfield
.xmmword
= 1;
4270 i
.types
[j
].bitfield
.ymmword
= 0;
4273 else if (i
.vec_encoding
!= vex_encoding_evex
4274 && !i
.types
[0].bitfield
.zmmword
4275 && !i
.types
[1].bitfield
.zmmword
4278 && is_evex_encoding (&i
.tm
)
4279 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4280 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4281 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4282 || (i
.tm
.base_opcode
& ~4) == 0x66db
4283 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4284 && i
.tm
.extension_opcode
== None
)
4287 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4288 vmovdqu32 and vmovdqu64:
4289 EVEX VOP %xmmM, %xmmN
4290 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4291 EVEX VOP %ymmM, %ymmN
4292 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4294 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4296 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4298 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4300 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4301 VOP, one of vpand, vpandn, vpor, vpxor:
4302 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4303 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4304 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4305 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4306 EVEX VOP{d,q} mem, %xmmM, %xmmN
4307 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4308 EVEX VOP{d,q} mem, %ymmM, %ymmN
4309 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4311 for (j
= 0; j
< i
.operands
; j
++)
4312 if (operand_type_check (i
.types
[j
], disp
)
4313 && i
.op
[j
].disps
->X_op
== O_constant
)
4315 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4316 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4317 bytes, we choose EVEX Disp8 over VEX Disp32. */
4318 int evex_disp8
, vex_disp8
;
4319 unsigned int memshift
= i
.memshift
;
4320 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4322 evex_disp8
= fits_in_disp8 (n
);
4324 vex_disp8
= fits_in_disp8 (n
);
4325 if (evex_disp8
!= vex_disp8
)
4327 i
.memshift
= memshift
;
4331 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4334 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4335 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4336 i
.tm
.opcode_modifier
.vex
4337 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4338 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4339 /* VPAND, VPOR, and VPXOR are commutative. */
4340 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4341 i
.tm
.opcode_modifier
.commutative
= 1;
4342 i
.tm
.opcode_modifier
.evex
= 0;
4343 i
.tm
.opcode_modifier
.masking
= 0;
4344 i
.tm
.opcode_modifier
.broadcast
= 0;
4345 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4348 i
.types
[j
].bitfield
.disp8
4349 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4353 /* Return non-zero for load instruction. */
4359 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4360 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4364 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4365 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4366 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4367 if (i
.tm
.opcode_modifier
.anysize
)
4370 /* pop, popf, popa. */
4371 if (strcmp (i
.tm
.name
, "pop") == 0
4372 || i
.tm
.base_opcode
== 0x9d
4373 || i
.tm
.base_opcode
== 0x61)
4376 /* movs, cmps, lods, scas. */
4377 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4381 if (base_opcode
== 0x6f
4382 || i
.tm
.base_opcode
== 0xd7)
4384 /* NB: For AMD-specific insns with implicit memory operands,
4385 they're intentionally not covered. */
4388 /* No memory operand. */
4389 if (!i
.mem_operands
)
4395 if (i
.tm
.base_opcode
== 0xae
4396 && i
.tm
.opcode_modifier
.vex
4397 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4398 && i
.tm
.extension_opcode
== 2)
4403 /* test, not, neg, mul, imul, div, idiv. */
4404 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4405 && i
.tm
.extension_opcode
!= 1)
4409 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4412 /* add, or, adc, sbb, and, sub, xor, cmp. */
4413 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4416 /* bt, bts, btr, btc. */
4417 if (i
.tm
.base_opcode
== 0xfba
4418 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4421 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4422 if ((base_opcode
== 0xc1
4423 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4424 && i
.tm
.extension_opcode
!= 6)
4427 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4428 if (i
.tm
.base_opcode
== 0xfc7
4429 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4430 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4431 || i
.tm
.extension_opcode
== 6))
4434 /* fxrstor, ldmxcsr, xrstor. */
4435 if (i
.tm
.base_opcode
== 0xfae
4436 && (i
.tm
.extension_opcode
== 1
4437 || i
.tm
.extension_opcode
== 2
4438 || i
.tm
.extension_opcode
== 5))
4441 /* lgdt, lidt, lmsw. */
4442 if (i
.tm
.base_opcode
== 0xf01
4443 && (i
.tm
.extension_opcode
== 2
4444 || i
.tm
.extension_opcode
== 3
4445 || i
.tm
.extension_opcode
== 6))
4448 /* Check for x87 instructions. */
4449 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4451 /* Skip fst, fstp, fstenv, fstcw. */
4452 if (i
.tm
.base_opcode
== 0xd9
4453 && (i
.tm
.extension_opcode
== 2
4454 || i
.tm
.extension_opcode
== 3
4455 || i
.tm
.extension_opcode
== 6
4456 || i
.tm
.extension_opcode
== 7))
4459 /* Skip fisttp, fist, fistp, fstp. */
4460 if (i
.tm
.base_opcode
== 0xdb
4461 && (i
.tm
.extension_opcode
== 1
4462 || i
.tm
.extension_opcode
== 2
4463 || i
.tm
.extension_opcode
== 3
4464 || i
.tm
.extension_opcode
== 7))
4467 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4468 if (i
.tm
.base_opcode
== 0xdd
4469 && (i
.tm
.extension_opcode
== 1
4470 || i
.tm
.extension_opcode
== 2
4471 || i
.tm
.extension_opcode
== 3
4472 || i
.tm
.extension_opcode
== 6
4473 || i
.tm
.extension_opcode
== 7))
4476 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4477 if (i
.tm
.base_opcode
== 0xdf
4478 && (i
.tm
.extension_opcode
== 1
4479 || i
.tm
.extension_opcode
== 2
4480 || i
.tm
.extension_opcode
== 3
4481 || i
.tm
.extension_opcode
== 6
4482 || i
.tm
.extension_opcode
== 7))
4489 dest
= i
.operands
- 1;
4491 /* Check fake imm8 operand and 3 source operands. */
4492 if ((i
.tm
.opcode_modifier
.immext
4493 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4494 && i
.types
[dest
].bitfield
.imm8
)
4497 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4499 && (base_opcode
== 0x1
4500 || base_opcode
== 0x9
4501 || base_opcode
== 0x11
4502 || base_opcode
== 0x19
4503 || base_opcode
== 0x21
4504 || base_opcode
== 0x29
4505 || base_opcode
== 0x31
4506 || base_opcode
== 0x39
4507 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4508 || base_opcode
== 0xfc1))
4511 /* Check for load instruction. */
4512 return (i
.types
[dest
].bitfield
.class != ClassNone
4513 || i
.types
[dest
].bitfield
.instance
== Accum
);
4516 /* Output lfence, 0xfaee8, after instruction. */
4519 insert_lfence_after (void)
4521 if (lfence_after_load
&& load_insn_p ())
4523 /* There are also two REP string instructions that require
4524 special treatment. Specifically, the compare string (CMPS)
4525 and scan string (SCAS) instructions set EFLAGS in a manner
4526 that depends on the data being compared/scanned. When used
4527 with a REP prefix, the number of iterations may therefore
4528 vary depending on this data. If the data is a program secret
4529 chosen by the adversary using an LVI method,
4530 then this data-dependent behavior may leak some aspect
4532 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4533 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4534 && i
.prefix
[REP_PREFIX
])
4536 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4539 char *p
= frag_more (3);
4546 /* Output lfence, 0xfaee8, before instruction. */
4549 insert_lfence_before (void)
4553 if (is_any_vex_encoding (&i
.tm
))
4556 if (i
.tm
.base_opcode
== 0xff
4557 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4559 /* Insert lfence before indirect branch if needed. */
4561 if (lfence_before_indirect_branch
== lfence_branch_none
)
4564 if (i
.operands
!= 1)
4567 if (i
.reg_operands
== 1)
4569 /* Indirect branch via register. Don't insert lfence with
4570 -mlfence-after-load=yes. */
4571 if (lfence_after_load
4572 || lfence_before_indirect_branch
== lfence_branch_memory
)
4575 else if (i
.mem_operands
== 1
4576 && lfence_before_indirect_branch
!= lfence_branch_register
)
4578 as_warn (_("indirect `%s` with memory operand should be avoided"),
4585 if (last_insn
.kind
!= last_insn_other
4586 && last_insn
.seg
== now_seg
)
4588 as_warn_where (last_insn
.file
, last_insn
.line
,
4589 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4590 last_insn
.name
, i
.tm
.name
);
4601 /* Output or/not/shl and lfence before near ret. */
4602 if (lfence_before_ret
!= lfence_before_ret_none
4603 && (i
.tm
.base_opcode
== 0xc2
4604 || i
.tm
.base_opcode
== 0xc3))
4606 if (last_insn
.kind
!= last_insn_other
4607 && last_insn
.seg
== now_seg
)
4609 as_warn_where (last_insn
.file
, last_insn
.line
,
4610 _("`%s` skips -mlfence-before-ret on `%s`"),
4611 last_insn
.name
, i
.tm
.name
);
4615 /* Near ret ingore operand size override under CPU64. */
4616 char prefix
= flag_code
== CODE_64BIT
4618 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4620 if (lfence_before_ret
== lfence_before_ret_not
)
4622 /* not: 0xf71424, may add prefix
4623 for operand size override or 64-bit code. */
4624 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4638 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4641 if (lfence_before_ret
== lfence_before_ret_or
)
4643 /* or: 0x830c2400, may add prefix
4644 for operand size override or 64-bit code. */
4650 /* shl: 0xc1242400, may add prefix
4651 for operand size override or 64-bit code. */
4666 /* This is the guts of the machine-dependent assembler. LINE points to a
4667 machine dependent instruction. This function is supposed to emit
4668 the frags/bytes it assembles to. */
4671 md_assemble (char *line
)
4674 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4675 const insn_template
*t
;
4677 /* Initialize globals. */
4678 memset (&i
, '\0', sizeof (i
));
4679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4680 i
.reloc
[j
] = NO_RELOC
;
4681 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4682 memset (im_expressions
, '\0', sizeof (im_expressions
));
4683 save_stack_p
= save_stack
;
4685 /* First parse an instruction mnemonic & call i386_operand for the operands.
4686 We assume that the scrubber has arranged it so that line[0] is the valid
4687 start of a (possibly prefixed) mnemonic. */
4689 line
= parse_insn (line
, mnemonic
);
4692 mnem_suffix
= i
.suffix
;
4694 line
= parse_operands (line
, mnemonic
);
4696 xfree (i
.memop1_string
);
4697 i
.memop1_string
= NULL
;
4701 /* Now we've parsed the mnemonic into a set of templates, and have the
4702 operands at hand. */
4704 /* All Intel opcodes have reversed operands except for "bound", "enter",
4705 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4706 intersegment "jmp" and "call" instructions with 2 immediate operands so
4707 that the immediate segment precedes the offset, as it does when in AT&T
4711 && (strcmp (mnemonic
, "bound") != 0)
4712 && (strcmp (mnemonic
, "invlpga") != 0)
4713 && (strncmp (mnemonic
, "monitor", 7) != 0)
4714 && (strncmp (mnemonic
, "mwait", 5) != 0)
4715 && (strcmp (mnemonic
, "tpause") != 0)
4716 && (strcmp (mnemonic
, "umwait") != 0)
4717 && !(operand_type_check (i
.types
[0], imm
)
4718 && operand_type_check (i
.types
[1], imm
)))
4721 /* The order of the immediates should be reversed
4722 for 2 immediates extrq and insertq instructions */
4723 if (i
.imm_operands
== 2
4724 && (strcmp (mnemonic
, "extrq") == 0
4725 || strcmp (mnemonic
, "insertq") == 0))
4726 swap_2_operands (0, 1);
4731 /* Don't optimize displacement for movabs since it only takes 64bit
4734 && i
.disp_encoding
!= disp_encoding_32bit
4735 && (flag_code
!= CODE_64BIT
4736 || strcmp (mnemonic
, "movabs") != 0))
4739 /* Next, we find a template that matches the given insn,
4740 making sure the overlap of the given operands types is consistent
4741 with the template operand types. */
4743 if (!(t
= match_template (mnem_suffix
)))
4746 if (sse_check
!= check_none
4747 && !i
.tm
.opcode_modifier
.noavx
4748 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4750 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4751 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4753 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4756 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4757 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4758 || i
.tm
.cpu_flags
.bitfield
.cpusha
4759 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4761 (sse_check
== check_warning
4763 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4766 if (i
.tm
.opcode_modifier
.fwait
)
4767 if (!add_prefix (FWAIT_OPCODE
))
4770 /* Check if REP prefix is OK. */
4771 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4773 as_bad (_("invalid instruction `%s' after `%s'"),
4774 i
.tm
.name
, i
.rep_prefix
);
4778 /* Check for lock without a lockable instruction. Destination operand
4779 must be memory unless it is xchg (0x86). */
4780 if (i
.prefix
[LOCK_PREFIX
]
4781 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4782 || i
.mem_operands
== 0
4783 || (i
.tm
.base_opcode
!= 0x86
4784 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4786 as_bad (_("expecting lockable instruction after `lock'"));
4790 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4791 if (i
.prefix
[DATA_PREFIX
]
4792 && (is_any_vex_encoding (&i
.tm
)
4793 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4794 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4796 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4800 /* Check if HLE prefix is OK. */
4801 if (i
.hle_prefix
&& !check_hle ())
4804 /* Check BND prefix. */
4805 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4806 as_bad (_("expecting valid branch instruction after `bnd'"));
4808 /* Check NOTRACK prefix. */
4809 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
4810 as_bad (_("expecting indirect branch instruction after `notrack'"));
4812 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4814 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4815 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4816 else if (flag_code
!= CODE_16BIT
4817 ? i
.prefix
[ADDR_PREFIX
]
4818 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4819 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4822 /* Insert BND prefix. */
4823 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4825 if (!i
.prefix
[BND_PREFIX
])
4826 add_prefix (BND_PREFIX_OPCODE
);
4827 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4829 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4830 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4834 /* Check string instruction segment overrides. */
4835 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4837 gas_assert (i
.mem_operands
);
4838 if (!check_string ())
4840 i
.disp_operands
= 0;
4843 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4844 optimize_encoding ();
4846 if (!process_suffix ())
4849 /* Update operand types and check extended states. */
4850 for (j
= 0; j
< i
.operands
; j
++)
4852 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4853 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4858 i
.xstate
|= xstate_mmx
;
4861 i
.xstate
|= xstate_mask
;
4864 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4865 i
.xstate
|= xstate_tmm
;
4866 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4867 i
.xstate
|= xstate_zmm
;
4868 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4869 i
.xstate
|= xstate_ymm
;
4870 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4871 i
.xstate
|= xstate_xmm
;
4876 /* Make still unresolved immediate matches conform to size of immediate
4877 given in i.suffix. */
4878 if (!finalize_imm ())
4881 if (i
.types
[0].bitfield
.imm1
)
4882 i
.imm_operands
= 0; /* kludge for shift insns. */
4884 /* We only need to check those implicit registers for instructions
4885 with 3 operands or less. */
4886 if (i
.operands
<= 3)
4887 for (j
= 0; j
< i
.operands
; j
++)
4888 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4889 && !i
.types
[j
].bitfield
.xmmword
)
4892 /* For insns with operands there are more diddles to do to the opcode. */
4895 if (!process_operands ())
4898 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4900 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4901 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4904 if (is_any_vex_encoding (&i
.tm
))
4906 if (!cpu_arch_flags
.bitfield
.cpui286
)
4908 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4913 /* Check for explicit REX prefix. */
4914 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4916 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4920 if (i
.tm
.opcode_modifier
.vex
)
4921 build_vex_prefix (t
);
4923 build_evex_prefix ();
4925 /* The individual REX.RXBW bits got consumed. */
4926 i
.rex
&= REX_OPCODE
;
4929 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4930 instructions may define INT_OPCODE as well, so avoid this corner
4931 case for those instructions that use MODRM. */
4932 if (i
.tm
.base_opcode
== INT_OPCODE
4933 && !i
.tm
.opcode_modifier
.modrm
4934 && i
.op
[0].imms
->X_add_number
== 3)
4936 i
.tm
.base_opcode
= INT3_OPCODE
;
4940 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4941 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4942 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4943 && i
.op
[0].disps
->X_op
== O_constant
)
4945 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4946 the absolute address given by the constant. Since ix86 jumps and
4947 calls are pc relative, we need to generate a reloc. */
4948 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4949 i
.op
[0].disps
->X_op
= O_symbol
;
4952 /* For 8 bit registers we need an empty rex prefix. Also if the
4953 instruction already has a prefix, we need to convert old
4954 registers to new ones. */
4956 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4957 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4958 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4959 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4960 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4961 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4966 i
.rex
|= REX_OPCODE
;
4967 for (x
= 0; x
< 2; x
++)
4969 /* Look for 8 bit operand that uses old registers. */
4970 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4971 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4973 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4974 /* In case it is "hi" register, give up. */
4975 if (i
.op
[x
].regs
->reg_num
> 3)
4976 as_bad (_("can't encode register '%s%s' in an "
4977 "instruction requiring REX prefix."),
4978 register_prefix
, i
.op
[x
].regs
->reg_name
);
4980 /* Otherwise it is equivalent to the extended register.
4981 Since the encoding doesn't change this is merely
4982 cosmetic cleanup for debug output. */
4984 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4989 if (i
.rex
== 0 && i
.rex_encoding
)
4991 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4992 that uses legacy register. If it is "hi" register, don't add
4993 the REX_OPCODE byte. */
4995 for (x
= 0; x
< 2; x
++)
4996 if (i
.types
[x
].bitfield
.class == Reg
4997 && i
.types
[x
].bitfield
.byte
4998 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4999 && i
.op
[x
].regs
->reg_num
> 3)
5001 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5002 i
.rex_encoding
= FALSE
;
5011 add_prefix (REX_OPCODE
| i
.rex
);
5013 insert_lfence_before ();
5015 /* We are ready to output the insn. */
5018 insert_lfence_after ();
5020 last_insn
.seg
= now_seg
;
5022 if (i
.tm
.opcode_modifier
.isprefix
)
5024 last_insn
.kind
= last_insn_prefix
;
5025 last_insn
.name
= i
.tm
.name
;
5026 last_insn
.file
= as_where (&last_insn
.line
);
5029 last_insn
.kind
= last_insn_other
;
5033 parse_insn (char *line
, char *mnemonic
)
5036 char *token_start
= l
;
5039 const insn_template
*t
;
5045 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5050 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5052 as_bad (_("no such instruction: `%s'"), token_start
);
5057 if (!is_space_char (*l
)
5058 && *l
!= END_OF_INSN
5060 || (*l
!= PREFIX_SEPARATOR
5063 as_bad (_("invalid character %s in mnemonic"),
5064 output_invalid (*l
));
5067 if (token_start
== l
)
5069 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5070 as_bad (_("expecting prefix; got nothing"));
5072 as_bad (_("expecting mnemonic; got nothing"));
5076 /* Look up instruction (or prefix) via hash table. */
5077 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5079 if (*l
!= END_OF_INSN
5080 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5081 && current_templates
5082 && current_templates
->start
->opcode_modifier
.isprefix
)
5084 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5086 as_bad ((flag_code
!= CODE_64BIT
5087 ? _("`%s' is only supported in 64-bit mode")
5088 : _("`%s' is not supported in 64-bit mode")),
5089 current_templates
->start
->name
);
5092 /* If we are in 16-bit mode, do not allow addr16 or data16.
5093 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5094 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5095 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5096 && flag_code
!= CODE_64BIT
5097 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5098 ^ (flag_code
== CODE_16BIT
)))
5100 as_bad (_("redundant %s prefix"),
5101 current_templates
->start
->name
);
5104 if (current_templates
->start
->opcode_length
== 0)
5106 /* Handle pseudo prefixes. */
5107 switch (current_templates
->start
->base_opcode
)
5111 i
.disp_encoding
= disp_encoding_8bit
;
5115 i
.disp_encoding
= disp_encoding_16bit
;
5119 i
.disp_encoding
= disp_encoding_32bit
;
5123 i
.dir_encoding
= dir_encoding_load
;
5127 i
.dir_encoding
= dir_encoding_store
;
5131 i
.vec_encoding
= vex_encoding_vex
;
5135 i
.vec_encoding
= vex_encoding_vex3
;
5139 i
.vec_encoding
= vex_encoding_evex
;
5143 i
.rex_encoding
= TRUE
;
5145 case Prefix_NoOptimize
:
5147 i
.no_optimize
= TRUE
;
5155 /* Add prefix, checking for repeated prefixes. */
5156 switch (add_prefix (current_templates
->start
->base_opcode
))
5161 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5162 i
.notrack_prefix
= current_templates
->start
->name
;
5165 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5166 i
.hle_prefix
= current_templates
->start
->name
;
5167 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5168 i
.bnd_prefix
= current_templates
->start
->name
;
5170 i
.rep_prefix
= current_templates
->start
->name
;
5176 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5183 if (!current_templates
)
5185 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5186 Check if we should swap operand or force 32bit displacement in
5188 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5189 i
.dir_encoding
= dir_encoding_swap
;
5190 else if (mnem_p
- 3 == dot_p
5193 i
.disp_encoding
= disp_encoding_8bit
;
5194 else if (mnem_p
- 4 == dot_p
5198 i
.disp_encoding
= disp_encoding_32bit
;
5203 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5206 if (!current_templates
)
5209 if (mnem_p
> mnemonic
)
5211 /* See if we can get a match by trimming off a suffix. */
5214 case WORD_MNEM_SUFFIX
:
5215 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5216 i
.suffix
= SHORT_MNEM_SUFFIX
;
5219 case BYTE_MNEM_SUFFIX
:
5220 case QWORD_MNEM_SUFFIX
:
5221 i
.suffix
= mnem_p
[-1];
5224 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5226 case SHORT_MNEM_SUFFIX
:
5227 case LONG_MNEM_SUFFIX
:
5230 i
.suffix
= mnem_p
[-1];
5233 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5241 if (intel_float_operand (mnemonic
) == 1)
5242 i
.suffix
= SHORT_MNEM_SUFFIX
;
5244 i
.suffix
= LONG_MNEM_SUFFIX
;
5247 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5253 if (!current_templates
)
5255 as_bad (_("no such instruction: `%s'"), token_start
);
5260 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5261 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5263 /* Check for a branch hint. We allow ",pt" and ",pn" for
5264 predict taken and predict not taken respectively.
5265 I'm not sure that branch hints actually do anything on loop
5266 and jcxz insns (JumpByte) for current Pentium4 chips. They
5267 may work in the future and it doesn't hurt to accept them
5269 if (l
[0] == ',' && l
[1] == 'p')
5273 if (!add_prefix (DS_PREFIX_OPCODE
))
5277 else if (l
[2] == 'n')
5279 if (!add_prefix (CS_PREFIX_OPCODE
))
5285 /* Any other comma loses. */
5288 as_bad (_("invalid character %s in mnemonic"),
5289 output_invalid (*l
));
5293 /* Check if instruction is supported on specified architecture. */
5295 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5297 supported
|= cpu_flags_match (t
);
5298 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5300 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5301 as_warn (_("use .code16 to ensure correct addressing mode"));
5307 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5308 as_bad (flag_code
== CODE_64BIT
5309 ? _("`%s' is not supported in 64-bit mode")
5310 : _("`%s' is only supported in 64-bit mode"),
5311 current_templates
->start
->name
);
5313 as_bad (_("`%s' is not supported on `%s%s'"),
5314 current_templates
->start
->name
,
5315 cpu_arch_name
? cpu_arch_name
: default_arch
,
5316 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5322 parse_operands (char *l
, const char *mnemonic
)
5326 /* 1 if operand is pending after ','. */
5327 unsigned int expecting_operand
= 0;
5329 /* Non-zero if operand parens not balanced. */
5330 unsigned int paren_not_balanced
;
5332 while (*l
!= END_OF_INSN
)
5334 /* Skip optional white space before operand. */
5335 if (is_space_char (*l
))
5337 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5339 as_bad (_("invalid character %s before operand %d"),
5340 output_invalid (*l
),
5344 token_start
= l
; /* After white space. */
5345 paren_not_balanced
= 0;
5346 while (paren_not_balanced
|| *l
!= ',')
5348 if (*l
== END_OF_INSN
)
5350 if (paren_not_balanced
)
5353 as_bad (_("unbalanced parenthesis in operand %d."),
5356 as_bad (_("unbalanced brackets in operand %d."),
5361 break; /* we are done */
5363 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5365 as_bad (_("invalid character %s in operand %d"),
5366 output_invalid (*l
),
5373 ++paren_not_balanced
;
5375 --paren_not_balanced
;
5380 ++paren_not_balanced
;
5382 --paren_not_balanced
;
5386 if (l
!= token_start
)
5387 { /* Yes, we've read in another operand. */
5388 unsigned int operand_ok
;
5389 this_operand
= i
.operands
++;
5390 if (i
.operands
> MAX_OPERANDS
)
5392 as_bad (_("spurious operands; (%d operands/instruction max)"),
5396 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5397 /* Now parse operand adding info to 'i' as we go along. */
5398 END_STRING_AND_SAVE (l
);
5400 if (i
.mem_operands
> 1)
5402 as_bad (_("too many memory references for `%s'"),
5409 i386_intel_operand (token_start
,
5410 intel_float_operand (mnemonic
));
5412 operand_ok
= i386_att_operand (token_start
);
5414 RESTORE_END_STRING (l
);
5420 if (expecting_operand
)
5422 expecting_operand_after_comma
:
5423 as_bad (_("expecting operand after ','; got nothing"));
5428 as_bad (_("expecting operand before ','; got nothing"));
5433 /* Now *l must be either ',' or END_OF_INSN. */
5436 if (*++l
== END_OF_INSN
)
5438 /* Just skip it, if it's \n complain. */
5439 goto expecting_operand_after_comma
;
5441 expecting_operand
= 1;
5448 swap_2_operands (int xchg1
, int xchg2
)
5450 union i386_op temp_op
;
5451 i386_operand_type temp_type
;
5452 unsigned int temp_flags
;
5453 enum bfd_reloc_code_real temp_reloc
;
5455 temp_type
= i
.types
[xchg2
];
5456 i
.types
[xchg2
] = i
.types
[xchg1
];
5457 i
.types
[xchg1
] = temp_type
;
5459 temp_flags
= i
.flags
[xchg2
];
5460 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5461 i
.flags
[xchg1
] = temp_flags
;
5463 temp_op
= i
.op
[xchg2
];
5464 i
.op
[xchg2
] = i
.op
[xchg1
];
5465 i
.op
[xchg1
] = temp_op
;
5467 temp_reloc
= i
.reloc
[xchg2
];
5468 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5469 i
.reloc
[xchg1
] = temp_reloc
;
5473 if (i
.mask
->operand
== xchg1
)
5474 i
.mask
->operand
= xchg2
;
5475 else if (i
.mask
->operand
== xchg2
)
5476 i
.mask
->operand
= xchg1
;
5480 if (i
.broadcast
->operand
== xchg1
)
5481 i
.broadcast
->operand
= xchg2
;
5482 else if (i
.broadcast
->operand
== xchg2
)
5483 i
.broadcast
->operand
= xchg1
;
5487 if (i
.rounding
->operand
== xchg1
)
5488 i
.rounding
->operand
= xchg2
;
5489 else if (i
.rounding
->operand
== xchg2
)
5490 i
.rounding
->operand
= xchg1
;
5495 swap_operands (void)
5501 swap_2_operands (1, i
.operands
- 2);
5505 swap_2_operands (0, i
.operands
- 1);
5511 if (i
.mem_operands
== 2)
5513 const seg_entry
*temp_seg
;
5514 temp_seg
= i
.seg
[0];
5515 i
.seg
[0] = i
.seg
[1];
5516 i
.seg
[1] = temp_seg
;
5520 /* Try to ensure constant immediates are represented in the smallest
5525 char guess_suffix
= 0;
5529 guess_suffix
= i
.suffix
;
5530 else if (i
.reg_operands
)
5532 /* Figure out a suffix from the last register operand specified.
5533 We can't do this properly yet, i.e. excluding special register
5534 instances, but the following works for instructions with
5535 immediates. In any case, we can't set i.suffix yet. */
5536 for (op
= i
.operands
; --op
>= 0;)
5537 if (i
.types
[op
].bitfield
.class != Reg
)
5539 else if (i
.types
[op
].bitfield
.byte
)
5541 guess_suffix
= BYTE_MNEM_SUFFIX
;
5544 else if (i
.types
[op
].bitfield
.word
)
5546 guess_suffix
= WORD_MNEM_SUFFIX
;
5549 else if (i
.types
[op
].bitfield
.dword
)
5551 guess_suffix
= LONG_MNEM_SUFFIX
;
5554 else if (i
.types
[op
].bitfield
.qword
)
5556 guess_suffix
= QWORD_MNEM_SUFFIX
;
5560 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5561 guess_suffix
= WORD_MNEM_SUFFIX
;
5563 for (op
= i
.operands
; --op
>= 0;)
5564 if (operand_type_check (i
.types
[op
], imm
))
5566 switch (i
.op
[op
].imms
->X_op
)
5569 /* If a suffix is given, this operand may be shortened. */
5570 switch (guess_suffix
)
5572 case LONG_MNEM_SUFFIX
:
5573 i
.types
[op
].bitfield
.imm32
= 1;
5574 i
.types
[op
].bitfield
.imm64
= 1;
5576 case WORD_MNEM_SUFFIX
:
5577 i
.types
[op
].bitfield
.imm16
= 1;
5578 i
.types
[op
].bitfield
.imm32
= 1;
5579 i
.types
[op
].bitfield
.imm32s
= 1;
5580 i
.types
[op
].bitfield
.imm64
= 1;
5582 case BYTE_MNEM_SUFFIX
:
5583 i
.types
[op
].bitfield
.imm8
= 1;
5584 i
.types
[op
].bitfield
.imm8s
= 1;
5585 i
.types
[op
].bitfield
.imm16
= 1;
5586 i
.types
[op
].bitfield
.imm32
= 1;
5587 i
.types
[op
].bitfield
.imm32s
= 1;
5588 i
.types
[op
].bitfield
.imm64
= 1;
5592 /* If this operand is at most 16 bits, convert it
5593 to a signed 16 bit number before trying to see
5594 whether it will fit in an even smaller size.
5595 This allows a 16-bit operand such as $0xffe0 to
5596 be recognised as within Imm8S range. */
5597 if ((i
.types
[op
].bitfield
.imm16
)
5598 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5600 i
.op
[op
].imms
->X_add_number
=
5601 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5604 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5605 if ((i
.types
[op
].bitfield
.imm32
)
5606 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5609 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5610 ^ ((offsetT
) 1 << 31))
5611 - ((offsetT
) 1 << 31));
5615 = operand_type_or (i
.types
[op
],
5616 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5618 /* We must avoid matching of Imm32 templates when 64bit
5619 only immediate is available. */
5620 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5621 i
.types
[op
].bitfield
.imm32
= 0;
5628 /* Symbols and expressions. */
5630 /* Convert symbolic operand to proper sizes for matching, but don't
5631 prevent matching a set of insns that only supports sizes other
5632 than those matching the insn suffix. */
5634 i386_operand_type mask
, allowed
;
5635 const insn_template
*t
;
5637 operand_type_set (&mask
, 0);
5638 operand_type_set (&allowed
, 0);
5640 for (t
= current_templates
->start
;
5641 t
< current_templates
->end
;
5644 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5645 allowed
= operand_type_and (allowed
, anyimm
);
5647 switch (guess_suffix
)
5649 case QWORD_MNEM_SUFFIX
:
5650 mask
.bitfield
.imm64
= 1;
5651 mask
.bitfield
.imm32s
= 1;
5653 case LONG_MNEM_SUFFIX
:
5654 mask
.bitfield
.imm32
= 1;
5656 case WORD_MNEM_SUFFIX
:
5657 mask
.bitfield
.imm16
= 1;
5659 case BYTE_MNEM_SUFFIX
:
5660 mask
.bitfield
.imm8
= 1;
5665 allowed
= operand_type_and (mask
, allowed
);
5666 if (!operand_type_all_zero (&allowed
))
5667 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5674 /* Try to use the smallest displacement type too. */
5676 optimize_disp (void)
5680 for (op
= i
.operands
; --op
>= 0;)
5681 if (operand_type_check (i
.types
[op
], disp
))
5683 if (i
.op
[op
].disps
->X_op
== O_constant
)
5685 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5687 if (i
.types
[op
].bitfield
.disp16
5688 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5690 /* If this operand is at most 16 bits, convert
5691 to a signed 16 bit number and don't use 64bit
5693 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5694 i
.types
[op
].bitfield
.disp64
= 0;
5697 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5698 if (i
.types
[op
].bitfield
.disp32
5699 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5701 /* If this operand is at most 32 bits, convert
5702 to a signed 32 bit number and don't use 64bit
5704 op_disp
&= (((offsetT
) 2 << 31) - 1);
5705 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5706 i
.types
[op
].bitfield
.disp64
= 0;
5709 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5711 i
.types
[op
].bitfield
.disp8
= 0;
5712 i
.types
[op
].bitfield
.disp16
= 0;
5713 i
.types
[op
].bitfield
.disp32
= 0;
5714 i
.types
[op
].bitfield
.disp32s
= 0;
5715 i
.types
[op
].bitfield
.disp64
= 0;
5719 else if (flag_code
== CODE_64BIT
)
5721 if (fits_in_signed_long (op_disp
))
5723 i
.types
[op
].bitfield
.disp64
= 0;
5724 i
.types
[op
].bitfield
.disp32s
= 1;
5726 if (i
.prefix
[ADDR_PREFIX
]
5727 && fits_in_unsigned_long (op_disp
))
5728 i
.types
[op
].bitfield
.disp32
= 1;
5730 if ((i
.types
[op
].bitfield
.disp32
5731 || i
.types
[op
].bitfield
.disp32s
5732 || i
.types
[op
].bitfield
.disp16
)
5733 && fits_in_disp8 (op_disp
))
5734 i
.types
[op
].bitfield
.disp8
= 1;
5736 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5737 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5739 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5740 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5741 i
.types
[op
].bitfield
.disp8
= 0;
5742 i
.types
[op
].bitfield
.disp16
= 0;
5743 i
.types
[op
].bitfield
.disp32
= 0;
5744 i
.types
[op
].bitfield
.disp32s
= 0;
5745 i
.types
[op
].bitfield
.disp64
= 0;
5748 /* We only support 64bit displacement on constants. */
5749 i
.types
[op
].bitfield
.disp64
= 0;
5753 /* Return 1 if there is a match in broadcast bytes between operand
5754 GIVEN and instruction template T. */
5757 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5759 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5760 && i
.types
[given
].bitfield
.byte
)
5761 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5762 && i
.types
[given
].bitfield
.word
)
5763 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5764 && i
.types
[given
].bitfield
.dword
)
5765 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5766 && i
.types
[given
].bitfield
.qword
));
5769 /* Check if operands are valid for the instruction. */
5772 check_VecOperands (const insn_template
*t
)
5777 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5778 any one operand are implicity requiring AVX512VL support if the actual
5779 operand size is YMMword or XMMword. Since this function runs after
5780 template matching, there's no need to check for YMMword/XMMword in
5782 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5783 if (!cpu_flags_all_zero (&cpu
)
5784 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5785 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5787 for (op
= 0; op
< t
->operands
; ++op
)
5789 if (t
->operand_types
[op
].bitfield
.zmmword
5790 && (i
.types
[op
].bitfield
.ymmword
5791 || i
.types
[op
].bitfield
.xmmword
))
5793 i
.error
= unsupported
;
5799 /* Without VSIB byte, we can't have a vector register for index. */
5800 if (!t
->opcode_modifier
.sib
5802 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5803 || i
.index_reg
->reg_type
.bitfield
.ymmword
5804 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5806 i
.error
= unsupported_vector_index_register
;
5810 /* Check if default mask is allowed. */
5811 if (t
->opcode_modifier
.nodefmask
5812 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5814 i
.error
= no_default_mask
;
5818 /* For VSIB byte, we need a vector register for index, and all vector
5819 registers must be distinct. */
5820 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5823 || !((t
->opcode_modifier
.sib
== VECSIB128
5824 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5825 || (t
->opcode_modifier
.sib
== VECSIB256
5826 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5827 || (t
->opcode_modifier
.sib
== VECSIB512
5828 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5830 i
.error
= invalid_vsib_address
;
5834 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5835 if (i
.reg_operands
== 2 && !i
.mask
)
5837 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5838 gas_assert (i
.types
[0].bitfield
.xmmword
5839 || i
.types
[0].bitfield
.ymmword
);
5840 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5841 gas_assert (i
.types
[2].bitfield
.xmmword
5842 || i
.types
[2].bitfield
.ymmword
);
5843 if (operand_check
== check_none
)
5845 if (register_number (i
.op
[0].regs
)
5846 != register_number (i
.index_reg
)
5847 && register_number (i
.op
[2].regs
)
5848 != register_number (i
.index_reg
)
5849 && register_number (i
.op
[0].regs
)
5850 != register_number (i
.op
[2].regs
))
5852 if (operand_check
== check_error
)
5854 i
.error
= invalid_vector_register_set
;
5857 as_warn (_("mask, index, and destination registers should be distinct"));
5859 else if (i
.reg_operands
== 1 && i
.mask
)
5861 if (i
.types
[1].bitfield
.class == RegSIMD
5862 && (i
.types
[1].bitfield
.xmmword
5863 || i
.types
[1].bitfield
.ymmword
5864 || i
.types
[1].bitfield
.zmmword
)
5865 && (register_number (i
.op
[1].regs
)
5866 == register_number (i
.index_reg
)))
5868 if (operand_check
== check_error
)
5870 i
.error
= invalid_vector_register_set
;
5873 if (operand_check
!= check_none
)
5874 as_warn (_("index and destination registers should be distinct"));
5879 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5881 if (t
->operand_types
[0].bitfield
.tmmword
5882 && i
.reg_operands
== 3)
5884 if (register_number (i
.op
[0].regs
)
5885 == register_number (i
.op
[1].regs
)
5886 || register_number (i
.op
[0].regs
)
5887 == register_number (i
.op
[2].regs
)
5888 || register_number (i
.op
[1].regs
)
5889 == register_number (i
.op
[2].regs
))
5891 i
.error
= invalid_tmm_register_set
;
5896 /* Check if broadcast is supported by the instruction and is applied
5897 to the memory operand. */
5900 i386_operand_type type
, overlap
;
5902 /* Check if specified broadcast is supported in this instruction,
5903 and its broadcast bytes match the memory operand. */
5904 op
= i
.broadcast
->operand
;
5905 if (!t
->opcode_modifier
.broadcast
5906 || !(i
.flags
[op
] & Operand_Mem
)
5907 || (!i
.types
[op
].bitfield
.unspecified
5908 && !match_broadcast_size (t
, op
)))
5911 i
.error
= unsupported_broadcast
;
5915 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5916 * i
.broadcast
->type
);
5917 operand_type_set (&type
, 0);
5918 switch (i
.broadcast
->bytes
)
5921 type
.bitfield
.word
= 1;
5924 type
.bitfield
.dword
= 1;
5927 type
.bitfield
.qword
= 1;
5930 type
.bitfield
.xmmword
= 1;
5933 type
.bitfield
.ymmword
= 1;
5936 type
.bitfield
.zmmword
= 1;
5942 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5943 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5944 && t
->operand_types
[op
].bitfield
.byte
5945 + t
->operand_types
[op
].bitfield
.word
5946 + t
->operand_types
[op
].bitfield
.dword
5947 + t
->operand_types
[op
].bitfield
.qword
> 1)
5949 overlap
.bitfield
.xmmword
= 0;
5950 overlap
.bitfield
.ymmword
= 0;
5951 overlap
.bitfield
.zmmword
= 0;
5953 if (operand_type_all_zero (&overlap
))
5956 if (t
->opcode_modifier
.checkregsize
)
5960 type
.bitfield
.baseindex
= 1;
5961 for (j
= 0; j
< i
.operands
; ++j
)
5964 && !operand_type_register_match(i
.types
[j
],
5965 t
->operand_types
[j
],
5967 t
->operand_types
[op
]))
5972 /* If broadcast is supported in this instruction, we need to check if
5973 operand of one-element size isn't specified without broadcast. */
5974 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5976 /* Find memory operand. */
5977 for (op
= 0; op
< i
.operands
; op
++)
5978 if (i
.flags
[op
] & Operand_Mem
)
5980 gas_assert (op
< i
.operands
);
5981 /* Check size of the memory operand. */
5982 if (match_broadcast_size (t
, op
))
5984 i
.error
= broadcast_needed
;
5989 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5991 /* Check if requested masking is supported. */
5994 switch (t
->opcode_modifier
.masking
)
5998 case MERGING_MASKING
:
5999 if (i
.mask
->zeroing
)
6002 i
.error
= unsupported_masking
;
6006 case DYNAMIC_MASKING
:
6007 /* Memory destinations allow only merging masking. */
6008 if (i
.mask
->zeroing
&& i
.mem_operands
)
6010 /* Find memory operand. */
6011 for (op
= 0; op
< i
.operands
; op
++)
6012 if (i
.flags
[op
] & Operand_Mem
)
6014 gas_assert (op
< i
.operands
);
6015 if (op
== i
.operands
- 1)
6017 i
.error
= unsupported_masking
;
6027 /* Check if masking is applied to dest operand. */
6028 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6030 i
.error
= mask_not_on_destination
;
6037 if (!t
->opcode_modifier
.sae
6038 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6040 i
.error
= unsupported_rc_sae
;
6043 /* If the instruction has several immediate operands and one of
6044 them is rounding, the rounding operand should be the last
6045 immediate operand. */
6046 if (i
.imm_operands
> 1
6047 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6049 i
.error
= rc_sae_operand_not_last_imm
;
6054 /* Check the special Imm4 cases; must be the first operand. */
6055 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6057 if (i
.op
[0].imms
->X_op
!= O_constant
6058 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6064 /* Turn off Imm<N> so that update_imm won't complain. */
6065 operand_type_set (&i
.types
[0], 0);
6068 /* Check vector Disp8 operand. */
6069 if (t
->opcode_modifier
.disp8memshift
6070 && i
.disp_encoding
!= disp_encoding_32bit
)
6073 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6074 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6075 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6078 const i386_operand_type
*type
= NULL
;
6081 for (op
= 0; op
< i
.operands
; op
++)
6082 if (i
.flags
[op
] & Operand_Mem
)
6084 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6085 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6086 else if (t
->operand_types
[op
].bitfield
.xmmword
6087 + t
->operand_types
[op
].bitfield
.ymmword
6088 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6089 type
= &t
->operand_types
[op
];
6090 else if (!i
.types
[op
].bitfield
.unspecified
)
6091 type
= &i
.types
[op
];
6093 else if (i
.types
[op
].bitfield
.class == RegSIMD
6094 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6096 if (i
.types
[op
].bitfield
.zmmword
)
6098 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6100 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6106 if (type
->bitfield
.zmmword
)
6108 else if (type
->bitfield
.ymmword
)
6110 else if (type
->bitfield
.xmmword
)
6114 /* For the check in fits_in_disp8(). */
6115 if (i
.memshift
== 0)
6119 for (op
= 0; op
< i
.operands
; op
++)
6120 if (operand_type_check (i
.types
[op
], disp
)
6121 && i
.op
[op
].disps
->X_op
== O_constant
)
6123 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6125 i
.types
[op
].bitfield
.disp8
= 1;
6128 i
.types
[op
].bitfield
.disp8
= 0;
6137 /* Check if encoding requirements are met by the instruction. */
6140 VEX_check_encoding (const insn_template
*t
)
6142 if (i
.vec_encoding
== vex_encoding_error
)
6144 i
.error
= unsupported
;
6148 if (i
.vec_encoding
== vex_encoding_evex
)
6150 /* This instruction must be encoded with EVEX prefix. */
6151 if (!is_evex_encoding (t
))
6153 i
.error
= unsupported
;
6159 if (!t
->opcode_modifier
.vex
)
6161 /* This instruction template doesn't have VEX prefix. */
6162 if (i
.vec_encoding
!= vex_encoding_default
)
6164 i
.error
= unsupported
;
6173 static const insn_template
*
6174 match_template (char mnem_suffix
)
6176 /* Points to template once we've found it. */
6177 const insn_template
*t
;
6178 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6179 i386_operand_type overlap4
;
6180 unsigned int found_reverse_match
;
6181 i386_opcode_modifier suffix_check
;
6182 i386_operand_type operand_types
[MAX_OPERANDS
];
6183 int addr_prefix_disp
;
6184 unsigned int j
, size_match
, check_register
;
6185 enum i386_error specific_error
= 0;
6187 #if MAX_OPERANDS != 5
6188 # error "MAX_OPERANDS must be 5."
6191 found_reverse_match
= 0;
6192 addr_prefix_disp
= -1;
6194 /* Prepare for mnemonic suffix check. */
6195 memset (&suffix_check
, 0, sizeof (suffix_check
));
6196 switch (mnem_suffix
)
6198 case BYTE_MNEM_SUFFIX
:
6199 suffix_check
.no_bsuf
= 1;
6201 case WORD_MNEM_SUFFIX
:
6202 suffix_check
.no_wsuf
= 1;
6204 case SHORT_MNEM_SUFFIX
:
6205 suffix_check
.no_ssuf
= 1;
6207 case LONG_MNEM_SUFFIX
:
6208 suffix_check
.no_lsuf
= 1;
6210 case QWORD_MNEM_SUFFIX
:
6211 suffix_check
.no_qsuf
= 1;
6214 /* NB: In Intel syntax, normally we can check for memory operand
6215 size when there is no mnemonic suffix. But jmp and call have
6216 2 different encodings with Dword memory operand size, one with
6217 No_ldSuf and the other without. i.suffix is set to
6218 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6219 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6220 suffix_check
.no_ldsuf
= 1;
6223 /* Must have right number of operands. */
6224 i
.error
= number_of_operands_mismatch
;
6226 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6228 addr_prefix_disp
= -1;
6229 found_reverse_match
= 0;
6231 if (i
.operands
!= t
->operands
)
6234 /* Check processor support. */
6235 i
.error
= unsupported
;
6236 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6239 /* Check Pseudo Prefix. */
6240 i
.error
= unsupported
;
6241 if (t
->opcode_modifier
.pseudovexprefix
6242 && !(i
.vec_encoding
== vex_encoding_vex
6243 || i
.vec_encoding
== vex_encoding_vex3
))
6246 /* Check AT&T mnemonic. */
6247 i
.error
= unsupported_with_intel_mnemonic
;
6248 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6251 /* Check AT&T/Intel syntax. */
6252 i
.error
= unsupported_syntax
;
6253 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6254 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6257 /* Check Intel64/AMD64 ISA. */
6261 /* Default: Don't accept Intel64. */
6262 if (t
->opcode_modifier
.isa64
== INTEL64
)
6266 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6267 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6271 /* -mintel64: Don't accept AMD64. */
6272 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6277 /* Check the suffix. */
6278 i
.error
= invalid_instruction_suffix
;
6279 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6280 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6281 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6282 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6283 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6284 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6287 size_match
= operand_size_match (t
);
6291 /* This is intentionally not
6293 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6295 as the case of a missing * on the operand is accepted (perhaps with
6296 a warning, issued further down). */
6297 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6299 i
.error
= operand_type_mismatch
;
6303 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6304 operand_types
[j
] = t
->operand_types
[j
];
6306 /* In general, don't allow
6307 - 64-bit operands outside of 64-bit mode,
6308 - 32-bit operands on pre-386. */
6309 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6310 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6311 && flag_code
!= CODE_64BIT
6312 && !(t
->base_opcode
== 0xfc7
6313 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
6314 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6315 || (i
.suffix
== LONG_MNEM_SUFFIX
6316 && !cpu_arch_flags
.bitfield
.cpui386
))
6318 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6319 && !intel_float_operand (t
->name
))
6320 : intel_float_operand (t
->name
) != 2)
6321 && (t
->operands
== i
.imm_operands
6322 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6323 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6324 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6325 || (operand_types
[j
].bitfield
.class != RegMMX
6326 && operand_types
[j
].bitfield
.class != RegSIMD
6327 && operand_types
[j
].bitfield
.class != RegMask
))
6328 && !t
->opcode_modifier
.sib
)
6331 /* Do not verify operands when there are none. */
6334 if (VEX_check_encoding (t
))
6336 specific_error
= i
.error
;
6340 /* We've found a match; break out of loop. */
6344 if (!t
->opcode_modifier
.jump
6345 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6347 /* There should be only one Disp operand. */
6348 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6349 if (operand_type_check (operand_types
[j
], disp
))
6351 if (j
< MAX_OPERANDS
)
6353 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6355 addr_prefix_disp
= j
;
6357 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6358 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6362 override
= !override
;
6365 if (operand_types
[j
].bitfield
.disp32
6366 && operand_types
[j
].bitfield
.disp16
)
6368 operand_types
[j
].bitfield
.disp16
= override
;
6369 operand_types
[j
].bitfield
.disp32
= !override
;
6371 operand_types
[j
].bitfield
.disp32s
= 0;
6372 operand_types
[j
].bitfield
.disp64
= 0;
6376 if (operand_types
[j
].bitfield
.disp32s
6377 || operand_types
[j
].bitfield
.disp64
)
6379 operand_types
[j
].bitfield
.disp64
&= !override
;
6380 operand_types
[j
].bitfield
.disp32s
&= !override
;
6381 operand_types
[j
].bitfield
.disp32
= override
;
6383 operand_types
[j
].bitfield
.disp16
= 0;
6389 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6390 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6393 /* We check register size if needed. */
6394 if (t
->opcode_modifier
.checkregsize
)
6396 check_register
= (1 << t
->operands
) - 1;
6398 check_register
&= ~(1 << i
.broadcast
->operand
);
6403 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6404 switch (t
->operands
)
6407 if (!operand_type_match (overlap0
, i
.types
[0]))
6411 /* xchg %eax, %eax is a special case. It is an alias for nop
6412 only in 32bit mode and we can use opcode 0x90. In 64bit
6413 mode, we can't use 0x90 for xchg %eax, %eax since it should
6414 zero-extend %eax to %rax. */
6415 if (flag_code
== CODE_64BIT
6416 && t
->base_opcode
== 0x90
6417 && i
.types
[0].bitfield
.instance
== Accum
6418 && i
.types
[0].bitfield
.dword
6419 && i
.types
[1].bitfield
.instance
== Accum
6420 && i
.types
[1].bitfield
.dword
)
6422 /* xrelease mov %eax, <disp> is another special case. It must not
6423 match the accumulator-only encoding of mov. */
6424 if (flag_code
!= CODE_64BIT
6426 && t
->base_opcode
== 0xa0
6427 && i
.types
[0].bitfield
.instance
== Accum
6428 && (i
.flags
[1] & Operand_Mem
))
6433 if (!(size_match
& MATCH_STRAIGHT
))
6435 /* Reverse direction of operands if swapping is possible in the first
6436 place (operands need to be symmetric) and
6437 - the load form is requested, and the template is a store form,
6438 - the store form is requested, and the template is a load form,
6439 - the non-default (swapped) form is requested. */
6440 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6441 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6442 && !operand_type_all_zero (&overlap1
))
6443 switch (i
.dir_encoding
)
6445 case dir_encoding_load
:
6446 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6447 || t
->opcode_modifier
.regmem
)
6451 case dir_encoding_store
:
6452 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6453 && !t
->opcode_modifier
.regmem
)
6457 case dir_encoding_swap
:
6460 case dir_encoding_default
:
6463 /* If we want store form, we skip the current load. */
6464 if ((i
.dir_encoding
== dir_encoding_store
6465 || i
.dir_encoding
== dir_encoding_swap
)
6466 && i
.mem_operands
== 0
6467 && t
->opcode_modifier
.load
)
6472 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6473 if (!operand_type_match (overlap0
, i
.types
[0])
6474 || !operand_type_match (overlap1
, i
.types
[1])
6475 || ((check_register
& 3) == 3
6476 && !operand_type_register_match (i
.types
[0],
6481 /* Check if other direction is valid ... */
6482 if (!t
->opcode_modifier
.d
)
6486 if (!(size_match
& MATCH_REVERSE
))
6488 /* Try reversing direction of operands. */
6489 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6490 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6491 if (!operand_type_match (overlap0
, i
.types
[0])
6492 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6494 && !operand_type_register_match (i
.types
[0],
6495 operand_types
[i
.operands
- 1],
6496 i
.types
[i
.operands
- 1],
6499 /* Does not match either direction. */
6502 /* found_reverse_match holds which of D or FloatR
6504 if (!t
->opcode_modifier
.d
)
6505 found_reverse_match
= 0;
6506 else if (operand_types
[0].bitfield
.tbyte
)
6507 found_reverse_match
= Opcode_FloatD
;
6508 else if (operand_types
[0].bitfield
.xmmword
6509 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6510 || operand_types
[0].bitfield
.class == RegMMX
6511 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6512 || is_any_vex_encoding(t
))
6513 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6514 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6516 found_reverse_match
= Opcode_D
;
6517 if (t
->opcode_modifier
.floatr
)
6518 found_reverse_match
|= Opcode_FloatR
;
6522 /* Found a forward 2 operand match here. */
6523 switch (t
->operands
)
6526 overlap4
= operand_type_and (i
.types
[4],
6530 overlap3
= operand_type_and (i
.types
[3],
6534 overlap2
= operand_type_and (i
.types
[2],
6539 switch (t
->operands
)
6542 if (!operand_type_match (overlap4
, i
.types
[4])
6543 || !operand_type_register_match (i
.types
[3],
6550 if (!operand_type_match (overlap3
, i
.types
[3])
6551 || ((check_register
& 0xa) == 0xa
6552 && !operand_type_register_match (i
.types
[1],
6556 || ((check_register
& 0xc) == 0xc
6557 && !operand_type_register_match (i
.types
[2],
6564 /* Here we make use of the fact that there are no
6565 reverse match 3 operand instructions. */
6566 if (!operand_type_match (overlap2
, i
.types
[2])
6567 || ((check_register
& 5) == 5
6568 && !operand_type_register_match (i
.types
[0],
6572 || ((check_register
& 6) == 6
6573 && !operand_type_register_match (i
.types
[1],
6581 /* Found either forward/reverse 2, 3 or 4 operand match here:
6582 slip through to break. */
6585 /* Check if vector operands are valid. */
6586 if (check_VecOperands (t
))
6588 specific_error
= i
.error
;
6592 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6593 if (VEX_check_encoding (t
))
6595 specific_error
= i
.error
;
6599 /* We've found a match; break out of loop. */
6603 if (t
== current_templates
->end
)
6605 /* We found no match. */
6606 const char *err_msg
;
6607 switch (specific_error
? specific_error
: i
.error
)
6611 case operand_size_mismatch
:
6612 err_msg
= _("operand size mismatch");
6614 case operand_type_mismatch
:
6615 err_msg
= _("operand type mismatch");
6617 case register_type_mismatch
:
6618 err_msg
= _("register type mismatch");
6620 case number_of_operands_mismatch
:
6621 err_msg
= _("number of operands mismatch");
6623 case invalid_instruction_suffix
:
6624 err_msg
= _("invalid instruction suffix");
6627 err_msg
= _("constant doesn't fit in 4 bits");
6629 case unsupported_with_intel_mnemonic
:
6630 err_msg
= _("unsupported with Intel mnemonic");
6632 case unsupported_syntax
:
6633 err_msg
= _("unsupported syntax");
6636 as_bad (_("unsupported instruction `%s'"),
6637 current_templates
->start
->name
);
6639 case invalid_sib_address
:
6640 err_msg
= _("invalid SIB address");
6642 case invalid_vsib_address
:
6643 err_msg
= _("invalid VSIB address");
6645 case invalid_vector_register_set
:
6646 err_msg
= _("mask, index, and destination registers must be distinct");
6648 case invalid_tmm_register_set
:
6649 err_msg
= _("all tmm registers must be distinct");
6651 case unsupported_vector_index_register
:
6652 err_msg
= _("unsupported vector index register");
6654 case unsupported_broadcast
:
6655 err_msg
= _("unsupported broadcast");
6657 case broadcast_needed
:
6658 err_msg
= _("broadcast is needed for operand of such type");
6660 case unsupported_masking
:
6661 err_msg
= _("unsupported masking");
6663 case mask_not_on_destination
:
6664 err_msg
= _("mask not on destination operand");
6666 case no_default_mask
:
6667 err_msg
= _("default mask isn't allowed");
6669 case unsupported_rc_sae
:
6670 err_msg
= _("unsupported static rounding/sae");
6672 case rc_sae_operand_not_last_imm
:
6674 err_msg
= _("RC/SAE operand must precede immediate operands");
6676 err_msg
= _("RC/SAE operand must follow immediate operands");
6678 case invalid_register_operand
:
6679 err_msg
= _("invalid register operand");
6682 as_bad (_("%s for `%s'"), err_msg
,
6683 current_templates
->start
->name
);
6687 if (!quiet_warnings
)
6690 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6691 as_warn (_("indirect %s without `*'"), t
->name
);
6693 if (t
->opcode_modifier
.isprefix
6694 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6696 /* Warn them that a data or address size prefix doesn't
6697 affect assembly of the next line of code. */
6698 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6702 /* Copy the template we found. */
6705 if (addr_prefix_disp
!= -1)
6706 i
.tm
.operand_types
[addr_prefix_disp
]
6707 = operand_types
[addr_prefix_disp
];
6709 if (found_reverse_match
)
6711 /* If we found a reverse match we must alter the opcode direction
6712 bit and clear/flip the regmem modifier one. found_reverse_match
6713 holds bits to change (different for int & float insns). */
6715 i
.tm
.base_opcode
^= found_reverse_match
;
6717 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6718 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6720 /* Certain SIMD insns have their load forms specified in the opcode
6721 table, and hence we need to _set_ RegMem instead of clearing it.
6722 We need to avoid setting the bit though on insns like KMOVW. */
6723 i
.tm
.opcode_modifier
.regmem
6724 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6725 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6726 && !i
.tm
.opcode_modifier
.regmem
;
6735 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6736 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6738 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6740 as_bad (_("`%s' operand %u must use `%ses' segment"),
6742 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6747 /* There's only ever one segment override allowed per instruction.
6748 This instruction possibly has a legal segment override on the
6749 second operand, so copy the segment to where non-string
6750 instructions store it, allowing common code. */
6751 i
.seg
[op
] = i
.seg
[1];
6757 process_suffix (void)
6759 bfd_boolean is_crc32
= FALSE
;
6761 /* If matched instruction specifies an explicit instruction mnemonic
6763 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6764 i
.suffix
= WORD_MNEM_SUFFIX
;
6765 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6766 i
.suffix
= LONG_MNEM_SUFFIX
;
6767 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6768 i
.suffix
= QWORD_MNEM_SUFFIX
;
6769 else if (i
.reg_operands
6770 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6771 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6773 unsigned int numop
= i
.operands
;
6775 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6776 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6778 /* movsx/movzx want only their source operand considered here, for the
6779 ambiguity checking below. The suffix will be replaced afterwards
6780 to represent the destination (register). */
6781 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6782 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6785 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6786 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6789 /* If there's no instruction mnemonic suffix we try to invent one
6790 based on GPR operands. */
6793 /* We take i.suffix from the last register operand specified,
6794 Destination register type is more significant than source
6795 register type. crc32 in SSE4.2 prefers source register
6797 unsigned int op
= is_crc32
? 1 : i
.operands
;
6800 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6801 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6803 if (i
.types
[op
].bitfield
.class != Reg
)
6805 if (i
.types
[op
].bitfield
.byte
)
6806 i
.suffix
= BYTE_MNEM_SUFFIX
;
6807 else if (i
.types
[op
].bitfield
.word
)
6808 i
.suffix
= WORD_MNEM_SUFFIX
;
6809 else if (i
.types
[op
].bitfield
.dword
)
6810 i
.suffix
= LONG_MNEM_SUFFIX
;
6811 else if (i
.types
[op
].bitfield
.qword
)
6812 i
.suffix
= QWORD_MNEM_SUFFIX
;
6818 /* As an exception, movsx/movzx silently default to a byte source
6820 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6821 && !i
.suffix
&& !intel_syntax
)
6822 i
.suffix
= BYTE_MNEM_SUFFIX
;
6824 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6827 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6828 && i
.tm
.opcode_modifier
.no_bsuf
)
6830 else if (!check_byte_reg ())
6833 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6836 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6837 && i
.tm
.opcode_modifier
.no_lsuf
6838 && !i
.tm
.opcode_modifier
.todword
6839 && !i
.tm
.opcode_modifier
.toqword
)
6841 else if (!check_long_reg ())
6844 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6847 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6848 && i
.tm
.opcode_modifier
.no_qsuf
6849 && !i
.tm
.opcode_modifier
.todword
6850 && !i
.tm
.opcode_modifier
.toqword
)
6852 else if (!check_qword_reg ())
6855 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6858 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6859 && i
.tm
.opcode_modifier
.no_wsuf
)
6861 else if (!check_word_reg ())
6864 else if (intel_syntax
6865 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6866 /* Do nothing if the instruction is going to ignore the prefix. */
6871 /* Undo the movsx/movzx change done above. */
6874 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6877 i
.suffix
= stackop_size
;
6878 if (stackop_size
== LONG_MNEM_SUFFIX
)
6880 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6881 .code16gcc directive to support 16-bit mode with
6882 32-bit address. For IRET without a suffix, generate
6883 16-bit IRET (opcode 0xcf) to return from an interrupt
6885 if (i
.tm
.base_opcode
== 0xcf)
6887 i
.suffix
= WORD_MNEM_SUFFIX
;
6888 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6890 /* Warn about changed behavior for segment register push/pop. */
6891 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6892 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6897 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6898 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6899 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6900 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6901 && i
.tm
.extension_opcode
<= 3)))
6906 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6908 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6909 || i
.tm
.opcode_modifier
.no_lsuf
)
6910 i
.suffix
= QWORD_MNEM_SUFFIX
;
6915 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6916 i
.suffix
= LONG_MNEM_SUFFIX
;
6919 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6920 i
.suffix
= WORD_MNEM_SUFFIX
;
6926 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6927 /* Also cover lret/retf/iret in 64-bit mode. */
6928 || (flag_code
== CODE_64BIT
6929 && !i
.tm
.opcode_modifier
.no_lsuf
6930 && !i
.tm
.opcode_modifier
.no_qsuf
))
6931 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6932 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6933 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6934 /* Accept FLDENV et al without suffix. */
6935 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6937 unsigned int suffixes
, evex
= 0;
6939 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6940 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6942 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6944 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6946 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6948 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6951 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6952 also suitable for AT&T syntax mode, it was requested that this be
6953 restricted to just Intel syntax. */
6954 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6958 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6960 if (is_evex_encoding (&i
.tm
)
6961 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6963 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6964 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6965 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6966 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6967 if (!i
.tm
.opcode_modifier
.evex
6968 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6969 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6972 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6973 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6974 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6977 /* Any properly sized operand disambiguates the insn. */
6978 if (i
.types
[op
].bitfield
.xmmword
6979 || i
.types
[op
].bitfield
.ymmword
6980 || i
.types
[op
].bitfield
.zmmword
)
6982 suffixes
&= ~(7 << 6);
6987 if ((i
.flags
[op
] & Operand_Mem
)
6988 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6990 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6992 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6994 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6996 if (is_evex_encoding (&i
.tm
))
7002 /* Are multiple suffixes / operand sizes allowed? */
7003 if (suffixes
& (suffixes
- 1))
7006 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7007 || operand_check
== check_error
))
7009 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7012 if (operand_check
== check_error
)
7014 as_bad (_("no instruction mnemonic suffix given and "
7015 "no register operands; can't size `%s'"), i
.tm
.name
);
7018 if (operand_check
== check_warning
)
7019 as_warn (_("%s; using default for `%s'"),
7021 ? _("ambiguous operand size")
7022 : _("no instruction mnemonic suffix given and "
7023 "no register operands"),
7026 if (i
.tm
.opcode_modifier
.floatmf
)
7027 i
.suffix
= SHORT_MNEM_SUFFIX
;
7028 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7029 || (i
.tm
.base_opcode
== 0x63
7030 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7031 /* handled below */;
7033 i
.tm
.opcode_modifier
.evex
= evex
;
7034 else if (flag_code
== CODE_16BIT
)
7035 i
.suffix
= WORD_MNEM_SUFFIX
;
7036 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7037 i
.suffix
= LONG_MNEM_SUFFIX
;
7039 i
.suffix
= QWORD_MNEM_SUFFIX
;
7043 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7044 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7046 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7047 In AT&T syntax, if there is no suffix (warned about above), the default
7048 will be byte extension. */
7049 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7050 i
.tm
.base_opcode
|= 1;
7052 /* For further processing, the suffix should represent the destination
7053 (register). This is already the case when one was used with
7054 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7055 no suffix to begin with. */
7056 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7058 if (i
.types
[1].bitfield
.word
)
7059 i
.suffix
= WORD_MNEM_SUFFIX
;
7060 else if (i
.types
[1].bitfield
.qword
)
7061 i
.suffix
= QWORD_MNEM_SUFFIX
;
7063 i
.suffix
= LONG_MNEM_SUFFIX
;
7065 i
.tm
.opcode_modifier
.w
= 0;
7069 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7070 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7071 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7073 /* Change the opcode based on the operand size given by i.suffix. */
7076 /* Size floating point instruction. */
7077 case LONG_MNEM_SUFFIX
:
7078 if (i
.tm
.opcode_modifier
.floatmf
)
7080 i
.tm
.base_opcode
^= 4;
7084 case WORD_MNEM_SUFFIX
:
7085 case QWORD_MNEM_SUFFIX
:
7086 /* It's not a byte, select word/dword operation. */
7087 if (i
.tm
.opcode_modifier
.w
)
7090 i
.tm
.base_opcode
|= 8;
7092 i
.tm
.base_opcode
|= 1;
7095 case SHORT_MNEM_SUFFIX
:
7096 /* Now select between word & dword operations via the operand
7097 size prefix, except for instructions that will ignore this
7099 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7100 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7101 && !i
.tm
.opcode_modifier
.floatmf
7102 && !is_any_vex_encoding (&i
.tm
)
7103 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7104 || (flag_code
== CODE_64BIT
7105 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7107 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7109 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7110 prefix
= ADDR_PREFIX_OPCODE
;
7112 if (!add_prefix (prefix
))
7116 /* Set mode64 for an operand. */
7117 if (i
.suffix
== QWORD_MNEM_SUFFIX
7118 && flag_code
== CODE_64BIT
7119 && !i
.tm
.opcode_modifier
.norex64
7120 && !i
.tm
.opcode_modifier
.vexw
7121 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7123 && ! (i
.operands
== 2
7124 && i
.tm
.base_opcode
== 0x90
7125 && i
.tm
.extension_opcode
== None
7126 && i
.types
[0].bitfield
.instance
== Accum
7127 && i
.types
[0].bitfield
.qword
7128 && i
.types
[1].bitfield
.instance
== Accum
7129 && i
.types
[1].bitfield
.qword
))
7135 /* Select word/dword/qword operation with explicit data sizing prefix
7136 when there are no suitable register operands. */
7137 if (i
.tm
.opcode_modifier
.w
7138 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7140 || (i
.reg_operands
== 1
7142 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7144 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7145 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7148 i
.tm
.base_opcode
|= 1;
7152 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7154 gas_assert (!i
.suffix
);
7155 gas_assert (i
.reg_operands
);
7157 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7160 /* The address size override prefix changes the size of the
7162 if (flag_code
== CODE_64BIT
7163 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7165 as_bad (_("16-bit addressing unavailable for `%s'"),
7170 if ((flag_code
== CODE_32BIT
7171 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7172 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7173 && !add_prefix (ADDR_PREFIX_OPCODE
))
7178 /* Check invalid register operand when the address size override
7179 prefix changes the size of register operands. */
7181 enum { need_word
, need_dword
, need_qword
} need
;
7183 /* Check the register operand for the address size prefix if
7184 the memory operand has no real registers, like symbol, DISP
7186 if (i
.mem_operands
== 1
7187 && i
.reg_operands
== 1
7189 && i
.types
[1].bitfield
.class == Reg
7190 && (flag_code
== CODE_32BIT
7191 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7192 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7193 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7195 && i
.base_reg
->reg_num
== RegIP
7196 && i
.base_reg
->reg_type
.bitfield
.qword
))
7197 && !add_prefix (ADDR_PREFIX_OPCODE
))
7200 if (flag_code
== CODE_32BIT
)
7201 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7202 else if (i
.prefix
[ADDR_PREFIX
])
7205 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7207 for (op
= 0; op
< i
.operands
; op
++)
7209 if (i
.types
[op
].bitfield
.class != Reg
)
7215 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7219 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7223 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7228 as_bad (_("invalid register operand size for `%s'"),
7239 check_byte_reg (void)
7243 for (op
= i
.operands
; --op
>= 0;)
7245 /* Skip non-register operands. */
7246 if (i
.types
[op
].bitfield
.class != Reg
)
7249 /* If this is an eight bit register, it's OK. If it's the 16 or
7250 32 bit version of an eight bit register, we will just use the
7251 low portion, and that's OK too. */
7252 if (i
.types
[op
].bitfield
.byte
)
7255 /* I/O port address operands are OK too. */
7256 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7257 && i
.tm
.operand_types
[op
].bitfield
.word
)
7260 /* crc32 only wants its source operand checked here. */
7261 if (i
.tm
.base_opcode
== 0xf38f0
7262 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7266 /* Any other register is bad. */
7267 as_bad (_("`%s%s' not allowed with `%s%c'"),
7268 register_prefix
, i
.op
[op
].regs
->reg_name
,
7269 i
.tm
.name
, i
.suffix
);
7276 check_long_reg (void)
7280 for (op
= i
.operands
; --op
>= 0;)
7281 /* Skip non-register operands. */
7282 if (i
.types
[op
].bitfield
.class != Reg
)
7284 /* Reject eight bit registers, except where the template requires
7285 them. (eg. movzb) */
7286 else if (i
.types
[op
].bitfield
.byte
7287 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7288 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7289 && (i
.tm
.operand_types
[op
].bitfield
.word
7290 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7292 as_bad (_("`%s%s' not allowed with `%s%c'"),
7294 i
.op
[op
].regs
->reg_name
,
7299 /* Error if the e prefix on a general reg is missing. */
7300 else if (i
.types
[op
].bitfield
.word
7301 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7302 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7303 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7305 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7306 register_prefix
, i
.op
[op
].regs
->reg_name
,
7310 /* Warn if the r prefix on a general reg is present. */
7311 else if (i
.types
[op
].bitfield
.qword
7312 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7313 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7314 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7317 && i
.tm
.opcode_modifier
.toqword
7318 && i
.types
[0].bitfield
.class != RegSIMD
)
7320 /* Convert to QWORD. We want REX byte. */
7321 i
.suffix
= QWORD_MNEM_SUFFIX
;
7325 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7326 register_prefix
, i
.op
[op
].regs
->reg_name
,
7335 check_qword_reg (void)
7339 for (op
= i
.operands
; --op
>= 0; )
7340 /* Skip non-register operands. */
7341 if (i
.types
[op
].bitfield
.class != Reg
)
7343 /* Reject eight bit registers, except where the template requires
7344 them. (eg. movzb) */
7345 else if (i
.types
[op
].bitfield
.byte
7346 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7347 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7348 && (i
.tm
.operand_types
[op
].bitfield
.word
7349 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7351 as_bad (_("`%s%s' not allowed with `%s%c'"),
7353 i
.op
[op
].regs
->reg_name
,
7358 /* Warn if the r prefix on a general reg is missing. */
7359 else if ((i
.types
[op
].bitfield
.word
7360 || i
.types
[op
].bitfield
.dword
)
7361 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7362 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7363 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7365 /* Prohibit these changes in the 64bit mode, since the
7366 lowering is more complicated. */
7368 && i
.tm
.opcode_modifier
.todword
7369 && i
.types
[0].bitfield
.class != RegSIMD
)
7371 /* Convert to DWORD. We don't want REX byte. */
7372 i
.suffix
= LONG_MNEM_SUFFIX
;
7376 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7377 register_prefix
, i
.op
[op
].regs
->reg_name
,
7386 check_word_reg (void)
7389 for (op
= i
.operands
; --op
>= 0;)
7390 /* Skip non-register operands. */
7391 if (i
.types
[op
].bitfield
.class != Reg
)
7393 /* Reject eight bit registers, except where the template requires
7394 them. (eg. movzb) */
7395 else if (i
.types
[op
].bitfield
.byte
7396 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7397 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7398 && (i
.tm
.operand_types
[op
].bitfield
.word
7399 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7401 as_bad (_("`%s%s' not allowed with `%s%c'"),
7403 i
.op
[op
].regs
->reg_name
,
7408 /* Error if the e or r prefix on a general reg is present. */
7409 else if ((i
.types
[op
].bitfield
.dword
7410 || i
.types
[op
].bitfield
.qword
)
7411 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7412 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7413 && i
.tm
.operand_types
[op
].bitfield
.word
)
7415 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7416 register_prefix
, i
.op
[op
].regs
->reg_name
,
7424 update_imm (unsigned int j
)
7426 i386_operand_type overlap
= i
.types
[j
];
7427 if ((overlap
.bitfield
.imm8
7428 || overlap
.bitfield
.imm8s
7429 || overlap
.bitfield
.imm16
7430 || overlap
.bitfield
.imm32
7431 || overlap
.bitfield
.imm32s
7432 || overlap
.bitfield
.imm64
)
7433 && !operand_type_equal (&overlap
, &imm8
)
7434 && !operand_type_equal (&overlap
, &imm8s
)
7435 && !operand_type_equal (&overlap
, &imm16
)
7436 && !operand_type_equal (&overlap
, &imm32
)
7437 && !operand_type_equal (&overlap
, &imm32s
)
7438 && !operand_type_equal (&overlap
, &imm64
))
7442 i386_operand_type temp
;
7444 operand_type_set (&temp
, 0);
7445 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7447 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7448 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7450 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7451 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7452 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7454 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7455 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7458 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7461 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7462 || operand_type_equal (&overlap
, &imm16_32
)
7463 || operand_type_equal (&overlap
, &imm16_32s
))
7465 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7470 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7471 overlap
= operand_type_and (overlap
, imm32s
);
7472 else if (i
.prefix
[DATA_PREFIX
])
7473 overlap
= operand_type_and (overlap
,
7474 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7475 if (!operand_type_equal (&overlap
, &imm8
)
7476 && !operand_type_equal (&overlap
, &imm8s
)
7477 && !operand_type_equal (&overlap
, &imm16
)
7478 && !operand_type_equal (&overlap
, &imm32
)
7479 && !operand_type_equal (&overlap
, &imm32s
)
7480 && !operand_type_equal (&overlap
, &imm64
))
7482 as_bad (_("no instruction mnemonic suffix given; "
7483 "can't determine immediate size"));
7487 i
.types
[j
] = overlap
;
7497 /* Update the first 2 immediate operands. */
7498 n
= i
.operands
> 2 ? 2 : i
.operands
;
7501 for (j
= 0; j
< n
; j
++)
7502 if (update_imm (j
) == 0)
7505 /* The 3rd operand can't be immediate operand. */
7506 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7513 process_operands (void)
7515 /* Default segment register this instruction will use for memory
7516 accesses. 0 means unknown. This is only for optimizing out
7517 unnecessary segment overrides. */
7518 const seg_entry
*default_seg
= 0;
7520 if (i
.tm
.opcode_modifier
.sse2avx
)
7522 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7524 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7525 i
.prefix
[REX_PREFIX
] = 0;
7528 /* ImmExt should be processed after SSE2AVX. */
7529 else if (i
.tm
.opcode_modifier
.immext
)
7532 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7534 unsigned int dupl
= i
.operands
;
7535 unsigned int dest
= dupl
- 1;
7538 /* The destination must be an xmm register. */
7539 gas_assert (i
.reg_operands
7540 && MAX_OPERANDS
> dupl
7541 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7543 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7544 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7546 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7548 /* Keep xmm0 for instructions with VEX prefix and 3
7550 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7551 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7556 /* We remove the first xmm0 and keep the number of
7557 operands unchanged, which in fact duplicates the
7559 for (j
= 1; j
< i
.operands
; j
++)
7561 i
.op
[j
- 1] = i
.op
[j
];
7562 i
.types
[j
- 1] = i
.types
[j
];
7563 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7564 i
.flags
[j
- 1] = i
.flags
[j
];
7568 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7570 gas_assert ((MAX_OPERANDS
- 1) > dupl
7571 && (i
.tm
.opcode_modifier
.vexsources
7574 /* Add the implicit xmm0 for instructions with VEX prefix
7576 for (j
= i
.operands
; j
> 0; j
--)
7578 i
.op
[j
] = i
.op
[j
- 1];
7579 i
.types
[j
] = i
.types
[j
- 1];
7580 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7581 i
.flags
[j
] = i
.flags
[j
- 1];
7584 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7585 i
.types
[0] = regxmm
;
7586 i
.tm
.operand_types
[0] = regxmm
;
7589 i
.reg_operands
+= 2;
7594 i
.op
[dupl
] = i
.op
[dest
];
7595 i
.types
[dupl
] = i
.types
[dest
];
7596 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7597 i
.flags
[dupl
] = i
.flags
[dest
];
7606 i
.op
[dupl
] = i
.op
[dest
];
7607 i
.types
[dupl
] = i
.types
[dest
];
7608 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7609 i
.flags
[dupl
] = i
.flags
[dest
];
7612 if (i
.tm
.opcode_modifier
.immext
)
7615 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7616 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7620 for (j
= 1; j
< i
.operands
; j
++)
7622 i
.op
[j
- 1] = i
.op
[j
];
7623 i
.types
[j
- 1] = i
.types
[j
];
7625 /* We need to adjust fields in i.tm since they are used by
7626 build_modrm_byte. */
7627 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7629 i
.flags
[j
- 1] = i
.flags
[j
];
7636 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7638 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7640 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7641 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7642 regnum
= register_number (i
.op
[1].regs
);
7643 first_reg_in_group
= regnum
& ~3;
7644 last_reg_in_group
= first_reg_in_group
+ 3;
7645 if (regnum
!= first_reg_in_group
)
7646 as_warn (_("source register `%s%s' implicitly denotes"
7647 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7648 register_prefix
, i
.op
[1].regs
->reg_name
,
7649 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7650 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7653 else if (i
.tm
.opcode_modifier
.regkludge
)
7655 /* The imul $imm, %reg instruction is converted into
7656 imul $imm, %reg, %reg, and the clr %reg instruction
7657 is converted into xor %reg, %reg. */
7659 unsigned int first_reg_op
;
7661 if (operand_type_check (i
.types
[0], reg
))
7665 /* Pretend we saw the extra register operand. */
7666 gas_assert (i
.reg_operands
== 1
7667 && i
.op
[first_reg_op
+ 1].regs
== 0);
7668 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7669 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7674 if (i
.tm
.opcode_modifier
.modrm
)
7676 /* The opcode is completed (modulo i.tm.extension_opcode which
7677 must be put into the modrm byte). Now, we make the modrm and
7678 index base bytes based on all the info we've collected. */
7680 default_seg
= build_modrm_byte ();
7682 else if (i
.types
[0].bitfield
.class == SReg
)
7684 if (flag_code
!= CODE_64BIT
7685 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7686 && i
.op
[0].regs
->reg_num
== 1
7687 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7688 && i
.op
[0].regs
->reg_num
< 4)
7690 as_bad (_("you can't `%s %s%s'"),
7691 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7694 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7696 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7697 i
.tm
.opcode_length
= 2;
7699 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7701 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7705 else if (i
.tm
.opcode_modifier
.isstring
)
7707 /* For the string instructions that allow a segment override
7708 on one of their operands, the default segment is ds. */
7711 else if (i
.short_form
)
7713 /* The register or float register operand is in operand
7715 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7717 /* Register goes in low 3 bits of opcode. */
7718 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7719 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7721 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7723 /* Warn about some common errors, but press on regardless.
7724 The first case can be generated by gcc (<= 2.8.1). */
7725 if (i
.operands
== 2)
7727 /* Reversed arguments on faddp, fsubp, etc. */
7728 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7729 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7730 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7734 /* Extraneous `l' suffix on fp insn. */
7735 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7736 register_prefix
, i
.op
[0].regs
->reg_name
);
7741 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7742 && i
.tm
.base_opcode
== 0x8d /* lea */
7743 && !is_any_vex_encoding(&i
.tm
))
7745 if (!quiet_warnings
)
7746 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7750 i
.prefix
[SEG_PREFIX
] = 0;
7754 /* If a segment was explicitly specified, and the specified segment
7755 is neither the default nor the one already recorded from a prefix,
7756 use an opcode prefix to select it. If we never figured out what
7757 the default segment is, then default_seg will be zero at this
7758 point, and the specified segment prefix will always be used. */
7760 && i
.seg
[0] != default_seg
7761 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7763 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7769 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7770 bfd_boolean do_sse2avx
)
7772 if (r
->reg_flags
& RegRex
)
7774 if (i
.rex
& rex_bit
)
7775 as_bad (_("same type of prefix used twice"));
7778 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7780 gas_assert (i
.vex
.register_specifier
== r
);
7781 i
.vex
.register_specifier
+= 8;
7784 if (r
->reg_flags
& RegVRex
)
7788 static const seg_entry
*
7789 build_modrm_byte (void)
7791 const seg_entry
*default_seg
= 0;
7792 unsigned int source
, dest
;
7795 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7798 unsigned int nds
, reg_slot
;
7801 dest
= i
.operands
- 1;
7804 /* There are 2 kinds of instructions:
7805 1. 5 operands: 4 register operands or 3 register operands
7806 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7807 VexW0 or VexW1. The destination must be either XMM, YMM or
7809 2. 4 operands: 4 register operands or 3 register operands
7810 plus 1 memory operand, with VexXDS. */
7811 gas_assert ((i
.reg_operands
== 4
7812 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7813 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7814 && i
.tm
.opcode_modifier
.vexw
7815 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7817 /* If VexW1 is set, the first non-immediate operand is the source and
7818 the second non-immediate one is encoded in the immediate operand. */
7819 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7821 source
= i
.imm_operands
;
7822 reg_slot
= i
.imm_operands
+ 1;
7826 source
= i
.imm_operands
+ 1;
7827 reg_slot
= i
.imm_operands
;
7830 if (i
.imm_operands
== 0)
7832 /* When there is no immediate operand, generate an 8bit
7833 immediate operand to encode the first operand. */
7834 exp
= &im_expressions
[i
.imm_operands
++];
7835 i
.op
[i
.operands
].imms
= exp
;
7836 i
.types
[i
.operands
] = imm8
;
7839 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7840 exp
->X_op
= O_constant
;
7841 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7842 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7846 gas_assert (i
.imm_operands
== 1);
7847 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7848 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7850 /* Turn on Imm8 again so that output_imm will generate it. */
7851 i
.types
[0].bitfield
.imm8
= 1;
7853 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7854 i
.op
[0].imms
->X_add_number
7855 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7856 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7859 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7860 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7865 /* i.reg_operands MUST be the number of real register operands;
7866 implicit registers do not count. If there are 3 register
7867 operands, it must be a instruction with VexNDS. For a
7868 instruction with VexNDD, the destination register is encoded
7869 in VEX prefix. If there are 4 register operands, it must be
7870 a instruction with VEX prefix and 3 sources. */
7871 if (i
.mem_operands
== 0
7872 && ((i
.reg_operands
== 2
7873 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7874 || (i
.reg_operands
== 3
7875 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7876 || (i
.reg_operands
== 4 && vex_3_sources
)))
7884 /* When there are 3 operands, one of them may be immediate,
7885 which may be the first or the last operand. Otherwise,
7886 the first operand must be shift count register (cl) or it
7887 is an instruction with VexNDS. */
7888 gas_assert (i
.imm_operands
== 1
7889 || (i
.imm_operands
== 0
7890 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7891 || (i
.types
[0].bitfield
.instance
== RegC
7892 && i
.types
[0].bitfield
.byte
))));
7893 if (operand_type_check (i
.types
[0], imm
)
7894 || (i
.types
[0].bitfield
.instance
== RegC
7895 && i
.types
[0].bitfield
.byte
))
7901 /* When there are 4 operands, the first two must be 8bit
7902 immediate operands. The source operand will be the 3rd
7905 For instructions with VexNDS, if the first operand
7906 an imm8, the source operand is the 2nd one. If the last
7907 operand is imm8, the source operand is the first one. */
7908 gas_assert ((i
.imm_operands
== 2
7909 && i
.types
[0].bitfield
.imm8
7910 && i
.types
[1].bitfield
.imm8
)
7911 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7912 && i
.imm_operands
== 1
7913 && (i
.types
[0].bitfield
.imm8
7914 || i
.types
[i
.operands
- 1].bitfield
.imm8
7916 if (i
.imm_operands
== 2)
7920 if (i
.types
[0].bitfield
.imm8
)
7927 if (is_evex_encoding (&i
.tm
))
7929 /* For EVEX instructions, when there are 5 operands, the
7930 first one must be immediate operand. If the second one
7931 is immediate operand, the source operand is the 3th
7932 one. If the last one is immediate operand, the source
7933 operand is the 2nd one. */
7934 gas_assert (i
.imm_operands
== 2
7935 && i
.tm
.opcode_modifier
.sae
7936 && operand_type_check (i
.types
[0], imm
));
7937 if (operand_type_check (i
.types
[1], imm
))
7939 else if (operand_type_check (i
.types
[4], imm
))
7953 /* RC/SAE operand could be between DEST and SRC. That happens
7954 when one operand is GPR and the other one is XMM/YMM/ZMM
7956 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7959 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7961 /* For instructions with VexNDS, the register-only source
7962 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7963 register. It is encoded in VEX prefix. */
7965 i386_operand_type op
;
7968 /* Swap two source operands if needed. */
7969 if (i
.tm
.opcode_modifier
.swapsources
)
7977 op
= i
.tm
.operand_types
[vvvv
];
7978 if ((dest
+ 1) >= i
.operands
7979 || ((op
.bitfield
.class != Reg
7980 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7981 && op
.bitfield
.class != RegSIMD
7982 && !operand_type_equal (&op
, ®mask
)))
7984 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7990 /* One of the register operands will be encoded in the i.rm.reg
7991 field, the other in the combined i.rm.mode and i.rm.regmem
7992 fields. If no form of this instruction supports a memory
7993 destination operand, then we assume the source operand may
7994 sometimes be a memory operand and so we need to store the
7995 destination in the i.rm.reg field. */
7996 if (!i
.tm
.opcode_modifier
.regmem
7997 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7999 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8000 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8001 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8002 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8006 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8007 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8008 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8009 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8011 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8013 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8016 add_prefix (LOCK_PREFIX_OPCODE
);
8020 { /* If it's not 2 reg operands... */
8025 unsigned int fake_zero_displacement
= 0;
8028 for (op
= 0; op
< i
.operands
; op
++)
8029 if (i
.flags
[op
] & Operand_Mem
)
8031 gas_assert (op
< i
.operands
);
8033 if (i
.tm
.opcode_modifier
.sib
)
8035 /* The index register of VSIB shouldn't be RegIZ. */
8036 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8037 && i
.index_reg
->reg_num
== RegIZ
)
8040 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8043 i
.sib
.base
= NO_BASE_REGISTER
;
8044 i
.sib
.scale
= i
.log2_scale_factor
;
8045 i
.types
[op
].bitfield
.disp8
= 0;
8046 i
.types
[op
].bitfield
.disp16
= 0;
8047 i
.types
[op
].bitfield
.disp64
= 0;
8048 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8050 /* Must be 32 bit */
8051 i
.types
[op
].bitfield
.disp32
= 1;
8052 i
.types
[op
].bitfield
.disp32s
= 0;
8056 i
.types
[op
].bitfield
.disp32
= 0;
8057 i
.types
[op
].bitfield
.disp32s
= 1;
8061 /* Since the mandatory SIB always has index register, so
8062 the code logic remains unchanged. The non-mandatory SIB
8063 without index register is allowed and will be handled
8067 if (i
.index_reg
->reg_num
== RegIZ
)
8068 i
.sib
.index
= NO_INDEX_REGISTER
;
8070 i
.sib
.index
= i
.index_reg
->reg_num
;
8071 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8077 if (i
.base_reg
== 0)
8080 if (!i
.disp_operands
)
8081 fake_zero_displacement
= 1;
8082 if (i
.index_reg
== 0)
8084 i386_operand_type newdisp
;
8086 /* Both check for VSIB and mandatory non-vector SIB. */
8087 gas_assert (!i
.tm
.opcode_modifier
.sib
8088 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8089 /* Operand is just <disp> */
8090 if (flag_code
== CODE_64BIT
)
8092 /* 64bit mode overwrites the 32bit absolute
8093 addressing by RIP relative addressing and
8094 absolute addressing is encoded by one of the
8095 redundant SIB forms. */
8096 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8097 i
.sib
.base
= NO_BASE_REGISTER
;
8098 i
.sib
.index
= NO_INDEX_REGISTER
;
8099 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8101 else if ((flag_code
== CODE_16BIT
)
8102 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8104 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8109 i
.rm
.regmem
= NO_BASE_REGISTER
;
8112 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8113 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8115 else if (!i
.tm
.opcode_modifier
.sib
)
8117 /* !i.base_reg && i.index_reg */
8118 if (i
.index_reg
->reg_num
== RegIZ
)
8119 i
.sib
.index
= NO_INDEX_REGISTER
;
8121 i
.sib
.index
= i
.index_reg
->reg_num
;
8122 i
.sib
.base
= NO_BASE_REGISTER
;
8123 i
.sib
.scale
= i
.log2_scale_factor
;
8124 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8125 i
.types
[op
].bitfield
.disp8
= 0;
8126 i
.types
[op
].bitfield
.disp16
= 0;
8127 i
.types
[op
].bitfield
.disp64
= 0;
8128 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8130 /* Must be 32 bit */
8131 i
.types
[op
].bitfield
.disp32
= 1;
8132 i
.types
[op
].bitfield
.disp32s
= 0;
8136 i
.types
[op
].bitfield
.disp32
= 0;
8137 i
.types
[op
].bitfield
.disp32s
= 1;
8139 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8143 /* RIP addressing for 64bit mode. */
8144 else if (i
.base_reg
->reg_num
== RegIP
)
8146 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8147 i
.rm
.regmem
= NO_BASE_REGISTER
;
8148 i
.types
[op
].bitfield
.disp8
= 0;
8149 i
.types
[op
].bitfield
.disp16
= 0;
8150 i
.types
[op
].bitfield
.disp32
= 0;
8151 i
.types
[op
].bitfield
.disp32s
= 1;
8152 i
.types
[op
].bitfield
.disp64
= 0;
8153 i
.flags
[op
] |= Operand_PCrel
;
8154 if (! i
.disp_operands
)
8155 fake_zero_displacement
= 1;
8157 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8159 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8160 switch (i
.base_reg
->reg_num
)
8163 if (i
.index_reg
== 0)
8165 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8166 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8170 if (i
.index_reg
== 0)
8173 if (operand_type_check (i
.types
[op
], disp
) == 0)
8175 /* fake (%bp) into 0(%bp) */
8176 if (i
.disp_encoding
== disp_encoding_16bit
)
8177 i
.types
[op
].bitfield
.disp16
= 1;
8179 i
.types
[op
].bitfield
.disp8
= 1;
8180 fake_zero_displacement
= 1;
8183 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8184 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8186 default: /* (%si) -> 4 or (%di) -> 5 */
8187 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8189 if (!fake_zero_displacement
8193 fake_zero_displacement
= 1;
8194 if (i
.disp_encoding
== disp_encoding_8bit
)
8195 i
.types
[op
].bitfield
.disp8
= 1;
8197 i
.types
[op
].bitfield
.disp16
= 1;
8199 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8201 else /* i.base_reg and 32/64 bit mode */
8203 if (flag_code
== CODE_64BIT
8204 && operand_type_check (i
.types
[op
], disp
))
8206 i
.types
[op
].bitfield
.disp16
= 0;
8207 i
.types
[op
].bitfield
.disp64
= 0;
8208 if (i
.prefix
[ADDR_PREFIX
] == 0)
8210 i
.types
[op
].bitfield
.disp32
= 0;
8211 i
.types
[op
].bitfield
.disp32s
= 1;
8215 i
.types
[op
].bitfield
.disp32
= 1;
8216 i
.types
[op
].bitfield
.disp32s
= 0;
8220 if (!i
.tm
.opcode_modifier
.sib
)
8221 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8222 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8224 i
.sib
.base
= i
.base_reg
->reg_num
;
8225 /* x86-64 ignores REX prefix bit here to avoid decoder
8227 if (!(i
.base_reg
->reg_flags
& RegRex
)
8228 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8229 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8231 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8233 fake_zero_displacement
= 1;
8234 if (i
.disp_encoding
== disp_encoding_32bit
)
8235 i
.types
[op
].bitfield
.disp32
= 1;
8237 i
.types
[op
].bitfield
.disp8
= 1;
8239 i
.sib
.scale
= i
.log2_scale_factor
;
8240 if (i
.index_reg
== 0)
8242 /* Only check for VSIB. */
8243 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8244 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8245 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8247 /* <disp>(%esp) becomes two byte modrm with no index
8248 register. We've already stored the code for esp
8249 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8250 Any base register besides %esp will not use the
8251 extra modrm byte. */
8252 i
.sib
.index
= NO_INDEX_REGISTER
;
8254 else if (!i
.tm
.opcode_modifier
.sib
)
8256 if (i
.index_reg
->reg_num
== RegIZ
)
8257 i
.sib
.index
= NO_INDEX_REGISTER
;
8259 i
.sib
.index
= i
.index_reg
->reg_num
;
8260 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8261 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8266 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8267 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8271 if (!fake_zero_displacement
8275 fake_zero_displacement
= 1;
8276 if (i
.disp_encoding
== disp_encoding_8bit
)
8277 i
.types
[op
].bitfield
.disp8
= 1;
8279 i
.types
[op
].bitfield
.disp32
= 1;
8281 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8285 if (fake_zero_displacement
)
8287 /* Fakes a zero displacement assuming that i.types[op]
8288 holds the correct displacement size. */
8291 gas_assert (i
.op
[op
].disps
== 0);
8292 exp
= &disp_expressions
[i
.disp_operands
++];
8293 i
.op
[op
].disps
= exp
;
8294 exp
->X_op
= O_constant
;
8295 exp
->X_add_number
= 0;
8296 exp
->X_add_symbol
= (symbolS
*) 0;
8297 exp
->X_op_symbol
= (symbolS
*) 0;
8305 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8307 if (operand_type_check (i
.types
[0], imm
))
8308 i
.vex
.register_specifier
= NULL
;
8311 /* VEX.vvvv encodes one of the sources when the first
8312 operand is not an immediate. */
8313 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8314 i
.vex
.register_specifier
= i
.op
[0].regs
;
8316 i
.vex
.register_specifier
= i
.op
[1].regs
;
8319 /* Destination is a XMM register encoded in the ModRM.reg
8321 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8322 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8325 /* ModRM.rm and VEX.B encodes the other source. */
8326 if (!i
.mem_operands
)
8330 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8331 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8333 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8335 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8339 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8341 i
.vex
.register_specifier
= i
.op
[2].regs
;
8342 if (!i
.mem_operands
)
8345 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8346 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8350 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8351 (if any) based on i.tm.extension_opcode. Again, we must be
8352 careful to make sure that segment/control/debug/test/MMX
8353 registers are coded into the i.rm.reg field. */
8354 else if (i
.reg_operands
)
8357 unsigned int vex_reg
= ~0;
8359 for (op
= 0; op
< i
.operands
; op
++)
8360 if (i
.types
[op
].bitfield
.class == Reg
8361 || i
.types
[op
].bitfield
.class == RegBND
8362 || i
.types
[op
].bitfield
.class == RegMask
8363 || i
.types
[op
].bitfield
.class == SReg
8364 || i
.types
[op
].bitfield
.class == RegCR
8365 || i
.types
[op
].bitfield
.class == RegDR
8366 || i
.types
[op
].bitfield
.class == RegTR
8367 || i
.types
[op
].bitfield
.class == RegSIMD
8368 || i
.types
[op
].bitfield
.class == RegMMX
)
8373 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8375 /* For instructions with VexNDS, the register-only
8376 source operand is encoded in VEX prefix. */
8377 gas_assert (mem
!= (unsigned int) ~0);
8382 gas_assert (op
< i
.operands
);
8386 /* Check register-only source operand when two source
8387 operands are swapped. */
8388 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8389 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8393 gas_assert (mem
== (vex_reg
+ 1)
8394 && op
< i
.operands
);
8399 gas_assert (vex_reg
< i
.operands
);
8403 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8405 /* For instructions with VexNDD, the register destination
8406 is encoded in VEX prefix. */
8407 if (i
.mem_operands
== 0)
8409 /* There is no memory operand. */
8410 gas_assert ((op
+ 2) == i
.operands
);
8415 /* There are only 2 non-immediate operands. */
8416 gas_assert (op
< i
.imm_operands
+ 2
8417 && i
.operands
== i
.imm_operands
+ 2);
8418 vex_reg
= i
.imm_operands
+ 1;
8422 gas_assert (op
< i
.operands
);
8424 if (vex_reg
!= (unsigned int) ~0)
8426 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8428 if ((type
->bitfield
.class != Reg
8429 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8430 && type
->bitfield
.class != RegSIMD
8431 && !operand_type_equal (type
, ®mask
))
8434 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8437 /* Don't set OP operand twice. */
8440 /* If there is an extension opcode to put here, the
8441 register number must be put into the regmem field. */
8442 if (i
.tm
.extension_opcode
!= None
)
8444 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8445 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8446 i
.tm
.opcode_modifier
.sse2avx
);
8450 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8451 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8452 i
.tm
.opcode_modifier
.sse2avx
);
8456 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8457 must set it to 3 to indicate this is a register operand
8458 in the regmem field. */
8459 if (!i
.mem_operands
)
8463 /* Fill in i.rm.reg field with extension opcode (if any). */
8464 if (i
.tm
.extension_opcode
!= None
)
8465 i
.rm
.reg
= i
.tm
.extension_opcode
;
8471 frag_opcode_byte (unsigned char byte
)
8473 if (now_seg
!= absolute_section
)
8474 FRAG_APPEND_1_CHAR (byte
);
8476 ++abs_section_offset
;
8480 flip_code16 (unsigned int code16
)
8482 gas_assert (i
.tm
.operands
== 1);
8484 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8485 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8486 || i
.tm
.operand_types
[0].bitfield
.disp32s
8487 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8492 output_branch (void)
8498 relax_substateT subtype
;
8502 if (now_seg
== absolute_section
)
8504 as_bad (_("relaxable branches not supported in absolute section"));
8508 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8509 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8512 if (i
.prefix
[DATA_PREFIX
] != 0)
8516 code16
^= flip_code16(code16
);
8518 /* Pentium4 branch hints. */
8519 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8520 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8525 if (i
.prefix
[REX_PREFIX
] != 0)
8531 /* BND prefixed jump. */
8532 if (i
.prefix
[BND_PREFIX
] != 0)
8538 if (i
.prefixes
!= 0)
8539 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8541 /* It's always a symbol; End frag & setup for relax.
8542 Make sure there is enough room in this frag for the largest
8543 instruction we may generate in md_convert_frag. This is 2
8544 bytes for the opcode and room for the prefix and largest
8546 frag_grow (prefix
+ 2 + 4);
8547 /* Prefix and 1 opcode byte go in fr_fix. */
8548 p
= frag_more (prefix
+ 1);
8549 if (i
.prefix
[DATA_PREFIX
] != 0)
8550 *p
++ = DATA_PREFIX_OPCODE
;
8551 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8552 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8553 *p
++ = i
.prefix
[SEG_PREFIX
];
8554 if (i
.prefix
[BND_PREFIX
] != 0)
8555 *p
++ = BND_PREFIX_OPCODE
;
8556 if (i
.prefix
[REX_PREFIX
] != 0)
8557 *p
++ = i
.prefix
[REX_PREFIX
];
8558 *p
= i
.tm
.base_opcode
;
8560 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8561 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8562 else if (cpu_arch_flags
.bitfield
.cpui386
)
8563 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8565 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8568 sym
= i
.op
[0].disps
->X_add_symbol
;
8569 off
= i
.op
[0].disps
->X_add_number
;
8571 if (i
.op
[0].disps
->X_op
!= O_constant
8572 && i
.op
[0].disps
->X_op
!= O_symbol
)
8574 /* Handle complex expressions. */
8575 sym
= make_expr_symbol (i
.op
[0].disps
);
8579 /* 1 possible extra opcode + 4 byte displacement go in var part.
8580 Pass reloc in fr_var. */
8581 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8584 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8585 /* Return TRUE iff PLT32 relocation should be used for branching to
8589 need_plt32_p (symbolS
*s
)
8591 /* PLT32 relocation is ELF only. */
8596 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8597 krtld support it. */
8601 /* Since there is no need to prepare for PLT branch on x86-64, we
8602 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8603 be used as a marker for 32-bit PC-relative branches. */
8610 /* Weak or undefined symbol need PLT32 relocation. */
8611 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8614 /* Non-global symbol doesn't need PLT32 relocation. */
8615 if (! S_IS_EXTERNAL (s
))
8618 /* Other global symbols need PLT32 relocation. NB: Symbol with
8619 non-default visibilities are treated as normal global symbol
8620 so that PLT32 relocation can be used as a marker for 32-bit
8621 PC-relative branches. It is useful for linker relaxation. */
8632 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8634 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8636 /* This is a loop or jecxz type instruction. */
8638 if (i
.prefix
[ADDR_PREFIX
] != 0)
8640 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8643 /* Pentium4 branch hints. */
8644 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8645 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8647 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8656 if (flag_code
== CODE_16BIT
)
8659 if (i
.prefix
[DATA_PREFIX
] != 0)
8661 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8663 code16
^= flip_code16(code16
);
8671 /* BND prefixed jump. */
8672 if (i
.prefix
[BND_PREFIX
] != 0)
8674 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8678 if (i
.prefix
[REX_PREFIX
] != 0)
8680 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8684 if (i
.prefixes
!= 0)
8685 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8687 if (now_seg
== absolute_section
)
8689 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8693 p
= frag_more (i
.tm
.opcode_length
+ size
);
8694 switch (i
.tm
.opcode_length
)
8697 *p
++ = i
.tm
.base_opcode
>> 8;
8700 *p
++ = i
.tm
.base_opcode
;
8706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8708 && jump_reloc
== NO_RELOC
8709 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8710 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8713 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8715 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8716 i
.op
[0].disps
, 1, jump_reloc
);
8718 /* All jumps handled here are signed, but don't use a signed limit
8719 check for 32 and 16 bit jumps as we want to allow wrap around at
8720 4G and 64k respectively. */
8722 fixP
->fx_signed
= 1;
8726 output_interseg_jump (void)
8734 if (flag_code
== CODE_16BIT
)
8738 if (i
.prefix
[DATA_PREFIX
] != 0)
8745 gas_assert (!i
.prefix
[REX_PREFIX
]);
8751 if (i
.prefixes
!= 0)
8752 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8754 if (now_seg
== absolute_section
)
8756 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8760 /* 1 opcode; 2 segment; offset */
8761 p
= frag_more (prefix
+ 1 + 2 + size
);
8763 if (i
.prefix
[DATA_PREFIX
] != 0)
8764 *p
++ = DATA_PREFIX_OPCODE
;
8766 if (i
.prefix
[REX_PREFIX
] != 0)
8767 *p
++ = i
.prefix
[REX_PREFIX
];
8769 *p
++ = i
.tm
.base_opcode
;
8770 if (i
.op
[1].imms
->X_op
== O_constant
)
8772 offsetT n
= i
.op
[1].imms
->X_add_number
;
8775 && !fits_in_unsigned_word (n
)
8776 && !fits_in_signed_word (n
))
8778 as_bad (_("16-bit jump out of range"));
8781 md_number_to_chars (p
, n
, size
);
8784 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8785 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8788 if (i
.op
[0].imms
->X_op
== O_constant
)
8789 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8791 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8792 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8795 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8800 asection
*seg
= now_seg
;
8801 subsegT subseg
= now_subseg
;
8803 unsigned int alignment
, align_size_1
;
8804 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8805 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8806 unsigned int padding
;
8808 if (!IS_ELF
|| !x86_used_note
)
8811 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8813 /* The .note.gnu.property section layout:
8815 Field Length Contents
8818 n_descsz 4 The note descriptor size
8819 n_type 4 NT_GNU_PROPERTY_TYPE_0
8821 n_desc n_descsz The program property array
8825 /* Create the .note.gnu.property section. */
8826 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8827 bfd_set_section_flags (sec
,
8834 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8845 bfd_set_section_alignment (sec
, alignment
);
8846 elf_section_type (sec
) = SHT_NOTE
;
8848 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8850 isa_1_descsz_raw
= 4 + 4 + 4;
8851 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8852 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8854 feature_2_descsz_raw
= isa_1_descsz
;
8855 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8857 feature_2_descsz_raw
+= 4 + 4 + 4;
8858 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8859 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8862 descsz
= feature_2_descsz
;
8863 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8864 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8866 /* Write n_namsz. */
8867 md_number_to_chars (p
, (valueT
) 4, 4);
8869 /* Write n_descsz. */
8870 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8873 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8876 memcpy (p
+ 4 * 3, "GNU", 4);
8878 /* Write 4-byte type. */
8879 md_number_to_chars (p
+ 4 * 4,
8880 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8882 /* Write 4-byte data size. */
8883 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8885 /* Write 4-byte data. */
8886 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8888 /* Zero out paddings. */
8889 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8891 memset (p
+ 4 * 7, 0, padding
);
8893 /* Write 4-byte type. */
8894 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8895 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8897 /* Write 4-byte data size. */
8898 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8900 /* Write 4-byte data. */
8901 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8902 (valueT
) x86_feature_2_used
, 4);
8904 /* Zero out paddings. */
8905 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8907 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8909 /* We probably can't restore the current segment, for there likely
8912 subseg_set (seg
, subseg
);
8917 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8918 const char *frag_now_ptr
)
8920 unsigned int len
= 0;
8922 if (start_frag
!= frag_now
)
8924 const fragS
*fr
= start_frag
;
8929 } while (fr
&& fr
!= frag_now
);
8932 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8935 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8936 be macro-fused with conditional jumps.
8937 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8938 or is one of the following format:
8951 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8953 /* No RIP address. */
8954 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8957 /* No VEX/EVEX encoding. */
8958 if (is_any_vex_encoding (&i
.tm
))
8961 /* add, sub without add/sub m, imm. */
8962 if (i
.tm
.base_opcode
<= 5
8963 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8964 || ((i
.tm
.base_opcode
| 3) == 0x83
8965 && (i
.tm
.extension_opcode
== 0x5
8966 || i
.tm
.extension_opcode
== 0x0)))
8968 *mf_cmp_p
= mf_cmp_alu_cmp
;
8969 return !(i
.mem_operands
&& i
.imm_operands
);
8972 /* and without and m, imm. */
8973 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8974 || ((i
.tm
.base_opcode
| 3) == 0x83
8975 && i
.tm
.extension_opcode
== 0x4))
8977 *mf_cmp_p
= mf_cmp_test_and
;
8978 return !(i
.mem_operands
&& i
.imm_operands
);
8981 /* test without test m imm. */
8982 if ((i
.tm
.base_opcode
| 1) == 0x85
8983 || (i
.tm
.base_opcode
| 1) == 0xa9
8984 || ((i
.tm
.base_opcode
| 1) == 0xf7
8985 && i
.tm
.extension_opcode
== 0))
8987 *mf_cmp_p
= mf_cmp_test_and
;
8988 return !(i
.mem_operands
&& i
.imm_operands
);
8991 /* cmp without cmp m, imm. */
8992 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8993 || ((i
.tm
.base_opcode
| 3) == 0x83
8994 && (i
.tm
.extension_opcode
== 0x7)))
8996 *mf_cmp_p
= mf_cmp_alu_cmp
;
8997 return !(i
.mem_operands
&& i
.imm_operands
);
9000 /* inc, dec without inc/dec m. */
9001 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9002 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9003 || ((i
.tm
.base_opcode
| 1) == 0xff
9004 && i
.tm
.extension_opcode
<= 0x1))
9006 *mf_cmp_p
= mf_cmp_incdec
;
9007 return !i
.mem_operands
;
9013 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9016 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9018 /* NB: Don't work with COND_JUMP86 without i386. */
9019 if (!align_branch_power
9020 || now_seg
== absolute_section
9021 || !cpu_arch_flags
.bitfield
.cpui386
9022 || !(align_branch
& align_branch_fused_bit
))
9025 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9027 if (last_insn
.kind
== last_insn_other
9028 || last_insn
.seg
!= now_seg
)
9031 as_warn_where (last_insn
.file
, last_insn
.line
,
9032 _("`%s` skips -malign-branch-boundary on `%s`"),
9033 last_insn
.name
, i
.tm
.name
);
9039 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9042 add_branch_prefix_frag_p (void)
9044 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9045 to PadLock instructions since they include prefixes in opcode. */
9046 if (!align_branch_power
9047 || !align_branch_prefix_size
9048 || now_seg
== absolute_section
9049 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9050 || !cpu_arch_flags
.bitfield
.cpui386
)
9053 /* Don't add prefix if it is a prefix or there is no operand in case
9054 that segment prefix is special. */
9055 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9058 if (last_insn
.kind
== last_insn_other
9059 || last_insn
.seg
!= now_seg
)
9063 as_warn_where (last_insn
.file
, last_insn
.line
,
9064 _("`%s` skips -malign-branch-boundary on `%s`"),
9065 last_insn
.name
, i
.tm
.name
);
9070 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9073 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9074 enum mf_jcc_kind
*mf_jcc_p
)
9078 /* NB: Don't work with COND_JUMP86 without i386. */
9079 if (!align_branch_power
9080 || now_seg
== absolute_section
9081 || !cpu_arch_flags
.bitfield
.cpui386
)
9086 /* Check for jcc and direct jmp. */
9087 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9089 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9091 *branch_p
= align_branch_jmp
;
9092 add_padding
= align_branch
& align_branch_jmp_bit
;
9096 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9097 igore the lowest bit. */
9098 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9099 *branch_p
= align_branch_jcc
;
9100 if ((align_branch
& align_branch_jcc_bit
))
9104 else if (is_any_vex_encoding (&i
.tm
))
9106 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9109 *branch_p
= align_branch_ret
;
9110 if ((align_branch
& align_branch_ret_bit
))
9115 /* Check for indirect jmp, direct and indirect calls. */
9116 if (i
.tm
.base_opcode
== 0xe8)
9119 *branch_p
= align_branch_call
;
9120 if ((align_branch
& align_branch_call_bit
))
9123 else if (i
.tm
.base_opcode
== 0xff
9124 && (i
.tm
.extension_opcode
== 2
9125 || i
.tm
.extension_opcode
== 4))
9127 /* Indirect call and jmp. */
9128 *branch_p
= align_branch_indirect
;
9129 if ((align_branch
& align_branch_indirect_bit
))
9136 && (i
.op
[0].disps
->X_op
== O_symbol
9137 || (i
.op
[0].disps
->X_op
== O_subtract
9138 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9140 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9141 /* No padding to call to global or undefined tls_get_addr. */
9142 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9143 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9149 && last_insn
.kind
!= last_insn_other
9150 && last_insn
.seg
== now_seg
)
9153 as_warn_where (last_insn
.file
, last_insn
.line
,
9154 _("`%s` skips -malign-branch-boundary on `%s`"),
9155 last_insn
.name
, i
.tm
.name
);
9165 fragS
*insn_start_frag
;
9166 offsetT insn_start_off
;
9167 fragS
*fragP
= NULL
;
9168 enum align_branch_kind branch
= align_branch_none
;
9169 /* The initializer is arbitrary just to avoid uninitialized error.
9170 it's actually either assigned in add_branch_padding_frag_p
9171 or never be used. */
9172 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9175 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9177 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9178 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9179 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9181 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9182 || i
.tm
.cpu_flags
.bitfield
.cpu287
9183 || i
.tm
.cpu_flags
.bitfield
.cpu387
9184 || i
.tm
.cpu_flags
.bitfield
.cpu687
9185 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9186 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9188 if ((i
.xstate
& xstate_mmx
)
9189 || i
.tm
.base_opcode
== 0xf77 /* emms */
9190 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9191 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9195 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9196 i
.xstate
|= xstate_zmm
;
9197 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9198 i
.xstate
|= xstate_ymm
;
9199 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9200 i
.xstate
|= xstate_xmm
;
9203 /* vzeroall / vzeroupper */
9204 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9205 i
.xstate
|= xstate_ymm
;
9207 if ((i
.xstate
& xstate_xmm
)
9208 /* ldmxcsr / stmxcsr */
9209 || (i
.tm
.base_opcode
== 0xfae && i
.tm
.cpu_flags
.bitfield
.cpusse
)
9210 /* vldmxcsr / vstmxcsr */
9211 || (i
.tm
.base_opcode
== 0xae && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9212 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9213 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9214 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9216 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9217 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9218 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9219 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9220 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9221 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9222 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9223 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9224 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9225 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9226 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9227 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9228 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9229 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9231 if (x86_feature_2_used
9232 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9233 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9234 || (i
.tm
.base_opcode
== 0xfc7
9235 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9236 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9238 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9239 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9240 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9241 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9242 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9243 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9244 /* LAHF-SAHF insns in 64-bit mode. */
9245 || (flag_code
== CODE_64BIT
9246 && (i
.tm
.base_opcode
| 1) == 0x9f))
9247 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9248 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9249 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9250 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9251 CpuAVX512DQ, LPW, TBM and AMX. */
9252 || (i
.tm
.opcode_modifier
.vex
9253 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9254 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9255 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9256 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9257 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9258 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9259 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9260 || i
.tm
.cpu_flags
.bitfield
.cpufma
9261 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9262 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9263 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9264 || (x86_feature_2_used
9265 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9266 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9267 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9268 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9269 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9270 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9271 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9272 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9273 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9275 || (i
.tm
.opcode_modifier
.evex
9276 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9277 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9278 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9279 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9283 /* Tie dwarf2 debug info to the address at the start of the insn.
9284 We can't do this after the insn has been output as the current
9285 frag may have been closed off. eg. by frag_var. */
9286 dwarf2_emit_insn (0);
9288 insn_start_frag
= frag_now
;
9289 insn_start_off
= frag_now_fix ();
9291 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9294 /* Branch can be 8 bytes. Leave some room for prefixes. */
9295 unsigned int max_branch_padding_size
= 14;
9297 /* Align section to boundary. */
9298 record_alignment (now_seg
, align_branch_power
);
9300 /* Make room for padding. */
9301 frag_grow (max_branch_padding_size
);
9303 /* Start of the padding. */
9308 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9309 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9312 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9313 fragP
->tc_frag_data
.branch_type
= branch
;
9314 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9318 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9320 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9321 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9323 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9324 output_interseg_jump ();
9327 /* Output normal instructions here. */
9331 enum mf_cmp_kind mf_cmp
;
9334 && (i
.tm
.base_opcode
== 0xfaee8
9335 || i
.tm
.base_opcode
== 0xfaef0
9336 || i
.tm
.base_opcode
== 0xfaef8))
9338 /* Encode lfence, mfence, and sfence as
9339 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9340 if (now_seg
!= absolute_section
)
9342 offsetT val
= 0x240483f0ULL
;
9345 md_number_to_chars (p
, val
, 5);
9348 abs_section_offset
+= 5;
9352 /* Some processors fail on LOCK prefix. This options makes
9353 assembler ignore LOCK prefix and serves as a workaround. */
9354 if (omit_lock_prefix
)
9356 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9358 i
.prefix
[LOCK_PREFIX
] = 0;
9362 /* Skip if this is a branch. */
9364 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9366 /* Make room for padding. */
9367 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9372 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9373 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9376 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9377 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9378 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9380 else if (add_branch_prefix_frag_p ())
9382 unsigned int max_prefix_size
= align_branch_prefix_size
;
9384 /* Make room for padding. */
9385 frag_grow (max_prefix_size
);
9390 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9391 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9394 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9397 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9398 don't need the explicit prefix. */
9399 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9401 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9410 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9411 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9415 switch (i
.tm
.opcode_length
)
9422 /* Check for pseudo prefixes. */
9423 as_bad_where (insn_start_frag
->fr_file
,
9424 insn_start_frag
->fr_line
,
9425 _("pseudo prefix without instruction"));
9435 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9436 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9437 R_X86_64_GOTTPOFF relocation so that linker can safely
9438 perform IE->LE optimization. A dummy REX_OPCODE prefix
9439 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9440 relocation for GDesc -> IE/LE optimization. */
9441 if (x86_elf_abi
== X86_64_X32_ABI
9443 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9444 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9445 && i
.prefix
[REX_PREFIX
] == 0)
9446 add_prefix (REX_OPCODE
);
9449 /* The prefix bytes. */
9450 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9452 frag_opcode_byte (*q
);
9456 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9462 frag_opcode_byte (*q
);
9465 /* There should be no other prefixes for instructions
9470 /* For EVEX instructions i.vrex should become 0 after
9471 build_evex_prefix. For VEX instructions upper 16 registers
9472 aren't available, so VREX should be 0. */
9475 /* Now the VEX prefix. */
9476 if (now_seg
!= absolute_section
)
9478 p
= frag_more (i
.vex
.length
);
9479 for (j
= 0; j
< i
.vex
.length
; j
++)
9480 p
[j
] = i
.vex
.bytes
[j
];
9483 abs_section_offset
+= i
.vex
.length
;
9486 /* Now the opcode; be careful about word order here! */
9487 if (now_seg
== absolute_section
)
9488 abs_section_offset
+= i
.tm
.opcode_length
;
9489 else if (i
.tm
.opcode_length
== 1)
9491 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9495 switch (i
.tm
.opcode_length
)
9499 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9500 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9504 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9514 /* Put out high byte first: can't use md_number_to_chars! */
9515 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9516 *p
= i
.tm
.base_opcode
& 0xff;
9519 /* Now the modrm byte and sib byte (if present). */
9520 if (i
.tm
.opcode_modifier
.modrm
)
9522 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9524 | (i
.rm
.mode
<< 6));
9525 /* If i.rm.regmem == ESP (4)
9526 && i.rm.mode != (Register mode)
9528 ==> need second modrm byte. */
9529 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9531 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9532 frag_opcode_byte ((i
.sib
.base
<< 0)
9533 | (i
.sib
.index
<< 3)
9534 | (i
.sib
.scale
<< 6));
9537 if (i
.disp_operands
)
9538 output_disp (insn_start_frag
, insn_start_off
);
9541 output_imm (insn_start_frag
, insn_start_off
);
9544 * frag_now_fix () returning plain abs_section_offset when we're in the
9545 * absolute section, and abs_section_offset not getting updated as data
9546 * gets added to the frag breaks the logic below.
9548 if (now_seg
!= absolute_section
)
9550 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9552 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9556 /* NB: Don't add prefix with GOTPC relocation since
9557 output_disp() above depends on the fixed encoding
9558 length. Can't add prefix with TLS relocation since
9559 it breaks TLS linker optimization. */
9560 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9561 /* Prefix count on the current instruction. */
9562 unsigned int count
= i
.vex
.length
;
9564 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9565 /* REX byte is encoded in VEX/EVEX prefix. */
9566 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9569 /* Count prefixes for extended opcode maps. */
9571 switch (i
.tm
.opcode_length
)
9574 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9577 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9589 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9598 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9601 /* Set the maximum prefix size in BRANCH_PREFIX
9603 if (fragP
->tc_frag_data
.max_bytes
> max
)
9604 fragP
->tc_frag_data
.max_bytes
= max
;
9605 if (fragP
->tc_frag_data
.max_bytes
> count
)
9606 fragP
->tc_frag_data
.max_bytes
-= count
;
9608 fragP
->tc_frag_data
.max_bytes
= 0;
9612 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9614 unsigned int max_prefix_size
;
9615 if (align_branch_prefix_size
> max
)
9616 max_prefix_size
= max
;
9618 max_prefix_size
= align_branch_prefix_size
;
9619 if (max_prefix_size
> count
)
9620 fragP
->tc_frag_data
.max_prefix_length
9621 = max_prefix_size
- count
;
9624 /* Use existing segment prefix if possible. Use CS
9625 segment prefix in 64-bit mode. In 32-bit mode, use SS
9626 segment prefix with ESP/EBP base register and use DS
9627 segment prefix without ESP/EBP base register. */
9628 if (i
.prefix
[SEG_PREFIX
])
9629 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9630 else if (flag_code
== CODE_64BIT
)
9631 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9633 && (i
.base_reg
->reg_num
== 4
9634 || i
.base_reg
->reg_num
== 5))
9635 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9637 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9642 /* NB: Don't work with COND_JUMP86 without i386. */
9643 if (align_branch_power
9644 && now_seg
!= absolute_section
9645 && cpu_arch_flags
.bitfield
.cpui386
)
9647 /* Terminate each frag so that we can add prefix and check for
9649 frag_wane (frag_now
);
9656 pi ("" /*line*/, &i
);
9658 #endif /* DEBUG386 */
9661 /* Return the size of the displacement operand N. */
9664 disp_size (unsigned int n
)
9668 if (i
.types
[n
].bitfield
.disp64
)
9670 else if (i
.types
[n
].bitfield
.disp8
)
9672 else if (i
.types
[n
].bitfield
.disp16
)
9677 /* Return the size of the immediate operand N. */
9680 imm_size (unsigned int n
)
9683 if (i
.types
[n
].bitfield
.imm64
)
9685 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9687 else if (i
.types
[n
].bitfield
.imm16
)
9693 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9698 for (n
= 0; n
< i
.operands
; n
++)
9700 if (operand_type_check (i
.types
[n
], disp
))
9702 int size
= disp_size (n
);
9704 if (now_seg
== absolute_section
)
9705 abs_section_offset
+= size
;
9706 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9708 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9710 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9712 p
= frag_more (size
);
9713 md_number_to_chars (p
, val
, size
);
9717 enum bfd_reloc_code_real reloc_type
;
9718 int sign
= i
.types
[n
].bitfield
.disp32s
;
9719 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9722 /* We can't have 8 bit displacement here. */
9723 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9725 /* The PC relative address is computed relative
9726 to the instruction boundary, so in case immediate
9727 fields follows, we need to adjust the value. */
9728 if (pcrel
&& i
.imm_operands
)
9733 for (n1
= 0; n1
< i
.operands
; n1
++)
9734 if (operand_type_check (i
.types
[n1
], imm
))
9736 /* Only one immediate is allowed for PC
9737 relative address. */
9738 gas_assert (sz
== 0);
9740 i
.op
[n
].disps
->X_add_number
-= sz
;
9742 /* We should find the immediate. */
9743 gas_assert (sz
!= 0);
9746 p
= frag_more (size
);
9747 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9749 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9750 && (((reloc_type
== BFD_RELOC_32
9751 || reloc_type
== BFD_RELOC_X86_64_32S
9752 || (reloc_type
== BFD_RELOC_64
9754 && (i
.op
[n
].disps
->X_op
== O_symbol
9755 || (i
.op
[n
].disps
->X_op
== O_add
9756 && ((symbol_get_value_expression
9757 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9759 || reloc_type
== BFD_RELOC_32_PCREL
))
9763 reloc_type
= BFD_RELOC_386_GOTPC
;
9764 i
.has_gotpc_tls_reloc
= TRUE
;
9765 i
.op
[n
].imms
->X_add_number
+=
9766 encoding_length (insn_start_frag
, insn_start_off
, p
);
9768 else if (reloc_type
== BFD_RELOC_64
)
9769 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9771 /* Don't do the adjustment for x86-64, as there
9772 the pcrel addressing is relative to the _next_
9773 insn, and that is taken care of in other code. */
9774 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9776 else if (align_branch_power
)
9780 case BFD_RELOC_386_TLS_GD
:
9781 case BFD_RELOC_386_TLS_LDM
:
9782 case BFD_RELOC_386_TLS_IE
:
9783 case BFD_RELOC_386_TLS_IE_32
:
9784 case BFD_RELOC_386_TLS_GOTIE
:
9785 case BFD_RELOC_386_TLS_GOTDESC
:
9786 case BFD_RELOC_386_TLS_DESC_CALL
:
9787 case BFD_RELOC_X86_64_TLSGD
:
9788 case BFD_RELOC_X86_64_TLSLD
:
9789 case BFD_RELOC_X86_64_GOTTPOFF
:
9790 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9791 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9792 i
.has_gotpc_tls_reloc
= TRUE
;
9797 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9798 size
, i
.op
[n
].disps
, pcrel
,
9800 /* Check for "call/jmp *mem", "mov mem, %reg",
9801 "test %reg, mem" and "binop mem, %reg" where binop
9802 is one of adc, add, and, cmp, or, sbb, sub, xor
9803 instructions without data prefix. Always generate
9804 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9805 if (i
.prefix
[DATA_PREFIX
] == 0
9806 && (generate_relax_relocations
9809 && i
.rm
.regmem
== 5))
9811 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9812 && !is_any_vex_encoding(&i
.tm
)
9813 && ((i
.operands
== 1
9814 && i
.tm
.base_opcode
== 0xff
9815 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9817 && (i
.tm
.base_opcode
== 0x8b
9818 || i
.tm
.base_opcode
== 0x85
9819 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9823 fixP
->fx_tcbit
= i
.rex
!= 0;
9825 && (i
.base_reg
->reg_num
== RegIP
))
9826 fixP
->fx_tcbit2
= 1;
9829 fixP
->fx_tcbit2
= 1;
9837 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9842 for (n
= 0; n
< i
.operands
; n
++)
9844 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9845 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9848 if (operand_type_check (i
.types
[n
], imm
))
9850 int size
= imm_size (n
);
9852 if (now_seg
== absolute_section
)
9853 abs_section_offset
+= size
;
9854 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9858 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9860 p
= frag_more (size
);
9861 md_number_to_chars (p
, val
, size
);
9865 /* Not absolute_section.
9866 Need a 32-bit fixup (don't support 8bit
9867 non-absolute imms). Try to support other
9869 enum bfd_reloc_code_real reloc_type
;
9872 if (i
.types
[n
].bitfield
.imm32s
9873 && (i
.suffix
== QWORD_MNEM_SUFFIX
9874 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9879 p
= frag_more (size
);
9880 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9882 /* This is tough to explain. We end up with this one if we
9883 * have operands that look like
9884 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9885 * obtain the absolute address of the GOT, and it is strongly
9886 * preferable from a performance point of view to avoid using
9887 * a runtime relocation for this. The actual sequence of
9888 * instructions often look something like:
9893 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9895 * The call and pop essentially return the absolute address
9896 * of the label .L66 and store it in %ebx. The linker itself
9897 * will ultimately change the first operand of the addl so
9898 * that %ebx points to the GOT, but to keep things simple, the
9899 * .o file must have this operand set so that it generates not
9900 * the absolute address of .L66, but the absolute address of
9901 * itself. This allows the linker itself simply treat a GOTPC
9902 * relocation as asking for a pcrel offset to the GOT to be
9903 * added in, and the addend of the relocation is stored in the
9904 * operand field for the instruction itself.
9906 * Our job here is to fix the operand so that it would add
9907 * the correct offset so that %ebx would point to itself. The
9908 * thing that is tricky is that .-.L66 will point to the
9909 * beginning of the instruction, so we need to further modify
9910 * the operand so that it will point to itself. There are
9911 * other cases where you have something like:
9913 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9915 * and here no correction would be required. Internally in
9916 * the assembler we treat operands of this form as not being
9917 * pcrel since the '.' is explicitly mentioned, and I wonder
9918 * whether it would simplify matters to do it this way. Who
9919 * knows. In earlier versions of the PIC patches, the
9920 * pcrel_adjust field was used to store the correction, but
9921 * since the expression is not pcrel, I felt it would be
9922 * confusing to do it this way. */
9924 if ((reloc_type
== BFD_RELOC_32
9925 || reloc_type
== BFD_RELOC_X86_64_32S
9926 || reloc_type
== BFD_RELOC_64
)
9928 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9929 && (i
.op
[n
].imms
->X_op
== O_symbol
9930 || (i
.op
[n
].imms
->X_op
== O_add
9931 && ((symbol_get_value_expression
9932 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9936 reloc_type
= BFD_RELOC_386_GOTPC
;
9938 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9940 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9941 i
.has_gotpc_tls_reloc
= TRUE
;
9942 i
.op
[n
].imms
->X_add_number
+=
9943 encoding_length (insn_start_frag
, insn_start_off
, p
);
9945 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9946 i
.op
[n
].imms
, 0, reloc_type
);
9952 /* x86_cons_fix_new is called via the expression parsing code when a
9953 reloc is needed. We use this hook to get the correct .got reloc. */
9954 static int cons_sign
= -1;
9957 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9958 expressionS
*exp
, bfd_reloc_code_real_type r
)
9960 r
= reloc (len
, 0, cons_sign
, r
);
9963 if (exp
->X_op
== O_secrel
)
9965 exp
->X_op
= O_symbol
;
9966 r
= BFD_RELOC_32_SECREL
;
9970 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9973 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9974 purpose of the `.dc.a' internal pseudo-op. */
9977 x86_address_bytes (void)
9979 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9981 return stdoutput
->arch_info
->bits_per_address
/ 8;
9984 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9986 # define lex_got(reloc, adjust, types) NULL
9988 /* Parse operands of the form
9989 <symbol>@GOTOFF+<nnn>
9990 and similar .plt or .got references.
9992 If we find one, set up the correct relocation in RELOC and copy the
9993 input string, minus the `@GOTOFF' into a malloc'd buffer for
9994 parsing by the calling routine. Return this buffer, and if ADJUST
9995 is non-null set it to the length of the string we removed from the
9996 input line. Otherwise return NULL. */
9998 lex_got (enum bfd_reloc_code_real
*rel
,
10000 i386_operand_type
*types
)
10002 /* Some of the relocations depend on the size of what field is to
10003 be relocated. But in our callers i386_immediate and i386_displacement
10004 we don't yet know the operand size (this will be set by insn
10005 matching). Hence we record the word32 relocation here,
10006 and adjust the reloc according to the real size in reloc(). */
10007 static const struct {
10010 const enum bfd_reloc_code_real rel
[2];
10011 const i386_operand_type types64
;
10012 bfd_boolean need_GOT_symbol
;
10014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10015 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10016 BFD_RELOC_SIZE32
},
10017 OPERAND_TYPE_IMM32_64
, FALSE
},
10019 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10020 BFD_RELOC_X86_64_PLTOFF64
},
10021 OPERAND_TYPE_IMM64
, TRUE
},
10022 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10023 BFD_RELOC_X86_64_PLT32
},
10024 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10025 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10026 BFD_RELOC_X86_64_GOTPLT64
},
10027 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10028 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10029 BFD_RELOC_X86_64_GOTOFF64
},
10030 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10031 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10032 BFD_RELOC_X86_64_GOTPCREL
},
10033 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10034 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10035 BFD_RELOC_X86_64_TLSGD
},
10036 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10037 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10038 _dummy_first_bfd_reloc_code_real
},
10039 OPERAND_TYPE_NONE
, TRUE
},
10040 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10041 BFD_RELOC_X86_64_TLSLD
},
10042 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10043 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10044 BFD_RELOC_X86_64_GOTTPOFF
},
10045 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10046 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10047 BFD_RELOC_X86_64_TPOFF32
},
10048 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10049 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10050 _dummy_first_bfd_reloc_code_real
},
10051 OPERAND_TYPE_NONE
, TRUE
},
10052 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10053 BFD_RELOC_X86_64_DTPOFF32
},
10054 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10055 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10056 _dummy_first_bfd_reloc_code_real
},
10057 OPERAND_TYPE_NONE
, TRUE
},
10058 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10059 _dummy_first_bfd_reloc_code_real
},
10060 OPERAND_TYPE_NONE
, TRUE
},
10061 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10062 BFD_RELOC_X86_64_GOT32
},
10063 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10064 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10065 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10066 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10067 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10068 BFD_RELOC_X86_64_TLSDESC_CALL
},
10069 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10074 #if defined (OBJ_MAYBE_ELF)
10079 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10080 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10083 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10085 int len
= gotrel
[j
].len
;
10086 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10088 if (gotrel
[j
].rel
[object_64bit
] != 0)
10091 char *tmpbuf
, *past_reloc
;
10093 *rel
= gotrel
[j
].rel
[object_64bit
];
10097 if (flag_code
!= CODE_64BIT
)
10099 types
->bitfield
.imm32
= 1;
10100 types
->bitfield
.disp32
= 1;
10103 *types
= gotrel
[j
].types64
;
10106 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10107 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10109 /* The length of the first part of our input line. */
10110 first
= cp
- input_line_pointer
;
10112 /* The second part goes from after the reloc token until
10113 (and including) an end_of_line char or comma. */
10114 past_reloc
= cp
+ 1 + len
;
10116 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10118 second
= cp
+ 1 - past_reloc
;
10120 /* Allocate and copy string. The trailing NUL shouldn't
10121 be necessary, but be safe. */
10122 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10123 memcpy (tmpbuf
, input_line_pointer
, first
);
10124 if (second
!= 0 && *past_reloc
!= ' ')
10125 /* Replace the relocation token with ' ', so that
10126 errors like foo@GOTOFF1 will be detected. */
10127 tmpbuf
[first
++] = ' ';
10129 /* Increment length by 1 if the relocation token is
10134 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10135 tmpbuf
[first
+ second
] = '\0';
10139 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10140 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10145 /* Might be a symbol version string. Don't as_bad here. */
10154 /* Parse operands of the form
10155 <symbol>@SECREL32+<nnn>
10157 If we find one, set up the correct relocation in RELOC and copy the
10158 input string, minus the `@SECREL32' into a malloc'd buffer for
10159 parsing by the calling routine. Return this buffer, and if ADJUST
10160 is non-null set it to the length of the string we removed from the
10161 input line. Otherwise return NULL.
10163 This function is copied from the ELF version above adjusted for PE targets. */
10166 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10167 int *adjust ATTRIBUTE_UNUSED
,
10168 i386_operand_type
*types
)
10170 static const struct
10174 const enum bfd_reloc_code_real rel
[2];
10175 const i386_operand_type types64
;
10179 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10180 BFD_RELOC_32_SECREL
},
10181 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10187 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10188 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10191 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10193 int len
= gotrel
[j
].len
;
10195 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10197 if (gotrel
[j
].rel
[object_64bit
] != 0)
10200 char *tmpbuf
, *past_reloc
;
10202 *rel
= gotrel
[j
].rel
[object_64bit
];
10208 if (flag_code
!= CODE_64BIT
)
10210 types
->bitfield
.imm32
= 1;
10211 types
->bitfield
.disp32
= 1;
10214 *types
= gotrel
[j
].types64
;
10217 /* The length of the first part of our input line. */
10218 first
= cp
- input_line_pointer
;
10220 /* The second part goes from after the reloc token until
10221 (and including) an end_of_line char or comma. */
10222 past_reloc
= cp
+ 1 + len
;
10224 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10226 second
= cp
+ 1 - past_reloc
;
10228 /* Allocate and copy string. The trailing NUL shouldn't
10229 be necessary, but be safe. */
10230 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10231 memcpy (tmpbuf
, input_line_pointer
, first
);
10232 if (second
!= 0 && *past_reloc
!= ' ')
10233 /* Replace the relocation token with ' ', so that
10234 errors like foo@SECLREL321 will be detected. */
10235 tmpbuf
[first
++] = ' ';
10236 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10237 tmpbuf
[first
+ second
] = '\0';
10241 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10242 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10247 /* Might be a symbol version string. Don't as_bad here. */
10253 bfd_reloc_code_real_type
10254 x86_cons (expressionS
*exp
, int size
)
10256 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10258 intel_syntax
= -intel_syntax
;
10261 if (size
== 4 || (object_64bit
&& size
== 8))
10263 /* Handle @GOTOFF and the like in an expression. */
10265 char *gotfree_input_line
;
10268 save
= input_line_pointer
;
10269 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10270 if (gotfree_input_line
)
10271 input_line_pointer
= gotfree_input_line
;
10275 if (gotfree_input_line
)
10277 /* expression () has merrily parsed up to the end of line,
10278 or a comma - in the wrong buffer. Transfer how far
10279 input_line_pointer has moved to the right buffer. */
10280 input_line_pointer
= (save
10281 + (input_line_pointer
- gotfree_input_line
)
10283 free (gotfree_input_line
);
10284 if (exp
->X_op
== O_constant
10285 || exp
->X_op
== O_absent
10286 || exp
->X_op
== O_illegal
10287 || exp
->X_op
== O_register
10288 || exp
->X_op
== O_big
)
10290 char c
= *input_line_pointer
;
10291 *input_line_pointer
= 0;
10292 as_bad (_("missing or invalid expression `%s'"), save
);
10293 *input_line_pointer
= c
;
10295 else if ((got_reloc
== BFD_RELOC_386_PLT32
10296 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10297 && exp
->X_op
!= O_symbol
)
10299 char c
= *input_line_pointer
;
10300 *input_line_pointer
= 0;
10301 as_bad (_("invalid PLT expression `%s'"), save
);
10302 *input_line_pointer
= c
;
10309 intel_syntax
= -intel_syntax
;
10312 i386_intel_simplify (exp
);
10318 signed_cons (int size
)
10320 if (flag_code
== CODE_64BIT
)
10328 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10335 if (exp
.X_op
== O_symbol
)
10336 exp
.X_op
= O_secrel
;
10338 emit_expr (&exp
, 4);
10340 while (*input_line_pointer
++ == ',');
10342 input_line_pointer
--;
10343 demand_empty_rest_of_line ();
10347 /* Handle Vector operations. */
10350 check_VecOperations (char *op_string
, char *op_end
)
10352 const reg_entry
*mask
;
10357 && (op_end
== NULL
|| op_string
< op_end
))
10360 if (*op_string
== '{')
10364 /* Check broadcasts. */
10365 if (strncmp (op_string
, "1to", 3) == 0)
10370 goto duplicated_vec_op
;
10373 if (*op_string
== '8')
10375 else if (*op_string
== '4')
10377 else if (*op_string
== '2')
10379 else if (*op_string
== '1'
10380 && *(op_string
+1) == '6')
10387 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10392 broadcast_op
.type
= bcst_type
;
10393 broadcast_op
.operand
= this_operand
;
10394 broadcast_op
.bytes
= 0;
10395 i
.broadcast
= &broadcast_op
;
10397 /* Check masking operation. */
10398 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10400 if (mask
== &bad_reg
)
10403 /* k0 can't be used for write mask. */
10404 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10406 as_bad (_("`%s%s' can't be used for write mask"),
10407 register_prefix
, mask
->reg_name
);
10413 mask_op
.mask
= mask
;
10414 mask_op
.zeroing
= 0;
10415 mask_op
.operand
= this_operand
;
10421 goto duplicated_vec_op
;
10423 i
.mask
->mask
= mask
;
10425 /* Only "{z}" is allowed here. No need to check
10426 zeroing mask explicitly. */
10427 if (i
.mask
->operand
!= this_operand
)
10429 as_bad (_("invalid write mask `%s'"), saved
);
10434 op_string
= end_op
;
10436 /* Check zeroing-flag for masking operation. */
10437 else if (*op_string
== 'z')
10441 mask_op
.mask
= NULL
;
10442 mask_op
.zeroing
= 1;
10443 mask_op
.operand
= this_operand
;
10448 if (i
.mask
->zeroing
)
10451 as_bad (_("duplicated `%s'"), saved
);
10455 i
.mask
->zeroing
= 1;
10457 /* Only "{%k}" is allowed here. No need to check mask
10458 register explicitly. */
10459 if (i
.mask
->operand
!= this_operand
)
10461 as_bad (_("invalid zeroing-masking `%s'"),
10470 goto unknown_vec_op
;
10472 if (*op_string
!= '}')
10474 as_bad (_("missing `}' in `%s'"), saved
);
10479 /* Strip whitespace since the addition of pseudo prefixes
10480 changed how the scrubber treats '{'. */
10481 if (is_space_char (*op_string
))
10487 /* We don't know this one. */
10488 as_bad (_("unknown vector operation: `%s'"), saved
);
10492 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10494 as_bad (_("zeroing-masking only allowed with write mask"));
10502 i386_immediate (char *imm_start
)
10504 char *save_input_line_pointer
;
10505 char *gotfree_input_line
;
10508 i386_operand_type types
;
10510 operand_type_set (&types
, ~0);
10512 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10514 as_bad (_("at most %d immediate operands are allowed"),
10515 MAX_IMMEDIATE_OPERANDS
);
10519 exp
= &im_expressions
[i
.imm_operands
++];
10520 i
.op
[this_operand
].imms
= exp
;
10522 if (is_space_char (*imm_start
))
10525 save_input_line_pointer
= input_line_pointer
;
10526 input_line_pointer
= imm_start
;
10528 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10529 if (gotfree_input_line
)
10530 input_line_pointer
= gotfree_input_line
;
10532 exp_seg
= expression (exp
);
10534 SKIP_WHITESPACE ();
10536 /* Handle vector operations. */
10537 if (*input_line_pointer
== '{')
10539 input_line_pointer
= check_VecOperations (input_line_pointer
,
10541 if (input_line_pointer
== NULL
)
10545 if (*input_line_pointer
)
10546 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10548 input_line_pointer
= save_input_line_pointer
;
10549 if (gotfree_input_line
)
10551 free (gotfree_input_line
);
10553 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10554 exp
->X_op
= O_illegal
;
10557 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10561 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10562 i386_operand_type types
, const char *imm_start
)
10564 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10567 as_bad (_("missing or invalid immediate expression `%s'"),
10571 else if (exp
->X_op
== O_constant
)
10573 /* Size it properly later. */
10574 i
.types
[this_operand
].bitfield
.imm64
= 1;
10575 /* If not 64bit, sign extend val. */
10576 if (flag_code
!= CODE_64BIT
10577 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10579 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10581 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10582 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10583 && exp_seg
!= absolute_section
10584 && exp_seg
!= text_section
10585 && exp_seg
!= data_section
10586 && exp_seg
!= bss_section
10587 && exp_seg
!= undefined_section
10588 && !bfd_is_com_section (exp_seg
))
10590 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10594 else if (!intel_syntax
&& exp_seg
== reg_section
)
10597 as_bad (_("illegal immediate register operand %s"), imm_start
);
10602 /* This is an address. The size of the address will be
10603 determined later, depending on destination register,
10604 suffix, or the default for the section. */
10605 i
.types
[this_operand
].bitfield
.imm8
= 1;
10606 i
.types
[this_operand
].bitfield
.imm16
= 1;
10607 i
.types
[this_operand
].bitfield
.imm32
= 1;
10608 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10609 i
.types
[this_operand
].bitfield
.imm64
= 1;
10610 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10618 i386_scale (char *scale
)
10621 char *save
= input_line_pointer
;
10623 input_line_pointer
= scale
;
10624 val
= get_absolute_expression ();
10629 i
.log2_scale_factor
= 0;
10632 i
.log2_scale_factor
= 1;
10635 i
.log2_scale_factor
= 2;
10638 i
.log2_scale_factor
= 3;
10642 char sep
= *input_line_pointer
;
10644 *input_line_pointer
= '\0';
10645 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10647 *input_line_pointer
= sep
;
10648 input_line_pointer
= save
;
10652 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10654 as_warn (_("scale factor of %d without an index register"),
10655 1 << i
.log2_scale_factor
);
10656 i
.log2_scale_factor
= 0;
10658 scale
= input_line_pointer
;
10659 input_line_pointer
= save
;
10664 i386_displacement (char *disp_start
, char *disp_end
)
10668 char *save_input_line_pointer
;
10669 char *gotfree_input_line
;
10671 i386_operand_type bigdisp
, types
= anydisp
;
10674 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10676 as_bad (_("at most %d displacement operands are allowed"),
10677 MAX_MEMORY_OPERANDS
);
10681 operand_type_set (&bigdisp
, 0);
10683 || i
.types
[this_operand
].bitfield
.baseindex
10684 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10685 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10687 i386_addressing_mode ();
10688 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10689 if (flag_code
== CODE_64BIT
)
10693 bigdisp
.bitfield
.disp32s
= 1;
10694 bigdisp
.bitfield
.disp64
= 1;
10697 bigdisp
.bitfield
.disp32
= 1;
10699 else if ((flag_code
== CODE_16BIT
) ^ override
)
10700 bigdisp
.bitfield
.disp16
= 1;
10702 bigdisp
.bitfield
.disp32
= 1;
10706 /* For PC-relative branches, the width of the displacement may be
10707 dependent upon data size, but is never dependent upon address size.
10708 Also make sure to not unintentionally match against a non-PC-relative
10709 branch template. */
10710 static templates aux_templates
;
10711 const insn_template
*t
= current_templates
->start
;
10712 bfd_boolean has_intel64
= FALSE
;
10714 aux_templates
.start
= t
;
10715 while (++t
< current_templates
->end
)
10717 if (t
->opcode_modifier
.jump
10718 != current_templates
->start
->opcode_modifier
.jump
)
10720 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10721 has_intel64
= TRUE
;
10723 if (t
< current_templates
->end
)
10725 aux_templates
.end
= t
;
10726 current_templates
= &aux_templates
;
10729 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10730 if (flag_code
== CODE_64BIT
)
10732 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10733 && (!intel64
|| !has_intel64
))
10734 bigdisp
.bitfield
.disp16
= 1;
10736 bigdisp
.bitfield
.disp32s
= 1;
10741 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10743 : LONG_MNEM_SUFFIX
));
10744 bigdisp
.bitfield
.disp32
= 1;
10745 if ((flag_code
== CODE_16BIT
) ^ override
)
10747 bigdisp
.bitfield
.disp32
= 0;
10748 bigdisp
.bitfield
.disp16
= 1;
10752 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10755 exp
= &disp_expressions
[i
.disp_operands
];
10756 i
.op
[this_operand
].disps
= exp
;
10758 save_input_line_pointer
= input_line_pointer
;
10759 input_line_pointer
= disp_start
;
10760 END_STRING_AND_SAVE (disp_end
);
10762 #ifndef GCC_ASM_O_HACK
10763 #define GCC_ASM_O_HACK 0
10766 END_STRING_AND_SAVE (disp_end
+ 1);
10767 if (i
.types
[this_operand
].bitfield
.baseIndex
10768 && displacement_string_end
[-1] == '+')
10770 /* This hack is to avoid a warning when using the "o"
10771 constraint within gcc asm statements.
10774 #define _set_tssldt_desc(n,addr,limit,type) \
10775 __asm__ __volatile__ ( \
10776 "movw %w2,%0\n\t" \
10777 "movw %w1,2+%0\n\t" \
10778 "rorl $16,%1\n\t" \
10779 "movb %b1,4+%0\n\t" \
10780 "movb %4,5+%0\n\t" \
10781 "movb $0,6+%0\n\t" \
10782 "movb %h1,7+%0\n\t" \
10784 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10786 This works great except that the output assembler ends
10787 up looking a bit weird if it turns out that there is
10788 no offset. You end up producing code that looks like:
10801 So here we provide the missing zero. */
10803 *displacement_string_end
= '0';
10806 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10807 if (gotfree_input_line
)
10808 input_line_pointer
= gotfree_input_line
;
10810 exp_seg
= expression (exp
);
10812 SKIP_WHITESPACE ();
10813 if (*input_line_pointer
)
10814 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10816 RESTORE_END_STRING (disp_end
+ 1);
10818 input_line_pointer
= save_input_line_pointer
;
10819 if (gotfree_input_line
)
10821 free (gotfree_input_line
);
10823 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10824 exp
->X_op
= O_illegal
;
10827 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10829 RESTORE_END_STRING (disp_end
);
10835 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10836 i386_operand_type types
, const char *disp_start
)
10838 i386_operand_type bigdisp
;
10841 /* We do this to make sure that the section symbol is in
10842 the symbol table. We will ultimately change the relocation
10843 to be relative to the beginning of the section. */
10844 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10845 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10846 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10848 if (exp
->X_op
!= O_symbol
)
10851 if (S_IS_LOCAL (exp
->X_add_symbol
)
10852 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10853 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10854 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10855 exp
->X_op
= O_subtract
;
10856 exp
->X_op_symbol
= GOT_symbol
;
10857 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10858 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10859 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10860 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10862 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10865 else if (exp
->X_op
== O_absent
10866 || exp
->X_op
== O_illegal
10867 || exp
->X_op
== O_big
)
10870 as_bad (_("missing or invalid displacement expression `%s'"),
10875 else if (flag_code
== CODE_64BIT
10876 && !i
.prefix
[ADDR_PREFIX
]
10877 && exp
->X_op
== O_constant
)
10879 /* Since displacement is signed extended to 64bit, don't allow
10880 disp32 and turn off disp32s if they are out of range. */
10881 i
.types
[this_operand
].bitfield
.disp32
= 0;
10882 if (!fits_in_signed_long (exp
->X_add_number
))
10884 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10885 if (i
.types
[this_operand
].bitfield
.baseindex
)
10887 as_bad (_("0x%lx out range of signed 32bit displacement"),
10888 (long) exp
->X_add_number
);
10894 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10895 else if (exp
->X_op
!= O_constant
10896 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10897 && exp_seg
!= absolute_section
10898 && exp_seg
!= text_section
10899 && exp_seg
!= data_section
10900 && exp_seg
!= bss_section
10901 && exp_seg
!= undefined_section
10902 && !bfd_is_com_section (exp_seg
))
10904 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10909 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10910 /* Constants get taken care of by optimize_disp(). */
10911 && exp
->X_op
!= O_constant
)
10912 i
.types
[this_operand
].bitfield
.disp8
= 1;
10914 /* Check if this is a displacement only operand. */
10915 bigdisp
= i
.types
[this_operand
];
10916 bigdisp
.bitfield
.disp8
= 0;
10917 bigdisp
.bitfield
.disp16
= 0;
10918 bigdisp
.bitfield
.disp32
= 0;
10919 bigdisp
.bitfield
.disp32s
= 0;
10920 bigdisp
.bitfield
.disp64
= 0;
10921 if (operand_type_all_zero (&bigdisp
))
10922 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10928 /* Return the active addressing mode, taking address override and
10929 registers forming the address into consideration. Update the
10930 address override prefix if necessary. */
10932 static enum flag_code
10933 i386_addressing_mode (void)
10935 enum flag_code addr_mode
;
10937 if (i
.prefix
[ADDR_PREFIX
])
10938 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10939 else if (flag_code
== CODE_16BIT
10940 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10941 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10942 from md_assemble() by "is not a valid base/index expression"
10943 when there is a base and/or index. */
10944 && !i
.types
[this_operand
].bitfield
.baseindex
)
10946 /* MPX insn memory operands with neither base nor index must be forced
10947 to use 32-bit addressing in 16-bit mode. */
10948 addr_mode
= CODE_32BIT
;
10949 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10951 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10952 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10956 addr_mode
= flag_code
;
10958 #if INFER_ADDR_PREFIX
10959 if (i
.mem_operands
== 0)
10961 /* Infer address prefix from the first memory operand. */
10962 const reg_entry
*addr_reg
= i
.base_reg
;
10964 if (addr_reg
== NULL
)
10965 addr_reg
= i
.index_reg
;
10969 if (addr_reg
->reg_type
.bitfield
.dword
)
10970 addr_mode
= CODE_32BIT
;
10971 else if (flag_code
!= CODE_64BIT
10972 && addr_reg
->reg_type
.bitfield
.word
)
10973 addr_mode
= CODE_16BIT
;
10975 if (addr_mode
!= flag_code
)
10977 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10979 /* Change the size of any displacement too. At most one
10980 of Disp16 or Disp32 is set.
10981 FIXME. There doesn't seem to be any real need for
10982 separate Disp16 and Disp32 flags. The same goes for
10983 Imm16 and Imm32. Removing them would probably clean
10984 up the code quite a lot. */
10985 if (flag_code
!= CODE_64BIT
10986 && (i
.types
[this_operand
].bitfield
.disp16
10987 || i
.types
[this_operand
].bitfield
.disp32
))
10988 i
.types
[this_operand
]
10989 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10999 /* Make sure the memory operand we've been dealt is valid.
11000 Return 1 on success, 0 on a failure. */
11003 i386_index_check (const char *operand_string
)
11005 const char *kind
= "base/index";
11006 enum flag_code addr_mode
= i386_addressing_mode ();
11007 const insn_template
*t
= current_templates
->start
;
11009 if (t
->opcode_modifier
.isstring
11010 && !t
->cpu_flags
.bitfield
.cpupadlock
11011 && (current_templates
->end
[-1].opcode_modifier
.isstring
11012 || i
.mem_operands
))
11014 /* Memory operands of string insns are special in that they only allow
11015 a single register (rDI, rSI, or rBX) as their memory address. */
11016 const reg_entry
*expected_reg
;
11017 static const char *di_si
[][2] =
11023 static const char *bx
[] = { "ebx", "bx", "rbx" };
11025 kind
= "string address";
11027 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11029 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11030 - IS_STRING_ES_OP0
;
11033 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11034 || ((!i
.mem_operands
!= !intel_syntax
)
11035 && current_templates
->end
[-1].operand_types
[1]
11036 .bitfield
.baseindex
))
11039 = (const reg_entry
*) str_hash_find (reg_hash
,
11040 di_si
[addr_mode
][op
== es_op
]);
11044 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11046 if (i
.base_reg
!= expected_reg
11048 || operand_type_check (i
.types
[this_operand
], disp
))
11050 /* The second memory operand must have the same size as
11054 && !((addr_mode
== CODE_64BIT
11055 && i
.base_reg
->reg_type
.bitfield
.qword
)
11056 || (addr_mode
== CODE_32BIT
11057 ? i
.base_reg
->reg_type
.bitfield
.dword
11058 : i
.base_reg
->reg_type
.bitfield
.word
)))
11061 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11063 intel_syntax
? '[' : '(',
11065 expected_reg
->reg_name
,
11066 intel_syntax
? ']' : ')');
11073 as_bad (_("`%s' is not a valid %s expression"),
11074 operand_string
, kind
);
11079 if (addr_mode
!= CODE_16BIT
)
11081 /* 32-bit/64-bit checks. */
11082 if (i
.disp_encoding
== disp_encoding_16bit
)
11085 as_bad (_("invalid `%s' prefix"),
11086 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11091 && ((addr_mode
== CODE_64BIT
11092 ? !i
.base_reg
->reg_type
.bitfield
.qword
11093 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11094 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11095 || i
.base_reg
->reg_num
== RegIZ
))
11097 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11098 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11099 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11100 && ((addr_mode
== CODE_64BIT
11101 ? !i
.index_reg
->reg_type
.bitfield
.qword
11102 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11103 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11106 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11107 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11108 && t
->base_opcode
== 0x0f1b)
11109 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11110 && (t
->base_opcode
& ~1) == 0x0f1a)
11111 || t
->opcode_modifier
.sib
== SIBMEM
)
11113 /* They cannot use RIP-relative addressing. */
11114 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11116 as_bad (_("`%s' cannot be used here"), operand_string
);
11120 /* bndldx and bndstx ignore their scale factor. */
11121 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11122 && (t
->base_opcode
& ~1) == 0x0f1a
11123 && i
.log2_scale_factor
)
11124 as_warn (_("register scaling is being ignored here"));
11129 /* 16-bit checks. */
11130 if (i
.disp_encoding
== disp_encoding_32bit
)
11134 && (!i
.base_reg
->reg_type
.bitfield
.word
11135 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11137 && (!i
.index_reg
->reg_type
.bitfield
.word
11138 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11140 && i
.base_reg
->reg_num
< 6
11141 && i
.index_reg
->reg_num
>= 6
11142 && i
.log2_scale_factor
== 0))))
11149 /* Handle vector immediates. */
11152 RC_SAE_immediate (const char *imm_start
)
11154 unsigned int match_found
, j
;
11155 const char *pstr
= imm_start
;
11163 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11165 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11169 rc_op
.type
= RC_NamesTable
[j
].type
;
11170 rc_op
.operand
= this_operand
;
11171 i
.rounding
= &rc_op
;
11175 as_bad (_("duplicated `%s'"), imm_start
);
11178 pstr
+= RC_NamesTable
[j
].len
;
11186 if (*pstr
++ != '}')
11188 as_bad (_("Missing '}': '%s'"), imm_start
);
11191 /* RC/SAE immediate string should contain nothing more. */;
11194 as_bad (_("Junk after '}': '%s'"), imm_start
);
11198 exp
= &im_expressions
[i
.imm_operands
++];
11199 i
.op
[this_operand
].imms
= exp
;
11201 exp
->X_op
= O_constant
;
11202 exp
->X_add_number
= 0;
11203 exp
->X_add_symbol
= (symbolS
*) 0;
11204 exp
->X_op_symbol
= (symbolS
*) 0;
11206 i
.types
[this_operand
].bitfield
.imm8
= 1;
11210 /* Only string instructions can have a second memory operand, so
11211 reduce current_templates to just those if it contains any. */
11213 maybe_adjust_templates (void)
11215 const insn_template
*t
;
11217 gas_assert (i
.mem_operands
== 1);
11219 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11220 if (t
->opcode_modifier
.isstring
)
11223 if (t
< current_templates
->end
)
11225 static templates aux_templates
;
11226 bfd_boolean recheck
;
11228 aux_templates
.start
= t
;
11229 for (; t
< current_templates
->end
; ++t
)
11230 if (!t
->opcode_modifier
.isstring
)
11232 aux_templates
.end
= t
;
11234 /* Determine whether to re-check the first memory operand. */
11235 recheck
= (aux_templates
.start
!= current_templates
->start
11236 || t
!= current_templates
->end
);
11238 current_templates
= &aux_templates
;
11242 i
.mem_operands
= 0;
11243 if (i
.memop1_string
!= NULL
11244 && i386_index_check (i
.memop1_string
) == 0)
11246 i
.mem_operands
= 1;
11253 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11257 i386_att_operand (char *operand_string
)
11259 const reg_entry
*r
;
11261 char *op_string
= operand_string
;
11263 if (is_space_char (*op_string
))
11266 /* We check for an absolute prefix (differentiating,
11267 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11268 if (*op_string
== ABSOLUTE_PREFIX
)
11271 if (is_space_char (*op_string
))
11273 i
.jumpabsolute
= TRUE
;
11276 /* Check if operand is a register. */
11277 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11279 i386_operand_type temp
;
11284 /* Check for a segment override by searching for ':' after a
11285 segment register. */
11286 op_string
= end_op
;
11287 if (is_space_char (*op_string
))
11289 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11291 switch (r
->reg_num
)
11294 i
.seg
[i
.mem_operands
] = &es
;
11297 i
.seg
[i
.mem_operands
] = &cs
;
11300 i
.seg
[i
.mem_operands
] = &ss
;
11303 i
.seg
[i
.mem_operands
] = &ds
;
11306 i
.seg
[i
.mem_operands
] = &fs
;
11309 i
.seg
[i
.mem_operands
] = &gs
;
11313 /* Skip the ':' and whitespace. */
11315 if (is_space_char (*op_string
))
11318 if (!is_digit_char (*op_string
)
11319 && !is_identifier_char (*op_string
)
11320 && *op_string
!= '('
11321 && *op_string
!= ABSOLUTE_PREFIX
)
11323 as_bad (_("bad memory operand `%s'"), op_string
);
11326 /* Handle case of %es:*foo. */
11327 if (*op_string
== ABSOLUTE_PREFIX
)
11330 if (is_space_char (*op_string
))
11332 i
.jumpabsolute
= TRUE
;
11334 goto do_memory_reference
;
11337 /* Handle vector operations. */
11338 if (*op_string
== '{')
11340 op_string
= check_VecOperations (op_string
, NULL
);
11341 if (op_string
== NULL
)
11347 as_bad (_("junk `%s' after register"), op_string
);
11350 temp
= r
->reg_type
;
11351 temp
.bitfield
.baseindex
= 0;
11352 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11354 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11355 i
.op
[this_operand
].regs
= r
;
11358 else if (*op_string
== REGISTER_PREFIX
)
11360 as_bad (_("bad register name `%s'"), op_string
);
11363 else if (*op_string
== IMMEDIATE_PREFIX
)
11366 if (i
.jumpabsolute
)
11368 as_bad (_("immediate operand illegal with absolute jump"));
11371 if (!i386_immediate (op_string
))
11374 else if (RC_SAE_immediate (operand_string
))
11376 /* If it is a RC or SAE immediate, do nothing. */
11379 else if (is_digit_char (*op_string
)
11380 || is_identifier_char (*op_string
)
11381 || *op_string
== '"'
11382 || *op_string
== '(')
11384 /* This is a memory reference of some sort. */
11387 /* Start and end of displacement string expression (if found). */
11388 char *displacement_string_start
;
11389 char *displacement_string_end
;
11392 do_memory_reference
:
11393 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11395 if ((i
.mem_operands
== 1
11396 && !current_templates
->start
->opcode_modifier
.isstring
)
11397 || i
.mem_operands
== 2)
11399 as_bad (_("too many memory references for `%s'"),
11400 current_templates
->start
->name
);
11404 /* Check for base index form. We detect the base index form by
11405 looking for an ')' at the end of the operand, searching
11406 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11408 base_string
= op_string
+ strlen (op_string
);
11410 /* Handle vector operations. */
11411 vop_start
= strchr (op_string
, '{');
11412 if (vop_start
&& vop_start
< base_string
)
11414 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11416 base_string
= vop_start
;
11420 if (is_space_char (*base_string
))
11423 /* If we only have a displacement, set-up for it to be parsed later. */
11424 displacement_string_start
= op_string
;
11425 displacement_string_end
= base_string
+ 1;
11427 if (*base_string
== ')')
11430 unsigned int parens_balanced
= 1;
11431 /* We've already checked that the number of left & right ()'s are
11432 equal, so this loop will not be infinite. */
11436 if (*base_string
== ')')
11438 if (*base_string
== '(')
11441 while (parens_balanced
);
11443 temp_string
= base_string
;
11445 /* Skip past '(' and whitespace. */
11447 if (is_space_char (*base_string
))
11450 if (*base_string
== ','
11451 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11454 displacement_string_end
= temp_string
;
11456 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11460 if (i
.base_reg
== &bad_reg
)
11462 base_string
= end_op
;
11463 if (is_space_char (*base_string
))
11467 /* There may be an index reg or scale factor here. */
11468 if (*base_string
== ',')
11471 if (is_space_char (*base_string
))
11474 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11477 if (i
.index_reg
== &bad_reg
)
11479 base_string
= end_op
;
11480 if (is_space_char (*base_string
))
11482 if (*base_string
== ',')
11485 if (is_space_char (*base_string
))
11488 else if (*base_string
!= ')')
11490 as_bad (_("expecting `,' or `)' "
11491 "after index register in `%s'"),
11496 else if (*base_string
== REGISTER_PREFIX
)
11498 end_op
= strchr (base_string
, ',');
11501 as_bad (_("bad register name `%s'"), base_string
);
11505 /* Check for scale factor. */
11506 if (*base_string
!= ')')
11508 char *end_scale
= i386_scale (base_string
);
11513 base_string
= end_scale
;
11514 if (is_space_char (*base_string
))
11516 if (*base_string
!= ')')
11518 as_bad (_("expecting `)' "
11519 "after scale factor in `%s'"),
11524 else if (!i
.index_reg
)
11526 as_bad (_("expecting index register or scale factor "
11527 "after `,'; got '%c'"),
11532 else if (*base_string
!= ')')
11534 as_bad (_("expecting `,' or `)' "
11535 "after base register in `%s'"),
11540 else if (*base_string
== REGISTER_PREFIX
)
11542 end_op
= strchr (base_string
, ',');
11545 as_bad (_("bad register name `%s'"), base_string
);
11550 /* If there's an expression beginning the operand, parse it,
11551 assuming displacement_string_start and
11552 displacement_string_end are meaningful. */
11553 if (displacement_string_start
!= displacement_string_end
)
11555 if (!i386_displacement (displacement_string_start
,
11556 displacement_string_end
))
11560 /* Special case for (%dx) while doing input/output op. */
11562 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11563 && i
.base_reg
->reg_type
.bitfield
.word
11564 && i
.index_reg
== 0
11565 && i
.log2_scale_factor
== 0
11566 && i
.seg
[i
.mem_operands
] == 0
11567 && !operand_type_check (i
.types
[this_operand
], disp
))
11569 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11573 if (i386_index_check (operand_string
) == 0)
11575 i
.flags
[this_operand
] |= Operand_Mem
;
11576 if (i
.mem_operands
== 0)
11577 i
.memop1_string
= xstrdup (operand_string
);
11582 /* It's not a memory operand; argh! */
11583 as_bad (_("invalid char %s beginning operand %d `%s'"),
11584 output_invalid (*op_string
),
11589 return 1; /* Normal return. */
11592 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11593 that an rs_machine_dependent frag may reach. */
11596 i386_frag_max_var (fragS
*frag
)
11598 /* The only relaxable frags are for jumps.
11599 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11600 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11601 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11606 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11608 /* STT_GNU_IFUNC symbol must go through PLT. */
11609 if ((symbol_get_bfdsym (fr_symbol
)->flags
11610 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11613 if (!S_IS_EXTERNAL (fr_symbol
))
11614 /* Symbol may be weak or local. */
11615 return !S_IS_WEAK (fr_symbol
);
11617 /* Global symbols with non-default visibility can't be preempted. */
11618 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11621 if (fr_var
!= NO_RELOC
)
11622 switch ((enum bfd_reloc_code_real
) fr_var
)
11624 case BFD_RELOC_386_PLT32
:
11625 case BFD_RELOC_X86_64_PLT32
:
11626 /* Symbol with PLT relocation may be preempted. */
11632 /* Global symbols with default visibility in a shared library may be
11633 preempted by another definition. */
11638 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11639 Note also work for Skylake and Cascadelake.
11640 ---------------------------------------------------------------------
11641 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11642 | ------ | ----------- | ------- | -------- |
11644 | Jno | N | N | Y |
11645 | Jc/Jb | Y | N | Y |
11646 | Jae/Jnb | Y | N | Y |
11647 | Je/Jz | Y | Y | Y |
11648 | Jne/Jnz | Y | Y | Y |
11649 | Jna/Jbe | Y | N | Y |
11650 | Ja/Jnbe | Y | N | Y |
11652 | Jns | N | N | Y |
11653 | Jp/Jpe | N | N | Y |
11654 | Jnp/Jpo | N | N | Y |
11655 | Jl/Jnge | Y | Y | Y |
11656 | Jge/Jnl | Y | Y | Y |
11657 | Jle/Jng | Y | Y | Y |
11658 | Jg/Jnle | Y | Y | Y |
11659 --------------------------------------------------------------------- */
11661 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11663 if (mf_cmp
== mf_cmp_alu_cmp
)
11664 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11665 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11666 if (mf_cmp
== mf_cmp_incdec
)
11667 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11668 || mf_jcc
== mf_jcc_jle
);
11669 if (mf_cmp
== mf_cmp_test_and
)
11674 /* Return the next non-empty frag. */
11677 i386_next_non_empty_frag (fragS
*fragP
)
11679 /* There may be a frag with a ".fill 0" when there is no room in
11680 the current frag for frag_grow in output_insn. */
11681 for (fragP
= fragP
->fr_next
;
11683 && fragP
->fr_type
== rs_fill
11684 && fragP
->fr_fix
== 0);
11685 fragP
= fragP
->fr_next
)
11690 /* Return the next jcc frag after BRANCH_PADDING. */
11693 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11695 fragS
*branch_fragP
;
11699 if (pad_fragP
->fr_type
== rs_machine_dependent
11700 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11701 == BRANCH_PADDING
))
11703 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11704 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11706 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11707 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11708 pad_fragP
->tc_frag_data
.mf_type
))
11709 return branch_fragP
;
11715 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11718 i386_classify_machine_dependent_frag (fragS
*fragP
)
11722 fragS
*branch_fragP
;
11724 unsigned int max_prefix_length
;
11726 if (fragP
->tc_frag_data
.classified
)
11729 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11730 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11731 for (next_fragP
= fragP
;
11732 next_fragP
!= NULL
;
11733 next_fragP
= next_fragP
->fr_next
)
11735 next_fragP
->tc_frag_data
.classified
= 1;
11736 if (next_fragP
->fr_type
== rs_machine_dependent
)
11737 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11739 case BRANCH_PADDING
:
11740 /* The BRANCH_PADDING frag must be followed by a branch
11742 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11743 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11745 case FUSED_JCC_PADDING
:
11746 /* Check if this is a fused jcc:
11748 CMP like instruction
11752 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11753 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11754 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11757 /* The BRANCH_PADDING frag is merged with the
11758 FUSED_JCC_PADDING frag. */
11759 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11760 /* CMP like instruction size. */
11761 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11762 frag_wane (pad_fragP
);
11763 /* Skip to branch_fragP. */
11764 next_fragP
= branch_fragP
;
11766 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11768 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11770 next_fragP
->fr_subtype
11771 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11772 next_fragP
->tc_frag_data
.max_bytes
11773 = next_fragP
->tc_frag_data
.max_prefix_length
;
11774 /* This will be updated in the BRANCH_PREFIX scan. */
11775 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11778 frag_wane (next_fragP
);
11783 /* Stop if there is no BRANCH_PREFIX. */
11784 if (!align_branch_prefix_size
)
11787 /* Scan for BRANCH_PREFIX. */
11788 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11790 if (fragP
->fr_type
!= rs_machine_dependent
11791 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11795 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11796 COND_JUMP_PREFIX. */
11797 max_prefix_length
= 0;
11798 for (next_fragP
= fragP
;
11799 next_fragP
!= NULL
;
11800 next_fragP
= next_fragP
->fr_next
)
11802 if (next_fragP
->fr_type
== rs_fill
)
11803 /* Skip rs_fill frags. */
11805 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11806 /* Stop for all other frags. */
11809 /* rs_machine_dependent frags. */
11810 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11813 /* Count BRANCH_PREFIX frags. */
11814 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11816 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11817 frag_wane (next_fragP
);
11821 += next_fragP
->tc_frag_data
.max_bytes
;
11823 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11825 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11826 == FUSED_JCC_PADDING
))
11828 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11829 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11833 /* Stop for other rs_machine_dependent frags. */
11837 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11839 /* Skip to the next frag. */
11840 fragP
= next_fragP
;
11844 /* Compute padding size for
11847 CMP like instruction
11849 COND_JUMP/UNCOND_JUMP
11854 COND_JUMP/UNCOND_JUMP
11858 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11860 unsigned int offset
, size
, padding_size
;
11861 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11863 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11865 address
= fragP
->fr_address
;
11866 address
+= fragP
->fr_fix
;
11868 /* CMP like instrunction size. */
11869 size
= fragP
->tc_frag_data
.cmp_size
;
11871 /* The base size of the branch frag. */
11872 size
+= branch_fragP
->fr_fix
;
11874 /* Add opcode and displacement bytes for the rs_machine_dependent
11876 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11877 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11879 /* Check if branch is within boundary and doesn't end at the last
11881 offset
= address
& ((1U << align_branch_power
) - 1);
11882 if ((offset
+ size
) >= (1U << align_branch_power
))
11883 /* Padding needed to avoid crossing boundary. */
11884 padding_size
= (1U << align_branch_power
) - offset
;
11886 /* No padding needed. */
11889 /* The return value may be saved in tc_frag_data.length which is
11891 if (!fits_in_unsigned_byte (padding_size
))
11894 return padding_size
;
11897 /* i386_generic_table_relax_frag()
11899 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11900 grow/shrink padding to align branch frags. Hand others to
11904 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11906 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11907 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11909 long padding_size
= i386_branch_padding_size (fragP
, 0);
11910 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11912 /* When the BRANCH_PREFIX frag is used, the computed address
11913 must match the actual address and there should be no padding. */
11914 if (fragP
->tc_frag_data
.padding_address
11915 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11919 /* Update the padding size. */
11921 fragP
->tc_frag_data
.length
= padding_size
;
11925 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11927 fragS
*padding_fragP
, *next_fragP
;
11928 long padding_size
, left_size
, last_size
;
11930 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11931 if (!padding_fragP
)
11932 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11933 return (fragP
->tc_frag_data
.length
11934 - fragP
->tc_frag_data
.last_length
);
11936 /* Compute the relative address of the padding frag in the very
11937 first time where the BRANCH_PREFIX frag sizes are zero. */
11938 if (!fragP
->tc_frag_data
.padding_address
)
11939 fragP
->tc_frag_data
.padding_address
11940 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11942 /* First update the last length from the previous interation. */
11943 left_size
= fragP
->tc_frag_data
.prefix_length
;
11944 for (next_fragP
= fragP
;
11945 next_fragP
!= padding_fragP
;
11946 next_fragP
= next_fragP
->fr_next
)
11947 if (next_fragP
->fr_type
== rs_machine_dependent
11948 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11953 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11957 if (max
> left_size
)
11962 next_fragP
->tc_frag_data
.last_length
= size
;
11966 next_fragP
->tc_frag_data
.last_length
= 0;
11969 /* Check the padding size for the padding frag. */
11970 padding_size
= i386_branch_padding_size
11971 (padding_fragP
, (fragP
->fr_address
11972 + fragP
->tc_frag_data
.padding_address
));
11974 last_size
= fragP
->tc_frag_data
.prefix_length
;
11975 /* Check if there is change from the last interation. */
11976 if (padding_size
== last_size
)
11978 /* Update the expected address of the padding frag. */
11979 padding_fragP
->tc_frag_data
.padding_address
11980 = (fragP
->fr_address
+ padding_size
11981 + fragP
->tc_frag_data
.padding_address
);
11985 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11987 /* No padding if there is no sufficient room. Clear the
11988 expected address of the padding frag. */
11989 padding_fragP
->tc_frag_data
.padding_address
= 0;
11993 /* Store the expected address of the padding frag. */
11994 padding_fragP
->tc_frag_data
.padding_address
11995 = (fragP
->fr_address
+ padding_size
11996 + fragP
->tc_frag_data
.padding_address
);
11998 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12000 /* Update the length for the current interation. */
12001 left_size
= padding_size
;
12002 for (next_fragP
= fragP
;
12003 next_fragP
!= padding_fragP
;
12004 next_fragP
= next_fragP
->fr_next
)
12005 if (next_fragP
->fr_type
== rs_machine_dependent
12006 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12011 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12015 if (max
> left_size
)
12020 next_fragP
->tc_frag_data
.length
= size
;
12024 next_fragP
->tc_frag_data
.length
= 0;
12027 return (fragP
->tc_frag_data
.length
12028 - fragP
->tc_frag_data
.last_length
);
12030 return relax_frag (segment
, fragP
, stretch
);
12033 /* md_estimate_size_before_relax()
12035 Called just before relax() for rs_machine_dependent frags. The x86
12036 assembler uses these frags to handle variable size jump
12039 Any symbol that is now undefined will not become defined.
12040 Return the correct fr_subtype in the frag.
12041 Return the initial "guess for variable size of frag" to caller.
12042 The guess is actually the growth beyond the fixed part. Whatever
12043 we do to grow the fixed or variable part contributes to our
12047 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12049 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12050 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12051 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12053 i386_classify_machine_dependent_frag (fragP
);
12054 return fragP
->tc_frag_data
.length
;
12057 /* We've already got fragP->fr_subtype right; all we have to do is
12058 check for un-relaxable symbols. On an ELF system, we can't relax
12059 an externally visible symbol, because it may be overridden by a
12061 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12064 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12067 #if defined (OBJ_COFF) && defined (TE_PE)
12068 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12069 && S_IS_WEAK (fragP
->fr_symbol
))
12073 /* Symbol is undefined in this segment, or we need to keep a
12074 reloc so that weak symbols can be overridden. */
12075 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12076 enum bfd_reloc_code_real reloc_type
;
12077 unsigned char *opcode
;
12080 if (fragP
->fr_var
!= NO_RELOC
)
12081 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12082 else if (size
== 2)
12083 reloc_type
= BFD_RELOC_16_PCREL
;
12084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12085 else if (need_plt32_p (fragP
->fr_symbol
))
12086 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12089 reloc_type
= BFD_RELOC_32_PCREL
;
12091 old_fr_fix
= fragP
->fr_fix
;
12092 opcode
= (unsigned char *) fragP
->fr_opcode
;
12094 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12097 /* Make jmp (0xeb) a (d)word displacement jump. */
12099 fragP
->fr_fix
+= size
;
12100 fix_new (fragP
, old_fr_fix
, size
,
12102 fragP
->fr_offset
, 1,
12108 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12110 /* Negate the condition, and branch past an
12111 unconditional jump. */
12114 /* Insert an unconditional jump. */
12116 /* We added two extra opcode bytes, and have a two byte
12118 fragP
->fr_fix
+= 2 + 2;
12119 fix_new (fragP
, old_fr_fix
+ 2, 2,
12121 fragP
->fr_offset
, 1,
12125 /* Fall through. */
12128 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12132 fragP
->fr_fix
+= 1;
12133 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12135 fragP
->fr_offset
, 1,
12136 BFD_RELOC_8_PCREL
);
12137 fixP
->fx_signed
= 1;
12141 /* This changes the byte-displacement jump 0x7N
12142 to the (d)word-displacement jump 0x0f,0x8N. */
12143 opcode
[1] = opcode
[0] + 0x10;
12144 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12145 /* We've added an opcode byte. */
12146 fragP
->fr_fix
+= 1 + size
;
12147 fix_new (fragP
, old_fr_fix
+ 1, size
,
12149 fragP
->fr_offset
, 1,
12154 BAD_CASE (fragP
->fr_subtype
);
12158 return fragP
->fr_fix
- old_fr_fix
;
12161 /* Guess size depending on current relax state. Initially the relax
12162 state will correspond to a short jump and we return 1, because
12163 the variable part of the frag (the branch offset) is one byte
12164 long. However, we can relax a section more than once and in that
12165 case we must either set fr_subtype back to the unrelaxed state,
12166 or return the value for the appropriate branch. */
12167 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12170 /* Called after relax() is finished.
12172 In: Address of frag.
12173 fr_type == rs_machine_dependent.
12174 fr_subtype is what the address relaxed to.
12176 Out: Any fixSs and constants are set up.
12177 Caller will turn frag into a ".space 0". */
12180 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12183 unsigned char *opcode
;
12184 unsigned char *where_to_put_displacement
= NULL
;
12185 offsetT target_address
;
12186 offsetT opcode_address
;
12187 unsigned int extension
= 0;
12188 offsetT displacement_from_opcode_start
;
12190 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12191 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12192 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12194 /* Generate nop padding. */
12195 unsigned int size
= fragP
->tc_frag_data
.length
;
12198 if (size
> fragP
->tc_frag_data
.max_bytes
)
12204 const char *branch
= "branch";
12205 const char *prefix
= "";
12206 fragS
*padding_fragP
;
12207 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12210 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12211 switch (fragP
->tc_frag_data
.default_prefix
)
12216 case CS_PREFIX_OPCODE
:
12219 case DS_PREFIX_OPCODE
:
12222 case ES_PREFIX_OPCODE
:
12225 case FS_PREFIX_OPCODE
:
12228 case GS_PREFIX_OPCODE
:
12231 case SS_PREFIX_OPCODE
:
12236 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12237 "%s within %d-byte boundary\n");
12239 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12240 "align %s within %d-byte boundary\n");
12244 padding_fragP
= fragP
;
12245 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12246 "%s within %d-byte boundary\n");
12250 switch (padding_fragP
->tc_frag_data
.branch_type
)
12252 case align_branch_jcc
:
12255 case align_branch_fused
:
12256 branch
= "fused jcc";
12258 case align_branch_jmp
:
12261 case align_branch_call
:
12264 case align_branch_indirect
:
12265 branch
= "indiret branch";
12267 case align_branch_ret
:
12274 fprintf (stdout
, msg
,
12275 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12276 (long long) fragP
->fr_address
, branch
,
12277 1 << align_branch_power
);
12279 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12280 memset (fragP
->fr_opcode
,
12281 fragP
->tc_frag_data
.default_prefix
, size
);
12283 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12285 fragP
->fr_fix
+= size
;
12290 opcode
= (unsigned char *) fragP
->fr_opcode
;
12292 /* Address we want to reach in file space. */
12293 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12295 /* Address opcode resides at in file space. */
12296 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12298 /* Displacement from opcode start to fill into instruction. */
12299 displacement_from_opcode_start
= target_address
- opcode_address
;
12301 if ((fragP
->fr_subtype
& BIG
) == 0)
12303 /* Don't have to change opcode. */
12304 extension
= 1; /* 1 opcode + 1 displacement */
12305 where_to_put_displacement
= &opcode
[1];
12309 if (no_cond_jump_promotion
12310 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12311 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12312 _("long jump required"));
12314 switch (fragP
->fr_subtype
)
12316 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12317 extension
= 4; /* 1 opcode + 4 displacement */
12319 where_to_put_displacement
= &opcode
[1];
12322 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12323 extension
= 2; /* 1 opcode + 2 displacement */
12325 where_to_put_displacement
= &opcode
[1];
12328 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12329 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12330 extension
= 5; /* 2 opcode + 4 displacement */
12331 opcode
[1] = opcode
[0] + 0x10;
12332 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12333 where_to_put_displacement
= &opcode
[2];
12336 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12337 extension
= 3; /* 2 opcode + 2 displacement */
12338 opcode
[1] = opcode
[0] + 0x10;
12339 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12340 where_to_put_displacement
= &opcode
[2];
12343 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12348 where_to_put_displacement
= &opcode
[3];
12352 BAD_CASE (fragP
->fr_subtype
);
12357 /* If size if less then four we are sure that the operand fits,
12358 but if it's 4, then it could be that the displacement is larger
12360 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12362 && ((addressT
) (displacement_from_opcode_start
- extension
12363 + ((addressT
) 1 << 31))
12364 > (((addressT
) 2 << 31) - 1)))
12366 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12367 _("jump target out of range"));
12368 /* Make us emit 0. */
12369 displacement_from_opcode_start
= extension
;
12371 /* Now put displacement after opcode. */
12372 md_number_to_chars ((char *) where_to_put_displacement
,
12373 (valueT
) (displacement_from_opcode_start
- extension
),
12374 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12375 fragP
->fr_fix
+= extension
;
12378 /* Apply a fixup (fixP) to segment data, once it has been determined
12379 by our caller that we have all the info we need to fix it up.
12381 Parameter valP is the pointer to the value of the bits.
12383 On the 386, immediates, displacements, and data pointers are all in
12384 the same (little-endian) format, so we don't need to care about which
12385 we are handling. */
12388 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12390 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12391 valueT value
= *valP
;
12393 #if !defined (TE_Mach)
12394 if (fixP
->fx_pcrel
)
12396 switch (fixP
->fx_r_type
)
12402 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12405 case BFD_RELOC_X86_64_32S
:
12406 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12409 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12412 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12417 if (fixP
->fx_addsy
!= NULL
12418 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12419 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12420 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12421 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12422 && !use_rela_relocations
)
12424 /* This is a hack. There should be a better way to handle this.
12425 This covers for the fact that bfd_install_relocation will
12426 subtract the current location (for partial_inplace, PC relative
12427 relocations); see more below. */
12431 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12434 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12439 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12441 if ((sym_seg
== seg
12442 || (symbol_section_p (fixP
->fx_addsy
)
12443 && sym_seg
!= absolute_section
))
12444 && !generic_force_reloc (fixP
))
12446 /* Yes, we add the values in twice. This is because
12447 bfd_install_relocation subtracts them out again. I think
12448 bfd_install_relocation is broken, but I don't dare change
12450 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12454 #if defined (OBJ_COFF) && defined (TE_PE)
12455 /* For some reason, the PE format does not store a
12456 section address offset for a PC relative symbol. */
12457 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12458 || S_IS_WEAK (fixP
->fx_addsy
))
12459 value
+= md_pcrel_from (fixP
);
12462 #if defined (OBJ_COFF) && defined (TE_PE)
12463 if (fixP
->fx_addsy
!= NULL
12464 && S_IS_WEAK (fixP
->fx_addsy
)
12465 /* PR 16858: Do not modify weak function references. */
12466 && ! fixP
->fx_pcrel
)
12468 #if !defined (TE_PEP)
12469 /* For x86 PE weak function symbols are neither PC-relative
12470 nor do they set S_IS_FUNCTION. So the only reliable way
12471 to detect them is to check the flags of their containing
12473 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12474 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12478 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12482 /* Fix a few things - the dynamic linker expects certain values here,
12483 and we must not disappoint it. */
12484 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12485 if (IS_ELF
&& fixP
->fx_addsy
)
12486 switch (fixP
->fx_r_type
)
12488 case BFD_RELOC_386_PLT32
:
12489 case BFD_RELOC_X86_64_PLT32
:
12490 /* Make the jump instruction point to the address of the operand.
12491 At runtime we merely add the offset to the actual PLT entry.
12492 NB: Subtract the offset size only for jump instructions. */
12493 if (fixP
->fx_pcrel
)
12497 case BFD_RELOC_386_TLS_GD
:
12498 case BFD_RELOC_386_TLS_LDM
:
12499 case BFD_RELOC_386_TLS_IE_32
:
12500 case BFD_RELOC_386_TLS_IE
:
12501 case BFD_RELOC_386_TLS_GOTIE
:
12502 case BFD_RELOC_386_TLS_GOTDESC
:
12503 case BFD_RELOC_X86_64_TLSGD
:
12504 case BFD_RELOC_X86_64_TLSLD
:
12505 case BFD_RELOC_X86_64_GOTTPOFF
:
12506 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12507 value
= 0; /* Fully resolved at runtime. No addend. */
12509 case BFD_RELOC_386_TLS_LE
:
12510 case BFD_RELOC_386_TLS_LDO_32
:
12511 case BFD_RELOC_386_TLS_LE_32
:
12512 case BFD_RELOC_X86_64_DTPOFF32
:
12513 case BFD_RELOC_X86_64_DTPOFF64
:
12514 case BFD_RELOC_X86_64_TPOFF32
:
12515 case BFD_RELOC_X86_64_TPOFF64
:
12516 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12519 case BFD_RELOC_386_TLS_DESC_CALL
:
12520 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12521 value
= 0; /* Fully resolved at runtime. No addend. */
12522 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12526 case BFD_RELOC_VTABLE_INHERIT
:
12527 case BFD_RELOC_VTABLE_ENTRY
:
12534 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12536 #endif /* !defined (TE_Mach) */
12538 /* Are we finished with this relocation now? */
12539 if (fixP
->fx_addsy
== NULL
)
12541 #if defined (OBJ_COFF) && defined (TE_PE)
12542 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12545 /* Remember value for tc_gen_reloc. */
12546 fixP
->fx_addnumber
= value
;
12547 /* Clear out the frag for now. */
12551 else if (use_rela_relocations
)
12553 fixP
->fx_no_overflow
= 1;
12554 /* Remember value for tc_gen_reloc. */
12555 fixP
->fx_addnumber
= value
;
12559 md_number_to_chars (p
, value
, fixP
->fx_size
);
12563 md_atof (int type
, char *litP
, int *sizeP
)
12565 /* This outputs the LITTLENUMs in REVERSE order;
12566 in accord with the bigendian 386. */
12567 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12570 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12573 output_invalid (int c
)
12576 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12579 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12580 "(0x%x)", (unsigned char) c
);
12581 return output_invalid_buf
;
12584 /* Verify that @r can be used in the current context. */
12586 static bfd_boolean
check_register (const reg_entry
*r
)
12588 if (allow_pseudo_reg
)
12591 if (operand_type_all_zero (&r
->reg_type
))
12594 if ((r
->reg_type
.bitfield
.dword
12595 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12596 || r
->reg_type
.bitfield
.class == RegCR
12597 || r
->reg_type
.bitfield
.class == RegDR
)
12598 && !cpu_arch_flags
.bitfield
.cpui386
)
12601 if (r
->reg_type
.bitfield
.class == RegTR
12602 && (flag_code
== CODE_64BIT
12603 || !cpu_arch_flags
.bitfield
.cpui386
12604 || cpu_arch_isa_flags
.bitfield
.cpui586
12605 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12608 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12611 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12613 if (r
->reg_type
.bitfield
.zmmword
12614 || r
->reg_type
.bitfield
.class == RegMask
)
12617 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12619 if (r
->reg_type
.bitfield
.ymmword
)
12622 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12627 if (r
->reg_type
.bitfield
.tmmword
12628 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12629 || flag_code
!= CODE_64BIT
))
12632 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12635 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12636 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12639 /* Upper 16 vector registers are only available with VREX in 64bit
12640 mode, and require EVEX encoding. */
12641 if (r
->reg_flags
& RegVRex
)
12643 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12644 || flag_code
!= CODE_64BIT
)
12647 if (i
.vec_encoding
== vex_encoding_default
)
12648 i
.vec_encoding
= vex_encoding_evex
;
12649 else if (i
.vec_encoding
!= vex_encoding_evex
)
12650 i
.vec_encoding
= vex_encoding_error
;
12653 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12654 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12655 && flag_code
!= CODE_64BIT
)
12658 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12665 /* REG_STRING starts *before* REGISTER_PREFIX. */
12667 static const reg_entry
*
12668 parse_real_register (char *reg_string
, char **end_op
)
12670 char *s
= reg_string
;
12672 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12673 const reg_entry
*r
;
12675 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12676 if (*s
== REGISTER_PREFIX
)
12679 if (is_space_char (*s
))
12682 p
= reg_name_given
;
12683 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12685 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12686 return (const reg_entry
*) NULL
;
12690 /* For naked regs, make sure that we are not dealing with an identifier.
12691 This prevents confusing an identifier like `eax_var' with register
12693 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12694 return (const reg_entry
*) NULL
;
12698 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12700 /* Handle floating point regs, allowing spaces in the (i) part. */
12701 if (r
== i386_regtab
/* %st is first entry of table */)
12703 if (!cpu_arch_flags
.bitfield
.cpu8087
12704 && !cpu_arch_flags
.bitfield
.cpu287
12705 && !cpu_arch_flags
.bitfield
.cpu387
12706 && !allow_pseudo_reg
)
12707 return (const reg_entry
*) NULL
;
12709 if (is_space_char (*s
))
12714 if (is_space_char (*s
))
12716 if (*s
>= '0' && *s
<= '7')
12718 int fpr
= *s
- '0';
12720 if (is_space_char (*s
))
12725 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12730 /* We have "%st(" then garbage. */
12731 return (const reg_entry
*) NULL
;
12735 return r
&& check_register (r
) ? r
: NULL
;
12738 /* REG_STRING starts *before* REGISTER_PREFIX. */
12740 static const reg_entry
*
12741 parse_register (char *reg_string
, char **end_op
)
12743 const reg_entry
*r
;
12745 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12746 r
= parse_real_register (reg_string
, end_op
);
12751 char *save
= input_line_pointer
;
12755 input_line_pointer
= reg_string
;
12756 c
= get_symbol_name (®_string
);
12757 symbolP
= symbol_find (reg_string
);
12758 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12760 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12762 know (e
->X_op
== O_register
);
12763 know (e
->X_add_number
>= 0
12764 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12765 r
= i386_regtab
+ e
->X_add_number
;
12766 if (!check_register (r
))
12768 as_bad (_("register '%s%s' cannot be used here"),
12769 register_prefix
, r
->reg_name
);
12772 *end_op
= input_line_pointer
;
12774 *input_line_pointer
= c
;
12775 input_line_pointer
= save
;
12781 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12783 const reg_entry
*r
;
12784 char *end
= input_line_pointer
;
12787 r
= parse_register (name
, &input_line_pointer
);
12788 if (r
&& end
<= input_line_pointer
)
12790 *nextcharP
= *input_line_pointer
;
12791 *input_line_pointer
= 0;
12794 e
->X_op
= O_register
;
12795 e
->X_add_number
= r
- i386_regtab
;
12798 e
->X_op
= O_illegal
;
12801 input_line_pointer
= end
;
12803 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12807 md_operand (expressionS
*e
)
12810 const reg_entry
*r
;
12812 switch (*input_line_pointer
)
12814 case REGISTER_PREFIX
:
12815 r
= parse_real_register (input_line_pointer
, &end
);
12818 e
->X_op
= O_register
;
12819 e
->X_add_number
= r
- i386_regtab
;
12820 input_line_pointer
= end
;
12825 gas_assert (intel_syntax
);
12826 end
= input_line_pointer
++;
12828 if (*input_line_pointer
== ']')
12830 ++input_line_pointer
;
12831 e
->X_op_symbol
= make_expr_symbol (e
);
12832 e
->X_add_symbol
= NULL
;
12833 e
->X_add_number
= 0;
12838 e
->X_op
= O_absent
;
12839 input_line_pointer
= end
;
12846 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12847 const char *md_shortopts
= "kVQ:sqnO::";
12849 const char *md_shortopts
= "qnO::";
12852 #define OPTION_32 (OPTION_MD_BASE + 0)
12853 #define OPTION_64 (OPTION_MD_BASE + 1)
12854 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12855 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12856 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12857 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12858 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12859 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12860 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12861 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12862 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12863 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12864 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12865 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12866 #define OPTION_X32 (OPTION_MD_BASE + 14)
12867 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12868 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12869 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12870 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12871 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12872 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12873 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12874 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12875 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12876 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12877 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12878 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12879 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12880 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12881 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12882 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12883 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12884 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12885 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12887 struct option md_longopts
[] =
12889 {"32", no_argument
, NULL
, OPTION_32
},
12890 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12891 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12892 {"64", no_argument
, NULL
, OPTION_64
},
12894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12895 {"x32", no_argument
, NULL
, OPTION_X32
},
12896 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12897 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12899 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12900 {"march", required_argument
, NULL
, OPTION_MARCH
},
12901 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12902 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12903 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12904 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12905 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12906 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12907 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12908 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12909 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12910 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12911 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12912 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12913 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12914 # if defined (TE_PE) || defined (TE_PEP)
12915 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12917 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12918 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12919 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12920 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12921 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12922 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12923 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12924 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12925 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12926 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12927 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12928 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12929 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12930 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12931 {NULL
, no_argument
, NULL
, 0}
12933 size_t md_longopts_size
= sizeof (md_longopts
);
12936 md_parse_option (int c
, const char *arg
)
12939 char *arch
, *next
, *saved
, *type
;
12944 optimize_align_code
= 0;
12948 quiet_warnings
= 1;
12951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12952 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12953 should be emitted or not. FIXME: Not implemented. */
12955 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12959 /* -V: SVR4 argument to print version ID. */
12961 print_version_id ();
12964 /* -k: Ignore for FreeBSD compatibility. */
12969 /* -s: On i386 Solaris, this tells the native assembler to use
12970 .stab instead of .stab.excl. We always use .stab anyhow. */
12973 case OPTION_MSHARED
:
12977 case OPTION_X86_USED_NOTE
:
12978 if (strcasecmp (arg
, "yes") == 0)
12980 else if (strcasecmp (arg
, "no") == 0)
12983 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12988 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12989 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12992 const char **list
, **l
;
12994 list
= bfd_target_list ();
12995 for (l
= list
; *l
!= NULL
; l
++)
12996 if (startswith (*l
, "elf64-x86-64")
12997 || strcmp (*l
, "coff-x86-64") == 0
12998 || strcmp (*l
, "pe-x86-64") == 0
12999 || strcmp (*l
, "pei-x86-64") == 0
13000 || strcmp (*l
, "mach-o-x86-64") == 0)
13002 default_arch
= "x86_64";
13006 as_fatal (_("no compiled in support for x86_64"));
13012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13016 const char **list
, **l
;
13018 list
= bfd_target_list ();
13019 for (l
= list
; *l
!= NULL
; l
++)
13020 if (startswith (*l
, "elf32-x86-64"))
13022 default_arch
= "x86_64:32";
13026 as_fatal (_("no compiled in support for 32bit x86_64"));
13030 as_fatal (_("32bit x86_64 is only supported for ELF"));
13035 default_arch
= "i386";
13038 case OPTION_DIVIDE
:
13039 #ifdef SVR4_COMMENT_CHARS
13044 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13046 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13050 i386_comment_chars
= n
;
13056 saved
= xstrdup (arg
);
13058 /* Allow -march=+nosse. */
13064 as_fatal (_("invalid -march= option: `%s'"), arg
);
13065 next
= strchr (arch
, '+');
13068 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13070 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13073 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13076 cpu_arch_name
= cpu_arch
[j
].name
;
13077 cpu_sub_arch_name
= NULL
;
13078 cpu_arch_flags
= cpu_arch
[j
].flags
;
13079 cpu_arch_isa
= cpu_arch
[j
].type
;
13080 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13081 if (!cpu_arch_tune_set
)
13083 cpu_arch_tune
= cpu_arch_isa
;
13084 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13088 else if (*cpu_arch
[j
].name
== '.'
13089 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13091 /* ISA extension. */
13092 i386_cpu_flags flags
;
13094 flags
= cpu_flags_or (cpu_arch_flags
,
13095 cpu_arch
[j
].flags
);
13097 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13099 if (cpu_sub_arch_name
)
13101 char *name
= cpu_sub_arch_name
;
13102 cpu_sub_arch_name
= concat (name
,
13104 (const char *) NULL
);
13108 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13109 cpu_arch_flags
= flags
;
13110 cpu_arch_isa_flags
= flags
;
13114 = cpu_flags_or (cpu_arch_isa_flags
,
13115 cpu_arch
[j
].flags
);
13120 if (j
>= ARRAY_SIZE (cpu_arch
))
13122 /* Disable an ISA extension. */
13123 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13124 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13126 i386_cpu_flags flags
;
13128 flags
= cpu_flags_and_not (cpu_arch_flags
,
13129 cpu_noarch
[j
].flags
);
13130 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13132 if (cpu_sub_arch_name
)
13134 char *name
= cpu_sub_arch_name
;
13135 cpu_sub_arch_name
= concat (arch
,
13136 (const char *) NULL
);
13140 cpu_sub_arch_name
= xstrdup (arch
);
13141 cpu_arch_flags
= flags
;
13142 cpu_arch_isa_flags
= flags
;
13147 if (j
>= ARRAY_SIZE (cpu_noarch
))
13148 j
= ARRAY_SIZE (cpu_arch
);
13151 if (j
>= ARRAY_SIZE (cpu_arch
))
13152 as_fatal (_("invalid -march= option: `%s'"), arg
);
13156 while (next
!= NULL
);
13162 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13163 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13165 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13167 cpu_arch_tune_set
= 1;
13168 cpu_arch_tune
= cpu_arch
[j
].type
;
13169 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13173 if (j
>= ARRAY_SIZE (cpu_arch
))
13174 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13177 case OPTION_MMNEMONIC
:
13178 if (strcasecmp (arg
, "att") == 0)
13179 intel_mnemonic
= 0;
13180 else if (strcasecmp (arg
, "intel") == 0)
13181 intel_mnemonic
= 1;
13183 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13186 case OPTION_MSYNTAX
:
13187 if (strcasecmp (arg
, "att") == 0)
13189 else if (strcasecmp (arg
, "intel") == 0)
13192 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13195 case OPTION_MINDEX_REG
:
13196 allow_index_reg
= 1;
13199 case OPTION_MNAKED_REG
:
13200 allow_naked_reg
= 1;
13203 case OPTION_MSSE2AVX
:
13207 case OPTION_MSSE_CHECK
:
13208 if (strcasecmp (arg
, "error") == 0)
13209 sse_check
= check_error
;
13210 else if (strcasecmp (arg
, "warning") == 0)
13211 sse_check
= check_warning
;
13212 else if (strcasecmp (arg
, "none") == 0)
13213 sse_check
= check_none
;
13215 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13218 case OPTION_MOPERAND_CHECK
:
13219 if (strcasecmp (arg
, "error") == 0)
13220 operand_check
= check_error
;
13221 else if (strcasecmp (arg
, "warning") == 0)
13222 operand_check
= check_warning
;
13223 else if (strcasecmp (arg
, "none") == 0)
13224 operand_check
= check_none
;
13226 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13229 case OPTION_MAVXSCALAR
:
13230 if (strcasecmp (arg
, "128") == 0)
13231 avxscalar
= vex128
;
13232 else if (strcasecmp (arg
, "256") == 0)
13233 avxscalar
= vex256
;
13235 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13238 case OPTION_MVEXWIG
:
13239 if (strcmp (arg
, "0") == 0)
13241 else if (strcmp (arg
, "1") == 0)
13244 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13247 case OPTION_MADD_BND_PREFIX
:
13248 add_bnd_prefix
= 1;
13251 case OPTION_MEVEXLIG
:
13252 if (strcmp (arg
, "128") == 0)
13253 evexlig
= evexl128
;
13254 else if (strcmp (arg
, "256") == 0)
13255 evexlig
= evexl256
;
13256 else if (strcmp (arg
, "512") == 0)
13257 evexlig
= evexl512
;
13259 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13262 case OPTION_MEVEXRCIG
:
13263 if (strcmp (arg
, "rne") == 0)
13265 else if (strcmp (arg
, "rd") == 0)
13267 else if (strcmp (arg
, "ru") == 0)
13269 else if (strcmp (arg
, "rz") == 0)
13272 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13275 case OPTION_MEVEXWIG
:
13276 if (strcmp (arg
, "0") == 0)
13278 else if (strcmp (arg
, "1") == 0)
13281 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13284 # if defined (TE_PE) || defined (TE_PEP)
13285 case OPTION_MBIG_OBJ
:
13290 case OPTION_MOMIT_LOCK_PREFIX
:
13291 if (strcasecmp (arg
, "yes") == 0)
13292 omit_lock_prefix
= 1;
13293 else if (strcasecmp (arg
, "no") == 0)
13294 omit_lock_prefix
= 0;
13296 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13299 case OPTION_MFENCE_AS_LOCK_ADD
:
13300 if (strcasecmp (arg
, "yes") == 0)
13302 else if (strcasecmp (arg
, "no") == 0)
13305 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13308 case OPTION_MLFENCE_AFTER_LOAD
:
13309 if (strcasecmp (arg
, "yes") == 0)
13310 lfence_after_load
= 1;
13311 else if (strcasecmp (arg
, "no") == 0)
13312 lfence_after_load
= 0;
13314 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13317 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13318 if (strcasecmp (arg
, "all") == 0)
13320 lfence_before_indirect_branch
= lfence_branch_all
;
13321 if (lfence_before_ret
== lfence_before_ret_none
)
13322 lfence_before_ret
= lfence_before_ret_shl
;
13324 else if (strcasecmp (arg
, "memory") == 0)
13325 lfence_before_indirect_branch
= lfence_branch_memory
;
13326 else if (strcasecmp (arg
, "register") == 0)
13327 lfence_before_indirect_branch
= lfence_branch_register
;
13328 else if (strcasecmp (arg
, "none") == 0)
13329 lfence_before_indirect_branch
= lfence_branch_none
;
13331 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13335 case OPTION_MLFENCE_BEFORE_RET
:
13336 if (strcasecmp (arg
, "or") == 0)
13337 lfence_before_ret
= lfence_before_ret_or
;
13338 else if (strcasecmp (arg
, "not") == 0)
13339 lfence_before_ret
= lfence_before_ret_not
;
13340 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13341 lfence_before_ret
= lfence_before_ret_shl
;
13342 else if (strcasecmp (arg
, "none") == 0)
13343 lfence_before_ret
= lfence_before_ret_none
;
13345 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13349 case OPTION_MRELAX_RELOCATIONS
:
13350 if (strcasecmp (arg
, "yes") == 0)
13351 generate_relax_relocations
= 1;
13352 else if (strcasecmp (arg
, "no") == 0)
13353 generate_relax_relocations
= 0;
13355 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13358 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13361 long int align
= strtoul (arg
, &end
, 0);
13366 align_branch_power
= 0;
13369 else if (align
>= 16)
13372 for (align_power
= 0;
13374 align
>>= 1, align_power
++)
13376 /* Limit alignment power to 31. */
13377 if (align
== 1 && align_power
< 32)
13379 align_branch_power
= align_power
;
13384 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13388 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13391 int align
= strtoul (arg
, &end
, 0);
13392 /* Some processors only support 5 prefixes. */
13393 if (*end
== '\0' && align
>= 0 && align
< 6)
13395 align_branch_prefix_size
= align
;
13398 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13403 case OPTION_MALIGN_BRANCH
:
13405 saved
= xstrdup (arg
);
13409 next
= strchr (type
, '+');
13412 if (strcasecmp (type
, "jcc") == 0)
13413 align_branch
|= align_branch_jcc_bit
;
13414 else if (strcasecmp (type
, "fused") == 0)
13415 align_branch
|= align_branch_fused_bit
;
13416 else if (strcasecmp (type
, "jmp") == 0)
13417 align_branch
|= align_branch_jmp_bit
;
13418 else if (strcasecmp (type
, "call") == 0)
13419 align_branch
|= align_branch_call_bit
;
13420 else if (strcasecmp (type
, "ret") == 0)
13421 align_branch
|= align_branch_ret_bit
;
13422 else if (strcasecmp (type
, "indirect") == 0)
13423 align_branch
|= align_branch_indirect_bit
;
13425 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13428 while (next
!= NULL
);
13432 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13433 align_branch_power
= 5;
13434 align_branch_prefix_size
= 5;
13435 align_branch
= (align_branch_jcc_bit
13436 | align_branch_fused_bit
13437 | align_branch_jmp_bit
);
13440 case OPTION_MAMD64
:
13444 case OPTION_MINTEL64
:
13452 /* Turn off -Os. */
13453 optimize_for_space
= 0;
13455 else if (*arg
== 's')
13457 optimize_for_space
= 1;
13458 /* Turn on all encoding optimizations. */
13459 optimize
= INT_MAX
;
13463 optimize
= atoi (arg
);
13464 /* Turn off -Os. */
13465 optimize_for_space
= 0;
13475 #define MESSAGE_TEMPLATE \
13479 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13480 int *left_p
, const char *name
, int len
)
13482 int size
= sizeof (MESSAGE_TEMPLATE
);
13483 int left
= *left_p
;
13485 /* Reserve 2 spaces for ", " or ",\0" */
13488 /* Check if there is any room. */
13496 p
= mempcpy (p
, name
, len
);
13500 /* Output the current message now and start a new one. */
13503 fprintf (stream
, "%s\n", message
);
13505 left
= size
- (start
- message
) - len
- 2;
13507 gas_assert (left
>= 0);
13509 p
= mempcpy (p
, name
, len
);
13517 show_arch (FILE *stream
, int ext
, int check
)
13519 static char message
[] = MESSAGE_TEMPLATE
;
13520 char *start
= message
+ 27;
13522 int size
= sizeof (MESSAGE_TEMPLATE
);
13529 left
= size
- (start
- message
);
13530 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13532 /* Should it be skipped? */
13533 if (cpu_arch
[j
].skip
)
13536 name
= cpu_arch
[j
].name
;
13537 len
= cpu_arch
[j
].len
;
13540 /* It is an extension. Skip if we aren't asked to show it. */
13551 /* It is an processor. Skip if we show only extension. */
13554 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13556 /* It is an impossible processor - skip. */
13560 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13563 /* Display disabled extensions. */
13565 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13567 name
= cpu_noarch
[j
].name
;
13568 len
= cpu_noarch
[j
].len
;
13569 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13574 fprintf (stream
, "%s\n", message
);
13578 md_show_usage (FILE *stream
)
13580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13581 fprintf (stream
, _("\
13582 -Qy, -Qn ignored\n\
13583 -V print assembler version number\n\
13586 fprintf (stream
, _("\
13587 -n Do not optimize code alignment\n\
13588 -q quieten some warnings\n"));
13589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13590 fprintf (stream
, _("\
13593 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13594 || defined (TE_PE) || defined (TE_PEP))
13595 fprintf (stream
, _("\
13596 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13598 #ifdef SVR4_COMMENT_CHARS
13599 fprintf (stream
, _("\
13600 --divide do not treat `/' as a comment character\n"));
13602 fprintf (stream
, _("\
13603 --divide ignored\n"));
13605 fprintf (stream
, _("\
13606 -march=CPU[,+EXTENSION...]\n\
13607 generate code for CPU and EXTENSION, CPU is one of:\n"));
13608 show_arch (stream
, 0, 1);
13609 fprintf (stream
, _("\
13610 EXTENSION is combination of:\n"));
13611 show_arch (stream
, 1, 0);
13612 fprintf (stream
, _("\
13613 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13614 show_arch (stream
, 0, 0);
13615 fprintf (stream
, _("\
13616 -msse2avx encode SSE instructions with VEX prefix\n"));
13617 fprintf (stream
, _("\
13618 -msse-check=[none|error|warning] (default: warning)\n\
13619 check SSE instructions\n"));
13620 fprintf (stream
, _("\
13621 -moperand-check=[none|error|warning] (default: warning)\n\
13622 check operand combinations for validity\n"));
13623 fprintf (stream
, _("\
13624 -mavxscalar=[128|256] (default: 128)\n\
13625 encode scalar AVX instructions with specific vector\n\
13627 fprintf (stream
, _("\
13628 -mvexwig=[0|1] (default: 0)\n\
13629 encode VEX instructions with specific VEX.W value\n\
13630 for VEX.W bit ignored instructions\n"));
13631 fprintf (stream
, _("\
13632 -mevexlig=[128|256|512] (default: 128)\n\
13633 encode scalar EVEX instructions with specific vector\n\
13635 fprintf (stream
, _("\
13636 -mevexwig=[0|1] (default: 0)\n\
13637 encode EVEX instructions with specific EVEX.W value\n\
13638 for EVEX.W bit ignored instructions\n"));
13639 fprintf (stream
, _("\
13640 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13641 encode EVEX instructions with specific EVEX.RC value\n\
13642 for SAE-only ignored instructions\n"));
13643 fprintf (stream
, _("\
13644 -mmnemonic=[att|intel] "));
13645 if (SYSV386_COMPAT
)
13646 fprintf (stream
, _("(default: att)\n"));
13648 fprintf (stream
, _("(default: intel)\n"));
13649 fprintf (stream
, _("\
13650 use AT&T/Intel mnemonic\n"));
13651 fprintf (stream
, _("\
13652 -msyntax=[att|intel] (default: att)\n\
13653 use AT&T/Intel syntax\n"));
13654 fprintf (stream
, _("\
13655 -mindex-reg support pseudo index registers\n"));
13656 fprintf (stream
, _("\
13657 -mnaked-reg don't require `%%' prefix for registers\n"));
13658 fprintf (stream
, _("\
13659 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13661 fprintf (stream
, _("\
13662 -mshared disable branch optimization for shared code\n"));
13663 fprintf (stream
, _("\
13664 -mx86-used-note=[no|yes] "));
13665 if (DEFAULT_X86_USED_NOTE
)
13666 fprintf (stream
, _("(default: yes)\n"));
13668 fprintf (stream
, _("(default: no)\n"));
13669 fprintf (stream
, _("\
13670 generate x86 used ISA and feature properties\n"));
13672 #if defined (TE_PE) || defined (TE_PEP)
13673 fprintf (stream
, _("\
13674 -mbig-obj generate big object files\n"));
13676 fprintf (stream
, _("\
13677 -momit-lock-prefix=[no|yes] (default: no)\n\
13678 strip all lock prefixes\n"));
13679 fprintf (stream
, _("\
13680 -mfence-as-lock-add=[no|yes] (default: no)\n\
13681 encode lfence, mfence and sfence as\n\
13682 lock addl $0x0, (%%{re}sp)\n"));
13683 fprintf (stream
, _("\
13684 -mrelax-relocations=[no|yes] "));
13685 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13686 fprintf (stream
, _("(default: yes)\n"));
13688 fprintf (stream
, _("(default: no)\n"));
13689 fprintf (stream
, _("\
13690 generate relax relocations\n"));
13691 fprintf (stream
, _("\
13692 -malign-branch-boundary=NUM (default: 0)\n\
13693 align branches within NUM byte boundary\n"));
13694 fprintf (stream
, _("\
13695 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13696 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13698 specify types of branches to align\n"));
13699 fprintf (stream
, _("\
13700 -malign-branch-prefix-size=NUM (default: 5)\n\
13701 align branches with NUM prefixes per instruction\n"));
13702 fprintf (stream
, _("\
13703 -mbranches-within-32B-boundaries\n\
13704 align branches within 32 byte boundary\n"));
13705 fprintf (stream
, _("\
13706 -mlfence-after-load=[no|yes] (default: no)\n\
13707 generate lfence after load\n"));
13708 fprintf (stream
, _("\
13709 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13710 generate lfence before indirect near branch\n"));
13711 fprintf (stream
, _("\
13712 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13713 generate lfence before ret\n"));
13714 fprintf (stream
, _("\
13715 -mamd64 accept only AMD64 ISA [default]\n"));
13716 fprintf (stream
, _("\
13717 -mintel64 accept only Intel64 ISA\n"));
13720 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13721 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13722 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13724 /* Pick the target format to use. */
13727 i386_target_format (void)
13729 if (!strncmp (default_arch
, "x86_64", 6))
13731 update_code_flag (CODE_64BIT
, 1);
13732 if (default_arch
[6] == '\0')
13733 x86_elf_abi
= X86_64_ABI
;
13735 x86_elf_abi
= X86_64_X32_ABI
;
13737 else if (!strcmp (default_arch
, "i386"))
13738 update_code_flag (CODE_32BIT
, 1);
13739 else if (!strcmp (default_arch
, "iamcu"))
13741 update_code_flag (CODE_32BIT
, 1);
13742 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13744 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13745 cpu_arch_name
= "iamcu";
13746 cpu_sub_arch_name
= NULL
;
13747 cpu_arch_flags
= iamcu_flags
;
13748 cpu_arch_isa
= PROCESSOR_IAMCU
;
13749 cpu_arch_isa_flags
= iamcu_flags
;
13750 if (!cpu_arch_tune_set
)
13752 cpu_arch_tune
= cpu_arch_isa
;
13753 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13756 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13757 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13761 as_fatal (_("unknown architecture"));
13763 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13764 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13765 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13766 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13768 switch (OUTPUT_FLAVOR
)
13770 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13771 case bfd_target_aout_flavour
:
13772 return AOUT_TARGET_FORMAT
;
13774 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13775 # if defined (TE_PE) || defined (TE_PEP)
13776 case bfd_target_coff_flavour
:
13777 if (flag_code
== CODE_64BIT
)
13778 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13780 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13781 # elif defined (TE_GO32)
13782 case bfd_target_coff_flavour
:
13783 return "coff-go32";
13785 case bfd_target_coff_flavour
:
13786 return "coff-i386";
13789 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13790 case bfd_target_elf_flavour
:
13792 const char *format
;
13794 switch (x86_elf_abi
)
13797 format
= ELF_TARGET_FORMAT
;
13799 tls_get_addr
= "___tls_get_addr";
13803 use_rela_relocations
= 1;
13806 tls_get_addr
= "__tls_get_addr";
13808 format
= ELF_TARGET_FORMAT64
;
13810 case X86_64_X32_ABI
:
13811 use_rela_relocations
= 1;
13814 tls_get_addr
= "__tls_get_addr";
13816 disallow_64bit_reloc
= 1;
13817 format
= ELF_TARGET_FORMAT32
;
13820 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13822 if (x86_elf_abi
!= X86_64_ABI
)
13823 as_fatal (_("Intel L1OM is 64bit only"));
13824 return ELF_TARGET_L1OM_FORMAT
;
13826 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13828 if (x86_elf_abi
!= X86_64_ABI
)
13829 as_fatal (_("Intel K1OM is 64bit only"));
13830 return ELF_TARGET_K1OM_FORMAT
;
13832 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13834 if (x86_elf_abi
!= I386_ABI
)
13835 as_fatal (_("Intel MCU is 32bit only"));
13836 return ELF_TARGET_IAMCU_FORMAT
;
13842 #if defined (OBJ_MACH_O)
13843 case bfd_target_mach_o_flavour
:
13844 if (flag_code
== CODE_64BIT
)
13846 use_rela_relocations
= 1;
13848 return "mach-o-x86-64";
13851 return "mach-o-i386";
13859 #endif /* OBJ_MAYBE_ more than one */
13862 md_undefined_symbol (char *name
)
13864 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13865 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13866 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13867 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13871 if (symbol_find (name
))
13872 as_bad (_("GOT already in symbol table"));
13873 GOT_symbol
= symbol_new (name
, undefined_section
,
13874 &zero_address_frag
, 0);
13881 /* Round up a section size to the appropriate boundary. */
13884 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13886 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13887 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13889 /* For a.out, force the section size to be aligned. If we don't do
13890 this, BFD will align it for us, but it will not write out the
13891 final bytes of the section. This may be a bug in BFD, but it is
13892 easier to fix it here since that is how the other a.out targets
13896 align
= bfd_section_alignment (segment
);
13897 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13904 /* On the i386, PC-relative offsets are relative to the start of the
13905 next instruction. That is, the address of the offset, plus its
13906 size, since the offset is always the last part of the insn. */
13909 md_pcrel_from (fixS
*fixP
)
13911 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13917 s_bss (int ignore ATTRIBUTE_UNUSED
)
13921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13923 obj_elf_section_change_hook ();
13925 temp
= get_absolute_expression ();
13926 subseg_set (bss_section
, (subsegT
) temp
);
13927 demand_empty_rest_of_line ();
13932 /* Remember constant directive. */
13935 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13937 if (last_insn
.kind
!= last_insn_directive
13938 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13940 last_insn
.seg
= now_seg
;
13941 last_insn
.kind
= last_insn_directive
;
13942 last_insn
.name
= "constant directive";
13943 last_insn
.file
= as_where (&last_insn
.line
);
13944 if (lfence_before_ret
!= lfence_before_ret_none
)
13946 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13947 as_warn (_("constant directive skips -mlfence-before-ret "
13948 "and -mlfence-before-indirect-branch"));
13950 as_warn (_("constant directive skips -mlfence-before-ret"));
13952 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13953 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13958 i386_validate_fix (fixS
*fixp
)
13960 if (fixp
->fx_subsy
)
13962 if (fixp
->fx_subsy
== GOT_symbol
)
13964 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13969 if (fixp
->fx_tcbit2
)
13970 fixp
->fx_r_type
= (fixp
->fx_tcbit
13971 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13972 : BFD_RELOC_X86_64_GOTPCRELX
);
13975 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13980 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13982 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13984 fixp
->fx_subsy
= 0;
13987 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13990 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13991 to section. Since PLT32 relocation must be against symbols,
13992 turn such PLT32 relocation into PC32 relocation. */
13994 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13995 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13996 && symbol_section_p (fixp
->fx_addsy
))
13997 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14000 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14001 && fixp
->fx_tcbit2
)
14002 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14009 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14012 bfd_reloc_code_real_type code
;
14014 switch (fixp
->fx_r_type
)
14016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14017 case BFD_RELOC_SIZE32
:
14018 case BFD_RELOC_SIZE64
:
14019 if (S_IS_DEFINED (fixp
->fx_addsy
)
14020 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14022 /* Resolve size relocation against local symbol to size of
14023 the symbol plus addend. */
14024 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14025 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14026 && !fits_in_unsigned_long (value
))
14027 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14028 _("symbol size computation overflow"));
14029 fixp
->fx_addsy
= NULL
;
14030 fixp
->fx_subsy
= NULL
;
14031 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14035 /* Fall through. */
14037 case BFD_RELOC_X86_64_PLT32
:
14038 case BFD_RELOC_X86_64_GOT32
:
14039 case BFD_RELOC_X86_64_GOTPCREL
:
14040 case BFD_RELOC_X86_64_GOTPCRELX
:
14041 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14042 case BFD_RELOC_386_PLT32
:
14043 case BFD_RELOC_386_GOT32
:
14044 case BFD_RELOC_386_GOT32X
:
14045 case BFD_RELOC_386_GOTOFF
:
14046 case BFD_RELOC_386_GOTPC
:
14047 case BFD_RELOC_386_TLS_GD
:
14048 case BFD_RELOC_386_TLS_LDM
:
14049 case BFD_RELOC_386_TLS_LDO_32
:
14050 case BFD_RELOC_386_TLS_IE_32
:
14051 case BFD_RELOC_386_TLS_IE
:
14052 case BFD_RELOC_386_TLS_GOTIE
:
14053 case BFD_RELOC_386_TLS_LE_32
:
14054 case BFD_RELOC_386_TLS_LE
:
14055 case BFD_RELOC_386_TLS_GOTDESC
:
14056 case BFD_RELOC_386_TLS_DESC_CALL
:
14057 case BFD_RELOC_X86_64_TLSGD
:
14058 case BFD_RELOC_X86_64_TLSLD
:
14059 case BFD_RELOC_X86_64_DTPOFF32
:
14060 case BFD_RELOC_X86_64_DTPOFF64
:
14061 case BFD_RELOC_X86_64_GOTTPOFF
:
14062 case BFD_RELOC_X86_64_TPOFF32
:
14063 case BFD_RELOC_X86_64_TPOFF64
:
14064 case BFD_RELOC_X86_64_GOTOFF64
:
14065 case BFD_RELOC_X86_64_GOTPC32
:
14066 case BFD_RELOC_X86_64_GOT64
:
14067 case BFD_RELOC_X86_64_GOTPCREL64
:
14068 case BFD_RELOC_X86_64_GOTPC64
:
14069 case BFD_RELOC_X86_64_GOTPLT64
:
14070 case BFD_RELOC_X86_64_PLTOFF64
:
14071 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14072 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14073 case BFD_RELOC_RVA
:
14074 case BFD_RELOC_VTABLE_ENTRY
:
14075 case BFD_RELOC_VTABLE_INHERIT
:
14077 case BFD_RELOC_32_SECREL
:
14079 code
= fixp
->fx_r_type
;
14081 case BFD_RELOC_X86_64_32S
:
14082 if (!fixp
->fx_pcrel
)
14084 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14085 code
= fixp
->fx_r_type
;
14088 /* Fall through. */
14090 if (fixp
->fx_pcrel
)
14092 switch (fixp
->fx_size
)
14095 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14096 _("can not do %d byte pc-relative relocation"),
14098 code
= BFD_RELOC_32_PCREL
;
14100 case 1: code
= BFD_RELOC_8_PCREL
; break;
14101 case 2: code
= BFD_RELOC_16_PCREL
; break;
14102 case 4: code
= BFD_RELOC_32_PCREL
; break;
14104 case 8: code
= BFD_RELOC_64_PCREL
; break;
14110 switch (fixp
->fx_size
)
14113 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14114 _("can not do %d byte relocation"),
14116 code
= BFD_RELOC_32
;
14118 case 1: code
= BFD_RELOC_8
; break;
14119 case 2: code
= BFD_RELOC_16
; break;
14120 case 4: code
= BFD_RELOC_32
; break;
14122 case 8: code
= BFD_RELOC_64
; break;
14129 if ((code
== BFD_RELOC_32
14130 || code
== BFD_RELOC_32_PCREL
14131 || code
== BFD_RELOC_X86_64_32S
)
14133 && fixp
->fx_addsy
== GOT_symbol
)
14136 code
= BFD_RELOC_386_GOTPC
;
14138 code
= BFD_RELOC_X86_64_GOTPC32
;
14140 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14142 && fixp
->fx_addsy
== GOT_symbol
)
14144 code
= BFD_RELOC_X86_64_GOTPC64
;
14147 rel
= XNEW (arelent
);
14148 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14149 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14151 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14153 if (!use_rela_relocations
)
14155 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14156 vtable entry to be used in the relocation's section offset. */
14157 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14158 rel
->address
= fixp
->fx_offset
;
14159 #if defined (OBJ_COFF) && defined (TE_PE)
14160 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14161 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14166 /* Use the rela in 64bit mode. */
14169 if (disallow_64bit_reloc
)
14172 case BFD_RELOC_X86_64_DTPOFF64
:
14173 case BFD_RELOC_X86_64_TPOFF64
:
14174 case BFD_RELOC_64_PCREL
:
14175 case BFD_RELOC_X86_64_GOTOFF64
:
14176 case BFD_RELOC_X86_64_GOT64
:
14177 case BFD_RELOC_X86_64_GOTPCREL64
:
14178 case BFD_RELOC_X86_64_GOTPC64
:
14179 case BFD_RELOC_X86_64_GOTPLT64
:
14180 case BFD_RELOC_X86_64_PLTOFF64
:
14181 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14182 _("cannot represent relocation type %s in x32 mode"),
14183 bfd_get_reloc_code_name (code
));
14189 if (!fixp
->fx_pcrel
)
14190 rel
->addend
= fixp
->fx_offset
;
14194 case BFD_RELOC_X86_64_PLT32
:
14195 case BFD_RELOC_X86_64_GOT32
:
14196 case BFD_RELOC_X86_64_GOTPCREL
:
14197 case BFD_RELOC_X86_64_GOTPCRELX
:
14198 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14199 case BFD_RELOC_X86_64_TLSGD
:
14200 case BFD_RELOC_X86_64_TLSLD
:
14201 case BFD_RELOC_X86_64_GOTTPOFF
:
14202 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14203 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14204 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14207 rel
->addend
= (section
->vma
14209 + fixp
->fx_addnumber
14210 + md_pcrel_from (fixp
));
14215 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14216 if (rel
->howto
== NULL
)
14218 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14219 _("cannot represent relocation type %s"),
14220 bfd_get_reloc_code_name (code
));
14221 /* Set howto to a garbage value so that we can keep going. */
14222 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14223 gas_assert (rel
->howto
!= NULL
);
14229 #include "tc-i386-intel.c"
14232 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14234 int saved_naked_reg
;
14235 char saved_register_dot
;
14237 saved_naked_reg
= allow_naked_reg
;
14238 allow_naked_reg
= 1;
14239 saved_register_dot
= register_chars
['.'];
14240 register_chars
['.'] = '.';
14241 allow_pseudo_reg
= 1;
14242 expression_and_evaluate (exp
);
14243 allow_pseudo_reg
= 0;
14244 register_chars
['.'] = saved_register_dot
;
14245 allow_naked_reg
= saved_naked_reg
;
14247 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14249 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14251 exp
->X_op
= O_constant
;
14252 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14253 .dw2_regnum
[flag_code
>> 1];
14256 exp
->X_op
= O_illegal
;
14261 tc_x86_frame_initial_instructions (void)
14263 static unsigned int sp_regno
[2];
14265 if (!sp_regno
[flag_code
>> 1])
14267 char *saved_input
= input_line_pointer
;
14268 char sp
[][4] = {"esp", "rsp"};
14271 input_line_pointer
= sp
[flag_code
>> 1];
14272 tc_x86_parse_to_dw2regnum (&exp
);
14273 gas_assert (exp
.X_op
== O_constant
);
14274 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14275 input_line_pointer
= saved_input
;
14278 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14279 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14283 x86_dwarf2_addr_size (void)
14285 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14286 if (x86_elf_abi
== X86_64_X32_ABI
)
14289 return bfd_arch_bits_per_address (stdoutput
) / 8;
14293 i386_elf_section_type (const char *str
, size_t len
)
14295 if (flag_code
== CODE_64BIT
14296 && len
== sizeof ("unwind") - 1
14297 && strncmp (str
, "unwind", 6) == 0)
14298 return SHT_X86_64_UNWIND
;
14305 i386_solaris_fix_up_eh_frame (segT sec
)
14307 if (flag_code
== CODE_64BIT
)
14308 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14314 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14318 exp
.X_op
= O_secrel
;
14319 exp
.X_add_symbol
= symbol
;
14320 exp
.X_add_number
= 0;
14321 emit_expr (&exp
, size
);
14325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14326 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14329 x86_64_section_letter (int letter
, const char **ptr_msg
)
14331 if (flag_code
== CODE_64BIT
)
14334 return SHF_X86_64_LARGE
;
14336 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14339 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14344 x86_64_section_word (char *str
, size_t len
)
14346 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14347 return SHF_X86_64_LARGE
;
14353 handle_large_common (int small ATTRIBUTE_UNUSED
)
14355 if (flag_code
!= CODE_64BIT
)
14357 s_comm_internal (0, elf_common_parse
);
14358 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14362 static segT lbss_section
;
14363 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14364 asection
*saved_bss_section
= bss_section
;
14366 if (lbss_section
== NULL
)
14368 flagword applicable
;
14369 segT seg
= now_seg
;
14370 subsegT subseg
= now_subseg
;
14372 /* The .lbss section is for local .largecomm symbols. */
14373 lbss_section
= subseg_new (".lbss", 0);
14374 applicable
= bfd_applicable_section_flags (stdoutput
);
14375 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14376 seg_info (lbss_section
)->bss
= 1;
14378 subseg_set (seg
, subseg
);
14381 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14382 bss_section
= lbss_section
;
14384 s_comm_internal (0, elf_common_parse
);
14386 elf_com_section_ptr
= saved_com_section_ptr
;
14387 bss_section
= saved_bss_section
;
14390 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */